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-rw-r--r--arch/arm/mach-omap1/Kconfig11
-rw-r--r--arch/arm/mach-omap1/Makefile4
-rw-r--r--arch/arm/mach-omap1/board-ams-delta.c5
-rw-r--r--arch/arm/mach-omap1/devices.c1
-rw-r--r--arch/arm/mach-omap1/flash.c1
-rw-r--r--arch/arm/mach-omap1/mailbox.c5
-rw-r--r--arch/arm/mach-omap1/mcbsp.c2
-rw-r--r--arch/arm/mach-omap1/mux.c2
-rw-r--r--arch/arm/mach-omap1/serial.c8
-rw-r--r--arch/arm/mach-omap1/time.c1
-rw-r--r--arch/arm/mach-omap2/Kconfig19
-rw-r--r--arch/arm/mach-omap2/Makefile7
-rw-r--r--arch/arm/mach-omap2/board-2430sdp.c2
-rw-r--r--arch/arm/mach-omap2/board-3430sdp.c2
-rw-r--r--arch/arm/mach-omap2/board-3630sdp.c2
-rw-r--r--arch/arm/mach-omap2/board-4430sdp.c14
-rw-r--r--arch/arm/mach-omap2/board-am3517crane.c69
-rw-r--r--arch/arm/mach-omap2/board-am3517evm.c2
-rw-r--r--arch/arm/mach-omap2/board-apollon.c2
-rw-r--r--arch/arm/mach-omap2/board-h4.c2
-rw-r--r--arch/arm/mach-omap2/board-igep0020.c37
-rw-r--r--arch/arm/mach-omap2/board-igep0030.c2
-rw-r--r--arch/arm/mach-omap2/board-ldp.c2
-rw-r--r--arch/arm/mach-omap2/board-n8x0.c28
-rw-r--r--arch/arm/mach-omap2/board-omap3beagle.c2
-rw-r--r--arch/arm/mach-omap2/board-omap3evm.c2
-rw-r--r--arch/arm/mach-omap2/board-omap3logic.c2
-rw-r--r--arch/arm/mach-omap2/board-omap3pandora.c2
-rw-r--r--arch/arm/mach-omap2/board-omap3stalker.c2
-rw-r--r--arch/arm/mach-omap2/board-omap3touchbook.c2
-rw-r--r--arch/arm/mach-omap2/board-omap4panda.c16
-rw-r--r--arch/arm/mach-omap2/board-overo.c2
-rw-r--r--arch/arm/mach-omap2/board-rx51-peripherals.c40
-rw-r--r--arch/arm/mach-omap2/board-rx51.c2
-rw-r--r--arch/arm/mach-omap2/board-zoom.c (renamed from arch/arm/mach-omap2/board-zoom3.c)102
-rw-r--r--arch/arm/mach-omap2/board-zoom2.c117
-rw-r--r--arch/arm/mach-omap2/cm-regbits-24xx.h4
-rw-r--r--arch/arm/mach-omap2/mux.c369
-rw-r--r--arch/arm/mach-omap2/mux.h85
-rw-r--r--arch/arm/mach-omap2/mux2420.c10
-rw-r--r--arch/arm/mach-omap2/mux2430.c10
-rw-r--r--arch/arm/mach-omap2/mux34xx.c9
-rw-r--r--arch/arm/mach-omap2/mux44xx.c1625
-rw-r--r--arch/arm/mach-omap2/mux44xx.h298
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2420_data.c145
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2430_data.c155
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_3xxx_data.c233
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_44xx_data.c237
-rw-r--r--arch/arm/mach-omap2/prm-regbits-34xx.h3
-rw-r--r--arch/arm/mach-omap2/serial.c27
-rw-r--r--arch/arm/mach-omap2/timer-gp.c3
-rw-r--r--arch/arm/plat-omap/dma.c2
-rw-r--r--arch/arm/plat-omap/gpio.c5
-rw-r--r--arch/arm/plat-omap/i2c.c126
-rw-r--r--arch/arm/plat-omap/include/plat/i2c.h13
-rw-r--r--arch/arm/plat-omap/include/plat/l4_3xxx.h24
-rw-r--r--arch/arm/plat-omap/include/plat/omap-serial.h12
-rw-r--r--arch/arm/plat-omap/include/plat/uncompress.h1
-rw-r--r--arch/arm/plat-omap/mcbsp.c16
-rw-r--r--arch/arm/plat-omap/sram.c2
60 files changed, 3391 insertions, 544 deletions
diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig
index 5f6496375404..8d2f2daba0c0 100644
--- a/arch/arm/mach-omap1/Kconfig
+++ b/arch/arm/mach-omap1/Kconfig
@@ -152,20 +152,11 @@ config MACH_NOKIA770
152config MACH_AMS_DELTA 152config MACH_AMS_DELTA
153 bool "Amstrad E3 (Delta)" 153 bool "Amstrad E3 (Delta)"
154 depends on ARCH_OMAP1 && ARCH_OMAP15XX 154 depends on ARCH_OMAP1 && ARCH_OMAP15XX
155 select FIQ
155 help 156 help
156 Support for the Amstrad E3 (codename Delta) videophone. Say Y here 157 Support for the Amstrad E3 (codename Delta) videophone. Say Y here
157 if you have such a device. 158 if you have such a device.
158 159
159config AMS_DELTA_FIQ
160 bool "Fast Interrupt Request (FIQ) support for the E3"
161 depends on MACH_AMS_DELTA
162 select FIQ
163 help
164 Provide a FIQ handler for the E3.
165 This allows for fast handling of interrupts generated
166 by the clock line of the E3 mailboard (or a PS/2 keyboard)
167 connected to the GPIO based external keyboard port.
168
169config MACH_OMAP_GENERIC 160config MACH_OMAP_GENERIC
170 bool "Generic OMAP board" 161 bool "Generic OMAP board"
171 depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX) 162 depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX)
diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile
index 9a304d854e33..de3cc130ab8e 100644
--- a/arch/arm/mach-omap1/Makefile
+++ b/arch/arm/mach-omap1/Makefile
@@ -39,8 +39,8 @@ obj-$(CONFIG_MACH_OMAP_PALMTE) += board-palmte.o
39obj-$(CONFIG_MACH_OMAP_PALMZ71) += board-palmz71.o 39obj-$(CONFIG_MACH_OMAP_PALMZ71) += board-palmz71.o
40obj-$(CONFIG_MACH_OMAP_PALMTT) += board-palmtt.o 40obj-$(CONFIG_MACH_OMAP_PALMTT) += board-palmtt.o
41obj-$(CONFIG_MACH_NOKIA770) += board-nokia770.o 41obj-$(CONFIG_MACH_NOKIA770) += board-nokia770.o
42obj-$(CONFIG_MACH_AMS_DELTA) += board-ams-delta.o 42obj-$(CONFIG_MACH_AMS_DELTA) += board-ams-delta.o ams-delta-fiq.o \
43obj-$(CONFIG_AMS_DELTA_FIQ) += ams-delta-fiq.o ams-delta-fiq-handler.o 43 ams-delta-fiq-handler.o
44obj-$(CONFIG_MACH_SX1) += board-sx1.o board-sx1-mmc.o 44obj-$(CONFIG_MACH_SX1) += board-sx1.o board-sx1-mmc.o
45obj-$(CONFIG_MACH_HERALD) += board-htcherald.o 45obj-$(CONFIG_MACH_HERALD) += board-htcherald.o
46 46
diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c
index 1d4163b9f0b7..9d97a72c5393 100644
--- a/arch/arm/mach-omap1/board-ams-delta.c
+++ b/arch/arm/mach-omap1/board-ams-delta.c
@@ -28,6 +28,7 @@
28#include <asm/mach/arch.h> 28#include <asm/mach/arch.h>
29#include <asm/mach/map.h> 29#include <asm/mach/map.h>
30 30
31#include <plat/io.h>
31#include <plat/board-ams-delta.h> 32#include <plat/board-ams-delta.h>
32#include <mach/gpio.h> 33#include <mach/gpio.h>
33#include <plat/keypad.h> 34#include <plat/keypad.h>
@@ -307,16 +308,14 @@ static void __init ams_delta_init(void)
307#endif 308#endif
308 platform_add_devices(ams_delta_devices, ARRAY_SIZE(ams_delta_devices)); 309 platform_add_devices(ams_delta_devices, ARRAY_SIZE(ams_delta_devices));
309 310
310#ifdef CONFIG_AMS_DELTA_FIQ
311 ams_delta_init_fiq(); 311 ams_delta_init_fiq();
312#endif
313 312
314 omap_writew(omap_readw(ARM_RSTCT1) | 0x0004, ARM_RSTCT1); 313 omap_writew(omap_readw(ARM_RSTCT1) | 0x0004, ARM_RSTCT1);
315} 314}
316 315
317static struct plat_serial8250_port ams_delta_modem_ports[] = { 316static struct plat_serial8250_port ams_delta_modem_ports[] = {
318 { 317 {
319 .membase = (void *) AMS_DELTA_MODEM_VIRT, 318 .membase = IOMEM(AMS_DELTA_MODEM_VIRT),
320 .mapbase = AMS_DELTA_MODEM_PHYS, 319 .mapbase = AMS_DELTA_MODEM_PHYS,
321 .irq = -EINVAL, /* changed later */ 320 .irq = -EINVAL, /* changed later */
322 .flags = UPF_BOOT_AUTOCONF, 321 .flags = UPF_BOOT_AUTOCONF,
diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c
index e7f9ee63dce5..86ad38a20c3e 100644
--- a/arch/arm/mach-omap1/devices.c
+++ b/arch/arm/mach-omap1/devices.c
@@ -17,6 +17,7 @@
17#include <linux/io.h> 17#include <linux/io.h>
18#include <linux/spi/spi.h> 18#include <linux/spi/spi.h>
19 19
20#include <mach/camera.h>
20#include <mach/hardware.h> 21#include <mach/hardware.h>
21#include <asm/mach/map.h> 22#include <asm/mach/map.h>
22 23
diff --git a/arch/arm/mach-omap1/flash.c b/arch/arm/mach-omap1/flash.c
index 0b07a78eeaa7..acd161666408 100644
--- a/arch/arm/mach-omap1/flash.c
+++ b/arch/arm/mach-omap1/flash.c
@@ -11,6 +11,7 @@
11 11
12#include <plat/io.h> 12#include <plat/io.h>
13#include <plat/tc.h> 13#include <plat/tc.h>
14#include <plat/flash.h>
14 15
15void omap1_set_vpp(struct map_info *map, int enable) 16void omap1_set_vpp(struct map_info *map, int enable)
16{ 17{
diff --git a/arch/arm/mach-omap1/mailbox.c b/arch/arm/mach-omap1/mailbox.c
index 1a85a421007f..c0e1f48aa119 100644
--- a/arch/arm/mach-omap1/mailbox.c
+++ b/arch/arm/mach-omap1/mailbox.c
@@ -133,19 +133,18 @@ static struct omap_mbox1_priv omap1_mbox_dsp_priv = {
133 }, 133 },
134}; 134};
135 135
136struct omap_mbox mbox_dsp_info = { 136static struct omap_mbox mbox_dsp_info = {
137 .name = "dsp", 137 .name = "dsp",
138 .ops = &omap1_mbox_ops, 138 .ops = &omap1_mbox_ops,
139 .priv = &omap1_mbox_dsp_priv, 139 .priv = &omap1_mbox_dsp_priv,
140}; 140};
141 141
142struct omap_mbox *omap1_mboxes[] = { &mbox_dsp_info, NULL }; 142static struct omap_mbox *omap1_mboxes[] = { &mbox_dsp_info, NULL };
143 143
144static int __devinit omap1_mbox_probe(struct platform_device *pdev) 144static int __devinit omap1_mbox_probe(struct platform_device *pdev)
145{ 145{
146 struct resource *mem; 146 struct resource *mem;
147 int ret; 147 int ret;
148 int i;
149 struct omap_mbox **list; 148 struct omap_mbox **list;
150 149
151 list = omap1_mboxes; 150 list = omap1_mboxes;
diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c
index b3a796a6da03..372ea711faee 100644
--- a/arch/arm/mach-omap1/mcbsp.c
+++ b/arch/arm/mach-omap1/mcbsp.c
@@ -174,7 +174,7 @@ static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = {
174#define OMAP16XX_MCBSP_REG_NUM 0 174#define OMAP16XX_MCBSP_REG_NUM 0
175#endif 175#endif
176 176
177int __init omap1_mcbsp_init(void) 177static int __init omap1_mcbsp_init(void)
178{ 178{
179 if (cpu_is_omap7xx()) { 179 if (cpu_is_omap7xx()) {
180 omap_mcbsp_count = OMAP7XX_MCBSP_PDATA_SZ; 180 omap_mcbsp_count = OMAP7XX_MCBSP_PDATA_SZ;
diff --git a/arch/arm/mach-omap1/mux.c b/arch/arm/mach-omap1/mux.c
index 7835add00344..5fdef7a34828 100644
--- a/arch/arm/mach-omap1/mux.c
+++ b/arch/arm/mach-omap1/mux.c
@@ -343,7 +343,7 @@ MUX_CFG("Y14_1610_CCP_DATAM", 9, 21, 6, 2, 3, 1, 2, 0, 0)
343#define OMAP1XXX_PINS_SZ 0 343#define OMAP1XXX_PINS_SZ 0
344#endif /* CONFIG_ARCH_OMAP15XX || CONFIG_ARCH_OMAP16XX */ 344#endif /* CONFIG_ARCH_OMAP15XX || CONFIG_ARCH_OMAP16XX */
345 345
346int __init_or_module omap1_cfg_reg(const struct pin_config *cfg) 346static int __init_or_module omap1_cfg_reg(const struct pin_config *cfg)
347{ 347{
348 static DEFINE_SPINLOCK(mux_spin_lock); 348 static DEFINE_SPINLOCK(mux_spin_lock);
349 unsigned long flags; 349 unsigned long flags;
diff --git a/arch/arm/mach-omap1/serial.c b/arch/arm/mach-omap1/serial.c
index b78d0749f13d..9e1c4d442d3e 100644
--- a/arch/arm/mach-omap1/serial.c
+++ b/arch/arm/mach-omap1/serial.c
@@ -27,6 +27,8 @@
27#include <mach/gpio.h> 27#include <mach/gpio.h>
28#include <plat/fpga.h> 28#include <plat/fpga.h>
29 29
30#include "pm.h"
31
30static struct clk * uart1_ck; 32static struct clk * uart1_ck;
31static struct clk * uart2_ck; 33static struct clk * uart2_ck;
32static struct clk * uart3_ck; 34static struct clk * uart3_ck;
@@ -52,9 +54,11 @@ static inline void omap_serial_outp(struct plat_serial8250_port *p, int offset,
52 */ 54 */
53static void __init omap_serial_reset(struct plat_serial8250_port *p) 55static void __init omap_serial_reset(struct plat_serial8250_port *p)
54{ 56{
55 omap_serial_outp(p, UART_OMAP_MDR1, 0x07); /* disable UART */ 57 omap_serial_outp(p, UART_OMAP_MDR1,
58 UART_OMAP_MDR1_DISABLE); /* disable UART */
56 omap_serial_outp(p, UART_OMAP_SCR, 0x08); /* TX watermark */ 59 omap_serial_outp(p, UART_OMAP_SCR, 0x08); /* TX watermark */
57 omap_serial_outp(p, UART_OMAP_MDR1, 0x00); /* enable UART */ 60 omap_serial_outp(p, UART_OMAP_MDR1,
61 UART_OMAP_MDR1_16X_MODE); /* enable UART */
58 62
59 if (!cpu_is_omap15xx()) { 63 if (!cpu_is_omap15xx()) {
60 omap_serial_outp(p, UART_OMAP_SYSC, 0x01); 64 omap_serial_outp(p, UART_OMAP_SYSC, 0x01);
diff --git a/arch/arm/mach-omap1/time.c b/arch/arm/mach-omap1/time.c
index 1be6a214d88d..7f75bc614ec0 100644
--- a/arch/arm/mach-omap1/time.c
+++ b/arch/arm/mach-omap1/time.c
@@ -52,6 +52,7 @@
52#include <asm/mach/irq.h> 52#include <asm/mach/irq.h>
53#include <asm/mach/time.h> 53#include <asm/mach/time.h>
54 54
55#include <plat/common.h>
55 56
56#define OMAP_MPU_TIMER_BASE OMAP_MPU_TIMER1_BASE 57#define OMAP_MPU_TIMER_BASE OMAP_MPU_TIMER1_BASE
57#define OMAP_MPU_TIMER_OFFSET 0x100 58#define OMAP_MPU_TIMER_OFFSET 0x100
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index ab784bfde908..144e7bb7c88c 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -85,6 +85,12 @@ config OMAP_PACKAGE_CUS
85config OMAP_PACKAGE_CBP 85config OMAP_PACKAGE_CBP
86 bool 86 bool
87 87
88config OMAP_PACKAGE_CBL
89 bool
90
91config OMAP_PACKAGE_CBS
92 bool
93
88comment "OMAP Board Type" 94comment "OMAP Board Type"
89 depends on ARCH_OMAP2PLUS 95 depends on ARCH_OMAP2PLUS
90 96
@@ -128,7 +134,6 @@ config MACH_DEVKIT8000
128 depends on ARCH_OMAP3 134 depends on ARCH_OMAP3
129 default y 135 default y
130 select OMAP_PACKAGE_CUS 136 select OMAP_PACKAGE_CUS
131 select OMAP_MUX
132 137
133config MACH_OMAP_LDP 138config MACH_OMAP_LDP
134 bool "OMAP3 LDP board" 139 bool "OMAP3 LDP board"
@@ -174,6 +179,11 @@ config MACH_OMAP3517EVM
174 default y 179 default y
175 select OMAP_PACKAGE_CBB 180 select OMAP_PACKAGE_CBB
176 181
182config MACH_CRANEBOARD
183 bool "AM3517/05 CRANE board"
184 depends on ARCH_OMAP3
185 select OMAP_PACKAGE_CBB
186
177config MACH_OMAP3_PANDORA 187config MACH_OMAP3_PANDORA
178 bool "OMAP3 Pandora" 188 bool "OMAP3 Pandora"
179 depends on ARCH_OMAP3 189 depends on ARCH_OMAP3
@@ -239,14 +249,12 @@ config MACH_CM_T35
239 depends on ARCH_OMAP3 249 depends on ARCH_OMAP3
240 default y 250 default y
241 select OMAP_PACKAGE_CUS 251 select OMAP_PACKAGE_CUS
242 select OMAP_MUX
243 252
244config MACH_CM_T3517 253config MACH_CM_T3517
245 bool "CompuLab CM-T3517 module" 254 bool "CompuLab CM-T3517 module"
246 depends on ARCH_OMAP3 255 depends on ARCH_OMAP3
247 default y 256 default y
248 select OMAP_PACKAGE_CBB 257 select OMAP_PACKAGE_CBB
249 select OMAP_MUX
250 258
251config MACH_IGEP0020 259config MACH_IGEP0020
252 bool "IGEP v2 board" 260 bool "IGEP v2 board"
@@ -265,7 +273,6 @@ config MACH_SBC3530
265 depends on ARCH_OMAP3 273 depends on ARCH_OMAP3
266 default y 274 default y
267 select OMAP_PACKAGE_CUS 275 select OMAP_PACKAGE_CUS
268 select OMAP_MUX
269 276
270config MACH_OMAP_3630SDP 277config MACH_OMAP_3630SDP
271 bool "OMAP3630 SDP board" 278 bool "OMAP3630 SDP board"
@@ -277,11 +284,15 @@ config MACH_OMAP_4430SDP
277 bool "OMAP 4430 SDP board" 284 bool "OMAP 4430 SDP board"
278 default y 285 default y
279 depends on ARCH_OMAP4 286 depends on ARCH_OMAP4
287 select OMAP_PACKAGE_CBL
288 select OMAP_PACKAGE_CBS
280 289
281config MACH_OMAP4_PANDA 290config MACH_OMAP4_PANDA
282 bool "OMAP4 Panda Board" 291 bool "OMAP4 Panda Board"
283 default y 292 default y
284 depends on ARCH_OMAP4 293 depends on ARCH_OMAP4
294 select OMAP_PACKAGE_CBL
295 select OMAP_PACKAGE_CBS
285 296
286config OMAP3_EMU 297config OMAP3_EMU
287 bool "OMAP3 debugging peripherals" 298 bool "OMAP3 debugging peripherals"
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 60e51bcf53bd..ce7b1f017670 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -42,6 +42,7 @@ AFLAGS_sram34xx.o :=-Wa,-march=armv7-a
42obj-$(CONFIG_ARCH_OMAP2420) += mux2420.o 42obj-$(CONFIG_ARCH_OMAP2420) += mux2420.o
43obj-$(CONFIG_ARCH_OMAP2430) += mux2430.o 43obj-$(CONFIG_ARCH_OMAP2430) += mux2430.o
44obj-$(CONFIG_ARCH_OMAP3) += mux34xx.o 44obj-$(CONFIG_ARCH_OMAP3) += mux34xx.o
45obj-$(CONFIG_ARCH_OMAP4) += mux44xx.o
45 46
46# SMS/SDRC 47# SMS/SDRC
47obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o 48obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o
@@ -144,12 +145,12 @@ obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51.o \
144 board-rx51-peripherals.o \ 145 board-rx51-peripherals.o \
145 board-rx51-video.o \ 146 board-rx51-video.o \
146 hsmmc.o 147 hsmmc.o
147obj-$(CONFIG_MACH_OMAP_ZOOM2) += board-zoom2.o \ 148obj-$(CONFIG_MACH_OMAP_ZOOM2) += board-zoom.o \
148 board-zoom-peripherals.o \ 149 board-zoom-peripherals.o \
149 board-flash.o \ 150 board-flash.o \
150 hsmmc.o \ 151 hsmmc.o \
151 board-zoom-debugboard.o 152 board-zoom-debugboard.o
152obj-$(CONFIG_MACH_OMAP_ZOOM3) += board-zoom3.o \ 153obj-$(CONFIG_MACH_OMAP_ZOOM3) += board-zoom.o \
153 board-zoom-peripherals.o \ 154 board-zoom-peripherals.o \
154 board-flash.o \ 155 board-flash.o \
155 hsmmc.o \ 156 hsmmc.o \
@@ -174,6 +175,8 @@ obj-$(CONFIG_MACH_OMAP4_PANDA) += board-omap4panda.o \
174 175
175obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o 176obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o
176 177
178obj-$(CONFIG_MACH_CRANEBOARD) += board-am3517crane.o
179
177obj-$(CONFIG_MACH_SBC3530) += board-omap3stalker.o \ 180obj-$(CONFIG_MACH_SBC3530) += board-omap3stalker.o \
178 hsmmc.o 181 hsmmc.o
179# Platform specific device init code 182# Platform specific device init code
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index b527f8d187ad..ee7ac993a277 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -218,8 +218,6 @@ static struct omap_usb_config sdp2430_usb_config __initdata = {
218static struct omap_board_mux board_mux[] __initdata = { 218static struct omap_board_mux board_mux[] __initdata = {
219 { .reg_offset = OMAP_MUX_TERMINATOR }, 219 { .reg_offset = OMAP_MUX_TERMINATOR },
220}; 220};
221#else
222#define board_mux NULL
223#endif 221#endif
224 222
225static void __init omap_2430sdp_init(void) 223static void __init omap_2430sdp_init(void)
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index 4e3742c512b8..ad4cb262719e 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -663,8 +663,6 @@ static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
663static struct omap_board_mux board_mux[] __initdata = { 663static struct omap_board_mux board_mux[] __initdata = {
664 { .reg_offset = OMAP_MUX_TERMINATOR }, 664 { .reg_offset = OMAP_MUX_TERMINATOR },
665}; 665};
666#else
667#define board_mux NULL
668#endif 666#endif
669 667
670/* 668/*
diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c
index bbcf580fa097..4cd96d70b9c7 100644
--- a/arch/arm/mach-omap2/board-3630sdp.c
+++ b/arch/arm/mach-omap2/board-3630sdp.c
@@ -83,8 +83,6 @@ static void __init omap_sdp_init_irq(void)
83static struct omap_board_mux board_mux[] __initdata = { 83static struct omap_board_mux board_mux[] __initdata = {
84 { .reg_offset = OMAP_MUX_TERMINATOR }, 84 { .reg_offset = OMAP_MUX_TERMINATOR },
85}; 85};
86#else
87#define board_mux NULL
88#endif 86#endif
89 87
90/* 88/*
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index df5a425a49d1..94d989bee8ad 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -35,6 +35,7 @@
35#include <plat/usb.h> 35#include <plat/usb.h>
36#include <plat/mmc.h> 36#include <plat/mmc.h>
37 37
38#include "mux.h"
38#include "hsmmc.h" 39#include "hsmmc.h"
39#include "timer-gp.h" 40#include "timer-gp.h"
40#include "control.h" 41#include "control.h"
@@ -505,9 +506,22 @@ static void __init omap_sfh7741prox_init(void)
505 } 506 }
506} 507}
507 508
509#ifdef CONFIG_OMAP_MUX
510static struct omap_board_mux board_mux[] __initdata = {
511 { .reg_offset = OMAP_MUX_TERMINATOR },
512};
513#else
514#define board_mux NULL
515#endif
516
508static void __init omap_4430sdp_init(void) 517static void __init omap_4430sdp_init(void)
509{ 518{
510 int status; 519 int status;
520 int package = OMAP_PACKAGE_CBS;
521
522 if (omap_rev() == OMAP4430_REV_ES1_0)
523 package = OMAP_PACKAGE_CBL;
524 omap4_mux_init(board_mux, package);
511 525
512 omap4_i2c_init(); 526 omap4_i2c_init();
513 omap_sfh7741prox_init(); 527 omap_sfh7741prox_init();
diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c
new file mode 100644
index 000000000000..13ead330e389
--- /dev/null
+++ b/arch/arm/mach-omap2/board-am3517crane.c
@@ -0,0 +1,69 @@
1/*
2 * Support for AM3517/05 Craneboard
3 * http://www.mistralsolutions.com/products/craneboard.php
4 *
5 * Copyright (C) 2010 Mistral Solutions Pvt Ltd. <www.mistralsolutions.com>
6 * Author: R.Srinath <srinath@mistralsolutions.com>
7 *
8 * Based on mach-omap2/board-am3517evm.c
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation version 2.
13 *
14 * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
15 * whether express or implied; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 */
19
20#include <linux/kernel.h>
21#include <linux/init.h>
22#include <linux/gpio.h>
23
24#include <mach/hardware.h>
25#include <asm/mach-types.h>
26#include <asm/mach/arch.h>
27#include <asm/mach/map.h>
28
29#include <plat/board.h>
30#include <plat/common.h>
31
32#include "mux.h"
33
34/* Board initialization */
35static struct omap_board_config_kernel am3517_crane_config[] __initdata = {
36};
37
38#ifdef CONFIG_OMAP_MUX
39static struct omap_board_mux board_mux[] __initdata = {
40 { .reg_offset = OMAP_MUX_TERMINATOR },
41};
42#else
43#define board_mux NULL
44#endif
45
46static void __init am3517_crane_init_irq(void)
47{
48 omap_board_config = am3517_crane_config;
49 omap_board_config_size = ARRAY_SIZE(am3517_crane_config);
50
51 omap2_init_common_hw(NULL, NULL);
52 omap_init_irq();
53 omap_gpio_init();
54}
55
56static void __init am3517_crane_init(void)
57{
58 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
59 omap_serial_init();
60}
61
62MACHINE_START(CRANEBOARD, "AM3517/05 CRANEBOARD")
63 .boot_params = 0x80000100,
64 .map_io = omap3_map_io,
65 .reserve = omap_reserve,
66 .init_irq = am3517_crane_init_irq,
67 .init_machine = am3517_crane_init,
68 .timer = &omap_timer,
69MACHINE_END
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index 07399505312b..63035d8231ef 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -442,8 +442,6 @@ static struct omap_board_mux board_mux[] __initdata = {
442 OMAP3_MUX(SAD2D_MCAD23, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN), 442 OMAP3_MUX(SAD2D_MCAD23, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
443 { .reg_offset = OMAP_MUX_TERMINATOR }, 443 { .reg_offset = OMAP_MUX_TERMINATOR },
444}; 444};
445#else
446#define board_mux NULL
447#endif 445#endif
448 446
449 447
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index 2c6db1aaeb29..b01d6e422d7a 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -314,8 +314,6 @@ static void __init apollon_usb_init(void)
314static struct omap_board_mux board_mux[] __initdata = { 314static struct omap_board_mux board_mux[] __initdata = {
315 { .reg_offset = OMAP_MUX_TERMINATOR }, 315 { .reg_offset = OMAP_MUX_TERMINATOR },
316}; 316};
317#else
318#define board_mux NULL
319#endif 317#endif
320 318
321static void __init omap_apollon_init(void) 319static void __init omap_apollon_init(void)
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index 929993b4bf26..263da1da181c 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -321,8 +321,6 @@ static struct i2c_board_info __initdata h4_i2c_board_info[] = {
321static struct omap_board_mux board_mux[] __initdata = { 321static struct omap_board_mux board_mux[] __initdata = {
322 { .reg_offset = OMAP_MUX_TERMINATOR }, 322 { .reg_offset = OMAP_MUX_TERMINATOR },
323}; 323};
324#else
325#define board_mux NULL
326#endif 324#endif
327 325
328static void __init omap_h4_init(void) 326static void __init omap_h4_init(void)
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index 5e035a58b809..6f8f9b4533f9 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -136,16 +136,9 @@ static struct mtd_partition igep2_onenand_partitions[] = {
136 }, 136 },
137}; 137};
138 138
139static int igep2_onenand_setup(void __iomem *onenand_base, int freq)
140{
141 /* nothing is required to be setup for onenand as of now */
142 return 0;
143}
144
145static struct omap_onenand_platform_data igep2_onenand_data = { 139static struct omap_onenand_platform_data igep2_onenand_data = {
146 .parts = igep2_onenand_partitions, 140 .parts = igep2_onenand_partitions,
147 .nr_parts = ARRAY_SIZE(igep2_onenand_partitions), 141 .nr_parts = ARRAY_SIZE(igep2_onenand_partitions),
148 .onenand_setup = igep2_onenand_setup,
149 .dma_channel = -1, /* disable DMA in OMAP OneNAND driver */ 142 .dma_channel = -1, /* disable DMA in OMAP OneNAND driver */
150}; 143};
151 144
@@ -159,35 +152,34 @@ static struct platform_device igep2_onenand_device = {
159 152
160static void __init igep2_flash_init(void) 153static void __init igep2_flash_init(void)
161{ 154{
162 u8 cs = 0; 155 u8 cs = 0;
163 u8 onenandcs = GPMC_CS_NUM + 1; 156 u8 onenandcs = GPMC_CS_NUM + 1;
164 157
165 while (cs < GPMC_CS_NUM) { 158 for (cs = 0; cs < GPMC_CS_NUM; cs++) {
166 u32 ret = 0; 159 u32 ret;
167 ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); 160 ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
168 161
169 /* Check if NAND/oneNAND is configured */ 162 /* Check if NAND/oneNAND is configured */
170 if ((ret & 0xC00) == 0x800) 163 if ((ret & 0xC00) == 0x800)
171 /* NAND found */ 164 /* NAND found */
172 pr_err("IGEP v2: Unsupported NAND found\n"); 165 pr_err("IGEP2: Unsupported NAND found\n");
173 else { 166 else {
174 ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); 167 ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
175 if ((ret & 0x3F) == (ONENAND_MAP >> 24)) 168 if ((ret & 0x3F) == (ONENAND_MAP >> 24))
176 /* ONENAND found */ 169 /* ONENAND found */
177 onenandcs = cs; 170 onenandcs = cs;
178 } 171 }
179 cs++;
180 } 172 }
173
181 if (onenandcs > GPMC_CS_NUM) { 174 if (onenandcs > GPMC_CS_NUM) {
182 pr_err("IGEP v2: Unable to find configuration in GPMC\n"); 175 pr_err("IGEP2: Unable to find configuration in GPMC\n");
183 return; 176 return;
184 } 177 }
185 178
186 if (onenandcs < GPMC_CS_NUM) { 179 igep2_onenand_data.cs = onenandcs;
187 igep2_onenand_data.cs = onenandcs; 180
188 if (platform_device_register(&igep2_onenand_device) < 0) 181 if (platform_device_register(&igep2_onenand_device) < 0)
189 pr_err("IGEP v2: Unable to register OneNAND device\n"); 182 pr_err("IGEP2: Unable to register OneNAND device\n");
190 }
191} 183}
192 184
193#else 185#else
@@ -254,9 +246,6 @@ static inline void __init igep2_init_smsc911x(void)
254static inline void __init igep2_init_smsc911x(void) { } 246static inline void __init igep2_init_smsc911x(void) { }
255#endif 247#endif
256 248
257static struct omap_board_config_kernel igep2_config[] __initdata = {
258};
259
260static struct regulator_consumer_supply igep2_vmmc1_supply = { 249static struct regulator_consumer_supply igep2_vmmc1_supply = {
261 .supply = "vmmc", 250 .supply = "vmmc",
262}; 251};
@@ -493,8 +482,6 @@ static struct platform_device *igep2_devices[] __initdata = {
493 482
494static void __init igep2_init_irq(void) 483static void __init igep2_init_irq(void)
495{ 484{
496 omap_board_config = igep2_config;
497 omap_board_config_size = ARRAY_SIZE(igep2_config);
498 omap2_init_common_hw(m65kxxxxam_sdrc_params, m65kxxxxam_sdrc_params); 485 omap2_init_common_hw(m65kxxxxam_sdrc_params, m65kxxxxam_sdrc_params);
499 omap_init_irq(); 486 omap_init_irq();
500 omap_gpio_init(); 487 omap_gpio_init();
@@ -577,8 +564,6 @@ static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
577static struct omap_board_mux board_mux[] __initdata = { 564static struct omap_board_mux board_mux[] __initdata = {
578 { .reg_offset = OMAP_MUX_TERMINATOR }, 565 { .reg_offset = OMAP_MUX_TERMINATOR },
579}; 566};
580#else
581#define board_mux NULL
582#endif 567#endif
583 568
584#if defined(CONFIG_LIBERTAS_SDIO) || defined(CONFIG_LIBERTAS_SDIO_MODULE) 569#if defined(CONFIG_LIBERTAS_SDIO) || defined(CONFIG_LIBERTAS_SDIO_MODULE)
diff --git a/arch/arm/mach-omap2/board-igep0030.c b/arch/arm/mach-omap2/board-igep0030.c
index 22b0b253e16b..8dc6ed3aa377 100644
--- a/arch/arm/mach-omap2/board-igep0030.c
+++ b/arch/arm/mach-omap2/board-igep0030.c
@@ -366,8 +366,6 @@ void __init igep3_wifi_bt_init(void) {}
366static struct omap_board_mux board_mux[] __initdata = { 366static struct omap_board_mux board_mux[] __initdata = {
367 { .reg_offset = OMAP_MUX_TERMINATOR }, 367 { .reg_offset = OMAP_MUX_TERMINATOR },
368}; 368};
369#else
370#define board_mux NULL
371#endif 369#endif
372 370
373static void __init igep3_init(void) 371static void __init igep3_init(void)
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index 001fd9713f39..84b4ea67d156 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -381,8 +381,6 @@ static struct platform_device *ldp_devices[] __initdata = {
381static struct omap_board_mux board_mux[] __initdata = { 381static struct omap_board_mux board_mux[] __initdata = {
382 { .reg_offset = OMAP_MUX_TERMINATOR }, 382 { .reg_offset = OMAP_MUX_TERMINATOR },
383}; 383};
384#else
385#define board_mux NULL
386#endif 384#endif
387 385
388static struct omap_musb_board_data musb_board_data = { 386static struct omap_musb_board_data musb_board_data = {
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
index e823c7042ab3..0a4bc7715c38 100644
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -184,23 +184,15 @@ static struct mtd_partition onenand_partitions[] = {
184 }, 184 },
185}; 185};
186 186
187static struct omap_onenand_platform_data board_onenand_data = { 187static struct omap_onenand_platform_data board_onenand_data[] = {
188 .cs = 0, 188 {
189 .gpio_irq = 26, 189 .cs = 0,
190 .parts = onenand_partitions, 190 .gpio_irq = 26,
191 .nr_parts = ARRAY_SIZE(onenand_partitions), 191 .parts = onenand_partitions,
192 .flags = ONENAND_SYNC_READ, 192 .nr_parts = ARRAY_SIZE(onenand_partitions),
193 .flags = ONENAND_SYNC_READ,
194 }
193}; 195};
194
195static void __init n8x0_onenand_init(void)
196{
197 gpmc_onenand_init(&board_onenand_data);
198}
199
200#else
201
202static void __init n8x0_onenand_init(void) {}
203
204#endif 196#endif
205 197
206#if defined(CONFIG_MENELAUS) && \ 198#if defined(CONFIG_MENELAUS) && \
@@ -653,8 +645,6 @@ static struct omap_board_mux board_mux[] __initdata = {
653 OMAP2420_MUX(EAC_AC_DOUT, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT), 645 OMAP2420_MUX(EAC_AC_DOUT, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT),
654 { .reg_offset = OMAP_MUX_TERMINATOR }, 646 { .reg_offset = OMAP_MUX_TERMINATOR },
655}; 647};
656#else
657#define board_mux NULL
658#endif 648#endif
659 649
660static void __init n8x0_init_machine(void) 650static void __init n8x0_init_machine(void)
@@ -671,7 +661,7 @@ static void __init n8x0_init_machine(void)
671 ARRAY_SIZE(n810_i2c_board_info_2)); 661 ARRAY_SIZE(n810_i2c_board_info_2));
672 662
673 omap_serial_init(); 663 omap_serial_init();
674 n8x0_onenand_init(); 664 gpmc_onenand_init(board_onenand_data);
675 n8x0_mmc_init(); 665 n8x0_mmc_init();
676 n8x0_usb_init(); 666 n8x0_usb_init();
677} 667}
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 14f42240ae79..d42c8c936053 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -548,8 +548,6 @@ static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
548static struct omap_board_mux board_mux[] __initdata = { 548static struct omap_board_mux board_mux[] __initdata = {
549 { .reg_offset = OMAP_MUX_TERMINATOR }, 549 { .reg_offset = OMAP_MUX_TERMINATOR },
550}; 550};
551#else
552#define board_mux NULL
553#endif 551#endif
554 552
555static struct omap_musb_board_data musb_board_data = { 553static struct omap_musb_board_data musb_board_data = {
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index b04365c6bb10..8f1e69a92056 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -654,8 +654,6 @@ static struct omap_board_mux board_mux[] __initdata = {
654 OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW), 654 OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW),
655 { .reg_offset = OMAP_MUX_TERMINATOR }, 655 { .reg_offset = OMAP_MUX_TERMINATOR },
656}; 656};
657#else
658#define board_mux NULL
659#endif 657#endif
660 658
661static struct omap_musb_board_data musb_board_data = { 659static struct omap_musb_board_data musb_board_data = {
diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c
index 5f7d2c1e7ef5..e2e9562f4de9 100644
--- a/arch/arm/mach-omap2/board-omap3logic.c
+++ b/arch/arm/mach-omap2/board-omap3logic.c
@@ -206,8 +206,6 @@ static void __init omap3logic_init_irq(void)
206static struct omap_board_mux board_mux[] __initdata = { 206static struct omap_board_mux board_mux[] __initdata = {
207 { .reg_offset = OMAP_MUX_TERMINATOR }, 207 { .reg_offset = OMAP_MUX_TERMINATOR },
208}; 208};
209#else
210#define board_mux NULL
211#endif 209#endif
212 210
213static void __init omap3logic_init(void) 211static void __init omap3logic_init(void)
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index 89ed1be2d62e..445b15843212 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -711,8 +711,6 @@ static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
711static struct omap_board_mux board_mux[] __initdata = { 711static struct omap_board_mux board_mux[] __initdata = {
712 { .reg_offset = OMAP_MUX_TERMINATOR }, 712 { .reg_offset = OMAP_MUX_TERMINATOR },
713}; 713};
714#else
715#define board_mux NULL
716#endif 714#endif
717 715
718static struct omap_musb_board_data musb_board_data = { 716static struct omap_musb_board_data musb_board_data = {
diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
index f25272125413..ba65fe8a9e10 100644
--- a/arch/arm/mach-omap2/board-omap3stalker.c
+++ b/arch/arm/mach-omap2/board-omap3stalker.c
@@ -616,8 +616,6 @@ static struct omap_board_mux board_mux[] __initdata = {
616 OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE), 616 OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE),
617 {.reg_offset = OMAP_MUX_TERMINATOR}, 617 {.reg_offset = OMAP_MUX_TERMINATOR},
618}; 618};
619#else
620#define board_mux NULL
621#endif 619#endif
622 620
623static struct omap_musb_board_data musb_board_data = { 621static struct omap_musb_board_data musb_board_data = {
diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
index 41104bb8774c..8d530a607f85 100644
--- a/arch/arm/mach-omap2/board-omap3touchbook.c
+++ b/arch/arm/mach-omap2/board-omap3touchbook.c
@@ -413,8 +413,6 @@ static struct omap_board_config_kernel omap3_touchbook_config[] __initdata = {
413static struct omap_board_mux board_mux[] __initdata = { 413static struct omap_board_mux board_mux[] __initdata = {
414 { .reg_offset = OMAP_MUX_TERMINATOR }, 414 { .reg_offset = OMAP_MUX_TERMINATOR },
415}; 415};
416#else
417#define board_mux NULL
418#endif 416#endif
419 417
420static void __init omap3_touchbook_init_irq(void) 418static void __init omap3_touchbook_init_irq(void)
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index 1ecd0a6cefb7..801f8146b00c 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -40,6 +40,7 @@
40 40
41#include "hsmmc.h" 41#include "hsmmc.h"
42#include "control.h" 42#include "control.h"
43#include "mux.h"
43 44
44#define GPIO_HUB_POWER 1 45#define GPIO_HUB_POWER 1
45#define GPIO_HUB_NRESET 62 46#define GPIO_HUB_NRESET 62
@@ -368,8 +369,23 @@ static int __init omap4_panda_i2c_init(void)
368 omap_register_i2c_bus(4, 400, NULL, 0); 369 omap_register_i2c_bus(4, 400, NULL, 0);
369 return 0; 370 return 0;
370} 371}
372
373#ifdef CONFIG_OMAP_MUX
374static struct omap_board_mux board_mux[] __initdata = {
375 { .reg_offset = OMAP_MUX_TERMINATOR },
376};
377#else
378#define board_mux NULL
379#endif
380
371static void __init omap4_panda_init(void) 381static void __init omap4_panda_init(void)
372{ 382{
383 int package = OMAP_PACKAGE_CBS;
384
385 if (omap_rev() == OMAP4430_REV_ES1_0)
386 package = OMAP_PACKAGE_CBL;
387 omap4_mux_init(board_mux, package);
388
373 omap4_panda_i2c_init(); 389 omap4_panda_i2c_init();
374 platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices)); 390 platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices));
375 omap_serial_init(); 391 omap_serial_init();
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index 7053bc0b46db..133b5ead830d 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -438,8 +438,6 @@ static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
438static struct omap_board_mux board_mux[] __initdata = { 438static struct omap_board_mux board_mux[] __initdata = {
439 { .reg_offset = OMAP_MUX_TERMINATOR }, 439 { .reg_offset = OMAP_MUX_TERMINATOR },
440}; 440};
441#else
442#define board_mux NULL
443#endif 441#endif
444 442
445static struct omap_musb_board_data musb_board_data = { 443static struct omap_musb_board_data musb_board_data = {
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index 3fec4d62a91a..126b724a5e2d 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -293,6 +293,8 @@ static struct omap_board_mux rx51_mmc2_off_mux[] = {
293 { .reg_offset = OMAP_MUX_TERMINATOR }, 293 { .reg_offset = OMAP_MUX_TERMINATOR },
294}; 294};
295 295
296static struct omap_mux_partition *partition;
297
296/* 298/*
297 * Current flows to eMMC when eMMC is off and the data lines are pulled up, 299 * Current flows to eMMC when eMMC is off and the data lines are pulled up,
298 * so pull them down. N.B. we pull 8 lines because we are using 8 lines. 300 * so pull them down. N.B. we pull 8 lines because we are using 8 lines.
@@ -300,9 +302,9 @@ static struct omap_board_mux rx51_mmc2_off_mux[] = {
300static void rx51_mmc2_remux(struct device *dev, int slot, int power_on) 302static void rx51_mmc2_remux(struct device *dev, int slot, int power_on)
301{ 303{
302 if (power_on) 304 if (power_on)
303 omap_mux_write_array(rx51_mmc2_on_mux); 305 omap_mux_write_array(partition, rx51_mmc2_on_mux);
304 else 306 else
305 omap_mux_write_array(rx51_mmc2_off_mux); 307 omap_mux_write_array(partition, rx51_mmc2_off_mux);
306} 308}
307 309
308static struct omap2_hsmmc_info mmc[] __initdata = { 310static struct omap2_hsmmc_info mmc[] __initdata = {
@@ -815,25 +817,15 @@ static struct mtd_partition onenand_partitions[] = {
815 }, 817 },
816}; 818};
817 819
818static struct omap_onenand_platform_data board_onenand_data = { 820static struct omap_onenand_platform_data board_onenand_data[] = {
819 .cs = 0, 821 {
820 .gpio_irq = 65, 822 .cs = 0,
821 .parts = onenand_partitions, 823 .gpio_irq = 65,
822 .nr_parts = ARRAY_SIZE(onenand_partitions), 824 .parts = onenand_partitions,
823 .flags = ONENAND_SYNC_READWRITE, 825 .nr_parts = ARRAY_SIZE(onenand_partitions),
826 .flags = ONENAND_SYNC_READWRITE,
827 }
824}; 828};
825
826static void __init board_onenand_init(void)
827{
828 gpmc_onenand_init(&board_onenand_data);
829}
830
831#else
832
833static inline void board_onenand_init(void)
834{
835}
836
837#endif 829#endif
838 830
839#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) 831#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
@@ -916,13 +908,17 @@ error:
916void __init rx51_peripherals_init(void) 908void __init rx51_peripherals_init(void)
917{ 909{
918 rx51_i2c_init(); 910 rx51_i2c_init();
919 board_onenand_init(); 911 gpmc_onenand_init(board_onenand_data);
920 board_smc91x_init(); 912 board_smc91x_init();
921 rx51_add_gpio_keys(); 913 rx51_add_gpio_keys();
922 rx51_init_wl1251(); 914 rx51_init_wl1251();
923 spi_register_board_info(rx51_peripherals_spi_board_info, 915 spi_register_board_info(rx51_peripherals_spi_board_info,
924 ARRAY_SIZE(rx51_peripherals_spi_board_info)); 916 ARRAY_SIZE(rx51_peripherals_spi_board_info));
925 omap2_hsmmc_init(mmc); 917
918 partition = omap_mux_get("core");
919 if (partition)
920 omap2_hsmmc_init(mmc);
921
926 platform_device_register(&rx51_charger_device); 922 platform_device_register(&rx51_charger_device);
927} 923}
928 924
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
index 36f2cf4efd57..f3b6e103b01c 100644
--- a/arch/arm/mach-omap2/board-rx51.c
+++ b/arch/arm/mach-omap2/board-rx51.c
@@ -117,8 +117,6 @@ extern void __init rx51_peripherals_init(void);
117static struct omap_board_mux board_mux[] __initdata = { 117static struct omap_board_mux board_mux[] __initdata = {
118 { .reg_offset = OMAP_MUX_TERMINATOR }, 118 { .reg_offset = OMAP_MUX_TERMINATOR },
119}; 119};
120#else
121#define board_mux NULL
122#endif 120#endif
123 121
124static struct omap_musb_board_data musb_board_data = { 122static struct omap_musb_board_data musb_board_data = {
diff --git a/arch/arm/mach-omap2/board-zoom3.c b/arch/arm/mach-omap2/board-zoom.c
index 5adde12c0395..27979fd527d3 100644
--- a/arch/arm/mach-omap2/board-zoom3.c
+++ b/arch/arm/mach-omap2/board-zoom.c
@@ -1,6 +1,9 @@
1/* 1/*
2 * Copyright (C) 2009 Texas Instruments Inc. 2 * Copyright (C) 2009-2010 Texas Instruments Inc.
3 * Mikkel Christensen <mlc@ti.com>
4 * Felipe Balbi <balbi@ti.com>
3 * 5 *
6 * Modified from mach-omap2/board-ldp.c
4 * 7 *
5 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
@@ -12,22 +15,55 @@
12#include <linux/platform_device.h> 15#include <linux/platform_device.h>
13#include <linux/input.h> 16#include <linux/input.h>
14#include <linux/gpio.h> 17#include <linux/gpio.h>
18#include <linux/i2c/twl.h>
15 19
16#include <asm/mach-types.h> 20#include <asm/mach-types.h>
17#include <asm/mach/arch.h> 21#include <asm/mach/arch.h>
18 22
19#include <mach/board-zoom.h>
20
21#include <plat/common.h> 23#include <plat/common.h>
22#include <plat/board.h> 24#include <plat/board.h>
23#include <plat/usb.h> 25#include <plat/usb.h>
24 26
27#include <mach/board-zoom.h>
28
25#include "board-flash.h" 29#include "board-flash.h"
26#include "mux.h" 30#include "mux.h"
31#include "sdram-micron-mt46h32m32lf-6.h"
27#include "sdram-hynix-h8mbx00u0mer-0em.h" 32#include "sdram-hynix-h8mbx00u0mer-0em.h"
28 33
29static struct omap_board_config_kernel zoom_config[] __initdata = { 34#define ZOOM3_EHCI_RESET_GPIO 64
35
36static void __init omap_zoom_init_irq(void)
37{
38 if (machine_is_omap_zoom2())
39 omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
40 mt46h32m32lf6_sdrc_params);
41 else if (machine_is_omap_zoom3())
42 omap2_init_common_hw(h8mbx00u0mer0em_sdrc_params,
43 h8mbx00u0mer0em_sdrc_params);
44
45 omap_init_irq();
46 omap_gpio_init();
47}
48
49#ifdef CONFIG_OMAP_MUX
50static struct omap_board_mux board_mux[] __initdata = {
51 /* WLAN IRQ - GPIO 162 */
52 OMAP3_MUX(MCBSP1_CLKX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP),
53 /* WLAN POWER ENABLE - GPIO 101 */
54 OMAP3_MUX(CAM_D2, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
55 /* WLAN SDIO: MMC3 CMD */
56 OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE3 | OMAP_PIN_INPUT_PULLUP),
57 /* WLAN SDIO: MMC3 CLK */
58 OMAP3_MUX(ETK_CLK, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
59 /* WLAN SDIO: MMC3 DAT[0-3] */
60 OMAP3_MUX(ETK_D3, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
61 OMAP3_MUX(ETK_D4, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
62 OMAP3_MUX(ETK_D5, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
63 OMAP3_MUX(ETK_D6, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
64 { .reg_offset = OMAP_MUX_TERMINATOR },
30}; 65};
66#endif
31 67
32static struct mtd_partition zoom_nand_partitions[] = { 68static struct mtd_partition zoom_nand_partitions[] = {
33 /* All the partition sizes are listed in terms of NAND block size */ 69 /* All the partition sizes are listed in terms of NAND block size */
@@ -70,59 +106,41 @@ static struct mtd_partition zoom_nand_partitions[] = {
70 }, 106 },
71}; 107};
72 108
73static void __init omap_zoom_init_irq(void)
74{
75 omap_board_config = zoom_config;
76 omap_board_config_size = ARRAY_SIZE(zoom_config);
77 omap2_init_common_hw(h8mbx00u0mer0em_sdrc_params,
78 h8mbx00u0mer0em_sdrc_params);
79 omap_init_irq();
80 omap_gpio_init();
81}
82
83#ifdef CONFIG_OMAP_MUX
84static struct omap_board_mux board_mux[] __initdata = {
85 /* WLAN IRQ - GPIO 162 */
86 OMAP3_MUX(MCBSP1_CLKX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP),
87 /* WLAN POWER ENABLE - GPIO 101 */
88 OMAP3_MUX(CAM_D2, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
89 /* WLAN SDIO: MMC3 CMD */
90 OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE3 | OMAP_PIN_INPUT_PULLUP),
91 /* WLAN SDIO: MMC3 CLK */
92 OMAP3_MUX(ETK_CLK, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
93 /* WLAN SDIO: MMC3 DAT[0-3] */
94 OMAP3_MUX(ETK_D3, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
95 OMAP3_MUX(ETK_D4, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
96 OMAP3_MUX(ETK_D5, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
97 OMAP3_MUX(ETK_D6, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
98 { .reg_offset = OMAP_MUX_TERMINATOR },
99};
100#else
101#define board_mux NULL
102#endif
103
104static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { 109static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
105 .port_mode[0] = EHCI_HCD_OMAP_MODE_UNKNOWN, 110 .port_mode[0] = EHCI_HCD_OMAP_MODE_UNKNOWN,
106 .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY, 111 .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY,
107 .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, 112 .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN,
108 .phy_reset = true, 113 .phy_reset = true,
109 .reset_gpio_port[0] = -EINVAL, 114 .reset_gpio_port[0] = -EINVAL,
110 .reset_gpio_port[1] = 64, 115 .reset_gpio_port[1] = ZOOM3_EHCI_RESET_GPIO,
111 .reset_gpio_port[2] = -EINVAL, 116 .reset_gpio_port[2] = -EINVAL,
112}; 117};
113 118
114static void __init omap_zoom_init(void) 119static void __init omap_zoom_init(void)
115{ 120{
116 omap3_mux_init(board_mux, OMAP_PACKAGE_CBP); 121 if (machine_is_omap_zoom2()) {
117 zoom_peripherals_init(); 122 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
123 } else if (machine_is_omap_zoom3()) {
124 omap3_mux_init(board_mux, OMAP_PACKAGE_CBP);
125 omap_mux_init_gpio(ZOOM3_EHCI_RESET_GPIO, OMAP_PIN_OUTPUT);
126 usb_ehci_init(&ehci_pdata);
127 }
128
118 board_nand_init(zoom_nand_partitions, 129 board_nand_init(zoom_nand_partitions,
119 ARRAY_SIZE(zoom_nand_partitions), ZOOM_NAND_CS); 130 ARRAY_SIZE(zoom_nand_partitions), ZOOM_NAND_CS);
120 zoom_debugboard_init(); 131 zoom_debugboard_init();
121 132 zoom_peripherals_init();
122 omap_mux_init_gpio(64, OMAP_PIN_OUTPUT);
123 usb_ehci_init(&ehci_pdata);
124} 133}
125 134
135MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board")
136 .boot_params = 0x80000100,
137 .map_io = omap3_map_io,
138 .reserve = omap_reserve,
139 .init_irq = omap_zoom_init_irq,
140 .init_machine = omap_zoom_init,
141 .timer = &omap_timer,
142MACHINE_END
143
126MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board") 144MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board")
127 .boot_params = 0x80000100, 145 .boot_params = 0x80000100,
128 .map_io = omap3_map_io, 146 .map_io = omap3_map_io,
diff --git a/arch/arm/mach-omap2/board-zoom2.c b/arch/arm/mach-omap2/board-zoom2.c
deleted file mode 100644
index 2992a9f3a585..000000000000
--- a/arch/arm/mach-omap2/board-zoom2.c
+++ /dev/null
@@ -1,117 +0,0 @@
1/*
2 * Copyright (C) 2009 Texas Instruments Inc.
3 * Mikkel Christensen <mlc@ti.com>
4 *
5 * Modified from mach-omap2/board-ldp.c
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/kernel.h>
13#include <linux/init.h>
14#include <linux/platform_device.h>
15#include <linux/input.h>
16#include <linux/gpio.h>
17#include <linux/i2c/twl.h>
18
19#include <asm/mach-types.h>
20#include <asm/mach/arch.h>
21
22#include <plat/common.h>
23#include <plat/board.h>
24
25#include <mach/board-zoom.h>
26
27#include "board-flash.h"
28#include "mux.h"
29#include "sdram-micron-mt46h32m32lf-6.h"
30
31static void __init omap_zoom2_init_irq(void)
32{
33 omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
34 mt46h32m32lf6_sdrc_params);
35 omap_init_irq();
36 omap_gpio_init();
37}
38
39#ifdef CONFIG_OMAP_MUX
40static struct omap_board_mux board_mux[] __initdata = {
41 /* WLAN IRQ - GPIO 162 */
42 OMAP3_MUX(MCBSP1_CLKX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP),
43 /* WLAN POWER ENABLE - GPIO 101 */
44 OMAP3_MUX(CAM_D2, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
45 /* WLAN SDIO: MMC3 CMD */
46 OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE3 | OMAP_PIN_INPUT_PULLUP),
47 /* WLAN SDIO: MMC3 CLK */
48 OMAP3_MUX(ETK_CLK, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
49 /* WLAN SDIO: MMC3 DAT[0-3] */
50 OMAP3_MUX(ETK_D3, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
51 OMAP3_MUX(ETK_D4, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
52 OMAP3_MUX(ETK_D5, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
53 OMAP3_MUX(ETK_D6, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP),
54 { .reg_offset = OMAP_MUX_TERMINATOR },
55};
56#else
57#define board_mux NULL
58#endif
59
60static struct mtd_partition zoom_nand_partitions[] = {
61 /* All the partition sizes are listed in terms of NAND block size */
62 {
63 .name = "X-Loader-NAND",
64 .offset = 0,
65 .size = 4 * (64 * 2048), /* 512KB, 0x80000 */
66 .mask_flags = MTD_WRITEABLE, /* force read-only */
67 },
68 {
69 .name = "U-Boot-NAND",
70 .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */
71 .size = 10 * (64 * 2048), /* 1.25MB, 0x140000 */
72 .mask_flags = MTD_WRITEABLE, /* force read-only */
73 },
74 {
75 .name = "Boot Env-NAND",
76 .offset = MTDPART_OFS_APPEND, /* Offset = 0x1c0000 */
77 .size = 2 * (64 * 2048), /* 256KB, 0x40000 */
78 },
79 {
80 .name = "Kernel-NAND",
81 .offset = MTDPART_OFS_APPEND, /* Offset = 0x0200000*/
82 .size = 240 * (64 * 2048), /* 30M, 0x1E00000 */
83 },
84 {
85 .name = "system",
86 .offset = MTDPART_OFS_APPEND, /* Offset = 0x2000000 */
87 .size = 3328 * (64 * 2048), /* 416M, 0x1A000000 */
88 },
89 {
90 .name = "userdata",
91 .offset = MTDPART_OFS_APPEND, /* Offset = 0x1C000000*/
92 .size = 256 * (64 * 2048), /* 32M, 0x2000000 */
93 },
94 {
95 .name = "cache",
96 .offset = MTDPART_OFS_APPEND, /* Offset = 0x1E000000*/
97 .size = 256 * (64 * 2048), /* 32M, 0x2000000 */
98 },
99};
100
101static void __init omap_zoom2_init(void)
102{
103 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
104 zoom_peripherals_init();
105 board_nand_init(zoom_nand_partitions,
106 ARRAY_SIZE(zoom_nand_partitions), ZOOM_NAND_CS);
107 zoom_debugboard_init();
108}
109
110MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board")
111 .boot_params = 0x80000100,
112 .map_io = omap3_map_io,
113 .reserve = omap_reserve,
114 .init_irq = omap_zoom2_init_irq,
115 .init_machine = omap_zoom2_init,
116 .timer = &omap_timer,
117MACHINE_END
diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h
index da51cc3ed7eb..9a106c04c4a0 100644
--- a/arch/arm/mach-omap2/cm-regbits-24xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-24xx.h
@@ -126,8 +126,12 @@
126#define OMAP24XX_ST_HDQ_MASK (1 << 23) 126#define OMAP24XX_ST_HDQ_MASK (1 << 23)
127#define OMAP2420_ST_I2C2_SHIFT 20 127#define OMAP2420_ST_I2C2_SHIFT 20
128#define OMAP2420_ST_I2C2_MASK (1 << 20) 128#define OMAP2420_ST_I2C2_MASK (1 << 20)
129#define OMAP2430_ST_I2CHS1_SHIFT 19
130#define OMAP2430_ST_I2CHS1_MASK (1 << 19)
129#define OMAP2420_ST_I2C1_SHIFT 19 131#define OMAP2420_ST_I2C1_SHIFT 19
130#define OMAP2420_ST_I2C1_MASK (1 << 19) 132#define OMAP2420_ST_I2C1_MASK (1 << 19)
133#define OMAP2430_ST_I2CHS2_SHIFT 20
134#define OMAP2430_ST_I2CHS2_MASK (1 << 20)
131#define OMAP24XX_ST_MCBSP2_SHIFT 16 135#define OMAP24XX_ST_MCBSP2_SHIFT 16
132#define OMAP24XX_ST_MCBSP2_MASK (1 << 16) 136#define OMAP24XX_ST_MCBSP2_MASK (1 << 16)
133#define OMAP24XX_ST_MCBSP1_SHIFT 15 137#define OMAP24XX_ST_MCBSP1_SHIFT 15
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 074536ae401f..3d71d93caab2 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -1,9 +1,9 @@
1/* 1/*
2 * linux/arch/arm/mach-omap2/mux.c 2 * linux/arch/arm/mach-omap2/mux.c
3 * 3 *
4 * OMAP2 and OMAP3 pin multiplexing configurations 4 * OMAP2, OMAP3 and OMAP4 pin multiplexing configurations
5 * 5 *
6 * Copyright (C) 2004 - 2008 Texas Instruments Inc. 6 * Copyright (C) 2004 - 2010 Texas Instruments Inc.
7 * Copyright (C) 2003 - 2008 Nokia Corporation 7 * Copyright (C) 2003 - 2008 Nokia Corporation
8 * 8 *
9 * Written by Tony Lindgren 9 * Written by Tony Lindgren
@@ -40,60 +40,72 @@
40 40
41#define OMAP_MUX_BASE_OFFSET 0x30 /* Offset from CTRL_BASE */ 41#define OMAP_MUX_BASE_OFFSET 0x30 /* Offset from CTRL_BASE */
42#define OMAP_MUX_BASE_SZ 0x5ca 42#define OMAP_MUX_BASE_SZ 0x5ca
43#define MUXABLE_GPIO_MODE3 BIT(0)
44 43
45struct omap_mux_entry { 44struct omap_mux_entry {
46 struct omap_mux mux; 45 struct omap_mux mux;
47 struct list_head node; 46 struct list_head node;
48}; 47};
49 48
50static unsigned long mux_phys; 49static LIST_HEAD(mux_partitions);
51static void __iomem *mux_base; 50static DEFINE_MUTEX(muxmode_mutex);
52static u8 omap_mux_flags;
53 51
54u16 omap_mux_read(u16 reg) 52struct omap_mux_partition *omap_mux_get(const char *name)
55{ 53{
56 if (cpu_is_omap24xx()) 54 struct omap_mux_partition *partition;
57 return __raw_readb(mux_base + reg); 55
56 list_for_each_entry(partition, &mux_partitions, node) {
57 if (!strcmp(name, partition->name))
58 return partition;
59 }
60
61 return NULL;
62}
63
64u16 omap_mux_read(struct omap_mux_partition *partition, u16 reg)
65{
66 if (partition->flags & OMAP_MUX_REG_8BIT)
67 return __raw_readb(partition->base + reg);
58 else 68 else
59 return __raw_readw(mux_base + reg); 69 return __raw_readw(partition->base + reg);
60} 70}
61 71
62void omap_mux_write(u16 val, u16 reg) 72void omap_mux_write(struct omap_mux_partition *partition, u16 val,
73 u16 reg)
63{ 74{
64 if (cpu_is_omap24xx()) 75 if (partition->flags & OMAP_MUX_REG_8BIT)
65 __raw_writeb(val, mux_base + reg); 76 __raw_writeb(val, partition->base + reg);
66 else 77 else
67 __raw_writew(val, mux_base + reg); 78 __raw_writew(val, partition->base + reg);
68} 79}
69 80
70void omap_mux_write_array(struct omap_board_mux *board_mux) 81void omap_mux_write_array(struct omap_mux_partition *partition,
82 struct omap_board_mux *board_mux)
71{ 83{
72 while (board_mux->reg_offset != OMAP_MUX_TERMINATOR) { 84 while (board_mux->reg_offset != OMAP_MUX_TERMINATOR) {
73 omap_mux_write(board_mux->value, board_mux->reg_offset); 85 omap_mux_write(partition, board_mux->value,
86 board_mux->reg_offset);
74 board_mux++; 87 board_mux++;
75 } 88 }
76} 89}
77 90
78static LIST_HEAD(muxmodes);
79static DEFINE_MUTEX(muxmode_mutex);
80
81#ifdef CONFIG_OMAP_MUX 91#ifdef CONFIG_OMAP_MUX
82 92
83static char *omap_mux_options; 93static char *omap_mux_options;
84 94
85int __init omap_mux_init_gpio(int gpio, int val) 95static int __init _omap_mux_init_gpio(struct omap_mux_partition *partition,
96 int gpio, int val)
86{ 97{
87 struct omap_mux_entry *e; 98 struct omap_mux_entry *e;
88 struct omap_mux *gpio_mux = NULL; 99 struct omap_mux *gpio_mux = NULL;
89 u16 old_mode; 100 u16 old_mode;
90 u16 mux_mode; 101 u16 mux_mode;
91 int found = 0; 102 int found = 0;
103 struct list_head *muxmodes = &partition->muxmodes;
92 104
93 if (!gpio) 105 if (!gpio)
94 return -EINVAL; 106 return -EINVAL;
95 107
96 list_for_each_entry(e, &muxmodes, node) { 108 list_for_each_entry(e, muxmodes, node) {
97 struct omap_mux *m = &e->mux; 109 struct omap_mux *m = &e->mux;
98 if (gpio == m->gpio) { 110 if (gpio == m->gpio) {
99 gpio_mux = m; 111 gpio_mux = m;
@@ -102,34 +114,50 @@ int __init omap_mux_init_gpio(int gpio, int val)
102 } 114 }
103 115
104 if (found == 0) { 116 if (found == 0) {
105 printk(KERN_ERR "mux: Could not set gpio%i\n", gpio); 117 pr_err("%s: Could not set gpio%i\n", __func__, gpio);
106 return -ENODEV; 118 return -ENODEV;
107 } 119 }
108 120
109 if (found > 1) { 121 if (found > 1) {
110 printk(KERN_INFO "mux: Multiple gpio paths (%d) for gpio%i\n", 122 pr_info("%s: Multiple gpio paths (%d) for gpio%i\n", __func__,
111 found, gpio); 123 found, gpio);
112 return -EINVAL; 124 return -EINVAL;
113 } 125 }
114 126
115 old_mode = omap_mux_read(gpio_mux->reg_offset); 127 old_mode = omap_mux_read(partition, gpio_mux->reg_offset);
116 mux_mode = val & ~(OMAP_MUX_NR_MODES - 1); 128 mux_mode = val & ~(OMAP_MUX_NR_MODES - 1);
117 if (omap_mux_flags & MUXABLE_GPIO_MODE3) 129 if (partition->flags & OMAP_MUX_GPIO_IN_MODE3)
118 mux_mode |= OMAP_MUX_MODE3; 130 mux_mode |= OMAP_MUX_MODE3;
119 else 131 else
120 mux_mode |= OMAP_MUX_MODE4; 132 mux_mode |= OMAP_MUX_MODE4;
121 printk(KERN_DEBUG "mux: Setting signal %s.gpio%i 0x%04x -> 0x%04x\n", 133 pr_debug("%s: Setting signal %s.gpio%i 0x%04x -> 0x%04x\n", __func__,
122 gpio_mux->muxnames[0], gpio, old_mode, mux_mode); 134 gpio_mux->muxnames[0], gpio, old_mode, mux_mode);
123 omap_mux_write(mux_mode, gpio_mux->reg_offset); 135 omap_mux_write(partition, mux_mode, gpio_mux->reg_offset);
124 136
125 return 0; 137 return 0;
126} 138}
127 139
128int __init omap_mux_init_signal(const char *muxname, int val) 140int __init omap_mux_init_gpio(int gpio, int val)
141{
142 struct omap_mux_partition *partition;
143 int ret;
144
145 list_for_each_entry(partition, &mux_partitions, node) {
146 ret = _omap_mux_init_gpio(partition, gpio, val);
147 if (!ret)
148 return ret;
149 }
150
151 return -ENODEV;
152}
153
154static int __init _omap_mux_init_signal(struct omap_mux_partition *partition,
155 const char *muxname, int val)
129{ 156{
130 struct omap_mux_entry *e; 157 struct omap_mux_entry *e;
131 const char *mode_name; 158 const char *mode_name;
132 int found = 0, mode0_len = 0; 159 int found = 0, mode0_len = 0;
160 struct list_head *muxmodes = &partition->muxmodes;
133 161
134 mode_name = strchr(muxname, '.'); 162 mode_name = strchr(muxname, '.');
135 if (mode_name) { 163 if (mode_name) {
@@ -139,7 +167,7 @@ int __init omap_mux_init_signal(const char *muxname, int val)
139 mode_name = muxname; 167 mode_name = muxname;
140 } 168 }
141 169
142 list_for_each_entry(e, &muxmodes, node) { 170 list_for_each_entry(e, muxmodes, node) {
143 struct omap_mux *m = &e->mux; 171 struct omap_mux *m = &e->mux;
144 char *m0_entry = m->muxnames[0]; 172 char *m0_entry = m->muxnames[0];
145 int i; 173 int i;
@@ -159,12 +187,14 @@ int __init omap_mux_init_signal(const char *muxname, int val)
159 u16 old_mode; 187 u16 old_mode;
160 u16 mux_mode; 188 u16 mux_mode;
161 189
162 old_mode = omap_mux_read(m->reg_offset); 190 old_mode = omap_mux_read(partition,
191 m->reg_offset);
163 mux_mode = val | i; 192 mux_mode = val | i;
164 printk(KERN_DEBUG "mux: Setting signal " 193 pr_debug("%s: Setting signal "
165 "%s.%s 0x%04x -> 0x%04x\n", 194 "%s.%s 0x%04x -> 0x%04x\n", __func__,
166 m0_entry, muxname, old_mode, mux_mode); 195 m0_entry, muxname, old_mode, mux_mode);
167 omap_mux_write(mux_mode, m->reg_offset); 196 omap_mux_write(partition, mux_mode,
197 m->reg_offset);
168 found++; 198 found++;
169 } 199 }
170 } 200 }
@@ -174,16 +204,31 @@ int __init omap_mux_init_signal(const char *muxname, int val)
174 return 0; 204 return 0;
175 205
176 if (found > 1) { 206 if (found > 1) {
177 printk(KERN_ERR "mux: Multiple signal paths (%i) for %s\n", 207 pr_err("%s: Multiple signal paths (%i) for %s\n", __func__,
178 found, muxname); 208 found, muxname);
179 return -EINVAL; 209 return -EINVAL;
180 } 210 }
181 211
182 printk(KERN_ERR "mux: Could not set signal %s\n", muxname); 212 pr_err("%s: Could not set signal %s\n", __func__, muxname);
183 213
184 return -ENODEV; 214 return -ENODEV;
185} 215}
186 216
217int __init omap_mux_init_signal(const char *muxname, int val)
218{
219 struct omap_mux_partition *partition;
220 int ret;
221
222 list_for_each_entry(partition, &mux_partitions, node) {
223 ret = _omap_mux_init_signal(partition, muxname, val);
224 if (!ret)
225 return ret;
226 }
227
228 return -ENODEV;
229
230}
231
187#ifdef CONFIG_DEBUG_FS 232#ifdef CONFIG_DEBUG_FS
188 233
189#define OMAP_MUX_MAX_NR_FLAGS 10 234#define OMAP_MUX_MAX_NR_FLAGS 10
@@ -248,13 +293,15 @@ static inline void omap_mux_decode(struct seq_file *s, u16 val)
248 } while (i-- > 0); 293 } while (i-- > 0);
249} 294}
250 295
251#define OMAP_MUX_DEFNAME_LEN 16 296#define OMAP_MUX_DEFNAME_LEN 32
252 297
253static int omap_mux_dbg_board_show(struct seq_file *s, void *unused) 298static int omap_mux_dbg_board_show(struct seq_file *s, void *unused)
254{ 299{
300 struct omap_mux_partition *partition = s->private;
255 struct omap_mux_entry *e; 301 struct omap_mux_entry *e;
302 u8 omap_gen = omap_rev() >> 28;
256 303
257 list_for_each_entry(e, &muxmodes, node) { 304 list_for_each_entry(e, &partition->muxmodes, node) {
258 struct omap_mux *m = &e->mux; 305 struct omap_mux *m = &e->mux;
259 char m0_def[OMAP_MUX_DEFNAME_LEN]; 306 char m0_def[OMAP_MUX_DEFNAME_LEN];
260 char *m0_name = m->muxnames[0]; 307 char *m0_name = m->muxnames[0];
@@ -272,11 +319,16 @@ static int omap_mux_dbg_board_show(struct seq_file *s, void *unused)
272 } 319 }
273 m0_def[i] = toupper(m0_name[i]); 320 m0_def[i] = toupper(m0_name[i]);
274 } 321 }
275 val = omap_mux_read(m->reg_offset); 322 val = omap_mux_read(partition, m->reg_offset);
276 mode = val & OMAP_MUX_MODE7; 323 mode = val & OMAP_MUX_MODE7;
277 324 if (mode != 0)
278 seq_printf(s, "OMAP%i_MUX(%s, ", 325 seq_printf(s, "/* %s */\n", m->muxnames[mode]);
279 cpu_is_omap34xx() ? 3 : 0, m0_def); 326
327 /*
328 * XXX: Might be revisited to support differences accross
329 * same OMAP generation.
330 */
331 seq_printf(s, "OMAP%d_MUX(%s, ", omap_gen, m0_def);
280 omap_mux_decode(s, val); 332 omap_mux_decode(s, val);
281 seq_printf(s, "),\n"); 333 seq_printf(s, "),\n");
282 } 334 }
@@ -286,7 +338,7 @@ static int omap_mux_dbg_board_show(struct seq_file *s, void *unused)
286 338
287static int omap_mux_dbg_board_open(struct inode *inode, struct file *file) 339static int omap_mux_dbg_board_open(struct inode *inode, struct file *file)
288{ 340{
289 return single_open(file, omap_mux_dbg_board_show, &inode->i_private); 341 return single_open(file, omap_mux_dbg_board_show, inode->i_private);
290} 342}
291 343
292static const struct file_operations omap_mux_dbg_board_fops = { 344static const struct file_operations omap_mux_dbg_board_fops = {
@@ -296,19 +348,43 @@ static const struct file_operations omap_mux_dbg_board_fops = {
296 .release = single_release, 348 .release = single_release,
297}; 349};
298 350
351static struct omap_mux_partition *omap_mux_get_partition(struct omap_mux *mux)
352{
353 struct omap_mux_partition *partition;
354
355 list_for_each_entry(partition, &mux_partitions, node) {
356 struct list_head *muxmodes = &partition->muxmodes;
357 struct omap_mux_entry *e;
358
359 list_for_each_entry(e, muxmodes, node) {
360 struct omap_mux *m = &e->mux;
361
362 if (m == mux)
363 return partition;
364 }
365 }
366
367 return NULL;
368}
369
299static int omap_mux_dbg_signal_show(struct seq_file *s, void *unused) 370static int omap_mux_dbg_signal_show(struct seq_file *s, void *unused)
300{ 371{
301 struct omap_mux *m = s->private; 372 struct omap_mux *m = s->private;
373 struct omap_mux_partition *partition;
302 const char *none = "NA"; 374 const char *none = "NA";
303 u16 val; 375 u16 val;
304 int mode; 376 int mode;
305 377
306 val = omap_mux_read(m->reg_offset); 378 partition = omap_mux_get_partition(m);
379 if (!partition)
380 return 0;
381
382 val = omap_mux_read(partition, m->reg_offset);
307 mode = val & OMAP_MUX_MODE7; 383 mode = val & OMAP_MUX_MODE7;
308 384
309 seq_printf(s, "name: %s.%s (0x%08lx/0x%03x = 0x%04x), b %s, t %s\n", 385 seq_printf(s, "name: %s.%s (0x%08x/0x%03x = 0x%04x), b %s, t %s\n",
310 m->muxnames[0], m->muxnames[mode], 386 m->muxnames[0], m->muxnames[mode],
311 mux_phys + m->reg_offset, m->reg_offset, val, 387 partition->phys + m->reg_offset, m->reg_offset, val,
312 m->balls[0] ? m->balls[0] : none, 388 m->balls[0] ? m->balls[0] : none,
313 m->balls[1] ? m->balls[1] : none); 389 m->balls[1] ? m->balls[1] : none);
314 seq_printf(s, "mode: "); 390 seq_printf(s, "mode: ");
@@ -330,14 +406,15 @@ static int omap_mux_dbg_signal_show(struct seq_file *s, void *unused)
330#define OMAP_MUX_MAX_ARG_CHAR 7 406#define OMAP_MUX_MAX_ARG_CHAR 7
331 407
332static ssize_t omap_mux_dbg_signal_write(struct file *file, 408static ssize_t omap_mux_dbg_signal_write(struct file *file,
333 const char __user *user_buf, 409 const char __user *user_buf,
334 size_t count, loff_t *ppos) 410 size_t count, loff_t *ppos)
335{ 411{
336 char buf[OMAP_MUX_MAX_ARG_CHAR]; 412 char buf[OMAP_MUX_MAX_ARG_CHAR];
337 struct seq_file *seqf; 413 struct seq_file *seqf;
338 struct omap_mux *m; 414 struct omap_mux *m;
339 unsigned long val; 415 unsigned long val;
340 int buf_size, ret; 416 int buf_size, ret;
417 struct omap_mux_partition *partition;
341 418
342 if (count > OMAP_MUX_MAX_ARG_CHAR) 419 if (count > OMAP_MUX_MAX_ARG_CHAR)
343 return -EINVAL; 420 return -EINVAL;
@@ -358,7 +435,11 @@ static ssize_t omap_mux_dbg_signal_write(struct file *file,
358 seqf = file->private_data; 435 seqf = file->private_data;
359 m = seqf->private; 436 m = seqf->private;
360 437
361 omap_mux_write((u16)val, m->reg_offset); 438 partition = omap_mux_get_partition(m);
439 if (!partition)
440 return -ENODEV;
441
442 omap_mux_write(partition, (u16)val, m->reg_offset);
362 *ppos += count; 443 *ppos += count;
363 444
364 return count; 445 return count;
@@ -379,22 +460,38 @@ static const struct file_operations omap_mux_dbg_signal_fops = {
379 460
380static struct dentry *mux_dbg_dir; 461static struct dentry *mux_dbg_dir;
381 462
382static void __init omap_mux_dbg_init(void) 463static void __init omap_mux_dbg_create_entry(
464 struct omap_mux_partition *partition,
465 struct dentry *mux_dbg_dir)
383{ 466{
384 struct omap_mux_entry *e; 467 struct omap_mux_entry *e;
385 468
469 list_for_each_entry(e, &partition->muxmodes, node) {
470 struct omap_mux *m = &e->mux;
471
472 (void)debugfs_create_file(m->muxnames[0], S_IWUGO, mux_dbg_dir,
473 m, &omap_mux_dbg_signal_fops);
474 }
475}
476
477static void __init omap_mux_dbg_init(void)
478{
479 struct omap_mux_partition *partition;
480 static struct dentry *mux_dbg_board_dir;
481
386 mux_dbg_dir = debugfs_create_dir("omap_mux", NULL); 482 mux_dbg_dir = debugfs_create_dir("omap_mux", NULL);
387 if (!mux_dbg_dir) 483 if (!mux_dbg_dir)
388 return; 484 return;
389 485
390 (void)debugfs_create_file("board", S_IRUGO, mux_dbg_dir, 486 mux_dbg_board_dir = debugfs_create_dir("board", mux_dbg_dir);
391 NULL, &omap_mux_dbg_board_fops); 487 if (!mux_dbg_board_dir)
392 488 return;
393 list_for_each_entry(e, &muxmodes, node) {
394 struct omap_mux *m = &e->mux;
395 489
396 (void)debugfs_create_file(m->muxnames[0], S_IWUGO, mux_dbg_dir, 490 list_for_each_entry(partition, &mux_partitions, node) {
397 m, &omap_mux_dbg_signal_fops); 491 omap_mux_dbg_create_entry(partition, mux_dbg_dir);
492 (void)debugfs_create_file(partition->name, S_IRUGO,
493 mux_dbg_board_dir, partition,
494 &omap_mux_dbg_board_fops);
398 } 495 }
399} 496}
400 497
@@ -421,23 +518,25 @@ static void __init omap_mux_free_names(struct omap_mux *m)
421/* Free all data except for GPIO pins unless CONFIG_DEBUG_FS is set */ 518/* Free all data except for GPIO pins unless CONFIG_DEBUG_FS is set */
422static int __init omap_mux_late_init(void) 519static int __init omap_mux_late_init(void)
423{ 520{
424 struct omap_mux_entry *e, *tmp; 521 struct omap_mux_partition *partition;
425 522
426 list_for_each_entry_safe(e, tmp, &muxmodes, node) { 523 list_for_each_entry(partition, &mux_partitions, node) {
427 struct omap_mux *m = &e->mux; 524 struct omap_mux_entry *e, *tmp;
428 u16 mode = omap_mux_read(m->reg_offset); 525 list_for_each_entry_safe(e, tmp, &partition->muxmodes, node) {
526 struct omap_mux *m = &e->mux;
527 u16 mode = omap_mux_read(partition, m->reg_offset);
429 528
430 if (OMAP_MODE_GPIO(mode)) 529 if (OMAP_MODE_GPIO(mode))
431 continue; 530 continue;
432 531
433#ifndef CONFIG_DEBUG_FS 532#ifndef CONFIG_DEBUG_FS
434 mutex_lock(&muxmode_mutex); 533 mutex_lock(&muxmode_mutex);
435 list_del(&e->node); 534 list_del(&e->node);
436 mutex_unlock(&muxmode_mutex); 535 mutex_unlock(&muxmode_mutex);
437 omap_mux_free_names(m); 536 omap_mux_free_names(m);
438 kfree(m); 537 kfree(m);
439#endif 538#endif
440 539 }
441 } 540 }
442 541
443 omap_mux_dbg_init(); 542 omap_mux_dbg_init();
@@ -462,8 +561,8 @@ static void __init omap_mux_package_fixup(struct omap_mux *p,
462 s++; 561 s++;
463 } 562 }
464 if (!found) 563 if (!found)
465 printk(KERN_ERR "mux: Unknown entry offset 0x%x\n", 564 pr_err("%s: Unknown entry offset 0x%x\n", __func__,
466 p->reg_offset); 565 p->reg_offset);
467 p++; 566 p++;
468 } 567 }
469} 568}
@@ -487,8 +586,8 @@ static void __init omap_mux_package_init_balls(struct omap_ball *b,
487 s++; 586 s++;
488 } 587 }
489 if (!found) 588 if (!found)
490 printk(KERN_ERR "mux: Unknown ball offset 0x%x\n", 589 pr_err("%s: Unknown ball offset 0x%x\n", __func__,
491 b->reg_offset); 590 b->reg_offset);
492 b++; 591 b++;
493 } 592 }
494} 593}
@@ -554,7 +653,7 @@ static void __init omap_mux_set_cmdline_signals(void)
554} 653}
555 654
556static int __init omap_mux_copy_names(struct omap_mux *src, 655static int __init omap_mux_copy_names(struct omap_mux *src,
557 struct omap_mux *dst) 656 struct omap_mux *dst)
558{ 657{
559 int i; 658 int i;
560 659
@@ -592,51 +691,63 @@ free:
592 691
593#endif /* CONFIG_OMAP_MUX */ 692#endif /* CONFIG_OMAP_MUX */
594 693
595static u16 omap_mux_get_by_gpio(int gpio) 694static struct omap_mux *omap_mux_get_by_gpio(
695 struct omap_mux_partition *partition,
696 int gpio)
596{ 697{
597 struct omap_mux_entry *e; 698 struct omap_mux_entry *e;
598 u16 offset = OMAP_MUX_TERMINATOR; 699 struct omap_mux *ret = NULL;
599 700
600 list_for_each_entry(e, &muxmodes, node) { 701 list_for_each_entry(e, &partition->muxmodes, node) {
601 struct omap_mux *m = &e->mux; 702 struct omap_mux *m = &e->mux;
602 if (m->gpio == gpio) { 703 if (m->gpio == gpio) {
603 offset = m->reg_offset; 704 ret = m;
604 break; 705 break;
605 } 706 }
606 } 707 }
607 708
608 return offset; 709 return ret;
609} 710}
610 711
611/* Needed for dynamic muxing of GPIO pins for off-idle */ 712/* Needed for dynamic muxing of GPIO pins for off-idle */
612u16 omap_mux_get_gpio(int gpio) 713u16 omap_mux_get_gpio(int gpio)
613{ 714{
614 u16 offset; 715 struct omap_mux_partition *partition;
716 struct omap_mux *m;
615 717
616 offset = omap_mux_get_by_gpio(gpio); 718 list_for_each_entry(partition, &mux_partitions, node) {
617 if (offset == OMAP_MUX_TERMINATOR) { 719 m = omap_mux_get_by_gpio(partition, gpio);
618 printk(KERN_ERR "mux: Could not get gpio%i\n", gpio); 720 if (m)
619 return offset; 721 return omap_mux_read(partition, m->reg_offset);
620 } 722 }
621 723
622 return omap_mux_read(offset); 724 if (!m || m->reg_offset == OMAP_MUX_TERMINATOR)
725 pr_err("%s: Could not get gpio%i\n", __func__, gpio);
726
727 return OMAP_MUX_TERMINATOR;
623} 728}
624 729
625/* Needed for dynamic muxing of GPIO pins for off-idle */ 730/* Needed for dynamic muxing of GPIO pins for off-idle */
626void omap_mux_set_gpio(u16 val, int gpio) 731void omap_mux_set_gpio(u16 val, int gpio)
627{ 732{
628 u16 offset; 733 struct omap_mux_partition *partition;
734 struct omap_mux *m = NULL;
629 735
630 offset = omap_mux_get_by_gpio(gpio); 736 list_for_each_entry(partition, &mux_partitions, node) {
631 if (offset == OMAP_MUX_TERMINATOR) { 737 m = omap_mux_get_by_gpio(partition, gpio);
632 printk(KERN_ERR "mux: Could not set gpio%i\n", gpio); 738 if (m) {
633 return; 739 omap_mux_write(partition, val, m->reg_offset);
740 return;
741 }
634 } 742 }
635 743
636 omap_mux_write(val, offset); 744 if (!m || m->reg_offset == OMAP_MUX_TERMINATOR)
745 pr_err("%s: Could not set gpio%i\n", __func__, gpio);
637} 746}
638 747
639static struct omap_mux * __init omap_mux_list_add(struct omap_mux *src) 748static struct omap_mux * __init omap_mux_list_add(
749 struct omap_mux_partition *partition,
750 struct omap_mux *src)
640{ 751{
641 struct omap_mux_entry *entry; 752 struct omap_mux_entry *entry;
642 struct omap_mux *m; 753 struct omap_mux *m;
@@ -656,7 +767,7 @@ static struct omap_mux * __init omap_mux_list_add(struct omap_mux *src)
656#endif 767#endif
657 768
658 mutex_lock(&muxmode_mutex); 769 mutex_lock(&muxmode_mutex);
659 list_add_tail(&entry->node, &muxmodes); 770 list_add_tail(&entry->node, &partition->muxmodes);
660 mutex_unlock(&muxmode_mutex); 771 mutex_unlock(&muxmode_mutex);
661 772
662 return m; 773 return m;
@@ -667,7 +778,8 @@ static struct omap_mux * __init omap_mux_list_add(struct omap_mux *src)
667 * the GPIO to mux offset mapping that is needed for dynamic muxing 778 * the GPIO to mux offset mapping that is needed for dynamic muxing
668 * of GPIO pins for off-idle. 779 * of GPIO pins for off-idle.
669 */ 780 */
670static void __init omap_mux_init_list(struct omap_mux *superset) 781static void __init omap_mux_init_list(struct omap_mux_partition *partition,
782 struct omap_mux *superset)
671{ 783{
672 while (superset->reg_offset != OMAP_MUX_TERMINATOR) { 784 while (superset->reg_offset != OMAP_MUX_TERMINATOR) {
673 struct omap_mux *entry; 785 struct omap_mux *entry;
@@ -679,15 +791,16 @@ static void __init omap_mux_init_list(struct omap_mux *superset)
679 } 791 }
680#else 792#else
681 /* Skip pins that are not muxed as GPIO by bootloader */ 793 /* Skip pins that are not muxed as GPIO by bootloader */
682 if (!OMAP_MODE_GPIO(omap_mux_read(superset->reg_offset))) { 794 if (!OMAP_MODE_GPIO(omap_mux_read(partition,
795 superset->reg_offset))) {
683 superset++; 796 superset++;
684 continue; 797 continue;
685 } 798 }
686#endif 799#endif
687 800
688 entry = omap_mux_list_add(superset); 801 entry = omap_mux_list_add(partition, superset);
689 if (!entry) { 802 if (!entry) {
690 printk(KERN_ERR "mux: Could not add entry\n"); 803 pr_err("%s: Could not add entry\n", __func__);
691 return; 804 return;
692 } 805 }
693 superset++; 806 superset++;
@@ -706,10 +819,11 @@ static void omap_mux_init_package(struct omap_mux *superset,
706 omap_mux_package_init_balls(package_balls, superset); 819 omap_mux_package_init_balls(package_balls, superset);
707} 820}
708 821
709static void omap_mux_init_signals(struct omap_board_mux *board_mux) 822static void omap_mux_init_signals(struct omap_mux_partition *partition,
823 struct omap_board_mux *board_mux)
710{ 824{
711 omap_mux_set_cmdline_signals(); 825 omap_mux_set_cmdline_signals();
712 omap_mux_write_array(board_mux); 826 omap_mux_write_array(partition, board_mux);
713} 827}
714 828
715#else 829#else
@@ -720,34 +834,49 @@ static void omap_mux_init_package(struct omap_mux *superset,
720{ 834{
721} 835}
722 836
723static void omap_mux_init_signals(struct omap_board_mux *board_mux) 837static void omap_mux_init_signals(struct omap_mux_partition *partition,
838 struct omap_board_mux *board_mux)
724{ 839{
725} 840}
726 841
727#endif 842#endif
728 843
729int __init omap_mux_init(u32 mux_pbase, u32 mux_size, 844static u32 mux_partitions_cnt;
730 struct omap_mux *superset,
731 struct omap_mux *package_subset,
732 struct omap_board_mux *board_mux,
733 struct omap_ball *package_balls)
734{
735 if (mux_base)
736 return -EBUSY;
737 845
738 mux_phys = mux_pbase; 846int __init omap_mux_init(const char *name, u32 flags,
739 mux_base = ioremap(mux_pbase, mux_size); 847 u32 mux_pbase, u32 mux_size,
740 if (!mux_base) { 848 struct omap_mux *superset,
741 printk(KERN_ERR "mux: Could not ioremap\n"); 849 struct omap_mux *package_subset,
850 struct omap_board_mux *board_mux,
851 struct omap_ball *package_balls)
852{
853 struct omap_mux_partition *partition;
854
855 partition = kzalloc(sizeof(struct omap_mux_partition), GFP_KERNEL);
856 if (!partition)
857 return -ENOMEM;
858
859 partition->name = name;
860 partition->flags = flags;
861 partition->size = mux_size;
862 partition->phys = mux_pbase;
863 partition->base = ioremap(mux_pbase, mux_size);
864 if (!partition->base) {
865 pr_err("%s: Could not ioremap mux partition at 0x%08x\n",
866 __func__, partition->phys);
742 return -ENODEV; 867 return -ENODEV;
743 } 868 }
744 869
745 if (cpu_is_omap24xx()) 870 INIT_LIST_HEAD(&partition->muxmodes);
746 omap_mux_flags = MUXABLE_GPIO_MODE3; 871
872 list_add_tail(&partition->node, &mux_partitions);
873 mux_partitions_cnt++;
874 pr_info("%s: Add partition: #%d: %s, flags: %x\n", __func__,
875 mux_partitions_cnt, partition->name, partition->flags);
747 876
748 omap_mux_init_package(superset, package_subset, package_balls); 877 omap_mux_init_package(superset, package_subset, package_balls);
749 omap_mux_init_list(superset); 878 omap_mux_init_list(partition, superset);
750 omap_mux_init_signals(board_mux); 879 omap_mux_init_signals(partition, board_mux);
751 880
752 return 0; 881 return 0;
753} 882}
diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h
index 350c04f27383..f5f7f4938057 100644
--- a/arch/arm/mach-omap2/mux.h
+++ b/arch/arm/mach-omap2/mux.h
@@ -1,6 +1,6 @@
1/* 1/*
2 * Copyright (C) 2009 Nokia 2 * Copyright (C) 2009 Nokia
3 * Copyright (C) 2009 Texas Instruments 3 * Copyright (C) 2009-2010 Texas Instruments
4 * 4 *
5 * This program is free software; you can redistribute it and/or modify 5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as 6 * it under the terms of the GNU General Public License version 2 as
@@ -10,6 +10,7 @@
10#include "mux2420.h" 10#include "mux2420.h"
11#include "mux2430.h" 11#include "mux2430.h"
12#include "mux34xx.h" 12#include "mux34xx.h"
13#include "mux44xx.h"
13 14
14#define OMAP_MUX_TERMINATOR 0xffff 15#define OMAP_MUX_TERMINATOR 0xffff
15 16
@@ -37,6 +38,9 @@
37#define OMAP_OFF_PULL_UP (1 << 13) 38#define OMAP_OFF_PULL_UP (1 << 13)
38#define OMAP_WAKEUP_EN (1 << 14) 39#define OMAP_WAKEUP_EN (1 << 14)
39 40
41/* 44xx specific mux bit defines */
42#define OMAP_WAKEUP_EVENT (1 << 15)
43
40/* Active pin states */ 44/* Active pin states */
41#define OMAP_PIN_OUTPUT 0 45#define OMAP_PIN_OUTPUT 0
42#define OMAP_PIN_INPUT OMAP_INPUT_EN 46#define OMAP_PIN_INPUT OMAP_INPUT_EN
@@ -56,8 +60,10 @@
56 60
57#define OMAP_MODE_GPIO(x) (((x) & OMAP_MUX_MODE7) == OMAP_MUX_MODE4) 61#define OMAP_MODE_GPIO(x) (((x) & OMAP_MUX_MODE7) == OMAP_MUX_MODE4)
58 62
59/* Flags for omap_mux_init */ 63/* Flags for omapX_mux_init */
60#define OMAP_PACKAGE_MASK 0xffff 64#define OMAP_PACKAGE_MASK 0xffff
65#define OMAP_PACKAGE_CBS 8 /* 547-pin 0.40 0.40 */
66#define OMAP_PACKAGE_CBL 7 /* 547-pin 0.40 0.40 */
61#define OMAP_PACKAGE_CBP 6 /* 515-pin 0.40 0.50 */ 67#define OMAP_PACKAGE_CBP 6 /* 515-pin 0.40 0.50 */
62#define OMAP_PACKAGE_CUS 5 /* 423-pin 0.65 */ 68#define OMAP_PACKAGE_CUS 5 /* 423-pin 0.65 */
63#define OMAP_PACKAGE_CBB 4 /* 515-pin 0.40 0.50 */ 69#define OMAP_PACKAGE_CBB 4 /* 515-pin 0.40 0.50 */
@@ -66,14 +72,47 @@
66#define OMAP_PACKAGE_ZAF 1 /* 2420 447-pin SIP */ 72#define OMAP_PACKAGE_ZAF 1 /* 2420 447-pin SIP */
67 73
68 74
69#define OMAP_MUX_NR_MODES 8 /* Available modes */ 75#define OMAP_MUX_NR_MODES 8 /* Available modes */
70#define OMAP_MUX_NR_SIDES 2 /* Bottom & top */ 76#define OMAP_MUX_NR_SIDES 2 /* Bottom & top */
77
78/*
79 * omap_mux_init flags definition:
80 *
81 * OMAP_MUX_REG_8BIT: Ensure that access to padconf is done in 8 bits.
82 * The default value is 16 bits.
83 * OMAP_MUX_GPIO_IN_MODE3: The GPIO is selected in mode3.
84 * The default is mode4.
85 */
86#define OMAP_MUX_REG_8BIT (1 << 0)
87#define OMAP_MUX_GPIO_IN_MODE3 (1 << 1)
88
89/**
90 * struct mux_partition - contain partition related information
91 * @name: name of the current partition
92 * @flags: flags specific to this partition
93 * @phys: physical address
94 * @size: partition size
95 * @base: virtual address after ioremap
96 * @muxmodes: list of nodes that belong to a partition
97 * @node: list node for the partitions linked list
98 */
99struct omap_mux_partition {
100 const char *name;
101 u32 flags;
102 u32 phys;
103 u32 size;
104 void __iomem *base;
105 struct list_head muxmodes;
106 struct list_head node;
107};
71 108
72/** 109/**
73 * struct omap_mux - data for omap mux register offset and it's value 110 * struct omap_mux - data for omap mux register offset and it's value
74 * @reg_offset: mux register offset from the mux base 111 * @reg_offset: mux register offset from the mux base
75 * @gpio: GPIO number 112 * @gpio: GPIO number
76 * @muxnames: available signal modes for a ball 113 * @muxnames: available signal modes for a ball
114 * @balls: available balls on the package
115 * @partition: mux partition
77 */ 116 */
78struct omap_mux { 117struct omap_mux {
79 u16 reg_offset; 118 u16 reg_offset;
@@ -133,6 +172,8 @@ static inline int omap_mux_init_signal(char *muxname, int val)
133 return 0; 172 return 0;
134} 173}
135 174
175static struct omap_board_mux *board_mux __initdata __maybe_unused;
176
136#endif 177#endif
137 178
138/** 179/**
@@ -151,28 +192,39 @@ u16 omap_mux_get_gpio(int gpio);
151void omap_mux_set_gpio(u16 val, int gpio); 192void omap_mux_set_gpio(u16 val, int gpio);
152 193
153/** 194/**
195 * omap_mux_get() - get a mux partition by name
196 * @name: Name of the mux partition
197 *
198 */
199struct omap_mux_partition *omap_mux_get(const char *name);
200
201/**
154 * omap_mux_read() - read mux register 202 * omap_mux_read() - read mux register
203 * @partition: Mux partition
155 * @mux_offset: Offset of the mux register 204 * @mux_offset: Offset of the mux register
156 * 205 *
157 */ 206 */
158u16 omap_mux_read(u16 mux_offset); 207u16 omap_mux_read(struct omap_mux_partition *p, u16 mux_offset);
159 208
160/** 209/**
161 * omap_mux_write() - write mux register 210 * omap_mux_write() - write mux register
211 * @partition: Mux partition
162 * @val: New mux register value 212 * @val: New mux register value
163 * @mux_offset: Offset of the mux register 213 * @mux_offset: Offset of the mux register
164 * 214 *
165 * This should be only needed for dynamic remuxing of non-gpio signals. 215 * This should be only needed for dynamic remuxing of non-gpio signals.
166 */ 216 */
167void omap_mux_write(u16 val, u16 mux_offset); 217void omap_mux_write(struct omap_mux_partition *p, u16 val, u16 mux_offset);
168 218
169/** 219/**
170 * omap_mux_write_array() - write an array of mux registers 220 * omap_mux_write_array() - write an array of mux registers
221 * @partition: Mux partition
171 * @board_mux: Array of mux registers terminated by MAP_MUX_TERMINATOR 222 * @board_mux: Array of mux registers terminated by MAP_MUX_TERMINATOR
172 * 223 *
173 * This should be only needed for dynamic remuxing of non-gpio signals. 224 * This should be only needed for dynamic remuxing of non-gpio signals.
174 */ 225 */
175void omap_mux_write_array(struct omap_board_mux *board_mux); 226void omap_mux_write_array(struct omap_mux_partition *p,
227 struct omap_board_mux *board_mux);
176 228
177/** 229/**
178 * omap2420_mux_init() - initialize mux system with board specific set 230 * omap2420_mux_init() - initialize mux system with board specific set
@@ -196,10 +248,19 @@ int omap2430_mux_init(struct omap_board_mux *board_mux, int flags);
196int omap3_mux_init(struct omap_board_mux *board_mux, int flags); 248int omap3_mux_init(struct omap_board_mux *board_mux, int flags);
197 249
198/** 250/**
251 * omap4_mux_init() - initialize mux system with board specific set
252 * @board_mux: Board specific mux table
253 * @flags: OMAP package type used for the board
254 */
255int omap4_mux_init(struct omap_board_mux *board_mux, int flags);
256
257/**
199 * omap_mux_init - private mux init function, do not call 258 * omap_mux_init - private mux init function, do not call
200 */ 259 */
201int omap_mux_init(u32 mux_pbase, u32 mux_size, 260int omap_mux_init(const char *name, u32 flags,
202 struct omap_mux *superset, 261 u32 mux_pbase, u32 mux_size,
203 struct omap_mux *package_subset, 262 struct omap_mux *superset,
204 struct omap_board_mux *board_mux, 263 struct omap_mux *package_subset,
205 struct omap_ball *package_balls); 264 struct omap_board_mux *board_mux,
265 struct omap_ball *package_balls);
266
diff --git a/arch/arm/mach-omap2/mux2420.c b/arch/arm/mach-omap2/mux2420.c
index 414af5434456..cf6de0971c6c 100644
--- a/arch/arm/mach-omap2/mux2420.c
+++ b/arch/arm/mach-omap2/mux2420.c
@@ -678,11 +678,13 @@ int __init omap2420_mux_init(struct omap_board_mux *board_subset, int flags)
678 case OMAP_PACKAGE_ZAF: 678 case OMAP_PACKAGE_ZAF:
679 /* REVISIT: Please add data */ 679 /* REVISIT: Please add data */
680 default: 680 default:
681 pr_warning("mux: No ball data available for omap2420 package\n"); 681 pr_warning("%s: No ball data available for omap2420 package\n",
682 __func__);
682 } 683 }
683 684
684 return omap_mux_init(OMAP2420_CONTROL_PADCONF_MUX_PBASE, 685 return omap_mux_init("core", OMAP_MUX_REG_8BIT | OMAP_MUX_GPIO_IN_MODE3,
686 OMAP2420_CONTROL_PADCONF_MUX_PBASE,
685 OMAP2420_CONTROL_PADCONF_MUX_SIZE, 687 OMAP2420_CONTROL_PADCONF_MUX_SIZE,
686 omap2420_muxmodes, NULL, board_subset, 688 omap2420_muxmodes, NULL, board_subset,
687 package_balls); 689 package_balls);
688} 690}
diff --git a/arch/arm/mach-omap2/mux2430.c b/arch/arm/mach-omap2/mux2430.c
index 84d2c5a7ecd7..4185f92553db 100644
--- a/arch/arm/mach-omap2/mux2430.c
+++ b/arch/arm/mach-omap2/mux2430.c
@@ -781,11 +781,13 @@ int __init omap2430_mux_init(struct omap_board_mux *board_subset, int flags)
781 package_balls = omap2430_pop_ball; 781 package_balls = omap2430_pop_ball;
782 break; 782 break;
783 default: 783 default:
784 pr_warning("mux: No ball data available for omap2420 package\n"); 784 pr_warning("%s: No ball data available for omap2420 package\n",
785 __func__);
785 } 786 }
786 787
787 return omap_mux_init(OMAP2430_CONTROL_PADCONF_MUX_PBASE, 788 return omap_mux_init("core", OMAP_MUX_REG_8BIT | OMAP_MUX_GPIO_IN_MODE3,
789 OMAP2430_CONTROL_PADCONF_MUX_PBASE,
788 OMAP2430_CONTROL_PADCONF_MUX_SIZE, 790 OMAP2430_CONTROL_PADCONF_MUX_SIZE,
789 omap2430_muxmodes, NULL, board_subset, 791 omap2430_muxmodes, NULL, board_subset,
790 package_balls); 792 package_balls);
791} 793}
diff --git a/arch/arm/mach-omap2/mux34xx.c b/arch/arm/mach-omap2/mux34xx.c
index 574e54ea3ab7..440c98e9a510 100644
--- a/arch/arm/mach-omap2/mux34xx.c
+++ b/arch/arm/mach-omap2/mux34xx.c
@@ -2049,12 +2049,13 @@ int __init omap3_mux_init(struct omap_board_mux *board_subset, int flags)
2049 package_balls = omap36xx_cbp_ball; 2049 package_balls = omap36xx_cbp_ball;
2050 break; 2050 break;
2051 default: 2051 default:
2052 printk(KERN_ERR "mux: Unknown omap package, mux disabled\n"); 2052 pr_err("%s Unknown omap package, mux disabled\n", __func__);
2053 return -EINVAL; 2053 return -EINVAL;
2054 } 2054 }
2055 2055
2056 return omap_mux_init(OMAP3_CONTROL_PADCONF_MUX_PBASE, 2056 return omap_mux_init("core", 0,
2057 OMAP3_CONTROL_PADCONF_MUX_PBASE,
2057 OMAP3_CONTROL_PADCONF_MUX_SIZE, 2058 OMAP3_CONTROL_PADCONF_MUX_SIZE,
2058 omap3_muxmodes, package_subset, board_subset, 2059 omap3_muxmodes, package_subset, board_subset,
2059 package_balls); 2060 package_balls);
2060} 2061}
diff --git a/arch/arm/mach-omap2/mux44xx.c b/arch/arm/mach-omap2/mux44xx.c
new file mode 100644
index 000000000000..980f11d45c79
--- /dev/null
+++ b/arch/arm/mach-omap2/mux44xx.c
@@ -0,0 +1,1625 @@
1/*
2 * OMAP44xx ES1.0 pin mux definition
3 *
4 * Copyright (C) 2010 Texas Instruments, Inc.
5 *
6 * Benoit Cousson (b-cousson@ti.com)
7 *
8 * - Based on mux34xx.c done by Tony Lindgren <tony@atomide.com>
9 *
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
20#include <linux/module.h>
21#include <linux/init.h>
22
23#include "mux.h"
24
25#ifdef CONFIG_OMAP_MUX
26
27#define _OMAP4_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \
28{ \
29 .reg_offset = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET), \
30 .gpio = (g), \
31 .muxnames = { m0, m1, m2, m3, m4, m5, m6, m7 }, \
32}
33
34#else
35
36#define _OMAP4_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \
37{ \
38 .reg_offset = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET), \
39 .gpio = (g), \
40}
41
42#endif
43
44#define _OMAP4_BALLENTRY(M0, bb, bt) \
45{ \
46 .reg_offset = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET), \
47 .balls = { bb, bt }, \
48}
49
50/*
51 * Superset of all mux modes for omap4 ES1.0
52 */
53static struct omap_mux __initdata omap4_core_muxmodes[] = {
54 _OMAP4_MUXENTRY(GPMC_AD0, 0, "gpmc_ad0", "sdmmc2_dat0", NULL, NULL,
55 NULL, NULL, NULL, NULL),
56 _OMAP4_MUXENTRY(GPMC_AD1, 0, "gpmc_ad1", "sdmmc2_dat1", NULL, NULL,
57 NULL, NULL, NULL, NULL),
58 _OMAP4_MUXENTRY(GPMC_AD2, 0, "gpmc_ad2", "sdmmc2_dat2", NULL, NULL,
59 NULL, NULL, NULL, NULL),
60 _OMAP4_MUXENTRY(GPMC_AD3, 0, "gpmc_ad3", "sdmmc2_dat3", NULL, NULL,
61 NULL, NULL, NULL, NULL),
62 _OMAP4_MUXENTRY(GPMC_AD4, 0, "gpmc_ad4", "sdmmc2_dat4",
63 "sdmmc2_dir_dat0", NULL, NULL, NULL, NULL, NULL),
64 _OMAP4_MUXENTRY(GPMC_AD5, 0, "gpmc_ad5", "sdmmc2_dat5",
65 "sdmmc2_dir_dat1", NULL, NULL, NULL, NULL, NULL),
66 _OMAP4_MUXENTRY(GPMC_AD6, 0, "gpmc_ad6", "sdmmc2_dat6",
67 "sdmmc2_dir_cmd", NULL, NULL, NULL, NULL, NULL),
68 _OMAP4_MUXENTRY(GPMC_AD7, 0, "gpmc_ad7", "sdmmc2_dat7",
69 "sdmmc2_clk_fdbk", NULL, NULL, NULL, NULL, NULL),
70 _OMAP4_MUXENTRY(GPMC_AD8, 32, "gpmc_ad8", "kpd_row0", "c2c_data15",
71 "gpio_32", NULL, NULL, NULL, NULL),
72 _OMAP4_MUXENTRY(GPMC_AD9, 33, "gpmc_ad9", "kpd_row1", "c2c_data14",
73 "gpio_33", NULL, NULL, NULL, NULL),
74 _OMAP4_MUXENTRY(GPMC_AD10, 34, "gpmc_ad10", "kpd_row2", "c2c_data13",
75 "gpio_34", NULL, NULL, NULL, NULL),
76 _OMAP4_MUXENTRY(GPMC_AD11, 35, "gpmc_ad11", "kpd_row3", "c2c_data12",
77 "gpio_35", NULL, NULL, NULL, NULL),
78 _OMAP4_MUXENTRY(GPMC_AD12, 36, "gpmc_ad12", "kpd_col0", "c2c_data11",
79 "gpio_36", NULL, NULL, NULL, NULL),
80 _OMAP4_MUXENTRY(GPMC_AD13, 37, "gpmc_ad13", "kpd_col1", "c2c_data10",
81 "gpio_37", NULL, NULL, NULL, NULL),
82 _OMAP4_MUXENTRY(GPMC_AD14, 38, "gpmc_ad14", "kpd_col2", "c2c_data9",
83 "gpio_38", NULL, NULL, NULL, NULL),
84 _OMAP4_MUXENTRY(GPMC_AD15, 39, "gpmc_ad15", "kpd_col3", "c2c_data8",
85 "gpio_39", NULL, NULL, NULL, NULL),
86 _OMAP4_MUXENTRY(GPMC_A16, 40, "gpmc_a16", "kpd_row4", "c2c_datain0",
87 "gpio_40", "venc_656_data0", NULL, NULL, NULL),
88 _OMAP4_MUXENTRY(GPMC_A17, 41, "gpmc_a17", "kpd_row5", "c2c_datain1",
89 "gpio_41", "venc_656_data1", NULL, NULL, "safe_mode"),
90 _OMAP4_MUXENTRY(GPMC_A18, 42, "gpmc_a18", "kpd_row6", "c2c_datain2",
91 "gpio_42", "venc_656_data2", NULL, NULL, "safe_mode"),
92 _OMAP4_MUXENTRY(GPMC_A19, 43, "gpmc_a19", "kpd_row7", "c2c_datain3",
93 "gpio_43", "venc_656_data3", NULL, NULL, "safe_mode"),
94 _OMAP4_MUXENTRY(GPMC_A20, 44, "gpmc_a20", "kpd_col4", "c2c_datain4",
95 "gpio_44", "venc_656_data4", NULL, NULL, "safe_mode"),
96 _OMAP4_MUXENTRY(GPMC_A21, 45, "gpmc_a21", "kpd_col5", "c2c_datain5",
97 "gpio_45", "venc_656_data5", NULL, NULL, "safe_mode"),
98 _OMAP4_MUXENTRY(GPMC_A22, 46, "gpmc_a22", "kpd_col6", "c2c_datain6",
99 "gpio_46", "venc_656_data6", NULL, NULL, "safe_mode"),
100 _OMAP4_MUXENTRY(GPMC_A23, 47, "gpmc_a23", "kpd_col7", "c2c_datain7",
101 "gpio_47", "venc_656_data7", NULL, NULL, "safe_mode"),
102 _OMAP4_MUXENTRY(GPMC_A24, 48, "gpmc_a24", NULL, "c2c_clkout0",
103 "gpio_48", NULL, NULL, NULL, "safe_mode"),
104 _OMAP4_MUXENTRY(GPMC_A25, 49, "gpmc_a25", NULL, "c2c_clkout1",
105 "gpio_49", NULL, NULL, NULL, "safe_mode"),
106 _OMAP4_MUXENTRY(GPMC_NCS0, 50, "gpmc_ncs0", NULL, NULL, "gpio_50",
107 "sys_ndmareq0", NULL, NULL, NULL),
108 _OMAP4_MUXENTRY(GPMC_NCS1, 51, "gpmc_ncs1", NULL, "c2c_dataout6",
109 "gpio_51", NULL, NULL, NULL, "safe_mode"),
110 _OMAP4_MUXENTRY(GPMC_NCS2, 52, "gpmc_ncs2", NULL, "c2c_dataout7",
111 "gpio_52", NULL, NULL, NULL, "safe_mode"),
112 _OMAP4_MUXENTRY(GPMC_NCS3, 53, "gpmc_ncs3", "gpmc_dir",
113 "c2c_dataout4", "gpio_53", NULL, NULL, NULL,
114 "safe_mode"),
115 _OMAP4_MUXENTRY(GPMC_NWP, 54, "gpmc_nwp", "dsi1_te0", NULL, "gpio_54",
116 "sys_ndmareq1", NULL, NULL, NULL),
117 _OMAP4_MUXENTRY(GPMC_CLK, 55, "gpmc_clk", NULL, NULL, "gpio_55",
118 "sys_ndmareq2", NULL, NULL, NULL),
119 _OMAP4_MUXENTRY(GPMC_NADV_ALE, 56, "gpmc_nadv_ale", "dsi1_te1", NULL,
120 "gpio_56", "sys_ndmareq3", NULL, NULL, NULL),
121 _OMAP4_MUXENTRY(GPMC_NOE, 0, "gpmc_noe", "sdmmc2_clk", NULL, NULL,
122 NULL, NULL, NULL, NULL),
123 _OMAP4_MUXENTRY(GPMC_NWE, 0, "gpmc_nwe", "sdmmc2_cmd", NULL, NULL,
124 NULL, NULL, NULL, NULL),
125 _OMAP4_MUXENTRY(GPMC_NBE0_CLE, 59, "gpmc_nbe0_cle", "dsi2_te0", NULL,
126 "gpio_59", NULL, NULL, NULL, NULL),
127 _OMAP4_MUXENTRY(GPMC_NBE1, 60, "gpmc_nbe1", NULL, "c2c_dataout5",
128 "gpio_60", NULL, NULL, NULL, "safe_mode"),
129 _OMAP4_MUXENTRY(GPMC_WAIT0, 61, "gpmc_wait0", "dsi2_te1", NULL,
130 "gpio_61", NULL, NULL, NULL, NULL),
131 _OMAP4_MUXENTRY(GPMC_WAIT1, 62, "gpmc_wait1", NULL, "c2c_dataout2",
132 "gpio_62", NULL, NULL, NULL, "safe_mode"),
133 _OMAP4_MUXENTRY(C2C_DATA11, 100, "c2c_data11", "usbc1_icusb_txen",
134 "c2c_dataout3", "gpio_100", "sys_ndmareq0", NULL,
135 NULL, "safe_mode"),
136 _OMAP4_MUXENTRY(C2C_DATA12, 101, "c2c_data12", "dsi1_te0",
137 "c2c_clkin0", "gpio_101", "sys_ndmareq1", NULL, NULL,
138 "safe_mode"),
139 _OMAP4_MUXENTRY(C2C_DATA13, 102, "c2c_data13", "dsi1_te1",
140 "c2c_clkin1", "gpio_102", "sys_ndmareq2", NULL, NULL,
141 "safe_mode"),
142 _OMAP4_MUXENTRY(C2C_DATA14, 103, "c2c_data14", "dsi2_te0",
143 "c2c_dataout0", "gpio_103", "sys_ndmareq3", NULL,
144 NULL, "safe_mode"),
145 _OMAP4_MUXENTRY(C2C_DATA15, 104, "c2c_data15", "dsi2_te1",
146 "c2c_dataout1", "gpio_104", NULL, NULL, NULL,
147 "safe_mode"),
148 _OMAP4_MUXENTRY(HDMI_HPD, 63, "hdmi_hpd", NULL, NULL, "gpio_63", NULL,
149 NULL, NULL, "safe_mode"),
150 _OMAP4_MUXENTRY(HDMI_CEC, 64, "hdmi_cec", NULL, NULL, "gpio_64", NULL,
151 NULL, NULL, "safe_mode"),
152 _OMAP4_MUXENTRY(HDMI_DDC_SCL, 65, "hdmi_ddc_scl", NULL, NULL,
153 "gpio_65", NULL, NULL, NULL, "safe_mode"),
154 _OMAP4_MUXENTRY(HDMI_DDC_SDA, 66, "hdmi_ddc_sda", NULL, NULL,
155 "gpio_66", NULL, NULL, NULL, "safe_mode"),
156 _OMAP4_MUXENTRY(CSI21_DX0, 0, "csi21_dx0", NULL, NULL, "gpi_67", NULL,
157 NULL, NULL, "safe_mode"),
158 _OMAP4_MUXENTRY(CSI21_DY0, 0, "csi21_dy0", NULL, NULL, "gpi_68", NULL,
159 NULL, NULL, "safe_mode"),
160 _OMAP4_MUXENTRY(CSI21_DX1, 0, "csi21_dx1", NULL, NULL, "gpi_69", NULL,
161 NULL, NULL, "safe_mode"),
162 _OMAP4_MUXENTRY(CSI21_DY1, 0, "csi21_dy1", NULL, NULL, "gpi_70", NULL,
163 NULL, NULL, "safe_mode"),
164 _OMAP4_MUXENTRY(CSI21_DX2, 0, "csi21_dx2", NULL, NULL, "gpi_71", NULL,
165 NULL, NULL, "safe_mode"),
166 _OMAP4_MUXENTRY(CSI21_DY2, 0, "csi21_dy2", NULL, NULL, "gpi_72", NULL,
167 NULL, NULL, "safe_mode"),
168 _OMAP4_MUXENTRY(CSI21_DX3, 0, "csi21_dx3", NULL, NULL, "gpi_73", NULL,
169 NULL, NULL, "safe_mode"),
170 _OMAP4_MUXENTRY(CSI21_DY3, 0, "csi21_dy3", NULL, NULL, "gpi_74", NULL,
171 NULL, NULL, "safe_mode"),
172 _OMAP4_MUXENTRY(CSI21_DX4, 0, "csi21_dx4", NULL, NULL, "gpi_75", NULL,
173 NULL, NULL, "safe_mode"),
174 _OMAP4_MUXENTRY(CSI21_DY4, 0, "csi21_dy4", NULL, NULL, "gpi_76", NULL,
175 NULL, NULL, "safe_mode"),
176 _OMAP4_MUXENTRY(CSI22_DX0, 0, "csi22_dx0", NULL, NULL, "gpi_77", NULL,
177 NULL, NULL, "safe_mode"),
178 _OMAP4_MUXENTRY(CSI22_DY0, 0, "csi22_dy0", NULL, NULL, "gpi_78", NULL,
179 NULL, NULL, "safe_mode"),
180 _OMAP4_MUXENTRY(CSI22_DX1, 0, "csi22_dx1", NULL, NULL, "gpi_79", NULL,
181 NULL, NULL, "safe_mode"),
182 _OMAP4_MUXENTRY(CSI22_DY1, 0, "csi22_dy1", NULL, NULL, "gpi_80", NULL,
183 NULL, NULL, "safe_mode"),
184 _OMAP4_MUXENTRY(CAM_SHUTTER, 81, "cam_shutter", NULL, NULL, "gpio_81",
185 NULL, NULL, NULL, "safe_mode"),
186 _OMAP4_MUXENTRY(CAM_STROBE, 82, "cam_strobe", NULL, NULL, "gpio_82",
187 NULL, NULL, NULL, "safe_mode"),
188 _OMAP4_MUXENTRY(CAM_GLOBALRESET, 83, "cam_globalreset", NULL, NULL,
189 "gpio_83", NULL, NULL, NULL, "safe_mode"),
190 _OMAP4_MUXENTRY(USBB1_ULPITLL_CLK, 84, "usbb1_ulpitll_clk",
191 "hsi1_cawake", NULL, "gpio_84", "usbb1_ulpiphy_clk",
192 NULL, "hw_dbg20", "safe_mode"),
193 _OMAP4_MUXENTRY(USBB1_ULPITLL_STP, 85, "usbb1_ulpitll_stp",
194 "hsi1_cadata", "mcbsp4_clkr", "gpio_85",
195 "usbb1_ulpiphy_stp", "usbb1_mm_rxdp", "hw_dbg21",
196 "safe_mode"),
197 _OMAP4_MUXENTRY(USBB1_ULPITLL_DIR, 86, "usbb1_ulpitll_dir",
198 "hsi1_caflag", "mcbsp4_fsr", "gpio_86",
199 "usbb1_ulpiphy_dir", NULL, "hw_dbg22", "safe_mode"),
200 _OMAP4_MUXENTRY(USBB1_ULPITLL_NXT, 87, "usbb1_ulpitll_nxt",
201 "hsi1_acready", "mcbsp4_fsx", "gpio_87",
202 "usbb1_ulpiphy_nxt", "usbb1_mm_rxdm", "hw_dbg23",
203 "safe_mode"),
204 _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT0, 88, "usbb1_ulpitll_dat0",
205 "hsi1_acwake", "mcbsp4_clkx", "gpio_88",
206 "usbb1_ulpiphy_dat0", "usbb1_mm_rxrcv", "hw_dbg24",
207 "safe_mode"),
208 _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT1, 89, "usbb1_ulpitll_dat1",
209 "hsi1_acdata", "mcbsp4_dx", "gpio_89",
210 "usbb1_ulpiphy_dat1", "usbb1_mm_txse0", "hw_dbg25",
211 "safe_mode"),
212 _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT2, 90, "usbb1_ulpitll_dat2",
213 "hsi1_acflag", "mcbsp4_dr", "gpio_90",
214 "usbb1_ulpiphy_dat2", "usbb1_mm_txdat", "hw_dbg26",
215 "safe_mode"),
216 _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT3, 91, "usbb1_ulpitll_dat3",
217 "hsi1_caready", NULL, "gpio_91", "usbb1_ulpiphy_dat3",
218 "usbb1_mm_txen", "hw_dbg27", "safe_mode"),
219 _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT4, 92, "usbb1_ulpitll_dat4",
220 "dmtimer8_pwm_evt", "abe_mcbsp3_dr", "gpio_92",
221 "usbb1_ulpiphy_dat4", NULL, "hw_dbg28", "safe_mode"),
222 _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT5, 93, "usbb1_ulpitll_dat5",
223 "dmtimer9_pwm_evt", "abe_mcbsp3_dx", "gpio_93",
224 "usbb1_ulpiphy_dat5", NULL, "hw_dbg29", "safe_mode"),
225 _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT6, 94, "usbb1_ulpitll_dat6",
226 "dmtimer10_pwm_evt", "abe_mcbsp3_clkx", "gpio_94",
227 "usbb1_ulpiphy_dat6", "abe_dmic_din3", "hw_dbg30",
228 "safe_mode"),
229 _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT7, 95, "usbb1_ulpitll_dat7",
230 "dmtimer11_pwm_evt", "abe_mcbsp3_fsx", "gpio_95",
231 "usbb1_ulpiphy_dat7", "abe_dmic_clk3", "hw_dbg31",
232 "safe_mode"),
233 _OMAP4_MUXENTRY(USBB1_HSIC_DATA, 96, "usbb1_hsic_data", NULL, NULL,
234 "gpio_96", NULL, NULL, NULL, "safe_mode"),
235 _OMAP4_MUXENTRY(USBB1_HSIC_STROBE, 97, "usbb1_hsic_strobe", NULL,
236 NULL, "gpio_97", NULL, NULL, NULL, "safe_mode"),
237 _OMAP4_MUXENTRY(USBC1_ICUSB_DP, 98, "usbc1_icusb_dp", NULL, NULL,
238 "gpio_98", NULL, NULL, NULL, "safe_mode"),
239 _OMAP4_MUXENTRY(USBC1_ICUSB_DM, 99, "usbc1_icusb_dm", NULL, NULL,
240 "gpio_99", NULL, NULL, NULL, "safe_mode"),
241 _OMAP4_MUXENTRY(SDMMC1_CLK, 100, "sdmmc1_clk", NULL, "dpm_emu19",
242 "gpio_100", NULL, NULL, NULL, "safe_mode"),
243 _OMAP4_MUXENTRY(SDMMC1_CMD, 101, "sdmmc1_cmd", NULL, "uart1_rx",
244 "gpio_101", NULL, NULL, NULL, "safe_mode"),
245 _OMAP4_MUXENTRY(SDMMC1_DAT0, 102, "sdmmc1_dat0", NULL, "dpm_emu18",
246 "gpio_102", NULL, NULL, NULL, "safe_mode"),
247 _OMAP4_MUXENTRY(SDMMC1_DAT1, 103, "sdmmc1_dat1", NULL, "dpm_emu17",
248 "gpio_103", NULL, NULL, NULL, "safe_mode"),
249 _OMAP4_MUXENTRY(SDMMC1_DAT2, 104, "sdmmc1_dat2", NULL, "dpm_emu16",
250 "gpio_104", "jtag_tms_tmsc", NULL, NULL, "safe_mode"),
251 _OMAP4_MUXENTRY(SDMMC1_DAT3, 105, "sdmmc1_dat3", NULL, "dpm_emu15",
252 "gpio_105", "jtag_tck", NULL, NULL, "safe_mode"),
253 _OMAP4_MUXENTRY(SDMMC1_DAT4, 106, "sdmmc1_dat4", NULL, NULL,
254 "gpio_106", NULL, NULL, NULL, "safe_mode"),
255 _OMAP4_MUXENTRY(SDMMC1_DAT5, 107, "sdmmc1_dat5", NULL, NULL,
256 "gpio_107", NULL, NULL, NULL, "safe_mode"),
257 _OMAP4_MUXENTRY(SDMMC1_DAT6, 108, "sdmmc1_dat6", NULL, NULL,
258 "gpio_108", NULL, NULL, NULL, "safe_mode"),
259 _OMAP4_MUXENTRY(SDMMC1_DAT7, 109, "sdmmc1_dat7", NULL, NULL,
260 "gpio_109", NULL, NULL, NULL, "safe_mode"),
261 _OMAP4_MUXENTRY(ABE_MCBSP2_CLKX, 110, "abe_mcbsp2_clkx", "mcspi2_clk",
262 "abe_mcasp_ahclkx", "gpio_110", "usbb2_mm_rxdm",
263 NULL, NULL, "safe_mode"),
264 _OMAP4_MUXENTRY(ABE_MCBSP2_DR, 111, "abe_mcbsp2_dr", "mcspi2_somi",
265 "abe_mcasp_axr", "gpio_111", "usbb2_mm_rxdp", NULL,
266 NULL, "safe_mode"),
267 _OMAP4_MUXENTRY(ABE_MCBSP2_DX, 112, "abe_mcbsp2_dx", "mcspi2_simo",
268 "abe_mcasp_amute", "gpio_112", "usbb2_mm_rxrcv", NULL,
269 NULL, "safe_mode"),
270 _OMAP4_MUXENTRY(ABE_MCBSP2_FSX, 113, "abe_mcbsp2_fsx", "mcspi2_cs0",
271 "abe_mcasp_afsx", "gpio_113", "usbb2_mm_txen", NULL,
272 NULL, "safe_mode"),
273 _OMAP4_MUXENTRY(ABE_MCBSP1_CLKX, 114, "abe_mcbsp1_clkx",
274 "abe_slimbus1_clock", NULL, "gpio_114", NULL, NULL,
275 NULL, "safe_mode"),
276 _OMAP4_MUXENTRY(ABE_MCBSP1_DR, 115, "abe_mcbsp1_dr",
277 "abe_slimbus1_data", NULL, "gpio_115", NULL, NULL,
278 NULL, "safe_mode"),
279 _OMAP4_MUXENTRY(ABE_MCBSP1_DX, 116, "abe_mcbsp1_dx", "sdmmc3_dat2",
280 "abe_mcasp_aclkx", "gpio_116", NULL, NULL, NULL,
281 "safe_mode"),
282 _OMAP4_MUXENTRY(ABE_MCBSP1_FSX, 117, "abe_mcbsp1_fsx", "sdmmc3_dat3",
283 "abe_mcasp_amutein", "gpio_117", NULL, NULL, NULL,
284 "safe_mode"),
285 _OMAP4_MUXENTRY(ABE_PDM_UL_DATA, 0, "abe_pdm_ul_data",
286 "abe_mcbsp3_dr", NULL, NULL, NULL, NULL, NULL,
287 "safe_mode"),
288 _OMAP4_MUXENTRY(ABE_PDM_DL_DATA, 0, "abe_pdm_dl_data",
289 "abe_mcbsp3_dx", NULL, NULL, NULL, NULL, NULL,
290 "safe_mode"),
291 _OMAP4_MUXENTRY(ABE_PDM_FRAME, 0, "abe_pdm_frame", "abe_mcbsp3_clkx",
292 NULL, NULL, NULL, NULL, NULL, "safe_mode"),
293 _OMAP4_MUXENTRY(ABE_PDM_LB_CLK, 0, "abe_pdm_lb_clk", "abe_mcbsp3_fsx",
294 NULL, NULL, NULL, NULL, NULL, "safe_mode"),
295 _OMAP4_MUXENTRY(ABE_CLKS, 118, "abe_clks", NULL, NULL, "gpio_118",
296 NULL, NULL, NULL, "safe_mode"),
297 _OMAP4_MUXENTRY(ABE_DMIC_CLK1, 119, "abe_dmic_clk1", NULL, NULL,
298 "gpio_119", "usbb2_mm_txse0", NULL, NULL,
299 "safe_mode"),
300 _OMAP4_MUXENTRY(ABE_DMIC_DIN1, 120, "abe_dmic_din1", NULL, NULL,
301 "gpio_120", "usbb2_mm_txdat", NULL, NULL,
302 "safe_mode"),
303 _OMAP4_MUXENTRY(ABE_DMIC_DIN2, 121, "abe_dmic_din2", "slimbus2_clock",
304 NULL, "gpio_121", NULL, NULL, NULL, "safe_mode"),
305 _OMAP4_MUXENTRY(ABE_DMIC_DIN3, 122, "abe_dmic_din3", "slimbus2_data",
306 "abe_dmic_clk2", "gpio_122", NULL, NULL, NULL,
307 "safe_mode"),
308 _OMAP4_MUXENTRY(UART2_CTS, 123, "uart2_cts", "sdmmc3_clk", NULL,
309 "gpio_123", NULL, NULL, NULL, "safe_mode"),
310 _OMAP4_MUXENTRY(UART2_RTS, 124, "uart2_rts", "sdmmc3_cmd", NULL,
311 "gpio_124", NULL, NULL, NULL, "safe_mode"),
312 _OMAP4_MUXENTRY(UART2_RX, 125, "uart2_rx", "sdmmc3_dat0", NULL,
313 "gpio_125", NULL, NULL, NULL, "safe_mode"),
314 _OMAP4_MUXENTRY(UART2_TX, 126, "uart2_tx", "sdmmc3_dat1", NULL,
315 "gpio_126", NULL, NULL, NULL, "safe_mode"),
316 _OMAP4_MUXENTRY(HDQ_SIO, 127, "hdq_sio", "i2c3_sccb", "i2c2_sccb",
317 "gpio_127", NULL, NULL, NULL, "safe_mode"),
318 _OMAP4_MUXENTRY(I2C1_SCL, 0, "i2c1_scl", NULL, NULL, NULL, NULL, NULL,
319 NULL, NULL),
320 _OMAP4_MUXENTRY(I2C1_SDA, 0, "i2c1_sda", NULL, NULL, NULL, NULL, NULL,
321 NULL, NULL),
322 _OMAP4_MUXENTRY(I2C2_SCL, 128, "i2c2_scl", "uart1_rx", NULL,
323 "gpio_128", NULL, NULL, NULL, "safe_mode"),
324 _OMAP4_MUXENTRY(I2C2_SDA, 129, "i2c2_sda", "uart1_tx", NULL,
325 "gpio_129", NULL, NULL, NULL, "safe_mode"),
326 _OMAP4_MUXENTRY(I2C3_SCL, 130, "i2c3_scl", NULL, NULL, "gpio_130",
327 NULL, NULL, NULL, "safe_mode"),
328 _OMAP4_MUXENTRY(I2C3_SDA, 131, "i2c3_sda", NULL, NULL, "gpio_131",
329 NULL, NULL, NULL, "safe_mode"),
330 _OMAP4_MUXENTRY(I2C4_SCL, 132, "i2c4_scl", NULL, NULL, "gpio_132",
331 NULL, NULL, NULL, "safe_mode"),
332 _OMAP4_MUXENTRY(I2C4_SDA, 133, "i2c4_sda", NULL, NULL, "gpio_133",
333 NULL, NULL, NULL, "safe_mode"),
334 _OMAP4_MUXENTRY(MCSPI1_CLK, 134, "mcspi1_clk", NULL, NULL, "gpio_134",
335 NULL, NULL, NULL, "safe_mode"),
336 _OMAP4_MUXENTRY(MCSPI1_SOMI, 135, "mcspi1_somi", NULL, NULL,
337 "gpio_135", NULL, NULL, NULL, "safe_mode"),
338 _OMAP4_MUXENTRY(MCSPI1_SIMO, 136, "mcspi1_simo", NULL, NULL,
339 "gpio_136", NULL, NULL, NULL, "safe_mode"),
340 _OMAP4_MUXENTRY(MCSPI1_CS0, 137, "mcspi1_cs0", NULL, NULL, "gpio_137",
341 NULL, NULL, NULL, "safe_mode"),
342 _OMAP4_MUXENTRY(MCSPI1_CS1, 138, "mcspi1_cs1", "uart1_rx", NULL,
343 "gpio_138", NULL, NULL, NULL, "safe_mode"),
344 _OMAP4_MUXENTRY(MCSPI1_CS2, 139, "mcspi1_cs2", "uart1_cts",
345 "slimbus2_clock", "gpio_139", NULL, NULL, NULL,
346 "safe_mode"),
347 _OMAP4_MUXENTRY(MCSPI1_CS3, 140, "mcspi1_cs3", "uart1_rts",
348 "slimbus2_data", "gpio_140", NULL, NULL, NULL,
349 "safe_mode"),
350 _OMAP4_MUXENTRY(UART3_CTS_RCTX, 141, "uart3_cts_rctx", "uart1_tx",
351 NULL, "gpio_141", NULL, NULL, NULL, "safe_mode"),
352 _OMAP4_MUXENTRY(UART3_RTS_SD, 142, "uart3_rts_sd", NULL, NULL,
353 "gpio_142", NULL, NULL, NULL, "safe_mode"),
354 _OMAP4_MUXENTRY(UART3_RX_IRRX, 143, "uart3_rx_irrx",
355 "dmtimer8_pwm_evt", NULL, "gpio_143", NULL, NULL,
356 NULL, "safe_mode"),
357 _OMAP4_MUXENTRY(UART3_TX_IRTX, 144, "uart3_tx_irtx",
358 "dmtimer9_pwm_evt", NULL, "gpio_144", NULL, NULL,
359 NULL, "safe_mode"),
360 _OMAP4_MUXENTRY(SDMMC5_CLK, 145, "sdmmc5_clk", "mcspi2_clk",
361 "usbc1_icusb_dp", "gpio_145", NULL, NULL, NULL,
362 "safe_mode"),
363 _OMAP4_MUXENTRY(SDMMC5_CMD, 146, "sdmmc5_cmd", "mcspi2_simo",
364 "usbc1_icusb_dm", "gpio_146", NULL, NULL, NULL,
365 "safe_mode"),
366 _OMAP4_MUXENTRY(SDMMC5_DAT0, 147, "sdmmc5_dat0", "mcspi2_somi",
367 "usbc1_icusb_rcv", "gpio_147", NULL, NULL, NULL,
368 "safe_mode"),
369 _OMAP4_MUXENTRY(SDMMC5_DAT1, 148, "sdmmc5_dat1", NULL,
370 "usbc1_icusb_txen", "gpio_148", NULL, NULL, NULL,
371 "safe_mode"),
372 _OMAP4_MUXENTRY(SDMMC5_DAT2, 149, "sdmmc5_dat2", "mcspi2_cs1", NULL,
373 "gpio_149", NULL, NULL, NULL, "safe_mode"),
374 _OMAP4_MUXENTRY(SDMMC5_DAT3, 150, "sdmmc5_dat3", "mcspi2_cs0", NULL,
375 "gpio_150", NULL, NULL, NULL, "safe_mode"),
376 _OMAP4_MUXENTRY(MCSPI4_CLK, 151, "mcspi4_clk", "sdmmc4_clk", NULL,
377 "gpio_151", NULL, NULL, NULL, "safe_mode"),
378 _OMAP4_MUXENTRY(MCSPI4_SIMO, 152, "mcspi4_simo", "sdmmc4_cmd", NULL,
379 "gpio_152", NULL, NULL, NULL, "safe_mode"),
380 _OMAP4_MUXENTRY(MCSPI4_SOMI, 153, "mcspi4_somi", "sdmmc4_dat0", NULL,
381 "gpio_153", NULL, NULL, NULL, "safe_mode"),
382 _OMAP4_MUXENTRY(MCSPI4_CS0, 154, "mcspi4_cs0", "sdmmc4_dat3", NULL,
383 "gpio_154", NULL, NULL, NULL, "safe_mode"),
384 _OMAP4_MUXENTRY(UART4_RX, 155, "uart4_rx", "sdmmc4_dat2", NULL,
385 "gpio_155", NULL, NULL, NULL, "safe_mode"),
386 _OMAP4_MUXENTRY(UART4_TX, 156, "uart4_tx", "sdmmc4_dat1", NULL,
387 "gpio_156", NULL, NULL, NULL, "safe_mode"),
388 _OMAP4_MUXENTRY(USBB2_ULPITLL_CLK, 157, "usbb2_ulpitll_clk",
389 "usbb2_ulpiphy_clk", "sdmmc4_cmd", "gpio_157",
390 "hsi2_cawake", NULL, NULL, "safe_mode"),
391 _OMAP4_MUXENTRY(USBB2_ULPITLL_STP, 158, "usbb2_ulpitll_stp",
392 "usbb2_ulpiphy_stp", "sdmmc4_clk", "gpio_158",
393 "hsi2_cadata", "dispc2_data23", NULL, "reserved"),
394 _OMAP4_MUXENTRY(USBB2_ULPITLL_DIR, 159, "usbb2_ulpitll_dir",
395 "usbb2_ulpiphy_dir", "sdmmc4_dat0", "gpio_159",
396 "hsi2_caflag", "dispc2_data22", NULL, "reserved"),
397 _OMAP4_MUXENTRY(USBB2_ULPITLL_NXT, 160, "usbb2_ulpitll_nxt",
398 "usbb2_ulpiphy_nxt", "sdmmc4_dat1", "gpio_160",
399 "hsi2_acready", "dispc2_data21", NULL, "reserved"),
400 _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT0, 161, "usbb2_ulpitll_dat0",
401 "usbb2_ulpiphy_dat0", "sdmmc4_dat2", "gpio_161",
402 "hsi2_acwake", "dispc2_data20", NULL, "reserved"),
403 _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT1, 162, "usbb2_ulpitll_dat1",
404 "usbb2_ulpiphy_dat1", "sdmmc4_dat3", "gpio_162",
405 "hsi2_acdata", "dispc2_data19", NULL, "reserved"),
406 _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT2, 163, "usbb2_ulpitll_dat2",
407 "usbb2_ulpiphy_dat2", "sdmmc3_dat2", "gpio_163",
408 "hsi2_acflag", "dispc2_data18", NULL, "reserved"),
409 _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT3, 164, "usbb2_ulpitll_dat3",
410 "usbb2_ulpiphy_dat3", "sdmmc3_dat1", "gpio_164",
411 "hsi2_caready", "dispc2_data15", NULL, "reserved"),
412 _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT4, 165, "usbb2_ulpitll_dat4",
413 "usbb2_ulpiphy_dat4", "sdmmc3_dat0", "gpio_165",
414 "mcspi3_somi", "dispc2_data14", NULL, "reserved"),
415 _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT5, 166, "usbb2_ulpitll_dat5",
416 "usbb2_ulpiphy_dat5", "sdmmc3_dat3", "gpio_166",
417 "mcspi3_cs0", "dispc2_data13", NULL, "reserved"),
418 _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT6, 167, "usbb2_ulpitll_dat6",
419 "usbb2_ulpiphy_dat6", "sdmmc3_cmd", "gpio_167",
420 "mcspi3_simo", "dispc2_data12", NULL, "reserved"),
421 _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT7, 168, "usbb2_ulpitll_dat7",
422 "usbb2_ulpiphy_dat7", "sdmmc3_clk", "gpio_168",
423 "mcspi3_clk", "dispc2_data11", NULL, "reserved"),
424 _OMAP4_MUXENTRY(USBB2_HSIC_DATA, 169, "usbb2_hsic_data", NULL, NULL,
425 "gpio_169", NULL, NULL, NULL, "safe_mode"),
426 _OMAP4_MUXENTRY(USBB2_HSIC_STROBE, 170, "usbb2_hsic_strobe", NULL,
427 NULL, "gpio_170", NULL, NULL, NULL, "safe_mode"),
428 _OMAP4_MUXENTRY(UNIPRO_TX0, 171, "unipro_tx0", "kpd_col0", NULL,
429 "gpio_171", NULL, NULL, NULL, "safe_mode"),
430 _OMAP4_MUXENTRY(UNIPRO_TY0, 172, "unipro_ty0", "kpd_col1", NULL,
431 "gpio_172", NULL, NULL, NULL, "safe_mode"),
432 _OMAP4_MUXENTRY(UNIPRO_TX1, 173, "unipro_tx1", "kpd_col2", NULL,
433 "gpio_173", NULL, NULL, NULL, "safe_mode"),
434 _OMAP4_MUXENTRY(UNIPRO_TY1, 174, "unipro_ty1", "kpd_col3", NULL,
435 "gpio_174", NULL, NULL, NULL, "safe_mode"),
436 _OMAP4_MUXENTRY(UNIPRO_TX2, 0, "unipro_tx2", "kpd_col4", NULL,
437 "gpio_0", NULL, NULL, NULL, "safe_mode"),
438 _OMAP4_MUXENTRY(UNIPRO_TY2, 1, "unipro_ty2", "kpd_col5", NULL,
439 "gpio_1", NULL, NULL, NULL, "safe_mode"),
440 _OMAP4_MUXENTRY(UNIPRO_RX0, 0, "unipro_rx0", "kpd_row0", NULL,
441 "gpi_175", NULL, NULL, NULL, "safe_mode"),
442 _OMAP4_MUXENTRY(UNIPRO_RY0, 0, "unipro_ry0", "kpd_row1", NULL,
443 "gpi_176", NULL, NULL, NULL, "safe_mode"),
444 _OMAP4_MUXENTRY(UNIPRO_RX1, 0, "unipro_rx1", "kpd_row2", NULL,
445 "gpi_177", NULL, NULL, NULL, "safe_mode"),
446 _OMAP4_MUXENTRY(UNIPRO_RY1, 0, "unipro_ry1", "kpd_row3", NULL,
447 "gpi_178", NULL, NULL, NULL, "safe_mode"),
448 _OMAP4_MUXENTRY(UNIPRO_RX2, 0, "unipro_rx2", "kpd_row4", NULL,
449 "gpi_2", NULL, NULL, NULL, "safe_mode"),
450 _OMAP4_MUXENTRY(UNIPRO_RY2, 0, "unipro_ry2", "kpd_row5", NULL,
451 "gpi_3", NULL, NULL, NULL, "safe_mode"),
452 _OMAP4_MUXENTRY(USBA0_OTG_CE, 0, "usba0_otg_ce", NULL, NULL, NULL,
453 NULL, NULL, NULL, NULL),
454 _OMAP4_MUXENTRY(USBA0_OTG_DP, 179, "usba0_otg_dp", "uart3_rx_irrx",
455 "uart2_rx", "gpio_179", NULL, NULL, NULL,
456 "safe_mode"),
457 _OMAP4_MUXENTRY(USBA0_OTG_DM, 180, "usba0_otg_dm", "uart3_tx_irtx",
458 "uart2_tx", "gpio_180", NULL, NULL, NULL,
459 "safe_mode"),
460 _OMAP4_MUXENTRY(FREF_CLK1_OUT, 181, "fref_clk1_out", NULL, NULL,
461 "gpio_181", NULL, NULL, NULL, "safe_mode"),
462 _OMAP4_MUXENTRY(FREF_CLK2_OUT, 182, "fref_clk2_out", NULL, NULL,
463 "gpio_182", NULL, NULL, NULL, "safe_mode"),
464 _OMAP4_MUXENTRY(SYS_NIRQ1, 0, "sys_nirq1", NULL, NULL, NULL, NULL,
465 NULL, NULL, "safe_mode"),
466 _OMAP4_MUXENTRY(SYS_NIRQ2, 183, "sys_nirq2", NULL, NULL, "gpio_183",
467 NULL, NULL, NULL, "safe_mode"),
468 _OMAP4_MUXENTRY(SYS_BOOT0, 184, "sys_boot0", NULL, NULL, "gpio_184",
469 NULL, NULL, NULL, "safe_mode"),
470 _OMAP4_MUXENTRY(SYS_BOOT1, 185, "sys_boot1", NULL, NULL, "gpio_185",
471 NULL, NULL, NULL, "safe_mode"),
472 _OMAP4_MUXENTRY(SYS_BOOT2, 186, "sys_boot2", NULL, NULL, "gpio_186",
473 NULL, NULL, NULL, "safe_mode"),
474 _OMAP4_MUXENTRY(SYS_BOOT3, 187, "sys_boot3", NULL, NULL, "gpio_187",
475 NULL, NULL, NULL, "safe_mode"),
476 _OMAP4_MUXENTRY(SYS_BOOT4, 188, "sys_boot4", NULL, NULL, "gpio_188",
477 NULL, NULL, NULL, "safe_mode"),
478 _OMAP4_MUXENTRY(SYS_BOOT5, 189, "sys_boot5", NULL, NULL, "gpio_189",
479 NULL, NULL, NULL, "safe_mode"),
480 _OMAP4_MUXENTRY(DPM_EMU0, 11, "dpm_emu0", NULL, NULL, "gpio_11", NULL,
481 NULL, "hw_dbg0", "safe_mode"),
482 _OMAP4_MUXENTRY(DPM_EMU1, 12, "dpm_emu1", NULL, NULL, "gpio_12", NULL,
483 NULL, "hw_dbg1", "safe_mode"),
484 _OMAP4_MUXENTRY(DPM_EMU2, 13, "dpm_emu2", "usba0_ulpiphy_clk", NULL,
485 "gpio_13", NULL, "dispc2_fid", "hw_dbg2", "reserved"),
486 _OMAP4_MUXENTRY(DPM_EMU3, 14, "dpm_emu3", "usba0_ulpiphy_stp", NULL,
487 "gpio_14", NULL, "dispc2_data10", "hw_dbg3",
488 "reserved"),
489 _OMAP4_MUXENTRY(DPM_EMU4, 15, "dpm_emu4", "usba0_ulpiphy_dir", NULL,
490 "gpio_15", NULL, "dispc2_data9", "hw_dbg4",
491 "reserved"),
492 _OMAP4_MUXENTRY(DPM_EMU5, 16, "dpm_emu5", "usba0_ulpiphy_nxt", NULL,
493 "gpio_16", "rfbi_te_vsync0", "dispc2_data16",
494 "hw_dbg5", "reserved"),
495 _OMAP4_MUXENTRY(DPM_EMU6, 17, "dpm_emu6", "usba0_ulpiphy_dat0",
496 "uart3_tx_irtx", "gpio_17", "rfbi_hsync0",
497 "dispc2_data17", "hw_dbg6", "reserved"),
498 _OMAP4_MUXENTRY(DPM_EMU7, 18, "dpm_emu7", "usba0_ulpiphy_dat1",
499 "uart3_rx_irrx", "gpio_18", "rfbi_cs0",
500 "dispc2_hsync", "hw_dbg7", "reserved"),
501 _OMAP4_MUXENTRY(DPM_EMU8, 19, "dpm_emu8", "usba0_ulpiphy_dat2",
502 "uart3_rts_sd", "gpio_19", "rfbi_re", "dispc2_pclk",
503 "hw_dbg8", "reserved"),
504 _OMAP4_MUXENTRY(DPM_EMU9, 20, "dpm_emu9", "usba0_ulpiphy_dat3",
505 "uart3_cts_rctx", "gpio_20", "rfbi_we",
506 "dispc2_vsync", "hw_dbg9", "reserved"),
507 _OMAP4_MUXENTRY(DPM_EMU10, 21, "dpm_emu10", "usba0_ulpiphy_dat4",
508 NULL, "gpio_21", "rfbi_a0", "dispc2_de", "hw_dbg10",
509 "reserved"),
510 _OMAP4_MUXENTRY(DPM_EMU11, 22, "dpm_emu11", "usba0_ulpiphy_dat5",
511 NULL, "gpio_22", "rfbi_data8", "dispc2_data8",
512 "hw_dbg11", "reserved"),
513 _OMAP4_MUXENTRY(DPM_EMU12, 23, "dpm_emu12", "usba0_ulpiphy_dat6",
514 NULL, "gpio_23", "rfbi_data7", "dispc2_data7",
515 "hw_dbg12", "reserved"),
516 _OMAP4_MUXENTRY(DPM_EMU13, 24, "dpm_emu13", "usba0_ulpiphy_dat7",
517 NULL, "gpio_24", "rfbi_data6", "dispc2_data6",
518 "hw_dbg13", "reserved"),
519 _OMAP4_MUXENTRY(DPM_EMU14, 25, "dpm_emu14", "sys_drm_msecure",
520 "uart1_rx", "gpio_25", "rfbi_data5", "dispc2_data5",
521 "hw_dbg14", "reserved"),
522 _OMAP4_MUXENTRY(DPM_EMU15, 26, "dpm_emu15", "sys_secure_indicator",
523 NULL, "gpio_26", "rfbi_data4", "dispc2_data4",
524 "hw_dbg15", "reserved"),
525 _OMAP4_MUXENTRY(DPM_EMU16, 27, "dpm_emu16", "dmtimer8_pwm_evt",
526 "dsi1_te0", "gpio_27", "rfbi_data3", "dispc2_data3",
527 "hw_dbg16", "reserved"),
528 _OMAP4_MUXENTRY(DPM_EMU17, 28, "dpm_emu17", "dmtimer9_pwm_evt",
529 "dsi1_te1", "gpio_28", "rfbi_data2", "dispc2_data2",
530 "hw_dbg17", "reserved"),
531 _OMAP4_MUXENTRY(DPM_EMU18, 190, "dpm_emu18", "dmtimer10_pwm_evt",
532 "dsi2_te0", "gpio_190", "rfbi_data1", "dispc2_data1",
533 "hw_dbg18", "reserved"),
534 _OMAP4_MUXENTRY(DPM_EMU19, 191, "dpm_emu19", "dmtimer11_pwm_evt",
535 "dsi2_te1", "gpio_191", "rfbi_data0", "dispc2_data0",
536 "hw_dbg19", "reserved"),
537 { .reg_offset = OMAP_MUX_TERMINATOR },
538};
539
540/*
541 * Balls for 44XX CBL package
542 * 547-pin CBL ES1.0 S-FPGA-N547, 0.40mm Ball Pitch (Top),
543 * 0.40mm Ball Pitch (Bottom)
544 */
545#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \
546 && defined(CONFIG_OMAP_PACKAGE_CBL)
547struct omap_ball __initdata omap4_core_cbl_ball[] = {
548 _OMAP4_BALLENTRY(GPMC_AD0, "c12", NULL),
549 _OMAP4_BALLENTRY(GPMC_AD1, "d12", NULL),
550 _OMAP4_BALLENTRY(GPMC_AD2, "c13", NULL),
551 _OMAP4_BALLENTRY(GPMC_AD3, "d13", NULL),
552 _OMAP4_BALLENTRY(GPMC_AD4, "c15", NULL),
553 _OMAP4_BALLENTRY(GPMC_AD5, "d15", NULL),
554 _OMAP4_BALLENTRY(GPMC_AD6, "a16", NULL),
555 _OMAP4_BALLENTRY(GPMC_AD7, "b16", NULL),
556 _OMAP4_BALLENTRY(GPMC_AD8, "c16", NULL),
557 _OMAP4_BALLENTRY(GPMC_AD9, "d16", NULL),
558 _OMAP4_BALLENTRY(GPMC_AD10, "c17", NULL),
559 _OMAP4_BALLENTRY(GPMC_AD11, "d17", NULL),
560 _OMAP4_BALLENTRY(GPMC_AD12, "c18", NULL),
561 _OMAP4_BALLENTRY(GPMC_AD13, "d18", NULL),
562 _OMAP4_BALLENTRY(GPMC_AD14, "c19", NULL),
563 _OMAP4_BALLENTRY(GPMC_AD15, "d19", NULL),
564 _OMAP4_BALLENTRY(GPMC_A16, "b17", NULL),
565 _OMAP4_BALLENTRY(GPMC_A17, "a18", NULL),
566 _OMAP4_BALLENTRY(GPMC_A18, "b18", NULL),
567 _OMAP4_BALLENTRY(GPMC_A19, "a19", NULL),
568 _OMAP4_BALLENTRY(GPMC_A20, "b19", NULL),
569 _OMAP4_BALLENTRY(GPMC_A21, "b20", NULL),
570 _OMAP4_BALLENTRY(GPMC_A22, "a21", NULL),
571 _OMAP4_BALLENTRY(GPMC_A23, "b21", NULL),
572 _OMAP4_BALLENTRY(GPMC_A24, "c20", NULL),
573 _OMAP4_BALLENTRY(GPMC_A25, "d20", NULL),
574 _OMAP4_BALLENTRY(GPMC_NCS0, "b25", NULL),
575 _OMAP4_BALLENTRY(GPMC_NCS1, "c21", NULL),
576 _OMAP4_BALLENTRY(GPMC_NCS2, "d21", NULL),
577 _OMAP4_BALLENTRY(GPMC_NCS3, "c22", NULL),
578 _OMAP4_BALLENTRY(GPMC_NWP, "c25", NULL),
579 _OMAP4_BALLENTRY(GPMC_CLK, "b22", NULL),
580 _OMAP4_BALLENTRY(GPMC_NADV_ALE, "d25", NULL),
581 _OMAP4_BALLENTRY(GPMC_NOE, "b11", NULL),
582 _OMAP4_BALLENTRY(GPMC_NWE, "b12", NULL),
583 _OMAP4_BALLENTRY(GPMC_NBE0_CLE, "c23", NULL),
584 _OMAP4_BALLENTRY(GPMC_NBE1, "d22", NULL),
585 _OMAP4_BALLENTRY(GPMC_WAIT0, "b26", NULL),
586 _OMAP4_BALLENTRY(GPMC_WAIT1, "b23", NULL),
587 _OMAP4_BALLENTRY(C2C_DATA11, "d23", NULL),
588 _OMAP4_BALLENTRY(C2C_DATA12, "a24", NULL),
589 _OMAP4_BALLENTRY(C2C_DATA13, "b24", NULL),
590 _OMAP4_BALLENTRY(C2C_DATA14, "c24", NULL),
591 _OMAP4_BALLENTRY(C2C_DATA15, "d24", NULL),
592 _OMAP4_BALLENTRY(HDMI_HPD, "b9", NULL),
593 _OMAP4_BALLENTRY(HDMI_CEC, "b10", NULL),
594 _OMAP4_BALLENTRY(HDMI_DDC_SCL, "a8", NULL),
595 _OMAP4_BALLENTRY(HDMI_DDC_SDA, "b8", NULL),
596 _OMAP4_BALLENTRY(CSI21_DX0, "r26", NULL),
597 _OMAP4_BALLENTRY(CSI21_DY0, "r25", NULL),
598 _OMAP4_BALLENTRY(CSI21_DX1, "t26", NULL),
599 _OMAP4_BALLENTRY(CSI21_DY1, "t25", NULL),
600 _OMAP4_BALLENTRY(CSI21_DX2, "u26", NULL),
601 _OMAP4_BALLENTRY(CSI21_DY2, "u25", NULL),
602 _OMAP4_BALLENTRY(CSI21_DX3, "v26", NULL),
603 _OMAP4_BALLENTRY(CSI21_DY3, "v25", NULL),
604 _OMAP4_BALLENTRY(CSI21_DX4, "w26", NULL),
605 _OMAP4_BALLENTRY(CSI21_DY4, "w25", NULL),
606 _OMAP4_BALLENTRY(CSI22_DX0, "m26", NULL),
607 _OMAP4_BALLENTRY(CSI22_DY0, "m25", NULL),
608 _OMAP4_BALLENTRY(CSI22_DX1, "n26", NULL),
609 _OMAP4_BALLENTRY(CSI22_DY1, "n25", NULL),
610 _OMAP4_BALLENTRY(CAM_SHUTTER, "t27", NULL),
611 _OMAP4_BALLENTRY(CAM_STROBE, "u27", NULL),
612 _OMAP4_BALLENTRY(CAM_GLOBALRESET, "v27", NULL),
613 _OMAP4_BALLENTRY(USBB1_ULPITLL_CLK, "ae18", NULL),
614 _OMAP4_BALLENTRY(USBB1_ULPITLL_STP, "ag19", NULL),
615 _OMAP4_BALLENTRY(USBB1_ULPITLL_DIR, "af19", NULL),
616 _OMAP4_BALLENTRY(USBB1_ULPITLL_NXT, "ae19", NULL),
617 _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT0, "af18", NULL),
618 _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT1, "ag18", NULL),
619 _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT2, "ae17", NULL),
620 _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT3, "af17", NULL),
621 _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT4, "ah17", NULL),
622 _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT5, "ae16", NULL),
623 _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT6, "af16", NULL),
624 _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT7, "ag16", NULL),
625 _OMAP4_BALLENTRY(USBB1_HSIC_DATA, "af14", NULL),
626 _OMAP4_BALLENTRY(USBB1_HSIC_STROBE, "ae14", NULL),
627 _OMAP4_BALLENTRY(USBC1_ICUSB_DP, "h2", NULL),
628 _OMAP4_BALLENTRY(USBC1_ICUSB_DM, "h3", NULL),
629 _OMAP4_BALLENTRY(SDMMC1_CLK, "d2", NULL),
630 _OMAP4_BALLENTRY(SDMMC1_CMD, "e3", NULL),
631 _OMAP4_BALLENTRY(SDMMC1_DAT0, "e4", NULL),
632 _OMAP4_BALLENTRY(SDMMC1_DAT1, "e2", NULL),
633 _OMAP4_BALLENTRY(SDMMC1_DAT2, "e1", NULL),
634 _OMAP4_BALLENTRY(SDMMC1_DAT3, "f4", NULL),
635 _OMAP4_BALLENTRY(SDMMC1_DAT4, "f3", NULL),
636 _OMAP4_BALLENTRY(SDMMC1_DAT5, "f1", NULL),
637 _OMAP4_BALLENTRY(SDMMC1_DAT6, "g4", NULL),
638 _OMAP4_BALLENTRY(SDMMC1_DAT7, "g3", NULL),
639 _OMAP4_BALLENTRY(ABE_MCBSP2_CLKX, "ad27", NULL),
640 _OMAP4_BALLENTRY(ABE_MCBSP2_DR, "ad26", NULL),
641 _OMAP4_BALLENTRY(ABE_MCBSP2_DX, "ad25", NULL),
642 _OMAP4_BALLENTRY(ABE_MCBSP2_FSX, "ac28", NULL),
643 _OMAP4_BALLENTRY(ABE_MCBSP1_CLKX, "ac26", NULL),
644 _OMAP4_BALLENTRY(ABE_MCBSP1_DR, "ac25", NULL),
645 _OMAP4_BALLENTRY(ABE_MCBSP1_DX, "ab25", NULL),
646 _OMAP4_BALLENTRY(ABE_MCBSP1_FSX, "ac27", NULL),
647 _OMAP4_BALLENTRY(ABE_PDM_UL_DATA, "ag25", NULL),
648 _OMAP4_BALLENTRY(ABE_PDM_DL_DATA, "af25", NULL),
649 _OMAP4_BALLENTRY(ABE_PDM_FRAME, "ae25", NULL),
650 _OMAP4_BALLENTRY(ABE_PDM_LB_CLK, "af26", NULL),
651 _OMAP4_BALLENTRY(ABE_CLKS, "ah26", NULL),
652 _OMAP4_BALLENTRY(ABE_DMIC_CLK1, "ae24", NULL),
653 _OMAP4_BALLENTRY(ABE_DMIC_DIN1, "af24", NULL),
654 _OMAP4_BALLENTRY(ABE_DMIC_DIN2, "ag24", NULL),
655 _OMAP4_BALLENTRY(ABE_DMIC_DIN3, "ah24", NULL),
656 _OMAP4_BALLENTRY(UART2_CTS, "ab26", NULL),
657 _OMAP4_BALLENTRY(UART2_RTS, "ab27", NULL),
658 _OMAP4_BALLENTRY(UART2_RX, "aa25", NULL),
659 _OMAP4_BALLENTRY(UART2_TX, "aa26", NULL),
660 _OMAP4_BALLENTRY(HDQ_SIO, "aa27", NULL),
661 _OMAP4_BALLENTRY(I2C1_SCL, "ae28", NULL),
662 _OMAP4_BALLENTRY(I2C1_SDA, "ae26", NULL),
663 _OMAP4_BALLENTRY(I2C2_SCL, "c26", NULL),
664 _OMAP4_BALLENTRY(I2C2_SDA, "d26", NULL),
665 _OMAP4_BALLENTRY(I2C3_SCL, "w27", NULL),
666 _OMAP4_BALLENTRY(I2C3_SDA, "y27", NULL),
667 _OMAP4_BALLENTRY(I2C4_SCL, "ag21", NULL),
668 _OMAP4_BALLENTRY(I2C4_SDA, "ah22", NULL),
669 _OMAP4_BALLENTRY(MCSPI1_CLK, "af22", NULL),
670 _OMAP4_BALLENTRY(MCSPI1_SOMI, "ae22", NULL),
671 _OMAP4_BALLENTRY(MCSPI1_SIMO, "ag22", NULL),
672 _OMAP4_BALLENTRY(MCSPI1_CS0, "ae23", NULL),
673 _OMAP4_BALLENTRY(MCSPI1_CS1, "af23", NULL),
674 _OMAP4_BALLENTRY(MCSPI1_CS2, "ag23", NULL),
675 _OMAP4_BALLENTRY(MCSPI1_CS3, "ah23", NULL),
676 _OMAP4_BALLENTRY(UART3_CTS_RCTX, "f27", NULL),
677 _OMAP4_BALLENTRY(UART3_RTS_SD, "f28", NULL),
678 _OMAP4_BALLENTRY(UART3_RX_IRRX, "g27", NULL),
679 _OMAP4_BALLENTRY(UART3_TX_IRTX, "g28", NULL),
680 _OMAP4_BALLENTRY(SDMMC5_CLK, "ae5", NULL),
681 _OMAP4_BALLENTRY(SDMMC5_CMD, "af5", NULL),
682 _OMAP4_BALLENTRY(SDMMC5_DAT0, "ae4", NULL),
683 _OMAP4_BALLENTRY(SDMMC5_DAT1, "af4", NULL),
684 _OMAP4_BALLENTRY(SDMMC5_DAT2, "ag3", NULL),
685 _OMAP4_BALLENTRY(SDMMC5_DAT3, "af3", NULL),
686 _OMAP4_BALLENTRY(MCSPI4_CLK, "ae21", NULL),
687 _OMAP4_BALLENTRY(MCSPI4_SIMO, "af20", NULL),
688 _OMAP4_BALLENTRY(MCSPI4_SOMI, "af21", NULL),
689 _OMAP4_BALLENTRY(MCSPI4_CS0, "ae20", NULL),
690 _OMAP4_BALLENTRY(UART4_RX, "ag20", NULL),
691 _OMAP4_BALLENTRY(UART4_TX, "ah19", NULL),
692 _OMAP4_BALLENTRY(USBB2_ULPITLL_CLK, "ag12", NULL),
693 _OMAP4_BALLENTRY(USBB2_ULPITLL_STP, "af12", NULL),
694 _OMAP4_BALLENTRY(USBB2_ULPITLL_DIR, "ae12", NULL),
695 _OMAP4_BALLENTRY(USBB2_ULPITLL_NXT, "ag13", NULL),
696 _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT0, "ae11", NULL),
697 _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT1, "af11", NULL),
698 _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT2, "ag11", NULL),
699 _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT3, "ah11", NULL),
700 _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT4, "ae10", NULL),
701 _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT5, "af10", NULL),
702 _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT6, "ag10", NULL),
703 _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT7, "ae9", NULL),
704 _OMAP4_BALLENTRY(USBB2_HSIC_DATA, "af13", NULL),
705 _OMAP4_BALLENTRY(USBB2_HSIC_STROBE, "ae13", NULL),
706 _OMAP4_BALLENTRY(UNIPRO_TX0, "g26", NULL),
707 _OMAP4_BALLENTRY(UNIPRO_TY0, "g25", NULL),
708 _OMAP4_BALLENTRY(UNIPRO_TX1, "h26", NULL),
709 _OMAP4_BALLENTRY(UNIPRO_TY1, "h25", NULL),
710 _OMAP4_BALLENTRY(UNIPRO_TX2, "j27", NULL),
711 _OMAP4_BALLENTRY(UNIPRO_TY2, "h27", NULL),
712 _OMAP4_BALLENTRY(UNIPRO_RX0, "j26", NULL),
713 _OMAP4_BALLENTRY(UNIPRO_RY0, "j25", NULL),
714 _OMAP4_BALLENTRY(UNIPRO_RX1, "k26", NULL),
715 _OMAP4_BALLENTRY(UNIPRO_RY1, "k25", NULL),
716 _OMAP4_BALLENTRY(UNIPRO_RX2, "l27", NULL),
717 _OMAP4_BALLENTRY(UNIPRO_RY2, "k27", NULL),
718 _OMAP4_BALLENTRY(USBA0_OTG_CE, "c3", NULL),
719 _OMAP4_BALLENTRY(USBA0_OTG_DP, "b5", NULL),
720 _OMAP4_BALLENTRY(USBA0_OTG_DM, "b4", NULL),
721 _OMAP4_BALLENTRY(FREF_CLK1_OUT, "aa28", NULL),
722 _OMAP4_BALLENTRY(FREF_CLK2_OUT, "y28", NULL),
723 _OMAP4_BALLENTRY(SYS_NIRQ1, "ae6", NULL),
724 _OMAP4_BALLENTRY(SYS_NIRQ2, "af6", NULL),
725 _OMAP4_BALLENTRY(SYS_BOOT0, "f26", NULL),
726 _OMAP4_BALLENTRY(SYS_BOOT1, "e27", NULL),
727 _OMAP4_BALLENTRY(SYS_BOOT2, "e26", NULL),
728 _OMAP4_BALLENTRY(SYS_BOOT3, "e25", NULL),
729 _OMAP4_BALLENTRY(SYS_BOOT4, "d28", NULL),
730 _OMAP4_BALLENTRY(SYS_BOOT5, "d27", NULL),
731 _OMAP4_BALLENTRY(DPM_EMU0, "m2", NULL),
732 _OMAP4_BALLENTRY(DPM_EMU1, "n2", NULL),
733 _OMAP4_BALLENTRY(DPM_EMU2, "p2", NULL),
734 _OMAP4_BALLENTRY(DPM_EMU3, "v1", NULL),
735 _OMAP4_BALLENTRY(DPM_EMU4, "v2", NULL),
736 _OMAP4_BALLENTRY(DPM_EMU5, "w1", NULL),
737 _OMAP4_BALLENTRY(DPM_EMU6, "w2", NULL),
738 _OMAP4_BALLENTRY(DPM_EMU7, "w3", NULL),
739 _OMAP4_BALLENTRY(DPM_EMU8, "w4", NULL),
740 _OMAP4_BALLENTRY(DPM_EMU9, "y2", NULL),
741 _OMAP4_BALLENTRY(DPM_EMU10, "y3", NULL),
742 _OMAP4_BALLENTRY(DPM_EMU11, "y4", NULL),
743 _OMAP4_BALLENTRY(DPM_EMU12, "aa1", NULL),
744 _OMAP4_BALLENTRY(DPM_EMU13, "aa2", NULL),
745 _OMAP4_BALLENTRY(DPM_EMU14, "aa3", NULL),
746 _OMAP4_BALLENTRY(DPM_EMU15, "aa4", NULL),
747 _OMAP4_BALLENTRY(DPM_EMU16, "ab2", NULL),
748 _OMAP4_BALLENTRY(DPM_EMU17, "ab3", NULL),
749 _OMAP4_BALLENTRY(DPM_EMU18, "ab4", NULL),
750 _OMAP4_BALLENTRY(DPM_EMU19, "ac4", NULL),
751 { .reg_offset = OMAP_MUX_TERMINATOR },
752};
753#else
754#define omap4_core_cbl_ball NULL
755#endif
756
757/*
758 * Superset of all mux modes for omap4 ES2.0
759 */
760static struct omap_mux __initdata omap4_es2_core_muxmodes[] = {
761 _OMAP4_MUXENTRY(GPMC_AD0, 0, "gpmc_ad0", "sdmmc2_dat0", NULL, NULL,
762 NULL, NULL, NULL, NULL),
763 _OMAP4_MUXENTRY(GPMC_AD1, 0, "gpmc_ad1", "sdmmc2_dat1", NULL, NULL,
764 NULL, NULL, NULL, NULL),
765 _OMAP4_MUXENTRY(GPMC_AD2, 0, "gpmc_ad2", "sdmmc2_dat2", NULL, NULL,
766 NULL, NULL, NULL, NULL),
767 _OMAP4_MUXENTRY(GPMC_AD3, 0, "gpmc_ad3", "sdmmc2_dat3", NULL, NULL,
768 NULL, NULL, NULL, NULL),
769 _OMAP4_MUXENTRY(GPMC_AD4, 0, "gpmc_ad4", "sdmmc2_dat4",
770 "sdmmc2_dir_dat0", NULL, NULL, NULL, NULL, NULL),
771 _OMAP4_MUXENTRY(GPMC_AD5, 0, "gpmc_ad5", "sdmmc2_dat5",
772 "sdmmc2_dir_dat1", NULL, NULL, NULL, NULL, NULL),
773 _OMAP4_MUXENTRY(GPMC_AD6, 0, "gpmc_ad6", "sdmmc2_dat6",
774 "sdmmc2_dir_cmd", NULL, NULL, NULL, NULL, NULL),
775 _OMAP4_MUXENTRY(GPMC_AD7, 0, "gpmc_ad7", "sdmmc2_dat7",
776 "sdmmc2_clk_fdbk", NULL, NULL, NULL, NULL, NULL),
777 _OMAP4_MUXENTRY(GPMC_AD8, 32, "gpmc_ad8", "kpd_row0", "c2c_data15",
778 "gpio_32", NULL, "sdmmc1_dat0", NULL, NULL),
779 _OMAP4_MUXENTRY(GPMC_AD9, 33, "gpmc_ad9", "kpd_row1", "c2c_data14",
780 "gpio_33", NULL, "sdmmc1_dat1", NULL, NULL),
781 _OMAP4_MUXENTRY(GPMC_AD10, 34, "gpmc_ad10", "kpd_row2", "c2c_data13",
782 "gpio_34", NULL, "sdmmc1_dat2", NULL, NULL),
783 _OMAP4_MUXENTRY(GPMC_AD11, 35, "gpmc_ad11", "kpd_row3", "c2c_data12",
784 "gpio_35", NULL, "sdmmc1_dat3", NULL, NULL),
785 _OMAP4_MUXENTRY(GPMC_AD12, 36, "gpmc_ad12", "kpd_col0", "c2c_data11",
786 "gpio_36", NULL, "sdmmc1_dat4", NULL, NULL),
787 _OMAP4_MUXENTRY(GPMC_AD13, 37, "gpmc_ad13", "kpd_col1", "c2c_data10",
788 "gpio_37", NULL, "sdmmc1_dat5", NULL, NULL),
789 _OMAP4_MUXENTRY(GPMC_AD14, 38, "gpmc_ad14", "kpd_col2", "c2c_data9",
790 "gpio_38", NULL, "sdmmc1_dat6", NULL, NULL),
791 _OMAP4_MUXENTRY(GPMC_AD15, 39, "gpmc_ad15", "kpd_col3", "c2c_data8",
792 "gpio_39", NULL, "sdmmc1_dat7", NULL, NULL),
793 _OMAP4_MUXENTRY(GPMC_A16, 40, "gpmc_a16", "kpd_row4", "c2c_datain0",
794 "gpio_40", "venc_656_data0", NULL, NULL, "safe_mode"),
795 _OMAP4_MUXENTRY(GPMC_A17, 41, "gpmc_a17", "kpd_row5", "c2c_datain1",
796 "gpio_41", "venc_656_data1", NULL, NULL, "safe_mode"),
797 _OMAP4_MUXENTRY(GPMC_A18, 42, "gpmc_a18", "kpd_row6", "c2c_datain2",
798 "gpio_42", "venc_656_data2", NULL, NULL, "safe_mode"),
799 _OMAP4_MUXENTRY(GPMC_A19, 43, "gpmc_a19", "kpd_row7", "c2c_datain3",
800 "gpio_43", "venc_656_data3", NULL, NULL, "safe_mode"),
801 _OMAP4_MUXENTRY(GPMC_A20, 44, "gpmc_a20", "kpd_col4", "c2c_datain4",
802 "gpio_44", "venc_656_data4", NULL, NULL, "safe_mode"),
803 _OMAP4_MUXENTRY(GPMC_A21, 45, "gpmc_a21", "kpd_col5", "c2c_datain5",
804 "gpio_45", "venc_656_data5", NULL, NULL, "safe_mode"),
805 _OMAP4_MUXENTRY(GPMC_A22, 46, "gpmc_a22", "kpd_col6", "c2c_datain6",
806 "gpio_46", "venc_656_data6", NULL, NULL, "safe_mode"),
807 _OMAP4_MUXENTRY(GPMC_A23, 47, "gpmc_a23", "kpd_col7", "c2c_datain7",
808 "gpio_47", "venc_656_data7", NULL, NULL, "safe_mode"),
809 _OMAP4_MUXENTRY(GPMC_A24, 48, "gpmc_a24", "kpd_col8", "c2c_clkout0",
810 "gpio_48", NULL, NULL, NULL, "safe_mode"),
811 _OMAP4_MUXENTRY(GPMC_A25, 49, "gpmc_a25", NULL, "c2c_clkout1",
812 "gpio_49", NULL, NULL, NULL, "safe_mode"),
813 _OMAP4_MUXENTRY(GPMC_NCS0, 50, "gpmc_ncs0", NULL, NULL, "gpio_50",
814 "sys_ndmareq0", NULL, NULL, NULL),
815 _OMAP4_MUXENTRY(GPMC_NCS1, 51, "gpmc_ncs1", NULL, "c2c_dataout6",
816 "gpio_51", NULL, NULL, NULL, "safe_mode"),
817 _OMAP4_MUXENTRY(GPMC_NCS2, 52, "gpmc_ncs2", "kpd_row8",
818 "c2c_dataout7", "gpio_52", NULL, NULL, NULL,
819 "safe_mode"),
820 _OMAP4_MUXENTRY(GPMC_NCS3, 53, "gpmc_ncs3", "gpmc_dir",
821 "c2c_dataout4", "gpio_53", NULL, NULL, NULL,
822 "safe_mode"),
823 _OMAP4_MUXENTRY(GPMC_NWP, 54, "gpmc_nwp", "dsi1_te0", NULL, "gpio_54",
824 "sys_ndmareq1", NULL, NULL, NULL),
825 _OMAP4_MUXENTRY(GPMC_CLK, 55, "gpmc_clk", NULL, NULL, "gpio_55",
826 "sys_ndmareq2", "sdmmc1_cmd", NULL, NULL),
827 _OMAP4_MUXENTRY(GPMC_NADV_ALE, 56, "gpmc_nadv_ale", "dsi1_te1", NULL,
828 "gpio_56", "sys_ndmareq3", "sdmmc1_clk", NULL, NULL),
829 _OMAP4_MUXENTRY(GPMC_NOE, 0, "gpmc_noe", "sdmmc2_clk", NULL, NULL,
830 NULL, NULL, NULL, NULL),
831 _OMAP4_MUXENTRY(GPMC_NWE, 0, "gpmc_nwe", "sdmmc2_cmd", NULL, NULL,
832 NULL, NULL, NULL, NULL),
833 _OMAP4_MUXENTRY(GPMC_NBE0_CLE, 59, "gpmc_nbe0_cle", "dsi2_te0", NULL,
834 "gpio_59", NULL, NULL, NULL, NULL),
835 _OMAP4_MUXENTRY(GPMC_NBE1, 60, "gpmc_nbe1", NULL, "c2c_dataout5",
836 "gpio_60", NULL, NULL, NULL, "safe_mode"),
837 _OMAP4_MUXENTRY(GPMC_WAIT0, 61, "gpmc_wait0", "dsi2_te1", NULL,
838 "gpio_61", NULL, NULL, NULL, NULL),
839 _OMAP4_MUXENTRY(GPMC_WAIT1, 62, "gpmc_wait1", NULL, "c2c_dataout2",
840 "gpio_62", NULL, NULL, NULL, "safe_mode"),
841 _OMAP4_MUXENTRY(GPMC_WAIT2, 100, "gpmc_wait2", "usbc1_icusb_txen",
842 "c2c_dataout3", "gpio_100", "sys_ndmareq0", NULL,
843 NULL, "safe_mode"),
844 _OMAP4_MUXENTRY(GPMC_NCS4, 101, "gpmc_ncs4", "dsi1_te0", "c2c_clkin0",
845 "gpio_101", "sys_ndmareq1", NULL, NULL, "safe_mode"),
846 _OMAP4_MUXENTRY(GPMC_NCS5, 102, "gpmc_ncs5", "dsi1_te1", "c2c_clkin1",
847 "gpio_102", "sys_ndmareq2", NULL, NULL, "safe_mode"),
848 _OMAP4_MUXENTRY(GPMC_NCS6, 103, "gpmc_ncs6", "dsi2_te0",
849 "c2c_dataout0", "gpio_103", "sys_ndmareq3", NULL,
850 NULL, "safe_mode"),
851 _OMAP4_MUXENTRY(GPMC_NCS7, 104, "gpmc_ncs7", "dsi2_te1",
852 "c2c_dataout1", "gpio_104", NULL, NULL, NULL,
853 "safe_mode"),
854 _OMAP4_MUXENTRY(HDMI_HPD, 63, "hdmi_hpd", NULL, NULL, "gpio_63", NULL,
855 NULL, NULL, "safe_mode"),
856 _OMAP4_MUXENTRY(HDMI_CEC, 64, "hdmi_cec", NULL, NULL, "gpio_64", NULL,
857 NULL, NULL, "safe_mode"),
858 _OMAP4_MUXENTRY(HDMI_DDC_SCL, 65, "hdmi_ddc_scl", NULL, NULL,
859 "gpio_65", NULL, NULL, NULL, "safe_mode"),
860 _OMAP4_MUXENTRY(HDMI_DDC_SDA, 66, "hdmi_ddc_sda", NULL, NULL,
861 "gpio_66", NULL, NULL, NULL, "safe_mode"),
862 _OMAP4_MUXENTRY(CSI21_DX0, 0, "csi21_dx0", NULL, NULL, "gpi_67", NULL,
863 NULL, NULL, "safe_mode"),
864 _OMAP4_MUXENTRY(CSI21_DY0, 0, "csi21_dy0", NULL, NULL, "gpi_68", NULL,
865 NULL, NULL, "safe_mode"),
866 _OMAP4_MUXENTRY(CSI21_DX1, 0, "csi21_dx1", NULL, NULL, "gpi_69", NULL,
867 NULL, NULL, "safe_mode"),
868 _OMAP4_MUXENTRY(CSI21_DY1, 0, "csi21_dy1", NULL, NULL, "gpi_70", NULL,
869 NULL, NULL, "safe_mode"),
870 _OMAP4_MUXENTRY(CSI21_DX2, 0, "csi21_dx2", NULL, NULL, "gpi_71", NULL,
871 NULL, NULL, "safe_mode"),
872 _OMAP4_MUXENTRY(CSI21_DY2, 0, "csi21_dy2", NULL, NULL, "gpi_72", NULL,
873 NULL, NULL, "safe_mode"),
874 _OMAP4_MUXENTRY(CSI21_DX3, 0, "csi21_dx3", NULL, NULL, "gpi_73", NULL,
875 NULL, NULL, "safe_mode"),
876 _OMAP4_MUXENTRY(CSI21_DY3, 0, "csi21_dy3", NULL, NULL, "gpi_74", NULL,
877 NULL, NULL, "safe_mode"),
878 _OMAP4_MUXENTRY(CSI21_DX4, 0, "csi21_dx4", NULL, NULL, "gpi_75", NULL,
879 NULL, NULL, "safe_mode"),
880 _OMAP4_MUXENTRY(CSI21_DY4, 0, "csi21_dy4", NULL, NULL, "gpi_76", NULL,
881 NULL, NULL, "safe_mode"),
882 _OMAP4_MUXENTRY(CSI22_DX0, 0, "csi22_dx0", NULL, NULL, "gpi_77", NULL,
883 NULL, NULL, "safe_mode"),
884 _OMAP4_MUXENTRY(CSI22_DY0, 0, "csi22_dy0", NULL, NULL, "gpi_78", NULL,
885 NULL, NULL, "safe_mode"),
886 _OMAP4_MUXENTRY(CSI22_DX1, 0, "csi22_dx1", NULL, NULL, "gpi_79", NULL,
887 NULL, NULL, "safe_mode"),
888 _OMAP4_MUXENTRY(CSI22_DY1, 0, "csi22_dy1", NULL, NULL, "gpi_80", NULL,
889 NULL, NULL, "safe_mode"),
890 _OMAP4_MUXENTRY(CAM_SHUTTER, 81, "cam_shutter", NULL, NULL, "gpio_81",
891 NULL, NULL, NULL, "safe_mode"),
892 _OMAP4_MUXENTRY(CAM_STROBE, 82, "cam_strobe", NULL, NULL, "gpio_82",
893 NULL, NULL, NULL, "safe_mode"),
894 _OMAP4_MUXENTRY(CAM_GLOBALRESET, 83, "cam_globalreset", NULL, NULL,
895 "gpio_83", NULL, NULL, NULL, "safe_mode"),
896 _OMAP4_MUXENTRY(USBB1_ULPITLL_CLK, 84, "usbb1_ulpitll_clk",
897 "hsi1_cawake", NULL, "gpio_84", "usbb1_ulpiphy_clk",
898 NULL, "hw_dbg20", "safe_mode"),
899 _OMAP4_MUXENTRY(USBB1_ULPITLL_STP, 85, "usbb1_ulpitll_stp",
900 "hsi1_cadata", "mcbsp4_clkr", "gpio_85",
901 "usbb1_ulpiphy_stp", "usbb1_mm_rxdp", "hw_dbg21",
902 "safe_mode"),
903 _OMAP4_MUXENTRY(USBB1_ULPITLL_DIR, 86, "usbb1_ulpitll_dir",
904 "hsi1_caflag", "mcbsp4_fsr", "gpio_86",
905 "usbb1_ulpiphy_dir", NULL, "hw_dbg22", "safe_mode"),
906 _OMAP4_MUXENTRY(USBB1_ULPITLL_NXT, 87, "usbb1_ulpitll_nxt",
907 "hsi1_acready", "mcbsp4_fsx", "gpio_87",
908 "usbb1_ulpiphy_nxt", "usbb1_mm_rxdm", "hw_dbg23",
909 "safe_mode"),
910 _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT0, 88, "usbb1_ulpitll_dat0",
911 "hsi1_acwake", "mcbsp4_clkx", "gpio_88",
912 "usbb1_ulpiphy_dat0", "usbb1_mm_txen", "hw_dbg24",
913 "safe_mode"),
914 _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT1, 89, "usbb1_ulpitll_dat1",
915 "hsi1_acdata", "mcbsp4_dx", "gpio_89",
916 "usbb1_ulpiphy_dat1", "usbb1_mm_txdat", "hw_dbg25",
917 "safe_mode"),
918 _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT2, 90, "usbb1_ulpitll_dat2",
919 "hsi1_acflag", "mcbsp4_dr", "gpio_90",
920 "usbb1_ulpiphy_dat2", "usbb1_mm_txse0", "hw_dbg26",
921 "safe_mode"),
922 _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT3, 91, "usbb1_ulpitll_dat3",
923 "hsi1_caready", NULL, "gpio_91", "usbb1_ulpiphy_dat3",
924 "usbb1_mm_rxrcv", "hw_dbg27", "safe_mode"),
925 _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT4, 92, "usbb1_ulpitll_dat4",
926 "dmtimer8_pwm_evt", "abe_mcbsp3_dr", "gpio_92",
927 "usbb1_ulpiphy_dat4", NULL, "hw_dbg28", "safe_mode"),
928 _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT5, 93, "usbb1_ulpitll_dat5",
929 "dmtimer9_pwm_evt", "abe_mcbsp3_dx", "gpio_93",
930 "usbb1_ulpiphy_dat5", NULL, "hw_dbg29", "safe_mode"),
931 _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT6, 94, "usbb1_ulpitll_dat6",
932 "dmtimer10_pwm_evt", "abe_mcbsp3_clkx", "gpio_94",
933 "usbb1_ulpiphy_dat6", "abe_dmic_din3", "hw_dbg30",
934 "safe_mode"),
935 _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT7, 95, "usbb1_ulpitll_dat7",
936 "dmtimer11_pwm_evt", "abe_mcbsp3_fsx", "gpio_95",
937 "usbb1_ulpiphy_dat7", "abe_dmic_clk3", "hw_dbg31",
938 "safe_mode"),
939 _OMAP4_MUXENTRY(USBB1_HSIC_DATA, 96, "usbb1_hsic_data", NULL, NULL,
940 "gpio_96", NULL, NULL, NULL, "safe_mode"),
941 _OMAP4_MUXENTRY(USBB1_HSIC_STROBE, 97, "usbb1_hsic_strobe", NULL,
942 NULL, "gpio_97", NULL, NULL, NULL, "safe_mode"),
943 _OMAP4_MUXENTRY(USBC1_ICUSB_DP, 98, "usbc1_icusb_dp", NULL, NULL,
944 "gpio_98", NULL, NULL, NULL, "safe_mode"),
945 _OMAP4_MUXENTRY(USBC1_ICUSB_DM, 99, "usbc1_icusb_dm", NULL, NULL,
946 "gpio_99", NULL, NULL, NULL, "safe_mode"),
947 _OMAP4_MUXENTRY(SDMMC1_CLK, 100, "sdmmc1_clk", NULL, "dpm_emu19",
948 "gpio_100", NULL, NULL, NULL, "safe_mode"),
949 _OMAP4_MUXENTRY(SDMMC1_CMD, 101, "sdmmc1_cmd", NULL, "uart1_rx",
950 "gpio_101", NULL, NULL, NULL, "safe_mode"),
951 _OMAP4_MUXENTRY(SDMMC1_DAT0, 102, "sdmmc1_dat0", NULL, "dpm_emu18",
952 "gpio_102", NULL, NULL, NULL, "safe_mode"),
953 _OMAP4_MUXENTRY(SDMMC1_DAT1, 103, "sdmmc1_dat1", NULL, "dpm_emu17",
954 "gpio_103", NULL, NULL, NULL, "safe_mode"),
955 _OMAP4_MUXENTRY(SDMMC1_DAT2, 104, "sdmmc1_dat2", NULL, "dpm_emu16",
956 "gpio_104", "jtag_tms_tmsc", NULL, NULL, "safe_mode"),
957 _OMAP4_MUXENTRY(SDMMC1_DAT3, 105, "sdmmc1_dat3", NULL, "dpm_emu15",
958 "gpio_105", "jtag_tck", NULL, NULL, "safe_mode"),
959 _OMAP4_MUXENTRY(SDMMC1_DAT4, 106, "sdmmc1_dat4", NULL, NULL,
960 "gpio_106", NULL, NULL, NULL, "safe_mode"),
961 _OMAP4_MUXENTRY(SDMMC1_DAT5, 107, "sdmmc1_dat5", NULL, NULL,
962 "gpio_107", NULL, NULL, NULL, "safe_mode"),
963 _OMAP4_MUXENTRY(SDMMC1_DAT6, 108, "sdmmc1_dat6", NULL, NULL,
964 "gpio_108", NULL, NULL, NULL, "safe_mode"),
965 _OMAP4_MUXENTRY(SDMMC1_DAT7, 109, "sdmmc1_dat7", NULL, NULL,
966 "gpio_109", NULL, NULL, NULL, "safe_mode"),
967 _OMAP4_MUXENTRY(ABE_MCBSP2_CLKX, 110, "abe_mcbsp2_clkx", "mcspi2_clk",
968 "abe_mcasp_ahclkx", "gpio_110", "usbb2_mm_rxdm",
969 NULL, NULL, "safe_mode"),
970 _OMAP4_MUXENTRY(ABE_MCBSP2_DR, 111, "abe_mcbsp2_dr", "mcspi2_somi",
971 "abe_mcasp_axr", "gpio_111", "usbb2_mm_rxdp", NULL,
972 NULL, "safe_mode"),
973 _OMAP4_MUXENTRY(ABE_MCBSP2_DX, 112, "abe_mcbsp2_dx", "mcspi2_simo",
974 "abe_mcasp_amute", "gpio_112", "usbb2_mm_rxrcv", NULL,
975 NULL, "safe_mode"),
976 _OMAP4_MUXENTRY(ABE_MCBSP2_FSX, 113, "abe_mcbsp2_fsx", "mcspi2_cs0",
977 "abe_mcasp_afsx", "gpio_113", "usbb2_mm_txen", NULL,
978 NULL, "safe_mode"),
979 _OMAP4_MUXENTRY(ABE_MCBSP1_CLKX, 114, "abe_mcbsp1_clkx",
980 "abe_slimbus1_clock", NULL, "gpio_114", NULL, NULL,
981 NULL, "safe_mode"),
982 _OMAP4_MUXENTRY(ABE_MCBSP1_DR, 115, "abe_mcbsp1_dr",
983 "abe_slimbus1_data", NULL, "gpio_115", NULL, NULL,
984 NULL, "safe_mode"),
985 _OMAP4_MUXENTRY(ABE_MCBSP1_DX, 116, "abe_mcbsp1_dx", "sdmmc3_dat2",
986 "abe_mcasp_aclkx", "gpio_116", NULL, NULL, NULL,
987 "safe_mode"),
988 _OMAP4_MUXENTRY(ABE_MCBSP1_FSX, 117, "abe_mcbsp1_fsx", "sdmmc3_dat3",
989 "abe_mcasp_amutein", "gpio_117", NULL, NULL, NULL,
990 "safe_mode"),
991 _OMAP4_MUXENTRY(ABE_PDM_UL_DATA, 0, "abe_pdm_ul_data",
992 "abe_mcbsp3_dr", NULL, NULL, NULL, NULL, NULL,
993 "safe_mode"),
994 _OMAP4_MUXENTRY(ABE_PDM_DL_DATA, 0, "abe_pdm_dl_data",
995 "abe_mcbsp3_dx", NULL, NULL, NULL, NULL, NULL,
996 "safe_mode"),
997 _OMAP4_MUXENTRY(ABE_PDM_FRAME, 0, "abe_pdm_frame", "abe_mcbsp3_clkx",
998 NULL, NULL, NULL, NULL, NULL, "safe_mode"),
999 _OMAP4_MUXENTRY(ABE_PDM_LB_CLK, 0, "abe_pdm_lb_clk", "abe_mcbsp3_fsx",
1000 NULL, NULL, NULL, NULL, NULL, "safe_mode"),
1001 _OMAP4_MUXENTRY(ABE_CLKS, 118, "abe_clks", NULL, NULL, "gpio_118",
1002 NULL, NULL, NULL, "safe_mode"),
1003 _OMAP4_MUXENTRY(ABE_DMIC_CLK1, 119, "abe_dmic_clk1", NULL, NULL,
1004 "gpio_119", "usbb2_mm_txse0", "uart4_cts", NULL,
1005 "safe_mode"),
1006 _OMAP4_MUXENTRY(ABE_DMIC_DIN1, 120, "abe_dmic_din1", NULL, NULL,
1007 "gpio_120", "usbb2_mm_txdat", "uart4_rts", NULL,
1008 "safe_mode"),
1009 _OMAP4_MUXENTRY(ABE_DMIC_DIN2, 121, "abe_dmic_din2", "slimbus2_clock",
1010 "abe_mcasp_axr", "gpio_121", NULL,
1011 "dmtimer11_pwm_evt", NULL, "safe_mode"),
1012 _OMAP4_MUXENTRY(ABE_DMIC_DIN3, 122, "abe_dmic_din3", "slimbus2_data",
1013 "abe_dmic_clk2", "gpio_122", NULL, "dmtimer9_pwm_evt",
1014 NULL, "safe_mode"),
1015 _OMAP4_MUXENTRY(UART2_CTS, 123, "uart2_cts", "sdmmc3_clk", NULL,
1016 "gpio_123", NULL, NULL, NULL, "safe_mode"),
1017 _OMAP4_MUXENTRY(UART2_RTS, 124, "uart2_rts", "sdmmc3_cmd", NULL,
1018 "gpio_124", NULL, NULL, NULL, "safe_mode"),
1019 _OMAP4_MUXENTRY(UART2_RX, 125, "uart2_rx", "sdmmc3_dat0", NULL,
1020 "gpio_125", NULL, NULL, NULL, "safe_mode"),
1021 _OMAP4_MUXENTRY(UART2_TX, 126, "uart2_tx", "sdmmc3_dat1", NULL,
1022 "gpio_126", NULL, NULL, NULL, "safe_mode"),
1023 _OMAP4_MUXENTRY(HDQ_SIO, 127, "hdq_sio", "i2c3_sccb", "i2c2_sccb",
1024 "gpio_127", NULL, NULL, NULL, "safe_mode"),
1025 _OMAP4_MUXENTRY(I2C1_SCL, 0, "i2c1_scl", NULL, NULL, NULL, NULL, NULL,
1026 NULL, NULL),
1027 _OMAP4_MUXENTRY(I2C1_SDA, 0, "i2c1_sda", NULL, NULL, NULL, NULL, NULL,
1028 NULL, NULL),
1029 _OMAP4_MUXENTRY(I2C2_SCL, 128, "i2c2_scl", "uart1_rx", NULL,
1030 "gpio_128", NULL, NULL, NULL, "safe_mode"),
1031 _OMAP4_MUXENTRY(I2C2_SDA, 129, "i2c2_sda", "uart1_tx", NULL,
1032 "gpio_129", NULL, NULL, NULL, "safe_mode"),
1033 _OMAP4_MUXENTRY(I2C3_SCL, 130, "i2c3_scl", NULL, NULL, "gpio_130",
1034 NULL, NULL, NULL, "safe_mode"),
1035 _OMAP4_MUXENTRY(I2C3_SDA, 131, "i2c3_sda", NULL, NULL, "gpio_131",
1036 NULL, NULL, NULL, "safe_mode"),
1037 _OMAP4_MUXENTRY(I2C4_SCL, 132, "i2c4_scl", NULL, NULL, "gpio_132",
1038 NULL, NULL, NULL, "safe_mode"),
1039 _OMAP4_MUXENTRY(I2C4_SDA, 133, "i2c4_sda", NULL, NULL, "gpio_133",
1040 NULL, NULL, NULL, "safe_mode"),
1041 _OMAP4_MUXENTRY(MCSPI1_CLK, 134, "mcspi1_clk", NULL, NULL, "gpio_134",
1042 NULL, NULL, NULL, "safe_mode"),
1043 _OMAP4_MUXENTRY(MCSPI1_SOMI, 135, "mcspi1_somi", NULL, NULL,
1044 "gpio_135", NULL, NULL, NULL, "safe_mode"),
1045 _OMAP4_MUXENTRY(MCSPI1_SIMO, 136, "mcspi1_simo", NULL, NULL,
1046 "gpio_136", NULL, NULL, NULL, "safe_mode"),
1047 _OMAP4_MUXENTRY(MCSPI1_CS0, 137, "mcspi1_cs0", NULL, NULL, "gpio_137",
1048 NULL, NULL, NULL, "safe_mode"),
1049 _OMAP4_MUXENTRY(MCSPI1_CS1, 138, "mcspi1_cs1", "uart1_rx", NULL,
1050 "gpio_138", NULL, NULL, NULL, "safe_mode"),
1051 _OMAP4_MUXENTRY(MCSPI1_CS2, 139, "mcspi1_cs2", "uart1_cts",
1052 "slimbus2_clock", "gpio_139", NULL, NULL, NULL,
1053 "safe_mode"),
1054 _OMAP4_MUXENTRY(MCSPI1_CS3, 140, "mcspi1_cs3", "uart1_rts",
1055 "slimbus2_data", "gpio_140", NULL, NULL, NULL,
1056 "safe_mode"),
1057 _OMAP4_MUXENTRY(UART3_CTS_RCTX, 141, "uart3_cts_rctx", "uart1_tx",
1058 NULL, "gpio_141", NULL, NULL, NULL, "safe_mode"),
1059 _OMAP4_MUXENTRY(UART3_RTS_SD, 142, "uart3_rts_sd", NULL, NULL,
1060 "gpio_142", NULL, NULL, NULL, "safe_mode"),
1061 _OMAP4_MUXENTRY(UART3_RX_IRRX, 143, "uart3_rx_irrx",
1062 "dmtimer8_pwm_evt", NULL, "gpio_143", NULL, NULL,
1063 NULL, "safe_mode"),
1064 _OMAP4_MUXENTRY(UART3_TX_IRTX, 144, "uart3_tx_irtx",
1065 "dmtimer9_pwm_evt", NULL, "gpio_144", NULL, NULL,
1066 NULL, "safe_mode"),
1067 _OMAP4_MUXENTRY(SDMMC5_CLK, 145, "sdmmc5_clk", "mcspi2_clk",
1068 "usbc1_icusb_dp", "gpio_145", NULL, "sdmmc2_clk",
1069 NULL, "safe_mode"),
1070 _OMAP4_MUXENTRY(SDMMC5_CMD, 146, "sdmmc5_cmd", "mcspi2_simo",
1071 "usbc1_icusb_dm", "gpio_146", NULL, "sdmmc2_cmd",
1072 NULL, "safe_mode"),
1073 _OMAP4_MUXENTRY(SDMMC5_DAT0, 147, "sdmmc5_dat0", "mcspi2_somi",
1074 "usbc1_icusb_rcv", "gpio_147", NULL, "sdmmc2_dat0",
1075 NULL, "safe_mode"),
1076 _OMAP4_MUXENTRY(SDMMC5_DAT1, 148, "sdmmc5_dat1", NULL,
1077 "usbc1_icusb_txen", "gpio_148", NULL, "sdmmc2_dat1",
1078 NULL, "safe_mode"),
1079 _OMAP4_MUXENTRY(SDMMC5_DAT2, 149, "sdmmc5_dat2", "mcspi2_cs1", NULL,
1080 "gpio_149", NULL, "sdmmc2_dat2", NULL, "safe_mode"),
1081 _OMAP4_MUXENTRY(SDMMC5_DAT3, 150, "sdmmc5_dat3", "mcspi2_cs0", NULL,
1082 "gpio_150", NULL, "sdmmc2_dat3", NULL, "safe_mode"),
1083 _OMAP4_MUXENTRY(MCSPI4_CLK, 151, "mcspi4_clk", "sdmmc4_clk",
1084 "kpd_col6", "gpio_151", NULL, NULL, NULL,
1085 "safe_mode"),
1086 _OMAP4_MUXENTRY(MCSPI4_SIMO, 152, "mcspi4_simo", "sdmmc4_cmd",
1087 "kpd_col7", "gpio_152", NULL, NULL, NULL,
1088 "safe_mode"),
1089 _OMAP4_MUXENTRY(MCSPI4_SOMI, 153, "mcspi4_somi", "sdmmc4_dat0",
1090 "kpd_row6", "gpio_153", NULL, NULL, NULL,
1091 "safe_mode"),
1092 _OMAP4_MUXENTRY(MCSPI4_CS0, 154, "mcspi4_cs0", "sdmmc4_dat3",
1093 "kpd_row7", "gpio_154", NULL, NULL, NULL,
1094 "safe_mode"),
1095 _OMAP4_MUXENTRY(UART4_RX, 155, "uart4_rx", "sdmmc4_dat2", "kpd_row8",
1096 "gpio_155", NULL, NULL, NULL, "safe_mode"),
1097 _OMAP4_MUXENTRY(UART4_TX, 156, "uart4_tx", "sdmmc4_dat1", "kpd_col8",
1098 "gpio_156", NULL, NULL, NULL, "safe_mode"),
1099 _OMAP4_MUXENTRY(USBB2_ULPITLL_CLK, 157, "usbb2_ulpitll_clk",
1100 "usbb2_ulpiphy_clk", "sdmmc4_cmd", "gpio_157",
1101 "hsi2_cawake", NULL, NULL, "safe_mode"),
1102 _OMAP4_MUXENTRY(USBB2_ULPITLL_STP, 158, "usbb2_ulpitll_stp",
1103 "usbb2_ulpiphy_stp", "sdmmc4_clk", "gpio_158",
1104 "hsi2_cadata", "dispc2_data23", NULL, "safe_mode"),
1105 _OMAP4_MUXENTRY(USBB2_ULPITLL_DIR, 159, "usbb2_ulpitll_dir",
1106 "usbb2_ulpiphy_dir", "sdmmc4_dat0", "gpio_159",
1107 "hsi2_caflag", "dispc2_data22", NULL, "safe_mode"),
1108 _OMAP4_MUXENTRY(USBB2_ULPITLL_NXT, 160, "usbb2_ulpitll_nxt",
1109 "usbb2_ulpiphy_nxt", "sdmmc4_dat1", "gpio_160",
1110 "hsi2_acready", "dispc2_data21", NULL, "safe_mode"),
1111 _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT0, 161, "usbb2_ulpitll_dat0",
1112 "usbb2_ulpiphy_dat0", "sdmmc4_dat2", "gpio_161",
1113 "hsi2_acwake", "dispc2_data20", "usbb2_mm_txen",
1114 "safe_mode"),
1115 _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT1, 162, "usbb2_ulpitll_dat1",
1116 "usbb2_ulpiphy_dat1", "sdmmc4_dat3", "gpio_162",
1117 "hsi2_acdata", "dispc2_data19", "usbb2_mm_txdat",
1118 "safe_mode"),
1119 _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT2, 163, "usbb2_ulpitll_dat2",
1120 "usbb2_ulpiphy_dat2", "sdmmc3_dat2", "gpio_163",
1121 "hsi2_acflag", "dispc2_data18", "usbb2_mm_txse0",
1122 "safe_mode"),
1123 _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT3, 164, "usbb2_ulpitll_dat3",
1124 "usbb2_ulpiphy_dat3", "sdmmc3_dat1", "gpio_164",
1125 "hsi2_caready", "dispc2_data15", "rfbi_data15",
1126 "safe_mode"),
1127 _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT4, 165, "usbb2_ulpitll_dat4",
1128 "usbb2_ulpiphy_dat4", "sdmmc3_dat0", "gpio_165",
1129 "mcspi3_somi", "dispc2_data14", "rfbi_data14",
1130 "safe_mode"),
1131 _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT5, 166, "usbb2_ulpitll_dat5",
1132 "usbb2_ulpiphy_dat5", "sdmmc3_dat3", "gpio_166",
1133 "mcspi3_cs0", "dispc2_data13", "rfbi_data13",
1134 "safe_mode"),
1135 _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT6, 167, "usbb2_ulpitll_dat6",
1136 "usbb2_ulpiphy_dat6", "sdmmc3_cmd", "gpio_167",
1137 "mcspi3_simo", "dispc2_data12", "rfbi_data12",
1138 "safe_mode"),
1139 _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT7, 168, "usbb2_ulpitll_dat7",
1140 "usbb2_ulpiphy_dat7", "sdmmc3_clk", "gpio_168",
1141 "mcspi3_clk", "dispc2_data11", "rfbi_data11",
1142 "safe_mode"),
1143 _OMAP4_MUXENTRY(USBB2_HSIC_DATA, 169, "usbb2_hsic_data", NULL, NULL,
1144 "gpio_169", NULL, NULL, NULL, "safe_mode"),
1145 _OMAP4_MUXENTRY(USBB2_HSIC_STROBE, 170, "usbb2_hsic_strobe", NULL,
1146 NULL, "gpio_170", NULL, NULL, NULL, "safe_mode"),
1147 _OMAP4_MUXENTRY(KPD_COL3, 171, "kpd_col3", "kpd_col0", NULL,
1148 "gpio_171", NULL, NULL, NULL, "safe_mode"),
1149 _OMAP4_MUXENTRY(KPD_COL4, 172, "kpd_col4", "kpd_col1", NULL,
1150 "gpio_172", NULL, NULL, NULL, "safe_mode"),
1151 _OMAP4_MUXENTRY(KPD_COL5, 173, "kpd_col5", "kpd_col2", NULL,
1152 "gpio_173", NULL, NULL, NULL, "safe_mode"),
1153 _OMAP4_MUXENTRY(KPD_COL0, 174, "kpd_col0", "kpd_col3", NULL,
1154 "gpio_174", NULL, NULL, NULL, "safe_mode"),
1155 _OMAP4_MUXENTRY(KPD_COL1, 0, "kpd_col1", "kpd_col4", NULL, "gpio_0",
1156 NULL, NULL, NULL, "safe_mode"),
1157 _OMAP4_MUXENTRY(KPD_COL2, 1, "kpd_col2", "kpd_col5", NULL, "gpio_1",
1158 NULL, NULL, NULL, "safe_mode"),
1159 _OMAP4_MUXENTRY(KPD_ROW3, 175, "kpd_row3", "kpd_row0", NULL,
1160 "gpio_175", NULL, NULL, NULL, "safe_mode"),
1161 _OMAP4_MUXENTRY(KPD_ROW4, 176, "kpd_row4", "kpd_row1", NULL,
1162 "gpio_176", NULL, NULL, NULL, "safe_mode"),
1163 _OMAP4_MUXENTRY(KPD_ROW5, 177, "kpd_row5", "kpd_row2", NULL,
1164 "gpio_177", NULL, NULL, NULL, "safe_mode"),
1165 _OMAP4_MUXENTRY(KPD_ROW0, 178, "kpd_row0", "kpd_row3", NULL,
1166 "gpio_178", NULL, NULL, NULL, "safe_mode"),
1167 _OMAP4_MUXENTRY(KPD_ROW1, 2, "kpd_row1", "kpd_row4", NULL, "gpio_2",
1168 NULL, NULL, NULL, "safe_mode"),
1169 _OMAP4_MUXENTRY(KPD_ROW2, 3, "kpd_row2", "kpd_row5", NULL, "gpio_3",
1170 NULL, NULL, NULL, "safe_mode"),
1171 _OMAP4_MUXENTRY(USBA0_OTG_CE, 0, "usba0_otg_ce", NULL, NULL, NULL,
1172 NULL, NULL, NULL, NULL),
1173 _OMAP4_MUXENTRY(USBA0_OTG_DP, 0, "usba0_otg_dp", "uart3_rx_irrx",
1174 "uart2_rx", NULL, NULL, NULL, NULL, "safe_mode"),
1175 _OMAP4_MUXENTRY(USBA0_OTG_DM, 0, "usba0_otg_dm", "uart3_tx_irtx",
1176 "uart2_tx", NULL, NULL, NULL, NULL, "safe_mode"),
1177 _OMAP4_MUXENTRY(FREF_CLK1_OUT, 181, "fref_clk1_out", NULL, NULL,
1178 "gpio_181", NULL, NULL, NULL, "safe_mode"),
1179 _OMAP4_MUXENTRY(FREF_CLK2_OUT, 182, "fref_clk2_out", NULL, NULL,
1180 "gpio_182", NULL, NULL, NULL, "safe_mode"),
1181 _OMAP4_MUXENTRY(SYS_NIRQ1, 0, "sys_nirq1", NULL, NULL, NULL, NULL,
1182 NULL, NULL, "safe_mode"),
1183 _OMAP4_MUXENTRY(SYS_NIRQ2, 183, "sys_nirq2", NULL, NULL, "gpio_183",
1184 NULL, NULL, NULL, "safe_mode"),
1185 _OMAP4_MUXENTRY(SYS_BOOT0, 184, "sys_boot0", NULL, NULL, "gpio_184",
1186 NULL, NULL, NULL, "safe_mode"),
1187 _OMAP4_MUXENTRY(SYS_BOOT1, 185, "sys_boot1", NULL, NULL, "gpio_185",
1188 NULL, NULL, NULL, "safe_mode"),
1189 _OMAP4_MUXENTRY(SYS_BOOT2, 186, "sys_boot2", NULL, NULL, "gpio_186",
1190 NULL, NULL, NULL, "safe_mode"),
1191 _OMAP4_MUXENTRY(SYS_BOOT3, 187, "sys_boot3", NULL, NULL, "gpio_187",
1192 NULL, NULL, NULL, "safe_mode"),
1193 _OMAP4_MUXENTRY(SYS_BOOT4, 188, "sys_boot4", NULL, NULL, "gpio_188",
1194 NULL, NULL, NULL, "safe_mode"),
1195 _OMAP4_MUXENTRY(SYS_BOOT5, 189, "sys_boot5", NULL, NULL, "gpio_189",
1196 NULL, NULL, NULL, "safe_mode"),
1197 _OMAP4_MUXENTRY(DPM_EMU0, 11, "dpm_emu0", NULL, NULL, "gpio_11", NULL,
1198 NULL, "hw_dbg0", "safe_mode"),
1199 _OMAP4_MUXENTRY(DPM_EMU1, 12, "dpm_emu1", NULL, NULL, "gpio_12", NULL,
1200 NULL, "hw_dbg1", "safe_mode"),
1201 _OMAP4_MUXENTRY(DPM_EMU2, 13, "dpm_emu2", "usba0_ulpiphy_clk", NULL,
1202 "gpio_13", NULL, "dispc2_fid", "hw_dbg2",
1203 "safe_mode"),
1204 _OMAP4_MUXENTRY(DPM_EMU3, 14, "dpm_emu3", "usba0_ulpiphy_stp", NULL,
1205 "gpio_14", "rfbi_data10", "dispc2_data10", "hw_dbg3",
1206 "safe_mode"),
1207 _OMAP4_MUXENTRY(DPM_EMU4, 15, "dpm_emu4", "usba0_ulpiphy_dir", NULL,
1208 "gpio_15", "rfbi_data9", "dispc2_data9", "hw_dbg4",
1209 "safe_mode"),
1210 _OMAP4_MUXENTRY(DPM_EMU5, 16, "dpm_emu5", "usba0_ulpiphy_nxt", NULL,
1211 "gpio_16", "rfbi_te_vsync0", "dispc2_data16",
1212 "hw_dbg5", "safe_mode"),
1213 _OMAP4_MUXENTRY(DPM_EMU6, 17, "dpm_emu6", "usba0_ulpiphy_dat0",
1214 "uart3_tx_irtx", "gpio_17", "rfbi_hsync0",
1215 "dispc2_data17", "hw_dbg6", "safe_mode"),
1216 _OMAP4_MUXENTRY(DPM_EMU7, 18, "dpm_emu7", "usba0_ulpiphy_dat1",
1217 "uart3_rx_irrx", "gpio_18", "rfbi_cs0",
1218 "dispc2_hsync", "hw_dbg7", "safe_mode"),
1219 _OMAP4_MUXENTRY(DPM_EMU8, 19, "dpm_emu8", "usba0_ulpiphy_dat2",
1220 "uart3_rts_sd", "gpio_19", "rfbi_re", "dispc2_pclk",
1221 "hw_dbg8", "safe_mode"),
1222 _OMAP4_MUXENTRY(DPM_EMU9, 20, "dpm_emu9", "usba0_ulpiphy_dat3",
1223 "uart3_cts_rctx", "gpio_20", "rfbi_we",
1224 "dispc2_vsync", "hw_dbg9", "safe_mode"),
1225 _OMAP4_MUXENTRY(DPM_EMU10, 21, "dpm_emu10", "usba0_ulpiphy_dat4",
1226 NULL, "gpio_21", "rfbi_a0", "dispc2_de", "hw_dbg10",
1227 "safe_mode"),
1228 _OMAP4_MUXENTRY(DPM_EMU11, 22, "dpm_emu11", "usba0_ulpiphy_dat5",
1229 NULL, "gpio_22", "rfbi_data8", "dispc2_data8",
1230 "hw_dbg11", "safe_mode"),
1231 _OMAP4_MUXENTRY(DPM_EMU12, 23, "dpm_emu12", "usba0_ulpiphy_dat6",
1232 NULL, "gpio_23", "rfbi_data7", "dispc2_data7",
1233 "hw_dbg12", "safe_mode"),
1234 _OMAP4_MUXENTRY(DPM_EMU13, 24, "dpm_emu13", "usba0_ulpiphy_dat7",
1235 NULL, "gpio_24", "rfbi_data6", "dispc2_data6",
1236 "hw_dbg13", "safe_mode"),
1237 _OMAP4_MUXENTRY(DPM_EMU14, 25, "dpm_emu14", "sys_drm_msecure",
1238 "uart1_rx", "gpio_25", "rfbi_data5", "dispc2_data5",
1239 "hw_dbg14", "safe_mode"),
1240 _OMAP4_MUXENTRY(DPM_EMU15, 26, "dpm_emu15", "sys_secure_indicator",
1241 NULL, "gpio_26", "rfbi_data4", "dispc2_data4",
1242 "hw_dbg15", "safe_mode"),
1243 _OMAP4_MUXENTRY(DPM_EMU16, 27, "dpm_emu16", "dmtimer8_pwm_evt",
1244 "dsi1_te0", "gpio_27", "rfbi_data3", "dispc2_data3",
1245 "hw_dbg16", "safe_mode"),
1246 _OMAP4_MUXENTRY(DPM_EMU17, 28, "dpm_emu17", "dmtimer9_pwm_evt",
1247 "dsi1_te1", "gpio_28", "rfbi_data2", "dispc2_data2",
1248 "hw_dbg17", "safe_mode"),
1249 _OMAP4_MUXENTRY(DPM_EMU18, 190, "dpm_emu18", "dmtimer10_pwm_evt",
1250 "dsi2_te0", "gpio_190", "rfbi_data1", "dispc2_data1",
1251 "hw_dbg18", "safe_mode"),
1252 _OMAP4_MUXENTRY(DPM_EMU19, 191, "dpm_emu19", "dmtimer11_pwm_evt",
1253 "dsi2_te1", "gpio_191", "rfbi_data0", "dispc2_data0",
1254 "hw_dbg19", "safe_mode"),
1255 { .reg_offset = OMAP_MUX_TERMINATOR },
1256};
1257
1258/*
1259 * Balls for 44XX CBS package
1260 * 547-pin CBL ES2.0 S-FPGA-N547, 0.40mm Ball Pitch (Top),
1261 * 0.40mm Ball Pitch (Bottom)
1262 */
1263#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \
1264 && defined(CONFIG_OMAP_PACKAGE_CBS)
1265struct omap_ball __initdata omap4_core_cbs_ball[] = {
1266 _OMAP4_BALLENTRY(GPMC_AD0, "c12", NULL),
1267 _OMAP4_BALLENTRY(GPMC_AD1, "d12", NULL),
1268 _OMAP4_BALLENTRY(GPMC_AD2, "c13", NULL),
1269 _OMAP4_BALLENTRY(GPMC_AD3, "d13", NULL),
1270 _OMAP4_BALLENTRY(GPMC_AD4, "c15", NULL),
1271 _OMAP4_BALLENTRY(GPMC_AD5, "d15", NULL),
1272 _OMAP4_BALLENTRY(GPMC_AD6, "a16", NULL),
1273 _OMAP4_BALLENTRY(GPMC_AD7, "b16", NULL),
1274 _OMAP4_BALLENTRY(GPMC_AD8, "c16", NULL),
1275 _OMAP4_BALLENTRY(GPMC_AD9, "d16", NULL),
1276 _OMAP4_BALLENTRY(GPMC_AD10, "c17", NULL),
1277 _OMAP4_BALLENTRY(GPMC_AD11, "d17", NULL),
1278 _OMAP4_BALLENTRY(GPMC_AD12, "c18", NULL),
1279 _OMAP4_BALLENTRY(GPMC_AD13, "d18", NULL),
1280 _OMAP4_BALLENTRY(GPMC_AD14, "c19", NULL),
1281 _OMAP4_BALLENTRY(GPMC_AD15, "d19", NULL),
1282 _OMAP4_BALLENTRY(GPMC_A16, "b17", NULL),
1283 _OMAP4_BALLENTRY(GPMC_A17, "a18", NULL),
1284 _OMAP4_BALLENTRY(GPMC_A18, "b18", NULL),
1285 _OMAP4_BALLENTRY(GPMC_A19, "a19", NULL),
1286 _OMAP4_BALLENTRY(GPMC_A20, "b19", NULL),
1287 _OMAP4_BALLENTRY(GPMC_A21, "b20", NULL),
1288 _OMAP4_BALLENTRY(GPMC_A22, "a21", NULL),
1289 _OMAP4_BALLENTRY(GPMC_A23, "b21", NULL),
1290 _OMAP4_BALLENTRY(GPMC_A24, "c20", NULL),
1291 _OMAP4_BALLENTRY(GPMC_A25, "d20", NULL),
1292 _OMAP4_BALLENTRY(GPMC_NCS0, "b25", NULL),
1293 _OMAP4_BALLENTRY(GPMC_NCS1, "c21", NULL),
1294 _OMAP4_BALLENTRY(GPMC_NCS2, "d21", NULL),
1295 _OMAP4_BALLENTRY(GPMC_NCS3, "c22", NULL),
1296 _OMAP4_BALLENTRY(GPMC_NWP, "c25", NULL),
1297 _OMAP4_BALLENTRY(GPMC_CLK, "b22", NULL),
1298 _OMAP4_BALLENTRY(GPMC_NADV_ALE, "d25", NULL),
1299 _OMAP4_BALLENTRY(GPMC_NOE, "b11", NULL),
1300 _OMAP4_BALLENTRY(GPMC_NWE, "b12", NULL),
1301 _OMAP4_BALLENTRY(GPMC_NBE0_CLE, "c23", NULL),
1302 _OMAP4_BALLENTRY(GPMC_NBE1, "d22", NULL),
1303 _OMAP4_BALLENTRY(GPMC_WAIT0, "b26", NULL),
1304 _OMAP4_BALLENTRY(GPMC_WAIT1, "b23", NULL),
1305 _OMAP4_BALLENTRY(GPMC_WAIT2, "d23", NULL),
1306 _OMAP4_BALLENTRY(GPMC_NCS4, "a24", NULL),
1307 _OMAP4_BALLENTRY(GPMC_NCS5, "b24", NULL),
1308 _OMAP4_BALLENTRY(GPMC_NCS6, "c24", NULL),
1309 _OMAP4_BALLENTRY(GPMC_NCS7, "d24", NULL),
1310 _OMAP4_BALLENTRY(HDMI_HPD, "b9", NULL),
1311 _OMAP4_BALLENTRY(HDMI_CEC, "b10", NULL),
1312 _OMAP4_BALLENTRY(HDMI_DDC_SCL, "a8", NULL),
1313 _OMAP4_BALLENTRY(HDMI_DDC_SDA, "b8", NULL),
1314 _OMAP4_BALLENTRY(CSI21_DX0, "r26", NULL),
1315 _OMAP4_BALLENTRY(CSI21_DY0, "r25", NULL),
1316 _OMAP4_BALLENTRY(CSI21_DX1, "t26", NULL),
1317 _OMAP4_BALLENTRY(CSI21_DY1, "t25", NULL),
1318 _OMAP4_BALLENTRY(CSI21_DX2, "u26", NULL),
1319 _OMAP4_BALLENTRY(CSI21_DY2, "u25", NULL),
1320 _OMAP4_BALLENTRY(CSI21_DX3, "v26", NULL),
1321 _OMAP4_BALLENTRY(CSI21_DY3, "v25", NULL),
1322 _OMAP4_BALLENTRY(CSI21_DX4, "w26", NULL),
1323 _OMAP4_BALLENTRY(CSI21_DY4, "w25", NULL),
1324 _OMAP4_BALLENTRY(CSI22_DX0, "m26", NULL),
1325 _OMAP4_BALLENTRY(CSI22_DY0, "m25", NULL),
1326 _OMAP4_BALLENTRY(CSI22_DX1, "n26", NULL),
1327 _OMAP4_BALLENTRY(CSI22_DY1, "n25", NULL),
1328 _OMAP4_BALLENTRY(CAM_SHUTTER, "t27", NULL),
1329 _OMAP4_BALLENTRY(CAM_STROBE, "u27", NULL),
1330 _OMAP4_BALLENTRY(CAM_GLOBALRESET, "v27", NULL),
1331 _OMAP4_BALLENTRY(USBB1_ULPITLL_CLK, "ae18", NULL),
1332 _OMAP4_BALLENTRY(USBB1_ULPITLL_STP, "ag19", NULL),
1333 _OMAP4_BALLENTRY(USBB1_ULPITLL_DIR, "af19", NULL),
1334 _OMAP4_BALLENTRY(USBB1_ULPITLL_NXT, "ae19", NULL),
1335 _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT0, "af18", NULL),
1336 _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT1, "ag18", NULL),
1337 _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT2, "ae17", NULL),
1338 _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT3, "af17", NULL),
1339 _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT4, "ah17", NULL),
1340 _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT5, "ae16", NULL),
1341 _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT6, "af16", NULL),
1342 _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT7, "ag16", NULL),
1343 _OMAP4_BALLENTRY(USBB1_HSIC_DATA, "af14", NULL),
1344 _OMAP4_BALLENTRY(USBB1_HSIC_STROBE, "ae14", NULL),
1345 _OMAP4_BALLENTRY(USBC1_ICUSB_DP, "h2", NULL),
1346 _OMAP4_BALLENTRY(USBC1_ICUSB_DM, "h3", NULL),
1347 _OMAP4_BALLENTRY(SDMMC1_CLK, "d2", NULL),
1348 _OMAP4_BALLENTRY(SDMMC1_CMD, "e3", NULL),
1349 _OMAP4_BALLENTRY(SDMMC1_DAT0, "e4", NULL),
1350 _OMAP4_BALLENTRY(SDMMC1_DAT1, "e2", NULL),
1351 _OMAP4_BALLENTRY(SDMMC1_DAT2, "e1", NULL),
1352 _OMAP4_BALLENTRY(SDMMC1_DAT3, "f4", NULL),
1353 _OMAP4_BALLENTRY(SDMMC1_DAT4, "f3", NULL),
1354 _OMAP4_BALLENTRY(SDMMC1_DAT5, "f1", NULL),
1355 _OMAP4_BALLENTRY(SDMMC1_DAT6, "g4", NULL),
1356 _OMAP4_BALLENTRY(SDMMC1_DAT7, "g3", NULL),
1357 _OMAP4_BALLENTRY(ABE_MCBSP2_CLKX, "ad27", NULL),
1358 _OMAP4_BALLENTRY(ABE_MCBSP2_DR, "ad26", NULL),
1359 _OMAP4_BALLENTRY(ABE_MCBSP2_DX, "ad25", NULL),
1360 _OMAP4_BALLENTRY(ABE_MCBSP2_FSX, "ac28", NULL),
1361 _OMAP4_BALLENTRY(ABE_MCBSP1_CLKX, "ac26", NULL),
1362 _OMAP4_BALLENTRY(ABE_MCBSP1_DR, "ac25", NULL),
1363 _OMAP4_BALLENTRY(ABE_MCBSP1_DX, "ab25", NULL),
1364 _OMAP4_BALLENTRY(ABE_MCBSP1_FSX, "ac27", NULL),
1365 _OMAP4_BALLENTRY(ABE_PDM_UL_DATA, "ag25", NULL),
1366 _OMAP4_BALLENTRY(ABE_PDM_DL_DATA, "af25", NULL),
1367 _OMAP4_BALLENTRY(ABE_PDM_FRAME, "ae25", NULL),
1368 _OMAP4_BALLENTRY(ABE_PDM_LB_CLK, "af26", NULL),
1369 _OMAP4_BALLENTRY(ABE_CLKS, "ah26", NULL),
1370 _OMAP4_BALLENTRY(ABE_DMIC_CLK1, "ae24", NULL),
1371 _OMAP4_BALLENTRY(ABE_DMIC_DIN1, "af24", NULL),
1372 _OMAP4_BALLENTRY(ABE_DMIC_DIN2, "ag24", NULL),
1373 _OMAP4_BALLENTRY(ABE_DMIC_DIN3, "ah24", NULL),
1374 _OMAP4_BALLENTRY(UART2_CTS, "ab26", NULL),
1375 _OMAP4_BALLENTRY(UART2_RTS, "ab27", NULL),
1376 _OMAP4_BALLENTRY(UART2_RX, "aa25", NULL),
1377 _OMAP4_BALLENTRY(UART2_TX, "aa26", NULL),
1378 _OMAP4_BALLENTRY(HDQ_SIO, "aa27", NULL),
1379 _OMAP4_BALLENTRY(I2C1_SCL, "ae28", NULL),
1380 _OMAP4_BALLENTRY(I2C1_SDA, "ae26", NULL),
1381 _OMAP4_BALLENTRY(I2C2_SCL, "c26", NULL),
1382 _OMAP4_BALLENTRY(I2C2_SDA, "d26", NULL),
1383 _OMAP4_BALLENTRY(I2C3_SCL, "w27", NULL),
1384 _OMAP4_BALLENTRY(I2C3_SDA, "y27", NULL),
1385 _OMAP4_BALLENTRY(I2C4_SCL, "ag21", NULL),
1386 _OMAP4_BALLENTRY(I2C4_SDA, "ah22", NULL),
1387 _OMAP4_BALLENTRY(MCSPI1_CLK, "af22", NULL),
1388 _OMAP4_BALLENTRY(MCSPI1_SOMI, "ae22", NULL),
1389 _OMAP4_BALLENTRY(MCSPI1_SIMO, "ag22", NULL),
1390 _OMAP4_BALLENTRY(MCSPI1_CS0, "ae23", NULL),
1391 _OMAP4_BALLENTRY(MCSPI1_CS1, "af23", NULL),
1392 _OMAP4_BALLENTRY(MCSPI1_CS2, "ag23", NULL),
1393 _OMAP4_BALLENTRY(MCSPI1_CS3, "ah23", NULL),
1394 _OMAP4_BALLENTRY(UART3_CTS_RCTX, "f27", NULL),
1395 _OMAP4_BALLENTRY(UART3_RTS_SD, "f28", NULL),
1396 _OMAP4_BALLENTRY(UART3_RX_IRRX, "g27", NULL),
1397 _OMAP4_BALLENTRY(UART3_TX_IRTX, "g28", NULL),
1398 _OMAP4_BALLENTRY(SDMMC5_CLK, "ae5", NULL),
1399 _OMAP4_BALLENTRY(SDMMC5_CMD, "af5", NULL),
1400 _OMAP4_BALLENTRY(SDMMC5_DAT0, "ae4", NULL),
1401 _OMAP4_BALLENTRY(SDMMC5_DAT1, "af4", NULL),
1402 _OMAP4_BALLENTRY(SDMMC5_DAT2, "ag3", NULL),
1403 _OMAP4_BALLENTRY(SDMMC5_DAT3, "af3", NULL),
1404 _OMAP4_BALLENTRY(MCSPI4_CLK, "ae21", NULL),
1405 _OMAP4_BALLENTRY(MCSPI4_SIMO, "af20", NULL),
1406 _OMAP4_BALLENTRY(MCSPI4_SOMI, "af21", NULL),
1407 _OMAP4_BALLENTRY(MCSPI4_CS0, "ae20", NULL),
1408 _OMAP4_BALLENTRY(UART4_RX, "ag20", NULL),
1409 _OMAP4_BALLENTRY(UART4_TX, "ah19", NULL),
1410 _OMAP4_BALLENTRY(USBB2_ULPITLL_CLK, "ag12", NULL),
1411 _OMAP4_BALLENTRY(USBB2_ULPITLL_STP, "af12", NULL),
1412 _OMAP4_BALLENTRY(USBB2_ULPITLL_DIR, "ae12", NULL),
1413 _OMAP4_BALLENTRY(USBB2_ULPITLL_NXT, "ag13", NULL),
1414 _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT0, "ae11", NULL),
1415 _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT1, "af11", NULL),
1416 _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT2, "ag11", NULL),
1417 _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT3, "ah11", NULL),
1418 _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT4, "ae10", NULL),
1419 _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT5, "af10", NULL),
1420 _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT6, "ag10", NULL),
1421 _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT7, "ae9", NULL),
1422 _OMAP4_BALLENTRY(USBB2_HSIC_DATA, "af13", NULL),
1423 _OMAP4_BALLENTRY(USBB2_HSIC_STROBE, "ae13", NULL),
1424 _OMAP4_BALLENTRY(KPD_COL3, "g26", NULL),
1425 _OMAP4_BALLENTRY(KPD_COL4, "g25", NULL),
1426 _OMAP4_BALLENTRY(KPD_COL5, "h26", NULL),
1427 _OMAP4_BALLENTRY(KPD_COL0, "h25", NULL),
1428 _OMAP4_BALLENTRY(KPD_COL1, "j27", NULL),
1429 _OMAP4_BALLENTRY(KPD_COL2, "h27", NULL),
1430 _OMAP4_BALLENTRY(KPD_ROW3, "j26", NULL),
1431 _OMAP4_BALLENTRY(KPD_ROW4, "j25", NULL),
1432 _OMAP4_BALLENTRY(KPD_ROW5, "k26", NULL),
1433 _OMAP4_BALLENTRY(KPD_ROW0, "k25", NULL),
1434 _OMAP4_BALLENTRY(KPD_ROW1, "l27", NULL),
1435 _OMAP4_BALLENTRY(KPD_ROW2, "k27", NULL),
1436 _OMAP4_BALLENTRY(USBA0_OTG_CE, "c3", NULL),
1437 _OMAP4_BALLENTRY(USBA0_OTG_DP, "b5", NULL),
1438 _OMAP4_BALLENTRY(USBA0_OTG_DM, "b4", NULL),
1439 _OMAP4_BALLENTRY(FREF_CLK1_OUT, "aa28", NULL),
1440 _OMAP4_BALLENTRY(FREF_CLK2_OUT, "y28", NULL),
1441 _OMAP4_BALLENTRY(SYS_NIRQ1, "ae6", NULL),
1442 _OMAP4_BALLENTRY(SYS_NIRQ2, "af6", NULL),
1443 _OMAP4_BALLENTRY(SYS_BOOT0, "f26", NULL),
1444 _OMAP4_BALLENTRY(SYS_BOOT1, "e27", NULL),
1445 _OMAP4_BALLENTRY(SYS_BOOT2, "e26", NULL),
1446 _OMAP4_BALLENTRY(SYS_BOOT3, "e25", NULL),
1447 _OMAP4_BALLENTRY(SYS_BOOT4, "d28", NULL),
1448 _OMAP4_BALLENTRY(SYS_BOOT5, "d27", NULL),
1449 _OMAP4_BALLENTRY(DPM_EMU0, "m2", NULL),
1450 _OMAP4_BALLENTRY(DPM_EMU1, "n2", NULL),
1451 _OMAP4_BALLENTRY(DPM_EMU2, "p2", NULL),
1452 _OMAP4_BALLENTRY(DPM_EMU3, "v1", NULL),
1453 _OMAP4_BALLENTRY(DPM_EMU4, "v2", NULL),
1454 _OMAP4_BALLENTRY(DPM_EMU5, "w1", NULL),
1455 _OMAP4_BALLENTRY(DPM_EMU6, "w2", NULL),
1456 _OMAP4_BALLENTRY(DPM_EMU7, "w3", NULL),
1457 _OMAP4_BALLENTRY(DPM_EMU8, "w4", NULL),
1458 _OMAP4_BALLENTRY(DPM_EMU9, "y2", NULL),
1459 _OMAP4_BALLENTRY(DPM_EMU10, "y3", NULL),
1460 _OMAP4_BALLENTRY(DPM_EMU11, "y4", NULL),
1461 _OMAP4_BALLENTRY(DPM_EMU12, "aa1", NULL),
1462 _OMAP4_BALLENTRY(DPM_EMU13, "aa2", NULL),
1463 _OMAP4_BALLENTRY(DPM_EMU14, "aa3", NULL),
1464 _OMAP4_BALLENTRY(DPM_EMU15, "aa4", NULL),
1465 _OMAP4_BALLENTRY(DPM_EMU16, "ab2", NULL),
1466 _OMAP4_BALLENTRY(DPM_EMU17, "ab3", NULL),
1467 _OMAP4_BALLENTRY(DPM_EMU18, "ab4", NULL),
1468 _OMAP4_BALLENTRY(DPM_EMU19, "ac4", NULL),
1469 { .reg_offset = OMAP_MUX_TERMINATOR },
1470};
1471#else
1472#define omap4_core_cbs_ball NULL
1473#endif
1474
1475/*
1476 * Superset of all mux modes for omap4
1477 */
1478static struct omap_mux __initdata omap4_wkup_muxmodes[] = {
1479 _OMAP4_MUXENTRY(SIM_IO, 0, "sim_io", NULL, NULL, "gpio_wk0", NULL,
1480 NULL, NULL, "safe_mode"),
1481 _OMAP4_MUXENTRY(SIM_CLK, 1, "sim_clk", NULL, NULL, "gpio_wk1", NULL,
1482 NULL, NULL, "safe_mode"),
1483 _OMAP4_MUXENTRY(SIM_RESET, 2, "sim_reset", NULL, NULL, "gpio_wk2",
1484 NULL, NULL, NULL, "safe_mode"),
1485 _OMAP4_MUXENTRY(SIM_CD, 3, "sim_cd", NULL, NULL, "gpio_wk3", NULL,
1486 NULL, NULL, "safe_mode"),
1487 _OMAP4_MUXENTRY(SIM_PWRCTRL, 4, "sim_pwrctrl", NULL, NULL, "gpio_wk4",
1488 NULL, NULL, NULL, "safe_mode"),
1489 _OMAP4_MUXENTRY(SR_SCL, 0, "sr_scl", NULL, NULL, NULL, NULL, NULL,
1490 NULL, NULL),
1491 _OMAP4_MUXENTRY(SR_SDA, 0, "sr_sda", NULL, NULL, NULL, NULL, NULL,
1492 NULL, NULL),
1493 _OMAP4_MUXENTRY(FREF_XTAL_IN, 0, "fref_xtal_in", NULL, NULL, NULL,
1494 "c2c_wakereqin", NULL, NULL, NULL),
1495 _OMAP4_MUXENTRY(FREF_SLICER_IN, 0, "fref_slicer_in", NULL, NULL,
1496 "gpi_wk5", "c2c_wakereqin", NULL, NULL, "safe_mode"),
1497 _OMAP4_MUXENTRY(FREF_CLK_IOREQ, 0, "fref_clk_ioreq", NULL, NULL, NULL,
1498 NULL, NULL, NULL, NULL),
1499 _OMAP4_MUXENTRY(FREF_CLK0_OUT, 6, "fref_clk0_out", "fref_clk1_req",
1500 "sys_drm_msecure", "gpio_wk6", NULL, NULL, NULL,
1501 "safe_mode"),
1502 _OMAP4_MUXENTRY(FREF_CLK3_REQ, 30, "fref_clk3_req", "fref_clk1_req",
1503 "sys_drm_msecure", "gpio_wk30", "c2c_wakereqin", NULL,
1504 NULL, "safe_mode"),
1505 _OMAP4_MUXENTRY(FREF_CLK3_OUT, 31, "fref_clk3_out", "fref_clk2_req",
1506 "sys_secure_indicator", "gpio_wk31", "c2c_wakereqout",
1507 NULL, NULL, "safe_mode"),
1508 _OMAP4_MUXENTRY(FREF_CLK4_REQ, 7, "fref_clk4_req", "fref_clk5_out",
1509 NULL, "gpio_wk7", NULL, NULL, NULL, NULL),
1510 _OMAP4_MUXENTRY(FREF_CLK4_OUT, 8, "fref_clk4_out", NULL, NULL,
1511 "gpio_wk8", NULL, NULL, NULL, NULL),
1512 _OMAP4_MUXENTRY(SYS_32K, 0, "sys_32k", NULL, NULL, NULL, NULL, NULL,
1513 NULL, NULL),
1514 _OMAP4_MUXENTRY(SYS_NRESPWRON, 0, "sys_nrespwron", NULL, NULL, NULL,
1515 NULL, NULL, NULL, NULL),
1516 _OMAP4_MUXENTRY(SYS_NRESWARM, 0, "sys_nreswarm", NULL, NULL, NULL,
1517 NULL, NULL, NULL, NULL),
1518 _OMAP4_MUXENTRY(SYS_PWR_REQ, 0, "sys_pwr_req", NULL, NULL, NULL, NULL,
1519 NULL, NULL, NULL),
1520 _OMAP4_MUXENTRY(SYS_PWRON_RESET_OUT, 29, "sys_pwron_reset_out", NULL,
1521 NULL, "gpio_wk29", NULL, NULL, NULL, NULL),
1522 _OMAP4_MUXENTRY(SYS_BOOT6, 9, "sys_boot6", "dpm_emu18", NULL,
1523 "gpio_wk9", "c2c_wakereqout", NULL, NULL,
1524 "safe_mode"),
1525 _OMAP4_MUXENTRY(SYS_BOOT7, 10, "sys_boot7", "dpm_emu19", NULL,
1526 "gpio_wk10", NULL, NULL, NULL, "safe_mode"),
1527 _OMAP4_MUXENTRY(JTAG_NTRST, 0, "jtag_ntrst", NULL, NULL, NULL, NULL,
1528 NULL, NULL, NULL),
1529 _OMAP4_MUXENTRY(JTAG_TCK, 0, "jtag_tck", NULL, NULL, NULL, NULL, NULL,
1530 NULL, "safe_mode"),
1531 _OMAP4_MUXENTRY(JTAG_RTCK, 0, "jtag_rtck", NULL, NULL, NULL, NULL,
1532 NULL, NULL, NULL),
1533 _OMAP4_MUXENTRY(JTAG_TMS_TMSC, 0, "jtag_tms_tmsc", NULL, NULL, NULL,
1534 NULL, NULL, NULL, "safe_mode"),
1535 _OMAP4_MUXENTRY(JTAG_TDI, 0, "jtag_tdi", NULL, NULL, NULL, NULL, NULL,
1536 NULL, NULL),
1537 _OMAP4_MUXENTRY(JTAG_TDO, 0, "jtag_tdo", NULL, NULL, NULL, NULL, NULL,
1538 NULL, NULL),
1539 { .reg_offset = OMAP_MUX_TERMINATOR },
1540};
1541
1542/*
1543 * Balls for 44XX CBL & CBS package - wakeup partition
1544 * 547-pin CBL ES1.0 S-FPGA-N547, 0.40mm Ball Pitch (Top),
1545 * 0.40mm Ball Pitch (Bottom)
1546 */
1547#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \
1548 && defined(CONFIG_OMAP_PACKAGE_CBL)
1549struct omap_ball __initdata omap4_wkup_cbl_cbs_ball[] = {
1550 _OMAP4_BALLENTRY(SIM_IO, "h4", NULL),
1551 _OMAP4_BALLENTRY(SIM_CLK, "j2", NULL),
1552 _OMAP4_BALLENTRY(SIM_RESET, "g2", NULL),
1553 _OMAP4_BALLENTRY(SIM_CD, "j1", NULL),
1554 _OMAP4_BALLENTRY(SIM_PWRCTRL, "k1", NULL),
1555 _OMAP4_BALLENTRY(SR_SCL, "ag9", NULL),
1556 _OMAP4_BALLENTRY(SR_SDA, "af9", NULL),
1557 _OMAP4_BALLENTRY(FREF_XTAL_IN, "ah6", NULL),
1558 _OMAP4_BALLENTRY(FREF_SLICER_IN, "ag8", NULL),
1559 _OMAP4_BALLENTRY(FREF_CLK_IOREQ, "ad1", NULL),
1560 _OMAP4_BALLENTRY(FREF_CLK0_OUT, "ad2", NULL),
1561 _OMAP4_BALLENTRY(FREF_CLK3_REQ, "ad3", NULL),
1562 _OMAP4_BALLENTRY(FREF_CLK3_OUT, "ad4", NULL),
1563 _OMAP4_BALLENTRY(FREF_CLK4_REQ, "ac2", NULL),
1564 _OMAP4_BALLENTRY(FREF_CLK4_OUT, "ac3", NULL),
1565 _OMAP4_BALLENTRY(SYS_32K, "ag7", NULL),
1566 _OMAP4_BALLENTRY(SYS_NRESPWRON, "ae7", NULL),
1567 _OMAP4_BALLENTRY(SYS_NRESWARM, "af7", NULL),
1568 _OMAP4_BALLENTRY(SYS_PWR_REQ, "ah7", NULL),
1569 _OMAP4_BALLENTRY(SYS_PWRON_RESET_OUT, "ag6", NULL),
1570 _OMAP4_BALLENTRY(SYS_BOOT6, "af8", NULL),
1571 _OMAP4_BALLENTRY(SYS_BOOT7, "ae8", NULL),
1572 _OMAP4_BALLENTRY(JTAG_NTRST, "ah2", NULL),
1573 _OMAP4_BALLENTRY(JTAG_TCK, "ag1", NULL),
1574 _OMAP4_BALLENTRY(JTAG_RTCK, "ae3", NULL),
1575 _OMAP4_BALLENTRY(JTAG_TMS_TMSC, "ah1", NULL),
1576 _OMAP4_BALLENTRY(JTAG_TDI, "ae1", NULL),
1577 _OMAP4_BALLENTRY(JTAG_TDO, "ae2", NULL),
1578 { .reg_offset = OMAP_MUX_TERMINATOR },
1579};
1580#else
1581#define omap4_wkup_cbl_cbs_ball NULL
1582#endif
1583
1584int __init omap4_mux_init(struct omap_board_mux *board_subset, int flags)
1585{
1586 struct omap_ball *package_balls_core;
1587 struct omap_ball *package_balls_wkup = omap4_wkup_cbl_cbs_ball;
1588 struct omap_mux *core_muxmodes;
1589 int ret;
1590
1591 switch (flags & OMAP_PACKAGE_MASK) {
1592 case OMAP_PACKAGE_CBL:
1593 pr_debug("%s: OMAP4430 ES1.0 -> OMAP_PACKAGE_CBL\n", __func__);
1594 package_balls_core = omap4_core_cbl_ball;
1595 core_muxmodes = omap4_core_muxmodes;
1596 break;
1597 case OMAP_PACKAGE_CBS:
1598 pr_debug("%s: OMAP4430 ES2.X -> OMAP_PACKAGE_CBS\n", __func__);
1599 package_balls_core = omap4_core_cbs_ball;
1600 core_muxmodes = omap4_es2_core_muxmodes;
1601 break;
1602 default:
1603 pr_err("%s: Unknown omap package, mux disabled\n", __func__);
1604 return -EINVAL;
1605 }
1606
1607 ret = omap_mux_init("core",
1608 OMAP_MUX_GPIO_IN_MODE3,
1609 OMAP4_CTRL_MODULE_PAD_CORE_MUX_PBASE,
1610 OMAP4_CTRL_MODULE_PAD_CORE_MUX_SIZE,
1611 core_muxmodes, NULL, board_subset,
1612 package_balls_core);
1613 if (ret)
1614 return ret;
1615
1616 ret = omap_mux_init("wkup",
1617 OMAP_MUX_GPIO_IN_MODE3,
1618 OMAP4_CTRL_MODULE_PAD_WKUP_MUX_PBASE,
1619 OMAP4_CTRL_MODULE_PAD_WKUP_MUX_SIZE,
1620 omap4_wkup_muxmodes, NULL, board_subset,
1621 package_balls_wkup);
1622
1623 return ret;
1624}
1625
diff --git a/arch/arm/mach-omap2/mux44xx.h b/arch/arm/mach-omap2/mux44xx.h
new file mode 100644
index 000000000000..c635026cd7e9
--- /dev/null
+++ b/arch/arm/mach-omap2/mux44xx.h
@@ -0,0 +1,298 @@
1/*
2 * OMAP44xx MUX registers and bitfields
3 *
4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
5 *
6 * Benoit Cousson (b-cousson@ti.com)
7 *
8 * This file is automatically generated from the OMAP hardware databases.
9 * We respectfully ask that any modifications to this file be coordinated
10 * with the public linux-omap@vger.kernel.org mailing list and the
11 * authors above to ensure that the autogeneration scripts are kept
12 * up-to-date with the file contents.
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18
19#ifndef __ARCH_ARM_MACH_OMAP2_MUX_44XX_H
20#define __ARCH_ARM_MACH_OMAP2_MUX_44XX_H
21
22#define OMAP4_MUX(M0, mux_value) \
23{ \
24 .reg_offset = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET), \
25 .value = (mux_value), \
26}
27
28/* ctrl_module_pad_core base address */
29#define OMAP4_CTRL_MODULE_PAD_CORE_MUX_PBASE 0x4a100000
30
31/* ctrl_module_pad_core registers offset */
32#define OMAP4_CTRL_MODULE_PAD_GPMC_AD0_OFFSET 0x0040
33#define OMAP4_CTRL_MODULE_PAD_GPMC_AD1_OFFSET 0x0042
34#define OMAP4_CTRL_MODULE_PAD_GPMC_AD2_OFFSET 0x0044
35#define OMAP4_CTRL_MODULE_PAD_GPMC_AD3_OFFSET 0x0046
36#define OMAP4_CTRL_MODULE_PAD_GPMC_AD4_OFFSET 0x0048
37#define OMAP4_CTRL_MODULE_PAD_GPMC_AD5_OFFSET 0x004a
38#define OMAP4_CTRL_MODULE_PAD_GPMC_AD6_OFFSET 0x004c
39#define OMAP4_CTRL_MODULE_PAD_GPMC_AD7_OFFSET 0x004e
40#define OMAP4_CTRL_MODULE_PAD_GPMC_AD8_OFFSET 0x0050
41#define OMAP4_CTRL_MODULE_PAD_GPMC_AD9_OFFSET 0x0052
42#define OMAP4_CTRL_MODULE_PAD_GPMC_AD10_OFFSET 0x0054
43#define OMAP4_CTRL_MODULE_PAD_GPMC_AD11_OFFSET 0x0056
44#define OMAP4_CTRL_MODULE_PAD_GPMC_AD12_OFFSET 0x0058
45#define OMAP4_CTRL_MODULE_PAD_GPMC_AD13_OFFSET 0x005a
46#define OMAP4_CTRL_MODULE_PAD_GPMC_AD14_OFFSET 0x005c
47#define OMAP4_CTRL_MODULE_PAD_GPMC_AD15_OFFSET 0x005e
48#define OMAP4_CTRL_MODULE_PAD_GPMC_A16_OFFSET 0x0060
49#define OMAP4_CTRL_MODULE_PAD_GPMC_A17_OFFSET 0x0062
50#define OMAP4_CTRL_MODULE_PAD_GPMC_A18_OFFSET 0x0064
51#define OMAP4_CTRL_MODULE_PAD_GPMC_A19_OFFSET 0x0066
52#define OMAP4_CTRL_MODULE_PAD_GPMC_A20_OFFSET 0x0068
53#define OMAP4_CTRL_MODULE_PAD_GPMC_A21_OFFSET 0x006a
54#define OMAP4_CTRL_MODULE_PAD_GPMC_A22_OFFSET 0x006c
55#define OMAP4_CTRL_MODULE_PAD_GPMC_A23_OFFSET 0x006e
56#define OMAP4_CTRL_MODULE_PAD_GPMC_A24_OFFSET 0x0070
57#define OMAP4_CTRL_MODULE_PAD_GPMC_A25_OFFSET 0x0072
58#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS0_OFFSET 0x0074
59#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS1_OFFSET 0x0076
60#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS2_OFFSET 0x0078
61#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS3_OFFSET 0x007a
62#define OMAP4_CTRL_MODULE_PAD_GPMC_NWP_OFFSET 0x007c
63#define OMAP4_CTRL_MODULE_PAD_GPMC_CLK_OFFSET 0x007e
64#define OMAP4_CTRL_MODULE_PAD_GPMC_NADV_ALE_OFFSET 0x0080
65#define OMAP4_CTRL_MODULE_PAD_GPMC_NOE_OFFSET 0x0082
66#define OMAP4_CTRL_MODULE_PAD_GPMC_NWE_OFFSET 0x0084
67#define OMAP4_CTRL_MODULE_PAD_GPMC_NBE0_CLE_OFFSET 0x0086
68#define OMAP4_CTRL_MODULE_PAD_GPMC_NBE1_OFFSET 0x0088
69#define OMAP4_CTRL_MODULE_PAD_GPMC_WAIT0_OFFSET 0x008a
70#define OMAP4_CTRL_MODULE_PAD_GPMC_WAIT1_OFFSET 0x008c
71#define OMAP4_CTRL_MODULE_PAD_C2C_DATA11_OFFSET 0x008e
72#define OMAP4_CTRL_MODULE_PAD_C2C_DATA12_OFFSET 0x0090
73#define OMAP4_CTRL_MODULE_PAD_C2C_DATA13_OFFSET 0x0092
74#define OMAP4_CTRL_MODULE_PAD_C2C_DATA14_OFFSET 0x0094
75#define OMAP4_CTRL_MODULE_PAD_C2C_DATA15_OFFSET 0x0096
76#define OMAP4_CTRL_MODULE_PAD_HDMI_HPD_OFFSET 0x0098
77#define OMAP4_CTRL_MODULE_PAD_HDMI_CEC_OFFSET 0x009a
78#define OMAP4_CTRL_MODULE_PAD_HDMI_DDC_SCL_OFFSET 0x009c
79#define OMAP4_CTRL_MODULE_PAD_HDMI_DDC_SDA_OFFSET 0x009e
80#define OMAP4_CTRL_MODULE_PAD_CSI21_DX0_OFFSET 0x00a0
81#define OMAP4_CTRL_MODULE_PAD_CSI21_DY0_OFFSET 0x00a2
82#define OMAP4_CTRL_MODULE_PAD_CSI21_DX1_OFFSET 0x00a4
83#define OMAP4_CTRL_MODULE_PAD_CSI21_DY1_OFFSET 0x00a6
84#define OMAP4_CTRL_MODULE_PAD_CSI21_DX2_OFFSET 0x00a8
85#define OMAP4_CTRL_MODULE_PAD_CSI21_DY2_OFFSET 0x00aa
86#define OMAP4_CTRL_MODULE_PAD_CSI21_DX3_OFFSET 0x00ac
87#define OMAP4_CTRL_MODULE_PAD_CSI21_DY3_OFFSET 0x00ae
88#define OMAP4_CTRL_MODULE_PAD_CSI21_DX4_OFFSET 0x00b0
89#define OMAP4_CTRL_MODULE_PAD_CSI21_DY4_OFFSET 0x00b2
90#define OMAP4_CTRL_MODULE_PAD_CSI22_DX0_OFFSET 0x00b4
91#define OMAP4_CTRL_MODULE_PAD_CSI22_DY0_OFFSET 0x00b6
92#define OMAP4_CTRL_MODULE_PAD_CSI22_DX1_OFFSET 0x00b8
93#define OMAP4_CTRL_MODULE_PAD_CSI22_DY1_OFFSET 0x00ba
94#define OMAP4_CTRL_MODULE_PAD_CAM_SHUTTER_OFFSET 0x00bc
95#define OMAP4_CTRL_MODULE_PAD_CAM_STROBE_OFFSET 0x00be
96#define OMAP4_CTRL_MODULE_PAD_CAM_GLOBALRESET_OFFSET 0x00c0
97#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_CLK_OFFSET 0x00c2
98#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_STP_OFFSET 0x00c4
99#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DIR_OFFSET 0x00c6
100#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_NXT_OFFSET 0x00c8
101#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT0_OFFSET 0x00ca
102#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT1_OFFSET 0x00cc
103#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT2_OFFSET 0x00ce
104#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT3_OFFSET 0x00d0
105#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT4_OFFSET 0x00d2
106#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT5_OFFSET 0x00d4
107#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT6_OFFSET 0x00d6
108#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT7_OFFSET 0x00d8
109#define OMAP4_CTRL_MODULE_PAD_USBB1_HSIC_DATA_OFFSET 0x00da
110#define OMAP4_CTRL_MODULE_PAD_USBB1_HSIC_STROBE_OFFSET 0x00dc
111#define OMAP4_CTRL_MODULE_PAD_USBC1_ICUSB_DP_OFFSET 0x00de
112#define OMAP4_CTRL_MODULE_PAD_USBC1_ICUSB_DM_OFFSET 0x00e0
113#define OMAP4_CTRL_MODULE_PAD_SDMMC1_CLK_OFFSET 0x00e2
114#define OMAP4_CTRL_MODULE_PAD_SDMMC1_CMD_OFFSET 0x00e4
115#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT0_OFFSET 0x00e6
116#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT1_OFFSET 0x00e8
117#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT2_OFFSET 0x00ea
118#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT3_OFFSET 0x00ec
119#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT4_OFFSET 0x00ee
120#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT5_OFFSET 0x00f0
121#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT6_OFFSET 0x00f2
122#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT7_OFFSET 0x00f4
123#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_CLKX_OFFSET 0x00f6
124#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_DR_OFFSET 0x00f8
125#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_DX_OFFSET 0x00fa
126#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_FSX_OFFSET 0x00fc
127#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_CLKX_OFFSET 0x00fe
128#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_DR_OFFSET 0x0100
129#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_DX_OFFSET 0x0102
130#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_FSX_OFFSET 0x0104
131#define OMAP4_CTRL_MODULE_PAD_ABE_PDM_UL_DATA_OFFSET 0x0106
132#define OMAP4_CTRL_MODULE_PAD_ABE_PDM_DL_DATA_OFFSET 0x0108
133#define OMAP4_CTRL_MODULE_PAD_ABE_PDM_FRAME_OFFSET 0x010a
134#define OMAP4_CTRL_MODULE_PAD_ABE_PDM_LB_CLK_OFFSET 0x010c
135#define OMAP4_CTRL_MODULE_PAD_ABE_CLKS_OFFSET 0x010e
136#define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_CLK1_OFFSET 0x0110
137#define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_DIN1_OFFSET 0x0112
138#define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_DIN2_OFFSET 0x0114
139#define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_DIN3_OFFSET 0x0116
140#define OMAP4_CTRL_MODULE_PAD_UART2_CTS_OFFSET 0x0118
141#define OMAP4_CTRL_MODULE_PAD_UART2_RTS_OFFSET 0x011a
142#define OMAP4_CTRL_MODULE_PAD_UART2_RX_OFFSET 0x011c
143#define OMAP4_CTRL_MODULE_PAD_UART2_TX_OFFSET 0x011e
144#define OMAP4_CTRL_MODULE_PAD_HDQ_SIO_OFFSET 0x0120
145#define OMAP4_CTRL_MODULE_PAD_I2C1_SCL_OFFSET 0x0122
146#define OMAP4_CTRL_MODULE_PAD_I2C1_SDA_OFFSET 0x0124
147#define OMAP4_CTRL_MODULE_PAD_I2C2_SCL_OFFSET 0x0126
148#define OMAP4_CTRL_MODULE_PAD_I2C2_SDA_OFFSET 0x0128
149#define OMAP4_CTRL_MODULE_PAD_I2C3_SCL_OFFSET 0x012a
150#define OMAP4_CTRL_MODULE_PAD_I2C3_SDA_OFFSET 0x012c
151#define OMAP4_CTRL_MODULE_PAD_I2C4_SCL_OFFSET 0x012e
152#define OMAP4_CTRL_MODULE_PAD_I2C4_SDA_OFFSET 0x0130
153#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CLK_OFFSET 0x0132
154#define OMAP4_CTRL_MODULE_PAD_MCSPI1_SOMI_OFFSET 0x0134
155#define OMAP4_CTRL_MODULE_PAD_MCSPI1_SIMO_OFFSET 0x0136
156#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS0_OFFSET 0x0138
157#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS1_OFFSET 0x013a
158#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS2_OFFSET 0x013c
159#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS3_OFFSET 0x013e
160#define OMAP4_CTRL_MODULE_PAD_UART3_CTS_RCTX_OFFSET 0x0140
161#define OMAP4_CTRL_MODULE_PAD_UART3_RTS_SD_OFFSET 0x0142
162#define OMAP4_CTRL_MODULE_PAD_UART3_RX_IRRX_OFFSET 0x0144
163#define OMAP4_CTRL_MODULE_PAD_UART3_TX_IRTX_OFFSET 0x0146
164#define OMAP4_CTRL_MODULE_PAD_SDMMC5_CLK_OFFSET 0x0148
165#define OMAP4_CTRL_MODULE_PAD_SDMMC5_CMD_OFFSET 0x014a
166#define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT0_OFFSET 0x014c
167#define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT1_OFFSET 0x014e
168#define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT2_OFFSET 0x0150
169#define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT3_OFFSET 0x0152
170#define OMAP4_CTRL_MODULE_PAD_MCSPI4_CLK_OFFSET 0x0154
171#define OMAP4_CTRL_MODULE_PAD_MCSPI4_SIMO_OFFSET 0x0156
172#define OMAP4_CTRL_MODULE_PAD_MCSPI4_SOMI_OFFSET 0x0158
173#define OMAP4_CTRL_MODULE_PAD_MCSPI4_CS0_OFFSET 0x015a
174#define OMAP4_CTRL_MODULE_PAD_UART4_RX_OFFSET 0x015c
175#define OMAP4_CTRL_MODULE_PAD_UART4_TX_OFFSET 0x015e
176#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_CLK_OFFSET 0x0160
177#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_STP_OFFSET 0x0162
178#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DIR_OFFSET 0x0164
179#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_NXT_OFFSET 0x0166
180#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT0_OFFSET 0x0168
181#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT1_OFFSET 0x016a
182#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT2_OFFSET 0x016c
183#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT3_OFFSET 0x016e
184#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT4_OFFSET 0x0170
185#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT5_OFFSET 0x0172
186#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT6_OFFSET 0x0174
187#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT7_OFFSET 0x0176
188#define OMAP4_CTRL_MODULE_PAD_USBB2_HSIC_DATA_OFFSET 0x0178
189#define OMAP4_CTRL_MODULE_PAD_USBB2_HSIC_STROBE_OFFSET 0x017a
190#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TX0_OFFSET 0x017c
191#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TY0_OFFSET 0x017e
192#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TX1_OFFSET 0x0180
193#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TY1_OFFSET 0x0182
194#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TX2_OFFSET 0x0184
195#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TY2_OFFSET 0x0186
196#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RX0_OFFSET 0x0188
197#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RY0_OFFSET 0x018a
198#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RX1_OFFSET 0x018c
199#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RY1_OFFSET 0x018e
200#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RX2_OFFSET 0x0190
201#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RY2_OFFSET 0x0192
202#define OMAP4_CTRL_MODULE_PAD_USBA0_OTG_CE_OFFSET 0x0194
203#define OMAP4_CTRL_MODULE_PAD_USBA0_OTG_DP_OFFSET 0x0196
204#define OMAP4_CTRL_MODULE_PAD_USBA0_OTG_DM_OFFSET 0x0198
205#define OMAP4_CTRL_MODULE_PAD_FREF_CLK1_OUT_OFFSET 0x019a
206#define OMAP4_CTRL_MODULE_PAD_FREF_CLK2_OUT_OFFSET 0x019c
207#define OMAP4_CTRL_MODULE_PAD_SYS_NIRQ1_OFFSET 0x019e
208#define OMAP4_CTRL_MODULE_PAD_SYS_NIRQ2_OFFSET 0x01a0
209#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT0_OFFSET 0x01a2
210#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT1_OFFSET 0x01a4
211#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT2_OFFSET 0x01a6
212#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT3_OFFSET 0x01a8
213#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT4_OFFSET 0x01aa
214#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT5_OFFSET 0x01ac
215#define OMAP4_CTRL_MODULE_PAD_DPM_EMU0_OFFSET 0x01ae
216#define OMAP4_CTRL_MODULE_PAD_DPM_EMU1_OFFSET 0x01b0
217#define OMAP4_CTRL_MODULE_PAD_DPM_EMU2_OFFSET 0x01b2
218#define OMAP4_CTRL_MODULE_PAD_DPM_EMU3_OFFSET 0x01b4
219#define OMAP4_CTRL_MODULE_PAD_DPM_EMU4_OFFSET 0x01b6
220#define OMAP4_CTRL_MODULE_PAD_DPM_EMU5_OFFSET 0x01b8
221#define OMAP4_CTRL_MODULE_PAD_DPM_EMU6_OFFSET 0x01ba
222#define OMAP4_CTRL_MODULE_PAD_DPM_EMU7_OFFSET 0x01bc
223#define OMAP4_CTRL_MODULE_PAD_DPM_EMU8_OFFSET 0x01be
224#define OMAP4_CTRL_MODULE_PAD_DPM_EMU9_OFFSET 0x01c0
225#define OMAP4_CTRL_MODULE_PAD_DPM_EMU10_OFFSET 0x01c2
226#define OMAP4_CTRL_MODULE_PAD_DPM_EMU11_OFFSET 0x01c4
227#define OMAP4_CTRL_MODULE_PAD_DPM_EMU12_OFFSET 0x01c6
228#define OMAP4_CTRL_MODULE_PAD_DPM_EMU13_OFFSET 0x01c8
229#define OMAP4_CTRL_MODULE_PAD_DPM_EMU14_OFFSET 0x01ca
230#define OMAP4_CTRL_MODULE_PAD_DPM_EMU15_OFFSET 0x01cc
231#define OMAP4_CTRL_MODULE_PAD_DPM_EMU16_OFFSET 0x01ce
232#define OMAP4_CTRL_MODULE_PAD_DPM_EMU17_OFFSET 0x01d0
233#define OMAP4_CTRL_MODULE_PAD_DPM_EMU18_OFFSET 0x01d2
234#define OMAP4_CTRL_MODULE_PAD_DPM_EMU19_OFFSET 0x01d4
235
236/* ES2.0 only */
237#define OMAP4_CTRL_MODULE_PAD_GPMC_WAIT2_OFFSET 0x008e
238#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS4_OFFSET 0x0090
239#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS5_OFFSET 0x0092
240#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS6_OFFSET 0x0094
241#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS7_OFFSET 0x0096
242
243#define OMAP4_CTRL_MODULE_PAD_KPD_COL3_OFFSET 0x017c
244#define OMAP4_CTRL_MODULE_PAD_KPD_COL4_OFFSET 0x017e
245#define OMAP4_CTRL_MODULE_PAD_KPD_COL5_OFFSET 0x0180
246#define OMAP4_CTRL_MODULE_PAD_KPD_COL0_OFFSET 0x0182
247#define OMAP4_CTRL_MODULE_PAD_KPD_COL1_OFFSET 0x0184
248#define OMAP4_CTRL_MODULE_PAD_KPD_COL2_OFFSET 0x0186
249#define OMAP4_CTRL_MODULE_PAD_KPD_ROW3_OFFSET 0x0188
250#define OMAP4_CTRL_MODULE_PAD_KPD_ROW4_OFFSET 0x018a
251#define OMAP4_CTRL_MODULE_PAD_KPD_ROW5_OFFSET 0x018c
252#define OMAP4_CTRL_MODULE_PAD_KPD_ROW0_OFFSET 0x018e
253#define OMAP4_CTRL_MODULE_PAD_KPD_ROW1_OFFSET 0x0190
254#define OMAP4_CTRL_MODULE_PAD_KPD_ROW2_OFFSET 0x0192
255
256
257#define OMAP4_CTRL_MODULE_PAD_CORE_MUX_SIZE \
258 (OMAP4_CTRL_MODULE_PAD_DPM_EMU19_OFFSET \
259 - OMAP4_CTRL_MODULE_PAD_GPMC_AD0_OFFSET + 2)
260
261/* ctrl_module_pad_wkup base address */
262#define OMAP4_CTRL_MODULE_PAD_WKUP_MUX_PBASE 0x4a31e000
263
264/* ctrl_module_pad_wkup registers offset */
265#define OMAP4_CTRL_MODULE_PAD_SIM_IO_OFFSET 0x0040
266#define OMAP4_CTRL_MODULE_PAD_SIM_CLK_OFFSET 0x0042
267#define OMAP4_CTRL_MODULE_PAD_SIM_RESET_OFFSET 0x0044
268#define OMAP4_CTRL_MODULE_PAD_SIM_CD_OFFSET 0x0046
269#define OMAP4_CTRL_MODULE_PAD_SIM_PWRCTRL_OFFSET 0x0048
270#define OMAP4_CTRL_MODULE_PAD_SR_SCL_OFFSET 0x004a
271#define OMAP4_CTRL_MODULE_PAD_SR_SDA_OFFSET 0x004c
272#define OMAP4_CTRL_MODULE_PAD_FREF_XTAL_IN_OFFSET 0x004e
273#define OMAP4_CTRL_MODULE_PAD_FREF_SLICER_IN_OFFSET 0x0050
274#define OMAP4_CTRL_MODULE_PAD_FREF_CLK_IOREQ_OFFSET 0x0052
275#define OMAP4_CTRL_MODULE_PAD_FREF_CLK0_OUT_OFFSET 0x0054
276#define OMAP4_CTRL_MODULE_PAD_FREF_CLK3_REQ_OFFSET 0x0056
277#define OMAP4_CTRL_MODULE_PAD_FREF_CLK3_OUT_OFFSET 0x0058
278#define OMAP4_CTRL_MODULE_PAD_FREF_CLK4_REQ_OFFSET 0x005a
279#define OMAP4_CTRL_MODULE_PAD_FREF_CLK4_OUT_OFFSET 0x005c
280#define OMAP4_CTRL_MODULE_PAD_SYS_32K_OFFSET 0x005e
281#define OMAP4_CTRL_MODULE_PAD_SYS_NRESPWRON_OFFSET 0x0060
282#define OMAP4_CTRL_MODULE_PAD_SYS_NRESWARM_OFFSET 0x0062
283#define OMAP4_CTRL_MODULE_PAD_SYS_PWR_REQ_OFFSET 0x0064
284#define OMAP4_CTRL_MODULE_PAD_SYS_PWRON_RESET_OUT_OFFSET 0x0066
285#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT6_OFFSET 0x0068
286#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT7_OFFSET 0x006a
287#define OMAP4_CTRL_MODULE_PAD_JTAG_NTRST_OFFSET 0x006c
288#define OMAP4_CTRL_MODULE_PAD_JTAG_TCK_OFFSET 0x006e
289#define OMAP4_CTRL_MODULE_PAD_JTAG_RTCK_OFFSET 0x0070
290#define OMAP4_CTRL_MODULE_PAD_JTAG_TMS_TMSC_OFFSET 0x0072
291#define OMAP4_CTRL_MODULE_PAD_JTAG_TDI_OFFSET 0x0074
292#define OMAP4_CTRL_MODULE_PAD_JTAG_TDO_OFFSET 0x0076
293
294#define OMAP4_CTRL_MODULE_PAD_WKUP_MUX_SIZE \
295 (OMAP4_CTRL_MODULE_PAD_JTAG_TDO_OFFSET \
296 - OMAP4_CTRL_MODULE_PAD_SIM_IO_OFFSET + 2)
297
298#endif
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index adf6e3632a2b..a1a3dd6303b4 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -16,11 +16,13 @@
16#include <plat/cpu.h> 16#include <plat/cpu.h>
17#include <plat/dma.h> 17#include <plat/dma.h>
18#include <plat/serial.h> 18#include <plat/serial.h>
19#include <plat/i2c.h>
20#include <plat/omap24xx.h>
19 21
20#include "omap_hwmod_common_data.h" 22#include "omap_hwmod_common_data.h"
21 23
22#include "prm-regbits-24xx.h"
23#include "cm-regbits-24xx.h" 24#include "cm-regbits-24xx.h"
25#include "prm-regbits-24xx.h"
24 26
25/* 27/*
26 * OMAP2420 hardware module integration data 28 * OMAP2420 hardware module integration data
@@ -77,6 +79,8 @@ static struct omap_hwmod omap2420_l4_wkup_hwmod;
77static struct omap_hwmod omap2420_uart1_hwmod; 79static struct omap_hwmod omap2420_uart1_hwmod;
78static struct omap_hwmod omap2420_uart2_hwmod; 80static struct omap_hwmod omap2420_uart2_hwmod;
79static struct omap_hwmod omap2420_uart3_hwmod; 81static struct omap_hwmod omap2420_uart3_hwmod;
82static struct omap_hwmod omap2420_i2c1_hwmod;
83static struct omap_hwmod omap2420_i2c2_hwmod;
80 84
81/* L4_CORE -> L4_WKUP interface */ 85/* L4_CORE -> L4_WKUP interface */
82static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = { 86static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = {
@@ -139,6 +143,45 @@ static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
139 .user = OCP_USER_MPU | OCP_USER_SDMA, 143 .user = OCP_USER_MPU | OCP_USER_SDMA,
140}; 144};
141 145
146/* I2C IP block address space length (in bytes) */
147#define OMAP2_I2C_AS_LEN 128
148
149/* L4 CORE -> I2C1 interface */
150static struct omap_hwmod_addr_space omap2420_i2c1_addr_space[] = {
151 {
152 .pa_start = 0x48070000,
153 .pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
154 .flags = ADDR_TYPE_RT,
155 },
156};
157
158static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
159 .master = &omap2420_l4_core_hwmod,
160 .slave = &omap2420_i2c1_hwmod,
161 .clk = "i2c1_ick",
162 .addr = omap2420_i2c1_addr_space,
163 .addr_cnt = ARRAY_SIZE(omap2420_i2c1_addr_space),
164 .user = OCP_USER_MPU | OCP_USER_SDMA,
165};
166
167/* L4 CORE -> I2C2 interface */
168static struct omap_hwmod_addr_space omap2420_i2c2_addr_space[] = {
169 {
170 .pa_start = 0x48072000,
171 .pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
172 .flags = ADDR_TYPE_RT,
173 },
174};
175
176static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
177 .master = &omap2420_l4_core_hwmod,
178 .slave = &omap2420_i2c2_hwmod,
179 .clk = "i2c2_ick",
180 .addr = omap2420_i2c2_addr_space,
181 .addr_cnt = ARRAY_SIZE(omap2420_i2c2_addr_space),
182 .user = OCP_USER_MPU | OCP_USER_SDMA,
183};
184
142/* Slave interfaces on the L4_CORE interconnect */ 185/* Slave interfaces on the L4_CORE interconnect */
143static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = { 186static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = {
144 &omap2420_l3_main__l4_core, 187 &omap2420_l3_main__l4_core,
@@ -150,6 +193,8 @@ static struct omap_hwmod_ocp_if *omap2420_l4_core_masters[] = {
150 &omap2_l4_core__uart1, 193 &omap2_l4_core__uart1,
151 &omap2_l4_core__uart2, 194 &omap2_l4_core__uart2,
152 &omap2_l4_core__uart3, 195 &omap2_l4_core__uart3,
196 &omap2420_l4_core__i2c1,
197 &omap2420_l4_core__i2c2
153}; 198};
154 199
155/* L4 CORE */ 200/* L4 CORE */
@@ -418,6 +463,100 @@ static struct omap_hwmod omap2420_uart3_hwmod = {
418 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), 463 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
419}; 464};
420 465
466/* I2C common */
467static struct omap_hwmod_class_sysconfig i2c_sysc = {
468 .rev_offs = 0x00,
469 .sysc_offs = 0x20,
470 .syss_offs = 0x10,
471 .sysc_flags = SYSC_HAS_SOFTRESET,
472 .sysc_fields = &omap_hwmod_sysc_type1,
473};
474
475static struct omap_hwmod_class i2c_class = {
476 .name = "i2c",
477 .sysc = &i2c_sysc,
478};
479
480static struct omap_i2c_dev_attr i2c_dev_attr;
481
482/* I2C1 */
483
484static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
485 { .irq = INT_24XX_I2C1_IRQ, },
486};
487
488static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
489 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
490 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
491};
492
493static struct omap_hwmod_ocp_if *omap2420_i2c1_slaves[] = {
494 &omap2420_l4_core__i2c1,
495};
496
497static struct omap_hwmod omap2420_i2c1_hwmod = {
498 .name = "i2c1",
499 .mpu_irqs = i2c1_mpu_irqs,
500 .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs),
501 .sdma_reqs = i2c1_sdma_reqs,
502 .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs),
503 .main_clk = "i2c1_fck",
504 .prcm = {
505 .omap2 = {
506 .module_offs = CORE_MOD,
507 .prcm_reg_id = 1,
508 .module_bit = OMAP2420_EN_I2C1_SHIFT,
509 .idlest_reg_id = 1,
510 .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,
511 },
512 },
513 .slaves = omap2420_i2c1_slaves,
514 .slaves_cnt = ARRAY_SIZE(omap2420_i2c1_slaves),
515 .class = &i2c_class,
516 .dev_attr = &i2c_dev_attr,
517 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
518 .flags = HWMOD_16BIT_REG,
519};
520
521/* I2C2 */
522
523static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
524 { .irq = INT_24XX_I2C2_IRQ, },
525};
526
527static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
528 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
529 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
530};
531
532static struct omap_hwmod_ocp_if *omap2420_i2c2_slaves[] = {
533 &omap2420_l4_core__i2c2,
534};
535
536static struct omap_hwmod omap2420_i2c2_hwmod = {
537 .name = "i2c2",
538 .mpu_irqs = i2c2_mpu_irqs,
539 .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs),
540 .sdma_reqs = i2c2_sdma_reqs,
541 .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs),
542 .main_clk = "i2c2_fck",
543 .prcm = {
544 .omap2 = {
545 .module_offs = CORE_MOD,
546 .prcm_reg_id = 1,
547 .module_bit = OMAP2420_EN_I2C2_SHIFT,
548 .idlest_reg_id = 1,
549 .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,
550 },
551 },
552 .slaves = omap2420_i2c2_slaves,
553 .slaves_cnt = ARRAY_SIZE(omap2420_i2c2_slaves),
554 .class = &i2c_class,
555 .dev_attr = &i2c_dev_attr,
556 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
557 .flags = HWMOD_16BIT_REG,
558};
559
421static __initdata struct omap_hwmod *omap2420_hwmods[] = { 560static __initdata struct omap_hwmod *omap2420_hwmods[] = {
422 &omap2420_l3_main_hwmod, 561 &omap2420_l3_main_hwmod,
423 &omap2420_l4_core_hwmod, 562 &omap2420_l4_core_hwmod,
@@ -428,6 +567,8 @@ static __initdata struct omap_hwmod *omap2420_hwmods[] = {
428 &omap2420_uart1_hwmod, 567 &omap2420_uart1_hwmod,
429 &omap2420_uart2_hwmod, 568 &omap2420_uart2_hwmod,
430 &omap2420_uart3_hwmod, 569 &omap2420_uart3_hwmod,
570 &omap2420_i2c1_hwmod,
571 &omap2420_i2c2_hwmod,
431 NULL, 572 NULL,
432}; 573};
433 574
@@ -435,5 +576,3 @@ int __init omap2420_hwmod_init(void)
435{ 576{
436 return omap_hwmod_init(omap2420_hwmods); 577 return omap_hwmod_init(omap2420_hwmods);
437} 578}
438
439
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 12d939e456cf..7cf0d3ab2a4a 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -16,6 +16,8 @@
16#include <plat/cpu.h> 16#include <plat/cpu.h>
17#include <plat/dma.h> 17#include <plat/dma.h>
18#include <plat/serial.h> 18#include <plat/serial.h>
19#include <plat/i2c.h>
20#include <plat/omap24xx.h>
19 21
20#include "omap_hwmod_common_data.h" 22#include "omap_hwmod_common_data.h"
21 23
@@ -77,6 +79,47 @@ static struct omap_hwmod omap2430_l4_wkup_hwmod;
77static struct omap_hwmod omap2430_uart1_hwmod; 79static struct omap_hwmod omap2430_uart1_hwmod;
78static struct omap_hwmod omap2430_uart2_hwmod; 80static struct omap_hwmod omap2430_uart2_hwmod;
79static struct omap_hwmod omap2430_uart3_hwmod; 81static struct omap_hwmod omap2430_uart3_hwmod;
82static struct omap_hwmod omap2430_i2c1_hwmod;
83static struct omap_hwmod omap2430_i2c2_hwmod;
84
85/* I2C IP block address space length (in bytes) */
86#define OMAP2_I2C_AS_LEN 128
87
88/* L4 CORE -> I2C1 interface */
89static struct omap_hwmod_addr_space omap2430_i2c1_addr_space[] = {
90 {
91 .pa_start = 0x48070000,
92 .pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
93 .flags = ADDR_TYPE_RT,
94 },
95};
96
97static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = {
98 .master = &omap2430_l4_core_hwmod,
99 .slave = &omap2430_i2c1_hwmod,
100 .clk = "i2c1_ick",
101 .addr = omap2430_i2c1_addr_space,
102 .addr_cnt = ARRAY_SIZE(omap2430_i2c1_addr_space),
103 .user = OCP_USER_MPU | OCP_USER_SDMA,
104};
105
106/* L4 CORE -> I2C2 interface */
107static struct omap_hwmod_addr_space omap2430_i2c2_addr_space[] = {
108 {
109 .pa_start = 0x48072000,
110 .pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
111 .flags = ADDR_TYPE_RT,
112 },
113};
114
115static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = {
116 .master = &omap2430_l4_core_hwmod,
117 .slave = &omap2430_i2c2_hwmod,
118 .clk = "i2c2_ick",
119 .addr = omap2430_i2c2_addr_space,
120 .addr_cnt = ARRAY_SIZE(omap2430_i2c2_addr_space),
121 .user = OCP_USER_MPU | OCP_USER_SDMA,
122};
80 123
81/* L4_CORE -> L4_WKUP interface */ 124/* L4_CORE -> L4_WKUP interface */
82static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = { 125static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = {
@@ -418,6 +461,114 @@ static struct omap_hwmod omap2430_uart3_hwmod = {
418 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 461 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
419}; 462};
420 463
464/* I2C common */
465static struct omap_hwmod_class_sysconfig i2c_sysc = {
466 .rev_offs = 0x00,
467 .sysc_offs = 0x20,
468 .syss_offs = 0x10,
469 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
470 .sysc_fields = &omap_hwmod_sysc_type1,
471};
472
473static struct omap_hwmod_class i2c_class = {
474 .name = "i2c",
475 .sysc = &i2c_sysc,
476};
477
478static struct omap_i2c_dev_attr i2c_dev_attr;
479
480/* I2C1 */
481
482static struct omap_i2c_dev_attr i2c1_dev_attr = {
483 .fifo_depth = 8, /* bytes */
484};
485
486static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
487 { .irq = INT_24XX_I2C1_IRQ, },
488};
489
490static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
491 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
492 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
493};
494
495static struct omap_hwmod_ocp_if *omap2430_i2c1_slaves[] = {
496 &omap2430_l4_core__i2c1,
497};
498
499static struct omap_hwmod omap2430_i2c1_hwmod = {
500 .name = "i2c1",
501 .mpu_irqs = i2c1_mpu_irqs,
502 .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs),
503 .sdma_reqs = i2c1_sdma_reqs,
504 .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs),
505 .main_clk = "i2chs1_fck",
506 .prcm = {
507 .omap2 = {
508 /*
509 * NOTE: The CM_FCLKEN* and CM_ICLKEN* for
510 * I2CHS IP's do not follow the usual pattern.
511 * prcm_reg_id alone cannot be used to program
512 * the iclk and fclk. Needs to be handled using
513 * additonal flags when clk handling is moved
514 * to hwmod framework.
515 */
516 .module_offs = CORE_MOD,
517 .prcm_reg_id = 1,
518 .module_bit = OMAP2430_EN_I2CHS1_SHIFT,
519 .idlest_reg_id = 1,
520 .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT,
521 },
522 },
523 .slaves = omap2430_i2c1_slaves,
524 .slaves_cnt = ARRAY_SIZE(omap2430_i2c1_slaves),
525 .class = &i2c_class,
526 .dev_attr = &i2c1_dev_attr,
527 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
528};
529
530/* I2C2 */
531
532static struct omap_i2c_dev_attr i2c2_dev_attr = {
533 .fifo_depth = 8, /* bytes */
534};
535
536static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
537 { .irq = INT_24XX_I2C2_IRQ, },
538};
539
540static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
541 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
542 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
543};
544
545static struct omap_hwmod_ocp_if *omap2430_i2c2_slaves[] = {
546 &omap2430_l4_core__i2c2,
547};
548
549static struct omap_hwmod omap2430_i2c2_hwmod = {
550 .name = "i2c2",
551 .mpu_irqs = i2c2_mpu_irqs,
552 .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs),
553 .sdma_reqs = i2c2_sdma_reqs,
554 .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs),
555 .main_clk = "i2chs2_fck",
556 .prcm = {
557 .omap2 = {
558 .module_offs = CORE_MOD,
559 .prcm_reg_id = 1,
560 .module_bit = OMAP2430_EN_I2CHS2_SHIFT,
561 .idlest_reg_id = 1,
562 .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT,
563 },
564 },
565 .slaves = omap2430_i2c2_slaves,
566 .slaves_cnt = ARRAY_SIZE(omap2430_i2c2_slaves),
567 .class = &i2c_class,
568 .dev_attr = &i2c2_dev_attr,
569 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
570};
571
421static __initdata struct omap_hwmod *omap2430_hwmods[] = { 572static __initdata struct omap_hwmod *omap2430_hwmods[] = {
422 &omap2430_l3_main_hwmod, 573 &omap2430_l3_main_hwmod,
423 &omap2430_l4_core_hwmod, 574 &omap2430_l4_core_hwmod,
@@ -428,6 +579,8 @@ static __initdata struct omap_hwmod *omap2430_hwmods[] = {
428 &omap2430_uart1_hwmod, 579 &omap2430_uart1_hwmod,
429 &omap2430_uart2_hwmod, 580 &omap2430_uart2_hwmod,
430 &omap2430_uart3_hwmod, 581 &omap2430_uart3_hwmod,
582 &omap2430_i2c1_hwmod,
583 &omap2430_i2c2_hwmod,
431 NULL, 584 NULL,
432}; 585};
433 586
@@ -435,5 +588,3 @@ int __init omap2430_hwmod_init(void)
435{ 588{
436 return omap_hwmod_init(omap2430_hwmods); 589 return omap_hwmod_init(omap2430_hwmods);
437} 590}
438
439
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index cb97ecf0a3f6..a8bed843079c 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -18,6 +18,9 @@
18#include <plat/cpu.h> 18#include <plat/cpu.h>
19#include <plat/dma.h> 19#include <plat/dma.h>
20#include <plat/serial.h> 20#include <plat/serial.h>
21#include <plat/l4_3xxx.h>
22#include <plat/i2c.h>
23#include <plat/omap34xx.h>
21 24
22#include "omap_hwmod_common_data.h" 25#include "omap_hwmod_common_data.h"
23 26
@@ -39,6 +42,9 @@ static struct omap_hwmod omap3xxx_l3_main_hwmod;
39static struct omap_hwmod omap3xxx_l4_core_hwmod; 42static struct omap_hwmod omap3xxx_l4_core_hwmod;
40static struct omap_hwmod omap3xxx_l4_per_hwmod; 43static struct omap_hwmod omap3xxx_l4_per_hwmod;
41static struct omap_hwmod omap3xxx_wd_timer2_hwmod; 44static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
45static struct omap_hwmod omap3xxx_i2c1_hwmod;
46static struct omap_hwmod omap3xxx_i2c2_hwmod;
47static struct omap_hwmod omap3xxx_i2c3_hwmod;
42 48
43/* L3 -> L4_CORE interface */ 49/* L3 -> L4_CORE interface */
44static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = { 50static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
@@ -169,6 +175,84 @@ static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
169 .user = OCP_USER_MPU | OCP_USER_SDMA, 175 .user = OCP_USER_MPU | OCP_USER_SDMA,
170}; 176};
171 177
178/* I2C IP block address space length (in bytes) */
179#define OMAP2_I2C_AS_LEN 128
180
181/* L4 CORE -> I2C1 interface */
182static struct omap_hwmod_addr_space omap3xxx_i2c1_addr_space[] = {
183 {
184 .pa_start = 0x48070000,
185 .pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
186 .flags = ADDR_TYPE_RT,
187 },
188};
189
190static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
191 .master = &omap3xxx_l4_core_hwmod,
192 .slave = &omap3xxx_i2c1_hwmod,
193 .clk = "i2c1_ick",
194 .addr = omap3xxx_i2c1_addr_space,
195 .addr_cnt = ARRAY_SIZE(omap3xxx_i2c1_addr_space),
196 .fw = {
197 .omap2 = {
198 .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION,
199 .l4_prot_group = 7,
200 .flags = OMAP_FIREWALL_L4,
201 }
202 },
203 .user = OCP_USER_MPU | OCP_USER_SDMA,
204};
205
206/* L4 CORE -> I2C2 interface */
207static struct omap_hwmod_addr_space omap3xxx_i2c2_addr_space[] = {
208 {
209 .pa_start = 0x48072000,
210 .pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
211 .flags = ADDR_TYPE_RT,
212 },
213};
214
215static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
216 .master = &omap3xxx_l4_core_hwmod,
217 .slave = &omap3xxx_i2c2_hwmod,
218 .clk = "i2c2_ick",
219 .addr = omap3xxx_i2c2_addr_space,
220 .addr_cnt = ARRAY_SIZE(omap3xxx_i2c2_addr_space),
221 .fw = {
222 .omap2 = {
223 .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION,
224 .l4_prot_group = 7,
225 .flags = OMAP_FIREWALL_L4,
226 }
227 },
228 .user = OCP_USER_MPU | OCP_USER_SDMA,
229};
230
231/* L4 CORE -> I2C3 interface */
232static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
233 {
234 .pa_start = 0x48060000,
235 .pa_end = 0x48060000 + OMAP2_I2C_AS_LEN - 1,
236 .flags = ADDR_TYPE_RT,
237 },
238};
239
240static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
241 .master = &omap3xxx_l4_core_hwmod,
242 .slave = &omap3xxx_i2c3_hwmod,
243 .clk = "i2c3_ick",
244 .addr = omap3xxx_i2c3_addr_space,
245 .addr_cnt = ARRAY_SIZE(omap3xxx_i2c3_addr_space),
246 .fw = {
247 .omap2 = {
248 .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION,
249 .l4_prot_group = 7,
250 .flags = OMAP_FIREWALL_L4,
251 }
252 },
253 .user = OCP_USER_MPU | OCP_USER_SDMA,
254};
255
172/* Slave interfaces on the L4_CORE interconnect */ 256/* Slave interfaces on the L4_CORE interconnect */
173static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = { 257static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
174 &omap3xxx_l3_main__l4_core, 258 &omap3xxx_l3_main__l4_core,
@@ -179,6 +263,9 @@ static struct omap_hwmod_ocp_if *omap3xxx_l4_core_masters[] = {
179 &omap3xxx_l4_core__l4_wkup, 263 &omap3xxx_l4_core__l4_wkup,
180 &omap3_l4_core__uart1, 264 &omap3_l4_core__uart1,
181 &omap3_l4_core__uart2, 265 &omap3_l4_core__uart2,
266 &omap3_l4_core__i2c1,
267 &omap3_l4_core__i2c2,
268 &omap3_l4_core__i2c3,
182}; 269};
183 270
184/* L4 CORE */ 271/* L4 CORE */
@@ -315,6 +402,18 @@ static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
315 .sysc_fields = &omap_hwmod_sysc_type1, 402 .sysc_fields = &omap_hwmod_sysc_type1,
316}; 403};
317 404
405/* I2C common */
406static struct omap_hwmod_class_sysconfig i2c_sysc = {
407 .rev_offs = 0x00,
408 .sysc_offs = 0x20,
409 .syss_offs = 0x10,
410 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
411 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
412 SYSC_HAS_AUTOIDLE),
413 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
414 .sysc_fields = &omap_hwmod_sysc_type1,
415};
416
318static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = { 417static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
319 .name = "wd_timer", 418 .name = "wd_timer",
320 .sysc = &omap3xxx_wd_timer_sysc, 419 .sysc = &omap3xxx_wd_timer_sysc,
@@ -509,6 +608,137 @@ static struct omap_hwmod omap3xxx_uart4_hwmod = {
509 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1), 608 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
510}; 609};
511 610
611static struct omap_hwmod_class i2c_class = {
612 .name = "i2c",
613 .sysc = &i2c_sysc,
614};
615
616/* I2C1 */
617
618static struct omap_i2c_dev_attr i2c1_dev_attr = {
619 .fifo_depth = 8, /* bytes */
620};
621
622static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
623 { .irq = INT_24XX_I2C1_IRQ, },
624};
625
626static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
627 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
628 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
629};
630
631static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
632 &omap3_l4_core__i2c1,
633};
634
635static struct omap_hwmod omap3xxx_i2c1_hwmod = {
636 .name = "i2c1",
637 .mpu_irqs = i2c1_mpu_irqs,
638 .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs),
639 .sdma_reqs = i2c1_sdma_reqs,
640 .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs),
641 .main_clk = "i2c1_fck",
642 .prcm = {
643 .omap2 = {
644 .module_offs = CORE_MOD,
645 .prcm_reg_id = 1,
646 .module_bit = OMAP3430_EN_I2C1_SHIFT,
647 .idlest_reg_id = 1,
648 .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
649 },
650 },
651 .slaves = omap3xxx_i2c1_slaves,
652 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c1_slaves),
653 .class = &i2c_class,
654 .dev_attr = &i2c1_dev_attr,
655 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
656};
657
658/* I2C2 */
659
660static struct omap_i2c_dev_attr i2c2_dev_attr = {
661 .fifo_depth = 8, /* bytes */
662};
663
664static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
665 { .irq = INT_24XX_I2C2_IRQ, },
666};
667
668static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
669 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
670 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
671};
672
673static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
674 &omap3_l4_core__i2c2,
675};
676
677static struct omap_hwmod omap3xxx_i2c2_hwmod = {
678 .name = "i2c2",
679 .mpu_irqs = i2c2_mpu_irqs,
680 .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs),
681 .sdma_reqs = i2c2_sdma_reqs,
682 .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs),
683 .main_clk = "i2c2_fck",
684 .prcm = {
685 .omap2 = {
686 .module_offs = CORE_MOD,
687 .prcm_reg_id = 1,
688 .module_bit = OMAP3430_EN_I2C2_SHIFT,
689 .idlest_reg_id = 1,
690 .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
691 },
692 },
693 .slaves = omap3xxx_i2c2_slaves,
694 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c2_slaves),
695 .class = &i2c_class,
696 .dev_attr = &i2c2_dev_attr,
697 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
698};
699
700/* I2C3 */
701
702static struct omap_i2c_dev_attr i2c3_dev_attr = {
703 .fifo_depth = 64, /* bytes */
704};
705
706static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
707 { .irq = INT_34XX_I2C3_IRQ, },
708};
709
710static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
711 { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
712 { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
713};
714
715static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
716 &omap3_l4_core__i2c3,
717};
718
719static struct omap_hwmod omap3xxx_i2c3_hwmod = {
720 .name = "i2c3",
721 .mpu_irqs = i2c3_mpu_irqs,
722 .mpu_irqs_cnt = ARRAY_SIZE(i2c3_mpu_irqs),
723 .sdma_reqs = i2c3_sdma_reqs,
724 .sdma_reqs_cnt = ARRAY_SIZE(i2c3_sdma_reqs),
725 .main_clk = "i2c3_fck",
726 .prcm = {
727 .omap2 = {
728 .module_offs = CORE_MOD,
729 .prcm_reg_id = 1,
730 .module_bit = OMAP3430_EN_I2C3_SHIFT,
731 .idlest_reg_id = 1,
732 .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
733 },
734 },
735 .slaves = omap3xxx_i2c3_slaves,
736 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c3_slaves),
737 .class = &i2c_class,
738 .dev_attr = &i2c3_dev_attr,
739 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
740};
741
512static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { 742static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
513 &omap3xxx_l3_main_hwmod, 743 &omap3xxx_l3_main_hwmod,
514 &omap3xxx_l4_core_hwmod, 744 &omap3xxx_l4_core_hwmod,
@@ -521,6 +751,9 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
521 &omap3xxx_uart2_hwmod, 751 &omap3xxx_uart2_hwmod,
522 &omap3xxx_uart3_hwmod, 752 &omap3xxx_uart3_hwmod,
523 &omap3xxx_uart4_hwmod, 753 &omap3xxx_uart4_hwmod,
754 &omap3xxx_i2c1_hwmod,
755 &omap3xxx_i2c2_hwmod,
756 &omap3xxx_i2c3_hwmod,
524 NULL, 757 NULL,
525}; 758};
526 759
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 7274db4de487..0d5c6eb7e4c1 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -383,6 +383,238 @@ static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
383}; 383};
384 384
385/* 385/*
386 * 'i2c' class
387 * multimaster high-speed i2c controller
388 */
389
390static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
391 .sysc_offs = 0x0010,
392 .syss_offs = 0x0090,
393 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
394 SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SOFTRESET |
395 SYSC_HAS_AUTOIDLE),
396 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
397 .sysc_fields = &omap_hwmod_sysc_type1,
398};
399
400static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
401 .name = "i2c",
402 .sysc = &omap44xx_i2c_sysc,
403};
404
405/* i2c1 */
406static struct omap_hwmod omap44xx_i2c1_hwmod;
407static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
408 { .irq = 56 + OMAP44XX_IRQ_GIC_START },
409};
410
411static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
412 { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
413 { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
414};
415
416static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
417 {
418 .pa_start = 0x48070000,
419 .pa_end = 0x480700ff,
420 .flags = ADDR_TYPE_RT
421 },
422};
423
424/* l4_per -> i2c1 */
425static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
426 .master = &omap44xx_l4_per_hwmod,
427 .slave = &omap44xx_i2c1_hwmod,
428 .clk = "l4_div_ck",
429 .addr = omap44xx_i2c1_addrs,
430 .addr_cnt = ARRAY_SIZE(omap44xx_i2c1_addrs),
431 .user = OCP_USER_MPU | OCP_USER_SDMA,
432};
433
434/* i2c1 slave ports */
435static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
436 &omap44xx_l4_per__i2c1,
437};
438
439static struct omap_hwmod omap44xx_i2c1_hwmod = {
440 .name = "i2c1",
441 .class = &omap44xx_i2c_hwmod_class,
442 .flags = HWMOD_INIT_NO_RESET,
443 .mpu_irqs = omap44xx_i2c1_irqs,
444 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c1_irqs),
445 .sdma_reqs = omap44xx_i2c1_sdma_reqs,
446 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c1_sdma_reqs),
447 .main_clk = "i2c1_fck",
448 .prcm = {
449 .omap4 = {
450 .clkctrl_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
451 },
452 },
453 .slaves = omap44xx_i2c1_slaves,
454 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c1_slaves),
455 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
456};
457
458/* i2c2 */
459static struct omap_hwmod omap44xx_i2c2_hwmod;
460static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
461 { .irq = 57 + OMAP44XX_IRQ_GIC_START },
462};
463
464static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
465 { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
466 { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
467};
468
469static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
470 {
471 .pa_start = 0x48072000,
472 .pa_end = 0x480720ff,
473 .flags = ADDR_TYPE_RT
474 },
475};
476
477/* l4_per -> i2c2 */
478static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
479 .master = &omap44xx_l4_per_hwmod,
480 .slave = &omap44xx_i2c2_hwmod,
481 .clk = "l4_div_ck",
482 .addr = omap44xx_i2c2_addrs,
483 .addr_cnt = ARRAY_SIZE(omap44xx_i2c2_addrs),
484 .user = OCP_USER_MPU | OCP_USER_SDMA,
485};
486
487/* i2c2 slave ports */
488static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
489 &omap44xx_l4_per__i2c2,
490};
491
492static struct omap_hwmod omap44xx_i2c2_hwmod = {
493 .name = "i2c2",
494 .class = &omap44xx_i2c_hwmod_class,
495 .flags = HWMOD_INIT_NO_RESET,
496 .mpu_irqs = omap44xx_i2c2_irqs,
497 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c2_irqs),
498 .sdma_reqs = omap44xx_i2c2_sdma_reqs,
499 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c2_sdma_reqs),
500 .main_clk = "i2c2_fck",
501 .prcm = {
502 .omap4 = {
503 .clkctrl_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
504 },
505 },
506 .slaves = omap44xx_i2c2_slaves,
507 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c2_slaves),
508 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
509};
510
511/* i2c3 */
512static struct omap_hwmod omap44xx_i2c3_hwmod;
513static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
514 { .irq = 61 + OMAP44XX_IRQ_GIC_START },
515};
516
517static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
518 { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
519 { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
520};
521
522static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
523 {
524 .pa_start = 0x48060000,
525 .pa_end = 0x480600ff,
526 .flags = ADDR_TYPE_RT
527 },
528};
529
530/* l4_per -> i2c3 */
531static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
532 .master = &omap44xx_l4_per_hwmod,
533 .slave = &omap44xx_i2c3_hwmod,
534 .clk = "l4_div_ck",
535 .addr = omap44xx_i2c3_addrs,
536 .addr_cnt = ARRAY_SIZE(omap44xx_i2c3_addrs),
537 .user = OCP_USER_MPU | OCP_USER_SDMA,
538};
539
540/* i2c3 slave ports */
541static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
542 &omap44xx_l4_per__i2c3,
543};
544
545static struct omap_hwmod omap44xx_i2c3_hwmod = {
546 .name = "i2c3",
547 .class = &omap44xx_i2c_hwmod_class,
548 .flags = HWMOD_INIT_NO_RESET,
549 .mpu_irqs = omap44xx_i2c3_irqs,
550 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c3_irqs),
551 .sdma_reqs = omap44xx_i2c3_sdma_reqs,
552 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c3_sdma_reqs),
553 .main_clk = "i2c3_fck",
554 .prcm = {
555 .omap4 = {
556 .clkctrl_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
557 },
558 },
559 .slaves = omap44xx_i2c3_slaves,
560 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c3_slaves),
561 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
562};
563
564/* i2c4 */
565static struct omap_hwmod omap44xx_i2c4_hwmod;
566static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
567 { .irq = 62 + OMAP44XX_IRQ_GIC_START },
568};
569
570static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
571 { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
572 { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
573};
574
575static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
576 {
577 .pa_start = 0x48350000,
578 .pa_end = 0x483500ff,
579 .flags = ADDR_TYPE_RT
580 },
581};
582
583/* l4_per -> i2c4 */
584static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
585 .master = &omap44xx_l4_per_hwmod,
586 .slave = &omap44xx_i2c4_hwmod,
587 .clk = "l4_div_ck",
588 .addr = omap44xx_i2c4_addrs,
589 .addr_cnt = ARRAY_SIZE(omap44xx_i2c4_addrs),
590 .user = OCP_USER_MPU | OCP_USER_SDMA,
591};
592
593/* i2c4 slave ports */
594static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
595 &omap44xx_l4_per__i2c4,
596};
597
598static struct omap_hwmod omap44xx_i2c4_hwmod = {
599 .name = "i2c4",
600 .class = &omap44xx_i2c_hwmod_class,
601 .flags = HWMOD_INIT_NO_RESET,
602 .mpu_irqs = omap44xx_i2c4_irqs,
603 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c4_irqs),
604 .sdma_reqs = omap44xx_i2c4_sdma_reqs,
605 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c4_sdma_reqs),
606 .main_clk = "i2c4_fck",
607 .prcm = {
608 .omap4 = {
609 .clkctrl_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
610 },
611 },
612 .slaves = omap44xx_i2c4_slaves,
613 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c4_slaves),
614 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
615};
616
617/*
386 * 'mpu_bus' class 618 * 'mpu_bus' class
387 * instance(s): mpu_private 619 * instance(s): mpu_private
388 */ 620 */
@@ -826,6 +1058,11 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
826 &omap44xx_l4_cfg_hwmod, 1058 &omap44xx_l4_cfg_hwmod,
827 &omap44xx_l4_per_hwmod, 1059 &omap44xx_l4_per_hwmod,
828 &omap44xx_l4_wkup_hwmod, 1060 &omap44xx_l4_wkup_hwmod,
1061 /* i2c class */
1062 &omap44xx_i2c1_hwmod,
1063 &omap44xx_i2c2_hwmod,
1064 &omap44xx_i2c3_hwmod,
1065 &omap44xx_i2c4_hwmod,
829 /* mpu_bus class */ 1066 /* mpu_bus class */
830 &omap44xx_mpu_private_hwmod, 1067 &omap44xx_mpu_private_hwmod,
831 1068
diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h
index 9e63cb743a97..ec1a710db9ce 100644
--- a/arch/arm/mach-omap2/prm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-34xx.h
@@ -101,8 +101,11 @@
101#define OMAP3430_GRPSEL_MCSPI3_MASK (1 << 20) 101#define OMAP3430_GRPSEL_MCSPI3_MASK (1 << 20)
102#define OMAP3430_GRPSEL_MCSPI2_MASK (1 << 19) 102#define OMAP3430_GRPSEL_MCSPI2_MASK (1 << 19)
103#define OMAP3430_GRPSEL_MCSPI1_MASK (1 << 18) 103#define OMAP3430_GRPSEL_MCSPI1_MASK (1 << 18)
104#define OMAP3430_GRPSEL_I2C3_SHIFT 17
104#define OMAP3430_GRPSEL_I2C3_MASK (1 << 17) 105#define OMAP3430_GRPSEL_I2C3_MASK (1 << 17)
106#define OMAP3430_GRPSEL_I2C2_SHIFT 16
105#define OMAP3430_GRPSEL_I2C2_MASK (1 << 16) 107#define OMAP3430_GRPSEL_I2C2_MASK (1 << 16)
108#define OMAP3430_GRPSEL_I2C1_SHIFT 15
106#define OMAP3430_GRPSEL_I2C1_MASK (1 << 15) 109#define OMAP3430_GRPSEL_I2C1_MASK (1 << 15)
107#define OMAP3430_GRPSEL_UART2_MASK (1 << 14) 110#define OMAP3430_GRPSEL_UART2_MASK (1 << 14)
108#define OMAP3430_GRPSEL_UART1_MASK (1 << 13) 111#define OMAP3430_GRPSEL_UART1_MASK (1 << 13)
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index d17960a1be25..9dc077e2d8af 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -169,9 +169,9 @@ static inline void serial_write_reg(struct omap_uart_state *uart, int offset,
169 169
170static inline void __init omap_uart_reset(struct omap_uart_state *uart) 170static inline void __init omap_uart_reset(struct omap_uart_state *uart)
171{ 171{
172 serial_write_reg(uart, UART_OMAP_MDR1, 0x07); 172 serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
173 serial_write_reg(uart, UART_OMAP_SCR, 0x08); 173 serial_write_reg(uart, UART_OMAP_SCR, 0x08);
174 serial_write_reg(uart, UART_OMAP_MDR1, 0x00); 174 serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_16X_MODE);
175} 175}
176 176
177#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) 177#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
@@ -219,7 +219,7 @@ static void omap_uart_save_context(struct omap_uart_state *uart)
219 return; 219 return;
220 220
221 lcr = serial_read_reg(uart, UART_LCR); 221 lcr = serial_read_reg(uart, UART_LCR);
222 serial_write_reg(uart, UART_LCR, 0xBF); 222 serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
223 uart->dll = serial_read_reg(uart, UART_DLL); 223 uart->dll = serial_read_reg(uart, UART_DLL);
224 uart->dlh = serial_read_reg(uart, UART_DLM); 224 uart->dlh = serial_read_reg(uart, UART_DLM);
225 serial_write_reg(uart, UART_LCR, lcr); 225 serial_write_reg(uart, UART_LCR, lcr);
@@ -227,7 +227,7 @@ static void omap_uart_save_context(struct omap_uart_state *uart)
227 uart->sysc = serial_read_reg(uart, UART_OMAP_SYSC); 227 uart->sysc = serial_read_reg(uart, UART_OMAP_SYSC);
228 uart->scr = serial_read_reg(uart, UART_OMAP_SCR); 228 uart->scr = serial_read_reg(uart, UART_OMAP_SCR);
229 uart->wer = serial_read_reg(uart, UART_OMAP_WER); 229 uart->wer = serial_read_reg(uart, UART_OMAP_WER);
230 serial_write_reg(uart, UART_LCR, 0x80); 230 serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_A);
231 uart->mcr = serial_read_reg(uart, UART_MCR); 231 uart->mcr = serial_read_reg(uart, UART_MCR);
232 serial_write_reg(uart, UART_LCR, lcr); 232 serial_write_reg(uart, UART_LCR, lcr);
233 233
@@ -247,32 +247,35 @@ static void omap_uart_restore_context(struct omap_uart_state *uart)
247 uart->context_valid = 0; 247 uart->context_valid = 0;
248 248
249 if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS) 249 if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS)
250 omap_uart_mdr1_errataset(uart, 0x07, 0xA0); 250 omap_uart_mdr1_errataset(uart, UART_OMAP_MDR1_DISABLE, 0xA0);
251 else 251 else
252 serial_write_reg(uart, UART_OMAP_MDR1, 0x7); 252 serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
253 serial_write_reg(uart, UART_LCR, 0xBF); /* Config B mode */ 253
254 serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
254 efr = serial_read_reg(uart, UART_EFR); 255 efr = serial_read_reg(uart, UART_EFR);
255 serial_write_reg(uart, UART_EFR, UART_EFR_ECB); 256 serial_write_reg(uart, UART_EFR, UART_EFR_ECB);
256 serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */ 257 serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */
257 serial_write_reg(uart, UART_IER, 0x0); 258 serial_write_reg(uart, UART_IER, 0x0);
258 serial_write_reg(uart, UART_LCR, 0xBF); /* Config B mode */ 259 serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
259 serial_write_reg(uart, UART_DLL, uart->dll); 260 serial_write_reg(uart, UART_DLL, uart->dll);
260 serial_write_reg(uart, UART_DLM, uart->dlh); 261 serial_write_reg(uart, UART_DLM, uart->dlh);
261 serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */ 262 serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */
262 serial_write_reg(uart, UART_IER, uart->ier); 263 serial_write_reg(uart, UART_IER, uart->ier);
263 serial_write_reg(uart, UART_LCR, 0x80); 264 serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_A);
264 serial_write_reg(uart, UART_MCR, uart->mcr); 265 serial_write_reg(uart, UART_MCR, uart->mcr);
265 serial_write_reg(uart, UART_LCR, 0xBF); /* Config B mode */ 266 serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
266 serial_write_reg(uart, UART_EFR, efr); 267 serial_write_reg(uart, UART_EFR, efr);
267 serial_write_reg(uart, UART_LCR, UART_LCR_WLEN8); 268 serial_write_reg(uart, UART_LCR, UART_LCR_WLEN8);
268 serial_write_reg(uart, UART_OMAP_SCR, uart->scr); 269 serial_write_reg(uart, UART_OMAP_SCR, uart->scr);
269 serial_write_reg(uart, UART_OMAP_WER, uart->wer); 270 serial_write_reg(uart, UART_OMAP_WER, uart->wer);
270 serial_write_reg(uart, UART_OMAP_SYSC, uart->sysc); 271 serial_write_reg(uart, UART_OMAP_SYSC, uart->sysc);
272
271 if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS) 273 if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS)
272 omap_uart_mdr1_errataset(uart, 0x00, 0xA1); 274 omap_uart_mdr1_errataset(uart, UART_OMAP_MDR1_16X_MODE, 0xA1);
273 else 275 else
274 /* UART 16x mode */ 276 /* UART 16x mode */
275 serial_write_reg(uart, UART_OMAP_MDR1, 0x00); 277 serial_write_reg(uart, UART_OMAP_MDR1,
278 UART_OMAP_MDR1_16X_MODE);
276} 279}
277#else 280#else
278static inline void omap_uart_save_context(struct omap_uart_state *uart) {} 281static inline void omap_uart_save_context(struct omap_uart_state *uart) {}
diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c
index e13c29eecf2b..f9052e1c6936 100644
--- a/arch/arm/mach-omap2/timer-gp.c
+++ b/arch/arm/mach-omap2/timer-gp.c
@@ -203,7 +203,7 @@ static struct clocksource clocksource_gpt = {
203static void __init omap2_gp_clocksource_init(void) 203static void __init omap2_gp_clocksource_init(void)
204{ 204{
205 static struct omap_dm_timer *gpt; 205 static struct omap_dm_timer *gpt;
206 u32 tick_rate, tick_period; 206 u32 tick_rate;
207 static char err1[] __initdata = KERN_ERR 207 static char err1[] __initdata = KERN_ERR
208 "%s: failed to request dm-timer\n"; 208 "%s: failed to request dm-timer\n";
209 static char err2[] __initdata = KERN_ERR 209 static char err2[] __initdata = KERN_ERR
@@ -216,7 +216,6 @@ static void __init omap2_gp_clocksource_init(void)
216 216
217 omap_dm_timer_set_source(gpt, OMAP_TIMER_SRC_SYS_CLK); 217 omap_dm_timer_set_source(gpt, OMAP_TIMER_SRC_SYS_CLK);
218 tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gpt)); 218 tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gpt));
219 tick_period = (tick_rate / HZ) - 1;
220 219
221 omap_dm_timer_set_load_start(gpt, 1, 0); 220 omap_dm_timer_set_load_start(gpt, 1, 0);
222 221
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 2c2826571d45..a863f5546a6b 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -174,7 +174,7 @@ static inline void omap_enable_channel_irq(int lch);
174 174
175#ifdef CONFIG_ARCH_OMAP15XX 175#ifdef CONFIG_ARCH_OMAP15XX
176/* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */ 176/* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
177int omap_dma_in_1510_mode(void) 177static int omap_dma_in_1510_mode(void)
178{ 178{
179 return enable_1510_mode; 179 return enable_1510_mode;
180} 180}
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index c05c653d1674..e0e2fa725269 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -1318,6 +1318,10 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1318 if (bank->method == METHOD_GPIO_44XX) 1318 if (bank->method == METHOD_GPIO_44XX)
1319 isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0; 1319 isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0;
1320#endif 1320#endif
1321
1322 if (WARN_ON(!isr_reg))
1323 goto exit;
1324
1321 while(1) { 1325 while(1) {
1322 u32 isr_saved, level_mask = 0; 1326 u32 isr_saved, level_mask = 0;
1323 u32 enabled; 1327 u32 enabled;
@@ -1377,6 +1381,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1377 configured, we must unmask the bank interrupt only after 1381 configured, we must unmask the bank interrupt only after
1378 handler(s) are executed in order to avoid spurious bank 1382 handler(s) are executed in order to avoid spurious bank
1379 interrupt */ 1383 interrupt */
1384exit:
1380 if (!unmasked) 1385 if (!unmasked)
1381 desc->chip->unmask(irq); 1386 desc->chip->unmask(irq);
1382 1387
diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c
index a5ce4f0aad35..db9c4efd79e3 100644
--- a/arch/arm/plat-omap/i2c.c
+++ b/arch/arm/plat-omap/i2c.c
@@ -27,18 +27,18 @@
27#include <linux/platform_device.h> 27#include <linux/platform_device.h>
28#include <linux/i2c.h> 28#include <linux/i2c.h>
29#include <linux/i2c-omap.h> 29#include <linux/i2c-omap.h>
30#include <linux/slab.h>
31#include <linux/err.h>
32#include <linux/clk.h>
30 33
31#include <mach/irqs.h> 34#include <mach/irqs.h>
32#include <plat/mux.h> 35#include <plat/mux.h>
33#include <plat/i2c.h> 36#include <plat/i2c.h>
34#include <plat/omap-pm.h> 37#include <plat/omap-pm.h>
38#include <plat/omap_device.h>
35 39
36#define OMAP_I2C_SIZE 0x3f 40#define OMAP_I2C_SIZE 0x3f
37#define OMAP1_I2C_BASE 0xfffb3800 41#define OMAP1_I2C_BASE 0xfffb3800
38#define OMAP2_I2C_BASE1 0x48070000
39#define OMAP2_I2C_BASE2 0x48072000
40#define OMAP2_I2C_BASE3 0x48060000
41#define OMAP4_I2C_BASE4 0x48350000
42 42
43static const char name[] = "i2c_omap"; 43static const char name[] = "i2c_omap";
44 44
@@ -55,15 +55,6 @@ static const char name[] = "i2c_omap";
55 55
56static struct resource i2c_resources[][2] = { 56static struct resource i2c_resources[][2] = {
57 { I2C_RESOURCE_BUILDER(0, 0) }, 57 { I2C_RESOURCE_BUILDER(0, 0) },
58#if defined(CONFIG_ARCH_OMAP2PLUS)
59 { I2C_RESOURCE_BUILDER(OMAP2_I2C_BASE2, 0) },
60#endif
61#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
62 { I2C_RESOURCE_BUILDER(OMAP2_I2C_BASE3, 0) },
63#endif
64#if defined(CONFIG_ARCH_OMAP4)
65 { I2C_RESOURCE_BUILDER(OMAP4_I2C_BASE4, 0) },
66#endif
67}; 58};
68 59
69#define I2C_DEV_BUILDER(bus_id, res, data) \ 60#define I2C_DEV_BUILDER(bus_id, res, data) \
@@ -77,18 +68,11 @@ static struct resource i2c_resources[][2] = {
77 }, \ 68 }, \
78 } 69 }
79 70
80static struct omap_i2c_bus_platform_data i2c_pdata[ARRAY_SIZE(i2c_resources)]; 71#define MAX_OMAP_I2C_HWMOD_NAME_LEN 16
72#define OMAP_I2C_MAX_CONTROLLERS 4
73static struct omap_i2c_bus_platform_data i2c_pdata[OMAP_I2C_MAX_CONTROLLERS];
81static struct platform_device omap_i2c_devices[] = { 74static struct platform_device omap_i2c_devices[] = {
82 I2C_DEV_BUILDER(1, i2c_resources[0], &i2c_pdata[0]), 75 I2C_DEV_BUILDER(1, i2c_resources[0], &i2c_pdata[0]),
83#if defined(CONFIG_ARCH_OMAP2PLUS)
84 I2C_DEV_BUILDER(2, i2c_resources[1], &i2c_pdata[1]),
85#endif
86#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
87 I2C_DEV_BUILDER(3, i2c_resources[2], &i2c_pdata[2]),
88#endif
89#if defined(CONFIG_ARCH_OMAP4)
90 I2C_DEV_BUILDER(4, i2c_resources[3], &i2c_pdata[3]),
91#endif
92}; 76};
93 77
94#define OMAP_I2C_CMDLINE_SETUP (BIT(31)) 78#define OMAP_I2C_CMDLINE_SETUP (BIT(31))
@@ -109,35 +93,25 @@ static int __init omap_i2c_nr_ports(void)
109 return ports; 93 return ports;
110} 94}
111 95
112/* Shared between omap2 and 3 */ 96static inline int omap1_i2c_add_bus(int bus_id)
113static resource_size_t omap2_i2c_irq[3] __initdata = {
114 INT_24XX_I2C1_IRQ,
115 INT_24XX_I2C2_IRQ,
116 INT_34XX_I2C3_IRQ,
117};
118
119static resource_size_t omap4_i2c_irq[4] __initdata = {
120 OMAP44XX_IRQ_I2C1,
121 OMAP44XX_IRQ_I2C2,
122 OMAP44XX_IRQ_I2C3,
123 OMAP44XX_IRQ_I2C4,
124};
125
126static inline int omap1_i2c_add_bus(struct platform_device *pdev, int bus_id)
127{ 97{
128 struct omap_i2c_bus_platform_data *pd; 98 struct platform_device *pdev;
99 struct omap_i2c_bus_platform_data *pdata;
129 struct resource *res; 100 struct resource *res;
130 101
131 pd = pdev->dev.platform_data; 102 omap1_i2c_mux_pins(bus_id);
103
104 pdev = &omap_i2c_devices[bus_id - 1];
132 res = pdev->resource; 105 res = pdev->resource;
133 res[0].start = OMAP1_I2C_BASE; 106 res[0].start = OMAP1_I2C_BASE;
134 res[0].end = res[0].start + OMAP_I2C_SIZE; 107 res[0].end = res[0].start + OMAP_I2C_SIZE;
135 res[1].start = INT_I2C; 108 res[1].start = INT_I2C;
136 omap1_i2c_mux_pins(bus_id); 109 pdata = &i2c_pdata[bus_id - 1];
137 110
138 return platform_device_register(pdev); 111 return platform_device_register(pdev);
139} 112}
140 113
114
141/* 115/*
142 * XXX This function is a temporary compatibility wrapper - only 116 * XXX This function is a temporary compatibility wrapper - only
143 * needed until the I2C driver can be converted to call 117 * needed until the I2C driver can be converted to call
@@ -148,52 +122,64 @@ static void omap_pm_set_max_mpu_wakeup_lat_compat(struct device *dev, long t)
148 omap_pm_set_max_mpu_wakeup_lat(dev, t); 122 omap_pm_set_max_mpu_wakeup_lat(dev, t);
149} 123}
150 124
151static inline int omap2_i2c_add_bus(struct platform_device *pdev, int bus_id) 125static struct omap_device_pm_latency omap_i2c_latency[] = {
152{ 126 [0] = {
153 struct resource *res; 127 .deactivate_func = omap_device_idle_hwmods,
154 resource_size_t *irq; 128 .activate_func = omap_device_enable_hwmods,
129 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
130 },
131};
155 132
156 res = pdev->resource; 133#ifdef CONFIG_ARCH_OMAP2PLUS
134static inline int omap2_i2c_add_bus(int bus_id)
135{
136 int l;
137 struct omap_hwmod *oh;
138 struct omap_device *od;
139 char oh_name[MAX_OMAP_I2C_HWMOD_NAME_LEN];
140 struct omap_i2c_bus_platform_data *pdata;
157 141
158 if (!cpu_is_omap44xx()) 142 omap2_i2c_mux_pins(bus_id);
159 irq = omap2_i2c_irq;
160 else
161 irq = omap4_i2c_irq;
162 143
163 if (bus_id == 1) { 144 l = snprintf(oh_name, MAX_OMAP_I2C_HWMOD_NAME_LEN, "i2c%d", bus_id);
164 res[0].start = OMAP2_I2C_BASE1; 145 WARN(l >= MAX_OMAP_I2C_HWMOD_NAME_LEN,
165 res[0].end = res[0].start + OMAP_I2C_SIZE; 146 "String buffer overflow in I2C%d device setup\n", bus_id);
147 oh = omap_hwmod_lookup(oh_name);
148 if (!oh) {
149 pr_err("Could not look up %s\n", oh_name);
150 return -EEXIST;
166 } 151 }
167 152
168 res[1].start = irq[bus_id - 1]; 153 pdata = &i2c_pdata[bus_id - 1];
169 omap2_i2c_mux_pins(bus_id);
170
171 /* 154 /*
172 * When waiting for completion of a i2c transfer, we need to 155 * When waiting for completion of a i2c transfer, we need to
173 * set a wake up latency constraint for the MPU. This is to 156 * set a wake up latency constraint for the MPU. This is to
174 * ensure quick enough wakeup from idle, when transfer 157 * ensure quick enough wakeup from idle, when transfer
175 * completes. 158 * completes.
159 * Only omap3 has support for constraints
176 */ 160 */
177 if (cpu_is_omap34xx()) { 161 if (cpu_is_omap34xx())
178 struct omap_i2c_bus_platform_data *pd; 162 pdata->set_mpu_wkup_lat = omap_pm_set_max_mpu_wakeup_lat_compat;
179 163 od = omap_device_build(name, bus_id, oh, pdata,
180 pd = pdev->dev.platform_data; 164 sizeof(struct omap_i2c_bus_platform_data),
181 pd->set_mpu_wkup_lat = omap_pm_set_max_mpu_wakeup_lat_compat; 165 omap_i2c_latency, ARRAY_SIZE(omap_i2c_latency), 0);
182 } 166 WARN(IS_ERR(od), "Could not build omap_device for %s\n", name);
183 167
184 return platform_device_register(pdev); 168 return PTR_ERR(od);
185} 169}
170#else
171static inline int omap2_i2c_add_bus(int bus_id)
172{
173 return 0;
174}
175#endif
186 176
187static int __init omap_i2c_add_bus(int bus_id) 177static int __init omap_i2c_add_bus(int bus_id)
188{ 178{
189 struct platform_device *pdev;
190
191 pdev = &omap_i2c_devices[bus_id - 1];
192
193 if (cpu_class_is_omap1()) 179 if (cpu_class_is_omap1())
194 return omap1_i2c_add_bus(pdev, bus_id); 180 return omap1_i2c_add_bus(bus_id);
195 else 181 else
196 return omap2_i2c_add_bus(pdev, bus_id); 182 return omap2_i2c_add_bus(bus_id);
197} 183}
198 184
199/** 185/**
diff --git a/arch/arm/plat-omap/include/plat/i2c.h b/arch/arm/plat-omap/include/plat/i2c.h
index 36a0befd6168..878d632c4092 100644
--- a/arch/arm/plat-omap/include/plat/i2c.h
+++ b/arch/arm/plat-omap/include/plat/i2c.h
@@ -36,6 +36,19 @@ static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
36} 36}
37#endif 37#endif
38 38
39/**
40 * i2c_dev_attr - OMAP I2C controller device attributes for omap_hwmod
41 * @fifo_depth: total controller FIFO size (in bytes)
42 * @flags: differences in hardware support capability
43 *
44 * @fifo_depth represents what exists on the hardware, not what is
45 * actually configured at runtime by the device driver.
46 */
47struct omap_i2c_dev_attr {
48 u8 fifo_depth;
49 u8 flags;
50};
51
39void __init omap1_i2c_mux_pins(int bus_id); 52void __init omap1_i2c_mux_pins(int bus_id);
40void __init omap2_i2c_mux_pins(int bus_id); 53void __init omap2_i2c_mux_pins(int bus_id);
41 54
diff --git a/arch/arm/plat-omap/include/plat/l4_3xxx.h b/arch/arm/plat-omap/include/plat/l4_3xxx.h
new file mode 100644
index 000000000000..5e1949375422
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/l4_3xxx.h
@@ -0,0 +1,24 @@
1/*
2 * arch/arm/plat-omap/include/mach/l4_3xxx.h - L4 firewall definitions
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Paul Walmsley
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 */
13#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_L4_3XXX_H
14#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_L4_3XXX_H
15
16/* L4 CORE */
17#define OMAP3_L4_CORE_FW_I2C1_REGION 21
18#define OMAP3_L4_CORE_FW_I2C1_TA_REGION 22
19#define OMAP3_L4_CORE_FW_I2C2_REGION 23
20#define OMAP3_L4_CORE_FW_I2C2_TA_REGION 24
21#define OMAP3_L4_CORE_FW_I2C3_REGION 73
22#define OMAP3_L4_CORE_FW_I2C3_TA_REGION 74
23
24#endif
diff --git a/arch/arm/plat-omap/include/plat/omap-serial.h b/arch/arm/plat-omap/include/plat/omap-serial.h
index c8dae02f0704..b3e0bad9b77e 100644
--- a/arch/arm/plat-omap/include/plat/omap-serial.h
+++ b/arch/arm/plat-omap/include/plat/omap-serial.h
@@ -31,20 +31,8 @@
31 */ 31 */
32#define OMAP_SERIAL_NAME "ttyO" 32#define OMAP_SERIAL_NAME "ttyO"
33 33
34#define OMAP_MDR1_DISABLE 0x07
35#define OMAP_MDR1_MODE13X 0x03
36#define OMAP_MDR1_MODE16X 0x00
37#define OMAP_MODE13X_SPEED 230400 34#define OMAP_MODE13X_SPEED 230400
38 35
39/*
40 * LCR = 0XBF: Switch to Configuration Mode B.
41 * In configuration mode b allow access
42 * to EFR,DLL,DLH.
43 * Reference OMAP TRM Chapter 17
44 * Section: 1.4.3 Mode Selection
45 */
46#define OMAP_UART_LCR_CONF_MDB 0XBF
47
48/* WER = 0x7F 36/* WER = 0x7F
49 * Enable module level wakeup in WER reg 37 * Enable module level wakeup in WER reg
50 */ 38 */
diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h
index 9036e374e0ac..229fbf2cbd26 100644
--- a/arch/arm/plat-omap/include/plat/uncompress.h
+++ b/arch/arm/plat-omap/include/plat/uncompress.h
@@ -145,6 +145,7 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
145 /* omap3 based boards using UART3 */ 145 /* omap3 based boards using UART3 */
146 DEBUG_LL_OMAP3(3, cm_t35); 146 DEBUG_LL_OMAP3(3, cm_t35);
147 DEBUG_LL_OMAP3(3, cm_t3517); 147 DEBUG_LL_OMAP3(3, cm_t3517);
148 DEBUG_LL_OMAP3(3, craneboard);
148 DEBUG_LL_OMAP3(3, igep0020); 149 DEBUG_LL_OMAP3(3, igep0020);
149 DEBUG_LL_OMAP3(3, igep0030); 150 DEBUG_LL_OMAP3(3, igep0030);
150 DEBUG_LL_OMAP3(3, nokia_rx51); 151 DEBUG_LL_OMAP3(3, nokia_rx51);
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
index eac4b978e9fd..fdecd339d4f8 100644
--- a/arch/arm/plat-omap/mcbsp.c
+++ b/arch/arm/plat-omap/mcbsp.c
@@ -755,7 +755,7 @@ int omap_mcbsp_request(unsigned int id)
755 goto err_kfree; 755 goto err_kfree;
756 } 756 }
757 757
758 mcbsp->free = 0; 758 mcbsp->free = false;
759 mcbsp->reg_cache = reg_cache; 759 mcbsp->reg_cache = reg_cache;
760 spin_unlock(&mcbsp->lock); 760 spin_unlock(&mcbsp->lock);
761 761
@@ -815,7 +815,7 @@ err_clk_disable:
815 clk_disable(mcbsp->iclk); 815 clk_disable(mcbsp->iclk);
816 816
817 spin_lock(&mcbsp->lock); 817 spin_lock(&mcbsp->lock);
818 mcbsp->free = 1; 818 mcbsp->free = true;
819 mcbsp->reg_cache = NULL; 819 mcbsp->reg_cache = NULL;
820err_kfree: 820err_kfree:
821 spin_unlock(&mcbsp->lock); 821 spin_unlock(&mcbsp->lock);
@@ -858,7 +858,7 @@ void omap_mcbsp_free(unsigned int id)
858 if (mcbsp->free) 858 if (mcbsp->free)
859 dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id); 859 dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id);
860 else 860 else
861 mcbsp->free = 1; 861 mcbsp->free = true;
862 mcbsp->reg_cache = NULL; 862 mcbsp->reg_cache = NULL;
863 spin_unlock(&mcbsp->lock); 863 spin_unlock(&mcbsp->lock);
864 864
@@ -1771,7 +1771,7 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
1771 1771
1772 spin_lock_init(&mcbsp->lock); 1772 spin_lock_init(&mcbsp->lock);
1773 mcbsp->id = id + 1; 1773 mcbsp->id = id + 1;
1774 mcbsp->free = 1; 1774 mcbsp->free = true;
1775 mcbsp->dma_tx_lch = -1; 1775 mcbsp->dma_tx_lch = -1;
1776 mcbsp->dma_rx_lch = -1; 1776 mcbsp->dma_rx_lch = -1;
1777 1777
@@ -1836,17 +1836,11 @@ static int __devexit omap_mcbsp_remove(struct platform_device *pdev)
1836 1836
1837 omap34xx_device_exit(mcbsp); 1837 omap34xx_device_exit(mcbsp);
1838 1838
1839 clk_disable(mcbsp->fclk);
1840 clk_disable(mcbsp->iclk);
1841 clk_put(mcbsp->fclk); 1839 clk_put(mcbsp->fclk);
1842 clk_put(mcbsp->iclk); 1840 clk_put(mcbsp->iclk);
1843 1841
1844 iounmap(mcbsp->io_base); 1842 iounmap(mcbsp->io_base);
1845 1843 kfree(mcbsp);
1846 mcbsp->fclk = NULL;
1847 mcbsp->iclk = NULL;
1848 mcbsp->free = 0;
1849 mcbsp->dev = NULL;
1850 } 1844 }
1851 1845
1852 return 0; 1846 return 0;
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index e2c8eebe6b3a..93641df487a1 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -270,7 +270,7 @@ void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl)
270 _omap_sram_reprogram_clock(dpllctl, ckctl); 270 _omap_sram_reprogram_clock(dpllctl, ckctl);
271} 271}
272 272
273int __init omap1_sram_init(void) 273static int __init omap1_sram_init(void)
274{ 274{
275 _omap_sram_reprogram_clock = 275 _omap_sram_reprogram_clock =
276 omap_sram_push(omap1_sram_reprogram_clock, 276 omap_sram_push(omap1_sram_reprogram_clock,
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-29 11:38:46 -0500