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-rw-r--r--arch/arm/Kconfig12
-rw-r--r--arch/arm/Makefile3
-rw-r--r--arch/arm/common/sa1111.c8
-rw-r--r--arch/arm/configs/mxs_defconfig129
-rw-r--r--arch/arm/configs/realview-smp_defconfig2
-rw-r--r--arch/arm/configs/realview_defconfig2
-rw-r--r--arch/arm/configs/stmp378x_defconfig128
-rw-r--r--arch/arm/configs/stmp37xx_defconfig108
-rw-r--r--arch/arm/configs/versatile_defconfig2
-rw-r--r--arch/arm/include/asm/dma.h4
-rw-r--r--arch/arm/include/asm/memory.h10
-rw-r--r--arch/arm/include/asm/sizes.h42
-rw-r--r--arch/arm/include/asm/smp.h6
-rw-r--r--arch/arm/kernel/smp.c7
-rw-r--r--arch/arm/mach-davinci/include/mach/memory.h18
-rw-r--r--arch/arm/mach-exynos4/include/mach/smp.h19
-rw-r--r--arch/arm/mach-exynos4/platsmp.c5
-rw-r--r--arch/arm/mach-h720x/include/mach/memory.h3
-rw-r--r--arch/arm/mach-integrator/integrator_ap.c13
-rw-r--r--arch/arm/mach-integrator/integrator_cp.c13
-rw-r--r--arch/arm/mach-ixp4xx/common-pci.c23
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/memory.h12
-rw-r--r--arch/arm/mach-msm/include/mach/smp.h23
-rw-r--r--arch/arm/mach-msm/platsmp.c4
-rw-r--r--arch/arm/mach-mxs/Kconfig10
-rw-r--r--arch/arm/mach-mxs/Makefile1
-rw-r--r--arch/arm/mach-mxs/mach-stmp378x_devb.c120
-rw-r--r--arch/arm/mach-omap1/flash.c2
-rw-r--r--arch/arm/mach-omap2/include/mach/omap4-common.h7
-rw-r--r--arch/arm/mach-omap2/omap-smp.c5
-rw-r--r--arch/arm/mach-pxa/cm-x2xx-pci.c27
-rw-r--r--arch/arm/mach-pxa/hx4700.c2
-rw-r--r--arch/arm/mach-pxa/include/mach/memory.h10
-rw-r--r--arch/arm/mach-pxa/magician.c2
-rw-r--r--arch/arm/mach-realview/core.c50
-rw-r--r--arch/arm/mach-realview/include/mach/memory.h9
-rw-r--r--arch/arm/mach-realview/include/mach/smp.h14
-rw-r--r--arch/arm/mach-realview/platsmp.c3
-rw-r--r--arch/arm/mach-s3c2410/nor-simtec.c2
-rw-r--r--arch/arm/mach-sa1100/include/mach/memory.h12
-rw-r--r--arch/arm/mach-shark/include/mach/memory.h20
-rw-r--r--arch/arm/mach-shmobile/include/mach/smp.h16
-rw-r--r--arch/arm/mach-shmobile/platsmp.c3
-rw-r--r--arch/arm/mach-stmp378x/Makefile2
-rw-r--r--arch/arm/mach-stmp378x/Makefile.boot3
-rw-r--r--arch/arm/mach-stmp378x/include/mach/entry-macro.S35
-rw-r--r--arch/arm/mach-stmp378x/include/mach/irqs.h95
-rw-r--r--arch/arm/mach-stmp378x/include/mach/pins.h151
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-apbh.h101
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-apbx.h119
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-audioin.h63
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-audioout.h104
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-bch.h56
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-clkctrl.h88
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-dcp.h87
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-digctl.h38
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-dram.h27
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-dri.h45
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-ecc8.h39
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-emi.h25
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-gpmi.h78
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-i2c.h55
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-icoll.h45
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-ir.h23
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-lcdif.h195
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-lradc.h99
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-ocotp.h40
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-pinctrl.h90
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-power.h63
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-pwm.h53
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-pxp.h140
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-rtc.h59
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-saif.h21
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-spdif.h49
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-ssp.h102
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-sydma.h23
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-timrot.h68
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-tvenc.h67
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-uartapp.h87
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-uartdbg.h268
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-usbctrl.h40
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-usbphy.h37
-rw-r--r--arch/arm/mach-stmp378x/stmp378x.c299
-rw-r--r--arch/arm/mach-stmp378x/stmp378x.h25
-rw-r--r--arch/arm/mach-stmp378x/stmp378x_devb.c332
-rw-r--r--arch/arm/mach-stmp37xx/Makefile2
-rw-r--r--arch/arm/mach-stmp37xx/Makefile.boot3
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/entry-macro.S37
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/irqs.h99
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/pins.h147
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-apbh.h97
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-apbx.h113
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-audioin.h61
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-audioout.h111
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-clkctrl.h72
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-digctl.h24
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-ecc8.h37
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-gpmi.h63
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-i2c.h55
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-icoll.h43
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-lcdif.h89
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-lradc.h97
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-pinctrl.h88
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-power.h56
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-pwm.h51
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-rtc.h57
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-ssp.h101
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-timrot.h49
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-uartapp.h85
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-uartdbg.h268
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-usbctl.h22
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-usbctrl.h22
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-usbphy.h37
-rw-r--r--arch/arm/mach-stmp37xx/stmp37xx.c219
-rw-r--r--arch/arm/mach-stmp37xx/stmp37xx.h24
-rw-r--r--arch/arm/mach-stmp37xx/stmp37xx_devb.c99
-rw-r--r--arch/arm/mach-tegra/include/mach/smp.h14
-rw-r--r--arch/arm/mach-tegra/platsmp.c3
-rw-r--r--arch/arm/mach-ux500/include/mach/smp.h24
-rw-r--r--arch/arm/mach-ux500/platsmp.c8
-rw-r--r--arch/arm/mach-versatile/core.c31
-rw-r--r--arch/arm/mach-vexpress/ct-ca9x4.c2
-rw-r--r--arch/arm/mach-vexpress/include/mach/smp.h13
-rw-r--r--arch/arm/mach-vexpress/v2m.c22
-rw-r--r--arch/arm/mm/init.c23
-rw-r--r--arch/arm/plat-omap/include/plat/flash.h2
-rw-r--r--arch/arm/plat-omap/include/plat/smp.h36
-rw-r--r--arch/arm/plat-stmp3xxx/Kconfig37
-rw-r--r--arch/arm/plat-stmp3xxx/Makefile5
-rw-r--r--arch/arm/plat-stmp3xxx/clock.c1134
-rw-r--r--arch/arm/plat-stmp3xxx/clock.h61
-rw-r--r--arch/arm/plat-stmp3xxx/core.c128
-rw-r--r--arch/arm/plat-stmp3xxx/devices.c389
-rw-r--r--arch/arm/plat-stmp3xxx/dma.c464
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/clkdev.h18
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/cputype.h33
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/debug-macro.S39
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/dma.h153
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/gpio.h28
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/gpmi.h12
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/hardware.h32
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/io.h25
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/memory.h22
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/mmc.h14
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/pinmux.h157
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/pins.h30
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/platform.h68
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/stmp3xxx.h54
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/system.h49
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/timex.h20
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/uncompress.h53
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/vmalloc.h12
-rw-r--r--arch/arm/plat-stmp3xxx/irq.c50
-rw-r--r--arch/arm/plat-stmp3xxx/pinmux.c550
-rw-r--r--arch/arm/plat-stmp3xxx/timer.c186
-rw-r--r--arch/arm/plat-versatile/platsmp.c3
156 files changed, 379 insertions, 10300 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 903c9c4bd68e..9dd61014864b 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -381,16 +381,6 @@ config ARCH_MXS
381 help 381 help
382 Support for Freescale MXS-based family of processors 382 Support for Freescale MXS-based family of processors
383 383
384config ARCH_STMP3XXX
385 bool "Freescale STMP3xxx"
386 select CPU_ARM926T
387 select CLKDEV_LOOKUP
388 select ARCH_REQUIRE_GPIOLIB
389 select GENERIC_CLOCKEVENTS
390 select USB_ARCH_HAS_EHCI
391 help
392 Support for systems based on the Freescale 3xxx CPUs.
393
394config ARCH_NETX 384config ARCH_NETX
395 bool "Hilscher NetX based" 385 bool "Hilscher NetX based"
396 select CLKSRC_MMIO 386 select CLKSRC_MMIO
@@ -1018,8 +1008,6 @@ source "arch/arm/mach-exynos4/Kconfig"
1018 1008
1019source "arch/arm/mach-shmobile/Kconfig" 1009source "arch/arm/mach-shmobile/Kconfig"
1020 1010
1021source "arch/arm/plat-stmp3xxx/Kconfig"
1022
1023source "arch/arm/mach-tegra/Kconfig" 1011source "arch/arm/mach-tegra/Kconfig"
1024 1012
1025source "arch/arm/mach-u300/Kconfig" 1013source "arch/arm/mach-u300/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index c7d321a3d95d..692c481196bd 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -185,8 +185,6 @@ machine-$(CONFIG_ARCH_EXYNOS4) := exynos4
185machine-$(CONFIG_ARCH_SA1100) := sa1100 185machine-$(CONFIG_ARCH_SA1100) := sa1100
186machine-$(CONFIG_ARCH_SHARK) := shark 186machine-$(CONFIG_ARCH_SHARK) := shark
187machine-$(CONFIG_ARCH_SHMOBILE) := shmobile 187machine-$(CONFIG_ARCH_SHMOBILE) := shmobile
188machine-$(CONFIG_ARCH_STMP378X) := stmp378x
189machine-$(CONFIG_ARCH_STMP37XX) := stmp37xx
190machine-$(CONFIG_ARCH_TCC8K) := tcc8k 188machine-$(CONFIG_ARCH_TCC8K) := tcc8k
191machine-$(CONFIG_ARCH_TEGRA) := tegra 189machine-$(CONFIG_ARCH_TEGRA) := tegra
192machine-$(CONFIG_ARCH_U300) := u300 190machine-$(CONFIG_ARCH_U300) := u300
@@ -207,7 +205,6 @@ machine-$(CONFIG_MACH_SPEAR600) := spear6xx
207plat-$(CONFIG_ARCH_MXC) := mxc 205plat-$(CONFIG_ARCH_MXC) := mxc
208plat-$(CONFIG_ARCH_OMAP) := omap 206plat-$(CONFIG_ARCH_OMAP) := omap
209plat-$(CONFIG_ARCH_S3C64XX) := samsung 207plat-$(CONFIG_ARCH_S3C64XX) := samsung
210plat-$(CONFIG_ARCH_STMP3XXX) := stmp3xxx
211plat-$(CONFIG_ARCH_TCC_926) := tcc 208plat-$(CONFIG_ARCH_TCC_926) := tcc
212plat-$(CONFIG_PLAT_IOP) := iop 209plat-$(CONFIG_PLAT_IOP) := iop
213plat-$(CONFIG_PLAT_NOMADIK) := nomadik 210plat-$(CONFIG_PLAT_NOMADIK) := nomadik
diff --git a/arch/arm/common/sa1111.c b/arch/arm/common/sa1111.c
index a12b33c0dc42..9c49a46a2b7a 100644
--- a/arch/arm/common/sa1111.c
+++ b/arch/arm/common/sa1111.c
@@ -185,14 +185,6 @@ static struct sa1111_dev_info sa1111_devices[] = {
185 }, 185 },
186}; 186};
187 187
188void __init sa1111_adjust_zones(unsigned long *size, unsigned long *holes)
189{
190 unsigned int sz = SZ_1M >> PAGE_SHIFT;
191
192 size[1] = size[0] - sz;
193 size[0] = sz;
194}
195
196/* 188/*
197 * SA1111 interrupt support. Since clearing an IRQ while there are 189 * SA1111 interrupt support. Since clearing an IRQ while there are
198 * active IRQs causes the interrupt output to pulse, the upper levels 190 * active IRQs causes the interrupt output to pulse, the upper levels
diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig
new file mode 100644
index 000000000000..2bf224310fb4
--- /dev/null
+++ b/arch/arm/configs/mxs_defconfig
@@ -0,0 +1,129 @@
1CONFIG_EXPERIMENTAL=y
2CONFIG_SYSVIPC=y
3CONFIG_TASKSTATS=y
4CONFIG_TASK_DELAY_ACCT=y
5CONFIG_TASK_XACCT=y
6CONFIG_TASK_IO_ACCOUNTING=y
7CONFIG_IKCONFIG=y
8CONFIG_IKCONFIG_PROC=y
9# CONFIG_UTS_NS is not set
10# CONFIG_IPC_NS is not set
11# CONFIG_USER_NS is not set
12# CONFIG_PID_NS is not set
13# CONFIG_NET_NS is not set
14CONFIG_PERF_EVENTS=y
15# CONFIG_COMPAT_BRK is not set
16CONFIG_MODULES=y
17CONFIG_MODULE_FORCE_LOAD=y
18CONFIG_MODULE_UNLOAD=y
19CONFIG_MODULE_FORCE_UNLOAD=y
20CONFIG_MODVERSIONS=y
21CONFIG_BLK_DEV_INTEGRITY=y
22# CONFIG_IOSCHED_DEADLINE is not set
23# CONFIG_IOSCHED_CFQ is not set
24CONFIG_ARCH_MXS=y
25CONFIG_MACH_STMP378X_DEVB=y
26CONFIG_MACH_TX28=y
27# CONFIG_ARM_THUMB is not set
28CONFIG_NO_HZ=y
29CONFIG_HIGH_RES_TIMERS=y
30CONFIG_PREEMPT_VOLUNTARY=y
31CONFIG_AEABI=y
32CONFIG_DEFAULT_MMAP_MIN_ADDR=65536
33CONFIG_AUTO_ZRELADDR=y
34CONFIG_FPE_NWFPE=y
35CONFIG_NET=y
36CONFIG_PACKET=y
37CONFIG_UNIX=y
38CONFIG_INET=y
39CONFIG_IP_PNP=y
40CONFIG_IP_PNP_DHCP=y
41CONFIG_SYN_COOKIES=y
42# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
43# CONFIG_INET_XFRM_MODE_TUNNEL is not set
44# CONFIG_INET_XFRM_MODE_BEET is not set
45# CONFIG_INET_LRO is not set
46# CONFIG_INET_DIAG is not set
47# CONFIG_IPV6 is not set
48CONFIG_CAN=m
49CONFIG_CAN_RAW=m
50CONFIG_CAN_BCM=m
51CONFIG_CAN_DEV=m
52CONFIG_CAN_FLEXCAN=m
53# CONFIG_WIRELESS is not set
54CONFIG_DEVTMPFS=y
55# CONFIG_FIRMWARE_IN_KERNEL is not set
56# CONFIG_BLK_DEV is not set
57CONFIG_NETDEVICES=y
58CONFIG_NET_ETHERNET=y
59CONFIG_ENC28J60=y
60# CONFIG_NETDEV_1000 is not set
61# CONFIG_NETDEV_10000 is not set
62# CONFIG_WLAN is not set
63# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
64CONFIG_INPUT_EVDEV=m
65# CONFIG_INPUT_KEYBOARD is not set
66# CONFIG_INPUT_MOUSE is not set
67CONFIG_INPUT_TOUCHSCREEN=y
68CONFIG_TOUCHSCREEN_TSC2007=m
69# CONFIG_SERIO is not set
70CONFIG_VT_HW_CONSOLE_BINDING=y
71CONFIG_DEVPTS_MULTIPLE_INSTANCES=y
72# CONFIG_LEGACY_PTYS is not set
73# CONFIG_DEVKMEM is not set
74CONFIG_SERIAL_AMBA_PL011=y
75CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
76# CONFIG_HW_RANDOM is not set
77CONFIG_I2C=m
78# CONFIG_I2C_COMPAT is not set
79CONFIG_I2C_CHARDEV=m
80CONFIG_I2C_MXS=m
81CONFIG_SPI=y
82CONFIG_SPI_GPIO=m
83CONFIG_DEBUG_GPIO=y
84CONFIG_GPIO_SYSFS=y
85# CONFIG_HWMON is not set
86# CONFIG_MFD_SUPPORT is not set
87CONFIG_DISPLAY_SUPPORT=m
88# CONFIG_HID_SUPPORT is not set
89# CONFIG_USB_SUPPORT is not set
90CONFIG_MMC=y
91CONFIG_MMC_MXS=y
92CONFIG_RTC_CLASS=m
93CONFIG_RTC_DRV_DS1307=m
94CONFIG_DMADEVICES=y
95CONFIG_MXS_DMA=y
96CONFIG_EXT3_FS=y
97# CONFIG_DNOTIFY is not set
98CONFIG_FSCACHE=m
99CONFIG_FSCACHE_STATS=y
100CONFIG_CACHEFILES=m
101CONFIG_TMPFS=y
102CONFIG_TMPFS_POSIX_ACL=y
103# CONFIG_MISC_FILESYSTEMS is not set
104CONFIG_NFS_FS=y
105CONFIG_NFS_V3=y
106CONFIG_NFS_V3_ACL=y
107CONFIG_NFS_V4=y
108CONFIG_ROOT_NFS=y
109CONFIG_PRINTK_TIME=y
110CONFIG_FRAME_WARN=2048
111CONFIG_MAGIC_SYSRQ=y
112CONFIG_UNUSED_SYMBOLS=y
113CONFIG_DEBUG_KERNEL=y
114CONFIG_LOCKUP_DETECTOR=y
115CONFIG_DETECT_HUNG_TASK=y
116CONFIG_TIMER_STATS=y
117CONFIG_PROVE_LOCKING=y
118CONFIG_DEBUG_SPINLOCK_SLEEP=y
119CONFIG_DEBUG_INFO=y
120CONFIG_SYSCTL_SYSCALL_CHECK=y
121CONFIG_BLK_DEV_IO_TRACE=y
122CONFIG_STRICT_DEVMEM=y
123CONFIG_DEBUG_USER=y
124CONFIG_CRYPTO=y
125CONFIG_CRYPTO_CRC32C=m
126# CONFIG_CRYPTO_ANSI_CPRNG is not set
127# CONFIG_CRYPTO_HW is not set
128CONFIG_CRC_ITU_T=m
129CONFIG_CRC7=m
diff --git a/arch/arm/configs/realview-smp_defconfig b/arch/arm/configs/realview-smp_defconfig
index 5ca7a61f7c01..abe61bf379d2 100644
--- a/arch/arm/configs/realview-smp_defconfig
+++ b/arch/arm/configs/realview-smp_defconfig
@@ -38,7 +38,7 @@ CONFIG_MTD_BLOCK=y
38CONFIG_MTD_CFI=y 38CONFIG_MTD_CFI=y
39CONFIG_MTD_CFI_INTELEXT=y 39CONFIG_MTD_CFI_INTELEXT=y
40CONFIG_MTD_CFI_AMDSTD=y 40CONFIG_MTD_CFI_AMDSTD=y
41CONFIG_MTD_ARM_INTEGRATOR=y 41CONFIG_MTD_PHYSMAP=y
42CONFIG_ARM_CHARLCD=y 42CONFIG_ARM_CHARLCD=y
43CONFIG_NETDEVICES=y 43CONFIG_NETDEVICES=y
44CONFIG_SMSC_PHY=y 44CONFIG_SMSC_PHY=y
diff --git a/arch/arm/configs/realview_defconfig b/arch/arm/configs/realview_defconfig
index fcaa60328051..7079cbe898a8 100644
--- a/arch/arm/configs/realview_defconfig
+++ b/arch/arm/configs/realview_defconfig
@@ -37,7 +37,7 @@ CONFIG_MTD_BLOCK=y
37CONFIG_MTD_CFI=y 37CONFIG_MTD_CFI=y
38CONFIG_MTD_CFI_INTELEXT=y 38CONFIG_MTD_CFI_INTELEXT=y
39CONFIG_MTD_CFI_AMDSTD=y 39CONFIG_MTD_CFI_AMDSTD=y
40CONFIG_MTD_ARM_INTEGRATOR=y 40CONFIG_MTD_PHYSMAP=y
41CONFIG_ARM_CHARLCD=y 41CONFIG_ARM_CHARLCD=y
42CONFIG_NETDEVICES=y 42CONFIG_NETDEVICES=y
43CONFIG_SMSC_PHY=y 43CONFIG_SMSC_PHY=y
diff --git a/arch/arm/configs/stmp378x_defconfig b/arch/arm/configs/stmp378x_defconfig
deleted file mode 100644
index 1079c2b6eb3a..000000000000
--- a/arch/arm/configs/stmp378x_defconfig
+++ /dev/null
@@ -1,128 +0,0 @@
1CONFIG_EXPERIMENTAL=y
2CONFIG_LOCALVERSION="-default"
3CONFIG_SYSVIPC=y
4CONFIG_POSIX_MQUEUE=y
5CONFIG_BSD_PROCESS_ACCT=y
6CONFIG_SYSFS_DEPRECATED_V2=y
7CONFIG_BLK_DEV_INITRD=y
8CONFIG_EXPERT=y
9CONFIG_SLAB=y
10CONFIG_MODULES=y
11CONFIG_MODULE_UNLOAD=y
12CONFIG_MODULE_FORCE_UNLOAD=y
13CONFIG_MODVERSIONS=y
14CONFIG_MODULE_SRCVERSION_ALL=y
15# CONFIG_BLK_DEV_BSG is not set
16CONFIG_ARCH_STMP3XXX=y
17CONFIG_ARCH_STMP378X=y
18CONFIG_NO_HZ=y
19CONFIG_HIGH_RES_TIMERS=y
20CONFIG_PREEMPT=y
21CONFIG_AEABI=y
22CONFIG_HIGHMEM=y
23CONFIG_ZBOOT_ROM_TEXT=0x0
24CONFIG_ZBOOT_ROM_BSS=0x0
25CONFIG_CMDLINE="console=ttySDBG0,115200 mem=32M"
26CONFIG_NET=y
27CONFIG_PACKET=y
28CONFIG_UNIX=y
29CONFIG_INET=y
30CONFIG_IP_MULTICAST=y
31CONFIG_IP_ADVANCED_ROUTER=y
32CONFIG_IP_MULTIPLE_TABLES=y
33CONFIG_IP_ROUTE_MULTIPATH=y
34CONFIG_IP_ROUTE_VERBOSE=y
35CONFIG_IP_PNP=y
36CONFIG_IP_PNP_DHCP=y
37CONFIG_IP_PNP_BOOTP=y
38CONFIG_IP_MROUTE=y
39CONFIG_IP_PIMSM_V1=y
40CONFIG_IP_PIMSM_V2=y
41CONFIG_SYN_COOKIES=y
42# CONFIG_INET_LRO is not set
43# CONFIG_IPV6 is not set
44CONFIG_NET_SCHED=y
45# CONFIG_WIRELESS is not set
46CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
47# CONFIG_STANDALONE is not set
48CONFIG_MTD=y
49CONFIG_MTD_CHAR=y
50CONFIG_MTD_NAND=y
51CONFIG_MTD_UBI=y
52CONFIG_MTD_UBI_GLUEBI=y
53CONFIG_BLK_DEV_LOOP=y
54CONFIG_BLK_DEV_CRYPTOLOOP=y
55CONFIG_BLK_DEV_RAM=y
56CONFIG_BLK_DEV_RAM_COUNT=4
57CONFIG_BLK_DEV_RAM_SIZE=6144
58# CONFIG_MISC_DEVICES is not set
59CONFIG_SCSI=y
60CONFIG_BLK_DEV_SD=y
61CONFIG_CHR_DEV_SG=y
62# CONFIG_SCSI_LOWLEVEL is not set
63CONFIG_INPUT_POLLDEV=y
64CONFIG_INPUT_MOUSEDEV_SCREEN_X=320
65CONFIG_INPUT_MOUSEDEV_SCREEN_Y=240
66CONFIG_INPUT_EVDEV=y
67# CONFIG_KEYBOARD_ATKBD is not set
68# CONFIG_INPUT_MOUSE is not set
69CONFIG_INPUT_TOUCHSCREEN=y
70CONFIG_INPUT_MISC=y
71# CONFIG_SERIO_SERPORT is not set
72CONFIG_VT_HW_CONSOLE_BINDING=y
73# CONFIG_LEGACY_PTYS is not set
74CONFIG_HW_RANDOM=y
75CONFIG_DEBUG_GPIO=y
76CONFIG_GPIO_SYSFS=y
77# CONFIG_HWMON is not set
78CONFIG_FB=y
79CONFIG_BACKLIGHT_LCD_SUPPORT=y
80CONFIG_LCD_CLASS_DEVICE=y
81CONFIG_BACKLIGHT_CLASS_DEVICE=y
82# CONFIG_VGA_CONSOLE is not set
83CONFIG_FRAMEBUFFER_CONSOLE=y
84CONFIG_LOGO=y
85# CONFIG_HID_SUPPORT is not set
86# CONFIG_USB_SUPPORT is not set
87# CONFIG_DNOTIFY is not set
88CONFIG_TMPFS=y
89CONFIG_CONFIGFS_FS=m
90# CONFIG_MISC_FILESYSTEMS is not set
91# CONFIG_NETWORK_FILESYSTEMS is not set
92# CONFIG_ENABLE_MUST_CHECK is not set
93CONFIG_STRIP_ASM_SYMS=y
94CONFIG_DEBUG_KERNEL=y
95CONFIG_DEBUG_SHIRQ=y
96# CONFIG_SCHED_DEBUG is not set
97CONFIG_DEBUG_OBJECTS=y
98CONFIG_DEBUG_OBJECTS_SELFTEST=y
99CONFIG_DEBUG_OBJECTS_FREE=y
100CONFIG_DEBUG_OBJECTS_TIMERS=y
101CONFIG_DEBUG_SLAB=y
102CONFIG_DEBUG_SLAB_LEAK=y
103CONFIG_DEBUG_RT_MUTEXES=y
104CONFIG_PROVE_LOCKING=y
105CONFIG_DEBUG_SPINLOCK_SLEEP=y
106CONFIG_DEBUG_KOBJECT=y
107# CONFIG_DEBUG_BUGVERBOSE is not set
108CONFIG_DEBUG_INFO=y
109# CONFIG_RCU_CPU_STALL_DETECTOR is not set
110CONFIG_SYSCTL_SYSCALL_CHECK=y
111CONFIG_BOOT_TRACER=y
112CONFIG_STACK_TRACER=y
113CONFIG_BLK_DEV_IO_TRACE=y
114CONFIG_KEYS=y
115CONFIG_KEYS_DEBUG_PROC_KEYS=y
116CONFIG_SECURITY=y
117CONFIG_CRYPTO_TEST=m
118CONFIG_CRYPTO_ECB=y
119CONFIG_CRYPTO_HMAC=y
120CONFIG_CRYPTO_MD5=y
121CONFIG_CRYPTO_SHA1=m
122CONFIG_CRYPTO_AES=m
123CONFIG_CRYPTO_DES=y
124CONFIG_CRYPTO_DEFLATE=y
125CONFIG_CRYPTO_LZO=y
126# CONFIG_CRYPTO_ANSI_CPRNG is not set
127CONFIG_CRC_CCITT=m
128CONFIG_CRC16=y
diff --git a/arch/arm/configs/stmp37xx_defconfig b/arch/arm/configs/stmp37xx_defconfig
deleted file mode 100644
index 564a5cc44085..000000000000
--- a/arch/arm/configs/stmp37xx_defconfig
+++ /dev/null
@@ -1,108 +0,0 @@
1CONFIG_EXPERIMENTAL=y
2CONFIG_LOCALVERSION="-default"
3CONFIG_SYSVIPC=y
4CONFIG_POSIX_MQUEUE=y
5CONFIG_BSD_PROCESS_ACCT=y
6CONFIG_SYSFS_DEPRECATED_V2=y
7CONFIG_BLK_DEV_INITRD=y
8CONFIG_EXPERT=y
9CONFIG_SLAB=y
10CONFIG_MODULES=y
11CONFIG_MODULE_UNLOAD=y
12CONFIG_MODULE_FORCE_UNLOAD=y
13CONFIG_MODVERSIONS=y
14CONFIG_MODULE_SRCVERSION_ALL=y
15# CONFIG_BLK_DEV_BSG is not set
16CONFIG_ARCH_STMP3XXX=y
17CONFIG_NO_HZ=y
18CONFIG_HIGH_RES_TIMERS=y
19CONFIG_PREEMPT=y
20CONFIG_AEABI=y
21CONFIG_ZBOOT_ROM_TEXT=0x0
22CONFIG_ZBOOT_ROM_BSS=0x0
23CONFIG_CMDLINE="console=ttySDBG0,115200 mem=32M lcd_panel=lms350 rdinit=/bin/sh ignore_loglevel"
24CONFIG_NET=y
25CONFIG_PACKET=y
26CONFIG_UNIX=y
27CONFIG_INET=y
28CONFIG_IP_MULTICAST=y
29CONFIG_IP_ADVANCED_ROUTER=y
30CONFIG_IP_MULTIPLE_TABLES=y
31CONFIG_IP_ROUTE_MULTIPATH=y
32CONFIG_IP_ROUTE_VERBOSE=y
33CONFIG_IP_PNP=y
34CONFIG_IP_PNP_DHCP=y
35CONFIG_IP_PNP_BOOTP=y
36CONFIG_IP_MROUTE=y
37CONFIG_IP_PIMSM_V1=y
38CONFIG_IP_PIMSM_V2=y
39CONFIG_SYN_COOKIES=y
40# CONFIG_INET_LRO is not set
41# CONFIG_IPV6 is not set
42CONFIG_NET_SCHED=y
43# CONFIG_WIRELESS is not set
44CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
45# CONFIG_STANDALONE is not set
46CONFIG_BLK_DEV_LOOP=y
47CONFIG_BLK_DEV_CRYPTOLOOP=y
48CONFIG_BLK_DEV_RAM=y
49CONFIG_BLK_DEV_RAM_COUNT=4
50CONFIG_BLK_DEV_RAM_SIZE=6144
51# CONFIG_MISC_DEVICES is not set
52CONFIG_SCSI=y
53CONFIG_BLK_DEV_SD=y
54CONFIG_CHR_DEV_SG=y
55# CONFIG_SCSI_LOWLEVEL is not set
56CONFIG_INPUT_POLLDEV=y
57CONFIG_INPUT_MOUSEDEV_SCREEN_X=320
58CONFIG_INPUT_MOUSEDEV_SCREEN_Y=240
59CONFIG_INPUT_EVDEV=y
60# CONFIG_KEYBOARD_ATKBD is not set
61# CONFIG_INPUT_MOUSE is not set
62CONFIG_INPUT_TOUCHSCREEN=y
63CONFIG_INPUT_MISC=y
64# CONFIG_SERIO_SERPORT is not set
65CONFIG_VT_HW_CONSOLE_BINDING=y
66# CONFIG_LEGACY_PTYS is not set
67CONFIG_HW_RANDOM=y
68CONFIG_DEBUG_GPIO=y
69CONFIG_GPIO_SYSFS=y
70# CONFIG_HWMON is not set
71CONFIG_FB=y
72CONFIG_BACKLIGHT_LCD_SUPPORT=y
73CONFIG_LCD_CLASS_DEVICE=y
74CONFIG_BACKLIGHT_CLASS_DEVICE=y
75# CONFIG_VGA_CONSOLE is not set
76CONFIG_FRAMEBUFFER_CONSOLE=y
77CONFIG_LOGO=y
78# CONFIG_HID_SUPPORT is not set
79# CONFIG_USB_SUPPORT is not set
80# CONFIG_DNOTIFY is not set
81CONFIG_TMPFS=y
82CONFIG_CONFIGFS_FS=m
83# CONFIG_MISC_FILESYSTEMS is not set
84# CONFIG_NETWORK_FILESYSTEMS is not set
85# CONFIG_ENABLE_MUST_CHECK is not set
86CONFIG_DEBUG_KERNEL=y
87# CONFIG_DEBUG_BUGVERBOSE is not set
88# CONFIG_RCU_CPU_STALL_DETECTOR is not set
89CONFIG_SYSCTL_SYSCALL_CHECK=y
90CONFIG_BOOT_TRACER=y
91CONFIG_STACK_TRACER=y
92CONFIG_BLK_DEV_IO_TRACE=y
93CONFIG_DEBUG_LL=y
94CONFIG_KEYS=y
95CONFIG_KEYS_DEBUG_PROC_KEYS=y
96CONFIG_SECURITY=y
97CONFIG_CRYPTO_TEST=m
98CONFIG_CRYPTO_ECB=y
99CONFIG_CRYPTO_HMAC=y
100CONFIG_CRYPTO_MD5=y
101CONFIG_CRYPTO_SHA1=m
102CONFIG_CRYPTO_AES=m
103CONFIG_CRYPTO_DES=y
104CONFIG_CRYPTO_DEFLATE=y
105CONFIG_CRYPTO_LZO=y
106# CONFIG_CRYPTO_ANSI_CPRNG is not set
107CONFIG_CRC_CCITT=m
108CONFIG_CRC16=y
diff --git a/arch/arm/configs/versatile_defconfig b/arch/arm/configs/versatile_defconfig
index 0ce710f47500..cdd4d2bd3962 100644
--- a/arch/arm/configs/versatile_defconfig
+++ b/arch/arm/configs/versatile_defconfig
@@ -32,7 +32,7 @@ CONFIG_MTD_BLOCK=y
32CONFIG_MTD_CFI=y 32CONFIG_MTD_CFI=y
33CONFIG_MTD_CFI_ADV_OPTIONS=y 33CONFIG_MTD_CFI_ADV_OPTIONS=y
34CONFIG_MTD_CFI_INTELEXT=y 34CONFIG_MTD_CFI_INTELEXT=y
35CONFIG_MTD_ARM_INTEGRATOR=y 35CONFIG_MTD_PHYSMAP=y
36CONFIG_BLK_DEV_RAM=y 36CONFIG_BLK_DEV_RAM=y
37CONFIG_EEPROM_LEGACY=m 37CONFIG_EEPROM_LEGACY=m
38CONFIG_NETDEVICES=y 38CONFIG_NETDEVICES=y
diff --git a/arch/arm/include/asm/dma.h b/arch/arm/include/asm/dma.h
index ca51143f97f1..42005542932b 100644
--- a/arch/arm/include/asm/dma.h
+++ b/arch/arm/include/asm/dma.h
@@ -6,8 +6,10 @@
6/* 6/*
7 * This is the maximum virtual address which can be DMA'd from. 7 * This is the maximum virtual address which can be DMA'd from.
8 */ 8 */
9#ifndef MAX_DMA_ADDRESS 9#ifndef ARM_DMA_ZONE_SIZE
10#define MAX_DMA_ADDRESS 0xffffffff 10#define MAX_DMA_ADDRESS 0xffffffff
11#else
12#define MAX_DMA_ADDRESS (PAGE_OFFSET + ARM_DMA_ZONE_SIZE)
11#endif 13#endif
12 14
13#ifdef CONFIG_ISA_DMA_API 15#ifdef CONFIG_ISA_DMA_API
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index 431077c5a867..af44a8fb3480 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -209,14 +209,10 @@ static inline unsigned long __phys_to_virt(unsigned long x)
209 * allocations. This must be the smallest DMA mask in the system, 209 * allocations. This must be the smallest DMA mask in the system,
210 * so a successful GFP_DMA allocation will always satisfy this. 210 * so a successful GFP_DMA allocation will always satisfy this.
211 */ 211 */
212#ifndef ISA_DMA_THRESHOLD 212#ifndef ARM_DMA_ZONE_SIZE
213#define ISA_DMA_THRESHOLD (0xffffffffULL) 213#define ISA_DMA_THRESHOLD (0xffffffffULL)
214#endif 214#else
215 215#define ISA_DMA_THRESHOLD (PHYS_OFFSET + ARM_DMA_ZONE_SIZE - 1)
216#ifndef arch_adjust_zones
217#define arch_adjust_zones(size,holes) do { } while (0)
218#elif !defined(CONFIG_ZONE_DMA)
219#error "custom arch_adjust_zones() requires CONFIG_ZONE_DMA"
220#endif 216#endif
221 217
222/* 218/*
diff --git a/arch/arm/include/asm/sizes.h b/arch/arm/include/asm/sizes.h
index 316bb2b2be3d..154b89b81d3e 100644
--- a/arch/arm/include/asm/sizes.h
+++ b/arch/arm/include/asm/sizes.h
@@ -16,44 +16,6 @@
16/* Size definitions 16/* Size definitions
17 * Copyright (C) ARM Limited 1998. All rights reserved. 17 * Copyright (C) ARM Limited 1998. All rights reserved.
18 */ 18 */
19#include <asm-generic/sizes.h>
19 20
20#ifndef __sizes_h 21#define SZ_48M (SZ_32M + SZ_16M)
21#define __sizes_h 1
22
23/* handy sizes */
24#define SZ_16 0x00000010
25#define SZ_32 0x00000020
26#define SZ_64 0x00000040
27#define SZ_128 0x00000080
28#define SZ_256 0x00000100
29#define SZ_512 0x00000200
30
31#define SZ_1K 0x00000400
32#define SZ_2K 0x00000800
33#define SZ_4K 0x00001000
34#define SZ_8K 0x00002000
35#define SZ_16K 0x00004000
36#define SZ_32K 0x00008000
37#define SZ_64K 0x00010000
38#define SZ_128K 0x00020000
39#define SZ_256K 0x00040000
40#define SZ_512K 0x00080000
41
42#define SZ_1M 0x00100000
43#define SZ_2M 0x00200000
44#define SZ_4M 0x00400000
45#define SZ_8M 0x00800000
46#define SZ_16M 0x01000000
47#define SZ_32M 0x02000000
48#define SZ_48M 0x03000000
49#define SZ_64M 0x04000000
50#define SZ_128M 0x08000000
51#define SZ_256M 0x10000000
52#define SZ_512M 0x20000000
53
54#define SZ_1G 0x40000000
55#define SZ_2G 0x80000000
56
57#endif
58
59/* END */
diff --git a/arch/arm/include/asm/smp.h b/arch/arm/include/asm/smp.h
index 96ed521f2408..a87664f54f93 100644
--- a/arch/arm/include/asm/smp.h
+++ b/arch/arm/include/asm/smp.h
@@ -14,8 +14,6 @@
14#include <linux/cpumask.h> 14#include <linux/cpumask.h>
15#include <linux/thread_info.h> 15#include <linux/thread_info.h>
16 16
17#include <mach/smp.h>
18
19#ifndef CONFIG_SMP 17#ifndef CONFIG_SMP
20# error "<asm/smp.h> included in non-SMP build" 18# error "<asm/smp.h> included in non-SMP build"
21#endif 19#endif
@@ -47,9 +45,9 @@ extern void smp_init_cpus(void);
47 45
48 46
49/* 47/*
50 * Raise an IPI cross call on CPUs in callmap. 48 * Provide a function to raise an IPI cross call on CPUs in callmap.
51 */ 49 */
52extern void smp_cross_call(const struct cpumask *mask, int ipi); 50extern void set_smp_cross_call(void (*)(const struct cpumask *, unsigned int));
53 51
54/* 52/*
55 * Boot a secondary CPU, and assign it the specified idle task. 53 * Boot a secondary CPU, and assign it the specified idle task.
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 007a0a950e75..d439a8f4c078 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -376,6 +376,13 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
376 } 376 }
377} 377}
378 378
379static void (*smp_cross_call)(const struct cpumask *, unsigned int);
380
381void __init set_smp_cross_call(void (*fn)(const struct cpumask *, unsigned int))
382{
383 smp_cross_call = fn;
384}
385
379void arch_send_call_function_ipi_mask(const struct cpumask *mask) 386void arch_send_call_function_ipi_mask(const struct cpumask *mask)
380{ 387{
381 smp_cross_call(mask, IPI_CALL_FUNC); 388 smp_cross_call(mask, IPI_CALL_FUNC);
diff --git a/arch/arm/mach-davinci/include/mach/memory.h b/arch/arm/mach-davinci/include/mach/memory.h
index 78822723f382..491249ef209c 100644
--- a/arch/arm/mach-davinci/include/mach/memory.h
+++ b/arch/arm/mach-davinci/include/mach/memory.h
@@ -41,27 +41,11 @@
41 */ 41 */
42#define CONSISTENT_DMA_SIZE (14<<20) 42#define CONSISTENT_DMA_SIZE (14<<20)
43 43
44#ifndef __ASSEMBLY__
45/* 44/*
46 * Restrict DMA-able region to workaround silicon bug. The bug 45 * Restrict DMA-able region to workaround silicon bug. The bug
47 * restricts buffers available for DMA to video hardware to be 46 * restricts buffers available for DMA to video hardware to be
48 * below 128M 47 * below 128M
49 */ 48 */
50static inline void 49#define ARM_DMA_ZONE_SIZE SZ_128M
51__arch_adjust_zones(unsigned long *size, unsigned long *holes)
52{
53 unsigned int sz = (128<<20) >> PAGE_SHIFT;
54
55 size[1] = size[0] - sz;
56 size[0] = sz;
57}
58
59#define arch_adjust_zones(zone_size, holes) \
60 if ((meminfo.bank[0].size >> 20) > 128) __arch_adjust_zones(zone_size, holes)
61
62#define ISA_DMA_THRESHOLD (PHYS_OFFSET + (128<<20) - 1)
63#define MAX_DMA_ADDRESS (PAGE_OFFSET + (128<<20))
64
65#endif
66 50
67#endif /* __ASM_ARCH_MEMORY_H */ 51#endif /* __ASM_ARCH_MEMORY_H */
diff --git a/arch/arm/mach-exynos4/include/mach/smp.h b/arch/arm/mach-exynos4/include/mach/smp.h
deleted file mode 100644
index a463dcebcfd3..000000000000
--- a/arch/arm/mach-exynos4/include/mach/smp.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/* linux/arch/arm/mach-exynos4/include/mach/smp.h
2 *
3 * Cloned from arch/arm/mach-realview/include/mach/smp.h
4*/
5
6#ifndef ASM_ARCH_SMP_H
7#define ASM_ARCH_SMP_H __FILE__
8
9#include <asm/hardware/gic.h>
10
11/*
12 * We use IRQ1 as the IPI
13 */
14static inline void smp_cross_call(const struct cpumask *mask, int ipi)
15{
16 gic_raise_softirq(mask, ipi);
17}
18
19#endif
diff --git a/arch/arm/mach-exynos4/platsmp.c b/arch/arm/mach-exynos4/platsmp.c
index 6d35878ec1aa..c5e65a02be8d 100644
--- a/arch/arm/mach-exynos4/platsmp.c
+++ b/arch/arm/mach-exynos4/platsmp.c
@@ -22,6 +22,7 @@
22#include <linux/io.h> 22#include <linux/io.h>
23 23
24#include <asm/cacheflush.h> 24#include <asm/cacheflush.h>
25#include <asm/hardware/gic.h>
25#include <asm/smp_scu.h> 26#include <asm/smp_scu.h>
26#include <asm/unified.h> 27#include <asm/unified.h>
27 28
@@ -104,7 +105,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
104 * the boot monitor to read the system wide flags register, 105 * the boot monitor to read the system wide flags register,
105 * and branch to the address found there. 106 * and branch to the address found there.
106 */ 107 */
107 smp_cross_call(cpumask_of(cpu), 1); 108 gic_raise_softirq(cpumask_of(cpu), 1);
108 109
109 timeout = jiffies + (1 * HZ); 110 timeout = jiffies + (1 * HZ);
110 while (time_before(jiffies, timeout)) { 111 while (time_before(jiffies, timeout)) {
@@ -147,6 +148,8 @@ void __init smp_init_cpus(void)
147 148
148 for (i = 0; i < ncores; i++) 149 for (i = 0; i < ncores; i++)
149 set_cpu_possible(i, true); 150 set_cpu_possible(i, true);
151
152 set_smp_cross_call(gic_raise_softirq);
150} 153}
151 154
152void __init platform_smp_prepare_cpus(unsigned int max_cpus) 155void __init platform_smp_prepare_cpus(unsigned int max_cpus)
diff --git a/arch/arm/mach-h720x/include/mach/memory.h b/arch/arm/mach-h720x/include/mach/memory.h
index 9d3687651462..b0b3baec9acf 100644
--- a/arch/arm/mach-h720x/include/mach/memory.h
+++ b/arch/arm/mach-h720x/include/mach/memory.h
@@ -13,7 +13,6 @@
13 * There should not be more than (0xd0000000 - 0xc0000000) 13 * There should not be more than (0xd0000000 - 0xc0000000)
14 * bytes of RAM. 14 * bytes of RAM.
15 */ 15 */
16#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_256M - 1) 16#define ARM_DMA_ZONE_SIZE SZ_256M
17#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_256M)
18 17
19#endif 18#endif
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index 6b151288f66c..2fbbdd5eac35 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -31,6 +31,7 @@
31#include <linux/clockchips.h> 31#include <linux/clockchips.h>
32#include <linux/interrupt.h> 32#include <linux/interrupt.h>
33#include <linux/io.h> 33#include <linux/io.h>
34#include <linux/mtd/physmap.h>
34 35
35#include <mach/hardware.h> 36#include <mach/hardware.h>
36#include <mach/platform.h> 37#include <mach/platform.h>
@@ -43,7 +44,6 @@
43#include <mach/lm.h> 44#include <mach/lm.h>
44 45
45#include <asm/mach/arch.h> 46#include <asm/mach/arch.h>
46#include <asm/mach/flash.h>
47#include <asm/mach/irq.h> 47#include <asm/mach/irq.h>
48#include <asm/mach/map.h> 48#include <asm/mach/map.h>
49#include <asm/mach/time.h> 49#include <asm/mach/time.h>
@@ -222,7 +222,7 @@ device_initcall(irq_syscore_init);
222#define EBI_CSR1 (VA_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET) 222#define EBI_CSR1 (VA_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET)
223#define EBI_LOCK (VA_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET) 223#define EBI_LOCK (VA_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET)
224 224
225static int ap_flash_init(void) 225static int ap_flash_init(struct platform_device *dev)
226{ 226{
227 u32 tmp; 227 u32 tmp;
228 228
@@ -239,7 +239,7 @@ static int ap_flash_init(void)
239 return 0; 239 return 0;
240} 240}
241 241
242static void ap_flash_exit(void) 242static void ap_flash_exit(struct platform_device *dev)
243{ 243{
244 u32 tmp; 244 u32 tmp;
245 245
@@ -255,15 +255,14 @@ static void ap_flash_exit(void)
255 } 255 }
256} 256}
257 257
258static void ap_flash_set_vpp(int on) 258static void ap_flash_set_vpp(struct platform_device *pdev, int on)
259{ 259{
260 void __iomem *reg = on ? SC_CTRLS : SC_CTRLC; 260 void __iomem *reg = on ? SC_CTRLS : SC_CTRLC;
261 261
262 writel(INTEGRATOR_SC_CTRL_nFLVPPEN, reg); 262 writel(INTEGRATOR_SC_CTRL_nFLVPPEN, reg);
263} 263}
264 264
265static struct flash_platform_data ap_flash_data = { 265static struct physmap_flash_data ap_flash_data = {
266 .map_name = "cfi_probe",
267 .width = 4, 266 .width = 4,
268 .init = ap_flash_init, 267 .init = ap_flash_init,
269 .exit = ap_flash_exit, 268 .exit = ap_flash_exit,
@@ -277,7 +276,7 @@ static struct resource cfi_flash_resource = {
277}; 276};
278 277
279static struct platform_device cfi_flash_device = { 278static struct platform_device cfi_flash_device = {
280 .name = "armflash", 279 .name = "physmap-flash",
281 .id = 0, 280 .id = 0,
282 .dev = { 281 .dev = {
283 .platform_data = &ap_flash_data, 282 .platform_data = &ap_flash_data,
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index c4914c69462b..4eb03ab5cb46 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -22,6 +22,7 @@
22#include <linux/io.h> 22#include <linux/io.h>
23#include <linux/gfp.h> 23#include <linux/gfp.h>
24#include <linux/clkdev.h> 24#include <linux/clkdev.h>
25#include <linux/mtd/physmap.h>
25 26
26#include <mach/hardware.h> 27#include <mach/hardware.h>
27#include <mach/platform.h> 28#include <mach/platform.h>
@@ -35,7 +36,6 @@
35#include <mach/lm.h> 36#include <mach/lm.h>
36 37
37#include <asm/mach/arch.h> 38#include <asm/mach/arch.h>
38#include <asm/mach/flash.h>
39#include <asm/mach/irq.h> 39#include <asm/mach/irq.h>
40#include <asm/mach/map.h> 40#include <asm/mach/map.h>
41#include <asm/mach/time.h> 41#include <asm/mach/time.h>
@@ -246,7 +246,7 @@ static struct clk_lookup cp_lookups[] = {
246/* 246/*
247 * Flash handling. 247 * Flash handling.
248 */ 248 */
249static int intcp_flash_init(void) 249static int intcp_flash_init(struct platform_device *dev)
250{ 250{
251 u32 val; 251 u32 val;
252 252
@@ -257,7 +257,7 @@ static int intcp_flash_init(void)
257 return 0; 257 return 0;
258} 258}
259 259
260static void intcp_flash_exit(void) 260static void intcp_flash_exit(struct platform_device *dev)
261{ 261{
262 u32 val; 262 u32 val;
263 263
@@ -266,7 +266,7 @@ static void intcp_flash_exit(void)
266 writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG); 266 writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
267} 267}
268 268
269static void intcp_flash_set_vpp(int on) 269static void intcp_flash_set_vpp(struct platform_device *pdev, int on)
270{ 270{
271 u32 val; 271 u32 val;
272 272
@@ -278,8 +278,7 @@ static void intcp_flash_set_vpp(int on)
278 writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG); 278 writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
279} 279}
280 280
281static struct flash_platform_data intcp_flash_data = { 281static struct physmap_flash_data intcp_flash_data = {
282 .map_name = "cfi_probe",
283 .width = 4, 282 .width = 4,
284 .init = intcp_flash_init, 283 .init = intcp_flash_init,
285 .exit = intcp_flash_exit, 284 .exit = intcp_flash_exit,
@@ -293,7 +292,7 @@ static struct resource intcp_flash_resource = {
293}; 292};
294 293
295static struct platform_device intcp_flash_device = { 294static struct platform_device intcp_flash_device = {
296 .name = "armflash", 295 .name = "physmap-flash",
297 .id = 0, 296 .id = 0,
298 .dev = { 297 .dev = {
299 .platform_data = &intcp_flash_data, 298 .platform_data = &intcp_flash_data,
diff --git a/arch/arm/mach-ixp4xx/common-pci.c b/arch/arm/mach-ixp4xx/common-pci.c
index a54b3db80366..e9a589395723 100644
--- a/arch/arm/mach-ixp4xx/common-pci.c
+++ b/arch/arm/mach-ixp4xx/common-pci.c
@@ -342,29 +342,6 @@ int dma_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size)
342 return (dev->bus == &pci_bus_type ) && ((dma_addr + size) >= SZ_64M); 342 return (dev->bus == &pci_bus_type ) && ((dma_addr + size) >= SZ_64M);
343} 343}
344 344
345/*
346 * Only first 64MB of memory can be accessed via PCI.
347 * We use GFP_DMA to allocate safe buffers to do map/unmap.
348 * This is really ugly and we need a better way of specifying
349 * DMA-capable regions of memory.
350 */
351void __init ixp4xx_adjust_zones(unsigned long *zone_size,
352 unsigned long *zhole_size)
353{
354 unsigned int sz = SZ_64M >> PAGE_SHIFT;
355
356 /*
357 * Only adjust if > 64M on current system
358 */
359 if (zone_size[0] <= sz)
360 return;
361
362 zone_size[1] = zone_size[0] - sz;
363 zone_size[0] = sz;
364 zhole_size[1] = zhole_size[0];
365 zhole_size[0] = 0;
366}
367
368void __init ixp4xx_pci_preinit(void) 345void __init ixp4xx_pci_preinit(void)
369{ 346{
370 unsigned long cpuid = read_cpuid_id(); 347 unsigned long cpuid = read_cpuid_id();
diff --git a/arch/arm/mach-ixp4xx/include/mach/memory.h b/arch/arm/mach-ixp4xx/include/mach/memory.h
index 6d388c9d0e20..34e79404671a 100644
--- a/arch/arm/mach-ixp4xx/include/mach/memory.h
+++ b/arch/arm/mach-ixp4xx/include/mach/memory.h
@@ -14,16 +14,8 @@
14 */ 14 */
15#define PLAT_PHYS_OFFSET UL(0x00000000) 15#define PLAT_PHYS_OFFSET UL(0x00000000)
16 16
17#if !defined(__ASSEMBLY__) && defined(CONFIG_PCI) 17#ifdef CONFIG_PCI
18 18#define ARM_DMA_ZONE_SIZE SZ_64M
19void ixp4xx_adjust_zones(unsigned long *size, unsigned long *holes);
20
21#define arch_adjust_zones(size, holes) \
22 ixp4xx_adjust_zones(size, holes)
23
24#define ISA_DMA_THRESHOLD (SZ_64M - 1)
25#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_64M)
26
27#endif 19#endif
28 20
29#endif 21#endif
diff --git a/arch/arm/mach-msm/include/mach/smp.h b/arch/arm/mach-msm/include/mach/smp.h
deleted file mode 100644
index 3c01000ecc80..000000000000
--- a/arch/arm/mach-msm/include/mach/smp.h
+++ /dev/null
@@ -1,23 +0,0 @@
1/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#ifndef __ASM_ARCH_MSM_SMP_H
14#define __ASM_ARCH_MSM_SMP_H
15
16#include <asm/hardware/gic.h>
17
18static inline void smp_cross_call(const struct cpumask *mask, int ipi)
19{
20 gic_raise_softirq(mask, ipi);
21}
22
23#endif
diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c
index 0f427bc94447..2034098cf015 100644
--- a/arch/arm/mach-msm/platsmp.c
+++ b/arch/arm/mach-msm/platsmp.c
@@ -119,7 +119,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
119 * the boot monitor to read the system wide flags register, 119 * the boot monitor to read the system wide flags register,
120 * and branch to the address found there. 120 * and branch to the address found there.
121 */ 121 */
122 smp_cross_call(cpumask_of(cpu), 1); 122 gic_raise_softirq(cpumask_of(cpu), 1);
123 123
124 timeout = jiffies + (1 * HZ); 124 timeout = jiffies + (1 * HZ);
125 while (time_before(jiffies, timeout)) { 125 while (time_before(jiffies, timeout)) {
@@ -151,6 +151,8 @@ void __init smp_init_cpus(void)
151 151
152 for (i = 0; i < NR_CPUS; i++) 152 for (i = 0; i < NR_CPUS; i++)
153 set_cpu_possible(i, true); 153 set_cpu_possible(i, true);
154
155 set_smp_cross_call(gic_raise_softirq);
154} 156}
155 157
156void __init platform_smp_prepare_cpus(unsigned int max_cpus) 158void __init platform_smp_prepare_cpus(unsigned int max_cpus)
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
index 4522fbb235d5..edacefac2270 100644
--- a/arch/arm/mach-mxs/Kconfig
+++ b/arch/arm/mach-mxs/Kconfig
@@ -17,6 +17,16 @@ config SOC_IMX28
17 17
18comment "MXS platforms:" 18comment "MXS platforms:"
19 19
20config MACH_STMP378X_DEVB
21 bool "Support STMP378x_devb Platform"
22 select SOC_IMX23
23 select MXS_HAVE_AMBA_DUART
24 select MXS_HAVE_PLATFORM_AUART
25 select MXS_HAVE_PLATFORM_MXS_MMC
26 help
27 Include support for STMP378x-devb platform. This includes specific
28 configurations for the board and its peripherals.
29
20config MACH_MX23EVK 30config MACH_MX23EVK
21 bool "Support MX23EVK Platform" 31 bool "Support MX23EVK Platform"
22 select SOC_IMX23 32 select SOC_IMX23
diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile
index 2f1f6141ca71..58e892376bf2 100644
--- a/arch/arm/mach-mxs/Makefile
+++ b/arch/arm/mach-mxs/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_PM) += pm.o
7obj-$(CONFIG_SOC_IMX23) += clock-mx23.o mm-mx23.o 7obj-$(CONFIG_SOC_IMX23) += clock-mx23.o mm-mx23.o
8obj-$(CONFIG_SOC_IMX28) += clock-mx28.o mm-mx28.o 8obj-$(CONFIG_SOC_IMX28) += clock-mx28.o mm-mx28.o
9 9
10obj-$(CONFIG_MACH_STMP378X_DEVB) += mach-stmp378x_devb.o
10obj-$(CONFIG_MACH_MX23EVK) += mach-mx23evk.o 11obj-$(CONFIG_MACH_MX23EVK) += mach-mx23evk.o
11obj-$(CONFIG_MACH_MX28EVK) += mach-mx28evk.o 12obj-$(CONFIG_MACH_MX28EVK) += mach-mx28evk.o
12obj-$(CONFIG_MODULE_TX28) += module-tx28.o 13obj-$(CONFIG_MODULE_TX28) += module-tx28.o
diff --git a/arch/arm/mach-mxs/mach-stmp378x_devb.c b/arch/arm/mach-mxs/mach-stmp378x_devb.c
new file mode 100644
index 000000000000..7f38d82b69af
--- /dev/null
+++ b/arch/arm/mach-mxs/mach-stmp378x_devb.c
@@ -0,0 +1,120 @@
1/*
2 * board setup for STMP378x-Development-Board
3 *
4 * based on mx23evk board setup and information gained form the original
5 * plat-stmp based board setup, now converted to mach-mxs.
6 *
7 * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
8 * Copyright (C) 2011 Wolfram Sang, Pengutronix e.K.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
19
20#include <linux/platform_device.h>
21#include <linux/gpio.h>
22#include <linux/irq.h>
23#include <linux/spi/spi.h>
24
25#include <asm/mach-types.h>
26#include <asm/mach/arch.h>
27#include <asm/mach/time.h>
28
29#include <mach/common.h>
30#include <mach/iomux-mx23.h>
31
32#include "devices-mx23.h"
33
34#define STMP378X_DEVB_MMC0_WRITE_PROTECT MXS_GPIO_NR(1, 30)
35#define STMP378X_DEVB_MMC0_SLOT_POWER MXS_GPIO_NR(1, 29)
36
37#define STMP378X_DEVB_PAD_AUART (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL)
38
39static const iomux_cfg_t stmp378x_dvb_pads[] __initconst = {
40 /* duart (extended setup missing in old boardcode, too */
41 MX23_PAD_PWM0__DUART_RX,
42 MX23_PAD_PWM1__DUART_TX,
43
44 /* auart */
45 MX23_PAD_AUART1_RX__AUART1_RX | STMP378X_DEVB_PAD_AUART,
46 MX23_PAD_AUART1_TX__AUART1_TX | STMP378X_DEVB_PAD_AUART,
47 MX23_PAD_AUART1_CTS__AUART1_CTS | STMP378X_DEVB_PAD_AUART,
48 MX23_PAD_AUART1_RTS__AUART1_RTS | STMP378X_DEVB_PAD_AUART,
49
50 /* mmc */
51 MX23_PAD_SSP1_DATA0__SSP1_DATA0 |
52 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
53 MX23_PAD_SSP1_DATA1__SSP1_DATA1 |
54 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
55 MX23_PAD_SSP1_DATA2__SSP1_DATA2 |
56 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
57 MX23_PAD_SSP1_DATA3__SSP1_DATA3 |
58 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
59 MX23_PAD_SSP1_CMD__SSP1_CMD |
60 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
61 MX23_PAD_SSP1_DETECT__SSP1_DETECT |
62 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
63 MX23_PAD_SSP1_SCK__SSP1_SCK |
64 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
65 MX23_PAD_PWM4__GPIO_1_30 | MXS_PAD_CTRL, /* write protect */
66 MX23_PAD_PWM3__GPIO_1_29 | MXS_PAD_CTRL, /* power enable */
67};
68
69static struct mxs_mmc_platform_data stmp378x_dvb_mmc_pdata __initdata = {
70 .wp_gpio = STMP378X_DEVB_MMC0_WRITE_PROTECT,
71};
72
73static struct spi_board_info spi_board_info[] __initdata = {
74#if defined(CONFIG_ENC28J60) || defined(CONFIG_ENC28J60_MODULE)
75 {
76 .modalias = "enc28j60",
77 .max_speed_hz = 6 * 1000 * 1000,
78 .bus_num = 1,
79 .chip_select = 0,
80 .platform_data = NULL,
81 },
82#endif
83};
84
85static void __init stmp378x_dvb_init(void)
86{
87 int ret;
88
89 mxs_iomux_setup_multiple_pads(stmp378x_dvb_pads,
90 ARRAY_SIZE(stmp378x_dvb_pads));
91
92 mx23_add_duart();
93 mx23_add_auart0();
94
95 /* power on mmc slot */
96 ret = gpio_request_one(STMP378X_DEVB_MMC0_SLOT_POWER,
97 GPIOF_OUT_INIT_LOW, "mmc0-slot-power");
98 if (ret)
99 pr_warn("could not power mmc (%d)\n", ret);
100
101 mx23_add_mxs_mmc(0, &stmp378x_dvb_mmc_pdata);
102
103 spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
104}
105
106static void __init stmp378x_dvb_timer_init(void)
107{
108 mx23_clocks_init();
109}
110
111static struct sys_timer stmp378x_dvb_timer = {
112 .init = stmp378x_dvb_timer_init,
113};
114
115MACHINE_START(STMP378X, "STMP378X")
116 .map_io = mx23_map_io,
117 .init_irq = mx23_init_irq,
118 .init_machine = stmp378x_dvb_init,
119 .timer = &stmp378x_dvb_timer,
120MACHINE_END
diff --git a/arch/arm/mach-omap1/flash.c b/arch/arm/mach-omap1/flash.c
index acd161666408..1749cb37dda0 100644
--- a/arch/arm/mach-omap1/flash.c
+++ b/arch/arm/mach-omap1/flash.c
@@ -13,7 +13,7 @@
13#include <plat/tc.h> 13#include <plat/tc.h>
14#include <plat/flash.h> 14#include <plat/flash.h>
15 15
16void omap1_set_vpp(struct map_info *map, int enable) 16void omap1_set_vpp(struct platform_device *pdev, int enable)
17{ 17{
18 static int count; 18 static int count;
19 u32 l; 19 u32 l;
diff --git a/arch/arm/mach-omap2/include/mach/omap4-common.h b/arch/arm/mach-omap2/include/mach/omap4-common.h
index de441c05a6a6..e4bd87619734 100644
--- a/arch/arm/mach-omap2/include/mach/omap4-common.h
+++ b/arch/arm/mach-omap2/include/mach/omap4-common.h
@@ -33,4 +33,11 @@ extern void __iomem *gic_dist_base_addr;
33extern void __init gic_init_irq(void); 33extern void __init gic_init_irq(void);
34extern void omap_smc1(u32 fn, u32 arg); 34extern void omap_smc1(u32 fn, u32 arg);
35 35
36#ifdef CONFIG_SMP
37/* Needed for secondary core boot */
38extern void omap_secondary_startup(void);
39extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
40extern void omap_auxcoreboot_addr(u32 cpu_addr);
41extern u32 omap_read_auxcoreboot0(void);
42#endif
36#endif 43#endif
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index b66cfe8bc464..ecfe93c4b585 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -21,6 +21,7 @@
21#include <linux/io.h> 21#include <linux/io.h>
22 22
23#include <asm/cacheflush.h> 23#include <asm/cacheflush.h>
24#include <asm/hardware/gic.h>
24#include <asm/smp_scu.h> 25#include <asm/smp_scu.h>
25#include <mach/hardware.h> 26#include <mach/hardware.h>
26#include <mach/omap4-common.h> 27#include <mach/omap4-common.h>
@@ -63,7 +64,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
63 omap_modify_auxcoreboot0(0x200, 0xfffffdff); 64 omap_modify_auxcoreboot0(0x200, 0xfffffdff);
64 flush_cache_all(); 65 flush_cache_all();
65 smp_wmb(); 66 smp_wmb();
66 smp_cross_call(cpumask_of(cpu), 1); 67 gic_raise_softirq(cpumask_of(cpu), 1);
67 68
68 /* 69 /*
69 * Now the secondary core is starting up let it run its 70 * Now the secondary core is starting up let it run its
@@ -118,6 +119,8 @@ void __init smp_init_cpus(void)
118 119
119 for (i = 0; i < ncores; i++) 120 for (i = 0; i < ncores; i++)
120 set_cpu_possible(i, true); 121 set_cpu_possible(i, true);
122
123 set_smp_cross_call(gic_raise_softirq);
121} 124}
122 125
123void __init platform_smp_prepare_cpus(unsigned int max_cpus) 126void __init platform_smp_prepare_cpus(unsigned int max_cpus)
diff --git a/arch/arm/mach-pxa/cm-x2xx-pci.c b/arch/arm/mach-pxa/cm-x2xx-pci.c
index 8b1a30959fae..1afc0fb7d6d5 100644
--- a/arch/arm/mach-pxa/cm-x2xx-pci.c
+++ b/arch/arm/mach-pxa/cm-x2xx-pci.c
@@ -29,33 +29,6 @@
29unsigned long it8152_base_address; 29unsigned long it8152_base_address;
30static int cmx2xx_it8152_irq_gpio; 30static int cmx2xx_it8152_irq_gpio;
31 31
32/*
33 * Only first 64MB of memory can be accessed via PCI.
34 * We use GFP_DMA to allocate safe buffers to do map/unmap.
35 * This is really ugly and we need a better way of specifying
36 * DMA-capable regions of memory.
37 */
38void __init cmx2xx_pci_adjust_zones(unsigned long *zone_size,
39 unsigned long *zhole_size)
40{
41 unsigned int sz = SZ_64M >> PAGE_SHIFT;
42
43 if (machine_is_armcore()) {
44 pr_info("Adjusting zones for CM-X2XX\n");
45
46 /*
47 * Only adjust if > 64M on current system
48 */
49 if (zone_size[0] <= sz)
50 return;
51
52 zone_size[1] = zone_size[0] - sz;
53 zone_size[0] = sz;
54 zhole_size[1] = zhole_size[0];
55 zhole_size[0] = 0;
56 }
57}
58
59static void cmx2xx_it8152_irq_demux(unsigned int irq, struct irq_desc *desc) 32static void cmx2xx_it8152_irq_demux(unsigned int irq, struct irq_desc *desc)
60{ 33{
61 /* clear our parent irq */ 34 /* clear our parent irq */
diff --git a/arch/arm/mach-pxa/hx4700.c b/arch/arm/mach-pxa/hx4700.c
index 9cdcca597924..f941a495a4a8 100644
--- a/arch/arm/mach-pxa/hx4700.c
+++ b/arch/arm/mach-pxa/hx4700.c
@@ -735,7 +735,7 @@ static struct platform_device bq24022 = {
735 * StrataFlash 735 * StrataFlash
736 */ 736 */
737 737
738static void hx4700_set_vpp(struct map_info *map, int vpp) 738static void hx4700_set_vpp(struct platform_device *pdev, int vpp)
739{ 739{
740 gpio_set_value(GPIO91_HX4700_FLASH_VPEN, vpp); 740 gpio_set_value(GPIO91_HX4700_FLASH_VPEN, vpp);
741} 741}
diff --git a/arch/arm/mach-pxa/include/mach/memory.h b/arch/arm/mach-pxa/include/mach/memory.h
index 7f68724dcc27..07734f37f8fd 100644
--- a/arch/arm/mach-pxa/include/mach/memory.h
+++ b/arch/arm/mach-pxa/include/mach/memory.h
@@ -17,14 +17,8 @@
17 */ 17 */
18#define PLAT_PHYS_OFFSET UL(0xa0000000) 18#define PLAT_PHYS_OFFSET UL(0xa0000000)
19 19
20#if !defined(__ASSEMBLY__) && defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI) 20#if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI)
21void cmx2xx_pci_adjust_zones(unsigned long *size, unsigned long *holes); 21#define ARM_DMA_ZONE_SIZE SZ_64M
22
23#define arch_adjust_zones(size, holes) \
24 cmx2xx_pci_adjust_zones(size, holes)
25
26#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_64M - 1)
27#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_64M)
28#endif 22#endif
29 23
30#endif 24#endif
diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c
index 9984ef70bd79..e1920572948a 100644
--- a/arch/arm/mach-pxa/magician.c
+++ b/arch/arm/mach-pxa/magician.c
@@ -662,7 +662,7 @@ static struct pxaohci_platform_data magician_ohci_info = {
662 * StrataFlash 662 * StrataFlash
663 */ 663 */
664 664
665static void magician_set_vpp(struct map_info *map, int vpp) 665static void magician_set_vpp(struct platform_device *pdev, int vpp)
666{ 666{
667 gpio_set_value(EGPIO_MAGICIAN_FLASH_VPP, vpp); 667 gpio_set_value(EGPIO_MAGICIAN_FLASH_VPP, vpp);
668} 668}
diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c
index 9f5155507d27..5c23450d2d1d 100644
--- a/arch/arm/mach-realview/core.c
+++ b/arch/arm/mach-realview/core.c
@@ -31,6 +31,7 @@
31#include <linux/amba/mmci.h> 31#include <linux/amba/mmci.h>
32#include <linux/gfp.h> 32#include <linux/gfp.h>
33#include <linux/clkdev.h> 33#include <linux/clkdev.h>
34#include <linux/mtd/physmap.h>
34 35
35#include <asm/system.h> 36#include <asm/system.h>
36#include <mach/hardware.h> 37#include <mach/hardware.h>
@@ -41,7 +42,6 @@
41#include <asm/hardware/icst.h> 42#include <asm/hardware/icst.h>
42 43
43#include <asm/mach/arch.h> 44#include <asm/mach/arch.h>
44#include <asm/mach/flash.h>
45#include <asm/mach/irq.h> 45#include <asm/mach/irq.h>
46#include <asm/mach/map.h> 46#include <asm/mach/map.h>
47 47
@@ -56,48 +56,9 @@
56 56
57#include "core.h" 57#include "core.h"
58 58
59#ifdef CONFIG_ZONE_DMA
60/*
61 * Adjust the zones if there are restrictions for DMA access.
62 */
63void __init realview_adjust_zones(unsigned long *size, unsigned long *hole)
64{
65 unsigned long dma_size = SZ_256M >> PAGE_SHIFT;
66
67 if (!machine_is_realview_pbx() || size[0] <= dma_size)
68 return;
69
70 size[ZONE_NORMAL] = size[0] - dma_size;
71 size[ZONE_DMA] = dma_size;
72 hole[ZONE_NORMAL] = hole[0];
73 hole[ZONE_DMA] = 0;
74}
75#endif
76
77
78#define REALVIEW_FLASHCTRL (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET) 59#define REALVIEW_FLASHCTRL (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET)
79 60
80static int realview_flash_init(void) 61static void realview_flash_set_vpp(struct platform_device *pdev, int on)
81{
82 u32 val;
83
84 val = __raw_readl(REALVIEW_FLASHCTRL);
85 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
86 __raw_writel(val, REALVIEW_FLASHCTRL);
87
88 return 0;
89}
90
91static void realview_flash_exit(void)
92{
93 u32 val;
94
95 val = __raw_readl(REALVIEW_FLASHCTRL);
96 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
97 __raw_writel(val, REALVIEW_FLASHCTRL);
98}
99
100static void realview_flash_set_vpp(int on)
101{ 62{
102 u32 val; 63 u32 val;
103 64
@@ -109,16 +70,13 @@ static void realview_flash_set_vpp(int on)
109 __raw_writel(val, REALVIEW_FLASHCTRL); 70 __raw_writel(val, REALVIEW_FLASHCTRL);
110} 71}
111 72
112static struct flash_platform_data realview_flash_data = { 73static struct physmap_flash_data realview_flash_data = {
113 .map_name = "cfi_probe",
114 .width = 4, 74 .width = 4,
115 .init = realview_flash_init,
116 .exit = realview_flash_exit,
117 .set_vpp = realview_flash_set_vpp, 75 .set_vpp = realview_flash_set_vpp,
118}; 76};
119 77
120struct platform_device realview_flash_device = { 78struct platform_device realview_flash_device = {
121 .name = "armflash", 79 .name = "physmap-flash",
122 .id = 0, 80 .id = 0,
123 .dev = { 81 .dev = {
124 .platform_data = &realview_flash_data, 82 .platform_data = &realview_flash_data,
diff --git a/arch/arm/mach-realview/include/mach/memory.h b/arch/arm/mach-realview/include/mach/memory.h
index e05fc2c4c080..1759fa673eea 100644
--- a/arch/arm/mach-realview/include/mach/memory.h
+++ b/arch/arm/mach-realview/include/mach/memory.h
@@ -29,13 +29,8 @@
29#define PLAT_PHYS_OFFSET UL(0x00000000) 29#define PLAT_PHYS_OFFSET UL(0x00000000)
30#endif 30#endif
31 31
32#if !defined(__ASSEMBLY__) && defined(CONFIG_ZONE_DMA) 32#ifdef CONFIG_ZONE_DMA
33extern void realview_adjust_zones(unsigned long *size, unsigned long *hole); 33#define ARM_DMA_ZONE_SIZE SZ_256M
34#define arch_adjust_zones(size, hole) \
35 realview_adjust_zones(size, hole)
36
37#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_256M - 1)
38#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_256M)
39#endif 34#endif
40 35
41#ifdef CONFIG_SPARSEMEM 36#ifdef CONFIG_SPARSEMEM
diff --git a/arch/arm/mach-realview/include/mach/smp.h b/arch/arm/mach-realview/include/mach/smp.h
deleted file mode 100644
index c8221b38ee7c..000000000000
--- a/arch/arm/mach-realview/include/mach/smp.h
+++ /dev/null
@@ -1,14 +0,0 @@
1#ifndef ASMARM_ARCH_SMP_H
2#define ASMARM_ARCH_SMP_H
3
4#include <asm/hardware/gic.h>
5
6/*
7 * We use IRQ1 as the IPI
8 */
9static inline void smp_cross_call(const struct cpumask *mask, int ipi)
10{
11 gic_raise_softirq(mask, ipi);
12}
13
14#endif
diff --git a/arch/arm/mach-realview/platsmp.c b/arch/arm/mach-realview/platsmp.c
index 23919229e12d..963bf0d8119a 100644
--- a/arch/arm/mach-realview/platsmp.c
+++ b/arch/arm/mach-realview/platsmp.c
@@ -14,6 +14,7 @@
14#include <linux/io.h> 14#include <linux/io.h>
15 15
16#include <mach/hardware.h> 16#include <mach/hardware.h>
17#include <asm/hardware/gic.h>
17#include <asm/mach-types.h> 18#include <asm/mach-types.h>
18#include <asm/smp_scu.h> 19#include <asm/smp_scu.h>
19#include <asm/unified.h> 20#include <asm/unified.h>
@@ -61,6 +62,8 @@ void __init smp_init_cpus(void)
61 62
62 for (i = 0; i < ncores; i++) 63 for (i = 0; i < ncores; i++)
63 set_cpu_possible(i, true); 64 set_cpu_possible(i, true);
65
66 set_smp_cross_call(gic_raise_softirq);
64} 67}
65 68
66void __init platform_smp_prepare_cpus(unsigned int max_cpus) 69void __init platform_smp_prepare_cpus(unsigned int max_cpus)
diff --git a/arch/arm/mach-s3c2410/nor-simtec.c b/arch/arm/mach-s3c2410/nor-simtec.c
index 598d130633dc..ad9f750f1e55 100644
--- a/arch/arm/mach-s3c2410/nor-simtec.c
+++ b/arch/arm/mach-s3c2410/nor-simtec.c
@@ -32,7 +32,7 @@
32 32
33#include "nor-simtec.h" 33#include "nor-simtec.h"
34 34
35static void simtec_nor_vpp(struct map_info *map, int vpp) 35static void simtec_nor_vpp(struct platform_device *pdev, int vpp)
36{ 36{
37 unsigned int val; 37 unsigned int val;
38 unsigned long flags; 38 unsigned long flags;
diff --git a/arch/arm/mach-sa1100/include/mach/memory.h b/arch/arm/mach-sa1100/include/mach/memory.h
index a44da6a2916c..cff31ee246b7 100644
--- a/arch/arm/mach-sa1100/include/mach/memory.h
+++ b/arch/arm/mach-sa1100/include/mach/memory.h
@@ -14,18 +14,8 @@
14 */ 14 */
15#define PLAT_PHYS_OFFSET UL(0xc0000000) 15#define PLAT_PHYS_OFFSET UL(0xc0000000)
16 16
17#ifndef __ASSEMBLY__
18
19#ifdef CONFIG_SA1111 17#ifdef CONFIG_SA1111
20void sa1111_adjust_zones(unsigned long *size, unsigned long *holes); 18#define ARM_DMA_ZONE_SIZE SZ_1M
21
22#define arch_adjust_zones(size, holes) \
23 sa1111_adjust_zones(size, holes)
24
25#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_1M - 1)
26#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_1M)
27
28#endif
29#endif 19#endif
30 20
31/* 21/*
diff --git a/arch/arm/mach-shark/include/mach/memory.h b/arch/arm/mach-shark/include/mach/memory.h
index 9afb17000008..4c0831f83b0c 100644
--- a/arch/arm/mach-shark/include/mach/memory.h
+++ b/arch/arm/mach-shark/include/mach/memory.h
@@ -17,25 +17,7 @@
17 */ 17 */
18#define PLAT_PHYS_OFFSET UL(0x08000000) 18#define PLAT_PHYS_OFFSET UL(0x08000000)
19 19
20#ifndef __ASSEMBLY__ 20#define ARM_DMA_ZONE_SIZE SZ_4M
21
22static inline void __arch_adjust_zones(unsigned long *zone_size, unsigned long *zhole_size)
23{
24 /* Only the first 4 MB (=1024 Pages) are usable for DMA */
25 /* See dev / -> .properties in OpenFirmware. */
26 zone_size[1] = zone_size[0] - 1024;
27 zone_size[0] = 1024;
28 zhole_size[1] = zhole_size[0];
29 zhole_size[0] = 0;
30}
31
32#define arch_adjust_zones(size, holes) \
33 __arch_adjust_zones(size, holes)
34
35#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_4M - 1)
36#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_4M)
37
38#endif
39 21
40/* 22/*
41 * Cache flushing area 23 * Cache flushing area
diff --git a/arch/arm/mach-shmobile/include/mach/smp.h b/arch/arm/mach-shmobile/include/mach/smp.h
deleted file mode 100644
index 50db94e927ad..000000000000
--- a/arch/arm/mach-shmobile/include/mach/smp.h
+++ /dev/null
@@ -1,16 +0,0 @@
1#ifndef __MACH_SMP_H
2#define __MACH_SMP_H
3
4#include <asm/hardware/gic.h>
5
6/*
7 * We use IRQ1 as the IPI
8 */
9static inline void smp_cross_call(const struct cpumask *mask, int ipi)
10{
11#if defined(CONFIG_ARM_GIC)
12 gic_raise_softirq(mask, ipi);
13#endif
14}
15
16#endif
diff --git a/arch/arm/mach-shmobile/platsmp.c b/arch/arm/mach-shmobile/platsmp.c
index 65e879bab4dc..f3888feb1c68 100644
--- a/arch/arm/mach-shmobile/platsmp.c
+++ b/arch/arm/mach-shmobile/platsmp.c
@@ -16,6 +16,7 @@
16#include <linux/device.h> 16#include <linux/device.h>
17#include <linux/smp.h> 17#include <linux/smp.h>
18#include <linux/io.h> 18#include <linux/io.h>
19#include <asm/hardware/gic.h>
19#include <asm/localtimer.h> 20#include <asm/localtimer.h>
20#include <asm/mach-types.h> 21#include <asm/mach-types.h>
21#include <mach/common.h> 22#include <mach/common.h>
@@ -57,6 +58,8 @@ void __init smp_init_cpus(void)
57 58
58 for (i = 0; i < ncores; i++) 59 for (i = 0; i < ncores; i++)
59 set_cpu_possible(i, true); 60 set_cpu_possible(i, true);
61
62 set_smp_cross_call(gic_raise_softirq);
60} 63}
61 64
62void __init platform_smp_prepare_cpus(unsigned int max_cpus) 65void __init platform_smp_prepare_cpus(unsigned int max_cpus)
diff --git a/arch/arm/mach-stmp378x/Makefile b/arch/arm/mach-stmp378x/Makefile
deleted file mode 100644
index d156f76b379f..000000000000
--- a/arch/arm/mach-stmp378x/Makefile
+++ /dev/null
@@ -1,2 +0,0 @@
1obj-$(CONFIG_ARCH_STMP378X) += stmp378x.o
2obj-$(CONFIG_MACH_STMP378X) += stmp378x_devb.o
diff --git a/arch/arm/mach-stmp378x/Makefile.boot b/arch/arm/mach-stmp378x/Makefile.boot
deleted file mode 100644
index 1568ad404d59..000000000000
--- a/arch/arm/mach-stmp378x/Makefile.boot
+++ /dev/null
@@ -1,3 +0,0 @@
1 zreladdr-y := 0x40008000
2params_phys-y := 0x40000100
3initrd_phys-y := 0x40800000
diff --git a/arch/arm/mach-stmp378x/include/mach/entry-macro.S b/arch/arm/mach-stmp378x/include/mach/entry-macro.S
deleted file mode 100644
index 731a92286da2..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/entry-macro.S
+++ /dev/null
@@ -1,35 +0,0 @@
1/*
2 * Low-level IRQ helper macros for Freescale STMP378X
3 *
4 * Embedded Alley Solutions, Inc <source@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18
19 .macro disable_fiq
20 .endm
21
22 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
23
24 mov \base, #0xf0000000 @ vm address of IRQ controller
25 ldr \irqnr, [\base, #0x70] @ HW_ICOLL_STAT
26 cmp \irqnr, #0x7f
27 moveqs \irqnr, #0 @ Zero flag set for no IRQ
28
29 .endm
30
31 .macro get_irqnr_preamble, base, tmp
32 .endm
33
34 .macro arch_ret_to_user, tmp1, tmp2
35 .endm
diff --git a/arch/arm/mach-stmp378x/include/mach/irqs.h b/arch/arm/mach-stmp378x/include/mach/irqs.h
deleted file mode 100644
index cc59673becdd..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/irqs.h
+++ /dev/null
@@ -1,95 +0,0 @@
1/*
2 * Freescale STMP378X interrupts
3 *
4 * Copyright (C) 2005 Sigmatel Inc
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18
19#define IRQ_DEBUG_UART 0
20#define IRQ_COMMS_RX 1
21#define IRQ_COMMS_TX 1
22#define IRQ_SSP2_ERROR 2
23#define IRQ_VDD5V 3
24#define IRQ_HEADPHONE_SHORT 4
25#define IRQ_DAC_DMA 5
26#define IRQ_DAC_ERROR 6
27#define IRQ_ADC_DMA 7
28#define IRQ_ADC_ERROR 8
29#define IRQ_SPDIF_DMA 9
30#define IRQ_SAIF2_DMA 9
31#define IRQ_SPDIF_ERROR 10
32#define IRQ_SAIF1_IRQ 10
33#define IRQ_SAIF2_IRQ 10
34#define IRQ_USB_CTRL 11
35#define IRQ_USB_WAKEUP 12
36#define IRQ_GPMI_DMA 13
37#define IRQ_SSP1_DMA 14
38#define IRQ_SSP_ERROR 15
39#define IRQ_GPIO0 16
40#define IRQ_GPIO1 17
41#define IRQ_GPIO2 18
42#define IRQ_SAIF1_DMA 19
43#define IRQ_SSP2_DMA 20
44#define IRQ_ECC8_IRQ 21
45#define IRQ_RTC_ALARM 22
46#define IRQ_UARTAPP_TX_DMA 23
47#define IRQ_UARTAPP_INTERNAL 24
48#define IRQ_UARTAPP_RX_DMA 25
49#define IRQ_I2C_DMA 26
50#define IRQ_I2C_ERROR 27
51#define IRQ_TIMER0 28
52#define IRQ_TIMER1 29
53#define IRQ_TIMER2 30
54#define IRQ_TIMER3 31
55#define IRQ_BATT_BRNOUT 32
56#define IRQ_VDDD_BRNOUT 33
57#define IRQ_VDDIO_BRNOUT 34
58#define IRQ_VDD18_BRNOUT 35
59#define IRQ_TOUCH_DETECT 36
60#define IRQ_LRADC_CH0 37
61#define IRQ_LRADC_CH1 38
62#define IRQ_LRADC_CH2 39
63#define IRQ_LRADC_CH3 40
64#define IRQ_LRADC_CH4 41
65#define IRQ_LRADC_CH5 42
66#define IRQ_LRADC_CH6 43
67#define IRQ_LRADC_CH7 44
68#define IRQ_LCDIF_DMA 45
69#define IRQ_LCDIF_ERROR 46
70#define IRQ_DIGCTL_DEBUG_TRAP 47
71#define IRQ_RTC_1MSEC 48
72#define IRQ_DRI_DMA 49
73#define IRQ_DRI_ATTENTION 50
74#define IRQ_GPMI_ATTENTION 51
75#define IRQ_IR 52
76#define IRQ_DCP_VMI 53
77#define IRQ_DCP 54
78#define IRQ_BCH 56
79#define IRQ_PXP 57
80#define IRQ_UARTAPP2_TX_DMA 58
81#define IRQ_UARTAPP2_INTERNAL 59
82#define IRQ_UARTAPP2_RX_DMA 60
83#define IRQ_VDAC_DETECT 61
84#define IRQ_VDD5V_DROOP 64
85#define IRQ_DCDC4P2_BO 65
86
87
88#define NR_REAL_IRQS 128
89#define NR_IRQS (NR_REAL_IRQS + 32 * 3)
90
91/* All interrupts are FIQ capable */
92#define FIQ_START IRQ_DEBUG_UART
93
94/* Hard disk IRQ is a GPMI attention IRQ */
95#define IRQ_HARDDISK IRQ_GPMI_ATTENTION
diff --git a/arch/arm/mach-stmp378x/include/mach/pins.h b/arch/arm/mach-stmp378x/include/mach/pins.h
deleted file mode 100644
index 93f952d35969..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/pins.h
+++ /dev/null
@@ -1,151 +0,0 @@
1/*
2 * Freescale STMP378X SoC pin multiplexing
3 *
4 * Author: Vladislav Buzov <vbuzov@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#ifndef __ASM_ARCH_PINS_H
19#define __ASM_ARCH_PINS_H
20
21/*
22 * Define all STMP378x pins, a pin name corresponds to a STMP378x hardware
23 * interface this pin belongs to.
24 */
25
26/* Bank 0 */
27#define PINID_GPMI_D00 STMP3XXX_PINID(0, 0)
28#define PINID_GPMI_D01 STMP3XXX_PINID(0, 1)
29#define PINID_GPMI_D02 STMP3XXX_PINID(0, 2)
30#define PINID_GPMI_D03 STMP3XXX_PINID(0, 3)
31#define PINID_GPMI_D04 STMP3XXX_PINID(0, 4)
32#define PINID_GPMI_D05 STMP3XXX_PINID(0, 5)
33#define PINID_GPMI_D06 STMP3XXX_PINID(0, 6)
34#define PINID_GPMI_D07 STMP3XXX_PINID(0, 7)
35#define PINID_GPMI_D08 STMP3XXX_PINID(0, 8)
36#define PINID_GPMI_D09 STMP3XXX_PINID(0, 9)
37#define PINID_GPMI_D10 STMP3XXX_PINID(0, 10)
38#define PINID_GPMI_D11 STMP3XXX_PINID(0, 11)
39#define PINID_GPMI_D12 STMP3XXX_PINID(0, 12)
40#define PINID_GPMI_D13 STMP3XXX_PINID(0, 13)
41#define PINID_GPMI_D14 STMP3XXX_PINID(0, 14)
42#define PINID_GPMI_D15 STMP3XXX_PINID(0, 15)
43#define PINID_GPMI_CLE STMP3XXX_PINID(0, 16)
44#define PINID_GPMI_ALE STMP3XXX_PINID(0, 17)
45#define PINID_GMPI_CE2N STMP3XXX_PINID(0, 18)
46#define PINID_GPMI_RDY0 STMP3XXX_PINID(0, 19)
47#define PINID_GPMI_RDY1 STMP3XXX_PINID(0, 20)
48#define PINID_GPMI_RDY2 STMP3XXX_PINID(0, 21)
49#define PINID_GPMI_RDY3 STMP3XXX_PINID(0, 22)
50#define PINID_GPMI_WPN STMP3XXX_PINID(0, 23)
51#define PINID_GPMI_WRN STMP3XXX_PINID(0, 24)
52#define PINID_GPMI_RDN STMP3XXX_PINID(0, 25)
53#define PINID_AUART1_CTS STMP3XXX_PINID(0, 26)
54#define PINID_AUART1_RTS STMP3XXX_PINID(0, 27)
55#define PINID_AUART1_RX STMP3XXX_PINID(0, 28)
56#define PINID_AUART1_TX STMP3XXX_PINID(0, 29)
57#define PINID_I2C_SCL STMP3XXX_PINID(0, 30)
58#define PINID_I2C_SDA STMP3XXX_PINID(0, 31)
59
60/* Bank 1 */
61#define PINID_LCD_D00 STMP3XXX_PINID(1, 0)
62#define PINID_LCD_D01 STMP3XXX_PINID(1, 1)
63#define PINID_LCD_D02 STMP3XXX_PINID(1, 2)
64#define PINID_LCD_D03 STMP3XXX_PINID(1, 3)
65#define PINID_LCD_D04 STMP3XXX_PINID(1, 4)
66#define PINID_LCD_D05 STMP3XXX_PINID(1, 5)
67#define PINID_LCD_D06 STMP3XXX_PINID(1, 6)
68#define PINID_LCD_D07 STMP3XXX_PINID(1, 7)
69#define PINID_LCD_D08 STMP3XXX_PINID(1, 8)
70#define PINID_LCD_D09 STMP3XXX_PINID(1, 9)
71#define PINID_LCD_D10 STMP3XXX_PINID(1, 10)
72#define PINID_LCD_D11 STMP3XXX_PINID(1, 11)
73#define PINID_LCD_D12 STMP3XXX_PINID(1, 12)
74#define PINID_LCD_D13 STMP3XXX_PINID(1, 13)
75#define PINID_LCD_D14 STMP3XXX_PINID(1, 14)
76#define PINID_LCD_D15 STMP3XXX_PINID(1, 15)
77#define PINID_LCD_D16 STMP3XXX_PINID(1, 16)
78#define PINID_LCD_D17 STMP3XXX_PINID(1, 17)
79#define PINID_LCD_RESET STMP3XXX_PINID(1, 18)
80#define PINID_LCD_RS STMP3XXX_PINID(1, 19)
81#define PINID_LCD_WR STMP3XXX_PINID(1, 20)
82#define PINID_LCD_CS STMP3XXX_PINID(1, 21)
83#define PINID_LCD_DOTCK STMP3XXX_PINID(1, 22)
84#define PINID_LCD_ENABLE STMP3XXX_PINID(1, 23)
85#define PINID_LCD_HSYNC STMP3XXX_PINID(1, 24)
86#define PINID_LCD_VSYNC STMP3XXX_PINID(1, 25)
87#define PINID_PWM0 STMP3XXX_PINID(1, 26)
88#define PINID_PWM1 STMP3XXX_PINID(1, 27)
89#define PINID_PWM2 STMP3XXX_PINID(1, 28)
90#define PINID_PWM3 STMP3XXX_PINID(1, 29)
91#define PINID_PWM4 STMP3XXX_PINID(1, 30)
92
93/* Bank 2 */
94#define PINID_SSP1_CMD STMP3XXX_PINID(2, 0)
95#define PINID_SSP1_DETECT STMP3XXX_PINID(2, 1)
96#define PINID_SSP1_DATA0 STMP3XXX_PINID(2, 2)
97#define PINID_SSP1_DATA1 STMP3XXX_PINID(2, 3)
98#define PINID_SSP1_DATA2 STMP3XXX_PINID(2, 4)
99#define PINID_SSP1_DATA3 STMP3XXX_PINID(2, 5)
100#define PINID_SSP1_SCK STMP3XXX_PINID(2, 6)
101#define PINID_ROTARYA STMP3XXX_PINID(2, 7)
102#define PINID_ROTARYB STMP3XXX_PINID(2, 8)
103#define PINID_EMI_A00 STMP3XXX_PINID(2, 9)
104#define PINID_EMI_A01 STMP3XXX_PINID(2, 10)
105#define PINID_EMI_A02 STMP3XXX_PINID(2, 11)
106#define PINID_EMI_A03 STMP3XXX_PINID(2, 12)
107#define PINID_EMI_A04 STMP3XXX_PINID(2, 13)
108#define PINID_EMI_A05 STMP3XXX_PINID(2, 14)
109#define PINID_EMI_A06 STMP3XXX_PINID(2, 15)
110#define PINID_EMI_A07 STMP3XXX_PINID(2, 16)
111#define PINID_EMI_A08 STMP3XXX_PINID(2, 17)
112#define PINID_EMI_A09 STMP3XXX_PINID(2, 18)
113#define PINID_EMI_A10 STMP3XXX_PINID(2, 19)
114#define PINID_EMI_A11 STMP3XXX_PINID(2, 20)
115#define PINID_EMI_A12 STMP3XXX_PINID(2, 21)
116#define PINID_EMI_BA0 STMP3XXX_PINID(2, 22)
117#define PINID_EMI_BA1 STMP3XXX_PINID(2, 23)
118#define PINID_EMI_CASN STMP3XXX_PINID(2, 24)
119#define PINID_EMI_CE0N STMP3XXX_PINID(2, 25)
120#define PINID_EMI_CE1N STMP3XXX_PINID(2, 26)
121#define PINID_GPMI_CE1N STMP3XXX_PINID(2, 27)
122#define PINID_GPMI_CE0N STMP3XXX_PINID(2, 28)
123#define PINID_EMI_CKE STMP3XXX_PINID(2, 29)
124#define PINID_EMI_RASN STMP3XXX_PINID(2, 30)
125#define PINID_EMI_WEN STMP3XXX_PINID(2, 31)
126
127/* Bank 3 */
128#define PINID_EMI_D00 STMP3XXX_PINID(3, 0)
129#define PINID_EMI_D01 STMP3XXX_PINID(3, 1)
130#define PINID_EMI_D02 STMP3XXX_PINID(3, 2)
131#define PINID_EMI_D03 STMP3XXX_PINID(3, 3)
132#define PINID_EMI_D04 STMP3XXX_PINID(3, 4)
133#define PINID_EMI_D05 STMP3XXX_PINID(3, 5)
134#define PINID_EMI_D06 STMP3XXX_PINID(3, 6)
135#define PINID_EMI_D07 STMP3XXX_PINID(3, 7)
136#define PINID_EMI_D08 STMP3XXX_PINID(3, 8)
137#define PINID_EMI_D09 STMP3XXX_PINID(3, 9)
138#define PINID_EMI_D10 STMP3XXX_PINID(3, 10)
139#define PINID_EMI_D11 STMP3XXX_PINID(3, 11)
140#define PINID_EMI_D12 STMP3XXX_PINID(3, 12)
141#define PINID_EMI_D13 STMP3XXX_PINID(3, 13)
142#define PINID_EMI_D14 STMP3XXX_PINID(3, 14)
143#define PINID_EMI_D15 STMP3XXX_PINID(3, 15)
144#define PINID_EMI_DQM0 STMP3XXX_PINID(3, 16)
145#define PINID_EMI_DQM1 STMP3XXX_PINID(3, 17)
146#define PINID_EMI_DQS0 STMP3XXX_PINID(3, 18)
147#define PINID_EMI_DQS1 STMP3XXX_PINID(3, 19)
148#define PINID_EMI_CLK STMP3XXX_PINID(3, 20)
149#define PINID_EMI_CLKN STMP3XXX_PINID(3, 21)
150
151#endif /* __ASM_ARCH_PINS_H */
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-apbh.h b/arch/arm/mach-stmp378x/include/mach/regs-apbh.h
deleted file mode 100644
index dbcf85b6ac2a..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-apbh.h
+++ /dev/null
@@ -1,101 +0,0 @@
1/*
2 * stmp378x: APBH register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef _MACH_REGS_APBH
22#define _MACH_REGS_APBH
23
24#define REGS_APBH_BASE (STMP3XXX_REGS_BASE + 0x4000)
25#define REGS_APBH_PHYS 0x80004000
26#define REGS_APBH_SIZE 0x2000
27
28#define HW_APBH_CTRL0 0x0
29#define BM_APBH_CTRL0_RESET_CHANNEL 0x00FF0000
30#define BP_APBH_CTRL0_RESET_CHANNEL 16
31#define BM_APBH_CTRL0_CLKGATE 0x40000000
32#define BM_APBH_CTRL0_SFTRST 0x80000000
33
34#define HW_APBH_CTRL1 0x10
35#define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0x00000001
36#define BP_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0
37
38#define HW_APBH_CTRL2 0x20
39
40#define HW_APBH_DEVSEL 0x30
41
42#define HW_APBH_CH0_NXTCMDAR (0x50 + 0 * 0x70)
43#define HW_APBH_CH1_NXTCMDAR (0x50 + 1 * 0x70)
44#define HW_APBH_CH2_NXTCMDAR (0x50 + 2 * 0x70)
45#define HW_APBH_CH3_NXTCMDAR (0x50 + 3 * 0x70)
46#define HW_APBH_CH4_NXTCMDAR (0x50 + 4 * 0x70)
47#define HW_APBH_CH5_NXTCMDAR (0x50 + 5 * 0x70)
48#define HW_APBH_CH6_NXTCMDAR (0x50 + 6 * 0x70)
49#define HW_APBH_CH7_NXTCMDAR (0x50 + 7 * 0x70)
50#define HW_APBH_CH8_NXTCMDAR (0x50 + 8 * 0x70)
51#define HW_APBH_CH9_NXTCMDAR (0x50 + 9 * 0x70)
52#define HW_APBH_CH10_NXTCMDAR (0x50 + 10 * 0x70)
53#define HW_APBH_CH11_NXTCMDAR (0x50 + 11 * 0x70)
54#define HW_APBH_CH12_NXTCMDAR (0x50 + 12 * 0x70)
55#define HW_APBH_CH13_NXTCMDAR (0x50 + 13 * 0x70)
56#define HW_APBH_CH14_NXTCMDAR (0x50 + 14 * 0x70)
57#define HW_APBH_CH15_NXTCMDAR (0x50 + 15 * 0x70)
58
59#define HW_APBH_CHn_NXTCMDAR 0x50
60
61#define BV_APBH_CHn_CMD_COMMAND__NO_DMA_XFER 0
62#define BV_APBH_CHn_CMD_COMMAND__DMA_WRITE 1
63#define BV_APBH_CHn_CMD_COMMAND__DMA_READ 2
64#define BV_APBH_CHn_CMD_COMMAND__DMA_SENSE 3
65#define BM_APBH_CHn_CMD_COMMAND 0x00000003
66#define BP_APBH_CHn_CMD_COMMAND 0
67#define BM_APBH_CHn_CMD_CHAIN 0x00000004
68#define BM_APBH_CHn_CMD_IRQONCMPLT 0x00000008
69#define BM_APBH_CHn_CMD_NANDLOCK 0x00000010
70#define BM_APBH_CHn_CMD_NANDWAIT4READY 0x00000020
71#define BM_APBH_CHn_CMD_SEMAPHORE 0x00000040
72#define BM_APBH_CHn_CMD_WAIT4ENDCMD 0x00000080
73#define BM_APBH_CHn_CMD_CMDWORDS 0x0000F000
74#define BP_APBH_CHn_CMD_CMDWORDS 12
75#define BM_APBH_CHn_CMD_XFER_COUNT 0xFFFF0000
76#define BP_APBH_CHn_CMD_XFER_COUNT 16
77
78#define HW_APBH_CH0_SEMA (0x80 + 0 * 0x70)
79#define HW_APBH_CH1_SEMA (0x80 + 1 * 0x70)
80#define HW_APBH_CH2_SEMA (0x80 + 2 * 0x70)
81#define HW_APBH_CH3_SEMA (0x80 + 3 * 0x70)
82#define HW_APBH_CH4_SEMA (0x80 + 4 * 0x70)
83#define HW_APBH_CH5_SEMA (0x80 + 5 * 0x70)
84#define HW_APBH_CH6_SEMA (0x80 + 6 * 0x70)
85#define HW_APBH_CH7_SEMA (0x80 + 7 * 0x70)
86#define HW_APBH_CH8_SEMA (0x80 + 8 * 0x70)
87#define HW_APBH_CH9_SEMA (0x80 + 9 * 0x70)
88#define HW_APBH_CH10_SEMA (0x80 + 10 * 0x70)
89#define HW_APBH_CH11_SEMA (0x80 + 11 * 0x70)
90#define HW_APBH_CH12_SEMA (0x80 + 12 * 0x70)
91#define HW_APBH_CH13_SEMA (0x80 + 13 * 0x70)
92#define HW_APBH_CH14_SEMA (0x80 + 14 * 0x70)
93#define HW_APBH_CH15_SEMA (0x80 + 15 * 0x70)
94
95#define HW_APBH_CHn_SEMA 0x80
96#define BM_APBH_CHn_SEMA_INCREMENT_SEMA 0x000000FF
97#define BP_APBH_CHn_SEMA_INCREMENT_SEMA 0
98#define BM_APBH_CHn_SEMA_PHORE 0x00FF0000
99#define BP_APBH_CHn_SEMA_PHORE 16
100
101#endif
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-apbx.h b/arch/arm/mach-stmp378x/include/mach/regs-apbx.h
deleted file mode 100644
index 3b934a4d27f0..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-apbx.h
+++ /dev/null
@@ -1,119 +0,0 @@
1/*
2 * stmp378x: APBX register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef _MACH_REGS_APBX
22#define _MACH_REGS_APBX
23
24#define REGS_APBX_BASE (STMP3XXX_REGS_BASE + 0x24000)
25#define REGS_APBX_PHYS 0x80024000
26#define REGS_APBX_SIZE 0x2000
27
28#define HW_APBX_CTRL0 0x0
29#define BM_APBX_CTRL0_CLKGATE 0x40000000
30#define BM_APBX_CTRL0_SFTRST 0x80000000
31
32#define HW_APBX_CTRL1 0x10
33
34#define HW_APBX_CTRL2 0x20
35
36#define HW_APBX_CHANNEL_CTRL 0x30
37#define BM_APBX_CHANNEL_CTRL_RESET_CHANNEL 0xFFFF0000
38#define BP_APBX_CHANNEL_CTRL_RESET_CHANNEL 16
39
40#define HW_APBX_DEVSEL 0x40
41
42#define HW_APBX_CH0_NXTCMDAR (0x110 + 0 * 0x70)
43#define HW_APBX_CH1_NXTCMDAR (0x110 + 1 * 0x70)
44#define HW_APBX_CH2_NXTCMDAR (0x110 + 2 * 0x70)
45#define HW_APBX_CH3_NXTCMDAR (0x110 + 3 * 0x70)
46#define HW_APBX_CH4_NXTCMDAR (0x110 + 4 * 0x70)
47#define HW_APBX_CH5_NXTCMDAR (0x110 + 5 * 0x70)
48#define HW_APBX_CH6_NXTCMDAR (0x110 + 6 * 0x70)
49#define HW_APBX_CH7_NXTCMDAR (0x110 + 7 * 0x70)
50#define HW_APBX_CH8_NXTCMDAR (0x110 + 8 * 0x70)
51#define HW_APBX_CH9_NXTCMDAR (0x110 + 9 * 0x70)
52#define HW_APBX_CH10_NXTCMDAR (0x110 + 10 * 0x70)
53#define HW_APBX_CH11_NXTCMDAR (0x110 + 11 * 0x70)
54#define HW_APBX_CH12_NXTCMDAR (0x110 + 12 * 0x70)
55#define HW_APBX_CH13_NXTCMDAR (0x110 + 13 * 0x70)
56#define HW_APBX_CH14_NXTCMDAR (0x110 + 14 * 0x70)
57#define HW_APBX_CH15_NXTCMDAR (0x110 + 15 * 0x70)
58
59#define HW_APBX_CHn_NXTCMDAR 0x110
60#define BM_APBX_CHn_CMD_COMMAND 0x00000003
61#define BP_APBX_CHn_CMD_COMMAND 0
62#define BV_APBX_CHn_CMD_COMMAND__NO_DMA_XFER 0
63#define BV_APBX_CHn_CMD_COMMAND__DMA_WRITE 1
64#define BV_APBX_CHn_CMD_COMMAND__DMA_READ 2
65#define BV_APBX_CHn_CMD_COMMAND__DMA_SENSE 3
66#define BM_APBX_CHn_CMD_CHAIN 0x00000004
67#define BM_APBX_CHn_CMD_IRQONCMPLT 0x00000008
68#define BM_APBX_CHn_CMD_SEMAPHORE 0x00000040
69#define BM_APBX_CHn_CMD_WAIT4ENDCMD 0x00000080
70#define BM_APBX_CHn_CMD_HALTONTERMINATE 0x00000100
71#define BM_APBX_CHn_CMD_CMDWORDS 0x0000F000
72#define BP_APBX_CHn_CMD_CMDWORDS 12
73#define BM_APBX_CHn_CMD_XFER_COUNT 0xFFFF0000
74#define BP_APBX_CHn_CMD_XFER_COUNT 16
75
76#define HW_APBX_CH0_BAR (0x130 + 0 * 0x70)
77#define HW_APBX_CH1_BAR (0x130 + 1 * 0x70)
78#define HW_APBX_CH2_BAR (0x130 + 2 * 0x70)
79#define HW_APBX_CH3_BAR (0x130 + 3 * 0x70)
80#define HW_APBX_CH4_BAR (0x130 + 4 * 0x70)
81#define HW_APBX_CH5_BAR (0x130 + 5 * 0x70)
82#define HW_APBX_CH6_BAR (0x130 + 6 * 0x70)
83#define HW_APBX_CH7_BAR (0x130 + 7 * 0x70)
84#define HW_APBX_CH8_BAR (0x130 + 8 * 0x70)
85#define HW_APBX_CH9_BAR (0x130 + 9 * 0x70)
86#define HW_APBX_CH10_BAR (0x130 + 10 * 0x70)
87#define HW_APBX_CH11_BAR (0x130 + 11 * 0x70)
88#define HW_APBX_CH12_BAR (0x130 + 12 * 0x70)
89#define HW_APBX_CH13_BAR (0x130 + 13 * 0x70)
90#define HW_APBX_CH14_BAR (0x130 + 14 * 0x70)
91#define HW_APBX_CH15_BAR (0x130 + 15 * 0x70)
92
93#define HW_APBX_CHn_BAR 0x130
94
95#define HW_APBX_CH0_SEMA (0x140 + 0 * 0x70)
96#define HW_APBX_CH1_SEMA (0x140 + 1 * 0x70)
97#define HW_APBX_CH2_SEMA (0x140 + 2 * 0x70)
98#define HW_APBX_CH3_SEMA (0x140 + 3 * 0x70)
99#define HW_APBX_CH4_SEMA (0x140 + 4 * 0x70)
100#define HW_APBX_CH5_SEMA (0x140 + 5 * 0x70)
101#define HW_APBX_CH6_SEMA (0x140 + 6 * 0x70)
102#define HW_APBX_CH7_SEMA (0x140 + 7 * 0x70)
103#define HW_APBX_CH8_SEMA (0x140 + 8 * 0x70)
104#define HW_APBX_CH9_SEMA (0x140 + 9 * 0x70)
105#define HW_APBX_CH10_SEMA (0x140 + 10 * 0x70)
106#define HW_APBX_CH11_SEMA (0x140 + 11 * 0x70)
107#define HW_APBX_CH12_SEMA (0x140 + 12 * 0x70)
108#define HW_APBX_CH13_SEMA (0x140 + 13 * 0x70)
109#define HW_APBX_CH14_SEMA (0x140 + 14 * 0x70)
110#define HW_APBX_CH15_SEMA (0x140 + 15 * 0x70)
111
112#define HW_APBX_CHn_SEMA 0x140
113#define BM_APBX_CHn_SEMA_INCREMENT_SEMA 0x000000FF
114#define BP_APBX_CHn_SEMA_INCREMENT_SEMA 0
115#define BM_APBX_CHn_SEMA_PHORE 0x00FF0000
116#define BP_APBX_CHn_SEMA_PHORE 16
117
118#endif
119
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-audioin.h b/arch/arm/mach-stmp378x/include/mach/regs-audioin.h
deleted file mode 100644
index 641ac6126f83..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-audioin.h
+++ /dev/null
@@ -1,63 +0,0 @@
1/*
2 * stmp378x: AUDIOIN register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_AUDIOIN_BASE (STMP3XXX_REGS_BASE + 0x4C000)
22#define REGS_AUDIOIN_PHYS 0x8004C000
23#define REGS_AUDIOIN_SIZE 0x2000
24
25#define HW_AUDIOIN_CTRL 0x0
26#define BM_AUDIOIN_CTRL_RUN 0x00000001
27#define BP_AUDIOIN_CTRL_RUN 0
28#define BM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN 0x00000002
29#define BM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ 0x00000004
30#define BM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008
31#define BM_AUDIOIN_CTRL_WORD_LENGTH 0x00000020
32#define BM_AUDIOIN_CTRL_CLKGATE 0x40000000
33#define BM_AUDIOIN_CTRL_SFTRST 0x80000000
34
35#define HW_AUDIOIN_STAT 0x10
36
37#define HW_AUDIOIN_ADCSRR 0x20
38
39#define HW_AUDIOIN_ADCVOLUME 0x30
40#define BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0x000000FF
41#define BP_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0
42#define BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT 0x00FF0000
43#define BP_AUDIOIN_ADCVOLUME_VOLUME_LEFT 16
44
45#define HW_AUDIOIN_ADCDEBUG 0x40
46
47#define HW_AUDIOIN_ADCVOL 0x50
48#define BM_AUDIOIN_ADCVOL_GAIN_RIGHT 0x0000000F
49#define BP_AUDIOIN_ADCVOL_GAIN_RIGHT 0
50#define BM_AUDIOIN_ADCVOL_SELECT_RIGHT 0x00000030
51#define BP_AUDIOIN_ADCVOL_SELECT_RIGHT 4
52#define BM_AUDIOIN_ADCVOL_GAIN_LEFT 0x00000F00
53#define BP_AUDIOIN_ADCVOL_GAIN_LEFT 8
54#define BM_AUDIOIN_ADCVOL_SELECT_LEFT 0x00003000
55#define BP_AUDIOIN_ADCVOL_SELECT_LEFT 12
56#define BM_AUDIOIN_ADCVOL_MUTE 0x01000000
57
58#define HW_AUDIOIN_MICLINE 0x60
59
60#define HW_AUDIOIN_ANACLKCTRL 0x70
61#define BM_AUDIOIN_ANACLKCTRL_CLKGATE 0x80000000
62
63#define HW_AUDIOIN_DATA 0x80
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-audioout.h b/arch/arm/mach-stmp378x/include/mach/regs-audioout.h
deleted file mode 100644
index f533e23694a0..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-audioout.h
+++ /dev/null
@@ -1,104 +0,0 @@
1/*
2 * stmp378x: AUDIOOUT register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_AUDIOOUT_BASE (STMP3XXX_REGS_BASE + 0x48000)
22#define REGS_AUDIOOUT_PHYS 0x80048000
23#define REGS_AUDIOOUT_SIZE 0x2000
24
25#define HW_AUDIOOUT_CTRL 0x0
26#define BM_AUDIOOUT_CTRL_RUN 0x00000001
27#define BP_AUDIOOUT_CTRL_RUN 0
28#define BM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN 0x00000002
29#define BM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ 0x00000004
30#define BM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008
31#define BM_AUDIOOUT_CTRL_WORD_LENGTH 0x00000040
32#define BM_AUDIOOUT_CTRL_CLKGATE 0x40000000
33#define BM_AUDIOOUT_CTRL_SFTRST 0x80000000
34
35#define HW_AUDIOOUT_STAT 0x10
36
37#define HW_AUDIOOUT_DACSRR 0x20
38#define BM_AUDIOOUT_DACSRR_SRC_FRAC 0x00001FFF
39#define BP_AUDIOOUT_DACSRR_SRC_FRAC 0
40#define BM_AUDIOOUT_DACSRR_SRC_INT 0x001F0000
41#define BP_AUDIOOUT_DACSRR_SRC_INT 16
42#define BM_AUDIOOUT_DACSRR_SRC_HOLD 0x07000000
43#define BP_AUDIOOUT_DACSRR_SRC_HOLD 24
44#define BM_AUDIOOUT_DACSRR_BASEMULT 0x70000000
45#define BP_AUDIOOUT_DACSRR_BASEMULT 28
46
47#define HW_AUDIOOUT_DACVOLUME 0x30
48#define BM_AUDIOOUT_DACVOLUME_MUTE_RIGHT 0x00000100
49#define BM_AUDIOOUT_DACVOLUME_MUTE_LEFT 0x01000000
50#define BM_AUDIOOUT_DACVOLUME_EN_ZCD 0x02000000
51
52#define HW_AUDIOOUT_DACDEBUG 0x40
53
54#define HW_AUDIOOUT_HPVOL 0x50
55#define BM_AUDIOOUT_HPVOL_MUTE 0x01000000
56#define BM_AUDIOOUT_HPVOL_EN_MSTR_ZCD 0x02000000
57
58#define HW_AUDIOOUT_PWRDN 0x70
59#define BM_AUDIOOUT_PWRDN_HEADPHONE 0x00000001
60#define BP_AUDIOOUT_PWRDN_HEADPHONE 0
61#define BM_AUDIOOUT_PWRDN_CAPLESS 0x00000010
62#define BM_AUDIOOUT_PWRDN_ADC 0x00000100
63#define BM_AUDIOOUT_PWRDN_DAC 0x00001000
64#define BM_AUDIOOUT_PWRDN_RIGHT_ADC 0x00010000
65#define BM_AUDIOOUT_PWRDN_SPEAKER 0x01000000
66
67#define HW_AUDIOOUT_REFCTRL 0x80
68#define BM_AUDIOOUT_REFCTRL_VAG_VAL 0x000000F0
69#define BP_AUDIOOUT_REFCTRL_VAG_VAL 4
70#define BM_AUDIOOUT_REFCTRL_ADC_REFVAL 0x00000F00
71#define BP_AUDIOOUT_REFCTRL_ADC_REFVAL 8
72#define BM_AUDIOOUT_REFCTRL_ADJ_VAG 0x00001000
73#define BM_AUDIOOUT_REFCTRL_ADJ_ADC 0x00002000
74#define BM_AUDIOOUT_REFCTRL_BIAS_CTRL 0x00030000
75#define BP_AUDIOOUT_REFCTRL_BIAS_CTRL 16
76#define BM_AUDIOOUT_REFCTRL_LOW_PWR 0x00080000
77#define BM_AUDIOOUT_REFCTRL_VBG_ADJ 0x00700000
78#define BP_AUDIOOUT_REFCTRL_VBG_ADJ 20
79#define BM_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS 0x01000000
80#define BM_AUDIOOUT_REFCTRL_RAISE_REF 0x02000000
81
82#define HW_AUDIOOUT_ANACTRL 0x90
83#define BM_AUDIOOUT_ANACTRL_HP_CLASSAB 0x00000010
84#define BM_AUDIOOUT_ANACTRL_HP_HOLD_GND 0x00000020
85
86#define HW_AUDIOOUT_TEST 0xA0
87#define BM_AUDIOOUT_TEST_HP_I1_ADJ 0x00C00000
88#define BP_AUDIOOUT_TEST_HP_I1_ADJ 22
89
90#define HW_AUDIOOUT_BISTCTRL 0xB0
91
92#define HW_AUDIOOUT_BISTSTAT0 0xC0
93
94#define HW_AUDIOOUT_BISTSTAT1 0xD0
95
96#define HW_AUDIOOUT_ANACLKCTRL 0xE0
97#define BM_AUDIOOUT_ANACLKCTRL_CLKGATE 0x80000000
98
99#define HW_AUDIOOUT_DATA 0xF0
100
101#define HW_AUDIOOUT_SPEAKERCTRL 0x100
102#define BM_AUDIOOUT_SPEAKERCTRL_MUTE 0x01000000
103
104#define HW_AUDIOOUT_VERSION 0x200
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-bch.h b/arch/arm/mach-stmp378x/include/mach/regs-bch.h
deleted file mode 100644
index 532d24650717..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-bch.h
+++ /dev/null
@@ -1,56 +0,0 @@
1/*
2 * stmp378x: BCH register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_BCH_BASE (STMP3XXX_REGS_BASE + 0xA000)
22#define REGS_BCH_PHYS 0x8000A000
23#define REGS_BCH_SIZE 0x2000
24
25#define HW_BCH_CTRL 0x0
26#define BM_BCH_CTRL_COMPLETE_IRQ 0x00000001
27#define BP_BCH_CTRL_COMPLETE_IRQ 0
28#define BM_BCH_CTRL_COMPLETE_IRQ_EN 0x00000100
29
30#define HW_BCH_STATUS0 0x10
31#define BM_BCH_STATUS0_UNCORRECTABLE 0x00000004
32#define BM_BCH_STATUS0_CORRECTED 0x00000008
33#define BM_BCH_STATUS0_STATUS_BLK0 0x0000FF00
34#define BP_BCH_STATUS0_STATUS_BLK0 8
35#define BM_BCH_STATUS0_COMPLETED_CE 0x000F0000
36#define BP_BCH_STATUS0_COMPLETED_CE 16
37
38#define HW_BCH_LAYOUTSELECT 0x70
39
40#define HW_BCH_FLASH0LAYOUT0 0x80
41#define BM_BCH_FLASH0LAYOUT0_DATA0_SIZE 0x00000FFF
42#define BP_BCH_FLASH0LAYOUT0_DATA0_SIZE 0
43#define BM_BCH_FLASH0LAYOUT0_ECC0 0x0000F000
44#define BP_BCH_FLASH0LAYOUT0_ECC0 12
45#define BM_BCH_FLASH0LAYOUT0_META_SIZE 0x00FF0000
46#define BP_BCH_FLASH0LAYOUT0_META_SIZE 16
47#define BM_BCH_FLASH0LAYOUT0_NBLOCKS 0xFF000000
48#define BP_BCH_FLASH0LAYOUT0_NBLOCKS 24
49#define BM_BCH_FLASH0LAYOUT1_DATAN_SIZE 0x00000FFF
50#define BP_BCH_FLASH0LAYOUT1_DATAN_SIZE 0
51#define BM_BCH_FLASH0LAYOUT1_ECCN 0x0000F000
52#define BP_BCH_FLASH0LAYOUT1_ECCN 12
53#define BM_BCH_FLASH0LAYOUT1_PAGE_SIZE 0xFFFF0000
54#define BP_BCH_FLASH0LAYOUT1_PAGE_SIZE 16
55
56#define HW_BCH_BLOCKNAME 0x150
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-clkctrl.h b/arch/arm/mach-stmp378x/include/mach/regs-clkctrl.h
deleted file mode 100644
index 7c546afd57a3..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-clkctrl.h
+++ /dev/null
@@ -1,88 +0,0 @@
1/*
2 * stmp378x: CLKCTRL register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef _MACH_REGS_CLKCTRL
22#define _MACH_REGS_CLKCTRL
23
24#define REGS_CLKCTRL_BASE (STMP3XXX_REGS_BASE + 0x40000)
25#define REGS_CLKCTRL_PHYS 0x80040000
26#define REGS_CLKCTRL_SIZE 0x2000
27
28#define HW_CLKCTRL_PLLCTRL0 0x0
29#define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x00040000
30
31#define HW_CLKCTRL_CPU 0x20
32#define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F
33#define BP_CLKCTRL_CPU_DIV_CPU 0
34
35#define HW_CLKCTRL_HBUS 0x30
36#define BM_CLKCTRL_HBUS_DIV 0x0000001F
37#define BP_CLKCTRL_HBUS_DIV 0
38#define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0x00000020
39
40#define HW_CLKCTRL_XBUS 0x40
41
42#define HW_CLKCTRL_XTAL 0x50
43#define BM_CLKCTRL_XTAL_DRI_CLK24M_GATE 0x10000000
44
45#define HW_CLKCTRL_PIX 0x60
46#define BM_CLKCTRL_PIX_DIV 0x00000FFF
47#define BP_CLKCTRL_PIX_DIV 0
48#define BM_CLKCTRL_PIX_CLKGATE 0x80000000
49
50#define HW_CLKCTRL_SSP 0x70
51
52#define HW_CLKCTRL_GPMI 0x80
53
54#define HW_CLKCTRL_SPDIF 0x90
55
56#define HW_CLKCTRL_EMI 0xA0
57#define BM_CLKCTRL_EMI_DIV_EMI 0x0000003F
58#define BP_CLKCTRL_EMI_DIV_EMI 0
59#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE 0x00010000
60#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x00020000
61#define BM_CLKCTRL_EMI_BUSY_REF_EMI 0x10000000
62#define BM_CLKCTRL_EMI_BUSY_REF_XTAL 0x20000000
63
64#define HW_CLKCTRL_IR 0xB0
65
66#define HW_CLKCTRL_SAIF 0xC0
67
68#define HW_CLKCTRL_TV 0xD0
69
70#define HW_CLKCTRL_ETM 0xE0
71
72#define HW_CLKCTRL_FRAC 0xF0
73#define BM_CLKCTRL_FRAC_EMIFRAC 0x00003F00
74#define BP_CLKCTRL_FRAC_EMIFRAC 8
75#define BM_CLKCTRL_FRAC_PIXFRAC 0x003F0000
76#define BP_CLKCTRL_FRAC_PIXFRAC 16
77#define BM_CLKCTRL_FRAC_CLKGATEPIX 0x00800000
78
79#define HW_CLKCTRL_FRAC1 0x100
80
81#define HW_CLKCTRL_CLKSEQ 0x110
82#define BM_CLKCTRL_CLKSEQ_BYPASS_PIX 0x00000002
83
84#define HW_CLKCTRL_RESET 0x120
85#define BM_CLKCTRL_RESET_DIG 0x00000001
86#define BP_CLKCTRL_RESET_DIG 0
87
88#endif
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-dcp.h b/arch/arm/mach-stmp378x/include/mach/regs-dcp.h
deleted file mode 100644
index fdedd00c0e28..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-dcp.h
+++ /dev/null
@@ -1,87 +0,0 @@
1/*
2 * stmp378x: DCP register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_DCP_BASE (STMP3XXX_REGS_BASE + 0x28000)
22#define REGS_DCP_PHYS 0x80028000
23#define REGS_DCP_SIZE 0x2000
24
25#define HW_DCP_CTRL 0x0
26#define BM_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE 0x000000FF
27#define BP_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE 0
28#define BM_DCP_CTRL_ENABLE_CONTEXT_CACHING 0x00400000
29#define BM_DCP_CTRL_GATHER_RESIDUAL_WRITES 0x00800000
30#define BM_DCP_CTRL_CLKGATE 0x40000000
31#define BM_DCP_CTRL_SFTRST 0x80000000
32
33#define HW_DCP_STAT 0x10
34#define BM_DCP_STAT_IRQ 0x0000000F
35#define BP_DCP_STAT_IRQ 0
36
37#define HW_DCP_CHANNELCTRL 0x20
38#define BM_DCP_CHANNELCTRL_ENABLE_CHANNEL 0x000000FF
39#define BP_DCP_CHANNELCTRL_ENABLE_CHANNEL 0
40
41#define HW_DCP_CONTEXT 0x50
42#define BM_DCP_PACKET1_INTERRUPT 0x00000001
43#define BP_DCP_PACKET1_INTERRUPT 0
44#define BM_DCP_PACKET1_DECR_SEMAPHORE 0x00000002
45#define BM_DCP_PACKET1_CHAIN 0x00000004
46#define BM_DCP_PACKET1_CHAIN_CONTIGUOUS 0x00000008
47#define BM_DCP_PACKET1_ENABLE_CIPHER 0x00000020
48#define BM_DCP_PACKET1_ENABLE_HASH 0x00000040
49#define BM_DCP_PACKET1_CIPHER_ENCRYPT 0x00000100
50#define BM_DCP_PACKET1_CIPHER_INIT 0x00000200
51#define BM_DCP_PACKET1_OTP_KEY 0x00000400
52#define BM_DCP_PACKET1_PAYLOAD_KEY 0x00000800
53#define BM_DCP_PACKET1_HASH_INIT 0x00001000
54#define BM_DCP_PACKET1_HASH_TERM 0x00002000
55#define BM_DCP_PACKET2_CIPHER_SELECT 0x0000000F
56#define BP_DCP_PACKET2_CIPHER_SELECT 0
57#define BM_DCP_PACKET2_CIPHER_MODE 0x000000F0
58#define BP_DCP_PACKET2_CIPHER_MODE 4
59#define BM_DCP_PACKET2_KEY_SELECT 0x0000FF00
60#define BP_DCP_PACKET2_KEY_SELECT 8
61#define BM_DCP_PACKET2_HASH_SELECT 0x000F0000
62#define BP_DCP_PACKET2_HASH_SELECT 16
63#define BM_DCP_PACKET2_CIPHER_CFG 0xFF000000
64#define BP_DCP_PACKET2_CIPHER_CFG 24
65
66#define HW_DCP_CH0CMDPTR (0x100 + 0 * 0x40)
67#define HW_DCP_CH1CMDPTR (0x100 + 1 * 0x40)
68#define HW_DCP_CH2CMDPTR (0x100 + 2 * 0x40)
69#define HW_DCP_CH3CMDPTR (0x100 + 3 * 0x40)
70
71#define HW_DCP_CHnCMDPTR 0x100
72
73#define HW_DCP_CH0SEMA (0x110 + 0 * 0x40)
74#define HW_DCP_CH1SEMA (0x110 + 1 * 0x40)
75#define HW_DCP_CH2SEMA (0x110 + 2 * 0x40)
76#define HW_DCP_CH3SEMA (0x110 + 3 * 0x40)
77
78#define HW_DCP_CHnSEMA 0x110
79#define BM_DCP_CHnSEMA_INCREMENT 0x000000FF
80#define BP_DCP_CHnSEMA_INCREMENT 0
81
82#define HW_DCP_CH0STAT (0x120 + 0 * 0x40)
83#define HW_DCP_CH1STAT (0x120 + 1 * 0x40)
84#define HW_DCP_CH2STAT (0x120 + 2 * 0x40)
85#define HW_DCP_CH3STAT (0x120 + 3 * 0x40)
86
87#define HW_DCP_CHnSTAT 0x120
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-digctl.h b/arch/arm/mach-stmp378x/include/mach/regs-digctl.h
deleted file mode 100644
index 5293005523b3..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-digctl.h
+++ /dev/null
@@ -1,38 +0,0 @@
1/*
2 * stmp378x: DIGCTL register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_DIGCTL_BASE (STMP3XXX_REGS_BASE + 0x1C000)
22#define REGS_DIGCTL_PHYS 0x8001C000
23#define REGS_DIGCTL_SIZE 0x2000
24
25#define HW_DIGCTL_CTRL 0x0
26#define BM_DIGCTL_CTRL_USB_CLKGATE 0x00000004
27
28#define HW_DIGCTL_ARMCACHE 0x2B0
29#define BM_DIGCTL_ARMCACHE_ITAG_SS 0x00000003
30#define BP_DIGCTL_ARMCACHE_ITAG_SS 0
31#define BM_DIGCTL_ARMCACHE_DTAG_SS 0x00000030
32#define BP_DIGCTL_ARMCACHE_DTAG_SS 4
33#define BM_DIGCTL_ARMCACHE_CACHE_SS 0x00000300
34#define BP_DIGCTL_ARMCACHE_CACHE_SS 8
35#define BM_DIGCTL_ARMCACHE_DRTY_SS 0x00003000
36#define BP_DIGCTL_ARMCACHE_DRTY_SS 12
37#define BM_DIGCTL_ARMCACHE_VALID_SS 0x00030000
38#define BP_DIGCTL_ARMCACHE_VALID_SS 16
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-dram.h b/arch/arm/mach-stmp378x/include/mach/regs-dram.h
deleted file mode 100644
index 02851431677c..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-dram.h
+++ /dev/null
@@ -1,27 +0,0 @@
1/*
2 * stmp378x: DRAM register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_DRAM_BASE (STMP3XXX_REGS_BASE + 0xE0000)
22#define REGS_DRAM_PHYS 0x800E0000
23#define REGS_DRAM_SIZE 0x2000
24
25#define HW_DRAM_CTL06 0x18
26
27#define HW_DRAM_CTL08 0x20
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-dri.h b/arch/arm/mach-stmp378x/include/mach/regs-dri.h
deleted file mode 100644
index da25f7e397e5..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-dri.h
+++ /dev/null
@@ -1,45 +0,0 @@
1/*
2 * stmp378x: DRI register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_DRI_BASE (STMP3XXX_REGS_BASE + 0x74000)
22#define REGS_DRI_PHYS 0x80074000
23#define REGS_DRI_SIZE 0x2000
24
25#define HW_DRI_CTRL 0x0
26#define BM_DRI_CTRL_RUN 0x00000001
27#define BP_DRI_CTRL_RUN 0
28#define BM_DRI_CTRL_ATTENTION_IRQ 0x00000002
29#define BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ 0x00000004
30#define BM_DRI_CTRL_OVERFLOW_IRQ 0x00000008
31#define BM_DRI_CTRL_ATTENTION_IRQ_EN 0x00000200
32#define BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN 0x00000400
33#define BM_DRI_CTRL_OVERFLOW_IRQ_EN 0x00000800
34#define BM_DRI_CTRL_REACQUIRE_PHASE 0x00008000
35#define BM_DRI_CTRL_STOP_ON_PILOT_ERROR 0x02000000
36#define BM_DRI_CTRL_STOP_ON_OFLOW_ERROR 0x04000000
37#define BM_DRI_CTRL_ENABLE_INPUTS 0x20000000
38#define BM_DRI_CTRL_CLKGATE 0x40000000
39#define BM_DRI_CTRL_SFTRST 0x80000000
40
41#define HW_DRI_TIMING 0x10
42#define BM_DRI_TIMING_GAP_DETECTION_INTERVAL 0x000000FF
43#define BP_DRI_TIMING_GAP_DETECTION_INTERVAL 0
44#define BM_DRI_TIMING_PILOT_REP_RATE 0x000F0000
45#define BP_DRI_TIMING_PILOT_REP_RATE 16
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-ecc8.h b/arch/arm/mach-stmp378x/include/mach/regs-ecc8.h
deleted file mode 100644
index cc353bec331b..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-ecc8.h
+++ /dev/null
@@ -1,39 +0,0 @@
1/*
2 * stmp378x: ECC8 register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_ECC8_BASE (STMP3XXX_REGS_BASE + 0x8000)
22#define REGS_ECC8_PHYS 0x80008000
23#define REGS_ECC8_SIZE 0x2000
24
25#define HW_ECC8_CTRL 0x0
26#define BM_ECC8_CTRL_COMPLETE_IRQ 0x00000001
27#define BP_ECC8_CTRL_COMPLETE_IRQ 0
28#define BM_ECC8_CTRL_COMPLETE_IRQ_EN 0x00000100
29#define BM_ECC8_CTRL_AHBM_SFTRST 0x20000000
30
31#define HW_ECC8_STATUS0 0x10
32#define BM_ECC8_STATUS0_UNCORRECTABLE 0x00000004
33#define BM_ECC8_STATUS0_CORRECTED 0x00000008
34#define BM_ECC8_STATUS0_STATUS_AUX 0x00000F00
35#define BP_ECC8_STATUS0_STATUS_AUX 8
36#define BM_ECC8_STATUS0_COMPLETED_CE 0x000F0000
37#define BP_ECC8_STATUS0_COMPLETED_CE 16
38
39#define HW_ECC8_STATUS1 0x20
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-emi.h b/arch/arm/mach-stmp378x/include/mach/regs-emi.h
deleted file mode 100644
index 98773fc33d7b..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-emi.h
+++ /dev/null
@@ -1,25 +0,0 @@
1/*
2 * stmp378x: EMI register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_EMI_BASE (STMP3XXX_REGS_BASE + 0x20000)
22#define REGS_EMI_PHYS 0x80020000
23#define REGS_EMI_SIZE 0x2000
24
25#define HW_EMI_STAT 0x10
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-gpmi.h b/arch/arm/mach-stmp378x/include/mach/regs-gpmi.h
deleted file mode 100644
index 2cc8bbe91687..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-gpmi.h
+++ /dev/null
@@ -1,78 +0,0 @@
1/*
2 * stmp378x: GPMI register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_GPMI_BASE (STMP3XXX_REGS_BASE + 0xC000)
22#define REGS_GPMI_PHYS 0x8000C000
23#define REGS_GPMI_SIZE 0x2000
24
25#define HW_GPMI_CTRL0 0x0
26#define BM_GPMI_CTRL0_XFER_COUNT 0x0000FFFF
27#define BP_GPMI_CTRL0_XFER_COUNT 0
28#define BM_GPMI_CTRL0_CS 0x00300000
29#define BP_GPMI_CTRL0_CS 20
30#define BM_GPMI_CTRL0_LOCK_CS 0x00400000
31#define BM_GPMI_CTRL0_WORD_LENGTH 0x00800000
32#define BM_GPMI_CTRL0_ADDRESS 0x000E0000
33#define BP_GPMI_CTRL0_ADDRESS 17
34#define BV_GPMI_CTRL0_ADDRESS__NAND_DATA 0x0
35#define BV_GPMI_CTRL0_ADDRESS__NAND_CLE 0x1
36#define BV_GPMI_CTRL0_ADDRESS__NAND_ALE 0x2
37#define BM_GPMI_CTRL0_ADDRESS_INCREMENT 0x00010000
38#define BM_GPMI_CTRL0_COMMAND_MODE 0x03000000
39#define BP_GPMI_CTRL0_COMMAND_MODE 24
40#define BV_GPMI_CTRL0_COMMAND_MODE__WRITE 0x0
41#define BV_GPMI_CTRL0_COMMAND_MODE__READ 0x1
42#define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE 0x2
43#define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY 0x3
44#define BM_GPMI_CTRL0_RUN 0x20000000
45#define BM_GPMI_CTRL0_CLKGATE 0x40000000
46#define BM_GPMI_CTRL0_SFTRST 0x80000000
47#define BM_GPMI_ECCCTRL_BUFFER_MASK 0x000001FF
48#define BP_GPMI_ECCCTRL_BUFFER_MASK 0
49#define BM_GPMI_ECCCTRL_ENABLE_ECC 0x00001000
50#define BM_GPMI_ECCCTRL_ECC_CMD 0x00006000
51#define BP_GPMI_ECCCTRL_ECC_CMD 13
52#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_4_BIT 0
53#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_4_BIT 1
54#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_8_BIT 2
55#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_8_BIT 3
56
57#define HW_GPMI_CTRL1 0x60
58#define BM_GPMI_CTRL1_GPMI_MODE 0x00000001
59#define BP_GPMI_CTRL1_GPMI_MODE 0
60#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY 0x00000004
61#define BM_GPMI_CTRL1_DEV_RESET 0x00000008
62#define BM_GPMI_CTRL1_TIMEOUT_IRQ 0x00000200
63#define BM_GPMI_CTRL1_DEV_IRQ 0x00000400
64#define BM_GPMI_CTRL1_RDN_DELAY 0x0000F000
65#define BP_GPMI_CTRL1_RDN_DELAY 12
66#define BM_GPMI_CTRL1_BCH_MODE 0x00040000
67
68#define HW_GPMI_TIMING0 0x70
69#define BM_GPMI_TIMING0_DATA_SETUP 0x000000FF
70#define BP_GPMI_TIMING0_DATA_SETUP 0
71#define BM_GPMI_TIMING0_DATA_HOLD 0x0000FF00
72#define BP_GPMI_TIMING0_DATA_HOLD 8
73#define BM_GPMI_TIMING0_ADDRESS_SETUP 0x00FF0000
74#define BP_GPMI_TIMING0_ADDRESS_SETUP 16
75
76#define HW_GPMI_TIMING1 0x80
77#define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 0xFFFF0000
78#define BP_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 16
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-i2c.h b/arch/arm/mach-stmp378x/include/mach/regs-i2c.h
deleted file mode 100644
index 13a234c99433..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-i2c.h
+++ /dev/null
@@ -1,55 +0,0 @@
1/*
2 * stmp378x: I2C register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_I2C_BASE (STMP3XXX_REGS_BASE + 0x58000)
22#define REGS_I2C_PHYS 0x80058000
23#define REGS_I2C_SIZE 0x2000
24
25#define HW_I2C_CTRL0 0x0
26#define BM_I2C_CTRL0_XFER_COUNT 0x0000FFFF
27#define BP_I2C_CTRL0_XFER_COUNT 0
28#define BM_I2C_CTRL0_DIRECTION 0x00010000
29#define BM_I2C_CTRL0_MASTER_MODE 0x00020000
30#define BM_I2C_CTRL0_PRE_SEND_START 0x00080000
31#define BM_I2C_CTRL0_POST_SEND_STOP 0x00100000
32#define BM_I2C_CTRL0_RETAIN_CLOCK 0x00200000
33#define BM_I2C_CTRL0_SEND_NAK_ON_LAST 0x02000000
34#define BM_I2C_CTRL0_CLKGATE 0x40000000
35#define BM_I2C_CTRL0_SFTRST 0x80000000
36
37#define HW_I2C_TIMING0 0x10
38
39#define HW_I2C_TIMING1 0x20
40
41#define HW_I2C_TIMING2 0x30
42
43#define HW_I2C_CTRL1 0x40
44#define BM_I2C_CTRL1_SLAVE_IRQ 0x00000001
45#define BP_I2C_CTRL1_SLAVE_IRQ 0
46#define BM_I2C_CTRL1_SLAVE_STOP_IRQ 0x00000002
47#define BM_I2C_CTRL1_MASTER_LOSS_IRQ 0x00000004
48#define BM_I2C_CTRL1_EARLY_TERM_IRQ 0x00000008
49#define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ 0x00000010
50#define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ 0x00000020
51#define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 0x00000040
52#define BM_I2C_CTRL1_BUS_FREE_IRQ 0x00000080
53#define BM_I2C_CTRL1_CLR_GOT_A_NAK 0x10000000
54
55#define HW_I2C_VERSION 0x90
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-icoll.h b/arch/arm/mach-stmp378x/include/mach/regs-icoll.h
deleted file mode 100644
index f996e80f40e7..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-icoll.h
+++ /dev/null
@@ -1,45 +0,0 @@
1/*
2 * stmp378x: ICOLL register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef _MACH_REGS_ICOLL
22#define _MACH_REGS_ICOLL
23
24#define REGS_ICOLL_BASE (STMP3XXX_REGS_BASE + 0x0)
25#define REGS_ICOLL_PHYS 0x80000000
26#define REGS_ICOLL_SIZE 0x2000
27
28#define HW_ICOLL_VECTOR 0x0
29
30#define HW_ICOLL_LEVELACK 0x10
31#define BM_ICOLL_LEVELACK_IRQLEVELACK 0x0000000F
32#define BP_ICOLL_LEVELACK_IRQLEVELACK 0
33
34#define HW_ICOLL_CTRL 0x20
35#define BM_ICOLL_CTRL_CLKGATE 0x40000000
36#define BM_ICOLL_CTRL_SFTRST 0x80000000
37
38#define HW_ICOLL_STAT 0x70
39
40#define HW_ICOLL_INTERRUPTn 0x120
41
42#define HW_ICOLL_INTERRUPTn 0x120
43#define BM_ICOLL_INTERRUPTn_ENABLE 0x00000004
44
45#endif
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-ir.h b/arch/arm/mach-stmp378x/include/mach/regs-ir.h
deleted file mode 100644
index a5b4ef10fab8..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-ir.h
+++ /dev/null
@@ -1,23 +0,0 @@
1/*
2 * stmp378x: IR register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_IR_BASE (STMP3XXX_REGS_BASE + 0x78000)
22#define REGS_IR_PHYS 0x80078000
23#define REGS_IR_SIZE 0x2000
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-lcdif.h b/arch/arm/mach-stmp378x/include/mach/regs-lcdif.h
deleted file mode 100644
index 9cdbef4badc3..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-lcdif.h
+++ /dev/null
@@ -1,195 +0,0 @@
1/*
2 * stmp378x: LCDIF register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_LCDIF_BASE (STMP3XXX_REGS_BASE + 0x30000)
22#define REGS_LCDIF_PHYS 0x80030000
23#define REGS_LCDIF_SIZE 0x2000
24
25#define HW_LCDIF_CTRL 0x0
26#define BM_LCDIF_CTRL_RUN 0x00000001
27#define BP_LCDIF_CTRL_RUN 0
28#define BM_LCDIF_CTRL_LCDIF_MASTER 0x00000020
29#define BM_LCDIF_CTRL_RGB_TO_YCBCR422_CSC 0x00000080
30#define BM_LCDIF_CTRL_WORD_LENGTH 0x00000300
31#define BP_LCDIF_CTRL_WORD_LENGTH 8
32#define BM_LCDIF_CTRL_LCD_DATABUS_WIDTH 0x00000C00
33#define BP_LCDIF_CTRL_LCD_DATABUS_WIDTH 10
34#define BM_LCDIF_CTRL_INPUT_DATA_SWIZZLE 0x0000C000
35#define BP_LCDIF_CTRL_INPUT_DATA_SWIZZLE 14
36#define BM_LCDIF_CTRL_DATA_SELECT 0x00010000
37#define BM_LCDIF_CTRL_DOTCLK_MODE 0x00020000
38#define BM_LCDIF_CTRL_VSYNC_MODE 0x00040000
39#define BM_LCDIF_CTRL_BYPASS_COUNT 0x00080000
40#define BM_LCDIF_CTRL_DVI_MODE 0x00100000
41#define BM_LCDIF_CTRL_SHIFT_NUM_BITS 0x03E00000
42#define BP_LCDIF_CTRL_SHIFT_NUM_BITS 21
43#define BM_LCDIF_CTRL_DATA_SHIFT_DIR 0x04000000
44#define BM_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE 0x08000000
45#define BM_LCDIF_CTRL_CLKGATE 0x40000000
46#define BM_LCDIF_CTRL_SFTRST 0x80000000
47
48#define HW_LCDIF_CTRL1 0x10
49#define BM_LCDIF_CTRL1_RESET 0x00000001
50#define BP_LCDIF_CTRL1_RESET 0
51#define BM_LCDIF_CTRL1_MODE86 0x00000002
52#define BM_LCDIF_CTRL1_BUSY_ENABLE 0x00000004
53#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ 0x00000100
54#define BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ 0x00000200
55#define BM_LCDIF_CTRL1_UNDERFLOW_IRQ 0x00000400
56#define BM_LCDIF_CTRL1_OVERFLOW_IRQ 0x00000800
57#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN 0x00001000
58#define BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT 0x000F0000
59#define BP_LCDIF_CTRL1_BYTE_PACKING_FORMAT 16
60#define BM_LCDIF_CTRL1_INTERLACE_FIELDS 0x00800000
61#define BM_LCDIF_CTRL1_RECOVER_ON_UNDERFLOW 0x01000000
62
63#define HW_LCDIF_TRANSFER_COUNT 0x20
64#define BM_LCDIF_TRANSFER_COUNT_H_COUNT 0x0000FFFF
65#define BP_LCDIF_TRANSFER_COUNT_H_COUNT 0
66#define BM_LCDIF_TRANSFER_COUNT_V_COUNT 0xFFFF0000
67#define BP_LCDIF_TRANSFER_COUNT_V_COUNT 16
68
69#define HW_LCDIF_CUR_BUF 0x30
70
71#define HW_LCDIF_NEXT_BUF 0x40
72
73#define HW_LCDIF_TIMING 0x60
74
75#define HW_LCDIF_VDCTRL0 0x70
76#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH 0x0003FFFF
77#define BP_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH 0
78#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT 0x00100000
79#define BM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT 0x00200000
80#define BM_LCDIF_VDCTRL0_ENABLE_POL 0x01000000
81#define BM_LCDIF_VDCTRL0_DOTCLK_POL 0x02000000
82#define BM_LCDIF_VDCTRL0_HSYNC_POL 0x04000000
83#define BM_LCDIF_VDCTRL0_VSYNC_POL 0x08000000
84#define BM_LCDIF_VDCTRL0_ENABLE_PRESENT 0x10000000
85#define BM_LCDIF_VDCTRL0_VSYNC_OEB 0x20000000
86
87#define HW_LCDIF_VDCTRL1 0x80
88#define BM_LCDIF_VDCTRL1_VSYNC_PERIOD 0xFFFFFFFF
89#define BP_LCDIF_VDCTRL1_VSYNC_PERIOD 0
90
91#define HW_LCDIF_VDCTRL2 0x90
92#define BM_LCDIF_VDCTRL2_HSYNC_PERIOD 0x0003FFFF
93#define BP_LCDIF_VDCTRL2_HSYNC_PERIOD 0
94#define BM_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 0xFF000000
95#define BP_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 24
96
97#define HW_LCDIF_VDCTRL3 0xA0
98#define BM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0x0000FFFF
99#define BP_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0
100#define BM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 0x0FFF0000
101#define BP_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 16
102
103#define HW_LCDIF_VDCTRL4 0xB0
104#define BM_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT 0x0003FFFF
105#define BP_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT 0
106#define BM_LCDIF_VDCTRL4_SYNC_SIGNALS_ON 0x00040000
107
108#define HW_LCDIF_DVICTRL0 0xC0
109#define BM_LCDIF_DVICTRL0_V_LINES_CNT 0x000003FF
110#define BP_LCDIF_DVICTRL0_V_LINES_CNT 0
111#define BM_LCDIF_DVICTRL0_H_BLANKING_CNT 0x000FFC00
112#define BP_LCDIF_DVICTRL0_H_BLANKING_CNT 10
113#define BM_LCDIF_DVICTRL0_H_ACTIVE_CNT 0x7FF00000
114#define BP_LCDIF_DVICTRL0_H_ACTIVE_CNT 20
115
116#define HW_LCDIF_DVICTRL1 0xD0
117#define BM_LCDIF_DVICTRL1_F2_START_LINE 0x000003FF
118#define BP_LCDIF_DVICTRL1_F2_START_LINE 0
119#define BM_LCDIF_DVICTRL1_F1_END_LINE 0x000FFC00
120#define BP_LCDIF_DVICTRL1_F1_END_LINE 10
121#define BM_LCDIF_DVICTRL1_F1_START_LINE 0x3FF00000
122#define BP_LCDIF_DVICTRL1_F1_START_LINE 20
123
124#define HW_LCDIF_DVICTRL2 0xE0
125#define BM_LCDIF_DVICTRL2_V1_BLANK_END_LINE 0x000003FF
126#define BP_LCDIF_DVICTRL2_V1_BLANK_END_LINE 0
127#define BM_LCDIF_DVICTRL2_V1_BLANK_START_LINE 0x000FFC00
128#define BP_LCDIF_DVICTRL2_V1_BLANK_START_LINE 10
129#define BM_LCDIF_DVICTRL2_F2_END_LINE 0x3FF00000
130#define BP_LCDIF_DVICTRL2_F2_END_LINE 20
131
132#define HW_LCDIF_DVICTRL3 0xF0
133#define BM_LCDIF_DVICTRL3_V2_BLANK_END_LINE 0x000003FF
134#define BP_LCDIF_DVICTRL3_V2_BLANK_END_LINE 0
135#define BM_LCDIF_DVICTRL3_V2_BLANK_START_LINE 0x03FF0000
136#define BP_LCDIF_DVICTRL3_V2_BLANK_START_LINE 16
137
138#define HW_LCDIF_DVICTRL4 0x100
139#define BM_LCDIF_DVICTRL4_H_FILL_CNT 0x000000FF
140#define BP_LCDIF_DVICTRL4_H_FILL_CNT 0
141#define BM_LCDIF_DVICTRL4_CR_FILL_VALUE 0x0000FF00
142#define BP_LCDIF_DVICTRL4_CR_FILL_VALUE 8
143#define BM_LCDIF_DVICTRL4_CB_FILL_VALUE 0x00FF0000
144#define BP_LCDIF_DVICTRL4_CB_FILL_VALUE 16
145#define BM_LCDIF_DVICTRL4_Y_FILL_VALUE 0xFF000000
146#define BP_LCDIF_DVICTRL4_Y_FILL_VALUE 24
147
148#define HW_LCDIF_CSC_COEFF0 0x110
149#define BM_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER 0x00000003
150#define BP_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER 0
151#define BM_LCDIF_CSC_COEFF0_C0 0x03FF0000
152#define BP_LCDIF_CSC_COEFF0_C0 16
153
154#define HW_LCDIF_CSC_COEFF1 0x120
155#define BM_LCDIF_CSC_COEFF1_C1 0x000003FF
156#define BP_LCDIF_CSC_COEFF1_C1 0
157#define BM_LCDIF_CSC_COEFF1_C2 0x03FF0000
158#define BP_LCDIF_CSC_COEFF1_C2 16
159
160#define HW_LCDIF_CSC_COEFF2 0x130
161#define BM_LCDIF_CSC_COEFF2_C3 0x000003FF
162#define BP_LCDIF_CSC_COEFF2_C3 0
163#define BM_LCDIF_CSC_COEFF2_C4 0x03FF0000
164#define BP_LCDIF_CSC_COEFF2_C4 16
165
166#define HW_LCDIF_CSC_COEFF3 0x140
167#define BM_LCDIF_CSC_COEFF3_C5 0x000003FF
168#define BP_LCDIF_CSC_COEFF3_C5 0
169#define BM_LCDIF_CSC_COEFF3_C6 0x03FF0000
170#define BP_LCDIF_CSC_COEFF3_C6 16
171
172#define HW_LCDIF_CSC_COEFF4 0x150
173#define BM_LCDIF_CSC_COEFF4_C7 0x000003FF
174#define BP_LCDIF_CSC_COEFF4_C7 0
175#define BM_LCDIF_CSC_COEFF4_C8 0x03FF0000
176#define BP_LCDIF_CSC_COEFF4_C8 16
177
178#define HW_LCDIF_CSC_OFFSET 0x160
179#define BM_LCDIF_CSC_OFFSET_Y_OFFSET 0x000001FF
180#define BP_LCDIF_CSC_OFFSET_Y_OFFSET 0
181#define BM_LCDIF_CSC_OFFSET_CBCR_OFFSET 0x01FF0000
182#define BP_LCDIF_CSC_OFFSET_CBCR_OFFSET 16
183
184#define HW_LCDIF_CSC_LIMIT 0x170
185#define BM_LCDIF_CSC_LIMIT_Y_MAX 0x000000FF
186#define BP_LCDIF_CSC_LIMIT_Y_MAX 0
187#define BM_LCDIF_CSC_LIMIT_Y_MIN 0x0000FF00
188#define BP_LCDIF_CSC_LIMIT_Y_MIN 8
189#define BM_LCDIF_CSC_LIMIT_CBCR_MAX 0x00FF0000
190#define BP_LCDIF_CSC_LIMIT_CBCR_MAX 16
191#define BM_LCDIF_CSC_LIMIT_CBCR_MIN 0xFF000000
192#define BP_LCDIF_CSC_LIMIT_CBCR_MIN 24
193
194#define HW_LCDIF_STAT 0x1D0
195#define BM_LCDIF_STAT_TXFIFO_EMPTY 0x04000000
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-lradc.h b/arch/arm/mach-stmp378x/include/mach/regs-lradc.h
deleted file mode 100644
index cb8cb06f8277..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-lradc.h
+++ /dev/null
@@ -1,99 +0,0 @@
1/*
2 * stmp378x: LRADC register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_LRADC_BASE (STMP3XXX_REGS_BASE + 0x50000)
22#define REGS_LRADC_PHYS 0x80050000
23#define REGS_LRADC_SIZE 0x2000
24
25#define HW_LRADC_CTRL0 0x0
26#define BM_LRADC_CTRL0_SCHEDULE 0x000000FF
27#define BP_LRADC_CTRL0_SCHEDULE 0
28#define BM_LRADC_CTRL0_XPLUS_ENABLE 0x00010000
29#define BM_LRADC_CTRL0_YPLUS_ENABLE 0x00020000
30#define BM_LRADC_CTRL0_XMINUS_ENABLE 0x00040000
31#define BM_LRADC_CTRL0_YMINUS_ENABLE 0x00080000
32#define BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE 0x00100000
33#define BM_LRADC_CTRL0_ONCHIP_GROUNDREF 0x00200000
34#define BM_LRADC_CTRL0_CLKGATE 0x40000000
35#define BM_LRADC_CTRL0_SFTRST 0x80000000
36
37#define HW_LRADC_CTRL1 0x10
38#define BM_LRADC_CTRL1_LRADC0_IRQ 0x00000001
39#define BP_LRADC_CTRL1_LRADC0_IRQ 0
40#define BM_LRADC_CTRL1_LRADC5_IRQ 0x00000020
41#define BM_LRADC_CTRL1_LRADC6_IRQ 0x00000040
42#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ 0x00000100
43#define BM_LRADC_CTRL1_LRADC0_IRQ_EN 0x00010000
44#define BM_LRADC_CTRL1_LRADC5_IRQ_EN 0x00200000
45#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN 0x01000000
46
47#define HW_LRADC_CTRL2 0x20
48#define BM_LRADC_CTRL2_BL_BRIGHTNESS 0x001F0000
49#define BP_LRADC_CTRL2_BL_BRIGHTNESS 16
50#define BM_LRADC_CTRL2_BL_MUX_SELECT 0x00200000
51#define BM_LRADC_CTRL2_BL_ENABLE 0x00400000
52#define BM_LRADC_CTRL2_DIVIDE_BY_TWO 0xFF000000
53#define BP_LRADC_CTRL2_DIVIDE_BY_TWO 24
54
55#define HW_LRADC_CTRL3 0x30
56#define BM_LRADC_CTRL3_CYCLE_TIME 0x00000300
57#define BP_LRADC_CTRL3_CYCLE_TIME 8
58
59#define HW_LRADC_STATUS 0x40
60#define BM_LRADC_STATUS_TOUCH_DETECT_RAW 0x00000001
61#define BP_LRADC_STATUS_TOUCH_DETECT_RAW 0
62
63#define HW_LRADC_CH0 (0x50 + 0 * 0x10)
64#define HW_LRADC_CH1 (0x50 + 1 * 0x10)
65#define HW_LRADC_CH2 (0x50 + 2 * 0x10)
66#define HW_LRADC_CH3 (0x50 + 3 * 0x10)
67#define HW_LRADC_CH4 (0x50 + 4 * 0x10)
68#define HW_LRADC_CH5 (0x50 + 5 * 0x10)
69#define HW_LRADC_CH6 (0x50 + 6 * 0x10)
70#define HW_LRADC_CH7 (0x50 + 7 * 0x10)
71
72#define HW_LRADC_CHn 0x50
73#define BM_LRADC_CHn_VALUE 0x0003FFFF
74#define BP_LRADC_CHn_VALUE 0
75#define BM_LRADC_CHn_NUM_SAMPLES 0x1F000000
76#define BP_LRADC_CHn_NUM_SAMPLES 24
77#define BM_LRADC_CHn_ACCUMULATE 0x20000000
78
79#define HW_LRADC_DELAY0 (0xD0 + 0 * 0x10)
80#define HW_LRADC_DELAY1 (0xD0 + 1 * 0x10)
81#define HW_LRADC_DELAY2 (0xD0 + 2 * 0x10)
82#define HW_LRADC_DELAY3 (0xD0 + 3 * 0x10)
83
84#define HW_LRADC_DELAYn 0xD0
85#define BM_LRADC_DELAYn_DELAY 0x000007FF
86#define BP_LRADC_DELAYn_DELAY 0
87#define BM_LRADC_DELAYn_LOOP_COUNT 0x0000F800
88#define BP_LRADC_DELAYn_LOOP_COUNT 11
89#define BM_LRADC_DELAYn_TRIGGER_DELAYS 0x000F0000
90#define BP_LRADC_DELAYn_TRIGGER_DELAYS 16
91#define BM_LRADC_DELAYn_KICK 0x00100000
92#define BM_LRADC_DELAYn_TRIGGER_LRADCS 0xFF000000
93#define BP_LRADC_DELAYn_TRIGGER_LRADCS 24
94
95#define HW_LRADC_CTRL4 0x140
96#define BM_LRADC_CTRL4_LRADC6SELECT 0x0F000000
97#define BP_LRADC_CTRL4_LRADC6SELECT 24
98#define BM_LRADC_CTRL4_LRADC7SELECT 0xF0000000
99#define BP_LRADC_CTRL4_LRADC7SELECT 28
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-ocotp.h b/arch/arm/mach-stmp378x/include/mach/regs-ocotp.h
deleted file mode 100644
index f0af64d9937e..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-ocotp.h
+++ /dev/null
@@ -1,40 +0,0 @@
1/*
2 * stmp378x: OCOTP register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_OCOTP_BASE (STMP3XXX_REGS_BASE + 0x2C000)
22#define REGS_OCOTP_PHYS 0x8002C000
23#define REGS_OCOTP_SIZE 0x2000
24
25#define HW_OCOTP_CTRL 0x0
26#define BM_OCOTP_CTRL_BUSY 0x00000100
27#define BM_OCOTP_CTRL_ERROR 0x00000200
28#define BM_OCOTP_CTRL_RD_BANK_OPEN 0x00001000
29#define BM_OCOTP_CTRL_RELOAD_SHADOWS 0x00002000
30#define BM_OCOTP_CTRL_WR_UNLOCK 0xFFFF0000
31#define BP_OCOTP_CTRL_WR_UNLOCK 16
32
33#define HW_OCOTP_DATA 0x10
34
35#define HW_OCOTP_CUST0 (0x20 + 0 * 0x10)
36#define HW_OCOTP_CUST1 (0x20 + 1 * 0x10)
37#define HW_OCOTP_CUST2 (0x20 + 2 * 0x10)
38#define HW_OCOTP_CUST3 (0x20 + 3 * 0x10)
39
40#define HW_OCOTP_CUSTn 0x20
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-pinctrl.h b/arch/arm/mach-stmp378x/include/mach/regs-pinctrl.h
deleted file mode 100644
index 50d90ea1b136..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-pinctrl.h
+++ /dev/null
@@ -1,90 +0,0 @@
1/*
2 * stmp378x: PINCTRL register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef _MACH_REGS_PINCTRL
22#define _MACH_REGS_PINCTRL
23
24#define REGS_PINCTRL_BASE (STMP3XXX_REGS_BASE + 0x18000)
25#define REGS_PINCTRL_PHYS 0x80018000
26#define REGS_PINCTRL_SIZE 0x2000
27
28#define HW_PINCTRL_MUXSEL0 0x100
29#define HW_PINCTRL_MUXSEL1 0x110
30#define HW_PINCTRL_MUXSEL2 0x120
31#define HW_PINCTRL_MUXSEL3 0x130
32#define HW_PINCTRL_MUXSEL4 0x140
33#define HW_PINCTRL_MUXSEL5 0x150
34#define HW_PINCTRL_MUXSEL6 0x160
35#define HW_PINCTRL_MUXSEL7 0x170
36
37#define HW_PINCTRL_DRIVE0 0x200
38#define HW_PINCTRL_DRIVE1 0x210
39#define HW_PINCTRL_DRIVE2 0x220
40#define HW_PINCTRL_DRIVE3 0x230
41#define HW_PINCTRL_DRIVE4 0x240
42#define HW_PINCTRL_DRIVE5 0x250
43#define HW_PINCTRL_DRIVE6 0x260
44#define HW_PINCTRL_DRIVE7 0x270
45#define HW_PINCTRL_DRIVE8 0x280
46#define HW_PINCTRL_DRIVE9 0x290
47#define HW_PINCTRL_DRIVE10 0x2A0
48#define HW_PINCTRL_DRIVE11 0x2B0
49#define HW_PINCTRL_DRIVE12 0x2C0
50#define HW_PINCTRL_DRIVE13 0x2D0
51#define HW_PINCTRL_DRIVE14 0x2E0
52
53#define HW_PINCTRL_PULL0 0x400
54#define HW_PINCTRL_PULL1 0x410
55#define HW_PINCTRL_PULL2 0x420
56#define HW_PINCTRL_PULL3 0x430
57
58#define HW_PINCTRL_DOUT0 0x500
59#define HW_PINCTRL_DOUT1 0x510
60#define HW_PINCTRL_DOUT2 0x520
61
62#define HW_PINCTRL_DIN0 0x600
63#define HW_PINCTRL_DIN1 0x610
64#define HW_PINCTRL_DIN2 0x620
65
66#define HW_PINCTRL_DOE0 0x700
67#define HW_PINCTRL_DOE1 0x710
68#define HW_PINCTRL_DOE2 0x720
69
70#define HW_PINCTRL_PIN2IRQ0 0x800
71#define HW_PINCTRL_PIN2IRQ1 0x810
72#define HW_PINCTRL_PIN2IRQ2 0x820
73
74#define HW_PINCTRL_IRQEN0 0x900
75#define HW_PINCTRL_IRQEN1 0x910
76#define HW_PINCTRL_IRQEN2 0x920
77
78#define HW_PINCTRL_IRQLEVEL0 0xA00
79#define HW_PINCTRL_IRQLEVEL1 0xA10
80#define HW_PINCTRL_IRQLEVEL2 0xA20
81
82#define HW_PINCTRL_IRQPOL0 0xB00
83#define HW_PINCTRL_IRQPOL1 0xB10
84#define HW_PINCTRL_IRQPOL2 0xB20
85
86#define HW_PINCTRL_IRQSTAT0 0xC00
87#define HW_PINCTRL_IRQSTAT1 0xC10
88#define HW_PINCTRL_IRQSTAT2 0xC20
89
90#endif
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-power.h b/arch/arm/mach-stmp378x/include/mach/regs-power.h
deleted file mode 100644
index e454c830f076..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-power.h
+++ /dev/null
@@ -1,63 +0,0 @@
1/*
2 * stmp378x: POWER register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef _MACH_REGS_POWER
22#define _MACH_REGS_POWER
23
24#define REGS_POWER_BASE (STMP3XXX_REGS_BASE + 0x44000)
25#define REGS_POWER_PHYS 0x80044000
26#define REGS_POWER_SIZE 0x2000
27
28#define HW_POWER_CTRL 0x0
29#define BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO 0x00000001
30#define BP_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO 0
31#define BM_POWER_CTRL_ENIRQ_PSWITCH 0x00020000
32#define BM_POWER_CTRL_PSWITCH_IRQ 0x00100000
33#define BM_POWER_CTRL_CLKGATE 0x40000000
34
35#define HW_POWER_5VCTRL 0x10
36#define BM_POWER_5VCTRL_ENABLE_LINREG_ILIMIT 0x00000040
37
38#define HW_POWER_MINPWR 0x20
39
40#define HW_POWER_CHARGE 0x30
41
42#define HW_POWER_VDDDCTRL 0x40
43
44#define HW_POWER_VDDACTRL 0x50
45
46#define HW_POWER_VDDIOCTRL 0x60
47#define BM_POWER_VDDIOCTRL_TRG 0x0000001F
48#define BP_POWER_VDDIOCTRL_TRG 0
49
50#define HW_POWER_STS 0xC0
51#define BM_POWER_STS_VBUSVALID 0x00000002
52#define BM_POWER_STS_BVALID 0x00000004
53#define BM_POWER_STS_AVALID 0x00000008
54#define BM_POWER_STS_DC_OK 0x00000200
55
56#define HW_POWER_RESET 0x100
57
58#define HW_POWER_DEBUG 0x110
59#define BM_POWER_DEBUG_BVALIDPIOLOCK 0x00000002
60#define BM_POWER_DEBUG_AVALIDPIOLOCK 0x00000004
61#define BM_POWER_DEBUG_VBUSVALIDPIOLOCK 0x00000008
62
63#endif
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-pwm.h b/arch/arm/mach-stmp378x/include/mach/regs-pwm.h
deleted file mode 100644
index 0d0f9e56ec77..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-pwm.h
+++ /dev/null
@@ -1,53 +0,0 @@
1/*
2 * stmp378x: PWM register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_PWM_BASE (STMP3XXX_REGS_BASE + 0x64000)
22#define REGS_PWM_PHYS 0x80064000
23#define REGS_PWM_SIZE 0x2000
24
25#define HW_PWM_CTRL 0x0
26#define BM_PWM_CTRL_PWM2_ENABLE 0x00000004
27#define BM_PWM_CTRL_PWM2_ANA_CTRL_ENABLE 0x00000020
28
29#define HW_PWM_ACTIVE0 (0x10 + 0 * 0x20)
30#define HW_PWM_ACTIVE1 (0x10 + 1 * 0x20)
31#define HW_PWM_ACTIVE2 (0x10 + 2 * 0x20)
32#define HW_PWM_ACTIVE3 (0x10 + 3 * 0x20)
33
34#define HW_PWM_ACTIVEn 0x10
35#define BM_PWM_ACTIVEn_ACTIVE 0x0000FFFF
36#define BP_PWM_ACTIVEn_ACTIVE 0
37#define BM_PWM_ACTIVEn_INACTIVE 0xFFFF0000
38#define BP_PWM_ACTIVEn_INACTIVE 16
39
40#define HW_PWM_PERIOD0 (0x20 + 0 * 0x20)
41#define HW_PWM_PERIOD1 (0x20 + 1 * 0x20)
42#define HW_PWM_PERIOD2 (0x20 + 2 * 0x20)
43#define HW_PWM_PERIOD3 (0x20 + 3 * 0x20)
44
45#define HW_PWM_PERIODn 0x20
46#define BM_PWM_PERIODn_PERIOD 0x0000FFFF
47#define BP_PWM_PERIODn_PERIOD 0
48#define BM_PWM_PERIODn_ACTIVE_STATE 0x00030000
49#define BP_PWM_PERIODn_ACTIVE_STATE 16
50#define BM_PWM_PERIODn_INACTIVE_STATE 0x000C0000
51#define BP_PWM_PERIODn_INACTIVE_STATE 18
52#define BM_PWM_PERIODn_CDIV 0x00700000
53#define BP_PWM_PERIODn_CDIV 20
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-pxp.h b/arch/arm/mach-stmp378x/include/mach/regs-pxp.h
deleted file mode 100644
index 54d297896de8..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-pxp.h
+++ /dev/null
@@ -1,140 +0,0 @@
1/*
2 * stmp378x: PXP register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_PXP_BASE (STMP3XXX_REGS_BASE + 0x2A000)
22#define REGS_PXP_PHYS 0x8002A000
23#define REGS_PXP_SIZE 0x2000
24
25#define HW_PXP_CTRL 0x0
26#define BM_PXP_CTRL_ENABLE 0x00000001
27#define BP_PXP_CTRL_ENABLE 0
28#define BM_PXP_CTRL_IRQ_ENABLE 0x00000002
29#define BM_PXP_CTRL_OUTPUT_RGB_FORMAT 0x000000F0
30#define BP_PXP_CTRL_OUTPUT_RGB_FORMAT 4
31#define BM_PXP_CTRL_ROTATE 0x00000300
32#define BP_PXP_CTRL_ROTATE 8
33#define BM_PXP_CTRL_HFLIP 0x00000400
34#define BM_PXP_CTRL_VFLIP 0x00000800
35#define BM_PXP_CTRL_S0_FORMAT 0x0000F000
36#define BP_PXP_CTRL_S0_FORMAT 12
37#define BM_PXP_CTRL_SCALE 0x00040000
38#define BM_PXP_CTRL_CROP 0x00080000
39
40#define HW_PXP_STAT 0x10
41#define BM_PXP_STAT_IRQ 0x00000001
42#define BP_PXP_STAT_IRQ 0
43
44#define HW_PXP_RGBBUF 0x20
45
46#define HW_PXP_RGBSIZE 0x40
47#define BM_PXP_RGBSIZE_HEIGHT 0x00000FFF
48#define BP_PXP_RGBSIZE_HEIGHT 0
49#define BM_PXP_RGBSIZE_WIDTH 0x00FFF000
50#define BP_PXP_RGBSIZE_WIDTH 12
51
52#define HW_PXP_S0BUF 0x50
53
54#define HW_PXP_S0UBUF 0x60
55
56#define HW_PXP_S0VBUF 0x70
57
58#define HW_PXP_S0PARAM 0x80
59#define BM_PXP_S0PARAM_HEIGHT 0x000000FF
60#define BP_PXP_S0PARAM_HEIGHT 0
61#define BM_PXP_S0PARAM_WIDTH 0x0000FF00
62#define BP_PXP_S0PARAM_WIDTH 8
63#define BM_PXP_S0PARAM_YBASE 0x00FF0000
64#define BP_PXP_S0PARAM_YBASE 16
65#define BM_PXP_S0PARAM_XBASE 0xFF000000
66#define BP_PXP_S0PARAM_XBASE 24
67
68#define HW_PXP_S0BACKGROUND 0x90
69
70#define HW_PXP_S0CROP 0xA0
71#define BM_PXP_S0CROP_HEIGHT 0x000000FF
72#define BP_PXP_S0CROP_HEIGHT 0
73#define BM_PXP_S0CROP_WIDTH 0x0000FF00
74#define BP_PXP_S0CROP_WIDTH 8
75#define BM_PXP_S0CROP_YBASE 0x00FF0000
76#define BP_PXP_S0CROP_YBASE 16
77#define BM_PXP_S0CROP_XBASE 0xFF000000
78#define BP_PXP_S0CROP_XBASE 24
79
80#define HW_PXP_S0SCALE 0xB0
81#define BM_PXP_S0SCALE_XSCALE 0x00003FFF
82#define BP_PXP_S0SCALE_XSCALE 0
83#define BM_PXP_S0SCALE_YSCALE 0x3FFF0000
84#define BP_PXP_S0SCALE_YSCALE 16
85
86#define HW_PXP_CSCCOEFF0 0xD0
87
88#define HW_PXP_CSCCOEFF1 0xE0
89
90#define HW_PXP_CSCCOEFF2 0xF0
91
92#define HW_PXP_S0COLORKEYLOW 0x180
93
94#define HW_PXP_S0COLORKEYHIGH 0x190
95
96#define HW_PXP_OL0 (0x200 + 0 * 0x40)
97#define HW_PXP_OL1 (0x200 + 1 * 0x40)
98#define HW_PXP_OL2 (0x200 + 2 * 0x40)
99#define HW_PXP_OL3 (0x200 + 3 * 0x40)
100#define HW_PXP_OL4 (0x200 + 4 * 0x40)
101#define HW_PXP_OL5 (0x200 + 5 * 0x40)
102#define HW_PXP_OL6 (0x200 + 6 * 0x40)
103#define HW_PXP_OL7 (0x200 + 7 * 0x40)
104
105#define HW_PXP_OLn 0x200
106
107#define HW_PXP_OL0SIZE (0x210 + 0 * 0x40)
108#define HW_PXP_OL1SIZE (0x210 + 1 * 0x40)
109#define HW_PXP_OL2SIZE (0x210 + 2 * 0x40)
110#define HW_PXP_OL3SIZE (0x210 + 3 * 0x40)
111#define HW_PXP_OL4SIZE (0x210 + 4 * 0x40)
112#define HW_PXP_OL5SIZE (0x210 + 5 * 0x40)
113#define HW_PXP_OL6SIZE (0x210 + 6 * 0x40)
114#define HW_PXP_OL7SIZE (0x210 + 7 * 0x40)
115
116#define HW_PXP_OLnSIZE 0x210
117#define BM_PXP_OLnSIZE_HEIGHT 0x000000FF
118#define BP_PXP_OLnSIZE_HEIGHT 0
119#define BM_PXP_OLnSIZE_WIDTH 0x0000FF00
120#define BP_PXP_OLnSIZE_WIDTH 8
121
122#define HW_PXP_OL0PARAM (0x220 + 0 * 0x40)
123#define HW_PXP_OL1PARAM (0x220 + 1 * 0x40)
124#define HW_PXP_OL2PARAM (0x220 + 2 * 0x40)
125#define HW_PXP_OL3PARAM (0x220 + 3 * 0x40)
126#define HW_PXP_OL4PARAM (0x220 + 4 * 0x40)
127#define HW_PXP_OL5PARAM (0x220 + 5 * 0x40)
128#define HW_PXP_OL6PARAM (0x220 + 6 * 0x40)
129#define HW_PXP_OL7PARAM (0x220 + 7 * 0x40)
130
131#define HW_PXP_OLnPARAM 0x220
132#define BM_PXP_OLnPARAM_ENABLE 0x00000001
133#define BP_PXP_OLnPARAM_ENABLE 0
134#define BM_PXP_OLnPARAM_ALPHA_CNTL 0x00000006
135#define BP_PXP_OLnPARAM_ALPHA_CNTL 1
136#define BM_PXP_OLnPARAM_ENABLE_COLORKEY 0x00000008
137#define BM_PXP_OLnPARAM_FORMAT 0x000000F0
138#define BP_PXP_OLnPARAM_FORMAT 4
139#define BM_PXP_OLnPARAM_ALPHA 0x0000FF00
140#define BP_PXP_OLnPARAM_ALPHA 8
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-rtc.h b/arch/arm/mach-stmp378x/include/mach/regs-rtc.h
deleted file mode 100644
index b8dbd6742d98..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-rtc.h
+++ /dev/null
@@ -1,59 +0,0 @@
1/*
2 * stmp378x: RTC register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_RTC_BASE (STMP3XXX_REGS_BASE + 0x5C000)
22#define REGS_RTC_PHYS 0x8005C000
23#define REGS_RTC_SIZE 0x2000
24
25#define HW_RTC_CTRL 0x0
26#define BM_RTC_CTRL_ALARM_IRQ_EN 0x00000001
27#define BP_RTC_CTRL_ALARM_IRQ_EN 0
28#define BM_RTC_CTRL_ONEMSEC_IRQ_EN 0x00000002
29#define BM_RTC_CTRL_ALARM_IRQ 0x00000004
30#define BM_RTC_CTRL_ONEMSEC_IRQ 0x00000008
31#define BM_RTC_CTRL_WATCHDOGEN 0x00000010
32
33#define HW_RTC_STAT 0x10
34#define BM_RTC_STAT_NEW_REGS 0x0000FF00
35#define BP_RTC_STAT_NEW_REGS 8
36#define BM_RTC_STAT_STALE_REGS 0x00FF0000
37#define BP_RTC_STAT_STALE_REGS 16
38#define BM_RTC_STAT_RTC_PRESENT 0x80000000
39
40#define HW_RTC_SECONDS 0x30
41
42#define HW_RTC_ALARM 0x40
43
44#define HW_RTC_WATCHDOG 0x50
45
46#define HW_RTC_PERSISTENT0 0x60
47#define BM_RTC_PERSISTENT0_ALARM_WAKE_EN 0x00000002
48#define BM_RTC_PERSISTENT0_ALARM_EN 0x00000004
49#define BM_RTC_PERSISTENT0_XTAL24MHZ_PWRUP 0x00000010
50#define BM_RTC_PERSISTENT0_XTAL32KHZ_PWRUP 0x00000020
51#define BM_RTC_PERSISTENT0_ALARM_WAKE 0x00000080
52#define BM_RTC_PERSISTENT0_SPARE_ANALOG 0xFFFC0000
53#define BP_RTC_PERSISTENT0_SPARE_ANALOG 18
54
55#define HW_RTC_PERSISTENT1 0x70
56#define BM_RTC_PERSISTENT1_GENERAL 0xFFFFFFFF
57#define BP_RTC_PERSISTENT1_GENERAL 0
58
59#define HW_RTC_VERSION 0xD0
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-saif.h b/arch/arm/mach-stmp378x/include/mach/regs-saif.h
deleted file mode 100644
index 6df41762c2a3..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-saif.h
+++ /dev/null
@@ -1,21 +0,0 @@
1/*
2 * stmp378x: SAIF register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_SAIF_SIZE 0x2000
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-spdif.h b/arch/arm/mach-stmp378x/include/mach/regs-spdif.h
deleted file mode 100644
index 801539848c28..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-spdif.h
+++ /dev/null
@@ -1,49 +0,0 @@
1/*
2 * stmp378x: SPDIF register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_SPDIF_BASE (STMP3XXX_REGS_BASE + 0x54000)
22#define REGS_SPDIF_PHYS 0x80054000
23#define REGS_SPDIF_SIZE 0x2000
24
25#define HW_SPDIF_CTRL 0x0
26#define BM_SPDIF_CTRL_RUN 0x00000001
27#define BP_SPDIF_CTRL_RUN 0
28#define BM_SPDIF_CTRL_FIFO_ERROR_IRQ_EN 0x00000002
29#define BM_SPDIF_CTRL_FIFO_OVERFLOW_IRQ 0x00000004
30#define BM_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008
31#define BM_SPDIF_CTRL_WORD_LENGTH 0x00000010
32#define BM_SPDIF_CTRL_CLKGATE 0x40000000
33#define BM_SPDIF_CTRL_SFTRST 0x80000000
34
35#define HW_SPDIF_STAT 0x10
36
37#define HW_SPDIF_FRAMECTRL 0x20
38
39#define HW_SPDIF_SRR 0x30
40#define BM_SPDIF_SRR_RATE 0x000FFFFF
41#define BP_SPDIF_SRR_RATE 0
42#define BM_SPDIF_SRR_BASEMULT 0x70000000
43#define BP_SPDIF_SRR_BASEMULT 28
44
45#define HW_SPDIF_DEBUG 0x40
46
47#define HW_SPDIF_DATA 0x50
48
49#define HW_SPDIF_VERSION 0x60
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-ssp.h b/arch/arm/mach-stmp378x/include/mach/regs-ssp.h
deleted file mode 100644
index 28aacf0f58ed..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-ssp.h
+++ /dev/null
@@ -1,102 +0,0 @@
1/*
2 * stmp378x: SSP register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_SSP1_BASE (STMP3XXX_REGS_BASE + 0x10000)
22#define REGS_SSP1_PHYS 0x80010000
23#define REGS_SSP2_BASE (STMP3XXX_REGS_BASE + 0x34000)
24#define REGS_SSP2_PHYS 0x80034000
25#define REGS_SSP_SIZE 0x2000
26
27#define HW_SSP_CTRL0 0x0
28#define BM_SSP_CTRL0_XFER_COUNT 0x0000FFFF
29#define BP_SSP_CTRL0_XFER_COUNT 0
30#define BM_SSP_CTRL0_ENABLE 0x00010000
31#define BM_SSP_CTRL0_GET_RESP 0x00020000
32#define BM_SSP_CTRL0_LONG_RESP 0x00080000
33#define BM_SSP_CTRL0_WAIT_FOR_CMD 0x00100000
34#define BM_SSP_CTRL0_WAIT_FOR_IRQ 0x00200000
35#define BM_SSP_CTRL0_BUS_WIDTH 0x00C00000
36#define BP_SSP_CTRL0_BUS_WIDTH 22
37#define BM_SSP_CTRL0_DATA_XFER 0x01000000
38#define BM_SSP_CTRL0_READ 0x02000000
39#define BM_SSP_CTRL0_IGNORE_CRC 0x04000000
40#define BM_SSP_CTRL0_LOCK_CS 0x08000000
41#define BM_SSP_CTRL0_RUN 0x20000000
42#define BM_SSP_CTRL0_CLKGATE 0x40000000
43#define BM_SSP_CTRL0_SFTRST 0x80000000
44
45#define HW_SSP_CMD0 0x10
46#define BM_SSP_CMD0_CMD 0x000000FF
47#define BP_SSP_CMD0_CMD 0
48#define BM_SSP_CMD0_BLOCK_COUNT 0x0000FF00
49#define BP_SSP_CMD0_BLOCK_COUNT 8
50#define BM_SSP_CMD0_BLOCK_SIZE 0x000F0000
51#define BP_SSP_CMD0_BLOCK_SIZE 16
52#define BM_SSP_CMD0_APPEND_8CYC 0x00100000
53#define BM_SSP_CMD1_CMD_ARG 0xFFFFFFFF
54#define BP_SSP_CMD1_CMD_ARG 0
55
56#define HW_SSP_TIMING 0x50
57#define BM_SSP_TIMING_CLOCK_RATE 0x000000FF
58#define BP_SSP_TIMING_CLOCK_RATE 0
59#define BM_SSP_TIMING_CLOCK_DIVIDE 0x0000FF00
60#define BP_SSP_TIMING_CLOCK_DIVIDE 8
61#define BM_SSP_TIMING_TIMEOUT 0xFFFF0000
62#define BP_SSP_TIMING_TIMEOUT 16
63
64#define HW_SSP_CTRL1 0x60
65#define BM_SSP_CTRL1_SSP_MODE 0x0000000F
66#define BP_SSP_CTRL1_SSP_MODE 0
67#define BM_SSP_CTRL1_WORD_LENGTH 0x000000F0
68#define BP_SSP_CTRL1_WORD_LENGTH 4
69#define BM_SSP_CTRL1_POLARITY 0x00000200
70#define BM_SSP_CTRL1_PHASE 0x00000400
71#define BM_SSP_CTRL1_DMA_ENABLE 0x00002000
72#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ 0x00008000
73#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN 0x00010000
74#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ 0x00020000
75#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ 0x00200000
76#define BM_SSP_CTRL1_DATA_CRC_IRQ_EN 0x00400000
77#define BM_SSP_CTRL1_DATA_CRC_IRQ 0x00800000
78#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN 0x01000000
79#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ 0x02000000
80#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN 0x04000000
81#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ 0x08000000
82#define BM_SSP_CTRL1_RESP_ERR_IRQ_EN 0x10000000
83#define BM_SSP_CTRL1_RESP_ERR_IRQ 0x20000000
84#define BM_SSP_CTRL1_SDIO_IRQ 0x80000000
85
86#define HW_SSP_DATA 0x70
87
88#define HW_SSP_SDRESP0 0x80
89
90#define HW_SSP_SDRESP1 0x90
91
92#define HW_SSP_SDRESP2 0xA0
93
94#define HW_SSP_SDRESP3 0xB0
95
96#define HW_SSP_STATUS 0xC0
97#define BM_SSP_STATUS_FIFO_EMPTY 0x00000020
98#define BM_SSP_STATUS_TIMEOUT 0x00001000
99#define BM_SSP_STATUS_RESP_TIMEOUT 0x00004000
100#define BM_SSP_STATUS_RESP_ERR 0x00008000
101#define BM_SSP_STATUS_RESP_CRC_ERR 0x00010000
102#define BM_SSP_STATUS_CARD_DETECT 0x10000000
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-sydma.h b/arch/arm/mach-stmp378x/include/mach/regs-sydma.h
deleted file mode 100644
index 08343a8b5566..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-sydma.h
+++ /dev/null
@@ -1,23 +0,0 @@
1/*
2 * stmp378x: SYDMA register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_SYDMA_BASE (STMP3XXX_REGS_BASE + 0x26000)
22#define REGS_SYDMA_PHYS 0x80026000
23#define REGS_SYDMA_SIZE 0x2000
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-timrot.h b/arch/arm/mach-stmp378x/include/mach/regs-timrot.h
deleted file mode 100644
index b5527957c67f..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-timrot.h
+++ /dev/null
@@ -1,68 +0,0 @@
1/*
2 * stmp378x: TIMROT register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef _MACH_REGS_TIMROT
22#define _MACH_REGS_TIMROT
23
24#define REGS_TIMROT_BASE (STMP3XXX_REGS_BASE + 0x68000)
25#define REGS_TIMROT_PHYS 0x80068000
26#define REGS_TIMROT_SIZE 0x2000
27
28#define HW_TIMROT_ROTCTRL 0x0
29#define BM_TIMROT_ROTCTRL_SELECT_A 0x00000007
30#define BP_TIMROT_ROTCTRL_SELECT_A 0
31#define BM_TIMROT_ROTCTRL_SELECT_B 0x00000070
32#define BP_TIMROT_ROTCTRL_SELECT_B 4
33#define BM_TIMROT_ROTCTRL_POLARITY_A 0x00000100
34#define BM_TIMROT_ROTCTRL_POLARITY_B 0x00000200
35#define BM_TIMROT_ROTCTRL_OVERSAMPLE 0x00000C00
36#define BP_TIMROT_ROTCTRL_OVERSAMPLE 10
37#define BM_TIMROT_ROTCTRL_RELATIVE 0x00001000
38#define BM_TIMROT_ROTCTRL_DIVIDER 0x003F0000
39#define BP_TIMROT_ROTCTRL_DIVIDER 16
40#define BM_TIMROT_ROTCTRL_ROTARY_PRESENT 0x20000000
41#define BM_TIMROT_ROTCTRL_CLKGATE 0x40000000
42#define BM_TIMROT_ROTCTRL_SFTRST 0x80000000
43
44#define HW_TIMROT_ROTCOUNT 0x10
45#define BM_TIMROT_ROTCOUNT_UPDOWN 0x0000FFFF
46#define BP_TIMROT_ROTCOUNT_UPDOWN 0
47
48#define HW_TIMROT_TIMCTRL0 (0x20 + 0 * 0x20)
49#define HW_TIMROT_TIMCTRL1 (0x20 + 1 * 0x20)
50#define HW_TIMROT_TIMCTRL2 (0x20 + 2 * 0x20)
51
52#define HW_TIMROT_TIMCTRLn 0x20
53#define BM_TIMROT_TIMCTRLn_SELECT 0x0000000F
54#define BP_TIMROT_TIMCTRLn_SELECT 0
55#define BM_TIMROT_TIMCTRLn_PRESCALE 0x00000030
56#define BP_TIMROT_TIMCTRLn_PRESCALE 4
57#define BM_TIMROT_TIMCTRLn_RELOAD 0x00000040
58#define BM_TIMROT_TIMCTRLn_UPDATE 0x00000080
59#define BM_TIMROT_TIMCTRLn_IRQ_EN 0x00004000
60#define BM_TIMROT_TIMCTRLn_IRQ 0x00008000
61
62#define HW_TIMROT_TIMCOUNT0 (0x30 + 0 * 0x20)
63#define HW_TIMROT_TIMCOUNT1 (0x30 + 1 * 0x20)
64#define HW_TIMROT_TIMCOUNT2 (0x30 + 2 * 0x20)
65
66#define HW_TIMROT_TIMCOUNTn 0x30
67
68#endif
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-tvenc.h b/arch/arm/mach-stmp378x/include/mach/regs-tvenc.h
deleted file mode 100644
index 7f895cb34350..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-tvenc.h
+++ /dev/null
@@ -1,67 +0,0 @@
1/*
2 * stmp378x: TVENC register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_TVENC_BASE (STMP3XXX_REGS_BASE + 0x38000)
22#define REGS_TVENC_PHYS 0x80038000
23#define REGS_TVENC_SIZE 0x2000
24
25#define HW_TVENC_CTRL 0x0
26#define BM_TVENC_CTRL_CLKGATE 0x40000000
27#define BM_TVENC_CTRL_SFTRST 0x80000000
28
29#define HW_TVENC_CONFIG 0x10
30#define BM_TVENC_CONFIG_ENCD_MODE 0x00000007
31#define BP_TVENC_CONFIG_ENCD_MODE 0
32#define BM_TVENC_CONFIG_SYNC_MODE 0x00000070
33#define BP_TVENC_CONFIG_SYNC_MODE 4
34#define BM_TVENC_CONFIG_FSYNC_PHS 0x00000200
35#define BM_TVENC_CONFIG_CGAIN 0x0000C000
36#define BP_TVENC_CONFIG_CGAIN 14
37#define BM_TVENC_CONFIG_YGAIN_SEL 0x00030000
38#define BP_TVENC_CONFIG_YGAIN_SEL 16
39#define BM_TVENC_CONFIG_PAL_SHAPE 0x00100000
40
41#define HW_TVENC_SYNCOFFSET 0x30
42
43#define HW_TVENC_COLORSUB0 0xC0
44
45#define HW_TVENC_COLORBURST 0x140
46#define BM_TVENC_COLORBURST_PBA 0x00FF0000
47#define BP_TVENC_COLORBURST_PBA 16
48#define BM_TVENC_COLORBURST_NBA 0xFF000000
49#define BP_TVENC_COLORBURST_NBA 24
50
51#define HW_TVENC_MACROVISION0 0x150
52
53#define HW_TVENC_MACROVISION1 0x160
54
55#define HW_TVENC_MACROVISION2 0x170
56
57#define HW_TVENC_MACROVISION3 0x180
58
59#define HW_TVENC_MACROVISION4 0x190
60
61#define HW_TVENC_DACCTRL 0x1A0
62#define BM_TVENC_DACCTRL_RVAL 0x00000070
63#define BP_TVENC_DACCTRL_RVAL 4
64#define BM_TVENC_DACCTRL_DUMP_TOVDD1 0x00000100
65#define BM_TVENC_DACCTRL_PWRUP1 0x00001000
66#define BM_TVENC_DACCTRL_GAINUP 0x00040000
67#define BM_TVENC_DACCTRL_GAINDN 0x00080000
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-uartapp.h b/arch/arm/mach-stmp378x/include/mach/regs-uartapp.h
deleted file mode 100644
index a251e68bb3a1..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-uartapp.h
+++ /dev/null
@@ -1,87 +0,0 @@
1/*
2 * stmp378x: UARTAPP register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_UARTAPP1_BASE (STMP3XXX_REGS_BASE + 0x6C000)
22#define REGS_UARTAPP1_PHYS 0x8006C000
23#define REGS_UARTAPP2_BASE (STMP3XXX_REGS_BASE + 0x6E000)
24#define REGS_UARTAPP2_PHYS 0x8006E000
25#define REGS_UARTAPP_SIZE 0x2000
26
27#define HW_UARTAPP_CTRL0 0x0
28#define BM_UARTAPP_CTRL0_XFER_COUNT 0x0000FFFF
29#define BP_UARTAPP_CTRL0_XFER_COUNT 0
30#define BM_UARTAPP_CTRL0_RXTIMEOUT 0x07FF0000
31#define BP_UARTAPP_CTRL0_RXTIMEOUT 16
32#define BM_UARTAPP_CTRL0_RXTO_ENABLE 0x08000000
33#define BM_UARTAPP_CTRL0_RUN 0x20000000
34#define BM_UARTAPP_CTRL0_SFTRST 0x80000000
35#define BM_UARTAPP_CTRL1_XFER_COUNT 0x0000FFFF
36#define BP_UARTAPP_CTRL1_XFER_COUNT 0
37#define BM_UARTAPP_CTRL1_RUN 0x10000000
38
39#define HW_UARTAPP_CTRL2 0x20
40#define BM_UARTAPP_CTRL2_UARTEN 0x00000001
41#define BP_UARTAPP_CTRL2_UARTEN 0
42#define BM_UARTAPP_CTRL2_TXE 0x00000100
43#define BM_UARTAPP_CTRL2_RXE 0x00000200
44#define BM_UARTAPP_CTRL2_RTS 0x00000800
45#define BM_UARTAPP_CTRL2_RTSEN 0x00004000
46#define BM_UARTAPP_CTRL2_CTSEN 0x00008000
47#define BM_UARTAPP_CTRL2_RXDMAE 0x01000000
48#define BM_UARTAPP_CTRL2_TXDMAE 0x02000000
49#define BM_UARTAPP_CTRL2_DMAONERR 0x04000000
50
51#define HW_UARTAPP_LINECTRL 0x30
52#define BM_UARTAPP_LINECTRL_BRK 0x00000001
53#define BP_UARTAPP_LINECTRL_BRK 0
54#define BM_UARTAPP_LINECTRL_PEN 0x00000002
55#define BM_UARTAPP_LINECTRL_EPS 0x00000004
56#define BM_UARTAPP_LINECTRL_STP2 0x00000008
57#define BM_UARTAPP_LINECTRL_FEN 0x00000010
58#define BM_UARTAPP_LINECTRL_WLEN 0x00000060
59#define BP_UARTAPP_LINECTRL_WLEN 5
60#define BM_UARTAPP_LINECTRL_SPS 0x00000080
61#define BM_UARTAPP_LINECTRL_BAUD_DIVFRAC 0x00003F00
62#define BP_UARTAPP_LINECTRL_BAUD_DIVFRAC 8
63#define BM_UARTAPP_LINECTRL_BAUD_DIVINT 0xFFFF0000
64#define BP_UARTAPP_LINECTRL_BAUD_DIVINT 16
65
66#define HW_UARTAPP_INTR 0x50
67#define BM_UARTAPP_INTR_CTSMIS 0x00000002
68#define BM_UARTAPP_INTR_RTIS 0x00000040
69#define BM_UARTAPP_INTR_CTSMIEN 0x00020000
70#define BM_UARTAPP_INTR_RXIEN 0x00100000
71#define BM_UARTAPP_INTR_RTIEN 0x00400000
72
73#define HW_UARTAPP_DATA 0x60
74
75#define HW_UARTAPP_STAT 0x70
76#define BM_UARTAPP_STAT_RXCOUNT 0x0000FFFF
77#define BP_UARTAPP_STAT_RXCOUNT 0
78#define BM_UARTAPP_STAT_FERR 0x00010000
79#define BM_UARTAPP_STAT_PERR 0x00020000
80#define BM_UARTAPP_STAT_BERR 0x00040000
81#define BM_UARTAPP_STAT_OERR 0x00080000
82#define BM_UARTAPP_STAT_RXFE 0x01000000
83#define BM_UARTAPP_STAT_TXFF 0x02000000
84#define BM_UARTAPP_STAT_TXFE 0x08000000
85#define BM_UARTAPP_STAT_CTS 0x10000000
86
87#define HW_UARTAPP_VERSION 0x90
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-uartdbg.h b/arch/arm/mach-stmp378x/include/mach/regs-uartdbg.h
deleted file mode 100644
index b810deb552a9..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-uartdbg.h
+++ /dev/null
@@ -1,268 +0,0 @@
1/*
2 * stmp378x: UARTDBG register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_UARTDBG_BASE (STMP3XXX_REGS_BASE + 0x70000)
22#define REGS_UARTDBG_PHYS 0x80070000
23#define REGS_UARTDBG_SIZE 0x2000
24
25#define HW_UARTDBGDR 0x00000000
26#define BP_UARTDBGDR_UNAVAILABLE 16
27#define BM_UARTDBGDR_UNAVAILABLE 0xFFFF0000
28#define BF_UARTDBGDR_UNAVAILABLE(v) \
29 (((v) << 16) & BM_UARTDBGDR_UNAVAILABLE)
30#define BP_UARTDBGDR_RESERVED 12
31#define BM_UARTDBGDR_RESERVED 0x0000F000
32#define BF_UARTDBGDR_RESERVED(v) \
33 (((v) << 12) & BM_UARTDBGDR_RESERVED)
34#define BM_UARTDBGDR_OE 0x00000800
35#define BM_UARTDBGDR_BE 0x00000400
36#define BM_UARTDBGDR_PE 0x00000200
37#define BM_UARTDBGDR_FE 0x00000100
38#define BP_UARTDBGDR_DATA 0
39#define BM_UARTDBGDR_DATA 0x000000FF
40#define BF_UARTDBGDR_DATA(v) \
41 (((v) << 0) & BM_UARTDBGDR_DATA)
42#define HW_UARTDBGRSR_ECR 0x00000004
43#define BP_UARTDBGRSR_ECR_UNAVAILABLE 8
44#define BM_UARTDBGRSR_ECR_UNAVAILABLE 0xFFFFFF00
45#define BF_UARTDBGRSR_ECR_UNAVAILABLE(v) \
46 (((v) << 8) & BM_UARTDBGRSR_ECR_UNAVAILABLE)
47#define BP_UARTDBGRSR_ECR_EC 4
48#define BM_UARTDBGRSR_ECR_EC 0x000000F0
49#define BF_UARTDBGRSR_ECR_EC(v) \
50 (((v) << 4) & BM_UARTDBGRSR_ECR_EC)
51#define BM_UARTDBGRSR_ECR_OE 0x00000008
52#define BM_UARTDBGRSR_ECR_BE 0x00000004
53#define BM_UARTDBGRSR_ECR_PE 0x00000002
54#define BM_UARTDBGRSR_ECR_FE 0x00000001
55#define HW_UARTDBGFR 0x00000018
56#define BP_UARTDBGFR_UNAVAILABLE 16
57#define BM_UARTDBGFR_UNAVAILABLE 0xFFFF0000
58#define BF_UARTDBGFR_UNAVAILABLE(v) \
59 (((v) << 16) & BM_UARTDBGFR_UNAVAILABLE)
60#define BP_UARTDBGFR_RESERVED 9
61#define BM_UARTDBGFR_RESERVED 0x0000FE00
62#define BF_UARTDBGFR_RESERVED(v) \
63 (((v) << 9) & BM_UARTDBGFR_RESERVED)
64#define BM_UARTDBGFR_RI 0x00000100
65#define BM_UARTDBGFR_TXFE 0x00000080
66#define BM_UARTDBGFR_RXFF 0x00000040
67#define BM_UARTDBGFR_TXFF 0x00000020
68#define BM_UARTDBGFR_RXFE 0x00000010
69#define BM_UARTDBGFR_BUSY 0x00000008
70#define BM_UARTDBGFR_DCD 0x00000004
71#define BM_UARTDBGFR_DSR 0x00000002
72#define BM_UARTDBGFR_CTS 0x00000001
73#define HW_UARTDBGILPR 0x00000020
74#define BP_UARTDBGILPR_UNAVAILABLE 8
75#define BM_UARTDBGILPR_UNAVAILABLE 0xFFFFFF00
76#define BF_UARTDBGILPR_UNAVAILABLE(v) \
77 (((v) << 8) & BM_UARTDBGILPR_UNAVAILABLE)
78#define BP_UARTDBGILPR_ILPDVSR 0
79#define BM_UARTDBGILPR_ILPDVSR 0x000000FF
80#define BF_UARTDBGILPR_ILPDVSR(v) \
81 (((v) << 0) & BM_UARTDBGILPR_ILPDVSR)
82#define HW_UARTDBGIBRD 0x00000024
83#define BP_UARTDBGIBRD_UNAVAILABLE 16
84#define BM_UARTDBGIBRD_UNAVAILABLE 0xFFFF0000
85#define BF_UARTDBGIBRD_UNAVAILABLE(v) \
86 (((v) << 16) & BM_UARTDBGIBRD_UNAVAILABLE)
87#define BP_UARTDBGIBRD_BAUD_DIVINT 0
88#define BM_UARTDBGIBRD_BAUD_DIVINT 0x0000FFFF
89#define BF_UARTDBGIBRD_BAUD_DIVINT(v) \
90 (((v) << 0) & BM_UARTDBGIBRD_BAUD_DIVINT)
91#define HW_UARTDBGFBRD 0x00000028
92#define BP_UARTDBGFBRD_UNAVAILABLE 8
93#define BM_UARTDBGFBRD_UNAVAILABLE 0xFFFFFF00
94#define BF_UARTDBGFBRD_UNAVAILABLE(v) \
95 (((v) << 8) & BM_UARTDBGFBRD_UNAVAILABLE)
96#define BP_UARTDBGFBRD_RESERVED 6
97#define BM_UARTDBGFBRD_RESERVED 0x000000C0
98#define BF_UARTDBGFBRD_RESERVED(v) \
99 (((v) << 6) & BM_UARTDBGFBRD_RESERVED)
100#define BP_UARTDBGFBRD_BAUD_DIVFRAC 0
101#define BM_UARTDBGFBRD_BAUD_DIVFRAC 0x0000003F
102#define BF_UARTDBGFBRD_BAUD_DIVFRAC(v) \
103 (((v) << 0) & BM_UARTDBGFBRD_BAUD_DIVFRAC)
104#define HW_UARTDBGLCR_H 0x0000002c
105#define BP_UARTDBGLCR_H_UNAVAILABLE 16
106#define BM_UARTDBGLCR_H_UNAVAILABLE 0xFFFF0000
107#define BF_UARTDBGLCR_H_UNAVAILABLE(v) \
108 (((v) << 16) & BM_UARTDBGLCR_H_UNAVAILABLE)
109#define BP_UARTDBGLCR_H_RESERVED 8
110#define BM_UARTDBGLCR_H_RESERVED 0x0000FF00
111#define BF_UARTDBGLCR_H_RESERVED(v) \
112 (((v) << 8) & BM_UARTDBGLCR_H_RESERVED)
113#define BM_UARTDBGLCR_H_SPS 0x00000080
114#define BP_UARTDBGLCR_H_WLEN 5
115#define BM_UARTDBGLCR_H_WLEN 0x00000060
116#define BF_UARTDBGLCR_H_WLEN(v) \
117 (((v) << 5) & BM_UARTDBGLCR_H_WLEN)
118#define BM_UARTDBGLCR_H_FEN 0x00000010
119#define BM_UARTDBGLCR_H_STP2 0x00000008
120#define BM_UARTDBGLCR_H_EPS 0x00000004
121#define BM_UARTDBGLCR_H_PEN 0x00000002
122#define BM_UARTDBGLCR_H_BRK 0x00000001
123#define HW_UARTDBGCR 0x00000030
124#define BP_UARTDBGCR_UNAVAILABLE 16
125#define BM_UARTDBGCR_UNAVAILABLE 0xFFFF0000
126#define BF_UARTDBGCR_UNAVAILABLE(v) \
127 (((v) << 16) & BM_UARTDBGCR_UNAVAILABLE)
128#define BM_UARTDBGCR_CTSEN 0x00008000
129#define BM_UARTDBGCR_RTSEN 0x00004000
130#define BM_UARTDBGCR_OUT2 0x00002000
131#define BM_UARTDBGCR_OUT1 0x00001000
132#define BM_UARTDBGCR_RTS 0x00000800
133#define BM_UARTDBGCR_DTR 0x00000400
134#define BM_UARTDBGCR_RXE 0x00000200
135#define BM_UARTDBGCR_TXE 0x00000100
136#define BM_UARTDBGCR_LBE 0x00000080
137#define BP_UARTDBGCR_RESERVED 3
138#define BM_UARTDBGCR_RESERVED 0x00000078
139#define BF_UARTDBGCR_RESERVED(v) \
140 (((v) << 3) & BM_UARTDBGCR_RESERVED)
141#define BM_UARTDBGCR_SIRLP 0x00000004
142#define BM_UARTDBGCR_SIREN 0x00000002
143#define BM_UARTDBGCR_UARTEN 0x00000001
144#define HW_UARTDBGIFLS 0x00000034
145#define BP_UARTDBGIFLS_UNAVAILABLE 16
146#define BM_UARTDBGIFLS_UNAVAILABLE 0xFFFF0000
147#define BF_UARTDBGIFLS_UNAVAILABLE(v) \
148 (((v) << 16) & BM_UARTDBGIFLS_UNAVAILABLE)
149#define BP_UARTDBGIFLS_RESERVED 6
150#define BM_UARTDBGIFLS_RESERVED 0x0000FFC0
151#define BF_UARTDBGIFLS_RESERVED(v) \
152 (((v) << 6) & BM_UARTDBGIFLS_RESERVED)
153#define BP_UARTDBGIFLS_RXIFLSEL 3
154#define BM_UARTDBGIFLS_RXIFLSEL 0x00000038
155#define BF_UARTDBGIFLS_RXIFLSEL(v) \
156 (((v) << 3) & BM_UARTDBGIFLS_RXIFLSEL)
157#define BV_UARTDBGIFLS_RXIFLSEL__NOT_EMPTY 0x0
158#define BV_UARTDBGIFLS_RXIFLSEL__ONE_QUARTER 0x1
159#define BV_UARTDBGIFLS_RXIFLSEL__ONE_HALF 0x2
160#define BV_UARTDBGIFLS_RXIFLSEL__THREE_QUARTERS 0x3
161#define BV_UARTDBGIFLS_RXIFLSEL__SEVEN_EIGHTHS 0x4
162#define BV_UARTDBGIFLS_RXIFLSEL__INVALID5 0x5
163#define BV_UARTDBGIFLS_RXIFLSEL__INVALID6 0x6
164#define BV_UARTDBGIFLS_RXIFLSEL__INVALID7 0x7
165#define BP_UARTDBGIFLS_TXIFLSEL 0
166#define BM_UARTDBGIFLS_TXIFLSEL 0x00000007
167#define BF_UARTDBGIFLS_TXIFLSEL(v) \
168 (((v) << 0) & BM_UARTDBGIFLS_TXIFLSEL)
169#define BV_UARTDBGIFLS_TXIFLSEL__EMPTY 0x0
170#define BV_UARTDBGIFLS_TXIFLSEL__ONE_QUARTER 0x1
171#define BV_UARTDBGIFLS_TXIFLSEL__ONE_HALF 0x2
172#define BV_UARTDBGIFLS_TXIFLSEL__THREE_QUARTERS 0x3
173#define BV_UARTDBGIFLS_TXIFLSEL__SEVEN_EIGHTHS 0x4
174#define BV_UARTDBGIFLS_TXIFLSEL__INVALID5 0x5
175#define BV_UARTDBGIFLS_TXIFLSEL__INVALID6 0x6
176#define BV_UARTDBGIFLS_TXIFLSEL__INVALID7 0x7
177#define HW_UARTDBGIMSC 0x00000038
178#define BP_UARTDBGIMSC_UNAVAILABLE 16
179#define BM_UARTDBGIMSC_UNAVAILABLE 0xFFFF0000
180#define BF_UARTDBGIMSC_UNAVAILABLE(v) \
181 (((v) << 16) & BM_UARTDBGIMSC_UNAVAILABLE)
182#define BP_UARTDBGIMSC_RESERVED 11
183#define BM_UARTDBGIMSC_RESERVED 0x0000F800
184#define BF_UARTDBGIMSC_RESERVED(v) \
185 (((v) << 11) & BM_UARTDBGIMSC_RESERVED)
186#define BM_UARTDBGIMSC_OEIM 0x00000400
187#define BM_UARTDBGIMSC_BEIM 0x00000200
188#define BM_UARTDBGIMSC_PEIM 0x00000100
189#define BM_UARTDBGIMSC_FEIM 0x00000080
190#define BM_UARTDBGIMSC_RTIM 0x00000040
191#define BM_UARTDBGIMSC_TXIM 0x00000020
192#define BM_UARTDBGIMSC_RXIM 0x00000010
193#define BM_UARTDBGIMSC_DSRMIM 0x00000008
194#define BM_UARTDBGIMSC_DCDMIM 0x00000004
195#define BM_UARTDBGIMSC_CTSMIM 0x00000002
196#define BM_UARTDBGIMSC_RIMIM 0x00000001
197#define HW_UARTDBGRIS 0x0000003c
198#define BP_UARTDBGRIS_UNAVAILABLE 16
199#define BM_UARTDBGRIS_UNAVAILABLE 0xFFFF0000
200#define BF_UARTDBGRIS_UNAVAILABLE(v) \
201 (((v) << 16) & BM_UARTDBGRIS_UNAVAILABLE)
202#define BP_UARTDBGRIS_RESERVED 11
203#define BM_UARTDBGRIS_RESERVED 0x0000F800
204#define BF_UARTDBGRIS_RESERVED(v) \
205 (((v) << 11) & BM_UARTDBGRIS_RESERVED)
206#define BM_UARTDBGRIS_OERIS 0x00000400
207#define BM_UARTDBGRIS_BERIS 0x00000200
208#define BM_UARTDBGRIS_PERIS 0x00000100
209#define BM_UARTDBGRIS_FERIS 0x00000080
210#define BM_UARTDBGRIS_RTRIS 0x00000040
211#define BM_UARTDBGRIS_TXRIS 0x00000020
212#define BM_UARTDBGRIS_RXRIS 0x00000010
213#define BM_UARTDBGRIS_DSRRMIS 0x00000008
214#define BM_UARTDBGRIS_DCDRMIS 0x00000004
215#define BM_UARTDBGRIS_CTSRMIS 0x00000002
216#define BM_UARTDBGRIS_RIRMIS 0x00000001
217#define HW_UARTDBGMIS 0x00000040
218#define BP_UARTDBGMIS_UNAVAILABLE 16
219#define BM_UARTDBGMIS_UNAVAILABLE 0xFFFF0000
220#define BF_UARTDBGMIS_UNAVAILABLE(v) \
221 (((v) << 16) & BM_UARTDBGMIS_UNAVAILABLE)
222#define BP_UARTDBGMIS_RESERVED 11
223#define BM_UARTDBGMIS_RESERVED 0x0000F800
224#define BF_UARTDBGMIS_RESERVED(v) \
225 (((v) << 11) & BM_UARTDBGMIS_RESERVED)
226#define BM_UARTDBGMIS_OEMIS 0x00000400
227#define BM_UARTDBGMIS_BEMIS 0x00000200
228#define BM_UARTDBGMIS_PEMIS 0x00000100
229#define BM_UARTDBGMIS_FEMIS 0x00000080
230#define BM_UARTDBGMIS_RTMIS 0x00000040
231#define BM_UARTDBGMIS_TXMIS 0x00000020
232#define BM_UARTDBGMIS_RXMIS 0x00000010
233#define BM_UARTDBGMIS_DSRMMIS 0x00000008
234#define BM_UARTDBGMIS_DCDMMIS 0x00000004
235#define BM_UARTDBGMIS_CTSMMIS 0x00000002
236#define BM_UARTDBGMIS_RIMMIS 0x00000001
237#define HW_UARTDBGICR 0x00000044
238#define BP_UARTDBGICR_UNAVAILABLE 16
239#define BM_UARTDBGICR_UNAVAILABLE 0xFFFF0000
240#define BF_UARTDBGICR_UNAVAILABLE(v) \
241 (((v) << 16) & BM_UARTDBGICR_UNAVAILABLE)
242#define BP_UARTDBGICR_RESERVED 11
243#define BM_UARTDBGICR_RESERVED 0x0000F800
244#define BF_UARTDBGICR_RESERVED(v) \
245 (((v) << 11) & BM_UARTDBGICR_RESERVED)
246#define BM_UARTDBGICR_OEIC 0x00000400
247#define BM_UARTDBGICR_BEIC 0x00000200
248#define BM_UARTDBGICR_PEIC 0x00000100
249#define BM_UARTDBGICR_FEIC 0x00000080
250#define BM_UARTDBGICR_RTIC 0x00000040
251#define BM_UARTDBGICR_TXIC 0x00000020
252#define BM_UARTDBGICR_RXIC 0x00000010
253#define BM_UARTDBGICR_DSRMIC 0x00000008
254#define BM_UARTDBGICR_DCDMIC 0x00000004
255#define BM_UARTDBGICR_CTSMIC 0x00000002
256#define BM_UARTDBGICR_RIMIC 0x00000001
257#define HW_UARTDBGDMACR 0x00000048
258#define BP_UARTDBGDMACR_UNAVAILABLE 16
259#define BM_UARTDBGDMACR_UNAVAILABLE 0xFFFF0000
260#define BF_UARTDBGDMACR_UNAVAILABLE(v) \
261 (((v) << 16) & BM_UARTDBGDMACR_UNAVAILABLE)
262#define BP_UARTDBGDMACR_RESERVED 3
263#define BM_UARTDBGDMACR_RESERVED 0x0000FFF8
264#define BF_UARTDBGDMACR_RESERVED(v) \
265 (((v) << 3) & BM_UARTDBGDMACR_RESERVED)
266#define BM_UARTDBGDMACR_DMAONERR 0x00000004
267#define BM_UARTDBGDMACR_TXDMAE 0x00000002
268#define BM_UARTDBGDMACR_RXDMAE 0x00000001
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-usbctrl.h b/arch/arm/mach-stmp378x/include/mach/regs-usbctrl.h
deleted file mode 100644
index 25112c1aa608..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-usbctrl.h
+++ /dev/null
@@ -1,40 +0,0 @@
1/*
2 * stmp378x: USBCTRL register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_USBCTRL_BASE (STMP3XXX_REGS_BASE + 0x80000)
22#define REGS_USBCTRL_PHYS 0x80080000
23#define REGS_USBCTRL_SIZE 0x2000
24
25#define HW_USBCTRL_USBCMD 0x140
26#define BM_USBCTRL_USBCMD_RS 0x00000001
27#define BP_USBCTRL_USBCMD_RS 0
28#define BM_USBCTRL_USBCMD_RST 0x00000002
29
30#define HW_USBCTRL_USBINTR 0x148
31#define BM_USBCTRL_USBINTR_UE 0x00000001
32#define BP_USBCTRL_USBINTR_UE 0
33
34#define HW_USBCTRL_PORTSC1 0x184
35#define BM_USBCTRL_PORTSC1_PHCD 0x00800000
36
37#define HW_USBCTRL_OTGSC 0x1A4
38#define BM_USBCTRL_OTGSC_ID 0x00000100
39#define BM_USBCTRL_OTGSC_IDIS 0x00010000
40#define BM_USBCTRL_OTGSC_IDIE 0x01000000
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-usbphy.h b/arch/arm/mach-stmp378x/include/mach/regs-usbphy.h
deleted file mode 100644
index 11f3b732dc92..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-usbphy.h
+++ /dev/null
@@ -1,37 +0,0 @@
1/*
2 * stmp378x: USBPHY register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_USBPHY_BASE (STMP3XXX_REGS_BASE + 0x7C000)
22#define REGS_USBPHY_PHYS 0x8007C000
23#define REGS_USBPHY_SIZE 0x2000
24
25#define HW_USBPHY_PWD 0x0
26
27#define HW_USBPHY_CTRL 0x30
28#define BM_USBPHY_CTRL_ENHOSTDISCONDETECT 0x00000002
29#define BM_USBPHY_CTRL_ENDEVPLUGINDETECT 0x00000010
30#define BM_USBPHY_CTRL_ENOTGIDDETECT 0x00000080
31#define BM_USBPHY_CTRL_ENIRQDEVPLUGIN 0x00000800
32#define BM_USBPHY_CTRL_CLKGATE 0x40000000
33#define BM_USBPHY_CTRL_SFTRST 0x80000000
34
35#define HW_USBPHY_STATUS 0x40
36#define BM_USBPHY_STATUS_DEVPLUGIN_STATUS 0x00000040
37#define BM_USBPHY_STATUS_OTGID_STATUS 0x00000100
diff --git a/arch/arm/mach-stmp378x/stmp378x.c b/arch/arm/mach-stmp378x/stmp378x.c
deleted file mode 100644
index c2f9fe04c112..000000000000
--- a/arch/arm/mach-stmp378x/stmp378x.c
+++ /dev/null
@@ -1,299 +0,0 @@
1/*
2 * Freescale STMP378X platform support
3 *
4 * Embedded Alley Solutions, Inc <source@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/platform_device.h>
21#include <linux/irq.h>
22#include <linux/dma-mapping.h>
23
24#include <asm/dma.h>
25#include <asm/setup.h>
26#include <asm/mach-types.h>
27
28#include <asm/mach/arch.h>
29#include <asm/mach/irq.h>
30#include <asm/mach/map.h>
31#include <asm/mach/time.h>
32
33#include <mach/pins.h>
34#include <mach/pinmux.h>
35#include <mach/dma.h>
36#include <mach/hardware.h>
37#include <mach/system.h>
38#include <mach/platform.h>
39#include <mach/stmp3xxx.h>
40#include <mach/regs-icoll.h>
41#include <mach/regs-apbh.h>
42#include <mach/regs-apbx.h>
43#include <mach/regs-pxp.h>
44#include <mach/regs-i2c.h>
45
46#include "stmp378x.h"
47/*
48 * IRQ handling
49 */
50static void stmp378x_ack_irq(struct irq_data *d)
51{
52 /* Tell ICOLL to release IRQ line */
53 __raw_writel(0, REGS_ICOLL_BASE + HW_ICOLL_VECTOR);
54
55 /* ACK current interrupt */
56 __raw_writel(0x01 /* BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 */,
57 REGS_ICOLL_BASE + HW_ICOLL_LEVELACK);
58
59 /* Barrier */
60 (void)__raw_readl(REGS_ICOLL_BASE + HW_ICOLL_STAT);
61}
62
63static void stmp378x_mask_irq(struct irq_data *d)
64{
65 /* IRQ disable */
66 stmp3xxx_clearl(BM_ICOLL_INTERRUPTn_ENABLE,
67 REGS_ICOLL_BASE + HW_ICOLL_INTERRUPTn + d->irq * 0x10);
68}
69
70static void stmp378x_unmask_irq(struct irq_data *d)
71{
72 /* IRQ enable */
73 stmp3xxx_setl(BM_ICOLL_INTERRUPTn_ENABLE,
74 REGS_ICOLL_BASE + HW_ICOLL_INTERRUPTn + d->irq * 0x10);
75}
76
77static struct irq_chip stmp378x_chip = {
78 .irq_ack = stmp378x_ack_irq,
79 .irq_mask = stmp378x_mask_irq,
80 .irq_unmask = stmp378x_unmask_irq,
81};
82
83void __init stmp378x_init_irq(void)
84{
85 stmp3xxx_init_irq(&stmp378x_chip);
86}
87
88/*
89 * DMA interrupt handling
90 */
91void stmp3xxx_arch_dma_enable_interrupt(int channel)
92{
93 void __iomem *c1, *c2;
94
95 switch (STMP3XXX_DMA_BUS(channel)) {
96 case STMP3XXX_BUS_APBH:
97 c1 = REGS_APBH_BASE + HW_APBH_CTRL1;
98 c2 = REGS_APBH_BASE + HW_APBH_CTRL2;
99 break;
100
101 case STMP3XXX_BUS_APBX:
102 c1 = REGS_APBX_BASE + HW_APBX_CTRL1;
103 c2 = REGS_APBX_BASE + HW_APBX_CTRL2;
104 break;
105
106 default:
107 return;
108 }
109 stmp3xxx_setl(1 << (16 + STMP3XXX_DMA_CHANNEL(channel)), c1);
110 stmp3xxx_setl(1 << (16 + STMP3XXX_DMA_CHANNEL(channel)), c2);
111}
112EXPORT_SYMBOL(stmp3xxx_arch_dma_enable_interrupt);
113
114void stmp3xxx_arch_dma_clear_interrupt(int channel)
115{
116 void __iomem *c1, *c2;
117
118 switch (STMP3XXX_DMA_BUS(channel)) {
119 case STMP3XXX_BUS_APBH:
120 c1 = REGS_APBH_BASE + HW_APBH_CTRL1;
121 c2 = REGS_APBH_BASE + HW_APBH_CTRL2;
122 break;
123
124 case STMP3XXX_BUS_APBX:
125 c1 = REGS_APBX_BASE + HW_APBX_CTRL1;
126 c2 = REGS_APBX_BASE + HW_APBX_CTRL2;
127 break;
128
129 default:
130 return;
131 }
132 stmp3xxx_clearl(1 << STMP3XXX_DMA_CHANNEL(channel), c1);
133 stmp3xxx_clearl(1 << STMP3XXX_DMA_CHANNEL(channel), c2);
134}
135EXPORT_SYMBOL(stmp3xxx_arch_dma_clear_interrupt);
136
137int stmp3xxx_arch_dma_is_interrupt(int channel)
138{
139 int r = 0;
140
141 switch (STMP3XXX_DMA_BUS(channel)) {
142 case STMP3XXX_BUS_APBH:
143 r = __raw_readl(REGS_APBH_BASE + HW_APBH_CTRL1) &
144 (1 << STMP3XXX_DMA_CHANNEL(channel));
145 break;
146
147 case STMP3XXX_BUS_APBX:
148 r = __raw_readl(REGS_APBX_BASE + HW_APBX_CTRL1) &
149 (1 << STMP3XXX_DMA_CHANNEL(channel));
150 break;
151 }
152 return r;
153}
154EXPORT_SYMBOL(stmp3xxx_arch_dma_is_interrupt);
155
156void stmp3xxx_arch_dma_reset_channel(int channel)
157{
158 unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
159 void __iomem *c0;
160 u32 mask;
161
162 switch (STMP3XXX_DMA_BUS(channel)) {
163 case STMP3XXX_BUS_APBH:
164 c0 = REGS_APBH_BASE + HW_APBH_CTRL0;
165 mask = chbit << BP_APBH_CTRL0_RESET_CHANNEL;
166 break;
167 case STMP3XXX_BUS_APBX:
168 c0 = REGS_APBX_BASE + HW_APBX_CHANNEL_CTRL;
169 mask = chbit << BP_APBX_CHANNEL_CTRL_RESET_CHANNEL;
170 break;
171 default:
172 return;
173 }
174
175 /* Reset channel and wait for it to complete */
176 stmp3xxx_setl(mask, c0);
177 while (__raw_readl(c0) & mask)
178 cpu_relax();
179}
180EXPORT_SYMBOL(stmp3xxx_arch_dma_reset_channel);
181
182void stmp3xxx_arch_dma_freeze(int channel)
183{
184 unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
185 u32 mask = 1 << chbit;
186
187 switch (STMP3XXX_DMA_BUS(channel)) {
188 case STMP3XXX_BUS_APBH:
189 stmp3xxx_setl(mask, REGS_APBH_BASE + HW_APBH_CTRL0);
190 break;
191 case STMP3XXX_BUS_APBX:
192 stmp3xxx_setl(mask, REGS_APBX_BASE + HW_APBX_CHANNEL_CTRL);
193 break;
194 }
195}
196EXPORT_SYMBOL(stmp3xxx_arch_dma_freeze);
197
198void stmp3xxx_arch_dma_unfreeze(int channel)
199{
200 unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
201 u32 mask = 1 << chbit;
202
203 switch (STMP3XXX_DMA_BUS(channel)) {
204 case STMP3XXX_BUS_APBH:
205 stmp3xxx_clearl(mask, REGS_APBH_BASE + HW_APBH_CTRL0);
206 break;
207 case STMP3XXX_BUS_APBX:
208 stmp3xxx_clearl(mask, REGS_APBX_BASE + HW_APBX_CHANNEL_CTRL);
209 break;
210 }
211}
212EXPORT_SYMBOL(stmp3xxx_arch_dma_unfreeze);
213
214/*
215 * The registers are all very closely mapped, so we might as well map them all
216 * with a single mapping
217 *
218 * Logical Physical
219 * f0000000 80000000 On-chip registers
220 * f1000000 00000000 32k on-chip SRAM
221 */
222
223static struct map_desc stmp378x_io_desc[] __initdata = {
224 {
225 .virtual = (u32)STMP3XXX_REGS_BASE,
226 .pfn = __phys_to_pfn(STMP3XXX_REGS_PHBASE),
227 .length = STMP3XXX_REGS_SIZE,
228 .type = MT_DEVICE,
229 },
230 {
231 .virtual = (u32)STMP3XXX_OCRAM_BASE,
232 .pfn = __phys_to_pfn(STMP3XXX_OCRAM_PHBASE),
233 .length = STMP3XXX_OCRAM_SIZE,
234 .type = MT_DEVICE,
235 },
236};
237
238
239static u64 common_dmamask = DMA_BIT_MASK(32);
240
241/*
242 * devices that are present only on stmp378x, not on all 3xxx boards:
243 * PxP
244 * I2C
245 */
246static struct resource pxp_resource[] = {
247 {
248 .flags = IORESOURCE_MEM,
249 .start = REGS_PXP_PHYS,
250 .end = REGS_PXP_PHYS + REGS_PXP_SIZE,
251 }, {
252 .flags = IORESOURCE_IRQ,
253 .start = IRQ_PXP,
254 .end = IRQ_PXP,
255 },
256};
257
258struct platform_device stmp378x_pxp = {
259 .name = "stmp3xxx-pxp",
260 .id = -1,
261 .dev = {
262 .dma_mask = &common_dmamask,
263 .coherent_dma_mask = DMA_BIT_MASK(32),
264 },
265 .num_resources = ARRAY_SIZE(pxp_resource),
266 .resource = pxp_resource,
267};
268
269static struct resource i2c_resources[] = {
270 {
271 .flags = IORESOURCE_IRQ,
272 .start = IRQ_I2C_ERROR,
273 .end = IRQ_I2C_ERROR,
274 }, {
275 .flags = IORESOURCE_MEM,
276 .start = REGS_I2C_PHYS,
277 .end = REGS_I2C_PHYS + REGS_I2C_SIZE,
278 }, {
279 .flags = IORESOURCE_DMA,
280 .start = STMP3XXX_DMA(3, STMP3XXX_BUS_APBX),
281 .end = STMP3XXX_DMA(3, STMP3XXX_BUS_APBX),
282 },
283};
284
285struct platform_device stmp378x_i2c = {
286 .name = "i2c_stmp3xxx",
287 .id = 0,
288 .dev = {
289 .dma_mask = &common_dmamask,
290 .coherent_dma_mask = DMA_BIT_MASK(32),
291 },
292 .resource = i2c_resources,
293 .num_resources = ARRAY_SIZE(i2c_resources),
294};
295
296void __init stmp378x_map_io(void)
297{
298 iotable_init(stmp378x_io_desc, ARRAY_SIZE(stmp378x_io_desc));
299}
diff --git a/arch/arm/mach-stmp378x/stmp378x.h b/arch/arm/mach-stmp378x/stmp378x.h
deleted file mode 100644
index 0dc15b3c891f..000000000000
--- a/arch/arm/mach-stmp378x/stmp378x.h
+++ /dev/null
@@ -1,25 +0,0 @@
1/*
2 * Freescale STMP37XX/STMP378X internal functions and data declarations
3 *
4 * Embedded Alley Solutions, Inc <source@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#ifndef __MACH_STMP378X_H
19#define __MACH_STMP378X_H
20
21void stmp378x_map_io(void);
22void stmp378x_init_irq(void);
23
24extern struct platform_device stmp378x_pxp, stmp378x_i2c;
25#endif /* __MACH_STMP378X_COMMON_H */
diff --git a/arch/arm/mach-stmp378x/stmp378x_devb.c b/arch/arm/mach-stmp378x/stmp378x_devb.c
deleted file mode 100644
index 06158848afd9..000000000000
--- a/arch/arm/mach-stmp378x/stmp378x_devb.c
+++ /dev/null
@@ -1,332 +0,0 @@
1/*
2 * Freescale STMP378X development board support
3 *
4 * Embedded Alley Solutions, Inc <source@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/io.h>
21#include <linux/platform_device.h>
22#include <linux/delay.h>
23#include <linux/clk.h>
24#include <linux/err.h>
25#include <linux/spi/spi.h>
26
27#include <asm/setup.h>
28#include <asm/mach-types.h>
29#include <asm/mach/arch.h>
30
31#include <mach/pins.h>
32#include <mach/pinmux.h>
33#include <mach/platform.h>
34#include <mach/stmp3xxx.h>
35#include <mach/mmc.h>
36#include <mach/gpmi.h>
37
38#include "stmp378x.h"
39
40static struct platform_device *devices[] = {
41 &stmp3xxx_dbguart,
42 &stmp3xxx_appuart,
43 &stmp3xxx_watchdog,
44 &stmp3xxx_touchscreen,
45 &stmp3xxx_rtc,
46 &stmp3xxx_keyboard,
47 &stmp3xxx_framebuffer,
48 &stmp3xxx_backlight,
49 &stmp3xxx_rotdec,
50 &stmp3xxx_persistent,
51 &stmp3xxx_dcp_bootstream,
52 &stmp3xxx_dcp,
53 &stmp3xxx_battery,
54 &stmp378x_pxp,
55 &stmp378x_i2c,
56};
57
58static struct pin_desc i2c_pins_desc[] = {
59 { PINID_I2C_SCL, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
60 { PINID_I2C_SDA, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
61};
62
63static struct pin_group i2c_pins = {
64 .pins = i2c_pins_desc,
65 .nr_pins = ARRAY_SIZE(i2c_pins_desc),
66};
67
68static struct pin_desc dbguart_pins_0[] = {
69 { PINID_PWM0, PIN_FUN3, },
70 { PINID_PWM1, PIN_FUN3, },
71};
72
73static struct pin_group dbguart_pins[] = {
74 [0] = {
75 .pins = dbguart_pins_0,
76 .nr_pins = ARRAY_SIZE(dbguart_pins_0),
77 },
78};
79
80static int dbguart_pins_control(int id, int request)
81{
82 int r = 0;
83
84 if (request)
85 r = stmp3xxx_request_pin_group(&dbguart_pins[id], "debug uart");
86 else
87 stmp3xxx_release_pin_group(&dbguart_pins[id], "debug uart");
88 return r;
89}
90
91static struct pin_desc appuart_pins_0[] = {
92 { PINID_AUART1_CTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
93 { PINID_AUART1_RTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
94 { PINID_AUART1_RX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
95 { PINID_AUART1_TX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
96};
97
98static struct pin_desc appuart_pins_1[] = {
99#if 0 /* enable these when second appuart will be connected */
100 { PINID_AUART2_CTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
101 { PINID_AUART2_RTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
102 { PINID_AUART2_RX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
103 { PINID_AUART2_TX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
104#endif
105};
106
107static struct pin_desc mmc_pins_desc[] = {
108 { PINID_SSP1_DATA0, PIN_FUN1, PIN_8MA, PIN_3_3V, 1 },
109 { PINID_SSP1_DATA1, PIN_FUN1, PIN_8MA, PIN_3_3V, 1 },
110 { PINID_SSP1_DATA2, PIN_FUN1, PIN_8MA, PIN_3_3V, 1 },
111 { PINID_SSP1_DATA3, PIN_FUN1, PIN_8MA, PIN_3_3V, 1 },
112 { PINID_SSP1_CMD, PIN_FUN1, PIN_8MA, PIN_3_3V, 1 },
113 { PINID_SSP1_SCK, PIN_FUN1, PIN_8MA, PIN_3_3V, 0 },
114 { PINID_SSP1_DETECT, PIN_FUN1, PIN_8MA, PIN_3_3V, 0 },
115};
116
117static struct pin_group mmc_pins = {
118 .pins = mmc_pins_desc,
119 .nr_pins = ARRAY_SIZE(mmc_pins_desc),
120};
121
122static int stmp3xxxmmc_get_wp(void)
123{
124 return gpio_get_value(PINID_PWM4);
125}
126
127static int stmp3xxxmmc_hw_init_ssp1(void)
128{
129 int ret;
130
131 ret = stmp3xxx_request_pin_group(&mmc_pins, "mmc");
132 if (ret)
133 goto out;
134
135 /* Configure write protect GPIO pin */
136 ret = gpio_request(PINID_PWM4, "mmc wp");
137 if (ret)
138 goto out_wp;
139
140 gpio_direction_input(PINID_PWM4);
141
142 /* Configure POWER pin as gpio to drive power to MMC slot */
143 ret = gpio_request(PINID_PWM3, "mmc power");
144 if (ret)
145 goto out_power;
146
147 gpio_direction_output(PINID_PWM3, 0);
148 mdelay(100);
149
150 return 0;
151
152out_power:
153 gpio_free(PINID_PWM4);
154out_wp:
155 stmp3xxx_release_pin_group(&mmc_pins, "mmc");
156out:
157 return ret;
158}
159
160static void stmp3xxxmmc_hw_release_ssp1(void)
161{
162 gpio_free(PINID_PWM3);
163 gpio_free(PINID_PWM4);
164 stmp3xxx_release_pin_group(&mmc_pins, "mmc");
165}
166
167static void stmp3xxxmmc_cmd_pullup_ssp1(int enable)
168{
169 stmp3xxx_pin_pullup(PINID_SSP1_CMD, enable, "mmc");
170}
171
172static unsigned long
173stmp3xxxmmc_setclock_ssp1(void __iomem *base, unsigned long hz)
174{
175 struct clk *ssp, *parent;
176 char *p;
177 long r;
178
179 ssp = clk_get(NULL, "ssp");
180
181 /* using SSP1, no timeout, clock rate 1 */
182 writel(BF(2, SSP_TIMING_CLOCK_DIVIDE) |
183 BF(0xFFFF, SSP_TIMING_TIMEOUT),
184 base + HW_SSP_TIMING);
185
186 p = (hz > 1000000) ? "io" : "osc_24M";
187 parent = clk_get(NULL, p);
188 clk_set_parent(ssp, parent);
189 r = clk_set_rate(ssp, 2 * hz / 1000);
190 clk_put(parent);
191 clk_put(ssp);
192
193 return hz;
194}
195
196static struct stmp3xxxmmc_platform_data mmc_data = {
197 .hw_init = stmp3xxxmmc_hw_init_ssp1,
198 .hw_release = stmp3xxxmmc_hw_release_ssp1,
199 .get_wp = stmp3xxxmmc_get_wp,
200 .cmd_pullup = stmp3xxxmmc_cmd_pullup_ssp1,
201 .setclock = stmp3xxxmmc_setclock_ssp1,
202};
203
204
205static struct pin_group appuart_pins[] = {
206 [0] = {
207 .pins = appuart_pins_0,
208 .nr_pins = ARRAY_SIZE(appuart_pins_0),
209 },
210 [1] = {
211 .pins = appuart_pins_1,
212 .nr_pins = ARRAY_SIZE(appuart_pins_1),
213 },
214};
215
216static struct pin_desc ssp1_pins_desc[] = {
217 { PINID_SSP1_SCK, PIN_FUN1, PIN_8MA, PIN_3_3V, 0, },
218 { PINID_SSP1_CMD, PIN_FUN1, PIN_4MA, PIN_3_3V, 0, },
219 { PINID_SSP1_DATA0, PIN_FUN1, PIN_4MA, PIN_3_3V, 0, },
220 { PINID_SSP1_DATA3, PIN_FUN1, PIN_4MA, PIN_3_3V, 0, },
221};
222
223static struct pin_desc ssp2_pins_desc[] = {
224 { PINID_GPMI_WRN, PIN_FUN3, PIN_8MA, PIN_3_3V, 0, },
225 { PINID_GPMI_RDY1, PIN_FUN3, PIN_4MA, PIN_3_3V, 0, },
226 { PINID_GPMI_D00, PIN_FUN3, PIN_4MA, PIN_3_3V, 0, },
227 { PINID_GPMI_D03, PIN_FUN3, PIN_4MA, PIN_3_3V, 0, },
228};
229
230static struct pin_group ssp1_pins = {
231 .pins = ssp1_pins_desc,
232 .nr_pins = ARRAY_SIZE(ssp1_pins_desc),
233};
234
235static struct pin_group ssp2_pins = {
236 .pins = ssp1_pins_desc,
237 .nr_pins = ARRAY_SIZE(ssp2_pins_desc),
238};
239
240static struct pin_desc gpmi_pins_desc[] = {
241 { PINID_GPMI_CE0N, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
242 { PINID_GPMI_CE1N, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
243 { PINID_GMPI_CE2N, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
244 { PINID_GPMI_CLE, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
245 { PINID_GPMI_ALE, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
246 { PINID_GPMI_WPN, PIN_FUN1, PIN_12MA, PIN_3_3V, 0 },
247 { PINID_GPMI_RDY1, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
248 { PINID_GPMI_D00, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
249 { PINID_GPMI_D01, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
250 { PINID_GPMI_D02, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
251 { PINID_GPMI_D03, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
252 { PINID_GPMI_D04, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
253 { PINID_GPMI_D05, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
254 { PINID_GPMI_D06, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
255 { PINID_GPMI_D07, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
256 { PINID_GPMI_RDY0, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
257 { PINID_GPMI_RDY2, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
258 { PINID_GPMI_RDY3, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
259 { PINID_GPMI_WRN, PIN_FUN1, PIN_12MA, PIN_3_3V, 0 },
260 { PINID_GPMI_RDN, PIN_FUN1, PIN_12MA, PIN_3_3V, 0 },
261};
262
263static struct pin_group gpmi_pins = {
264 .pins = gpmi_pins_desc,
265 .nr_pins = ARRAY_SIZE(gpmi_pins_desc),
266};
267
268static struct mtd_partition gpmi_partitions[] = {
269 [0] = {
270 .name = "boot",
271 .size = 10 * SZ_1M,
272 .offset = 0,
273 },
274 [1] = {
275 .name = "data",
276 .size = MTDPART_SIZ_FULL,
277 .offset = MTDPART_OFS_APPEND,
278 },
279};
280
281static struct gpmi_platform_data gpmi_data = {
282 .pins = &gpmi_pins,
283 .nr_parts = ARRAY_SIZE(gpmi_partitions),
284 .parts = gpmi_partitions,
285 .part_types = { "cmdline", NULL },
286};
287
288static struct spi_board_info spi_board_info[] __initdata = {
289#if defined(CONFIG_ENC28J60) || defined(CONFIG_ENC28J60_MODULE)
290 {
291 .modalias = "enc28j60",
292 .max_speed_hz = 6 * 1000 * 1000,
293 .bus_num = 1,
294 .chip_select = 0,
295 .platform_data = NULL,
296 },
297#endif
298};
299
300static void __init stmp378x_devb_init(void)
301{
302 stmp3xxx_pinmux_init(NR_REAL_IRQS);
303
304 /* init stmp3xxx platform */
305 stmp3xxx_init();
306
307 stmp3xxx_dbguart.dev.platform_data = dbguart_pins_control;
308 stmp3xxx_appuart.dev.platform_data = appuart_pins;
309 stmp3xxx_mmc.dev.platform_data = &mmc_data;
310 stmp3xxx_gpmi.dev.platform_data = &gpmi_data;
311 stmp3xxx_spi1.dev.platform_data = &ssp1_pins;
312 stmp3xxx_spi2.dev.platform_data = &ssp2_pins;
313 stmp378x_i2c.dev.platform_data = &i2c_pins;
314
315 /* register spi devices */
316 spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
317
318 /* add board's devices */
319 platform_add_devices(devices, ARRAY_SIZE(devices));
320
321 /* add devices selected by command line ssp1= and ssp2= options */
322 stmp3xxx_ssp1_device_register();
323 stmp3xxx_ssp2_device_register();
324}
325
326MACHINE_START(STMP378X, "STMP378X")
327 .boot_params = 0x40000100,
328 .map_io = stmp378x_map_io,
329 .init_irq = stmp378x_init_irq,
330 .timer = &stmp3xxx_timer,
331 .init_machine = stmp378x_devb_init,
332MACHINE_END
diff --git a/arch/arm/mach-stmp37xx/Makefile b/arch/arm/mach-stmp37xx/Makefile
deleted file mode 100644
index 57deffd09fbf..000000000000
--- a/arch/arm/mach-stmp37xx/Makefile
+++ /dev/null
@@ -1,2 +0,0 @@
1obj-$(CONFIG_ARCH_STMP37XX) += stmp37xx.o
2obj-$(CONFIG_MACH_STMP37XX) += stmp37xx_devb.o
diff --git a/arch/arm/mach-stmp37xx/Makefile.boot b/arch/arm/mach-stmp37xx/Makefile.boot
deleted file mode 100644
index 1568ad404d59..000000000000
--- a/arch/arm/mach-stmp37xx/Makefile.boot
+++ /dev/null
@@ -1,3 +0,0 @@
1 zreladdr-y := 0x40008000
2params_phys-y := 0x40000100
3initrd_phys-y := 0x40800000
diff --git a/arch/arm/mach-stmp37xx/include/mach/entry-macro.S b/arch/arm/mach-stmp37xx/include/mach/entry-macro.S
deleted file mode 100644
index fed2787b6c34..000000000000
--- a/arch/arm/mach-stmp37xx/include/mach/entry-macro.S
+++ /dev/null
@@ -1,37 +0,0 @@
1/*
2 * Low-level IRQ helper macros for Freescale STMP37XX
3 *
4 * Embedded Alley Solutions, Inc <source@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18
19 .macro disable_fiq
20 .endm
21
22 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
23
24 mov \base, #0xf0000000 @ vm address of IRQ controller
25 ldr \irqnr, [\base, #0x30] @ HW_ICOLL_STAT
26 cmp \irqnr, #0x3f
27 movne \irqstat, #0 @ Ack this IRQ
28 strne \irqstat, [\base, #0x00]@ HW_ICOLL_VECTOR
29 moveqs \irqnr, #0 @ Zero flag set for no IRQ
30
31 .endm
32
33 .macro get_irqnr_preamble, base, tmp
34 .endm
35
36 .macro arch_ret_to_user, tmp1, tmp2
37 .endm
diff --git a/arch/arm/mach-stmp37xx/include/mach/irqs.h b/arch/arm/mach-stmp37xx/include/mach/irqs.h
deleted file mode 100644
index 98f12938550d..000000000000
--- a/arch/arm/mach-stmp37xx/include/mach/irqs.h
+++ /dev/null
@@ -1,99 +0,0 @@
1/*
2 * Freescale STMP37XX interrupts
3 *
4 * Copyright (C) 2005 Sigmatel Inc
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#ifndef _ASM_ARCH_IRQS_H
19#define _ASM_ARCH_IRQS_H
20
21#define IRQ_DEBUG_UART 0
22#define IRQ_COMMS_RX 1
23#define IRQ_COMMS_TX 1
24#define IRQ_SSP2_ERROR 2
25#define IRQ_VDD5V 3
26#define IRQ_HEADPHONE_SHORT 4
27#define IRQ_DAC_DMA 5
28#define IRQ_DAC_ERROR 6
29#define IRQ_ADC_DMA 7
30#define IRQ_ADC_ERROR 8
31#define IRQ_SPDIF_DMA 9
32#define IRQ_SAIF2_DMA 9
33#define IRQ_SPDIF_ERROR 10
34#define IRQ_SAIF1_IRQ 10
35#define IRQ_SAIF2_IRQ 10
36#define IRQ_USB_CTRL 11
37#define IRQ_USB_WAKEUP 12
38#define IRQ_GPMI_DMA 13
39#define IRQ_SSP1_DMA 14
40#define IRQ_SSP_ERROR 15
41#define IRQ_GPIO0 16
42#define IRQ_GPIO1 17
43#define IRQ_GPIO2 18
44#define IRQ_SAIF1_DMA 19
45#define IRQ_SSP2_DMA 20
46#define IRQ_ECC8_IRQ 21
47#define IRQ_RTC_ALARM 22
48#define IRQ_UARTAPP_TX_DMA 23
49#define IRQ_UARTAPP_INTERNAL 24
50#define IRQ_UARTAPP_RX_DMA 25
51#define IRQ_I2C_DMA 26
52#define IRQ_I2C_ERROR 27
53#define IRQ_TIMER0 28
54#define IRQ_TIMER1 29
55#define IRQ_TIMER2 30
56#define IRQ_TIMER3 31
57#define IRQ_BATT_BRNOUT 32
58#define IRQ_VDDD_BRNOUT 33
59#define IRQ_VDDIO_BRNOUT 34
60#define IRQ_VDD18_BRNOUT 35
61#define IRQ_TOUCH_DETECT 36
62#define IRQ_LRADC_CH0 37
63#define IRQ_LRADC_CH1 38
64#define IRQ_LRADC_CH2 39
65#define IRQ_LRADC_CH3 40
66#define IRQ_LRADC_CH4 41
67#define IRQ_LRADC_CH5 42
68#define IRQ_LRADC_CH6 43
69#define IRQ_LRADC_CH7 44
70#define IRQ_LCDIF_DMA 45
71#define IRQ_LCDIF_ERROR 46
72#define IRQ_DIGCTL_DEBUG_TRAP 47
73#define IRQ_RTC_1MSEC 48
74#define IRQ_DRI_DMA 49
75#define IRQ_DRI_ATTENTION 50
76#define IRQ_GPMI_ATTENTION 51
77#define IRQ_IR 52
78#define IRQ_DCP_VMI 53
79#define IRQ_DCP 54
80#define IRQ_RESERVED_55 55
81#define IRQ_RESERVED_56 56
82#define IRQ_RESERVED_57 57
83#define IRQ_RESERVED_58 58
84#define IRQ_RESERVED_59 59
85#define SW_IRQ_60 60
86#define SW_IRQ_61 61
87#define SW_IRQ_62 62
88#define SW_IRQ_63 63
89
90#define NR_REAL_IRQS 64
91#define NR_IRQS (NR_REAL_IRQS + 32 * 3)
92
93/* TIMER and BRNOUT are FIQ capable */
94#define FIQ_START IRQ_TIMER0
95
96/* Hard disk IRQ is a GPMI attention IRQ */
97#define IRQ_HARDDISK IRQ_GPMI_ATTENTION
98
99#endif /* _ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-stmp37xx/include/mach/pins.h b/arch/arm/mach-stmp37xx/include/mach/pins.h
deleted file mode 100644
index d56de0c471d8..000000000000
--- a/arch/arm/mach-stmp37xx/include/mach/pins.h
+++ /dev/null
@@ -1,147 +0,0 @@
1/*
2 * Freescale STMP37XX SoC pin multiplexing
3 *
4 * Author: Vladislav Buzov <vbuzov@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#ifndef __ASM_ARCH_PINS_H
19#define __ASM_ARCH_PINS_H
20
21/*
22 * Define all STMP37XX pins, a pin name corresponds to a STMP37xx hardware
23 * interface this pin belongs to.
24 */
25
26/* Bank 0 */
27#define PINID_GPMI_D00 STMP3XXX_PINID(0, 0)
28#define PINID_GPMI_D01 STMP3XXX_PINID(0, 1)
29#define PINID_GPMI_D02 STMP3XXX_PINID(0, 2)
30#define PINID_GPMI_D03 STMP3XXX_PINID(0, 3)
31#define PINID_GPMI_D04 STMP3XXX_PINID(0, 4)
32#define PINID_GPMI_D05 STMP3XXX_PINID(0, 5)
33#define PINID_GPMI_D06 STMP3XXX_PINID(0, 6)
34#define PINID_GPMI_D07 STMP3XXX_PINID(0, 7)
35#define PINID_GPMI_D08 STMP3XXX_PINID(0, 8)
36#define PINID_GPMI_D09 STMP3XXX_PINID(0, 9)
37#define PINID_GPMI_D10 STMP3XXX_PINID(0, 10)
38#define PINID_GPMI_D11 STMP3XXX_PINID(0, 11)
39#define PINID_GPMI_D12 STMP3XXX_PINID(0, 12)
40#define PINID_GPMI_D13 STMP3XXX_PINID(0, 13)
41#define PINID_GPMI_D14 STMP3XXX_PINID(0, 14)
42#define PINID_GPMI_D15 STMP3XXX_PINID(0, 15)
43#define PINID_GPMI_A0 STMP3XXX_PINID(0, 16)
44#define PINID_GPMI_A1 STMP3XXX_PINID(0, 17)
45#define PINID_GPMI_A2 STMP3XXX_PINID(0, 18)
46#define PINID_GPMI_RDY0 STMP3XXX_PINID(0, 19)
47#define PINID_GPMI_RDY2 STMP3XXX_PINID(0, 20)
48#define PINID_GPMI_RDY3 STMP3XXX_PINID(0, 21)
49#define PINID_GPMI_RESETN STMP3XXX_PINID(0, 22)
50#define PINID_GPMI_IRQ STMP3XXX_PINID(0, 23)
51#define PINID_GPMI_WRN STMP3XXX_PINID(0, 24)
52#define PINID_GPMI_RDN STMP3XXX_PINID(0, 25)
53#define PINID_UART2_CTS STMP3XXX_PINID(0, 26)
54#define PINID_UART2_RTS STMP3XXX_PINID(0, 27)
55#define PINID_UART2_RX STMP3XXX_PINID(0, 28)
56#define PINID_UART2_TX STMP3XXX_PINID(0, 29)
57
58/* Bank 1 */
59#define PINID_LCD_D00 STMP3XXX_PINID(1, 0)
60#define PINID_LCD_D01 STMP3XXX_PINID(1, 1)
61#define PINID_LCD_D02 STMP3XXX_PINID(1, 2)
62#define PINID_LCD_D03 STMP3XXX_PINID(1, 3)
63#define PINID_LCD_D04 STMP3XXX_PINID(1, 4)
64#define PINID_LCD_D05 STMP3XXX_PINID(1, 5)
65#define PINID_LCD_D06 STMP3XXX_PINID(1, 6)
66#define PINID_LCD_D07 STMP3XXX_PINID(1, 7)
67#define PINID_LCD_D08 STMP3XXX_PINID(1, 8)
68#define PINID_LCD_D09 STMP3XXX_PINID(1, 9)
69#define PINID_LCD_D10 STMP3XXX_PINID(1, 10)
70#define PINID_LCD_D11 STMP3XXX_PINID(1, 11)
71#define PINID_LCD_D12 STMP3XXX_PINID(1, 12)
72#define PINID_LCD_D13 STMP3XXX_PINID(1, 13)
73#define PINID_LCD_D14 STMP3XXX_PINID(1, 14)
74#define PINID_LCD_D15 STMP3XXX_PINID(1, 15)
75#define PINID_LCD_RESET STMP3XXX_PINID(1, 16)
76#define PINID_LCD_RS STMP3XXX_PINID(1, 17)
77#define PINID_LCD_WR_RWN STMP3XXX_PINID(1, 18)
78#define PINID_LCD_RD_E STMP3XXX_PINID(1, 19)
79#define PINID_LCD_CS STMP3XXX_PINID(1, 20)
80#define PINID_LCD_BUSY STMP3XXX_PINID(1, 21)
81#define PINID_SSP1_CMD STMP3XXX_PINID(1, 22)
82#define PINID_SSP1_SCK STMP3XXX_PINID(1, 23)
83#define PINID_SSP1_DATA0 STMP3XXX_PINID(1, 24)
84#define PINID_SSP1_DATA1 STMP3XXX_PINID(1, 25)
85#define PINID_SSP1_DATA2 STMP3XXX_PINID(1, 26)
86#define PINID_SSP1_DATA3 STMP3XXX_PINID(1, 27)
87#define PINID_SSP1_DETECT STMP3XXX_PINID(1, 28)
88
89/* Bank 2 */
90#define PINID_PWM0 STMP3XXX_PINID(2, 0)
91#define PINID_PWM1 STMP3XXX_PINID(2, 1)
92#define PINID_PWM2 STMP3XXX_PINID(2, 2)
93#define PINID_PWM3 STMP3XXX_PINID(2, 3)
94#define PINID_PWM4 STMP3XXX_PINID(2, 4)
95#define PINID_I2C_SCL STMP3XXX_PINID(2, 5)
96#define PINID_I2C_SDA STMP3XXX_PINID(2, 6)
97#define PINID_ROTTARYA STMP3XXX_PINID(2, 7)
98#define PINID_ROTTARYB STMP3XXX_PINID(2, 8)
99#define PINID_EMI_CKE STMP3XXX_PINID(2, 9)
100#define PINID_EMI_RASN STMP3XXX_PINID(2, 10)
101#define PINID_EMI_CASN STMP3XXX_PINID(2, 11)
102#define PINID_EMI_CE0N STMP3XXX_PINID(2, 12)
103#define PINID_EMI_CE1N STMP3XXX_PINID(2, 13)
104#define PINID_EMI_CE2N STMP3XXX_PINID(2, 14)
105#define PINID_EMI_CE3N STMP3XXX_PINID(2, 15)
106#define PINID_EMI_A00 STMP3XXX_PINID(2, 16)
107#define PINID_EMI_A01 STMP3XXX_PINID(2, 17)
108#define PINID_EMI_A02 STMP3XXX_PINID(2, 18)
109#define PINID_EMI_A03 STMP3XXX_PINID(2, 19)
110#define PINID_EMI_A04 STMP3XXX_PINID(2, 20)
111#define PINID_EMI_A05 STMP3XXX_PINID(2, 21)
112#define PINID_EMI_A06 STMP3XXX_PINID(2, 22)
113#define PINID_EMI_A07 STMP3XXX_PINID(2, 23)
114#define PINID_EMI_A08 STMP3XXX_PINID(2, 24)
115#define PINID_EMI_A09 STMP3XXX_PINID(2, 25)
116#define PINID_EMI_A10 STMP3XXX_PINID(2, 26)
117#define PINID_EMI_A11 STMP3XXX_PINID(2, 27)
118#define PINID_EMI_A12 STMP3XXX_PINID(2, 28)
119#define PINID_EMI_A13 STMP3XXX_PINID(2, 29)
120#define PINID_EMI_A14 STMP3XXX_PINID(2, 30)
121#define PINID_EMI_WEN STMP3XXX_PINID(2, 31)
122
123/* Bank 3 */
124#define PINID_EMI_D00 STMP3XXX_PINID(3, 0)
125#define PINID_EMI_D01 STMP3XXX_PINID(3, 1)
126#define PINID_EMI_D02 STMP3XXX_PINID(3, 2)
127#define PINID_EMI_D03 STMP3XXX_PINID(3, 3)
128#define PINID_EMI_D04 STMP3XXX_PINID(3, 4)
129#define PINID_EMI_D05 STMP3XXX_PINID(3, 5)
130#define PINID_EMI_D06 STMP3XXX_PINID(3, 6)
131#define PINID_EMI_D07 STMP3XXX_PINID(3, 7)
132#define PINID_EMI_D08 STMP3XXX_PINID(3, 8)
133#define PINID_EMI_D09 STMP3XXX_PINID(3, 9)
134#define PINID_EMI_D10 STMP3XXX_PINID(3, 10)
135#define PINID_EMI_D11 STMP3XXX_PINID(3, 11)
136#define PINID_EMI_D12 STMP3XXX_PINID(3, 12)
137#define PINID_EMI_D13 STMP3XXX_PINID(3, 13)
138#define PINID_EMI_D14 STMP3XXX_PINID(3, 14)
139#define PINID_EMI_D15 STMP3XXX_PINID(3, 15)
140#define PINID_EMI_DQS0 STMP3XXX_PINID(3, 16)
141#define PINID_EMI_DQS1 STMP3XXX_PINID(3, 17)
142#define PINID_EMI_DQM0 STMP3XXX_PINID(3, 18)
143#define PINID_EMI_DQM1 STMP3XXX_PINID(3, 19)
144#define PINID_EMI_CLK STMP3XXX_PINID(3, 20)
145#define PINID_EMI_CLKN STMP3XXX_PINID(3, 21)
146
147#endif /* __ASM_ARCH_PINS_H */
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-apbh.h b/arch/arm/mach-stmp37xx/include/mach/regs-apbh.h
deleted file mode 100644
index a323aa9a21f2..000000000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-apbh.h
+++ /dev/null
@@ -1,97 +0,0 @@
1/*
2 * stmp37xx: APBH register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef _MACH_REGS_APBH
22#define _MACH_REGS_APBH
23
24#define REGS_APBH_BASE (STMP3XXX_REGS_BASE + 0x4000)
25
26#define HW_APBH_CTRL0 0x0
27#define BM_APBH_CTRL0_RESET_CHANNEL 0x00FF0000
28#define BP_APBH_CTRL0_RESET_CHANNEL 16
29#define BM_APBH_CTRL0_CLKGATE 0x40000000
30#define BM_APBH_CTRL0_SFTRST 0x80000000
31
32#define HW_APBH_CTRL1 0x10
33#define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0x00000001
34#define BP_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0
35
36#define HW_APBH_DEVSEL 0x20
37
38#define HW_APBH_CH0_NXTCMDAR (0x50 + 0 * 0x70)
39#define HW_APBH_CH1_NXTCMDAR (0x50 + 1 * 0x70)
40#define HW_APBH_CH2_NXTCMDAR (0x50 + 2 * 0x70)
41#define HW_APBH_CH3_NXTCMDAR (0x50 + 3 * 0x70)
42#define HW_APBH_CH4_NXTCMDAR (0x50 + 4 * 0x70)
43#define HW_APBH_CH5_NXTCMDAR (0x50 + 5 * 0x70)
44#define HW_APBH_CH6_NXTCMDAR (0x50 + 6 * 0x70)
45#define HW_APBH_CH7_NXTCMDAR (0x50 + 7 * 0x70)
46#define HW_APBH_CH8_NXTCMDAR (0x50 + 8 * 0x70)
47#define HW_APBH_CH9_NXTCMDAR (0x50 + 9 * 0x70)
48#define HW_APBH_CH10_NXTCMDAR (0x50 + 10 * 0x70)
49#define HW_APBH_CH11_NXTCMDAR (0x50 + 11 * 0x70)
50#define HW_APBH_CH12_NXTCMDAR (0x50 + 12 * 0x70)
51#define HW_APBH_CH13_NXTCMDAR (0x50 + 13 * 0x70)
52#define HW_APBH_CH14_NXTCMDAR (0x50 + 14 * 0x70)
53#define HW_APBH_CH15_NXTCMDAR (0x50 + 15 * 0x70)
54
55#define HW_APBH_CHn_NXTCMDAR 0x50
56
57#define BM_APBH_CHn_CMD_MODE 0x00000003
58#define BP_APBH_CHn_CMD_MODE 0x00000001
59#define BV_APBH_CHn_CMD_MODE_NOOP 0
60#define BV_APBH_CHn_CMD_MODE_WRITE 1
61#define BV_APBH_CHn_CMD_MODE_READ 2
62#define BV_APBH_CHn_CMD_MODE_SENSE 3
63#define BM_APBH_CHn_CMD_CHAIN 0x00000004
64#define BM_APBH_CHn_CMD_IRQONCMPLT 0x00000008
65#define BM_APBH_CHn_CMD_NANDLOCK 0x00000010
66#define BM_APBH_CHn_CMD_NANDWAIT4READY 0x00000020
67#define BM_APBH_CHn_CMD_SEMAPHORE 0x00000040
68#define BM_APBH_CHn_CMD_WAIT4ENDCMD 0x00000080
69#define BM_APBH_CHn_CMD_CMDWORDS 0x0000F000
70#define BP_APBH_CHn_CMD_CMDWORDS 12
71#define BM_APBH_CHn_CMD_XFER_COUNT 0xFFFF0000
72#define BP_APBH_CHn_CMD_XFER_COUNT 16
73
74#define HW_APBH_CH0_SEMA (0x80 + 0 * 0x70)
75#define HW_APBH_CH1_SEMA (0x80 + 1 * 0x70)
76#define HW_APBH_CH2_SEMA (0x80 + 2 * 0x70)
77#define HW_APBH_CH3_SEMA (0x80 + 3 * 0x70)
78#define HW_APBH_CH4_SEMA (0x80 + 4 * 0x70)
79#define HW_APBH_CH5_SEMA (0x80 + 5 * 0x70)
80#define HW_APBH_CH6_SEMA (0x80 + 6 * 0x70)
81#define HW_APBH_CH7_SEMA (0x80 + 7 * 0x70)
82#define HW_APBH_CH8_SEMA (0x80 + 8 * 0x70)
83#define HW_APBH_CH9_SEMA (0x80 + 9 * 0x70)
84#define HW_APBH_CH10_SEMA (0x80 + 10 * 0x70)
85#define HW_APBH_CH11_SEMA (0x80 + 11 * 0x70)
86#define HW_APBH_CH12_SEMA (0x80 + 12 * 0x70)
87#define HW_APBH_CH13_SEMA (0x80 + 13 * 0x70)
88#define HW_APBH_CH14_SEMA (0x80 + 14 * 0x70)
89#define HW_APBH_CH15_SEMA (0x80 + 15 * 0x70)
90
91#define HW_APBH_CHn_SEMA 0x80
92#define BM_APBH_CHn_SEMA_INCREMENT_SEMA 0x000000FF
93#define BP_APBH_CHn_SEMA_INCREMENT_SEMA 0
94#define BM_APBH_CHn_SEMA_PHORE 0x00FF0000
95#define BP_APBH_CHn_SEMA_PHORE 16
96
97#endif
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-apbx.h b/arch/arm/mach-stmp37xx/include/mach/regs-apbx.h
deleted file mode 100644
index 6d080cd5b702..000000000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-apbx.h
+++ /dev/null
@@ -1,113 +0,0 @@
1/*
2 * stmp37xx: APBX register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef _MACH_REGS_APBX
22#define _MACH_REGS_APBX
23
24#define REGS_APBX_BASE (STMP3XXX_REGS_BASE + 0x24000)
25
26#define HW_APBX_CTRL0 0x0
27#define BM_APBX_CTRL0_RESET_CHANNEL 0x00FF0000
28#define BP_APBX_CTRL0_RESET_CHANNEL 16
29#define BM_APBX_CTRL0_CLKGATE 0x40000000
30#define BM_APBX_CTRL0_SFTRST 0x80000000
31
32#define HW_APBX_CTRL1 0x10
33
34#define HW_APBX_DEVSEL 0x20
35
36#define HW_APBX_CH0_NXTCMDAR (0x50 + 0 * 0x70)
37#define HW_APBX_CH1_NXTCMDAR (0x50 + 1 * 0x70)
38#define HW_APBX_CH2_NXTCMDAR (0x50 + 2 * 0x70)
39#define HW_APBX_CH3_NXTCMDAR (0x50 + 3 * 0x70)
40#define HW_APBX_CH4_NXTCMDAR (0x50 + 4 * 0x70)
41#define HW_APBX_CH5_NXTCMDAR (0x50 + 5 * 0x70)
42#define HW_APBX_CH6_NXTCMDAR (0x50 + 6 * 0x70)
43#define HW_APBX_CH7_NXTCMDAR (0x50 + 7 * 0x70)
44#define HW_APBX_CH8_NXTCMDAR (0x50 + 8 * 0x70)
45#define HW_APBX_CH9_NXTCMDAR (0x50 + 9 * 0x70)
46#define HW_APBX_CH10_NXTCMDAR (0x50 + 10 * 0x70)
47#define HW_APBX_CH11_NXTCMDAR (0x50 + 11 * 0x70)
48#define HW_APBX_CH12_NXTCMDAR (0x50 + 12 * 0x70)
49#define HW_APBX_CH13_NXTCMDAR (0x50 + 13 * 0x70)
50#define HW_APBX_CH14_NXTCMDAR (0x50 + 14 * 0x70)
51#define HW_APBX_CH15_NXTCMDAR (0x50 + 15 * 0x70)
52
53#define HW_APBX_CHn_NXTCMDAR 0x50
54#define BM_APBX_CHn_CMD_MODE 0x00000003
55#define BP_APBX_CHn_CMD_MODE 0x00000001
56#define BV_APBX_CHn_CMD_MODE_NOOP 0
57#define BV_APBX_CHn_CMD_MODE_WRITE 1
58#define BV_APBX_CHn_CMD_MODE_READ 2
59#define BV_APBX_CHn_CMD_MODE_SENSE 3
60#define BM_APBX_CHn_CMD_COMMAND 0x00000003
61#define BP_APBX_CHn_CMD_COMMAND 0
62#define BM_APBX_CHn_CMD_CHAIN 0x00000004
63#define BM_APBX_CHn_CMD_IRQONCMPLT 0x00000008
64#define BM_APBX_CHn_CMD_SEMAPHORE 0x00000040
65#define BM_APBX_CHn_CMD_WAIT4ENDCMD 0x00000080
66#define BM_APBX_CHn_CMD_CMDWORDS 0x0000F000
67#define BP_APBX_CHn_CMD_CMDWORDS 12
68#define BM_APBX_CHn_CMD_XFER_COUNT 0xFFFF0000
69#define BP_APBX_CHn_CMD_XFER_COUNT 16
70
71#define HW_APBX_CH0_BAR (0x70 + 0 * 0x70)
72#define HW_APBX_CH1_BAR (0x70 + 1 * 0x70)
73#define HW_APBX_CH2_BAR (0x70 + 2 * 0x70)
74#define HW_APBX_CH3_BAR (0x70 + 3 * 0x70)
75#define HW_APBX_CH4_BAR (0x70 + 4 * 0x70)
76#define HW_APBX_CH5_BAR (0x70 + 5 * 0x70)
77#define HW_APBX_CH6_BAR (0x70 + 6 * 0x70)
78#define HW_APBX_CH7_BAR (0x70 + 7 * 0x70)
79#define HW_APBX_CH8_BAR (0x70 + 8 * 0x70)
80#define HW_APBX_CH9_BAR (0x70 + 9 * 0x70)
81#define HW_APBX_CH10_BAR (0x70 + 10 * 0x70)
82#define HW_APBX_CH11_BAR (0x70 + 11 * 0x70)
83#define HW_APBX_CH12_BAR (0x70 + 12 * 0x70)
84#define HW_APBX_CH13_BAR (0x70 + 13 * 0x70)
85#define HW_APBX_CH14_BAR (0x70 + 14 * 0x70)
86#define HW_APBX_CH15_BAR (0x70 + 15 * 0x70)
87
88#define HW_APBX_CHn_BAR 0x70
89
90#define HW_APBX_CH0_SEMA (0x80 + 0 * 0x70)
91#define HW_APBX_CH1_SEMA (0x80 + 1 * 0x70)
92#define HW_APBX_CH2_SEMA (0x80 + 2 * 0x70)
93#define HW_APBX_CH3_SEMA (0x80 + 3 * 0x70)
94#define HW_APBX_CH4_SEMA (0x80 + 4 * 0x70)
95#define HW_APBX_CH5_SEMA (0x80 + 5 * 0x70)
96#define HW_APBX_CH6_SEMA (0x80 + 6 * 0x70)
97#define HW_APBX_CH7_SEMA (0x80 + 7 * 0x70)
98#define HW_APBX_CH8_SEMA (0x80 + 8 * 0x70)
99#define HW_APBX_CH9_SEMA (0x80 + 9 * 0x70)
100#define HW_APBX_CH10_SEMA (0x80 + 10 * 0x70)
101#define HW_APBX_CH11_SEMA (0x80 + 11 * 0x70)
102#define HW_APBX_CH12_SEMA (0x80 + 12 * 0x70)
103#define HW_APBX_CH13_SEMA (0x80 + 13 * 0x70)
104#define HW_APBX_CH14_SEMA (0x80 + 14 * 0x70)
105#define HW_APBX_CH15_SEMA (0x80 + 15 * 0x70)
106
107#define HW_APBX_CHn_SEMA 0x80
108#define BM_APBX_CHn_SEMA_INCREMENT_SEMA 0x000000FF
109#define BP_APBX_CHn_SEMA_INCREMENT_SEMA 0
110#define BM_APBX_CHn_SEMA_PHORE 0x00FF0000
111#define BP_APBX_CHn_SEMA_PHORE 16
112
113#endif
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-audioin.h b/arch/arm/mach-stmp37xx/include/mach/regs-audioin.h
deleted file mode 100644
index 3b511f947a53..000000000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-audioin.h
+++ /dev/null
@@ -1,61 +0,0 @@
1/*
2 * stmp37xx: AUDIOIN register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_AUDIOIN_BASE (STMP3XXX_REGS_BASE + 0x4C000)
22
23#define HW_AUDIOIN_CTRL 0x0
24#define BM_AUDIOIN_CTRL_RUN 0x00000001
25#define BP_AUDIOIN_CTRL_RUN 0
26#define BM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN 0x00000002
27#define BM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ 0x00000004
28#define BM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008
29#define BM_AUDIOIN_CTRL_WORD_LENGTH 0x00000020
30#define BM_AUDIOIN_CTRL_CLKGATE 0x40000000
31#define BM_AUDIOIN_CTRL_SFTRST 0x80000000
32
33#define HW_AUDIOIN_STAT 0x10
34
35#define HW_AUDIOIN_ADCSRR 0x20
36
37#define HW_AUDIOIN_ADCVOLUME 0x30
38#define BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0x000000FF
39#define BP_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0
40#define BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT 0x00FF0000
41#define BP_AUDIOIN_ADCVOLUME_VOLUME_LEFT 16
42
43#define HW_AUDIOIN_ADCDEBUG 0x40
44
45#define HW_AUDIOIN_ADCVOL 0x50
46#define BM_AUDIOIN_ADCVOL_GAIN_RIGHT 0x0000000F
47#define BP_AUDIOIN_ADCVOL_GAIN_RIGHT 0
48#define BM_AUDIOIN_ADCVOL_SELECT_RIGHT 0x00000030
49#define BP_AUDIOIN_ADCVOL_SELECT_RIGHT 4
50#define BM_AUDIOIN_ADCVOL_GAIN_LEFT 0x00000F00
51#define BP_AUDIOIN_ADCVOL_GAIN_LEFT 8
52#define BM_AUDIOIN_ADCVOL_SELECT_LEFT 0x00003000
53#define BP_AUDIOIN_ADCVOL_SELECT_LEFT 12
54#define BM_AUDIOIN_ADCVOL_MUTE 0x01000000
55
56#define HW_AUDIOIN_MICLINE 0x60
57
58#define HW_AUDIOIN_ANACLKCTRL 0x70
59#define BM_AUDIOIN_ANACLKCTRL_CLKGATE 0x80000000
60
61#define HW_AUDIOIN_DATA 0x80
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-audioout.h b/arch/arm/mach-stmp37xx/include/mach/regs-audioout.h
deleted file mode 100644
index ca1942b8a3e9..000000000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-audioout.h
+++ /dev/null
@@ -1,111 +0,0 @@
1/*
2 * stmp37xx: AUDIOOUT register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_AUDIOOUT_BASE (STMP3XXX_REGS_BASE + 0x48000)
22
23#define HW_AUDIOOUT_CTRL 0x0
24#define BM_AUDIOOUT_CTRL_RUN 0x00000001
25#define BP_AUDIOOUT_CTRL_RUN 0
26#define BM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN 0x00000002
27#define BM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ 0x00000004
28#define BM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008
29#define BM_AUDIOOUT_CTRL_WORD_LENGTH 0x00000040
30#define BM_AUDIOOUT_CTRL_CLKGATE 0x40000000
31#define BM_AUDIOOUT_CTRL_SFTRST 0x80000000
32
33#define HW_AUDIOOUT_STAT 0x10
34
35#define HW_AUDIOOUT_DACSRR 0x20
36#define BM_AUDIOOUT_DACSRR_SRC_FRAC 0x00001FFF
37#define BP_AUDIOOUT_DACSRR_SRC_FRAC 0
38#define BM_AUDIOOUT_DACSRR_SRC_INT 0x001F0000
39#define BP_AUDIOOUT_DACSRR_SRC_INT 16
40#define BM_AUDIOOUT_DACSRR_SRC_HOLD 0x07000000
41#define BP_AUDIOOUT_DACSRR_SRC_HOLD 24
42#define BM_AUDIOOUT_DACSRR_BASEMULT 0x70000000
43#define BP_AUDIOOUT_DACSRR_BASEMULT 28
44
45#define HW_AUDIOOUT_DACVOLUME 0x30
46#define BM_AUDIOOUT_DACVOLUME_MUTE_RIGHT 0x00000100
47#define BM_AUDIOOUT_DACVOLUME_MUTE_LEFT 0x01000000
48#define BM_AUDIOOUT_DACVOLUME_EN_ZCD 0x02000000
49
50#define HW_AUDIOOUT_DACDEBUG 0x40
51
52#define HW_AUDIOOUT_HPVOL 0x50
53#define BM_AUDIOOUT_HPVOL_MUTE 0x01000000
54#define BM_AUDIOOUT_HPVOL_EN_MSTR_ZCD 0x02000000
55
56#define HW_AUDIOOUT_PWRDN 0x70
57#define BM_AUDIOOUT_PWRDN_HEADPHONE 0x00000001
58#define BP_AUDIOOUT_PWRDN_HEADPHONE 0
59#define BM_AUDIOOUT_PWRDN_CAPLESS 0x00000010
60#define BM_AUDIOOUT_PWRDN_ADC 0x00000100
61#define BM_AUDIOOUT_PWRDN_DAC 0x00001000
62#define BM_AUDIOOUT_PWRDN_RIGHT_ADC 0x00010000
63#define BM_AUDIOOUT_PWRDN_LINEOUT 0x01000000
64
65#define HW_AUDIOOUT_REFCTRL 0x80
66#define BM_AUDIOOUT_REFCTRL_VAG_VAL 0x000000F0
67#define BP_AUDIOOUT_REFCTRL_VAG_VAL 4
68#define BM_AUDIOOUT_REFCTRL_ADC_REFVAL 0x00000F00
69#define BP_AUDIOOUT_REFCTRL_ADC_REFVAL 8
70#define BM_AUDIOOUT_REFCTRL_ADJ_VAG 0x00001000
71#define BM_AUDIOOUT_REFCTRL_ADJ_ADC 0x00002000
72#define BM_AUDIOOUT_REFCTRL_BIAS_CTRL 0x00030000
73#define BP_AUDIOOUT_REFCTRL_BIAS_CTRL 16
74#define BM_AUDIOOUT_REFCTRL_LOW_PWR 0x00080000
75#define BM_AUDIOOUT_REFCTRL_VBG_ADJ 0x00700000
76#define BP_AUDIOOUT_REFCTRL_VBG_ADJ 20
77#define BM_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS 0x01000000
78#define BM_AUDIOOUT_REFCTRL_RAISE_REF 0x02000000
79
80#define HW_AUDIOOUT_ANACTRL 0x90
81#define BM_AUDIOOUT_ANACTRL_HP_CLASSAB 0x00000010
82#define BM_AUDIOOUT_ANACTRL_HP_HOLD_GND 0x00000020
83
84#define HW_AUDIOOUT_TEST 0xA0
85#define BM_AUDIOOUT_TEST_HP_I1_ADJ 0x00C00000
86#define BP_AUDIOOUT_TEST_HP_I1_ADJ 22
87
88#define HW_AUDIOOUT_BISTCTRL 0xB0
89
90#define HW_AUDIOOUT_BISTSTAT0 0xC0
91
92#define HW_AUDIOOUT_BISTSTAT1 0xD0
93
94#define HW_AUDIOOUT_ANACLKCTRL 0xE0
95#define BM_AUDIOOUT_ANACLKCTRL_CLKGATE 0x80000000
96
97#define HW_AUDIOOUT_DATA 0xF0
98
99#define HW_AUDIOOUT_LINEOUTCTRL 0x100
100#define BM_AUDIOOUT_LINEOUTCTRL_VOL_RIGHT 0x0000001F
101#define BP_AUDIOOUT_LINEOUTCTRL_VOL_RIGHT 0
102#define BM_AUDIOOUT_LINEOUTCTRL_VOL_LEFT 0x00001F00
103#define BP_AUDIOOUT_LINEOUTCTRL_VOL_LEFT 8
104#define BM_AUDIOOUT_LINEOUTCTRL_CHARGE_CAP 0x00007000
105#define BP_AUDIOOUT_LINEOUTCTRL_CHARGE_CAP 12
106#define BM_AUDIOOUT_LINEOUTCTRL_VAG_CTRL 0x00F00000
107#define BP_AUDIOOUT_LINEOUTCTRL_VAG_CTRL 20
108#define BM_AUDIOOUT_LINEOUTCTRL_MUTE 0x01000000
109#define BM_AUDIOOUT_LINEOUTCTRL_EN_ZCD 0x02000000
110
111#define HW_AUDIOOUT_VERSION 0x200
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-clkctrl.h b/arch/arm/mach-stmp37xx/include/mach/regs-clkctrl.h
deleted file mode 100644
index 47f5c92fdaf6..000000000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-clkctrl.h
+++ /dev/null
@@ -1,72 +0,0 @@
1/*
2 * stmp37xx: CLKCTRL register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef _MACH_REGS_CLKCTRL
22#define _MACH_REGS_CLKCTRL
23
24#define REGS_CLKCTRL_BASE (STMP3XXX_REGS_BASE + 0x40000)
25
26#define HW_CLKCTRL_PLLCTRL0 0x0
27#define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x00040000
28
29#define HW_CLKCTRL_CPU 0x20
30#define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F
31#define BP_CLKCTRL_CPU_DIV_CPU 0
32
33#define HW_CLKCTRL_HBUS 0x30
34#define BM_CLKCTRL_HBUS_DIV 0x0000001F
35#define BP_CLKCTRL_HBUS_DIV 0
36
37#define HW_CLKCTRL_XBUS 0x40
38
39#define HW_CLKCTRL_XTAL 0x50
40
41#define HW_CLKCTRL_PIX 0x60
42#define BM_CLKCTRL_PIX_DIV 0x00007FFF
43#define BP_CLKCTRL_PIX_DIV 0
44#define BM_CLKCTRL_PIX_CLKGATE 0x80000000
45
46#define HW_CLKCTRL_SSP 0x70
47
48#define HW_CLKCTRL_GPMI 0x80
49
50#define HW_CLKCTRL_SPDIF 0x90
51
52#define HW_CLKCTRL_EMI 0xA0
53
54#define HW_CLKCTRL_IR 0xB0
55
56#define HW_CLKCTRL_SAIF 0xC0
57
58#define HW_CLKCTRL_FRAC 0xD0
59#define BM_CLKCTRL_FRAC_EMIFRAC 0x00003F00
60#define BP_CLKCTRL_FRAC_EMIFRAC 8
61#define BM_CLKCTRL_FRAC_PIXFRAC 0x003F0000
62#define BP_CLKCTRL_FRAC_PIXFRAC 16
63#define BM_CLKCTRL_FRAC_CLKGATEPIX 0x00800000
64
65#define HW_CLKCTRL_CLKSEQ 0xE0
66#define BM_CLKCTRL_CLKSEQ_BYPASS_PIX 0x00000002
67
68#define HW_CLKCTRL_RESET 0xF0
69#define BM_CLKCTRL_RESET_DIG 0x00000001
70#define BP_CLKCTRL_RESET_DIG 0
71
72#endif
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-digctl.h b/arch/arm/mach-stmp37xx/include/mach/regs-digctl.h
deleted file mode 100644
index ba1bbe265c20..000000000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-digctl.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * stmp37xx: DIGCTL register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_DIGCTL_BASE (STMP3XXX_REGS_BASE + 0x1C000)
22
23#define HW_DIGCTL_CTRL 0x0
24#define BM_DIGCTL_CTRL_USB_CLKGATE 0x00000004
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-ecc8.h b/arch/arm/mach-stmp37xx/include/mach/regs-ecc8.h
deleted file mode 100644
index 3b6d990a3af5..000000000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-ecc8.h
+++ /dev/null
@@ -1,37 +0,0 @@
1/*
2 * stmp37xx: ECC8 register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_ECC8_BASE (STMP3XXX_REGS_BASE + 0x8000)
22
23#define HW_ECC8_CTRL 0x0
24#define BM_ECC8_CTRL_COMPLETE_IRQ 0x00000001
25#define BP_ECC8_CTRL_COMPLETE_IRQ 0
26#define BM_ECC8_CTRL_COMPLETE_IRQ_EN 0x00000100
27#define BM_ECC8_CTRL_AHBM_SFTRST 0x20000000
28
29#define HW_ECC8_STATUS0 0x10
30#define BM_ECC8_STATUS0_UNCORRECTABLE 0x00000004
31#define BM_ECC8_STATUS0_CORRECTED 0x00000008
32#define BM_ECC8_STATUS0_STATUS_AUX 0x00000F00
33#define BP_ECC8_STATUS0_STATUS_AUX 8
34#define BM_ECC8_STATUS0_COMPLETED_CE 0x000F0000
35#define BP_ECC8_STATUS0_COMPLETED_CE 16
36
37#define HW_ECC8_STATUS1 0x20
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-gpmi.h b/arch/arm/mach-stmp37xx/include/mach/regs-gpmi.h
deleted file mode 100644
index f2b304f54490..000000000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-gpmi.h
+++ /dev/null
@@ -1,63 +0,0 @@
1/*
2 * stmp37xx: GPMI register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_GPMI_BASE (STMP3XXX_REGS_BASE + 0xC000)
22#define REGS_GPMI_PHYS 0x8000C000
23#define REGS_GPMI_SIZE 0x2000
24
25#define HW_GPMI_CTRL0 0x0
26#define BM_GPMI_CTRL0_XFER_COUNT 0x0000FFFF
27#define BP_GPMI_CTRL0_XFER_COUNT 0
28#define BM_GPMI_CTRL0_CS 0x00300000
29#define BP_GPMI_CTRL0_CS 20
30#define BM_GPMI_CTRL0_LOCK_CS 0x00400000
31#define BM_GPMI_CTRL0_WORD_LENGTH 0x00800000
32#define BM_GPMI_CTRL0_COMMAND_MODE 0x03000000
33#define BP_GPMI_CTRL0_COMMAND_MODE 24
34#define BV_GPMI_CTRL0_COMMAND_MODE__WRITE 0x0
35#define BV_GPMI_CTRL0_COMMAND_MODE__READ 0x1
36#define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE 0x2
37#define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY 0x3
38#define BM_GPMI_CTRL0_RUN 0x20000000
39#define BM_GPMI_CTRL0_CLKGATE 0x40000000
40#define BM_GPMI_CTRL0_SFTRST 0x80000000
41#define BM_GPMI_ECCCTRL_ENABLE_ECC 0x00001000
42#define BM_GPMI_ECCCTRL_ECC_CMD 0x00006000
43#define BP_GPMI_ECCCTRL_ECC_CMD 13
44
45#define HW_GPMI_CTRL1 0x60
46#define BM_GPMI_CTRL1_GPMI_MODE 0x00000003
47#define BP_GPMI_CTRL1_GPMI_MODE 0
48#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY 0x00000004
49#define BM_GPMI_CTRL1_DEV_RESET 0x00000008
50#define BM_GPMI_CTRL1_TIMEOUT_IRQ 0x00000200
51#define BM_GPMI_CTRL1_DEV_IRQ 0x00000400
52#define BM_GPMI_CTRL1_DSAMPLE_TIME 0x00007000
53#define BP_GPMI_CTRL1_DSAMPLE_TIME 12
54
55#define HW_GPMI_TIMING0 0x70
56#define BM_GPMI_TIMING0_DATA_SETUP 0x000000FF
57#define BP_GPMI_TIMING0_DATA_SETUP 0
58#define BM_GPMI_TIMING0_DATA_HOLD 0x0000FF00
59#define BP_GPMI_TIMING0_DATA_HOLD 8
60
61#define HW_GPMI_TIMING1 0x80
62#define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 0xFFFF0000
63#define BP_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 16
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-i2c.h b/arch/arm/mach-stmp37xx/include/mach/regs-i2c.h
deleted file mode 100644
index 35882a9b8bc5..000000000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-i2c.h
+++ /dev/null
@@ -1,55 +0,0 @@
1/*
2 * stmp37xx: I2C register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_I2C_BASE (STMP3XXX_REGS_BASE + 0x58000)
22#define REGS_I2C_PHYS 0x80058000
23#define REGS_I2C_SIZE 0x2000
24
25#define HW_I2C_CTRL0 0x0
26#define BM_I2C_CTRL0_XFER_COUNT 0x0000FFFF
27#define BP_I2C_CTRL0_XFER_COUNT 0
28#define BM_I2C_CTRL0_DIRECTION 0x00010000
29#define BM_I2C_CTRL0_MASTER_MODE 0x00020000
30#define BM_I2C_CTRL0_PRE_SEND_START 0x00080000
31#define BM_I2C_CTRL0_POST_SEND_STOP 0x00100000
32#define BM_I2C_CTRL0_RETAIN_CLOCK 0x00200000
33#define BM_I2C_CTRL0_SEND_NAK_ON_LAST 0x02000000
34#define BM_I2C_CTRL0_CLKGATE 0x40000000
35#define BM_I2C_CTRL0_SFTRST 0x80000000
36
37#define HW_I2C_TIMING0 0x10
38
39#define HW_I2C_TIMING1 0x20
40
41#define HW_I2C_TIMING2 0x30
42
43#define HW_I2C_CTRL1 0x40
44#define BM_I2C_CTRL1_SLAVE_IRQ 0x00000001
45#define BP_I2C_CTRL1_SLAVE_IRQ 0
46#define BM_I2C_CTRL1_SLAVE_STOP_IRQ 0x00000002
47#define BM_I2C_CTRL1_MASTER_LOSS_IRQ 0x00000004
48#define BM_I2C_CTRL1_EARLY_TERM_IRQ 0x00000008
49#define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ 0x00000010
50#define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ 0x00000020
51#define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 0x00000040
52#define BM_I2C_CTRL1_BUS_FREE_IRQ 0x00000080
53#define BM_I2C_CTRL1_CLR_GOT_A_NAK 0x10000000
54
55#define HW_I2C_VERSION 0x90
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-icoll.h b/arch/arm/mach-stmp37xx/include/mach/regs-icoll.h
deleted file mode 100644
index 3b7c92239e20..000000000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-icoll.h
+++ /dev/null
@@ -1,43 +0,0 @@
1/*
2 * stmp37xx: ICOLL register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef _MACH_REGS_ICOLL
22#define _MACH_REGS_ICOLL
23
24#define REGS_ICOLL_BASE (STMP3XXX_REGS_BASE + 0x0)
25
26#define HW_ICOLL_VECTOR 0x0
27
28#define HW_ICOLL_LEVELACK 0x10
29
30#define HW_ICOLL_CTRL 0x20
31#define BM_ICOLL_CTRL_CLKGATE 0x40000000
32#define BM_ICOLL_CTRL_SFTRST 0x80000000
33
34#define HW_ICOLL_STAT 0x30
35
36#define HW_ICOLL_PRIORITY0 (0x60 + 0 * 0x10)
37#define HW_ICOLL_PRIORITY1 (0x60 + 1 * 0x10)
38#define HW_ICOLL_PRIORITY2 (0x60 + 2 * 0x10)
39#define HW_ICOLL_PRIORITY3 (0x60 + 3 * 0x10)
40
41#define HW_ICOLL_PRIORITYn 0x60
42
43#endif
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-lcdif.h b/arch/arm/mach-stmp37xx/include/mach/regs-lcdif.h
deleted file mode 100644
index 72514e8b0737..000000000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-lcdif.h
+++ /dev/null
@@ -1,89 +0,0 @@
1/*
2 * stmp37xx: LCDIF register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_LCDIF_BASE (STMP3XXX_REGS_BASE + 0x30000)
22#define REGS_LCDIF_PHYS 0x80030000
23#define REGS_LCDIF_SIZE 0x2000
24
25#define HW_LCDIF_CTRL 0x0
26#define BM_LCDIF_CTRL_COUNT 0x0000FFFF
27#define BP_LCDIF_CTRL_COUNT 0
28#define BM_LCDIF_CTRL_RUN 0x00010000
29#define BM_LCDIF_CTRL_WORD_LENGTH 0x00020000
30#define BM_LCDIF_CTRL_DATA_SELECT 0x00040000
31#define BM_LCDIF_CTRL_DOTCLK_MODE 0x00080000
32#define BM_LCDIF_CTRL_VSYNC_MODE 0x00100000
33#define BM_LCDIF_CTRL_DATA_SWIZZLE 0x00600000
34#define BP_LCDIF_CTRL_DATA_SWIZZLE 21
35#define BM_LCDIF_CTRL_BYPASS_COUNT 0x00800000
36#define BM_LCDIF_CTRL_SHIFT_NUM_BITS 0x06000000
37#define BP_LCDIF_CTRL_SHIFT_NUM_BITS 25
38#define BM_LCDIF_CTRL_DATA_SHIFT_DIR 0x08000000
39#define BM_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE 0x10000000
40#define BM_LCDIF_CTRL_CLKGATE 0x40000000
41#define BM_LCDIF_CTRL_SFTRST 0x80000000
42
43#define HW_LCDIF_CTRL1 0x10
44#define BM_LCDIF_CTRL1_RESET 0x00000001
45#define BP_LCDIF_CTRL1_RESET 0
46#define BM_LCDIF_CTRL1_MODE86 0x00000002
47#define BM_LCDIF_CTRL1_BUSY_ENABLE 0x00000004
48#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ 0x00000100
49#define BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ 0x00000200
50#define BM_LCDIF_CTRL1_UNDERFLOW_IRQ 0x00000400
51#define BM_LCDIF_CTRL1_OVERFLOW_IRQ 0x00000800
52#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN 0x00001000
53#define BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT 0x000F0000
54#define BP_LCDIF_CTRL1_BYTE_PACKING_FORMAT 16
55
56#define HW_LCDIF_TIMING 0x20
57
58#define HW_LCDIF_VDCTRL0 0x30
59#define BM_LCDIF_VDCTRL0_VALID_DATA_CNT 0x000003FF
60#define BP_LCDIF_VDCTRL0_VALID_DATA_CNT 0
61#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT 0x00100000
62#define BM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT 0x00200000
63#define BM_LCDIF_VDCTRL0_ENABLE_POL 0x01000000
64#define BM_LCDIF_VDCTRL0_DOTCLK_POL 0x02000000
65#define BM_LCDIF_VDCTRL0_HSYNC_POL 0x04000000
66#define BM_LCDIF_VDCTRL0_VSYNC_POL 0x08000000
67#define BM_LCDIF_VDCTRL0_ENABLE_PRESENT 0x10000000
68#define BM_LCDIF_VDCTRL0_VSYNC_OEB 0x20000000
69
70#define HW_LCDIF_VDCTRL1 0x40
71#define BM_LCDIF_VDCTRL1_VSYNC_PERIOD 0x000FFFFF
72#define BP_LCDIF_VDCTRL1_VSYNC_PERIOD 0
73#define BM_LCDIF_VDCTRL1_VSYNC_PULSE_WIDTH 0xFFF00000
74#define BP_LCDIF_VDCTRL1_VSYNC_PULSE_WIDTH 20
75
76#define HW_LCDIF_VDCTRL2 0x50
77#define BM_LCDIF_VDCTRL2_VALID_DATA_CNT 0x000007FF
78#define BP_LCDIF_VDCTRL2_VALID_DATA_CNT 0
79#define BM_LCDIF_VDCTRL2_HSYNC_PERIOD 0x007FF800
80#define BP_LCDIF_VDCTRL2_HSYNC_PERIOD 11
81#define BM_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 0xFF800000
82#define BP_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 23
83
84#define HW_LCDIF_VDCTRL3 0x60
85#define BM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0x000001FF
86#define BP_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0
87#define BM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 0x00FFF000
88#define BP_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 12
89#define BM_LCDIF_VDCTRL3_SYNC_SIGNALS_ON 0x01000000
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-lradc.h b/arch/arm/mach-stmp37xx/include/mach/regs-lradc.h
deleted file mode 100644
index cc7b4702d1cd..000000000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-lradc.h
+++ /dev/null
@@ -1,97 +0,0 @@
1/*
2 * stmp37xx: LRADC register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_LRADC_BASE (STMP3XXX_REGS_BASE + 0x50000)
22
23#define HW_LRADC_CTRL0 0x0
24#define BM_LRADC_CTRL0_SCHEDULE 0x000000FF
25#define BP_LRADC_CTRL0_SCHEDULE 0
26#define BM_LRADC_CTRL0_XPLUS_ENABLE 0x00010000
27#define BM_LRADC_CTRL0_YPLUS_ENABLE 0x00020000
28#define BM_LRADC_CTRL0_XMINUS_ENABLE 0x00040000
29#define BM_LRADC_CTRL0_YMINUS_ENABLE 0x00080000
30#define BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE 0x00100000
31#define BM_LRADC_CTRL0_ONCHIP_GROUNDREF 0x00200000
32#define BM_LRADC_CTRL0_CLKGATE 0x40000000
33#define BM_LRADC_CTRL0_SFTRST 0x80000000
34
35#define HW_LRADC_CTRL1 0x10
36#define BM_LRADC_CTRL1_LRADC0_IRQ 0x00000001
37#define BP_LRADC_CTRL1_LRADC0_IRQ 0
38#define BM_LRADC_CTRL1_LRADC5_IRQ 0x00000020
39#define BM_LRADC_CTRL1_LRADC6_IRQ 0x00000040
40#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ 0x00000100
41#define BM_LRADC_CTRL1_LRADC0_IRQ_EN 0x00010000
42#define BM_LRADC_CTRL1_LRADC5_IRQ_EN 0x00200000
43#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN 0x01000000
44
45#define HW_LRADC_CTRL2 0x20
46#define BM_LRADC_CTRL2_BL_BRIGHTNESS 0x001F0000
47#define BP_LRADC_CTRL2_BL_BRIGHTNESS 16
48#define BM_LRADC_CTRL2_BL_MUX_SELECT 0x00200000
49#define BM_LRADC_CTRL2_BL_ENABLE 0x00400000
50#define BM_LRADC_CTRL2_DIVIDE_BY_TWO 0xFF000000
51#define BP_LRADC_CTRL2_DIVIDE_BY_TWO 24
52
53#define HW_LRADC_CTRL3 0x30
54#define BM_LRADC_CTRL3_CYCLE_TIME 0x00000300
55#define BP_LRADC_CTRL3_CYCLE_TIME 8
56
57#define HW_LRADC_STATUS 0x40
58#define BM_LRADC_STATUS_TOUCH_DETECT_RAW 0x00000001
59#define BP_LRADC_STATUS_TOUCH_DETECT_RAW 0
60
61#define HW_LRADC_CH0 (0x50 + 0 * 0x10)
62#define HW_LRADC_CH1 (0x50 + 1 * 0x10)
63#define HW_LRADC_CH2 (0x50 + 2 * 0x10)
64#define HW_LRADC_CH3 (0x50 + 3 * 0x10)
65#define HW_LRADC_CH4 (0x50 + 4 * 0x10)
66#define HW_LRADC_CH5 (0x50 + 5 * 0x10)
67#define HW_LRADC_CH6 (0x50 + 6 * 0x10)
68#define HW_LRADC_CH7 (0x50 + 7 * 0x10)
69
70#define HW_LRADC_CHn 0x50
71#define BM_LRADC_CHn_VALUE 0x0003FFFF
72#define BP_LRADC_CHn_VALUE 0
73#define BM_LRADC_CHn_NUM_SAMPLES 0x1F000000
74#define BP_LRADC_CHn_NUM_SAMPLES 24
75#define BM_LRADC_CHn_ACCUMULATE 0x20000000
76
77#define HW_LRADC_DELAY0 (0xD0 + 0 * 0x10)
78#define HW_LRADC_DELAY1 (0xD0 + 1 * 0x10)
79#define HW_LRADC_DELAY2 (0xD0 + 2 * 0x10)
80#define HW_LRADC_DELAY3 (0xD0 + 3 * 0x10)
81
82#define HW_LRADC_DELAYn 0xD0
83#define BM_LRADC_DELAYn_DELAY 0x000007FF
84#define BP_LRADC_DELAYn_DELAY 0
85#define BM_LRADC_DELAYn_LOOP_COUNT 0x0000F800
86#define BP_LRADC_DELAYn_LOOP_COUNT 11
87#define BM_LRADC_DELAYn_TRIGGER_DELAYS 0x000F0000
88#define BP_LRADC_DELAYn_TRIGGER_DELAYS 16
89#define BM_LRADC_DELAYn_KICK 0x00100000
90#define BM_LRADC_DELAYn_TRIGGER_LRADCS 0xFF000000
91#define BP_LRADC_DELAYn_TRIGGER_LRADCS 24
92
93#define HW_LRADC_CTRL4 0x140
94#define BM_LRADC_CTRL4_LRADC6SELECT 0x0F000000
95#define BP_LRADC_CTRL4_LRADC6SELECT 24
96#define BM_LRADC_CTRL4_LRADC7SELECT 0xF0000000
97#define BP_LRADC_CTRL4_LRADC7SELECT 28
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-pinctrl.h b/arch/arm/mach-stmp37xx/include/mach/regs-pinctrl.h
deleted file mode 100644
index d5efce2388c7..000000000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-pinctrl.h
+++ /dev/null
@@ -1,88 +0,0 @@
1/*
2 * stmp37xx: PINCTRL register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef _MACH_REGS_PINCTRL
22#define _MACH_REGS_PINCTRL
23
24#define REGS_PINCTRL_BASE (STMP3XXX_REGS_BASE + 0x18000)
25
26#define HW_PINCTRL_MUXSEL0 0x100
27#define HW_PINCTRL_MUXSEL1 0x110
28#define HW_PINCTRL_MUXSEL2 0x120
29#define HW_PINCTRL_MUXSEL3 0x130
30#define HW_PINCTRL_MUXSEL4 0x140
31#define HW_PINCTRL_MUXSEL5 0x150
32#define HW_PINCTRL_MUXSEL6 0x160
33#define HW_PINCTRL_MUXSEL7 0x170
34
35#define HW_PINCTRL_DRIVE0 0x200
36#define HW_PINCTRL_DRIVE1 0x210
37#define HW_PINCTRL_DRIVE2 0x220
38#define HW_PINCTRL_DRIVE3 0x230
39#define HW_PINCTRL_DRIVE4 0x240
40#define HW_PINCTRL_DRIVE5 0x250
41#define HW_PINCTRL_DRIVE6 0x260
42#define HW_PINCTRL_DRIVE7 0x270
43#define HW_PINCTRL_DRIVE8 0x280
44#define HW_PINCTRL_DRIVE9 0x290
45#define HW_PINCTRL_DRIVE10 0x2A0
46#define HW_PINCTRL_DRIVE11 0x2B0
47#define HW_PINCTRL_DRIVE12 0x2C0
48#define HW_PINCTRL_DRIVE13 0x2D0
49#define HW_PINCTRL_DRIVE14 0x2E0
50
51#define HW_PINCTRL_PULL0 0x300
52#define HW_PINCTRL_PULL1 0x310
53#define HW_PINCTRL_PULL2 0x320
54#define HW_PINCTRL_PULL3 0x330
55
56#define HW_PINCTRL_DOUT0 0x400
57#define HW_PINCTRL_DOUT1 0x410
58#define HW_PINCTRL_DOUT2 0x420
59
60#define HW_PINCTRL_DIN0 0x500
61#define HW_PINCTRL_DIN1 0x510
62#define HW_PINCTRL_DIN2 0x520
63
64#define HW_PINCTRL_DOE0 0x600
65#define HW_PINCTRL_DOE1 0x610
66#define HW_PINCTRL_DOE2 0x620
67
68#define HW_PINCTRL_PIN2IRQ0 0x700
69#define HW_PINCTRL_PIN2IRQ1 0x710
70#define HW_PINCTRL_PIN2IRQ2 0x720
71
72#define HW_PINCTRL_IRQEN0 0x800
73#define HW_PINCTRL_IRQEN1 0x810
74#define HW_PINCTRL_IRQEN2 0x820
75
76#define HW_PINCTRL_IRQLEVEL0 0x900
77#define HW_PINCTRL_IRQLEVEL1 0x910
78#define HW_PINCTRL_IRQLEVEL2 0x920
79
80#define HW_PINCTRL_IRQPOL0 0xA00
81#define HW_PINCTRL_IRQPOL1 0xA10
82#define HW_PINCTRL_IRQPOL2 0xA20
83
84#define HW_PINCTRL_IRQSTAT0 0xB00
85#define HW_PINCTRL_IRQSTAT1 0xB10
86#define HW_PINCTRL_IRQSTAT2 0xB20
87
88#endif
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-power.h b/arch/arm/mach-stmp37xx/include/mach/regs-power.h
deleted file mode 100644
index 0e733d74a229..000000000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-power.h
+++ /dev/null
@@ -1,56 +0,0 @@
1/*
2 * stmp37xx: POWER register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef _MACH_REGS_POWER
22#define _MACH_REGS_POWER
23
24#define REGS_POWER_BASE (STMP3XXX_REGS_BASE + 0x44000)
25
26#define HW_POWER_CTRL 0x0
27#define BM_POWER_CTRL_CLKGATE 0x40000000
28
29#define HW_POWER_5VCTRL 0x10
30
31#define HW_POWER_MINPWR 0x20
32
33#define HW_POWER_CHARGE 0x30
34
35#define HW_POWER_VDDDCTRL 0x40
36
37#define HW_POWER_VDDACTRL 0x50
38
39#define HW_POWER_VDDIOCTRL 0x60
40#define BM_POWER_VDDIOCTRL_TRG 0x0000001F
41#define BP_POWER_VDDIOCTRL_TRG 0
42
43#define HW_POWER_STS 0xB0
44#define BM_POWER_STS_VBUSVALID 0x00000002
45#define BM_POWER_STS_BVALID 0x00000004
46#define BM_POWER_STS_AVALID 0x00000008
47#define BM_POWER_STS_DC_OK 0x00000100
48
49#define HW_POWER_RESET 0xE0
50
51#define HW_POWER_DEBUG 0xF0
52#define BM_POWER_DEBUG_BVALIDPIOLOCK 0x00000002
53#define BM_POWER_DEBUG_AVALIDPIOLOCK 0x00000004
54#define BM_POWER_DEBUG_VBUSVALIDPIOLOCK 0x00000008
55
56#endif
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-pwm.h b/arch/arm/mach-stmp37xx/include/mach/regs-pwm.h
deleted file mode 100644
index 15966a1b62e0..000000000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-pwm.h
+++ /dev/null
@@ -1,51 +0,0 @@
1/*
2 * stmp37xx: PWM register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_PWM_BASE (STMP3XXX_REGS_BASE + 0x64000)
22
23#define HW_PWM_CTRL 0x0
24#define BM_PWM_CTRL_PWM2_ENABLE 0x00000004
25#define BM_PWM_CTRL_PWM2_ANA_CTRL_ENABLE 0x00000020
26
27#define HW_PWM_ACTIVE0 (0x10 + 0 * 0x20)
28#define HW_PWM_ACTIVE1 (0x10 + 1 * 0x20)
29#define HW_PWM_ACTIVE2 (0x10 + 2 * 0x20)
30#define HW_PWM_ACTIVE3 (0x10 + 3 * 0x20)
31
32#define HW_PWM_ACTIVEn 0x10
33#define BM_PWM_ACTIVEn_ACTIVE 0x0000FFFF
34#define BP_PWM_ACTIVEn_ACTIVE 0
35#define BM_PWM_ACTIVEn_INACTIVE 0xFFFF0000
36#define BP_PWM_ACTIVEn_INACTIVE 16
37
38#define HW_PWM_PERIOD0 (0x20 + 0 * 0x20)
39#define HW_PWM_PERIOD1 (0x20 + 1 * 0x20)
40#define HW_PWM_PERIOD2 (0x20 + 2 * 0x20)
41#define HW_PWM_PERIOD3 (0x20 + 3 * 0x20)
42
43#define HW_PWM_PERIODn 0x20
44#define BM_PWM_PERIODn_PERIOD 0x0000FFFF
45#define BP_PWM_PERIODn_PERIOD 0
46#define BM_PWM_PERIODn_ACTIVE_STATE 0x00030000
47#define BP_PWM_PERIODn_ACTIVE_STATE 16
48#define BM_PWM_PERIODn_INACTIVE_STATE 0x000C0000
49#define BP_PWM_PERIODn_INACTIVE_STATE 18
50#define BM_PWM_PERIODn_CDIV 0x00700000
51#define BP_PWM_PERIODn_CDIV 20
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-rtc.h b/arch/arm/mach-stmp37xx/include/mach/regs-rtc.h
deleted file mode 100644
index fac40edc38a1..000000000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-rtc.h
+++ /dev/null
@@ -1,57 +0,0 @@
1/*
2 * stmp37xx: RTC register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_RTC_BASE (STMP3XXX_REGS_BASE + 0x5C000)
22#define REGS_RTC_PHYS 0x8005C000
23#define REGS_RTC_SIZE 0x2000
24
25#define HW_RTC_CTRL 0x0
26#define BM_RTC_CTRL_ALARM_IRQ_EN 0x00000001
27#define BP_RTC_CTRL_ALARM_IRQ_EN 0
28#define BM_RTC_CTRL_ONEMSEC_IRQ_EN 0x00000002
29#define BM_RTC_CTRL_ALARM_IRQ 0x00000004
30#define BM_RTC_CTRL_ONEMSEC_IRQ 0x00000008
31#define BM_RTC_CTRL_WATCHDOGEN 0x00000010
32
33#define HW_RTC_STAT 0x10
34#define BM_RTC_STAT_NEW_REGS 0x0000FF00
35#define BP_RTC_STAT_NEW_REGS 8
36#define BM_RTC_STAT_STALE_REGS 0x00FF0000
37#define BP_RTC_STAT_STALE_REGS 16
38#define BM_RTC_STAT_RTC_PRESENT 0x80000000
39
40#define HW_RTC_SECONDS 0x30
41
42#define HW_RTC_ALARM 0x40
43
44#define HW_RTC_WATCHDOG 0x50
45
46#define HW_RTC_PERSISTENT0 0x60
47#define BM_RTC_PERSISTENT0_ALARM_WAKE_EN 0x00000002
48#define BM_RTC_PERSISTENT0_ALARM_EN 0x00000004
49#define BM_RTC_PERSISTENT0_XTAL24MHZ_PWRUP 0x00000010
50#define BM_RTC_PERSISTENT0_XTAL32KHZ_PWRUP 0x00000020
51#define BM_RTC_PERSISTENT0_ALARM_WAKE 0x00000080
52#define BM_RTC_PERSISTENT0_SPARE_ANALOG 0xFFFC0000
53#define BP_RTC_PERSISTENT0_SPARE_ANALOG 18
54
55#define HW_RTC_PERSISTENT1 0x70
56
57#define HW_RTC_VERSION 0xD0
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-ssp.h b/arch/arm/mach-stmp37xx/include/mach/regs-ssp.h
deleted file mode 100644
index cbde891a06c2..000000000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-ssp.h
+++ /dev/null
@@ -1,101 +0,0 @@
1/*
2 * stmp37xx: SSP register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_SSP_BASE (STMP3XXX_REGS_BASE + 0x10000)
22#define REGS_SSP1_PHYS 0x80010000
23#define REGS_SSP2_PHYS 0x80034000
24#define REGS_SSP_SIZE 0x2000
25
26#define HW_SSP_CTRL0 0x0
27#define BM_SSP_CTRL0_XFER_COUNT 0x0000FFFF
28#define BP_SSP_CTRL0_XFER_COUNT 0
29#define BM_SSP_CTRL0_ENABLE 0x00010000
30#define BM_SSP_CTRL0_GET_RESP 0x00020000
31#define BM_SSP_CTRL0_LONG_RESP 0x00080000
32#define BM_SSP_CTRL0_WAIT_FOR_CMD 0x00100000
33#define BM_SSP_CTRL0_WAIT_FOR_IRQ 0x00200000
34#define BM_SSP_CTRL0_BUS_WIDTH 0x00C00000
35#define BP_SSP_CTRL0_BUS_WIDTH 22
36#define BM_SSP_CTRL0_DATA_XFER 0x01000000
37#define BM_SSP_CTRL0_READ 0x02000000
38#define BM_SSP_CTRL0_IGNORE_CRC 0x04000000
39#define BM_SSP_CTRL0_LOCK_CS 0x08000000
40#define BM_SSP_CTRL0_RUN 0x20000000
41#define BM_SSP_CTRL0_CLKGATE 0x40000000
42#define BM_SSP_CTRL0_SFTRST 0x80000000
43
44#define HW_SSP_CMD0 0x10
45#define BM_SSP_CMD0_CMD 0x000000FF
46#define BP_SSP_CMD0_CMD 0
47#define BM_SSP_CMD0_BLOCK_COUNT 0x0000FF00
48#define BP_SSP_CMD0_BLOCK_COUNT 8
49#define BM_SSP_CMD0_BLOCK_SIZE 0x000F0000
50#define BP_SSP_CMD0_BLOCK_SIZE 16
51#define BM_SSP_CMD0_APPEND_8CYC 0x00100000
52#define BM_SSP_CMD1_CMD_ARG 0xFFFFFFFF
53#define BP_SSP_CMD1_CMD_ARG 0
54
55#define HW_SSP_TIMING 0x50
56#define BM_SSP_TIMING_CLOCK_RATE 0x000000FF
57#define BP_SSP_TIMING_CLOCK_RATE 0
58#define BM_SSP_TIMING_CLOCK_DIVIDE 0x0000FF00
59#define BP_SSP_TIMING_CLOCK_DIVIDE 8
60#define BM_SSP_TIMING_TIMEOUT 0xFFFF0000
61#define BP_SSP_TIMING_TIMEOUT 16
62
63#define HW_SSP_CTRL1 0x60
64#define BM_SSP_CTRL1_SSP_MODE 0x0000000F
65#define BP_SSP_CTRL1_SSP_MODE 0
66#define BM_SSP_CTRL1_WORD_LENGTH 0x000000F0
67#define BP_SSP_CTRL1_WORD_LENGTH 4
68#define BM_SSP_CTRL1_POLARITY 0x00000200
69#define BM_SSP_CTRL1_PHASE 0x00000400
70#define BM_SSP_CTRL1_DMA_ENABLE 0x00002000
71#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ 0x00008000
72#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN 0x00010000
73#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ 0x00020000
74#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ 0x00200000
75#define BM_SSP_CTRL1_DATA_CRC_IRQ_EN 0x00400000
76#define BM_SSP_CTRL1_DATA_CRC_IRQ 0x00800000
77#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN 0x01000000
78#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ 0x02000000
79#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN 0x04000000
80#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ 0x08000000
81#define BM_SSP_CTRL1_RESP_ERR_IRQ_EN 0x10000000
82#define BM_SSP_CTRL1_RESP_ERR_IRQ 0x20000000
83#define BM_SSP_CTRL1_SDIO_IRQ 0x80000000
84
85#define HW_SSP_DATA 0x70
86
87#define HW_SSP_SDRESP0 0x80
88
89#define HW_SSP_SDRESP1 0x90
90
91#define HW_SSP_SDRESP2 0xA0
92
93#define HW_SSP_SDRESP3 0xB0
94
95#define HW_SSP_STATUS 0xC0
96#define BM_SSP_STATUS_FIFO_EMPTY 0x00000020
97#define BM_SSP_STATUS_TIMEOUT 0x00001000
98#define BM_SSP_STATUS_RESP_TIMEOUT 0x00004000
99#define BM_SSP_STATUS_RESP_ERR 0x00008000
100#define BM_SSP_STATUS_RESP_CRC_ERR 0x00010000
101#define BM_SSP_STATUS_CARD_DETECT 0x10000000
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-timrot.h b/arch/arm/mach-stmp37xx/include/mach/regs-timrot.h
deleted file mode 100644
index 4af0f6edfa78..000000000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-timrot.h
+++ /dev/null
@@ -1,49 +0,0 @@
1/*
2 * stmp37xx: TIMROT register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef _MACH_REGS_TIMROT
22#define _MACH_REGS_TIMROT
23
24#define REGS_TIMROT_BASE (STMP3XXX_REGS_BASE + 0x68000)
25
26#define HW_TIMROT_ROTCTRL 0x0
27#define BM_TIMROT_ROTCTRL_CLKGATE 0x40000000
28#define BM_TIMROT_ROTCTRL_SFTRST 0x80000000
29
30#define HW_TIMROT_TIMCTRL0 (0x20 + 0 * 0x20)
31#define HW_TIMROT_TIMCTRL1 (0x20 + 1 * 0x20)
32#define HW_TIMROT_TIMCTRL2 (0x20 + 2 * 0x20)
33
34#define HW_TIMROT_TIMCTRLn 0x20
35#define BM_TIMROT_TIMCTRLn_SELECT 0x0000000F
36#define BP_TIMROT_TIMCTRLn_SELECT 0
37#define BM_TIMROT_TIMCTRLn_PRESCALE 0x00000030
38#define BP_TIMROT_TIMCTRLn_PRESCALE 4
39#define BM_TIMROT_TIMCTRLn_RELOAD 0x00000040
40#define BM_TIMROT_TIMCTRLn_UPDATE 0x00000080
41#define BM_TIMROT_TIMCTRLn_IRQ_EN 0x00004000
42#define BM_TIMROT_TIMCTRLn_IRQ 0x00008000
43
44#define HW_TIMROT_TIMCOUNT0 (0x30 + 0 * 0x20)
45#define HW_TIMROT_TIMCOUNT1 (0x30 + 1 * 0x20)
46#define HW_TIMROT_TIMCOUNT2 (0x30 + 2 * 0x20)
47
48#define HW_TIMROT_TIMCOUNTn 0x30
49#endif
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-uartapp.h b/arch/arm/mach-stmp37xx/include/mach/regs-uartapp.h
deleted file mode 100644
index 0594275d860c..000000000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-uartapp.h
+++ /dev/null
@@ -1,85 +0,0 @@
1/*
2 * stmp37xx: UARTAPP register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_UARTAPP_BASE (STMP3XXX_REGS_BASE + 0x6C000)
22#define REGS_UARTAPP1_PHYS 0x8006C000
23#define REGS_UARTAPP_SIZE 0x2000
24
25#define HW_UARTAPP_CTRL0 0x0
26#define BM_UARTAPP_CTRL0_XFER_COUNT 0x0000FFFF
27#define BP_UARTAPP_CTRL0_XFER_COUNT 0
28#define BM_UARTAPP_CTRL0_RXTIMEOUT 0x07FF0000
29#define BP_UARTAPP_CTRL0_RXTIMEOUT 16
30#define BM_UARTAPP_CTRL0_RXTO_ENABLE 0x08000000
31#define BM_UARTAPP_CTRL0_RUN 0x20000000
32#define BM_UARTAPP_CTRL0_SFTRST 0x80000000
33#define BM_UARTAPP_CTRL1_XFER_COUNT 0x0000FFFF
34#define BP_UARTAPP_CTRL1_XFER_COUNT 0
35#define BM_UARTAPP_CTRL1_RUN 0x10000000
36
37#define HW_UARTAPP_CTRL2 0x20
38#define BM_UARTAPP_CTRL2_UARTEN 0x00000001
39#define BP_UARTAPP_CTRL2_UARTEN 0
40#define BM_UARTAPP_CTRL2_TXE 0x00000100
41#define BM_UARTAPP_CTRL2_RXE 0x00000200
42#define BM_UARTAPP_CTRL2_RTS 0x00000800
43#define BM_UARTAPP_CTRL2_RTSEN 0x00004000
44#define BM_UARTAPP_CTRL2_CTSEN 0x00008000
45#define BM_UARTAPP_CTRL2_RXDMAE 0x01000000
46#define BM_UARTAPP_CTRL2_TXDMAE 0x02000000
47#define BM_UARTAPP_CTRL2_DMAONERR 0x04000000
48
49#define HW_UARTAPP_LINECTRL 0x30
50#define BM_UARTAPP_LINECTRL_BRK 0x00000001
51#define BP_UARTAPP_LINECTRL_BRK 0
52#define BM_UARTAPP_LINECTRL_PEN 0x00000002
53#define BM_UARTAPP_LINECTRL_EPS 0x00000004
54#define BM_UARTAPP_LINECTRL_STP2 0x00000008
55#define BM_UARTAPP_LINECTRL_FEN 0x00000010
56#define BM_UARTAPP_LINECTRL_WLEN 0x00000060
57#define BP_UARTAPP_LINECTRL_WLEN 5
58#define BM_UARTAPP_LINECTRL_SPS 0x00000080
59#define BM_UARTAPP_LINECTRL_BAUD_DIVFRAC 0x00003F00
60#define BP_UARTAPP_LINECTRL_BAUD_DIVFRAC 8
61#define BM_UARTAPP_LINECTRL_BAUD_DIVINT 0xFFFF0000
62#define BP_UARTAPP_LINECTRL_BAUD_DIVINT 16
63
64#define HW_UARTAPP_INTR 0x50
65#define BM_UARTAPP_INTR_CTSMIS 0x00000002
66#define BM_UARTAPP_INTR_RTIS 0x00000040
67#define BM_UARTAPP_INTR_CTSMIEN 0x00020000
68#define BM_UARTAPP_INTR_RXIEN 0x00100000
69#define BM_UARTAPP_INTR_RTIEN 0x00400000
70
71#define HW_UARTAPP_DATA 0x60
72
73#define HW_UARTAPP_STAT 0x70
74#define BM_UARTAPP_STAT_RXCOUNT 0x0000FFFF
75#define BP_UARTAPP_STAT_RXCOUNT 0
76#define BM_UARTAPP_STAT_FERR 0x00010000
77#define BM_UARTAPP_STAT_PERR 0x00020000
78#define BM_UARTAPP_STAT_BERR 0x00040000
79#define BM_UARTAPP_STAT_OERR 0x00080000
80#define BM_UARTAPP_STAT_RXFE 0x01000000
81#define BM_UARTAPP_STAT_TXFF 0x02000000
82#define BM_UARTAPP_STAT_TXFE 0x08000000
83#define BM_UARTAPP_STAT_CTS 0x10000000
84
85#define HW_UARTAPP_VERSION 0x90
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-uartdbg.h b/arch/arm/mach-stmp37xx/include/mach/regs-uartdbg.h
deleted file mode 100644
index b810deb552a9..000000000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-uartdbg.h
+++ /dev/null
@@ -1,268 +0,0 @@
1/*
2 * stmp378x: UARTDBG register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_UARTDBG_BASE (STMP3XXX_REGS_BASE + 0x70000)
22#define REGS_UARTDBG_PHYS 0x80070000
23#define REGS_UARTDBG_SIZE 0x2000
24
25#define HW_UARTDBGDR 0x00000000
26#define BP_UARTDBGDR_UNAVAILABLE 16
27#define BM_UARTDBGDR_UNAVAILABLE 0xFFFF0000
28#define BF_UARTDBGDR_UNAVAILABLE(v) \
29 (((v) << 16) & BM_UARTDBGDR_UNAVAILABLE)
30#define BP_UARTDBGDR_RESERVED 12
31#define BM_UARTDBGDR_RESERVED 0x0000F000
32#define BF_UARTDBGDR_RESERVED(v) \
33 (((v) << 12) & BM_UARTDBGDR_RESERVED)
34#define BM_UARTDBGDR_OE 0x00000800
35#define BM_UARTDBGDR_BE 0x00000400
36#define BM_UARTDBGDR_PE 0x00000200
37#define BM_UARTDBGDR_FE 0x00000100
38#define BP_UARTDBGDR_DATA 0
39#define BM_UARTDBGDR_DATA 0x000000FF
40#define BF_UARTDBGDR_DATA(v) \
41 (((v) << 0) & BM_UARTDBGDR_DATA)
42#define HW_UARTDBGRSR_ECR 0x00000004
43#define BP_UARTDBGRSR_ECR_UNAVAILABLE 8
44#define BM_UARTDBGRSR_ECR_UNAVAILABLE 0xFFFFFF00
45#define BF_UARTDBGRSR_ECR_UNAVAILABLE(v) \
46 (((v) << 8) & BM_UARTDBGRSR_ECR_UNAVAILABLE)
47#define BP_UARTDBGRSR_ECR_EC 4
48#define BM_UARTDBGRSR_ECR_EC 0x000000F0
49#define BF_UARTDBGRSR_ECR_EC(v) \
50 (((v) << 4) & BM_UARTDBGRSR_ECR_EC)
51#define BM_UARTDBGRSR_ECR_OE 0x00000008
52#define BM_UARTDBGRSR_ECR_BE 0x00000004
53#define BM_UARTDBGRSR_ECR_PE 0x00000002
54#define BM_UARTDBGRSR_ECR_FE 0x00000001
55#define HW_UARTDBGFR 0x00000018
56#define BP_UARTDBGFR_UNAVAILABLE 16
57#define BM_UARTDBGFR_UNAVAILABLE 0xFFFF0000
58#define BF_UARTDBGFR_UNAVAILABLE(v) \
59 (((v) << 16) & BM_UARTDBGFR_UNAVAILABLE)
60#define BP_UARTDBGFR_RESERVED 9
61#define BM_UARTDBGFR_RESERVED 0x0000FE00
62#define BF_UARTDBGFR_RESERVED(v) \
63 (((v) << 9) & BM_UARTDBGFR_RESERVED)
64#define BM_UARTDBGFR_RI 0x00000100
65#define BM_UARTDBGFR_TXFE 0x00000080
66#define BM_UARTDBGFR_RXFF 0x00000040
67#define BM_UARTDBGFR_TXFF 0x00000020
68#define BM_UARTDBGFR_RXFE 0x00000010
69#define BM_UARTDBGFR_BUSY 0x00000008
70#define BM_UARTDBGFR_DCD 0x00000004
71#define BM_UARTDBGFR_DSR 0x00000002
72#define BM_UARTDBGFR_CTS 0x00000001
73#define HW_UARTDBGILPR 0x00000020
74#define BP_UARTDBGILPR_UNAVAILABLE 8
75#define BM_UARTDBGILPR_UNAVAILABLE 0xFFFFFF00
76#define BF_UARTDBGILPR_UNAVAILABLE(v) \
77 (((v) << 8) & BM_UARTDBGILPR_UNAVAILABLE)
78#define BP_UARTDBGILPR_ILPDVSR 0
79#define BM_UARTDBGILPR_ILPDVSR 0x000000FF
80#define BF_UARTDBGILPR_ILPDVSR(v) \
81 (((v) << 0) & BM_UARTDBGILPR_ILPDVSR)
82#define HW_UARTDBGIBRD 0x00000024
83#define BP_UARTDBGIBRD_UNAVAILABLE 16
84#define BM_UARTDBGIBRD_UNAVAILABLE 0xFFFF0000
85#define BF_UARTDBGIBRD_UNAVAILABLE(v) \
86 (((v) << 16) & BM_UARTDBGIBRD_UNAVAILABLE)
87#define BP_UARTDBGIBRD_BAUD_DIVINT 0
88#define BM_UARTDBGIBRD_BAUD_DIVINT 0x0000FFFF
89#define BF_UARTDBGIBRD_BAUD_DIVINT(v) \
90 (((v) << 0) & BM_UARTDBGIBRD_BAUD_DIVINT)
91#define HW_UARTDBGFBRD 0x00000028
92#define BP_UARTDBGFBRD_UNAVAILABLE 8
93#define BM_UARTDBGFBRD_UNAVAILABLE 0xFFFFFF00
94#define BF_UARTDBGFBRD_UNAVAILABLE(v) \
95 (((v) << 8) & BM_UARTDBGFBRD_UNAVAILABLE)
96#define BP_UARTDBGFBRD_RESERVED 6
97#define BM_UARTDBGFBRD_RESERVED 0x000000C0
98#define BF_UARTDBGFBRD_RESERVED(v) \
99 (((v) << 6) & BM_UARTDBGFBRD_RESERVED)
100#define BP_UARTDBGFBRD_BAUD_DIVFRAC 0
101#define BM_UARTDBGFBRD_BAUD_DIVFRAC 0x0000003F
102#define BF_UARTDBGFBRD_BAUD_DIVFRAC(v) \
103 (((v) << 0) & BM_UARTDBGFBRD_BAUD_DIVFRAC)
104#define HW_UARTDBGLCR_H 0x0000002c
105#define BP_UARTDBGLCR_H_UNAVAILABLE 16
106#define BM_UARTDBGLCR_H_UNAVAILABLE 0xFFFF0000
107#define BF_UARTDBGLCR_H_UNAVAILABLE(v) \
108 (((v) << 16) & BM_UARTDBGLCR_H_UNAVAILABLE)
109#define BP_UARTDBGLCR_H_RESERVED 8
110#define BM_UARTDBGLCR_H_RESERVED 0x0000FF00
111#define BF_UARTDBGLCR_H_RESERVED(v) \
112 (((v) << 8) & BM_UARTDBGLCR_H_RESERVED)
113#define BM_UARTDBGLCR_H_SPS 0x00000080
114#define BP_UARTDBGLCR_H_WLEN 5
115#define BM_UARTDBGLCR_H_WLEN 0x00000060
116#define BF_UARTDBGLCR_H_WLEN(v) \
117 (((v) << 5) & BM_UARTDBGLCR_H_WLEN)
118#define BM_UARTDBGLCR_H_FEN 0x00000010
119#define BM_UARTDBGLCR_H_STP2 0x00000008
120#define BM_UARTDBGLCR_H_EPS 0x00000004
121#define BM_UARTDBGLCR_H_PEN 0x00000002
122#define BM_UARTDBGLCR_H_BRK 0x00000001
123#define HW_UARTDBGCR 0x00000030
124#define BP_UARTDBGCR_UNAVAILABLE 16
125#define BM_UARTDBGCR_UNAVAILABLE 0xFFFF0000
126#define BF_UARTDBGCR_UNAVAILABLE(v) \
127 (((v) << 16) & BM_UARTDBGCR_UNAVAILABLE)
128#define BM_UARTDBGCR_CTSEN 0x00008000
129#define BM_UARTDBGCR_RTSEN 0x00004000
130#define BM_UARTDBGCR_OUT2 0x00002000
131#define BM_UARTDBGCR_OUT1 0x00001000
132#define BM_UARTDBGCR_RTS 0x00000800
133#define BM_UARTDBGCR_DTR 0x00000400
134#define BM_UARTDBGCR_RXE 0x00000200
135#define BM_UARTDBGCR_TXE 0x00000100
136#define BM_UARTDBGCR_LBE 0x00000080
137#define BP_UARTDBGCR_RESERVED 3
138#define BM_UARTDBGCR_RESERVED 0x00000078
139#define BF_UARTDBGCR_RESERVED(v) \
140 (((v) << 3) & BM_UARTDBGCR_RESERVED)
141#define BM_UARTDBGCR_SIRLP 0x00000004
142#define BM_UARTDBGCR_SIREN 0x00000002
143#define BM_UARTDBGCR_UARTEN 0x00000001
144#define HW_UARTDBGIFLS 0x00000034
145#define BP_UARTDBGIFLS_UNAVAILABLE 16
146#define BM_UARTDBGIFLS_UNAVAILABLE 0xFFFF0000
147#define BF_UARTDBGIFLS_UNAVAILABLE(v) \
148 (((v) << 16) & BM_UARTDBGIFLS_UNAVAILABLE)
149#define BP_UARTDBGIFLS_RESERVED 6
150#define BM_UARTDBGIFLS_RESERVED 0x0000FFC0
151#define BF_UARTDBGIFLS_RESERVED(v) \
152 (((v) << 6) & BM_UARTDBGIFLS_RESERVED)
153#define BP_UARTDBGIFLS_RXIFLSEL 3
154#define BM_UARTDBGIFLS_RXIFLSEL 0x00000038
155#define BF_UARTDBGIFLS_RXIFLSEL(v) \
156 (((v) << 3) & BM_UARTDBGIFLS_RXIFLSEL)
157#define BV_UARTDBGIFLS_RXIFLSEL__NOT_EMPTY 0x0
158#define BV_UARTDBGIFLS_RXIFLSEL__ONE_QUARTER 0x1
159#define BV_UARTDBGIFLS_RXIFLSEL__ONE_HALF 0x2
160#define BV_UARTDBGIFLS_RXIFLSEL__THREE_QUARTERS 0x3
161#define BV_UARTDBGIFLS_RXIFLSEL__SEVEN_EIGHTHS 0x4
162#define BV_UARTDBGIFLS_RXIFLSEL__INVALID5 0x5
163#define BV_UARTDBGIFLS_RXIFLSEL__INVALID6 0x6
164#define BV_UARTDBGIFLS_RXIFLSEL__INVALID7 0x7
165#define BP_UARTDBGIFLS_TXIFLSEL 0
166#define BM_UARTDBGIFLS_TXIFLSEL 0x00000007
167#define BF_UARTDBGIFLS_TXIFLSEL(v) \
168 (((v) << 0) & BM_UARTDBGIFLS_TXIFLSEL)
169#define BV_UARTDBGIFLS_TXIFLSEL__EMPTY 0x0
170#define BV_UARTDBGIFLS_TXIFLSEL__ONE_QUARTER 0x1
171#define BV_UARTDBGIFLS_TXIFLSEL__ONE_HALF 0x2
172#define BV_UARTDBGIFLS_TXIFLSEL__THREE_QUARTERS 0x3
173#define BV_UARTDBGIFLS_TXIFLSEL__SEVEN_EIGHTHS 0x4
174#define BV_UARTDBGIFLS_TXIFLSEL__INVALID5 0x5
175#define BV_UARTDBGIFLS_TXIFLSEL__INVALID6 0x6
176#define BV_UARTDBGIFLS_TXIFLSEL__INVALID7 0x7
177#define HW_UARTDBGIMSC 0x00000038
178#define BP_UARTDBGIMSC_UNAVAILABLE 16
179#define BM_UARTDBGIMSC_UNAVAILABLE 0xFFFF0000
180#define BF_UARTDBGIMSC_UNAVAILABLE(v) \
181 (((v) << 16) & BM_UARTDBGIMSC_UNAVAILABLE)
182#define BP_UARTDBGIMSC_RESERVED 11
183#define BM_UARTDBGIMSC_RESERVED 0x0000F800
184#define BF_UARTDBGIMSC_RESERVED(v) \
185 (((v) << 11) & BM_UARTDBGIMSC_RESERVED)
186#define BM_UARTDBGIMSC_OEIM 0x00000400
187#define BM_UARTDBGIMSC_BEIM 0x00000200
188#define BM_UARTDBGIMSC_PEIM 0x00000100
189#define BM_UARTDBGIMSC_FEIM 0x00000080
190#define BM_UARTDBGIMSC_RTIM 0x00000040
191#define BM_UARTDBGIMSC_TXIM 0x00000020
192#define BM_UARTDBGIMSC_RXIM 0x00000010
193#define BM_UARTDBGIMSC_DSRMIM 0x00000008
194#define BM_UARTDBGIMSC_DCDMIM 0x00000004
195#define BM_UARTDBGIMSC_CTSMIM 0x00000002
196#define BM_UARTDBGIMSC_RIMIM 0x00000001
197#define HW_UARTDBGRIS 0x0000003c
198#define BP_UARTDBGRIS_UNAVAILABLE 16
199#define BM_UARTDBGRIS_UNAVAILABLE 0xFFFF0000
200#define BF_UARTDBGRIS_UNAVAILABLE(v) \
201 (((v) << 16) & BM_UARTDBGRIS_UNAVAILABLE)
202#define BP_UARTDBGRIS_RESERVED 11
203#define BM_UARTDBGRIS_RESERVED 0x0000F800
204#define BF_UARTDBGRIS_RESERVED(v) \
205 (((v) << 11) & BM_UARTDBGRIS_RESERVED)
206#define BM_UARTDBGRIS_OERIS 0x00000400
207#define BM_UARTDBGRIS_BERIS 0x00000200
208#define BM_UARTDBGRIS_PERIS 0x00000100
209#define BM_UARTDBGRIS_FERIS 0x00000080
210#define BM_UARTDBGRIS_RTRIS 0x00000040
211#define BM_UARTDBGRIS_TXRIS 0x00000020
212#define BM_UARTDBGRIS_RXRIS 0x00000010
213#define BM_UARTDBGRIS_DSRRMIS 0x00000008
214#define BM_UARTDBGRIS_DCDRMIS 0x00000004
215#define BM_UARTDBGRIS_CTSRMIS 0x00000002
216#define BM_UARTDBGRIS_RIRMIS 0x00000001
217#define HW_UARTDBGMIS 0x00000040
218#define BP_UARTDBGMIS_UNAVAILABLE 16
219#define BM_UARTDBGMIS_UNAVAILABLE 0xFFFF0000
220#define BF_UARTDBGMIS_UNAVAILABLE(v) \
221 (((v) << 16) & BM_UARTDBGMIS_UNAVAILABLE)
222#define BP_UARTDBGMIS_RESERVED 11
223#define BM_UARTDBGMIS_RESERVED 0x0000F800
224#define BF_UARTDBGMIS_RESERVED(v) \
225 (((v) << 11) & BM_UARTDBGMIS_RESERVED)
226#define BM_UARTDBGMIS_OEMIS 0x00000400
227#define BM_UARTDBGMIS_BEMIS 0x00000200
228#define BM_UARTDBGMIS_PEMIS 0x00000100
229#define BM_UARTDBGMIS_FEMIS 0x00000080
230#define BM_UARTDBGMIS_RTMIS 0x00000040
231#define BM_UARTDBGMIS_TXMIS 0x00000020
232#define BM_UARTDBGMIS_RXMIS 0x00000010
233#define BM_UARTDBGMIS_DSRMMIS 0x00000008
234#define BM_UARTDBGMIS_DCDMMIS 0x00000004
235#define BM_UARTDBGMIS_CTSMMIS 0x00000002
236#define BM_UARTDBGMIS_RIMMIS 0x00000001
237#define HW_UARTDBGICR 0x00000044
238#define BP_UARTDBGICR_UNAVAILABLE 16
239#define BM_UARTDBGICR_UNAVAILABLE 0xFFFF0000
240#define BF_UARTDBGICR_UNAVAILABLE(v) \
241 (((v) << 16) & BM_UARTDBGICR_UNAVAILABLE)
242#define BP_UARTDBGICR_RESERVED 11
243#define BM_UARTDBGICR_RESERVED 0x0000F800
244#define BF_UARTDBGICR_RESERVED(v) \
245 (((v) << 11) & BM_UARTDBGICR_RESERVED)
246#define BM_UARTDBGICR_OEIC 0x00000400
247#define BM_UARTDBGICR_BEIC 0x00000200
248#define BM_UARTDBGICR_PEIC 0x00000100
249#define BM_UARTDBGICR_FEIC 0x00000080
250#define BM_UARTDBGICR_RTIC 0x00000040
251#define BM_UARTDBGICR_TXIC 0x00000020
252#define BM_UARTDBGICR_RXIC 0x00000010
253#define BM_UARTDBGICR_DSRMIC 0x00000008
254#define BM_UARTDBGICR_DCDMIC 0x00000004
255#define BM_UARTDBGICR_CTSMIC 0x00000002
256#define BM_UARTDBGICR_RIMIC 0x00000001
257#define HW_UARTDBGDMACR 0x00000048
258#define BP_UARTDBGDMACR_UNAVAILABLE 16
259#define BM_UARTDBGDMACR_UNAVAILABLE 0xFFFF0000
260#define BF_UARTDBGDMACR_UNAVAILABLE(v) \
261 (((v) << 16) & BM_UARTDBGDMACR_UNAVAILABLE)
262#define BP_UARTDBGDMACR_RESERVED 3
263#define BM_UARTDBGDMACR_RESERVED 0x0000FFF8
264#define BF_UARTDBGDMACR_RESERVED(v) \
265 (((v) << 3) & BM_UARTDBGDMACR_RESERVED)
266#define BM_UARTDBGDMACR_DMAONERR 0x00000004
267#define BM_UARTDBGDMACR_TXDMAE 0x00000002
268#define BM_UARTDBGDMACR_RXDMAE 0x00000001
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-usbctl.h b/arch/arm/mach-stmp37xx/include/mach/regs-usbctl.h
deleted file mode 100644
index 9145e22df32c..000000000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-usbctl.h
+++ /dev/null
@@ -1,22 +0,0 @@
1/*
2 * stmp37xx: USBCTL register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_USBCTL_BASE (STMP3XXX_REGS_BASE + 0x80000)
22#define REGS_USBCTL_PHYS 0x80000
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-usbctrl.h b/arch/arm/mach-stmp37xx/include/mach/regs-usbctrl.h
deleted file mode 100644
index 1a2ae9cbdfed..000000000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-usbctrl.h
+++ /dev/null
@@ -1,22 +0,0 @@
1/*
2 * stmp37xx: USBCTRL register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_USBCTRL_BASE (STMP3XXX_REGS_BASE + 0x80000)
22#define REGS_USBCTRL_PHYS 0x80080000
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-usbphy.h b/arch/arm/mach-stmp37xx/include/mach/regs-usbphy.h
deleted file mode 100644
index b7fce0fbc560..000000000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-usbphy.h
+++ /dev/null
@@ -1,37 +0,0 @@
1/*
2 * stmp37xx: USBPHY register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_USBPHY_BASE (STMP3XXX_REGS_BASE + 0x7C000)
22
23#define HW_USBPHY_PWD 0x0
24
25#define HW_USBPHY_CTRL 0x30
26#define BM_USBPHY_CTRL_ENHSPRECHARGEXMIT 0x00000001
27#define BP_USBPHY_CTRL_ENHSPRECHARGEXMIT 0
28#define BM_USBPHY_CTRL_ENHOSTDISCONDETECT 0x00000002
29#define BM_USBPHY_CTRL_ENDEVPLUGINDETECT 0x00000010
30#define BM_USBPHY_CTRL_ENOTGIDDETECT 0x00000080
31#define BM_USBPHY_CTRL_ENIRQDEVPLUGIN 0x00000800
32#define BM_USBPHY_CTRL_CLKGATE 0x40000000
33#define BM_USBPHY_CTRL_SFTRST 0x80000000
34
35#define HW_USBPHY_STATUS 0x40
36#define BM_USBPHY_STATUS_DEVPLUGIN_STATUS 0x00000040
37#define BM_USBPHY_STATUS_OTGID_STATUS 0x00000100
diff --git a/arch/arm/mach-stmp37xx/stmp37xx.c b/arch/arm/mach-stmp37xx/stmp37xx.c
deleted file mode 100644
index a9aed06ff376..000000000000
--- a/arch/arm/mach-stmp37xx/stmp37xx.c
+++ /dev/null
@@ -1,219 +0,0 @@
1/*
2 * Freescale STMP37XX platform support
3 *
4 * Embedded Alley Solutions, Inc <source@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#include <linux/types.h>
19#include <linux/kernel.h>
20#include <linux/init.h>
21#include <linux/device.h>
22#include <linux/platform_device.h>
23#include <linux/irq.h>
24#include <linux/io.h>
25
26#include <asm/setup.h>
27#include <asm/mach-types.h>
28
29#include <asm/mach/arch.h>
30#include <asm/mach/irq.h>
31#include <asm/mach/map.h>
32#include <asm/mach/time.h>
33
34#include <mach/stmp3xxx.h>
35#include <mach/dma.h>
36
37#include <mach/platform.h>
38#include <mach/regs-icoll.h>
39#include <mach/regs-apbh.h>
40#include <mach/regs-apbx.h>
41#include "stmp37xx.h"
42
43/*
44 * IRQ handling
45 */
46static void stmp37xx_ack_irq(struct irq_data *d)
47{
48 /* Disable IRQ */
49 stmp3xxx_clearl(0x04 << ((d->irq % 4) * 8),
50 REGS_ICOLL_BASE + HW_ICOLL_PRIORITYn + d->irq / 4 * 0x10);
51
52 /* ACK current interrupt */
53 __raw_writel(1, REGS_ICOLL_BASE + HW_ICOLL_LEVELACK);
54
55 /* Barrier */
56 (void)__raw_readl(REGS_ICOLL_BASE + HW_ICOLL_STAT);
57}
58
59static void stmp37xx_mask_irq(struct irq_data *d)
60{
61 /* IRQ disable */
62 stmp3xxx_clearl(0x04 << ((d->irq % 4) * 8),
63 REGS_ICOLL_BASE + HW_ICOLL_PRIORITYn + d->irq / 4 * 0x10);
64}
65
66static void stmp37xx_unmask_irq(struct irq_data *d)
67{
68 /* IRQ enable */
69 stmp3xxx_setl(0x04 << ((d->irq % 4) * 8),
70 REGS_ICOLL_BASE + HW_ICOLL_PRIORITYn + d->irq / 4 * 0x10);
71}
72
73static struct irq_chip stmp37xx_chip = {
74 .irq_ack = stmp37xx_ack_irq,
75 .irq_mask = stmp37xx_mask_irq,
76 .irq_unmask = stmp37xx_unmask_irq,
77};
78
79void __init stmp37xx_init_irq(void)
80{
81 stmp3xxx_init_irq(&stmp37xx_chip);
82}
83
84/*
85 * DMA interrupt handling
86 */
87void stmp3xxx_arch_dma_enable_interrupt(int channel)
88{
89 switch (STMP3XXX_DMA_BUS(channel)) {
90 case STMP3XXX_BUS_APBH:
91 stmp3xxx_setl(1 << (8 + STMP3XXX_DMA_CHANNEL(channel)),
92 REGS_APBH_BASE + HW_APBH_CTRL1);
93 break;
94
95 case STMP3XXX_BUS_APBX:
96 stmp3xxx_setl(1 << (8 + STMP3XXX_DMA_CHANNEL(channel)),
97 REGS_APBX_BASE + HW_APBX_CTRL1);
98 break;
99 }
100}
101EXPORT_SYMBOL(stmp3xxx_arch_dma_enable_interrupt);
102
103void stmp3xxx_arch_dma_clear_interrupt(int channel)
104{
105 switch (STMP3XXX_DMA_BUS(channel)) {
106 case STMP3XXX_BUS_APBH:
107 stmp3xxx_clearl(1 << STMP3XXX_DMA_CHANNEL(channel),
108 REGS_APBH_BASE + HW_APBH_CTRL1);
109 break;
110
111 case STMP3XXX_BUS_APBX:
112 stmp3xxx_clearl(1 << STMP3XXX_DMA_CHANNEL(channel),
113 REGS_APBX_BASE + HW_APBX_CTRL1);
114 break;
115 }
116}
117EXPORT_SYMBOL(stmp3xxx_arch_dma_clear_interrupt);
118
119int stmp3xxx_arch_dma_is_interrupt(int channel)
120{
121 int r = 0;
122
123 switch (STMP3XXX_DMA_BUS(channel)) {
124 case STMP3XXX_BUS_APBH:
125 r = __raw_readl(REGS_APBH_BASE + HW_APBH_CTRL1) &
126 (1 << STMP3XXX_DMA_CHANNEL(channel));
127 break;
128
129 case STMP3XXX_BUS_APBX:
130 r = __raw_readl(REGS_APBH_BASE + HW_APBH_CTRL1) &
131 (1 << STMP3XXX_DMA_CHANNEL(channel));
132 break;
133 }
134 return r;
135}
136EXPORT_SYMBOL(stmp3xxx_arch_dma_is_interrupt);
137
138void stmp3xxx_arch_dma_reset_channel(int channel)
139{
140 unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
141
142 switch (STMP3XXX_DMA_BUS(channel)) {
143 case STMP3XXX_BUS_APBH:
144 /* Reset channel and wait for it to complete */
145 stmp3xxx_setl(chbit << BP_APBH_CTRL0_RESET_CHANNEL,
146 REGS_APBH_BASE + HW_APBH_CTRL0);
147 while (__raw_readl(REGS_APBH_BASE + HW_APBH_CTRL0) &
148 (chbit << BP_APBH_CTRL0_RESET_CHANNEL))
149 cpu_relax();
150 break;
151
152 case STMP3XXX_BUS_APBX:
153 stmp3xxx_setl(chbit << BP_APBX_CTRL0_RESET_CHANNEL,
154 REGS_APBX_BASE + HW_APBX_CTRL0);
155 while (__raw_readl(REGS_APBX_BASE + HW_APBX_CTRL0) &
156 (chbit << BP_APBX_CTRL0_RESET_CHANNEL))
157 cpu_relax();
158 break;
159 }
160}
161EXPORT_SYMBOL(stmp3xxx_arch_dma_reset_channel);
162
163void stmp3xxx_arch_dma_freeze(int channel)
164{
165 unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
166
167 switch (STMP3XXX_DMA_BUS(channel)) {
168 case STMP3XXX_BUS_APBH:
169 stmp3xxx_setl(1 << chbit, REGS_APBH_BASE + HW_APBH_CTRL0);
170 break;
171 case STMP3XXX_BUS_APBX:
172 stmp3xxx_setl(1 << chbit, REGS_APBH_BASE + HW_APBH_CTRL0);
173 break;
174 }
175}
176EXPORT_SYMBOL(stmp3xxx_arch_dma_freeze);
177
178void stmp3xxx_arch_dma_unfreeze(int channel)
179{
180 unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
181
182 switch (STMP3XXX_DMA_BUS(channel)) {
183 case STMP3XXX_BUS_APBH:
184 stmp3xxx_clearl(1 << chbit, REGS_APBH_BASE + HW_APBH_CTRL0);
185 break;
186 case STMP3XXX_BUS_APBX:
187 stmp3xxx_clearl(1 << chbit, REGS_APBH_BASE + HW_APBH_CTRL0);
188 break;
189 }
190}
191EXPORT_SYMBOL(stmp3xxx_arch_dma_unfreeze);
192
193/*
194 * The registers are all very closely mapped, so we might as well map them all
195 * with a single mapping
196 *
197 * Logical Physical
198 * f0000000 80000000 On-chip registers
199 * f1000000 00000000 32k on-chip SRAM
200 */
201static struct map_desc stmp37xx_io_desc[] __initdata = {
202 {
203 .virtual = (u32)STMP3XXX_REGS_BASE,
204 .pfn = __phys_to_pfn(STMP3XXX_REGS_PHBASE),
205 .length = SZ_1M,
206 .type = MT_DEVICE
207 },
208 {
209 .virtual = (u32)STMP3XXX_OCRAM_BASE,
210 .pfn = __phys_to_pfn(STMP3XXX_OCRAM_PHBASE),
211 .length = STMP3XXX_OCRAM_SIZE,
212 .type = MT_DEVICE,
213 },
214};
215
216void __init stmp37xx_map_io(void)
217{
218 iotable_init(stmp37xx_io_desc, ARRAY_SIZE(stmp37xx_io_desc));
219}
diff --git a/arch/arm/mach-stmp37xx/stmp37xx.h b/arch/arm/mach-stmp37xx/stmp37xx.h
deleted file mode 100644
index 0b75fb796a64..000000000000
--- a/arch/arm/mach-stmp37xx/stmp37xx.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * Freescale STMP37XX/STMP378X internal functions and data declarations
3 *
4 * Embedded Alley Solutions, Inc <source@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#ifndef __MACH_STMP37XX_H
19#define __MACH_STMP37XX_H
20
21void stmp37xx_map_io(void);
22void stmp37xx_init_irq(void);
23
24#endif /* __MACH_STMP37XX_H */
diff --git a/arch/arm/mach-stmp37xx/stmp37xx_devb.c b/arch/arm/mach-stmp37xx/stmp37xx_devb.c
deleted file mode 100644
index 311d8552d362..000000000000
--- a/arch/arm/mach-stmp37xx/stmp37xx_devb.c
+++ /dev/null
@@ -1,99 +0,0 @@
1/*
2 * Freescale STMP37XX development board support
3 *
4 * Embedded Alley Solutions, Inc <source@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/device.h>
21#include <linux/platform_device.h>
22#include <asm/setup.h>
23#include <asm/mach-types.h>
24#include <asm/mach/arch.h>
25
26#include <mach/stmp3xxx.h>
27#include <mach/pins.h>
28#include <mach/pinmux.h>
29#include "stmp37xx.h"
30
31/*
32 * List of STMP37xx development board specific devices
33 */
34static struct platform_device *stmp37xx_devb_devices[] = {
35 &stmp3xxx_dbguart,
36 &stmp3xxx_appuart,
37};
38
39static struct pin_desc dbguart_pins_0[] = {
40 { PINID_PWM0, PIN_FUN3, },
41 { PINID_PWM1, PIN_FUN3, },
42};
43
44struct pin_desc appuart_pins_0[] = {
45 { PINID_UART2_CTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
46 { PINID_UART2_RTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
47 { PINID_UART2_RX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
48 { PINID_UART2_TX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
49};
50
51static struct pin_group appuart_pins[] = {
52 [0] = {
53 .pins = appuart_pins_0,
54 .nr_pins = ARRAY_SIZE(appuart_pins_0),
55 },
56 /* 37xx has the only app uart */
57};
58
59static struct pin_group dbguart_pins[] = {
60 [0] = {
61 .pins = dbguart_pins_0,
62 .nr_pins = ARRAY_SIZE(dbguart_pins_0),
63 },
64};
65
66static int dbguart_pins_control(int id, int request)
67{
68 int r = 0;
69
70 if (request)
71 r = stmp3xxx_request_pin_group(&dbguart_pins[id], "debug uart");
72 else
73 stmp3xxx_release_pin_group(&dbguart_pins[id], "debug uart");
74 return r;
75}
76
77
78static void __init stmp37xx_devb_init(void)
79{
80 stmp3xxx_pinmux_init(NR_REAL_IRQS);
81
82 /* Init STMP3xxx platform */
83 stmp3xxx_init();
84
85 stmp3xxx_dbguart.dev.platform_data = dbguart_pins_control;
86 stmp3xxx_appuart.dev.platform_data = appuart_pins;
87
88 /* Add STMP37xx development board devices */
89 platform_add_devices(stmp37xx_devb_devices,
90 ARRAY_SIZE(stmp37xx_devb_devices));
91}
92
93MACHINE_START(STMP37XX, "STMP37XX")
94 .boot_params = 0x40000100,
95 .map_io = stmp37xx_map_io,
96 .init_irq = stmp37xx_init_irq,
97 .timer = &stmp3xxx_timer,
98 .init_machine = stmp37xx_devb_init,
99MACHINE_END
diff --git a/arch/arm/mach-tegra/include/mach/smp.h b/arch/arm/mach-tegra/include/mach/smp.h
deleted file mode 100644
index c8221b38ee7c..000000000000
--- a/arch/arm/mach-tegra/include/mach/smp.h
+++ /dev/null
@@ -1,14 +0,0 @@
1#ifndef ASMARM_ARCH_SMP_H
2#define ASMARM_ARCH_SMP_H
3
4#include <asm/hardware/gic.h>
5
6/*
7 * We use IRQ1 as the IPI
8 */
9static inline void smp_cross_call(const struct cpumask *mask, int ipi)
10{
11 gic_raise_softirq(mask, ipi);
12}
13
14#endif
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index ec1f68924edf..b8ae3c978dee 100644
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -20,6 +20,7 @@
20#include <linux/io.h> 20#include <linux/io.h>
21 21
22#include <asm/cacheflush.h> 22#include <asm/cacheflush.h>
23#include <asm/hardware/gic.h>
23#include <mach/hardware.h> 24#include <mach/hardware.h>
24#include <asm/mach-types.h> 25#include <asm/mach-types.h>
25#include <asm/smp_scu.h> 26#include <asm/smp_scu.h>
@@ -122,6 +123,8 @@ void __init smp_init_cpus(void)
122 123
123 for (i = 0; i < ncores; i++) 124 for (i = 0; i < ncores; i++)
124 cpu_set(i, cpu_possible_map); 125 cpu_set(i, cpu_possible_map);
126
127 set_smp_cross_call(gic_raise_softirq);
125} 128}
126 129
127void __init platform_smp_prepare_cpus(unsigned int max_cpus) 130void __init platform_smp_prepare_cpus(unsigned int max_cpus)
diff --git a/arch/arm/mach-ux500/include/mach/smp.h b/arch/arm/mach-ux500/include/mach/smp.h
deleted file mode 100644
index ca2b15b1b3b1..000000000000
--- a/arch/arm/mach-ux500/include/mach/smp.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * This file is based ARM realview platform.
3 * Copyright (C) ARM Limited.
4 *
5 * This file is licensed under the terms of the GNU General Public
6 * License version 2. This program is licensed "as is" without any
7 * warranty of any kind, whether express or implied.
8 */
9#ifndef ASMARM_ARCH_SMP_H
10#define ASMARM_ARCH_SMP_H
11
12#include <asm/hardware/gic.h>
13
14/* This is required to wakeup the secondary core */
15extern void u8500_secondary_startup(void);
16
17/*
18 * We use IRQ1 as the IPI
19 */
20static inline void smp_cross_call(const struct cpumask *mask, int ipi)
21{
22 gic_raise_softirq(mask, ipi);
23}
24#endif
diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c
index 4fff4d408417..0c527fe2cebb 100644
--- a/arch/arm/mach-ux500/platsmp.c
+++ b/arch/arm/mach-ux500/platsmp.c
@@ -18,10 +18,14 @@
18#include <linux/io.h> 18#include <linux/io.h>
19 19
20#include <asm/cacheflush.h> 20#include <asm/cacheflush.h>
21#include <asm/hardware/gic.h>
21#include <asm/smp_scu.h> 22#include <asm/smp_scu.h>
22#include <mach/hardware.h> 23#include <mach/hardware.h>
23#include <mach/setup.h> 24#include <mach/setup.h>
24 25
26/* This is called from headsmp.S to wakeup the secondary core */
27extern void u8500_secondary_startup(void);
28
25/* 29/*
26 * control for which core is the next to come out of the secondary 30 * control for which core is the next to come out of the secondary
27 * boot "holding pen" 31 * boot "holding pen"
@@ -94,7 +98,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
94 */ 98 */
95 write_pen_release(cpu); 99 write_pen_release(cpu);
96 100
97 smp_cross_call(cpumask_of(cpu), 1); 101 gic_raise_softirq(cpumask_of(cpu), 1);
98 102
99 timeout = jiffies + (1 * HZ); 103 timeout = jiffies + (1 * HZ);
100 while (time_before(jiffies, timeout)) { 104 while (time_before(jiffies, timeout)) {
@@ -162,6 +166,8 @@ void __init smp_init_cpus(void)
162 166
163 for (i = 0; i < ncores; i++) 167 for (i = 0; i < ncores; i++)
164 set_cpu_possible(i, true); 168 set_cpu_possible(i, true);
169
170 set_smp_cross_call(gic_raise_softirq);
165} 171}
166 172
167void __init platform_smp_prepare_cpus(unsigned int max_cpus) 173void __init platform_smp_prepare_cpus(unsigned int max_cpus)
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index 4e78c379c5c6..0c99cf076c63 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -32,6 +32,7 @@
32#include <linux/io.h> 32#include <linux/io.h>
33#include <linux/gfp.h> 33#include <linux/gfp.h>
34#include <linux/clkdev.h> 34#include <linux/clkdev.h>
35#include <linux/mtd/physmap.h>
35 36
36#include <asm/system.h> 37#include <asm/system.h>
37#include <asm/irq.h> 38#include <asm/irq.h>
@@ -42,7 +43,6 @@
42#include <asm/mach-types.h> 43#include <asm/mach-types.h>
43 44
44#include <asm/mach/arch.h> 45#include <asm/mach/arch.h>
45#include <asm/mach/flash.h>
46#include <asm/mach/irq.h> 46#include <asm/mach/irq.h>
47#include <asm/mach/time.h> 47#include <asm/mach/time.h>
48#include <asm/mach/map.h> 48#include <asm/mach/map.h>
@@ -190,27 +190,7 @@ void __init versatile_map_io(void)
190 190
191#define VERSATILE_FLASHCTRL (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET) 191#define VERSATILE_FLASHCTRL (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET)
192 192
193static int versatile_flash_init(void) 193static void versatile_flash_set_vpp(struct platform_device *pdev, int on)
194{
195 u32 val;
196
197 val = __raw_readl(VERSATILE_FLASHCTRL);
198 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
199 __raw_writel(val, VERSATILE_FLASHCTRL);
200
201 return 0;
202}
203
204static void versatile_flash_exit(void)
205{
206 u32 val;
207
208 val = __raw_readl(VERSATILE_FLASHCTRL);
209 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
210 __raw_writel(val, VERSATILE_FLASHCTRL);
211}
212
213static void versatile_flash_set_vpp(int on)
214{ 194{
215 u32 val; 195 u32 val;
216 196
@@ -222,11 +202,8 @@ static void versatile_flash_set_vpp(int on)
222 __raw_writel(val, VERSATILE_FLASHCTRL); 202 __raw_writel(val, VERSATILE_FLASHCTRL);
223} 203}
224 204
225static struct flash_platform_data versatile_flash_data = { 205static struct physmap_flash_data versatile_flash_data = {
226 .map_name = "cfi_probe",
227 .width = 4, 206 .width = 4,
228 .init = versatile_flash_init,
229 .exit = versatile_flash_exit,
230 .set_vpp = versatile_flash_set_vpp, 207 .set_vpp = versatile_flash_set_vpp,
231}; 208};
232 209
@@ -237,7 +214,7 @@ static struct resource versatile_flash_resource = {
237}; 214};
238 215
239static struct platform_device versatile_flash_device = { 216static struct platform_device versatile_flash_device = {
240 .name = "armflash", 217 .name = "physmap-flash",
241 .id = 0, 218 .id = 0,
242 .dev = { 219 .dev = {
243 .platform_data = &versatile_flash_data, 220 .platform_data = &versatile_flash_data,
diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c
index 2023a9e5211c..765a71ff7f3b 100644
--- a/arch/arm/mach-vexpress/ct-ca9x4.c
+++ b/arch/arm/mach-vexpress/ct-ca9x4.c
@@ -223,6 +223,8 @@ static void ct_ca9x4_init_cpu_map(void)
223 223
224 for (i = 0; i < ncores; ++i) 224 for (i = 0; i < ncores; ++i)
225 set_cpu_possible(i, true); 225 set_cpu_possible(i, true);
226
227 set_smp_cross_call(gic_raise_softirq);
226} 228}
227 229
228static void ct_ca9x4_smp_enable(unsigned int max_cpus) 230static void ct_ca9x4_smp_enable(unsigned int max_cpus)
diff --git a/arch/arm/mach-vexpress/include/mach/smp.h b/arch/arm/mach-vexpress/include/mach/smp.h
deleted file mode 100644
index 4c05e4a9713a..000000000000
--- a/arch/arm/mach-vexpress/include/mach/smp.h
+++ /dev/null
@@ -1,13 +0,0 @@
1#ifndef __MACH_SMP_H
2#define __MACH_SMP_H
3
4#include <asm/hardware/gic.h>
5
6/*
7 * We use IRQ1 as the IPI
8 */
9static inline void smp_cross_call(const struct cpumask *mask, int ipi)
10{
11 gic_raise_softirq(mask, ipi);
12}
13#endif
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index 9d9d4af384e2..285edcd2da2a 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -13,11 +13,11 @@
13#include <linux/sysdev.h> 13#include <linux/sysdev.h>
14#include <linux/usb/isp1760.h> 14#include <linux/usb/isp1760.h>
15#include <linux/clkdev.h> 15#include <linux/clkdev.h>
16#include <linux/mtd/physmap.h>
16 17
17#include <asm/mach-types.h> 18#include <asm/mach-types.h>
18#include <asm/sizes.h> 19#include <asm/sizes.h>
19#include <asm/mach/arch.h> 20#include <asm/mach/arch.h>
20#include <asm/mach/flash.h>
21#include <asm/mach/map.h> 21#include <asm/mach/map.h>
22#include <asm/mach/time.h> 22#include <asm/mach/time.h>
23#include <asm/hardware/arm_timer.h> 23#include <asm/hardware/arm_timer.h>
@@ -207,27 +207,13 @@ static struct platform_device v2m_usb_device = {
207 .dev.platform_data = &v2m_usb_config, 207 .dev.platform_data = &v2m_usb_config,
208}; 208};
209 209
210static int v2m_flash_init(void) 210static void v2m_flash_set_vpp(struct platform_device *pdev, int on)
211{
212 writel(0, MMIO_P2V(V2M_SYS_FLASH));
213 return 0;
214}
215
216static void v2m_flash_exit(void)
217{
218 writel(0, MMIO_P2V(V2M_SYS_FLASH));
219}
220
221static void v2m_flash_set_vpp(int on)
222{ 211{
223 writel(on != 0, MMIO_P2V(V2M_SYS_FLASH)); 212 writel(on != 0, MMIO_P2V(V2M_SYS_FLASH));
224} 213}
225 214
226static struct flash_platform_data v2m_flash_data = { 215static struct physmap_flash_data v2m_flash_data = {
227 .map_name = "cfi_probe",
228 .width = 4, 216 .width = 4,
229 .init = v2m_flash_init,
230 .exit = v2m_flash_exit,
231 .set_vpp = v2m_flash_set_vpp, 217 .set_vpp = v2m_flash_set_vpp,
232}; 218};
233 219
@@ -244,7 +230,7 @@ static struct resource v2m_flash_resources[] = {
244}; 230};
245 231
246static struct platform_device v2m_flash_device = { 232static struct platform_device v2m_flash_device = {
247 .name = "armflash", 233 .name = "physmap-flash",
248 .id = -1, 234 .id = -1,
249 .resource = v2m_flash_resources, 235 .resource = v2m_flash_resources,
250 .num_resources = ARRAY_SIZE(v2m_flash_resources), 236 .num_resources = ARRAY_SIZE(v2m_flash_resources),
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index e591513bb53e..76f82ae44efb 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -201,6 +201,20 @@ static void __init arm_bootmem_init(unsigned long start_pfn,
201 } 201 }
202} 202}
203 203
204#ifdef CONFIG_ZONE_DMA
205static void __init arm_adjust_dma_zone(unsigned long *size, unsigned long *hole,
206 unsigned long dma_size)
207{
208 if (size[0] <= dma_size)
209 return;
210
211 size[ZONE_NORMAL] = size[0] - dma_size;
212 size[ZONE_DMA] = dma_size;
213 hole[ZONE_NORMAL] = hole[0];
214 hole[ZONE_DMA] = 0;
215}
216#endif
217
204static void __init arm_bootmem_free(unsigned long min, unsigned long max_low, 218static void __init arm_bootmem_free(unsigned long min, unsigned long max_low,
205 unsigned long max_high) 219 unsigned long max_high)
206{ 220{
@@ -243,11 +257,18 @@ static void __init arm_bootmem_free(unsigned long min, unsigned long max_low,
243#endif 257#endif
244 } 258 }
245 259
260#ifdef ARM_DMA_ZONE_SIZE
261#ifndef CONFIG_ZONE_DMA
262#error ARM_DMA_ZONE_SIZE set but no DMA zone to limit allocations
263#endif
264
246 /* 265 /*
247 * Adjust the sizes according to any special requirements for 266 * Adjust the sizes according to any special requirements for
248 * this machine type. 267 * this machine type.
249 */ 268 */
250 arch_adjust_zones(zone_size, zhole_size); 269 arm_adjust_dma_zone(zone_size, zhole_size,
270 ARM_DMA_ZONE_SIZE >> PAGE_SHIFT);
271#endif
251 272
252 free_area_init_node(0, zone_size, min, zhole_size); 273 free_area_init_node(0, zone_size, min, zhole_size);
253} 274}
diff --git a/arch/arm/plat-omap/include/plat/flash.h b/arch/arm/plat-omap/include/plat/flash.h
index 3e6327016b40..3083195123ea 100644
--- a/arch/arm/plat-omap/include/plat/flash.h
+++ b/arch/arm/plat-omap/include/plat/flash.h
@@ -11,6 +11,6 @@
11 11
12#include <linux/mtd/map.h> 12#include <linux/mtd/map.h>
13 13
14extern void omap1_set_vpp(struct map_info *map, int enable); 14extern void omap1_set_vpp(struct platform_device *pdev, int enable);
15 15
16#endif 16#endif
diff --git a/arch/arm/plat-omap/include/plat/smp.h b/arch/arm/plat-omap/include/plat/smp.h
deleted file mode 100644
index 7a10257909ef..000000000000
--- a/arch/arm/plat-omap/include/plat/smp.h
+++ /dev/null
@@ -1,36 +0,0 @@
1/*
2 * OMAP4 machine specific smp.h
3 *
4 * Copyright (C) 2009 Texas Instruments, Inc.
5 *
6 * Author:
7 * Santosh Shilimkar <santosh.shilimkar@ti.com>
8 *
9 * Interface functions needed for the SMP. This file is based on arm
10 * realview smp platform.
11 * Copyright (c) 2003 ARM Limited.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17#ifndef OMAP_ARCH_SMP_H
18#define OMAP_ARCH_SMP_H
19
20#include <asm/hardware/gic.h>
21
22/* Needed for secondary core boot */
23extern void omap_secondary_startup(void);
24extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
25extern void omap_auxcoreboot_addr(u32 cpu_addr);
26extern u32 omap_read_auxcoreboot0(void);
27
28/*
29 * We use Soft IRQ1 as the IPI
30 */
31static inline void smp_cross_call(const struct cpumask *mask, int ipi)
32{
33 gic_raise_softirq(mask, ipi);
34}
35
36#endif
diff --git a/arch/arm/plat-stmp3xxx/Kconfig b/arch/arm/plat-stmp3xxx/Kconfig
deleted file mode 100644
index 2cf37c35951b..000000000000
--- a/arch/arm/plat-stmp3xxx/Kconfig
+++ /dev/null
@@ -1,37 +0,0 @@
1if ARCH_STMP3XXX
2
3menu "Freescale STMP3xxx implementations"
4
5choice
6 prompt "Select STMP3xxx chip family"
7
8config ARCH_STMP37XX
9 bool "Freescale SMTP37xx"
10 select CPU_ARM926T
11 ---help---
12 STMP37xx refers to 3700 through 3769 chips
13
14config ARCH_STMP378X
15 bool "Freescale STMP378x"
16 select CPU_ARM926T
17 ---help---
18 STMP378x refers to 3780 through 3789 chips
19
20endchoice
21
22choice
23 prompt "Select STMP3xxx board type"
24
25config MACH_STMP37XX
26 depends on ARCH_STMP37XX
27 bool "Freescale STMP37xx development board"
28
29config MACH_STMP378X
30 depends on ARCH_STMP378X
31 bool "Freescale STMP378x development board"
32
33endchoice
34
35endmenu
36
37endif
diff --git a/arch/arm/plat-stmp3xxx/Makefile b/arch/arm/plat-stmp3xxx/Makefile
deleted file mode 100644
index 31dd518f37a5..000000000000
--- a/arch/arm/plat-stmp3xxx/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
1#
2# Makefile for the linux kernel.
3#
4# Object file lists.
5obj-y += core.o timer.o irq.o dma.o clock.o pinmux.o devices.o
diff --git a/arch/arm/plat-stmp3xxx/clock.c b/arch/arm/plat-stmp3xxx/clock.c
deleted file mode 100644
index 2e712e17ce72..000000000000
--- a/arch/arm/plat-stmp3xxx/clock.c
+++ /dev/null
@@ -1,1134 +0,0 @@
1/*
2 * Clock manipulation routines for Freescale STMP37XX/STMP378X
3 *
4 * Author: Vitaly Wool <vital@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#define DEBUG
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/init.h>
22#include <linux/clk.h>
23#include <linux/spinlock.h>
24#include <linux/errno.h>
25#include <linux/err.h>
26#include <linux/delay.h>
27#include <linux/io.h>
28#include <linux/clkdev.h>
29
30#include <asm/mach-types.h>
31#include <mach/platform.h>
32#include <mach/regs-clkctrl.h>
33
34#include "clock.h"
35
36static DEFINE_SPINLOCK(clocks_lock);
37
38static struct clk osc_24M;
39static struct clk pll_clk;
40static struct clk cpu_clk;
41static struct clk hclk;
42
43static int propagate_rate(struct clk *);
44
45static inline int clk_is_busy(struct clk *clk)
46{
47 return __raw_readl(clk->busy_reg) & (1 << clk->busy_bit);
48}
49
50static inline int clk_good(struct clk *clk)
51{
52 return clk && !IS_ERR(clk) && clk->ops;
53}
54
55static int std_clk_enable(struct clk *clk)
56{
57 if (clk->enable_reg) {
58 u32 clk_reg = __raw_readl(clk->enable_reg);
59 if (clk->enable_negate)
60 clk_reg &= ~(1 << clk->enable_shift);
61 else
62 clk_reg |= (1 << clk->enable_shift);
63 __raw_writel(clk_reg, clk->enable_reg);
64 if (clk->enable_wait)
65 udelay(clk->enable_wait);
66 return 0;
67 } else
68 return -EINVAL;
69}
70
71static int std_clk_disable(struct clk *clk)
72{
73 if (clk->enable_reg) {
74 u32 clk_reg = __raw_readl(clk->enable_reg);
75 if (clk->enable_negate)
76 clk_reg |= (1 << clk->enable_shift);
77 else
78 clk_reg &= ~(1 << clk->enable_shift);
79 __raw_writel(clk_reg, clk->enable_reg);
80 return 0;
81 } else
82 return -EINVAL;
83}
84
85static int io_set_rate(struct clk *clk, u32 rate)
86{
87 u32 reg_frac, clkctrl_frac;
88 int i, ret = 0, mask = 0x1f;
89
90 clkctrl_frac = (clk->parent->rate * 18 + rate - 1) / rate;
91
92 if (clkctrl_frac < 18 || clkctrl_frac > 35) {
93 ret = -EINVAL;
94 goto out;
95 }
96
97 reg_frac = __raw_readl(clk->scale_reg);
98 reg_frac &= ~(mask << clk->scale_shift);
99 __raw_writel(reg_frac | (clkctrl_frac << clk->scale_shift),
100 clk->scale_reg);
101 if (clk->busy_reg) {
102 for (i = 10000; i; i--)
103 if (!clk_is_busy(clk))
104 break;
105 if (!i)
106 ret = -ETIMEDOUT;
107 else
108 ret = 0;
109 }
110out:
111 return ret;
112}
113
114static long io_get_rate(struct clk *clk)
115{
116 long rate = clk->parent->rate * 18;
117 int mask = 0x1f;
118
119 rate /= (__raw_readl(clk->scale_reg) >> clk->scale_shift) & mask;
120 clk->rate = rate;
121
122 return rate;
123}
124
125static long per_get_rate(struct clk *clk)
126{
127 long rate = clk->parent->rate;
128 long div;
129 const int mask = 0xff;
130
131 if (clk->enable_reg &&
132 !(__raw_readl(clk->enable_reg) & clk->enable_shift))
133 clk->rate = 0;
134 else {
135 div = (__raw_readl(clk->scale_reg) >> clk->scale_shift) & mask;
136 if (div)
137 rate /= div;
138 clk->rate = rate;
139 }
140
141 return clk->rate;
142}
143
144static int per_set_rate(struct clk *clk, u32 rate)
145{
146 int ret = -EINVAL;
147 int div = (clk->parent->rate + rate - 1) / rate;
148 u32 reg_frac;
149 const int mask = 0xff;
150 int try = 10;
151 int i = -1;
152
153 if (div == 0 || div > mask)
154 goto out;
155
156 reg_frac = __raw_readl(clk->scale_reg);
157 reg_frac &= ~(mask << clk->scale_shift);
158
159 while (try--) {
160 __raw_writel(reg_frac | (div << clk->scale_shift),
161 clk->scale_reg);
162
163 if (clk->busy_reg) {
164 for (i = 10000; i; i--)
165 if (!clk_is_busy(clk))
166 break;
167 }
168 if (i)
169 break;
170 }
171
172 if (!i)
173 ret = -ETIMEDOUT;
174 else
175 ret = 0;
176
177out:
178 if (ret != 0)
179 printk(KERN_ERR "%s: error %d\n", __func__, ret);
180 return ret;
181}
182
183static long lcdif_get_rate(struct clk *clk)
184{
185 long rate = clk->parent->rate;
186 long div;
187 const int mask = 0xff;
188
189 div = (__raw_readl(clk->scale_reg) >> clk->scale_shift) & mask;
190 if (div) {
191 rate /= div;
192 div = (__raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC) &
193 BM_CLKCTRL_FRAC_PIXFRAC) >> BP_CLKCTRL_FRAC_PIXFRAC;
194 rate /= div;
195 }
196 clk->rate = rate;
197
198 return rate;
199}
200
201static int lcdif_set_rate(struct clk *clk, u32 rate)
202{
203 int ret = 0;
204 /*
205 * On 3700, we can get most timings exact by modifying ref_pix
206 * and the divider, but keeping the phase timings at 1 (2
207 * phases per cycle).
208 *
209 * ref_pix can be between 480e6*18/35=246.9MHz and 480e6*18/18=480MHz,
210 * which is between 18/(18*480e6)=2.084ns and 35/(18*480e6)=4.050ns.
211 *
212 * ns_cycle >= 2*18e3/(18*480) = 25/6
213 * ns_cycle <= 2*35e3/(18*480) = 875/108
214 *
215 * Multiply the ns_cycle by 'div' to lengthen it until it fits the
216 * bounds. This is the divider we'll use after ref_pix.
217 *
218 * 6 * ns_cycle >= 25 * div
219 * 108 * ns_cycle <= 875 * div
220 */
221 u32 ns_cycle = 1000000 / rate;
222 u32 div, reg_val;
223 u32 lowest_result = (u32) -1;
224 u32 lowest_div = 0, lowest_fracdiv = 0;
225
226 for (div = 1; div < 256; ++div) {
227 u32 fracdiv;
228 u32 ps_result;
229 int lower_bound = 6 * ns_cycle >= 25 * div;
230 int upper_bound = 108 * ns_cycle <= 875 * div;
231 if (!lower_bound)
232 break;
233 if (!upper_bound)
234 continue;
235 /*
236 * Found a matching div. Calculate fractional divider needed,
237 * rounded up.
238 */
239 fracdiv = ((clk->parent->rate / 1000 * 18 / 2) *
240 ns_cycle + 1000 * div - 1) /
241 (1000 * div);
242 if (fracdiv < 18 || fracdiv > 35) {
243 ret = -EINVAL;
244 goto out;
245 }
246 /* Calculate the actual cycle time this results in */
247 ps_result = 6250 * div * fracdiv / 27;
248
249 /* Use the fastest result that doesn't break ns_cycle */
250 if (ps_result <= lowest_result) {
251 lowest_result = ps_result;
252 lowest_div = div;
253 lowest_fracdiv = fracdiv;
254 }
255 }
256
257 if (div >= 256 || lowest_result == (u32) -1) {
258 ret = -EINVAL;
259 goto out;
260 }
261 pr_debug("Programming PFD=%u,DIV=%u ref_pix=%uMHz "
262 "PIXCLK=%uMHz cycle=%u.%03uns\n",
263 lowest_fracdiv, lowest_div,
264 480*18/lowest_fracdiv, 480*18/lowest_fracdiv/lowest_div,
265 lowest_result / 1000, lowest_result % 1000);
266
267 /* Program ref_pix phase fractional divider */
268 reg_val = __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC);
269 reg_val &= ~BM_CLKCTRL_FRAC_PIXFRAC;
270 reg_val |= BF(lowest_fracdiv, CLKCTRL_FRAC_PIXFRAC);
271 __raw_writel(reg_val, REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC);
272
273 /* Ungate PFD */
274 stmp3xxx_clearl(BM_CLKCTRL_FRAC_CLKGATEPIX,
275 REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC);
276
277 /* Program pix divider */
278 reg_val = __raw_readl(clk->scale_reg);
279 reg_val &= ~(BM_CLKCTRL_PIX_DIV | BM_CLKCTRL_PIX_CLKGATE);
280 reg_val |= BF(lowest_div, CLKCTRL_PIX_DIV);
281 __raw_writel(reg_val, clk->scale_reg);
282
283 /* Wait for divider update */
284 if (clk->busy_reg) {
285 int i;
286 for (i = 10000; i; i--)
287 if (!clk_is_busy(clk))
288 break;
289 if (!i) {
290 ret = -ETIMEDOUT;
291 goto out;
292 }
293 }
294
295 /* Switch to ref_pix source */
296 reg_val = __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ);
297 reg_val &= ~BM_CLKCTRL_CLKSEQ_BYPASS_PIX;
298 __raw_writel(reg_val, REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ);
299
300out:
301 return ret;
302}
303
304
305static int cpu_set_rate(struct clk *clk, u32 rate)
306{
307 u32 reg_val;
308
309 if (rate < 24000)
310 return -EINVAL;
311 else if (rate == 24000) {
312 /* switch to the 24M source */
313 clk_set_parent(clk, &osc_24M);
314 } else {
315 int i;
316 u32 clkctrl_cpu = 1;
317 u32 c = clkctrl_cpu;
318 u32 clkctrl_frac = 1;
319 u32 val;
320 for ( ; c < 0x40; c++) {
321 u32 f = (pll_clk.rate*18/c + rate/2) / rate;
322 int s1, s2;
323
324 if (f < 18 || f > 35)
325 continue;
326 s1 = pll_clk.rate*18/clkctrl_frac/clkctrl_cpu - rate;
327 s2 = pll_clk.rate*18/c/f - rate;
328 pr_debug("%s: s1 %d, s2 %d\n", __func__, s1, s2);
329 if (abs(s1) > abs(s2)) {
330 clkctrl_cpu = c;
331 clkctrl_frac = f;
332 }
333 if (s2 == 0)
334 break;
335 };
336 pr_debug("%s: clkctrl_cpu %d, clkctrl_frac %d\n", __func__,
337 clkctrl_cpu, clkctrl_frac);
338 if (c == 0x40) {
339 int d = pll_clk.rate*18/clkctrl_frac/clkctrl_cpu -
340 rate;
341 if (abs(d) > 100 ||
342 clkctrl_frac < 18 || clkctrl_frac > 35)
343 return -EINVAL;
344 }
345
346 /* 4.6.2 */
347 val = __raw_readl(clk->scale_reg);
348 val &= ~(0x3f << clk->scale_shift);
349 val |= clkctrl_frac;
350 clk_set_parent(clk, &osc_24M);
351 udelay(10);
352 __raw_writel(val, clk->scale_reg);
353 /* ungate */
354 __raw_writel(1<<7, clk->scale_reg + 8);
355 /* write clkctrl_cpu */
356 clk->saved_div = clkctrl_cpu;
357
358 reg_val = __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU);
359 reg_val &= ~0x3F;
360 reg_val |= clkctrl_cpu;
361 __raw_writel(reg_val, REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU);
362
363 for (i = 10000; i; i--)
364 if (!clk_is_busy(clk))
365 break;
366 if (!i) {
367 printk(KERN_ERR "couldn't set up CPU divisor\n");
368 return -ETIMEDOUT;
369 }
370 clk_set_parent(clk, &pll_clk);
371 clk->saved_div = 0;
372 udelay(10);
373 }
374 return 0;
375}
376
377static long cpu_get_rate(struct clk *clk)
378{
379 long rate = clk->parent->rate * 18;
380
381 rate /= (__raw_readl(clk->scale_reg) >> clk->scale_shift) & 0x3f;
382 rate /= __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU) & 0x3f;
383 rate = ((rate + 9) / 10) * 10;
384 clk->rate = rate;
385
386 return rate;
387}
388
389static long cpu_round_rate(struct clk *clk, u32 rate)
390{
391 unsigned long r = 0;
392
393 if (rate <= 24000)
394 r = 24000;
395 else {
396 u32 clkctrl_cpu = 1;
397 u32 clkctrl_frac;
398 do {
399 clkctrl_frac =
400 (pll_clk.rate*18 / clkctrl_cpu + rate/2) / rate;
401 if (clkctrl_frac > 35)
402 continue;
403 if (pll_clk.rate*18 / clkctrl_frac / clkctrl_cpu/10 ==
404 rate / 10)
405 break;
406 } while (pll_clk.rate / 2 >= clkctrl_cpu++ * rate);
407 if (pll_clk.rate / 2 < (clkctrl_cpu - 1) * rate)
408 clkctrl_cpu--;
409 pr_debug("%s: clkctrl_cpu %d, clkctrl_frac %d\n", __func__,
410 clkctrl_cpu, clkctrl_frac);
411 if (clkctrl_frac < 18)
412 clkctrl_frac = 18;
413 if (clkctrl_frac > 35)
414 clkctrl_frac = 35;
415
416 r = pll_clk.rate * 18;
417 r /= clkctrl_frac;
418 r /= clkctrl_cpu;
419 r = 10 * ((r + 9) / 10);
420 }
421 return r;
422}
423
424static long emi_get_rate(struct clk *clk)
425{
426 long rate = clk->parent->rate * 18;
427
428 rate /= (__raw_readl(clk->scale_reg) >> clk->scale_shift) & 0x3f;
429 rate /= __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_EMI) & 0x3f;
430 clk->rate = rate;
431
432 return rate;
433}
434
435static int clkseq_set_parent(struct clk *clk, struct clk *parent)
436{
437 int ret = -EINVAL;
438 int shift = 8;
439
440 /* bypass? */
441 if (parent == &osc_24M)
442 shift = 4;
443
444 if (clk->bypass_reg) {
445#ifdef CONFIG_ARCH_STMP378X
446 u32 hbus_val, cpu_val;
447
448 if (clk == &cpu_clk && shift == 4) {
449 hbus_val = __raw_readl(REGS_CLKCTRL_BASE +
450 HW_CLKCTRL_HBUS);
451 cpu_val = __raw_readl(REGS_CLKCTRL_BASE +
452 HW_CLKCTRL_CPU);
453
454 hbus_val &= ~(BM_CLKCTRL_HBUS_DIV_FRAC_EN |
455 BM_CLKCTRL_HBUS_DIV);
456 clk->saved_div = cpu_val & BM_CLKCTRL_CPU_DIV_CPU;
457 cpu_val &= ~BM_CLKCTRL_CPU_DIV_CPU;
458 cpu_val |= 1;
459
460 if (machine_is_stmp378x()) {
461 __raw_writel(hbus_val,
462 REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS);
463 __raw_writel(cpu_val,
464 REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU);
465 hclk.rate = 0;
466 }
467 } else if (clk == &cpu_clk && shift == 8) {
468 hbus_val = __raw_readl(REGS_CLKCTRL_BASE +
469 HW_CLKCTRL_HBUS);
470 cpu_val = __raw_readl(REGS_CLKCTRL_BASE +
471 HW_CLKCTRL_CPU);
472 hbus_val &= ~(BM_CLKCTRL_HBUS_DIV_FRAC_EN |
473 BM_CLKCTRL_HBUS_DIV);
474 hbus_val |= 2;
475 cpu_val &= ~BM_CLKCTRL_CPU_DIV_CPU;
476 if (clk->saved_div)
477 cpu_val |= clk->saved_div;
478 else
479 cpu_val |= 2;
480
481 if (machine_is_stmp378x()) {
482 __raw_writel(hbus_val,
483 REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS);
484 __raw_writel(cpu_val,
485 REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU);
486 hclk.rate = 0;
487 }
488 }
489#endif
490 __raw_writel(1 << clk->bypass_shift, clk->bypass_reg + shift);
491
492 ret = 0;
493 }
494
495 return ret;
496}
497
498static int hbus_set_rate(struct clk *clk, u32 rate)
499{
500 u8 div = 0;
501 int is_frac = 0;
502 u32 clkctrl_hbus;
503 struct clk *parent = clk->parent;
504
505 pr_debug("%s: rate %d, parent rate %d\n", __func__, rate,
506 parent->rate);
507
508 if (rate > parent->rate)
509 return -EINVAL;
510
511 if (((parent->rate + rate/2) / rate) * rate != parent->rate &&
512 parent->rate / rate < 32) {
513 pr_debug("%s: switching to fractional mode\n", __func__);
514 is_frac = 1;
515 }
516
517 if (is_frac)
518 div = (32 * rate + parent->rate / 2) / parent->rate;
519 else
520 div = (parent->rate + rate - 1) / rate;
521 pr_debug("%s: div calculated is %d\n", __func__, div);
522 if (!div || div > 0x1f)
523 return -EINVAL;
524
525 clk_set_parent(&cpu_clk, &osc_24M);
526 udelay(10);
527 clkctrl_hbus = __raw_readl(clk->scale_reg);
528 clkctrl_hbus &= ~0x3f;
529 clkctrl_hbus |= div;
530 clkctrl_hbus |= (is_frac << 5);
531
532 __raw_writel(clkctrl_hbus, clk->scale_reg);
533 if (clk->busy_reg) {
534 int i;
535 for (i = 10000; i; i--)
536 if (!clk_is_busy(clk))
537 break;
538 if (!i) {
539 printk(KERN_ERR "couldn't set up CPU divisor\n");
540 return -ETIMEDOUT;
541 }
542 }
543 clk_set_parent(&cpu_clk, &pll_clk);
544 __raw_writel(clkctrl_hbus, clk->scale_reg);
545 udelay(10);
546 return 0;
547}
548
549static long hbus_get_rate(struct clk *clk)
550{
551 long rate = clk->parent->rate;
552
553 if (__raw_readl(clk->scale_reg) & 0x20) {
554 rate *= __raw_readl(clk->scale_reg) & 0x1f;
555 rate /= 32;
556 } else
557 rate /= __raw_readl(clk->scale_reg) & 0x1f;
558 clk->rate = rate;
559
560 return rate;
561}
562
563static int xbus_set_rate(struct clk *clk, u32 rate)
564{
565 u16 div = 0;
566 u32 clkctrl_xbus;
567
568 pr_debug("%s: rate %d, parent rate %d\n", __func__, rate,
569 clk->parent->rate);
570
571 div = (clk->parent->rate + rate - 1) / rate;
572 pr_debug("%s: div calculated is %d\n", __func__, div);
573 if (!div || div > 0x3ff)
574 return -EINVAL;
575
576 clkctrl_xbus = __raw_readl(clk->scale_reg);
577 clkctrl_xbus &= ~0x3ff;
578 clkctrl_xbus |= div;
579 __raw_writel(clkctrl_xbus, clk->scale_reg);
580 if (clk->busy_reg) {
581 int i;
582 for (i = 10000; i; i--)
583 if (!clk_is_busy(clk))
584 break;
585 if (!i) {
586 printk(KERN_ERR "couldn't set up xbus divisor\n");
587 return -ETIMEDOUT;
588 }
589 }
590 return 0;
591}
592
593static long xbus_get_rate(struct clk *clk)
594{
595 long rate = clk->parent->rate;
596
597 rate /= __raw_readl(clk->scale_reg) & 0x3ff;
598 clk->rate = rate;
599
600 return rate;
601}
602
603
604/* Clock ops */
605
606static struct clk_ops std_ops = {
607 .enable = std_clk_enable,
608 .disable = std_clk_disable,
609 .get_rate = per_get_rate,
610 .set_rate = per_set_rate,
611 .set_parent = clkseq_set_parent,
612};
613
614static struct clk_ops min_ops = {
615 .enable = std_clk_enable,
616 .disable = std_clk_disable,
617};
618
619static struct clk_ops cpu_ops = {
620 .enable = std_clk_enable,
621 .disable = std_clk_disable,
622 .get_rate = cpu_get_rate,
623 .set_rate = cpu_set_rate,
624 .round_rate = cpu_round_rate,
625 .set_parent = clkseq_set_parent,
626};
627
628static struct clk_ops io_ops = {
629 .enable = std_clk_enable,
630 .disable = std_clk_disable,
631 .get_rate = io_get_rate,
632 .set_rate = io_set_rate,
633};
634
635static struct clk_ops hbus_ops = {
636 .get_rate = hbus_get_rate,
637 .set_rate = hbus_set_rate,
638};
639
640static struct clk_ops xbus_ops = {
641 .get_rate = xbus_get_rate,
642 .set_rate = xbus_set_rate,
643};
644
645static struct clk_ops lcdif_ops = {
646 .enable = std_clk_enable,
647 .disable = std_clk_disable,
648 .get_rate = lcdif_get_rate,
649 .set_rate = lcdif_set_rate,
650 .set_parent = clkseq_set_parent,
651};
652
653static struct clk_ops emi_ops = {
654 .get_rate = emi_get_rate,
655};
656
657/* List of on-chip clocks */
658
659static struct clk osc_24M = {
660 .flags = FIXED_RATE | ENABLED,
661 .rate = 24000,
662};
663
664static struct clk pll_clk = {
665 .parent = &osc_24M,
666 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PLLCTRL0,
667 .enable_shift = 16,
668 .enable_wait = 10,
669 .flags = FIXED_RATE | ENABLED,
670 .rate = 480000,
671 .ops = &min_ops,
672};
673
674static struct clk cpu_clk = {
675 .parent = &pll_clk,
676 .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC,
677 .scale_shift = 0,
678 .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
679 .bypass_shift = 7,
680 .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU,
681 .busy_bit = 28,
682 .flags = RATE_PROPAGATES | ENABLED,
683 .ops = &cpu_ops,
684};
685
686static struct clk io_clk = {
687 .parent = &pll_clk,
688 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC,
689 .enable_shift = 31,
690 .enable_negate = 1,
691 .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC,
692 .scale_shift = 24,
693 .flags = RATE_PROPAGATES | ENABLED,
694 .ops = &io_ops,
695};
696
697static struct clk hclk = {
698 .parent = &cpu_clk,
699 .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS,
700 .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
701 .bypass_shift = 7,
702 .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS,
703 .busy_bit = 29,
704 .flags = RATE_PROPAGATES | ENABLED,
705 .ops = &hbus_ops,
706};
707
708static struct clk xclk = {
709 .parent = &osc_24M,
710 .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XBUS,
711 .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XBUS,
712 .busy_bit = 31,
713 .flags = RATE_PROPAGATES | ENABLED,
714 .ops = &xbus_ops,
715};
716
717static struct clk uart_clk = {
718 .parent = &xclk,
719 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL,
720 .enable_shift = 31,
721 .enable_negate = 1,
722 .flags = ENABLED,
723 .ops = &min_ops,
724};
725
726static struct clk audio_clk = {
727 .parent = &xclk,
728 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL,
729 .enable_shift = 30,
730 .enable_negate = 1,
731 .ops = &min_ops,
732};
733
734static struct clk pwm_clk = {
735 .parent = &xclk,
736 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL,
737 .enable_shift = 29,
738 .enable_negate = 1,
739 .ops = &min_ops,
740};
741
742static struct clk dri_clk = {
743 .parent = &xclk,
744 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL,
745 .enable_shift = 28,
746 .enable_negate = 1,
747 .ops = &min_ops,
748};
749
750static struct clk digctl_clk = {
751 .parent = &xclk,
752 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL,
753 .enable_shift = 27,
754 .enable_negate = 1,
755 .ops = &min_ops,
756};
757
758static struct clk timer_clk = {
759 .parent = &xclk,
760 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL,
761 .enable_shift = 26,
762 .enable_negate = 1,
763 .flags = ENABLED,
764 .ops = &min_ops,
765};
766
767static struct clk lcdif_clk = {
768 .parent = &pll_clk,
769 .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PIX,
770 .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PIX,
771 .busy_bit = 29,
772 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PIX,
773 .enable_shift = 31,
774 .enable_negate = 1,
775 .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
776 .bypass_shift = 1,
777 .flags = NEEDS_SET_PARENT,
778 .ops = &lcdif_ops,
779};
780
781static struct clk ssp_clk = {
782 .parent = &io_clk,
783 .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SSP,
784 .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SSP,
785 .busy_bit = 29,
786 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SSP,
787 .enable_shift = 31,
788 .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
789 .bypass_shift = 5,
790 .enable_negate = 1,
791 .flags = NEEDS_SET_PARENT,
792 .ops = &std_ops,
793};
794
795static struct clk gpmi_clk = {
796 .parent = &io_clk,
797 .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_GPMI,
798 .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_GPMI,
799 .busy_bit = 29,
800 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_GPMI,
801 .enable_shift = 31,
802 .enable_negate = 1,
803 .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
804 .bypass_shift = 4,
805 .flags = NEEDS_SET_PARENT,
806 .ops = &std_ops,
807};
808
809static struct clk spdif_clk = {
810 .parent = &pll_clk,
811 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SPDIF,
812 .enable_shift = 31,
813 .enable_negate = 1,
814 .ops = &min_ops,
815};
816
817static struct clk emi_clk = {
818 .parent = &pll_clk,
819 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_EMI,
820 .enable_shift = 31,
821 .enable_negate = 1,
822 .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC,
823 .scale_shift = 8,
824 .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_EMI,
825 .busy_bit = 28,
826 .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
827 .bypass_shift = 6,
828 .flags = ENABLED,
829 .ops = &emi_ops,
830};
831
832static struct clk ir_clk = {
833 .parent = &io_clk,
834 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_IR,
835 .enable_shift = 31,
836 .enable_negate = 1,
837 .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
838 .bypass_shift = 3,
839 .ops = &min_ops,
840};
841
842static struct clk saif_clk = {
843 .parent = &pll_clk,
844 .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SAIF,
845 .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SAIF,
846 .busy_bit = 29,
847 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SAIF,
848 .enable_shift = 31,
849 .enable_negate = 1,
850 .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
851 .bypass_shift = 0,
852 .ops = &std_ops,
853};
854
855static struct clk usb_clk = {
856 .parent = &pll_clk,
857 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PLLCTRL0,
858 .enable_shift = 18,
859 .enable_negate = 1,
860 .ops = &min_ops,
861};
862
863/* list of all the clocks */
864static struct clk_lookup onchip_clks[] = {
865 {
866 .con_id = "osc_24M",
867 .clk = &osc_24M,
868 }, {
869 .con_id = "pll",
870 .clk = &pll_clk,
871 }, {
872 .con_id = "cpu",
873 .clk = &cpu_clk,
874 }, {
875 .con_id = "hclk",
876 .clk = &hclk,
877 }, {
878 .con_id = "xclk",
879 .clk = &xclk,
880 }, {
881 .con_id = "io",
882 .clk = &io_clk,
883 }, {
884 .con_id = "uart",
885 .clk = &uart_clk,
886 }, {
887 .con_id = "audio",
888 .clk = &audio_clk,
889 }, {
890 .con_id = "pwm",
891 .clk = &pwm_clk,
892 }, {
893 .con_id = "dri",
894 .clk = &dri_clk,
895 }, {
896 .con_id = "digctl",
897 .clk = &digctl_clk,
898 }, {
899 .con_id = "timer",
900 .clk = &timer_clk,
901 }, {
902 .con_id = "lcdif",
903 .clk = &lcdif_clk,
904 }, {
905 .con_id = "ssp",
906 .clk = &ssp_clk,
907 }, {
908 .con_id = "gpmi",
909 .clk = &gpmi_clk,
910 }, {
911 .con_id = "spdif",
912 .clk = &spdif_clk,
913 }, {
914 .con_id = "emi",
915 .clk = &emi_clk,
916 }, {
917 .con_id = "ir",
918 .clk = &ir_clk,
919 }, {
920 .con_id = "saif",
921 .clk = &saif_clk,
922 }, {
923 .con_id = "usb",
924 .clk = &usb_clk,
925 },
926};
927
928static int __init propagate_rate(struct clk *clk)
929{
930 struct clk_lookup *cl;
931
932 for (cl = onchip_clks; cl < onchip_clks + ARRAY_SIZE(onchip_clks);
933 cl++) {
934 if (unlikely(!clk_good(cl->clk)))
935 continue;
936 if (cl->clk->parent == clk && cl->clk->ops->get_rate) {
937 cl->clk->ops->get_rate(cl->clk);
938 if (cl->clk->flags & RATE_PROPAGATES)
939 propagate_rate(cl->clk);
940 }
941 }
942
943 return 0;
944}
945
946/* Exported API */
947unsigned long clk_get_rate(struct clk *clk)
948{
949 if (unlikely(!clk_good(clk)))
950 return 0;
951
952 if (clk->rate != 0)
953 return clk->rate;
954
955 if (clk->ops->get_rate != NULL)
956 return clk->ops->get_rate(clk);
957
958 return clk_get_rate(clk->parent);
959}
960EXPORT_SYMBOL(clk_get_rate);
961
962long clk_round_rate(struct clk *clk, unsigned long rate)
963{
964 if (unlikely(!clk_good(clk)))
965 return 0;
966
967 if (clk->ops->round_rate)
968 return clk->ops->round_rate(clk, rate);
969
970 return 0;
971}
972EXPORT_SYMBOL(clk_round_rate);
973
974static inline int close_enough(long rate1, long rate2)
975{
976 return rate1 && !((rate2 - rate1) * 1000 / rate1);
977}
978
979int clk_set_rate(struct clk *clk, unsigned long rate)
980{
981 int ret = -EINVAL;
982
983 if (unlikely(!clk_good(clk)))
984 goto out;
985
986 if (clk->flags & FIXED_RATE || !clk->ops->set_rate)
987 goto out;
988
989 else if (!close_enough(clk->rate, rate)) {
990 ret = clk->ops->set_rate(clk, rate);
991 if (ret < 0)
992 goto out;
993 clk->rate = rate;
994 if (clk->flags & RATE_PROPAGATES)
995 propagate_rate(clk);
996 } else
997 ret = 0;
998
999out:
1000 return ret;
1001}
1002EXPORT_SYMBOL(clk_set_rate);
1003
1004int clk_enable(struct clk *clk)
1005{
1006 unsigned long clocks_flags;
1007
1008 if (unlikely(!clk_good(clk)))
1009 return -EINVAL;
1010
1011 if (clk->parent)
1012 clk_enable(clk->parent);
1013
1014 spin_lock_irqsave(&clocks_lock, clocks_flags);
1015
1016 clk->usage++;
1017 if (clk->ops && clk->ops->enable)
1018 clk->ops->enable(clk);
1019
1020 spin_unlock_irqrestore(&clocks_lock, clocks_flags);
1021 return 0;
1022}
1023EXPORT_SYMBOL(clk_enable);
1024
1025static void local_clk_disable(struct clk *clk)
1026{
1027 if (unlikely(!clk_good(clk)))
1028 return;
1029
1030 if (clk->usage == 0 && clk->ops->disable)
1031 clk->ops->disable(clk);
1032
1033 if (clk->parent)
1034 local_clk_disable(clk->parent);
1035}
1036
1037void clk_disable(struct clk *clk)
1038{
1039 unsigned long clocks_flags;
1040
1041 if (unlikely(!clk_good(clk)))
1042 return;
1043
1044 spin_lock_irqsave(&clocks_lock, clocks_flags);
1045
1046 if ((--clk->usage) == 0 && clk->ops->disable)
1047 clk->ops->disable(clk);
1048
1049 spin_unlock_irqrestore(&clocks_lock, clocks_flags);
1050 if (clk->parent)
1051 clk_disable(clk->parent);
1052}
1053EXPORT_SYMBOL(clk_disable);
1054
1055/* Some additional API */
1056int clk_set_parent(struct clk *clk, struct clk *parent)
1057{
1058 int ret = -ENODEV;
1059 unsigned long clocks_flags;
1060
1061 if (unlikely(!clk_good(clk)))
1062 goto out;
1063
1064 if (!clk->ops->set_parent)
1065 goto out;
1066
1067 spin_lock_irqsave(&clocks_lock, clocks_flags);
1068
1069 ret = clk->ops->set_parent(clk, parent);
1070 if (!ret) {
1071 /* disable if usage count is 0 */
1072 local_clk_disable(parent);
1073
1074 parent->usage += clk->usage;
1075 clk->parent->usage -= clk->usage;
1076
1077 /* disable if new usage count is 0 */
1078 local_clk_disable(clk->parent);
1079
1080 clk->parent = parent;
1081 }
1082 spin_unlock_irqrestore(&clocks_lock, clocks_flags);
1083
1084out:
1085 return ret;
1086}
1087EXPORT_SYMBOL(clk_set_parent);
1088
1089struct clk *clk_get_parent(struct clk *clk)
1090{
1091 if (unlikely(!clk_good(clk)))
1092 return NULL;
1093 return clk->parent;
1094}
1095EXPORT_SYMBOL(clk_get_parent);
1096
1097static int __init clk_init(void)
1098{
1099 struct clk_lookup *cl;
1100 struct clk_ops *ops;
1101
1102 spin_lock_init(&clocks_lock);
1103
1104 for (cl = onchip_clks; cl < onchip_clks + ARRAY_SIZE(onchip_clks);
1105 cl++) {
1106 if (cl->clk->flags & ENABLED)
1107 clk_enable(cl->clk);
1108 else
1109 local_clk_disable(cl->clk);
1110
1111 ops = cl->clk->ops;
1112
1113 if ((cl->clk->flags & NEEDS_INITIALIZATION) &&
1114 ops && ops->set_rate)
1115 ops->set_rate(cl->clk, cl->clk->rate);
1116
1117 if (cl->clk->flags & FIXED_RATE) {
1118 if (cl->clk->flags & RATE_PROPAGATES)
1119 propagate_rate(cl->clk);
1120 } else {
1121 if (ops && ops->get_rate)
1122 ops->get_rate(cl->clk);
1123 }
1124
1125 if (cl->clk->flags & NEEDS_SET_PARENT) {
1126 if (ops && ops->set_parent)
1127 ops->set_parent(cl->clk, cl->clk->parent);
1128 }
1129 }
1130 clkdev_add_table(onchip_clks, ARRAY_SIZE(onchip_clks));
1131 return 0;
1132}
1133
1134arch_initcall(clk_init);
diff --git a/arch/arm/plat-stmp3xxx/clock.h b/arch/arm/plat-stmp3xxx/clock.h
deleted file mode 100644
index a6611e1a3510..000000000000
--- a/arch/arm/plat-stmp3xxx/clock.h
+++ /dev/null
@@ -1,61 +0,0 @@
1/*
2 * Clock control driver for Freescale STMP37XX/STMP378X - internal header file
3 *
4 * Author: Vitaly Wool <vital@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#ifndef __ARCH_ARM_STMX3XXX_CLOCK_H__
19#define __ARCH_ARM_STMX3XXX_CLOCK_H__
20
21#ifndef __ASSEMBLER__
22
23struct clk_ops {
24 int (*enable) (struct clk *);
25 int (*disable) (struct clk *);
26 long (*get_rate) (struct clk *);
27 long (*round_rate) (struct clk *, u32);
28 int (*set_rate) (struct clk *, u32);
29 int (*set_parent) (struct clk *, struct clk *);
30};
31
32struct clk {
33 struct clk *parent;
34 u32 rate;
35 u32 flags;
36 u8 scale_shift;
37 u8 enable_shift;
38 u8 bypass_shift;
39 u8 busy_bit;
40 s8 usage;
41 int enable_wait;
42 int enable_negate;
43 u32 saved_div;
44 void __iomem *enable_reg;
45 void __iomem *scale_reg;
46 void __iomem *bypass_reg;
47 void __iomem *busy_reg;
48 struct clk_ops *ops;
49};
50
51#endif /* __ASSEMBLER__ */
52
53/* Flags */
54#define RATE_PROPAGATES (1<<0)
55#define NEEDS_INITIALIZATION (1<<1)
56#define PARENT_SET_RATE (1<<2)
57#define FIXED_RATE (1<<3)
58#define ENABLED (1<<4)
59#define NEEDS_SET_PARENT (1<<5)
60
61#endif
diff --git a/arch/arm/plat-stmp3xxx/core.c b/arch/arm/plat-stmp3xxx/core.c
deleted file mode 100644
index 37b8a09148a4..000000000000
--- a/arch/arm/plat-stmp3xxx/core.c
+++ /dev/null
@@ -1,128 +0,0 @@
1/*
2 * Freescale STMP37XX/STMP378X core routines
3 *
4 * Embedded Alley Solutions, Inc <source@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/io.h>
21
22#include <mach/stmp3xxx.h>
23#include <mach/platform.h>
24#include <mach/dma.h>
25#include <mach/regs-clkctrl.h>
26
27static int __stmp3xxx_reset_block(void __iomem *hwreg, int just_enable)
28{
29 u32 c;
30 int timeout;
31
32 /* the process of software reset of IP block is done
33 in several steps:
34
35 - clear SFTRST and wait for block is enabled;
36 - clear clock gating (CLKGATE bit);
37 - set the SFTRST again and wait for block is in reset;
38 - clear SFTRST and wait for reset completion.
39 */
40 c = __raw_readl(hwreg);
41 c &= ~(1<<31); /* clear SFTRST */
42 __raw_writel(c, hwreg);
43 for (timeout = 1000000; timeout > 0; timeout--)
44 /* still in SFTRST state ? */
45 if ((__raw_readl(hwreg) & (1<<31)) == 0)
46 break;
47 if (timeout <= 0) {
48 printk(KERN_ERR"%s(%p): timeout when enabling\n",
49 __func__, hwreg);
50 return -ETIME;
51 }
52
53 c = __raw_readl(hwreg);
54 c &= ~(1<<30); /* clear CLKGATE */
55 __raw_writel(c, hwreg);
56
57 if (!just_enable) {
58 c = __raw_readl(hwreg);
59 c |= (1<<31); /* now again set SFTRST */
60 __raw_writel(c, hwreg);
61 for (timeout = 1000000; timeout > 0; timeout--)
62 /* poll until CLKGATE set */
63 if (__raw_readl(hwreg) & (1<<30))
64 break;
65 if (timeout <= 0) {
66 printk(KERN_ERR"%s(%p): timeout when resetting\n",
67 __func__, hwreg);
68 return -ETIME;
69 }
70
71 c = __raw_readl(hwreg);
72 c &= ~(1<<31); /* clear SFTRST */
73 __raw_writel(c, hwreg);
74 for (timeout = 1000000; timeout > 0; timeout--)
75 /* still in SFTRST state ? */
76 if ((__raw_readl(hwreg) & (1<<31)) == 0)
77 break;
78 if (timeout <= 0) {
79 printk(KERN_ERR"%s(%p): timeout when enabling "
80 "after reset\n", __func__, hwreg);
81 return -ETIME;
82 }
83
84 c = __raw_readl(hwreg);
85 c &= ~(1<<30); /* clear CLKGATE */
86 __raw_writel(c, hwreg);
87 }
88 for (timeout = 1000000; timeout > 0; timeout--)
89 /* still in SFTRST state ? */
90 if ((__raw_readl(hwreg) & (1<<30)) == 0)
91 break;
92
93 if (timeout <= 0) {
94 printk(KERN_ERR"%s(%p): timeout when unclockgating\n",
95 __func__, hwreg);
96 return -ETIME;
97 }
98
99 return 0;
100}
101
102int stmp3xxx_reset_block(void __iomem *hwreg, int just_enable)
103{
104 int try = 10;
105 int r;
106
107 while (try--) {
108 r = __stmp3xxx_reset_block(hwreg, just_enable);
109 if (!r)
110 break;
111 pr_debug("%s: try %d failed\n", __func__, 10 - try);
112 }
113 return r;
114}
115EXPORT_SYMBOL(stmp3xxx_reset_block);
116
117struct platform_device stmp3xxx_dbguart = {
118 .name = "stmp3xxx-dbguart",
119 .id = -1,
120};
121
122void __init stmp3xxx_init(void)
123{
124 /* Turn off auto-slow and other tricks */
125 stmp3xxx_clearl(0x7f00000, REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS);
126
127 stmp3xxx_dma_init();
128}
diff --git a/arch/arm/plat-stmp3xxx/devices.c b/arch/arm/plat-stmp3xxx/devices.c
deleted file mode 100644
index 68fed4b8746a..000000000000
--- a/arch/arm/plat-stmp3xxx/devices.c
+++ /dev/null
@@ -1,389 +0,0 @@
1/*
2* Freescale STMP37XX/STMP378X platform devices
3*
4* Embedded Alley Solutions, Inc <source@embeddedalley.com>
5*
6* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8*/
9
10/*
11* The code contained herein is licensed under the GNU General Public
12* License. You may obtain a copy of the GNU General Public License
13* Version 2 or later at the following locations:
14*
15* http://www.opensource.org/licenses/gpl-license.html
16* http://www.gnu.org/copyleft/gpl.html
17*/
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/device.h>
21#include <linux/platform_device.h>
22#include <linux/dma-mapping.h>
23
24#include <mach/dma.h>
25#include <mach/platform.h>
26#include <mach/stmp3xxx.h>
27#include <mach/regs-lcdif.h>
28#include <mach/regs-uartapp.h>
29#include <mach/regs-gpmi.h>
30#include <mach/regs-usbctrl.h>
31#include <mach/regs-ssp.h>
32#include <mach/regs-rtc.h>
33
34static u64 common_dmamask = DMA_BIT_MASK(32);
35
36static struct resource appuart_resources[] = {
37 {
38 .start = IRQ_UARTAPP_INTERNAL,
39 .end = IRQ_UARTAPP_INTERNAL,
40 .flags = IORESOURCE_IRQ,
41 }, {
42 .start = IRQ_UARTAPP_RX_DMA,
43 .end = IRQ_UARTAPP_RX_DMA,
44 .flags = IORESOURCE_IRQ,
45 }, {
46 .start = IRQ_UARTAPP_TX_DMA,
47 .end = IRQ_UARTAPP_TX_DMA,
48 .flags = IORESOURCE_IRQ,
49 }, {
50 .start = REGS_UARTAPP1_PHYS,
51 .end = REGS_UARTAPP1_PHYS + REGS_UARTAPP_SIZE,
52 .flags = IORESOURCE_MEM,
53 }, {
54 /* Rx DMA channel */
55 .start = STMP3XXX_DMA(6, STMP3XXX_BUS_APBX),
56 .end = STMP3XXX_DMA(6, STMP3XXX_BUS_APBX),
57 .flags = IORESOURCE_DMA,
58 }, {
59 /* Tx DMA channel */
60 .start = STMP3XXX_DMA(7, STMP3XXX_BUS_APBX),
61 .end = STMP3XXX_DMA(7, STMP3XXX_BUS_APBX),
62 .flags = IORESOURCE_DMA,
63 },
64};
65
66struct platform_device stmp3xxx_appuart = {
67 .name = "stmp3xxx-appuart",
68 .id = 0,
69 .resource = appuart_resources,
70 .num_resources = ARRAY_SIZE(appuart_resources),
71 .dev = {
72 .dma_mask = &common_dmamask,
73 .coherent_dma_mask = DMA_BIT_MASK(32),
74 },
75};
76
77struct platform_device stmp3xxx_watchdog = {
78 .name = "stmp3xxx_wdt",
79 .id = -1,
80};
81
82static struct resource ts_resource[] = {
83 {
84 .flags = IORESOURCE_IRQ,
85 .start = IRQ_TOUCH_DETECT,
86 .end = IRQ_TOUCH_DETECT,
87 }, {
88 .flags = IORESOURCE_IRQ,
89 .start = IRQ_LRADC_CH5,
90 .end = IRQ_LRADC_CH5,
91 },
92};
93
94struct platform_device stmp3xxx_touchscreen = {
95 .name = "stmp3xxx_ts",
96 .id = -1,
97 .resource = ts_resource,
98 .num_resources = ARRAY_SIZE(ts_resource),
99};
100
101/*
102* Keypad device
103*/
104struct platform_device stmp3xxx_keyboard = {
105 .name = "stmp3xxx-keyboard",
106 .id = -1,
107};
108
109static struct resource gpmi_resources[] = {
110 {
111 .flags = IORESOURCE_MEM,
112 .start = REGS_GPMI_PHYS,
113 .end = REGS_GPMI_PHYS + REGS_GPMI_SIZE,
114 }, {
115 .flags = IORESOURCE_IRQ,
116 .start = IRQ_GPMI_DMA,
117 .end = IRQ_GPMI_DMA,
118 }, {
119 .flags = IORESOURCE_DMA,
120 .start = STMP3XXX_DMA(4, STMP3XXX_BUS_APBH),
121 .end = STMP3XXX_DMA(8, STMP3XXX_BUS_APBH),
122 },
123};
124
125struct platform_device stmp3xxx_gpmi = {
126 .name = "gpmi",
127 .id = -1,
128 .dev = {
129 .dma_mask = &common_dmamask,
130 .coherent_dma_mask = DMA_BIT_MASK(32),
131 },
132 .resource = gpmi_resources,
133 .num_resources = ARRAY_SIZE(gpmi_resources),
134};
135
136static struct resource mmc1_resource[] = {
137 {
138 .flags = IORESOURCE_MEM,
139 .start = REGS_SSP1_PHYS,
140 .end = REGS_SSP1_PHYS + REGS_SSP_SIZE,
141 }, {
142 .flags = IORESOURCE_DMA,
143 .start = STMP3XXX_DMA(1, STMP3XXX_BUS_APBH),
144 .end = STMP3XXX_DMA(1, STMP3XXX_BUS_APBH),
145 }, {
146 .flags = IORESOURCE_IRQ,
147 .start = IRQ_SSP1_DMA,
148 .end = IRQ_SSP1_DMA,
149 }, {
150 .flags = IORESOURCE_IRQ,
151 .start = IRQ_SSP_ERROR,
152 .end = IRQ_SSP_ERROR,
153 },
154};
155
156struct platform_device stmp3xxx_mmc = {
157 .name = "stmp3xxx-mmc",
158 .id = 1,
159 .dev = {
160 .dma_mask = &common_dmamask,
161 .coherent_dma_mask = DMA_BIT_MASK(32),
162 },
163 .resource = mmc1_resource,
164 .num_resources = ARRAY_SIZE(mmc1_resource),
165};
166
167static struct resource usb_resources[] = {
168 {
169 .start = REGS_USBCTRL_PHYS,
170 .end = REGS_USBCTRL_PHYS + SZ_4K,
171 .flags = IORESOURCE_MEM,
172 }, {
173 .start = IRQ_USB_CTRL,
174 .end = IRQ_USB_CTRL,
175 .flags = IORESOURCE_IRQ,
176 },
177};
178
179struct platform_device stmp3xxx_udc = {
180 .name = "fsl-usb2-udc",
181 .id = -1,
182 .dev = {
183 .dma_mask = &common_dmamask,
184 .coherent_dma_mask = DMA_BIT_MASK(32),
185 },
186 .resource = usb_resources,
187 .num_resources = ARRAY_SIZE(usb_resources),
188};
189
190struct platform_device stmp3xxx_ehci = {
191 .name = "fsl-ehci",
192 .id = -1,
193 .dev = {
194 .dma_mask = &common_dmamask,
195 .coherent_dma_mask = DMA_BIT_MASK(32),
196 },
197 .resource = usb_resources,
198 .num_resources = ARRAY_SIZE(usb_resources),
199};
200
201static struct resource rtc_resources[] = {
202 {
203 .start = REGS_RTC_PHYS,
204 .end = REGS_RTC_PHYS + REGS_RTC_SIZE,
205 .flags = IORESOURCE_MEM,
206 }, {
207 .start = IRQ_RTC_ALARM,
208 .end = IRQ_RTC_ALARM,
209 .flags = IORESOURCE_IRQ,
210 }, {
211 .start = IRQ_RTC_1MSEC,
212 .end = IRQ_RTC_1MSEC,
213 .flags = IORESOURCE_IRQ,
214 },
215};
216
217struct platform_device stmp3xxx_rtc = {
218 .name = "stmp3xxx-rtc",
219 .id = -1,
220 .resource = rtc_resources,
221 .num_resources = ARRAY_SIZE(rtc_resources),
222};
223
224static struct resource ssp1_resources[] = {
225 {
226 .start = REGS_SSP1_PHYS,
227 .end = REGS_SSP1_PHYS + REGS_SSP_SIZE,
228 .flags = IORESOURCE_MEM,
229 }, {
230 .start = IRQ_SSP1_DMA,
231 .end = IRQ_SSP1_DMA,
232 .flags = IORESOURCE_IRQ,
233 }, {
234 .start = STMP3XXX_DMA(1, STMP3XXX_BUS_APBH),
235 .end = STMP3XXX_DMA(1, STMP3XXX_BUS_APBH),
236 .flags = IORESOURCE_DMA,
237 },
238};
239
240static struct resource ssp2_resources[] = {
241 {
242 .start = REGS_SSP2_PHYS,
243 .end = REGS_SSP2_PHYS + REGS_SSP_SIZE,
244 .flags = IORESOURCE_MEM,
245 }, {
246 .start = IRQ_SSP2_DMA,
247 .end = IRQ_SSP2_DMA,
248 .flags = IORESOURCE_IRQ,
249 }, {
250 .start = STMP3XXX_DMA(2, STMP3XXX_BUS_APBH),
251 .end = STMP3XXX_DMA(2, STMP3XXX_BUS_APBH),
252 .flags = IORESOURCE_DMA,
253 },
254};
255
256struct platform_device stmp3xxx_spi1 = {
257 .name = "stmp3xxx_ssp",
258 .id = 1,
259 .dev = {
260 .dma_mask = &common_dmamask,
261 .coherent_dma_mask = DMA_BIT_MASK(32),
262 },
263 .resource = ssp1_resources,
264 .num_resources = ARRAY_SIZE(ssp1_resources),
265};
266
267struct platform_device stmp3xxx_spi2 = {
268 .name = "stmp3xxx_ssp",
269 .id = 2,
270 .dev = {
271 .dma_mask = &common_dmamask,
272 .coherent_dma_mask = DMA_BIT_MASK(32),
273 },
274 .resource = ssp2_resources,
275 .num_resources = ARRAY_SIZE(ssp2_resources),
276};
277
278static struct resource fb_resource[] = {
279 {
280 .flags = IORESOURCE_IRQ,
281 .start = IRQ_LCDIF_DMA,
282 .end = IRQ_LCDIF_DMA,
283 }, {
284 .flags = IORESOURCE_IRQ,
285 .start = IRQ_LCDIF_ERROR,
286 .end = IRQ_LCDIF_ERROR,
287 }, {
288 .flags = IORESOURCE_MEM,
289 .start = REGS_LCDIF_PHYS,
290 .end = REGS_LCDIF_PHYS + REGS_LCDIF_SIZE,
291 },
292};
293
294struct platform_device stmp3xxx_framebuffer = {
295 .name = "stmp3xxx-fb",
296 .id = -1,
297 .dev = {
298 .dma_mask = &common_dmamask,
299 .coherent_dma_mask = DMA_BIT_MASK(32),
300 },
301 .num_resources = ARRAY_SIZE(fb_resource),
302 .resource = fb_resource,
303};
304
305#define CMDLINE_DEVICE_CHOOSE(name, dev1, dev2) \
306 static char *cmdline_device_##name; \
307 static int cmdline_device_##name##_setup(char *dev) \
308 { \
309 cmdline_device_##name = dev + 1; \
310 return 0; \
311 } \
312 __setup(#name, cmdline_device_##name##_setup); \
313 int stmp3xxx_##name##_device_register(void) \
314 { \
315 struct platform_device *d = NULL; \
316 if (!cmdline_device_##name || \
317 !strcmp(cmdline_device_##name, #dev1)) \
318 d = &stmp3xxx_##dev1; \
319 else if (!strcmp(cmdline_device_##name, #dev2)) \
320 d = &stmp3xxx_##dev2; \
321 else \
322 printk(KERN_ERR"Unknown %s assignment '%s'.\n", \
323 #name, cmdline_device_##name); \
324 return d ? platform_device_register(d) : -ENOENT; \
325 }
326
327CMDLINE_DEVICE_CHOOSE(ssp1, mmc, spi1)
328CMDLINE_DEVICE_CHOOSE(ssp2, gpmi, spi2)
329
330struct platform_device stmp3xxx_backlight = {
331 .name = "stmp3xxx-bl",
332 .id = -1,
333};
334
335struct platform_device stmp3xxx_rotdec = {
336 .name = "stmp3xxx-rotdec",
337 .id = -1,
338};
339
340struct platform_device stmp3xxx_persistent = {
341 .name = "stmp3xxx-persistent",
342 .id = -1,
343};
344
345struct platform_device stmp3xxx_dcp_bootstream = {
346 .name = "stmp3xxx-dcpboot",
347 .id = -1,
348 .dev = {
349 .dma_mask = &common_dmamask,
350 .coherent_dma_mask = DMA_BIT_MASK(32),
351 },
352};
353
354static struct resource dcp_resources[] = {
355 {
356 .start = IRQ_DCP_VMI,
357 .end = IRQ_DCP_VMI,
358 .flags = IORESOURCE_IRQ,
359 }, {
360 .start = IRQ_DCP,
361 .end = IRQ_DCP,
362 .flags = IORESOURCE_IRQ,
363 },
364};
365
366struct platform_device stmp3xxx_dcp = {
367 .name = "stmp3xxx-dcp",
368 .id = -1,
369 .resource = dcp_resources,
370 .num_resources = ARRAY_SIZE(dcp_resources),
371 .dev = {
372 .dma_mask = &common_dmamask,
373 .coherent_dma_mask = DMA_BIT_MASK(32),
374 },
375};
376
377static struct resource battery_resource[] = {
378 {
379 .flags = IORESOURCE_IRQ,
380 .start = IRQ_VDD5V,
381 .end = IRQ_VDD5V,
382 },
383};
384
385struct platform_device stmp3xxx_battery = {
386 .name = "stmp3xxx-battery",
387 .resource = battery_resource,
388 .num_resources = ARRAY_SIZE(battery_resource),
389};
diff --git a/arch/arm/plat-stmp3xxx/dma.c b/arch/arm/plat-stmp3xxx/dma.c
deleted file mode 100644
index b4dcf8c0477d..000000000000
--- a/arch/arm/plat-stmp3xxx/dma.c
+++ /dev/null
@@ -1,464 +0,0 @@
1/*
2 * DMA helper routines for Freescale STMP37XX/STMP378X
3 *
4 * Author: dmitry pervushin <dpervushin@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#include <linux/gfp.h>
19#include <linux/kernel.h>
20#include <linux/device.h>
21#include <linux/dmapool.h>
22#include <linux/sysdev.h>
23#include <linux/cpufreq.h>
24
25#include <asm/page.h>
26
27#include <mach/platform.h>
28#include <mach/dma.h>
29#include <mach/regs-apbx.h>
30#include <mach/regs-apbh.h>
31
32static const size_t pool_item_size = sizeof(struct stmp3xxx_dma_command);
33static const size_t pool_alignment = 8;
34static struct stmp3xxx_dma_user {
35 void *pool;
36 int inuse;
37 const char *name;
38} channels[MAX_DMA_CHANNELS];
39
40#define IS_VALID_CHANNEL(ch) ((ch) >= 0 && (ch) < MAX_DMA_CHANNELS)
41#define IS_USED(ch) (channels[ch].inuse)
42
43int stmp3xxx_dma_request(int ch, struct device *dev, const char *name)
44{
45 struct stmp3xxx_dma_user *user;
46 int err = 0;
47
48 user = channels + ch;
49 if (!IS_VALID_CHANNEL(ch)) {
50 err = -ENODEV;
51 goto out;
52 }
53 if (IS_USED(ch)) {
54 err = -EBUSY;
55 goto out;
56 }
57 /* Create a pool to allocate dma commands from */
58 user->pool = dma_pool_create(name, dev, pool_item_size,
59 pool_alignment, PAGE_SIZE);
60 if (user->pool == NULL) {
61 err = -ENOMEM;
62 goto out;
63 }
64 user->name = name;
65 user->inuse++;
66out:
67 return err;
68}
69EXPORT_SYMBOL(stmp3xxx_dma_request);
70
71int stmp3xxx_dma_release(int ch)
72{
73 struct stmp3xxx_dma_user *user = channels + ch;
74 int err = 0;
75
76 if (!IS_VALID_CHANNEL(ch)) {
77 err = -ENODEV;
78 goto out;
79 }
80 if (!IS_USED(ch)) {
81 err = -EBUSY;
82 goto out;
83 }
84 BUG_ON(user->pool == NULL);
85 dma_pool_destroy(user->pool);
86 user->inuse--;
87out:
88 return err;
89}
90EXPORT_SYMBOL(stmp3xxx_dma_release);
91
92int stmp3xxx_dma_read_semaphore(int channel)
93{
94 int sem = -1;
95
96 switch (STMP3XXX_DMA_BUS(channel)) {
97 case STMP3XXX_BUS_APBH:
98 sem = __raw_readl(REGS_APBH_BASE + HW_APBH_CHn_SEMA +
99 STMP3XXX_DMA_CHANNEL(channel) * 0x70);
100 sem &= BM_APBH_CHn_SEMA_PHORE;
101 sem >>= BP_APBH_CHn_SEMA_PHORE;
102 break;
103
104 case STMP3XXX_BUS_APBX:
105 sem = __raw_readl(REGS_APBX_BASE + HW_APBX_CHn_SEMA +
106 STMP3XXX_DMA_CHANNEL(channel) * 0x70);
107 sem &= BM_APBX_CHn_SEMA_PHORE;
108 sem >>= BP_APBX_CHn_SEMA_PHORE;
109 break;
110 default:
111 BUG();
112 }
113 return sem;
114}
115EXPORT_SYMBOL(stmp3xxx_dma_read_semaphore);
116
117int stmp3xxx_dma_allocate_command(int channel,
118 struct stmp3xxx_dma_descriptor *descriptor)
119{
120 struct stmp3xxx_dma_user *user = channels + channel;
121 int err = 0;
122
123 if (!IS_VALID_CHANNEL(channel)) {
124 err = -ENODEV;
125 goto out;
126 }
127 if (!IS_USED(channel)) {
128 err = -EBUSY;
129 goto out;
130 }
131 if (descriptor == NULL) {
132 err = -EINVAL;
133 goto out;
134 }
135
136 /* Allocate memory for a command from the buffer */
137 descriptor->command =
138 dma_pool_alloc(user->pool, GFP_KERNEL, &descriptor->handle);
139
140 /* Check it worked */
141 if (!descriptor->command) {
142 err = -ENOMEM;
143 goto out;
144 }
145
146 memset(descriptor->command, 0, pool_item_size);
147out:
148 WARN_ON(err);
149 return err;
150}
151EXPORT_SYMBOL(stmp3xxx_dma_allocate_command);
152
153int stmp3xxx_dma_free_command(int channel,
154 struct stmp3xxx_dma_descriptor *descriptor)
155{
156 int err = 0;
157
158 if (!IS_VALID_CHANNEL(channel)) {
159 err = -ENODEV;
160 goto out;
161 }
162 if (!IS_USED(channel)) {
163 err = -EBUSY;
164 goto out;
165 }
166
167 /* Return the command memory to the pool */
168 dma_pool_free(channels[channel].pool, descriptor->command,
169 descriptor->handle);
170
171 /* Initialise descriptor so we're not tempted to use it */
172 descriptor->command = NULL;
173 descriptor->handle = 0;
174 descriptor->virtual_buf_ptr = NULL;
175 descriptor->next_descr = NULL;
176
177 WARN_ON(err);
178out:
179 return err;
180}
181EXPORT_SYMBOL(stmp3xxx_dma_free_command);
182
183void stmp3xxx_dma_go(int channel,
184 struct stmp3xxx_dma_descriptor *head, u32 semaphore)
185{
186 int ch = STMP3XXX_DMA_CHANNEL(channel);
187 void __iomem *c, *s;
188
189 switch (STMP3XXX_DMA_BUS(channel)) {
190 case STMP3XXX_BUS_APBH:
191 c = REGS_APBH_BASE + HW_APBH_CHn_NXTCMDAR + 0x70 * ch;
192 s = REGS_APBH_BASE + HW_APBH_CHn_SEMA + 0x70 * ch;
193 break;
194
195 case STMP3XXX_BUS_APBX:
196 c = REGS_APBX_BASE + HW_APBX_CHn_NXTCMDAR + 0x70 * ch;
197 s = REGS_APBX_BASE + HW_APBX_CHn_SEMA + 0x70 * ch;
198 break;
199
200 default:
201 return;
202 }
203
204 /* Set next command */
205 __raw_writel(head->handle, c);
206 /* Set counting semaphore (kicks off transfer). Assumes
207 peripheral has been set up correctly */
208 __raw_writel(semaphore, s);
209}
210EXPORT_SYMBOL(stmp3xxx_dma_go);
211
212int stmp3xxx_dma_running(int channel)
213{
214 switch (STMP3XXX_DMA_BUS(channel)) {
215 case STMP3XXX_BUS_APBH:
216 return (__raw_readl(REGS_APBH_BASE + HW_APBH_CHn_SEMA +
217 0x70 * STMP3XXX_DMA_CHANNEL(channel))) &
218 BM_APBH_CHn_SEMA_PHORE;
219
220 case STMP3XXX_BUS_APBX:
221 return (__raw_readl(REGS_APBX_BASE + HW_APBX_CHn_SEMA +
222 0x70 * STMP3XXX_DMA_CHANNEL(channel))) &
223 BM_APBX_CHn_SEMA_PHORE;
224 default:
225 BUG();
226 return 0;
227 }
228}
229EXPORT_SYMBOL(stmp3xxx_dma_running);
230
231/*
232 * Circular dma chain management
233 */
234void stmp3xxx_dma_free_chain(struct stmp37xx_circ_dma_chain *chain)
235{
236 int i;
237
238 for (i = 0; i < chain->total_count; i++)
239 stmp3xxx_dma_free_command(
240 STMP3XXX_DMA(chain->channel, chain->bus),
241 &chain->chain[i]);
242}
243EXPORT_SYMBOL(stmp3xxx_dma_free_chain);
244
245int stmp3xxx_dma_make_chain(int ch, struct stmp37xx_circ_dma_chain *chain,
246 struct stmp3xxx_dma_descriptor descriptors[],
247 unsigned items)
248{
249 int i;
250 int err = 0;
251
252 if (items == 0)
253 return err;
254
255 for (i = 0; i < items; i++) {
256 err = stmp3xxx_dma_allocate_command(ch, &descriptors[i]);
257 if (err) {
258 WARN_ON(err);
259 /*
260 * Couldn't allocate the whole chain.
261 * deallocate what has been allocated
262 */
263 if (i) {
264 do {
265 stmp3xxx_dma_free_command(ch,
266 &descriptors
267 [i]);
268 } while (i-- > 0);
269 }
270 return err;
271 }
272
273 /* link them! */
274 if (i > 0) {
275 descriptors[i - 1].next_descr = &descriptors[i];
276 descriptors[i - 1].command->next =
277 descriptors[i].handle;
278 }
279 }
280
281 /* make list circular */
282 descriptors[items - 1].next_descr = &descriptors[0];
283 descriptors[items - 1].command->next = descriptors[0].handle;
284
285 chain->total_count = items;
286 chain->chain = descriptors;
287 chain->free_index = 0;
288 chain->active_index = 0;
289 chain->cooked_index = 0;
290 chain->free_count = items;
291 chain->active_count = 0;
292 chain->cooked_count = 0;
293 chain->bus = STMP3XXX_DMA_BUS(ch);
294 chain->channel = STMP3XXX_DMA_CHANNEL(ch);
295 return err;
296}
297EXPORT_SYMBOL(stmp3xxx_dma_make_chain);
298
299void stmp37xx_circ_clear_chain(struct stmp37xx_circ_dma_chain *chain)
300{
301 BUG_ON(stmp3xxx_dma_running(STMP3XXX_DMA(chain->channel, chain->bus)));
302 chain->free_index = 0;
303 chain->active_index = 0;
304 chain->cooked_index = 0;
305 chain->free_count = chain->total_count;
306 chain->active_count = 0;
307 chain->cooked_count = 0;
308}
309EXPORT_SYMBOL(stmp37xx_circ_clear_chain);
310
311void stmp37xx_circ_advance_free(struct stmp37xx_circ_dma_chain *chain,
312 unsigned count)
313{
314 BUG_ON(chain->cooked_count < count);
315
316 chain->cooked_count -= count;
317 chain->cooked_index += count;
318 chain->cooked_index %= chain->total_count;
319 chain->free_count += count;
320}
321EXPORT_SYMBOL(stmp37xx_circ_advance_free);
322
323void stmp37xx_circ_advance_active(struct stmp37xx_circ_dma_chain *chain,
324 unsigned count)
325{
326 void __iomem *c;
327 u32 mask_clr, mask;
328 BUG_ON(chain->free_count < count);
329
330 chain->free_count -= count;
331 chain->free_index += count;
332 chain->free_index %= chain->total_count;
333 chain->active_count += count;
334
335 switch (chain->bus) {
336 case STMP3XXX_BUS_APBH:
337 c = REGS_APBH_BASE + HW_APBH_CHn_SEMA + 0x70 * chain->channel;
338 mask_clr = BM_APBH_CHn_SEMA_INCREMENT_SEMA;
339 mask = BF(count, APBH_CHn_SEMA_INCREMENT_SEMA);
340 break;
341 case STMP3XXX_BUS_APBX:
342 c = REGS_APBX_BASE + HW_APBX_CHn_SEMA + 0x70 * chain->channel;
343 mask_clr = BM_APBX_CHn_SEMA_INCREMENT_SEMA;
344 mask = BF(count, APBX_CHn_SEMA_INCREMENT_SEMA);
345 break;
346 default:
347 BUG();
348 return;
349 }
350
351 /* Set counting semaphore (kicks off transfer). Assumes
352 peripheral has been set up correctly */
353 stmp3xxx_clearl(mask_clr, c);
354 stmp3xxx_setl(mask, c);
355}
356EXPORT_SYMBOL(stmp37xx_circ_advance_active);
357
358unsigned stmp37xx_circ_advance_cooked(struct stmp37xx_circ_dma_chain *chain)
359{
360 unsigned cooked;
361
362 cooked = chain->active_count -
363 stmp3xxx_dma_read_semaphore(STMP3XXX_DMA(chain->channel, chain->bus));
364
365 chain->active_count -= cooked;
366 chain->active_index += cooked;
367 chain->active_index %= chain->total_count;
368
369 chain->cooked_count += cooked;
370
371 return cooked;
372}
373EXPORT_SYMBOL(stmp37xx_circ_advance_cooked);
374
375void stmp3xxx_dma_set_alt_target(int channel, int function)
376{
377#if defined(CONFIG_ARCH_STMP37XX)
378 unsigned bits = 4;
379#elif defined(CONFIG_ARCH_STMP378X)
380 unsigned bits = 2;
381#else
382#error wrong arch
383#endif
384 int shift = STMP3XXX_DMA_CHANNEL(channel) * bits;
385 unsigned mask = (1<<bits) - 1;
386 void __iomem *c;
387
388 BUG_ON(function < 0 || function >= (1<<bits));
389 pr_debug("%s: channel = %d, using mask %x, "
390 "shift = %d\n", __func__, channel, mask, shift);
391
392 switch (STMP3XXX_DMA_BUS(channel)) {
393 case STMP3XXX_BUS_APBH:
394 c = REGS_APBH_BASE + HW_APBH_DEVSEL;
395 break;
396 case STMP3XXX_BUS_APBX:
397 c = REGS_APBX_BASE + HW_APBX_DEVSEL;
398 break;
399 default:
400 BUG();
401 }
402 stmp3xxx_clearl(mask << shift, c);
403 stmp3xxx_setl(mask << shift, c);
404}
405EXPORT_SYMBOL(stmp3xxx_dma_set_alt_target);
406
407void stmp3xxx_dma_suspend(void)
408{
409 stmp3xxx_setl(BM_APBH_CTRL0_CLKGATE, REGS_APBH_BASE + HW_APBH_CTRL0);
410 stmp3xxx_setl(BM_APBX_CTRL0_CLKGATE, REGS_APBX_BASE + HW_APBX_CTRL0);
411}
412
413void stmp3xxx_dma_resume(void)
414{
415 stmp3xxx_clearl(BM_APBH_CTRL0_CLKGATE | BM_APBH_CTRL0_SFTRST,
416 REGS_APBH_BASE + HW_APBH_CTRL0);
417 stmp3xxx_clearl(BM_APBX_CTRL0_CLKGATE | BM_APBX_CTRL0_SFTRST,
418 REGS_APBX_BASE + HW_APBX_CTRL0);
419}
420
421#ifdef CONFIG_CPU_FREQ
422
423struct dma_notifier_block {
424 struct notifier_block nb;
425 void *data;
426};
427
428static int dma_cpufreq_notifier(struct notifier_block *self,
429 unsigned long phase, void *p)
430{
431 switch (phase) {
432 case CPUFREQ_POSTCHANGE:
433 stmp3xxx_dma_resume();
434 break;
435
436 case CPUFREQ_PRECHANGE:
437 stmp3xxx_dma_suspend();
438 break;
439
440 default:
441 break;
442 }
443
444 return NOTIFY_DONE;
445}
446
447static struct dma_notifier_block dma_cpufreq_nb = {
448 .nb = {
449 .notifier_call = dma_cpufreq_notifier,
450 },
451};
452#endif /* CONFIG_CPU_FREQ */
453
454void __init stmp3xxx_dma_init(void)
455{
456 stmp3xxx_clearl(BM_APBH_CTRL0_CLKGATE | BM_APBH_CTRL0_SFTRST,
457 REGS_APBH_BASE + HW_APBH_CTRL0);
458 stmp3xxx_clearl(BM_APBX_CTRL0_CLKGATE | BM_APBX_CTRL0_SFTRST,
459 REGS_APBX_BASE + HW_APBX_CTRL0);
460#ifdef CONFIG_CPU_FREQ
461 cpufreq_register_notifier(&dma_cpufreq_nb.nb,
462 CPUFREQ_TRANSITION_NOTIFIER);
463#endif /* CONFIG_CPU_FREQ */
464}
diff --git a/arch/arm/plat-stmp3xxx/include/mach/clkdev.h b/arch/arm/plat-stmp3xxx/include/mach/clkdev.h
deleted file mode 100644
index f9c39772d7c5..000000000000
--- a/arch/arm/plat-stmp3xxx/include/mach/clkdev.h
+++ /dev/null
@@ -1,18 +0,0 @@
1/*
2 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12#ifndef __ASM_MACH_CLKDEV_H
13#define __ASM_MACH_CLKDEV_H
14
15#define __clk_get(clk) ({ 1; })
16#define __clk_put(clk) do { } while (0)
17
18#endif
diff --git a/arch/arm/plat-stmp3xxx/include/mach/cputype.h b/arch/arm/plat-stmp3xxx/include/mach/cputype.h
deleted file mode 100644
index b4e205b95f2c..000000000000
--- a/arch/arm/plat-stmp3xxx/include/mach/cputype.h
+++ /dev/null
@@ -1,33 +0,0 @@
1/*
2 * Freescale STMP37XX/STMP378X CPU type detection
3 *
4 * Embedded Alley Solutions, Inc <source@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#ifndef __ASM_PLAT_CPU_H
19#define __ASM_PLAT_CPU_H
20
21#ifdef CONFIG_ARCH_STMP37XX
22#define cpu_is_stmp37xx() (1)
23#else
24#define cpu_is_stmp37xx() (0)
25#endif
26
27#ifdef CONFIG_ARCH_STMP378X
28#define cpu_is_stmp378x() (1)
29#else
30#define cpu_is_stmp378x() (0)
31#endif
32
33#endif /* __ASM_PLAT_CPU_H */
diff --git a/arch/arm/plat-stmp3xxx/include/mach/debug-macro.S b/arch/arm/plat-stmp3xxx/include/mach/debug-macro.S
deleted file mode 100644
index d3a0985c9681..000000000000
--- a/arch/arm/plat-stmp3xxx/include/mach/debug-macro.S
+++ /dev/null
@@ -1,39 +0,0 @@
1/*
2 * Debugging macro include header
3 *
4 * Embedded Alley Solutions, Inc <source@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18
19 .macro addruart, rp, rv
20 mov \rp, #0x00070000
21 add \rv, \rp, #0xf0000000 @ virtual base
22 add \rp, \rp, #0x80000000 @ physical base
23 .endm
24
25 .macro senduart,rd,rx
26 strb \rd, [\rx, #0] @ data register at 0
27 .endm
28
29 .macro waituart,rd,rx
301001: ldr \rd, [\rx, #0x18] @ UARTFLG
31 tst \rd, #1 << 5 @ UARTFLGUTXFF - 1 when full
32 bne 1001b
33 .endm
34
35 .macro busyuart,rd,rx
361001: ldr \rd, [\rx, #0x18] @ UARTFLG
37 tst \rd, #1 << 3 @ UARTFLGUBUSY - 1 when busy
38 bne 1001b
39 .endm
diff --git a/arch/arm/plat-stmp3xxx/include/mach/dma.h b/arch/arm/plat-stmp3xxx/include/mach/dma.h
deleted file mode 100644
index 7c58557c6766..000000000000
--- a/arch/arm/plat-stmp3xxx/include/mach/dma.h
+++ /dev/null
@@ -1,153 +0,0 @@
1/*
2 * Freescale STMP37XX/STMP378X DMA helper interface
3 *
4 * Embedded Alley Solutions, Inc <source@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#ifndef __ASM_PLAT_STMP3XXX_DMA_H
19#define __ASM_PLAT_STMP3XXX_DMA_H
20
21#include <linux/platform_device.h>
22#include <linux/dmapool.h>
23
24#if !defined(MAX_PIO_WORDS)
25#define MAX_PIO_WORDS (15)
26#endif
27
28#define STMP3XXX_BUS_APBH 0
29#define STMP3XXX_BUS_APBX 1
30#define STMP3XXX_DMA_MAX_CHANNEL 16
31#define STMP3XXX_DMA_BUS(dma) ((dma) / 16)
32#define STMP3XXX_DMA_CHANNEL(dma) ((dma) % 16)
33#define STMP3XXX_DMA(channel, bus) ((bus) * 16 + (channel))
34#define MAX_DMA_ADDRESS 0xffffffff
35#define MAX_DMA_CHANNELS 32
36
37struct stmp3xxx_dma_command {
38 u32 next;
39 u32 cmd;
40 union {
41 u32 buf_ptr;
42 u32 alternate;
43 };
44 u32 pio_words[MAX_PIO_WORDS];
45};
46
47struct stmp3xxx_dma_descriptor {
48 struct stmp3xxx_dma_command *command;
49 dma_addr_t handle;
50
51 /* The virtual address of the buffer pointer */
52 void *virtual_buf_ptr;
53 /* The next descriptor in a the DMA chain (optional) */
54 struct stmp3xxx_dma_descriptor *next_descr;
55};
56
57struct stmp37xx_circ_dma_chain {
58 unsigned total_count;
59 struct stmp3xxx_dma_descriptor *chain;
60
61 unsigned free_index;
62 unsigned free_count;
63 unsigned active_index;
64 unsigned active_count;
65 unsigned cooked_index;
66 unsigned cooked_count;
67
68 int bus;
69 unsigned channel;
70};
71
72static inline struct stmp3xxx_dma_descriptor
73 *stmp3xxx_dma_circ_get_free_head(struct stmp37xx_circ_dma_chain *chain)
74{
75 return &(chain->chain[chain->free_index]);
76}
77
78static inline struct stmp3xxx_dma_descriptor
79 *stmp3xxx_dma_circ_get_cooked_head(struct stmp37xx_circ_dma_chain *chain)
80{
81 return &(chain->chain[chain->cooked_index]);
82}
83
84int stmp3xxx_dma_request(int ch, struct device *dev, const char *name);
85int stmp3xxx_dma_release(int ch);
86int stmp3xxx_dma_allocate_command(int ch,
87 struct stmp3xxx_dma_descriptor *descriptor);
88int stmp3xxx_dma_free_command(int ch,
89 struct stmp3xxx_dma_descriptor *descriptor);
90void stmp3xxx_dma_continue(int channel, u32 semaphore);
91void stmp3xxx_dma_go(int ch, struct stmp3xxx_dma_descriptor *head,
92 u32 semaphore);
93int stmp3xxx_dma_running(int ch);
94int stmp3xxx_dma_make_chain(int ch, struct stmp37xx_circ_dma_chain *chain,
95 struct stmp3xxx_dma_descriptor descriptors[],
96 unsigned items);
97void stmp3xxx_dma_free_chain(struct stmp37xx_circ_dma_chain *chain);
98void stmp37xx_circ_clear_chain(struct stmp37xx_circ_dma_chain *chain);
99void stmp37xx_circ_advance_free(struct stmp37xx_circ_dma_chain *chain,
100 unsigned count);
101void stmp37xx_circ_advance_active(struct stmp37xx_circ_dma_chain *chain,
102 unsigned count);
103unsigned stmp37xx_circ_advance_cooked(struct stmp37xx_circ_dma_chain *chain);
104int stmp3xxx_dma_read_semaphore(int ch);
105void stmp3xxx_dma_init(void);
106void stmp3xxx_dma_set_alt_target(int ch, int target);
107void stmp3xxx_dma_suspend(void);
108void stmp3xxx_dma_resume(void);
109
110/*
111 * STMP37xx and STMP378x have different DMA control
112 * registers layout
113 */
114
115void stmp3xxx_arch_dma_freeze(int ch);
116void stmp3xxx_arch_dma_unfreeze(int ch);
117void stmp3xxx_arch_dma_reset_channel(int ch);
118void stmp3xxx_arch_dma_enable_interrupt(int ch);
119void stmp3xxx_arch_dma_clear_interrupt(int ch);
120int stmp3xxx_arch_dma_is_interrupt(int ch);
121
122static inline void stmp3xxx_dma_reset_channel(int ch)
123{
124 stmp3xxx_arch_dma_reset_channel(ch);
125}
126
127
128static inline void stmp3xxx_dma_freeze(int ch)
129{
130 stmp3xxx_arch_dma_freeze(ch);
131}
132
133static inline void stmp3xxx_dma_unfreeze(int ch)
134{
135 stmp3xxx_arch_dma_unfreeze(ch);
136}
137
138static inline void stmp3xxx_dma_enable_interrupt(int ch)
139{
140 stmp3xxx_arch_dma_enable_interrupt(ch);
141}
142
143static inline void stmp3xxx_dma_clear_interrupt(int ch)
144{
145 stmp3xxx_arch_dma_clear_interrupt(ch);
146}
147
148static inline int stmp3xxx_dma_is_interrupt(int ch)
149{
150 return stmp3xxx_arch_dma_is_interrupt(ch);
151}
152
153#endif /* __ASM_PLAT_STMP3XXX_DMA_H */
diff --git a/arch/arm/plat-stmp3xxx/include/mach/gpio.h b/arch/arm/plat-stmp3xxx/include/mach/gpio.h
deleted file mode 100644
index a8b579256170..000000000000
--- a/arch/arm/plat-stmp3xxx/include/mach/gpio.h
+++ /dev/null
@@ -1,28 +0,0 @@
1/*
2 * Freescale STMP37XX/STMP378X GPIO interface
3 *
4 * Embedded Alley Solutions, Inc <source@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#ifndef __ASM_PLAT_GPIO_H
19#define __ASM_PLAT_GPIO_H
20
21#define ARCH_NR_GPIOS (32 * 3)
22#define gpio_to_irq(gpio) __gpio_to_irq(gpio)
23#define gpio_get_value(gpio) __gpio_get_value(gpio)
24#define gpio_set_value(gpio, value) __gpio_set_value(gpio, value)
25
26#include <asm-generic/gpio.h>
27
28#endif /* __ASM_PLAT_GPIO_H */
diff --git a/arch/arm/plat-stmp3xxx/include/mach/gpmi.h b/arch/arm/plat-stmp3xxx/include/mach/gpmi.h
deleted file mode 100644
index e166432910ad..000000000000
--- a/arch/arm/plat-stmp3xxx/include/mach/gpmi.h
+++ /dev/null
@@ -1,12 +0,0 @@
1#ifndef __MACH_GPMI_H
2
3#include <linux/mtd/partitions.h>
4#include <mach/regs-gpmi.h>
5
6struct gpmi_platform_data {
7 void *pins;
8 int nr_parts;
9 struct mtd_partition *parts;
10 const char *part_types[];
11};
12#endif
diff --git a/arch/arm/plat-stmp3xxx/include/mach/hardware.h b/arch/arm/plat-stmp3xxx/include/mach/hardware.h
deleted file mode 100644
index 47b8978405bc..000000000000
--- a/arch/arm/plat-stmp3xxx/include/mach/hardware.h
+++ /dev/null
@@ -1,32 +0,0 @@
1/*
2 * This file contains the hardware definitions of the Freescale STMP3XXX
3 *
4 * Copyright (C) 2005 Sigmatel Inc
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#ifndef __ASM_ARCH_HARDWARE_H
19#define __ASM_ARCH_HARDWARE_H
20
21/*
22 * Where in virtual memory the IO devices (timers, system controllers
23 * and so on)
24 */
25#define IO_BASE 0xF0000000 /* VA of IO */
26#define IO_SIZE 0x00100000 /* How much? */
27#define IO_START 0x80000000 /* PA of IO */
28
29/* macro to get at IO space when running virtually */
30#define IO_ADDRESS(x) (((x) & 0x000fffff) | IO_BASE)
31
32#endif
diff --git a/arch/arm/plat-stmp3xxx/include/mach/io.h b/arch/arm/plat-stmp3xxx/include/mach/io.h
deleted file mode 100644
index d08b1b7f3d1c..000000000000
--- a/arch/arm/plat-stmp3xxx/include/mach/io.h
+++ /dev/null
@@ -1,25 +0,0 @@
1/*
2 * Copyright (C) 2005 Sigmatel Inc
3 *
4 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 */
7
8/*
9 * The code contained herein is licensed under the GNU General Public
10 * License. You may obtain a copy of the GNU General Public License
11 * Version 2 or later at the following locations:
12 *
13 * http://www.opensource.org/licenses/gpl-license.html
14 * http://www.gnu.org/copyleft/gpl.html
15 */
16#ifndef __ASM_ARM_ARCH_IO_H
17#define __ASM_ARM_ARCH_IO_H
18
19#define IO_SPACE_LIMIT 0xffffffff
20
21#define __io(a) __typesafe_io(a)
22#define __mem_pci(a) (a)
23#define __mem_isa(a) (a)
24
25#endif
diff --git a/arch/arm/plat-stmp3xxx/include/mach/memory.h b/arch/arm/plat-stmp3xxx/include/mach/memory.h
deleted file mode 100644
index 61fa54882e12..000000000000
--- a/arch/arm/plat-stmp3xxx/include/mach/memory.h
+++ /dev/null
@@ -1,22 +0,0 @@
1/*
2 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
4 */
5
6/*
7 * The code contained herein is licensed under the GNU General Public
8 * License. You may obtain a copy of the GNU General Public License
9 * Version 2 or later at the following locations:
10 *
11 * http://www.opensource.org/licenses/gpl-license.html
12 * http://www.gnu.org/copyleft/gpl.html
13 */
14#ifndef __ASM_ARCH_MEMORY_H
15#define __ASM_ARCH_MEMORY_H
16
17/*
18 * Physical DRAM offset.
19 */
20#define PLAT_PHYS_OFFSET UL(0x40000000)
21
22#endif
diff --git a/arch/arm/plat-stmp3xxx/include/mach/mmc.h b/arch/arm/plat-stmp3xxx/include/mach/mmc.h
deleted file mode 100644
index ba81e1543761..000000000000
--- a/arch/arm/plat-stmp3xxx/include/mach/mmc.h
+++ /dev/null
@@ -1,14 +0,0 @@
1#ifndef _MACH_MMC_H
2#define _MACH_MMC_H
3
4#include <mach/regs-ssp.h>
5
6struct stmp3xxxmmc_platform_data {
7 int (*get_wp)(void);
8 unsigned long (*setclock)(void __iomem *base, unsigned long);
9 void (*cmd_pullup)(int);
10 int (*hw_init)(void);
11 void (*hw_release)(void);
12};
13
14#endif
diff --git a/arch/arm/plat-stmp3xxx/include/mach/pinmux.h b/arch/arm/plat-stmp3xxx/include/mach/pinmux.h
deleted file mode 100644
index cc5af82279ad..000000000000
--- a/arch/arm/plat-stmp3xxx/include/mach/pinmux.h
+++ /dev/null
@@ -1,157 +0,0 @@
1/*
2 * Freescale STMP37XX/STMP378X Pin Multiplexing
3 *
4 * Author: Vladislav Buzov <vbuzov@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#ifndef __PINMUX_H
19#define __PINMUX_H
20
21#include <linux/spinlock.h>
22#include <linux/types.h>
23#include <linux/gpio.h>
24#include <asm-generic/gpio.h>
25
26/* Pin definitions */
27#include "pins.h"
28#include <mach/pins.h>
29
30/*
31 * Each pin may be routed up to four different HW interfaces
32 * including GPIO
33 */
34enum pin_fun {
35 PIN_FUN1 = 0,
36 PIN_FUN2,
37 PIN_FUN3,
38 PIN_GPIO,
39};
40
41/*
42 * Each pin may have different output drive strength in range from
43 * 4mA to 20mA. The most common case is 4, 8 and 12 mA strengths.
44 */
45enum pin_strength {
46 PIN_4MA = 0,
47 PIN_8MA,
48 PIN_12MA,
49 PIN_16MA,
50 PIN_20MA,
51};
52
53/*
54 * Each pin can be programmed for 1.8V or 3.3V
55 */
56enum pin_voltage {
57 PIN_1_8V = 0,
58 PIN_3_3V,
59};
60
61/*
62 * Structure to define a group of pins and their parameters
63 */
64struct pin_desc {
65 unsigned id;
66 enum pin_fun fun;
67 enum pin_strength strength;
68 enum pin_voltage voltage;
69 unsigned pullup:1;
70};
71
72struct pin_group {
73 struct pin_desc *pins;
74 int nr_pins;
75};
76
77/* Set pin drive strength */
78void stmp3xxx_pin_strength(unsigned id, enum pin_strength strength,
79 const char *label);
80
81/* Set pin voltage */
82void stmp3xxx_pin_voltage(unsigned id, enum pin_voltage voltage,
83 const char *label);
84
85/* Enable pull-up resistor for a pin */
86void stmp3xxx_pin_pullup(unsigned id, int enable, const char *label);
87
88/*
89 * Request a pin ownership, only one module (identified by @label)
90 * may own a pin.
91 */
92int stmp3xxx_request_pin(unsigned id, enum pin_fun fun, const char *label);
93
94/* Release pin */
95void stmp3xxx_release_pin(unsigned id, const char *label);
96
97void stmp3xxx_set_pin_type(unsigned id, enum pin_fun fun);
98
99/*
100 * Each bank is associated with a number of registers to control
101 * pin function, drive strength, voltage and pull-up reigster. The
102 * number of registers of a given type depends on the number of bits
103 * describin particular pin.
104 */
105#define HW_MUXSEL_NUM 2 /* registers per bank */
106#define HW_MUXSEL_PIN_LEN 2 /* bits per pin */
107#define HW_MUXSEL_PIN_NUM 16 /* pins per register */
108#define HW_MUXSEL_PINFUN_MASK 0x3 /* pin function mask */
109#define HW_MUXSEL_PINFUN_NUM 4 /* four options for a pin */
110
111#define HW_DRIVE_NUM 4 /* registers per bank */
112#define HW_DRIVE_PIN_LEN 4 /* bits per pin */
113#define HW_DRIVE_PIN_NUM 8 /* pins per register */
114#define HW_DRIVE_PINDRV_MASK 0x3 /* pin strength mask - 2 bits */
115#define HW_DRIVE_PINDRV_NUM 5 /* five possible strength values */
116#define HW_DRIVE_PINV_MASK 0x4 /* pin voltage mask - 1 bit */
117
118
119struct stmp3xxx_pinmux_bank {
120 struct gpio_chip chip;
121
122 /* Pins allocation map */
123 unsigned long pin_map;
124
125 /* Pin owner names */
126 const char *pin_labels[32];
127
128 /* Bank registers */
129 void __iomem *hw_muxsel[HW_MUXSEL_NUM];
130 void __iomem *hw_drive[HW_DRIVE_NUM];
131 void __iomem *hw_pull;
132
133 void __iomem *pin2irq,
134 *irqlevel,
135 *irqpolarity,
136 *irqen,
137 *irqstat;
138
139 /* HW MUXSEL register function bit values */
140 u8 functions[HW_MUXSEL_PINFUN_NUM];
141
142 /*
143 * HW DRIVE register strength bit values:
144 * 0xff - requested strength is not supported for this bank
145 */
146 u8 strengths[HW_DRIVE_PINDRV_NUM];
147
148 /* GPIO things */
149 void __iomem *hw_gpio_in,
150 *hw_gpio_out,
151 *hw_gpio_doe;
152 int irq, virq;
153};
154
155int __init stmp3xxx_pinmux_init(int virtual_irq_start);
156
157#endif /* __PINMUX_H */
diff --git a/arch/arm/plat-stmp3xxx/include/mach/pins.h b/arch/arm/plat-stmp3xxx/include/mach/pins.h
deleted file mode 100644
index c573318e1caa..000000000000
--- a/arch/arm/plat-stmp3xxx/include/mach/pins.h
+++ /dev/null
@@ -1,30 +0,0 @@
1/*
2 * Freescale STMP37XX/STMP378X Pin multiplexing interface definitions
3 *
4 * Author: Vladislav Buzov <vbuzov@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#ifndef __ASM_PLAT_PINS_H
19#define __ASM_PLAT_PINS_H
20
21#define STMP3XXX_PINID(bank, pin) (bank * 32 + pin)
22#define STMP3XXX_PINID_TO_BANK(pinid) (pinid / 32)
23#define STMP3XXX_PINID_TO_PINNUM(pinid) (pinid % 32)
24
25/*
26 * Special invalid pin identificator to show a pin doesn't exist
27 */
28#define PINID_NO_PIN STMP3XXX_PINID(0xFF, 0xFF)
29
30#endif /* __ASM_PLAT_PINS_H */
diff --git a/arch/arm/plat-stmp3xxx/include/mach/platform.h b/arch/arm/plat-stmp3xxx/include/mach/platform.h
deleted file mode 100644
index 7007ddaa91eb..000000000000
--- a/arch/arm/plat-stmp3xxx/include/mach/platform.h
+++ /dev/null
@@ -1,68 +0,0 @@
1/*
2 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
4 */
5
6/*
7 * The code contained herein is licensed under the GNU General Public
8 * License. You may obtain a copy of the GNU General Public License
9 * Version 2 or later at the following locations:
10 *
11 * http://www.opensource.org/licenses/gpl-license.html
12 * http://www.gnu.org/copyleft/gpl.html
13 */
14#ifndef __ASM_PLAT_PLATFORM_H
15#define __ASM_PLAT_PLATFORM_H
16
17#ifndef __ASSEMBLER__
18#include <linux/io.h>
19#endif
20#include <asm/sizes.h>
21
22/* Virtual address where registers are mapped */
23#define STMP3XXX_REGS_PHBASE 0x80000000
24#ifdef __ASSEMBLER__
25#define STMP3XXX_REGS_BASE 0xF0000000
26#else
27#define STMP3XXX_REGS_BASE (void __iomem *)0xF0000000
28#endif
29#define STMP3XXX_REGS_SIZE SZ_1M
30
31/* Virtual address where OCRAM is mapped */
32#define STMP3XXX_OCRAM_PHBASE 0x00000000
33#ifdef __ASSEMBLER__
34#define STMP3XXX_OCRAM_BASE 0xf1000000
35#else
36#define STMP3XXX_OCRAM_BASE (void __iomem *)0xf1000000
37#endif
38#define STMP3XXX_OCRAM_SIZE (32 * SZ_1K)
39
40#ifdef CONFIG_ARCH_STMP37XX
41#define IRQ_PRIORITY_REG_RD HW_ICOLL_PRIORITYn_RD
42#define IRQ_PRIORITY_REG_WR HW_ICOLL_PRIORITYn_WR
43#endif
44
45#ifdef CONFIG_ARCH_STMP378X
46#define IRQ_PRIORITY_REG_RD HW_ICOLL_INTERRUPTn_RD
47#define IRQ_PRIORITY_REG_WR HW_ICOLL_INTERRUPTn_WR
48#endif
49
50#define HW_STMP3XXX_SET 0x04
51#define HW_STMP3XXX_CLR 0x08
52#define HW_STMP3XXX_TOG 0x0c
53
54#ifndef __ASSEMBLER__
55static inline void stmp3xxx_clearl(u32 v, void __iomem *r)
56{
57 __raw_writel(v, r + HW_STMP3XXX_CLR);
58}
59
60static inline void stmp3xxx_setl(u32 v, void __iomem *r)
61{
62 __raw_writel(v, r + HW_STMP3XXX_SET);
63}
64#endif
65
66#define BF(value, field) (((value) << BP_##field) & BM_##field)
67
68#endif /* __ASM_ARCH_PLATFORM_H */
diff --git a/arch/arm/plat-stmp3xxx/include/mach/stmp3xxx.h b/arch/arm/plat-stmp3xxx/include/mach/stmp3xxx.h
deleted file mode 100644
index 2e300feaa4cf..000000000000
--- a/arch/arm/plat-stmp3xxx/include/mach/stmp3xxx.h
+++ /dev/null
@@ -1,54 +0,0 @@
1/*
2 * Freescale STMP37XX/STMP378X core structure and function declarations
3 *
4 * Embedded Alley Solutions, Inc <source@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#ifndef __ASM_PLAT_STMP3XXX_H
19#define __ASM_PLAT_STMP3XXX_H
20
21#include <linux/irq.h>
22
23extern struct sys_timer stmp3xxx_timer;
24
25void stmp3xxx_init_irq(struct irq_chip *chip);
26void stmp3xxx_init(void);
27int stmp3xxx_reset_block(void __iomem *hwreg, int just_enable);
28extern struct platform_device stmp3xxx_dbguart,
29 stmp3xxx_appuart,
30 stmp3xxx_watchdog,
31 stmp3xxx_touchscreen,
32 stmp3xxx_keyboard,
33 stmp3xxx_gpmi,
34 stmp3xxx_mmc,
35 stmp3xxx_udc,
36 stmp3xxx_ehci,
37 stmp3xxx_rtc,
38 stmp3xxx_spi1,
39 stmp3xxx_spi2,
40 stmp3xxx_backlight,
41 stmp3xxx_rotdec,
42 stmp3xxx_dcp,
43 stmp3xxx_dcp_bootstream,
44 stmp3xxx_persistent,
45 stmp3xxx_framebuffer,
46 stmp3xxx_battery;
47int stmp3xxx_ssp1_device_register(void);
48int stmp3xxx_ssp2_device_register(void);
49
50struct pin_group;
51void stmp3xxx_release_pin_group(struct pin_group *pin_group, const char *label);
52int stmp3xxx_request_pin_group(struct pin_group *pin_group, const char *label);
53
54#endif /* __ASM_PLAT_STMP3XXX_H */
diff --git a/arch/arm/plat-stmp3xxx/include/mach/system.h b/arch/arm/plat-stmp3xxx/include/mach/system.h
deleted file mode 100644
index 28a988889319..000000000000
--- a/arch/arm/plat-stmp3xxx/include/mach/system.h
+++ /dev/null
@@ -1,49 +0,0 @@
1/*
2 * Copyright (C) 2005 Sigmatel Inc
3 *
4 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 */
7
8/*
9 * The code contained herein is licensed under the GNU General Public
10 * License. You may obtain a copy of the GNU General Public License
11 * Version 2 or later at the following locations:
12 *
13 * http://www.opensource.org/licenses/gpl-license.html
14 * http://www.gnu.org/copyleft/gpl.html
15 */
16#ifndef __ASM_ARCH_SYSTEM_H
17#define __ASM_ARCH_SYSTEM_H
18
19#include <asm/proc-fns.h>
20#include <mach/platform.h>
21#include <mach/regs-clkctrl.h>
22#include <mach/regs-power.h>
23
24static inline void arch_idle(void)
25{
26 /*
27 * This should do all the clock switching
28 * and wait for interrupt tricks
29 */
30
31 cpu_do_idle();
32}
33
34static inline void arch_reset(char mode, const char *cmd)
35{
36 /* Set BATTCHRG to default value */
37 __raw_writel(0x00010000, REGS_POWER_BASE + HW_POWER_CHARGE);
38
39 /* Set MINPWR to default value */
40 __raw_writel(0, REGS_POWER_BASE + HW_POWER_MINPWR);
41
42 /* Reset digital side of chip (but not power or RTC) */
43 __raw_writel(BM_CLKCTRL_RESET_DIG,
44 REGS_CLKCTRL_BASE + HW_CLKCTRL_RESET);
45
46 /* Should not return */
47}
48
49#endif
diff --git a/arch/arm/plat-stmp3xxx/include/mach/timex.h b/arch/arm/plat-stmp3xxx/include/mach/timex.h
deleted file mode 100644
index 3373985d7a8e..000000000000
--- a/arch/arm/plat-stmp3xxx/include/mach/timex.h
+++ /dev/null
@@ -1,20 +0,0 @@
1/*
2 * Copyright (C) 1999 ARM Limited
3 *
4 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 */
7
8/*
9 * The code contained herein is licensed under the GNU General Public
10 * License. You may obtain a copy of the GNU General Public License
11 * Version 2 or later at the following locations:
12 *
13 * http://www.opensource.org/licenses/gpl-license.html
14 * http://www.gnu.org/copyleft/gpl.html
15 */
16
17/*
18 * System time clock is sourced from the 32k clock
19 */
20#define CLOCK_TICK_RATE (32768)
diff --git a/arch/arm/plat-stmp3xxx/include/mach/uncompress.h b/arch/arm/plat-stmp3xxx/include/mach/uncompress.h
deleted file mode 100644
index f79f5ee56cd4..000000000000
--- a/arch/arm/plat-stmp3xxx/include/mach/uncompress.h
+++ /dev/null
@@ -1,53 +0,0 @@
1/*
2 *
3 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
4 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
5 */
6
7/*
8 * The code contained herein is licensed under the GNU General Public
9 * License. You may obtain a copy of the GNU General Public License
10 * Version 2 or later at the following locations:
11 *
12 * http://www.opensource.org/licenses/gpl-license.html
13 * http://www.gnu.org/copyleft/gpl.html
14 */
15#ifndef __ASM_PLAT_UNCOMPRESS_H
16#define __ASM_PLAT_UNCOMPRESS_H
17
18/*
19 * Register includes are for when the MMU enabled; we need to define our
20 * own stuff here for pre-MMU use
21 */
22#define UARTDBG_BASE 0x80070000
23#define UART(c) (((volatile unsigned *)UARTDBG_BASE)[c])
24
25/*
26 * This does not append a newline
27 */
28static void putc(char c)
29{
30 /* Wait for TX fifo empty */
31 while ((UART(6) & (1<<7)) == 0)
32 continue;
33
34 /* Write byte */
35 UART(0) = c;
36
37 /* Wait for last bit to exit the UART */
38 while (UART(6) & (1<<3))
39 continue;
40}
41
42static void flush(void)
43{
44}
45
46/*
47 * nothing to do
48 */
49#define arch_decomp_setup()
50
51#define arch_decomp_wdog()
52
53#endif /* __ASM_PLAT_UNCOMPRESS_H */
diff --git a/arch/arm/plat-stmp3xxx/include/mach/vmalloc.h b/arch/arm/plat-stmp3xxx/include/mach/vmalloc.h
deleted file mode 100644
index 943c1a29d641..000000000000
--- a/arch/arm/plat-stmp3xxx/include/mach/vmalloc.h
+++ /dev/null
@@ -1,12 +0,0 @@
1/*
2 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12#define VMALLOC_END 0xf0000000UL
diff --git a/arch/arm/plat-stmp3xxx/irq.c b/arch/arm/plat-stmp3xxx/irq.c
deleted file mode 100644
index 6fdf9acf82ed..000000000000
--- a/arch/arm/plat-stmp3xxx/irq.c
+++ /dev/null
@@ -1,50 +0,0 @@
1/*
2 * Freescale STMP37XX/STMP378X common interrupt handling code
3 *
4 * Author: Vladislav Buzov <vbuzov@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#include <linux/init.h>
19#include <linux/interrupt.h>
20#include <linux/delay.h>
21#include <linux/irq.h>
22#include <linux/sysdev.h>
23
24#include <mach/stmp3xxx.h>
25#include <mach/platform.h>
26#include <mach/regs-icoll.h>
27
28void __init stmp3xxx_init_irq(struct irq_chip *chip)
29{
30 unsigned int i, lv;
31
32 /* Reset the interrupt controller */
33 stmp3xxx_reset_block(REGS_ICOLL_BASE + HW_ICOLL_CTRL, true);
34
35 /* Disable all interrupts initially */
36 for (i = 0; i < NR_REAL_IRQS; i++) {
37 chip->irq_mask(irq_get_irq_data(i));
38 irq_set_chip_and_handler(i, chip, handle_level_irq);
39 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
40 }
41
42 /* Ensure vector is cleared */
43 for (lv = 0; lv < 4; lv++)
44 __raw_writel(1 << lv, REGS_ICOLL_BASE + HW_ICOLL_LEVELACK);
45 __raw_writel(0, REGS_ICOLL_BASE + HW_ICOLL_VECTOR);
46
47 /* Barrier */
48 (void)__raw_readl(REGS_ICOLL_BASE + HW_ICOLL_STAT);
49}
50
diff --git a/arch/arm/plat-stmp3xxx/pinmux.c b/arch/arm/plat-stmp3xxx/pinmux.c
deleted file mode 100644
index 3def03b3217d..000000000000
--- a/arch/arm/plat-stmp3xxx/pinmux.c
+++ /dev/null
@@ -1,550 +0,0 @@
1/*
2 * Freescale STMP378X/STMP378X Pin Multiplexing
3 *
4 * Author: Vladislav Buzov <vbuzov@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#define DEBUG
19#include <linux/module.h>
20#include <linux/kernel.h>
21#include <linux/errno.h>
22#include <linux/sysdev.h>
23#include <linux/string.h>
24#include <linux/bitops.h>
25#include <linux/irq.h>
26
27#include <mach/hardware.h>
28#include <mach/platform.h>
29#include <mach/regs-pinctrl.h>
30#include <mach/pins.h>
31#include <mach/pinmux.h>
32
33#define NR_BANKS ARRAY_SIZE(pinmux_banks)
34static struct stmp3xxx_pinmux_bank pinmux_banks[] = {
35 [0] = {
36 .hw_muxsel = {
37 REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL0,
38 REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL1,
39 },
40 .hw_drive = {
41 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE0,
42 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE1,
43 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE2,
44 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE3,
45 },
46 .hw_pull = REGS_PINCTRL_BASE + HW_PINCTRL_PULL0,
47 .functions = { 0x0, 0x1, 0x2, 0x3 },
48 .strengths = { 0x0, 0x1, 0x2, 0x3, 0xff },
49
50 .hw_gpio_in = REGS_PINCTRL_BASE + HW_PINCTRL_DIN0,
51 .hw_gpio_out = REGS_PINCTRL_BASE + HW_PINCTRL_DOUT0,
52 .hw_gpio_doe = REGS_PINCTRL_BASE + HW_PINCTRL_DOE0,
53 .irq = IRQ_GPIO0,
54
55 .pin2irq = REGS_PINCTRL_BASE + HW_PINCTRL_PIN2IRQ0,
56 .irqstat = REGS_PINCTRL_BASE + HW_PINCTRL_IRQSTAT0,
57 .irqlevel = REGS_PINCTRL_BASE + HW_PINCTRL_IRQLEVEL0,
58 .irqpolarity = REGS_PINCTRL_BASE + HW_PINCTRL_IRQPOL0,
59 .irqen = REGS_PINCTRL_BASE + HW_PINCTRL_IRQEN0,
60 },
61 [1] = {
62 .hw_muxsel = {
63 REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL2,
64 REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL3,
65 },
66 .hw_drive = {
67 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE4,
68 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE5,
69 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE6,
70 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE7,
71 },
72 .hw_pull = REGS_PINCTRL_BASE + HW_PINCTRL_PULL1,
73 .functions = { 0x0, 0x1, 0x2, 0x3 },
74 .strengths = { 0x0, 0x1, 0x2, 0x3, 0xff },
75
76 .hw_gpio_in = REGS_PINCTRL_BASE + HW_PINCTRL_DIN1,
77 .hw_gpio_out = REGS_PINCTRL_BASE + HW_PINCTRL_DOUT1,
78 .hw_gpio_doe = REGS_PINCTRL_BASE + HW_PINCTRL_DOE1,
79 .irq = IRQ_GPIO1,
80
81 .pin2irq = REGS_PINCTRL_BASE + HW_PINCTRL_PIN2IRQ1,
82 .irqstat = REGS_PINCTRL_BASE + HW_PINCTRL_IRQSTAT1,
83 .irqlevel = REGS_PINCTRL_BASE + HW_PINCTRL_IRQLEVEL1,
84 .irqpolarity = REGS_PINCTRL_BASE + HW_PINCTRL_IRQPOL1,
85 .irqen = REGS_PINCTRL_BASE + HW_PINCTRL_IRQEN1,
86 },
87 [2] = {
88 .hw_muxsel = {
89 REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL4,
90 REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL5,
91 },
92 .hw_drive = {
93 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE8,
94 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE9,
95 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE10,
96 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE11,
97 },
98 .hw_pull = REGS_PINCTRL_BASE + HW_PINCTRL_PULL2,
99 .functions = { 0x0, 0x1, 0x2, 0x3 },
100 .strengths = { 0x0, 0x1, 0x2, 0x1, 0x2 },
101
102 .hw_gpio_in = REGS_PINCTRL_BASE + HW_PINCTRL_DIN2,
103 .hw_gpio_out = REGS_PINCTRL_BASE + HW_PINCTRL_DOUT2,
104 .hw_gpio_doe = REGS_PINCTRL_BASE + HW_PINCTRL_DOE2,
105 .irq = IRQ_GPIO2,
106
107 .pin2irq = REGS_PINCTRL_BASE + HW_PINCTRL_PIN2IRQ2,
108 .irqstat = REGS_PINCTRL_BASE + HW_PINCTRL_IRQSTAT2,
109 .irqlevel = REGS_PINCTRL_BASE + HW_PINCTRL_IRQLEVEL2,
110 .irqpolarity = REGS_PINCTRL_BASE + HW_PINCTRL_IRQPOL2,
111 .irqen = REGS_PINCTRL_BASE + HW_PINCTRL_IRQEN2,
112 },
113 [3] = {
114 .hw_muxsel = {
115 REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL6,
116 REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL7,
117 },
118 .hw_drive = {
119 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE12,
120 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE13,
121 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE14,
122 NULL,
123 },
124 .hw_pull = REGS_PINCTRL_BASE + HW_PINCTRL_PULL3,
125 .functions = {0x0, 0x1, 0x2, 0x3},
126 .strengths = {0x0, 0x1, 0x2, 0x3, 0xff},
127 },
128};
129
130static inline struct stmp3xxx_pinmux_bank *
131stmp3xxx_pinmux_bank(unsigned id, unsigned *bank, unsigned *pin)
132{
133 unsigned b, p;
134
135 b = STMP3XXX_PINID_TO_BANK(id);
136 p = STMP3XXX_PINID_TO_PINNUM(id);
137 BUG_ON(b >= NR_BANKS);
138 if (bank)
139 *bank = b;
140 if (pin)
141 *pin = p;
142 return &pinmux_banks[b];
143}
144
145/* Check if requested pin is owned by caller */
146static int stmp3xxx_check_pin(unsigned id, const char *label)
147{
148 unsigned pin;
149 struct stmp3xxx_pinmux_bank *pm = stmp3xxx_pinmux_bank(id, NULL, &pin);
150
151 if (!test_bit(pin, &pm->pin_map)) {
152 printk(KERN_WARNING
153 "%s: Accessing free pin %x, caller %s\n",
154 __func__, id, label);
155
156 return -EINVAL;
157 }
158
159 if (label && pm->pin_labels[pin] &&
160 strcmp(label, pm->pin_labels[pin])) {
161 printk(KERN_WARNING
162 "%s: Wrong pin owner %x, caller %s owner %s\n",
163 __func__, id, label, pm->pin_labels[pin]);
164
165 return -EINVAL;
166 }
167 return 0;
168}
169
170void stmp3xxx_pin_strength(unsigned id, enum pin_strength strength,
171 const char *label)
172{
173 struct stmp3xxx_pinmux_bank *pbank;
174 void __iomem *hwdrive;
175 u32 shift, val;
176 u32 bank, pin;
177
178 pbank = stmp3xxx_pinmux_bank(id, &bank, &pin);
179 pr_debug("%s: label %s bank %d pin %d strength %d\n", __func__, label,
180 bank, pin, strength);
181
182 hwdrive = pbank->hw_drive[pin / HW_DRIVE_PIN_NUM];
183 shift = (pin % HW_DRIVE_PIN_NUM) * HW_DRIVE_PIN_LEN;
184 val = pbank->strengths[strength];
185 if (val == 0xff) {
186 printk(KERN_WARNING
187 "%s: strength is not supported for bank %d, caller %s",
188 __func__, bank, label);
189 return;
190 }
191
192 if (stmp3xxx_check_pin(id, label))
193 return;
194
195 pr_debug("%s: writing 0x%x to 0x%p register\n", __func__,
196 val << shift, hwdrive);
197 stmp3xxx_clearl(HW_DRIVE_PINDRV_MASK << shift, hwdrive);
198 stmp3xxx_setl(val << shift, hwdrive);
199}
200
201void stmp3xxx_pin_voltage(unsigned id, enum pin_voltage voltage,
202 const char *label)
203{
204 struct stmp3xxx_pinmux_bank *pbank;
205 void __iomem *hwdrive;
206 u32 shift;
207 u32 bank, pin;
208
209 pbank = stmp3xxx_pinmux_bank(id, &bank, &pin);
210 pr_debug("%s: label %s bank %d pin %d voltage %d\n", __func__, label,
211 bank, pin, voltage);
212
213 hwdrive = pbank->hw_drive[pin / HW_DRIVE_PIN_NUM];
214 shift = (pin % HW_DRIVE_PIN_NUM) * HW_DRIVE_PIN_LEN;
215
216 if (stmp3xxx_check_pin(id, label))
217 return;
218
219 pr_debug("%s: changing 0x%x bit in 0x%p register\n",
220 __func__, HW_DRIVE_PINV_MASK << shift, hwdrive);
221 if (voltage == PIN_1_8V)
222 stmp3xxx_clearl(HW_DRIVE_PINV_MASK << shift, hwdrive);
223 else
224 stmp3xxx_setl(HW_DRIVE_PINV_MASK << shift, hwdrive);
225}
226
227void stmp3xxx_pin_pullup(unsigned id, int enable, const char *label)
228{
229 struct stmp3xxx_pinmux_bank *pbank;
230 void __iomem *hwpull;
231 u32 bank, pin;
232
233 pbank = stmp3xxx_pinmux_bank(id, &bank, &pin);
234 pr_debug("%s: label %s bank %d pin %d enable %d\n", __func__, label,
235 bank, pin, enable);
236
237 hwpull = pbank->hw_pull;
238
239 if (stmp3xxx_check_pin(id, label))
240 return;
241
242 pr_debug("%s: changing 0x%x bit in 0x%p register\n",
243 __func__, 1 << pin, hwpull);
244 if (enable)
245 stmp3xxx_setl(1 << pin, hwpull);
246 else
247 stmp3xxx_clearl(1 << pin, hwpull);
248}
249
250int stmp3xxx_request_pin(unsigned id, enum pin_fun fun, const char *label)
251{
252 struct stmp3xxx_pinmux_bank *pbank;
253 u32 bank, pin;
254 int ret = 0;
255
256 pbank = stmp3xxx_pinmux_bank(id, &bank, &pin);
257 pr_debug("%s: label %s bank %d pin %d fun %d\n", __func__, label,
258 bank, pin, fun);
259
260 if (test_bit(pin, &pbank->pin_map)) {
261 printk(KERN_WARNING
262 "%s: CONFLICT DETECTED pin %d:%d caller %s owner %s\n",
263 __func__, bank, pin, label, pbank->pin_labels[pin]);
264 return -EBUSY;
265 }
266
267 set_bit(pin, &pbank->pin_map);
268 pbank->pin_labels[pin] = label;
269
270 stmp3xxx_set_pin_type(id, fun);
271
272 return ret;
273}
274
275void stmp3xxx_set_pin_type(unsigned id, enum pin_fun fun)
276{
277 struct stmp3xxx_pinmux_bank *pbank;
278 void __iomem *hwmux;
279 u32 shift, val;
280 u32 bank, pin;
281
282 pbank = stmp3xxx_pinmux_bank(id, &bank, &pin);
283
284 hwmux = pbank->hw_muxsel[pin / HW_MUXSEL_PIN_NUM];
285 shift = (pin % HW_MUXSEL_PIN_NUM) * HW_MUXSEL_PIN_LEN;
286
287 val = pbank->functions[fun];
288 shift = (pin % HW_MUXSEL_PIN_NUM) * HW_MUXSEL_PIN_LEN;
289 pr_debug("%s: writing 0x%x to 0x%p register\n",
290 __func__, val << shift, hwmux);
291 stmp3xxx_clearl(HW_MUXSEL_PINFUN_MASK << shift, hwmux);
292 stmp3xxx_setl(val << shift, hwmux);
293}
294
295void stmp3xxx_release_pin(unsigned id, const char *label)
296{
297 struct stmp3xxx_pinmux_bank *pbank;
298 u32 bank, pin;
299
300 pbank = stmp3xxx_pinmux_bank(id, &bank, &pin);
301 pr_debug("%s: label %s bank %d pin %d\n", __func__, label, bank, pin);
302
303 if (stmp3xxx_check_pin(id, label))
304 return;
305
306 clear_bit(pin, &pbank->pin_map);
307 pbank->pin_labels[pin] = NULL;
308}
309
310int stmp3xxx_request_pin_group(struct pin_group *pin_group, const char *label)
311{
312 struct pin_desc *pin;
313 int p;
314 int err = 0;
315
316 /* Allocate and configure pins */
317 for (p = 0; p < pin_group->nr_pins; p++) {
318 pr_debug("%s: #%d\n", __func__, p);
319 pin = &pin_group->pins[p];
320
321 err = stmp3xxx_request_pin(pin->id, pin->fun, label);
322 if (err)
323 goto out_err;
324
325 stmp3xxx_pin_strength(pin->id, pin->strength, label);
326 stmp3xxx_pin_voltage(pin->id, pin->voltage, label);
327 stmp3xxx_pin_pullup(pin->id, pin->pullup, label);
328 }
329
330 return 0;
331
332out_err:
333 /* Release allocated pins in case of error */
334 while (--p >= 0) {
335 pr_debug("%s: releasing #%d\n", __func__, p);
336 stmp3xxx_release_pin(pin_group->pins[p].id, label);
337 }
338 return err;
339}
340EXPORT_SYMBOL(stmp3xxx_request_pin_group);
341
342void stmp3xxx_release_pin_group(struct pin_group *pin_group, const char *label)
343{
344 struct pin_desc *pin;
345 int p;
346
347 for (p = 0; p < pin_group->nr_pins; p++) {
348 pin = &pin_group->pins[p];
349 stmp3xxx_release_pin(pin->id, label);
350 }
351}
352EXPORT_SYMBOL(stmp3xxx_release_pin_group);
353
354static int stmp3xxx_irq_data_to_gpio(struct irq_data *d,
355 struct stmp3xxx_pinmux_bank **bank, unsigned *gpio)
356{
357 struct stmp3xxx_pinmux_bank *pm;
358
359 for (pm = pinmux_banks; pm < pinmux_banks + NR_BANKS; pm++)
360 if (pm->virq <= d->irq && d->irq < pm->virq + 32) {
361 *bank = pm;
362 *gpio = d->irq - pm->virq;
363 return 0;
364 }
365 return -ENOENT;
366}
367
368static int stmp3xxx_set_irqtype(struct irq_data *d, unsigned type)
369{
370 struct stmp3xxx_pinmux_bank *pm;
371 unsigned gpio;
372 int l, p;
373
374 stmp3xxx_irq_data_to_gpio(d, &pm, &gpio);
375 switch (type) {
376 case IRQ_TYPE_EDGE_RISING:
377 l = 0; p = 1; break;
378 case IRQ_TYPE_EDGE_FALLING:
379 l = 0; p = 0; break;
380 case IRQ_TYPE_LEVEL_HIGH:
381 l = 1; p = 1; break;
382 case IRQ_TYPE_LEVEL_LOW:
383 l = 1; p = 0; break;
384 default:
385 pr_debug("%s: Incorrect GPIO interrupt type 0x%x\n",
386 __func__, type);
387 return -ENXIO;
388 }
389
390 if (l)
391 stmp3xxx_setl(1 << gpio, pm->irqlevel);
392 else
393 stmp3xxx_clearl(1 << gpio, pm->irqlevel);
394 if (p)
395 stmp3xxx_setl(1 << gpio, pm->irqpolarity);
396 else
397 stmp3xxx_clearl(1 << gpio, pm->irqpolarity);
398 return 0;
399}
400
401static void stmp3xxx_pin_ack_irq(struct irq_data *d)
402{
403 u32 stat;
404 struct stmp3xxx_pinmux_bank *pm;
405 unsigned gpio;
406
407 stmp3xxx_irq_data_to_gpio(d, &pm, &gpio);
408 stat = __raw_readl(pm->irqstat) & (1 << gpio);
409 stmp3xxx_clearl(stat, pm->irqstat);
410}
411
412static void stmp3xxx_pin_mask_irq(struct irq_data *d)
413{
414 struct stmp3xxx_pinmux_bank *pm;
415 unsigned gpio;
416
417 stmp3xxx_irq_data_to_gpio(d, &pm, &gpio);
418 stmp3xxx_clearl(1 << gpio, pm->irqen);
419 stmp3xxx_clearl(1 << gpio, pm->pin2irq);
420}
421
422static void stmp3xxx_pin_unmask_irq(struct irq_data *d)
423{
424 struct stmp3xxx_pinmux_bank *pm;
425 unsigned gpio;
426
427 stmp3xxx_irq_data_to_gpio(d, &pm, &gpio);
428 stmp3xxx_setl(1 << gpio, pm->irqen);
429 stmp3xxx_setl(1 << gpio, pm->pin2irq);
430}
431
432static inline
433struct stmp3xxx_pinmux_bank *to_pinmux_bank(struct gpio_chip *chip)
434{
435 return container_of(chip, struct stmp3xxx_pinmux_bank, chip);
436}
437
438static int stmp3xxx_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
439{
440 struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip);
441 return pm->virq + offset;
442}
443
444static int stmp3xxx_gpio_get(struct gpio_chip *chip, unsigned offset)
445{
446 struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip);
447 unsigned v;
448
449 v = __raw_readl(pm->hw_gpio_in) & (1 << offset);
450 return v ? 1 : 0;
451}
452
453static void stmp3xxx_gpio_set(struct gpio_chip *chip, unsigned offset, int v)
454{
455 struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip);
456
457 if (v)
458 stmp3xxx_setl(1 << offset, pm->hw_gpio_out);
459 else
460 stmp3xxx_clearl(1 << offset, pm->hw_gpio_out);
461}
462
463static int stmp3xxx_gpio_output(struct gpio_chip *chip, unsigned offset, int v)
464{
465 struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip);
466
467 stmp3xxx_setl(1 << offset, pm->hw_gpio_doe);
468 stmp3xxx_gpio_set(chip, offset, v);
469 return 0;
470}
471
472static int stmp3xxx_gpio_input(struct gpio_chip *chip, unsigned offset)
473{
474 struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip);
475
476 stmp3xxx_clearl(1 << offset, pm->hw_gpio_doe);
477 return 0;
478}
479
480static int stmp3xxx_gpio_request(struct gpio_chip *chip, unsigned offset)
481{
482 return stmp3xxx_request_pin(chip->base + offset, PIN_GPIO, "gpio");
483}
484
485static void stmp3xxx_gpio_free(struct gpio_chip *chip, unsigned offset)
486{
487 stmp3xxx_release_pin(chip->base + offset, "gpio");
488}
489
490static void stmp3xxx_gpio_irq(u32 irq, struct irq_desc *desc)
491{
492 struct stmp3xxx_pinmux_bank *pm = irq_get_handler_data(irq);
493 int gpio_irq = pm->virq;
494 u32 stat = __raw_readl(pm->irqstat);
495
496 while (stat) {
497 if (stat & 1)
498 generic_handle_irq(gpio_irq);
499 gpio_irq++;
500 stat >>= 1;
501 }
502}
503
504static struct irq_chip gpio_irq_chip = {
505 .irq_ack = stmp3xxx_pin_ack_irq,
506 .irq_mask = stmp3xxx_pin_mask_irq,
507 .irq_unmask = stmp3xxx_pin_unmask_irq,
508 .irq_set_type = stmp3xxx_set_irqtype,
509};
510
511int __init stmp3xxx_pinmux_init(int virtual_irq_start)
512{
513 int b, r = 0;
514 struct stmp3xxx_pinmux_bank *pm;
515 int virq;
516
517 for (b = 0; b < 3; b++) {
518 /* only banks 0,1,2 are allowed to GPIO */
519 pm = pinmux_banks + b;
520 pm->chip.base = 32 * b;
521 pm->chip.ngpio = 32;
522 pm->chip.owner = THIS_MODULE;
523 pm->chip.can_sleep = 1;
524 pm->chip.exported = 1;
525 pm->chip.to_irq = stmp3xxx_gpio_to_irq;
526 pm->chip.direction_input = stmp3xxx_gpio_input;
527 pm->chip.direction_output = stmp3xxx_gpio_output;
528 pm->chip.get = stmp3xxx_gpio_get;
529 pm->chip.set = stmp3xxx_gpio_set;
530 pm->chip.request = stmp3xxx_gpio_request;
531 pm->chip.free = stmp3xxx_gpio_free;
532 pm->virq = virtual_irq_start + b * 32;
533
534 for (virq = pm->virq; virq < pm->virq; virq++) {
535 gpio_irq_chip.irq_mask(irq_get_irq_data(virq));
536 irq_set_chip_and_handler(virq, &gpio_irq_chip,
537 handle_level_irq);
538 set_irq_flags(virq, IRQF_VALID);
539 }
540 r = gpiochip_add(&pm->chip);
541 if (r < 0)
542 break;
543 irq_set_chained_handler(pm->irq, stmp3xxx_gpio_irq);
544 irq_set_handler_data(pm->irq, pm);
545 }
546 return r;
547}
548
549MODULE_AUTHOR("Vladislav Buzov");
550MODULE_LICENSE("GPL");
diff --git a/arch/arm/plat-stmp3xxx/timer.c b/arch/arm/plat-stmp3xxx/timer.c
deleted file mode 100644
index c395630a6edc..000000000000
--- a/arch/arm/plat-stmp3xxx/timer.c
+++ /dev/null
@@ -1,186 +0,0 @@
1/*
2 * System timer for Freescale STMP37XX/STMP378X
3 *
4 * Embedded Alley Solutions, Inc <source@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/spinlock.h>
21#include <linux/clocksource.h>
22#include <linux/clockchips.h>
23#include <linux/io.h>
24#include <linux/irq.h>
25#include <linux/interrupt.h>
26
27#include <asm/mach/time.h>
28#include <mach/stmp3xxx.h>
29#include <mach/platform.h>
30#include <mach/regs-timrot.h>
31
32static irqreturn_t
33stmp3xxx_timer_interrupt(int irq, void *dev_id)
34{
35 struct clock_event_device *c = dev_id;
36
37 /* timer 0 */
38 if (__raw_readl(REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0) &
39 BM_TIMROT_TIMCTRLn_IRQ) {
40 stmp3xxx_clearl(BM_TIMROT_TIMCTRLn_IRQ,
41 REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0);
42 c->event_handler(c);
43 }
44
45 /* timer 1 */
46 else if (__raw_readl(REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1)
47 & BM_TIMROT_TIMCTRLn_IRQ) {
48 stmp3xxx_clearl(BM_TIMROT_TIMCTRLn_IRQ,
49 REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1);
50 stmp3xxx_clearl(BM_TIMROT_TIMCTRLn_IRQ_EN,
51 REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1);
52 __raw_writel(0xFFFF, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1);
53 }
54
55 return IRQ_HANDLED;
56}
57
58static cycle_t stmp3xxx_clock_read(struct clocksource *cs)
59{
60 return ~((__raw_readl(REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1)
61 & 0xFFFF0000) >> 16);
62}
63
64static int
65stmp3xxx_timrot_set_next_event(unsigned long delta,
66 struct clock_event_device *dev)
67{
68 /* reload the timer */
69 __raw_writel(delta, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0);
70 return 0;
71}
72
73static void
74stmp3xxx_timrot_set_mode(enum clock_event_mode mode,
75 struct clock_event_device *dev)
76{
77}
78
79static struct clock_event_device ckevt_timrot = {
80 .name = "timrot",
81 .features = CLOCK_EVT_FEAT_ONESHOT,
82 .shift = 32,
83 .set_next_event = stmp3xxx_timrot_set_next_event,
84 .set_mode = stmp3xxx_timrot_set_mode,
85};
86
87static struct clocksource cksrc_stmp3xxx = {
88 .name = "cksrc_stmp3xxx",
89 .rating = 250,
90 .read = stmp3xxx_clock_read,
91 .mask = CLOCKSOURCE_MASK(16),
92 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
93};
94
95static struct irqaction stmp3xxx_timer_irq = {
96 .name = "stmp3xxx_timer",
97 .flags = IRQF_DISABLED | IRQF_TIMER,
98 .handler = stmp3xxx_timer_interrupt,
99 .dev_id = &ckevt_timrot,
100};
101
102
103/*
104 * Set up timer interrupt, and return the current time in seconds.
105 */
106static void __init stmp3xxx_init_timer(void)
107{
108 ckevt_timrot.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC,
109 ckevt_timrot.shift);
110 ckevt_timrot.min_delta_ns = clockevent_delta2ns(2, &ckevt_timrot);
111 ckevt_timrot.max_delta_ns = clockevent_delta2ns(0xFFF, &ckevt_timrot);
112 ckevt_timrot.cpumask = cpumask_of(0);
113
114 stmp3xxx_reset_block(REGS_TIMROT_BASE, false);
115
116 /* clear two timers */
117 __raw_writel(0, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0);
118 __raw_writel(0, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1);
119
120 /* configure them */
121 __raw_writel(
122 (8 << BP_TIMROT_TIMCTRLn_SELECT) | /* 32 kHz */
123 BM_TIMROT_TIMCTRLn_RELOAD |
124 BM_TIMROT_TIMCTRLn_UPDATE |
125 BM_TIMROT_TIMCTRLn_IRQ_EN,
126 REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0);
127 __raw_writel(
128 (8 << BP_TIMROT_TIMCTRLn_SELECT) | /* 32 kHz */
129 BM_TIMROT_TIMCTRLn_RELOAD |
130 BM_TIMROT_TIMCTRLn_UPDATE |
131 BM_TIMROT_TIMCTRLn_IRQ_EN,
132 REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1);
133
134 __raw_writel(CLOCK_TICK_RATE / HZ - 1,
135 REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0);
136 __raw_writel(0xFFFF, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1);
137
138 setup_irq(IRQ_TIMER0, &stmp3xxx_timer_irq);
139
140 clocksource_register_hz(&cksrc_stmp3xxx, CLOCK_TICK_RATE);
141 clockevents_register_device(&ckevt_timrot);
142}
143
144#ifdef CONFIG_PM
145
146void stmp3xxx_suspend_timer(void)
147{
148 stmp3xxx_clearl(BM_TIMROT_TIMCTRLn_IRQ_EN | BM_TIMROT_TIMCTRLn_IRQ,
149 REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0);
150 stmp3xxx_setl(BM_TIMROT_ROTCTRL_CLKGATE,
151 REGS_TIMROT_BASE + HW_TIMROT_ROTCTRL);
152}
153
154void stmp3xxx_resume_timer(void)
155{
156 stmp3xxx_clearl(BM_TIMROT_ROTCTRL_SFTRST | BM_TIMROT_ROTCTRL_CLKGATE,
157 REGS_TIMROT_BASE + HW_TIMROT_ROTCTRL);
158 __raw_writel(
159 8 << BP_TIMROT_TIMCTRLn_SELECT | /* 32 kHz */
160 BM_TIMROT_TIMCTRLn_RELOAD |
161 BM_TIMROT_TIMCTRLn_UPDATE |
162 BM_TIMROT_TIMCTRLn_IRQ_EN,
163 REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0);
164 __raw_writel(
165 8 << BP_TIMROT_TIMCTRLn_SELECT | /* 32 kHz */
166 BM_TIMROT_TIMCTRLn_RELOAD |
167 BM_TIMROT_TIMCTRLn_UPDATE |
168 BM_TIMROT_TIMCTRLn_IRQ_EN,
169 REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1);
170 __raw_writel(CLOCK_TICK_RATE / HZ - 1,
171 REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0);
172 __raw_writel(0xFFFF, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1);
173}
174
175#else
176
177#define stmp3xxx_suspend_timer NULL
178#define stmp3xxx_resume_timer NULL
179
180#endif /* CONFIG_PM */
181
182struct sys_timer stmp3xxx_timer = {
183 .init = stmp3xxx_init_timer,
184 .suspend = stmp3xxx_suspend_timer,
185 .resume = stmp3xxx_resume_timer,
186};
diff --git a/arch/arm/plat-versatile/platsmp.c b/arch/arm/plat-versatile/platsmp.c
index ba3d471d4bcf..51ecfea09b27 100644
--- a/arch/arm/plat-versatile/platsmp.c
+++ b/arch/arm/plat-versatile/platsmp.c
@@ -16,6 +16,7 @@
16#include <linux/smp.h> 16#include <linux/smp.h>
17 17
18#include <asm/cacheflush.h> 18#include <asm/cacheflush.h>
19#include <asm/hardware/gic.h>
19 20
20/* 21/*
21 * control for which core is the next to come out of the secondary 22 * control for which core is the next to come out of the secondary
@@ -83,7 +84,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
83 * the boot monitor to read the system wide flags register, 84 * the boot monitor to read the system wide flags register,
84 * and branch to the address found there. 85 * and branch to the address found there.
85 */ 86 */
86 smp_cross_call(cpumask_of(cpu), 1); 87 gic_raise_softirq(cpumask_of(cpu), 1);
87 88
88 timeout = jiffies + (1 * HZ); 89 timeout = jiffies + (1 * HZ);
89 while (time_before(jiffies, timeout)) { 90 while (time_before(jiffies, timeout)) {