3 files changed, 42 insertions, 31 deletions

diff --git a/arch/mips/au1000/common/cputable.c b/arch/mips/au1000/common/cputable.c
index d8df5fdb045f..5c0d35d6e22a 100644
--- a/arch/mips/au1000/common/cputable.c
+++ b/arch/mips/au1000/common/cputable.c
@@ -22,24 +22,24 @@ struct cpu_spec* cur_cpu_spec[NR_CPUS];
 /* With some thought, we can probably use the mask to reduce the
  * size of the table.
  */
-struct cpu_spec cpu_specs[] = {
-    { 0xffffffff, 0x00030100, "Au1000 DA", 1, 0 },
-    { 0xffffffff, 0x00030201, "Au1000 HA", 1, 0 },
-    { 0xffffffff, 0x00030202, "Au1000 HB", 1, 0 },
-    { 0xffffffff, 0x00030203, "Au1000 HC", 1, 1 },
-    { 0xffffffff, 0x00030204, "Au1000 HD", 1, 1 },
-    { 0xffffffff, 0x01030200, "Au1500 AB", 1, 1 },
-    { 0xffffffff, 0x01030201, "Au1500 AC", 0, 1 },
-    { 0xffffffff, 0x01030202, "Au1500 AD", 0, 1 },
-    { 0xffffffff, 0x02030200, "Au1100 AB", 1, 1 },
-    { 0xffffffff, 0x02030201, "Au1100 BA", 1, 1 },
-    { 0xffffffff, 0x02030202, "Au1100 BC", 1, 1 },
-    { 0xffffffff, 0x02030203, "Au1100 BD", 0, 1 },
-    { 0xffffffff, 0x02030204, "Au1100 BE", 0, 1 },
-    { 0xffffffff, 0x03030200, "Au1550 AA", 0, 1 },
-    { 0xffffffff, 0x04030200, "Au1200 AB", 0, 0 },
-    { 0xffffffff, 0x04030201, "Au1200 AC", 1, 0 },
-    { 0x00000000, 0x00000000, "Unknown Au1xxx", 1, 0 },
+struct cpu_spec cpu_specs[] = {
+        { 0xffffffff, 0x00030100, "Au1000 DA", 1, 0, 1 },
+        { 0xffffffff, 0x00030201, "Au1000 HA", 1, 0, 1 },
+        { 0xffffffff, 0x00030202, "Au1000 HB", 1, 0, 1 },
+        { 0xffffffff, 0x00030203, "Au1000 HC", 1, 1, 0 },
+        { 0xffffffff, 0x00030204, "Au1000 HD", 1, 1, 0 },
+        { 0xffffffff, 0x01030200, "Au1500 AB", 1, 1, 0 },
+        { 0xffffffff, 0x01030201, "Au1500 AC", 0, 1, 0 },
+        { 0xffffffff, 0x01030202, "Au1500 AD", 0, 1, 0 },
+        { 0xffffffff, 0x02030200, "Au1100 AB", 1, 1, 0 },
+        { 0xffffffff, 0x02030201, "Au1100 BA", 1, 1, 0 },
+        { 0xffffffff, 0x02030202, "Au1100 BC", 1, 1, 0 },
+        { 0xffffffff, 0x02030203, "Au1100 BD", 0, 1, 0 },
+        { 0xffffffff, 0x02030204, "Au1100 BE", 0, 1, 0 },
+        { 0xffffffff, 0x03030200, "Au1550 AA", 0, 1, 0 },
+        { 0xffffffff, 0x04030200, "Au1200 AB", 0, 0, 0 },
+        { 0xffffffff, 0x04030201, "Au1200 AC", 1, 0, 0 },
+        { 0x00000000, 0x00000000, "Unknown Au1xxx", 1, 0, 0 }
 };
 
 void
diff --git a/arch/mips/au1000/common/setup.c b/arch/mips/au1000/common/setup.c
index d885e3848ec6..9e4ab80caab6 100644
--- a/arch/mips/au1000/common/setup.c
+++ b/arch/mips/au1000/common/setup.c
@@ -57,7 +57,7 @@ void __init plat_mem_setup(void)
 {
         struct  cpu_spec *sp;
         char *argptr;
-        unsigned long prid, cpupll, bclk = 1;
+        unsigned long prid, cpufreq, bclk = 1;
 
         set_cpuspec();
         sp = cur_cpu_spec[0];
@@ -65,8 +65,15 @@ void __init plat_mem_setup(void)
         board_setup();  /* board specific setup */
 
         prid = read_c0_prid();
-        cpupll = (au_readl(0xB1900060) & 0x3F) * 12;
-        printk("(PRId %08lx) @ %ldMHZ\n", prid, cpupll);
+        if (sp->cpu_pll_wo)
+#ifdef CONFIG_SOC_AU1000_FREQUENCY
+                cpufreq = CONFIG_SOC_AU1000_FREQUENCY / 1000000;
+#else
+                cpufreq = 396;
+#endif
+        else
+                cpufreq = (au_readl(SYS_CPUPLL) & 0x3F) * 12;
+        printk(KERN_INFO "(PRID %08lx) @ %ld MHz\n", prid, cpufreq);
 
         bclk = sp->cpu_bclk;
         if (bclk)
diff --git a/arch/mips/au1000/common/time.c b/arch/mips/au1000/common/time.c
index f113b512d7b1..e122bbc6cd88 100644
--- a/arch/mips/au1000/common/time.c
+++ b/arch/mips/au1000/common/time.c
@@ -209,18 +209,22 @@ unsigned long cal_r4koff(void)
                 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S);
                 au_writel(0, SYS_TOYWRITE);
                 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S);
+        } else
+                no_au1xxx_32khz = 1;
 
-                cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) *
-                        AU1000_SRC_CLK;
-        }
-        else {
-                /* The 32KHz oscillator isn't running, so assume there
-                 * isn't one and grab the processor speed from the PLL.
-                 * NOTE: some old silicon doesn't allow reading the PLL.
-                 */
+        /*
+         * On early Au1000, sys_cpupll was write-only. Since these
+         * silicon versions of Au1000 are not sold by AMD, we don't bend
+         * over backwards trying to determine the frequency.
+         */
+        if (cur_cpu_spec[0]->cpu_pll_wo)
+#ifdef CONFIG_SOC_AU1000_FREQUENCY
+                cpu_speed = CONFIG_SOC_AU1000_FREQUENCY;
+#else
+                cpu_speed = 396000000;
+#endif
+        else
                 cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * AU1000_SRC_CLK;
-                no_au1xxx_32khz = 1;
-        }
         mips_hpt_frequency = cpu_speed;
         // Equation: Baudrate = CPU / (SD * 2 * CLKDIV * 16)
         set_au1x00_uart_baud_base(cpu_speed / (2 * ((int)(au_readl(SYS_POWERCTRL)&0x03) + 2) * 16));