diff options
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/mach-tegra/tegra2_clocks.c | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c index cf1c9d0ef7e1..ae3b308e22a4 100644 --- a/arch/arm/mach-tegra/tegra2_clocks.c +++ b/arch/arm/mach-tegra/tegra2_clocks.c | |||
@@ -110,6 +110,8 @@ | |||
110 | #define PLLD_MISC_DIV_RST (1<<23) | 110 | #define PLLD_MISC_DIV_RST (1<<23) |
111 | #define PLLD_MISC_DCCON_SHIFT 12 | 111 | #define PLLD_MISC_DCCON_SHIFT 12 |
112 | 112 | ||
113 | #define PLLE_MISC_READY (1 << 15) | ||
114 | |||
113 | #define PERIPH_CLK_TO_ENB_REG(c) ((c->clk_num / 32) * 4) | 115 | #define PERIPH_CLK_TO_ENB_REG(c) ((c->clk_num / 32) * 4) |
114 | #define PERIPH_CLK_TO_ENB_SET_REG(c) ((c->clk_num / 32) * 8) | 116 | #define PERIPH_CLK_TO_ENB_SET_REG(c) ((c->clk_num / 32) * 8) |
115 | #define PERIPH_CLK_TO_ENB_BIT(c) (1 << (c->clk_num % 32)) | 117 | #define PERIPH_CLK_TO_ENB_BIT(c) (1 << (c->clk_num % 32)) |
@@ -567,6 +569,31 @@ static struct clk_ops tegra_pllx_ops = { | |||
567 | .set_rate = tegra2_pll_clk_set_rate, | 569 | .set_rate = tegra2_pll_clk_set_rate, |
568 | }; | 570 | }; |
569 | 571 | ||
572 | static int tegra2_plle_clk_enable(struct clk *c) | ||
573 | { | ||
574 | u32 val; | ||
575 | |||
576 | pr_debug("%s on clock %s\n", __func__, c->name); | ||
577 | |||
578 | mdelay(1); | ||
579 | |||
580 | val = clk_readl(c->reg + PLL_BASE); | ||
581 | if (!(val & PLLE_MISC_READY)) | ||
582 | return -EBUSY; | ||
583 | |||
584 | val = clk_readl(c->reg + PLL_BASE); | ||
585 | val |= PLL_BASE_ENABLE | PLL_BASE_BYPASS; | ||
586 | clk_writel(val, c->reg + PLL_BASE); | ||
587 | |||
588 | return 0; | ||
589 | } | ||
590 | |||
591 | static struct clk_ops tegra_plle_ops = { | ||
592 | .init = tegra2_pll_clk_init, | ||
593 | .enable = tegra2_plle_clk_enable, | ||
594 | .set_rate = tegra2_pll_clk_set_rate, | ||
595 | }; | ||
596 | |||
570 | /* Clock divider ops */ | 597 | /* Clock divider ops */ |
571 | static void tegra2_pll_div_clk_init(struct clk *c) | 598 | static void tegra2_pll_div_clk_init(struct clk *c) |
572 | { | 599 | { |
@@ -1317,6 +1344,23 @@ static struct clk tegra_pll_x = { | |||
1317 | .max_rate = 1000000000, | 1344 | .max_rate = 1000000000, |
1318 | }; | 1345 | }; |
1319 | 1346 | ||
1347 | static struct clk_pll_table tegra_pll_e_table[] = { | ||
1348 | { 12000000, 100000000, 200, 24, 1, 0 }, | ||
1349 | { 0, 0, 0, 0, 0, 0 }, | ||
1350 | }; | ||
1351 | |||
1352 | static struct clk tegra_pll_e = { | ||
1353 | .name = "pll_e", | ||
1354 | .flags = PLL_ALT_MISC_REG, | ||
1355 | .ops = &tegra_plle_ops, | ||
1356 | .input_min = 12000000, | ||
1357 | .input_max = 12000000, | ||
1358 | .max_rate = 100000000, | ||
1359 | .parent = &tegra_clk_m, | ||
1360 | .reg = 0xe8, | ||
1361 | .pll_table = tegra_pll_e_table, | ||
1362 | }; | ||
1363 | |||
1320 | static struct clk tegra_clk_d = { | 1364 | static struct clk tegra_clk_d = { |
1321 | .name = "clk_d", | 1365 | .name = "clk_d", |
1322 | .flags = PERIPH_NO_RESET, | 1366 | .flags = PERIPH_NO_RESET, |
@@ -1626,6 +1670,9 @@ struct clk tegra_periph_clks[] = { | |||
1626 | PERIPH_CLK("csi", "csi", NULL, 52, 0, 72000000, mux_pllp_out3, 0), | 1670 | PERIPH_CLK("csi", "csi", NULL, 52, 0, 72000000, mux_pllp_out3, 0), |
1627 | PERIPH_CLK("isp", "isp", NULL, 23, 0, 150000000, mux_clk_m, 0), /* same frequency as VI */ | 1671 | PERIPH_CLK("isp", "isp", NULL, 23, 0, 150000000, mux_clk_m, 0), /* same frequency as VI */ |
1628 | PERIPH_CLK("csus", "csus", NULL, 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET), | 1672 | PERIPH_CLK("csus", "csus", NULL, 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET), |
1673 | PERIPH_CLK("pex", NULL, "pex", 70, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET), | ||
1674 | PERIPH_CLK("afi", NULL, "afi", 72, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET), | ||
1675 | PERIPH_CLK("pcie_xclk", NULL, "pcie_xclk", 74, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET), | ||
1629 | }; | 1676 | }; |
1630 | 1677 | ||
1631 | #define CLK_DUPLICATE(_name, _dev, _con) \ | 1678 | #define CLK_DUPLICATE(_name, _dev, _con) \ |
@@ -1679,6 +1726,7 @@ struct clk_lookup tegra_clk_lookups[] = { | |||
1679 | CLK(NULL, "pll_d_out0", &tegra_pll_d_out0), | 1726 | CLK(NULL, "pll_d_out0", &tegra_pll_d_out0), |
1680 | CLK(NULL, "pll_u", &tegra_pll_u), | 1727 | CLK(NULL, "pll_u", &tegra_pll_u), |
1681 | CLK(NULL, "pll_x", &tegra_pll_x), | 1728 | CLK(NULL, "pll_x", &tegra_pll_x), |
1729 | CLK(NULL, "pll_e", &tegra_pll_e), | ||
1682 | CLK(NULL, "cclk", &tegra_clk_cclk), | 1730 | CLK(NULL, "cclk", &tegra_clk_cclk), |
1683 | CLK(NULL, "sclk", &tegra_clk_sclk), | 1731 | CLK(NULL, "sclk", &tegra_clk_sclk), |
1684 | CLK(NULL, "hclk", &tegra_clk_hclk), | 1732 | CLK(NULL, "hclk", &tegra_clk_hclk), |