192 files changed, 6812 insertions, 1700 deletions

diff --git a/arch/arm/configs/rx51_defconfig b/arch/arm/configs/rx51_defconfig
index eb2cb31825c0..f238df66efd4 100644
--- a/arch/arm/configs/rx51_defconfig
+++ b/arch/arm/configs/rx51_defconfig
@@ -282,7 +282,7 @@ CONFIG_ALIGNMENT_TRAP=y
 #
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="init=/sbin/preinit ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs rootflags=bulk_read,no_chk_data_crc rw console=ttyMTD,log console=tty0"
+CONFIG_CMDLINE="init=/sbin/preinit ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs rootflags=bulk_read,no_chk_data_crc rw console=ttyMTD,log console=tty0 console=ttyS2,115200n8"
 # CONFIG_XIP_KERNEL is not set
 # CONFIG_KEXEC is not set
 
@@ -1354,7 +1354,7 @@ CONFIG_USB_OTG_UTILS=y
 # CONFIG_USB_GPIO_VBUS is not set
 # CONFIG_ISP1301_OMAP is not set
 CONFIG_TWL4030_USB=y
-CONFIG_MMC=m
+CONFIG_MMC=y
 # CONFIG_MMC_DEBUG is not set
 # CONFIG_MMC_UNSAFE_RESUME is not set
 
@@ -1449,7 +1449,8 @@ CONFIG_RTC_DRV_TWL4030=m
 # on-CPU RTC drivers
 #
 # CONFIG_DMADEVICES is not set
-# CONFIG_REGULATOR is not set
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_TWL4030=y
 # CONFIG_UIO is not set
 # CONFIG_STAGING is not set
 
diff --git a/arch/arm/include/asm/setup.h b/arch/arm/include/asm/setup.h
index ee1304f22f94..5ccce0a9b03c 100644
--- a/arch/arm/include/asm/setup.h
+++ b/arch/arm/include/asm/setup.h
@@ -201,7 +201,8 @@ static struct tagtable __tagtable_##fn __tag = { tag, fn }
 struct membank {
         unsigned long start;
         unsigned long size;
-        int           node;
+        unsigned short node;
+        unsigned short highmem;
 };
 
 struct meminfo {
diff --git a/arch/arm/mach-ixp4xx/include/mach/io.h b/arch/arm/mach-ixp4xx/include/mach/io.h
index ce63048d45eb..8a947d42a6f1 100644
--- a/arch/arm/mach-ixp4xx/include/mach/io.h
+++ b/arch/arm/mach-ixp4xx/include/mach/io.h
@@ -17,7 +17,7 @@
 
 #include <mach/hardware.h>
 
-#define IO_SPACE_LIMIT 0xffff0000
+#define IO_SPACE_LIMIT 0x0000ffff
 
 extern int (*ixp4xx_pci_read)(u32 addr, u32 cmd, u32* data);
 extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data);
diff --git a/arch/arm/mach-mx3/mx31moboard-devboard.c b/arch/arm/mach-mx3/mx31moboard-devboard.c
index 4704405165a1..b48581e7dedd 100644
--- a/arch/arm/mach-mx3/mx31moboard-devboard.c
+++ b/arch/arm/mach-mx3/mx31moboard-devboard.c
@@ -63,7 +63,7 @@ static struct imxuart_platform_data uart_pdata = {
 
 static int devboard_sdhc2_get_ro(struct device *dev)
 {
-        return gpio_get_value(SDHC2_WP);
+        return !gpio_get_value(SDHC2_WP);
 }
 
 static int devboard_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
diff --git a/arch/arm/mach-mx3/mx31moboard-marxbot.c b/arch/arm/mach-mx3/mx31moboard-marxbot.c
index 641c3d6153ae..901fb0166c0e 100644
--- a/arch/arm/mach-mx3/mx31moboard-marxbot.c
+++ b/arch/arm/mach-mx3/mx31moboard-marxbot.c
@@ -67,7 +67,7 @@ static unsigned int marxbot_pins[] = {
 
 static int marxbot_sdhc2_get_ro(struct device *dev)
 {
-        return gpio_get_value(SDHC2_WP);
+        return !gpio_get_value(SDHC2_WP);
 }
 
 static int marxbot_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
diff --git a/arch/arm/mach-mx3/mx31moboard.c b/arch/arm/mach-mx3/mx31moboard.c
index a17f2e411609..2a2da4739ecf 100644
--- a/arch/arm/mach-mx3/mx31moboard.c
+++ b/arch/arm/mach-mx3/mx31moboard.c
@@ -94,7 +94,7 @@ static struct imxi2c_platform_data moboard_i2c1_pdata = {
 
 static int moboard_sdhc1_get_ro(struct device *dev)
 {
-        return gpio_get_value(SDHC1_WP);
+        return !gpio_get_value(SDHC1_WP);
 }
 
 static int moboard_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
diff --git a/arch/arm/mach-mx3/pcm037_eet.c b/arch/arm/mach-mx3/pcm037_eet.c
index fe52fb1bb8b7..8d386000fc40 100644
--- a/arch/arm/mach-mx3/pcm037_eet.c
+++ b/arch/arm/mach-mx3/pcm037_eet.c
@@ -24,15 +24,6 @@
 #include "devices.h"
 
 static unsigned int pcm037_eet_pins[] = {
-        /* SPI #1 */
-        MX31_PIN_CSPI1_MISO__MISO,
-        MX31_PIN_CSPI1_MOSI__MOSI,
-        MX31_PIN_CSPI1_SCLK__SCLK,
-        MX31_PIN_CSPI1_SPI_RDY__SPI_RDY,
-        MX31_PIN_CSPI1_SS0__SS0,
-        MX31_PIN_CSPI1_SS1__SS1,
-        MX31_PIN_CSPI1_SS2__SS2,
-
         /* Reserve and hardwire GPIO 57 high - S6E63D6 chipselect */
         IOMUX_MODE(MX31_PIN_KEY_COL7, IOMUX_CONFIG_GPIO),
         /* GPIO keys */
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index 9c3fdcdf76c3..8ec2a132904d 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -141,7 +141,7 @@ static inline void board_smc91x_init(void)
 
 static void __init omap_2430sdp_init_irq(void)
 {
-        omap2_init_common_hw(NULL);
+        omap2_init_common_hw(NULL, NULL);
         omap_init_irq();
         omap_gpio_init();
 }
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index 496a90e4ea7a..ac262cd74503 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -169,7 +169,7 @@ static struct platform_device *sdp3430_devices[] __initdata = {
 
 static void __init omap_3430sdp_init_irq(void)
 {
-        omap2_init_common_hw(hyb18m512160af6_sdrc_params);
+        omap2_init_common_hw(hyb18m512160af6_sdrc_params, NULL);
         omap_init_irq();
         omap_gpio_init();
 }
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index 57e477bd89c6..b0c7402248f7 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -59,7 +59,7 @@ static void __init gic_init_irq(void)
 
 static void __init omap_4430sdp_init_irq(void)
 {
-        omap2_init_common_hw(NULL);
+        omap2_init_common_hw(NULL, NULL);
 #ifdef CONFIG_OMAP_32K_TIMER
         omap2_gp_clockevent_set_gptimer(1);
 #endif
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index 06dfba888b0c..dcfc20d03894 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -250,7 +250,7 @@ out:
 
 static void __init omap_apollon_init_irq(void)
 {
-        omap2_init_common_hw(NULL);
+        omap2_init_common_hw(NULL, NULL);
         omap_init_irq();
         omap_gpio_init();
         apollon_init_smc91x();
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 3492162a65c3..fd00aa03690c 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -33,7 +33,7 @@
 
 static void __init omap_generic_init_irq(void)
 {
-        omap2_init_common_hw(NULL);
+        omap2_init_common_hw(NULL, NULL);
         omap_init_irq();
 }
 
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index e7d017cdc438..7b1d61d5bb2c 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -270,7 +270,7 @@ static void __init h4_init_flash(void)
 
 static void __init omap_h4_init_irq(void)
 {
-        omap2_init_common_hw(NULL);
+        omap2_init_common_hw(NULL, NULL);
         omap_init_irq();
         omap_gpio_init();
         h4_init_flash();
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index d8bc0a7dcb8d..ea383f88cb1b 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -270,7 +270,7 @@ static inline void __init ldp_init_smsc911x(void)
 
 static void __init omap_ldp_init_irq(void)
 {
-        omap2_init_common_hw(NULL);
+        omap2_init_common_hw(NULL, NULL);
         omap_init_irq();
         omap_gpio_init();
         ldp_init_smsc911x();
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 991ac9c38032..e00ba128cece 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -282,7 +282,8 @@ static int __init omap3_beagle_i2c_init(void)
 
 static void __init omap3_beagle_init_irq(void)
 {
-        omap2_init_common_hw(mt46h32m32lf6_sdrc_params);
+        omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
+                             mt46h32m32lf6_sdrc_params);
         omap_init_irq();
 #ifdef CONFIG_OMAP_32K_TIMER
         omap2_gp_clockevent_set_gptimer(12);
@@ -408,6 +409,10 @@ static void __init omap3_beagle_init(void)
 
         usb_musb_init();
         omap3beagle_flash_init();
+
+        /* Ensure SDRC pins are mux'd for self-refresh */
+        omap_cfg_reg(H16_34XX_SDRC_CKE0);
+        omap_cfg_reg(H17_34XX_SDRC_CKE1);
 }
 
 static void __init omap3_beagle_map_io(void)
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index cf3dd771a678..c4b144647dc5 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -280,7 +280,7 @@ struct spi_board_info omap3evm_spi_board_info[] = {
 
 static void __init omap3_evm_init_irq(void)
 {
-        omap2_init_common_hw(mt46h32m32lf6_sdrc_params);
+        omap2_init_common_hw(mt46h32m32lf6_sdrc_params, NULL);
         omap_init_irq();
         omap_gpio_init();
         omap3evm_init_smc911x();
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index e32aa23ce962..864ee3d021f7 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -40,6 +40,7 @@
 #include <mach/mcspi.h>
 #include <mach/usb.h>
 #include <mach/keypad.h>
+#include <mach/mux.h>
 
 #include "sdram-micron-mt46h32m32lf-6.h"
 #include "mmc-twl4030.h"
@@ -310,7 +311,8 @@ static int __init omap3pandora_i2c_init(void)
 
 static void __init omap3pandora_init_irq(void)
 {
-        omap2_init_common_hw(mt46h32m32lf6_sdrc_params);
+        omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
+                             mt46h32m32lf6_sdrc_params);
         omap_init_irq();
         omap_gpio_init();
 }
@@ -397,6 +399,10 @@ static void __init omap3pandora_init(void)
         omap3pandora_ads7846_init();
         pandora_keys_gpio_init();
         usb_musb_init();
+
+        /* Ensure SDRC pins are mux'd for self-refresh */
+        omap_cfg_reg(H16_34XX_SDRC_CKE0);
+        omap_cfg_reg(H17_34XX_SDRC_CKE1);
 }
 
 static void __init omap3pandora_map_io(void)
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index dff5528fbfb5..6bce23004aa4 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -44,6 +44,7 @@
 #include <mach/gpmc.h>
 #include <mach/hardware.h>
 #include <mach/nand.h>
+#include <mach/mux.h>
 #include <mach/usb.h>
 
 #include "sdram-micron-mt46h32m32lf-6.h"
@@ -51,6 +52,7 @@
 
 #define OVERO_GPIO_BT_XGATE     15
 #define OVERO_GPIO_W2W_NRESET   16
+#define OVERO_GPIO_PENDOWN      114
 #define OVERO_GPIO_BT_NRESET    164
 #define OVERO_GPIO_USBH_CPEN    168
 #define OVERO_GPIO_USBH_NRESET  183
@@ -146,7 +148,7 @@ static struct platform_device overo_smsc911x_device = {
         .name           = "smsc911x",
         .id             = -1,
         .num_resources  = ARRAY_SIZE(overo_smsc911x_resources),
-        .resource       = &overo_smsc911x_resources,
+        .resource       = overo_smsc911x_resources,
         .dev            = {
                 .platform_data = &overo_smsc911x_config,
         },
@@ -360,7 +362,8 @@ static int __init overo_i2c_init(void)
 
 static void __init overo_init_irq(void)
 {
-        omap2_init_common_hw(mt46h32m32lf6_sdrc_params);
+        omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
+                             mt46h32m32lf6_sdrc_params);
         omap_init_irq();
         omap_gpio_init();
 }
@@ -395,6 +398,10 @@ static void __init overo_init(void)
         overo_ads7846_init();
         overo_init_smsc911x();
 
+        /* Ensure SDRC pins are mux'd for self-refresh */
+        omap_cfg_reg(H16_34XX_SDRC_CKE0);
+        omap_cfg_reg(H17_34XX_SDRC_CKE1);
+
         if ((gpio_request(OVERO_GPIO_W2W_NRESET,
                           "OVERO_GPIO_W2W_NRESET") == 0) &&
             (gpio_direction_output(OVERO_GPIO_W2W_NRESET, 1) == 0)) {
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index 9a0bf6744a05..56d931a425f7 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -278,6 +278,10 @@ static struct twl4030_gpio_platform_data rx51_gpio_data = {
         .setup                  = rx51_twlgpio_setup,
 };
 
+static struct twl4030_usb_data rx51_usb_data = {
+        .usb_mode               = T2_USB_MODE_ULPI,
+};
+
 static struct twl4030_platform_data rx51_twldata = {
         .irq_base               = TWL4030_IRQ_BASE,
         .irq_end                = TWL4030_IRQ_END,
@@ -286,6 +290,7 @@ static struct twl4030_platform_data rx51_twldata = {
         .gpio                   = &rx51_gpio_data,
         .keypad                 = &rx51_kp_data,
         .madc                   = &rx51_madc_data,
+        .usb                    = &rx51_usb_data,
 
         .vaux1                  = &rx51_vaux1,
         .vaux2                  = &rx51_vaux2,
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
index 374ff63c3eb2..1c9e07fe8266 100644
--- a/arch/arm/mach-omap2/board-rx51.c
+++ b/arch/arm/mach-omap2/board-rx51.c
@@ -61,7 +61,7 @@ static struct omap_board_config_kernel rx51_config[] = {
 
 static void __init rx51_init_irq(void)
 {
-        omap2_init_common_hw(NULL);
+        omap2_init_common_hw(NULL, NULL);
         omap_init_irq();
         omap_gpio_init();
 }
@@ -75,6 +75,10 @@ static void __init rx51_init(void)
         omap_serial_init();
         usb_musb_init();
         rx51_peripherals_init();
+
+        /* Ensure SDRC pins are mux'd for self-refresh */
+        omap_cfg_reg(H16_34XX_SDRC_CKE0);
+        omap_cfg_reg(H17_34XX_SDRC_CKE1);
 }
 
 static void __init rx51_map_io(void)
diff --git a/arch/arm/mach-omap2/board-zoom2.c b/arch/arm/mach-omap2/board-zoom2.c
index bcc0f7632dea..427b7b8b1237 100644
--- a/arch/arm/mach-omap2/board-zoom2.c
+++ b/arch/arm/mach-omap2/board-zoom2.c
@@ -25,7 +25,7 @@
 
 static void __init omap_zoom2_init_irq(void)
 {
-        omap2_init_common_hw(NULL);
+        omap2_init_common_hw(NULL, NULL);
         omap_init_irq();
         omap_gpio_init();
 }
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index b0665f161c03..456e2ad5f621 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -27,6 +27,7 @@
 #include <mach/clock.h>
 #include <mach/clockdomain.h>
 #include <mach/cpu.h>
+#include <mach/prcm.h>
 #include <asm/div64.h>
 
 #include <mach/sdrc.h>
@@ -38,8 +39,6 @@
 #include "cm-regbits-24xx.h"
 #include "cm-regbits-34xx.h"
 
-#define MAX_CLOCK_ENABLE_WAIT           100000
-
 /* DPLL rate rounding: minimum DPLL multiplier, divider values */
 #define DPLL_MIN_MULTIPLIER             1
 #define DPLL_MIN_DIVIDER                1
@@ -274,83 +273,97 @@ unsigned long omap2_fixed_divisor_recalc(struct clk *clk)
 }
 
 /**
- * omap2_wait_clock_ready - wait for clock to enable
- * @reg: physical address of clock IDLEST register
- * @mask: value to mask against to determine if the clock is active
- * @name: name of the clock (for printk)
+ * omap2_clk_dflt_find_companion - find companion clock to @clk
+ * @clk: struct clk * to find the companion clock of
+ * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in
+ * @other_bit: u8 ** to return the companion clock bit shift in
+ *
+ * Note: We don't need special code here for INVERT_ENABLE for the
+ * time being since INVERT_ENABLE only applies to clocks enabled by
+ * CM_CLKEN_PLL
  *
- * Returns 1 if the clock enabled in time, or 0 if it failed to enable
- * in roughly MAX_CLOCK_ENABLE_WAIT microseconds.
+ * Convert CM_ICLKEN* <-> CM_FCLKEN*.  This conversion assumes it's
+ * just a matter of XORing the bits.
+ *
+ * Some clocks don't have companion clocks.  For example, modules with
+ * only an interface clock (such as MAILBOXES) don't have a companion
+ * clock.  Right now, this code relies on the hardware exporting a bit
+ * in the correct companion register that indicates that the
+ * nonexistent 'companion clock' is active.  Future patches will
+ * associate this type of code with per-module data structures to
+ * avoid this issue, and remove the casts.  No return value.
  */
-int omap2_wait_clock_ready(void __iomem *reg, u32 mask, const char *name)
+void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg,
+                                   u8 *other_bit)
 {
-        int i = 0;
-        int ena = 0;
+        u32 r;
 
         /*
-         * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
-         * 34xx reverses this, just to keep us on our toes
+         * Convert CM_ICLKEN* <-> CM_FCLKEN*.  This conversion assumes
+         * it's just a matter of XORing the bits.
          */
-        if (cpu_mask & (RATE_IN_242X | RATE_IN_243X))
-                ena = mask;
-        else if (cpu_mask & RATE_IN_343X)
-                ena = 0;
-
-        /* Wait for lock */
-        while (((__raw_readl(reg) & mask) != ena) &&
-               (i++ < MAX_CLOCK_ENABLE_WAIT)) {
-                udelay(1);
-        }
-
-        if (i <= MAX_CLOCK_ENABLE_WAIT)
-                pr_debug("Clock %s stable after %d loops\n", name, i);
-        else
-                printk(KERN_ERR "Clock %s didn't enable in %d tries\n",
-                       name, MAX_CLOCK_ENABLE_WAIT);
-
-
-        return (i < MAX_CLOCK_ENABLE_WAIT) ? 1 : 0;
-};
+        r = ((__force u32)clk->enable_reg ^ (CM_FCLKEN ^ CM_ICLKEN));
 
+        *other_reg = (__force void __iomem *)r;
+        *other_bit = clk->enable_bit;
+}
 
-/*
- * Note: We don't need special code here for INVERT_ENABLE
- * for the time being since INVERT_ENABLE only applies to clocks enabled by
- * CM_CLKEN_PLL
+/**
+ * omap2_clk_dflt_find_idlest - find CM_IDLEST reg va, bit shift for @clk
+ * @clk: struct clk * to find IDLEST info for
+ * @idlest_reg: void __iomem ** to return the CM_IDLEST va in
+ * @idlest_bit: u8 ** to return the CM_IDLEST bit shift in
+ *
+ * Return the CM_IDLEST register address and bit shift corresponding
+ * to the module that "owns" this clock.  This default code assumes
+ * that the CM_IDLEST bit shift is the CM_*CLKEN bit shift, and that
+ * the IDLEST register address ID corresponds to the CM_*CLKEN
+ * register address ID (e.g., that CM_FCLKEN2 corresponds to
+ * CM_IDLEST2).  This is not true for all modules.  No return value.
  */
-static void omap2_clk_wait_ready(struct clk *clk)
+void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg,
+                                u8 *idlest_bit)
 {
-        void __iomem *reg, *other_reg, *st_reg;
-        u32 bit;
+        u32 r;
 
-        /*
-         * REVISIT: This code is pretty ugly.  It would be nice to generalize
-         * it and pull it into struct clk itself somehow.
-         */
-        reg = clk->enable_reg;
+        r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
+        *idlest_reg = (__force void __iomem *)r;
+        *idlest_bit = clk->enable_bit;
+}
 
-        /*
-         * Convert CM_ICLKEN* <-> CM_FCLKEN*.  This conversion assumes
-         * it's just a matter of XORing the bits.
-         */
-        other_reg = (void __iomem *)((u32)reg ^ (CM_FCLKEN ^ CM_ICLKEN));
+/**
+ * omap2_module_wait_ready - wait for an OMAP module to leave IDLE
+ * @clk: struct clk * belonging to the module
+ *
+ * If the necessary clocks for the OMAP hardware IP block that
+ * corresponds to clock @clk are enabled, then wait for the module to
+ * indicate readiness (i.e., to leave IDLE).  This code does not
+ * belong in the clock code and will be moved in the medium term to
+ * module-dependent code.  No return value.
+ */
+static void omap2_module_wait_ready(struct clk *clk)
+{
+        void __iomem *companion_reg, *idlest_reg;
+        u8 other_bit, idlest_bit;
+
+        /* Not all modules have multiple clocks that their IDLEST depends on */
+        if (clk->ops->find_companion) {
+                clk->ops->find_companion(clk, &companion_reg, &other_bit);
+                if (!(__raw_readl(companion_reg) & (1 << other_bit)))
+                        return;
+        }
 
-        /* Check if both functional and interface clocks
-         * are running. */
-        bit = 1 << clk->enable_bit;
-        if (!(__raw_readl(other_reg) & bit))
-                return;
-        st_reg = (void __iomem *)(((u32)other_reg & ~0xf0) | 0x20); /* CM_IDLEST* */
+        clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit);
 
-        omap2_wait_clock_ready(st_reg, bit, clk->name);
+        omap2_cm_wait_idlest(idlest_reg, (1 << idlest_bit), clk->name);
 }
 
-static int omap2_dflt_clk_enable(struct clk *clk)
+int omap2_dflt_clk_enable(struct clk *clk)
 {
         u32 v;
 
         if (unlikely(clk->enable_reg == NULL)) {
-                printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
+                pr_err("clock.c: Enable for %s without enable code\n",
                        clk->name);
                 return 0; /* REVISIT: -EINVAL */
         }
@@ -363,26 +376,13 @@ static int omap2_dflt_clk_enable(struct clk *clk)
         __raw_writel(v, clk->enable_reg);
         v = __raw_readl(clk->enable_reg); /* OCP barrier */
 
-        return 0;
-}
+        if (clk->ops->find_idlest)
+                omap2_module_wait_ready(clk);
 
-static int omap2_dflt_clk_enable_wait(struct clk *clk)
-{
-        int ret;
-
-        if (!clk->enable_reg) {
-                printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
-                       clk->name);
-                return 0; /* REVISIT: -EINVAL */
-        }
-
-        ret = omap2_dflt_clk_enable(clk);
-        if (ret == 0)
-                omap2_clk_wait_ready(clk);
-        return ret;
+        return 0;
 }
 
-static void omap2_dflt_clk_disable(struct clk *clk)
+void omap2_dflt_clk_disable(struct clk *clk)
 {
         u32 v;
 
@@ -406,8 +406,10 @@ static void omap2_dflt_clk_disable(struct clk *clk)
 }
 
 const struct clkops clkops_omap2_dflt_wait = {
-        .enable         = omap2_dflt_clk_enable_wait,
+        .enable         = omap2_dflt_clk_enable,
         .disable        = omap2_dflt_clk_disable,
+        .find_companion = omap2_clk_dflt_find_companion,
+        .find_idlest    = omap2_clk_dflt_find_idlest,
 };
 
 const struct clkops clkops_omap2_dflt = {
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 2679ddfa6424..9ae7540f8af2 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -65,6 +65,12 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
 u32 omap2_get_dpll_rate(struct clk *clk);
 int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name);
 void omap2_clk_prepare_for_reboot(void);
+int omap2_dflt_clk_enable(struct clk *clk);
+void omap2_dflt_clk_disable(struct clk *clk);
+void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg,
+                                   u8 *other_bit);
+void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg,
+                                u8 *idlest_bit);
 
 extern const struct clkops clkops_omap2_dflt_wait;
 extern const struct clkops clkops_omap2_dflt;
diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c
index 44de0271fc2f..bc5d3ac66611 100644
--- a/arch/arm/mach-omap2/clock24xx.c
+++ b/arch/arm/mach-omap2/clock24xx.c
@@ -30,6 +30,7 @@
 
 #include <mach/clock.h>
 #include <mach/sram.h>
+#include <mach/prcm.h>
 #include <asm/div64.h>
 #include <asm/clkdev.h>
 
@@ -43,6 +44,18 @@
 static const struct clkops clkops_oscck;
 static const struct clkops clkops_fixed;
 
+static void omap2430_clk_i2chs_find_idlest(struct clk *clk,
+                                           void __iomem **idlest_reg,
+                                           u8 *idlest_bit);
+
+/* 2430 I2CHS has non-standard IDLEST register */
+static const struct clkops clkops_omap2430_i2chs_wait = {
+        .enable         = omap2_dflt_clk_enable,
+        .disable        = omap2_dflt_clk_disable,
+        .find_idlest    = omap2430_clk_i2chs_find_idlest,
+        .find_companion = omap2_clk_dflt_find_companion,
+};
+
 #include "clock24xx.h"
 
 struct omap_clk {
@@ -240,6 +253,26 @@ static void __iomem *prcm_clksrc_ctrl;
  *-------------------------------------------------------------------------*/
 
 /**
+ * omap2430_clk_i2chs_find_idlest - return CM_IDLEST info for 2430 I2CHS
+ * @clk: struct clk * being enabled
+ * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
+ * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
+ *
+ * OMAP2430 I2CHS CM_IDLEST bits are in CM_IDLEST1_CORE, but the
+ * CM_*CLKEN bits are in CM_{I,F}CLKEN2_CORE.  This custom function
+ * passes back the correct CM_IDLEST register address for I2CHS
+ * modules.  No return value.
+ */
+static void omap2430_clk_i2chs_find_idlest(struct clk *clk,
+                                           void __iomem **idlest_reg,
+                                           u8 *idlest_bit)
+{
+        *idlest_reg = OMAP_CM_REGADDR(CORE_MOD, CM_IDLEST);
+        *idlest_bit = clk->enable_bit;
+}
+
+
+/**
  * omap2xxx_clk_get_core_rate - return the CORE_CLK rate
  * @clk: pointer to the combined dpll_ck + core_ck (currently "dpll_ck")
  *
@@ -325,8 +358,8 @@ static int omap2_clk_fixed_enable(struct clk *clk)
         else if (clk == &apll54_ck)
                 cval = OMAP24XX_ST_54M_APLL;
 
-        omap2_wait_clock_ready(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), cval,
-                            clk->name);
+        omap2_cm_wait_idlest(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), cval,
+                             clk->name);
 
         /*
          * REVISIT: Should we return an error code if omap2_wait_clock_ready()
diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h
index 458f00cdcbea..d19cf7a7d8db 100644
--- a/arch/arm/mach-omap2/clock24xx.h
+++ b/arch/arm/mach-omap2/clock24xx.h
@@ -2337,7 +2337,7 @@ static struct clk i2c2_fck = {
 
 static struct clk i2chs2_fck = {
         .name           = "i2c_fck",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2430_i2chs_wait,
         .id             = 2,
         .parent         = &func_96m_ck,
         .clkdm_name     = "core_l4_clkdm",
@@ -2370,7 +2370,7 @@ static struct clk i2c1_fck = {
 
 static struct clk i2chs1_fck = {
         .name           = "i2c_fck",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2430_i2chs_wait,
         .id             = 1,
         .parent         = &func_96m_ck,
         .clkdm_name     = "core_l4_clkdm",
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 045da923e75b..cd7819cc0c9e 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -2,7 +2,7 @@
  * OMAP3-specific clock framework functions
  *
  * Copyright (C) 2007-2008 Texas Instruments, Inc.
- * Copyright (C) 2007-2008 Nokia Corporation
+ * Copyright (C) 2007-2009 Nokia Corporation
  *
  * Written by Paul Walmsley
  * Testing and integration fixes by Jouni Högander
@@ -41,6 +41,37 @@
 
 static const struct clkops clkops_noncore_dpll_ops;
 
+static void omap3430es2_clk_ssi_find_idlest(struct clk *clk,
+                                            void __iomem **idlest_reg,
+                                            u8 *idlest_bit);
+static void omap3430es2_clk_hsotgusb_find_idlest(struct clk *clk,
+                                            void __iomem **idlest_reg,
+                                            u8 *idlest_bit);
+static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk *clk,
+                                                    void __iomem **idlest_reg,
+                                                    u8 *idlest_bit);
+
+static const struct clkops clkops_omap3430es2_ssi_wait = {
+        .enable         = omap2_dflt_clk_enable,
+        .disable        = omap2_dflt_clk_disable,
+        .find_idlest    = omap3430es2_clk_ssi_find_idlest,
+        .find_companion = omap2_clk_dflt_find_companion,
+};
+
+static const struct clkops clkops_omap3430es2_hsotgusb_wait = {
+        .enable         = omap2_dflt_clk_enable,
+        .disable        = omap2_dflt_clk_disable,
+        .find_idlest    = omap3430es2_clk_hsotgusb_find_idlest,
+        .find_companion = omap2_clk_dflt_find_companion,
+};
+
+static const struct clkops clkops_omap3430es2_dss_usbhost_wait = {
+        .enable         = omap2_dflt_clk_enable,
+        .disable        = omap2_dflt_clk_disable,
+        .find_idlest    = omap3430es2_clk_dss_usbhost_find_idlest,
+        .find_companion = omap2_clk_dflt_find_companion,
+};
+
 #include "clock34xx.h"
 
 struct omap_clk {
@@ -157,10 +188,13 @@ static struct omap_clk omap34xx_clks[] = {
         CLK(NULL,       "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
         CLK(NULL,       "core_12m_fck", &core_12m_fck,  CK_343X),
         CLK("omap_hdq.0", "fck",        &hdq_fck,       CK_343X),
-        CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck,   CK_343X),
-        CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck,   CK_343X),
+        CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es1,   CK_3430ES1),
+        CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es2,   CK_3430ES2),
+        CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck_3430es1,   CK_3430ES1),
+        CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck_3430es2,   CK_3430ES2),
         CLK(NULL,       "core_l3_ick",  &core_l3_ick,   CK_343X),
-        CLK("musb_hdrc",        "ick",  &hsotgusb_ick,  CK_343X),
+        CLK("musb_hdrc",        "ick",  &hsotgusb_ick_3430es1,  CK_3430ES1),
+        CLK("musb_hdrc",        "ick",  &hsotgusb_ick_3430es2,  CK_3430ES2),
         CLK(NULL,       "sdrc_ick",     &sdrc_ick,      CK_343X),
         CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_343X),
         CLK(NULL,       "security_l3_ick", &security_l3_ick, CK_343X),
@@ -193,18 +227,21 @@ static struct omap_clk omap34xx_clks[] = {
         CLK(NULL,       "mailboxes_ick", &mailboxes_ick, CK_343X),
         CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_343X),
         CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick,    CK_343X),
-        CLK(NULL,       "ssi_ick",      &ssi_ick,       CK_343X),
+        CLK(NULL,       "ssi_ick",      &ssi_ick_3430es1,       CK_3430ES1),
+        CLK(NULL,       "ssi_ick",      &ssi_ick_3430es2,       CK_3430ES2),
         CLK(NULL,       "usb_l4_ick",   &usb_l4_ick,    CK_3430ES1),
         CLK(NULL,       "security_l4_ick2", &security_l4_ick2, CK_343X),
         CLK(NULL,       "aes1_ick",     &aes1_ick,      CK_343X),
         CLK("omap_rng", "ick",          &rng_ick,       CK_343X),
         CLK(NULL,       "sha11_ick",    &sha11_ick,     CK_343X),
         CLK(NULL,       "des1_ick",     &des1_ick,      CK_343X),
-        CLK("omapfb",   "dss1_fck",     &dss1_alwon_fck, CK_343X),
+        CLK("omapfb",   "dss1_fck",     &dss1_alwon_fck_3430es1, CK_3430ES1),
+        CLK("omapfb",   "dss1_fck",     &dss1_alwon_fck_3430es2, CK_3430ES2),
         CLK("omapfb",   "tv_fck",       &dss_tv_fck,    CK_343X),
         CLK("omapfb",   "video_fck",    &dss_96m_fck,   CK_343X),
         CLK("omapfb",   "dss2_fck",     &dss2_alwon_fck, CK_343X),
-        CLK("omapfb",   "ick",          &dss_ick,       CK_343X),
+        CLK("omapfb",   "ick",          &dss_ick_3430es1,       CK_3430ES1),
+        CLK("omapfb",   "ick",          &dss_ick_3430es2,       CK_3430ES2),
         CLK(NULL,       "cam_mclk",     &cam_mclk,      CK_343X),
         CLK(NULL,       "cam_ick",      &cam_ick,       CK_343X),
         CLK(NULL,       "csi2_96m_fck", &csi2_96m_fck,  CK_343X),
@@ -301,6 +338,73 @@ static struct omap_clk omap34xx_clks[] = {
 #define SDRC_MPURATE_LOOPS              96
 
 /**
+ * omap3430es2_clk_ssi_find_idlest - return CM_IDLEST info for SSI
+ * @clk: struct clk * being enabled
+ * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
+ * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
+ *
+ * The OMAP3430ES2 SSI target CM_IDLEST bit is at a different shift
+ * from the CM_{I,F}CLKEN bit.  Pass back the correct info via
+ * @idlest_reg and @idlest_bit.  No return value.
+ */
+static void omap3430es2_clk_ssi_find_idlest(struct clk *clk,
+                                            void __iomem **idlest_reg,
+                                            u8 *idlest_bit)
+{
+        u32 r;
+
+        r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
+        *idlest_reg = (__force void __iomem *)r;
+        *idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT;
+}
+
+/**
+ * omap3430es2_clk_dss_usbhost_find_idlest - CM_IDLEST info for DSS, USBHOST
+ * @clk: struct clk * being enabled
+ * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
+ * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
+ *
+ * Some OMAP modules on OMAP3 ES2+ chips have both initiator and
+ * target IDLEST bits.  For our purposes, we are concerned with the
+ * target IDLEST bits, which exist at a different bit position than
+ * the *CLKEN bit position for these modules (DSS and USBHOST) (The
+ * default find_idlest code assumes that they are at the same
+ * position.)  No return value.
+ */
+static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk *clk,
+                                                    void __iomem **idlest_reg,
+                                                    u8 *idlest_bit)
+{
+        u32 r;
+
+        r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
+        *idlest_reg = (__force void __iomem *)r;
+        /* USBHOST_IDLE has same shift */
+        *idlest_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT;
+}
+
+/**
+ * omap3430es2_clk_hsotgusb_find_idlest - return CM_IDLEST info for HSOTGUSB
+ * @clk: struct clk * being enabled
+ * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
+ * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
+ *
+ * The OMAP3430ES2 HSOTGUSB target CM_IDLEST bit is at a different
+ * shift from the CM_{I,F}CLKEN bit.  Pass back the correct info via
+ * @idlest_reg and @idlest_bit.  No return value.
+ */
+static void omap3430es2_clk_hsotgusb_find_idlest(struct clk *clk,
+                                                 void __iomem **idlest_reg,
+                                                 u8 *idlest_bit)
+{
+        u32 r;
+
+        r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
+        *idlest_reg = (__force void __iomem *)r;
+        *idlest_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT;
+}
+
+/**
  * omap3_dpll_recalc - recalculate DPLL rate
  * @clk: DPLL struct clk
  *
@@ -725,7 +829,9 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
         u32 unlock_dll = 0;
         u32 c;
         unsigned long validrate, sdrcrate, mpurate;
-        struct omap_sdrc_params *sp;
+        struct omap_sdrc_params *sdrc_cs0;
+        struct omap_sdrc_params *sdrc_cs1;
+        int ret;
 
         if (!clk || !rate)
                 return -EINVAL;
@@ -743,8 +849,8 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
         else
                 sdrcrate >>= ((clk->rate / rate) >> 1);
 
-        sp = omap2_sdrc_get_params(sdrcrate);
-        if (!sp)
+        ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1);
+        if (ret)
                 return -EINVAL;
 
         if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) {
@@ -765,12 +871,29 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
 
         pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
                  validrate);
-        pr_debug("clock: SDRC timing params used: %08x %08x %08x\n",
-                 sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb);
-
-        omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla,
-                                  sp->actim_ctrlb, new_div, unlock_dll, c,
-                                  sp->mr, rate > clk->rate);
+        pr_debug("clock: SDRC CS0 timing params used:"
+                 " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
+                 sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
+                 sdrc_cs0->actim_ctrlb, sdrc_cs0->mr);
+        if (sdrc_cs1)
+                pr_debug("clock: SDRC CS1 timing params used: "
+                 " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
+                 sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
+                 sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
+
+        if (sdrc_cs1)
+                omap3_configure_core_dpll(
+                                  new_div, unlock_dll, c, rate > clk->rate,
+                                  sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
+                                  sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
+                                  sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
+                                  sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
+        else
+                omap3_configure_core_dpll(
+                                  new_div, unlock_dll, c, rate > clk->rate,
+                                  sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
+                                  sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
+                                  0, 0, 0, 0);
 
         return 0;
 }
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index e433aec4efdd..57cc2725b923 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -1568,7 +1568,7 @@ static const struct clksel ssi_ssr_clksel[] = {
         { .parent = NULL }
 };
 
-static struct clk ssi_ssr_fck = {
+static struct clk ssi_ssr_fck_3430es1 = {
         .name           = "ssi_ssr_fck",
         .ops            = &clkops_omap2_dflt,
         .init           = &omap2_init_clksel_parent,
@@ -1581,10 +1581,31 @@ static struct clk ssi_ssr_fck = {
         .recalc         = &omap2_clksel_recalc,
 };
 
-static struct clk ssi_sst_fck = {
+static struct clk ssi_ssr_fck_3430es2 = {
+        .name           = "ssi_ssr_fck",
+        .ops            = &clkops_omap3430es2_ssi_wait,
+        .init           = &omap2_init_clksel_parent,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_SSI_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
+        .clksel         = ssi_ssr_clksel,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk ssi_sst_fck_3430es1 = {
         .name           = "ssi_sst_fck",
         .ops            = &clkops_null,
-        .parent         = &ssi_ssr_fck,
+        .parent         = &ssi_ssr_fck_3430es1,
+        .fixed_div      = 2,
+        .recalc         = &omap2_fixed_divisor_recalc,
+};
+
+static struct clk ssi_sst_fck_3430es2 = {
+        .name           = "ssi_sst_fck",
+        .ops            = &clkops_null,
+        .parent         = &ssi_ssr_fck_3430es2,
         .fixed_div      = 2,
         .recalc         = &omap2_fixed_divisor_recalc,
 };
@@ -1606,9 +1627,19 @@ static struct clk core_l3_ick = {
         .recalc         = &followparent_recalc,
 };
 
-static struct clk hsotgusb_ick = {
+static struct clk hsotgusb_ick_3430es1 = {
         .name           = "hsotgusb_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_dflt,
+        .parent         = &core_l3_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
+        .clkdm_name     = "core_l3_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk hsotgusb_ick_3430es2 = {
+        .name           = "hsotgusb_ick",
+        .ops            = &clkops_omap3430es2_hsotgusb_wait,
         .parent         = &core_l3_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
@@ -1947,7 +1978,7 @@ static struct clk ssi_l4_ick = {
         .recalc         = &followparent_recalc,
 };
 
-static struct clk ssi_ick = {
+static struct clk ssi_ick_3430es1 = {
         .name           = "ssi_ick",
         .ops            = &clkops_omap2_dflt,
         .parent         = &ssi_l4_ick,
@@ -1957,6 +1988,16 @@ static struct clk ssi_ick = {
         .recalc         = &followparent_recalc,
 };
 
+static struct clk ssi_ick_3430es2 = {
+        .name           = "ssi_ick",
+        .ops            = &clkops_omap3430es2_ssi_wait,
+        .parent         = &ssi_l4_ick,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+        .enable_bit     = OMAP3430_EN_SSI_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
 /* REVISIT: Technically the TRM claims that this is CORE_CLK based,
  * but l4_ick makes more sense to me */
 
@@ -2024,7 +2065,7 @@ static struct clk des1_ick = {
 };
 
 /* DSS */
-static struct clk dss1_alwon_fck = {
+static struct clk dss1_alwon_fck_3430es1 = {
         .name           = "dss1_alwon_fck",
         .ops            = &clkops_omap2_dflt,
         .parent         = &dpll4_m4x2_ck,
@@ -2034,6 +2075,16 @@ static struct clk dss1_alwon_fck = {
         .recalc         = &followparent_recalc,
 };
 
+static struct clk dss1_alwon_fck_3430es2 = {
+        .name           = "dss1_alwon_fck",
+        .ops            = &clkops_omap3430es2_dss_usbhost_wait,
+        .parent         = &dpll4_m4x2_ck,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
+        .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
+        .clkdm_name     = "dss_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
 static struct clk dss_tv_fck = {
         .name           = "dss_tv_fck",
         .ops            = &clkops_omap2_dflt,
@@ -2067,7 +2118,7 @@ static struct clk dss2_alwon_fck = {
         .recalc         = &followparent_recalc,
 };
 
-static struct clk dss_ick = {
+static struct clk dss_ick_3430es1 = {
         /* Handles both L3 and L4 clocks */
         .name           = "dss_ick",
         .ops            = &clkops_omap2_dflt,
@@ -2079,6 +2130,18 @@ static struct clk dss_ick = {
         .recalc         = &followparent_recalc,
 };
 
+static struct clk dss_ick_3430es2 = {
+        /* Handles both L3 and L4 clocks */
+        .name           = "dss_ick",
+        .ops            = &clkops_omap3430es2_dss_usbhost_wait,
+        .parent         = &l4_ick,
+        .init           = &omap2_init_clk_clkdm,
+        .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
+        .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
+        .clkdm_name     = "dss_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
 /* CAM */
 
 static struct clk cam_mclk = {
@@ -2118,7 +2181,7 @@ static struct clk csi2_96m_fck = {
 
 static struct clk usbhost_120m_fck = {
         .name           = "usbhost_120m_fck",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_dflt,
         .parent         = &dpll5_m2_ck,
         .init           = &omap2_init_clk_clkdm,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
@@ -2129,7 +2192,7 @@ static struct clk usbhost_120m_fck = {
 
 static struct clk usbhost_48m_fck = {
         .name           = "usbhost_48m_fck",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap3430es2_dss_usbhost_wait,
         .parent         = &omap_48m_fck,
         .init           = &omap2_init_clk_clkdm,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
@@ -2141,7 +2204,7 @@ static struct clk usbhost_48m_fck = {
 static struct clk usbhost_ick = {
         /* Handles both L3 and L4 clocks */
         .name           = "usbhost_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap3430es2_dss_usbhost_wait,
         .parent         = &l4_ick,
         .init           = &omap2_init_clk_clkdm,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h
index 1d3c93bf86d3..f3c91a1ca391 100644
--- a/arch/arm/mach-omap2/cm.h
+++ b/arch/arm/mach-omap2/cm.h
@@ -29,9 +29,9 @@
  * These registers appear once per CM module.
  */
 
-#define OMAP3430_CM_REVISION            OMAP_CM_REGADDR(OCP_MOD, 0x0000)
-#define OMAP3430_CM_SYSCONFIG           OMAP_CM_REGADDR(OCP_MOD, 0x0010)
-#define OMAP3430_CM_POLCTRL             OMAP_CM_REGADDR(OCP_MOD, 0x009c)
+#define OMAP3430_CM_REVISION            OMAP34XX_CM_REGADDR(OCP_MOD, 0x0000)
+#define OMAP3430_CM_SYSCONFIG           OMAP34XX_CM_REGADDR(OCP_MOD, 0x0010)
+#define OMAP3430_CM_POLCTRL             OMAP34XX_CM_REGADDR(OCP_MOD, 0x009c)
 
 #define OMAP3_CM_CLKOUT_CTRL_OFFSET     0x0070
 #define OMAP3430_CM_CLKOUT_CTRL         OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 3a86b0f66031..e9b9bcb19b4e 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -276,14 +276,15 @@ static int __init _omap2_init_reprogram_sdrc(void)
         return v;
 }
 
-void __init omap2_init_common_hw(struct omap_sdrc_params *sp)
+void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
+                                 struct omap_sdrc_params *sdrc_cs1)
 {
         omap2_mux_init();
 #ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once the clkdev is ready */
         pwrdm_init(powerdomains_omap);
         clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps);
         omap2_clk_init();
-        omap2_sdrc_init(sp);
+        omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
         _omap2_init_reprogram_sdrc();
 #endif
         gpmc_init();
diff --git a/arch/arm/mach-omap2/mmc-twl4030.c b/arch/arm/mach-omap2/mmc-twl4030.c
index 1541fd4c8d0f..3c04c2f1b23f 100644
--- a/arch/arm/mach-omap2/mmc-twl4030.c
+++ b/arch/arm/mach-omap2/mmc-twl4030.c
@@ -119,6 +119,7 @@ static int twl_mmc_late_init(struct device *dev)
                                 if (i != 0)
                                         break;
                                 ret = PTR_ERR(reg);
+                                hsmmc[i].vcc = NULL;
                                 goto err;
                         }
                         hsmmc[i].vcc = reg;
@@ -165,8 +166,13 @@ done:
 static void twl_mmc_cleanup(struct device *dev)
 {
         struct omap_mmc_platform_data *mmc = dev->platform_data;
+        int i;
 
         gpio_free(mmc->slots[0].switch_pin);
+        for(i = 0; i < ARRAY_SIZE(hsmmc); i++) {
+                regulator_put(hsmmc[i].vcc);
+                regulator_put(hsmmc[i].vcc_aux);
+        }
 }
 
 #ifdef CONFIG_PM
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 026c4fc883a7..43d6b92b65f2 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -486,6 +486,12 @@ MUX_CFG_34XX("H19_34XX_GPIO164_OUT", 0x19c,
                 OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT)
 MUX_CFG_34XX("J25_34XX_GPIO170", 0x1c6,
                 OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
+
+/* OMAP3 SDRC CKE signals to SDR/DDR ram chips */
+MUX_CFG_34XX("H16_34XX_SDRC_CKE0", 0x262,
+                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT)
+MUX_CFG_34XX("H17_34XX_SDRC_CKE1", 0x264,
+                OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT)
 };
 
 #define OMAP34XX_PINS_SZ        ARRAY_SIZE(omap34xx_pins)
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index f7b3baf76678..21201cd4117b 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -11,9 +11,6 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_PM_H
 #define __ARCH_ARM_MACH_OMAP2_PM_H
 
-extern int omap2_pm_init(void);
-extern int omap3_pm_init(void);
-
 #ifdef CONFIG_PM_DEBUG
 extern void omap2_pm_dump(int mode, int resume, unsigned int us);
 extern int omap2_pm_debug;
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index db1025562fb0..528dbdc26e23 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -470,7 +470,7 @@ static void __init prcm_setup_regs(void)
                           WKUP_MOD, PM_WKEN);
 }
 
-int __init omap2_pm_init(void)
+static int __init omap2_pm_init(void)
 {
         u32 l;
 
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 841d4c5ed8be..488d595d8e4b 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -39,7 +39,9 @@
 struct power_state {
         struct powerdomain *pwrdm;
         u32 next_state;
+#ifdef CONFIG_SUSPEND
         u32 saved_state;
+#endif
         struct list_head node;
 };
 
@@ -293,6 +295,9 @@ out:
         local_irq_enable();
 }
 
+#ifdef CONFIG_SUSPEND
+static suspend_state_t suspend_state;
+
 static int omap3_pm_prepare(void)
 {
         disable_hlt();
@@ -321,7 +326,6 @@ static int omap3_pm_suspend(void)
 restore:
         /* Restore next_pwrsts */
         list_for_each_entry(pwrst, &pwrst_list, node) {
-                set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
                 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
                 if (state > pwrst->next_state) {
                         printk(KERN_INFO "Powerdomain (%s) didn't enter "
@@ -329,6 +333,7 @@ restore:
                                pwrst->pwrdm->name, pwrst->next_state);
                         ret = -1;
                 }
+                set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
         }
         if (ret)
                 printk(KERN_ERR "Could not enter target state in pm_suspend\n");
@@ -339,11 +344,11 @@ restore:
         return ret;
 }
 
-static int omap3_pm_enter(suspend_state_t state)
+static int omap3_pm_enter(suspend_state_t unused)
 {
         int ret = 0;
 
-        switch (state) {
+        switch (suspend_state) {
         case PM_SUSPEND_STANDBY:
         case PM_SUSPEND_MEM:
                 ret = omap3_pm_suspend();
@@ -360,12 +365,30 @@ static void omap3_pm_finish(void)
         enable_hlt();
 }
 
+/* Hooks to enable / disable UART interrupts during suspend */
+static int omap3_pm_begin(suspend_state_t state)
+{
+        suspend_state = state;
+        omap_uart_enable_irqs(0);
+        return 0;
+}
+
+static void omap3_pm_end(void)
+{
+        suspend_state = PM_SUSPEND_ON;
+        omap_uart_enable_irqs(1);
+        return;
+}
+
 static struct platform_suspend_ops omap_pm_ops = {
+        .begin          = omap3_pm_begin,
+        .end            = omap3_pm_end,
         .prepare        = omap3_pm_prepare,
         .enter          = omap3_pm_enter,
         .finish         = omap3_pm_finish,
         .valid          = suspend_valid_only_mem,
 };
+#endif /* CONFIG_SUSPEND */
 
 
 /**
@@ -613,6 +636,24 @@ static void __init prcm_setup_regs(void)
         /* Clear any pending PRCM interrupts */
         prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 
+        /* Don't attach IVA interrupts */
+        prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
+        prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
+        prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
+        prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
+
+        /* Clear any pending 'reset' flags */
+        prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST);
+        prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST);
+        prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST);
+        prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST);
+        prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST);
+        prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST);
+        prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST);
+
+        /* Clear any pending PRCM interrupts */
+        prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
+
         omap3_iva_idle();
         omap3_d2d_idle();
 }
@@ -652,7 +693,7 @@ static int __init clkdms_setup(struct clockdomain *clkdm)
         return 0;
 }
 
-int __init omap3_pm_init(void)
+static int __init omap3_pm_init(void)
 {
         struct power_state *pwrst, *tmp;
         int ret;
@@ -692,7 +733,9 @@ int __init omap3_pm_init(void)
         _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend,
                                          omap34xx_cpu_suspend_sz);
 
+#ifdef CONFIG_SUSPEND
         suspend_set_ops(&omap_pm_ops);
+#endif /* CONFIG_SUSPEND */
 
         pm_idle = omap3_pm_idle;
 
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index f945156d5585..ced555a4cd1a 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -17,6 +17,7 @@
 #include <linux/init.h>
 #include <linux/clk.h>
 #include <linux/io.h>
+#include <linux/delay.h>
 
 #include <mach/common.h>
 #include <mach/prcm.h>
@@ -28,6 +29,8 @@
 static void __iomem *prm_base;
 static void __iomem *cm_base;
 
+#define MAX_MODULE_ENABLE_WAIT          100000
+
 u32 omap_prcm_get_reset_sources(void)
 {
         /* XXX This presumably needs modification for 34XX */
@@ -120,6 +123,46 @@ u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
 }
 EXPORT_SYMBOL(cm_rmw_mod_reg_bits);
 
+/**
+ * omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness
+ * @reg: physical address of module IDLEST register
+ * @mask: value to mask against to determine if the module is active
+ * @name: name of the clock (for printk)
+ *
+ * Returns 1 if the module indicated readiness in time, or 0 if it
+ * failed to enable in roughly MAX_MODULE_ENABLE_WAIT microseconds.
+ */
+int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, const char *name)
+{
+        int i = 0;
+        int ena = 0;
+
+        /*
+         * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
+         * 34xx reverses this, just to keep us on our toes
+         */
+        if (cpu_is_omap24xx())
+                ena = mask;
+        else if (cpu_is_omap34xx())
+                ena = 0;
+        else
+                BUG();
+
+        /* Wait for lock */
+        while (((__raw_readl(reg) & mask) != ena) &&
+               (i++ < MAX_MODULE_ENABLE_WAIT))
+                udelay(1);
+
+        if (i < MAX_MODULE_ENABLE_WAIT)
+                pr_debug("cm: Module associated with clock %s ready after %d "
+                         "loops\n", name, i);
+        else
+                pr_err("cm: Module associated with clock %s didn't enable in "
+                       "%d tries\n", name, MAX_MODULE_ENABLE_WAIT);
+
+        return (i < MAX_MODULE_ENABLE_WAIT) ? 1 : 0;
+};
+
 void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
 {
         prm_base = omap2_globals->prm;
diff --git a/arch/arm/mach-omap2/sdrc.c b/arch/arm/mach-omap2/sdrc.c
index 2045441e8385..9e3bd4fa7810 100644
--- a/arch/arm/mach-omap2/sdrc.c
+++ b/arch/arm/mach-omap2/sdrc.c
@@ -32,7 +32,7 @@
 #include <mach/sdrc.h>
 #include "sdrc.h"
 
-static struct omap_sdrc_params *sdrc_init_params;
+static struct omap_sdrc_params *sdrc_init_params_cs0, *sdrc_init_params_cs1;
 
 void __iomem *omap2_sdrc_base;
 void __iomem *omap2_sms_base;
@@ -45,33 +45,49 @@ void __iomem *omap2_sms_base;
 /**
  * omap2_sdrc_get_params - return SDRC register values for a given clock rate
  * @r: SDRC clock rate (in Hz)
+ * @sdrc_cs0: chip select 0 ram timings **
+ * @sdrc_cs1: chip select 1 ram timings **
  *
  * Return pre-calculated values for the SDRC_ACTIM_CTRLA,
- * SDRC_ACTIM_CTRLB, SDRC_RFR_CTRL, and SDRC_MR registers, for a given
- * SDRC clock rate 'r'.  These parameters control various timing
- * delays in the SDRAM controller that are expressed in terms of the
- * number of SDRC clock cycles to wait; hence the clock rate
- * dependency. Note that sdrc_init_params must be sorted rate
- * descending.  Also assumes that both chip-selects use the same
- * timing parameters.  Returns a struct omap_sdrc_params * upon
- * success, or NULL upon failure.
+ *  SDRC_ACTIM_CTRLB, SDRC_RFR_CTRL and SDRC_MR registers in sdrc_cs[01]
+ *  structs,for a given SDRC clock rate 'r'.
+ * These parameters control various timing delays in the SDRAM controller
+ *  that are expressed in terms of the number of SDRC clock cycles to
+ *  wait; hence the clock rate dependency.
+ *
+ * Supports 2 different timing parameters for both chip selects.
+ *
+ * Note 1: the sdrc_init_params_cs[01] must be sorted rate descending.
+ * Note 2: If sdrc_init_params_cs_1 is not NULL it must be of same size
+ *  as sdrc_init_params_cs_0.
+ *
+ * Fills in the struct omap_sdrc_params * for each chip select.
+ * Returns 0 upon success or -1 upon failure.
  */
-struct omap_sdrc_params *omap2_sdrc_get_params(unsigned long r)
+int omap2_sdrc_get_params(unsigned long r,
+                          struct omap_sdrc_params **sdrc_cs0,
+                          struct omap_sdrc_params **sdrc_cs1)
 {
-        struct omap_sdrc_params *sp;
+        struct omap_sdrc_params *sp0, *sp1;
 
-        if (!sdrc_init_params)
-                return NULL;
+        if (!sdrc_init_params_cs0)
+                return -1;
 
-        sp = sdrc_init_params;
+        sp0 = sdrc_init_params_cs0;
+        sp1 = sdrc_init_params_cs1;
 
-        while (sp->rate && sp->rate != r)
-                sp++;
+        while (sp0->rate && sp0->rate != r) {
+                sp0++;
+                if (sdrc_init_params_cs1)
+                        sp1++;
+        }
 
-        if (!sp->rate)
-                return NULL;
+        if (!sp0->rate)
+                return -1;
 
-        return sp;
+        *sdrc_cs0 = sp0;
+        *sdrc_cs1 = sp1;
+        return 0;
 }
 
 
@@ -83,13 +99,15 @@ void __init omap2_set_globals_sdrc(struct omap_globals *omap2_globals)
 
 /**
  * omap2_sdrc_init - initialize SMS, SDRC devices on boot
- * @sp: pointer to a null-terminated list of struct omap_sdrc_params
+ * @sdrc_cs[01]: pointers to a null-terminated list of struct omap_sdrc_params
+ *  Support for 2 chip selects timings
  *
  * Turn on smart idle modes for SDRAM scheduler and controller.
  * Program a known-good configuration for the SDRC to deal with buggy
  * bootloaders.
  */
-void __init omap2_sdrc_init(struct omap_sdrc_params *sp)
+void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
+                            struct omap_sdrc_params *sdrc_cs1)
 {
         u32 l;
 
@@ -103,11 +121,15 @@ void __init omap2_sdrc_init(struct omap_sdrc_params *sp)
         l |= (0x2 << 3);
         sdrc_write_reg(l, SDRC_SYSCONFIG);
 
-        sdrc_init_params = sp;
+        sdrc_init_params_cs0 = sdrc_cs0;
+        sdrc_init_params_cs1 = sdrc_cs1;
 
         /* XXX Enable SRFRONIDLEREQ here also? */
+        /*
+         * PWDENA should not be set due to 34xx erratum 1.150 - PWDENA
+         * can cause random memory corruption
+         */
         l = (1 << SDRC_POWER_EXTCLKDIS_SHIFT) |
-                (1 << SDRC_POWER_PWDENA_SHIFT) |
                 (1 << SDRC_POWER_PAGEPOLICY_SHIFT);
         sdrc_write_reg(l, SDRC_POWER);
 }
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index b094c15bfe47..a7421a50410b 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -54,6 +54,7 @@ struct omap_uart_state {
 
         struct plat_serial8250_port *p;
         struct list_head node;
+        struct platform_device pdev;
 
 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
         int context_valid;
@@ -68,10 +69,9 @@ struct omap_uart_state {
 #endif
 };
 
-static struct omap_uart_state omap_uart[OMAP_MAX_NR_PORTS];
 static LIST_HEAD(uart_list);
 
-static struct plat_serial8250_port serial_platform_data[] = {
+static struct plat_serial8250_port serial_platform_data0[] = {
         {
                 .membase        = IO_ADDRESS(OMAP_UART1_BASE),
                 .mapbase        = OMAP_UART1_BASE,
@@ -81,6 +81,12 @@ static struct plat_serial8250_port serial_platform_data[] = {
                 .regshift       = 2,
                 .uartclk        = OMAP24XX_BASE_BAUD * 16,
         }, {
+                .flags          = 0
+        }
+};
+
+static struct plat_serial8250_port serial_platform_data1[] = {
+        {
                 .membase        = IO_ADDRESS(OMAP_UART2_BASE),
                 .mapbase        = OMAP_UART2_BASE,
                 .irq            = 73,
@@ -89,6 +95,12 @@ static struct plat_serial8250_port serial_platform_data[] = {
                 .regshift       = 2,
                 .uartclk        = OMAP24XX_BASE_BAUD * 16,
         }, {
+                .flags          = 0
+        }
+};
+
+static struct plat_serial8250_port serial_platform_data2[] = {
+        {
                 .membase        = IO_ADDRESS(OMAP_UART3_BASE),
                 .mapbase        = OMAP_UART3_BASE,
                 .irq            = 74,
@@ -217,6 +229,40 @@ static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
         clk_disable(uart->fck);
 }
 
+static void omap_uart_enable_wakeup(struct omap_uart_state *uart)
+{
+        /* Set wake-enable bit */
+        if (uart->wk_en && uart->wk_mask) {
+                u32 v = __raw_readl(uart->wk_en);
+                v |= uart->wk_mask;
+                __raw_writel(v, uart->wk_en);
+        }
+
+        /* Ensure IOPAD wake-enables are set */
+        if (cpu_is_omap34xx() && uart->padconf) {
+                u16 v = omap_ctrl_readw(uart->padconf);
+                v |= OMAP3_PADCONF_WAKEUPENABLE0;
+                omap_ctrl_writew(v, uart->padconf);
+        }
+}
+
+static void omap_uart_disable_wakeup(struct omap_uart_state *uart)
+{
+        /* Clear wake-enable bit */
+        if (uart->wk_en && uart->wk_mask) {
+                u32 v = __raw_readl(uart->wk_en);
+                v &= ~uart->wk_mask;
+                __raw_writel(v, uart->wk_en);
+        }
+
+        /* Ensure IOPAD wake-enables are cleared */
+        if (cpu_is_omap34xx() && uart->padconf) {
+                u16 v = omap_ctrl_readw(uart->padconf);
+                v &= ~OMAP3_PADCONF_WAKEUPENABLE0;
+                omap_ctrl_writew(v, uart->padconf);
+        }
+}
+
 static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
                                           int enable)
 {
@@ -246,6 +292,11 @@ static void omap_uart_block_sleep(struct omap_uart_state *uart)
 
 static void omap_uart_allow_sleep(struct omap_uart_state *uart)
 {
+        if (device_may_wakeup(&uart->pdev.dev))
+                omap_uart_enable_wakeup(uart);
+        else
+                omap_uart_disable_wakeup(uart);
+
         if (!uart->clocked)
                 return;
 
@@ -292,7 +343,6 @@ void omap_uart_resume_idle(int num)
                         /* Check for normal UART wakeup */
                         if (__raw_readl(uart->wk_st) & uart->wk_mask)
                                 omap_uart_block_sleep(uart);
-
                         return;
                 }
         }
@@ -346,16 +396,13 @@ static irqreturn_t omap_uart_interrupt(int irq, void *dev_id)
         return IRQ_NONE;
 }
 
-static u32 sleep_timeout = DEFAULT_TIMEOUT;
-
 static void omap_uart_idle_init(struct omap_uart_state *uart)
 {
-        u32 v;
         struct plat_serial8250_port *p = uart->p;
         int ret;
 
         uart->can_sleep = 0;
-        uart->timeout = sleep_timeout;
+        uart->timeout = DEFAULT_TIMEOUT;
         setup_timer(&uart->timer, omap_uart_idle_timer,
                     (unsigned long) uart);
         mod_timer(&uart->timer, jiffies + uart->timeout);
@@ -413,76 +460,101 @@ static void omap_uart_idle_init(struct omap_uart_state *uart)
                 uart->padconf = 0;
         }
 
-        /* Set wake-enable bit */
-        if (uart->wk_en && uart->wk_mask) {
-                v = __raw_readl(uart->wk_en);
-                v |= uart->wk_mask;
-                __raw_writel(v, uart->wk_en);
-        }
-
-        /* Ensure IOPAD wake-enables are set */
-        if (cpu_is_omap34xx() && uart->padconf) {
-                u16 v;
-
-                v = omap_ctrl_readw(uart->padconf);
-                v |= OMAP3_PADCONF_WAKEUPENABLE0;
-                omap_ctrl_writew(v, uart->padconf);
-        }
-
         p->flags |= UPF_SHARE_IRQ;
         ret = request_irq(p->irq, omap_uart_interrupt, IRQF_SHARED,
                           "serial idle", (void *)uart);
         WARN_ON(ret);
 }
 
-static ssize_t sleep_timeout_show(struct kobject *kobj,
-                                  struct kobj_attribute *attr,
+void omap_uart_enable_irqs(int enable)
+{
+        int ret;
+        struct omap_uart_state *uart;
+
+        list_for_each_entry(uart, &uart_list, node) {
+                if (enable)
+                        ret = request_irq(uart->p->irq, omap_uart_interrupt,
+                                IRQF_SHARED, "serial idle", (void *)uart);
+                else
+                        free_irq(uart->p->irq, (void *)uart);
+        }
+}
+
+static ssize_t sleep_timeout_show(struct device *dev,
+                                  struct device_attribute *attr,
                                   char *buf)
 {
-        return sprintf(buf, "%u\n", sleep_timeout / HZ);
+        struct platform_device *pdev = container_of(dev,
+                                        struct platform_device, dev);
+        struct omap_uart_state *uart = container_of(pdev,
+                                        struct omap_uart_state, pdev);
+
+        return sprintf(buf, "%u\n", uart->timeout / HZ);
 }
 
-static ssize_t sleep_timeout_store(struct kobject *kobj,
-                                   struct kobj_attribute *attr,
+static ssize_t sleep_timeout_store(struct device *dev,
+                                   struct device_attribute *attr,
                                    const char *buf, size_t n)
 {
-        struct omap_uart_state *uart;
+        struct platform_device *pdev = container_of(dev,
+                                        struct platform_device, dev);
+        struct omap_uart_state *uart = container_of(pdev,
+                                        struct omap_uart_state, pdev);
         unsigned int value;
 
         if (sscanf(buf, "%u", &value) != 1) {
                 printk(KERN_ERR "sleep_timeout_store: Invalid value\n");
                 return -EINVAL;
         }
-        sleep_timeout = value * HZ;
-        list_for_each_entry(uart, &uart_list, node) {
-                uart->timeout = sleep_timeout;
-                if (uart->timeout)
-                        mod_timer(&uart->timer, jiffies + uart->timeout);
-                else
-                        /* A zero value means disable timeout feature */
-                        omap_uart_block_sleep(uart);
-        }
+
+        uart->timeout = value * HZ;
+        if (uart->timeout)
+                mod_timer(&uart->timer, jiffies + uart->timeout);
+        else
+                /* A zero value means disable timeout feature */
+                omap_uart_block_sleep(uart);
+
         return n;
 }
 
-static struct kobj_attribute sleep_timeout_attr =
-        __ATTR(sleep_timeout, 0644, sleep_timeout_show, sleep_timeout_store);
-
+DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show, sleep_timeout_store);
+#define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr))
 #else
 static inline void omap_uart_idle_init(struct omap_uart_state *uart) {}
+#define DEV_CREATE_FILE(dev, attr)
 #endif /* CONFIG_PM */
 
-static struct platform_device serial_device = {
-        .name                   = "serial8250",
-        .id                     = PLAT8250_DEV_PLATFORM,
-        .dev                    = {
-                .platform_data  = serial_platform_data,
+static struct omap_uart_state omap_uart[OMAP_MAX_NR_PORTS] = {
+        {
+                .pdev = {
+                        .name                   = "serial8250",
+                        .id                     = PLAT8250_DEV_PLATFORM,
+                        .dev                    = {
+                                .platform_data  = serial_platform_data0,
+                        },
+                },
+        }, {
+                .pdev = {
+                        .name                   = "serial8250",
+                        .id                     = PLAT8250_DEV_PLATFORM1,
+                        .dev                    = {
+                                .platform_data  = serial_platform_data1,
+                        },
+                },
+        }, {
+                .pdev = {
+                        .name                   = "serial8250",
+                        .id                     = PLAT8250_DEV_PLATFORM2,
+                        .dev                    = {
+                                .platform_data  = serial_platform_data2,
+                        },
+                },
         },
 };
 
 void __init omap_serial_init(void)
 {
-        int i, err;
+        int i;
         const struct omap_uart_config *info;
         char name[16];
 
@@ -496,14 +568,12 @@ void __init omap_serial_init(void)
 
         if (info == NULL)
                 return;
-        if (cpu_is_omap44xx()) {
-                for (i = 0; i < OMAP_MAX_NR_PORTS; i++)
-                        serial_platform_data[i].irq += 32;
-        }
 
         for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
-                struct plat_serial8250_port *p = serial_platform_data + i;
                 struct omap_uart_state *uart = &omap_uart[i];
+                struct platform_device *pdev = &uart->pdev;
+                struct device *dev = &pdev->dev;
+                struct plat_serial8250_port *p = dev->platform_data;
 
                 if (!(info->enabled_uarts & (1 << i))) {
                         p->membase = NULL;
@@ -531,20 +601,21 @@ void __init omap_serial_init(void)
                 uart->num = i;
                 p->private_data = uart;
                 uart->p = p;
-                list_add(&uart->node, &uart_list);
+                list_add_tail(&uart->node, &uart_list);
+
+                if (cpu_is_omap44xx())
+                        p->irq += 32;
 
                 omap_uart_enable_clocks(uart);
                 omap_uart_reset(uart);
                 omap_uart_idle_init(uart);
-        }
-
-        err = platform_device_register(&serial_device);
-
-#ifdef CONFIG_PM
-        if (!err)
-                err = sysfs_create_file(&serial_device.dev.kobj,
-                                        &sleep_timeout_attr.attr);
-#endif
 
+                if (WARN_ON(platform_device_register(pdev)))
+                        continue;
+                if ((cpu_is_omap34xx() && uart->padconf) ||
+                    (uart->wk_en && uart->wk_mask)) {
+                        device_init_wakeup(dev, true);
+                        DEV_CREATE_FILE(dev, &dev_attr_sleep_timeout);
+                }
+        }
 }
-
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
index f41f8d96ddba..82aa4a3d160c 100644
--- a/arch/arm/mach-omap2/sram34xx.S
+++ b/arch/arm/mach-omap2/sram34xx.S
@@ -36,7 +36,7 @@
 
         .text
 
-/* r4 parameters */
+/* r1 parameters */
 #define SDRC_NO_UNLOCK_DLL              0x0
 #define SDRC_UNLOCK_DLL                 0x1
 
@@ -58,7 +58,6 @@
 
 /* SDRC_POWER bit settings */
 #define SRFRONIDLEREQ_MASK              0x40
-#define PWDENA_MASK                     0x4
 
 /* CM_IDLEST1_CORE bit settings */
 #define ST_SDRC_MASK                    0x2
@@ -71,41 +70,72 @@
 
 /*
  * omap3_sram_configure_core_dpll - change DPLL3 M2 divider
- * r0 = new SDRC_RFR_CTRL register contents
- * r1 = new SDRC_ACTIM_CTRLA register contents
- * r2 = new SDRC_ACTIM_CTRLB register contents
- * r3 = new M2 divider setting (only 1 and 2 supported right now)
- * r4 = unlock SDRC DLL? (1 = yes, 0 = no).  Only unlock DLL for
+ *
+ * Params passed in registers:
+ *  r0 = new M2 divider setting (only 1 and 2 supported right now)
+ *  r1 = unlock SDRC DLL? (1 = yes, 0 = no).  Only unlock DLL for
  *      SDRC rates < 83MHz
- * r5 = number of MPU cycles to wait for SDRC to stabilize after
+ *  r2 = number of MPU cycles to wait for SDRC to stabilize after
  *      reprogramming the SDRC when switching to a slower MPU speed
- * r6 = new SDRC_MR_0 register value
- * r7 = increasing SDRC rate? (1 = yes, 0 = no)
+ *  r3 = increasing SDRC rate? (1 = yes, 0 = no)
+ *
+ * Params passed via the stack. The needed params will be copied in SRAM
+ *  before use by the code in SRAM (SDRAM is not accessible during SDRC
+ *  reconfiguration):
+ *  new SDRC_RFR_CTRL_0 register contents
+ *  new SDRC_ACTIM_CTRL_A_0 register contents
+ *  new SDRC_ACTIM_CTRL_B_0 register contents
+ *  new SDRC_MR_0 register value
+ *  new SDRC_RFR_CTRL_1 register contents
+ *  new SDRC_ACTIM_CTRL_A_1 register contents
+ *  new SDRC_ACTIM_CTRL_B_1 register contents
+ *  new SDRC_MR_1 register value
  *
+ * If the param SDRC_RFR_CTRL_1 is 0, the parameters
+ *  are not programmed into the SDRC CS1 registers
  */
 ENTRY(omap3_sram_configure_core_dpll)
         stmfd   sp!, {r1-r12, lr}       @ store regs to stack
-        ldr     r4, [sp, #52]           @ pull extra args off the stack
-        ldr     r5, [sp, #56]           @ load extra args from the stack
-        ldr     r6, [sp, #60]           @ load extra args from the stack
-        ldr     r7, [sp, #64]           @ load extra args from the stack
+
+                                        @ pull the extra args off the stack
+                                        @  and store them in SRAM
+        ldr     r4, [sp, #52]
+        str     r4, omap_sdrc_rfr_ctrl_0_val
+        ldr     r4, [sp, #56]
+        str     r4, omap_sdrc_actim_ctrl_a_0_val
+        ldr     r4, [sp, #60]
+        str     r4, omap_sdrc_actim_ctrl_b_0_val
+        ldr     r4, [sp, #64]
+        str     r4, omap_sdrc_mr_0_val
+        ldr     r4, [sp, #68]
+        str     r4, omap_sdrc_rfr_ctrl_1_val
+        cmp     r4, #0                  @ if SDRC_RFR_CTRL_1 is 0,
+        beq     skip_cs1_params         @  do not use cs1 params
+        ldr     r4, [sp, #72]
+        str     r4, omap_sdrc_actim_ctrl_a_1_val
+        ldr     r4, [sp, #76]
+        str     r4, omap_sdrc_actim_ctrl_b_1_val
+        ldr     r4, [sp, #80]
+        str     r4, omap_sdrc_mr_1_val
+skip_cs1_params:
         dsb                             @ flush buffered writes to interconnect
-        cmp     r7, #1                  @ if increasing SDRC clk rate,
+
+        cmp     r3, #1                  @ if increasing SDRC clk rate,
         bleq    configure_sdrc          @ program the SDRC regs early (for RFR)
-        cmp     r4, #SDRC_UNLOCK_DLL    @ set the intended DLL state
+        cmp     r1, #SDRC_UNLOCK_DLL    @ set the intended DLL state
         bleq    unlock_dll
         blne    lock_dll
         bl      sdram_in_selfrefresh    @ put SDRAM in self refresh, idle SDRC
         bl      configure_core_dpll     @ change the DPLL3 M2 divider
+        mov     r12, r2
+        bl      wait_clk_stable         @ wait for SDRC to stabilize
         bl      enable_sdrc             @ take SDRC out of idle
-        cmp     r4, #SDRC_UNLOCK_DLL    @ wait for DLL status to change
+        cmp     r1, #SDRC_UNLOCK_DLL    @ wait for DLL status to change
         bleq    wait_dll_unlock
         blne    wait_dll_lock
-        cmp     r7, #1                  @ if increasing SDRC clk rate,
+        cmp     r3, #1                  @ if increasing SDRC clk rate,
         beq     return_to_sdram         @ return to SDRAM code, otherwise,
         bl      configure_sdrc          @ reprogram SDRC regs now
-        mov     r12, r5
-        bl      wait_clk_stable         @ wait for SDRC to stabilize
 return_to_sdram:
         isb                             @ prevent speculative exec past here
         mov     r0, #0                  @ return value
@@ -113,7 +143,7 @@ return_to_sdram:
 unlock_dll:
         ldr     r11, omap3_sdrc_dlla_ctrl
         ldr     r12, [r11]
-        and     r12, r12, #FIXEDDELAY_MASK
+        bic     r12, r12, #FIXEDDELAY_MASK
         orr     r12, r12, #FIXEDDELAY_DEFAULT
         orr     r12, r12, #DLLIDLE_MASK
         str     r12, [r11]              @ (no OCP barrier needed)
@@ -129,7 +159,6 @@ sdram_in_selfrefresh:
         ldr     r12, [r11]              @ read the contents of SDRC_POWER
         mov     r9, r12                 @ keep a copy of SDRC_POWER bits
         orr     r12, r12, #SRFRONIDLEREQ_MASK   @ enable self refresh on idle
-        bic     r12, r12, #PWDENA_MASK  @ clear PWDENA
         str     r12, [r11]              @ write back to SDRC_POWER register
         ldr     r12, [r11]              @ posted-write barrier for SDRC
 idle_sdrc:
@@ -149,7 +178,7 @@ configure_core_dpll:
         ldr     r12, [r11]
         ldr     r10, core_m2_mask_val   @ modify m2 for core dpll
         and     r12, r12, r10
-        orr     r12, r12, r3, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT
+        orr     r12, r12, r0, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT
         str     r12, [r11]
         ldr     r12, [r11]              @ posted-write barrier for CM
         bx      lr
@@ -187,15 +216,34 @@ wait_dll_unlock:
         bne     wait_dll_unlock
         bx      lr
 configure_sdrc:
-        ldr     r11, omap3_sdrc_rfr_ctrl
-        str     r0, [r11]
-        ldr     r11, omap3_sdrc_actim_ctrla
-        str     r1, [r11]
-        ldr     r11, omap3_sdrc_actim_ctrlb
-        str     r2, [r11]
+        ldr     r12, omap_sdrc_rfr_ctrl_0_val   @ fetch value from SRAM
+        ldr     r11, omap3_sdrc_rfr_ctrl_0      @ fetch addr from SRAM
+        str     r12, [r11]                      @ store
+        ldr     r12, omap_sdrc_actim_ctrl_a_0_val
+        ldr     r11, omap3_sdrc_actim_ctrl_a_0
+        str     r12, [r11]
+        ldr     r12, omap_sdrc_actim_ctrl_b_0_val
+        ldr     r11, omap3_sdrc_actim_ctrl_b_0
+        str     r12, [r11]
+        ldr     r12, omap_sdrc_mr_0_val
         ldr     r11, omap3_sdrc_mr_0
-        str     r6, [r11]
-        ldr     r6, [r11]               @ posted-write barrier for SDRC
+        str     r12, [r11]
+        ldr     r12, omap_sdrc_rfr_ctrl_1_val
+        cmp     r12, #0                 @ if SDRC_RFR_CTRL_1 is 0,
+        beq     skip_cs1_prog           @  do not program cs1 params
+        ldr     r11, omap3_sdrc_rfr_ctrl_1
+        str     r12, [r11]
+        ldr     r12, omap_sdrc_actim_ctrl_a_1_val
+        ldr     r11, omap3_sdrc_actim_ctrl_a_1
+        str     r12, [r11]
+        ldr     r12, omap_sdrc_actim_ctrl_b_1_val
+        ldr     r11, omap3_sdrc_actim_ctrl_b_1
+        str     r12, [r11]
+        ldr     r12, omap_sdrc_mr_1_val
+        ldr     r11, omap3_sdrc_mr_1
+        str     r12, [r11]
+skip_cs1_prog:
+        ldr     r12, [r11]              @ posted-write barrier for SDRC
         bx      lr
 
 omap3_sdrc_power:
@@ -206,14 +254,40 @@ omap3_cm_idlest1_core:
         .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST)
 omap3_cm_iclken1_core:
         .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1)
-omap3_sdrc_rfr_ctrl:
+
+omap3_sdrc_rfr_ctrl_0:
         .word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_0)
-omap3_sdrc_actim_ctrla:
+omap3_sdrc_rfr_ctrl_1:
+        .word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_1)
+omap3_sdrc_actim_ctrl_a_0:
         .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0)
-omap3_sdrc_actim_ctrlb:
+omap3_sdrc_actim_ctrl_a_1:
+        .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_1)
+omap3_sdrc_actim_ctrl_b_0:
         .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0)
+omap3_sdrc_actim_ctrl_b_1:
+        .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_1)
 omap3_sdrc_mr_0:
         .word OMAP34XX_SDRC_REGADDR(SDRC_MR_0)
+omap3_sdrc_mr_1:
+        .word OMAP34XX_SDRC_REGADDR(SDRC_MR_1)
+omap_sdrc_rfr_ctrl_0_val:
+        .word 0xDEADBEEF
+omap_sdrc_rfr_ctrl_1_val:
+        .word 0xDEADBEEF
+omap_sdrc_actim_ctrl_a_0_val:
+        .word 0xDEADBEEF
+omap_sdrc_actim_ctrl_a_1_val:
+        .word 0xDEADBEEF
+omap_sdrc_actim_ctrl_b_0_val:
+        .word 0xDEADBEEF
+omap_sdrc_actim_ctrl_b_1_val:
+        .word 0xDEADBEEF
+omap_sdrc_mr_0_val:
+        .word 0xDEADBEEF
+omap_sdrc_mr_1_val:
+        .word 0xDEADBEEF
+
 omap3_sdrc_dlla_status:
         .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
 omap3_sdrc_dlla_ctrl:
@@ -223,3 +297,4 @@ core_m2_mask_val:
 
 ENTRY(omap3_sram_configure_core_dpll_sz)
         .word   . - omap3_sram_configure_core_dpll
+
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index 7936085dd758..2e9b8ccd8ec2 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -510,7 +510,7 @@ static struct db_chip db_chips[] __initdata = {
         }
 };
 
-static void u300_init_check_chip(void)
+static void __init u300_init_check_chip(void)
 {
 
         u16 val;
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 8277802ec859..3a7279c1ce5e 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -120,6 +120,32 @@ void show_mem(void)
         printk("%d pages swap cached\n", cached);
 }
 
+static void __init find_node_limits(int node, struct meminfo *mi,
+        unsigned long *min, unsigned long *max_low, unsigned long *max_high)
+{
+        int i;
+
+        *min = -1UL;
+        *max_low = *max_high = 0;
+
+        for_each_nodebank(i, mi, node) {
+                struct membank *bank = &mi->bank[i];
+                unsigned long start, end;
+
+                start = bank_pfn_start(bank);
+                end = bank_pfn_end(bank);
+
+                if (*min > start)
+                        *min = start;
+                if (*max_high < end)
+                        *max_high = end;
+                if (bank->highmem)
+                        continue;
+                if (*max_low < end)
+                        *max_low = end;
+        }
+}
+
 /*
  * FIXME: We really want to avoid allocating the bootmap bitmap
  * over the top of the initrd.  Hopefully, this is located towards
@@ -210,41 +236,25 @@ static inline void map_memory_bank(struct membank *bank)
 #endif
 }
 
-static unsigned long __init bootmem_init_node(int node, struct meminfo *mi)
+static void __init bootmem_init_node(int node, struct meminfo *mi,
+        unsigned long start_pfn, unsigned long end_pfn)
 {
-        unsigned long start_pfn, end_pfn, boot_pfn;
+        unsigned long boot_pfn;
         unsigned int boot_pages;
         pg_data_t *pgdat;
         int i;
 
-        start_pfn = -1UL;
-        end_pfn = 0;
-
         /*
-         * Calculate the pfn range, and map the memory banks for this node.
+         * Map the memory banks for this node.
          */
         for_each_nodebank(i, mi, node) {
                 struct membank *bank = &mi->bank[i];
-                unsigned long start, end;
 
-                start = bank_pfn_start(bank);
-                end = bank_pfn_end(bank);
-
-                if (start_pfn > start)
-                        start_pfn = start;
-                if (end_pfn < end)
-                        end_pfn = end;
-
-                map_memory_bank(bank);
+                if (!bank->highmem)
+                        map_memory_bank(bank);
         }
 
         /*
-         * If there is no memory in this node, ignore it.
-         */
-        if (end_pfn == 0)
-                return end_pfn;
-
-        /*
          * Allocate the bootmem bitmap page.
          */
         boot_pages = bootmem_bootmap_pages(end_pfn - start_pfn);
@@ -260,7 +270,8 @@ static unsigned long __init bootmem_init_node(int node, struct meminfo *mi)
 
         for_each_nodebank(i, mi, node) {
                 struct membank *bank = &mi->bank[i];
-                free_bootmem_node(pgdat, bank_phys_start(bank), bank_phys_size(bank));
+                if (!bank->highmem)
+                        free_bootmem_node(pgdat, bank_phys_start(bank), bank_phys_size(bank));
                 memory_present(node, bank_pfn_start(bank), bank_pfn_end(bank));
         }
 
@@ -269,8 +280,6 @@ static unsigned long __init bootmem_init_node(int node, struct meminfo *mi)
          */
         reserve_bootmem_node(pgdat, boot_pfn << PAGE_SHIFT,
                              boot_pages << PAGE_SHIFT, BOOTMEM_DEFAULT);
-
-        return end_pfn;
 }
 
 static void __init bootmem_reserve_initrd(int node)
@@ -297,33 +306,39 @@ static void __init bootmem_reserve_initrd(int node)
 static void __init bootmem_free_node(int node, struct meminfo *mi)
 {
         unsigned long zone_size[MAX_NR_ZONES], zhole_size[MAX_NR_ZONES];
-        unsigned long start_pfn, end_pfn;
-        pg_data_t *pgdat = NODE_DATA(node);
+        unsigned long min, max_low, max_high;
         int i;
 
-        start_pfn = pgdat->bdata->node_min_pfn;
-        end_pfn = pgdat->bdata->node_low_pfn;
+        find_node_limits(node, mi, &min, &max_low, &max_high);
 
         /*
          * initialise the zones within this node.
          */
         memset(zone_size, 0, sizeof(zone_size));
-        memset(zhole_size, 0, sizeof(zhole_size));
 
         /*
          * The size of this node has already been determined.  If we need
          * to do anything fancy with the allocation of this memory to the
          * zones, now is the time to do it.
          */
-        zone_size[0] = end_pfn - start_pfn;
+        zone_size[0] = max_low - min;
+#ifdef CONFIG_HIGHMEM
+        zone_size[ZONE_HIGHMEM] = max_high - max_low;
+#endif
 
         /*
          * For each bank in this node, calculate the size of the holes.
          *  holes = node_size - sum(bank_sizes_in_node)
          */
-        zhole_size[0] = zone_size[0];
-        for_each_nodebank(i, mi, node)
-                zhole_size[0] -= bank_pfn_size(&mi->bank[i]);
+        memcpy(zhole_size, zone_size, sizeof(zhole_size));
+        for_each_nodebank(i, mi, node) {
+                int idx = 0;
+#ifdef CONFIG_HIGHMEM
+                if (mi->bank[i].highmem)
+                        idx = ZONE_HIGHMEM;
+#endif
+                zhole_size[idx] -= bank_pfn_size(&mi->bank[i]);
+        }
 
         /*
          * Adjust the sizes according to any special requirements for
@@ -331,13 +346,13 @@ static void __init bootmem_free_node(int node, struct meminfo *mi)
          */
         arch_adjust_zones(node, zone_size, zhole_size);
 
-        free_area_init_node(node, zone_size, start_pfn, zhole_size);
+        free_area_init_node(node, zone_size, min, zhole_size);
 }
 
 void __init bootmem_init(void)
 {
         struct meminfo *mi = &meminfo;
-        unsigned long memend_pfn = 0;
+        unsigned long min, max_low, max_high;
         int node, initrd_node;
 
         /*
@@ -345,11 +360,29 @@ void __init bootmem_init(void)
          */
         initrd_node = check_initrd(mi);
 
+        max_low = max_high = 0;
+
         /*
          * Run through each node initialising the bootmem allocator.
          */
         for_each_node(node) {
-                unsigned long end_pfn = bootmem_init_node(node, mi);
+                unsigned long node_low, node_high;
+
+                find_node_limits(node, mi, &min, &node_low, &node_high);
+
+                if (node_low > max_low)
+                        max_low = node_low;
+                if (node_high > max_high)
+                        max_high = node_high;
+
+                /*
+                 * If there is no memory in this node, ignore it.
+                 * (We can't have nodes which have no lowmem)
+                 */
+                if (node_low == 0)
+                        continue;
+
+                bootmem_init_node(node, mi, min, node_low);
 
                 /*
                  * Reserve any special node zero regions.
@@ -362,12 +395,6 @@ void __init bootmem_init(void)
                  */
                 if (node == initrd_node)
                         bootmem_reserve_initrd(node);
-
-                /*
-                 * Remember the highest memory PFN.
-                 */
-                if (end_pfn > memend_pfn)
-                        memend_pfn = end_pfn;
         }
 
         /*
@@ -383,7 +410,7 @@ void __init bootmem_init(void)
         for_each_node(node)
                 bootmem_free_node(node, mi);
 
-        high_memory = __va((memend_pfn << PAGE_SHIFT) - 1) + 1;
+        high_memory = __va((max_low << PAGE_SHIFT) - 1) + 1;
 
         /*
          * This doesn't seem to be used by the Linux memory manager any
@@ -393,7 +420,8 @@ void __init bootmem_init(void)
          * Note: max_low_pfn and max_pfn reflect the number of _pages_ in
          * the system, not the maximum PFN.
          */
-        max_pfn = max_low_pfn = memend_pfn - PHYS_PFN_OFFSET;
+        max_low_pfn = max_low - PHYS_PFN_OFFSET;
+        max_pfn = max_high - PHYS_PFN_OFFSET;
 }
 
 static inline int free_area(unsigned long pfn, unsigned long end, char *s)
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 4722582b17b8..4426ee67ceca 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -687,13 +687,19 @@ __early_param("vmalloc=", early_vmalloc);
 
 static void __init sanity_check_meminfo(void)
 {
-        int i, j;
+        int i, j, highmem = 0;
 
         for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
                 struct membank *bank = &meminfo.bank[j];
                 *bank = meminfo.bank[i];
 
 #ifdef CONFIG_HIGHMEM
+                if (__va(bank->start) > VMALLOC_MIN ||
+                    __va(bank->start) < (void *)PAGE_OFFSET)
+                        highmem = 1;
+
+                bank->highmem = highmem;
+
                 /*
                  * Split those memory banks which are partially overlapping
                  * the vmalloc area greatly simplifying things later.
@@ -714,6 +720,7 @@ static void __init sanity_check_meminfo(void)
                                 i++;
                                 bank[1].size -= VMALLOC_MIN - __va(bank->start);
                                 bank[1].start = __pa(VMALLOC_MIN - 1) + 1;
+                                bank[1].highmem = highmem = 1;
                                 j++;
                         }
                         bank->size = VMALLOC_MIN - __va(bank->start);
diff --git a/arch/arm/plat-omap/cpu-omap.c b/arch/arm/plat-omap/cpu-omap.c
index 843e8af64066..1868c0d8f9b5 100644
--- a/arch/arm/plat-omap/cpu-omap.c
+++ b/arch/arm/plat-omap/cpu-omap.c
@@ -78,10 +78,10 @@ static int omap_target(struct cpufreq_policy *policy,
 
         /* Ensure desired rate is within allowed range.  Some govenors
          * (ondemand) will just pass target_freq=0 to get the minimum. */
-        if (target_freq < policy->cpuinfo.min_freq)
-                target_freq = policy->cpuinfo.min_freq;
-        if (target_freq > policy->cpuinfo.max_freq)
-                target_freq = policy->cpuinfo.max_freq;
+        if (target_freq < policy->min)
+                target_freq = policy->min;
+        if (target_freq > policy->max)
+                target_freq = policy->max;
 
         freqs.old = omap_getspeed(0);
         freqs.new = clk_round_rate(mpu_clk, target_freq * 1000) / 1000;
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 7677a4a1cef2..e3ac94f09006 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -946,7 +946,9 @@ void omap_start_dma(int lch)
 
                         cur_lch = next_lch;
                 } while (next_lch != -1);
-        } else if (cpu_class_is_omap2()) {
+        } else if (cpu_is_omap242x() ||
+                (cpu_is_omap243x() &&  omap_type() <= OMAP2430_REV_ES1_0)) {
+
                 /* Errata: Need to write lch even if not using chaining */
                 dma_write(lch, CLNK_CTRL(lch));
         }
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 26b387c12423..9298bc0ab171 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -476,14 +476,12 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
         __raw_writel(l, reg);
 }
 
-static int __omap_get_gpio_datain(int gpio)
+static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
 {
-        struct gpio_bank *bank;
         void __iomem *reg;
 
         if (check_gpio(gpio) < 0)
                 return -EINVAL;
-        bank = get_gpio_bank(gpio);
         reg = bank->base;
         switch (bank->method) {
 #ifdef CONFIG_ARCH_OMAP1
@@ -524,6 +522,53 @@ static int __omap_get_gpio_datain(int gpio)
                         & (1 << get_gpio_index(gpio))) != 0;
 }
 
+static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
+{
+        void __iomem *reg;
+
+        if (check_gpio(gpio) < 0)
+                return -EINVAL;
+        reg = bank->base;
+
+        switch (bank->method) {
+#ifdef CONFIG_ARCH_OMAP1
+        case METHOD_MPUIO:
+                reg += OMAP_MPUIO_OUTPUT;
+                break;
+#endif
+#ifdef CONFIG_ARCH_OMAP15XX
+        case METHOD_GPIO_1510:
+                reg += OMAP1510_GPIO_DATA_OUTPUT;
+                break;
+#endif
+#ifdef CONFIG_ARCH_OMAP16XX
+        case METHOD_GPIO_1610:
+                reg += OMAP1610_GPIO_DATAOUT;
+                break;
+#endif
+#ifdef CONFIG_ARCH_OMAP730
+        case METHOD_GPIO_730:
+                reg += OMAP730_GPIO_DATA_OUTPUT;
+                break;
+#endif
+#ifdef CONFIG_ARCH_OMAP850
+        case METHOD_GPIO_850:
+                reg += OMAP850_GPIO_DATA_OUTPUT;
+                break;
+#endif
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
+                defined(CONFIG_ARCH_OMAP4)
+        case METHOD_GPIO_24XX:
+                reg += OMAP24XX_GPIO_DATAOUT;
+                break;
+#endif
+        default:
+                return -EINVAL;
+        }
+
+        return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0;
+}
+
 #define MOD_REG_BIT(reg, bit_mask, set) \
 do {    \
         int l = __raw_readl(base + reg); \
@@ -1189,6 +1234,7 @@ static void gpio_mask_irq(unsigned int irq)
         struct gpio_bank *bank = get_irq_chip_data(irq);
 
         _set_gpio_irqenable(bank, gpio, 0);
+        _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
 }
 
 static void gpio_unmask_irq(unsigned int irq)
@@ -1196,6 +1242,11 @@ static void gpio_unmask_irq(unsigned int irq)
         unsigned int gpio = irq - IH_GPIO_BASE;
         struct gpio_bank *bank = get_irq_chip_data(irq);
         unsigned int irq_mask = 1 << get_gpio_index(gpio);
+        struct irq_desc *desc = irq_to_desc(irq);
+        u32 trigger = desc->status & IRQ_TYPE_SENSE_MASK;
+
+        if (trigger)
+                _set_gpio_triggering(bank, get_gpio_index(gpio), trigger);
 
         /* For level-triggered GPIOs, the clearing must be done after
          * the HW source is cleared, thus after the handler has run */
@@ -1350,9 +1401,49 @@ static int gpio_input(struct gpio_chip *chip, unsigned offset)
         return 0;
 }
 
+static int gpio_is_input(struct gpio_bank *bank, int mask)
+{
+        void __iomem *reg = bank->base;
+
+        switch (bank->method) {
+        case METHOD_MPUIO:
+                reg += OMAP_MPUIO_IO_CNTL;
+                break;
+        case METHOD_GPIO_1510:
+                reg += OMAP1510_GPIO_DIR_CONTROL;
+                break;
+        case METHOD_GPIO_1610:
+                reg += OMAP1610_GPIO_DIRECTION;
+                break;
+        case METHOD_GPIO_730:
+                reg += OMAP730_GPIO_DIR_CONTROL;
+                break;
+        case METHOD_GPIO_850:
+                reg += OMAP850_GPIO_DIR_CONTROL;
+                break;
+        case METHOD_GPIO_24XX:
+                reg += OMAP24XX_GPIO_OE;
+                break;
+        }
+        return __raw_readl(reg) & mask;
+}
+
 static int gpio_get(struct gpio_chip *chip, unsigned offset)
 {
-        return __omap_get_gpio_datain(chip->base + offset);
+        struct gpio_bank *bank;
+        void __iomem *reg;
+        int gpio;
+        u32 mask;
+
+        gpio = chip->base + offset;
+        bank = get_gpio_bank(gpio);
+        reg = bank->base;
+        mask = 1 << get_gpio_index(gpio);
+
+        if (gpio_is_input(bank, mask))
+                return _get_gpio_datain(bank, gpio);
+        else
+                return _get_gpio_dataout(bank, gpio);
 }
 
 static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
@@ -1886,34 +1977,6 @@ arch_initcall(omap_gpio_sysinit);
 #include <linux/debugfs.h>
 #include <linux/seq_file.h>
 
-static int gpio_is_input(struct gpio_bank *bank, int mask)
-{
-        void __iomem *reg = bank->base;
-
-        switch (bank->method) {
-        case METHOD_MPUIO:
-                reg += OMAP_MPUIO_IO_CNTL;
-                break;
-        case METHOD_GPIO_1510:
-                reg += OMAP1510_GPIO_DIR_CONTROL;
-                break;
-        case METHOD_GPIO_1610:
-                reg += OMAP1610_GPIO_DIRECTION;
-                break;
-        case METHOD_GPIO_730:
-                reg += OMAP730_GPIO_DIR_CONTROL;
-                break;
-        case METHOD_GPIO_850:
-                reg += OMAP850_GPIO_DIR_CONTROL;
-                break;
-        case METHOD_GPIO_24XX:
-                reg += OMAP24XX_GPIO_OE;
-                break;
-        }
-        return __raw_readl(reg) & mask;
-}
-
-
 static int dbg_gpio_show(struct seq_file *s, void *unused)
 {
         unsigned        i, j, gpio;
diff --git a/arch/arm/plat-omap/include/mach/clock.h b/arch/arm/plat-omap/include/mach/clock.h
index f9f65e1ba3f1..4b8b0d65cbf2 100644
--- a/arch/arm/plat-omap/include/mach/clock.h
+++ b/arch/arm/plat-omap/include/mach/clock.h
@@ -20,6 +20,8 @@ struct clockdomain;
 struct clkops {
         int                     (*enable)(struct clk *);
         void                    (*disable)(struct clk *);
+        void                    (*find_idlest)(struct clk *, void __iomem **, u8 *);
+        void                    (*find_companion)(struct clk *, void __iomem **, u8 *);
 };
 
 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
diff --git a/arch/arm/plat-omap/include/mach/cpu.h b/arch/arm/plat-omap/include/mach/cpu.h
index 285eaa3a8275..11e73d9e8928 100644
--- a/arch/arm/plat-omap/include/mach/cpu.h
+++ b/arch/arm/plat-omap/include/mach/cpu.h
@@ -378,9 +378,6 @@ IS_OMAP_TYPE(3430, 0x3430)
 #define cpu_class_is_omap2()    (cpu_is_omap24xx() || cpu_is_omap34xx() || \
                                 cpu_is_omap44xx())
 
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
-                        defined(CONFIG_ARCH_OMAP4)
-
 /* Various silicon revisions for omap2 */
 #define OMAP242X_CLASS          0x24200024
 #define OMAP2420_REV_ES1_0      0x24200024
@@ -436,5 +433,3 @@ IS_OMAP_TYPE(3430, 0x3430)
 
 int omap_chip_is(struct omap_chip_id oci);
 void omap2_check_revision(void);
-
-#endif    /* defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) */
diff --git a/arch/arm/plat-omap/include/mach/io.h b/arch/arm/plat-omap/include/mach/io.h
index 73f483d56ca6..21fb0efdda86 100644
--- a/arch/arm/plat-omap/include/mach/io.h
+++ b/arch/arm/plat-omap/include/mach/io.h
@@ -228,7 +228,8 @@ extern void omap1_map_common_io(void);
 extern void omap1_init_common_hw(void);
 
 extern void omap2_map_common_io(void);
-extern void omap2_init_common_hw(struct omap_sdrc_params *sp);
+extern void omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
+                                 struct omap_sdrc_params *sdrc_cs1);
 
 #define __arch_ioremap(p,s,t)   omap_ioremap(p,s,t)
 #define __arch_iounmap(v)       omap_iounmap(v)
diff --git a/arch/arm/plat-omap/include/mach/mux.h b/arch/arm/plat-omap/include/mach/mux.h
index 85a621705766..80281c458baf 100644
--- a/arch/arm/plat-omap/include/mach/mux.h
+++ b/arch/arm/plat-omap/include/mach/mux.h
@@ -853,6 +853,10 @@ enum omap34xx_index {
         AE5_34XX_GPIO143,
         H19_34XX_GPIO164_OUT,
         J25_34XX_GPIO170,
+
+        /* OMAP3 SDRC CKE signals to SDR/DDR ram chips */
+        H16_34XX_SDRC_CKE0,
+        H17_34XX_SDRC_CKE1,
 };
 
 struct omap_mux_cfg {
diff --git a/arch/arm/plat-omap/include/mach/prcm.h b/arch/arm/plat-omap/include/mach/prcm.h
index 24ac3c715912..cda2a70397b4 100644
--- a/arch/arm/plat-omap/include/mach/prcm.h
+++ b/arch/arm/plat-omap/include/mach/prcm.h
@@ -25,6 +25,7 @@
 
 u32 omap_prcm_get_reset_sources(void);
 void omap_prcm_arch_reset(char mode);
+int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, const char *name);
 
 #endif
 
diff --git a/arch/arm/plat-omap/include/mach/sdrc.h b/arch/arm/plat-omap/include/mach/sdrc.h
index adc73522491f..0be18e4ff182 100644
--- a/arch/arm/plat-omap/include/mach/sdrc.h
+++ b/arch/arm/plat-omap/include/mach/sdrc.h
@@ -30,6 +30,10 @@
 #define SDRC_ACTIM_CTRL_A_0     0x09c
 #define SDRC_ACTIM_CTRL_B_0     0x0a0
 #define SDRC_RFR_CTRL_0         0x0a4
+#define SDRC_MR_1               0x0B4
+#define SDRC_ACTIM_CTRL_A_1     0x0C4
+#define SDRC_ACTIM_CTRL_B_1     0x0C8
+#define SDRC_RFR_CTRL_1         0x0D4
 
 /*
  * These values represent the number of memory clock cycles between
@@ -102,8 +106,11 @@ struct omap_sdrc_params {
         u32 mr;
 };
 
-void __init omap2_sdrc_init(struct omap_sdrc_params *sp);
-struct omap_sdrc_params *omap2_sdrc_get_params(unsigned long r);
+void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
+                            struct omap_sdrc_params *sdrc_cs1);
+int omap2_sdrc_get_params(unsigned long r,
+                          struct omap_sdrc_params **sdrc_cs0,
+                          struct omap_sdrc_params **sdrc_cs1);
 
 #ifdef CONFIG_ARCH_OMAP2
 
diff --git a/arch/arm/plat-omap/include/mach/serial.h b/arch/arm/plat-omap/include/mach/serial.h
index 13abd02d1527..def0529c75eb 100644
--- a/arch/arm/plat-omap/include/mach/serial.h
+++ b/arch/arm/plat-omap/include/mach/serial.h
@@ -59,6 +59,7 @@ extern void omap_uart_check_wakeup(void);
 extern void omap_uart_prepare_suspend(void);
 extern void omap_uart_prepare_idle(int num);
 extern void omap_uart_resume_idle(int num);
+extern void omap_uart_enable_irqs(int enable);
 #endif
 
 #endif
diff --git a/arch/arm/plat-omap/include/mach/sram.h b/arch/arm/plat-omap/include/mach/sram.h
index 4d53cc59d7a3..8974e3fc2691 100644
--- a/arch/arm/plat-omap/include/mach/sram.h
+++ b/arch/arm/plat-omap/include/mach/sram.h
@@ -21,11 +21,12 @@ extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
                                       u32 mem_type);
 extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
 
-extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl,
-                                     u32 sdrc_actim_ctrla,
-                                     u32 sdrc_actim_ctrlb, u32 m2,
-                                     u32 unlock_dll, u32 f, u32 sdrc_mr,
-                                     u32 inc);
+extern u32 omap3_configure_core_dpll(
+                        u32 m2, u32 unlock_dll, u32 f, u32 inc,
+                        u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
+                        u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
+                        u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
+                        u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
 
 /* Do not use these */
 extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
@@ -59,12 +60,12 @@ extern void omap243x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
                                                 u32 mem_type);
 extern unsigned long omap243x_sram_reprogram_sdrc_sz;
 
-
-extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl,
-                                          u32 sdrc_actim_ctrla,
-                                          u32 sdrc_actim_ctrlb, u32 m2,
-                                          u32 unlock_dll, u32 f, u32 sdrc_mr,
-                                          u32 inc);
+extern u32 omap3_sram_configure_core_dpll(
+                        u32 m2, u32 unlock_dll, u32 f, u32 inc,
+                        u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
+                        u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
+                        u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
+                        u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
 extern unsigned long omap3_sram_configure_core_dpll_sz;
 
 #endif
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 4ea73804d21e..5eae7876979c 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -44,9 +44,9 @@
 #define OMAP2_SRAM_VA           0xe3000000
 #define OMAP2_SRAM_PUB_VA       (OMAP2_SRAM_VA + 0x800)
 #define OMAP3_SRAM_PA           0x40200000
-#define OMAP3_SRAM_VA           0xd7000000
+#define OMAP3_SRAM_VA           0xe3000000
 #define OMAP3_SRAM_PUB_PA       0x40208000
-#define OMAP3_SRAM_PUB_VA       0xd7008000
+#define OMAP3_SRAM_PUB_VA       (OMAP3_SRAM_VA + 0x8000)
 #define OMAP4_SRAM_PA           0x40200000              /*0x402f0000*/
 #define OMAP4_SRAM_VA           0xd7000000              /*0xd70f0000*/
 
@@ -373,20 +373,26 @@ static inline int omap243x_sram_init(void)
 
 #ifdef CONFIG_ARCH_OMAP3
 
-static u32 (*_omap3_sram_configure_core_dpll)(u32 sdrc_rfr_ctrl,
-                                              u32 sdrc_actim_ctrla,
-                                              u32 sdrc_actim_ctrlb,
-                                              u32 m2, u32 unlock_dll,
-                                              u32 f, u32 sdrc_mr, u32 inc);
-u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla,
-                              u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll,
-                              u32 f, u32 sdrc_mr, u32 inc)
+static u32 (*_omap3_sram_configure_core_dpll)(
+                        u32 m2, u32 unlock_dll, u32 f, u32 inc,
+                        u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
+                        u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
+                        u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
+                        u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
+
+u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc,
+                        u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
+                        u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
+                        u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
+                        u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1)
 {
         BUG_ON(!_omap3_sram_configure_core_dpll);
-        return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl,
-                                               sdrc_actim_ctrla,
-                                               sdrc_actim_ctrlb, m2,
-                                               unlock_dll, f, sdrc_mr, inc);
+        return _omap3_sram_configure_core_dpll(
+                        m2, unlock_dll, f, inc,
+                        sdrc_rfr_ctrl_0, sdrc_actim_ctrl_a_0,
+                        sdrc_actim_ctrl_b_0, sdrc_mr_0,
+                        sdrc_rfr_ctrl_1, sdrc_actim_ctrl_a_1,
+                        sdrc_actim_ctrl_b_1, sdrc_mr_1);
 }
 
 /* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */
diff --git a/arch/arm/plat-s3c24xx/clock-dclk.c b/arch/arm/plat-s3c24xx/clock-dclk.c
index 5b75a797b5ab..0afb217a775e 100644
--- a/arch/arm/plat-s3c24xx/clock-dclk.c
+++ b/arch/arm/plat-s3c24xx/clock-dclk.c
@@ -129,7 +129,7 @@ static int s3c24xx_clkout_setparent(struct clk *clk, struct clk *parent)
 
         /* calculate the MISCCR setting for the clock */
 
-        if (parent == &clk_xtal)
+        if (parent == &clk_mpll)
                 source = S3C2410_MISCCR_CLK0_MPLL;
         else if (parent == &clk_upll)
                 source = S3C2410_MISCCR_CLK0_UPLL;
diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h
index 96a14a426a7c..4320239cf4ef 100644
--- a/arch/mips/include/asm/page.h
+++ b/arch/mips/include/asm/page.h
@@ -32,10 +32,12 @@
 #define PAGE_SIZE       (1UL << PAGE_SHIFT)
 #define PAGE_MASK       (~((1 << PAGE_SHIFT) - 1))
 
+#ifdef CONFIG_HUGETLB_PAGE
 #define HPAGE_SHIFT     (PAGE_SHIFT + PAGE_SHIFT - 3)
 #define HPAGE_SIZE      ((1UL) << HPAGE_SHIFT)
 #define HPAGE_MASK      (~(HPAGE_SIZE - 1))
 #define HUGETLB_PAGE_ORDER      (HPAGE_SHIFT - PAGE_SHIFT)
+#endif /* CONFIG_HUGETLB_PAGE */
 
 #ifndef __ASSEMBLY__
 
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index d00131ca0835..4c0747e8ed74 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -472,7 +472,7 @@ config PPC_16K_PAGES
         bool "16k page size" if 44x
 
 config PPC_64K_PAGES
-        bool "64k page size" if 44x || PPC_STD_MMU_64
+        bool "64k page size" if 44x || PPC_STD_MMU_64 || PPC_BOOK3E_64
         select PPC_HAS_HASH_64K if PPC_STD_MMU_64
 
 config PPC_256K_PAGES
@@ -492,16 +492,16 @@ endchoice
 
 config FORCE_MAX_ZONEORDER
         int "Maximum zone order"
-        range 9 64 if PPC_STD_MMU_64 && PPC_64K_PAGES
-        default "9" if PPC_STD_MMU_64 && PPC_64K_PAGES
-        range 13 64 if PPC_STD_MMU_64 && !PPC_64K_PAGES
-        default "13" if PPC_STD_MMU_64 && !PPC_64K_PAGES
-        range 9 64 if PPC_STD_MMU_32 && PPC_16K_PAGES
-        default "9" if PPC_STD_MMU_32 && PPC_16K_PAGES
-        range 7 64 if PPC_STD_MMU_32 && PPC_64K_PAGES
-        default "7" if PPC_STD_MMU_32 && PPC_64K_PAGES
-        range 5 64 if PPC_STD_MMU_32 && PPC_256K_PAGES
-        default "5" if PPC_STD_MMU_32 && PPC_256K_PAGES
+        range 9 64 if PPC64 && PPC_64K_PAGES
+        default "9" if PPC64 && PPC_64K_PAGES
+        range 13 64 if PPC64 && !PPC_64K_PAGES
+        default "13" if PPC64 && !PPC_64K_PAGES
+        range 9 64 if PPC32 && PPC_16K_PAGES
+        default "9" if PPC32 && PPC_16K_PAGES
+        range 7 64 if PPC32 && PPC_64K_PAGES
+        default "7" if PPC32 && PPC_64K_PAGES
+        range 5 64 if PPC32 && PPC_256K_PAGES
+        default "5" if PPC32 && PPC_256K_PAGES
         range 11 64
         default "11"
         help
diff --git a/arch/powerpc/Makefile b/arch/powerpc/Makefile
index bc35f4e2b81c..952a3963e9e8 100644
--- a/arch/powerpc/Makefile
+++ b/arch/powerpc/Makefile
@@ -77,7 +77,7 @@ CPP		= $(CC) -E $(KBUILD_CFLAGS)
 CHECKFLAGS      += -m$(CONFIG_WORD_SIZE) -D__powerpc__ -D__powerpc$(CONFIG_WORD_SIZE)__
 
 ifeq ($(CONFIG_PPC64),y)
-GCC_BROKEN_VEC  := $(shell if [ $(call cc-version) -lt 0400 ] ; then echo "y"; fi)
+GCC_BROKEN_VEC  := $(call cc-ifversion, -lt, 0400, y)
 
 ifeq ($(CONFIG_POWER4_ONLY),y)
 ifeq ($(CONFIG_ALTIVEC),y)
diff --git a/arch/powerpc/boot/dts/canyonlands.dts b/arch/powerpc/boot/dts/canyonlands.dts
index 5fd1ad09bdf2..c920170b7dfe 100644
--- a/arch/powerpc/boot/dts/canyonlands.dts
+++ b/arch/powerpc/boot/dts/canyonlands.dts
@@ -1,7 +1,7 @@
 /*
  * Device Tree Source for AMCC Canyonlands (460EX)
  *
- * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de>
+ * Copyright 2008-2009 DENX Software Engineering, Stefan Roese <sr@denx.de>
  *
  * This file is licensed under the terms of the GNU General Public
  * License version 2.  This program is licensed "as is" without
@@ -149,19 +149,19 @@
                                         /*RXDE*/  0x5 0x4>;
                 };
 
-                USB0: ehci@bffd0400 {
-                        compatible = "ibm,usb-ehci-460ex", "usb-ehci";
-                        interrupt-parent = <&UIC2>;
-                        interrupts = <0x1d 4>;
-                        reg = <4 0xbffd0400 0x90 4 0xbffd0490 0x70>;
-                };
+                USB0: ehci@bffd0400 {
+                        compatible = "ibm,usb-ehci-460ex", "usb-ehci";
+                        interrupt-parent = <&UIC2>;
+                        interrupts = <0x1d 4>;
+                        reg = <4 0xbffd0400 0x90 4 0xbffd0490 0x70>;
+                };
 
-                USB1: usb@bffd0000 {
-                        compatible = "ohci-le";
-                        reg = <4 0xbffd0000 0x60>;
-                        interrupt-parent = <&UIC2>;
-                        interrupts = <0x1e 4>;
-                };
+                USB1: usb@bffd0000 {
+                        compatible = "ohci-le";
+                        reg = <4 0xbffd0000 0x60>;
+                        interrupt-parent = <&UIC2>;
+                        interrupts = <0x1e 4>;
+                };
 
                 POB0: opb {
                         compatible = "ibm,opb-460ex", "ibm,opb";
@@ -215,6 +215,29 @@
                                                 reg = <0x03fa0000 0x00060000>;
                                         };
                                 };
+
+                                ndfc@3,0 {
+                                        compatible = "ibm,ndfc";
+                                        reg = <0x00000003 0x00000000 0x00002000>;
+                                        ccr = <0x00001000>;
+                                        bank-settings = <0x80002222>;
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+
+                                        nand {
+                                                #address-cells = <1>;
+                                                #size-cells = <1>;
+
+                                                partition@0 {
+                                                        label = "u-boot";
+                                                        reg = <0x00000000 0x00100000>;
+                                                };
+                                                partition@100000 {
+                                                        label = "user";
+                                                        reg = <0x00000000 0x03f00000>;
+                                                };
+                                        };
+                                };
                         };
 
                         UART0: serial@ef600300 {
diff --git a/arch/powerpc/boot/dts/gef_sbc310.dts b/arch/powerpc/boot/dts/gef_sbc310.dts
index 0f4c9ec2c3a6..2107d3c7cfe1 100644
--- a/arch/powerpc/boot/dts/gef_sbc310.dts
+++ b/arch/powerpc/boot/dts/gef_sbc310.dts
@@ -83,34 +83,34 @@
 
                 /* flash@0,0 is a mirror of part of the memory in flash@1,0
                 flash@0,0 {
-                        compatible = "cfi-flash";
-                        reg = <0 0 0x01000000>;
+                        compatible = "gef,sbc310-firmware-mirror", "cfi-flash";
+                        reg = <0x0 0x0 0x01000000>;
                         bank-width = <2>;
                         device-width = <2>;
                         #address-cells = <1>;
                         #size-cells = <1>;
                         partition@0 {
                                 label = "firmware";
-                                reg = <0x00000000 0x01000000>;
+                                reg = <0x0 0x01000000>;
                                 read-only;
                         };
                 };
                 */
 
                 flash@1,0 {
-                        compatible = "cfi-flash";
-                        reg = <1 0 0x8000000>;
+                        compatible = "gef,sbc310-paged-flash", "cfi-flash";
+                        reg = <0x1 0x0 0x8000000>;
                         bank-width = <2>;
                         device-width = <2>;
                         #address-cells = <1>;
                         #size-cells = <1>;
                         partition@0 {
                                 label = "user";
-                                reg = <0x00000000 0x07800000>;
+                                reg = <0x0 0x7800000>;
                         };
                         partition@7800000 {
                                 label = "firmware";
-                                reg = <0x07800000 0x00800000>;
+                                reg = <0x7800000 0x800000>;
                                 read-only;
                         };
                 };
@@ -121,18 +121,16 @@
                 };
 
                 wdt@4,2000 {
-                        #interrupt-cells = <2>;
-                        device_type = "watchdog";
-                        compatible = "gef,fpga-wdt";
+                        compatible = "gef,sbc310-fpga-wdt", "gef,fpga-wdt-1.00",
+                                "gef,fpga-wdt";
                         reg = <0x4 0x2000 0x8>;
                         interrupts = <0x1a 0x4>;
                         interrupt-parent = <&gef_pic>;
                 };
 /*
                 wdt@4,2010 {
-                        #interrupt-cells = <2>;
-                        device_type = "watchdog";
-                        compatible = "gef,fpga-wdt";
+                        compatible = "gef,sbc310-fpga-wdt", "gef,fpga-wdt-1.00",
+                                "gef,fpga-wdt";
                         reg = <0x4 0x2010 0x8>;
                         interrupts = <0x1b 0x4>;
                         interrupt-parent = <&gef_pic>;
@@ -141,7 +139,7 @@
                 gef_pic: pic@4,4000 {
                         #interrupt-cells = <1>;
                         interrupt-controller;
-                        compatible = "gef,fpga-pic";
+                        compatible = "gef,sbc310-fpga-pic", "gef,fpga-pic";
                         reg = <0x4 0x4000 0x20>;
                         interrupts = <0x8
                                       0x9>;
@@ -161,7 +159,7 @@
                 #size-cells = <1>;
                 #interrupt-cells = <2>;
                 device_type = "soc";
-                compatible = "simple-bus";
+                compatible = "fsl,mpc8641-soc", "simple-bus";
                 ranges = <0x0 0xfef00000 0x00100000>;
                 bus-frequency = <33333333>;
 
@@ -376,4 +374,40 @@
                                   0x0 0x00400000>;
                 };
         };
+
+        pci1: pcie@fef09000 {
+                compatible = "fsl,mpc8641-pcie";
+                device_type = "pci";
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                reg = <0xfef09000 0x1000>;
+                bus-range = <0x0 0xff>;
+                ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
+                          0x01000000 0x0 0x00000000 0xfe400000 0x0 0x00400000>;
+                clock-frequency = <33333333>;
+                interrupt-parent = <&mpic>;
+                interrupts = <0x19 0x2>;
+                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+                interrupt-map = <
+                        0x0000 0x0 0x0 0x1 &mpic 0x4 0x2
+                        0x0000 0x0 0x0 0x2 &mpic 0x5 0x2
+                        0x0000 0x0 0x0 0x3 &mpic 0x6 0x2
+                        0x0000 0x0 0x0 0x4 &mpic 0x7 0x2
+                        >;
+
+                pcie@0 {
+                        reg = <0 0 0 0 0>;
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        device_type = "pci";
+                        ranges = <0x02000000 0x0 0xc0000000
+                                  0x02000000 0x0 0xc0000000
+                                  0x0 0x20000000
+
+                                  0x01000000 0x0 0x00000000
+                                  0x01000000 0x0 0x00000000
+                                  0x0 0x00400000>;
+                };
+        };
 };
diff --git a/arch/powerpc/boot/dts/kilauea.dts b/arch/powerpc/boot/dts/kilauea.dts
index 5e6b08ff6f67..c46561456ede 100644
--- a/arch/powerpc/boot/dts/kilauea.dts
+++ b/arch/powerpc/boot/dts/kilauea.dts
@@ -1,7 +1,7 @@
 /*
  * Device Tree Source for AMCC Kilauea (405EX)
  *
- * Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de>
+ * Copyright 2007-2009 DENX Software Engineering, Stefan Roese <sr@denx.de>
  *
  * This file is licensed under the terms of the GNU General Public
  * License version 2.  This program is licensed "as is" without
@@ -150,7 +150,11 @@
                                         #size-cells = <1>;
                                         partition@0 {
                                                 label = "kernel";
-                                                reg = <0x00000000 0x00200000>;
+                                                reg = <0x00000000 0x001e0000>;
+                                        };
+                                        partition@1e0000 {
+                                                label = "dtb";
+                                                reg = <0x001e0000 0x00020000>;
                                         };
                                         partition@200000 {
                                                 label = "root";
@@ -169,6 +173,29 @@
                                                 reg = <0x03fa0000 0x00060000>;
                                         };
                                 };
+
+                                ndfc@1,0 {
+                                        compatible = "ibm,ndfc";
+                                        reg = <0x00000001 0x00000000 0x00002000>;
+                                        ccr = <0x00001000>;
+                                        bank-settings = <0x80002222>;
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+
+                                        nand {
+                                                #address-cells = <1>;
+                                                #size-cells = <1>;
+
+                                                partition@0 {
+                                                        label = "u-boot";
+                                                        reg = <0x00000000 0x00100000>;
+                                                };
+                                                partition@100000 {
+                                                        label = "user";
+                                                        reg = <0x00000000 0x03f00000>;
+                                                };
+                                        };
+                                };
                         };
 
                         UART0: serial@ef600200 {
@@ -198,6 +225,18 @@
                                 reg = <0xef600400 0x00000014>;
                                 interrupt-parent = <&UIC0>;
                                 interrupts = <0x2 0x4>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                rtc@68 {
+                                        compatible = "dallas,ds1338";
+                                        reg = <0x68>;
+                                };
+
+                                dtt@48 {
+                                        compatible = "dallas,ds1775";
+                                        reg = <0x48>;
+                                };
                         };
 
                         IIC1: i2c@ef600500 {
@@ -207,7 +246,6 @@
                                 interrupts = <0x7 0x4>;
                         };
 
-
                         RGMII0: emac-rgmii@ef600b00 {
                                 compatible = "ibm,rgmii-405ex", "ibm,rgmii";
                                 reg = <0xef600b00 0x00000104>;
diff --git a/arch/powerpc/boot/dts/mgcoge.dts b/arch/powerpc/boot/dts/mgcoge.dts
index 633255a97557..0ce96644176d 100644
--- a/arch/powerpc/boot/dts/mgcoge.dts
+++ b/arch/powerpc/boot/dts/mgcoge.dts
@@ -162,6 +162,59 @@
                                 fixed-link = <0 0 10 0 0>;
                         };
 
+                        i2c@11860 {
+                                compatible = "fsl,mpc8272-i2c",
+                                             "fsl,cpm2-i2c";
+                                reg = <0x11860 0x20 0x8afc 0x2>;
+                                interrupts = <1 8>;
+                                interrupt-parent = <&PIC>;
+                                fsl,cpm-command = <0x29600000>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        mdio@10d40 {
+                                compatible = "fsl,cpm2-mdio-bitbang";
+                                reg = <0x10d00 0x14>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                fsl,mdio-pin = <12>;
+                                fsl,mdc-pin = <13>;
+
+                                phy0: ethernet-phy@0 {
+                                        reg = <0x0>;
+                                };
+
+                                phy1: ethernet-phy@1 {
+                                        reg = <0x1>;
+                                };
+                        };
+
+                        /* FCC1 management to switch */
+                        ethernet@11300 {
+                                device_type = "network";
+                                compatible = "fsl,cpm2-fcc-enet";
+                                reg = <0x11300 0x20 0x8400 0x100 0x11390 0x1>;
+                                local-mac-address = [ 00 01 02 03 04 07 ];
+                                interrupts = <32 8>;
+                                interrupt-parent = <&PIC>;
+                                phy-handle = <&phy0>;
+                                linux,network-index = <1>;
+                                fsl,cpm-command = <0x12000300>;
+                        };
+
+                        /* FCC2 to redundant core unit over backplane */
+                        ethernet@11320 {
+                                device_type = "network";
+                                compatible = "fsl,cpm2-fcc-enet";
+                                reg = <0x11320 0x20 0x8500 0x100 0x113b0 0x1>;
+                                local-mac-address = [ 00 01 02 03 04 08 ];
+                                interrupts = <33 8>;
+                                interrupt-parent = <&PIC>;
+                                phy-handle = <&phy1>;
+                                linux,network-index = <2>;
+                                fsl,cpm-command = <0x16200300>;
+                        };
                 };
 
                 PIC: interrupt-controller@10c00 {
diff --git a/arch/powerpc/boot/dts/mpc8377_rdb.dts b/arch/powerpc/boot/dts/mpc8377_rdb.dts
index 4f06dbc0d27e..28e022ac4179 100644
--- a/arch/powerpc/boot/dts/mpc8377_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc8377_rdb.dts
@@ -174,7 +174,7 @@
                                 interrupts = <42 0x8>;
                                 interrupt-parent = <&ipic>;
                                 /* Filled in by U-Boot */
-                                clock-frequency = <0>;
+                                clock-frequency = <111111111>;
                         };
                 };
 
diff --git a/arch/powerpc/boot/dts/mpc8377_wlan.dts b/arch/powerpc/boot/dts/mpc8377_wlan.dts
new file mode 100644
index 000000000000..3febc4e91b10
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8377_wlan.dts
@@ -0,0 +1,464 @@
+/*
+ * MPC8377E WLAN Device Tree Source
+ *
+ * Copyright 2007-2009 Freescale Semiconductor Inc.
+ * Copyright 2009 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+
+/ {
+        compatible = "fsl,mpc8377wlan";
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        aliases {
+                ethernet0 = &enet0;
+                ethernet1 = &enet1;
+                serial0 = &serial0;
+                serial1 = &serial1;
+                pci0 = &pci0;
+                pci1 = &pci1;
+                pci2 = &pci2;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                PowerPC,8377@0 {
+                        device_type = "cpu";
+                        reg = <0x0>;
+                        d-cache-line-size = <32>;
+                        i-cache-line-size = <32>;
+                        d-cache-size = <32768>;
+                        i-cache-size = <32768>;
+                        timebase-frequency = <0>;
+                        bus-frequency = <0>;
+                        clock-frequency = <0>;
+                };
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x20000000>;  // 512MB at 0
+        };
+
+        localbus@e0005000 {
+                #address-cells = <2>;
+                #size-cells = <1>;
+                compatible = "fsl,mpc8377-elbc", "fsl,elbc", "simple-bus";
+                reg = <0xe0005000 0x1000>;
+                interrupts = <77 0x8>;
+                interrupt-parent = <&ipic>;
+                ranges = <0x0 0x0 0xfc000000 0x04000000>;
+
+                flash@0,0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "cfi-flash";
+                        reg = <0x0 0x0 0x4000000>;
+                        bank-width = <2>;
+                        device-width = <1>;
+
+                        partition@0 {
+                                reg = <0 0x8000>;
+                                label = "u-boot";
+                                read-only;
+                        };
+
+                        partition@a0000 {
+                                reg = <0xa0000 0x300000>;
+                                label = "kernel";
+                        };
+
+                        partition@3a0000 {
+                                reg = <0x3a0000 0x3c60000>;
+                                label = "rootfs";
+                        };
+                };
+        };
+
+        immr@e0000000 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                device_type = "soc";
+                compatible = "simple-bus";
+                ranges = <0x0 0xe0000000 0x00100000>;
+                reg = <0xe0000000 0x00000200>;
+                bus-frequency = <0>;
+
+                wdt@200 {
+                        device_type = "watchdog";
+                        compatible = "mpc83xx_wdt";
+                        reg = <0x200 0x100>;
+                };
+
+                gpio1: gpio-controller@c00 {
+                        #gpio-cells = <2>;
+                        compatible = "fsl,mpc8377-gpio", "fsl,mpc8349-gpio";
+                        reg = <0xc00 0x100>;
+                        interrupts = <74 0x8>;
+                        interrupt-parent = <&ipic>;
+                        gpio-controller;
+                };
+
+                gpio2: gpio-controller@d00 {
+                        #gpio-cells = <2>;
+                        compatible = "fsl,mpc8377-gpio", "fsl,mpc8349-gpio";
+                        reg = <0xd00 0x100>;
+                        interrupts = <75 0x8>;
+                        interrupt-parent = <&ipic>;
+                        gpio-controller;
+                };
+
+                sleep-nexus {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "simple-bus";
+                        sleep = <&pmc 0x0c000000>;
+                        ranges;
+
+                        i2c@3000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                cell-index = <0>;
+                                compatible = "fsl-i2c";
+                                reg = <0x3000 0x100>;
+                                interrupts = <14 0x8>;
+                                interrupt-parent = <&ipic>;
+                                dfsrr;
+
+                                at24@50 {
+                                        compatible = "at24,24c256";
+                                        reg = <0x50>;
+                                };
+
+                                rtc@68 {
+                                        compatible = "dallas,ds1339";
+                                        reg = <0x68>;
+                                };
+                        };
+
+                        sdhci@2e000 {
+                                compatible = "fsl,mpc8377-esdhc", "fsl,esdhc";
+                                reg = <0x2e000 0x1000>;
+                                interrupts = <42 0x8>;
+                                interrupt-parent = <&ipic>;
+                                clock-frequency = <133333333>;
+                        };
+                };
+
+                i2c@3100 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        cell-index = <1>;
+                        compatible = "fsl-i2c";
+                        reg = <0x3100 0x100>;
+                        interrupts = <15 0x8>;
+                        interrupt-parent = <&ipic>;
+                        dfsrr;
+                };
+
+                spi@7000 {
+                        cell-index = <0>;
+                        compatible = "fsl,spi";
+                        reg = <0x7000 0x1000>;
+                        interrupts = <16 0x8>;
+                        interrupt-parent = <&ipic>;
+                        mode = "cpu";
+                };
+
+                dma@82a8 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "fsl,mpc8377-dma", "fsl,elo-dma";
+                        reg = <0x82a8 4>;
+                        ranges = <0 0x8100 0x1a8>;
+                        interrupt-parent = <&ipic>;
+                        interrupts = <71 8>;
+                        cell-index = <0>;
+                        dma-channel@0 {
+                                compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
+                                reg = <0 0x80>;
+                                cell-index = <0>;
+                                interrupt-parent = <&ipic>;
+                                interrupts = <71 8>;
+                        };
+                        dma-channel@80 {
+                                compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
+                                reg = <0x80 0x80>;
+                                cell-index = <1>;
+                                interrupt-parent = <&ipic>;
+                                interrupts = <71 8>;
+                        };
+                        dma-channel@100 {
+                                compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
+                                reg = <0x100 0x80>;
+                                cell-index = <2>;
+                                interrupt-parent = <&ipic>;
+                                interrupts = <71 8>;
+                        };
+                        dma-channel@180 {
+                                compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
+                                reg = <0x180 0x28>;
+                                cell-index = <3>;
+                                interrupt-parent = <&ipic>;
+                                interrupts = <71 8>;
+                        };
+                };
+
+                usb@23000 {
+                        compatible = "fsl-usb2-dr";
+                        reg = <0x23000 0x1000>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        interrupt-parent = <&ipic>;
+                        interrupts = <38 0x8>;
+                        phy_type = "ulpi";
+                        sleep = <&pmc 0x00c00000>;
+                };
+
+                enet0: ethernet@24000 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        cell-index = <0>;
+                        device_type = "network";
+                        model = "eTSEC";
+                        compatible = "gianfar";
+                        reg = <0x24000 0x1000>;
+                        ranges = <0x0 0x24000 0x1000>;
+                        local-mac-address = [ 00 00 00 00 00 00 ];
+                        interrupts = <32 0x8 33 0x8 34 0x8>;
+                        phy-connection-type = "mii";
+                        interrupt-parent = <&ipic>;
+                        tbi-handle = <&tbi0>;
+                        phy-handle = <&phy2>;
+                        sleep = <&pmc 0xc0000000>;
+                        fsl,magic-packet;
+
+                        mdio@520 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,gianfar-mdio";
+                                reg = <0x520 0x20>;
+
+                                phy2: ethernet-phy@2 {
+                                        interrupt-parent = <&ipic>;
+                                        interrupts = <17 0x8>;
+                                        reg = <0x2>;
+                                        device_type = "ethernet-phy";
+                                };
+
+                                phy3: ethernet-phy@3 {
+                                        interrupt-parent = <&ipic>;
+                                        interrupts = <18 0x8>;
+                                        reg = <0x3>;
+                                        device_type = "ethernet-phy";
+                                };
+
+                                tbi0: tbi-phy@11 {
+                                        reg = <0x11>;
+                                        device_type = "tbi-phy";
+                                };
+                        };
+                };
+
+                enet1: ethernet@25000 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        cell-index = <1>;
+                        device_type = "network";
+                        model = "eTSEC";
+                        compatible = "gianfar";
+                        reg = <0x25000 0x1000>;
+                        ranges = <0x0 0x25000 0x1000>;
+                        local-mac-address = [ 00 00 00 00 00 00 ];
+                        interrupts = <35 0x8 36 0x8 37 0x8>;
+                        phy-connection-type = "mii";
+                        interrupt-parent = <&ipic>;
+                        phy-handle = <&phy3>;
+                        tbi-handle = <&tbi1>;
+                        sleep = <&pmc 0x30000000>;
+                        fsl,magic-packet;
+
+                        mdio@520 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,gianfar-tbi";
+                                reg = <0x520 0x20>;
+
+                                tbi1: tbi-phy@11 {
+                                        reg = <0x11>;
+                                        device_type = "tbi-phy";
+                                };
+                        };
+                };
+
+                serial0: serial@4500 {
+                        cell-index = <0>;
+                        device_type = "serial";
+                        compatible = "ns16550";
+                        reg = <0x4500 0x100>;
+                        clock-frequency = <0>;
+                        interrupts = <9 0x8>;
+                        interrupt-parent = <&ipic>;
+                };
+
+                serial1: serial@4600 {
+                        cell-index = <1>;
+                        device_type = "serial";
+                        compatible = "ns16550";
+                        reg = <0x4600 0x100>;
+                        clock-frequency = <0>;
+                        interrupts = <10 0x8>;
+                        interrupt-parent = <&ipic>;
+                };
+
+                crypto@30000 {
+                        compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
+                                     "fsl,sec2.1", "fsl,sec2.0";
+                        reg = <0x30000 0x10000>;
+                        interrupts = <11 0x8>;
+                        interrupt-parent = <&ipic>;
+                        fsl,num-channels = <4>;
+                        fsl,channel-fifo-len = <24>;
+                        fsl,exec-units-mask = <0x9fe>;
+                        fsl,descriptor-types-mask = <0x3ab0ebf>;
+                        sleep = <&pmc 0x03000000>;
+                };
+
+                sata@18000 {
+                        compatible = "fsl,mpc8377-sata", "fsl,pq-sata";
+                        reg = <0x18000 0x1000>;
+                        interrupts = <44 0x8>;
+                        interrupt-parent = <&ipic>;
+                        sleep = <&pmc 0x000000c0>;
+                };
+
+                sata@19000 {
+                        compatible = "fsl,mpc8377-sata", "fsl,pq-sata";
+                        reg = <0x19000 0x1000>;
+                        interrupts = <45 0x8>;
+                        interrupt-parent = <&ipic>;
+                        sleep = <&pmc 0x00000030>;
+                };
+
+                /* IPIC
+                 * interrupts cell = <intr #, sense>
+                 * sense values match linux IORESOURCE_IRQ_* defines:
+                 * sense == 8: Level, low assertion
+                 * sense == 2: Edge, high-to-low change
+                 */
+                ipic: interrupt-controller@700 {
+                        compatible = "fsl,ipic";
+                        interrupt-controller;
+                        #address-cells = <0>;
+                        #interrupt-cells = <2>;
+                        reg = <0x700 0x100>;
+                };
+
+                pmc: power@b00 {
+                        compatible = "fsl,mpc8377-pmc", "fsl,mpc8349-pmc";
+                        reg = <0xb00 0x100 0xa00 0x100>;
+                        interrupts = <80 0x8>;
+                        interrupt-parent = <&ipic>;
+                };
+        };
+
+        pci0: pci@e0008500 {
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                                /* IRQ5 = 21 = 0x15, IRQ6 = 0x16, IRQ7 = 23 = 0x17 */
+
+                                /* IDSEL AD14 IRQ6 inta */
+                                 0x7000 0x0 0x0 0x1 &ipic 22 0x8
+
+                                /* IDSEL AD15 IRQ5 inta */
+                                 0x7800 0x0 0x0 0x1 &ipic 21 0x8>;
+                interrupt-parent = <&ipic>;
+                interrupts = <66 0x8>;
+                bus-range = <0 0>;
+                ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
+                          0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
+                          0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
+                sleep = <&pmc 0x00010000>;
+                clock-frequency = <66666666>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                reg = <0xe0008500 0x100         /* internal registers */
+                       0xe0008300 0x8>;         /* config space access registers */
+                compatible = "fsl,mpc8349-pci";
+                device_type = "pci";
+        };
+
+        pci1: pcie@e0009000 {
+                #address-cells = <3>;
+                #size-cells = <2>;
+                #interrupt-cells = <1>;
+                device_type = "pci";
+                compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
+                reg = <0xe0009000 0x00001000>;
+                ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000
+                          0x01000000 0 0x00000000 0xb8000000 0 0x00800000>;
+                bus-range = <0 255>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <0 0 0 1 &ipic 1 8
+                                 0 0 0 2 &ipic 1 8
+                                 0 0 0 3 &ipic 1 8
+                                 0 0 0 4 &ipic 1 8>;
+                sleep = <&pmc 0x00300000>;
+                clock-frequency = <0>;
+
+                pcie@0 {
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+                        device_type = "pci";
+                        reg = <0 0 0 0 0>;
+                        ranges = <0x02000000 0 0xa8000000
+                                  0x02000000 0 0xa8000000
+                                  0 0x10000000
+                                  0x01000000 0 0x00000000
+                                  0x01000000 0 0x00000000
+                                  0 0x00800000>;
+                };
+        };
+
+        pci2: pcie@e000a000 {
+                #address-cells = <3>;
+                #size-cells = <2>;
+                #interrupt-cells = <1>;
+                device_type = "pci";
+                compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
+                reg = <0xe000a000 0x00001000>;
+                ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000
+                          0x01000000 0 0x00000000 0xd8000000 0 0x00800000>;
+                bus-range = <0 255>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <0 0 0 1 &ipic 2 8
+                                 0 0 0 2 &ipic 2 8
+                                 0 0 0 3 &ipic 2 8
+                                 0 0 0 4 &ipic 2 8>;
+                sleep = <&pmc 0x000c0000>;
+                clock-frequency = <0>;
+
+                pcie@0 {
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+                        device_type = "pci";
+                        reg = <0 0 0 0 0>;
+                        ranges = <0x02000000 0 0xc8000000
+                                  0x02000000 0 0xc8000000
+                                  0 0x10000000
+                                  0x01000000 0 0x00000000
+                                  0x01000000 0 0x00000000
+                                  0 0x00800000>;
+                };
+        };
+};
diff --git a/arch/powerpc/boot/dts/mpc8378_rdb.dts b/arch/powerpc/boot/dts/mpc8378_rdb.dts
index aabf3437cadf..a11ead8214b4 100644
--- a/arch/powerpc/boot/dts/mpc8378_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc8378_rdb.dts
@@ -174,7 +174,7 @@
                                 interrupts = <42 0x8>;
                                 interrupt-parent = <&ipic>;
                                 /* Filled in by U-Boot */
-                                clock-frequency = <0>;
+                                clock-frequency = <111111111>;
                         };
                 };
 
diff --git a/arch/powerpc/boot/dts/mpc8379_rdb.dts b/arch/powerpc/boot/dts/mpc8379_rdb.dts
index 9b1da864d890..e35dfba587c8 100644
--- a/arch/powerpc/boot/dts/mpc8379_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc8379_rdb.dts
@@ -172,7 +172,7 @@
                                 interrupts = <42 0x8>;
                                 interrupt-parent = <&ipic>;
                                 /* Filled in by U-Boot */
-                                clock-frequency = <0>;
+                                clock-frequency = <111111111>;
                         };
                 };
 
diff --git a/arch/powerpc/boot/dts/mpc8536ds.dts b/arch/powerpc/boot/dts/mpc8536ds.dts
index e781ad2f1f8a..22caf69e6efd 100644
--- a/arch/powerpc/boot/dts/mpc8536ds.dts
+++ b/arch/powerpc/boot/dts/mpc8536ds.dts
@@ -14,8 +14,8 @@
 / {
         model = "fsl,mpc8536ds";
         compatible = "fsl,mpc8536ds";
-        #address-cells = <1>;
-        #size-cells = <1>;
+        #address-cells = <2>;
+        #size-cells = <2>;
 
         aliases {
                 ethernet0 = &enet0;
@@ -42,7 +42,7 @@
 
         memory {
                 device_type = "memory";
-                reg = <00000000 00000000>;      // Filled by U-Boot
+                reg = <0 0 0 0>;        // Filled by U-Boot
         };
 
         soc@ffe00000 {
@@ -50,7 +50,7 @@
                 #size-cells = <1>;
                 device_type = "soc";
                 compatible = "simple-bus";
-                ranges = <0x0 0xffe00000 0x100000>;
+                ranges = <0x0 0 0xffe00000 0x100000>;
                 bus-frequency = <0>;            // Filled out by uboot.
 
                 ecm-law@0 {
@@ -347,13 +347,13 @@
                 interrupt-parent = <&mpic>;
                 interrupts = <24 0x2>;
                 bus-range = <0 0xff>;
-                ranges = <0x02000000 0 0x80000000 0x80000000 0 0x10000000
-                          0x01000000 0 0x00000000 0xffc00000 0 0x00010000>;
+                ranges = <0x02000000 0 0x80000000 0 0x80000000 0 0x10000000
+                          0x01000000 0 0x00000000 0 0xffc00000 0 0x00010000>;
                 clock-frequency = <66666666>;
                 #interrupt-cells = <1>;
                 #size-cells = <2>;
                 #address-cells = <3>;
-                reg = <0xffe08000 0x1000>;
+                reg = <0 0xffe08000 0 0x1000>;
         };
 
         pci1: pcie@ffe09000 {
@@ -362,10 +362,10 @@
                 #interrupt-cells = <1>;
                 #size-cells = <2>;
                 #address-cells = <3>;
-                reg = <0xffe09000 0x1000>;
+                reg = <0 0xffe09000 0 0x1000>;
                 bus-range = <0 0xff>;
-                ranges = <0x02000000 0 0x98000000 0x98000000 0 0x08000000
-                          0x01000000 0 0x00000000 0xffc20000 0 0x00010000>;
+                ranges = <0x02000000 0 0x98000000 0 0x98000000 0 0x08000000
+                          0x01000000 0 0x00000000 0 0xffc20000 0 0x00010000>;
                 clock-frequency = <33333333>;
                 interrupt-parent = <&mpic>;
                 interrupts = <25 0x2>;
@@ -398,10 +398,10 @@
                 #interrupt-cells = <1>;
                 #size-cells = <2>;
                 #address-cells = <3>;
-                reg = <0xffe0a000 0x1000>;
+                reg = <0 0xffe0a000 0 0x1000>;
                 bus-range = <0 0xff>;
-                ranges = <0x02000000 0 0x90000000 0x90000000 0 0x08000000
-                          0x01000000 0 0x00000000 0xffc10000 0 0x00010000>;
+                ranges = <0x02000000 0 0x90000000 0 0x90000000 0 0x08000000
+                          0x01000000 0 0x00000000 0 0xffc10000 0 0x00010000>;
                 clock-frequency = <33333333>;
                 interrupt-parent = <&mpic>;
                 interrupts = <26 0x2>;
@@ -434,10 +434,10 @@
                 #interrupt-cells = <1>;
                 #size-cells = <2>;
                 #address-cells = <3>;
-                reg = <0xffe0b000 0x1000>;
+                reg = <0 0xffe0b000 0 0x1000>;
                 bus-range = <0 0xff>;
-                ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x20000000
-                          0x01000000 0 0x00000000 0xffc30000 0 0x00010000>;
+                ranges = <0x02000000 0 0xa0000000 0 0xa0000000 0 0x20000000
+                          0x01000000 0 0x00000000 0 0xffc30000 0 0x00010000>;
                 clock-frequency = <33333333>;
                 interrupt-parent = <&mpic>;
                 interrupts = <27 0x2>;
diff --git a/arch/powerpc/boot/dts/mpc8536ds_36b.dts b/arch/powerpc/boot/dts/mpc8536ds_36b.dts
new file mode 100644
index 000000000000..113ed8b7c898
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8536ds_36b.dts
@@ -0,0 +1,467 @@
+/*
+ * MPC8536 DS Device Tree Source
+ *
+ * Copyright 2008-2009 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+
+/ {
+        model = "fsl,mpc8536ds";
+        compatible = "fsl,mpc8536ds";
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        aliases {
+                ethernet0 = &enet0;
+                ethernet1 = &enet1;
+                serial0 = &serial0;
+                serial1 = &serial1;
+                pci0 = &pci0;
+                pci1 = &pci1;
+                pci2 = &pci2;
+                pci3 = &pci3;
+        };
+
+        cpus {
+                #cpus = <1>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                PowerPC,8536@0 {
+                        device_type = "cpu";
+                        reg = <0>;
+                        next-level-cache = <&L2>;
+                };
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0 0 0 0>;        // Filled by U-Boot
+        };
+
+        soc@fffe00000 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                device_type = "soc";
+                compatible = "simple-bus";
+                ranges = <0x0 0xf 0xffe00000 0x100000>;
+                bus-frequency = <0>;            // Filled out by uboot.
+
+                ecm-law@0 {
+                        compatible = "fsl,ecm-law";
+                        reg = <0x0 0x1000>;
+                        fsl,num-laws = <12>;
+                };
+
+                ecm@1000 {
+                        compatible = "fsl,mpc8536-ecm", "fsl,ecm";
+                        reg = <0x1000 0x1000>;
+                        interrupts = <17 2>;
+                        interrupt-parent = <&mpic>;
+                };
+
+                memory-controller@2000 {
+                        compatible = "fsl,mpc8536-memory-controller";
+                        reg = <0x2000 0x1000>;
+                        interrupt-parent = <&mpic>;
+                        interrupts = <18 0x2>;
+                };
+
+                L2: l2-cache-controller@20000 {
+                        compatible = "fsl,mpc8536-l2-cache-controller";
+                        reg = <0x20000 0x1000>;
+                        interrupt-parent = <&mpic>;
+                        interrupts = <16 0x2>;
+                };
+
+                i2c@3000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        cell-index = <0>;
+                        compatible = "fsl-i2c";
+                        reg = <0x3000 0x100>;
+                        interrupts = <43 0x2>;
+                        interrupt-parent = <&mpic>;
+                        dfsrr;
+                };
+
+                i2c@3100 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        cell-index = <1>;
+                        compatible = "fsl-i2c";
+                        reg = <0x3100 0x100>;
+                        interrupts = <43 0x2>;
+                        interrupt-parent = <&mpic>;
+                        dfsrr;
+                        rtc@68 {
+                                compatible = "dallas,ds3232";
+                                reg = <0x68>;
+                                interrupts = <0 0x1>;
+                                interrupt-parent = <&mpic>;
+                        };
+                };
+
+                dma@21300 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "fsl,mpc8536-dma", "fsl,eloplus-dma";
+                        reg = <0x21300 4>;
+                        ranges = <0 0x21100 0x200>;
+                        cell-index = <0>;
+                        dma-channel@0 {
+                                compatible = "fsl,mpc8536-dma-channel",
+                                             "fsl,eloplus-dma-channel";
+                                reg = <0x0 0x80>;
+                                cell-index = <0>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <20 2>;
+                        };
+                        dma-channel@80 {
+                                compatible = "fsl,mpc8536-dma-channel",
+                                             "fsl,eloplus-dma-channel";
+                                reg = <0x80 0x80>;
+                                cell-index = <1>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <21 2>;
+                        };
+                        dma-channel@100 {
+                                compatible = "fsl,mpc8536-dma-channel",
+                                             "fsl,eloplus-dma-channel";
+                                reg = <0x100 0x80>;
+                                cell-index = <2>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <22 2>;
+                        };
+                        dma-channel@180 {
+                                compatible = "fsl,mpc8536-dma-channel",
+                                             "fsl,eloplus-dma-channel";
+                                reg = <0x180 0x80>;
+                                cell-index = <3>;
+                                interrupt-parent = <&mpic>;
+                                interrupts = <23 2>;
+                        };
+                };
+
+                usb@22000 {
+                        compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
+                        reg = <0x22000 0x1000>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        interrupt-parent = <&mpic>;
+                        interrupts = <28 0x2>;
+                        phy_type = "ulpi";
+                };
+
+                usb@23000 {
+                        compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
+                        reg = <0x23000 0x1000>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        interrupt-parent = <&mpic>;
+                        interrupts = <46 0x2>;
+                        phy_type = "ulpi";
+                };
+
+                enet0: ethernet@24000 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        cell-index = <0>;
+                        device_type = "network";
+                        model = "eTSEC";
+                        compatible = "gianfar";
+                        reg = <0x24000 0x1000>;
+                        ranges = <0x0 0x24000 0x1000>;
+                        local-mac-address = [ 00 00 00 00 00 00 ];
+                        interrupts = <29 2 30 2 34 2>;
+                        interrupt-parent = <&mpic>;
+                        tbi-handle = <&tbi0>;
+                        phy-handle = <&phy1>;
+                        phy-connection-type = "rgmii-id";
+
+                        mdio@520 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,gianfar-mdio";
+                                reg = <0x520 0x20>;
+
+                                phy0: ethernet-phy@0 {
+                                        interrupt-parent = <&mpic>;
+                                        interrupts = <10 0x1>;
+                                        reg = <0>;
+                                        device_type = "ethernet-phy";
+                                };
+                                phy1: ethernet-phy@1 {
+                                        interrupt-parent = <&mpic>;
+                                        interrupts = <10 0x1>;
+                                        reg = <1>;
+                                        device_type = "ethernet-phy";
+                                };
+                                tbi0: tbi-phy@11 {
+                                        reg = <0x11>;
+                                        device_type = "tbi-phy";
+                                };
+                        };
+                };
+
+                enet1: ethernet@26000 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        cell-index = <1>;
+                        device_type = "network";
+                        model = "eTSEC";
+                        compatible = "gianfar";
+                        reg = <0x26000 0x1000>;
+                        ranges = <0x0 0x26000 0x1000>;
+                        local-mac-address = [ 00 00 00 00 00 00 ];
+                        interrupts = <31 2 32 2 33 2>;
+                        interrupt-parent = <&mpic>;
+                        tbi-handle = <&tbi1>;
+                        phy-handle = <&phy0>;
+                        phy-connection-type = "rgmii-id";
+
+                        mdio@520 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,gianfar-tbi";
+                                reg = <0x520 0x20>;
+
+                                tbi1: tbi-phy@11 {
+                                        reg = <0x11>;
+                                        device_type = "tbi-phy";
+                                };
+                        };
+                };
+
+                usb@2b000 {
+                        compatible = "fsl,mpc8536-usb2-dr", "fsl-usb2-dr";
+                        reg = <0x2b000 0x1000>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        interrupt-parent = <&mpic>;
+                        interrupts = <60 0x2>;
+                        dr_mode = "peripheral";
+                        phy_type = "ulpi";
+                };
+
+                serial0: serial@4500 {
+                        cell-index = <0>;
+                        device_type = "serial";
+                        compatible = "ns16550";
+                        reg = <0x4500 0x100>;
+                        clock-frequency = <0>;
+                        interrupts = <42 0x2>;
+                        interrupt-parent = <&mpic>;
+                };
+
+                serial1: serial@4600 {
+                        cell-index = <1>;
+                        device_type = "serial";
+                        compatible = "ns16550";
+                        reg = <0x4600 0x100>;
+                        clock-frequency = <0>;
+                        interrupts = <42 0x2>;
+                        interrupt-parent = <&mpic>;
+                };
+
+                crypto@30000 {
+                        compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
+                                     "fsl,sec2.1", "fsl,sec2.0";
+                        reg = <0x30000 0x10000>;
+                        interrupts = <45 2 58 2>;
+                        interrupt-parent = <&mpic>;
+                        fsl,num-channels = <4>;
+                        fsl,channel-fifo-len = <24>;
+                        fsl,exec-units-mask = <0x9fe>;
+                        fsl,descriptor-types-mask = <0x3ab0ebf>;
+                };
+
+                sata@18000 {
+                        compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
+                        reg = <0x18000 0x1000>;
+                        cell-index = <1>;
+                        interrupts = <74 0x2>;
+                        interrupt-parent = <&mpic>;
+                };
+
+                sata@19000 {
+                        compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
+                        reg = <0x19000 0x1000>;
+                        cell-index = <2>;
+                        interrupts = <41 0x2>;
+                        interrupt-parent = <&mpic>;
+                };
+
+                global-utilities@e0000 {        //global utilities block
+                        compatible = "fsl,mpc8548-guts";
+                        reg = <0xe0000 0x1000>;
+                        fsl,has-rstcr;
+                };
+
+                mpic: pic@40000 {
+                        clock-frequency = <0>;
+                        interrupt-controller;
+                        #address-cells = <0>;
+                        #interrupt-cells = <2>;
+                        reg = <0x40000 0x40000>;
+                        compatible = "chrp,open-pic";
+                        device_type = "open-pic";
+                        big-endian;
+                };
+
+                msi@41600 {
+                        compatible = "fsl,mpc8536-msi", "fsl,mpic-msi";
+                        reg = <0x41600 0x80>;
+                        msi-available-ranges = <0 0x100>;
+                        interrupts = <
+                                0xe0 0
+                                0xe1 0
+                                0xe2 0
+                                0xe3 0
+                                0xe4 0
+                                0xe5 0
+                                0xe6 0
+                                0xe7 0>;
+                        interrupt-parent = <&mpic>;
+                };
+        };
+
+        pci0: pci@fffe08000 {
+                compatible = "fsl,mpc8540-pci";
+                device_type = "pci";
+                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+                interrupt-map = <
+
+                        /* IDSEL 0x11 J17 Slot 1 */
+                        0x8800 0 0 1 &mpic 1 1
+                        0x8800 0 0 2 &mpic 2 1
+                        0x8800 0 0 3 &mpic 3 1
+                        0x8800 0 0 4 &mpic 4 1>;
+
+                interrupt-parent = <&mpic>;
+                interrupts = <24 0x2>;
+                bus-range = <0 0xff>;
+                ranges = <0x02000000 0 0xf0000000 0xc 0x00000000 0 0x10000000
+                          0x01000000 0 0x00000000 0xf 0xffc00000 0 0x00010000>;
+                clock-frequency = <66666666>;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                reg = <0xf 0xffe08000 0 0x1000>;
+        };
+
+        pci1: pcie@fffe09000 {
+                compatible = "fsl,mpc8548-pcie";
+                device_type = "pci";
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                reg = <0xf 0xffe09000 0 0x1000>;
+                bus-range = <0 0xff>;
+                ranges = <0x02000000 0 0xf8000000 0xc 0x18000000 0 0x08000000
+                          0x01000000 0 0x00000000 0xf 0xffc20000 0 0x00010000>;
+                clock-frequency = <33333333>;
+                interrupt-parent = <&mpic>;
+                interrupts = <25 0x2>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0 0 1 &mpic 4 1
+                        0000 0 0 2 &mpic 5 1
+                        0000 0 0 3 &mpic 6 1
+                        0000 0 0 4 &mpic 7 1
+                        >;
+                pcie@0 {
+                        reg = <0 0 0 0 0>;
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        device_type = "pci";
+                        ranges = <0x02000000 0 0xf8000000
+                                  0x02000000 0 0xf8000000
+                                  0 0x08000000
+
+                                  0x01000000 0 0x00000000
+                                  0x01000000 0 0x00000000
+                                  0 0x00010000>;
+                };
+        };
+
+        pci2: pcie@fffe0a000 {
+                compatible = "fsl,mpc8548-pcie";
+                device_type = "pci";
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                reg = <0xf 0xffe0a000 0 0x1000>;
+                bus-range = <0 0xff>;
+                ranges = <0x02000000 0 0xf8000000 0xc 0x10000000 0 0x08000000
+                          0x01000000 0 0x00000000 0xf 0xffc10000 0 0x00010000>;
+                clock-frequency = <33333333>;
+                interrupt-parent = <&mpic>;
+                interrupts = <26 0x2>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0 0 1 &mpic 0 1
+                        0000 0 0 2 &mpic 1 1
+                        0000 0 0 3 &mpic 2 1
+                        0000 0 0 4 &mpic 3 1
+                        >;
+                pcie@0 {
+                        reg = <0 0 0 0 0>;
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        device_type = "pci";
+                        ranges = <0x02000000 0 0xf8000000
+                                  0x02000000 0 0xf8000000
+                                  0 0x08000000
+
+                                  0x01000000 0 0x00000000
+                                  0x01000000 0 0x00000000
+                                  0 0x00010000>;
+                };
+        };
+
+        pci3: pcie@fffe0b000 {
+                compatible = "fsl,mpc8548-pcie";
+                device_type = "pci";
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                reg = <0xf 0xffe0b000 0 0x1000>;
+                bus-range = <0 0xff>;
+                ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x20000000
+                          0x01000000 0 0x00000000 0xf 0xffc30000 0 0x00010000>;
+                clock-frequency = <33333333>;
+                interrupt-parent = <&mpic>;
+                interrupts = <27 0x2>;
+                interrupt-map-mask = <0xf800 0 0 7>;
+                interrupt-map = <
+                        /* IDSEL 0x0 */
+                        0000 0 0 1 &mpic 8 1
+                        0000 0 0 2 &mpic 9 1
+                        0000 0 0 3 &mpic 10 1
+                        0000 0 0 4 &mpic 11 1
+                        >;
+
+                pcie@0 {
+                        reg = <0 0 0 0 0>;
+                        #size-cells = <2>;
+                        #address-cells = <3>;
+                        device_type = "pci";
+                        ranges = <0x02000000 0 0xe0000000
+                                  0x02000000 0 0xe0000000
+                                  0 0x20000000
+
+                                  0x01000000 0 0x00000000
+                                  0x01000000 0 0x00000000
+                                  0 0x00100000>;
+                };
+        };
+};
diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts
index 475be1433fe1..4173af387c63 100644
--- a/arch/powerpc/boot/dts/mpc8548cds.dts
+++ b/arch/powerpc/boot/dts/mpc8548cds.dts
@@ -100,6 +100,21 @@
                         interrupts = <43 2>;
                         interrupt-parent = <&mpic>;
                         dfsrr;
+
+                        eeprom@50 {
+                                compatible = "atmel,24c64";
+                                reg = <0x50>;
+                        };
+
+                        eeprom@56 {
+                                compatible = "atmel,24c64";
+                                reg = <0x56>;
+                        };
+
+                        eeprom@57 {
+                                compatible = "atmel,24c64";
+                                reg = <0x57>;
+                        };
                 };
 
                 i2c@3100 {
@@ -111,6 +126,11 @@
                         interrupts = <43 2>;
                         interrupt-parent = <&mpic>;
                         dfsrr;
+
+                        eeprom@50 {
+                                compatible = "atmel,24c64";
+                                reg = <0x50>;
+                        };
                 };
 
                 dma@21300 {
diff --git a/arch/powerpc/boot/mktree.c b/arch/powerpc/boot/mktree.c
index c2baae0a3d89..e2ae24340fc8 100644
--- a/arch/powerpc/boot/mktree.c
+++ b/arch/powerpc/boot/mktree.c
@@ -36,7 +36,7 @@ typedef struct boot_block {
 } boot_block_t;
 
 #define IMGBLK  512
-char    tmpbuf[IMGBLK];
+unsigned int    tmpbuf[IMGBLK / sizeof(unsigned int)];
 
 int main(int argc, char *argv[])
 {
@@ -95,13 +95,13 @@ int main(int argc, char *argv[])
 
         /* Assume zImage is an ELF file, and skip the 64K header.
         */
-        if (read(in_fd, tmpbuf, IMGBLK) != IMGBLK) {
+        if (read(in_fd, tmpbuf, sizeof(tmpbuf)) != sizeof(tmpbuf)) {
                 fprintf(stderr, "%s is too small to be an ELF image\n",
                                 argv[1]);
                 exit(4);
         }
 
-        if ((*(unsigned int *)tmpbuf) != htonl(0x7f454c46)) {
+        if (tmpbuf[0] != htonl(0x7f454c46)) {
                 fprintf(stderr, "%s is not an ELF image\n", argv[1]);
                 exit(4);
         }
@@ -121,11 +121,11 @@ int main(int argc, char *argv[])
         }
 
         while (nblks-- > 0) {
-                if (read(in_fd, tmpbuf, IMGBLK) < 0) {
+                if (read(in_fd, tmpbuf, sizeof(tmpbuf)) < 0) {
                         perror("zImage read");
                         exit(5);
                 }
-                cp = (unsigned int *)tmpbuf;
+                cp = tmpbuf;
                 for (i = 0; i < sizeof(tmpbuf) / sizeof(unsigned int); i++)
                         cksum += *cp++;
                 if (write(out_fd, tmpbuf, sizeof(tmpbuf)) != sizeof(tmpbuf)) {
diff --git a/arch/powerpc/boot/wrapper b/arch/powerpc/boot/wrapper
index 4db487d1d2a8..ac9e9a58b2b0 100755
--- a/arch/powerpc/boot/wrapper
+++ b/arch/powerpc/boot/wrapper
@@ -46,6 +46,7 @@ CROSS=
 # directory for object and other files used by this script
 object=arch/powerpc/boot
 objbin=$object
+dtc=scripts/dtc/dtc
 
 # directory for working files
 tmpdir=.
@@ -124,7 +125,7 @@ if [ -n "$dts" ]; then
     if [ -z "$dtb" ]; then
         dtb="$platform.dtb"
     fi
-    $object/dtc -O dtb -o "$dtb" -b 0 "$dts"
+    $dtc -O dtb -o "$dtb" -b 0 "$dts"
 fi
 
 if [ -z "$kernel" ]; then
diff --git a/arch/powerpc/configs/40x/kilauea_defconfig b/arch/powerpc/configs/40x/kilauea_defconfig
index 865725effe93..9a05ec0ec312 100644
--- a/arch/powerpc/configs/40x/kilauea_defconfig
+++ b/arch/powerpc/configs/40x/kilauea_defconfig
@@ -1,14 +1,14 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.30-rc7
-# Wed Jun  3 10:18:16 2009
+# Linux kernel version: 2.6.31-rc4
+# Wed Jul 29 13:28:37 2009
 #
 # CONFIG_PPC64 is not set
 
 #
 # Processor support
 #
-# CONFIG_6xx is not set
+# CONFIG_PPC_BOOK3S_32 is not set
 # CONFIG_PPC_85xx is not set
 # CONFIG_PPC_8xx is not set
 CONFIG_40x=y
@@ -32,11 +32,11 @@ CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
 CONFIG_IRQ_PER_CPU=y
 CONFIG_STACKTRACE_SUPPORT=y
 CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 CONFIG_LOCKDEP_SUPPORT=y
 CONFIG_RWSEM_XCHGADD_ALGORITHM=y
 CONFIG_ARCH_HAS_ILOG2_U32=y
 CONFIG_GENERIC_HWEIGHT=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
 CONFIG_GENERIC_FIND_NEXT_BIT=y
 # CONFIG_ARCH_NO_VIRT_TO_BUS is not set
 CONFIG_PPC=y
@@ -57,6 +57,7 @@ CONFIG_PPC_DCR_NATIVE=y
 CONFIG_PPC_DCR=y
 CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
 
 #
 # General setup
@@ -108,7 +109,6 @@ CONFIG_SYSCTL_SYSCALL=y
 CONFIG_KALLSYMS=y
 CONFIG_KALLSYMS_ALL=y
 CONFIG_KALLSYMS_EXTRA_PASS=y
-# CONFIG_STRIP_ASM_SYMS is not set
 CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
@@ -121,9 +121,16 @@ CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
 CONFIG_AIO=y
+CONFIG_HAVE_PERF_COUNTERS=y
+
+#
+# Performance Counters
+#
+# CONFIG_PERF_COUNTERS is not set
 CONFIG_VM_EVENT_COUNTERS=y
 CONFIG_PCI_QUIRKS=y
 CONFIG_SLUB_DEBUG=y
+# CONFIG_STRIP_ASM_SYMS is not set
 CONFIG_COMPAT_BRK=y
 # CONFIG_SLAB is not set
 CONFIG_SLUB=y
@@ -137,6 +144,11 @@ CONFIG_HAVE_IOREMAP_PROT=y
 CONFIG_HAVE_KPROBES=y
 CONFIG_HAVE_KRETPROBES=y
 CONFIG_HAVE_ARCH_TRACEHOOK=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
 # CONFIG_SLOW_WORK is not set
 # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
 CONFIG_SLABINFO=y
@@ -149,7 +161,7 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_BLOCK=y
-CONFIG_LBD=y
+CONFIG_LBDAF=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_BLK_DEV_INTEGRITY is not set
 
@@ -220,6 +232,7 @@ CONFIG_BINFMT_ELF=y
 # CONFIG_BINFMT_MISC is not set
 # CONFIG_MATH_EMULATION is not set
 # CONFIG_IOMMU_HELPER is not set
+# CONFIG_SWIOTLB is not set
 CONFIG_PPC_NEED_DMA_SYNC_OPS=y
 CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
 CONFIG_ARCH_HAS_WALK_MEMORY=y
@@ -239,9 +252,9 @@ CONFIG_MIGRATION=y
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_BOUNCE=y
 CONFIG_VIRT_TO_BUS=y
-CONFIG_UNEVICTABLE_LRU=y
 CONFIG_HAVE_MLOCK=y
 CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
 CONFIG_PPC_4K_PAGES=y
 # CONFIG_PPC_16K_PAGES is not set
 # CONFIG_PPC_64K_PAGES is not set
@@ -344,6 +357,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
 # CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
 # CONFIG_NET_SCHED is not set
 # CONFIG_DCB is not set
 
@@ -393,9 +407,8 @@ CONFIG_MTD_OF_PARTS=y
 # User Modules And Translation Layers
 #
 CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLKDEVS=m
-CONFIG_MTD_BLOCK=m
-# CONFIG_MTD_BLOCK_RO is not set
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
 # CONFIG_FTL is not set
 # CONFIG_NFTL is not set
 # CONFIG_INFTL is not set
@@ -452,7 +465,17 @@ CONFIG_MTD_PHYSMAP_OF=y
 # CONFIG_MTD_DOC2000 is not set
 # CONFIG_MTD_DOC2001 is not set
 # CONFIG_MTD_DOC2001PLUS is not set
-# CONFIG_MTD_NAND is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+CONFIG_MTD_NAND_ECC_SMC=y
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+CONFIG_MTD_NAND_NDFC=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_CAFE is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_NAND_FSL_ELBC is not set
 # CONFIG_MTD_ONENAND is not set
 
 #
@@ -465,6 +488,7 @@ CONFIG_MTD_PHYSMAP_OF=y
 #
 # CONFIG_MTD_UBI is not set
 CONFIG_OF_DEVICE=y
+CONFIG_OF_I2C=y
 # CONFIG_PARPORT is not set
 CONFIG_BLK_DEV=y
 # CONFIG_BLK_DEV_FD is not set
@@ -504,14 +528,17 @@ CONFIG_HAVE_IDE=y
 #
 
 #
-# Enable only one of the two stacks, unless you know what you are doing
+# You can enable one or both FireWire driver stacks.
+#
+
+#
+# See the help texts for more information.
 #
 # CONFIG_FIREWIRE is not set
 # CONFIG_IEEE1394 is not set
 # CONFIG_I2O is not set
 # CONFIG_MACINTOSH_DRIVERS is not set
 CONFIG_NETDEVICES=y
-CONFIG_COMPAT_NET_DEV_OPS=y
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
 # CONFIG_MACVLAN is not set
@@ -546,6 +573,7 @@ CONFIG_IBM_NEW_EMAC_EMAC4=y
 # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
 # CONFIG_NET_PCI is not set
 # CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
 # CONFIG_ATL2 is not set
 # CONFIG_NETDEV_1000 is not set
 # CONFIG_NETDEV_10000 is not set
@@ -621,20 +649,150 @@ CONFIG_LEGACY_PTY_COUNT=256
 # CONFIG_IPMI_HANDLER is not set
 # CONFIG_HW_RANDOM is not set
 # CONFIG_NVRAM is not set
-# CONFIG_GEN_RTC is not set
 # CONFIG_R3964 is not set
 # CONFIG_APPLICOM is not set
 # CONFIG_RAW_DRIVER is not set
 # CONFIG_TCG_TPM is not set
 CONFIG_DEVPORT=y
-# CONFIG_I2C is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# PC SMBus host controller drivers
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_ISCH is not set
+# CONFIG_I2C_PIIX4 is not set
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+CONFIG_I2C_IBM_IIC=y
+# CONFIG_I2C_MPC is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+
+#
+# Graphics adapter I2C/DDC channel drivers
+#
+# CONFIG_I2C_VOODOO3 is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
 # CONFIG_SPI is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
 CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
 # CONFIG_GPIOLIB is not set
 # CONFIG_W1 is not set
 # CONFIG_POWER_SUPPLY is not set
-# CONFIG_HWMON is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7462 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7473 is not set
+# CONFIG_SENSORS_ADT7475 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_I5K_AMB is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_G760A is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+CONFIG_SENSORS_LM75=y
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_LTC4215 is not set
+# CONFIG_SENSORS_LTC4245 is not set
+# CONFIG_SENSORS_LM95241 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_SIS5595 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_TMP401 is not set
+# CONFIG_SENSORS_VIA686A is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_VT8231 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
 CONFIG_THERMAL=y
+# CONFIG_THERMAL_HWMON is not set
 # CONFIG_WATCHDOG is not set
 CONFIG_SSB_POSSIBLE=y
 
@@ -649,24 +807,15 @@ CONFIG_SSB_POSSIBLE=y
 # CONFIG_MFD_CORE is not set
 # CONFIG_MFD_SM501 is not set
 # CONFIG_HTC_PASIC3 is not set
+# CONFIG_TWL4030_CORE is not set
 # CONFIG_MFD_TMIO is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_AB3100_CORE is not set
 # CONFIG_REGULATOR is not set
-
-#
-# Multimedia devices
-#
-
-#
-# Multimedia core support
-#
-# CONFIG_VIDEO_DEV is not set
-# CONFIG_DVB_CORE is not set
-# CONFIG_VIDEO_MEDIA is not set
-
-#
-# Multimedia drivers
-#
-# CONFIG_DAB is not set
+# CONFIG_MEDIA_SUPPORT is not set
 
 #
 # Graphics support
@@ -691,10 +840,69 @@ CONFIG_SSB_POSSIBLE=y
 # CONFIG_ACCESSIBILITY is not set
 # CONFIG_INFINIBAND is not set
 # CONFIG_EDAC is not set
-# CONFIG_RTC_CLASS is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+CONFIG_RTC_DRV_DS1307=y
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+
+#
+# SPI RTC drivers
+#
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_RTC_DRV_GENERIC is not set
 # CONFIG_DMADEVICES is not set
 # CONFIG_AUXDISPLAY is not set
 # CONFIG_UIO is not set
+
+#
+# TI VLYNQ
+#
 # CONFIG_STAGING is not set
 
 #
@@ -708,11 +916,12 @@ CONFIG_EXT2_FS=y
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
-CONFIG_FILE_LOCKING=y
 # CONFIG_XFS_FS is not set
 # CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
 # CONFIG_BTRFS_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
 CONFIG_DNOTIFY=y
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
@@ -818,6 +1027,7 @@ CONFIG_HAS_IOPORT=y
 CONFIG_HAS_DMA=y
 CONFIG_HAVE_LMB=y
 CONFIG_NLATTR=y
+CONFIG_GENERIC_ATOMIC64=y
 
 #
 # Kernel hacking
@@ -848,6 +1058,9 @@ CONFIG_SCHED_DEBUG=y
 # CONFIG_RT_MUTEX_TESTER is not set
 # CONFIG_DEBUG_SPINLOCK is not set
 # CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
 # CONFIG_DEBUG_SPINLOCK_SLEEP is not set
 # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
 # CONFIG_DEBUG_KOBJECT is not set
@@ -859,7 +1072,6 @@ CONFIG_DEBUG_BUGVERBOSE=y
 # CONFIG_DEBUG_LIST is not set
 # CONFIG_DEBUG_SG is not set
 # CONFIG_DEBUG_NOTIFIERS is not set
-# CONFIG_BOOT_PRINTK_DELAY is not set
 # CONFIG_RCU_TORTURE_TEST is not set
 # CONFIG_RCU_CPU_STALL_DETECTOR is not set
 # CONFIG_BACKTRACE_SELF_TEST is not set
@@ -873,16 +1085,15 @@ CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
 CONFIG_HAVE_DYNAMIC_FTRACE=y
 CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
 CONFIG_TRACING_SUPPORT=y
-
-#
-# Tracers
-#
+CONFIG_FTRACE=y
 # CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
 # CONFIG_SCHED_TRACER is not set
-# CONFIG_CONTEXT_SWITCH_TRACER is not set
-# CONFIG_EVENT_TRACER is not set
+# CONFIG_ENABLE_DEFAULT_TRACERS is not set
 # CONFIG_BOOT_TRACER is not set
-# CONFIG_TRACE_BRANCH_PROFILING is not set
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
 # CONFIG_STACK_TRACER is not set
 # CONFIG_KMEMTRACE is not set
 # CONFIG_WORKQUEUE_TRACER is not set
@@ -891,6 +1102,9 @@ CONFIG_TRACING_SUPPORT=y
 # CONFIG_SAMPLES is not set
 CONFIG_HAVE_ARCH_KGDB=y
 # CONFIG_KGDB is not set
+# CONFIG_KMEMCHECK is not set
+# CONFIG_PPC_DISABLE_WERROR is not set
+CONFIG_PPC_WERROR=y
 CONFIG_PRINT_STACK_DEPTH=64
 # CONFIG_DEBUG_STACKOVERFLOW is not set
 # CONFIG_DEBUG_STACK_USAGE is not set
diff --git a/arch/powerpc/configs/44x/canyonlands_defconfig b/arch/powerpc/configs/44x/canyonlands_defconfig
index 5e85412eb9fa..b312b166be66 100644
--- a/arch/powerpc/configs/44x/canyonlands_defconfig
+++ b/arch/powerpc/configs/44x/canyonlands_defconfig
@@ -1,14 +1,14 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.29-rc3
-# Mon Feb  2 13:13:04 2009
+# Linux kernel version: 2.6.31-rc4
+# Wed Jul 29 17:27:20 2009
 #
 # CONFIG_PPC64 is not set
 
 #
 # Processor support
 #
-# CONFIG_6xx is not set
+# CONFIG_PPC_BOOK3S_32 is not set
 # CONFIG_PPC_85xx is not set
 # CONFIG_PPC_8xx is not set
 # CONFIG_40x is not set
@@ -31,15 +31,16 @@ CONFIG_GENERIC_TIME=y
 CONFIG_GENERIC_TIME_VSYSCALL=y
 CONFIG_GENERIC_CLOCKEVENTS=y
 CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
 # CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
 CONFIG_IRQ_PER_CPU=y
 CONFIG_STACKTRACE_SUPPORT=y
 CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 CONFIG_LOCKDEP_SUPPORT=y
 CONFIG_RWSEM_XCHGADD_ALGORITHM=y
 CONFIG_ARCH_HAS_ILOG2_U32=y
 CONFIG_GENERIC_HWEIGHT=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
 CONFIG_GENERIC_FIND_NEXT_BIT=y
 # CONFIG_ARCH_NO_VIRT_TO_BUS is not set
 CONFIG_PPC=y
@@ -53,11 +54,14 @@ CONFIG_PPC_UDBG_16550=y
 # CONFIG_GENERIC_TBSYNC is not set
 CONFIG_AUDIT_ARCH=y
 CONFIG_GENERIC_BUG=y
+CONFIG_DTC=y
 # CONFIG_DEFAULT_UIMAGE is not set
 CONFIG_PPC_DCR_NATIVE=y
 # CONFIG_PPC_DCR_MMIO is not set
 CONFIG_PPC_DCR=y
+CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
 
 #
 # General setup
@@ -71,6 +75,7 @@ CONFIG_SWAP=y
 CONFIG_SYSVIPC=y
 CONFIG_SYSVIPC_SYSCTL=y
 CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
 # CONFIG_AUDIT is not set
@@ -93,8 +98,12 @@ CONFIG_SYSFS_DEPRECATED_V2=y
 # CONFIG_NAMESPACES is not set
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
 CONFIG_EMBEDDED=y
 CONFIG_SYSCTL_SYSCALL=y
 CONFIG_KALLSYMS=y
@@ -104,23 +113,30 @@ CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
 CONFIG_ELF_CORE=y
-CONFIG_COMPAT_BRK=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
-CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
 CONFIG_SIGNALFD=y
 CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
 CONFIG_AIO=y
+CONFIG_HAVE_PERF_COUNTERS=y
+
+#
+# Performance Counters
+#
+# CONFIG_PERF_COUNTERS is not set
 CONFIG_VM_EVENT_COUNTERS=y
 CONFIG_PCI_QUIRKS=y
 CONFIG_SLUB_DEBUG=y
+# CONFIG_STRIP_ASM_SYMS is not set
+CONFIG_COMPAT_BRK=y
 # CONFIG_SLAB is not set
 CONFIG_SLUB=y
 # CONFIG_SLOB is not set
 # CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
 CONFIG_HAVE_OPROFILE=y
 # CONFIG_KPROBES is not set
 CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
@@ -128,6 +144,12 @@ CONFIG_HAVE_IOREMAP_PROT=y
 CONFIG_HAVE_KPROBES=y
 CONFIG_HAVE_KRETPROBES=y
 CONFIG_HAVE_ARCH_TRACEHOOK=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+# CONFIG_SLOW_WORK is not set
 # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
 CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
@@ -139,8 +161,7 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_BLOCK=y
-CONFIG_LBD=y
-# CONFIG_BLK_DEV_IO_TRACE is not set
+CONFIG_LBDAF=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_BLK_DEV_INTEGRITY is not set
 
@@ -176,6 +197,7 @@ CONFIG_PPC4xx_PCI_EXPRESS=y
 # CONFIG_ARCHES is not set
 CONFIG_CANYONLANDS=y
 # CONFIG_GLACIER is not set
+# CONFIG_REDWOOD is not set
 # CONFIG_YOSEMITE is not set
 # CONFIG_XILINX_VIRTEX440_GENERIC_BOARD is not set
 CONFIG_PPC44x_SIMPLE=y
@@ -218,6 +240,7 @@ CONFIG_BINFMT_ELF=y
 # CONFIG_BINFMT_MISC is not set
 # CONFIG_MATH_EMULATION is not set
 # CONFIG_IOMMU_HELPER is not set
+# CONFIG_SWIOTLB is not set
 CONFIG_PPC_NEED_DMA_SYNC_OPS=y
 CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
 CONFIG_ARCH_HAS_WALK_MEMORY=y
@@ -237,10 +260,14 @@ CONFIG_PHYS_ADDR_T_64BIT=y
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_BOUNCE=y
 CONFIG_VIRT_TO_BUS=y
-CONFIG_UNEVICTABLE_LRU=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_STDBINUTILS=y
 CONFIG_PPC_4K_PAGES=y
 # CONFIG_PPC_16K_PAGES is not set
 # CONFIG_PPC_64K_PAGES is not set
+# CONFIG_PPC_256K_PAGES is not set
 CONFIG_FORCE_MAX_ZONEORDER=11
 CONFIG_PROC_DEVICETREE=y
 CONFIG_CMDLINE_BOOL=y
@@ -265,6 +292,7 @@ CONFIG_ARCH_SUPPORTS_MSI=y
 # CONFIG_PCI_LEGACY is not set
 # CONFIG_PCI_DEBUG is not set
 # CONFIG_PCI_STUB is not set
+# CONFIG_PCI_IOV is not set
 # CONFIG_PCCARD is not set
 # CONFIG_HOTPLUG_PCI is not set
 # CONFIG_HAS_RAPIDIO is not set
@@ -282,14 +310,12 @@ CONFIG_PAGE_OFFSET=0xc0000000
 CONFIG_KERNEL_START=0xc0000000
 CONFIG_PHYSICAL_START=0x00000000
 CONFIG_TASK_SIZE=0xc0000000
-CONFIG_CONSISTENT_START=0xff100000
 CONFIG_CONSISTENT_SIZE=0x00200000
 CONFIG_NET=y
 
 #
 # Networking options
 #
-CONFIG_COMPAT_NET_DEV_OPS=y
 CONFIG_PACKET=y
 # CONFIG_PACKET_MMAP is not set
 CONFIG_UNIX=y
@@ -339,6 +365,8 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_LAPB is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
 # CONFIG_NET_SCHED is not set
 # CONFIG_DCB is not set
 
@@ -351,7 +379,6 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
 # CONFIG_AF_RXRPC is not set
-# CONFIG_PHONET is not set
 # CONFIG_WIRELESS is not set
 # CONFIG_WIMAX is not set
 # CONFIG_RFKILL is not set
@@ -375,7 +402,101 @@ CONFIG_EXTRA_FIRMWARE=""
 # CONFIG_SYS_HYPERVISOR is not set
 CONFIG_CONNECTOR=y
 CONFIG_PROC_EVENTS=y
-# CONFIG_MTD is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_OF_PARTS=y
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PHYSMAP is not set
+CONFIG_MTD_PHYSMAP_OF=y
+# CONFIG_MTD_INTEL_VR_NOR is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+CONFIG_MTD_NAND_ECC_SMC=y
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+CONFIG_MTD_NAND_NDFC=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_CAFE is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_NAND_FSL_ELBC is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
 CONFIG_OF_DEVICE=y
 CONFIG_OF_I2C=y
 # CONFIG_PARPORT is not set
@@ -418,7 +539,11 @@ CONFIG_HAVE_IDE=y
 #
 
 #
-# Enable only one of the two stacks, unless you know what you are doing
+# You can enable one or both FireWire driver stacks.
+#
+
+#
+# See the help texts for more information.
 #
 # CONFIG_FIREWIRE is not set
 # CONFIG_IEEE1394 is not set
@@ -439,6 +564,8 @@ CONFIG_NET_ETHERNET=y
 # CONFIG_SUNGEM is not set
 # CONFIG_CASSINI is not set
 # CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_ETHOC is not set
+# CONFIG_DNET is not set
 # CONFIG_NET_TULIP is not set
 # CONFIG_HP100 is not set
 CONFIG_IBM_NEW_EMAC=y
@@ -457,6 +584,7 @@ CONFIG_IBM_NEW_EMAC_EMAC4=y
 # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
 # CONFIG_NET_PCI is not set
 # CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
 # CONFIG_ATL2 is not set
 # CONFIG_NETDEV_1000 is not set
 # CONFIG_NETDEV_10000 is not set
@@ -467,7 +595,6 @@ CONFIG_IBM_NEW_EMAC_EMAC4=y
 #
 # CONFIG_WLAN_PRE80211 is not set
 # CONFIG_WLAN_80211 is not set
-# CONFIG_IWLWIFI_LEDS is not set
 
 #
 # Enable WiMAX (Networking options) to see the WiMAX drivers
@@ -542,7 +669,6 @@ CONFIG_LEGACY_PTY_COUNT=256
 # CONFIG_IPMI_HANDLER is not set
 # CONFIG_HW_RANDOM is not set
 # CONFIG_NVRAM is not set
-# CONFIG_GEN_RTC is not set
 # CONFIG_R3964 is not set
 # CONFIG_APPLICOM is not set
 # CONFIG_RAW_DRIVER is not set
@@ -608,14 +734,17 @@ CONFIG_I2C_IBM_IIC=y
 # CONFIG_SENSORS_PCF8574 is not set
 # CONFIG_PCF8575 is not set
 # CONFIG_SENSORS_PCA9539 is not set
-# CONFIG_SENSORS_PCF8591 is not set
-# CONFIG_SENSORS_MAX6875 is not set
 # CONFIG_SENSORS_TSL2550 is not set
 # CONFIG_I2C_DEBUG_CORE is not set
 # CONFIG_I2C_DEBUG_ALGO is not set
 # CONFIG_I2C_DEBUG_BUS is not set
 # CONFIG_I2C_DEBUG_CHIP is not set
 # CONFIG_SPI is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
 CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
 # CONFIG_GPIOLIB is not set
 # CONFIG_W1 is not set
@@ -640,6 +769,7 @@ CONFIG_SENSORS_AD7414=y
 # CONFIG_SENSORS_F71805F is not set
 # CONFIG_SENSORS_F71882FG is not set
 # CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_G760A is not set
 # CONFIG_SENSORS_GL518SM is not set
 # CONFIG_SENSORS_GL520SM is not set
 # CONFIG_SENSORS_IT87 is not set
@@ -654,11 +784,14 @@ CONFIG_SENSORS_AD7414=y
 # CONFIG_SENSORS_LM90 is not set
 # CONFIG_SENSORS_LM92 is not set
 # CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_LTC4215 is not set
 # CONFIG_SENSORS_LTC4245 is not set
+# CONFIG_SENSORS_LM95241 is not set
 # CONFIG_SENSORS_MAX1619 is not set
 # CONFIG_SENSORS_MAX6650 is not set
 # CONFIG_SENSORS_PC87360 is not set
 # CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_PCF8591 is not set
 # CONFIG_SENSORS_SIS5595 is not set
 # CONFIG_SENSORS_DME1737 is not set
 # CONFIG_SENSORS_SMSC47M1 is not set
@@ -666,6 +799,7 @@ CONFIG_SENSORS_AD7414=y
 # CONFIG_SENSORS_SMSC47B397 is not set
 # CONFIG_SENSORS_ADS7828 is not set
 # CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_TMP401 is not set
 # CONFIG_SENSORS_VIA686A is not set
 # CONFIG_SENSORS_VT1211 is not set
 # CONFIG_SENSORS_VT8231 is not set
@@ -700,24 +834,9 @@ CONFIG_SSB_POSSIBLE=y
 # CONFIG_MFD_WM8400 is not set
 # CONFIG_MFD_WM8350_I2C is not set
 # CONFIG_MFD_PCF50633 is not set
+# CONFIG_AB3100_CORE is not set
 # CONFIG_REGULATOR is not set
-
-#
-# Multimedia devices
-#
-
-#
-# Multimedia core support
-#
-# CONFIG_VIDEO_DEV is not set
-# CONFIG_DVB_CORE is not set
-# CONFIG_VIDEO_MEDIA is not set
-
-#
-# Multimedia drivers
-#
-# CONFIG_DAB is not set
-# CONFIG_USB_DABUSB is not set
+# CONFIG_MEDIA_SUPPORT is not set
 
 #
 # Graphics support
@@ -759,6 +878,7 @@ CONFIG_USB_MON=y
 # USB Host Controller Drivers
 #
 # CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_XHCI_HCD is not set
 CONFIG_USB_EHCI_HCD=m
 # CONFIG_USB_EHCI_ROOT_HUB_TT is not set
 # CONFIG_USB_EHCI_TT_NEWSCHED is not set
@@ -767,9 +887,9 @@ CONFIG_USB_EHCI_HCD_PPC_OF=y
 # CONFIG_USB_ISP116X_HCD is not set
 # CONFIG_USB_ISP1760_HCD is not set
 CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_OHCI_HCD_PPC_OF=y
 CONFIG_USB_OHCI_HCD_PPC_OF_BE=y
 CONFIG_USB_OHCI_HCD_PPC_OF_LE=y
+CONFIG_USB_OHCI_HCD_PPC_OF=y
 CONFIG_USB_OHCI_HCD_PCI=y
 CONFIG_USB_OHCI_BIG_ENDIAN_DESC=y
 CONFIG_USB_OHCI_BIG_ENDIAN_MMIO=y
@@ -789,11 +909,11 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y
 # CONFIG_USB_TMC is not set
 
 #
-# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
 #
 
 #
-# see USB_STORAGE Help for more information
+# also be needed; see USB_STORAGE Help for more info
 #
 CONFIG_USB_LIBUSUAL=y
 
@@ -821,7 +941,6 @@ CONFIG_USB_LIBUSUAL=y
 # CONFIG_USB_LED is not set
 # CONFIG_USB_CYPRESS_CY7C63 is not set
 # CONFIG_USB_CYTHERM is not set
-# CONFIG_USB_PHIDGET is not set
 # CONFIG_USB_IDMOUSE is not set
 # CONFIG_USB_FTDI_ELAN is not set
 # CONFIG_USB_APPLEDISPLAY is not set
@@ -837,6 +956,7 @@ CONFIG_USB_LIBUSUAL=y
 #
 # OTG and related infrastructure
 #
+# CONFIG_NOP_USB_XCEIV is not set
 # CONFIG_UWB is not set
 # CONFIG_MMC is not set
 # CONFIG_MEMSTICK is not set
@@ -844,9 +964,70 @@ CONFIG_USB_LIBUSUAL=y
 # CONFIG_ACCESSIBILITY is not set
 # CONFIG_INFINIBAND is not set
 # CONFIG_EDAC is not set
-# CONFIG_RTC_CLASS is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+CONFIG_RTC_DRV_M41T80=y
+# CONFIG_RTC_DRV_M41T80_WDT is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+
+#
+# SPI RTC drivers
+#
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_RTC_DRV_GENERIC is not set
 # CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
 # CONFIG_UIO is not set
+
+#
+# TI VLYNQ
+#
 # CONFIG_STAGING is not set
 
 #
@@ -860,11 +1041,12 @@ CONFIG_EXT2_FS=y
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
-CONFIG_FILE_LOCKING=y
 # CONFIG_XFS_FS is not set
 # CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
 # CONFIG_BTRFS_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
 CONFIG_DNOTIFY=y
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
@@ -874,6 +1056,11 @@ CONFIG_INOTIFY_USER=y
 # CONFIG_FUSE_FS is not set
 
 #
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
 # CD-ROM/DVD Filesystems
 #
 # CONFIG_ISO9660_FS is not set
@@ -906,6 +1093,7 @@ CONFIG_MISC_FILESYSTEMS=y
 # CONFIG_BEFS_FS is not set
 # CONFIG_BFS_FS is not set
 # CONFIG_EFS_FS is not set
+# CONFIG_JFFS2_FS is not set
 CONFIG_CRAMFS=y
 # CONFIG_SQUASHFS is not set
 # CONFIG_VXFS_FS is not set
@@ -916,6 +1104,7 @@ CONFIG_CRAMFS=y
 # CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
+# CONFIG_NILFS2_FS is not set
 CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
@@ -927,7 +1116,6 @@ CONFIG_LOCKD=y
 CONFIG_LOCKD_V4=y
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
-# CONFIG_SUNRPC_REGISTER_V4 is not set
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 # CONFIG_SMB_FS is not set
@@ -941,8 +1129,48 @@ CONFIG_SUNRPC=y
 #
 # CONFIG_PARTITION_ADVANCED is not set
 CONFIG_MSDOS_PARTITION=y
-# CONFIG_NLS is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
 # CONFIG_DLM is not set
+# CONFIG_BINARY_PRINTF is not set
 
 #
 # Library routines
@@ -957,11 +1185,13 @@ CONFIG_CRC32=y
 # CONFIG_CRC7 is not set
 # CONFIG_LIBCRC32C is not set
 CONFIG_ZLIB_INFLATE=y
-CONFIG_PLIST=y
+CONFIG_DECOMPRESS_GZIP=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
 CONFIG_HAS_DMA=y
 CONFIG_HAVE_LMB=y
+CONFIG_NLATTR=y
+CONFIG_GENERIC_ATOMIC64=y
 
 #
 # Kernel hacking
@@ -979,6 +1209,9 @@ CONFIG_DEBUG_KERNEL=y
 CONFIG_DETECT_SOFTLOCKUP=y
 # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
 CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
 CONFIG_SCHED_DEBUG=y
 # CONFIG_SCHEDSTATS is not set
 # CONFIG_TIMER_STATS is not set
@@ -989,6 +1222,9 @@ CONFIG_SCHED_DEBUG=y
 # CONFIG_RT_MUTEX_TESTER is not set
 # CONFIG_DEBUG_SPINLOCK is not set
 # CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
 # CONFIG_DEBUG_SPINLOCK_SLEEP is not set
 # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
 # CONFIG_DEBUG_KOBJECT is not set
@@ -1000,7 +1236,6 @@ CONFIG_SCHED_DEBUG=y
 # CONFIG_DEBUG_LIST is not set
 # CONFIG_DEBUG_SG is not set
 # CONFIG_DEBUG_NOTIFIERS is not set
-# CONFIG_BOOT_PRINTK_DELAY is not set
 # CONFIG_RCU_TORTURE_TEST is not set
 # CONFIG_RCU_CPU_STALL_DETECTOR is not set
 # CONFIG_BACKTRACE_SELF_TEST is not set
@@ -1008,27 +1243,36 @@ CONFIG_SCHED_DEBUG=y
 # CONFIG_FAULT_INJECTION is not set
 # CONFIG_LATENCYTOP is not set
 CONFIG_SYSCTL_SYSCALL_CHECK=y
+# CONFIG_DEBUG_PAGEALLOC is not set
 CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
 CONFIG_HAVE_DYNAMIC_FTRACE=y
 CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-
-#
-# Tracers
-#
+CONFIG_TRACING_SUPPORT=y
+CONFIG_FTRACE=y
 # CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
 # CONFIG_SCHED_TRACER is not set
-# CONFIG_CONTEXT_SWITCH_TRACER is not set
+# CONFIG_ENABLE_DEFAULT_TRACERS is not set
 # CONFIG_BOOT_TRACER is not set
-# CONFIG_TRACE_BRANCH_PROFILING is not set
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
 # CONFIG_STACK_TRACER is not set
-# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
+# CONFIG_KMEMTRACE is not set
+# CONFIG_WORKQUEUE_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_DYNAMIC_DEBUG is not set
 # CONFIG_SAMPLES is not set
 CONFIG_HAVE_ARCH_KGDB=y
 # CONFIG_KGDB is not set
+# CONFIG_KMEMCHECK is not set
+# CONFIG_PPC_DISABLE_WERROR is not set
+CONFIG_PPC_WERROR=y
 CONFIG_PRINT_STACK_DEPTH=64
 # CONFIG_DEBUG_STACKOVERFLOW is not set
 # CONFIG_DEBUG_STACK_USAGE is not set
-# CONFIG_DEBUG_PAGEALLOC is not set
+# CONFIG_PPC_EMULATED_STATS is not set
 # CONFIG_CODE_PATCHING_SELFTEST is not set
 # CONFIG_FTR_FIXUP_SELFTEST is not set
 # CONFIG_MSI_BITMAP_SELFTEST is not set
diff --git a/arch/powerpc/include/asm/bitops.h b/arch/powerpc/include/asm/bitops.h
index 897eade3afbe..56f2f2ea5631 100644
--- a/arch/powerpc/include/asm/bitops.h
+++ b/arch/powerpc/include/asm/bitops.h
@@ -56,174 +56,102 @@
 #define BITOP_WORD(nr)          ((nr) / BITS_PER_LONG)
 #define BITOP_LE_SWIZZLE        ((BITS_PER_LONG-1) & ~0x7)
 
+/* Macro for generating the ***_bits() functions */
+#define DEFINE_BITOP(fn, op, prefix, postfix)   \
+static __inline__ void fn(unsigned long mask,   \
+                volatile unsigned long *_p)     \
+{                                               \
+        unsigned long old;                      \
+        unsigned long *p = (unsigned long *)_p; \
+        __asm__ __volatile__ (                  \
+        prefix                                  \
+"1:"    PPC_LLARX "%0,0,%3\n"                   \
+        stringify_in_c(op) "%0,%0,%2\n"         \
+        PPC405_ERR77(0,%3)                      \
+        PPC_STLCX "%0,0,%3\n"                   \
+        "bne- 1b\n"                             \
+        postfix                                 \
+        : "=&r" (old), "+m" (*p)                \
+        : "r" (mask), "r" (p)                   \
+        : "cc", "memory");                      \
+}
+
+DEFINE_BITOP(set_bits, or, "", "")
+DEFINE_BITOP(clear_bits, andc, "", "")
+DEFINE_BITOP(clear_bits_unlock, andc, LWSYNC_ON_SMP, "")
+DEFINE_BITOP(change_bits, xor, "", "")
+
 static __inline__ void set_bit(int nr, volatile unsigned long *addr)
 {
-        unsigned long old;
-        unsigned long mask = BITOP_MASK(nr);
-        unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
-
-        __asm__ __volatile__(
-"1:"    PPC_LLARX "%0,0,%3      # set_bit\n"
-        "or     %0,%0,%2\n"
-        PPC405_ERR77(0,%3)
-        PPC_STLCX "%0,0,%3\n"
-        "bne-   1b"
-        : "=&r" (old), "+m" (*p)
-        : "r" (mask), "r" (p)
-        : "cc" );
+        set_bits(BITOP_MASK(nr), addr + BITOP_WORD(nr));
 }
 
 static __inline__ void clear_bit(int nr, volatile unsigned long *addr)
 {
-        unsigned long old;
-        unsigned long mask = BITOP_MASK(nr);
-        unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
-
-        __asm__ __volatile__(
-"1:"    PPC_LLARX "%0,0,%3      # clear_bit\n"
-        "andc   %0,%0,%2\n"
-        PPC405_ERR77(0,%3)
-        PPC_STLCX "%0,0,%3\n"
-        "bne-   1b"
-        : "=&r" (old), "+m" (*p)
-        : "r" (mask), "r" (p)
-        : "cc" );
+        clear_bits(BITOP_MASK(nr), addr + BITOP_WORD(nr));
 }
 
 static __inline__ void clear_bit_unlock(int nr, volatile unsigned long *addr)
 {
-        unsigned long old;
-        unsigned long mask = BITOP_MASK(nr);
-        unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
-
-        __asm__ __volatile__(
-        LWSYNC_ON_SMP
-"1:"    PPC_LLARX "%0,0,%3      # clear_bit_unlock\n"
-        "andc   %0,%0,%2\n"
-        PPC405_ERR77(0,%3)
-        PPC_STLCX "%0,0,%3\n"
-        "bne-   1b"
-        : "=&r" (old), "+m" (*p)
-        : "r" (mask), "r" (p)
-        : "cc", "memory");
+        clear_bits_unlock(BITOP_MASK(nr), addr + BITOP_WORD(nr));
 }
 
 static __inline__ void change_bit(int nr, volatile unsigned long *addr)
 {
-        unsigned long old;
-        unsigned long mask = BITOP_MASK(nr);
-        unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
-
-        __asm__ __volatile__(
-"1:"    PPC_LLARX "%0,0,%3      # change_bit\n"
-        "xor    %0,%0,%2\n"
-        PPC405_ERR77(0,%3)
-        PPC_STLCX "%0,0,%3\n"
-        "bne-   1b"
-        : "=&r" (old), "+m" (*p)
-        : "r" (mask), "r" (p)
-        : "cc" );
+        change_bits(BITOP_MASK(nr), addr + BITOP_WORD(nr));
+}
+
+/* Like DEFINE_BITOP(), with changes to the arguments to 'op' and the output
+ * operands. */
+#define DEFINE_TESTOP(fn, op, prefix, postfix)  \
+static __inline__ unsigned long fn(             \
+                unsigned long mask,             \
+                volatile unsigned long *_p)     \
+{                                               \
+        unsigned long old, t;                   \
+        unsigned long *p = (unsigned long *)_p; \
+        __asm__ __volatile__ (                  \
+        prefix                                  \
+"1:"    PPC_LLARX "%0,0,%3\n"                   \
+        stringify_in_c(op) "%1,%0,%2\n"         \
+        PPC405_ERR77(0,%3)                      \
+        PPC_STLCX "%1,0,%3\n"                   \
+        "bne- 1b\n"                             \
+        postfix                                 \
+        : "=&r" (old), "=&r" (t)                \
+        : "r" (mask), "r" (p)                   \
+        : "cc", "memory");                      \
+        return (old & mask);                    \
 }
 
+DEFINE_TESTOP(test_and_set_bits, or, LWSYNC_ON_SMP, ISYNC_ON_SMP)
+DEFINE_TESTOP(test_and_set_bits_lock, or, "", ISYNC_ON_SMP)
+DEFINE_TESTOP(test_and_clear_bits, andc, LWSYNC_ON_SMP, ISYNC_ON_SMP)
+DEFINE_TESTOP(test_and_change_bits, xor, LWSYNC_ON_SMP, ISYNC_ON_SMP)
+
 static __inline__ int test_and_set_bit(unsigned long nr,
                                        volatile unsigned long *addr)
 {
-        unsigned long old, t;
-        unsigned long mask = BITOP_MASK(nr);
-        unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
-
-        __asm__ __volatile__(
-        LWSYNC_ON_SMP
-"1:"    PPC_LLARX "%0,0,%3              # test_and_set_bit\n"
-        "or     %1,%0,%2 \n"
-        PPC405_ERR77(0,%3)
-        PPC_STLCX "%1,0,%3 \n"
-        "bne-   1b"
-        ISYNC_ON_SMP
-        : "=&r" (old), "=&r" (t)
-        : "r" (mask), "r" (p)
-        : "cc", "memory");
-
-        return (old & mask) != 0;
+        return test_and_set_bits(BITOP_MASK(nr), addr + BITOP_WORD(nr)) != 0;
 }
 
 static __inline__ int test_and_set_bit_lock(unsigned long nr,
                                        volatile unsigned long *addr)
 {
-        unsigned long old, t;
-        unsigned long mask = BITOP_MASK(nr);
-        unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
-
-        __asm__ __volatile__(
-"1:"    PPC_LLARX "%0,0,%3              # test_and_set_bit_lock\n"
-        "or     %1,%0,%2 \n"
-        PPC405_ERR77(0,%3)
-        PPC_STLCX "%1,0,%3 \n"
-        "bne-   1b"
-        ISYNC_ON_SMP
-        : "=&r" (old), "=&r" (t)
-        : "r" (mask), "r" (p)
-        : "cc", "memory");
-
-        return (old & mask) != 0;
+        return test_and_set_bits_lock(BITOP_MASK(nr),
+                                addr + BITOP_WORD(nr)) != 0;
 }
 
 static __inline__ int test_and_clear_bit(unsigned long nr,
                                          volatile unsigned long *addr)
 {
-        unsigned long old, t;
-        unsigned long mask = BITOP_MASK(nr);
-        unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
-
-        __asm__ __volatile__(
-        LWSYNC_ON_SMP
-"1:"    PPC_LLARX "%0,0,%3              # test_and_clear_bit\n"
-        "andc   %1,%0,%2 \n"
-        PPC405_ERR77(0,%3)
-        PPC_STLCX "%1,0,%3 \n"
-        "bne-   1b"
-        ISYNC_ON_SMP
-        : "=&r" (old), "=&r" (t)
-        : "r" (mask), "r" (p)
-        : "cc", "memory");
-
-        return (old & mask) != 0;
+        return test_and_clear_bits(BITOP_MASK(nr), addr + BITOP_WORD(nr)) != 0;
 }
 
 static __inline__ int test_and_change_bit(unsigned long nr,
                                           volatile unsigned long *addr)
 {
-        unsigned long old, t;
-        unsigned long mask = BITOP_MASK(nr);
-        unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
-
-        __asm__ __volatile__(
-        LWSYNC_ON_SMP
-"1:"    PPC_LLARX "%0,0,%3              # test_and_change_bit\n"
-        "xor    %1,%0,%2 \n"
-        PPC405_ERR77(0,%3)
-        PPC_STLCX "%1,0,%3 \n"
-        "bne-   1b"
-        ISYNC_ON_SMP
-        : "=&r" (old), "=&r" (t)
-        : "r" (mask), "r" (p)
-        : "cc", "memory");
-
-        return (old & mask) != 0;
-}
-
-static __inline__ void set_bits(unsigned long mask, unsigned long *addr)
-{
-        unsigned long old;
-
-        __asm__ __volatile__(
-"1:"    PPC_LLARX "%0,0,%3         # set_bits\n"
-        "or     %0,%0,%2\n"
-        PPC_STLCX "%0,0,%3\n"
-        "bne-   1b"
-        : "=&r" (old), "+m" (*addr)
-        : "r" (mask), "r" (addr)
-        : "cc");
+        return test_and_change_bits(BITOP_MASK(nr), addr + BITOP_WORD(nr)) != 0;
 }
 
 #include <asm-generic/bitops/non-atomic.h>
diff --git a/arch/powerpc/include/asm/cell-regs.h b/arch/powerpc/include/asm/cell-regs.h
index fd6fd00434ef..fdf64fd25950 100644
--- a/arch/powerpc/include/asm/cell-regs.h
+++ b/arch/powerpc/include/asm/cell-regs.h
@@ -303,6 +303,17 @@ struct cbe_mic_tm_regs {
 extern struct cbe_mic_tm_regs __iomem *cbe_get_mic_tm_regs(struct device_node *np);
 extern struct cbe_mic_tm_regs __iomem *cbe_get_cpu_mic_tm_regs(int cpu);
 
+
+/* Cell page table entries */
+#define CBE_IOPTE_PP_W          0x8000000000000000ul /* protection: write */
+#define CBE_IOPTE_PP_R          0x4000000000000000ul /* protection: read */
+#define CBE_IOPTE_M             0x2000000000000000ul /* coherency required */
+#define CBE_IOPTE_SO_R          0x1000000000000000ul /* ordering: writes */
+#define CBE_IOPTE_SO_RW         0x1800000000000000ul /* ordering: r & w */
+#define CBE_IOPTE_RPN_Mask      0x07fffffffffff000ul /* RPN */
+#define CBE_IOPTE_H             0x0000000000000800ul /* cache hint */
+#define CBE_IOPTE_IOID_Mask     0x00000000000007fful /* ioid */
+
 /* some utility functions to deal with SMT */
 extern u32 cbe_get_hw_thread_id(int cpu);
 extern u32 cbe_cpu_to_node(int cpu);
diff --git a/arch/powerpc/include/asm/cputhreads.h b/arch/powerpc/include/asm/cputhreads.h
index fb11b0c459b8..a8e18447c62b 100644
--- a/arch/powerpc/include/asm/cputhreads.h
+++ b/arch/powerpc/include/asm/cputhreads.h
@@ -5,6 +5,15 @@
 
 /*
  * Mapping of threads to cores
+ *
+ * Note: This implementation is limited to a power of 2 number of
+ * threads per core and the same number for each core in the system
+ * (though it would work if some processors had less threads as long
+ * as the CPU numbers are still allocated, just not brought offline).
+ *
+ * However, the API allows for a different implementation in the future
+ * if needed, as long as you only use the functions and not the variables
+ * directly.
  */
 
 #ifdef CONFIG_SMP
@@ -67,5 +76,12 @@ static inline int cpu_first_thread_in_core(int cpu)
         return cpu & ~(threads_per_core - 1);
 }
 
+static inline int cpu_last_thread_in_core(int cpu)
+{
+        return cpu | (threads_per_core - 1);
+}
+
+
+
 #endif /* _ASM_POWERPC_CPUTHREADS_H */
 
diff --git a/arch/powerpc/include/asm/exception-64e.h b/arch/powerpc/include/asm/exception-64e.h
new file mode 100644
index 000000000000..94cb3d79d125
--- /dev/null
+++ b/arch/powerpc/include/asm/exception-64e.h
@@ -0,0 +1,201 @@
+/*
+ *  Definitions for use by exception code on Book3-E
+ *
+ *  Copyright (C) 2008 Ben. Herrenschmidt (benh@kernel.crashing.org), IBM Corp.
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  as published by the Free Software Foundation; either version
+ *  2 of the License, or (at your option) any later version.
+ */
+#ifndef _ASM_POWERPC_EXCEPTION_64E_H
+#define _ASM_POWERPC_EXCEPTION_64E_H
+
+/*
+ * SPRGs usage an other considerations...
+ *
+ * Since TLB miss and other standard exceptions can be interrupted by
+ * critical exceptions which can themselves be interrupted by machine
+ * checks, and since the two later can themselves cause a TLB miss when
+ * hitting the linear mapping for the kernel stacks, we need to be a bit
+ * creative on how we use SPRGs.
+ *
+ * The base idea is that we have one SRPG reserved for critical and one
+ * for machine check interrupts. Those are used to save a GPR that can
+ * then be used to get the PACA, and store as much context as we need
+ * to save in there. That includes saving the SPRGs used by the TLB miss
+ * handler for linear mapping misses and the associated SRR0/1 due to
+ * the above re-entrancy issue.
+ *
+ * So here's the current usage pattern. It's done regardless of which
+ * SPRGs are user-readable though, thus we might have to change some of
+ * this later. In order to do that more easily, we use special constants
+ * for naming them
+ *
+ * WARNING: Some of these SPRGs are user readable. We need to do something
+ * about it as some point by making sure they can't be used to leak kernel
+ * critical data
+ */
+
+
+/* We are out of SPRGs so we save some things in the PACA. The normal
+ * exception frame is smaller than the CRIT or MC one though
+ */
+#define EX_R1           (0 * 8)
+#define EX_CR           (1 * 8)
+#define EX_R10          (2 * 8)
+#define EX_R11          (3 * 8)
+#define EX_R14          (4 * 8)
+#define EX_R15          (5 * 8)
+
+/* The TLB miss exception uses different slots */
+
+#define EX_TLB_R10      ( 0 * 8)
+#define EX_TLB_R11      ( 1 * 8)
+#define EX_TLB_R12      ( 2 * 8)
+#define EX_TLB_R13      ( 3 * 8)
+#define EX_TLB_R14      ( 4 * 8)
+#define EX_TLB_R15      ( 5 * 8)
+#define EX_TLB_R16      ( 6 * 8)
+#define EX_TLB_CR       ( 7 * 8)
+#define EX_TLB_DEAR     ( 8 * 8) /* Level 0 and 2 only */
+#define EX_TLB_ESR      ( 9 * 8) /* Level 0 and 2 only */
+#define EX_TLB_SRR0     (10 * 8)
+#define EX_TLB_SRR1     (11 * 8)
+#define EX_TLB_MMUCR0   (12 * 8) /* Level 0 */
+#define EX_TLB_MAS1     (12 * 8) /* Level 0 */
+#define EX_TLB_MAS2     (13 * 8) /* Level 0 */
+#ifdef CONFIG_BOOK3E_MMU_TLB_STATS
+#define EX_TLB_R8       (14 * 8)
+#define EX_TLB_R9       (15 * 8)
+#define EX_TLB_LR       (16 * 8)
+#define EX_TLB_SIZE     (17 * 8)
+#else
+#define EX_TLB_SIZE     (14 * 8)
+#endif
+
+#define START_EXCEPTION(label)                                          \
+        .globl exc_##label##_book3e;                                    \
+exc_##label##_book3e:
+
+/* TLB miss exception prolog
+ *
+ * This prolog handles re-entrancy (up to 3 levels supported in the PACA
+ * though we currently don't test for overflow). It provides you with a
+ * re-entrancy safe working space of r10...r16 and CR with r12 being used
+ * as the exception area pointer in the PACA for that level of re-entrancy
+ * and r13 containing the PACA pointer.
+ *
+ * SRR0 and SRR1 are saved, but DEAR and ESR are not, since they don't apply
+ * as-is for instruction exceptions. It's up to the actual exception code
+ * to save them as well if required.
+ */
+#define TLB_MISS_PROLOG                                                     \
+        mtspr   SPRN_SPRG_TLB_SCRATCH,r12;                                  \
+        mfspr   r12,SPRN_SPRG_TLB_EXFRAME;                                  \
+        std     r10,EX_TLB_R10(r12);                                        \
+        mfcr    r10;                                                        \
+        std     r11,EX_TLB_R11(r12);                                        \
+        mfspr   r11,SPRN_SPRG_TLB_SCRATCH;                                  \
+        std     r13,EX_TLB_R13(r12);                                        \
+        mfspr   r13,SPRN_SPRG_PACA;                                         \
+        std     r14,EX_TLB_R14(r12);                                        \
+        addi    r14,r12,EX_TLB_SIZE;                                        \
+        std     r15,EX_TLB_R15(r12);                                        \
+        mfspr   r15,SPRN_SRR1;                                              \
+        std     r16,EX_TLB_R16(r12);                                        \
+        mfspr   r16,SPRN_SRR0;                                              \
+        std     r10,EX_TLB_CR(r12);                                         \
+        std     r11,EX_TLB_R12(r12);                                        \
+        mtspr   SPRN_SPRG_TLB_EXFRAME,r14;                                  \
+        std     r15,EX_TLB_SRR1(r12);                                       \
+        std     r16,EX_TLB_SRR0(r12);                                       \
+        TLB_MISS_PROLOG_STATS
+
+/* And these are the matching epilogs that restores things
+ *
+ * There are 3 epilogs:
+ *
+ * - SUCCESS       : Unwinds one level
+ * - ERROR         : restore from level 0 and reset
+ * - ERROR_SPECIAL : restore from current level and reset
+ *
+ * Normal errors use ERROR, that is, they restore the initial fault context
+ * and trigger a fault. However, there is a special case for linear mapping
+ * errors. Those should basically never happen, but if they do happen, we
+ * want the error to point out the context that did that linear mapping
+ * fault, not the initial level 0 (basically, we got a bogus PGF or something
+ * like that). For userland errors on the linear mapping, there is no
+ * difference since those are always level 0 anyway
+ */
+
+#define TLB_MISS_RESTORE(freg)                                              \
+        ld      r14,EX_TLB_CR(r12);                                         \
+        ld      r10,EX_TLB_R10(r12);                                        \
+        ld      r15,EX_TLB_SRR0(r12);                                       \
+        ld      r16,EX_TLB_SRR1(r12);                                       \
+        mtspr   SPRN_SPRG_TLB_EXFRAME,freg;                                 \
+        ld      r11,EX_TLB_R11(r12);                                        \
+        mtcr    r14;                                                        \
+        ld      r13,EX_TLB_R13(r12);                                        \
+        ld      r14,EX_TLB_R14(r12);                                        \
+        mtspr   SPRN_SRR0,r15;                                              \
+        ld      r15,EX_TLB_R15(r12);                                        \
+        mtspr   SPRN_SRR1,r16;                                              \
+        TLB_MISS_RESTORE_STATS                                              \
+        ld      r16,EX_TLB_R16(r12);                                        \
+        ld      r12,EX_TLB_R12(r12);                                        \
+
+#define TLB_MISS_EPILOG_SUCCESS                                             \
+        TLB_MISS_RESTORE(r12)
+
+#define TLB_MISS_EPILOG_ERROR                                               \
+        addi    r12,r13,PACA_EXTLB;                                         \
+        TLB_MISS_RESTORE(r12)
+
+#define TLB_MISS_EPILOG_ERROR_SPECIAL                                       \
+        addi    r11,r13,PACA_EXTLB;                                         \
+        TLB_MISS_RESTORE(r11)
+
+#ifdef CONFIG_BOOK3E_MMU_TLB_STATS
+#define TLB_MISS_PROLOG_STATS                                               \
+        mflr    r10;                                                        \
+        std     r8,EX_TLB_R8(r12);                                          \
+        std     r9,EX_TLB_R9(r12);                                          \
+        std     r10,EX_TLB_LR(r12);
+#define TLB_MISS_RESTORE_STATS                                              \
+        ld      r16,EX_TLB_LR(r12);                                         \
+        ld      r9,EX_TLB_R9(r12);                                          \
+        ld      r8,EX_TLB_R8(r12);                                          \
+        mtlr    r16;
+#define TLB_MISS_STATS_D(name)                                              \
+        addi    r9,r13,MMSTAT_DSTATS+name;                                  \
+        bl      .tlb_stat_inc;
+#define TLB_MISS_STATS_I(name)                                              \
+        addi    r9,r13,MMSTAT_ISTATS+name;                                  \
+        bl      .tlb_stat_inc;
+#define TLB_MISS_STATS_X(name)                                              \
+        ld      r8,PACA_EXTLB+EX_TLB_ESR(r13);                              \
+        cmpdi   cr2,r8,-1;                                                  \
+        beq     cr2,61f;                                                    \
+        addi    r9,r13,MMSTAT_DSTATS+name;                                  \
+        b       62f;                                                        \
+61:     addi    r9,r13,MMSTAT_ISTATS+name;                                  \
+62:     bl      .tlb_stat_inc;
+#define TLB_MISS_STATS_SAVE_INFO                                            \
+        std     r14,EX_TLB_ESR(r12);    /* save ESR */                      \
+
+
+#else
+#define TLB_MISS_PROLOG_STATS
+#define TLB_MISS_RESTORE_STATS
+#define TLB_MISS_STATS_D(name)
+#define TLB_MISS_STATS_I(name)
+#define TLB_MISS_STATS_X(name)
+#define TLB_MISS_STATS_Y(name)
+#define TLB_MISS_STATS_SAVE_INFO
+#endif
+
+
+#endif /* _ASM_POWERPC_EXCEPTION_64E_H */
+
diff --git a/arch/powerpc/include/asm/exception.h b/arch/powerpc/include/asm/exception-64s.h
index d3d4534e3c74..a98653b26231 100644
--- a/arch/powerpc/include/asm/exception.h
+++ b/arch/powerpc/include/asm/exception-64s.h
@@ -57,17 +57,16 @@
         addi    reg,reg,(label)-_stext; /* virt addr of handler ... */
 
 #define EXCEPTION_PROLOG_1(area)                                \
-        mfspr   r13,SPRN_SPRG3;         /* get paca address into r13 */ \
+        mfspr   r13,SPRN_SPRG_PACA;     /* get paca address into r13 */ \
         std     r9,area+EX_R9(r13);     /* save r9 - r12 */             \
         std     r10,area+EX_R10(r13);                                   \
         std     r11,area+EX_R11(r13);                                   \
         std     r12,area+EX_R12(r13);                                   \
-        mfspr   r9,SPRN_SPRG1;                                          \
+        mfspr   r9,SPRN_SPRG_SCRATCH0;                                  \
         std     r9,area+EX_R13(r13);                                    \
         mfcr    r9
 
-#define EXCEPTION_PROLOG_PSERIES(area, label)                           \
-        EXCEPTION_PROLOG_1(area);                                       \
+#define EXCEPTION_PROLOG_PSERIES_1(label)                               \
         ld      r12,PACAKBASE(r13);     /* get high part of &label */   \
         ld      r10,PACAKMSR(r13);      /* get MSR value for kernel */  \
         mfspr   r11,SPRN_SRR0;          /* save SRR0 */                 \
@@ -78,6 +77,10 @@
         rfid;                                                           \
         b       .       /* prevent speculative execution */
 
+#define EXCEPTION_PROLOG_PSERIES(area, label)                           \
+        EXCEPTION_PROLOG_1(area);                                       \
+        EXCEPTION_PROLOG_PSERIES_1(label);
+
 /*
  * The common exception prolog is used for all except a few exceptions
  * such as a segment miss on a kernel address.  We have to be prepared
@@ -144,7 +147,7 @@
         .globl label##_pSeries;                         \
 label##_pSeries:                                        \
         HMT_MEDIUM;                                     \
-        mtspr   SPRN_SPRG1,r13;         /* save r13 */  \
+        mtspr   SPRN_SPRG_SCRATCH0,r13;         /* save r13 */  \
         EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common)
 
 #define HSTD_EXCEPTION_PSERIES(n, label)                \
@@ -152,13 +155,13 @@ label##_pSeries:					\
         .globl label##_pSeries;                         \
 label##_pSeries:                                        \
         HMT_MEDIUM;                                     \
-        mtspr   SPRN_SPRG1,r20;         /* save r20 */  \
+        mtspr   SPRN_SPRG_SCRATCH0,r20; /* save r20 */  \
         mfspr   r20,SPRN_HSRR0;         /* copy HSRR0 to SRR0 */ \
         mtspr   SPRN_SRR0,r20;                          \
         mfspr   r20,SPRN_HSRR1;         /* copy HSRR0 to SRR0 */ \
         mtspr   SPRN_SRR1,r20;                          \
-        mfspr   r20,SPRN_SPRG1;         /* restore r20 */ \
-        mtspr   SPRN_SPRG1,r13;         /* save r13 */  \
+        mfspr   r20,SPRN_SPRG_SCRATCH0; /* restore r20 */ \
+        mtspr   SPRN_SPRG_SCRATCH0,r13;         /* save r13 */  \
         EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common)
 
 
@@ -167,15 +170,15 @@ label##_pSeries:					\
         .globl label##_pSeries;                                         \
 label##_pSeries:                                                        \
         HMT_MEDIUM;                                                     \
-        mtspr   SPRN_SPRG1,r13;         /* save r13 */                  \
-        mfspr   r13,SPRN_SPRG3;         /* get paca address into r13 */ \
+        mtspr   SPRN_SPRG_SCRATCH0,r13; /* save r13 */                  \
+        mfspr   r13,SPRN_SPRG_PACA;     /* get paca address into r13 */ \
         std     r9,PACA_EXGEN+EX_R9(r13);       /* save r9, r10 */      \
         std     r10,PACA_EXGEN+EX_R10(r13);                             \
         lbz     r10,PACASOFTIRQEN(r13);                                 \
         mfcr    r9;                                                     \
         cmpwi   r10,0;                                                  \
         beq     masked_interrupt;                                       \
-        mfspr   r10,SPRN_SPRG1;                                         \
+        mfspr   r10,SPRN_SPRG_SCRATCH0;                                 \
         std     r10,PACA_EXGEN+EX_R13(r13);                             \
         std     r11,PACA_EXGEN+EX_R11(r13);                             \
         std     r12,PACA_EXGEN+EX_R12(r13);                             \
diff --git a/arch/powerpc/include/asm/hardirq.h b/arch/powerpc/include/asm/hardirq.h
index 288e14d53b7f..fb3c05a0cbbf 100644
--- a/arch/powerpc/include/asm/hardirq.h
+++ b/arch/powerpc/include/asm/hardirq.h
@@ -1,29 +1 @@
-#ifndef _ASM_POWERPC_HARDIRQ_H
-#define _ASM_POWERPC_HARDIRQ_H
-#ifdef __KERNEL__
-
-#include <asm/irq.h>
-#include <asm/bug.h>
-
-/* The __last_jiffy_stamp field is needed to ensure that no decrementer
- * interrupt is lost on SMP machines. Since on most CPUs it is in the same
- * cache line as local_irq_count, it is cheap to access and is also used on UP
- * for uniformity.
- */
-typedef struct {
-        unsigned int __softirq_pending; /* set_bit is used on this */
-        unsigned int __last_jiffy_stamp;
-} ____cacheline_aligned irq_cpustat_t;
-
-#include <linux/irq_cpustat.h>  /* Standard mappings for irq_cpustat_t above */
-
-#define last_jiffy_stamp(cpu) __IRQ_STAT((cpu), __last_jiffy_stamp)
-
-static inline void ack_bad_irq(int irq)
-{
-        printk(KERN_CRIT "illegal vector %d received!\n", irq);
-        BUG();
-}
-
-#endif /* __KERNEL__ */
-#endif /* _ASM_POWERPC_HARDIRQ_H */
+#include <asm-generic/hardirq.h>
diff --git a/arch/powerpc/include/asm/hw_irq.h b/arch/powerpc/include/asm/hw_irq.h
index 8b505eaaa38a..e73d554538dd 100644
--- a/arch/powerpc/include/asm/hw_irq.h
+++ b/arch/powerpc/include/asm/hw_irq.h
@@ -49,8 +49,13 @@ extern void iseries_handle_interrupts(void);
 #define raw_irqs_disabled()             (local_get_flags() == 0)
 #define raw_irqs_disabled_flags(flags)  ((flags) == 0)
 
+#ifdef CONFIG_PPC_BOOK3E
+#define __hard_irq_enable()     __asm__ __volatile__("wrteei 1": : :"memory");
+#define __hard_irq_disable()    __asm__ __volatile__("wrteei 0": : :"memory");
+#else
 #define __hard_irq_enable()     __mtmsrd(mfmsr() | MSR_EE, 1)
 #define __hard_irq_disable()    __mtmsrd(mfmsr() & ~MSR_EE, 1)
+#endif
 
 #define  hard_irq_disable()                     \
         do {                                    \
diff --git a/arch/powerpc/include/asm/iommu.h b/arch/powerpc/include/asm/iommu.h
index 7ead7c16fb7c..7464c0daddd1 100644
--- a/arch/powerpc/include/asm/iommu.h
+++ b/arch/powerpc/include/asm/iommu.h
@@ -35,16 +35,6 @@
 #define IOMMU_PAGE_MASK       (~((1 << IOMMU_PAGE_SHIFT) - 1))
 #define IOMMU_PAGE_ALIGN(addr) _ALIGN_UP(addr, IOMMU_PAGE_SIZE)
 
-/* Cell page table entries */
-#define CBE_IOPTE_PP_W          0x8000000000000000ul /* protection: write */
-#define CBE_IOPTE_PP_R          0x4000000000000000ul /* protection: read */
-#define CBE_IOPTE_M             0x2000000000000000ul /* coherency required */
-#define CBE_IOPTE_SO_R          0x1000000000000000ul /* ordering: writes */
-#define CBE_IOPTE_SO_RW         0x1800000000000000ul /* ordering: r & w */
-#define CBE_IOPTE_RPN_Mask      0x07fffffffffff000ul /* RPN */
-#define CBE_IOPTE_H             0x0000000000000800ul /* cache hint */
-#define CBE_IOPTE_IOID_Mask     0x00000000000007fful /* ioid */
-
 /* Boot time flags */
 extern int iommu_is_off;
 extern int iommu_force_on;
diff --git a/arch/powerpc/include/asm/mmu-40x.h b/arch/powerpc/include/asm/mmu-40x.h
index 776f415a36aa..34916865eaef 100644
--- a/arch/powerpc/include/asm/mmu-40x.h
+++ b/arch/powerpc/include/asm/mmu-40x.h
@@ -61,4 +61,7 @@ typedef struct {
 
 #endif /* !__ASSEMBLY__ */
 
+#define mmu_virtual_psize       MMU_PAGE_4K
+#define mmu_linear_psize        MMU_PAGE_256M
+
 #endif /* _ASM_POWERPC_MMU_40X_H_ */
diff --git a/arch/powerpc/include/asm/mmu-44x.h b/arch/powerpc/include/asm/mmu-44x.h
index 3c86576bfefa..0372669383a8 100644
--- a/arch/powerpc/include/asm/mmu-44x.h
+++ b/arch/powerpc/include/asm/mmu-44x.h
@@ -79,16 +79,22 @@ typedef struct {
 
 #if (PAGE_SHIFT == 12)
 #define PPC44x_TLBE_SIZE        PPC44x_TLB_4K
+#define mmu_virtual_psize       MMU_PAGE_4K
 #elif (PAGE_SHIFT == 14)
 #define PPC44x_TLBE_SIZE        PPC44x_TLB_16K
+#define mmu_virtual_psize       MMU_PAGE_16K
 #elif (PAGE_SHIFT == 16)
 #define PPC44x_TLBE_SIZE        PPC44x_TLB_64K
+#define mmu_virtual_psize       MMU_PAGE_64K
 #elif (PAGE_SHIFT == 18)
 #define PPC44x_TLBE_SIZE        PPC44x_TLB_256K
+#define mmu_virtual_psize       MMU_PAGE_256K
 #else
 #error "Unsupported PAGE_SIZE"
 #endif
 
+#define mmu_linear_psize        MMU_PAGE_256M
+
 #define PPC44x_PGD_OFF_SHIFT    (32 - PGDIR_SHIFT + PGD_T_LOG2)
 #define PPC44x_PGD_OFF_MASK_BIT (PGDIR_SHIFT - PGD_T_LOG2)
 #define PPC44x_PTE_ADD_SHIFT    (32 - PGDIR_SHIFT + PTE_SHIFT + PTE_T_LOG2)
diff --git a/arch/powerpc/include/asm/mmu-8xx.h b/arch/powerpc/include/asm/mmu-8xx.h
index 07865a357848..3d11d3ce79ec 100644
--- a/arch/powerpc/include/asm/mmu-8xx.h
+++ b/arch/powerpc/include/asm/mmu-8xx.h
@@ -143,4 +143,7 @@ typedef struct {
 } mm_context_t;
 #endif /* !__ASSEMBLY__ */
 
+#define mmu_virtual_psize       MMU_PAGE_4K
+#define mmu_linear_psize        MMU_PAGE_8M
+
 #endif /* _ASM_POWERPC_MMU_8XX_H_ */
diff --git a/arch/powerpc/include/asm/mmu-book3e.h b/arch/powerpc/include/asm/mmu-book3e.h
index 7e74cff81d86..d74580469361 100644
--- a/arch/powerpc/include/asm/mmu-book3e.h
+++ b/arch/powerpc/include/asm/mmu-book3e.h
@@ -38,58 +38,128 @@
 #define BOOK3E_PAGESZ_1TB       30
 #define BOOK3E_PAGESZ_2TB       31
 
-#define MAS0_TLBSEL(x)  ((x << 28) & 0x30000000)
-#define MAS0_ESEL(x)    ((x << 16) & 0x0FFF0000)
-#define MAS0_NV(x)      ((x) & 0x00000FFF)
-
-#define MAS1_VALID      0x80000000
-#define MAS1_IPROT      0x40000000
-#define MAS1_TID(x)     ((x << 16) & 0x3FFF0000)
-#define MAS1_IND        0x00002000
-#define MAS1_TS         0x00001000
-#define MAS1_TSIZE(x)   ((x << 7) & 0x00000F80)
-
-#define MAS2_EPN        0xFFFFF000
-#define MAS2_X0         0x00000040
-#define MAS2_X1         0x00000020
-#define MAS2_W          0x00000010
-#define MAS2_I          0x00000008
-#define MAS2_M          0x00000004
-#define MAS2_G          0x00000002
-#define MAS2_E          0x00000001
+/* MAS registers bit definitions */
+
+#define MAS0_TLBSEL(x)          ((x << 28) & 0x30000000)
+#define MAS0_ESEL(x)            ((x << 16) & 0x0FFF0000)
+#define MAS0_NV(x)              ((x) & 0x00000FFF)
+#define MAS0_HES                0x00004000
+#define MAS0_WQ_ALLWAYS         0x00000000
+#define MAS0_WQ_COND            0x00001000
+#define MAS0_WQ_CLR_RSRV        0x00002000
+
+#define MAS1_VALID              0x80000000
+#define MAS1_IPROT              0x40000000
+#define MAS1_TID(x)             ((x << 16) & 0x3FFF0000)
+#define MAS1_IND                0x00002000
+#define MAS1_TS                 0x00001000
+#define MAS1_TSIZE_MASK         0x00000f80
+#define MAS1_TSIZE_SHIFT        7
+#define MAS1_TSIZE(x)           ((x << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK)
+
+#define MAS2_EPN                0xFFFFF000
+#define MAS2_X0                 0x00000040
+#define MAS2_X1                 0x00000020
+#define MAS2_W                  0x00000010
+#define MAS2_I                  0x00000008
+#define MAS2_M                  0x00000004
+#define MAS2_G                  0x00000002
+#define MAS2_E                  0x00000001
 #define MAS2_EPN_MASK(size)             (~0 << (size + 10))
 #define MAS2_VAL(addr, size, flags)     ((addr) & MAS2_EPN_MASK(size) | (flags))
 
-#define MAS3_RPN        0xFFFFF000
-#define MAS3_U0         0x00000200
-#define MAS3_U1         0x00000100
-#define MAS3_U2         0x00000080
-#define MAS3_U3         0x00000040
-#define MAS3_UX         0x00000020
-#define MAS3_SX         0x00000010
-#define MAS3_UW         0x00000008
-#define MAS3_SW         0x00000004
-#define MAS3_UR         0x00000002
-#define MAS3_SR         0x00000001
-
-#define MAS4_TLBSELD(x) MAS0_TLBSEL(x)
-#define MAS4_INDD       0x00008000
-#define MAS4_TSIZED(x)  MAS1_TSIZE(x)
-#define MAS4_X0D        0x00000040
-#define MAS4_X1D        0x00000020
-#define MAS4_WD         0x00000010
-#define MAS4_ID         0x00000008
-#define MAS4_MD         0x00000004
-#define MAS4_GD         0x00000002
-#define MAS4_ED         0x00000001
-
-#define MAS6_SPID0      0x3FFF0000
-#define MAS6_SPID1      0x00007FFE
-#define MAS6_ISIZE(x)   MAS1_TSIZE(x)
-#define MAS6_SAS        0x00000001
-#define MAS6_SPID       MAS6_SPID0
-
-#define MAS7_RPN        0xFFFFFFFF
+#define MAS3_RPN                0xFFFFF000
+#define MAS3_U0                 0x00000200
+#define MAS3_U1                 0x00000100
+#define MAS3_U2                 0x00000080
+#define MAS3_U3                 0x00000040
+#define MAS3_UX                 0x00000020
+#define MAS3_SX                 0x00000010
+#define MAS3_UW                 0x00000008
+#define MAS3_SW                 0x00000004
+#define MAS3_UR                 0x00000002
+#define MAS3_SR                 0x00000001
+#define MAS3_SPSIZE             0x0000003e
+#define MAS3_SPSIZE_SHIFT       1
+
+#define MAS4_TLBSELD(x)         MAS0_TLBSEL(x)
+#define MAS4_INDD               0x00008000      /* Default IND */
+#define MAS4_TSIZED(x)          MAS1_TSIZE(x)
+#define MAS4_X0D                0x00000040
+#define MAS4_X1D                0x00000020
+#define MAS4_WD                 0x00000010
+#define MAS4_ID                 0x00000008
+#define MAS4_MD                 0x00000004
+#define MAS4_GD                 0x00000002
+#define MAS4_ED                 0x00000001
+#define MAS4_WIMGED_MASK        0x0000001f      /* Default WIMGE */
+#define MAS4_WIMGED_SHIFT       0
+#define MAS4_VLED               MAS4_X1D        /* Default VLE */
+#define MAS4_ACMD               0x000000c0      /* Default ACM */
+#define MAS4_ACMD_SHIFT         6
+#define MAS4_TSIZED_MASK        0x00000f80      /* Default TSIZE */
+#define MAS4_TSIZED_SHIFT       7
+
+#define MAS6_SPID0              0x3FFF0000
+#define MAS6_SPID1              0x00007FFE
+#define MAS6_ISIZE(x)           MAS1_TSIZE(x)
+#define MAS6_SAS                0x00000001
+#define MAS6_SPID               MAS6_SPID0
+#define MAS6_SIND               0x00000002      /* Indirect page */
+#define MAS6_SIND_SHIFT         1
+#define MAS6_SPID_MASK          0x3fff0000
+#define MAS6_SPID_SHIFT         16
+#define MAS6_ISIZE_MASK         0x00000f80
+#define MAS6_ISIZE_SHIFT        7
+
+#define MAS7_RPN                0xFFFFFFFF
+
+/* TLBnCFG encoding */
+#define TLBnCFG_N_ENTRY         0x00000fff      /* number of entries */
+#define TLBnCFG_HES             0x00002000      /* HW select supported */
+#define TLBnCFG_IPROT           0x00008000      /* IPROT supported */
+#define TLBnCFG_GTWE            0x00010000      /* Guest can write */
+#define TLBnCFG_IND             0x00020000      /* IND entries supported */
+#define TLBnCFG_PT              0x00040000      /* Can load from page table */
+#define TLBnCFG_ASSOC           0xff000000      /* Associativity */
+
+/* TLBnPS encoding */
+#define TLBnPS_4K               0x00000004
+#define TLBnPS_8K               0x00000008
+#define TLBnPS_16K              0x00000010
+#define TLBnPS_32K              0x00000020
+#define TLBnPS_64K              0x00000040
+#define TLBnPS_128K             0x00000080
+#define TLBnPS_256K             0x00000100
+#define TLBnPS_512K             0x00000200
+#define TLBnPS_1M               0x00000400
+#define TLBnPS_2M               0x00000800
+#define TLBnPS_4M               0x00001000
+#define TLBnPS_8M               0x00002000
+#define TLBnPS_16M              0x00004000
+#define TLBnPS_32M              0x00008000
+#define TLBnPS_64M              0x00010000
+#define TLBnPS_128M             0x00020000
+#define TLBnPS_256M             0x00040000
+#define TLBnPS_512M             0x00080000
+#define TLBnPS_1G               0x00100000
+#define TLBnPS_2G               0x00200000
+#define TLBnPS_4G               0x00400000
+#define TLBnPS_8G               0x00800000
+#define TLBnPS_16G              0x01000000
+#define TLBnPS_32G              0x02000000
+#define TLBnPS_64G              0x04000000
+#define TLBnPS_128G             0x08000000
+#define TLBnPS_256G             0x10000000
+
+/* tlbilx action encoding */
+#define TLBILX_T_ALL                    0
+#define TLBILX_T_TID                    1
+#define TLBILX_T_FULLMATCH              3
+#define TLBILX_T_CLASS0                 4
+#define TLBILX_T_CLASS1                 5
+#define TLBILX_T_CLASS2                 6
+#define TLBILX_T_CLASS3                 7
 
 #ifndef __ASSEMBLY__
 
@@ -100,6 +170,34 @@ typedef struct {
         unsigned int    active;
         unsigned long   vdso_base;
 } mm_context_t;
+
+/* Page size definitions, common between 32 and 64-bit
+ *
+ *    shift : is the "PAGE_SHIFT" value for that page size
+ *    penc  : is the pte encoding mask
+ *
+ */
+struct mmu_psize_def
+{
+        unsigned int    shift;  /* number of bits */
+        unsigned int    enc;    /* PTE encoding */
+};
+extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
+
+/* The page sizes use the same names as 64-bit hash but are
+ * constants
+ */
+#if defined(CONFIG_PPC_4K_PAGES)
+#define mmu_virtual_psize       MMU_PAGE_4K
+#elif defined(CONFIG_PPC_64K_PAGES)
+#define mmu_virtual_psize       MMU_PAGE_64K
+#else
+#error Unsupported page size
+#endif
+
+extern int mmu_linear_psize;
+extern int mmu_vmemmap_psize;
+
 #endif /* !__ASSEMBLY__ */
 
 #endif /* _ASM_POWERPC_MMU_BOOK3E_H_ */
diff --git a/arch/powerpc/include/asm/mmu-hash32.h b/arch/powerpc/include/asm/mmu-hash32.h
index 16b1a1e77e64..382fc689f204 100644
--- a/arch/powerpc/include/asm/mmu-hash32.h
+++ b/arch/powerpc/include/asm/mmu-hash32.h
@@ -80,4 +80,10 @@ typedef struct {
 
 #endif /* !__ASSEMBLY__ */
 
+/* We happily ignore the smaller BATs on 601, we don't actually use
+ * those definitions on hash32 at the moment anyway
+ */
+#define mmu_virtual_psize       MMU_PAGE_4K
+#define mmu_linear_psize        MMU_PAGE_256M
+
 #endif /* _ASM_POWERPC_MMU_HASH32_H_ */
diff --git a/arch/powerpc/include/asm/mmu-hash64.h b/arch/powerpc/include/asm/mmu-hash64.h
index 98c104a09961..b537903b9fca 100644
--- a/arch/powerpc/include/asm/mmu-hash64.h
+++ b/arch/powerpc/include/asm/mmu-hash64.h
@@ -139,26 +139,6 @@ struct mmu_psize_def
 #endif /* __ASSEMBLY__ */
 
 /*
- * The kernel use the constants below to index in the page sizes array.
- * The use of fixed constants for this purpose is better for performances
- * of the low level hash refill handlers.
- *
- * A non supported page size has a "shift" field set to 0
- *
- * Any new page size being implemented can get a new entry in here. Whether
- * the kernel will use it or not is a different matter though. The actual page
- * size used by hugetlbfs is not defined here and may be made variable
- */
-
-#define MMU_PAGE_4K             0       /* 4K */
-#define MMU_PAGE_64K            1       /* 64K */
-#define MMU_PAGE_64K_AP         2       /* 64K Admixed (in a 4K segment) */
-#define MMU_PAGE_1M             3       /* 1M */
-#define MMU_PAGE_16M            4       /* 16M */
-#define MMU_PAGE_16G            5       /* 16G */
-#define MMU_PAGE_COUNT          6
-
-/*
  * Segment sizes.
  * These are the values used by hardware in the B field of
  * SLB entries and the first dword of MMU hashtable entries.
diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
index fb57ded592f9..2fcfefc60894 100644
--- a/arch/powerpc/include/asm/mmu.h
+++ b/arch/powerpc/include/asm/mmu.h
@@ -17,6 +17,7 @@
 #define MMU_FTR_TYPE_40x                ASM_CONST(0x00000004)
 #define MMU_FTR_TYPE_44x                ASM_CONST(0x00000008)
 #define MMU_FTR_TYPE_FSL_E              ASM_CONST(0x00000010)
+#define MMU_FTR_TYPE_3E                 ASM_CONST(0x00000020)
 
 /*
  * This is individual features
@@ -73,6 +74,41 @@ extern void early_init_mmu_secondary(void);
 
 #endif /* !__ASSEMBLY__ */
 
+/* The kernel use the constants below to index in the page sizes array.
+ * The use of fixed constants for this purpose is better for performances
+ * of the low level hash refill handlers.
+ *
+ * A non supported page size has a "shift" field set to 0
+ *
+ * Any new page size being implemented can get a new entry in here. Whether
+ * the kernel will use it or not is a different matter though. The actual page
+ * size used by hugetlbfs is not defined here and may be made variable
+ *
+ * Note: This array ended up being a false good idea as it's growing to the
+ * point where I wonder if we should replace it with something different,
+ * to think about, feedback welcome. --BenH.
+ */
+
+/* There are #define as they have to be used in assembly
+ *
+ * WARNING: If you change this list, make sure to update the array of
+ * names currently in arch/powerpc/mm/hugetlbpage.c or bad things will
+ * happen
+ */
+#define MMU_PAGE_4K     0
+#define MMU_PAGE_16K    1
+#define MMU_PAGE_64K    2
+#define MMU_PAGE_64K_AP 3       /* "Admixed pages" (hash64 only) */
+#define MMU_PAGE_256K   4
+#define MMU_PAGE_1M     5
+#define MMU_PAGE_8M     6
+#define MMU_PAGE_16M    7
+#define MMU_PAGE_256M   8
+#define MMU_PAGE_1G     9
+#define MMU_PAGE_16G    10
+#define MMU_PAGE_64G    11
+#define MMU_PAGE_COUNT  12
+
 
 #if defined(CONFIG_PPC_STD_MMU_64)
 /* 64-bit classic hash table MMU */
@@ -94,5 +130,6 @@ extern void early_init_mmu_secondary(void);
 #  include <asm/mmu-8xx.h>
 #endif
 
+
 #endif /* __KERNEL__ */
 #endif /* _ASM_POWERPC_MMU_H_ */
diff --git a/arch/powerpc/include/asm/mmu_context.h b/arch/powerpc/include/asm/mmu_context.h
index b7063669f972..b34e94d94435 100644
--- a/arch/powerpc/include/asm/mmu_context.h
+++ b/arch/powerpc/include/asm/mmu_context.h
@@ -14,7 +14,6 @@
 /*
  * Most if the context management is out of line
  */
-extern void mmu_context_init(void);
 extern int init_new_context(struct task_struct *tsk, struct mm_struct *mm);
 extern void destroy_context(struct mm_struct *mm);
 
@@ -23,6 +22,12 @@ extern void switch_stab(struct task_struct *tsk, struct mm_struct *mm);
 extern void switch_slb(struct task_struct *tsk, struct mm_struct *mm);
 extern void set_context(unsigned long id, pgd_t *pgd);
 
+#ifdef CONFIG_PPC_BOOK3S_64
+static inline void mmu_context_init(void) { }
+#else
+extern void mmu_context_init(void);
+#endif
+
 /*
  * switch_mm is the entry point called from the architecture independent
  * code in kernel/sched.c
@@ -38,6 +43,10 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
         tsk->thread.pgdir = next->pgd;
 #endif /* CONFIG_PPC32 */
 
+        /* 64-bit Book3E keeps track of current PGD in the PACA */
+#ifdef CONFIG_PPC_BOOK3E_64
+        get_paca()->pgd = next->pgd;
+#endif
         /* Nothing else to do if we aren't actually switching */
         if (prev == next)
                 return;
@@ -84,6 +93,10 @@ static inline void activate_mm(struct mm_struct *prev, struct mm_struct *next)
 static inline void enter_lazy_tlb(struct mm_struct *mm,
                                   struct task_struct *tsk)
 {
+        /* 64-bit Book3E keeps track of current PGD in the PACA */
+#ifdef CONFIG_PPC_BOOK3E_64
+        get_paca()->pgd = NULL;
+#endif
 }
 
 #endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/paca.h b/arch/powerpc/include/asm/paca.h
index c8a3cbfe02ff..b634456ea893 100644
--- a/arch/powerpc/include/asm/paca.h
+++ b/arch/powerpc/include/asm/paca.h
@@ -14,9 +14,11 @@
 #define _ASM_POWERPC_PACA_H
 #ifdef __KERNEL__
 
-#include        <asm/types.h>
-#include        <asm/lppaca.h>
-#include        <asm/mmu.h>
+#include <asm/types.h>
+#include <asm/lppaca.h>
+#include <asm/mmu.h>
+#include <asm/page.h>
+#include <asm/exception-64e.h>
 
 register struct paca_struct *local_paca asm("r13");
 
@@ -91,6 +93,21 @@ struct paca_struct {
         u16 slb_cache[SLB_CACHE_ENTRIES];
 #endif /* CONFIG_PPC_STD_MMU_64 */
 
+#ifdef CONFIG_PPC_BOOK3E
+        pgd_t *pgd;                     /* Current PGD */
+        pgd_t *kernel_pgd;              /* Kernel PGD */
+        u64 exgen[8] __attribute__((aligned(0x80)));
+        u64 extlb[EX_TLB_SIZE*3] __attribute__((aligned(0x80)));
+        u64 exmc[8];            /* used for machine checks */
+        u64 excrit[8];          /* used for crit interrupts */
+        u64 exdbg[8];           /* used for debug interrupts */
+
+        /* Kernel stack pointers for use by special exceptions */
+        void *mc_kstack;
+        void *crit_kstack;
+        void *dbg_kstack;
+#endif /* CONFIG_PPC_BOOK3E */
+
         mm_context_t context;
 
         /*
diff --git a/arch/powerpc/include/asm/page.h b/arch/powerpc/include/asm/page.h
index 4940662ee87e..ff24254990e1 100644
--- a/arch/powerpc/include/asm/page.h
+++ b/arch/powerpc/include/asm/page.h
@@ -139,7 +139,11 @@ extern phys_addr_t kernstart_addr;
  * Don't compare things with KERNELBASE or PAGE_OFFSET to test for
  * "kernelness", use is_kernel_addr() - it should do what you want.
  */
+#ifdef CONFIG_PPC_BOOK3E_64
+#define is_kernel_addr(x)       ((x) >= 0x8000000000000000ul)
+#else
 #define is_kernel_addr(x)       ((x) >= PAGE_OFFSET)
+#endif
 
 #ifndef __ASSEMBLY__
 
diff --git a/arch/powerpc/include/asm/page_64.h b/arch/powerpc/include/asm/page_64.h
index 5817a3b747e5..3f17b83f55a1 100644
--- a/arch/powerpc/include/asm/page_64.h
+++ b/arch/powerpc/include/asm/page_64.h
@@ -135,12 +135,22 @@ extern void slice_set_range_psize(struct mm_struct *mm, unsigned long start,
 #endif /* __ASSEMBLY__ */
 #else
 #define slice_init()
+#ifdef CONFIG_PPC_STD_MMU_64
 #define get_slice_psize(mm, addr)       ((mm)->context.user_psize)
 #define slice_set_user_psize(mm, psize)         \
 do {                                            \
         (mm)->context.user_psize = (psize);     \
         (mm)->context.sllp = SLB_VSID_USER | mmu_psize_defs[(psize)].sllp; \
 } while (0)
+#else /* CONFIG_PPC_STD_MMU_64 */
+#ifdef CONFIG_PPC_64K_PAGES
+#define get_slice_psize(mm, addr)       MMU_PAGE_64K
+#else /* CONFIG_PPC_64K_PAGES */
+#define get_slice_psize(mm, addr)       MMU_PAGE_4K
+#endif /* !CONFIG_PPC_64K_PAGES */
+#define slice_set_user_psize(mm, psize) do { BUG(); } while(0)
+#endif /* !CONFIG_PPC_STD_MMU_64 */
+
 #define slice_set_range_psize(mm, start, len, psize)    \
         slice_set_user_psize((mm), (psize))
 #define slice_mm_new_context(mm)        1
diff --git a/arch/powerpc/include/asm/pgalloc.h b/arch/powerpc/include/asm/pgalloc.h
index 1730e5e298d6..f2e812de7c3c 100644
--- a/arch/powerpc/include/asm/pgalloc.h
+++ b/arch/powerpc/include/asm/pgalloc.h
@@ -4,6 +4,15 @@
 
 #include <linux/mm.h>
 
+#ifdef CONFIG_PPC_BOOK3E
+extern void tlb_flush_pgtable(struct mmu_gather *tlb, unsigned long address);
+#else /* CONFIG_PPC_BOOK3E */
+static inline void tlb_flush_pgtable(struct mmu_gather *tlb,
+                                     unsigned long address)
+{
+}
+#endif /* !CONFIG_PPC_BOOK3E */
+
 static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
 {
         free_page((unsigned long)pte);
@@ -19,7 +28,12 @@ typedef struct pgtable_free {
         unsigned long val;
 } pgtable_free_t;
 
-#define PGF_CACHENUM_MASK       0x7
+/* This needs to be big enough to allow for MMU_PAGE_COUNT + 2 to be stored
+ * and small enough to fit in the low bits of any naturally aligned page
+ * table cache entry. Arbitrarily set to 0x1f, that should give us some
+ * room to grow
+ */
+#define PGF_CACHENUM_MASK       0x1f
 
 static inline pgtable_free_t pgtable_free_cache(void *p, int cachenum,
                                                 unsigned long mask)
@@ -35,19 +49,27 @@ static inline pgtable_free_t pgtable_free_cache(void *p, int cachenum,
 #include <asm/pgalloc-32.h>
 #endif
 
-extern void pgtable_free_tlb(struct mmu_gather *tlb, pgtable_free_t pgf);
-
 #ifdef CONFIG_SMP
-#define __pte_free_tlb(tlb,ptepage,address)             \
-do { \
-        pgtable_page_dtor(ptepage); \
-        pgtable_free_tlb(tlb, pgtable_free_cache(page_address(ptepage), \
-                                        PTE_NONCACHE_NUM, PTE_TABLE_SIZE-1)); \
-} while (0)
-#else
-#define __pte_free_tlb(tlb, pte, address)       pte_free((tlb)->mm, (pte))
-#endif
+extern void pgtable_free_tlb(struct mmu_gather *tlb, pgtable_free_t pgf);
+extern void pte_free_finish(void);
+#else /* CONFIG_SMP */
+static inline void pgtable_free_tlb(struct mmu_gather *tlb, pgtable_free_t pgf)
+{
+        pgtable_free(pgf);
+}
+static inline void pte_free_finish(void) { }
+#endif /* !CONFIG_SMP */
 
+static inline void __pte_free_tlb(struct mmu_gather *tlb, struct page *ptepage,
+                                  unsigned long address)
+{
+        pgtable_free_t pgf = pgtable_free_cache(page_address(ptepage),
+                                                PTE_NONCACHE_NUM,
+                                                PTE_TABLE_SIZE-1);
+        tlb_flush_pgtable(tlb, address);
+        pgtable_page_dtor(ptepage);
+        pgtable_free_tlb(tlb, pgf);
+}
 
 #endif /* __KERNEL__ */
 #endif /* _ASM_POWERPC_PGALLOC_H */
diff --git a/arch/powerpc/include/asm/pgtable-ppc64-64k.h b/arch/powerpc/include/asm/pgtable-ppc64-64k.h
index 6cc085b945a5..90533ddcd703 100644
--- a/arch/powerpc/include/asm/pgtable-ppc64-64k.h
+++ b/arch/powerpc/include/asm/pgtable-ppc64-64k.h
@@ -10,10 +10,10 @@
 #define PGD_INDEX_SIZE  4
 
 #ifndef __ASSEMBLY__
-
 #define PTE_TABLE_SIZE  (sizeof(real_pte_t) << PTE_INDEX_SIZE)
 #define PMD_TABLE_SIZE  (sizeof(pmd_t) << PMD_INDEX_SIZE)
 #define PGD_TABLE_SIZE  (sizeof(pgd_t) << PGD_INDEX_SIZE)
+#endif  /* __ASSEMBLY__ */
 
 #define PTRS_PER_PTE    (1 << PTE_INDEX_SIZE)
 #define PTRS_PER_PMD    (1 << PMD_INDEX_SIZE)
@@ -32,8 +32,6 @@
 #define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
 #define PGDIR_MASK      (~(PGDIR_SIZE-1))
 
-#endif  /* __ASSEMBLY__ */
-
 /* Bits to mask out from a PMD to get to the PTE page */
 #define PMD_MASKED_BITS         0x1ff
 /* Bits to mask out from a PGD/PUD to get to the PMD page */
diff --git a/arch/powerpc/include/asm/pgtable-ppc64.h b/arch/powerpc/include/asm/pgtable-ppc64.h
index 8cd083c61503..200ec2dfa034 100644
--- a/arch/powerpc/include/asm/pgtable-ppc64.h
+++ b/arch/powerpc/include/asm/pgtable-ppc64.h
@@ -5,11 +5,6 @@
  * the ppc64 hashed page table.
  */
 
-#ifndef __ASSEMBLY__
-#include <linux/stddef.h>
-#include <asm/tlbflush.h>
-#endif /* __ASSEMBLY__ */
-
 #ifdef CONFIG_PPC_64K_PAGES
 #include <asm/pgtable-ppc64-64k.h>
 #else
@@ -38,26 +33,47 @@
 #endif
 
 /*
- * Define the address range of the vmalloc VM area.
+ * Define the address range of the kernel non-linear virtual area
+ */
+
+#ifdef CONFIG_PPC_BOOK3E
+#define KERN_VIRT_START ASM_CONST(0x8000000000000000)
+#else
+#define KERN_VIRT_START ASM_CONST(0xD000000000000000)
+#endif
+#define KERN_VIRT_SIZE  PGTABLE_RANGE
+
+/*
+ * The vmalloc space starts at the beginning of that region, and
+ * occupies half of it on hash CPUs and a quarter of it on Book3E
+ * (we keep a quarter for the virtual memmap)
  */
-#define VMALLOC_START ASM_CONST(0xD000000000000000)
-#define VMALLOC_SIZE  (PGTABLE_RANGE >> 1)
-#define VMALLOC_END   (VMALLOC_START + VMALLOC_SIZE)
+#define VMALLOC_START   KERN_VIRT_START
+#ifdef CONFIG_PPC_BOOK3E
+#define VMALLOC_SIZE    (KERN_VIRT_SIZE >> 2)
+#else
+#define VMALLOC_SIZE    (KERN_VIRT_SIZE >> 1)
+#endif
+#define VMALLOC_END     (VMALLOC_START + VMALLOC_SIZE)
 
 /*
- * Define the address ranges for MMIO and IO space :
+ * The second half of the kernel virtual space is used for IO mappings,
+ * it's itself carved into the PIO region (ISA and PHB IO space) and
+ * the ioremap space
  *
- *  ISA_IO_BASE = VMALLOC_END, 64K reserved area
+ *  ISA_IO_BASE = KERN_IO_START, 64K reserved area
  *  PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces
  * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE
  */
+#define KERN_IO_START   (KERN_VIRT_START + (KERN_VIRT_SIZE >> 1))
 #define FULL_IO_SIZE    0x80000000ul
-#define  ISA_IO_BASE    (VMALLOC_END)
-#define  ISA_IO_END     (VMALLOC_END + 0x10000ul)
+#define  ISA_IO_BASE    (KERN_IO_START)
+#define  ISA_IO_END     (KERN_IO_START + 0x10000ul)
 #define  PHB_IO_BASE    (ISA_IO_END)
-#define  PHB_IO_END     (VMALLOC_END + FULL_IO_SIZE)
+#define  PHB_IO_END     (KERN_IO_START + FULL_IO_SIZE)
 #define IOREMAP_BASE    (PHB_IO_END)
-#define IOREMAP_END     (VMALLOC_START + PGTABLE_RANGE)
+#define IOREMAP_END     (KERN_VIRT_START + KERN_VIRT_SIZE)
+
 
 /*
  * Region IDs
@@ -68,23 +84,32 @@
 
 #define VMALLOC_REGION_ID       (REGION_ID(VMALLOC_START))
 #define KERNEL_REGION_ID        (REGION_ID(PAGE_OFFSET))
-#define VMEMMAP_REGION_ID       (0xfUL)
+#define VMEMMAP_REGION_ID       (0xfUL) /* Server only */
 #define USER_REGION_ID          (0UL)
 
 /*
- * Defines the address of the vmemap area, in its own region
+ * Defines the address of the vmemap area, in its own region on
+ * hash table CPUs and after the vmalloc space on Book3E
  */
+#ifdef CONFIG_PPC_BOOK3E
+#define VMEMMAP_BASE            VMALLOC_END
+#define VMEMMAP_END             KERN_IO_START
+#else
 #define VMEMMAP_BASE            (VMEMMAP_REGION_ID << REGION_SHIFT)
+#endif
 #define vmemmap                 ((struct page *)VMEMMAP_BASE)
 
 
 /*
  * Include the PTE bits definitions
  */
+#ifdef CONFIG_PPC_BOOK3S
 #include <asm/pte-hash64.h>
+#else
+#include <asm/pte-book3e.h>
+#endif
 #include <asm/pte-common.h>
 
-
 #ifdef CONFIG_PPC_MM_SLICES
 #define HAVE_ARCH_UNMAPPED_AREA
 #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
@@ -92,6 +117,9 @@
 
 #ifndef __ASSEMBLY__
 
+#include <linux/stddef.h>
+#include <asm/tlbflush.h>
+
 /*
  * This is the default implementation of various PTE accessors, it's
  * used in all cases except Book3S with 64K pages where we have a
diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h
index b74f16d45cb4..ef9aa84cac5a 100644
--- a/arch/powerpc/include/asm/ppc-opcode.h
+++ b/arch/powerpc/include/asm/ppc-opcode.h
@@ -48,6 +48,8 @@
 #define PPC_INST_TLBIE                  0x7c000264
 #define PPC_INST_TLBILX                 0x7c000024
 #define PPC_INST_WAIT                   0x7c00007c
+#define PPC_INST_TLBIVAX                0x7c000624
+#define PPC_INST_TLBSRX_DOT             0x7c0006a5
 
 /* macros to insert fields into opcodes */
 #define __PPC_RA(a)     (((a) & 0x1f) << 16)
@@ -76,6 +78,10 @@
                                         __PPC_WC(w))
 #define PPC_TLBIE(lp,a)         stringify_in_c(.long PPC_INST_TLBIE | \
                                                __PPC_RB(a) | __PPC_RS(lp))
+#define PPC_TLBSRX_DOT(a,b)     stringify_in_c(.long PPC_INST_TLBSRX_DOT | \
+                                        __PPC_RA(a) | __PPC_RB(b))
+#define PPC_TLBIVAX(a,b)        stringify_in_c(.long PPC_INST_TLBIVAX | \
+                                        __PPC_RA(a) | __PPC_RB(b))
 
 /*
  * Define what the VSX XX1 form instructions will look like, then add
diff --git a/arch/powerpc/include/asm/ppc_asm.h b/arch/powerpc/include/asm/ppc_asm.h
index f9729529c20d..dfae6e916dfb 100644
--- a/arch/powerpc/include/asm/ppc_asm.h
+++ b/arch/powerpc/include/asm/ppc_asm.h
@@ -375,8 +375,15 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
 #define PPC440EP_ERR42
 #endif
 
-
-#if defined(CONFIG_BOOKE)
+/*
+ * toreal/fromreal/tophys/tovirt macros. 32-bit BookE makes them
+ * keep the address intact to be compatible with code shared with
+ * 32-bit classic.
+ *
+ * On the other hand, I find it useful to have them behave as expected
+ * by their name (ie always do the addition) on 64-bit BookE
+ */
+#if defined(CONFIG_BOOKE) && !defined(CONFIG_PPC64)
 #define toreal(rd)
 #define fromreal(rd)
 
@@ -426,10 +433,9 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
         .previous
 #endif
 
-#ifdef CONFIG_PPC64
+#ifdef CONFIG_PPC_BOOK3S_64
 #define RFI             rfid
 #define MTMSRD(r)       mtmsrd  r
-
 #else
 #define FIX_SRR1(ra, rb)
 #ifndef CONFIG_40x
diff --git a/arch/powerpc/include/asm/pte-book3e.h b/arch/powerpc/include/asm/pte-book3e.h
new file mode 100644
index 000000000000..1d27c77d7704
--- /dev/null
+++ b/arch/powerpc/include/asm/pte-book3e.h
@@ -0,0 +1,70 @@
+#ifndef _ASM_POWERPC_PTE_BOOK3E_H
+#define _ASM_POWERPC_PTE_BOOK3E_H
+#ifdef __KERNEL__
+
+/* PTE bit definitions for processors compliant to the Book3E
+ * architecture 2.06 or later. The position of the PTE bits
+ * matches the HW definition of the optional Embedded Page Table
+ * category.
+ */
+
+/* Architected bits */
+#define _PAGE_PRESENT   0x000001 /* software: pte contains a translation */
+#define _PAGE_FILE      0x000002 /* (!present only) software: pte holds file offset */
+#define _PAGE_SW1       0x000002
+#define _PAGE_BAP_SR    0x000004
+#define _PAGE_BAP_UR    0x000008
+#define _PAGE_BAP_SW    0x000010
+#define _PAGE_BAP_UW    0x000020
+#define _PAGE_BAP_SX    0x000040
+#define _PAGE_BAP_UX    0x000080
+#define _PAGE_PSIZE_MSK 0x000f00
+#define _PAGE_PSIZE_4K  0x000200
+#define _PAGE_PSIZE_64K 0x000600
+#define _PAGE_PSIZE_1M  0x000a00
+#define _PAGE_PSIZE_16M 0x000e00
+#define _PAGE_DIRTY     0x001000 /* C: page changed */
+#define _PAGE_SW0       0x002000
+#define _PAGE_U3        0x004000
+#define _PAGE_U2        0x008000
+#define _PAGE_U1        0x010000
+#define _PAGE_U0        0x020000
+#define _PAGE_ACCESSED  0x040000
+#define _PAGE_LENDIAN   0x080000
+#define _PAGE_GUARDED   0x100000
+#define _PAGE_COHERENT  0x200000 /* M: enforce memory coherence */
+#define _PAGE_NO_CACHE  0x400000 /* I: cache inhibit */
+#define _PAGE_WRITETHRU 0x800000 /* W: cache write-through */
+
+/* "Higher level" linux bit combinations */
+#define _PAGE_EXEC      _PAGE_BAP_SX /* Can be executed from potentially */
+#define _PAGE_HWEXEC    _PAGE_BAP_UX /* .. and was cache cleaned */
+#define _PAGE_RW        (_PAGE_BAP_SW | _PAGE_BAP_UW) /* User write permission */
+#define _PAGE_KERNEL_RW (_PAGE_BAP_SW | _PAGE_BAP_SR | _PAGE_DIRTY)
+#define _PAGE_KERNEL_RO (_PAGE_BAP_SR)
+#define _PAGE_USER      (_PAGE_BAP_UR | _PAGE_BAP_SR) /* Can be read */
+
+#define _PAGE_HASHPTE   0
+#define _PAGE_BUSY      0
+
+#define _PAGE_SPECIAL   _PAGE_SW0
+
+/* Flags to be preserved on PTE modifications */
+#define _PAGE_HPTEFLAGS _PAGE_BUSY
+
+/* Base page size */
+#ifdef CONFIG_PPC_64K_PAGES
+#define _PAGE_PSIZE     _PAGE_PSIZE_64K
+#define PTE_RPN_SHIFT   (28)
+#else
+#define _PAGE_PSIZE     _PAGE_PSIZE_4K
+#define PTE_RPN_SHIFT   (24)
+#endif
+
+/* On 32-bit, we never clear the top part of the PTE */
+#ifdef CONFIG_PPC32
+#define _PTE_NONE_MASK  0xffffffff00000000ULL
+#endif
+
+#endif /* __KERNEL__ */
+#endif /*  _ASM_POWERPC_PTE_FSL_BOOKE_H */
diff --git a/arch/powerpc/include/asm/pte-common.h b/arch/powerpc/include/asm/pte-common.h
index a7e210b6b48c..8bb6464ba619 100644
--- a/arch/powerpc/include/asm/pte-common.h
+++ b/arch/powerpc/include/asm/pte-common.h
@@ -34,6 +34,9 @@
 #ifndef _PAGE_4K_PFN
 #define _PAGE_4K_PFN            0
 #endif
+#ifndef _PAGE_SAO
+#define _PAGE_SAO       0
+#endif
 #ifndef _PAGE_PSIZE
 #define _PAGE_PSIZE             0
 #endif
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 1170267736d3..6315edc205d8 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -98,19 +98,15 @@
 #define MSR_RI          __MASK(MSR_RI_LG)       /* Recoverable Exception */
 #define MSR_LE          __MASK(MSR_LE_LG)       /* Little Endian */
 
-#ifdef CONFIG_PPC64
+#if defined(CONFIG_PPC_BOOK3S_64)
+/* Server variant */
 #define MSR_            MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_ISF |MSR_HV
 #define MSR_KERNEL      MSR_ | MSR_SF
-
 #define MSR_USER32      MSR_ | MSR_PR | MSR_EE
 #define MSR_USER64      MSR_USER32 | MSR_SF
-
-#else /* 32-bit */
+#elif defined(CONFIG_PPC_BOOK3S_32) || defined(CONFIG_8xx)
 /* Default MSR for kernel mode. */
-#ifndef MSR_KERNEL      /* reg_booke.h also defines this */
 #define MSR_KERNEL      (MSR_ME|MSR_RI|MSR_IR|MSR_DR)
-#endif
-
 #define MSR_USER        (MSR_KERNEL|MSR_PR|MSR_EE)
 #endif
 
@@ -646,6 +642,137 @@
 #endif
 
 /*
+ * SPRG usage:
+ *
+ * All 64-bit:
+ *      - SPRG1 stores PACA pointer
+ *
+ * 64-bit server:
+ *      - SPRG0 unused (reserved for HV on Power4)
+ *      - SPRG2 scratch for exception vectors
+ *      - SPRG3 unused (user visible)
+ *
+ * 64-bit embedded
+ *      - SPRG0 generic exception scratch
+ *      - SPRG2 TLB exception stack
+ *      - SPRG3 unused (user visible)
+ *      - SPRG4 unused (user visible)
+ *      - SPRG6 TLB miss scratch (user visible, sorry !)
+ *      - SPRG7 critical exception scratch
+ *      - SPRG8 machine check exception scratch
+ *      - SPRG9 debug exception scratch
+ *
+ * All 32-bit:
+ *      - SPRG3 current thread_info pointer
+ *        (virtual on BookE, physical on others)
+ *
+ * 32-bit classic:
+ *      - SPRG0 scratch for exception vectors
+ *      - SPRG1 scratch for exception vectors
+ *      - SPRG2 indicator that we are in RTAS
+ *      - SPRG4 (603 only) pseudo TLB LRU data
+ *
+ * 32-bit 40x:
+ *      - SPRG0 scratch for exception vectors
+ *      - SPRG1 scratch for exception vectors
+ *      - SPRG2 scratch for exception vectors
+ *      - SPRG4 scratch for exception vectors (not 403)
+ *      - SPRG5 scratch for exception vectors (not 403)
+ *      - SPRG6 scratch for exception vectors (not 403)
+ *      - SPRG7 scratch for exception vectors (not 403)
+ *
+ * 32-bit 440 and FSL BookE:
+ *      - SPRG0 scratch for exception vectors
+ *      - SPRG1 scratch for exception vectors (*)
+ *      - SPRG2 scratch for crit interrupts handler
+ *      - SPRG4 scratch for exception vectors
+ *      - SPRG5 scratch for exception vectors
+ *      - SPRG6 scratch for machine check handler
+ *      - SPRG7 scratch for exception vectors
+ *      - SPRG9 scratch for debug vectors (e500 only)
+ *
+ *      Additionally, BookE separates "read" and "write"
+ *      of those registers. That allows to use the userspace
+ *      readable variant for reads, which can avoid a fault
+ *      with KVM type virtualization.
+ *
+ *      (*) Under KVM, the host SPRG1 is used to point to
+ *      the current VCPU data structure
+ *
+ * 32-bit 8xx:
+ *      - SPRG0 scratch for exception vectors
+ *      - SPRG1 scratch for exception vectors
+ *      - SPRG2 apparently unused but initialized
+ *
+ */
+#ifdef CONFIG_PPC64
+#define SPRN_SPRG_PACA          SPRN_SPRG1
+#else
+#define SPRN_SPRG_THREAD        SPRN_SPRG3
+#endif
+
+#ifdef CONFIG_PPC_BOOK3S_64
+#define SPRN_SPRG_SCRATCH0      SPRN_SPRG2
+#endif
+
+#ifdef CONFIG_PPC_BOOK3E_64
+#define SPRN_SPRG_MC_SCRATCH    SPRN_SPRG8
+#define SPRN_SPRG_CRIT_SCRATCH  SPRN_SPRG7
+#define SPRN_SPRG_DBG_SCRATCH   SPRN_SPRG9
+#define SPRN_SPRG_TLB_EXFRAME   SPRN_SPRG2
+#define SPRN_SPRG_TLB_SCRATCH   SPRN_SPRG6
+#define SPRN_SPRG_GEN_SCRATCH   SPRN_SPRG0
+#endif
+
+#ifdef CONFIG_PPC_BOOK3S_32
+#define SPRN_SPRG_SCRATCH0      SPRN_SPRG0
+#define SPRN_SPRG_SCRATCH1      SPRN_SPRG1
+#define SPRN_SPRG_RTAS          SPRN_SPRG2
+#define SPRN_SPRG_603_LRU       SPRN_SPRG4
+#endif
+
+#ifdef CONFIG_40x
+#define SPRN_SPRG_SCRATCH0      SPRN_SPRG0
+#define SPRN_SPRG_SCRATCH1      SPRN_SPRG1
+#define SPRN_SPRG_SCRATCH2      SPRN_SPRG2
+#define SPRN_SPRG_SCRATCH3      SPRN_SPRG4
+#define SPRN_SPRG_SCRATCH4      SPRN_SPRG5
+#define SPRN_SPRG_SCRATCH5      SPRN_SPRG6
+#define SPRN_SPRG_SCRATCH6      SPRN_SPRG7
+#endif
+
+#ifdef CONFIG_BOOKE
+#define SPRN_SPRG_RSCRATCH0     SPRN_SPRG0
+#define SPRN_SPRG_WSCRATCH0     SPRN_SPRG0
+#define SPRN_SPRG_RSCRATCH1     SPRN_SPRG1
+#define SPRN_SPRG_WSCRATCH1     SPRN_SPRG1
+#define SPRN_SPRG_RSCRATCH_CRIT SPRN_SPRG2
+#define SPRN_SPRG_WSCRATCH_CRIT SPRN_SPRG2
+#define SPRN_SPRG_RSCRATCH2     SPRN_SPRG4R
+#define SPRN_SPRG_WSCRATCH2     SPRN_SPRG4W
+#define SPRN_SPRG_RSCRATCH3     SPRN_SPRG5R
+#define SPRN_SPRG_WSCRATCH3     SPRN_SPRG5W
+#define SPRN_SPRG_RSCRATCH_MC   SPRN_SPRG6R
+#define SPRN_SPRG_WSCRATCH_MC   SPRN_SPRG6W
+#define SPRN_SPRG_RSCRATCH4     SPRN_SPRG7R
+#define SPRN_SPRG_WSCRATCH4     SPRN_SPRG7W
+#ifdef CONFIG_E200
+#define SPRN_SPRG_RSCRATCH_DBG  SPRN_SPRG6R
+#define SPRN_SPRG_WSCRATCH_DBG  SPRN_SPRG6W
+#else
+#define SPRN_SPRG_RSCRATCH_DBG  SPRN_SPRG9
+#define SPRN_SPRG_WSCRATCH_DBG  SPRN_SPRG9
+#endif
+#define SPRN_SPRG_RVCPU         SPRN_SPRG1
+#define SPRN_SPRG_WVCPU         SPRN_SPRG1
+#endif
+
+#ifdef CONFIG_8xx
+#define SPRN_SPRG_SCRATCH0      SPRN_SPRG0
+#define SPRN_SPRG_SCRATCH1      SPRN_SPRG1
+#endif
+
+/*
  * An mtfsf instruction with the L bit set. On CPUs that support this a
  * full 64bits of FPSCR is restored and on other CPUs the L bit is ignored.
  *
diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h
index 6bcf364cbb2f..2c9c706e6448 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -18,18 +18,26 @@
 #define MSR_IS          MSR_IR  /* Instruction Space */
 #define MSR_DS          MSR_DR  /* Data Space */
 #define MSR_PMM         (1<<2)  /* Performance monitor mark bit */
+#define MSR_CM          (1<<31) /* Computation Mode (0=32-bit, 1=64-bit) */
 
-/* Default MSR for kernel mode. */
-#if defined (CONFIG_40x)
+#if defined(CONFIG_PPC_BOOK3E_64)
+#define MSR_            MSR_ME | MSR_CE
+#define MSR_KERNEL      MSR_ | MSR_CM
+#define MSR_USER32      MSR_ | MSR_PR | MSR_EE
+#define MSR_USER64      MSR_USER32 | MSR_CM
+#elif defined (CONFIG_40x)
 #define MSR_KERNEL      (MSR_ME|MSR_RI|MSR_IR|MSR_DR|MSR_CE)
-#elif defined(CONFIG_BOOKE)
+#define MSR_USER        (MSR_KERNEL|MSR_PR|MSR_EE)
+#else
 #define MSR_KERNEL      (MSR_ME|MSR_RI|MSR_CE)
+#define MSR_USER        (MSR_KERNEL|MSR_PR|MSR_EE)
 #endif
 
 /* Special Purpose Registers (SPRNs)*/
 #define SPRN_DECAR      0x036   /* Decrementer Auto Reload Register */
 #define SPRN_IVPR       0x03F   /* Interrupt Vector Prefix Register */
 #define SPRN_USPRG0     0x100   /* User Special Purpose Register General 0 */
+#define SPRN_SPRG3R     0x103   /* Special Purpose Register General 3 Read */
 #define SPRN_SPRG4R     0x104   /* Special Purpose Register General 4 Read */
 #define SPRN_SPRG5R     0x105   /* Special Purpose Register General 5 Read */
 #define SPRN_SPRG6R     0x106   /* Special Purpose Register General 6 Read */
@@ -38,11 +46,18 @@
 #define SPRN_SPRG5W     0x115   /* Special Purpose Register General 5 Write */
 #define SPRN_SPRG6W     0x116   /* Special Purpose Register General 6 Write */
 #define SPRN_SPRG7W     0x117   /* Special Purpose Register General 7 Write */
+#define SPRN_EPCR       0x133   /* Embedded Processor Control Register */
 #define SPRN_DBCR2      0x136   /* Debug Control Register 2 */
 #define SPRN_IAC3       0x13A   /* Instruction Address Compare 3 */
 #define SPRN_IAC4       0x13B   /* Instruction Address Compare 4 */
 #define SPRN_DVC1       0x13E   /* Data Value Compare Register 1 */
 #define SPRN_DVC2       0x13F   /* Data Value Compare Register 2 */
+#define SPRN_MAS8       0x155   /* MMU Assist Register 8 */
+#define SPRN_TLB0PS     0x158   /* TLB 0 Page Size Register */
+#define SPRN_MAS5_MAS6  0x15c   /* MMU Assist Register 5 || 6 */
+#define SPRN_MAS8_MAS1  0x15d   /* MMU Assist Register 8 || 1 */
+#define SPRN_MAS7_MAS3  0x174   /* MMU Assist Register 7 || 3 */
+#define SPRN_MAS0_MAS1  0x175   /* MMU Assist Register 0 || 1 */
 #define SPRN_IVOR0      0x190   /* Interrupt Vector Offset Register 0 */
 #define SPRN_IVOR1      0x191   /* Interrupt Vector Offset Register 1 */
 #define SPRN_IVOR2      0x192   /* Interrupt Vector Offset Register 2 */
@@ -425,6 +440,27 @@
 #define SGR_NORMAL      0               /* Speculative fetching allowed. */
 #define SGR_GUARDED     1               /* Speculative fetching disallowed. */
 
+/* Bit definitions for EPCR */
+#define SPRN_EPCR_EXTGS         0x80000000      /* External Input interrupt
+                                                 * directed to Guest state */
+#define SPRN_EPCR_DTLBGS        0x40000000      /* Data TLB Error interrupt
+                                                 * directed to guest state */
+#define SPRN_EPCR_ITLBGS        0x20000000      /* Instr. TLB error interrupt
+                                                 * directed to guest state */
+#define SPRN_EPCR_DSIGS         0x10000000      /* Data Storage interrupt
+                                                 * directed to guest state */
+#define SPRN_EPCR_ISIGS         0x08000000      /* Instr. Storage interrupt
+                                                 * directed to guest state */
+#define SPRN_EPCR_DUVD          0x04000000      /* Disable Hypervisor Debug */
+#define SPRN_EPCR_ICM           0x02000000      /* Interrupt computation mode
+                                                 * (copied to MSR:CM on intr) */
+#define SPRN_EPCR_GICM          0x01000000      /* Guest Interrupt Comp. mode */
+#define SPRN_EPCR_DGTMI         0x00800000      /* Disable TLB Guest Management
+                                                 * instructions */
+#define SPRN_EPCR_DMIUH         0x00400000      /* Disable MAS Interrupt updates
+                                                 * for hypervisor */
+
+
 /*
  * The IBM-403 is an even more odd special case, as it is much
  * older than the IBM-405 series.  We put these down here incase someone
diff --git a/arch/powerpc/include/asm/smp.h b/arch/powerpc/include/asm/smp.h
index c25f73d1d842..c0d3b8af9319 100644
--- a/arch/powerpc/include/asm/smp.h
+++ b/arch/powerpc/include/asm/smp.h
@@ -148,6 +148,16 @@ extern struct smp_ops_t *smp_ops;
 extern void arch_send_call_function_single_ipi(int cpu);
 extern void arch_send_call_function_ipi(cpumask_t mask);
 
+/* Definitions relative to the secondary CPU spin loop
+ * and entry point. Not all of them exist on both 32 and
+ * 64-bit but defining them all here doesn't harm
+ */
+extern void generic_secondary_smp_init(void);
+extern void generic_secondary_thread_init(void);
+extern unsigned long __secondary_hold_spinloop;
+extern unsigned long __secondary_hold_acknowledge;
+extern char __secondary_hold;
+
 #endif /* __ASSEMBLY__ */
 
 #endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/systbl.h b/arch/powerpc/include/asm/systbl.h
index 370600ca2765..ed24bd92fe49 100644
--- a/arch/powerpc/include/asm/systbl.h
+++ b/arch/powerpc/include/asm/systbl.h
@@ -95,8 +95,8 @@ SYSCALL(reboot)
 SYSX(sys_ni_syscall,compat_sys_old_readdir,sys_old_readdir)
 SYSCALL_SPU(mmap)
 SYSCALL_SPU(munmap)
-SYSCALL_SPU(truncate)
-SYSCALL_SPU(ftruncate)
+COMPAT_SYS_SPU(truncate)
+COMPAT_SYS_SPU(ftruncate)
 SYSCALL_SPU(fchmod)
 SYSCALL_SPU(fchown)
 COMPAT_SYS_SPU(getpriority)
diff --git a/arch/powerpc/include/asm/tlb.h b/arch/powerpc/include/asm/tlb.h
index e20ff7541f36..e2b428b0f7ba 100644
--- a/arch/powerpc/include/asm/tlb.h
+++ b/arch/powerpc/include/asm/tlb.h
@@ -25,57 +25,25 @@
 
 #include <linux/pagemap.h>
 
-struct mmu_gather;
-
 #define tlb_start_vma(tlb, vma) do { } while (0)
 #define tlb_end_vma(tlb, vma)   do { } while (0)
 
-#if !defined(CONFIG_PPC_STD_MMU)
-
-#define tlb_flush(tlb)                  flush_tlb_mm((tlb)->mm)
-
-#elif defined(__powerpc64__)
-
-extern void pte_free_finish(void);
-
-static inline void tlb_flush(struct mmu_gather *tlb)
-{
-        struct ppc64_tlb_batch *tlbbatch = &__get_cpu_var(ppc64_tlb_batch);
-
-        /* If there's a TLB batch pending, then we must flush it because the
-         * pages are going to be freed and we really don't want to have a CPU
-         * access a freed page because it has a stale TLB
-         */
-        if (tlbbatch->index)
-                __flush_tlb_pending(tlbbatch);
-
-        pte_free_finish();
-}
-
-#else
-
 extern void tlb_flush(struct mmu_gather *tlb);
 
-#endif
-
 /* Get the generic bits... */
 #include <asm-generic/tlb.h>
 
-#if !defined(CONFIG_PPC_STD_MMU) || defined(__powerpc64__)
-
-#define __tlb_remove_tlb_entry(tlb, pte, address) do { } while (0)
-
-#else
 extern void flush_hash_entry(struct mm_struct *mm, pte_t *ptep,
                              unsigned long address);
 
 static inline void __tlb_remove_tlb_entry(struct mmu_gather *tlb, pte_t *ptep,
-                                        unsigned long address)
+                                          unsigned long address)
 {
+#ifdef CONFIG_PPC_STD_MMU_32
         if (pte_val(*ptep) & _PAGE_HASHPTE)
                 flush_hash_entry(tlb->mm, ptep, address);
+#endif
 }
 
-#endif
 #endif /* __KERNEL__ */
 #endif /* __ASM_POWERPC_TLB_H */
diff --git a/arch/powerpc/include/asm/tlbflush.h b/arch/powerpc/include/asm/tlbflush.h
index abbe3419d1dd..d50a380b2b6f 100644
--- a/arch/powerpc/include/asm/tlbflush.h
+++ b/arch/powerpc/include/asm/tlbflush.h
@@ -6,7 +6,7 @@
  *
  *  - flush_tlb_mm(mm) flushes the specified mm context TLB's
  *  - flush_tlb_page(vma, vmaddr) flushes one page
- *  - local_flush_tlb_mm(mm) flushes the specified mm context on
+ *  - local_flush_tlb_mm(mm, full) flushes the specified mm context on
  *                           the local processor
  *  - local_flush_tlb_page(vma, vmaddr) flushes one page on the local processor
  *  - flush_tlb_page_nohash(vma, vmaddr) flushes one page if SW loaded TLB
@@ -29,7 +29,8 @@
  * specific tlbie's
  */
 
-#include <linux/mm.h>
+struct vm_area_struct;
+struct mm_struct;
 
 #define MMU_NO_CONTEXT          ((unsigned int)-1)
 
@@ -40,12 +41,18 @@ extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
 extern void local_flush_tlb_mm(struct mm_struct *mm);
 extern void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr);
 
+extern void __local_flush_tlb_page(struct mm_struct *mm, unsigned long vmaddr,
+                                   int tsize, int ind);
+
 #ifdef CONFIG_SMP
 extern void flush_tlb_mm(struct mm_struct *mm);
 extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr);
+extern void __flush_tlb_page(struct mm_struct *mm, unsigned long vmaddr,
+                             int tsize, int ind);
 #else
 #define flush_tlb_mm(mm)                local_flush_tlb_mm(mm)
 #define flush_tlb_page(vma,addr)        local_flush_tlb_page(vma,addr)
+#define __flush_tlb_page(mm,addr,p,i)   __local_flush_tlb_page(mm,addr,p,i)
 #endif
 #define flush_tlb_page_nohash(vma,addr) flush_tlb_page(vma,addr)
 
diff --git a/arch/powerpc/include/asm/vdso.h b/arch/powerpc/include/asm/vdso.h
index 26fc449bd989..dc0419b66f17 100644
--- a/arch/powerpc/include/asm/vdso.h
+++ b/arch/powerpc/include/asm/vdso.h
@@ -7,9 +7,8 @@
 #define VDSO32_LBASE    0x100000
 #define VDSO64_LBASE    0x100000
 
-/* Default map addresses */
+/* Default map addresses for 32bit vDSO */
 #define VDSO32_MBASE    VDSO32_LBASE
-#define VDSO64_MBASE    VDSO64_LBASE
 
 #define VDSO_VERSION_STRING     LINUX_2.6.15
 
diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile
index 9619285f64e8..7c83edbc2155 100644
--- a/arch/powerpc/kernel/Makefile
+++ b/arch/powerpc/kernel/Makefile
@@ -33,10 +33,10 @@ obj-y				:= cputable.o ptrace.o syscalls.o \
 obj-y                           += vdso32/
 obj-$(CONFIG_PPC64)             += setup_64.o sys_ppc32.o \
                                    signal_64.o ptrace32.o \
-                                   paca.o cpu_setup_ppc970.o \
-                                   cpu_setup_pa6t.o \
-                                   firmware.o nvram_64.o
+                                   paca.o nvram_64.o firmware.o
+obj-$(CONFIG_PPC_BOOK3S_64)     += cpu_setup_ppc970.o cpu_setup_pa6t.o
 obj64-$(CONFIG_RELOCATABLE)     += reloc_64.o
+obj-$(CONFIG_PPC_BOOK3E_64)     += exceptions-64e.o
 obj-$(CONFIG_PPC64)             += vdso64/
 obj-$(CONFIG_ALTIVEC)           += vecemu.o
 obj-$(CONFIG_PPC_970_NAP)       += idle_power4.o
@@ -63,8 +63,8 @@ obj-$(CONFIG_MODULES)		+= module.o module_$(CONFIG_WORD_SIZE).o
 obj-$(CONFIG_44x)               += cpu_setup_44x.o
 obj-$(CONFIG_FSL_BOOKE)         += cpu_setup_fsl_booke.o dbell.o
 
-extra-$(CONFIG_PPC_STD_MMU)     := head_32.o
-extra-$(CONFIG_PPC64)           := head_64.o
+extra-y                         := head_$(CONFIG_WORD_SIZE).o
+extra-$(CONFIG_PPC_BOOK3E_32)   := head_new_booke.o
 extra-$(CONFIG_40x)             := head_40x.o
 extra-$(CONFIG_44x)             := head_44x.o
 extra-$(CONFIG_FSL_BOOKE)       := head_fsl_booke.o
@@ -115,6 +115,13 @@ ifneq ($(CONFIG_XMON)$(CONFIG_KEXEC),)
 obj-y                           += ppc_save_regs.o
 endif
 
+# Disable GCOV in odd or sensitive code
+GCOV_PROFILE_prom_init.o := n
+GCOV_PROFILE_ftrace.o := n
+GCOV_PROFILE_machine_kexec_64.o := n
+GCOV_PROFILE_machine_kexec_32.o := n
+GCOV_PROFILE_kprobes.o := n
+
 extra-$(CONFIG_PPC_FPU)         += fpu.o
 extra-$(CONFIG_ALTIVEC)         += vector.o
 extra-$(CONFIG_PPC64)           += entry_64.o
diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c
index 197b15646eeb..f0df285f0f87 100644
--- a/arch/powerpc/kernel/asm-offsets.c
+++ b/arch/powerpc/kernel/asm-offsets.c
@@ -52,9 +52,11 @@
 #include <linux/kvm_host.h>
 #endif
 
+#ifdef CONFIG_PPC32
 #if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
 #include "head_booke.h"
 #endif
+#endif
 
 #if defined(CONFIG_FSL_BOOKE)
 #include "../mm/mmu_decl.h"
@@ -140,6 +142,20 @@ int main(void)
                                             context.high_slices_psize));
         DEFINE(MMUPSIZEDEFSIZE, sizeof(struct mmu_psize_def));
 #endif /* CONFIG_PPC_MM_SLICES */
+
+#ifdef CONFIG_PPC_BOOK3E
+        DEFINE(PACAPGD, offsetof(struct paca_struct, pgd));
+        DEFINE(PACA_KERNELPGD, offsetof(struct paca_struct, kernel_pgd));
+        DEFINE(PACA_EXGEN, offsetof(struct paca_struct, exgen));
+        DEFINE(PACA_EXTLB, offsetof(struct paca_struct, extlb));
+        DEFINE(PACA_EXMC, offsetof(struct paca_struct, exmc));
+        DEFINE(PACA_EXCRIT, offsetof(struct paca_struct, excrit));
+        DEFINE(PACA_EXDBG, offsetof(struct paca_struct, exdbg));
+        DEFINE(PACA_MC_STACK, offsetof(struct paca_struct, mc_kstack));
+        DEFINE(PACA_CRIT_STACK, offsetof(struct paca_struct, crit_kstack));
+        DEFINE(PACA_DBG_STACK, offsetof(struct paca_struct, dbg_kstack));
+#endif /* CONFIG_PPC_BOOK3E */
+
 #ifdef CONFIG_PPC_STD_MMU_64
         DEFINE(PACASTABREAL, offsetof(struct paca_struct, stab_real));
         DEFINE(PACASTABVIRT, offsetof(struct paca_struct, stab_addr));
@@ -262,6 +278,7 @@ int main(void)
         DEFINE(_SRR1, STACK_FRAME_OVERHEAD+sizeof(struct pt_regs)+8);
 #endif /* CONFIG_PPC64 */
 
+#if defined(CONFIG_PPC32)
 #if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
         DEFINE(EXC_LVL_SIZE, STACK_EXC_LVL_FRAME_SIZE);
         DEFINE(MAS0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas0));
@@ -280,7 +297,7 @@ int main(void)
         DEFINE(_DSRR1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, dsrr1));
         DEFINE(SAVED_KSP_LIMIT, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, saved_ksp_limit));
 #endif
-
+#endif
         DEFINE(CLONE_VM, CLONE_VM);
         DEFINE(CLONE_UNTRACED, CLONE_UNTRACED);
 
diff --git a/arch/powerpc/kernel/cpu_setup_6xx.S b/arch/powerpc/kernel/cpu_setup_6xx.S
index 1e9949e68856..55cba4a8a959 100644
--- a/arch/powerpc/kernel/cpu_setup_6xx.S
+++ b/arch/powerpc/kernel/cpu_setup_6xx.S
@@ -21,7 +21,7 @@ _GLOBAL(__setup_cpu_603)
         mflr    r4
 BEGIN_MMU_FTR_SECTION
         li      r10,0
-        mtspr   SPRN_SPRG4,r10          /* init SW LRU tracking */
+        mtspr   SPRN_SPRG_603_LRU,r10           /* init SW LRU tracking */
 END_MMU_FTR_SECTION_IFSET(MMU_FTR_NEED_DTLB_SW_LRU)
 BEGIN_FTR_SECTION
         bl      __init_fpu_registers
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index 4a24a2fc4574..9f38ecb17859 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -93,7 +93,7 @@ extern void __restore_cpu_power7(void);
                                  PPC_FEATURE_BOOKE)
 
 static struct cpu_spec __initdata cpu_specs[] = {
-#ifdef CONFIG_PPC64
+#ifdef CONFIG_PPC_BOOK3S_64
         {       /* Power3 */
                 .pvr_mask               = 0xffff0000,
                 .pvr_value              = 0x00400000,
@@ -508,7 +508,30 @@ static struct cpu_spec __initdata cpu_specs[] = {
                 .machine_check          = machine_check_generic,
                 .platform               = "power4",
         }
-#endif  /* CONFIG_PPC64 */
+#endif  /* CONFIG_PPC_BOOK3S_64 */
+#ifdef CONFIG_PPC_BOOK3E_64
+        {       /* This is a default entry to get going, to be replaced by
+                 * a real one at some stage
+                 */
+#define CPU_FTRS_BASE_BOOK3E    (CPU_FTR_USE_TB | \
+            CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_SMT | \
+            CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
+                .pvr_mask               = 0x00000000,
+                .pvr_value              = 0x00000000,
+                .cpu_name               = "Book3E",
+                .cpu_features           = CPU_FTRS_BASE_BOOK3E,
+                .cpu_user_features      = COMMON_USER_PPC64,
+                .mmu_features           = MMU_FTR_TYPE_3E | MMU_FTR_USE_TLBILX |
+                                          MMU_FTR_USE_TLBIVAX_BCAST |
+                                          MMU_FTR_LOCK_BCAST_INVAL,
+                .icache_bsize           = 64,
+                .dcache_bsize           = 64,
+                .num_pmcs               = 0,
+                .machine_check          = machine_check_generic,
+                .platform               = "power6",
+        },
+#endif
+
 #ifdef CONFIG_PPC32
 #if CLASSIC_PPC
         {       /* 601 */
@@ -1630,7 +1653,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
                 .platform               = "ppc440",
         },
         { /* 460EX */
-                .pvr_mask               = 0xffff0002,
+                .pvr_mask               = 0xffff0006,
                 .pvr_value              = 0x13020002,
                 .cpu_name               = "460EX",
                 .cpu_features           = CPU_FTRS_440x6,
@@ -1642,8 +1665,21 @@ static struct cpu_spec __initdata cpu_specs[] = {
                 .machine_check          = machine_check_440A,
                 .platform               = "ppc440",
         },
+        { /* 460EX Rev B */
+                .pvr_mask               = 0xffff0007,
+                .pvr_value              = 0x13020004,
+                .cpu_name               = "460EX Rev. B",
+                .cpu_features           = CPU_FTRS_440x6,
+                .cpu_user_features      = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
+                .mmu_features           = MMU_FTR_TYPE_44x,
+                .icache_bsize           = 32,
+                .dcache_bsize           = 32,
+                .cpu_setup              = __setup_cpu_460ex,
+                .machine_check          = machine_check_440A,
+                .platform               = "ppc440",
+        },
         { /* 460GT */
-                .pvr_mask               = 0xffff0002,
+                .pvr_mask               = 0xffff0006,
                 .pvr_value              = 0x13020000,
                 .cpu_name               = "460GT",
                 .cpu_features           = CPU_FTRS_440x6,
@@ -1655,6 +1691,19 @@ static struct cpu_spec __initdata cpu_specs[] = {
                 .machine_check          = machine_check_440A,
                 .platform               = "ppc440",
         },
+        { /* 460GT Rev B */
+                .pvr_mask               = 0xffff0007,
+                .pvr_value              = 0x13020005,
+                .cpu_name               = "460GT Rev. B",
+                .cpu_features           = CPU_FTRS_440x6,
+                .cpu_user_features      = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
+                .mmu_features           = MMU_FTR_TYPE_44x,
+                .icache_bsize           = 32,
+                .dcache_bsize           = 32,
+                .cpu_setup              = __setup_cpu_460gt,
+                .machine_check          = machine_check_440A,
+                .platform               = "ppc440",
+        },
         { /* 460SX */
                 .pvr_mask               = 0xffffff00,
                 .pvr_value              = 0x13541800,
diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S
index 3cadba60a4b6..1175a8539e6c 100644
--- a/arch/powerpc/kernel/entry_32.S
+++ b/arch/powerpc/kernel/entry_32.S
@@ -88,7 +88,7 @@ crit_transfer_to_handler:
         mfspr   r0,SPRN_SRR1
         stw     r0,_SRR1(r11)
 
-        mfspr   r8,SPRN_SPRG3
+        mfspr   r8,SPRN_SPRG_THREAD
         lwz     r0,KSP_LIMIT(r8)
         stw     r0,SAVED_KSP_LIMIT(r11)
         rlwimi  r0,r1,0,0,(31-THREAD_SHIFT)
@@ -108,7 +108,7 @@ crit_transfer_to_handler:
         mfspr   r0,SPRN_SRR1
         stw     r0,crit_srr1@l(0)
 
-        mfspr   r8,SPRN_SPRG3
+        mfspr   r8,SPRN_SPRG_THREAD
         lwz     r0,KSP_LIMIT(r8)
         stw     r0,saved_ksp_limit@l(0)
         rlwimi  r0,r1,0,0,(31-THREAD_SHIFT)
@@ -138,7 +138,7 @@ transfer_to_handler:
         mfspr   r2,SPRN_XER
         stw     r12,_CTR(r11)
         stw     r2,_XER(r11)
-        mfspr   r12,SPRN_SPRG3
+        mfspr   r12,SPRN_SPRG_THREAD
         addi    r2,r12,-THREAD
         tovirt(r2,r2)                   /* set r2 to current */
         beq     2f                      /* if from user, fix up THREAD.regs */
@@ -680,7 +680,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_SPE)
 
         tophys(r0,r4)
         CLR_TOP32(r0)
-        mtspr   SPRN_SPRG3,r0   /* Update current THREAD phys addr */
+        mtspr   SPRN_SPRG_THREAD,r0     /* Update current THREAD phys addr */
         lwz     r1,KSP(r4)      /* Load new stack pointer */
 
         /* save the old current 'last' for return value */
@@ -1057,7 +1057,7 @@ exc_exit_restart_end:
 #ifdef CONFIG_40x
         .globl  ret_from_crit_exc
 ret_from_crit_exc:
-        mfspr   r9,SPRN_SPRG3
+        mfspr   r9,SPRN_SPRG_THREAD
         lis     r10,saved_ksp_limit@ha;
         lwz     r10,saved_ksp_limit@l(r10);
         tovirt(r9,r9);
@@ -1074,7 +1074,7 @@ ret_from_crit_exc:
 #ifdef CONFIG_BOOKE
         .globl  ret_from_crit_exc
 ret_from_crit_exc:
-        mfspr   r9,SPRN_SPRG3
+        mfspr   r9,SPRN_SPRG_THREAD
         lwz     r10,SAVED_KSP_LIMIT(r1)
         stw     r10,KSP_LIMIT(r9)
         RESTORE_xSRR(SRR0,SRR1);
@@ -1083,7 +1083,7 @@ ret_from_crit_exc:
 
         .globl  ret_from_debug_exc
 ret_from_debug_exc:
-        mfspr   r9,SPRN_SPRG3
+        mfspr   r9,SPRN_SPRG_THREAD
         lwz     r10,SAVED_KSP_LIMIT(r1)
         stw     r10,KSP_LIMIT(r9)
         lwz     r9,THREAD_INFO-THREAD(r9)
@@ -1097,7 +1097,7 @@ ret_from_debug_exc:
 
         .globl  ret_from_mcheck_exc
 ret_from_mcheck_exc:
-        mfspr   r9,SPRN_SPRG3
+        mfspr   r9,SPRN_SPRG_THREAD
         lwz     r10,SAVED_KSP_LIMIT(r1)
         stw     r10,KSP_LIMIT(r9)
         RESTORE_xSRR(SRR0,SRR1);
@@ -1255,7 +1255,7 @@ _GLOBAL(enter_rtas)
         MTMSRD(r0)              /* don't get trashed */
         li      r9,MSR_KERNEL & ~(MSR_IR|MSR_DR)
         mtlr    r6
-        mtspr   SPRN_SPRG2,r7
+        mtspr   SPRN_SPRG_RTAS,r7
         mtspr   SPRN_SRR0,r8
         mtspr   SPRN_SRR1,r9
         RFI
@@ -1265,7 +1265,7 @@ _GLOBAL(enter_rtas)
         FIX_SRR1(r9,r0)
         addi    r1,r1,INT_FRAME_SIZE
         li      r0,0
-        mtspr   SPRN_SPRG2,r0
+        mtspr   SPRN_SPRG_RTAS,r0
         mtspr   SPRN_SRR0,r8
         mtspr   SPRN_SRR1,r9
         RFI                     /* return to caller */
diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S
index 43e073477c34..66bcda34a6bb 100644
--- a/arch/powerpc/kernel/entry_64.S
+++ b/arch/powerpc/kernel/entry_64.S
@@ -120,9 +120,15 @@ BEGIN_FW_FTR_SECTION
 2:
 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
 #endif /* CONFIG_PPC_ISERIES */
+
+        /* Hard enable interrupts */
+#ifdef CONFIG_PPC_BOOK3E
+        wrteei  1
+#else
         mfmsr   r11
         ori     r11,r11,MSR_EE
         mtmsrd  r11,1
+#endif /* CONFIG_PPC_BOOK3E */
 
 #ifdef SHOW_SYSCALLS
         bl      .do_show_syscall
@@ -168,15 +174,25 @@ syscall_exit:
 #endif
         clrrdi  r12,r1,THREAD_SHIFT
 
-        /* disable interrupts so current_thread_info()->flags can't change,
-           and so that we don't get interrupted after loading SRR0/1. */
         ld      r8,_MSR(r1)
+#ifdef CONFIG_PPC_BOOK3S
+        /* No MSR:RI on BookE */
         andi.   r10,r8,MSR_RI
         beq-    unrecov_restore
+#endif
+
+        /* Disable interrupts so current_thread_info()->flags can't change,
+         * and so that we don't get interrupted after loading SRR0/1.
+         */
+#ifdef CONFIG_PPC_BOOK3E
+        wrteei  0
+#else
         mfmsr   r10
         rldicl  r10,r10,48,1
         rotldi  r10,r10,16
         mtmsrd  r10,1
+#endif /* CONFIG_PPC_BOOK3E */
+
         ld      r9,TI_FLAGS(r12)
         li      r11,-_LAST_ERRNO
         andi.   r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP|_TIF_USER_WORK_MASK|_TIF_PERSYSCALL_MASK)
@@ -194,9 +210,13 @@ syscall_error_cont:
          * userspace and we take an exception after restoring r13,
          * we end up corrupting the userspace r13 value.
          */
+#ifdef CONFIG_PPC_BOOK3S
+        /* No MSR:RI on BookE */
         li      r12,MSR_RI
         andc    r11,r10,r12
         mtmsrd  r11,1                   /* clear MSR.RI */
+#endif /* CONFIG_PPC_BOOK3S */
+
         beq-    1f
         ACCOUNT_CPU_USER_EXIT(r11, r12)
         ld      r13,GPR13(r1)   /* only restore r13 if returning to usermode */
@@ -206,7 +226,7 @@ syscall_error_cont:
         mtcr    r5
         mtspr   SPRN_SRR0,r7
         mtspr   SPRN_SRR1,r8
-        rfid
+        RFI
         b       .       /* prevent speculative execution */
 
 syscall_error:  
@@ -276,9 +296,13 @@ syscall_exit_work:
         beq     .ret_from_except_lite
 
         /* Re-enable interrupts */
+#ifdef CONFIG_PPC_BOOK3E
+        wrteei  1
+#else
         mfmsr   r10
         ori     r10,r10,MSR_EE
         mtmsrd  r10,1
+#endif /* CONFIG_PPC_BOOK3E */
 
         bl      .save_nvgprs
         addi    r3,r1,STACK_FRAME_OVERHEAD
@@ -380,7 +404,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
         and.    r0,r0,r22
         beq+    1f
         andc    r22,r22,r0
-        mtmsrd  r22
+        MTMSRD(r22)
         isync
 1:      std     r20,_NIP(r1)
         mfcr    r23
@@ -399,6 +423,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
         std     r6,PACACURRENT(r13)     /* Set new 'current' */
 
         ld      r8,KSP(r4)      /* new stack pointer */
+#ifdef CONFIG_PPC_BOOK3S
 BEGIN_FTR_SECTION
   BEGIN_FTR_SECTION_NESTED(95)
         clrrdi  r6,r8,28        /* get its ESID */
@@ -445,8 +470,9 @@ END_FTR_SECTION_IFSET(CPU_FTR_1T_SEGMENT)
         slbie   r6              /* Workaround POWER5 < DD2.1 issue */
         slbmte  r7,r0
         isync
-
 2:
+#endif /* !CONFIG_PPC_BOOK3S */
+
         clrrdi  r7,r8,THREAD_SHIFT      /* base of new stack */
         /* Note: this uses SWITCH_FRAME_SIZE rather than INT_FRAME_SIZE
            because we don't need to leave the 288-byte ABI gap at the
@@ -490,10 +516,14 @@ _GLOBAL(ret_from_except_lite)
          * can't change between when we test it and when we return
          * from the interrupt.
          */
+#ifdef CONFIG_PPC_BOOK3E
+        wrteei  0
+#else
         mfmsr   r10             /* Get current interrupt state */
         rldicl  r9,r10,48,1     /* clear MSR_EE */
         rotldi  r9,r9,16
         mtmsrd  r9,1            /* Update machine state */
+#endif /* CONFIG_PPC_BOOK3E */
 
 #ifdef CONFIG_PREEMPT
         clrrdi  r9,r1,THREAD_SHIFT      /* current_thread_info() */
@@ -540,6 +570,9 @@ ALT_FW_FTR_SECTION_END_IFCLR(FW_FEATURE_ISERIES)
         rldicl  r4,r3,49,63             /* r0 = (r3 >> 15) & 1 */
         stb     r4,PACAHARDIRQEN(r13)
 
+#ifdef CONFIG_PPC_BOOK3E
+        b       .exception_return_book3e
+#else
         ld      r4,_CTR(r1)
         ld      r0,_LINK(r1)
         mtctr   r4
@@ -588,6 +621,8 @@ ALT_FW_FTR_SECTION_END_IFCLR(FW_FEATURE_ISERIES)
         rfid
         b       .       /* prevent speculative execution */
 
+#endif /* CONFIG_PPC_BOOK3E */
+
 iseries_check_pending_irqs:
 #ifdef CONFIG_PPC_ISERIES
         ld      r5,SOFTE(r1)
@@ -638,6 +673,11 @@ do_work:
         li      r0,1
         stb     r0,PACASOFTIRQEN(r13)
         stb     r0,PACAHARDIRQEN(r13)
+#ifdef CONFIG_PPC_BOOK3E
+        wrteei  1
+        bl      .preempt_schedule
+        wrteei  0
+#else
         ori     r10,r10,MSR_EE
         mtmsrd  r10,1           /* reenable interrupts */
         bl      .preempt_schedule
@@ -646,6 +686,7 @@ do_work:
         rldicl  r10,r10,48,1    /* disable interrupts again */
         rotldi  r10,r10,16
         mtmsrd  r10,1
+#endif /* CONFIG_PPC_BOOK3E */
         ld      r4,TI_FLAGS(r9)
         andi.   r0,r4,_TIF_NEED_RESCHED
         bne     1b
@@ -654,8 +695,12 @@ do_work:
 user_work:
 #endif
         /* Enable interrupts */
+#ifdef CONFIG_PPC_BOOK3E
+        wrteei  1
+#else
         ori     r10,r10,MSR_EE
         mtmsrd  r10,1
+#endif /* CONFIG_PPC_BOOK3E */
 
         andi.   r0,r4,_TIF_NEED_RESCHED
         beq     1f
@@ -762,7 +807,7 @@ _GLOBAL(enter_rtas)
 
 _STATIC(rtas_return_loc)
         /* relocation is off at this point */
-        mfspr   r4,SPRN_SPRG3           /* Get PACA */
+        mfspr   r4,SPRN_SPRG_PACA       /* Get PACA */
         clrldi  r4,r4,2                 /* convert to realmode address */
 
         bcl     20,31,$+4
@@ -793,7 +838,7 @@ _STATIC(rtas_restore_regs)
         REST_8GPRS(14, r1)              /* Restore the non-volatiles */
         REST_10GPRS(22, r1)             /* ditto */
 
-        mfspr   r13,SPRN_SPRG3
+        mfspr   r13,SPRN_SPRG_PACA
 
         ld      r4,_CCR(r1)
         mtcr    r4
@@ -823,33 +868,24 @@ _GLOBAL(enter_prom)
          * of all registers that it saves.  We therefore save those registers
          * PROM might touch to the stack.  (r0, r3-r13 are caller saved)
          */
-        SAVE_8GPRS(2, r1)
+        SAVE_GPR(2, r1)
         SAVE_GPR(13, r1)
         SAVE_8GPRS(14, r1)
         SAVE_10GPRS(22, r1)
-        mfcr    r4
-        std     r4,_CCR(r1)
-        mfctr   r5
-        std     r5,_CTR(r1)
-        mfspr   r6,SPRN_XER
-        std     r6,_XER(r1)
-        mfdar   r7
-        std     r7,_DAR(r1)
-        mfdsisr r8
-        std     r8,_DSISR(r1)
-        mfsrr0  r9
-        std     r9,_SRR0(r1)
-        mfsrr1  r10
-        std     r10,_SRR1(r1)
+        mfcr    r10
         mfmsr   r11
+        std     r10,_CCR(r1)
         std     r11,_MSR(r1)
 
         /* Get the PROM entrypoint */
-        ld      r0,GPR4(r1)
-        mtlr    r0
+        mtlr    r4
 
         /* Switch MSR to 32 bits mode
          */
+#ifdef CONFIG_PPC_BOOK3E
+        rlwinm  r11,r11,0,1,31
+        mtmsr   r11
+#else /* CONFIG_PPC_BOOK3E */
         mfmsr   r11
         li      r12,1
         rldicr  r12,r12,MSR_SF_LG,(63-MSR_SF_LG)
@@ -858,10 +894,10 @@ _GLOBAL(enter_prom)
         rldicr  r12,r12,MSR_ISF_LG,(63-MSR_ISF_LG)
         andc    r11,r11,r12
         mtmsrd  r11
+#endif /* CONFIG_PPC_BOOK3E */
         isync
 
-        /* Restore arguments & enter PROM here... */
-        ld      r3,GPR3(r1)
+        /* Enter PROM here... */
         blrl
 
         /* Just make sure that r1 top 32 bits didn't get
@@ -871,7 +907,7 @@ _GLOBAL(enter_prom)
 
         /* Restore the MSR (back to 64 bits) */
         ld      r0,_MSR(r1)
-        mtmsrd  r0
+        MTMSRD(r0)
         isync
 
         /* Restore other registers */
@@ -881,18 +917,6 @@ _GLOBAL(enter_prom)
         REST_10GPRS(22, r1)
         ld      r4,_CCR(r1)
         mtcr    r4
-        ld      r5,_CTR(r1)
-        mtctr   r5
-        ld      r6,_XER(r1)
-        mtspr   SPRN_XER,r6
-        ld      r7,_DAR(r1)
-        mtdar   r7
-        ld      r8,_DSISR(r1)
-        mtdsisr r8
-        ld      r9,_SRR0(r1)
-        mtsrr0  r9
-        ld      r10,_SRR1(r1)
-        mtsrr1  r10
         
         addi    r1,r1,PROM_FRAME_SIZE
         ld      r0,16(r1)
diff --git a/arch/powerpc/kernel/exceptions-64e.S b/arch/powerpc/kernel/exceptions-64e.S
new file mode 100644
index 000000000000..695d4847d228
--- /dev/null
+++ b/arch/powerpc/kernel/exceptions-64e.S
@@ -0,0 +1,784 @@
+/*
+ *  Boot code and exception vectors for Book3E processors
+ *
+ *  Copyright (C) 2007 Ben. Herrenschmidt (benh@kernel.crashing.org), IBM Corp.
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  as published by the Free Software Foundation; either version
+ *  2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/threads.h>
+#include <asm/reg.h>
+#include <asm/page.h>
+#include <asm/ppc_asm.h>
+#include <asm/asm-offsets.h>
+#include <asm/cputable.h>
+#include <asm/setup.h>
+#include <asm/thread_info.h>
+#include <asm/reg.h>
+#include <asm/exception-64e.h>
+#include <asm/bug.h>
+#include <asm/irqflags.h>
+#include <asm/ptrace.h>
+#include <asm/ppc-opcode.h>
+#include <asm/mmu.h>
+
+/* XXX This will ultimately add space for a special exception save
+ *     structure used to save things like SRR0/SRR1, SPRGs, MAS, etc...
+ *     when taking special interrupts. For now we don't support that,
+ *     special interrupts from within a non-standard level will probably
+ *     blow you up
+ */
+#define SPECIAL_EXC_FRAME_SIZE  INT_FRAME_SIZE
+
+/* Exception prolog code for all exceptions */
+#define EXCEPTION_PROLOG(n, type, addition)                                 \
+        mtspr   SPRN_SPRG_##type##_SCRATCH,r13; /* get spare registers */   \
+        mfspr   r13,SPRN_SPRG_PACA;     /* get PACA */                      \
+        std     r10,PACA_EX##type+EX_R10(r13);                              \
+        std     r11,PACA_EX##type+EX_R11(r13);                              \
+        mfcr    r10;                    /* save CR */                       \
+        addition;                       /* additional code for that exc. */ \
+        std     r1,PACA_EX##type+EX_R1(r13); /* save old r1 in the PACA */  \
+        stw     r10,PACA_EX##type+EX_CR(r13); /* save old CR in the PACA */ \
+        mfspr   r11,SPRN_##type##_SRR1;/* what are we coming from */        \
+        type##_SET_KSTACK;              /* get special stack if necessary */\
+        andi.   r10,r11,MSR_PR;         /* save stack pointer */            \
+        beq     1f;                     /* branch around if supervisor */   \
+        ld      r1,PACAKSAVE(r13);      /* get kernel stack coming from usr */\
+1:      cmpdi   cr1,r1,0;               /* check if SP makes sense */       \
+        bge-    cr1,exc_##n##_bad_stack;/* bad stack (TODO: out of line) */ \
+        mfspr   r10,SPRN_##type##_SRR0; /* read SRR0 before touching stack */
+
+/* Exception type-specific macros */
+#define GEN_SET_KSTACK                                                      \
+        subi    r1,r1,INT_FRAME_SIZE;   /* alloc frame on kernel stack */
+#define SPRN_GEN_SRR0   SPRN_SRR0
+#define SPRN_GEN_SRR1   SPRN_SRR1
+
+#define CRIT_SET_KSTACK                                                     \
+        ld      r1,PACA_CRIT_STACK(r13);                                    \
+        subi    r1,r1,SPECIAL_EXC_FRAME_SIZE;
+#define SPRN_CRIT_SRR0  SPRN_CSRR0
+#define SPRN_CRIT_SRR1  SPRN_CSRR1
+
+#define DBG_SET_KSTACK                                                      \
+        ld      r1,PACA_DBG_STACK(r13);                                     \
+        subi    r1,r1,SPECIAL_EXC_FRAME_SIZE;
+#define SPRN_DBG_SRR0   SPRN_DSRR0
+#define SPRN_DBG_SRR1   SPRN_DSRR1
+
+#define MC_SET_KSTACK                                                       \
+        ld      r1,PACA_MC_STACK(r13);                                      \
+        subi    r1,r1,SPECIAL_EXC_FRAME_SIZE;
+#define SPRN_MC_SRR0    SPRN_MCSRR0
+#define SPRN_MC_SRR1    SPRN_MCSRR1
+
+#define NORMAL_EXCEPTION_PROLOG(n, addition)                                \
+        EXCEPTION_PROLOG(n, GEN, addition##_GEN)
+
+#define CRIT_EXCEPTION_PROLOG(n, addition)                                  \
+        EXCEPTION_PROLOG(n, CRIT, addition##_CRIT)
+
+#define DBG_EXCEPTION_PROLOG(n, addition)                                   \
+        EXCEPTION_PROLOG(n, DBG, addition##_DBG)
+
+#define MC_EXCEPTION_PROLOG(n, addition)                                    \
+        EXCEPTION_PROLOG(n, MC, addition##_MC)
+
+
+/* Variants of the "addition" argument for the prolog
+ */
+#define PROLOG_ADDITION_NONE_GEN
+#define PROLOG_ADDITION_NONE_CRIT
+#define PROLOG_ADDITION_NONE_DBG
+#define PROLOG_ADDITION_NONE_MC
+
+#define PROLOG_ADDITION_MASKABLE_GEN                                        \
+        lbz     r11,PACASOFTIRQEN(r13); /* are irqs soft-disabled ? */      \
+        cmpwi   cr0,r11,0;              /* yes -> go out of line */         \
+        beq     masked_interrupt_book3e;
+
+#define PROLOG_ADDITION_2REGS_GEN                                           \
+        std     r14,PACA_EXGEN+EX_R14(r13);                                 \
+        std     r15,PACA_EXGEN+EX_R15(r13)
+
+#define PROLOG_ADDITION_1REG_GEN                                            \
+        std     r14,PACA_EXGEN+EX_R14(r13);
+
+#define PROLOG_ADDITION_2REGS_CRIT                                          \
+        std     r14,PACA_EXCRIT+EX_R14(r13);                                \
+        std     r15,PACA_EXCRIT+EX_R15(r13)
+
+#define PROLOG_ADDITION_2REGS_DBG                                           \
+        std     r14,PACA_EXDBG+EX_R14(r13);                                 \
+        std     r15,PACA_EXDBG+EX_R15(r13)
+
+#define PROLOG_ADDITION_2REGS_MC                                            \
+        std     r14,PACA_EXMC+EX_R14(r13);                                  \
+        std     r15,PACA_EXMC+EX_R15(r13)
+
+/* Core exception code for all exceptions except TLB misses.
+ * XXX: Needs to make SPRN_SPRG_GEN depend on exception type
+ */
+#define EXCEPTION_COMMON(n, excf, ints)                                     \
+        std     r0,GPR0(r1);            /* save r0 in stackframe */         \
+        std     r2,GPR2(r1);            /* save r2 in stackframe */         \
+        SAVE_4GPRS(3, r1);              /* save r3 - r6 in stackframe */    \
+        SAVE_2GPRS(7, r1);              /* save r7, r8 in stackframe */     \
+        std     r9,GPR9(r1);            /* save r9 in stackframe */         \
+        std     r10,_NIP(r1);           /* save SRR0 to stackframe */       \
+        std     r11,_MSR(r1);           /* save SRR1 to stackframe */       \
+        ACCOUNT_CPU_USER_ENTRY(r10,r11);/* accounting (uses cr0+eq) */      \
+        ld      r3,excf+EX_R10(r13);    /* get back r10 */                  \
+        ld      r4,excf+EX_R11(r13);    /* get back r11 */                  \
+        mfspr   r5,SPRN_SPRG_GEN_SCRATCH;/* get back r13 */                 \
+        std     r12,GPR12(r1);          /* save r12 in stackframe */        \
+        ld      r2,PACATOC(r13);        /* get kernel TOC into r2 */        \
+        mflr    r6;                     /* save LR in stackframe */         \
+        mfctr   r7;                     /* save CTR in stackframe */        \
+        mfspr   r8,SPRN_XER;            /* save XER in stackframe */        \
+        ld      r9,excf+EX_R1(r13);     /* load orig r1 back from PACA */   \
+        lwz     r10,excf+EX_CR(r13);    /* load orig CR back from PACA  */  \
+        lbz     r11,PACASOFTIRQEN(r13); /* get current IRQ softe */         \
+        ld      r12,exception_marker@toc(r2);                               \
+        li      r0,0;                                                       \
+        std     r3,GPR10(r1);           /* save r10 to stackframe */        \
+        std     r4,GPR11(r1);           /* save r11 to stackframe */        \
+        std     r5,GPR13(r1);           /* save it to stackframe */         \
+        std     r6,_LINK(r1);                                               \
+        std     r7,_CTR(r1);                                                \
+        std     r8,_XER(r1);                                                \
+        li      r3,(n)+1;               /* indicate partial regs in trap */ \
+        std     r9,0(r1);               /* store stack frame back link */   \
+        std     r10,_CCR(r1);           /* store orig CR in stackframe */   \
+        std     r9,GPR1(r1);            /* store stack frame back link */   \
+        std     r11,SOFTE(r1);          /* and save it to stackframe */     \
+        std     r12,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */       \
+        std     r3,_TRAP(r1);           /* set trap number              */  \
+        std     r0,RESULT(r1);          /* clear regs->result */            \
+        ints;
+
+/* Variants for the "ints" argument */
+#define INTS_KEEP
+#define INTS_DISABLE_SOFT                                                   \
+        stb     r0,PACASOFTIRQEN(r13);  /* mark interrupts soft-disabled */ \
+        TRACE_DISABLE_INTS;
+#define INTS_DISABLE_HARD                                                   \
+        stb     r0,PACAHARDIRQEN(r13); /* and hard disabled */
+#define INTS_DISABLE_ALL                                                    \
+        INTS_DISABLE_SOFT                                                   \
+        INTS_DISABLE_HARD
+
+/* This is called by exceptions that used INTS_KEEP (that is did not clear
+ * neither soft nor hard IRQ indicators in the PACA. This will restore MSR:EE
+ * to it's previous value
+ *
+ * XXX In the long run, we may want to open-code it in order to separate the
+ *     load from the wrtee, thus limiting the latency caused by the dependency
+ *     but at this point, I'll favor code clarity until we have a near to final
+ *     implementation
+ */
+#define INTS_RESTORE_HARD                                                   \
+        ld      r11,_MSR(r1);                                               \
+        wrtee   r11;
+
+/* XXX FIXME: Restore r14/r15 when necessary */
+#define BAD_STACK_TRAMPOLINE(n)                                             \
+exc_##n##_bad_stack:                                                        \
+        li      r1,(n);                 /* get exception number */          \
+        sth     r1,PACA_TRAP_SAVE(r13); /* store trap */                    \
+        b       bad_stack_book3e;       /* bad stack error */
+
+#define EXCEPTION_STUB(loc, label)                                      \
+        . = interrupt_base_book3e + loc;                                \
+        nop;    /* To make debug interrupts happy */                    \
+        b       exc_##label##_book3e;
+
+#define ACK_NONE(r)
+#define ACK_DEC(r)                                                      \
+        lis     r,TSR_DIS@h;                                            \
+        mtspr   SPRN_TSR,r
+#define ACK_FIT(r)                                                      \
+        lis     r,TSR_FIS@h;                                            \
+        mtspr   SPRN_TSR,r
+
+#define MASKABLE_EXCEPTION(trapnum, label, hdlr, ack)                   \
+        START_EXCEPTION(label);                                         \
+        NORMAL_EXCEPTION_PROLOG(trapnum, PROLOG_ADDITION_MASKABLE)      \
+        EXCEPTION_COMMON(trapnum, PACA_EXGEN, INTS_DISABLE_ALL)         \
+        ack(r8);                                                        \
+        addi    r3,r1,STACK_FRAME_OVERHEAD;                             \
+        bl      hdlr;                                                   \
+        b       .ret_from_except_lite;
+
+/* This value is used to mark exception frames on the stack. */
+        .section        ".toc","aw"
+exception_marker:
+        .tc     ID_EXC_MARKER[TC],STACK_FRAME_REGS_MARKER
+
+
+/*
+ * And here we have the exception vectors !
+ */
+
+        .text
+        .balign 0x1000
+        .globl interrupt_base_book3e
+interrupt_base_book3e:                                  /* fake trap */
+        /* Note: If real debug exceptions are supported by the HW, the vector
+         * below will have to be patched up to point to an appropriate handler
+         */
+        EXCEPTION_STUB(0x000, machine_check)            /* 0x0200 */
+        EXCEPTION_STUB(0x020, critical_input)           /* 0x0580 */
+        EXCEPTION_STUB(0x040, debug_crit)               /* 0x0d00 */
+        EXCEPTION_STUB(0x060, data_storage)             /* 0x0300 */
+        EXCEPTION_STUB(0x080, instruction_storage)      /* 0x0400 */
+        EXCEPTION_STUB(0x0a0, external_input)           /* 0x0500 */
+        EXCEPTION_STUB(0x0c0, alignment)                /* 0x0600 */
+        EXCEPTION_STUB(0x0e0, program)                  /* 0x0700 */
+        EXCEPTION_STUB(0x100, fp_unavailable)           /* 0x0800 */
+        EXCEPTION_STUB(0x120, system_call)              /* 0x0c00 */
+        EXCEPTION_STUB(0x140, ap_unavailable)           /* 0x0f20 */
+        EXCEPTION_STUB(0x160, decrementer)              /* 0x0900 */
+        EXCEPTION_STUB(0x180, fixed_interval)           /* 0x0980 */
+        EXCEPTION_STUB(0x1a0, watchdog)                 /* 0x09f0 */
+        EXCEPTION_STUB(0x1c0, data_tlb_miss)
+        EXCEPTION_STUB(0x1e0, instruction_tlb_miss)
+
+#if 0
+        EXCEPTION_STUB(0x280, processor_doorbell)
+        EXCEPTION_STUB(0x220, processor_doorbell_crit)
+#endif
+        .globl interrupt_end_book3e
+interrupt_end_book3e:
+
+/* Critical Input Interrupt */
+        START_EXCEPTION(critical_input);
+        CRIT_EXCEPTION_PROLOG(0x100, PROLOG_ADDITION_NONE)
+//      EXCEPTION_COMMON(0x100, PACA_EXCRIT, INTS_DISABLE_ALL)
+//      bl      special_reg_save_crit
+//      addi    r3,r1,STACK_FRAME_OVERHEAD
+//      bl      .critical_exception
+//      b       ret_from_crit_except
+        b       .
+
+/* Machine Check Interrupt */
+        START_EXCEPTION(machine_check);
+        CRIT_EXCEPTION_PROLOG(0x200, PROLOG_ADDITION_NONE)
+//      EXCEPTION_COMMON(0x200, PACA_EXMC, INTS_DISABLE_ALL)
+//      bl      special_reg_save_mc
+//      addi    r3,r1,STACK_FRAME_OVERHEAD
+//      bl      .machine_check_exception
+//      b       ret_from_mc_except
+        b       .
+
+/* Data Storage Interrupt */
+        START_EXCEPTION(data_storage)
+        NORMAL_EXCEPTION_PROLOG(0x300, PROLOG_ADDITION_2REGS)
+        mfspr   r14,SPRN_DEAR
+        mfspr   r15,SPRN_ESR
+        EXCEPTION_COMMON(0x300, PACA_EXGEN, INTS_KEEP)
+        b       storage_fault_common
+
+/* Instruction Storage Interrupt */
+        START_EXCEPTION(instruction_storage);
+        NORMAL_EXCEPTION_PROLOG(0x400, PROLOG_ADDITION_2REGS)
+        li      r15,0
+        mr      r14,r10
+        EXCEPTION_COMMON(0x400, PACA_EXGEN, INTS_KEEP)
+        b       storage_fault_common
+
+/* External Input Interrupt */
+        MASKABLE_EXCEPTION(0x500, external_input, .do_IRQ, ACK_NONE)
+
+/* Alignment */
+        START_EXCEPTION(alignment);
+        NORMAL_EXCEPTION_PROLOG(0x600, PROLOG_ADDITION_2REGS)
+        mfspr   r14,SPRN_DEAR
+        mfspr   r15,SPRN_ESR
+        EXCEPTION_COMMON(0x600, PACA_EXGEN, INTS_KEEP)
+        b       alignment_more  /* no room, go out of line */
+
+/* Program Interrupt */
+        START_EXCEPTION(program);
+        NORMAL_EXCEPTION_PROLOG(0x700, PROLOG_ADDITION_1REG)
+        mfspr   r14,SPRN_ESR
+        EXCEPTION_COMMON(0x700, PACA_EXGEN, INTS_DISABLE_SOFT)
+        std     r14,_DSISR(r1)
+        addi    r3,r1,STACK_FRAME_OVERHEAD
+        ld      r14,PACA_EXGEN+EX_R14(r13)
+        bl      .save_nvgprs
+        INTS_RESTORE_HARD
+        bl      .program_check_exception
+        b       .ret_from_except
+
+/* Floating Point Unavailable Interrupt */
+        START_EXCEPTION(fp_unavailable);
+        NORMAL_EXCEPTION_PROLOG(0x800, PROLOG_ADDITION_NONE)
+        /* we can probably do a shorter exception entry for that one... */
+        EXCEPTION_COMMON(0x800, PACA_EXGEN, INTS_KEEP)
+        bne     1f                      /* if from user, just load it up */
+        bl      .save_nvgprs
+        addi    r3,r1,STACK_FRAME_OVERHEAD
+        INTS_RESTORE_HARD
+        bl      .kernel_fp_unavailable_exception
+        BUG_OPCODE
+1:      ld      r12,_MSR(r1)
+        bl      .load_up_fpu
+        b       fast_exception_return
+
+/* Decrementer Interrupt */
+        MASKABLE_EXCEPTION(0x900, decrementer, .timer_interrupt, ACK_DEC)
+
+/* Fixed Interval Timer Interrupt */
+        MASKABLE_EXCEPTION(0x980, fixed_interval, .unknown_exception, ACK_FIT)
+
+/* Watchdog Timer Interrupt */
+        START_EXCEPTION(watchdog);
+        CRIT_EXCEPTION_PROLOG(0x9f0, PROLOG_ADDITION_NONE)
+//      EXCEPTION_COMMON(0x9f0, PACA_EXCRIT, INTS_DISABLE_ALL)
+//      bl      special_reg_save_crit
+//      addi    r3,r1,STACK_FRAME_OVERHEAD
+//      bl      .unknown_exception
+//      b       ret_from_crit_except
+        b       .
+
+/* System Call Interrupt */
+        START_EXCEPTION(system_call)
+        mr      r9,r13                  /* keep a copy of userland r13 */
+        mfspr   r11,SPRN_SRR0           /* get return address */
+        mfspr   r12,SPRN_SRR1           /* get previous MSR */
+        mfspr   r13,SPRN_SPRG_PACA      /* get our PACA */
+        b       system_call_common
+
+/* Auxillary Processor Unavailable Interrupt */
+        START_EXCEPTION(ap_unavailable);
+        NORMAL_EXCEPTION_PROLOG(0xf20, PROLOG_ADDITION_NONE)
+        EXCEPTION_COMMON(0xf20, PACA_EXGEN, INTS_KEEP)
+        addi    r3,r1,STACK_FRAME_OVERHEAD
+        bl      .save_nvgprs
+        INTS_RESTORE_HARD
+        bl      .unknown_exception
+        b       .ret_from_except
+
+/* Debug exception as a critical interrupt*/
+        START_EXCEPTION(debug_crit);
+        CRIT_EXCEPTION_PROLOG(0xd00, PROLOG_ADDITION_2REGS)
+
+        /*
+         * If there is a single step or branch-taken exception in an
+         * exception entry sequence, it was probably meant to apply to
+         * the code where the exception occurred (since exception entry
+         * doesn't turn off DE automatically).  We simulate the effect
+         * of turning off DE on entry to an exception handler by turning
+         * off DE in the CSRR1 value and clearing the debug status.
+         */
+
+        mfspr   r14,SPRN_DBSR           /* check single-step/branch taken */
+        andis.  r15,r14,DBSR_IC@h
+        beq+    1f
+
+        LOAD_REG_IMMEDIATE(r14,interrupt_base_book3e)
+        LOAD_REG_IMMEDIATE(r15,interrupt_end_book3e)
+        cmpld   cr0,r10,r14
+        cmpld   cr1,r10,r15
+        blt+    cr0,1f
+        bge+    cr1,1f
+
+        /* here it looks like we got an inappropriate debug exception. */
+        lis     r14,DBSR_IC@h           /* clear the IC event */
+        rlwinm  r11,r11,0,~MSR_DE       /* clear DE in the CSRR1 value */
+        mtspr   SPRN_DBSR,r14
+        mtspr   SPRN_CSRR1,r11
+        lwz     r10,PACA_EXCRIT+EX_CR(r13)      /* restore registers */
+        ld      r1,PACA_EXCRIT+EX_R1(r13)
+        ld      r14,PACA_EXCRIT+EX_R14(r13)
+        ld      r15,PACA_EXCRIT+EX_R15(r13)
+        mtcr    r10
+        ld      r10,PACA_EXCRIT+EX_R10(r13)     /* restore registers */
+        ld      r11,PACA_EXCRIT+EX_R11(r13)
+        mfspr   r13,SPRN_SPRG_CRIT_SCRATCH
+        rfci
+
+        /* Normal debug exception */
+        /* XXX We only handle coming from userspace for now since we can't
+         *     quite save properly an interrupted kernel state yet
+         */
+1:      andi.   r14,r11,MSR_PR;         /* check for userspace again */
+        beq     kernel_dbg_exc;         /* if from kernel mode */
+
+        /* Now we mash up things to make it look like we are coming on a
+         * normal exception
+         */
+        mfspr   r15,SPRN_SPRG_CRIT_SCRATCH
+        mtspr   SPRN_SPRG_GEN_SCRATCH,r15
+        mfspr   r14,SPRN_DBSR
+        EXCEPTION_COMMON(0xd00, PACA_EXCRIT, INTS_DISABLE_ALL)
+        std     r14,_DSISR(r1)
+        addi    r3,r1,STACK_FRAME_OVERHEAD
+        mr      r4,r14
+        ld      r14,PACA_EXCRIT+EX_R14(r13)
+        ld      r15,PACA_EXCRIT+EX_R15(r13)
+        bl      .save_nvgprs
+        bl      .DebugException
+        b       .ret_from_except
+
+kernel_dbg_exc:
+        b       .       /* NYI */
+
+
+/*
+ * An interrupt came in while soft-disabled; clear EE in SRR1,
+ * clear paca->hard_enabled and return.
+ */
+masked_interrupt_book3e:
+        mtcr    r10
+        stb     r11,PACAHARDIRQEN(r13)
+        mfspr   r10,SPRN_SRR1
+        rldicl  r11,r10,48,1            /* clear MSR_EE */
+        rotldi  r10,r11,16
+        mtspr   SPRN_SRR1,r10
+        ld      r10,PACA_EXGEN+EX_R10(r13);     /* restore registers */
+        ld      r11,PACA_EXGEN+EX_R11(r13);
+        mfspr   r13,SPRN_SPRG_GEN_SCRATCH;
+        rfi
+        b       .
+
+/*
+ * This is called from 0x300 and 0x400 handlers after the prologs with
+ * r14 and r15 containing the fault address and error code, with the
+ * original values stashed away in the PACA
+ */
+storage_fault_common:
+        std     r14,_DAR(r1)
+        std     r15,_DSISR(r1)
+        addi    r3,r1,STACK_FRAME_OVERHEAD
+        mr      r4,r14
+        mr      r5,r15
+        ld      r14,PACA_EXGEN+EX_R14(r13)
+        ld      r15,PACA_EXGEN+EX_R15(r13)
+        INTS_RESTORE_HARD
+        bl      .do_page_fault
+        cmpdi   r3,0
+        bne-    1f
+        b       .ret_from_except_lite
+1:      bl      .save_nvgprs
+        mr      r5,r3
+        addi    r3,r1,STACK_FRAME_OVERHEAD
+        ld      r4,_DAR(r1)
+        bl      .bad_page_fault
+        b       .ret_from_except
+
+/*
+ * Alignment exception doesn't fit entirely in the 0x100 bytes so it
+ * continues here.
+ */
+alignment_more:
+        std     r14,_DAR(r1)
+        std     r15,_DSISR(r1)
+        addi    r3,r1,STACK_FRAME_OVERHEAD
+        ld      r14,PACA_EXGEN+EX_R14(r13)
+        ld      r15,PACA_EXGEN+EX_R15(r13)
+        bl      .save_nvgprs
+        INTS_RESTORE_HARD
+        bl      .alignment_exception
+        b       .ret_from_except
+
+/*
+ * We branch here from entry_64.S for the last stage of the exception
+ * return code path. MSR:EE is expected to be off at that point
+ */
+_GLOBAL(exception_return_book3e)
+        b       1f
+
+/* This is the return from load_up_fpu fast path which could do with
+ * less GPR restores in fact, but for now we have a single return path
+ */
+        .globl fast_exception_return
+fast_exception_return:
+        wrteei  0
+1:      mr      r0,r13
+        ld      r10,_MSR(r1)
+        REST_4GPRS(2, r1)
+        andi.   r6,r10,MSR_PR
+        REST_2GPRS(6, r1)
+        beq     1f
+        ACCOUNT_CPU_USER_EXIT(r10, r11)
+        ld      r0,GPR13(r1)
+
+1:      stdcx.  r0,0,r1         /* to clear the reservation */
+
+        ld      r8,_CCR(r1)
+        ld      r9,_LINK(r1)
+        ld      r10,_CTR(r1)
+        ld      r11,_XER(r1)
+        mtcr    r8
+        mtlr    r9
+        mtctr   r10
+        mtxer   r11
+        REST_2GPRS(8, r1)
+        ld      r10,GPR10(r1)
+        ld      r11,GPR11(r1)
+        ld      r12,GPR12(r1)
+        mtspr   SPRN_SPRG_GEN_SCRATCH,r0
+
+        std     r10,PACA_EXGEN+EX_R10(r13);
+        std     r11,PACA_EXGEN+EX_R11(r13);
+        ld      r10,_NIP(r1)
+        ld      r11,_MSR(r1)
+        ld      r0,GPR0(r1)
+        ld      r1,GPR1(r1)
+        mtspr   SPRN_SRR0,r10
+        mtspr   SPRN_SRR1,r11
+        ld      r10,PACA_EXGEN+EX_R10(r13)
+        ld      r11,PACA_EXGEN+EX_R11(r13)
+        mfspr   r13,SPRN_SPRG_GEN_SCRATCH
+        rfi
+
+/*
+ * Trampolines used when spotting a bad kernel stack pointer in
+ * the exception entry code.
+ *
+ * TODO: move some bits like SRR0 read to trampoline, pass PACA
+ * index around, etc... to handle crit & mcheck
+ */
+BAD_STACK_TRAMPOLINE(0x000)
+BAD_STACK_TRAMPOLINE(0x100)
+BAD_STACK_TRAMPOLINE(0x200)
+BAD_STACK_TRAMPOLINE(0x300)
+BAD_STACK_TRAMPOLINE(0x400)
+BAD_STACK_TRAMPOLINE(0x500)
+BAD_STACK_TRAMPOLINE(0x600)
+BAD_STACK_TRAMPOLINE(0x700)
+BAD_STACK_TRAMPOLINE(0x800)
+BAD_STACK_TRAMPOLINE(0x900)
+BAD_STACK_TRAMPOLINE(0x980)
+BAD_STACK_TRAMPOLINE(0x9f0)
+BAD_STACK_TRAMPOLINE(0xa00)
+BAD_STACK_TRAMPOLINE(0xb00)
+BAD_STACK_TRAMPOLINE(0xc00)
+BAD_STACK_TRAMPOLINE(0xd00)
+BAD_STACK_TRAMPOLINE(0xe00)
+BAD_STACK_TRAMPOLINE(0xf00)
+BAD_STACK_TRAMPOLINE(0xf20)
+
+        .globl  bad_stack_book3e
+bad_stack_book3e:
+        /* XXX: Needs to make SPRN_SPRG_GEN depend on exception type */
+        mfspr   r10,SPRN_SRR0;            /* read SRR0 before touching stack */
+        ld      r1,PACAEMERGSP(r13)
+        subi    r1,r1,64+INT_FRAME_SIZE
+        std     r10,_NIP(r1)
+        std     r11,_MSR(r1)
+        ld      r10,PACA_EXGEN+EX_R1(r13) /* FIXME for crit & mcheck */
+        lwz     r11,PACA_EXGEN+EX_CR(r13) /* FIXME for crit & mcheck */
+        std     r10,GPR1(r1)
+        std     r11,_CCR(r1)
+        mfspr   r10,SPRN_DEAR
+        mfspr   r11,SPRN_ESR
+        std     r10,_DAR(r1)
+        std     r11,_DSISR(r1)
+        std     r0,GPR0(r1);            /* save r0 in stackframe */         \
+        std     r2,GPR2(r1);            /* save r2 in stackframe */         \
+        SAVE_4GPRS(3, r1);              /* save r3 - r6 in stackframe */    \
+        SAVE_2GPRS(7, r1);              /* save r7, r8 in stackframe */     \
+        std     r9,GPR9(r1);            /* save r9 in stackframe */         \
+        ld      r3,PACA_EXGEN+EX_R10(r13);/* get back r10 */                \
+        ld      r4,PACA_EXGEN+EX_R11(r13);/* get back r11 */                \
+        mfspr   r5,SPRN_SPRG_GEN_SCRATCH;/* get back r13 XXX can be wrong */ \
+        std     r3,GPR10(r1);           /* save r10 to stackframe */        \
+        std     r4,GPR11(r1);           /* save r11 to stackframe */        \
+        std     r12,GPR12(r1);          /* save r12 in stackframe */        \
+        std     r5,GPR13(r1);           /* save it to stackframe */         \
+        mflr    r10
+        mfctr   r11
+        mfxer   r12
+        std     r10,_LINK(r1)
+        std     r11,_CTR(r1)
+        std     r12,_XER(r1)
+        SAVE_10GPRS(14,r1)
+        SAVE_8GPRS(24,r1)
+        lhz     r12,PACA_TRAP_SAVE(r13)
+        std     r12,_TRAP(r1)
+        addi    r11,r1,INT_FRAME_SIZE
+        std     r11,0(r1)
+        li      r12,0
+        std     r12,0(r11)
+        ld      r2,PACATOC(r13)
+1:      addi    r3,r1,STACK_FRAME_OVERHEAD
+        bl      .kernel_bad_stack
+        b       1b
+
+/*
+ * Setup the initial TLB for a core. This current implementation
+ * assume that whatever we are running off will not conflict with
+ * the new mapping at PAGE_OFFSET.
+ * We also make various assumptions about the processor we run on,
+ * this might have to be made more flexible based on the content
+ * of MMUCFG and friends.
+ */
+_GLOBAL(initial_tlb_book3e)
+
+        /* Setup MAS 0,1,2,3 and 7 for tlbwe of a 1G entry that maps the
+         * kernel linear mapping. We also set MAS8 once for all here though
+         * that will have to be made dependent on whether we are running under
+         * a hypervisor I suppose.
+         */
+        li      r3,MAS0_HES | MAS0_WQ_ALLWAYS
+        mtspr   SPRN_MAS0,r3
+        lis     r3,(MAS1_VALID | MAS1_IPROT)@h
+        ori     r3,r3,BOOK3E_PAGESZ_1GB << MAS1_TSIZE_SHIFT
+        mtspr   SPRN_MAS1,r3
+        LOAD_REG_IMMEDIATE(r3, PAGE_OFFSET | MAS2_M)
+        mtspr   SPRN_MAS2,r3
+        li      r3,MAS3_SR | MAS3_SW | MAS3_SX
+        mtspr   SPRN_MAS7_MAS3,r3
+        li      r3,0
+        mtspr   SPRN_MAS8,r3
+
+        /* Write the TLB entry */
+        tlbwe
+
+        /* Now we branch the new virtual address mapped by this entry */
+        LOAD_REG_IMMEDIATE(r3,1f)
+        mtctr   r3
+        bctr
+
+1:      /* We are now running at PAGE_OFFSET, clean the TLB of everything
+         * else (XXX we should scan for bolted crap from the firmware too)
+         */
+        PPC_TLBILX(0,0,0)
+        sync
+        isync
+
+        /* We translate LR and return */
+        mflr    r3
+        tovirt(r3,r3)
+        mtlr    r3
+        blr
+
+/*
+ * Main entry (boot CPU, thread 0)
+ *
+ * We enter here from head_64.S, possibly after the prom_init trampoline
+ * with r3 and r4 already saved to r31 and 30 respectively and in 64 bits
+ * mode. Anything else is as it was left by the bootloader
+ *
+ * Initial requirements of this port:
+ *
+ * - Kernel loaded at 0 physical
+ * - A good lump of memory mapped 0:0 by UTLB entry 0
+ * - MSR:IS & MSR:DS set to 0
+ *
+ * Note that some of the above requirements will be relaxed in the future
+ * as the kernel becomes smarter at dealing with different initial conditions
+ * but for now you have to be careful
+ */
+_GLOBAL(start_initialization_book3e)
+        mflr    r28
+
+        /* First, we need to setup some initial TLBs to map the kernel
+         * text, data and bss at PAGE_OFFSET. We don't have a real mode
+         * and always use AS 0, so we just set it up to match our link
+         * address and never use 0 based addresses.
+         */
+        bl      .initial_tlb_book3e
+
+        /* Init global core bits */
+        bl      .init_core_book3e
+
+        /* Init per-thread bits */
+        bl      .init_thread_book3e
+
+        /* Return to common init code */
+        tovirt(r28,r28)
+        mtlr    r28
+        blr
+
+
+/*
+ * Secondary core/processor entry
+ *
+ * This is entered for thread 0 of a secondary core, all other threads
+ * are expected to be stopped. It's similar to start_initialization_book3e
+ * except that it's generally entered from the holding loop in head_64.S
+ * after CPUs have been gathered by Open Firmware.
+ *
+ * We assume we are in 32 bits mode running with whatever TLB entry was
+ * set for us by the firmware or POR engine.
+ */
+_GLOBAL(book3e_secondary_core_init_tlb_set)
+        li      r4,1
+        b       .generic_secondary_smp_init
+
+_GLOBAL(book3e_secondary_core_init)
+        mflr    r28
+
+        /* Do we need to setup initial TLB entry ? */
+        cmplwi  r4,0
+        bne     2f
+
+        /* Setup TLB for this core */
+        bl      .initial_tlb_book3e
+
+        /* We can return from the above running at a different
+         * address, so recalculate r2 (TOC)
+         */
+        bl      .relative_toc
+
+        /* Init global core bits */
+2:      bl      .init_core_book3e
+
+        /* Init per-thread bits */
+3:      bl      .init_thread_book3e
+
+        /* Return to common init code at proper virtual address.
+         *
+         * Due to various previous assumptions, we know we entered this
+         * function at either the final PAGE_OFFSET mapping or using a
+         * 1:1 mapping at 0, so we don't bother doing a complicated check
+         * here, we just ensure the return address has the right top bits.
+         *
+         * Note that if we ever want to be smarter about where we can be
+         * started from, we have to be careful that by the time we reach
+         * the code below we may already be running at a different location
+         * than the one we were called from since initial_tlb_book3e can
+         * have moved us already.
+         */
+        cmpdi   cr0,r28,0
+        blt     1f
+        lis     r3,PAGE_OFFSET@highest
+        sldi    r3,r3,32
+        or      r28,r28,r3
+1:      mtlr    r28
+        blr
+
+_GLOBAL(book3e_secondary_thread_init)
+        mflr    r28
+        b       3b
+
+_STATIC(init_core_book3e)
+        /* Establish the interrupt vector base */
+        LOAD_REG_IMMEDIATE(r3, interrupt_base_book3e)
+        mtspr   SPRN_IVPR,r3
+        sync
+        blr
+
+_STATIC(init_thread_book3e)
+        lis     r3,(SPRN_EPCR_ICM | SPRN_EPCR_GICM)@h
+        mtspr   SPRN_EPCR,r3
+
+        /* Make sure interrupts are off */
+        wrteei  0
+
+        /* disable watchdog and FIT and enable DEC interrupts */
+        lis     r3,TCR_DIE@h
+        mtspr   SPRN_TCR,r3
+
+        blr
+
+
+
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index 8ac85e08ffae..1808876edcc9 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -12,6 +12,8 @@
  *
  */
 
+#include <asm/exception-64s.h>
+
 /*
  * We layout physical memory as follows:
  * 0x0000 - 0x00ff : Secondary processor spin code
@@ -22,18 +24,6 @@
  * 0x8000 -        : Early init and support code
  */
 
-
-/*
- *   SPRG Usage
- *
- *   Register   Definition
- *
- *   SPRG0      reserved for hypervisor
- *   SPRG1      temp - used to save gpr
- *   SPRG2      temp - used to save gpr
- *   SPRG3      virt addr of paca
- */
-
 /*
  * This is the start of the interrupt handlers for pSeries
  * This code runs with relocation off.
@@ -51,34 +41,44 @@ __start_interrupts:
         . = 0x200
 _machine_check_pSeries:
         HMT_MEDIUM
-        mtspr   SPRN_SPRG1,r13          /* save r13 */
+        mtspr   SPRN_SPRG_SCRATCH0,r13          /* save r13 */
         EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common)
 
         . = 0x300
         .globl data_access_pSeries
 data_access_pSeries:
         HMT_MEDIUM
-        mtspr   SPRN_SPRG1,r13
+        mtspr   SPRN_SPRG_SCRATCH0,r13
 BEGIN_FTR_SECTION
-        mtspr   SPRN_SPRG2,r12
-        mfspr   r13,SPRN_DAR
-        mfspr   r12,SPRN_DSISR
-        srdi    r13,r13,60
-        rlwimi  r13,r12,16,0x20
-        mfcr    r12
-        cmpwi   r13,0x2c
+        mfspr   r13,SPRN_SPRG_PACA
+        std     r9,PACA_EXSLB+EX_R9(r13)
+        std     r10,PACA_EXSLB+EX_R10(r13)
+        mfspr   r10,SPRN_DAR
+        mfspr   r9,SPRN_DSISR
+        srdi    r10,r10,60
+        rlwimi  r10,r9,16,0x20
+        mfcr    r9
+        cmpwi   r10,0x2c
         beq     do_stab_bolted_pSeries
-        mtcrf   0x80,r12
-        mfspr   r12,SPRN_SPRG2
-END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
+        ld      r10,PACA_EXSLB+EX_R10(r13)
+        std     r11,PACA_EXGEN+EX_R11(r13)
+        ld      r11,PACA_EXSLB+EX_R9(r13)
+        std     r12,PACA_EXGEN+EX_R12(r13)
+        mfspr   r12,SPRN_SPRG_SCRATCH0
+        std     r10,PACA_EXGEN+EX_R10(r13)
+        std     r11,PACA_EXGEN+EX_R9(r13)
+        std     r12,PACA_EXGEN+EX_R13(r13)
+        EXCEPTION_PROLOG_PSERIES_1(data_access_common)
+FTR_SECTION_ELSE
         EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common)
+ALT_FTR_SECTION_END_IFCLR(CPU_FTR_SLB)
 
         . = 0x380
         .globl data_access_slb_pSeries
 data_access_slb_pSeries:
         HMT_MEDIUM
-        mtspr   SPRN_SPRG1,r13
-        mfspr   r13,SPRN_SPRG3          /* get paca address into r13 */
+        mtspr   SPRN_SPRG_SCRATCH0,r13
+        mfspr   r13,SPRN_SPRG_PACA              /* get paca address into r13 */
         std     r3,PACA_EXSLB+EX_R3(r13)
         mfspr   r3,SPRN_DAR
         std     r9,PACA_EXSLB+EX_R9(r13)        /* save r9 - r12 */
@@ -91,7 +91,7 @@ data_access_slb_pSeries:
         std     r10,PACA_EXSLB+EX_R10(r13)
         std     r11,PACA_EXSLB+EX_R11(r13)
         std     r12,PACA_EXSLB+EX_R12(r13)
-        mfspr   r10,SPRN_SPRG1
+        mfspr   r10,SPRN_SPRG_SCRATCH0
         std     r10,PACA_EXSLB+EX_R13(r13)
         mfspr   r12,SPRN_SRR1           /* and SRR1 */
 #ifndef CONFIG_RELOCATABLE
@@ -115,8 +115,8 @@ data_access_slb_pSeries:
         .globl instruction_access_slb_pSeries
 instruction_access_slb_pSeries:
         HMT_MEDIUM
-        mtspr   SPRN_SPRG1,r13
-        mfspr   r13,SPRN_SPRG3          /* get paca address into r13 */
+        mtspr   SPRN_SPRG_SCRATCH0,r13
+        mfspr   r13,SPRN_SPRG_PACA              /* get paca address into r13 */
         std     r3,PACA_EXSLB+EX_R3(r13)
         mfspr   r3,SPRN_SRR0            /* SRR0 is faulting address */
         std     r9,PACA_EXSLB+EX_R9(r13)        /* save r9 - r12 */
@@ -129,7 +129,7 @@ instruction_access_slb_pSeries:
         std     r10,PACA_EXSLB+EX_R10(r13)
         std     r11,PACA_EXSLB+EX_R11(r13)
         std     r12,PACA_EXSLB+EX_R12(r13)
-        mfspr   r10,SPRN_SPRG1
+        mfspr   r10,SPRN_SPRG_SCRATCH0
         std     r10,PACA_EXSLB+EX_R13(r13)
         mfspr   r12,SPRN_SRR1           /* and SRR1 */
 #ifndef CONFIG_RELOCATABLE
@@ -159,7 +159,7 @@ BEGIN_FTR_SECTION
         beq-    1f
 END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE)
         mr      r9,r13
-        mfspr   r13,SPRN_SPRG3
+        mfspr   r13,SPRN_SPRG_PACA
         mfspr   r11,SPRN_SRR0
         ld      r12,PACAKBASE(r13)
         ld      r10,PACAKMSR(r13)
@@ -228,15 +228,17 @@ masked_interrupt:
         rotldi  r10,r10,16
         mtspr   SPRN_SRR1,r10
         ld      r10,PACA_EXGEN+EX_R10(r13)
-        mfspr   r13,SPRN_SPRG1
+        mfspr   r13,SPRN_SPRG_SCRATCH0
         rfid
         b       .
 
         .align  7
 do_stab_bolted_pSeries:
-        mtcrf   0x80,r12
-        mfspr   r12,SPRN_SPRG2
-        EXCEPTION_PROLOG_PSERIES(PACA_EXSLB, .do_stab_bolted)
+        std     r11,PACA_EXSLB+EX_R11(r13)
+        std     r12,PACA_EXSLB+EX_R12(r13)
+        mfspr   r10,SPRN_SPRG_SCRATCH0
+        std     r10,PACA_EXSLB+EX_R13(r13)
+        EXCEPTION_PROLOG_PSERIES_1(.do_stab_bolted)
 
 #ifdef CONFIG_PPC_PSERIES
 /*
@@ -246,14 +248,14 @@ do_stab_bolted_pSeries:
       .align 7
 system_reset_fwnmi:
         HMT_MEDIUM
-        mtspr   SPRN_SPRG1,r13          /* save r13 */
+        mtspr   SPRN_SPRG_SCRATCH0,r13          /* save r13 */
         EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common)
 
         .globl machine_check_fwnmi
       .align 7
 machine_check_fwnmi:
         HMT_MEDIUM
-        mtspr   SPRN_SPRG1,r13          /* save r13 */
+        mtspr   SPRN_SPRG_SCRATCH0,r13          /* save r13 */
         EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common)
 
 #endif /* CONFIG_PPC_PSERIES */
@@ -268,7 +270,7 @@ slb_miss_user_pseries:
         std     r10,PACA_EXGEN+EX_R10(r13)
         std     r11,PACA_EXGEN+EX_R11(r13)
         std     r12,PACA_EXGEN+EX_R12(r13)
-        mfspr   r10,SPRG1
+        mfspr   r10,SPRG_SCRATCH0
         ld      r11,PACA_EXSLB+EX_R9(r13)
         ld      r12,PACA_EXSLB+EX_R3(r13)
         std     r10,PACA_EXGEN+EX_R13(r13)
diff --git a/arch/powerpc/kernel/fpu.S b/arch/powerpc/kernel/fpu.S
index 2436df33c6f4..fc8f5b14019c 100644
--- a/arch/powerpc/kernel/fpu.S
+++ b/arch/powerpc/kernel/fpu.S
@@ -91,7 +91,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_VSX)
 #endif /* CONFIG_SMP */
         /* enable use of FP after return */
 #ifdef CONFIG_PPC32
-        mfspr   r5,SPRN_SPRG3           /* current task's THREAD (phys) */
+        mfspr   r5,SPRN_SPRG_THREAD             /* current task's THREAD (phys) */
         lwz     r4,THREAD_FPEXC_MODE(r5)
         ori     r9,r9,MSR_FP            /* enable FP for current */
         or      r9,r9,r4
diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S
index fc2132942754..829c3fe7c5a2 100644
--- a/arch/powerpc/kernel/head_32.S
+++ b/arch/powerpc/kernel/head_32.S
@@ -244,8 +244,8 @@ __secondary_hold_acknowledge:
  * task's thread_struct.
  */
 #define EXCEPTION_PROLOG        \
-        mtspr   SPRN_SPRG0,r10; \
-        mtspr   SPRN_SPRG1,r11; \
+        mtspr   SPRN_SPRG_SCRATCH0,r10; \
+        mtspr   SPRN_SPRG_SCRATCH1,r11; \
         mfcr    r10;            \
         EXCEPTION_PROLOG_1;     \
         EXCEPTION_PROLOG_2
@@ -255,7 +255,7 @@ __secondary_hold_acknowledge:
         andi.   r11,r11,MSR_PR; \
         tophys(r11,r1);                 /* use tophys(r1) if kernel */ \
         beq     1f;             \
-        mfspr   r11,SPRN_SPRG3; \
+        mfspr   r11,SPRN_SPRG_THREAD;   \
         lwz     r11,THREAD_INFO-THREAD(r11);    \
         addi    r11,r11,THREAD_SIZE;    \
         tophys(r11,r11);        \
@@ -267,9 +267,9 @@ __secondary_hold_acknowledge:
         stw     r10,_CCR(r11);          /* save registers */ \
         stw     r12,GPR12(r11); \
         stw     r9,GPR9(r11);   \
-        mfspr   r10,SPRN_SPRG0; \
+        mfspr   r10,SPRN_SPRG_SCRATCH0; \
         stw     r10,GPR10(r11); \
-        mfspr   r12,SPRN_SPRG1; \
+        mfspr   r12,SPRN_SPRG_SCRATCH1; \
         stw     r12,GPR11(r11); \
         mflr    r10;            \
         stw     r10,_LINK(r11); \
@@ -355,11 +355,11 @@ i##n:								\
  *      -- paulus.
  */
         . = 0x200
-        mtspr   SPRN_SPRG0,r10
-        mtspr   SPRN_SPRG1,r11
+        mtspr   SPRN_SPRG_SCRATCH0,r10
+        mtspr   SPRN_SPRG_SCRATCH1,r11
         mfcr    r10
 #ifdef CONFIG_PPC_CHRP
-        mfspr   r11,SPRN_SPRG2
+        mfspr   r11,SPRN_SPRG_RTAS
         cmpwi   0,r11,0
         bne     7f
 #endif /* CONFIG_PPC_CHRP */
@@ -367,7 +367,7 @@ i##n:								\
 7:      EXCEPTION_PROLOG_2
         addi    r3,r1,STACK_FRAME_OVERHEAD
 #ifdef CONFIG_PPC_CHRP
-        mfspr   r4,SPRN_SPRG2
+        mfspr   r4,SPRN_SPRG_RTAS
         cmpwi   cr1,r4,0
         bne     cr1,1f
 #endif
@@ -485,7 +485,7 @@ InstructionTLBMiss:
         mfspr   r3,SPRN_IMISS
         lis     r1,PAGE_OFFSET@h                /* check if kernel address */
         cmplw   0,r1,r3
-        mfspr   r2,SPRN_SPRG3
+        mfspr   r2,SPRN_SPRG_THREAD
         li      r1,_PAGE_USER|_PAGE_PRESENT /* low addresses tested as user */
         lwz     r2,PGDIR(r2)
         bge-    112f
@@ -559,7 +559,7 @@ DataLoadTLBMiss:
         mfspr   r3,SPRN_DMISS
         lis     r1,PAGE_OFFSET@h                /* check if kernel address */
         cmplw   0,r1,r3
-        mfspr   r2,SPRN_SPRG3
+        mfspr   r2,SPRN_SPRG_THREAD
         li      r1,_PAGE_USER|_PAGE_PRESENT /* low addresses tested as user */
         lwz     r2,PGDIR(r2)
         bge-    112f
@@ -598,12 +598,12 @@ END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
         mtcrf   0x80,r2
 BEGIN_MMU_FTR_SECTION
         li      r0,1
-        mfspr   r1,SPRN_SPRG4
+        mfspr   r1,SPRN_SPRG_603_LRU
         rlwinm  r2,r3,20,27,31          /* Get Address bits 15:19 */
         slw     r0,r0,r2
         xor     r1,r0,r1
         srw     r0,r1,r2
-        mtspr   SPRN_SPRG4,r1
+        mtspr   SPRN_SPRG_603_LRU,r1
         mfspr   r2,SPRN_SRR1
         rlwimi  r2,r0,31-14,14,14
         mtspr   SPRN_SRR1,r2
@@ -643,7 +643,7 @@ DataStoreTLBMiss:
         mfspr   r3,SPRN_DMISS
         lis     r1,PAGE_OFFSET@h                /* check if kernel address */
         cmplw   0,r1,r3
-        mfspr   r2,SPRN_SPRG3
+        mfspr   r2,SPRN_SPRG_THREAD
         li      r1,_PAGE_RW|_PAGE_USER|_PAGE_PRESENT /* access flags */
         lwz     r2,PGDIR(r2)
         bge-    112f
@@ -678,12 +678,12 @@ END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
         mtcrf   0x80,r2
 BEGIN_MMU_FTR_SECTION
         li      r0,1
-        mfspr   r1,SPRN_SPRG4
+        mfspr   r1,SPRN_SPRG_603_LRU
         rlwinm  r2,r3,20,27,31          /* Get Address bits 15:19 */
         slw     r0,r0,r2
         xor     r1,r0,r1
         srw     r0,r1,r2
-        mtspr   SPRN_SPRG4,r1
+        mtspr   SPRN_SPRG_603_LRU,r1
         mfspr   r2,SPRN_SRR1
         rlwimi  r2,r0,31-14,14,14
         mtspr   SPRN_SRR1,r2
@@ -864,9 +864,9 @@ __secondary_start:
         tophys(r4,r2)
         addi    r4,r4,THREAD    /* phys address of our thread_struct */
         CLR_TOP32(r4)
-        mtspr   SPRN_SPRG3,r4
+        mtspr   SPRN_SPRG_THREAD,r4
         li      r3,0
-        mtspr   SPRN_SPRG2,r3   /* 0 => not in RTAS */
+        mtspr   SPRN_SPRG_RTAS,r3       /* 0 => not in RTAS */
 
         /* enable MMU and jump to start_secondary */
         li      r4,MSR_KERNEL
@@ -947,9 +947,9 @@ start_here:
         tophys(r4,r2)
         addi    r4,r4,THREAD    /* init task's THREAD */
         CLR_TOP32(r4)
-        mtspr   SPRN_SPRG3,r4
+        mtspr   SPRN_SPRG_THREAD,r4
         li      r3,0
-        mtspr   SPRN_SPRG2,r3   /* 0 => not in RTAS */
+        mtspr   SPRN_SPRG_RTAS,r3       /* 0 => not in RTAS */
 
         /* stack */
         lis     r1,init_thread_union@ha
diff --git a/arch/powerpc/kernel/head_40x.S b/arch/powerpc/kernel/head_40x.S
index 0c96911d4299..a90625f9b485 100644
--- a/arch/powerpc/kernel/head_40x.S
+++ b/arch/powerpc/kernel/head_40x.S
@@ -103,21 +103,21 @@ _ENTRY(saved_ksp_limit)
 
 /*
  * Exception vector entry code. This code runs with address translation
- * turned off (i.e. using physical addresses). We assume SPRG3 has the
- * physical address of the current task thread_struct.
+ * turned off (i.e. using physical addresses). We assume SPRG_THREAD has
+ * the physical address of the current task thread_struct.
  * Note that we have to have decremented r1 before we write to any fields
  * of the exception frame, since a critical interrupt could occur at any
  * time, and it will write to the area immediately below the current r1.
  */
 #define NORMAL_EXCEPTION_PROLOG                                              \
-        mtspr   SPRN_SPRG0,r10;         /* save two registers to work with */\
-        mtspr   SPRN_SPRG1,r11;                                              \
-        mtspr   SPRN_SPRG2,r1;                                               \
+        mtspr   SPRN_SPRG_SCRATCH0,r10; /* save two registers to work with */\
+        mtspr   SPRN_SPRG_SCRATCH1,r11;                                      \
+        mtspr   SPRN_SPRG_SCRATCH2,r1;                                       \
         mfcr    r10;                    /* save CR in r10 for now          */\
         mfspr   r11,SPRN_SRR1;          /* check whether user or kernel    */\
         andi.   r11,r11,MSR_PR;                                              \
         beq     1f;                                                          \
-        mfspr   r1,SPRN_SPRG3;          /* if from user, start at top of   */\
+        mfspr   r1,SPRN_SPRG_THREAD;    /* if from user, start at top of   */\
         lwz     r1,THREAD_INFO-THREAD(r1); /* this thread's kernel stack   */\
         addi    r1,r1,THREAD_SIZE;                                           \
 1:      subi    r1,r1,INT_FRAME_SIZE;   /* Allocate an exception frame     */\
@@ -125,13 +125,13 @@ _ENTRY(saved_ksp_limit)
         stw     r10,_CCR(r11);          /* save various registers          */\
         stw     r12,GPR12(r11);                                              \
         stw     r9,GPR9(r11);                                                \
-        mfspr   r10,SPRN_SPRG0;                                              \
+        mfspr   r10,SPRN_SPRG_SCRATCH0;                                      \
         stw     r10,GPR10(r11);                                              \
-        mfspr   r12,SPRN_SPRG1;                                              \
+        mfspr   r12,SPRN_SPRG_SCRATCH1;                                      \
         stw     r12,GPR11(r11);                                              \
         mflr    r10;                                                         \
         stw     r10,_LINK(r11);                                              \
-        mfspr   r10,SPRN_SPRG2;                                              \
+        mfspr   r10,SPRN_SPRG_SCRATCH2;                                      \
         mfspr   r12,SPRN_SRR0;                                               \
         stw     r10,GPR1(r11);                                               \
         mfspr   r9,SPRN_SRR1;                                                \
@@ -160,7 +160,7 @@ _ENTRY(saved_ksp_limit)
         lwz     r11,critirq_ctx@l(r11);                                      \
         beq     1f;                                                          \
         /* COMING FROM USER MODE */                                          \
-        mfspr   r11,SPRN_SPRG3;         /* if from user, start at top of   */\
+        mfspr   r11,SPRN_SPRG_THREAD;   /* if from user, start at top of   */\
         lwz     r11,THREAD_INFO-THREAD(r11); /* this thread's kernel stack */\
 1:      addi    r11,r11,THREAD_SIZE-INT_FRAME_SIZE; /* Alloc an excpt frm  */\
         tophys(r11,r11);                                                     \
@@ -265,8 +265,8 @@ label:
  * and exit.  Otherwise, we call heavywight functions to do the work.
  */
         START_EXCEPTION(0x0300, DataStorage)
-        mtspr   SPRN_SPRG0, r10         /* Save some working registers */
-        mtspr   SPRN_SPRG1, r11
+        mtspr   SPRN_SPRG_SCRATCH0, r10 /* Save some working registers */
+        mtspr   SPRN_SPRG_SCRATCH1, r11
 #ifdef CONFIG_403GCX
         stw     r12, 0(r0)
         stw     r9, 4(r0)
@@ -275,12 +275,12 @@ label:
         stw     r11, 8(r0)
         stw     r12, 12(r0)
 #else
-        mtspr   SPRN_SPRG4, r12
-        mtspr   SPRN_SPRG5, r9
+        mtspr   SPRN_SPRG_SCRATCH3, r12
+        mtspr   SPRN_SPRG_SCRATCH4, r9
         mfcr    r11
         mfspr   r12, SPRN_PID
-        mtspr   SPRN_SPRG7, r11
-        mtspr   SPRN_SPRG6, r12
+        mtspr   SPRN_SPRG_SCRATCH6, r11
+        mtspr   SPRN_SPRG_SCRATCH5, r12
 #endif
 
         /* First, check if it was a zone fault (which means a user
@@ -308,7 +308,7 @@ label:
         /* Get the PGD for the current thread.
          */
 3:
-        mfspr   r11,SPRN_SPRG3
+        mfspr   r11,SPRN_SPRG_THREAD
         lwz     r11,PGDIR(r11)
 4:
         tophys(r11, r11)
@@ -355,15 +355,15 @@ label:
         lwz     r9, 4(r0)
         lwz     r12, 0(r0)
 #else
-        mfspr   r12, SPRN_SPRG6
-        mfspr   r11, SPRN_SPRG7
+        mfspr   r12, SPRN_SPRG_SCRATCH5
+        mfspr   r11, SPRN_SPRG_SCRATCH6
         mtspr   SPRN_PID, r12
         mtcr    r11
-        mfspr   r9, SPRN_SPRG5
-        mfspr   r12, SPRN_SPRG4
+        mfspr   r9, SPRN_SPRG_SCRATCH4
+        mfspr   r12, SPRN_SPRG_SCRATCH3
 #endif
-        mfspr   r11, SPRN_SPRG1
-        mfspr   r10, SPRN_SPRG0
+        mfspr   r11, SPRN_SPRG_SCRATCH1
+        mfspr   r10, SPRN_SPRG_SCRATCH0
         PPC405_ERR77_SYNC
         rfi                     /* Should sync shadow TLBs */
         b       .               /* prevent prefetch past rfi */
@@ -380,15 +380,15 @@ label:
         lwz     r9, 4(r0)
         lwz     r12, 0(r0)
 #else
-        mfspr   r12, SPRN_SPRG6
-        mfspr   r11, SPRN_SPRG7
+        mfspr   r12, SPRN_SPRG_SCRATCH5
+        mfspr   r11, SPRN_SPRG_SCRATCH6
         mtspr   SPRN_PID, r12
         mtcr    r11
-        mfspr   r9, SPRN_SPRG5
-        mfspr   r12, SPRN_SPRG4
+        mfspr   r9, SPRN_SPRG_SCRATCH4
+        mfspr   r12, SPRN_SPRG_SCRATCH3
 #endif
-        mfspr   r11, SPRN_SPRG1
-        mfspr   r10, SPRN_SPRG0
+        mfspr   r11, SPRN_SPRG_SCRATCH1
+        mfspr   r10, SPRN_SPRG_SCRATCH0
         b       DataAccess
 
 /*
@@ -466,8 +466,8 @@ label:
  * load TLB entries from the page table if they exist.
  */
         START_EXCEPTION(0x1100, DTLBMiss)
-        mtspr   SPRN_SPRG0, r10         /* Save some working registers */
-        mtspr   SPRN_SPRG1, r11
+        mtspr   SPRN_SPRG_SCRATCH0, r10 /* Save some working registers */
+        mtspr   SPRN_SPRG_SCRATCH1, r11
 #ifdef CONFIG_403GCX
         stw     r12, 0(r0)
         stw     r9, 4(r0)
@@ -476,12 +476,12 @@ label:
         stw     r11, 8(r0)
         stw     r12, 12(r0)
 #else
-        mtspr   SPRN_SPRG4, r12
-        mtspr   SPRN_SPRG5, r9
+        mtspr   SPRN_SPRG_SCRATCH3, r12
+        mtspr   SPRN_SPRG_SCRATCH4, r9
         mfcr    r11
         mfspr   r12, SPRN_PID
-        mtspr   SPRN_SPRG7, r11
-        mtspr   SPRN_SPRG6, r12
+        mtspr   SPRN_SPRG_SCRATCH6, r11
+        mtspr   SPRN_SPRG_SCRATCH5, r12
 #endif
         mfspr   r10, SPRN_DEAR          /* Get faulting address */
 
@@ -500,7 +500,7 @@ label:
         /* Get the PGD for the current thread.
          */
 3:
-        mfspr   r11,SPRN_SPRG3
+        mfspr   r11,SPRN_SPRG_THREAD
         lwz     r11,PGDIR(r11)
 4:
         tophys(r11, r11)
@@ -550,15 +550,15 @@ label:
         lwz     r9, 4(r0)
         lwz     r12, 0(r0)
 #else
-        mfspr   r12, SPRN_SPRG6
-        mfspr   r11, SPRN_SPRG7
+        mfspr   r12, SPRN_SPRG_SCRATCH5
+        mfspr   r11, SPRN_SPRG_SCRATCH6
         mtspr   SPRN_PID, r12
         mtcr    r11
-        mfspr   r9, SPRN_SPRG5
-        mfspr   r12, SPRN_SPRG4
+        mfspr   r9, SPRN_SPRG_SCRATCH4
+        mfspr   r12, SPRN_SPRG_SCRATCH3
 #endif
-        mfspr   r11, SPRN_SPRG1
-        mfspr   r10, SPRN_SPRG0
+        mfspr   r11, SPRN_SPRG_SCRATCH1
+        mfspr   r10, SPRN_SPRG_SCRATCH0
         b       DataAccess
 
 /* 0x1200 - Instruction TLB Miss Exception
@@ -566,8 +566,8 @@ label:
  * registers and bailout to a different point.
  */
         START_EXCEPTION(0x1200, ITLBMiss)
-        mtspr   SPRN_SPRG0, r10         /* Save some working registers */
-        mtspr   SPRN_SPRG1, r11
+        mtspr   SPRN_SPRG_SCRATCH0, r10  /* Save some working registers */
+        mtspr   SPRN_SPRG_SCRATCH1, r11
 #ifdef CONFIG_403GCX
         stw     r12, 0(r0)
         stw     r9, 4(r0)
@@ -576,12 +576,12 @@ label:
         stw     r11, 8(r0)
         stw     r12, 12(r0)
 #else
-        mtspr   SPRN_SPRG4, r12
-        mtspr   SPRN_SPRG5, r9
+        mtspr   SPRN_SPRG_SCRATCH3, r12
+        mtspr   SPRN_SPRG_SCRATCH4, r9
         mfcr    r11
         mfspr   r12, SPRN_PID
-        mtspr   SPRN_SPRG7, r11
-        mtspr   SPRN_SPRG6, r12
+        mtspr   SPRN_SPRG_SCRATCH6, r11
+        mtspr   SPRN_SPRG_SCRATCH5, r12
 #endif
         mfspr   r10, SPRN_SRR0          /* Get faulting address */
 
@@ -600,7 +600,7 @@ label:
         /* Get the PGD for the current thread.
          */
 3:
-        mfspr   r11,SPRN_SPRG3
+        mfspr   r11,SPRN_SPRG_THREAD
         lwz     r11,PGDIR(r11)
 4:
         tophys(r11, r11)
@@ -650,15 +650,15 @@ label:
         lwz     r9, 4(r0)
         lwz     r12, 0(r0)
 #else
-        mfspr   r12, SPRN_SPRG6
-        mfspr   r11, SPRN_SPRG7
+        mfspr   r12, SPRN_SPRG_SCRATCH5
+        mfspr   r11, SPRN_SPRG_SCRATCH6
         mtspr   SPRN_PID, r12
         mtcr    r11
-        mfspr   r9, SPRN_SPRG5
-        mfspr   r12, SPRN_SPRG4
+        mfspr   r9, SPRN_SPRG_SCRATCH4
+        mfspr   r12, SPRN_SPRG_SCRATCH3
 #endif
-        mfspr   r11, SPRN_SPRG1
-        mfspr   r10, SPRN_SPRG0
+        mfspr   r11, SPRN_SPRG_SCRATCH1
+        mfspr   r10, SPRN_SPRG_SCRATCH0
         b       InstructionAccess
 
         EXCEPTION(0x1300, Trap_13, unknown_exception, EXC_XFER_EE)
@@ -803,15 +803,15 @@ finish_tlb_load:
         lwz     r9, 4(r0)
         lwz     r12, 0(r0)
 #else
-        mfspr   r12, SPRN_SPRG6
-        mfspr   r11, SPRN_SPRG7
+        mfspr   r12, SPRN_SPRG_SCRATCH5
+        mfspr   r11, SPRN_SPRG_SCRATCH6
         mtspr   SPRN_PID, r12
         mtcr    r11
-        mfspr   r9, SPRN_SPRG5
-        mfspr   r12, SPRN_SPRG4
+        mfspr   r9, SPRN_SPRG_SCRATCH4
+        mfspr   r12, SPRN_SPRG_SCRATCH3
 #endif
-        mfspr   r11, SPRN_SPRG1
-        mfspr   r10, SPRN_SPRG0
+        mfspr   r11, SPRN_SPRG_SCRATCH1
+        mfspr   r10, SPRN_SPRG_SCRATCH0
         PPC405_ERR77_SYNC
         rfi                     /* Should sync shadow TLBs */
         b       .               /* prevent prefetch past rfi */
@@ -835,7 +835,7 @@ start_here:
         /* ptr to phys current thread */
         tophys(r4,r2)
         addi    r4,r4,THREAD    /* init task's THREAD */
-        mtspr   SPRN_SPRG3,r4
+        mtspr   SPRN_SPRG_THREAD,r4
 
         /* stack */
         lis     r1,init_thread_union@ha
diff --git a/arch/powerpc/kernel/head_44x.S b/arch/powerpc/kernel/head_44x.S
index 18d8a1677c4d..656cfb2d6666 100644
--- a/arch/powerpc/kernel/head_44x.S
+++ b/arch/powerpc/kernel/head_44x.S
@@ -239,7 +239,7 @@ skpinv:	addi	r4,r4,1				/* Increment */
 
         /* ptr to current thread */
         addi    r4,r2,THREAD    /* init task's THREAD */
-        mtspr   SPRN_SPRG3,r4
+        mtspr   SPRN_SPRG_THREAD,r4
 
         /* stack */
         lis     r1,init_thread_union@h
@@ -350,12 +350,12 @@ interrupt_base:
 
         /* Data TLB Error Interrupt */
         START_EXCEPTION(DataTLBError)
-        mtspr   SPRN_SPRG0, r10         /* Save some working registers */
-        mtspr   SPRN_SPRG1, r11
-        mtspr   SPRN_SPRG4W, r12
-        mtspr   SPRN_SPRG5W, r13
+        mtspr   SPRN_SPRG_WSCRATCH0, r10                /* Save some working registers */
+        mtspr   SPRN_SPRG_WSCRATCH1, r11
+        mtspr   SPRN_SPRG_WSCRATCH2, r12
+        mtspr   SPRN_SPRG_WSCRATCH3, r13
         mfcr    r11
-        mtspr   SPRN_SPRG7W, r11
+        mtspr   SPRN_SPRG_WSCRATCH4, r11
         mfspr   r10, SPRN_DEAR          /* Get faulting address */
 
         /* If we are faulting a kernel address, we have to use the
@@ -374,7 +374,7 @@ interrupt_base:
 
         /* Get the PGD for the current thread */
 3:
-        mfspr   r11,SPRN_SPRG3
+        mfspr   r11,SPRN_SPRG_THREAD
         lwz     r11,PGDIR(r11)
 
         /* Load PID into MMUCR TID */
@@ -446,12 +446,12 @@ tlb_44x_patch_hwater_D:
         /* The bailout.  Restore registers to pre-exception conditions
          * and call the heavyweights to help us out.
          */
-        mfspr   r11, SPRN_SPRG7R
+        mfspr   r11, SPRN_SPRG_RSCRATCH4
         mtcr    r11
-        mfspr   r13, SPRN_SPRG5R
-        mfspr   r12, SPRN_SPRG4R
-        mfspr   r11, SPRN_SPRG1
-        mfspr   r10, SPRN_SPRG0
+        mfspr   r13, SPRN_SPRG_RSCRATCH3
+        mfspr   r12, SPRN_SPRG_RSCRATCH2
+        mfspr   r11, SPRN_SPRG_RSCRATCH1
+        mfspr   r10, SPRN_SPRG_RSCRATCH0
         b       DataStorage
 
         /* Instruction TLB Error Interrupt */
@@ -461,12 +461,12 @@ tlb_44x_patch_hwater_D:
          * to a different point.
          */
         START_EXCEPTION(InstructionTLBError)
-        mtspr   SPRN_SPRG0, r10         /* Save some working registers */
-        mtspr   SPRN_SPRG1, r11
-        mtspr   SPRN_SPRG4W, r12
-        mtspr   SPRN_SPRG5W, r13
+        mtspr   SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
+        mtspr   SPRN_SPRG_WSCRATCH1, r11
+        mtspr   SPRN_SPRG_WSCRATCH2, r12
+        mtspr   SPRN_SPRG_WSCRATCH3, r13
         mfcr    r11
-        mtspr   SPRN_SPRG7W, r11
+        mtspr   SPRN_SPRG_WSCRATCH4, r11
         mfspr   r10, SPRN_SRR0          /* Get faulting address */
 
         /* If we are faulting a kernel address, we have to use the
@@ -485,7 +485,7 @@ tlb_44x_patch_hwater_D:
 
         /* Get the PGD for the current thread */
 3:
-        mfspr   r11,SPRN_SPRG3
+        mfspr   r11,SPRN_SPRG_THREAD
         lwz     r11,PGDIR(r11)
 
         /* Load PID into MMUCR TID */
@@ -542,12 +542,12 @@ tlb_44x_patch_hwater_I:
         /* The bailout.  Restore registers to pre-exception conditions
          * and call the heavyweights to help us out.
          */
-        mfspr   r11, SPRN_SPRG7R
+        mfspr   r11, SPRN_SPRG_RSCRATCH4
         mtcr    r11
-        mfspr   r13, SPRN_SPRG5R
-        mfspr   r12, SPRN_SPRG4R
-        mfspr   r11, SPRN_SPRG1
-        mfspr   r10, SPRN_SPRG0
+        mfspr   r13, SPRN_SPRG_RSCRATCH3
+        mfspr   r12, SPRN_SPRG_RSCRATCH2
+        mfspr   r11, SPRN_SPRG_RSCRATCH1
+        mfspr   r10, SPRN_SPRG_RSCRATCH0
         b       InstructionStorage
 
         /* Debug Interrupt */
@@ -593,12 +593,12 @@ finish_tlb_load:
 
         /* Done...restore registers and get out of here.
         */
-        mfspr   r11, SPRN_SPRG7R
+        mfspr   r11, SPRN_SPRG_RSCRATCH4
         mtcr    r11
-        mfspr   r13, SPRN_SPRG5R
-        mfspr   r12, SPRN_SPRG4R
-        mfspr   r11, SPRN_SPRG1
-        mfspr   r10, SPRN_SPRG0
+        mfspr   r13, SPRN_SPRG_RSCRATCH3
+        mfspr   r12, SPRN_SPRG_RSCRATCH2
+        mfspr   r11, SPRN_SPRG_RSCRATCH1
+        mfspr   r10, SPRN_SPRG_RSCRATCH0
         rfi                                     /* Force context change */
 
 /*
diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S
index 012505ebd9f9..c38afdb45d7b 100644
--- a/arch/powerpc/kernel/head_64.S
+++ b/arch/powerpc/kernel/head_64.S
@@ -36,7 +36,6 @@
 #include <asm/thread_info.h>
 #include <asm/firmware.h>
 #include <asm/page_64.h>
-#include <asm/exception.h>
 #include <asm/irqflags.h>
 
 /* The physical memory is layed out such that the secondary processor
@@ -122,10 +121,11 @@ __run_at_load:
  */
         .globl  __secondary_hold
 __secondary_hold:
+#ifndef CONFIG_PPC_BOOK3E
         mfmsr   r24
         ori     r24,r24,MSR_RI
         mtmsrd  r24                     /* RI on */
-
+#endif
         /* Grab our physical cpu number */
         mr      r24,r3
 
@@ -144,6 +144,7 @@ __secondary_hold:
         ld      r4,0(r4)                /* deref function descriptor */
         mtctr   r4
         mr      r3,r24
+        li      r4,0
         bctr
 #else
         BUG_OPCODE
@@ -164,21 +165,49 @@ exception_marker:
 #include "exceptions-64s.S"
 #endif
 
+_GLOBAL(generic_secondary_thread_init)
+        mr      r24,r3
+
+        /* turn on 64-bit mode */
+        bl      .enable_64b_mode
+
+        /* get a valid TOC pointer, wherever we're mapped at */
+        bl      .relative_toc
+
+#ifdef CONFIG_PPC_BOOK3E
+        /* Book3E initialization */
+        mr      r3,r24
+        bl      .book3e_secondary_thread_init
+#endif
+        b       generic_secondary_common_init
 
 /*
  * On pSeries and most other platforms, secondary processors spin
  * in the following code.
  * At entry, r3 = this processor's number (physical cpu id)
+ *
+ * On Book3E, r4 = 1 to indicate that the initial TLB entry for
+ * this core already exists (setup via some other mechanism such
+ * as SCOM before entry).
  */
 _GLOBAL(generic_secondary_smp_init)
         mr      r24,r3
-        
+        mr      r25,r4
+
         /* turn on 64-bit mode */
         bl      .enable_64b_mode
 
-        /* get the TOC pointer (real address) */
+        /* get a valid TOC pointer, wherever we're mapped at */
         bl      .relative_toc
 
+#ifdef CONFIG_PPC_BOOK3E
+        /* Book3E initialization */
+        mr      r3,r24
+        mr      r4,r25
+        bl      .book3e_secondary_core_init
+#endif
+
+generic_secondary_common_init:
         /* Set up a paca value for this processor. Since we have the
          * physical cpu id in r24, we need to search the pacas to find
          * which logical id maps to our physical one.
@@ -196,7 +225,12 @@ _GLOBAL(generic_secondary_smp_init)
         mr      r3,r24                  /* not found, copy phys to r3    */
         b       .kexec_wait             /* next kernel might do better   */
 
-2:      mtspr   SPRN_SPRG3,r13          /* Save vaddr of paca in SPRG3   */
+2:      mtspr   SPRN_SPRG_PACA,r13      /* Save vaddr of paca in an SPRG */
+#ifdef CONFIG_PPC_BOOK3E
+        addi    r12,r13,PACA_EXTLB      /* and TLB exc frame in another  */
+        mtspr   SPRN_SPRG_TLB_EXFRAME,r12
+#endif
+
         /* From now on, r24 is expected to be logical cpuid */
         mr      r24,r5
 3:      HMT_LOW
@@ -232,6 +266,7 @@ _GLOBAL(generic_secondary_smp_init)
  * Turn the MMU off.
  * Assumes we're mapped EA == RA if the MMU is on.
  */
+#ifdef CONFIG_PPC_BOOK3S
 _STATIC(__mmu_off)
         mfmsr   r3
         andi.   r0,r3,MSR_IR|MSR_DR
@@ -243,6 +278,7 @@ _STATIC(__mmu_off)
         sync
         rfid
         b       .       /* prevent speculative execution */
+#endif
 
 
 /*
@@ -280,6 +316,10 @@ _GLOBAL(__start_initialization_multiplatform)
         mr      r31,r3
         mr      r30,r4
 
+#ifdef CONFIG_PPC_BOOK3E
+        bl      .start_initialization_book3e
+        b       .__after_prom_start
+#else
         /* Setup some critical 970 SPRs before switching MMU off */
         mfspr   r0,SPRN_PVR
         srwi    r0,r0,16
@@ -297,6 +337,7 @@ _GLOBAL(__start_initialization_multiplatform)
         /* Switch off MMU if not already off */
         bl      .__mmu_off
         b       .__after_prom_start
+#endif /* CONFIG_PPC_BOOK3E */
 
 _INIT_STATIC(__boot_from_prom)
 #ifdef CONFIG_PPC_OF_BOOT_TRAMPOLINE
@@ -359,10 +400,16 @@ _STATIC(__after_prom_start)
  * Note: This process overwrites the OF exception vectors.
  */
         li      r3,0                    /* target addr */
+#ifdef CONFIG_PPC_BOOK3E
+        tovirt(r3,r3)                   /* on booke, we already run at PAGE_OFFSET */
+#endif
         mr.     r4,r26                  /* In some cases the loader may  */
         beq     9f                      /* have already put us at zero */
         li      r6,0x100                /* Start offset, the first 0x100 */
                                         /* bytes were copied earlier.    */
+#ifdef CONFIG_PPC_BOOK3E
+        tovirt(r6,r6)                   /* on booke, we already run at PAGE_OFFSET */
+#endif
 
 #ifdef CONFIG_CRASH_DUMP
 /*
@@ -485,7 +532,7 @@ _GLOBAL(pmac_secondary_start)
         LOAD_REG_ADDR(r4,paca)          /* Get base vaddr of paca array */
         mulli   r13,r24,PACA_SIZE       /* Calculate vaddr of right paca */
         add     r13,r13,r4              /* for this processor.          */
-        mtspr   SPRN_SPRG3,r13          /* Save vaddr of paca in SPRG3  */
+        mtspr   SPRN_SPRG_PACA,r13      /* Save vaddr of paca in an SPRG*/
 
         /* Create a temp kernel stack for use before relocation is on.  */
         ld      r1,PACAEMERGSP(r13)
@@ -503,11 +550,14 @@ _GLOBAL(pmac_secondary_start)
  *   1. Processor number
  *   2. Segment table pointer (virtual address)
  * On entry the following are set:
- *   r1 = stack pointer.  vaddr for iSeries, raddr (temp stack) for pSeries
- *   r24   = cpu# (in Linux terms)
- *   r13   = paca virtual address
- *   SPRG3 = paca virtual address
+ *   r1        = stack pointer.  vaddr for iSeries, raddr (temp stack) for pSeries
+ *   r24       = cpu# (in Linux terms)
+ *   r13       = paca virtual address
+ *   SPRG_PACA = paca virtual address
  */
+        .section ".text";
+        .align 2 ;
+
         .globl  __secondary_start
 __secondary_start:
         /* Set thread priority to MEDIUM */
@@ -544,7 +594,7 @@ END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES)
 
         mtspr   SPRN_SRR0,r3
         mtspr   SPRN_SRR1,r4
-        rfid
+        RFI
         b       .       /* prevent speculative execution */
 
 /* 
@@ -565,11 +615,16 @@ _GLOBAL(start_secondary_prolog)
  */
 _GLOBAL(enable_64b_mode)
         mfmsr   r11                     /* grab the current MSR */
+#ifdef CONFIG_PPC_BOOK3E
+        oris    r11,r11,0x8000          /* CM bit set, we'll set ICM later */
+        mtmsr   r11
+#else /* CONFIG_PPC_BOOK3E */
         li      r12,(MSR_SF | MSR_ISF)@highest
         sldi    r12,r12,48
         or      r11,r11,r12
         mtmsrd  r11
         isync
+#endif
         blr
 
 /*
@@ -613,9 +668,11 @@ _INIT_STATIC(start_here_multiplatform)
         bdnz    3b
 4:
 
+#ifndef CONFIG_PPC_BOOK3E
         mfmsr   r6
         ori     r6,r6,MSR_RI
         mtmsrd  r6                      /* RI on */
+#endif
 
 #ifdef CONFIG_RELOCATABLE
         /* Save the physical address we're running at in kernstart_addr */
@@ -642,13 +699,13 @@ _INIT_STATIC(start_here_multiplatform)
 
         /* Restore parameters passed from prom_init/kexec */
         mr      r3,r31
-        bl      .early_setup            /* also sets r13 and SPRG3 */
+        bl      .early_setup            /* also sets r13 and SPRG_PACA */
 
         LOAD_REG_ADDR(r3, .start_here_common)
         ld      r4,PACAKMSR(r13)
         mtspr   SPRN_SRR0,r3
         mtspr   SPRN_SRR1,r4
-        rfid
+        RFI
         b       .       /* prevent speculative execution */
         
         /* This is where all platforms converge execution */
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 52ff8c53b93c..6ded19d01891 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -110,8 +110,8 @@ turn_on_mmu:
  * task's thread_struct.
  */
 #define EXCEPTION_PROLOG        \
-        mtspr   SPRN_SPRG0,r10; \
-        mtspr   SPRN_SPRG1,r11; \
+        mtspr   SPRN_SPRG_SCRATCH0,r10; \
+        mtspr   SPRN_SPRG_SCRATCH1,r11; \
         mfcr    r10;            \
         EXCEPTION_PROLOG_1;     \
         EXCEPTION_PROLOG_2
@@ -121,7 +121,7 @@ turn_on_mmu:
         andi.   r11,r11,MSR_PR; \
         tophys(r11,r1);                 /* use tophys(r1) if kernel */ \
         beq     1f;             \
-        mfspr   r11,SPRN_SPRG3; \
+        mfspr   r11,SPRN_SPRG_THREAD;   \
         lwz     r11,THREAD_INFO-THREAD(r11);    \
         addi    r11,r11,THREAD_SIZE;    \
         tophys(r11,r11);        \
@@ -133,9 +133,9 @@ turn_on_mmu:
         stw     r10,_CCR(r11);          /* save registers */ \
         stw     r12,GPR12(r11); \
         stw     r9,GPR9(r11);   \
-        mfspr   r10,SPRN_SPRG0; \
+        mfspr   r10,SPRN_SPRG_SCRATCH0; \
         stw     r10,GPR10(r11); \
-        mfspr   r12,SPRN_SPRG1; \
+        mfspr   r12,SPRN_SPRG_SCRATCH1; \
         stw     r12,GPR11(r11); \
         mflr    r10;            \
         stw     r10,_LINK(r11); \
@@ -603,8 +603,9 @@ start_here:
         /* ptr to phys current thread */
         tophys(r4,r2)
         addi    r4,r4,THREAD    /* init task's THREAD */
-        mtspr   SPRN_SPRG3,r4
+        mtspr   SPRN_SPRG_THREAD,r4
         li      r3,0
+        /* XXX What is that for ? SPRG2 appears otherwise unused on 8xx */
         mtspr   SPRN_SPRG2,r3   /* 0 => r1 has kernel sp */
 
         /* stack */
diff --git a/arch/powerpc/kernel/head_booke.h b/arch/powerpc/kernel/head_booke.h
index 5f9febc8d143..50504ae39cb7 100644
--- a/arch/powerpc/kernel/head_booke.h
+++ b/arch/powerpc/kernel/head_booke.h
@@ -20,14 +20,14 @@
 #endif
 
 #define NORMAL_EXCEPTION_PROLOG                                              \
-        mtspr   SPRN_SPRG0,r10;         /* save two registers to work with */\
-        mtspr   SPRN_SPRG1,r11;                                              \
-        mtspr   SPRN_SPRG4W,r1;                                              \
+        mtspr   SPRN_SPRG_WSCRATCH0,r10;/* save two registers to work with */\
+        mtspr   SPRN_SPRG_WSCRATCH1,r11;                                     \
+        mtspr   SPRN_SPRG_WSCRATCH2,r1;                                      \
         mfcr    r10;                    /* save CR in r10 for now          */\
         mfspr   r11,SPRN_SRR1;          /* check whether user or kernel    */\
         andi.   r11,r11,MSR_PR;                                              \
         beq     1f;                                                          \
-        mfspr   r1,SPRN_SPRG3;          /* if from user, start at top of   */\
+        mfspr   r1,SPRN_SPRG_THREAD;    /* if from user, start at top of   */\
         lwz     r1,THREAD_INFO-THREAD(r1); /* this thread's kernel stack   */\
         ALLOC_STACK_FRAME(r1, THREAD_SIZE);                                  \
 1:      subi    r1,r1,INT_FRAME_SIZE;   /* Allocate an exception frame     */\
@@ -35,13 +35,13 @@
         stw     r10,_CCR(r11);          /* save various registers          */\
         stw     r12,GPR12(r11);                                              \
         stw     r9,GPR9(r11);                                                \
-        mfspr   r10,SPRN_SPRG0;                                              \
+        mfspr   r10,SPRN_SPRG_RSCRATCH0;                                        \
         stw     r10,GPR10(r11);                                              \
-        mfspr   r12,SPRN_SPRG1;                                              \
+        mfspr   r12,SPRN_SPRG_RSCRATCH1;                                     \
         stw     r12,GPR11(r11);                                              \
         mflr    r10;                                                         \
         stw     r10,_LINK(r11);                                              \
-        mfspr   r10,SPRN_SPRG4R;                                             \
+        mfspr   r10,SPRN_SPRG_RSCRATCH2;                                     \
         mfspr   r12,SPRN_SRR0;                                               \
         stw     r10,GPR1(r11);                                               \
         mfspr   r9,SPRN_SRR1;                                                \
@@ -69,21 +69,11 @@
  * providing configurations that micro-optimize space usage.
  */
 
-/* CRIT_SPRG only used in critical exception handling */
-#define CRIT_SPRG       SPRN_SPRG2
-/* MCHECK_SPRG only used in machine check exception handling */
-#define MCHECK_SPRG     SPRN_SPRG6W
-
-#define MCHECK_STACK_BASE       mcheckirq_ctx
+#define MC_STACK_BASE           mcheckirq_ctx
 #define CRIT_STACK_BASE         critirq_ctx
 
 /* only on e500mc/e200 */
-#define DEBUG_STACK_BASE        dbgirq_ctx
-#ifdef CONFIG_E200
-#define DEBUG_SPRG              SPRN_SPRG6W
-#else
-#define DEBUG_SPRG              SPRN_SPRG9
-#endif
+#define DBG_STACK_BASE          dbgirq_ctx
 
 #define EXC_LVL_FRAME_OVERHEAD  (THREAD_SIZE - INT_FRAME_SIZE - EXC_LVL_SIZE)
 
@@ -110,7 +100,7 @@
  * critical/machine check exception stack at low physical addresses.
  */
 #define EXC_LEVEL_EXCEPTION_PROLOG(exc_level, exc_level_srr0, exc_level_srr1) \
-        mtspr   exc_level##_SPRG,r8;                                         \
+        mtspr   SPRN_SPRG_WSCRATCH_##exc_level,r8;                           \
         BOOKE_LOAD_EXC_LEVEL_STACK(exc_level);/* r8 points to the exc_level stack*/ \
         stw     r9,GPR9(r8);            /* save various registers          */\
         mfcr    r9;                     /* save CR in r9 for now           */\
@@ -119,7 +109,7 @@
         stw     r9,_CCR(r8);            /* save CR on stack                */\
         mfspr   r10,exc_level_srr1;     /* check whether user or kernel    */\
         andi.   r10,r10,MSR_PR;                                              \
-        mfspr   r11,SPRN_SPRG3;         /* if from user, start at top of   */\
+        mfspr   r11,SPRN_SPRG_THREAD;   /* if from user, start at top of   */\
         lwz     r11,THREAD_INFO-THREAD(r11); /* this thread's kernel stack */\
         addi    r11,r11,EXC_LVL_FRAME_OVERHEAD; /* allocate stack frame    */\
         beq     1f;                                                          \
@@ -140,7 +130,7 @@
         lwz     r9,TI_TASK-EXC_LVL_FRAME_OVERHEAD(r11);                      \
         stw     r9,TI_TASK-EXC_LVL_FRAME_OVERHEAD(r8);                       \
         mr      r11,r8;                                                      \
-2:      mfspr   r8,exc_level##_SPRG;                                         \
+2:      mfspr   r8,SPRN_SPRG_RSCRATCH_##exc_level;                           \
         stw     r12,GPR12(r11);         /* save various registers          */\
         mflr    r10;                                                         \
         stw     r10,_LINK(r11);                                              \
@@ -161,9 +151,9 @@
 #define CRITICAL_EXCEPTION_PROLOG \
                 EXC_LEVEL_EXCEPTION_PROLOG(CRIT, SPRN_CSRR0, SPRN_CSRR1)
 #define DEBUG_EXCEPTION_PROLOG \
-                EXC_LEVEL_EXCEPTION_PROLOG(DEBUG, SPRN_DSRR0, SPRN_DSRR1)
+                EXC_LEVEL_EXCEPTION_PROLOG(DBG, SPRN_DSRR0, SPRN_DSRR1)
 #define MCHECK_EXCEPTION_PROLOG \
-                EXC_LEVEL_EXCEPTION_PROLOG(MCHECK, SPRN_MCSRR0, SPRN_MCSRR1)
+                EXC_LEVEL_EXCEPTION_PROLOG(MC, SPRN_MCSRR0, SPRN_MCSRR1)
 
 /*
  * Exception vectors.
@@ -282,13 +272,13 @@ label:
         mtspr   SPRN_DSRR1,r9;                                                \
         lwz     r9,GPR9(r11);                                                 \
         lwz     r12,GPR12(r11);                                               \
-        mtspr   DEBUG_SPRG,r8;                                                \
-        BOOKE_LOAD_EXC_LEVEL_STACK(DEBUG); /* r8 points to the debug stack */ \
+        mtspr   SPRN_SPRG_WSCRATCH_DBG,r8;                                    \
+        BOOKE_LOAD_EXC_LEVEL_STACK(DBG); /* r8 points to the debug stack */ \
         lwz     r10,GPR10(r8);                                                \
         lwz     r11,GPR11(r8);                                                \
-        mfspr   r8,DEBUG_SPRG;                                                \
+        mfspr   r8,SPRN_SPRG_RSCRATCH_DBG;                                    \
                                                                               \
-        PPC_RFDI;                                                                     \
+        PPC_RFDI;                                                             \
         b       .;                                                            \
                                                                               \
         /* continue normal handling for a debug exception... */               \
@@ -335,11 +325,11 @@ label:
         mtspr   SPRN_CSRR1,r9;                                                \
         lwz     r9,GPR9(r11);                                                 \
         lwz     r12,GPR12(r11);                                               \
-        mtspr   CRIT_SPRG,r8;                                                 \
+        mtspr   SPRN_SPRG_WSCRATCH_CRIT,r8;                                   \
         BOOKE_LOAD_EXC_LEVEL_STACK(CRIT); /* r8 points to the debug stack */  \
         lwz     r10,GPR10(r8);                                                \
         lwz     r11,GPR11(r8);                                                \
-        mfspr   r8,CRIT_SPRG;                                                 \
+        mfspr   r8,SPRN_SPRG_RSCRATCH_CRIT;                                   \
                                                                               \
         rfci;                                                                 \
         b       .;                                                            \
diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S
index 5bdcc06d294c..eca80482ae72 100644
--- a/arch/powerpc/kernel/head_fsl_booke.S
+++ b/arch/powerpc/kernel/head_fsl_booke.S
@@ -361,7 +361,7 @@ skpinv:	addi	r6,r6,1				/* Increment */
 
         /* ptr to current thread */
         addi    r4,r2,THREAD    /* init task's THREAD */
-        mtspr   SPRN_SPRG3,r4
+        mtspr   SPRN_SPRG_THREAD,r4
 
         /* stack */
         lis     r1,init_thread_union@h
@@ -532,12 +532,12 @@ interrupt_base:
 
         /* Data TLB Error Interrupt */
         START_EXCEPTION(DataTLBError)
-        mtspr   SPRN_SPRG0, r10         /* Save some working registers */
-        mtspr   SPRN_SPRG1, r11
-        mtspr   SPRN_SPRG4W, r12
-        mtspr   SPRN_SPRG5W, r13
+        mtspr   SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
+        mtspr   SPRN_SPRG_WSCRATCH1, r11
+        mtspr   SPRN_SPRG_WSCRATCH2, r12
+        mtspr   SPRN_SPRG_WSCRATCH3, r13
         mfcr    r11
-        mtspr   SPRN_SPRG7W, r11
+        mtspr   SPRN_SPRG_WSCRATCH4, r11
         mfspr   r10, SPRN_DEAR          /* Get faulting address */
 
         /* If we are faulting a kernel address, we have to use the
@@ -557,7 +557,7 @@ interrupt_base:
 
         /* Get the PGD for the current thread */
 3:
-        mfspr   r11,SPRN_SPRG3
+        mfspr   r11,SPRN_SPRG_THREAD
         lwz     r11,PGDIR(r11)
 
 4:
@@ -598,12 +598,12 @@ interrupt_base:
         /* The bailout.  Restore registers to pre-exception conditions
          * and call the heavyweights to help us out.
          */
-        mfspr   r11, SPRN_SPRG7R
+        mfspr   r11, SPRN_SPRG_RSCRATCH4
         mtcr    r11
-        mfspr   r13, SPRN_SPRG5R
-        mfspr   r12, SPRN_SPRG4R
-        mfspr   r11, SPRN_SPRG1
-        mfspr   r10, SPRN_SPRG0
+        mfspr   r13, SPRN_SPRG_RSCRATCH3
+        mfspr   r12, SPRN_SPRG_RSCRATCH2
+        mfspr   r11, SPRN_SPRG_RSCRATCH1
+        mfspr   r10, SPRN_SPRG_RSCRATCH0
         b       DataStorage
 
         /* Instruction TLB Error Interrupt */
@@ -613,12 +613,12 @@ interrupt_base:
          * to a different point.
          */
         START_EXCEPTION(InstructionTLBError)
-        mtspr   SPRN_SPRG0, r10         /* Save some working registers */
-        mtspr   SPRN_SPRG1, r11
-        mtspr   SPRN_SPRG4W, r12
-        mtspr   SPRN_SPRG5W, r13
+        mtspr   SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
+        mtspr   SPRN_SPRG_WSCRATCH1, r11
+        mtspr   SPRN_SPRG_WSCRATCH2, r12
+        mtspr   SPRN_SPRG_WSCRATCH3, r13
         mfcr    r11
-        mtspr   SPRN_SPRG7W, r11
+        mtspr   SPRN_SPRG_WSCRATCH4, r11
         mfspr   r10, SPRN_SRR0          /* Get faulting address */
 
         /* If we are faulting a kernel address, we have to use the
@@ -638,7 +638,7 @@ interrupt_base:
 
         /* Get the PGD for the current thread */
 3:
-        mfspr   r11,SPRN_SPRG3
+        mfspr   r11,SPRN_SPRG_THREAD
         lwz     r11,PGDIR(r11)
 
 4:
@@ -666,12 +666,12 @@ interrupt_base:
         /* The bailout.  Restore registers to pre-exception conditions
          * and call the heavyweights to help us out.
          */
-        mfspr   r11, SPRN_SPRG7R
+        mfspr   r11, SPRN_SPRG_RSCRATCH4
         mtcr    r11
-        mfspr   r13, SPRN_SPRG5R
-        mfspr   r12, SPRN_SPRG4R
-        mfspr   r11, SPRN_SPRG1
-        mfspr   r10, SPRN_SPRG0
+        mfspr   r13, SPRN_SPRG_RSCRATCH3
+        mfspr   r12, SPRN_SPRG_RSCRATCH2
+        mfspr   r11, SPRN_SPRG_RSCRATCH1
+        mfspr   r10, SPRN_SPRG_RSCRATCH0
         b       InstructionStorage
 
 #ifdef CONFIG_SPE
@@ -790,12 +790,12 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_BIG_PHYS)
         tlbwe
 
         /* Done...restore registers and get out of here.  */
-        mfspr   r11, SPRN_SPRG7R
+        mfspr   r11, SPRN_SPRG_RSCRATCH4
         mtcr    r11
-        mfspr   r13, SPRN_SPRG5R
-        mfspr   r12, SPRN_SPRG4R
-        mfspr   r11, SPRN_SPRG1
-        mfspr   r10, SPRN_SPRG0
+        mfspr   r13, SPRN_SPRG_RSCRATCH3
+        mfspr   r12, SPRN_SPRG_RSCRATCH2
+        mfspr   r11, SPRN_SPRG_RSCRATCH1
+        mfspr   r10, SPRN_SPRG_RSCRATCH0
         rfi                                     /* Force context change */
 
 #ifdef CONFIG_SPE
@@ -839,7 +839,7 @@ load_up_spe:
 #endif /* !CONFIG_SMP */
         /* enable use of SPE after return */
         oris    r9,r9,MSR_SPE@h
-        mfspr   r5,SPRN_SPRG3           /* current task's THREAD (phys) */
+        mfspr   r5,SPRN_SPRG_THREAD     /* current task's THREAD (phys) */
         li      r4,1
         li      r10,THREAD_ACC
         stw     r4,THREAD_USED_SPE(r5)
@@ -1118,7 +1118,7 @@ __secondary_start:
 
         /* ptr to current thread */
         addi    r4,r2,THREAD    /* address of our thread_struct */
-        mtspr   SPRN_SPRG3,r4
+        mtspr   SPRN_SPRG_THREAD,r4
 
         /* Setup the defaults for TLB entries */
         li      r4,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l
diff --git a/arch/powerpc/kernel/paca.c b/arch/powerpc/kernel/paca.c
index e9962c7f8a09..d16b1ea55d44 100644
--- a/arch/powerpc/kernel/paca.c
+++ b/arch/powerpc/kernel/paca.c
@@ -13,6 +13,7 @@
 #include <asm/lppaca.h>
 #include <asm/paca.h>
 #include <asm/sections.h>
+#include <asm/pgtable.h>
 
 /* This symbol is provided by the linker - let it fill in the paca
  * field correctly */
@@ -87,6 +88,8 @@ void __init initialise_pacas(void)
 
 #ifdef CONFIG_PPC_BOOK3S
                 new_paca->lppaca_ptr = &lppaca[cpu];
+#else
+                new_paca->kernel_pgd = swapper_pg_dir;
 #endif
                 new_paca->lock_token = 0x8000;
                 new_paca->paca_index = cpu;
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index 892a9f2e6d76..678ff132e8b0 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -664,6 +664,7 @@ int copy_thread(unsigned long clone_flags, unsigned long usp,
                 sp_vsid |= SLB_VSID_KERNEL | llp;
                 p->thread.ksp_vsid = sp_vsid;
         }
+#endif /* CONFIG_PPC_STD_MMU_64 */
 
         /*
          * The PPC64 ABI makes use of a TOC to contain function 
@@ -671,6 +672,7 @@ int copy_thread(unsigned long clone_flags, unsigned long usp,
          * to the TOC entry.  The first entry is a pointer to the actual
          * function.
          */
+#ifdef CONFIG_PPC64
         kregs->nip = *((unsigned long *)ret_from_fork);
 #else
         kregs->nip = (unsigned long)ret_from_fork;
diff --git a/arch/powerpc/kernel/prom_init.c b/arch/powerpc/kernel/prom_init.c
index a538824616fd..864334b337a3 100644
--- a/arch/powerpc/kernel/prom_init.c
+++ b/arch/powerpc/kernel/prom_init.c
@@ -190,6 +190,8 @@ static int __initdata of_platform;
 
 static char __initdata prom_cmd_line[COMMAND_LINE_SIZE];
 
+static unsigned long __initdata prom_memory_limit;
+
 static unsigned long __initdata alloc_top;
 static unsigned long __initdata alloc_top_high;
 static unsigned long __initdata alloc_bottom;
@@ -484,6 +486,67 @@ static int __init prom_setprop(phandle node, const char *nodename,
         return call_prom("interpret", 1, 1, (u32)(unsigned long) cmd);
 }
 
+/* We can't use the standard versions because of RELOC headaches. */
+#define isxdigit(c)     (('0' <= (c) && (c) <= '9') \
+                         || ('a' <= (c) && (c) <= 'f') \
+                         || ('A' <= (c) && (c) <= 'F'))
+
+#define isdigit(c)      ('0' <= (c) && (c) <= '9')
+#define islower(c)      ('a' <= (c) && (c) <= 'z')
+#define toupper(c)      (islower(c) ? ((c) - 'a' + 'A') : (c))
+
+unsigned long prom_strtoul(const char *cp, const char **endp)
+{
+        unsigned long result = 0, base = 10, value;
+
+        if (*cp == '0') {
+                base = 8;
+                cp++;
+                if (toupper(*cp) == 'X') {
+                        cp++;
+                        base = 16;
+                }
+        }
+
+        while (isxdigit(*cp) &&
+               (value = isdigit(*cp) ? *cp - '0' : toupper(*cp) - 'A' + 10) < base) {
+                result = result * base + value;
+                cp++;
+        }
+
+        if (endp)
+                *endp = cp;
+
+        return result;
+}
+
+unsigned long prom_memparse(const char *ptr, const char **retptr)
+{
+        unsigned long ret = prom_strtoul(ptr, retptr);
+        int shift = 0;
+
+        /*
+         * We can't use a switch here because GCC *may* generate a
+         * jump table which won't work, because we're not running at
+         * the address we're linked at.
+         */
+        if ('G' == **retptr || 'g' == **retptr)
+                shift = 30;
+
+        if ('M' == **retptr || 'm' == **retptr)
+                shift = 20;
+
+        if ('K' == **retptr || 'k' == **retptr)
+                shift = 10;
+
+        if (shift) {
+                ret <<= shift;
+                (*retptr)++;
+        }
+
+        return ret;
+}
+
 /*
  * Early parsing of the command line passed to the kernel, used for
  * "mem=x" and the options that affect the iommu
@@ -491,9 +554,8 @@ static int __init prom_setprop(phandle node, const char *nodename,
 static void __init early_cmdline_parse(void)
 {
         struct prom_t *_prom = &RELOC(prom);
-#ifdef CONFIG_PPC64
         const char *opt;
-#endif
+
         char *p;
         int l = 0;
 
@@ -521,6 +583,15 @@ static void __init early_cmdline_parse(void)
                         RELOC(prom_iommu_force_on) = 1;
         }
 #endif
+        opt = strstr(RELOC(prom_cmd_line), RELOC("mem="));
+        if (opt) {
+                opt += 4;
+                RELOC(prom_memory_limit) = prom_memparse(opt, (const char **)&opt);
+#ifdef CONFIG_PPC64
+                /* Align to 16 MB == size of ppc64 large page */
+                RELOC(prom_memory_limit) = ALIGN(RELOC(prom_memory_limit), 0x1000000);
+#endif
+        }
 }
 
 #ifdef CONFIG_PPC_PSERIES
@@ -1027,6 +1098,29 @@ static void __init prom_init_mem(void)
         }
 
         /*
+         * If prom_memory_limit is set we reduce the upper limits *except* for
+         * alloc_top_high. This must be the real top of RAM so we can put
+         * TCE's up there.
+         */
+
+        RELOC(alloc_top_high) = RELOC(ram_top);
+
+        if (RELOC(prom_memory_limit)) {
+                if (RELOC(prom_memory_limit) <= RELOC(alloc_bottom)) {
+                        prom_printf("Ignoring mem=%x <= alloc_bottom.\n",
+                                RELOC(prom_memory_limit));
+                        RELOC(prom_memory_limit) = 0;
+                } else if (RELOC(prom_memory_limit) >= RELOC(ram_top)) {
+                        prom_printf("Ignoring mem=%x >= ram_top.\n",
+                                RELOC(prom_memory_limit));
+                        RELOC(prom_memory_limit) = 0;
+                } else {
+                        RELOC(ram_top) = RELOC(prom_memory_limit);
+                        RELOC(rmo_top) = min(RELOC(rmo_top), RELOC(prom_memory_limit));
+                }
+        }
+
+        /*
          * Setup our top alloc point, that is top of RMO or top of
          * segment 0 when running non-LPAR.
          * Some RS64 machines have buggy firmware where claims up at
@@ -1041,6 +1135,7 @@ static void __init prom_init_mem(void)
         RELOC(alloc_top_high) = RELOC(ram_top);
 
         prom_printf("memory layout at init:\n");
+        prom_printf("  memory_limit : %x (16 MB aligned)\n", RELOC(prom_memory_limit));
         prom_printf("  alloc_bottom : %x\n", RELOC(alloc_bottom));
         prom_printf("  alloc_top    : %x\n", RELOC(alloc_top));
         prom_printf("  alloc_top_hi : %x\n", RELOC(alloc_top_high));
@@ -1259,10 +1354,6 @@ static void __init prom_initialize_tce_table(void)
  *
  * -- Cort
  */
-extern char __secondary_hold;
-extern unsigned long __secondary_hold_spinloop;
-extern unsigned long __secondary_hold_acknowledge;
-
 /*
  * We want to reference the copy of __secondary_hold_* in the
  * 0 - 0x100 address range
@@ -2399,6 +2490,10 @@ unsigned long __init prom_init(unsigned long r3, unsigned long r4,
         /*
          * Fill in some infos for use by the kernel later on
          */
+        if (RELOC(prom_memory_limit))
+                prom_setprop(_prom->chosen, "/chosen", "linux,memory-limit",
+                             &RELOC(prom_memory_limit),
+                             sizeof(prom_memory_limit));
 #ifdef CONFIG_PPC64
         if (RELOC(prom_iommu_off))
                 prom_setprop(_prom->chosen, "/chosen", "linux,iommu-off",
diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c
index 1f6816003ebe..87df51720641 100644
--- a/arch/powerpc/kernel/setup_64.c
+++ b/arch/powerpc/kernel/setup_64.c
@@ -62,6 +62,7 @@
 #include <asm/udbg.h>
 #include <asm/kexec.h>
 #include <asm/swiotlb.h>
+#include <asm/mmu_context.h>
 
 #include "setup.h"
 
@@ -142,11 +143,14 @@ early_param("smt-enabled", early_smt_enabled);
 #define check_smt_enabled()
 #endif /* CONFIG_SMP */
 
-/* Put the paca pointer into r13 and SPRG3 */
+/* Put the paca pointer into r13 and SPRG_PACA */
 void __init setup_paca(int cpu)
 {
         local_paca = &paca[cpu];
-        mtspr(SPRN_SPRG3, local_paca);
+        mtspr(SPRN_SPRG_PACA, local_paca);
+#ifdef CONFIG_PPC_BOOK3E
+        mtspr(SPRN_SPRG_TLB_EXFRAME, local_paca->extlb);
+#endif
 }
 
 /*
@@ -230,9 +234,6 @@ void early_setup_secondary(void)
 #endif /* CONFIG_SMP */
 
 #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC)
-extern unsigned long __secondary_hold_spinloop;
-extern void generic_secondary_smp_init(void);
-
 void smp_release_cpus(void)
 {
         unsigned long *ptr;
@@ -453,6 +454,24 @@ static void __init irqstack_early_init(void)
 #define irqstack_early_init()
 #endif
 
+#ifdef CONFIG_PPC_BOOK3E
+static void __init exc_lvl_early_init(void)
+{
+        unsigned int i;
+
+        for_each_possible_cpu(i) {
+                critirq_ctx[i] = (struct thread_info *)
+                        __va(lmb_alloc(THREAD_SIZE, THREAD_SIZE));
+                dbgirq_ctx[i] = (struct thread_info *)
+                        __va(lmb_alloc(THREAD_SIZE, THREAD_SIZE));
+                mcheckirq_ctx[i] = (struct thread_info *)
+                        __va(lmb_alloc(THREAD_SIZE, THREAD_SIZE));
+        }
+}
+#else
+#define exc_lvl_early_init()
+#endif
+
 /*
  * Stack space used when we detect a bad kernel stack pointer, and
  * early in SMP boots before relocation is enabled.
@@ -512,6 +531,7 @@ void __init setup_arch(char **cmdline_p)
         init_mm.brk = klimit;
         
         irqstack_early_init();
+        exc_lvl_early_init();
         emergency_stack_init();
 
 #ifdef CONFIG_PPC_STD_MMU_64
@@ -534,6 +554,10 @@ void __init setup_arch(char **cmdline_p)
 #endif
 
         paging_init();
+
+        /* Initialize the MMU context management stuff */
+        mmu_context_init();
+
         ppc64_boot_msg(0x15, "Setup Done");
 }
 
diff --git a/arch/powerpc/kernel/sys_ppc32.c b/arch/powerpc/kernel/sys_ppc32.c
index bb1cfcfdbbbb..1cc5e9e5da96 100644
--- a/arch/powerpc/kernel/sys_ppc32.c
+++ b/arch/powerpc/kernel/sys_ppc32.c
@@ -343,6 +343,18 @@ off_t ppc32_lseek(unsigned int fd, u32 offset, unsigned int origin)
         return sys_lseek(fd, (int)offset, origin);
 }
 
+long compat_sys_truncate(const char __user * path, u32 length)
+{
+        /* sign extend length */
+        return sys_truncate(path, (int)length);
+}
+
+long compat_sys_ftruncate(int fd, u32 length)
+{
+        /* sign extend length */
+        return sys_ftruncate(fd, (int)length);
+}
+
 /* Note: it is necessary to treat bufsiz as an unsigned int,
  * with the corresponding cast to a signed int to insure that the 
  * proper conversion (sign extension) between the register representation of a signed int (msr in 32-bit mode)
diff --git a/arch/powerpc/kernel/time.c b/arch/powerpc/kernel/time.c
index eae4511ceeac..edb1edb36469 100644
--- a/arch/powerpc/kernel/time.c
+++ b/arch/powerpc/kernel/time.c
@@ -479,7 +479,8 @@ static int __init iSeries_tb_recal(void)
                 unsigned long tb_ticks = tb - iSeries_recal_tb;
                 unsigned long titan_usec = (titan - iSeries_recal_titan) >> 12;
                 unsigned long new_tb_ticks_per_sec   = (tb_ticks * USEC_PER_SEC)/titan_usec;
-                unsigned long new_tb_ticks_per_jiffy = (new_tb_ticks_per_sec+(HZ/2))/HZ;
+                unsigned long new_tb_ticks_per_jiffy =
+                        DIV_ROUND_CLOSEST(new_tb_ticks_per_sec, HZ);
                 long tick_diff = new_tb_ticks_per_jiffy - tb_ticks_per_jiffy;
                 char sign = '+';                
                 /* make sure tb_ticks_per_sec and tb_ticks_per_jiffy are consistent */
diff --git a/arch/powerpc/kernel/vdso.c b/arch/powerpc/kernel/vdso.c
index ad06d5c75b15..a0abce251d0a 100644
--- a/arch/powerpc/kernel/vdso.c
+++ b/arch/powerpc/kernel/vdso.c
@@ -203,7 +203,12 @@ int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp)
         } else {
                 vdso_pagelist = vdso64_pagelist;
                 vdso_pages = vdso64_pages;
-                vdso_base = VDSO64_MBASE;
+                /*
+                 * On 64bit we don't have a preferred map address. This
+                 * allows get_unmapped_area to find an area near other mmaps
+                 * and most likely share a SLB entry.
+                 */
+                vdso_base = 0;
         }
 #else
         vdso_pagelist = vdso32_pagelist;
diff --git a/arch/powerpc/kernel/vdso32/Makefile b/arch/powerpc/kernel/vdso32/Makefile
index c3d57bd01a88..b54b81688132 100644
--- a/arch/powerpc/kernel/vdso32/Makefile
+++ b/arch/powerpc/kernel/vdso32/Makefile
@@ -12,6 +12,7 @@ endif
 targets := $(obj-vdso32) vdso32.so vdso32.so.dbg
 obj-vdso32 := $(addprefix $(obj)/, $(obj-vdso32))
 
+GCOV_PROFILE := n
 
 EXTRA_CFLAGS := -shared -fno-common -fno-builtin
 EXTRA_CFLAGS += -nostdlib -Wl,-soname=linux-vdso32.so.1 \
diff --git a/arch/powerpc/kernel/vdso64/Makefile b/arch/powerpc/kernel/vdso64/Makefile
index fa7f1b8f3e50..dd0c8e936775 100644
--- a/arch/powerpc/kernel/vdso64/Makefile
+++ b/arch/powerpc/kernel/vdso64/Makefile
@@ -7,6 +7,8 @@ obj-vdso64 = sigtramp.o gettimeofday.o datapage.o cacheflush.o note.o
 targets := $(obj-vdso64) vdso64.so vdso64.so.dbg
 obj-vdso64 := $(addprefix $(obj)/, $(obj-vdso64))
 
+GCOV_PROFILE := n
+
 EXTRA_CFLAGS := -shared -fno-common -fno-builtin
 EXTRA_CFLAGS += -nostdlib -Wl,-soname=linux-vdso64.so.1 \
                 $(call ld-option, -Wl$(comma)--hash-style=sysv)
diff --git a/arch/powerpc/kernel/vector.S b/arch/powerpc/kernel/vector.S
index ea4d64644d02..67b6916f0e94 100644
--- a/arch/powerpc/kernel/vector.S
+++ b/arch/powerpc/kernel/vector.S
@@ -65,7 +65,7 @@ _GLOBAL(load_up_altivec)
 1:
         /* enable use of VMX after return */
 #ifdef CONFIG_PPC32
-        mfspr   r5,SPRN_SPRG3           /* current task's THREAD (phys) */
+        mfspr   r5,SPRN_SPRG_THREAD             /* current task's THREAD (phys) */
         oris    r9,r9,MSR_VEC@h
 #else
         ld      r4,PACACURRENT(r13)
diff --git a/arch/powerpc/kernel/vmlinux.lds.S b/arch/powerpc/kernel/vmlinux.lds.S
index 8ef8a14abc95..3bb09975e342 100644
--- a/arch/powerpc/kernel/vmlinux.lds.S
+++ b/arch/powerpc/kernel/vmlinux.lds.S
@@ -245,10 +245,6 @@ SECTIONS
         }
 #endif
 
-        . = ALIGN(PAGE_SIZE);
-        _edata  =  .;
-        PROVIDE32 (edata = .);
-
         /* The initial task and kernel stack */
 #ifdef CONFIG_PPC32
         . = ALIGN(8192);
@@ -282,6 +278,10 @@ SECTIONS
                 __nosave_end = .;
         }
 
+        . = ALIGN(PAGE_SIZE);
+        _edata  =  .;
+        PROVIDE32 (edata = .);
+
 /*
  * And finally the bss
  */
diff --git a/arch/powerpc/kvm/booke_interrupts.S b/arch/powerpc/kvm/booke_interrupts.S
index d0c6f841bbd1..380a78cf484d 100644
--- a/arch/powerpc/kvm/booke_interrupts.S
+++ b/arch/powerpc/kvm/booke_interrupts.S
@@ -56,8 +56,8 @@
 .macro KVM_HANDLER ivor_nr
 _GLOBAL(kvmppc_handler_\ivor_nr)
         /* Get pointer to vcpu and record exit number. */
-        mtspr   SPRN_SPRG0, r4
-        mfspr   r4, SPRN_SPRG1
+        mtspr   SPRN_SPRG_WSCRATCH0, r4
+        mfspr   r4, SPRN_SPRG_RVCPU
         stw     r5, VCPU_GPR(r5)(r4)
         stw     r6, VCPU_GPR(r6)(r4)
         mfctr   r5
@@ -95,7 +95,7 @@ _GLOBAL(kvmppc_handler_len)
 
 
 /* Registers:
- *  SPRG0: guest r4
+ *  SPRG_SCRATCH0: guest r4
  *  r4: vcpu pointer
  *  r5: KVM exit number
  */
@@ -181,7 +181,7 @@ _GLOBAL(kvmppc_resume_host)
         stw     r3, VCPU_LR(r4)
         mfxer   r3
         stw     r3, VCPU_XER(r4)
-        mfspr   r3, SPRN_SPRG0
+        mfspr   r3, SPRN_SPRG_RSCRATCH0
         stw     r3, VCPU_GPR(r4)(r4)
         mfspr   r3, SPRN_SRR0
         stw     r3, VCPU_PC(r4)
@@ -374,7 +374,7 @@ lightweight_exit:
         mtspr   SPRN_IVPR, r8
 
         /* Save vcpu pointer for the exception handlers. */
-        mtspr   SPRN_SPRG1, r4
+        mtspr   SPRN_SPRG_WVCPU, r4
 
         /* Can't switch the stack pointer until after IVPR is switched,
          * because host interrupt handlers would get confused. */
@@ -384,13 +384,13 @@ lightweight_exit:
         /* Host interrupt handlers may have clobbered these guest-readable
          * SPRGs, so we need to reload them here with the guest's values. */
         lwz     r3, VCPU_SPRG4(r4)
-        mtspr   SPRN_SPRG4, r3
+        mtspr   SPRN_SPRG4W, r3
         lwz     r3, VCPU_SPRG5(r4)
-        mtspr   SPRN_SPRG5, r3
+        mtspr   SPRN_SPRG5W, r3
         lwz     r3, VCPU_SPRG6(r4)
-        mtspr   SPRN_SPRG6, r3
+        mtspr   SPRN_SPRG6W, r3
         lwz     r3, VCPU_SPRG7(r4)
-        mtspr   SPRN_SPRG7, r3
+        mtspr   SPRN_SPRG7W, r3
 
 #ifdef CONFIG_KVM_EXIT_TIMING
         /* save enter time */
diff --git a/arch/powerpc/mm/Makefile b/arch/powerpc/mm/Makefile
index 3e68363405b7..6fb8fc8d2fea 100644
--- a/arch/powerpc/mm/Makefile
+++ b/arch/powerpc/mm/Makefile
@@ -13,6 +13,7 @@ obj-y				:= fault.o mem.o pgtable.o gup.o \
                                    pgtable_$(CONFIG_WORD_SIZE).o
 obj-$(CONFIG_PPC_MMU_NOHASH)    += mmu_context_nohash.o tlb_nohash.o \
                                    tlb_nohash_low.o
+obj-$(CONFIG_PPC_BOOK3E)        += tlb_low_$(CONFIG_WORD_SIZE)e.o
 obj-$(CONFIG_PPC64)             += mmap_64.o
 hash64-$(CONFIG_PPC_NATIVE)     := hash_native_64.o
 obj-$(CONFIG_PPC_STD_MMU_64)    += hash_utils_64.o \
diff --git a/arch/powerpc/mm/fsl_booke_mmu.c b/arch/powerpc/mm/fsl_booke_mmu.c
index bb3d65998e6b..dc93e95b256e 100644
--- a/arch/powerpc/mm/fsl_booke_mmu.c
+++ b/arch/powerpc/mm/fsl_booke_mmu.c
@@ -161,7 +161,7 @@ unsigned long __init mmu_mapin_ram(void)
         unsigned long virt = PAGE_OFFSET;
         phys_addr_t phys = memstart_addr;
 
-        while (cam[tlbcam_index] && tlbcam_index < ARRAY_SIZE(cam)) {
+        while (tlbcam_index < ARRAY_SIZE(cam) && cam[tlbcam_index]) {
                 settlbcam(tlbcam_index, virt, phys, cam[tlbcam_index], PAGE_KERNEL_X, 0);
                 virt += cam[tlbcam_index];
                 phys += cam[tlbcam_index];
diff --git a/arch/powerpc/mm/hash_low_32.S b/arch/powerpc/mm/hash_low_32.S
index 14af8cedab70..b13d58932bf6 100644
--- a/arch/powerpc/mm/hash_low_32.S
+++ b/arch/powerpc/mm/hash_low_32.S
@@ -40,7 +40,7 @@ mmu_hash_lock:
  * The address is in r4, and r3 contains an access flag:
  * _PAGE_RW (0x400) if a write.
  * r9 contains the SRR1 value, from which we use the MSR_PR bit.
- * SPRG3 contains the physical address of the current task's thread.
+ * SPRG_THREAD contains the physical address of the current task's thread.
  *
  * Returns to the caller if the access is illegal or there is no
  * mapping for the address.  Otherwise it places an appropriate PTE
@@ -68,7 +68,7 @@ _GLOBAL(hash_page)
         /* Get PTE (linux-style) and check access */
         lis     r0,KERNELBASE@h         /* check if kernel address */
         cmplw   0,r4,r0
-        mfspr   r8,SPRN_SPRG3           /* current task's THREAD (phys) */
+        mfspr   r8,SPRN_SPRG_THREAD     /* current task's THREAD (phys) */
         ori     r3,r3,_PAGE_USER|_PAGE_PRESENT /* test low addresses as user */
         lwz     r5,PGDIR(r8)            /* virt page-table root */
         blt+    112f                    /* assume user more likely */
diff --git a/arch/powerpc/mm/hugetlbpage.c b/arch/powerpc/mm/hugetlbpage.c
index c46ef2ffa3d9..90df6ffe3a43 100644
--- a/arch/powerpc/mm/hugetlbpage.c
+++ b/arch/powerpc/mm/hugetlbpage.c
@@ -57,8 +57,10 @@ unsigned int mmu_huge_psizes[MMU_PAGE_COUNT] = { }; /* initialize all to 0 */
 #define HUGEPTE_CACHE_NAME(psize)       (huge_pgtable_cache_name[psize])
 
 static const char *huge_pgtable_cache_name[MMU_PAGE_COUNT] = {
-        "unused_4K", "hugepte_cache_64K", "unused_64K_AP",
-        "hugepte_cache_1M", "hugepte_cache_16M", "hugepte_cache_16G"
+        [MMU_PAGE_64K]  = "hugepte_cache_64K",
+        [MMU_PAGE_1M]   = "hugepte_cache_1M",
+        [MMU_PAGE_16M]  = "hugepte_cache_16M",
+        [MMU_PAGE_16G]  = "hugepte_cache_16G",
 };
 
 /* Flag to mark huge PD pointers.  This means pmd_bad() and pud_bad()
@@ -700,6 +702,8 @@ static void __init set_huge_psize(int psize)
                 if (mmu_huge_psizes[psize] ||
                    mmu_psize_defs[psize].shift == PAGE_SHIFT)
                         return;
+                if (WARN_ON(HUGEPTE_CACHE_NAME(psize) == NULL))
+                        return;
                 hugetlb_add_hstate(mmu_psize_defs[psize].shift - PAGE_SHIFT);
 
                 switch (mmu_psize_defs[psize].shift) {
diff --git a/arch/powerpc/mm/init_32.c b/arch/powerpc/mm/init_32.c
index 3de6a0d93824..3ef5084b90ca 100644
--- a/arch/powerpc/mm/init_32.c
+++ b/arch/powerpc/mm/init_32.c
@@ -54,8 +54,6 @@
 #endif
 #define MAX_LOW_MEM     CONFIG_LOWMEM_SIZE
 
-DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
-
 phys_addr_t total_memory;
 phys_addr_t total_lowmem;
 
diff --git a/arch/powerpc/mm/init_64.c b/arch/powerpc/mm/init_64.c
index 68a821add28d..31582329cd67 100644
--- a/arch/powerpc/mm/init_64.c
+++ b/arch/powerpc/mm/init_64.c
@@ -205,6 +205,47 @@ static int __meminit vmemmap_populated(unsigned long start, int page_size)
         return 0;
 }
 
+/* On hash-based CPUs, the vmemmap is bolted in the hash table.
+ *
+ * On Book3E CPUs, the vmemmap is currently mapped in the top half of
+ * the vmalloc space using normal page tables, though the size of
+ * pages encoded in the PTEs can be different
+ */
+
+#ifdef CONFIG_PPC_BOOK3E
+static void __meminit vmemmap_create_mapping(unsigned long start,
+                                             unsigned long page_size,
+                                             unsigned long phys)
+{
+        /* Create a PTE encoding without page size */
+        unsigned long i, flags = _PAGE_PRESENT | _PAGE_ACCESSED |
+                _PAGE_KERNEL_RW;
+
+        /* PTEs only contain page size encodings up to 32M */
+        BUG_ON(mmu_psize_defs[mmu_vmemmap_psize].enc > 0xf);
+
+        /* Encode the size in the PTE */
+        flags |= mmu_psize_defs[mmu_vmemmap_psize].enc << 8;
+
+        /* For each PTE for that area, map things. Note that we don't
+         * increment phys because all PTEs are of the large size and
+         * thus must have the low bits clear
+         */
+        for (i = 0; i < page_size; i += PAGE_SIZE)
+                BUG_ON(map_kernel_page(start + i, phys, flags));
+}
+#else /* CONFIG_PPC_BOOK3E */
+static void __meminit vmemmap_create_mapping(unsigned long start,
+                                             unsigned long page_size,
+                                             unsigned long phys)
+{
+        int  mapped = htab_bolt_mapping(start, start + page_size, phys,
+                                        PAGE_KERNEL, mmu_vmemmap_psize,
+                                        mmu_kernel_ssize);
+        BUG_ON(mapped < 0);
+}
+#endif /* CONFIG_PPC_BOOK3E */
+
 int __meminit vmemmap_populate(struct page *start_page,
                                unsigned long nr_pages, int node)
 {
@@ -215,8 +256,11 @@ int __meminit vmemmap_populate(struct page *start_page,
         /* Align to the page size of the linear mapping. */
         start = _ALIGN_DOWN(start, page_size);
 
+        pr_debug("vmemmap_populate page %p, %ld pages, node %d\n",
+                 start_page, nr_pages, node);
+        pr_debug(" -> map %lx..%lx\n", start, end);
+
         for (; start < end; start += page_size) {
-                int mapped;
                 void *p;
 
                 if (vmemmap_populated(start, page_size))
@@ -226,13 +270,10 @@ int __meminit vmemmap_populate(struct page *start_page,
                 if (!p)
                         return -ENOMEM;
 
-                pr_debug("vmemmap %08lx allocated at %p, physical %08lx.\n",
-                        start, p, __pa(p));
+                pr_debug("      * %016lx..%016lx allocated at %p\n",
+                         start, start + page_size, p);
 
-                mapped = htab_bolt_mapping(start, start + page_size, __pa(p),
-                                           pgprot_val(PAGE_KERNEL),
-                                           mmu_vmemmap_psize, mmu_kernel_ssize);
-                BUG_ON(mapped < 0);
+                vmemmap_create_mapping(start, page_size, __pa(p));
         }
 
         return 0;
diff --git a/arch/powerpc/mm/mmu_context_nohash.c b/arch/powerpc/mm/mmu_context_nohash.c
index b1a727def15b..c2f93dc470e6 100644
--- a/arch/powerpc/mm/mmu_context_nohash.c
+++ b/arch/powerpc/mm/mmu_context_nohash.c
@@ -25,10 +25,20 @@
  *     also clear mm->cpu_vm_mask bits when processes are migrated
  */
 
-#undef DEBUG
-#define DEBUG_STEAL_ONLY
-#undef DEBUG_MAP_CONSISTENCY
-/*#define DEBUG_CLAMP_LAST_CONTEXT   15 */
+#define DEBUG_MAP_CONSISTENCY
+#define DEBUG_CLAMP_LAST_CONTEXT   31
+//#define DEBUG_HARDER
+
+/* We don't use DEBUG because it tends to be compiled in always nowadays
+ * and this would generate way too much output
+ */
+#ifdef DEBUG_HARDER
+#define pr_hard(args...)        printk(KERN_DEBUG args)
+#define pr_hardcont(args...)    printk(KERN_CONT args)
+#else
+#define pr_hard(args...)        do { } while(0)
+#define pr_hardcont(args...)    do { } while(0)
+#endif
 
 #include <linux/kernel.h>
 #include <linux/mm.h>
@@ -71,7 +81,7 @@ static DEFINE_SPINLOCK(context_lock);
 static unsigned int steal_context_smp(unsigned int id)
 {
         struct mm_struct *mm;
-        unsigned int cpu, max;
+        unsigned int cpu, max, i;
 
         max = last_context - first_context;
 
@@ -89,15 +99,22 @@ static unsigned int steal_context_smp(unsigned int id)
                                 id = first_context;
                         continue;
                 }
-                pr_devel("[%d] steal context %d from mm @%p\n",
-                         smp_processor_id(), id, mm);
+                pr_hardcont(" | steal %d from 0x%p", id, mm);
 
                 /* Mark this mm has having no context anymore */
                 mm->context.id = MMU_NO_CONTEXT;
 
-                /* Mark it stale on all CPUs that used this mm */
-                for_each_cpu(cpu, mm_cpumask(mm))
-                        __set_bit(id, stale_map[cpu]);
+                /* Mark it stale on all CPUs that used this mm. For threaded
+                 * implementations, we set it on all threads on each core
+                 * represented in the mask. A future implementation will use
+                 * a core map instead but this will do for now.
+                 */
+                for_each_cpu(cpu, mm_cpumask(mm)) {
+                        for (i = cpu_first_thread_in_core(cpu);
+                             i <= cpu_last_thread_in_core(cpu); i++)
+                                __set_bit(id, stale_map[i]);
+                        cpu = i - 1;
+                }
                 return id;
         }
 
@@ -126,7 +143,7 @@ static unsigned int steal_context_up(unsigned int id)
         /* Pick up the victim mm */
         mm = context_mm[id];
 
-        pr_devel("[%d] steal context %d from mm @%p\n", cpu, id, mm);
+        pr_hardcont(" | steal %d from 0x%p", id, mm);
 
         /* Flush the TLB for that context */
         local_flush_tlb_mm(mm);
@@ -173,25 +190,20 @@ static void context_check_map(void) { }
 
 void switch_mmu_context(struct mm_struct *prev, struct mm_struct *next)
 {
-        unsigned int id, cpu = smp_processor_id();
+        unsigned int i, id, cpu = smp_processor_id();
         unsigned long *map;
 
         /* No lockless fast path .. yet */
         spin_lock(&context_lock);
 
-#ifndef DEBUG_STEAL_ONLY
-        pr_devel("[%d] activating context for mm @%p, active=%d, id=%d\n",
-                 cpu, next, next->context.active, next->context.id);
-#endif
+        pr_hard("[%d] activating context for mm @%p, active=%d, id=%d",
+                cpu, next, next->context.active, next->context.id);
 
 #ifdef CONFIG_SMP
         /* Mark us active and the previous one not anymore */
         next->context.active++;
         if (prev) {
-#ifndef DEBUG_STEAL_ONLY
-                pr_devel(" old context %p active was: %d\n",
-                         prev, prev->context.active);
-#endif
+                pr_hardcont(" (old=0x%p a=%d)", prev, prev->context.active);
                 WARN_ON(prev->context.active < 1);
                 prev->context.active--;
         }
@@ -201,8 +213,14 @@ void switch_mmu_context(struct mm_struct *prev, struct mm_struct *next)
 
         /* If we already have a valid assigned context, skip all that */
         id = next->context.id;
-        if (likely(id != MMU_NO_CONTEXT))
+        if (likely(id != MMU_NO_CONTEXT)) {
+#ifdef DEBUG_MAP_CONSISTENCY
+                if (context_mm[id] != next)
+                        pr_err("MMU: mm 0x%p has id %d but context_mm[%d] says 0x%p\n",
+                               next, id, id, context_mm[id]);
+#endif
                 goto ctxt_ok;
+        }
 
         /* We really don't have a context, let's try to acquire one */
         id = next_context;
@@ -235,11 +253,7 @@ void switch_mmu_context(struct mm_struct *prev, struct mm_struct *next)
         next_context = id + 1;
         context_mm[id] = next;
         next->context.id = id;
-
-#ifndef DEBUG_STEAL_ONLY
-        pr_devel("[%d] picked up new id %d, nrf is now %d\n",
-                 cpu, id, nr_free_contexts);
-#endif
+        pr_hardcont(" | new id=%d,nrf=%d", id, nr_free_contexts);
 
         context_check_map();
  ctxt_ok:
@@ -248,15 +262,21 @@ void switch_mmu_context(struct mm_struct *prev, struct mm_struct *next)
          * local TLB for it and unmark it before we use it
          */
         if (test_bit(id, stale_map[cpu])) {
-                pr_devel("[%d] flushing stale context %d for mm @%p !\n",
-                         cpu, id, next);
+                pr_hardcont(" | stale flush %d [%d..%d]",
+                            id, cpu_first_thread_in_core(cpu),
+                            cpu_last_thread_in_core(cpu));
+
                 local_flush_tlb_mm(next);
 
                 /* XXX This clear should ultimately be part of local_flush_tlb_mm */
-                __clear_bit(id, stale_map[cpu]);
+                for (i = cpu_first_thread_in_core(cpu);
+                     i <= cpu_last_thread_in_core(cpu); i++) {
+                        __clear_bit(id, stale_map[i]);
+                }
         }
 
         /* Flick the MMU and release lock */
+        pr_hardcont(" -> %d\n", id);
         set_context(id, next->pgd);
         spin_unlock(&context_lock);
 }
@@ -266,6 +286,8 @@ void switch_mmu_context(struct mm_struct *prev, struct mm_struct *next)
  */
 int init_new_context(struct task_struct *t, struct mm_struct *mm)
 {
+        pr_hard("initing context for mm @%p\n", mm);
+
         mm->context.id = MMU_NO_CONTEXT;
         mm->context.active = 0;
 
@@ -305,7 +327,9 @@ static int __cpuinit mmu_context_cpu_notify(struct notifier_block *self,
                                             unsigned long action, void *hcpu)
 {
         unsigned int cpu = (unsigned int)(long)hcpu;
-
+#ifdef CONFIG_HOTPLUG_CPU
+        struct task_struct *p;
+#endif
         /* We don't touch CPU 0 map, it's allocated at aboot and kept
          * around forever
          */
@@ -324,8 +348,16 @@ static int __cpuinit mmu_context_cpu_notify(struct notifier_block *self,
                 pr_devel("MMU: Freeing stale context map for CPU %d\n", cpu);
                 kfree(stale_map[cpu]);
                 stale_map[cpu] = NULL;
-                break;
-#endif
+
+                /* We also clear the cpu_vm_mask bits of CPUs going away */
+                read_lock(&tasklist_lock);
+                for_each_process(p) {
+                        if (p->mm)
+                                cpu_mask_clear_cpu(cpu, mm_cpumask(p->mm));
+                }
+                read_unlock(&tasklist_lock);
+        break;
+#endif /* CONFIG_HOTPLUG_CPU */
         }
         return NOTIFY_OK;
 }
diff --git a/arch/powerpc/mm/mmu_decl.h b/arch/powerpc/mm/mmu_decl.h
index d1f9c62dc177..d2e5321d5ea6 100644
--- a/arch/powerpc/mm/mmu_decl.h
+++ b/arch/powerpc/mm/mmu_decl.h
@@ -36,21 +36,37 @@ static inline void _tlbil_pid(unsigned int pid)
 {
         asm volatile ("sync; tlbia; isync" : : : "memory");
 }
+#define _tlbil_pid_noind(pid)   _tlbil_pid(pid)
+
 #else /* CONFIG_40x || CONFIG_8xx */
 extern void _tlbil_all(void);
 extern void _tlbil_pid(unsigned int pid);
+#ifdef CONFIG_PPC_BOOK3E
+extern void _tlbil_pid_noind(unsigned int pid);
+#else
+#define _tlbil_pid_noind(pid)   _tlbil_pid(pid)
+#endif
 #endif /* !(CONFIG_40x || CONFIG_8xx) */
 
 /*
  * On 8xx, we directly inline tlbie, on others, it's extern
  */
 #ifdef CONFIG_8xx
-static inline void _tlbil_va(unsigned long address, unsigned int pid)
+static inline void _tlbil_va(unsigned long address, unsigned int pid,
+                             unsigned int tsize, unsigned int ind)
 {
         asm volatile ("tlbie %0; sync" : : "r" (address) : "memory");
 }
-#else /* CONFIG_8xx */
-extern void _tlbil_va(unsigned long address, unsigned int pid);
+#elif defined(CONFIG_PPC_BOOK3E)
+extern void _tlbil_va(unsigned long address, unsigned int pid,
+                      unsigned int tsize, unsigned int ind);
+#else
+extern void __tlbil_va(unsigned long address, unsigned int pid);
+static inline void _tlbil_va(unsigned long address, unsigned int pid,
+                             unsigned int tsize, unsigned int ind)
+{
+        __tlbil_va(address, pid);
+}
 #endif /* CONIFG_8xx */
 
 /*
@@ -58,10 +74,16 @@ extern void _tlbil_va(unsigned long address, unsigned int pid);
  * implementation. When that becomes the case, this will be
  * an extern.
  */
-static inline void _tlbivax_bcast(unsigned long address, unsigned int pid)
+#ifdef CONFIG_PPC_BOOK3E
+extern void _tlbivax_bcast(unsigned long address, unsigned int pid,
+                           unsigned int tsize, unsigned int ind);
+#else
+static inline void _tlbivax_bcast(unsigned long address, unsigned int pid,
+                                   unsigned int tsize, unsigned int ind)
 {
         BUG();
 }
+#endif
 
 #else /* CONFIG_PPC_MMU_NOHASH */
 
@@ -99,7 +121,12 @@ extern unsigned int rtas_data, rtas_size;
 struct hash_pte;
 extern struct hash_pte *Hash, *Hash_end;
 extern unsigned long Hash_size, Hash_mask;
-#endif
+
+#endif /* CONFIG_PPC32 */
+
+#ifdef CONFIG_PPC64
+extern int map_kernel_page(unsigned long ea, unsigned long pa, int flags);
+#endif /* CONFIG_PPC64 */
 
 extern unsigned long ioremap_bot;
 extern unsigned long __max_low_memory;
diff --git a/arch/powerpc/mm/pgtable.c b/arch/powerpc/mm/pgtable.c
index 627767d6169b..b6b32487e740 100644
--- a/arch/powerpc/mm/pgtable.c
+++ b/arch/powerpc/mm/pgtable.c
@@ -30,6 +30,16 @@
 #include <asm/tlbflush.h>
 #include <asm/tlb.h>
 
+DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
+
+#ifdef CONFIG_SMP
+
+/*
+ * Handle batching of page table freeing on SMP. Page tables are
+ * queued up and send to be freed later by RCU in order to avoid
+ * freeing a page table page that is being walked without locks
+ */
+
 static DEFINE_PER_CPU(struct pte_freelist_batch *, pte_freelist_cur);
 static unsigned long pte_freelist_forced_free;
 
@@ -116,6 +126,8 @@ void pte_free_finish(void)
         *batchp = NULL;
 }
 
+#endif /* CONFIG_SMP */
+
 /*
  * Handle i/d cache flushing, called from set_pte_at() or ptep_set_access_flags()
  */
@@ -242,7 +254,7 @@ void assert_pte_locked(struct mm_struct *mm, unsigned long addr)
         BUG_ON(pud_none(*pud));
         pmd = pmd_offset(pud, addr);
         BUG_ON(!pmd_present(*pmd));
-        BUG_ON(!spin_is_locked(pte_lockptr(mm, pmd)));
+        assert_spin_locked(pte_lockptr(mm, pmd));
 }
 #endif /* CONFIG_DEBUG_VM */
 
diff --git a/arch/powerpc/mm/pgtable_64.c b/arch/powerpc/mm/pgtable_64.c
index bfa7db6b2fd5..853d5565eed5 100644
--- a/arch/powerpc/mm/pgtable_64.c
+++ b/arch/powerpc/mm/pgtable_64.c
@@ -33,6 +33,8 @@
 #include <linux/stddef.h>
 #include <linux/vmalloc.h>
 #include <linux/init.h>
+#include <linux/bootmem.h>
+#include <linux/lmb.h>
 
 #include <asm/pgalloc.h>
 #include <asm/page.h>
@@ -55,19 +57,36 @@
 
 unsigned long ioremap_bot = IOREMAP_BASE;
 
+
+#ifdef CONFIG_PPC_MMU_NOHASH
+static void *early_alloc_pgtable(unsigned long size)
+{
+        void *pt;
+
+        if (init_bootmem_done)
+                pt = __alloc_bootmem(size, size, __pa(MAX_DMA_ADDRESS));
+        else
+                pt = __va(lmb_alloc_base(size, size,
+                                         __pa(MAX_DMA_ADDRESS)));
+        memset(pt, 0, size);
+
+        return pt;
+}
+#endif /* CONFIG_PPC_MMU_NOHASH */
+
 /*
- * map_io_page currently only called by __ioremap
- * map_io_page adds an entry to the ioremap page table
+ * map_kernel_page currently only called by __ioremap
+ * map_kernel_page adds an entry to the ioremap page table
  * and adds an entry to the HPT, possibly bolting it
  */
-static int map_io_page(unsigned long ea, unsigned long pa, int flags)
+int map_kernel_page(unsigned long ea, unsigned long pa, int flags)
 {
         pgd_t *pgdp;
         pud_t *pudp;
         pmd_t *pmdp;
         pte_t *ptep;
 
-        if (mem_init_done) {
+        if (slab_is_available()) {
                 pgdp = pgd_offset_k(ea);
                 pudp = pud_alloc(&init_mm, pgdp, ea);
                 if (!pudp)
@@ -81,6 +100,35 @@ static int map_io_page(unsigned long ea, unsigned long pa, int flags)
                 set_pte_at(&init_mm, ea, ptep, pfn_pte(pa >> PAGE_SHIFT,
                                                           __pgprot(flags)));
         } else {
+#ifdef CONFIG_PPC_MMU_NOHASH
+                /* Warning ! This will blow up if bootmem is not initialized
+                 * which our ppc64 code is keen to do that, we'll need to
+                 * fix it and/or be more careful
+                 */
+                pgdp = pgd_offset_k(ea);
+#ifdef PUD_TABLE_SIZE
+                if (pgd_none(*pgdp)) {
+                        pudp = early_alloc_pgtable(PUD_TABLE_SIZE);
+                        BUG_ON(pudp == NULL);
+                        pgd_populate(&init_mm, pgdp, pudp);
+                }
+#endif /* PUD_TABLE_SIZE */
+                pudp = pud_offset(pgdp, ea);
+                if (pud_none(*pudp)) {
+                        pmdp = early_alloc_pgtable(PMD_TABLE_SIZE);
+                        BUG_ON(pmdp == NULL);
+                        pud_populate(&init_mm, pudp, pmdp);
+                }
+                pmdp = pmd_offset(pudp, ea);
+                if (!pmd_present(*pmdp)) {
+                        ptep = early_alloc_pgtable(PAGE_SIZE);
+                        BUG_ON(ptep == NULL);
+                        pmd_populate_kernel(&init_mm, pmdp, ptep);
+                }
+                ptep = pte_offset_kernel(pmdp, ea);
+                set_pte_at(&init_mm, ea, ptep, pfn_pte(pa >> PAGE_SHIFT,
+                                                          __pgprot(flags)));
+#else /* CONFIG_PPC_MMU_NOHASH */
                 /*
                  * If the mm subsystem is not fully up, we cannot create a
                  * linux page table entry for this mapping.  Simply bolt an
@@ -93,6 +141,7 @@ static int map_io_page(unsigned long ea, unsigned long pa, int flags)
                                "memory at %016lx !\n", pa);
                         return -ENOMEM;
                 }
+#endif /* !CONFIG_PPC_MMU_NOHASH */
         }
         return 0;
 }
@@ -124,7 +173,7 @@ void __iomem * __ioremap_at(phys_addr_t pa, void *ea, unsigned long size,
         WARN_ON(size & ~PAGE_MASK);
 
         for (i = 0; i < size; i += PAGE_SIZE)
-                if (map_io_page((unsigned long)ea+i, pa+i, flags))
+                if (map_kernel_page((unsigned long)ea+i, pa+i, flags))
                         return NULL;
 
         return (void __iomem *)ea;
diff --git a/arch/powerpc/mm/slb.c b/arch/powerpc/mm/slb.c
index a685652effeb..07961c5c169e 100644
--- a/arch/powerpc/mm/slb.c
+++ b/arch/powerpc/mm/slb.c
@@ -191,7 +191,7 @@ void switch_slb(struct task_struct *tsk, struct mm_struct *mm)
         unsigned long slbie_data = 0;
         unsigned long pc = KSTK_EIP(tsk);
         unsigned long stack = KSTK_ESP(tsk);
-        unsigned long unmapped_base;
+        unsigned long exec_base;
 
         /*
          * We need interrupts hard-disabled here, not just soft-disabled,
@@ -227,29 +227,23 @@ void switch_slb(struct task_struct *tsk, struct mm_struct *mm)
 
         /*
          * preload some userspace segments into the SLB.
+         * Almost all 32 and 64bit PowerPC executables are linked at
+         * 0x10000000 so it makes sense to preload this segment.
          */
-        if (test_tsk_thread_flag(tsk, TIF_32BIT))
-                unmapped_base = TASK_UNMAPPED_BASE_USER32;
-        else
-                unmapped_base = TASK_UNMAPPED_BASE_USER64;
+        exec_base = 0x10000000;
 
-        if (is_kernel_addr(pc))
-                return;
-        slb_allocate(pc);
-
-        if (esids_match(pc,stack))
+        if (is_kernel_addr(pc) || is_kernel_addr(stack) ||
+            is_kernel_addr(exec_base))
                 return;
 
-        if (is_kernel_addr(stack))
-                return;
-        slb_allocate(stack);
+        slb_allocate(pc);
 
-        if (esids_match(pc,unmapped_base) || esids_match(stack,unmapped_base))
-                return;
+        if (!esids_match(pc, stack))
+                slb_allocate(stack);
 
-        if (is_kernel_addr(unmapped_base))
-                return;
-        slb_allocate(unmapped_base);
+        if (!esids_match(pc, exec_base) &&
+            !esids_match(stack, exec_base))
+                slb_allocate(exec_base);
 }
 
 static inline void patch_slb_encoding(unsigned int *insn_addr,
diff --git a/arch/powerpc/mm/tlb_hash32.c b/arch/powerpc/mm/tlb_hash32.c
index 65190587a365..8aaa8b7eb324 100644
--- a/arch/powerpc/mm/tlb_hash32.c
+++ b/arch/powerpc/mm/tlb_hash32.c
@@ -71,6 +71,9 @@ void tlb_flush(struct mmu_gather *tlb)
                  */
                 _tlbia();
         }
+
+        /* Push out batch of freed page tables */
+        pte_free_finish();
 }
 
 /*
diff --git a/arch/powerpc/mm/tlb_hash64.c b/arch/powerpc/mm/tlb_hash64.c
index 937eb90677d9..2b2f35f6985e 100644
--- a/arch/powerpc/mm/tlb_hash64.c
+++ b/arch/powerpc/mm/tlb_hash64.c
@@ -33,11 +33,6 @@
 
 DEFINE_PER_CPU(struct ppc64_tlb_batch, ppc64_tlb_batch);
 
-/* This is declared as we are using the more or less generic
- * arch/powerpc/include/asm/tlb.h file -- tgall
- */
-DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
-
 /*
  * A linux PTE was changed and the corresponding hash table entry
  * neesd to be flushed. This function will either perform the flush
@@ -154,6 +149,21 @@ void __flush_tlb_pending(struct ppc64_tlb_batch *batch)
         batch->index = 0;
 }
 
+void tlb_flush(struct mmu_gather *tlb)
+{
+        struct ppc64_tlb_batch *tlbbatch = &__get_cpu_var(ppc64_tlb_batch);
+
+        /* If there's a TLB batch pending, then we must flush it because the
+         * pages are going to be freed and we really don't want to have a CPU
+         * access a freed page because it has a stale TLB
+         */
+        if (tlbbatch->index)
+                __flush_tlb_pending(tlbbatch);
+
+        /* Push out batch of freed page tables */
+        pte_free_finish();
+}
+
 /**
  * __flush_hash_table_range - Flush all HPTEs for a given address range
  *                            from the hash table (and the TLB). But keeps
diff --git a/arch/powerpc/mm/tlb_low_64e.S b/arch/powerpc/mm/tlb_low_64e.S
new file mode 100644
index 000000000000..10d524ded7b2
--- /dev/null
+++ b/arch/powerpc/mm/tlb_low_64e.S
@@ -0,0 +1,734 @@
+/*
+ *  Low leve TLB miss handlers for Book3E
+ *
+ *  Copyright (C) 2008-2009
+ *      Ben. Herrenschmidt (benh@kernel.crashing.org), IBM Corp.
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  as published by the Free Software Foundation; either version
+ *  2 of the License, or (at your option) any later version.
+ */
+
+#include <asm/processor.h>
+#include <asm/reg.h>
+#include <asm/page.h>
+#include <asm/mmu.h>
+#include <asm/ppc_asm.h>
+#include <asm/asm-offsets.h>
+#include <asm/cputable.h>
+#include <asm/pgtable.h>
+#include <asm/reg.h>
+#include <asm/exception-64e.h>
+#include <asm/ppc-opcode.h>
+
+#ifdef CONFIG_PPC_64K_PAGES
+#define VPTE_PMD_SHIFT  (PTE_INDEX_SIZE+1)
+#else
+#define VPTE_PMD_SHIFT  (PTE_INDEX_SIZE)
+#endif
+#define VPTE_PUD_SHIFT  (VPTE_PMD_SHIFT + PMD_INDEX_SIZE)
+#define VPTE_PGD_SHIFT  (VPTE_PUD_SHIFT + PUD_INDEX_SIZE)
+#define VPTE_INDEX_SIZE (VPTE_PGD_SHIFT + PGD_INDEX_SIZE)
+
+
+/**********************************************************************
+ *                                                                    *
+ * TLB miss handling for Book3E with TLB reservation and HES support  *
+ *                                                                    *
+ **********************************************************************/
+
+
+/* Data TLB miss */
+        START_EXCEPTION(data_tlb_miss)
+        TLB_MISS_PROLOG
+
+        /* Now we handle the fault proper. We only save DEAR in normal
+         * fault case since that's the only interesting values here.
+         * We could probably also optimize by not saving SRR0/1 in the
+         * linear mapping case but I'll leave that for later
+         */
+        mfspr   r14,SPRN_ESR
+        mfspr   r16,SPRN_DEAR           /* get faulting address */
+        srdi    r15,r16,60              /* get region */
+        cmpldi  cr0,r15,0xc             /* linear mapping ? */
+        TLB_MISS_STATS_SAVE_INFO
+        beq     tlb_load_linear         /* yes -> go to linear map load */
+
+        /* The page tables are mapped virtually linear. At this point, though,
+         * we don't know whether we are trying to fault in a first level
+         * virtual address or a virtual page table address. We can get that
+         * from bit 0x1 of the region ID which we have set for a page table
+         */
+        andi.   r10,r15,0x1
+        bne-    virt_page_table_tlb_miss
+
+        std     r14,EX_TLB_ESR(r12);    /* save ESR */
+        std     r16,EX_TLB_DEAR(r12);   /* save DEAR */
+
+         /* We need _PAGE_PRESENT and  _PAGE_ACCESSED set */
+        li      r11,_PAGE_PRESENT
+        oris    r11,r11,_PAGE_ACCESSED@h
+
+        /* We do the user/kernel test for the PID here along with the RW test
+         */
+        cmpldi  cr0,r15,0               /* Check for user region */
+
+        /* We pre-test some combination of permissions to avoid double
+         * faults:
+         *
+         * We move the ESR:ST bit into the position of _PAGE_BAP_SW in the PTE
+         * ESR_ST   is 0x00800000
+         * _PAGE_BAP_SW is 0x00000010
+         * So the shift is >> 19. This tests for supervisor writeability.
+         * If the page happens to be supervisor writeable and not user
+         * writeable, we will take a new fault later, but that should be
+         * a rare enough case.
+         *
+         * We also move ESR_ST in _PAGE_DIRTY position
+         * _PAGE_DIRTY is 0x00001000 so the shift is >> 11
+         *
+         * MAS1 is preset for all we need except for TID that needs to
+         * be cleared for kernel translations
+         */
+        rlwimi  r11,r14,32-19,27,27
+        rlwimi  r11,r14,32-16,19,19
+        beq     normal_tlb_miss
+        /* XXX replace the RMW cycles with immediate loads + writes */
+1:      mfspr   r10,SPRN_MAS1
+        cmpldi  cr0,r15,8               /* Check for vmalloc region */
+        rlwinm  r10,r10,0,16,1          /* Clear TID */
+        mtspr   SPRN_MAS1,r10
+        beq+    normal_tlb_miss
+
+        /* We got a crappy address, just fault with whatever DEAR and ESR
+         * are here
+         */
+        TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT)
+        TLB_MISS_EPILOG_ERROR
+        b       exc_data_storage_book3e
+
+/* Instruction TLB miss */
+        START_EXCEPTION(instruction_tlb_miss)
+        TLB_MISS_PROLOG
+
+        /* If we take a recursive fault, the second level handler may need
+         * to know whether we are handling a data or instruction fault in
+         * order to get to the right store fault handler. We provide that
+         * info by writing a crazy value in ESR in our exception frame
+         */
+        li      r14,-1  /* store to exception frame is done later */
+
+        /* Now we handle the fault proper. We only save DEAR in the non
+         * linear mapping case since we know the linear mapping case will
+         * not re-enter. We could indeed optimize and also not save SRR0/1
+         * in the linear mapping case but I'll leave that for later
+         *
+         * Faulting address is SRR0 which is already in r16
+         */
+        srdi    r15,r16,60              /* get region */
+        cmpldi  cr0,r15,0xc             /* linear mapping ? */
+        TLB_MISS_STATS_SAVE_INFO
+        beq     tlb_load_linear         /* yes -> go to linear map load */
+
+        /* We do the user/kernel test for the PID here along with the RW test
+         */
+        li      r11,_PAGE_PRESENT|_PAGE_HWEXEC  /* Base perm */
+        oris    r11,r11,_PAGE_ACCESSED@h
+
+        cmpldi  cr0,r15,0                       /* Check for user region */
+        std     r14,EX_TLB_ESR(r12)             /* write crazy -1 to frame */
+        beq     normal_tlb_miss
+        /* XXX replace the RMW cycles with immediate loads + writes */
+1:      mfspr   r10,SPRN_MAS1
+        cmpldi  cr0,r15,8                       /* Check for vmalloc region */
+        rlwinm  r10,r10,0,16,1                  /* Clear TID */
+        mtspr   SPRN_MAS1,r10
+        beq+    normal_tlb_miss
+
+        /* We got a crappy address, just fault */
+        TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT)
+        TLB_MISS_EPILOG_ERROR
+        b       exc_instruction_storage_book3e
+
+/*
+ * This is the guts of the first-level TLB miss handler for direct
+ * misses. We are entered with:
+ *
+ * r16 = faulting address
+ * r15 = region ID
+ * r14 = crap (free to use)
+ * r13 = PACA
+ * r12 = TLB exception frame in PACA
+ * r11 = PTE permission mask
+ * r10 = crap (free to use)
+ */
+normal_tlb_miss:
+        /* So we first construct the page table address. We do that by
+         * shifting the bottom of the address (not the region ID) by
+         * PAGE_SHIFT-3, clearing the bottom 3 bits (get a PTE ptr) and
+         * or'ing the fourth high bit.
+         *
+         * NOTE: For 64K pages, we do things slightly differently in
+         * order to handle the weird page table format used by linux
+         */
+        ori     r10,r15,0x1
+#ifdef CONFIG_PPC_64K_PAGES
+        /* For the top bits, 16 bytes per PTE */
+        rldicl  r14,r16,64-(PAGE_SHIFT-4),PAGE_SHIFT-4+4
+        /* Now create the bottom bits as 0 in position 0x8000 and
+         * the rest calculated for 8 bytes per PTE
+         */
+        rldicl  r15,r16,64-(PAGE_SHIFT-3),64-15
+        /* Insert the bottom bits in */
+        rlwimi  r14,r15,0,16,31
+#else
+        rldicl  r14,r16,64-(PAGE_SHIFT-3),PAGE_SHIFT-3+4
+#endif
+        sldi    r15,r10,60
+        clrrdi  r14,r14,3
+        or      r10,r15,r14
+
+        /* Set the TLB reservation and seach for existing entry. Then load
+         * the entry.
+         */
+        PPC_TLBSRX_DOT(0,r16)
+        ld      r14,0(r10)
+        beq     normal_tlb_miss_done
+
+finish_normal_tlb_miss:
+        /* Check if required permissions are met */
+        andc.   r15,r11,r14
+        bne-    normal_tlb_miss_access_fault
+
+        /* Now we build the MAS:
+         *
+         * MAS 0   :    Fully setup with defaults in MAS4 and TLBnCFG
+         * MAS 1   :    Almost fully setup
+         *               - PID already updated by caller if necessary
+         *               - TSIZE need change if !base page size, not
+         *                 yet implemented for now
+         * MAS 2   :    Defaults not useful, need to be redone
+         * MAS 3+7 :    Needs to be done
+         *
+         * TODO: mix up code below for better scheduling
+         */
+        clrrdi  r11,r16,12              /* Clear low crap in EA */
+        rlwimi  r11,r14,32-19,27,31     /* Insert WIMGE */
+        mtspr   SPRN_MAS2,r11
+
+        /* Check page size, if not standard, update MAS1 */
+        rldicl  r11,r14,64-8,64-8
+#ifdef CONFIG_PPC_64K_PAGES
+        cmpldi  cr0,r11,BOOK3E_PAGESZ_64K
+#else
+        cmpldi  cr0,r11,BOOK3E_PAGESZ_4K
+#endif
+        beq-    1f
+        mfspr   r11,SPRN_MAS1
+        rlwimi  r11,r14,31,21,24
+        rlwinm  r11,r11,0,21,19
+        mtspr   SPRN_MAS1,r11
+1:
+        /* Move RPN in position */
+        rldicr  r11,r14,64-(PTE_RPN_SHIFT-PAGE_SHIFT),63-PAGE_SHIFT
+        clrldi  r15,r11,12              /* Clear crap at the top */
+        rlwimi  r15,r14,32-8,22,25      /* Move in U bits */
+        rlwimi  r15,r14,32-2,26,31      /* Move in BAP bits */
+
+        /* Mask out SW and UW if !DIRTY (XXX optimize this !) */
+        andi.   r11,r14,_PAGE_DIRTY
+        bne     1f
+        li      r11,MAS3_SW|MAS3_UW
+        andc    r15,r15,r11
+1:      mtspr   SPRN_MAS7_MAS3,r15
+
+        tlbwe
+
+normal_tlb_miss_done:
+        /* We don't bother with restoring DEAR or ESR since we know we are
+         * level 0 and just going back to userland. They are only needed
+         * if you are going to take an access fault
+         */
+        TLB_MISS_STATS_X(MMSTAT_TLB_MISS_NORM_OK)
+        TLB_MISS_EPILOG_SUCCESS
+        rfi
+
+normal_tlb_miss_access_fault:
+        /* We need to check if it was an instruction miss */
+        andi.   r10,r11,_PAGE_HWEXEC
+        bne     1f
+        ld      r14,EX_TLB_DEAR(r12)
+        ld      r15,EX_TLB_ESR(r12)
+        mtspr   SPRN_DEAR,r14
+        mtspr   SPRN_ESR,r15
+        TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT)
+        TLB_MISS_EPILOG_ERROR
+        b       exc_data_storage_book3e
+1:      TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT)
+        TLB_MISS_EPILOG_ERROR
+        b       exc_instruction_storage_book3e
+
+
+/*
+ * This is the guts of the second-level TLB miss handler for direct
+ * misses. We are entered with:
+ *
+ * r16 = virtual page table faulting address
+ * r15 = region (top 4 bits of address)
+ * r14 = crap (free to use)
+ * r13 = PACA
+ * r12 = TLB exception frame in PACA
+ * r11 = crap (free to use)
+ * r10 = crap (free to use)
+ *
+ * Note that this should only ever be called as a second level handler
+ * with the current scheme when using SW load.
+ * That means we can always get the original fault DEAR at
+ * EX_TLB_DEAR-EX_TLB_SIZE(r12)
+ *
+ * It can be re-entered by the linear mapping miss handler. However, to
+ * avoid too much complication, it will restart the whole fault at level
+ * 0 so we don't care too much about clobbers
+ *
+ * XXX That code was written back when we couldn't clobber r14. We can now,
+ * so we could probably optimize things a bit
+ */
+virt_page_table_tlb_miss:
+        /* Are we hitting a kernel page table ? */
+        andi.   r10,r15,0x8
+
+        /* The cool thing now is that r10 contains 0 for user and 8 for kernel,
+         * and we happen to have the swapper_pg_dir at offset 8 from the user
+         * pgdir in the PACA :-).
+         */
+        add     r11,r10,r13
+
+        /* If kernel, we need to clear MAS1 TID */
+        beq     1f
+        /* XXX replace the RMW cycles with immediate loads + writes */
+        mfspr   r10,SPRN_MAS1
+        rlwinm  r10,r10,0,16,1                  /* Clear TID */
+        mtspr   SPRN_MAS1,r10
+1:
+        /* Search if we already have a TLB entry for that virtual address, and
+         * if we do, bail out.
+         */
+        PPC_TLBSRX_DOT(0,r16)
+        beq     virt_page_table_tlb_miss_done
+
+        /* Now, we need to walk the page tables. First check if we are in
+         * range.
+         */
+        rldicl. r10,r16,64-(VPTE_INDEX_SIZE+3),VPTE_INDEX_SIZE+3+4
+        bne-    virt_page_table_tlb_miss_fault
+
+        /* Get the PGD pointer */
+        ld      r15,PACAPGD(r11)
+        cmpldi  cr0,r15,0
+        beq-    virt_page_table_tlb_miss_fault
+
+        /* Get to PGD entry */
+        rldicl  r11,r16,64-VPTE_PGD_SHIFT,64-PGD_INDEX_SIZE-3
+        clrrdi  r10,r11,3
+        ldx     r15,r10,r15
+        cmpldi  cr0,r15,0
+        beq     virt_page_table_tlb_miss_fault
+
+#ifndef CONFIG_PPC_64K_PAGES
+        /* Get to PUD entry */
+        rldicl  r11,r16,64-VPTE_PUD_SHIFT,64-PUD_INDEX_SIZE-3
+        clrrdi  r10,r11,3
+        ldx     r15,r10,r15
+        cmpldi  cr0,r15,0
+        beq     virt_page_table_tlb_miss_fault
+#endif /* CONFIG_PPC_64K_PAGES */
+
+        /* Get to PMD entry */
+        rldicl  r11,r16,64-VPTE_PMD_SHIFT,64-PMD_INDEX_SIZE-3
+        clrrdi  r10,r11,3
+        ldx     r15,r10,r15
+        cmpldi  cr0,r15,0
+        beq     virt_page_table_tlb_miss_fault
+
+        /* Ok, we're all right, we can now create a kernel translation for
+         * a 4K or 64K page from r16 -> r15.
+         */
+        /* Now we build the MAS:
+         *
+         * MAS 0   :    Fully setup with defaults in MAS4 and TLBnCFG
+         * MAS 1   :    Almost fully setup
+         *               - PID already updated by caller if necessary
+         *               - TSIZE for now is base page size always
+         * MAS 2   :    Use defaults
+         * MAS 3+7 :    Needs to be done
+         *
+         * So we only do MAS 2 and 3 for now...
+         */
+        clrldi  r11,r15,4               /* remove region ID from RPN */
+        ori     r10,r11,1               /* Or-in SR */
+        mtspr   SPRN_MAS7_MAS3,r10
+
+        tlbwe
+
+virt_page_table_tlb_miss_done:
+
+        /* We have overriden MAS2:EPN but currently our primary TLB miss
+         * handler will always restore it so that should not be an issue,
+         * if we ever optimize the primary handler to not write MAS2 on
+         * some cases, we'll have to restore MAS2:EPN here based on the
+         * original fault's DEAR. If we do that we have to modify the
+         * ITLB miss handler to also store SRR0 in the exception frame
+         * as DEAR.
+         *
+         * However, one nasty thing we did is we cleared the reservation
+         * (well, potentially we did). We do a trick here thus if we
+         * are not a level 0 exception (we interrupted the TLB miss) we
+         * offset the return address by -4 in order to replay the tlbsrx
+         * instruction there
+         */
+        subf    r10,r13,r12
+        cmpldi  cr0,r10,PACA_EXTLB+EX_TLB_SIZE
+        bne-    1f
+        ld      r11,PACA_EXTLB+EX_TLB_SIZE+EX_TLB_SRR0(r13)
+        addi    r10,r11,-4
+        std     r10,PACA_EXTLB+EX_TLB_SIZE+EX_TLB_SRR0(r13)
+1:
+        /* Return to caller, normal case */
+        TLB_MISS_STATS_X(MMSTAT_TLB_MISS_PT_OK);
+        TLB_MISS_EPILOG_SUCCESS
+        rfi
+
+virt_page_table_tlb_miss_fault:
+        /* If we fault here, things are a little bit tricky. We need to call
+         * either data or instruction store fault, and we need to retreive
+         * the original fault address and ESR (for data).
+         *
+         * The thing is, we know that in normal circumstances, this is
+         * always called as a second level tlb miss for SW load or as a first
+         * level TLB miss for HW load, so we should be able to peek at the
+         * relevant informations in the first exception frame in the PACA.
+         *
+         * However, we do need to double check that, because we may just hit
+         * a stray kernel pointer or a userland attack trying to hit those
+         * areas. If that is the case, we do a data fault. (We can't get here
+         * from an instruction tlb miss anyway).
+         *
+         * Note also that when going to a fault, we must unwind the previous
+         * level as well. Since we are doing that, we don't need to clear or
+         * restore the TLB reservation neither.
+         */
+        subf    r10,r13,r12
+        cmpldi  cr0,r10,PACA_EXTLB+EX_TLB_SIZE
+        bne-    virt_page_table_tlb_miss_whacko_fault
+
+        /* We dig the original DEAR and ESR from slot 0 */
+        ld      r15,EX_TLB_DEAR+PACA_EXTLB(r13)
+        ld      r16,EX_TLB_ESR+PACA_EXTLB(r13)
+
+        /* We check for the "special" ESR value for instruction faults */
+        cmpdi   cr0,r16,-1
+        beq     1f
+        mtspr   SPRN_DEAR,r15
+        mtspr   SPRN_ESR,r16
+        TLB_MISS_STATS_D(MMSTAT_TLB_MISS_PT_FAULT);
+        TLB_MISS_EPILOG_ERROR
+        b       exc_data_storage_book3e
+1:      TLB_MISS_STATS_I(MMSTAT_TLB_MISS_PT_FAULT);
+        TLB_MISS_EPILOG_ERROR
+        b       exc_instruction_storage_book3e
+
+virt_page_table_tlb_miss_whacko_fault:
+        /* The linear fault will restart everything so ESR and DEAR will
+         * not have been clobbered, let's just fault with what we have
+         */
+        TLB_MISS_STATS_X(MMSTAT_TLB_MISS_PT_FAULT);
+        TLB_MISS_EPILOG_ERROR
+        b       exc_data_storage_book3e
+
+
+/**************************************************************
+ *                                                            *
+ * TLB miss handling for Book3E with hw page table support    *
+ *                                                            *
+ **************************************************************/
+
+
+/* Data TLB miss */
+        START_EXCEPTION(data_tlb_miss_htw)
+        TLB_MISS_PROLOG
+
+        /* Now we handle the fault proper. We only save DEAR in normal
+         * fault case since that's the only interesting values here.
+         * We could probably also optimize by not saving SRR0/1 in the
+         * linear mapping case but I'll leave that for later
+         */
+        mfspr   r14,SPRN_ESR
+        mfspr   r16,SPRN_DEAR           /* get faulting address */
+        srdi    r11,r16,60              /* get region */
+        cmpldi  cr0,r11,0xc             /* linear mapping ? */
+        TLB_MISS_STATS_SAVE_INFO
+        beq     tlb_load_linear         /* yes -> go to linear map load */
+
+        /* We do the user/kernel test for the PID here along with the RW test
+         */
+        cmpldi  cr0,r11,0               /* Check for user region */
+        ld      r15,PACAPGD(r13)        /* Load user pgdir */
+        beq     htw_tlb_miss
+
+        /* XXX replace the RMW cycles with immediate loads + writes */
+1:      mfspr   r10,SPRN_MAS1
+        cmpldi  cr0,r11,8               /* Check for vmalloc region */
+        rlwinm  r10,r10,0,16,1          /* Clear TID */
+        mtspr   SPRN_MAS1,r10
+        ld      r15,PACA_KERNELPGD(r13) /* Load kernel pgdir */
+        beq+    htw_tlb_miss
+
+        /* We got a crappy address, just fault with whatever DEAR and ESR
+         * are here
+         */
+        TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT)
+        TLB_MISS_EPILOG_ERROR
+        b       exc_data_storage_book3e
+
+/* Instruction TLB miss */
+        START_EXCEPTION(instruction_tlb_miss_htw)
+        TLB_MISS_PROLOG
+
+        /* If we take a recursive fault, the second level handler may need
+         * to know whether we are handling a data or instruction fault in
+         * order to get to the right store fault handler. We provide that
+         * info by keeping a crazy value for ESR in r14
+         */
+        li      r14,-1  /* store to exception frame is done later */
+
+        /* Now we handle the fault proper. We only save DEAR in the non
+         * linear mapping case since we know the linear mapping case will
+         * not re-enter. We could indeed optimize and also not save SRR0/1
+         * in the linear mapping case but I'll leave that for later
+         *
+         * Faulting address is SRR0 which is already in r16
+         */
+        srdi    r11,r16,60              /* get region */
+        cmpldi  cr0,r11,0xc             /* linear mapping ? */
+        TLB_MISS_STATS_SAVE_INFO
+        beq     tlb_load_linear         /* yes -> go to linear map load */
+
+        /* We do the user/kernel test for the PID here along with the RW test
+         */
+        cmpldi  cr0,r11,0                       /* Check for user region */
+        ld      r15,PACAPGD(r13)                /* Load user pgdir */
+        beq     htw_tlb_miss
+
+        /* XXX replace the RMW cycles with immediate loads + writes */
+1:      mfspr   r10,SPRN_MAS1
+        cmpldi  cr0,r11,8                       /* Check for vmalloc region */
+        rlwinm  r10,r10,0,16,1                  /* Clear TID */
+        mtspr   SPRN_MAS1,r10
+        ld      r15,PACA_KERNELPGD(r13)         /* Load kernel pgdir */
+        beq+    htw_tlb_miss
+
+        /* We got a crappy address, just fault */
+        TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT)
+        TLB_MISS_EPILOG_ERROR
+        b       exc_instruction_storage_book3e
+
+
+/*
+ * This is the guts of the second-level TLB miss handler for direct
+ * misses. We are entered with:
+ *
+ * r16 = virtual page table faulting address
+ * r15 = PGD pointer
+ * r14 = ESR
+ * r13 = PACA
+ * r12 = TLB exception frame in PACA
+ * r11 = crap (free to use)
+ * r10 = crap (free to use)
+ *
+ * It can be re-entered by the linear mapping miss handler. However, to
+ * avoid too much complication, it will save/restore things for us
+ */
+htw_tlb_miss:
+        /* Search if we already have a TLB entry for that virtual address, and
+         * if we do, bail out.
+         *
+         * MAS1:IND should be already set based on MAS4
+         */
+        PPC_TLBSRX_DOT(0,r16)
+        beq     htw_tlb_miss_done
+
+        /* Now, we need to walk the page tables. First check if we are in
+         * range.
+         */
+        rldicl. r10,r16,64-PGTABLE_EADDR_SIZE,PGTABLE_EADDR_SIZE+4
+        bne-    htw_tlb_miss_fault
+
+        /* Get the PGD pointer */
+        cmpldi  cr0,r15,0
+        beq-    htw_tlb_miss_fault
+
+        /* Get to PGD entry */
+        rldicl  r11,r16,64-(PGDIR_SHIFT-3),64-PGD_INDEX_SIZE-3
+        clrrdi  r10,r11,3
+        ldx     r15,r10,r15
+        cmpldi  cr0,r15,0
+        beq     htw_tlb_miss_fault
+
+#ifndef CONFIG_PPC_64K_PAGES
+        /* Get to PUD entry */
+        rldicl  r11,r16,64-(PUD_SHIFT-3),64-PUD_INDEX_SIZE-3
+        clrrdi  r10,r11,3
+        ldx     r15,r10,r15
+        cmpldi  cr0,r15,0
+        beq     htw_tlb_miss_fault
+#endif /* CONFIG_PPC_64K_PAGES */
+
+        /* Get to PMD entry */
+        rldicl  r11,r16,64-(PMD_SHIFT-3),64-PMD_INDEX_SIZE-3
+        clrrdi  r10,r11,3
+        ldx     r15,r10,r15
+        cmpldi  cr0,r15,0
+        beq     htw_tlb_miss_fault
+
+        /* Ok, we're all right, we can now create an indirect entry for
+         * a 1M or 256M page.
+         *
+         * The last trick is now that because we use "half" pages for
+         * the HTW (1M IND is 2K and 256M IND is 32K) we need to account
+         * for an added LSB bit to the RPN. For 64K pages, there is no
+         * problem as we already use 32K arrays (half PTE pages), but for
+         * 4K page we need to extract a bit from the virtual address and
+         * insert it into the "PA52" bit of the RPN.
+         */
+#ifndef CONFIG_PPC_64K_PAGES
+        rlwimi  r15,r16,32-9,20,20
+#endif
+        /* Now we build the MAS:
+         *
+         * MAS 0   :    Fully setup with defaults in MAS4 and TLBnCFG
+         * MAS 1   :    Almost fully setup
+         *               - PID already updated by caller if necessary
+         *               - TSIZE for now is base ind page size always
+         * MAS 2   :    Use defaults
+         * MAS 3+7 :    Needs to be done
+         */
+#ifdef CONFIG_PPC_64K_PAGES
+        ori     r10,r15,(BOOK3E_PAGESZ_64K << MAS3_SPSIZE_SHIFT)
+#else
+        ori     r10,r15,(BOOK3E_PAGESZ_4K << MAS3_SPSIZE_SHIFT)
+#endif
+        mtspr   SPRN_MAS7_MAS3,r10
+
+        tlbwe
+
+htw_tlb_miss_done:
+        /* We don't bother with restoring DEAR or ESR since we know we are
+         * level 0 and just going back to userland. They are only needed
+         * if you are going to take an access fault
+         */
+        TLB_MISS_STATS_X(MMSTAT_TLB_MISS_PT_OK)
+        TLB_MISS_EPILOG_SUCCESS
+        rfi
+
+htw_tlb_miss_fault:
+        /* We need to check if it was an instruction miss. We know this
+         * though because r14 would contain -1
+         */
+        cmpdi   cr0,r14,-1
+        beq     1f
+        mtspr   SPRN_DEAR,r16
+        mtspr   SPRN_ESR,r14
+        TLB_MISS_STATS_D(MMSTAT_TLB_MISS_PT_FAULT)
+        TLB_MISS_EPILOG_ERROR
+        b       exc_data_storage_book3e
+1:      TLB_MISS_STATS_I(MMSTAT_TLB_MISS_PT_FAULT)
+        TLB_MISS_EPILOG_ERROR
+        b       exc_instruction_storage_book3e
+
+/*
+ * This is the guts of "any" level TLB miss handler for kernel linear
+ * mapping misses. We are entered with:
+ *
+ *
+ * r16 = faulting address
+ * r15 = crap (free to use)
+ * r14 = ESR (data) or -1 (instruction)
+ * r13 = PACA
+ * r12 = TLB exception frame in PACA
+ * r11 = crap (free to use)
+ * r10 = crap (free to use)
+ *
+ * In addition we know that we will not re-enter, so in theory, we could
+ * use a simpler epilog not restoring SRR0/1 etc.. but we'll do that later.
+ *
+ * We also need to be careful about MAS registers here & TLB reservation,
+ * as we know we'll have clobbered them if we interrupt the main TLB miss
+ * handlers in which case we probably want to do a full restart at level
+ * 0 rather than saving / restoring the MAS.
+ *
+ * Note: If we care about performance of that core, we can easily shuffle
+ *       a few things around
+ */
+tlb_load_linear:
+        /* For now, we assume the linear mapping is contiguous and stops at
+         * linear_map_top. We also assume the size is a multiple of 1G, thus
+         * we only use 1G pages for now. That might have to be changed in a
+         * final implementation, especially when dealing with hypervisors
+         */
+        ld      r11,PACATOC(r13)
+        ld      r11,linear_map_top@got(r11)
+        ld      r10,0(r11)
+        cmpld   cr0,r10,r16
+        bge     tlb_load_linear_fault
+
+        /* MAS1 need whole new setup. */
+        li      r15,(BOOK3E_PAGESZ_1GB<<MAS1_TSIZE_SHIFT)
+        oris    r15,r15,MAS1_VALID@h    /* MAS1 needs V and TSIZE */
+        mtspr   SPRN_MAS1,r15
+
+        /* Already somebody there ? */
+        PPC_TLBSRX_DOT(0,r16)
+        beq     tlb_load_linear_done
+
+        /* Now we build the remaining MAS. MAS0 and 2 should be fine
+         * with their defaults, which leaves us with MAS 3 and 7. The
+         * mapping is linear, so we just take the address, clear the
+         * region bits, and or in the permission bits which are currently
+         * hard wired
+         */
+        clrrdi  r10,r16,30              /* 1G page index */
+        clrldi  r10,r10,4               /* clear region bits */
+        ori     r10,r10,MAS3_SR|MAS3_SW|MAS3_SX
+        mtspr   SPRN_MAS7_MAS3,r10
+
+        tlbwe
+
+tlb_load_linear_done:
+        /* We use the "error" epilog for success as we do want to
+         * restore to the initial faulting context, whatever it was.
+         * We do that because we can't resume a fault within a TLB
+         * miss handler, due to MAS and TLB reservation being clobbered.
+         */
+        TLB_MISS_STATS_X(MMSTAT_TLB_MISS_LINEAR)
+        TLB_MISS_EPILOG_ERROR
+        rfi
+
+tlb_load_linear_fault:
+        /* We keep the DEAR and ESR around, this shouldn't have happened */
+        cmpdi   cr0,r14,-1
+        beq     1f
+        TLB_MISS_EPILOG_ERROR_SPECIAL
+        b       exc_data_storage_book3e
+1:      TLB_MISS_EPILOG_ERROR_SPECIAL
+        b       exc_instruction_storage_book3e
+
+
+#ifdef CONFIG_BOOK3E_MMU_TLB_STATS
+.tlb_stat_inc:
+1:      ldarx   r8,0,r9
+        addi    r8,r8,1
+        stdcx.  r8,0,r9
+        bne-    1b
+        blr
+#endif
diff --git a/arch/powerpc/mm/tlb_nohash.c b/arch/powerpc/mm/tlb_nohash.c
index ad2eb4d34dd4..2fbc680c2c71 100644
--- a/arch/powerpc/mm/tlb_nohash.c
+++ b/arch/powerpc/mm/tlb_nohash.c
@@ -7,8 +7,8 @@
  *
  *  -- BenH
  *
- * Copyright 2008 Ben Herrenschmidt <benh@kernel.crashing.org>
- *                IBM Corp.
+ * Copyright 2008,2009 Ben Herrenschmidt <benh@kernel.crashing.org>
+ *                     IBM Corp.
  *
  *  Derived from arch/ppc/mm/init.c:
  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
@@ -34,12 +34,71 @@
 #include <linux/pagemap.h>
 #include <linux/preempt.h>
 #include <linux/spinlock.h>
+#include <linux/lmb.h>
 
 #include <asm/tlbflush.h>
 #include <asm/tlb.h>
+#include <asm/code-patching.h>
 
 #include "mmu_decl.h"
 
+#ifdef CONFIG_PPC_BOOK3E
+struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT] = {
+        [MMU_PAGE_4K] = {
+                .shift  = 12,
+                .enc    = BOOK3E_PAGESZ_4K,
+        },
+        [MMU_PAGE_16K] = {
+                .shift  = 14,
+                .enc    = BOOK3E_PAGESZ_16K,
+        },
+        [MMU_PAGE_64K] = {
+                .shift  = 16,
+                .enc    = BOOK3E_PAGESZ_64K,
+        },
+        [MMU_PAGE_1M] = {
+                .shift  = 20,
+                .enc    = BOOK3E_PAGESZ_1M,
+        },
+        [MMU_PAGE_16M] = {
+                .shift  = 24,
+                .enc    = BOOK3E_PAGESZ_16M,
+        },
+        [MMU_PAGE_256M] = {
+                .shift  = 28,
+                .enc    = BOOK3E_PAGESZ_256M,
+        },
+        [MMU_PAGE_1G] = {
+                .shift  = 30,
+                .enc    = BOOK3E_PAGESZ_1GB,
+        },
+};
+static inline int mmu_get_tsize(int psize)
+{
+        return mmu_psize_defs[psize].enc;
+}
+#else
+static inline int mmu_get_tsize(int psize)
+{
+        /* This isn't used on !Book3E for now */
+        return 0;
+}
+#endif
+
+/* The variables below are currently only used on 64-bit Book3E
+ * though this will probably be made common with other nohash
+ * implementations at some point
+ */
+#ifdef CONFIG_PPC64
+
+int mmu_linear_psize;           /* Page size used for the linear mapping */
+int mmu_pte_psize;              /* Page size used for PTE pages */
+int mmu_vmemmap_psize;          /* Page size used for the virtual mem map */
+int book3e_htw_enabled;         /* Is HW tablewalk enabled ? */
+unsigned long linear_map_top;   /* Top of linear mapping */
+
+#endif /* CONFIG_PPC64 */
+
 /*
  * Base TLB flushing operations:
  *
@@ -67,18 +126,24 @@ void local_flush_tlb_mm(struct mm_struct *mm)
 }
 EXPORT_SYMBOL(local_flush_tlb_mm);
 
-void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr)
+void __local_flush_tlb_page(struct mm_struct *mm, unsigned long vmaddr,
+                            int tsize, int ind)
 {
         unsigned int pid;
 
         preempt_disable();
-        pid = vma ? vma->vm_mm->context.id : 0;
+        pid = mm ? mm->context.id : 0;
         if (pid != MMU_NO_CONTEXT)
-                _tlbil_va(vmaddr, pid);
+                _tlbil_va(vmaddr, pid, tsize, ind);
         preempt_enable();
 }
-EXPORT_SYMBOL(local_flush_tlb_page);
 
+void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr)
+{
+        __local_flush_tlb_page(vma ? vma->vm_mm : NULL, vmaddr,
+                               mmu_get_tsize(mmu_virtual_psize), 0);
+}
+EXPORT_SYMBOL(local_flush_tlb_page);
 
 /*
  * And here are the SMP non-local implementations
@@ -87,9 +152,17 @@ EXPORT_SYMBOL(local_flush_tlb_page);
 
 static DEFINE_SPINLOCK(tlbivax_lock);
 
+static int mm_is_core_local(struct mm_struct *mm)
+{
+        return cpumask_subset(mm_cpumask(mm),
+                              topology_thread_cpumask(smp_processor_id()));
+}
+
 struct tlb_flush_param {
         unsigned long addr;
         unsigned int pid;
+        unsigned int tsize;
+        unsigned int ind;
 };
 
 static void do_flush_tlb_mm_ipi(void *param)
@@ -103,7 +176,7 @@ static void do_flush_tlb_page_ipi(void *param)
 {
         struct tlb_flush_param *p = param;
 
-        _tlbil_va(p->addr, p->pid);
+        _tlbil_va(p->addr, p->pid, p->tsize, p->ind);
 }
 
 
@@ -131,7 +204,7 @@ void flush_tlb_mm(struct mm_struct *mm)
         pid = mm->context.id;
         if (unlikely(pid == MMU_NO_CONTEXT))
                 goto no_context;
-        if (!cpumask_equal(mm_cpumask(mm), cpumask_of(smp_processor_id()))) {
+        if (!mm_is_core_local(mm)) {
                 struct tlb_flush_param p = { .pid = pid };
                 /* Ignores smp_processor_id() even if set. */
                 smp_call_function_many(mm_cpumask(mm),
@@ -143,37 +216,49 @@ void flush_tlb_mm(struct mm_struct *mm)
 }
 EXPORT_SYMBOL(flush_tlb_mm);
 
-void flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr)
+void __flush_tlb_page(struct mm_struct *mm, unsigned long vmaddr,
+                      int tsize, int ind)
 {
         struct cpumask *cpu_mask;
         unsigned int pid;
 
         preempt_disable();
-        pid = vma ? vma->vm_mm->context.id : 0;
+        pid = mm ? mm->context.id : 0;
         if (unlikely(pid == MMU_NO_CONTEXT))
                 goto bail;
-        cpu_mask = mm_cpumask(vma->vm_mm);
-        if (!cpumask_equal(cpu_mask, cpumask_of(smp_processor_id()))) {
+        cpu_mask = mm_cpumask(mm);
+        if (!mm_is_core_local(mm)) {
                 /* If broadcast tlbivax is supported, use it */
                 if (mmu_has_feature(MMU_FTR_USE_TLBIVAX_BCAST)) {
                         int lock = mmu_has_feature(MMU_FTR_LOCK_BCAST_INVAL);
                         if (lock)
                                 spin_lock(&tlbivax_lock);
-                        _tlbivax_bcast(vmaddr, pid);
+                        _tlbivax_bcast(vmaddr, pid, tsize, ind);
                         if (lock)
                                 spin_unlock(&tlbivax_lock);
                         goto bail;
                 } else {
-                        struct tlb_flush_param p = { .pid = pid, .addr = vmaddr };
+                        struct tlb_flush_param p = {
+                                .pid = pid,
+                                .addr = vmaddr,
+                                .tsize = tsize,
+                                .ind = ind,
+                        };
                         /* Ignores smp_processor_id() even if set in cpu_mask */
                         smp_call_function_many(cpu_mask,
                                                do_flush_tlb_page_ipi, &p, 1);
                 }
         }
-        _tlbil_va(vmaddr, pid);
+        _tlbil_va(vmaddr, pid, tsize, ind);
  bail:
         preempt_enable();
 }
+
+void flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr)
+{
+        __flush_tlb_page(vma ? vma->vm_mm : NULL, vmaddr,
+                         mmu_get_tsize(mmu_virtual_psize), 0);
+}
 EXPORT_SYMBOL(flush_tlb_page);
 
 #endif /* CONFIG_SMP */
@@ -207,3 +292,156 @@ void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
         flush_tlb_mm(vma->vm_mm);
 }
 EXPORT_SYMBOL(flush_tlb_range);
+
+void tlb_flush(struct mmu_gather *tlb)
+{
+        flush_tlb_mm(tlb->mm);
+
+        /* Push out batch of freed page tables */
+        pte_free_finish();
+}
+
+/*
+ * Below are functions specific to the 64-bit variant of Book3E though that
+ * may change in the future
+ */
+
+#ifdef CONFIG_PPC64
+
+/*
+ * Handling of virtual linear page tables or indirect TLB entries
+ * flushing when PTE pages are freed
+ */
+void tlb_flush_pgtable(struct mmu_gather *tlb, unsigned long address)
+{
+        int tsize = mmu_psize_defs[mmu_pte_psize].enc;
+
+        if (book3e_htw_enabled) {
+                unsigned long start = address & PMD_MASK;
+                unsigned long end = address + PMD_SIZE;
+                unsigned long size = 1UL << mmu_psize_defs[mmu_pte_psize].shift;
+
+                /* This isn't the most optimal, ideally we would factor out the
+                 * while preempt & CPU mask mucking around, or even the IPI but
+                 * it will do for now
+                 */
+                while (start < end) {
+                        __flush_tlb_page(tlb->mm, start, tsize, 1);
+                        start += size;
+                }
+        } else {
+                unsigned long rmask = 0xf000000000000000ul;
+                unsigned long rid = (address & rmask) | 0x1000000000000000ul;
+                unsigned long vpte = address & ~rmask;
+
+#ifdef CONFIG_PPC_64K_PAGES
+                vpte = (vpte >> (PAGE_SHIFT - 4)) & ~0xfffful;
+#else
+                vpte = (vpte >> (PAGE_SHIFT - 3)) & ~0xffful;
+#endif
+                vpte |= rid;
+                __flush_tlb_page(tlb->mm, vpte, tsize, 0);
+        }
+}
+
+/*
+ * Early initialization of the MMU TLB code
+ */
+static void __early_init_mmu(int boot_cpu)
+{
+        extern unsigned int interrupt_base_book3e;
+        extern unsigned int exc_data_tlb_miss_htw_book3e;
+        extern unsigned int exc_instruction_tlb_miss_htw_book3e;
+
+        unsigned int *ibase = &interrupt_base_book3e;
+        unsigned int mas4;
+
+        /* XXX This will have to be decided at runtime, but right
+         * now our boot and TLB miss code hard wires it. Ideally
+         * we should find out a suitable page size and patch the
+         * TLB miss code (either that or use the PACA to store
+         * the value we want)
+         */
+        mmu_linear_psize = MMU_PAGE_1G;
+
+        /* XXX This should be decided at runtime based on supported
+         * page sizes in the TLB, but for now let's assume 16M is
+         * always there and a good fit (which it probably is)
+         */
+        mmu_vmemmap_psize = MMU_PAGE_16M;
+
+        /* Check if HW tablewalk is present, and if yes, enable it by:
+         *
+         * - patching the TLB miss handlers to branch to the
+         *   one dedicates to it
+         *
+         * - setting the global book3e_htw_enabled
+         *
+         * - Set MAS4:INDD and default page size
+         */
+
+        /* XXX This code only checks for TLB 0 capabilities and doesn't
+         *     check what page size combos are supported by the HW. It
+         *     also doesn't handle the case where a separate array holds
+         *     the IND entries from the array loaded by the PT.
+         */
+        if (boot_cpu) {
+                unsigned int tlb0cfg = mfspr(SPRN_TLB0CFG);
+
+                /* Check if HW loader is supported */
+                if ((tlb0cfg & TLBnCFG_IND) &&
+                    (tlb0cfg & TLBnCFG_PT)) {
+                        patch_branch(ibase + (0x1c0 / 4),
+                             (unsigned long)&exc_data_tlb_miss_htw_book3e, 0);
+                        patch_branch(ibase + (0x1e0 / 4),
+                             (unsigned long)&exc_instruction_tlb_miss_htw_book3e, 0);
+                        book3e_htw_enabled = 1;
+                }
+                pr_info("MMU: Book3E Page Tables %s\n",
+                        book3e_htw_enabled ? "Enabled" : "Disabled");
+        }
+
+        /* Set MAS4 based on page table setting */
+
+        mas4 = 0x4 << MAS4_WIMGED_SHIFT;
+        if (book3e_htw_enabled) {
+                mas4 |= mas4 | MAS4_INDD;
+#ifdef CONFIG_PPC_64K_PAGES
+                mas4 |= BOOK3E_PAGESZ_256M << MAS4_TSIZED_SHIFT;
+                mmu_pte_psize = MMU_PAGE_256M;
+#else
+                mas4 |= BOOK3E_PAGESZ_1M << MAS4_TSIZED_SHIFT;
+                mmu_pte_psize = MMU_PAGE_1M;
+#endif
+        } else {
+#ifdef CONFIG_PPC_64K_PAGES
+                mas4 |= BOOK3E_PAGESZ_64K << MAS4_TSIZED_SHIFT;
+#else
+                mas4 |= BOOK3E_PAGESZ_4K << MAS4_TSIZED_SHIFT;
+#endif
+                mmu_pte_psize = mmu_virtual_psize;
+        }
+        mtspr(SPRN_MAS4, mas4);
+
+        /* Set the global containing the top of the linear mapping
+         * for use by the TLB miss code
+         */
+        linear_map_top = lmb_end_of_DRAM();
+
+        /* A sync won't hurt us after mucking around with
+         * the MMU configuration
+         */
+        mb();
+}
+
+void __init early_init_mmu(void)
+{
+        __early_init_mmu(1);
+}
+
+void __cpuinit early_init_mmu_secondary(void)
+{
+        __early_init_mmu(0);
+}
+
+#endif /* CONFIG_PPC64 */
diff --git a/arch/powerpc/mm/tlb_nohash_low.S b/arch/powerpc/mm/tlb_nohash_low.S
index 3037911279b1..7bcd9fbf6cc6 100644
--- a/arch/powerpc/mm/tlb_nohash_low.S
+++ b/arch/powerpc/mm/tlb_nohash_low.S
@@ -39,7 +39,7 @@
 /*
  * 40x implementation needs only tlbil_va
  */
-_GLOBAL(_tlbil_va)
+_GLOBAL(__tlbil_va)
         /* We run the search with interrupts disabled because we have to change
          * the PID and I don't want to preempt when that happens.
          */
@@ -71,7 +71,7 @@ _GLOBAL(_tlbil_va)
  * 440 implementation uses tlbsx/we for tlbil_va and a full sweep
  * of the TLB for everything else.
  */
-_GLOBAL(_tlbil_va)
+_GLOBAL(__tlbil_va)
         mfspr   r5,SPRN_MMUCR
         rlwimi  r5,r4,0,24,31                   /* Set TID */
 
@@ -170,7 +170,7 @@ ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_USE_TLBILX)
  * Flush MMU TLB for a particular address, but only on the local processor
  * (no broadcast)
  */
-_GLOBAL(_tlbil_va)
+_GLOBAL(__tlbil_va)
         mfmsr   r10
         wrteei  0
         slwi    r4,r4,16
@@ -191,6 +191,85 @@ ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_TLBILX)
         isync
 1:      wrtee   r10
         blr
+#elif defined(CONFIG_PPC_BOOK3E)
+/*
+ * New Book3E (>= 2.06) implementation
+ *
+ * Note: We may be able to get away without the interrupt masking stuff
+ * if we save/restore MAS6 on exceptions that might modify it
+ */
+_GLOBAL(_tlbil_pid)
+        slwi    r4,r3,MAS6_SPID_SHIFT
+        mfmsr   r10
+        wrteei  0
+        mtspr   SPRN_MAS6,r4
+        PPC_TLBILX_PID(0,0)
+        wrtee   r10
+        msync
+        isync
+        blr
+
+_GLOBAL(_tlbil_pid_noind)
+        slwi    r4,r3,MAS6_SPID_SHIFT
+        mfmsr   r10
+        ori     r4,r4,MAS6_SIND
+        wrteei  0
+        mtspr   SPRN_MAS6,r4
+        PPC_TLBILX_PID(0,0)
+        wrtee   r10
+        msync
+        isync
+        blr
+
+_GLOBAL(_tlbil_all)
+        PPC_TLBILX_ALL(0,0)
+        msync
+        isync
+        blr
+
+_GLOBAL(_tlbil_va)
+        mfmsr   r10
+        wrteei  0
+        cmpwi   cr0,r6,0
+        slwi    r4,r4,MAS6_SPID_SHIFT
+        rlwimi  r4,r5,MAS6_ISIZE_SHIFT,MAS6_ISIZE_MASK
+        beq     1f
+        rlwimi  r4,r6,MAS6_SIND_SHIFT,MAS6_SIND
+1:      mtspr   SPRN_MAS6,r4            /* assume AS=0 for now */
+        PPC_TLBILX_VA(0,r3)
+        msync
+        isync
+        wrtee   r10
+        blr
+
+_GLOBAL(_tlbivax_bcast)
+        mfmsr   r10
+        wrteei  0
+        cmpwi   cr0,r6,0
+        slwi    r4,r4,MAS6_SPID_SHIFT
+        rlwimi  r4,r5,MAS6_ISIZE_SHIFT,MAS6_ISIZE_MASK
+        beq     1f
+        rlwimi  r4,r6,MAS6_SIND_SHIFT,MAS6_SIND
+1:      mtspr   SPRN_MAS6,r4            /* assume AS=0 for now */
+        PPC_TLBIVAX(0,r3)
+        eieio
+        tlbsync
+        sync
+        wrtee   r10
+        blr
+
+_GLOBAL(set_context)
+#ifdef CONFIG_BDI_SWITCH
+        /* Context switch the PTE pointer for the Abatron BDI2000.
+         * The PGDIR is the second parameter.
+         */
+        lis     r5, abatron_pteptrs@h
+        ori     r5, r5, abatron_pteptrs@l
+        stw     r4, 0x4(r5)
+#endif
+        mtspr   SPRN_PID,r3
+        isync                   /* Force context change */
+        blr
 #else
 #error Unsupported processor type !
 #endif
diff --git a/arch/powerpc/platforms/82xx/mgcoge.c b/arch/powerpc/platforms/82xx/mgcoge.c
index c2af169c1d1d..7a5de9eb3c73 100644
--- a/arch/powerpc/platforms/82xx/mgcoge.c
+++ b/arch/powerpc/platforms/82xx/mgcoge.c
@@ -50,16 +50,63 @@ struct cpm_pin {
 static __initdata struct cpm_pin mgcoge_pins[] = {
 
         /* SMC2 */
-        {1, 8, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
-        {1, 9, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+        {0, 8, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+        {0, 9, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
 
         /* SCC4 */
-        {3, 25, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
-        {3, 24, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
-        {3,  9, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
-        {3,  8, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
-        {4, 22, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
-        {4, 21, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+        {2, 25, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+        {2, 24, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+        {2,  9, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+        {2,  8, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+        {3, 22, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+        {3, 21, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+
+        /* FCC1 */
+        {0, 14, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+        {0, 15, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+        {0, 16, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+        {0, 17, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+        {0, 18, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+        {0, 19, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+        {0, 20, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+        {0, 21, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+        {0, 26, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
+        {0, 27, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
+        {0, 28, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
+        {0, 29, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
+        {0, 30, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
+        {0, 31, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
+
+        {2, 22, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+        {2, 23, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+
+        /* FCC2 */
+        {1, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+        {1, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+        {1, 20, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+        {1, 21, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+        {1, 22, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+        {1, 23, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+        {1, 24, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+        {1, 25, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+        {1, 26, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+        {1, 27, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+        {1, 28, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+        {1, 29, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
+        {1, 30, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+        {1, 31, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
+
+        {2, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+        {2, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
+
+        /* MDC */
+        {0, 13, CPM_PIN_OUTPUT | CPM_PIN_GPIO},
+
+#if defined(CONFIG_I2C_CPM)
+        /* I2C */
+        {3, 14, CPM_PIN_INPUT | CPM_PIN_SECONDARY | CPM_PIN_OPENDRAIN},
+        {3, 15, CPM_PIN_INPUT | CPM_PIN_SECONDARY | CPM_PIN_OPENDRAIN},
+#endif
 };
 
 static void __init init_ioports(void)
@@ -68,12 +115,16 @@ static void __init init_ioports(void)
 
         for (i = 0; i < ARRAY_SIZE(mgcoge_pins); i++) {
                 const struct cpm_pin *pin = &mgcoge_pins[i];
-                cpm2_set_pin(pin->port - 1, pin->pin, pin->flags);
+                cpm2_set_pin(pin->port, pin->pin, pin->flags);
         }
 
         cpm2_smc_clk_setup(CPM_CLK_SMC2, CPM_BRG8);
         cpm2_clk_setup(CPM_CLK_SCC4, CPM_CLK7, CPM_CLK_RX);
         cpm2_clk_setup(CPM_CLK_SCC4, CPM_CLK8, CPM_CLK_TX);
+        cpm2_clk_setup(CPM_CLK_FCC1, CPM_CLK10, CPM_CLK_RX);
+        cpm2_clk_setup(CPM_CLK_FCC1, CPM_CLK9,  CPM_CLK_TX);
+        cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK13, CPM_CLK_RX);
+        cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK14, CPM_CLK_TX);
 }
 
 static void __init mgcoge_setup_arch(void)
diff --git a/arch/powerpc/platforms/83xx/Kconfig b/arch/powerpc/platforms/83xx/Kconfig
index 083ebee9a16d..f49a2548c5ff 100644
--- a/arch/powerpc/platforms/83xx/Kconfig
+++ b/arch/powerpc/platforms/83xx/Kconfig
@@ -75,11 +75,11 @@ config MPC837x_MDS
           This option enables support for the MPC837x MDS Processor Board.
 
 config MPC837x_RDB
-        bool "Freescale MPC837x RDB"
+        bool "Freescale MPC837x RDB/WLAN"
         select DEFAULT_UIMAGE
         select PPC_MPC837x
         help
-          This option enables support for the MPC837x RDB Board.
+          This option enables support for the MPC837x RDB and WLAN Boards.
 
 config SBC834x
         bool "Wind River SBC834x"
diff --git a/arch/powerpc/platforms/83xx/mpc837x_rdb.c b/arch/powerpc/platforms/83xx/mpc837x_rdb.c
index 76f3b32a155e..a1908d261240 100644
--- a/arch/powerpc/platforms/83xx/mpc837x_rdb.c
+++ b/arch/powerpc/platforms/83xx/mpc837x_rdb.c
@@ -17,10 +17,32 @@
 #include <asm/time.h>
 #include <asm/ipic.h>
 #include <asm/udbg.h>
+#include <sysdev/fsl_soc.h>
 #include <sysdev/fsl_pci.h>
 
 #include "mpc83xx.h"
 
+static void mpc837x_rdb_sd_cfg(void)
+{
+        void __iomem *im;
+
+        im = ioremap(get_immrbase(), 0x1000);
+        if (!im) {
+                WARN_ON(1);
+                return;
+        }
+
+        /*
+         * On RDB boards (in contrast to MDS) USBB pins are used for SD only,
+         * so we can safely mux them away from the USB block.
+         */
+        clrsetbits_be32(im + MPC83XX_SICRL_OFFS, MPC837X_SICRL_USBB_MASK,
+                                                 MPC837X_SICRL_SD);
+        clrsetbits_be32(im + MPC83XX_SICRH_OFFS, MPC837X_SICRH_SPI_MASK,
+                                                 MPC837X_SICRH_SD);
+        iounmap(im);
+}
+
 /* ************************************************************************
  *
  * Setup the architecture
@@ -42,6 +64,7 @@ static void __init mpc837x_rdb_setup_arch(void)
                 mpc83xx_add_bridge(np);
 #endif
         mpc837x_usb_cfg();
+        mpc837x_rdb_sd_cfg();
 }
 
 static struct of_device_id mpc837x_ids[] = {
@@ -86,11 +109,12 @@ static int __init mpc837x_rdb_probe(void)
 
         return of_flat_dt_is_compatible(root, "fsl,mpc8377rdb") ||
                of_flat_dt_is_compatible(root, "fsl,mpc8378rdb") ||
-               of_flat_dt_is_compatible(root, "fsl,mpc8379rdb");
+               of_flat_dt_is_compatible(root, "fsl,mpc8379rdb") ||
+               of_flat_dt_is_compatible(root, "fsl,mpc8377wlan");
 }
 
 define_machine(mpc837x_rdb) {
-        .name                   = "MPC837x RDB",
+        .name                   = "MPC837x RDB/WLAN",
         .probe                  = mpc837x_rdb_probe,
         .setup_arch             = mpc837x_rdb_setup_arch,
         .init_IRQ               = mpc837x_rdb_init_IRQ,
diff --git a/arch/powerpc/platforms/83xx/mpc83xx.h b/arch/powerpc/platforms/83xx/mpc83xx.h
index d1dc5b0b4fbf..0fea8811d45b 100644
--- a/arch/powerpc/platforms/83xx/mpc83xx.h
+++ b/arch/powerpc/platforms/83xx/mpc83xx.h
@@ -30,6 +30,8 @@
 #define MPC8315_SICRL_USB_ULPI     0x00000054
 #define MPC837X_SICRL_USB_MASK     0xf0000000
 #define MPC837X_SICRL_USB_ULPI     0x50000000
+#define MPC837X_SICRL_USBB_MASK    0x30000000
+#define MPC837X_SICRL_SD           0x20000000
 
 /* system i/o configuration register high */
 #define MPC83XX_SICRH_OFFS         0x118
@@ -38,6 +40,8 @@
 #define MPC831X_SICRH_USB_ULPI     0x000000a0
 #define MPC8315_SICRH_USB_MASK     0x0000ff00
 #define MPC8315_SICRH_USB_ULPI     0x00000000
+#define MPC837X_SICRH_SPI_MASK     0x00000003
+#define MPC837X_SICRH_SD           0x00000001
 
 /* USB Control Register */
 #define FSL_USB2_CONTROL_OFFS      0x500
diff --git a/arch/powerpc/platforms/85xx/smp.c b/arch/powerpc/platforms/85xx/smp.c
index 62c592ede641..9f526ba31c1e 100644
--- a/arch/powerpc/platforms/85xx/smp.c
+++ b/arch/powerpc/platforms/85xx/smp.c
@@ -25,7 +25,6 @@
 
 #include <sysdev/fsl_soc.h>
 
-extern volatile unsigned long __secondary_hold_acknowledge;
 extern void __early_start(void);
 
 #define BOOT_ENTRY_ADDR_UPPER   0
diff --git a/arch/powerpc/platforms/86xx/gef_ppc9a.c b/arch/powerpc/platforms/86xx/gef_ppc9a.c
index 2efa052975e6..287f7bd17dd9 100644
--- a/arch/powerpc/platforms/86xx/gef_ppc9a.c
+++ b/arch/powerpc/platforms/86xx/gef_ppc9a.c
@@ -102,8 +102,8 @@ static unsigned int gef_ppc9a_get_pcb_rev(void)
 {
         unsigned int reg;
 
-        reg = ioread32(ppc9a_regs);
-        return (reg >> 8) & 0xff;
+        reg = ioread32be(ppc9a_regs);
+        return (reg >> 16) & 0xff;
 }
 
 /* Return the board (software) revision */
@@ -111,8 +111,8 @@ static unsigned int gef_ppc9a_get_board_rev(void)
 {
         unsigned int reg;
 
-        reg = ioread32(ppc9a_regs);
-        return (reg >> 16) & 0xff;
+        reg = ioread32be(ppc9a_regs);
+        return (reg >> 8) & 0xff;
 }
 
 /* Return the FPGA revision */
@@ -120,8 +120,26 @@ static unsigned int gef_ppc9a_get_fpga_rev(void)
 {
         unsigned int reg;
 
-        reg = ioread32(ppc9a_regs);
-        return (reg >> 24) & 0xf;
+        reg = ioread32be(ppc9a_regs);
+        return reg & 0xf;
+}
+
+/* Return VME Geographical Address */
+static unsigned int gef_ppc9a_get_vme_geo_addr(void)
+{
+        unsigned int reg;
+
+        reg = ioread32be(ppc9a_regs + 0x4);
+        return reg & 0x1f;
+}
+
+/* Return VME System Controller Status */
+static unsigned int gef_ppc9a_get_vme_is_syscon(void)
+{
+        unsigned int reg;
+
+        reg = ioread32be(ppc9a_regs + 0x4);
+        return (reg >> 9) & 0x1;
 }
 
 static void gef_ppc9a_show_cpuinfo(struct seq_file *m)
@@ -131,10 +149,15 @@ static void gef_ppc9a_show_cpuinfo(struct seq_file *m)
         seq_printf(m, "Vendor\t\t: GE Fanuc Intelligent Platforms\n");
 
         seq_printf(m, "Revision\t: %u%c\n", gef_ppc9a_get_pcb_rev(),
-                ('A' + gef_ppc9a_get_board_rev() - 1));
+                ('A' + gef_ppc9a_get_board_rev()));
         seq_printf(m, "FPGA Revision\t: %u\n", gef_ppc9a_get_fpga_rev());
 
         seq_printf(m, "SVR\t\t: 0x%x\n", svid);
+
+        seq_printf(m, "VME geo. addr\t: %u\n", gef_ppc9a_get_vme_geo_addr());
+
+        seq_printf(m, "VME syscon\t: %s\n",
+                gef_ppc9a_get_vme_is_syscon() ? "yes" : "no");
 }
 
 static void __init gef_ppc9a_nec_fixup(struct pci_dev *pdev)
diff --git a/arch/powerpc/platforms/86xx/mpc86xx_smp.c b/arch/powerpc/platforms/86xx/mpc86xx_smp.c
index d84bbb508ee7..eacea0e3fcc8 100644
--- a/arch/powerpc/platforms/86xx/mpc86xx_smp.c
+++ b/arch/powerpc/platforms/86xx/mpc86xx_smp.c
@@ -27,7 +27,6 @@
 #include "mpc86xx.h"
 
 extern void __secondary_start_mpc86xx(void);
-extern unsigned long __secondary_hold_acknowledge;
 
 #define MCM_PORT_CONFIG_OFFSET  0x10
 
diff --git a/arch/powerpc/platforms/Kconfig.cputype b/arch/powerpc/platforms/Kconfig.cputype
index 61187bec7506..9efc8bda01b4 100644
--- a/arch/powerpc/platforms/Kconfig.cputype
+++ b/arch/powerpc/platforms/Kconfig.cputype
@@ -57,15 +57,35 @@ config E200
 
 endchoice
 
-config PPC_BOOK3S_64
-        def_bool y
+choice
+        prompt "Processor Type"
         depends on PPC64
+        help
+          There are two families of 64 bit PowerPC chips supported.
+          The most common ones are the desktop and server CPUs
+          (POWER3, RS64, POWER4, POWER5, POWER5+, POWER6, ...)
+
+          The other are the "embedded" processors compliant with the
+          "Book 3E" variant of the architecture
+
+config PPC_BOOK3S_64
+        bool "Server processors"
         select PPC_FPU
 
+config PPC_BOOK3E_64
+        bool "Embedded processors"
+        select PPC_FPU # Make it a choice ?
+
+endchoice
+
 config PPC_BOOK3S
         def_bool y
         depends on PPC_BOOK3S_32 || PPC_BOOK3S_64
 
+config PPC_BOOK3E
+        def_bool y
+        depends on PPC_BOOK3E_64
+
 config POWER4_ONLY
         bool "Optimize for POWER4"
         depends on PPC64 && PPC_BOOK3S
@@ -125,7 +145,7 @@ config 4xx
 
 config BOOKE
         bool
-        depends on E200 || E500 || 44x
+        depends on E200 || E500 || 44x || PPC_BOOK3E
         default y
 
 config FSL_BOOKE
@@ -223,9 +243,17 @@ config PPC_MMU_NOHASH
         def_bool y
         depends on !PPC_STD_MMU
 
+config PPC_MMU_NOHASH_32
+        def_bool y
+        depends on PPC_MMU_NOHASH && PPC32
+
+config PPC_MMU_NOHASH_64
+        def_bool y
+        depends on PPC_MMU_NOHASH && PPC64
+
 config PPC_BOOK3E_MMU
         def_bool y
-        depends on FSL_BOOKE
+        depends on FSL_BOOKE || PPC_BOOK3E
 
 config PPC_MM_SLICES
         bool
@@ -257,7 +285,7 @@ config PPC_PERF_CTRS
          This enables the powerpc-specific perf_counter back-end.
 
 config SMP
-        depends on PPC_STD_MMU || FSL_BOOKE
+        depends on PPC_BOOK3S || PPC_BOOK3E || FSL_BOOKE
         bool "Symmetric multi-processing support"
         ---help---
           This enables support for systems with more than one CPU. If you have
diff --git a/arch/powerpc/platforms/amigaone/setup.c b/arch/powerpc/platforms/amigaone/setup.c
index 443035366c12..9290a7a442d0 100644
--- a/arch/powerpc/platforms/amigaone/setup.c
+++ b/arch/powerpc/platforms/amigaone/setup.c
@@ -110,13 +110,16 @@ void __init amigaone_init_IRQ(void)
         irq_set_default_host(i8259_get_host());
 }
 
-void __init amigaone_init(void)
+static int __init request_isa_regions(void)
 {
         request_region(0x00, 0x20, "dma1");
         request_region(0x40, 0x20, "timer");
         request_region(0x80, 0x10, "dma page reg");
         request_region(0xc0, 0x20, "dma2");
+
+        return 0;
 }
+machine_device_initcall(amigaone, request_isa_regions);
 
 void amigaone_restart(char *cmd)
 {
@@ -161,7 +164,6 @@ define_machine(amigaone) {
         .name                   = "AmigaOne",
         .probe                  = amigaone_probe,
         .setup_arch             = amigaone_setup_arch,
-        .init                   = amigaone_init,
         .show_cpuinfo           = amigaone_show_cpuinfo,
         .init_IRQ               = amigaone_init_IRQ,
         .restart                = amigaone_restart,
diff --git a/arch/powerpc/platforms/cell/Kconfig b/arch/powerpc/platforms/cell/Kconfig
index 50f17bdd3c16..48cd7d2e1b75 100644
--- a/arch/powerpc/platforms/cell/Kconfig
+++ b/arch/powerpc/platforms/cell/Kconfig
@@ -80,13 +80,6 @@ config SPU_FS_64K_LS
           uses 4K pages. This can improve performances of applications
           using multiple SPEs by lowering the TLB pressure on them.
 
-config SPU_TRACE
-        tristate "SPU event tracing support"
-        depends on SPU_FS && MARKERS
-        help
-          This option allows reading a trace of spu-related events through
-          the sputrace file in procfs.
-
 config SPU_BASE
         bool
         default n
diff --git a/arch/powerpc/platforms/cell/celleb_setup.c b/arch/powerpc/platforms/cell/celleb_setup.c
index 07c234f6b2b6..e53845579770 100644
--- a/arch/powerpc/platforms/cell/celleb_setup.c
+++ b/arch/powerpc/platforms/cell/celleb_setup.c
@@ -80,8 +80,7 @@ static void celleb_show_cpuinfo(struct seq_file *m)
 
 static int __init celleb_machine_type_hack(char *ptr)
 {
-        strncpy(celleb_machine_type, ptr, sizeof(celleb_machine_type));
-        celleb_machine_type[sizeof(celleb_machine_type)-1] = 0;
+        strlcpy(celleb_machine_type, ptr, sizeof(celleb_machine_type));
         return 0;
 }
 
diff --git a/arch/powerpc/platforms/cell/smp.c b/arch/powerpc/platforms/cell/smp.c
index bc97fada48c6..f774530075b7 100644
--- a/arch/powerpc/platforms/cell/smp.c
+++ b/arch/powerpc/platforms/cell/smp.c
@@ -58,8 +58,6 @@
  */
 static cpumask_t of_spin_map;
 
-extern void generic_secondary_smp_init(unsigned long);
-
 /**
  * smp_startup_cpu() - start the given cpu
  *
diff --git a/arch/powerpc/platforms/cell/spufs/Makefile b/arch/powerpc/platforms/cell/spufs/Makefile
index 99610a6361f2..b93f877ba504 100644
--- a/arch/powerpc/platforms/cell/spufs/Makefile
+++ b/arch/powerpc/platforms/cell/spufs/Makefile
@@ -4,7 +4,8 @@ spufs-y += inode.o file.o context.o syscalls.o coredump.o
 spufs-y += sched.o backing_ops.o hw_ops.o run.o gang.o
 spufs-y += switch.o fault.o lscsa_alloc.o
 
-obj-$(CONFIG_SPU_TRACE) += sputrace.o
+# magic for the trace events
+CFLAGS_sched.o := -I$(src)
 
 # Rules to build switch.o with the help of SPU tool chain
 SPU_CROSS       := spu-
diff --git a/arch/powerpc/platforms/cell/spufs/context.c b/arch/powerpc/platforms/cell/spufs/context.c
index db5398c0339f..0c87bcd2452a 100644
--- a/arch/powerpc/platforms/cell/spufs/context.c
+++ b/arch/powerpc/platforms/cell/spufs/context.c
@@ -28,6 +28,7 @@
 #include <asm/spu.h>
 #include <asm/spu_csa.h>
 #include "spufs.h"
+#include "sputrace.h"
 
 
 atomic_t nr_spu_contexts = ATOMIC_INIT(0);
diff --git a/arch/powerpc/platforms/cell/spufs/file.c b/arch/powerpc/platforms/cell/spufs/file.c
index d6a519e6e1c1..ab8aef9bb8ea 100644
--- a/arch/powerpc/platforms/cell/spufs/file.c
+++ b/arch/powerpc/platforms/cell/spufs/file.c
@@ -38,6 +38,7 @@
 #include <asm/uaccess.h>
 
 #include "spufs.h"
+#include "sputrace.h"
 
 #define SPUFS_MMAP_4K (PAGE_SIZE == 0x1000)
 
diff --git a/arch/powerpc/platforms/cell/spufs/sched.c b/arch/powerpc/platforms/cell/spufs/sched.c
index f085369301b1..bb5b77c66d05 100644
--- a/arch/powerpc/platforms/cell/spufs/sched.c
+++ b/arch/powerpc/platforms/cell/spufs/sched.c
@@ -47,6 +47,8 @@
 #include <asm/spu_csa.h>
 #include <asm/spu_priv1.h>
 #include "spufs.h"
+#define CREATE_TRACE_POINTS
+#include "sputrace.h"
 
 struct spu_prio_array {
         DECLARE_BITMAP(bitmap, MAX_PRIO);
diff --git a/arch/powerpc/platforms/cell/spufs/spufs.h b/arch/powerpc/platforms/cell/spufs/spufs.h
index ae31573bea4a..c448bac65518 100644
--- a/arch/powerpc/platforms/cell/spufs/spufs.h
+++ b/arch/powerpc/platforms/cell/spufs/spufs.h
@@ -373,9 +373,4 @@ extern void spu_free_lscsa(struct spu_state *csa);
 extern void spuctx_switch_state(struct spu_context *ctx,
                 enum spu_utilization_state new_state);
 
-#define spu_context_trace(name, ctx, spu) \
-        trace_mark(name, "ctx %p spu %p", ctx, spu);
-#define spu_context_nospu_trace(name, ctx) \
-        trace_mark(name, "ctx %p", ctx);
-
 #endif
diff --git a/arch/powerpc/platforms/cell/spufs/sputrace.c b/arch/powerpc/platforms/cell/spufs/sputrace.c
deleted file mode 100644
index d0b1f3f4d9c8..000000000000
--- a/arch/powerpc/platforms/cell/spufs/sputrace.c
+++ /dev/null
@@ -1,272 +0,0 @@
-/*
- * Copyright (C) 2007 IBM Deutschland Entwicklung GmbH
- *      Released under GPL v2.
- *
- * Partially based on net/ipv4/tcp_probe.c.
- *
- * Simple tracing facility for spu contexts.
- */
-#include <linux/sched.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/marker.h>
-#include <linux/proc_fs.h>
-#include <linux/wait.h>
-#include <asm/atomic.h>
-#include <asm/uaccess.h>
-#include "spufs.h"
-
-struct spu_probe {
-        const char *name;
-        const char *format;
-        marker_probe_func *probe_func;
-};
-
-struct sputrace {
-        ktime_t tstamp;
-        int owner_tid; /* owner */
-        int curr_tid;
-        const char *name;
-        int number;
-};
-
-static int bufsize __read_mostly = 16384;
-MODULE_PARM_DESC(bufsize, "Log buffer size (number of records)");
-module_param(bufsize, int, 0);
-
-
-static DEFINE_SPINLOCK(sputrace_lock);
-static DECLARE_WAIT_QUEUE_HEAD(sputrace_wait);
-static ktime_t sputrace_start;
-static unsigned long sputrace_head, sputrace_tail;
-static struct sputrace *sputrace_log;
-static int sputrace_logging;
-
-static int sputrace_used(void)
-{
-        return (sputrace_head - sputrace_tail) % bufsize;
-}
-
-static inline int sputrace_avail(void)
-{
-        return bufsize - sputrace_used();
-}
-
-static int sputrace_sprint(char *tbuf, int n)
-{
-        const struct sputrace *t = sputrace_log + sputrace_tail % bufsize;
-        struct timespec tv =
-                ktime_to_timespec(ktime_sub(t->tstamp, sputrace_start));
-
-        return snprintf(tbuf, n,
-                "[%lu.%09lu] %d: %s (ctxthread = %d, spu = %d)\n",
-                (unsigned long) tv.tv_sec,
-                (unsigned long) tv.tv_nsec,
-                t->curr_tid,
-                t->name,
-                t->owner_tid,
-                t->number);
-}
-
-static ssize_t sputrace_read(struct file *file, char __user *buf,
-                size_t len, loff_t *ppos)
-{
-        int error = 0, cnt = 0;
-
-        if (!buf || len < 0)
-                return -EINVAL;
-
-        while (cnt < len) {
-                char tbuf[128];
-                int width;
-
-                /* If we have data ready to return, don't block waiting
-                 * for more */
-                if (cnt > 0 && sputrace_used() == 0)
-                        break;
-
-                error = wait_event_interruptible(sputrace_wait,
-                                                 sputrace_used() > 0);
-                if (error)
-                        break;
-
-                spin_lock(&sputrace_lock);
-                if (sputrace_head == sputrace_tail) {
-                        spin_unlock(&sputrace_lock);
-                        continue;
-                }
-
-                width = sputrace_sprint(tbuf, sizeof(tbuf));
-                if (width < len)
-                        sputrace_tail = (sputrace_tail + 1) % bufsize;
-                spin_unlock(&sputrace_lock);
-
-                if (width >= len)
-                        break;
-
-                error = copy_to_user(buf + cnt, tbuf, width);
-                if (error)
-                        break;
-                cnt += width;
-        }
-
-        return cnt == 0 ? error : cnt;
-}
-
-static int sputrace_open(struct inode *inode, struct file *file)
-{
-        int rc;
-
-        spin_lock(&sputrace_lock);
-        if (sputrace_logging) {
-                rc = -EBUSY;
-                goto out;
-        }
-
-        sputrace_logging = 1;
-        sputrace_head = sputrace_tail = 0;
-        sputrace_start = ktime_get();
-        rc = 0;
-
-out:
-        spin_unlock(&sputrace_lock);
-        return rc;
-}
-
-static int sputrace_release(struct inode *inode, struct file *file)
-{
-        spin_lock(&sputrace_lock);
-        sputrace_logging = 0;
-        spin_unlock(&sputrace_lock);
-        return 0;
-}
-
-static const struct file_operations sputrace_fops = {
-        .owner   = THIS_MODULE,
-        .open    = sputrace_open,
-        .read    = sputrace_read,
-        .release = sputrace_release,
-};
-
-static void sputrace_log_item(const char *name, struct spu_context *ctx,
-                struct spu *spu)
-{
-        spin_lock(&sputrace_lock);
-
-        if (!sputrace_logging) {
-                spin_unlock(&sputrace_lock);
-                return;
-        }
-
-        if (sputrace_avail() > 1) {
-                struct sputrace *t = sputrace_log + sputrace_head;
-
-                t->tstamp = ktime_get();
-                t->owner_tid = ctx->tid;
-                t->name = name;
-                t->curr_tid = current->pid;
-                t->number = spu ? spu->number : -1;
-
-                sputrace_head = (sputrace_head + 1) % bufsize;
-        } else {
-                printk(KERN_WARNING
-                       "sputrace: lost samples due to full buffer.\n");
-        }
-        spin_unlock(&sputrace_lock);
-
-        wake_up(&sputrace_wait);
-}
-
-static void spu_context_event(void *probe_private, void *call_data,
-                const char *format, va_list *args)
-{
-        struct spu_probe *p = probe_private;
-        struct spu_context *ctx;
-        struct spu *spu;
-
-        ctx = va_arg(*args, struct spu_context *);
-        spu = va_arg(*args, struct spu *);
-
-        sputrace_log_item(p->name, ctx, spu);
-}
-
-static void spu_context_nospu_event(void *probe_private, void *call_data,
-                const char *format, va_list *args)
-{
-        struct spu_probe *p = probe_private;
-        struct spu_context *ctx;
-
-        ctx = va_arg(*args, struct spu_context *);
-
-        sputrace_log_item(p->name, ctx, NULL);
-}
-
-struct spu_probe spu_probes[] = {
-        { "spu_bind_context__enter", "ctx %p spu %p", spu_context_event },
-        { "spu_unbind_context__enter", "ctx %p spu %p", spu_context_event },
-        { "spu_get_idle__enter", "ctx %p", spu_context_nospu_event },
-        { "spu_get_idle__found", "ctx %p spu %p", spu_context_event },
-        { "spu_get_idle__not_found", "ctx %p", spu_context_nospu_event },
-        { "spu_find_victim__enter", "ctx %p", spu_context_nospu_event },
-        { "spusched_tick__preempt", "ctx %p spu %p", spu_context_event },
-        { "spusched_tick__newslice", "ctx %p", spu_context_nospu_event },
-        { "spu_yield__enter", "ctx %p", spu_context_nospu_event },
-        { "spu_deactivate__enter", "ctx %p", spu_context_nospu_event },
-        { "__spu_deactivate__unload", "ctx %p spu %p", spu_context_event },
-        { "spufs_ps_fault__enter", "ctx %p", spu_context_nospu_event },
-        { "spufs_ps_fault__sleep", "ctx %p", spu_context_nospu_event },
-        { "spufs_ps_fault__wake", "ctx %p spu %p", spu_context_event },
-        { "spufs_ps_fault__insert", "ctx %p spu %p", spu_context_event },
-        { "spu_acquire_saved__enter", "ctx %p", spu_context_nospu_event },
-        { "destroy_spu_context__enter", "ctx %p", spu_context_nospu_event },
-        { "spufs_stop_callback__enter", "ctx %p spu %p", spu_context_event },
-};
-
-static int __init sputrace_init(void)
-{
-        struct proc_dir_entry *entry;
-        int i, error = -ENOMEM;
-
-        sputrace_log = kcalloc(bufsize, sizeof(struct sputrace), GFP_KERNEL);
-        if (!sputrace_log)
-                goto out;
-
-        entry = proc_create("sputrace", S_IRUSR, NULL, &sputrace_fops);
-        if (!entry)
-                goto out_free_log;
-
-        for (i = 0; i < ARRAY_SIZE(spu_probes); i++) {
-                struct spu_probe *p = &spu_probes[i];
-
-                error = marker_probe_register(p->name, p->format,
-                                              p->probe_func, p);
-                if (error)
-                        printk(KERN_INFO "Unable to register probe %s\n",
-                                        p->name);
-        }
-
-        return 0;
-
-out_free_log:
-        kfree(sputrace_log);
-out:
-        return -ENOMEM;
-}
-
-static void __exit sputrace_exit(void)
-{
-        int i;
-
-        for (i = 0; i < ARRAY_SIZE(spu_probes); i++)
-                marker_probe_unregister(spu_probes[i].name,
-                        spu_probes[i].probe_func, &spu_probes[i]);
-
-        remove_proc_entry("sputrace", NULL);
-        kfree(sputrace_log);
-        marker_synchronize_unregister();
-}
-
-module_init(sputrace_init);
-module_exit(sputrace_exit);
-
-MODULE_LICENSE("GPL");
diff --git a/arch/powerpc/platforms/cell/spufs/sputrace.h b/arch/powerpc/platforms/cell/spufs/sputrace.h
new file mode 100644
index 000000000000..db2656aa4103
--- /dev/null
+++ b/arch/powerpc/platforms/cell/spufs/sputrace.h
@@ -0,0 +1,39 @@
+#if !defined(_TRACE_SPUFS_H) || defined(TRACE_HEADER_MULTI_READ)
+#define _TRACE_SPUFS_H
+
+#include <linux/tracepoint.h>
+
+#undef TRACE_SYSTEM
+#define TRACE_SYSTEM spufs
+
+TRACE_EVENT(spufs_context,
+        TP_PROTO(struct spu_context *ctx, struct spu *spu, const char *name),
+        TP_ARGS(ctx, spu, name),
+
+        TP_STRUCT__entry(
+                __field(const char *, name)
+                __field(int, owner_tid)
+                __field(int, number)
+        ),
+
+        TP_fast_assign(
+                __entry->name = name;
+                __entry->owner_tid = ctx->tid;
+                __entry->number = spu ? spu->number : -1;
+        ),
+
+        TP_printk("%s (ctxthread = %d, spu = %d)",
+                __entry->name, __entry->owner_tid, __entry->number)
+);
+
+#define spu_context_trace(name, ctx, spu) \
+        trace_spufs_context(ctx, spu, __stringify(name))
+#define spu_context_nospu_trace(name, ctx) \
+        trace_spufs_context(ctx, NULL, __stringify(name))
+
+#endif /* _TRACE_SPUFS_H */
+
+#undef TRACE_INCLUDE_PATH
+#define TRACE_INCLUDE_PATH .
+#define TRACE_INCLUDE_FILE sputrace
+#include <trace/define_trace.h>
diff --git a/arch/powerpc/platforms/iseries/exception.S b/arch/powerpc/platforms/iseries/exception.S
index 2f581521eb9b..5369653dcf6a 100644
--- a/arch/powerpc/platforms/iseries/exception.S
+++ b/arch/powerpc/platforms/iseries/exception.S
@@ -47,7 +47,7 @@ system_reset_iSeries:
         LOAD_REG_ADDR(r13, paca)
         mulli   r0,r23,PACA_SIZE
         add     r13,r13,r0
-        mtspr   SPRN_SPRG3,r13          /* Save it away for the future */
+        mtspr   SPRN_SPRG_PACA,r13      /* Save it away for the future */
         mfmsr   r24
         ori     r24,r24,MSR_RI
         mtmsrd  r24                     /* RI on */
@@ -116,7 +116,7 @@ iSeries_secondary_smp_loop:
 #endif /* CONFIG_SMP */
         li      r0,-1                   /* r0=-1 indicates a Hypervisor call */
         sc                              /* Invoke the hypervisor via a system call */
-        mfspr   r13,SPRN_SPRG3          /* Put r13 back ???? */
+        mfspr   r13,SPRN_SPRG_PACA      /* Put r13 back ???? */
         b       2b                      /* If SMP not configured, secondaries
                                          * loop forever */
 
@@ -126,34 +126,45 @@ iSeries_secondary_smp_loop:
 
         .globl data_access_iSeries
 data_access_iSeries:
-        mtspr   SPRN_SPRG1,r13
+        mtspr   SPRN_SPRG_SCRATCH0,r13
 BEGIN_FTR_SECTION
-        mtspr   SPRN_SPRG2,r12
-        mfspr   r13,SPRN_DAR
-        mfspr   r12,SPRN_DSISR
-        srdi    r13,r13,60
-        rlwimi  r13,r12,16,0x20
-        mfcr    r12
-        cmpwi   r13,0x2c
+        mfspr   r13,SPRN_SPRG_PACA
+        std     r9,PACA_EXSLB+EX_R9(r13)
+        std     r10,PACA_EXSLB+EX_R10(r13)
+        mfspr   r10,SPRN_DAR
+        mfspr   r9,SPRN_DSISR
+        srdi    r10,r10,60
+        rlwimi  r10,r9,16,0x20
+        mfcr    r9
+        cmpwi   r10,0x2c
         beq     .do_stab_bolted_iSeries
-        mtcrf   0x80,r12
-        mfspr   r12,SPRN_SPRG2
-END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
+        ld      r10,PACA_EXSLB+EX_R10(r13)
+        std     r11,PACA_EXGEN+EX_R11(r13)
+        ld      r11,PACA_EXSLB+EX_R9(r13)
+        std     r12,PACA_EXGEN+EX_R12(r13)
+        mfspr   r12,SPRN_SPRG_SCRATCH0
+        std     r10,PACA_EXGEN+EX_R10(r13)
+        std     r11,PACA_EXGEN+EX_R9(r13)
+        std     r12,PACA_EXGEN+EX_R13(r13)
+        EXCEPTION_PROLOG_ISERIES_1
+FTR_SECTION_ELSE
         EXCEPTION_PROLOG_1(PACA_EXGEN)
         EXCEPTION_PROLOG_ISERIES_1
+ALT_FTR_SECTION_END_IFCLR(CPU_FTR_SLB)
         b       data_access_common
 
 .do_stab_bolted_iSeries:
-        mtcrf   0x80,r12
-        mfspr   r12,SPRN_SPRG2
-        EXCEPTION_PROLOG_1(PACA_EXSLB)
+        std     r11,PACA_EXSLB+EX_R11(r13)
+        std     r12,PACA_EXSLB+EX_R12(r13)
+        mfspr   r10,SPRN_SPRG_SCRATCH0
+        std     r10,PACA_EXSLB+EX_R13(r13)
         EXCEPTION_PROLOG_ISERIES_1
         b       .do_stab_bolted
 
         .globl  data_access_slb_iSeries
 data_access_slb_iSeries:
-        mtspr   SPRN_SPRG1,r13          /* save r13 */
-        mfspr   r13,SPRN_SPRG3          /* get paca address into r13 */
+        mtspr   SPRN_SPRG_SCRATCH0,r13  /* save r13 */
+        mfspr   r13,SPRN_SPRG_PACA      /* get paca address into r13 */
         std     r3,PACA_EXSLB+EX_R3(r13)
         mfspr   r3,SPRN_DAR
         std     r9,PACA_EXSLB+EX_R9(r13)
@@ -165,7 +176,7 @@ data_access_slb_iSeries:
         std     r10,PACA_EXSLB+EX_R10(r13)
         std     r11,PACA_EXSLB+EX_R11(r13)
         std     r12,PACA_EXSLB+EX_R12(r13)
-        mfspr   r10,SPRN_SPRG1
+        mfspr   r10,SPRN_SPRG_SCRATCH0
         std     r10,PACA_EXSLB+EX_R13(r13)
         ld      r12,PACALPPACAPTR(r13)
         ld      r12,LPPACASRR1(r12)
@@ -175,8 +186,8 @@ data_access_slb_iSeries:
 
         .globl  instruction_access_slb_iSeries
 instruction_access_slb_iSeries:
-        mtspr   SPRN_SPRG1,r13          /* save r13 */
-        mfspr   r13,SPRN_SPRG3          /* get paca address into r13 */
+        mtspr   SPRN_SPRG_SCRATCH0,r13  /* save r13 */
+        mfspr   r13,SPRN_SPRG_PACA      /* get paca address into r13 */
         std     r3,PACA_EXSLB+EX_R3(r13)
         ld      r3,PACALPPACAPTR(r13)
         ld      r3,LPPACASRR0(r3)       /* get SRR0 value */
@@ -189,7 +200,7 @@ instruction_access_slb_iSeries:
         std     r10,PACA_EXSLB+EX_R10(r13)
         std     r11,PACA_EXSLB+EX_R11(r13)
         std     r12,PACA_EXSLB+EX_R12(r13)
-        mfspr   r10,SPRN_SPRG1
+        mfspr   r10,SPRN_SPRG_SCRATCH0
         std     r10,PACA_EXSLB+EX_R13(r13)
         ld      r12,PACALPPACAPTR(r13)
         ld      r12,LPPACASRR1(r12)
@@ -200,7 +211,7 @@ slb_miss_user_iseries:
         std     r10,PACA_EXGEN+EX_R10(r13)
         std     r11,PACA_EXGEN+EX_R11(r13)
         std     r12,PACA_EXGEN+EX_R12(r13)
-        mfspr   r10,SPRG1
+        mfspr   r10,SPRG_SCRATCH0
         ld      r11,PACA_EXSLB+EX_R9(r13)
         ld      r12,PACA_EXSLB+EX_R3(r13)
         std     r10,PACA_EXGEN+EX_R13(r13)
@@ -221,7 +232,7 @@ slb_miss_user_iseries:
         .globl  system_call_iSeries
 system_call_iSeries:
         mr      r9,r13
-        mfspr   r13,SPRN_SPRG3
+        mfspr   r13,SPRN_SPRG_PACA
         EXCEPTION_PROLOG_ISERIES_1
         b       system_call_common
 
diff --git a/arch/powerpc/platforms/iseries/exception.h b/arch/powerpc/platforms/iseries/exception.h
index ced45a8fa1aa..bae3fba5ad8e 100644
--- a/arch/powerpc/platforms/iseries/exception.h
+++ b/arch/powerpc/platforms/iseries/exception.h
@@ -24,7 +24,7 @@
  *  as published by the Free Software Foundation; either version
  *  2 of the License, or (at your option) any later version.
  */
-#include <asm/exception.h>
+#include <asm/exception-64s.h>
 
 #define EXCEPTION_PROLOG_ISERIES_1                                      \
         mfmsr   r10;                                                    \
@@ -38,7 +38,7 @@
         .globl label##_iSeries;                                         \
 label##_iSeries:                                                        \
         HMT_MEDIUM;                                                     \
-        mtspr   SPRN_SPRG1,r13;         /* save r13 */                  \
+        mtspr   SPRN_SPRG_SCRATCH0,r13; /* save r13 */                  \
         EXCEPTION_PROLOG_1(area);                                       \
         EXCEPTION_PROLOG_ISERIES_1;                                     \
         b       label##_common
@@ -47,7 +47,7 @@ label##_iSeries:							\
         .globl label##_iSeries;                                         \
 label##_iSeries:                                                        \
         HMT_MEDIUM;                                                     \
-        mtspr   SPRN_SPRG1,r13;         /* save r13 */                  \
+        mtspr   SPRN_SPRG_SCRATCH0,r13; /* save r13 */                  \
         EXCEPTION_PROLOG_1(PACA_EXGEN);                                 \
         lbz     r10,PACASOFTIRQEN(r13);                                 \
         cmpwi   0,r10,0;                                                \
diff --git a/arch/powerpc/platforms/pasemi/idle.c b/arch/powerpc/platforms/pasemi/idle.c
index 43911d8b0206..75b296bc51af 100644
--- a/arch/powerpc/platforms/pasemi/idle.c
+++ b/arch/powerpc/platforms/pasemi/idle.c
@@ -90,7 +90,7 @@ machine_late_initcall(pasemi, pasemi_idle_init);
 static int __init idle_param(char *p)
 {
         int i;
-        for (i = 0; i < sizeof(modes)/sizeof(struct sleep_mode); i++) {
+        for (i = 0; i < ARRAY_SIZE(modes); i++) {
                 if (!strcmp(modes[i].name, p)) {
                         current_mode = i;
                         break;
diff --git a/arch/powerpc/platforms/powermac/feature.c b/arch/powerpc/platforms/powermac/feature.c
index e6c0040ee797..fbc9bbd74dbd 100644
--- a/arch/powerpc/platforms/powermac/feature.c
+++ b/arch/powerpc/platforms/powermac/feature.c
@@ -2419,13 +2419,13 @@ static int __init probe_motherboard(void)
         dt = of_find_node_by_name(NULL, "device-tree");
         if (dt != NULL)
                 model = of_get_property(dt, "model", NULL);
-        for(i=0; model && i<(sizeof(pmac_mb_defs)/sizeof(struct pmac_mb_def)); i++) {
+        for(i=0; model && i<ARRAY_SIZE(pmac_mb_defs); i++) {
             if (strcmp(model, pmac_mb_defs[i].model_string) == 0) {
                 pmac_mb = pmac_mb_defs[i];
                 goto found;
             }
         }
-        for(i=0; i<(sizeof(pmac_mb_defs)/sizeof(struct pmac_mb_def)); i++) {
+        for(i=0; i<ARRAY_SIZE(pmac_mb_defs); i++) {
             if (machine_is_compatible(pmac_mb_defs[i].model_string)) {
                 pmac_mb = pmac_mb_defs[i];
                 goto found;
@@ -2589,9 +2589,16 @@ static void __init probe_uninorth(void)
         if (address == 0)
                 return;
         uninorth_base = ioremap(address, 0x40000);
+        if (uninorth_base == NULL)
+                return;
         uninorth_rev = in_be32(UN_REG(UNI_N_VERSION));
-        if (uninorth_maj == 3 || uninorth_maj == 4)
+        if (uninorth_maj == 3 || uninorth_maj == 4) {
                 u3_ht_base = ioremap(address + U3_HT_CONFIG_BASE, 0x1000);
+                if (u3_ht_base == NULL) {
+                        iounmap(uninorth_base);
+                        return;
+                }
+        }
 
         printk(KERN_INFO "Found %s memory controller & host bridge"
                " @ 0x%08x revision: 0x%02x\n", uninorth_maj == 3 ? "U3" :
diff --git a/arch/powerpc/platforms/powermac/smp.c b/arch/powerpc/platforms/powermac/smp.c
index 6d4da7b46b41..937a38e73178 100644
--- a/arch/powerpc/platforms/powermac/smp.c
+++ b/arch/powerpc/platforms/powermac/smp.c
@@ -408,7 +408,7 @@ static void __init smp_psurge_setup_cpu(int cpu_nr)
         /* reset the entry point so if we get another intr we won't
          * try to startup again */
         out_be32(psurge_start, 0x100);
-        if (setup_irq(30, &psurge_irqaction))
+        if (setup_irq(irq_create_mapping(NULL, 30), &psurge_irqaction))
                 printk(KERN_ERR "Couldn't get primary IPI interrupt");
 }
 
diff --git a/arch/powerpc/platforms/ps3/mm.c b/arch/powerpc/platforms/ps3/mm.c
index 846eb8b57fd1..189a25b80735 100644
--- a/arch/powerpc/platforms/ps3/mm.c
+++ b/arch/powerpc/platforms/ps3/mm.c
@@ -23,8 +23,8 @@
 #include <linux/memory_hotplug.h>
 #include <linux/lmb.h>
 
+#include <asm/cell-regs.h>
 #include <asm/firmware.h>
-#include <asm/iommu.h>
 #include <asm/prom.h>
 #include <asm/udbg.h>
 #include <asm/lv1call.h>
diff --git a/arch/powerpc/platforms/ps3/system-bus.c b/arch/powerpc/platforms/ps3/system-bus.c
index 3f763c5284ac..676f989ed4e4 100644
--- a/arch/powerpc/platforms/ps3/system-bus.c
+++ b/arch/powerpc/platforms/ps3/system-bus.c
@@ -27,7 +27,7 @@
 #include <asm/udbg.h>
 #include <asm/lv1call.h>
 #include <asm/firmware.h>
-#include <asm/iommu.h>
+#include <asm/cell-regs.h>
 
 #include "platform.h"
 
diff --git a/arch/powerpc/platforms/pseries/smp.c b/arch/powerpc/platforms/pseries/smp.c
index 1f8f6cfb94f7..440000cc7130 100644
--- a/arch/powerpc/platforms/pseries/smp.c
+++ b/arch/powerpc/platforms/pseries/smp.c
@@ -56,8 +56,6 @@
  */
 static cpumask_t of_spin_map;
 
-extern void generic_secondary_smp_init(unsigned long);
-
 /**
  * smp_startup_cpu() - start the given cpu
  *
diff --git a/arch/powerpc/sysdev/fsl_rio.c b/arch/powerpc/sysdev/fsl_rio.c
index cbb3bed75d3c..757a83fe5e59 100644
--- a/arch/powerpc/sysdev/fsl_rio.c
+++ b/arch/powerpc/sysdev/fsl_rio.c
@@ -1057,6 +1057,10 @@ int fsl_rio_setup(struct of_device *dev)
                         law_start, law_size);
 
         ops = kmalloc(sizeof(struct rio_ops), GFP_KERNEL);
+        if (!ops) {
+                rc = -ENOMEM;
+                goto err_ops;
+        }
         ops->lcread = fsl_local_config_read;
         ops->lcwrite = fsl_local_config_write;
         ops->cread = fsl_rio_config_read;
@@ -1064,6 +1068,10 @@ int fsl_rio_setup(struct of_device *dev)
         ops->dsend = fsl_rio_doorbell_send;
 
         port = kzalloc(sizeof(struct rio_mport), GFP_KERNEL);
+        if (!port) {
+                rc = -ENOMEM;
+                goto err_port;
+        }
         port->id = 0;
         port->index = 0;
 
@@ -1071,7 +1079,7 @@ int fsl_rio_setup(struct of_device *dev)
         if (!priv) {
                 printk(KERN_ERR "Can't alloc memory for 'priv'\n");
                 rc = -ENOMEM;
-                goto err;
+                goto err_priv;
         }
 
         INIT_LIST_HEAD(&port->dbells);
@@ -1169,11 +1177,13 @@ int fsl_rio_setup(struct of_device *dev)
 
         return 0;
 err:
-        if (priv)
-                iounmap(priv->regs_win);
-        kfree(ops);
+        iounmap(priv->regs_win);
         kfree(priv);
+err_priv:
         kfree(port);
+err_port:
+        kfree(ops);
+err_ops:
         return rc;
 }
 
diff --git a/arch/powerpc/sysdev/ipic.c b/arch/powerpc/sysdev/ipic.c
index 69e2630c9062..cb7689c4bfbd 100644
--- a/arch/powerpc/sysdev/ipic.c
+++ b/arch/powerpc/sysdev/ipic.c
@@ -735,8 +735,10 @@ struct ipic * __init ipic_init(struct device_node *node, unsigned int flags)
         ipic->irqhost = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR,
                                        NR_IPIC_INTS,
                                        &ipic_host_ops, 0);
-        if (ipic->irqhost == NULL)
+        if (ipic->irqhost == NULL) {
+                kfree(ipic);
                 return NULL;
+        }
 
         ipic->regs = ioremap(res.start, res.end - res.start + 1);
 
@@ -781,6 +783,9 @@ struct ipic * __init ipic_init(struct device_node *node, unsigned int flags)
         primary_ipic = ipic;
         irq_set_default_host(primary_ipic->irqhost);
 
+        ipic_write(ipic->regs, IPIC_SIMSR_H, 0);
+        ipic_write(ipic->regs, IPIC_SIMSR_L, 0);
+
         printk ("IPIC (%d IRQ sources) at %p\n", NR_IPIC_INTS,
                         primary_ipic->regs);
 
diff --git a/arch/powerpc/sysdev/mmio_nvram.c b/arch/powerpc/sysdev/mmio_nvram.c
index 7b49633a4bd0..207324209065 100644
--- a/arch/powerpc/sysdev/mmio_nvram.c
+++ b/arch/powerpc/sysdev/mmio_nvram.c
@@ -53,6 +53,23 @@ static ssize_t mmio_nvram_read(char *buf, size_t count, loff_t *index)
         return count;
 }
 
+static unsigned char mmio_nvram_read_val(int addr)
+{
+        unsigned long flags;
+        unsigned char val;
+
+        if (addr >= mmio_nvram_len)
+                return 0xff;
+
+        spin_lock_irqsave(&mmio_nvram_lock, flags);
+
+        val = ioread8(mmio_nvram_start + addr);
+
+        spin_unlock_irqrestore(&mmio_nvram_lock, flags);
+
+        return val;
+}
+
 static ssize_t mmio_nvram_write(char *buf, size_t count, loff_t *index)
 {
         unsigned long flags;
@@ -72,6 +89,19 @@ static ssize_t mmio_nvram_write(char *buf, size_t count, loff_t *index)
         return count;
 }
 
+void mmio_nvram_write_val(int addr, unsigned char val)
+{
+        unsigned long flags;
+
+        if (addr < mmio_nvram_len) {
+                spin_lock_irqsave(&mmio_nvram_lock, flags);
+
+                iowrite8(val, mmio_nvram_start + addr);
+
+                spin_unlock_irqrestore(&mmio_nvram_lock, flags);
+        }
+}
+
 static ssize_t mmio_nvram_get_size(void)
 {
         return mmio_nvram_len;
@@ -114,6 +144,8 @@ int __init mmio_nvram_init(void)
         printk(KERN_INFO "mmio NVRAM, %luk at 0x%lx mapped to %p\n",
                mmio_nvram_len >> 10, nvram_addr, mmio_nvram_start);
 
+        ppc_md.nvram_read_val   = mmio_nvram_read_val;
+        ppc_md.nvram_write_val  = mmio_nvram_write_val;
         ppc_md.nvram_read       = mmio_nvram_read;
         ppc_md.nvram_write      = mmio_nvram_write;
         ppc_md.nvram_size       = mmio_nvram_get_size;
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index 3981ae4cb58e..30c44e6b0413 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -230,14 +230,16 @@ static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigne
 {
         unsigned int    isu = src_no >> mpic->isu_shift;
         unsigned int    idx = src_no & mpic->isu_mask;
+        unsigned int    val;
 
+        val = _mpic_read(mpic->reg_type, &mpic->isus[isu],
+                         reg + (idx * MPIC_INFO(IRQ_STRIDE)));
 #ifdef CONFIG_MPIC_BROKEN_REGREAD
         if (reg == 0)
-                return mpic->isu_reg0_shadow[idx];
-        else
+                val = (val & (MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY)) |
+                        mpic->isu_reg0_shadow[src_no];
 #endif
-                return _mpic_read(mpic->reg_type, &mpic->isus[isu],
-                                  reg + (idx * MPIC_INFO(IRQ_STRIDE)));
+        return val;
 }
 
 static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
@@ -251,7 +253,8 @@ static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
 
 #ifdef CONFIG_MPIC_BROKEN_REGREAD
         if (reg == 0)
-                mpic->isu_reg0_shadow[idx] = value;
+                mpic->isu_reg0_shadow[src_no] =
+                        value & ~(MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY);
 #endif
 }
 
diff --git a/arch/powerpc/sysdev/qe_lib/qe_ic.c b/arch/powerpc/sysdev/qe_lib/qe_ic.c
index 074905c3ee5a..3faa42e03a85 100644
--- a/arch/powerpc/sysdev/qe_lib/qe_ic.c
+++ b/arch/powerpc/sysdev/qe_lib/qe_ic.c
@@ -339,8 +339,10 @@ void __init qe_ic_init(struct device_node *node, unsigned int flags,
 
         qe_ic->irqhost = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR,
                                         NR_QE_IC_INTS, &qe_ic_host_ops, 0);
-        if (qe_ic->irqhost == NULL)
+        if (qe_ic->irqhost == NULL) {
+                kfree(qe_ic);
                 return;
+        }
 
         qe_ic->regs = ioremap(res.start, res.end - res.start + 1);
 
@@ -352,6 +354,7 @@ void __init qe_ic_init(struct device_node *node, unsigned int flags,
 
         if (qe_ic->virq_low == NO_IRQ) {
                 printk(KERN_ERR "Failed to map QE_IC low IRQ\n");
+                kfree(qe_ic);
                 return;
         }
 
diff --git a/arch/powerpc/xmon/Makefile b/arch/powerpc/xmon/Makefile
index 85ab97ab840a..faa81b6a6612 100644
--- a/arch/powerpc/xmon/Makefile
+++ b/arch/powerpc/xmon/Makefile
@@ -2,6 +2,8 @@
 
 subdir-ccflags-$(CONFIG_PPC_WERROR) := -Werror
 
+GCOV_PROFILE := n
+
 ifdef CONFIG_PPC64
 EXTRA_CFLAGS += -mno-minimal-toc
 endif
diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
index e1f33a81e5e1..0e09a45ac79a 100644
--- a/arch/powerpc/xmon/xmon.c
+++ b/arch/powerpc/xmon/xmon.c
@@ -2570,7 +2570,7 @@ static void xmon_print_symbol(unsigned long address, const char *mid,
         printf("%s", after);
 }
 
-#ifdef CONFIG_PPC64
+#ifdef CONFIG_PPC_BOOK3S_64
 static void dump_slb(void)
 {
         int i;
diff --git a/arch/sh/boards/mach-se/7724/setup.c b/arch/sh/boards/mach-se/7724/setup.c
index 8fed45a2fb85..15456a0773bf 100644
--- a/arch/sh/boards/mach-se/7724/setup.c
+++ b/arch/sh/boards/mach-se/7724/setup.c
@@ -238,7 +238,7 @@ static struct platform_device ceu1_device = {
         },
 };
 
-/* KEYSC */
+/* KEYSC in SoC (Needs SW33-2 set to ON) */
 static struct sh_keysc_info keysc_info = {
         .mode = SH_KEYSC_MODE_1,
         .scan_timing = 10,
@@ -255,12 +255,13 @@ static struct sh_keysc_info keysc_info = {
 
 static struct resource keysc_resources[] = {
         [0] = {
-                .start  = 0x1a204000,
-                .end    = 0x1a20400f,
+                .name   = "KEYSC",
+                .start  = 0x044b0000,
+                .end    = 0x044b000f,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = IRQ0_KEY,
+                .start  = 79,
                 .flags  = IORESOURCE_IRQ,
         },
 };
diff --git a/arch/sh/kernel/cpu/shmobile/sleep.S b/arch/sh/kernel/cpu/shmobile/sleep.S
index 5d888ef53d82..baf2d7d46b05 100644
--- a/arch/sh/kernel/cpu/shmobile/sleep.S
+++ b/arch/sh/kernel/cpu/shmobile/sleep.S
@@ -26,8 +26,30 @@ ENTRY(sh_mobile_standby)
 
         tst     #SUSP_SH_SF, r0
         bt      skip_set_sf
+#ifdef CONFIG_CPU_SUBTYPE_SH7724
+        /* DBSC: put memory in self-refresh mode */
 
-        /* SDRAM: disable power down and put in self-refresh mode */
+        mov.l   dben_reg, r4
+        mov.l   dben_data0, r1
+        mov.l   r1, @r4
+
+        mov.l   dbrfpdn0_reg, r4
+        mov.l   dbrfpdn0_data0, r1
+        mov.l   r1, @r4
+
+        mov.l   dbcmdcnt_reg, r4
+        mov.l   dbcmdcnt_data0, r1
+        mov.l   r1, @r4
+
+        mov.l   dbcmdcnt_reg, r4
+        mov.l   dbcmdcnt_data1, r1
+        mov.l   r1, @r4
+
+        mov.l   dbrfpdn0_reg, r4
+        mov.l   dbrfpdn0_data1, r1
+        mov.l   r1, @r4
+#else
+        /* SBSC: disable power down and put in self-refresh mode */
         mov.l   1f, r4
         mov.l   2f, r1
         mov.l   @r4, r2
@@ -35,6 +57,7 @@ ENTRY(sh_mobile_standby)
         mov.l   3f, r3
         and     r3, r2
         mov.l   r2, @r4
+#endif
 
 skip_set_sf:
         tst     #SUSP_SH_SLEEP, r0
@@ -84,7 +107,36 @@ done_sleep:
         tst     #SUSP_SH_SF, r0
         bt      skip_restore_sf
 
-        /* SDRAM: set auto-refresh mode */
+#ifdef CONFIG_CPU_SUBTYPE_SH7724
+        /* DBSC: put memory in auto-refresh mode */
+
+        mov.l   dbrfpdn0_reg, r4
+        mov.l   dbrfpdn0_data0, r1
+        mov.l   r1, @r4
+
+        /* sleep 140 ns */
+        nop
+        nop
+        nop
+        nop
+
+        mov.l   dbcmdcnt_reg, r4
+        mov.l   dbcmdcnt_data0, r1
+        mov.l   r1, @r4
+
+        mov.l   dbcmdcnt_reg, r4
+        mov.l   dbcmdcnt_data1, r1
+        mov.l   r1, @r4
+
+        mov.l   dben_reg, r4
+        mov.l   dben_data1, r1
+        mov.l   r1, @r4
+
+        mov.l   dbrfpdn0_reg, r4
+        mov.l   dbrfpdn0_data2, r1
+        mov.l   r1, @r4
+#else
+        /* SBSC: set auto-refresh mode */
         mov.l   1f, r4
         mov.l   @r4, r2
         mov.l   4f, r3
@@ -98,15 +150,29 @@ done_sleep:
         add     r4, r3
         or      r2, r3
         mov.l   r3, @r1
+#endif
 skip_restore_sf:
         rts
          nop
 
         .balign 4
+#ifdef CONFIG_CPU_SUBTYPE_SH7724
+dben_reg:       .long   0xfd000010 /* DBEN */
+dben_data0:     .long   0
+dben_data1:     .long   1
+dbrfpdn0_reg:   .long   0xfd000040 /* DBRFPDN0 */
+dbrfpdn0_data0: .long   0
+dbrfpdn0_data1: .long   1
+dbrfpdn0_data2: .long   0x00010000
+dbcmdcnt_reg:   .long   0xfd000014 /* DBCMDCNT */
+dbcmdcnt_data0: .long   2
+dbcmdcnt_data1: .long   4
+#else
 1:      .long   0xfe400008 /* SDCR0 */
 2:      .long   0x00000400
 3:      .long   0xffff7fff
 4:      .long   0xfffffbff
+#endif
 5:      .long   0xa4150020 /* STBCR */
 6:      .long   0xfe40001c /* RTCOR */
 7:      .long   0xfe400018 /* RTCNT */
diff --git a/arch/sparc/kernel/smp_64.c b/arch/sparc/kernel/smp_64.c
index fa44eaf8d897..3691907a43b4 100644
--- a/arch/sparc/kernel/smp_64.c
+++ b/arch/sparc/kernel/smp_64.c
@@ -1499,7 +1499,7 @@ void __init setup_per_cpu_areas(void)
         dyn_size = pcpur_size - static_size - PERCPU_MODULE_RESERVE;
 
 
-        ptrs_size = PFN_ALIGN(num_possible_cpus() * sizeof(pcpur_ptrs[0]));
+        ptrs_size = PFN_ALIGN(nr_cpu_ids * sizeof(pcpur_ptrs[0]));
         pcpur_ptrs = alloc_bootmem(ptrs_size);
 
         for_each_possible_cpu(cpu) {
@@ -1514,7 +1514,7 @@ void __init setup_per_cpu_areas(void)
 
         /* allocate address and map */
         vm.flags = VM_ALLOC;
-        vm.size = num_possible_cpus() * PCPU_CHUNK_SIZE;
+        vm.size = nr_cpu_ids * PCPU_CHUNK_SIZE;
         vm_area_register_early(&vm, PCPU_CHUNK_SIZE);
 
         for_each_possible_cpu(cpu) {
diff --git a/arch/x86/include/asm/uv/uv_bau.h b/arch/x86/include/asm/uv/uv_bau.h
index bddd44f2f0ab..80e2984f521c 100644
--- a/arch/x86/include/asm/uv/uv_bau.h
+++ b/arch/x86/include/asm/uv/uv_bau.h
@@ -133,7 +133,7 @@ struct bau_msg_payload {
  * see table 4.2.3.0.1 in broacast_assist spec.
  */
 struct bau_msg_header {
-        unsigned int dest_subnodeid:6;  /* must be zero */
+        unsigned int dest_subnodeid:6;  /* must be 0x10, for the LB */
         /* bits 5:0 */
         unsigned int base_dest_nodeid:15; /* nasid>>1 (pnode) of */
         /* bits 20:6 */                   /* first bit in node_map */
diff --git a/arch/x86/kernel/apic/x2apic_uv_x.c b/arch/x86/kernel/apic/x2apic_uv_x.c
index 832e908adcb5..601159374e87 100644
--- a/arch/x86/kernel/apic/x2apic_uv_x.c
+++ b/arch/x86/kernel/apic/x2apic_uv_x.c
@@ -46,7 +46,7 @@ static int early_get_nodeid(void)
         return node_id.s.node_id;
 }
 
-static int uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
+static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
 {
         if (!strcmp(oem_id, "SGI")) {
                 if (!strcmp(oem_table_id, "UVL"))
@@ -253,7 +253,7 @@ static void uv_send_IPI_self(int vector)
         apic_write(APIC_SELF_IPI, vector);
 }
 
-struct apic apic_x2apic_uv_x = {
+struct apic __refdata apic_x2apic_uv_x = {
 
         .name                           = "UV large system",
         .probe                          = NULL,
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index 1cfb623ce11c..01213048f62f 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -1226,8 +1226,13 @@ static void mce_init(void)
 }
 
 /* Add per CPU specific workarounds here */
-static void mce_cpu_quirks(struct cpuinfo_x86 *c)
+static int mce_cpu_quirks(struct cpuinfo_x86 *c)
 {
+        if (c->x86_vendor == X86_VENDOR_UNKNOWN) {
+                pr_info("MCE: unknown CPU type - not enabling MCE support.\n");
+                return -EOPNOTSUPP;
+        }
+
         /* This should be disabled by the BIOS, but isn't always */
         if (c->x86_vendor == X86_VENDOR_AMD) {
                 if (c->x86 == 15 && banks > 4) {
@@ -1273,11 +1278,20 @@ static void mce_cpu_quirks(struct cpuinfo_x86 *c)
                 if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
                         monarch_timeout < 0)
                         monarch_timeout = USEC_PER_SEC;
+
+                /*
+                 * There are also broken BIOSes on some Pentium M and
+                 * earlier systems:
+                 */
+                if (c->x86 == 6 && c->x86_model <= 13 && mce_bootlog < 0)
+                        mce_bootlog = 0;
         }
         if (monarch_timeout < 0)
                 monarch_timeout = 0;
         if (mce_bootlog != 0)
                 mce_panic_timeout = 30;
+
+        return 0;
 }
 
 static void __cpuinit mce_ancient_init(struct cpuinfo_x86 *c)
@@ -1338,11 +1352,10 @@ void __cpuinit mcheck_init(struct cpuinfo_x86 *c)
         if (!mce_available(c))
                 return;
 
-        if (mce_cap_init() < 0) {
+        if (mce_cap_init() < 0 || mce_cpu_quirks(c) < 0) {
                 mce_disabled = 1;
                 return;
         }
-        mce_cpu_quirks(c);
 
         machine_check_vector = do_machine_check;
 
diff --git a/arch/x86/kernel/cpu/mcheck/therm_throt.c b/arch/x86/kernel/cpu/mcheck/therm_throt.c
index 8bc64cfbe936..5957a93e5173 100644
--- a/arch/x86/kernel/cpu/mcheck/therm_throt.c
+++ b/arch/x86/kernel/cpu/mcheck/therm_throt.c
@@ -116,11 +116,14 @@ static int therm_throt_process(int curr)
                        cpu, __get_cpu_var(thermal_throttle_count));
 
                 add_taint(TAINT_MACHINE_CHECK);
-        } else if (was_throttled) {
+                return 1;
+        }
+        if (was_throttled) {
                 printk(KERN_INFO "CPU%d: Temperature/speed normal\n", cpu);
+                return 1;
         }
 
-        return 1;
+        return 0;
 }
 
 #ifdef CONFIG_SYSFS
diff --git a/arch/x86/kernel/setup_percpu.c b/arch/x86/kernel/setup_percpu.c
index 29a3eef7cf4a..07d81916f212 100644
--- a/arch/x86/kernel/setup_percpu.c
+++ b/arch/x86/kernel/setup_percpu.c
@@ -165,7 +165,7 @@ static ssize_t __init setup_pcpu_lpage(size_t static_size, bool chosen)
 
         if (!chosen) {
                 size_t vm_size = VMALLOC_END - VMALLOC_START;
-                size_t tot_size = num_possible_cpus() * PMD_SIZE;
+                size_t tot_size = nr_cpu_ids * PMD_SIZE;
 
                 /* on non-NUMA, embedding is better */
                 if (!pcpu_need_numa())
@@ -199,7 +199,7 @@ static ssize_t __init setup_pcpu_lpage(size_t static_size, bool chosen)
         dyn_size = pcpul_size - static_size - PERCPU_FIRST_CHUNK_RESERVE;
 
         /* allocate pointer array and alloc large pages */
-        map_size = PFN_ALIGN(num_possible_cpus() * sizeof(pcpul_map[0]));
+        map_size = PFN_ALIGN(nr_cpu_ids * sizeof(pcpul_map[0]));
         pcpul_map = alloc_bootmem(map_size);
 
         for_each_possible_cpu(cpu) {
@@ -228,7 +228,7 @@ static ssize_t __init setup_pcpu_lpage(size_t static_size, bool chosen)
 
         /* allocate address and map */
         pcpul_vm.flags = VM_ALLOC;
-        pcpul_vm.size = num_possible_cpus() * PMD_SIZE;
+        pcpul_vm.size = nr_cpu_ids * PMD_SIZE;
         vm_area_register_early(&pcpul_vm, PMD_SIZE);
 
         for_each_possible_cpu(cpu) {
@@ -250,8 +250,8 @@ static ssize_t __init setup_pcpu_lpage(size_t static_size, bool chosen)
                                      PMD_SIZE, pcpul_vm.addr, NULL);
 
         /* sort pcpul_map array for pcpu_lpage_remapped() */
-        for (i = 0; i < num_possible_cpus() - 1; i++)
-                for (j = i + 1; j < num_possible_cpus(); j++)
+        for (i = 0; i < nr_cpu_ids - 1; i++)
+                for (j = i + 1; j < nr_cpu_ids; j++)
                         if (pcpul_map[i].ptr > pcpul_map[j].ptr) {
                                 struct pcpul_ent tmp = pcpul_map[i];
                                 pcpul_map[i] = pcpul_map[j];
@@ -288,7 +288,7 @@ void *pcpu_lpage_remapped(void *kaddr)
 {
         void *pmd_addr = (void *)((unsigned long)kaddr & PMD_MASK);
         unsigned long offset = (unsigned long)kaddr & ~PMD_MASK;
-        int left = 0, right = num_possible_cpus() - 1;
+        int left = 0, right = nr_cpu_ids - 1;
         int pos;
 
         /* pcpul in use at all? */
@@ -377,7 +377,7 @@ static ssize_t __init setup_pcpu_4k(size_t static_size)
         pcpu4k_nr_static_pages = PFN_UP(static_size);
 
         /* unaligned allocations can't be freed, round up to page size */
-        pages_size = PFN_ALIGN(pcpu4k_nr_static_pages * num_possible_cpus()
+        pages_size = PFN_ALIGN(pcpu4k_nr_static_pages * nr_cpu_ids
                                * sizeof(pcpu4k_pages[0]));
         pcpu4k_pages = alloc_bootmem(pages_size);
 
diff --git a/arch/x86/kernel/tlb_uv.c b/arch/x86/kernel/tlb_uv.c
index 8ccabb8a2f6a..77b9689f8edb 100644
--- a/arch/x86/kernel/tlb_uv.c
+++ b/arch/x86/kernel/tlb_uv.c
@@ -744,6 +744,7 @@ uv_activation_descriptor_init(int node, int pnode)
                  * note that base_dest_nodeid is actually a nasid.
                  */
                 ad2->header.base_dest_nodeid = uv_partition_base_pnode << 1;
+                ad2->header.dest_subnodeid = 0x10; /* the LB */
                 ad2->header.command = UV_NET_ENDPOINT_INTD;
                 ad2->header.int_both = 1;
                 /*