1602 files changed, 53275 insertions, 54767 deletions
diff --git a/arch/Kconfig b/arch/Kconfig
index 684eb5af439d..1f9461b9cc89 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -145,6 +145,21 @@ config HAVE_DMA_ATTRS
 config USE_GENERIC_SMP_HELPERS
        bool
+config GENERIC_SMP_IDLE_THREAD
+       bool
+# Select if arch init_task initializer is different to init/init_task.c
+config ARCH_INIT_TASK
+       bool
+# Select if arch has its private alloc_task_struct() function
+config ARCH_TASK_STRUCT_ALLOCATOR
+        bool
+# Select if arch has its private alloc_thread_info() function
+config ARCH_THREAD_INFO_ALLOCATOR
+        bool
 config HAVE_REGS_AND_STACK_ACCESS_API
        bool
        help
@@ -216,4 +231,27 @@ config HAVE_CMPXCHG_DOUBLE
 config ARCH_WANT_OLD_COMPAT_IPC
        bool
+config HAVE_ARCH_SECCOMP_FILTER
+        bool
+        help
+          An arch should select this symbol if it provides all of these things:
+          - syscall_get_arch()
+          - syscall_get_arguments()
+          - syscall_rollback()
+          - syscall_set_return_value()
+          - SIGSYS siginfo_t support
+          - secure_computing is called from a ptrace_event()-safe context
+          - secure_computing return value is checked and a return value of -1
+            results in the system call being skipped immediately.
+config SECCOMP_FILTER
+        def_bool y
+        depends on HAVE_ARCH_SECCOMP_FILTER && SECCOMP && NET
+        help
+          Enable tasks to build secure computing environments defined
+          in terms of Berkeley Packet Filter programs which implement
+          task-defined system call filtering polices.
+          See Documentation/prctl/seccomp_filter.txt for details.
 source "kernel/gcov/Kconfig"
diff --git a/arch/alpha/Kconfig b/arch/alpha/Kconfig
index 56a4df952fb0..0893f023efb8 100644
--- a/arch/alpha/Kconfig
+++ b/arch/alpha/Kconfig
@@ -15,6 +15,7 @@ config ALPHA
        select GENERIC_IRQ_SHOW
        select ARCH_WANT_OPTIONAL_GPIOLIB
        select ARCH_HAVE_NMI_SAFE_CMPXCHG
+        select GENERIC_SMP_IDLE_THREAD
        help
          The Alpha is a 64-bit general-purpose processor designed and
          marketed by the Digital Equipment Corporation of blessed memory,
@@ -477,7 +478,7 @@ config ALPHA_BROKEN_IRQ_MASK
 config VGA_HOSE
        bool
-        depends on ALPHA_GENERIC || ALPHA_TITAN || ALPHA_MARVEL || ALPHA_TSUNAMI
+        depends on VGA_CONSOLE && (ALPHA_GENERIC || ALPHA_TITAN || ALPHA_MARVEL || ALPHA_TSUNAMI)
        default y
        help
          Support VGA on an arbitrary hose; needed for several platforms
diff --git a/arch/alpha/include/asm/atomic.h b/arch/alpha/include/asm/atomic.h
index f62251e82ffa..3bb7ffeae3bc 100644
--- a/arch/alpha/include/asm/atomic.h
+++ b/arch/alpha/include/asm/atomic.h
@@ -3,6 +3,7 @@
 #include <linux/types.h>
 #include <asm/barrier.h>
+#include <asm/cmpxchg.h>
 /*
 * Atomic operations that C can't guarantee us.  Useful for
@@ -168,73 +169,6 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
        return result;
 }
-/*
- * Atomic exchange routines.
- */
-#define __ASM__MB
-#define ____xchg(type, args...)         __xchg ## type ## _local(args)
-#define ____cmpxchg(type, args...)      __cmpxchg ## type ## _local(args)
-#include <asm/xchg.h>
-#define xchg_local(ptr,x)                                               \
-  ({                                                                    \
-     __typeof__(*(ptr)) _x_ = (x);                                      \
-     (__typeof__(*(ptr))) __xchg_local((ptr), (unsigned long)_x_,       \
-                                       sizeof(*(ptr)));                 \
-  })
-#define cmpxchg_local(ptr, o, n)                                        \
-  ({                                                                    \
-     __typeof__(*(ptr)) _o_ = (o);                                      \
-     __typeof__(*(ptr)) _n_ = (n);                                      \
-     (__typeof__(*(ptr))) __cmpxchg_local((ptr), (unsigned long)_o_,    \
-                                          (unsigned long)_n_,           \
-                                          sizeof(*(ptr)));              \
-  })
-#define cmpxchg64_local(ptr, o, n)                                      \
-  ({                                                                    \
-        BUILD_BUG_ON(sizeof(*(ptr)) != 8);                              \
-        cmpxchg_local((ptr), (o), (n));                                 \
-  })
-#ifdef CONFIG_SMP
-#undef __ASM__MB
-#define __ASM__MB       "\tmb\n"
-#endif
-#undef ____xchg
-#undef ____cmpxchg
-#define ____xchg(type, args...)         __xchg ##type(args)
-#define ____cmpxchg(type, args...)      __cmpxchg ##type(args)
-#include <asm/xchg.h>
-#define xchg(ptr,x)                                                     \
-  ({                                                                    \
-     __typeof__(*(ptr)) _x_ = (x);                                      \
-     (__typeof__(*(ptr))) __xchg((ptr), (unsigned long)_x_,             \
-                                 sizeof(*(ptr)));                       \
-  })
-#define cmpxchg(ptr, o, n)                                              \
-  ({                                                                    \
-     __typeof__(*(ptr)) _o_ = (o);                                      \
-     __typeof__(*(ptr)) _n_ = (n);                                      \
-     (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_,          \
-                                    (unsigned long)_n_, sizeof(*(ptr)));\
-  })
-#define cmpxchg64(ptr, o, n)                                            \
-  ({                                                                    \
-        BUILD_BUG_ON(sizeof(*(ptr)) != 8);                              \
-        cmpxchg((ptr), (o), (n));                                       \
-  })
-#undef __ASM__MB
-#undef ____cmpxchg
-#define __HAVE_ARCH_CMPXCHG 1
 #define atomic64_cmpxchg(v, old, new) (cmpxchg(&((v)->counter), old, new))
 #define atomic64_xchg(v, new) (xchg(&((v)->counter), new))
diff --git a/arch/alpha/include/asm/cmpxchg.h b/arch/alpha/include/asm/cmpxchg.h
new file mode 100644
index 000000000000..429e8cd0d78e
--- /dev/null
+++ b/arch/alpha/include/asm/cmpxchg.h
@@ -0,0 +1,71 @@
+#ifndef _ALPHA_CMPXCHG_H
+#define _ALPHA_CMPXCHG_H
+/*
+ * Atomic exchange routines.
+ */
+#define __ASM__MB
+#define ____xchg(type, args...)         __xchg ## type ## _local(args)
+#define ____cmpxchg(type, args...)      __cmpxchg ## type ## _local(args)
+#include <asm/xchg.h>
+#define xchg_local(ptr, x)                                              \
+({                                                                      \
+        __typeof__(*(ptr)) _x_ = (x);                                   \
+        (__typeof__(*(ptr))) __xchg_local((ptr), (unsigned long)_x_,    \
+                                       sizeof(*(ptr)));                 \
+})
+#define cmpxchg_local(ptr, o, n)                                        \
+({                                                                      \
+        __typeof__(*(ptr)) _o_ = (o);                                   \
+        __typeof__(*(ptr)) _n_ = (n);                                   \
+        (__typeof__(*(ptr))) __cmpxchg_local((ptr), (unsigned long)_o_, \
+                                          (unsigned long)_n_,           \
+                                          sizeof(*(ptr)));              \
+})
+#define cmpxchg64_local(ptr, o, n)                                      \
+({                                                                      \
+        BUILD_BUG_ON(sizeof(*(ptr)) != 8);                              \
+        cmpxchg_local((ptr), (o), (n));                                 \
+})
+#ifdef CONFIG_SMP
+#undef __ASM__MB
+#define __ASM__MB       "\tmb\n"
+#endif
+#undef ____xchg
+#undef ____cmpxchg
+#define ____xchg(type, args...)         __xchg ##type(args)
+#define ____cmpxchg(type, args...)      __cmpxchg ##type(args)
+#include <asm/xchg.h>
+#define xchg(ptr, x)                                                    \
+({                                                                      \
+        __typeof__(*(ptr)) _x_ = (x);                                   \
+        (__typeof__(*(ptr))) __xchg((ptr), (unsigned long)_x_,          \
+                                 sizeof(*(ptr)));                       \
+})
+#define cmpxchg(ptr, o, n)                                              \
+({                                                                      \
+        __typeof__(*(ptr)) _o_ = (o);                                   \
+        __typeof__(*(ptr)) _n_ = (n);                                   \
+        (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_,       \
+                                    (unsigned long)_n_, sizeof(*(ptr)));\
+})
+#define cmpxchg64(ptr, o, n)                                            \
+({                                                                      \
+        BUILD_BUG_ON(sizeof(*(ptr)) != 8);                              \
+        cmpxchg((ptr), (o), (n));                                       \
+})
+#undef __ASM__MB
+#undef ____cmpxchg
+#define __HAVE_ARCH_CMPXCHG 1
+#endif /* _ALPHA_CMPXCHG_H */
diff --git a/arch/alpha/include/asm/rtc.h b/arch/alpha/include/asm/rtc.h
index 1f7fba671ae6..d70408d36677 100644
--- a/arch/alpha/include/asm/rtc.h
+++ b/arch/alpha/include/asm/rtc.h
@@ -1,14 +1,10 @@
 #ifndef _ALPHA_RTC_H
 #define _ALPHA_RTC_H
-#if defined(CONFIG_ALPHA_GENERIC)
+#if defined(CONFIG_ALPHA_MARVEL) && defined(CONFIG_SMP) \
+ || defined(CONFIG_ALPHA_GENERIC)
 # define get_rtc_time           alpha_mv.rtc_get_time
 # define set_rtc_time           alpha_mv.rtc_set_time
-#else
-# if defined(CONFIG_ALPHA_MARVEL) && defined(CONFIG_SMP)
-#  define get_rtc_time          marvel_get_rtc_time
-#  define set_rtc_time          marvel_set_rtc_time
-# endif
 #endif
 #include <asm-generic/rtc.h>
diff --git a/arch/alpha/include/asm/xchg.h b/arch/alpha/include/asm/xchg.h
index 1d1b436fbff2..0ca9724597c1 100644
--- a/arch/alpha/include/asm/xchg.h
+++ b/arch/alpha/include/asm/xchg.h
@@ -1,10 +1,10 @@
-#ifndef _ALPHA_ATOMIC_H
+#ifndef _ALPHA_CMPXCHG_H
 #error Do not include xchg.h directly!
 #else
 /*
 * xchg/xchg_local and cmpxchg/cmpxchg_local share the same code
 * except that local version do not have the expensive memory barrier.
- * So this file is included twice from asm/system.h.
+ * So this file is included twice from asm/cmpxchg.h.
 */
 /*
diff --git a/arch/alpha/kernel/Makefile b/arch/alpha/kernel/Makefile
index 7a6d908bb865..84ec46b38f7d 100644
--- a/arch/alpha/kernel/Makefile
+++ b/arch/alpha/kernel/Makefile
@@ -6,7 +6,7 @@ extra-y		:= head.o vmlinux.lds
 asflags-y       := $(KBUILD_CFLAGS)
 ccflags-y       := -Wno-sign-compare
-obj-y    := entry.o traps.o process.o init_task.o osf_sys.o irq.o \
+obj-y    := entry.o traps.o process.o osf_sys.o irq.o \
            irq_alpha.o signal.o setup.o ptrace.o time.o \
            alpha_ksyms.o systbls.o err_common.o io.o
diff --git a/arch/alpha/kernel/core_tsunami.c b/arch/alpha/kernel/core_tsunami.c
index 5e7c28f92f19..61893d7bdda5 100644
--- a/arch/alpha/kernel/core_tsunami.c
+++ b/arch/alpha/kernel/core_tsunami.c
@@ -11,6 +11,7 @@
 #include <asm/core_tsunami.h>
 #undef __EXTERN_INLINE
+#include <linux/module.h>
 #include <linux/types.h>
 #include <linux/pci.h>
 #include <linux/sched.h>
diff --git a/arch/alpha/kernel/init_task.c b/arch/alpha/kernel/init_task.c
deleted file mode 100644
index 6f80ca4f9766..000000000000
--- a/arch/alpha/kernel/init_task.c
+++ /dev/null
@@ -1,17 +0,0 @@
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/sched.h>
-#include <linux/init.h>
-#include <linux/init_task.h>
-#include <linux/fs.h>
-#include <linux/mqueue.h>
-#include <asm/uaccess.h>
-static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
-static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
-struct task_struct init_task = INIT_TASK(init_task);
-EXPORT_SYMBOL(init_task);
-union thread_union init_thread_union __init_task_data =
-        { INIT_THREAD_INFO(init_task) };
diff --git a/arch/alpha/kernel/perf_event.c b/arch/alpha/kernel/perf_event.c
index 0dae252f7a33..d821b17047e0 100644
--- a/arch/alpha/kernel/perf_event.c
+++ b/arch/alpha/kernel/perf_event.c
@@ -824,7 +824,6 @@ static void alpha_perf_event_irq_handler(unsigned long la_ptr,
        idx = la_ptr;
-        perf_sample_data_init(&data, 0);
        for (j = 0; j < cpuc->n_events; j++) {
                if (cpuc->current_idx[j] == idx)
                        break;
@@ -848,7 +847,7 @@ static void alpha_perf_event_irq_handler(unsigned long la_ptr,
        hwc = &event->hw;
        alpha_perf_event_update(event, hwc, idx, alpha_pmu->pmc_max_period[idx]+1);
-        data.period = event->hw.last_period;
+        perf_sample_data_init(&data, 0, hwc->last_period);
        if (alpha_perf_event_set_period(event, hwc, idx)) {
                if (perf_event_overflow(event, &data, regs)) {
diff --git a/arch/alpha/kernel/smp.c b/arch/alpha/kernel/smp.c
index 50d438db1f6b..35ddc02bfa4a 100644
--- a/arch/alpha/kernel/smp.c
+++ b/arch/alpha/kernel/smp.c
@@ -357,24 +357,10 @@ secondary_cpu_start(int cpuid, struct task_struct *idle)
 * Bring one cpu online.
 */
 static int __cpuinit
-smp_boot_one_cpu(int cpuid)
+smp_boot_one_cpu(int cpuid, struct task_struct *idle)
 {
-        struct task_struct *idle;
        unsigned long timeout;
-        /* Cook up an idler for this guy.  Note that the address we
-           give to kernel_thread is irrelevant -- it's going to start
-           where HWRPB.CPU_restart says to start.  But this gets all
-           the other task-y sort of data structures set up like we
-           wish.  We can't use kernel_thread since we must avoid
-           rescheduling the child.  */
-        idle = fork_idle(cpuid);
-        if (IS_ERR(idle))
-                panic("failed fork for CPU %d", cpuid);
-        DBGS(("smp_boot_one_cpu: CPU %d state 0x%lx flags 0x%lx\n",
-              cpuid, idle->state, idle->flags));
        /* Signal the secondary to wait a moment.  */
        smp_secondary_alive = -1;
@@ -487,9 +473,9 @@ smp_prepare_boot_cpu(void)
 }
 int __cpuinit
-__cpu_up(unsigned int cpu)
+__cpu_up(unsigned int cpu, struct task_struct *tidle)
 {
-        smp_boot_one_cpu(cpu);
+        smp_boot_one_cpu(cpu, tidle);
        return cpu_online(cpu) ? 0 : -ENOSYS;
 }
diff --git a/arch/alpha/kernel/sys_marvel.c b/arch/alpha/kernel/sys_marvel.c
index 14a4b6a7cf59..407accc80877 100644
--- a/arch/alpha/kernel/sys_marvel.c
+++ b/arch/alpha/kernel/sys_marvel.c
@@ -317,7 +317,7 @@ marvel_init_irq(void)
 }
 static int 
-marvel_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+marvel_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 {
        struct pci_controller *hose = dev->sysdata;
        struct io7_port *io7_port = hose->sysdata;
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 73f90dd5554b..76edcfe8b56f 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -11,6 +11,7 @@ config ARM
        select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
        select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
        select HAVE_ARCH_KGDB
+        select HAVE_ARCH_TRACEHOOK
        select HAVE_KPROBES if !XIP_KERNEL
        select HAVE_KRETPROBES if (HAVE_KPROBES)
        select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
@@ -30,10 +31,15 @@ config ARM
        select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
        select HAVE_C_RECORDMCOUNT
        select HAVE_GENERIC_HARDIRQS
+        select HARDIRQS_SW_RESEND
+        select GENERIC_IRQ_PROBE
        select GENERIC_IRQ_SHOW
+        select GENERIC_IRQ_PROBE
+        select HARDIRQS_SW_RESEND
        select CPU_PM if (SUSPEND || CPU_IDLE)
        select GENERIC_PCI_IOMAP
-        select HAVE_BPF_JIT if NET
+        select HAVE_BPF_JIT
+        select GENERIC_SMP_IDLE_THREAD
        help
          The ARM series is a line of low-power-consumption RISC chip designs
          licensed by ARM Ltd and targeted at embedded applications and
@@ -126,14 +132,6 @@ config TRACE_IRQFLAGS_SUPPORT
        bool
        default y
-config HARDIRQS_SW_RESEND
-        bool
-        default y
-config GENERIC_IRQ_PROBE
-        bool
-        default y
 config GENERIC_LOCKBREAK
        bool
        default y
@@ -159,9 +157,6 @@ config ARCH_HAS_CPUFREQ
          and that the relevant menu configurations are displayed for
          it.
-config ARCH_HAS_CPU_IDLE_WAIT
-       def_bool y
 config GENERIC_HWEIGHT
        bool
        default y
@@ -280,6 +275,7 @@ config ARCH_INTEGRATOR
        select NEED_MACH_IO_H
        select NEED_MACH_MEMORY_H
        select SPARSE_IRQ
+        select MULTI_IRQ_HANDLER
        help
          Support for ARM's Integrator platform.
@@ -340,8 +336,8 @@ config ARCH_AT91
        select IRQ_DOMAIN
        select NEED_MACH_IO_H if PCCARD
        help
-          This enables support for systems based on the Atmel AT91RM9200,
+          This enables support for systems based on Atmel
-          AT91SAM9 processors.
+          AT91RM9200 and AT91SAM9* processors.
 config ARCH_BCMRING
        bool "Broadcom BCMRING"
@@ -373,12 +369,12 @@ config ARCH_HIGHBANK
          Support for the Calxeda Highbank SoC based boards.
 config ARCH_CLPS711X
-        bool "Cirrus Logic CLPS711x/EP721x-based"
+        bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
        select CPU_ARM720T
        select ARCH_USES_GETTIMEOFFSET
        select NEED_MACH_MEMORY_H
        help
-          Support for Cirrus Logic 711x/721x based boards.
+          Support for Cirrus Logic 711x/721x/731x based boards.
 config ARCH_CNS3XXX
        bool "Cavium Networks CNS3XXX family"
@@ -407,6 +403,8 @@ config ARCH_PRIMA2
        select CLKDEV_LOOKUP
        select GENERIC_IRQ_CHIP
        select MIGHT_HAVE_CACHE_L2X0
+        select PINCTRL
+        select PINCTRL_SIRF
        select USE_OF
        select ZONE_DMA
        help
@@ -469,6 +467,7 @@ config ARCH_MXS
        select CLKDEV_LOOKUP
        select CLKSRC_MMIO
        select HAVE_CLK_PREPARE
+        select PINCTRL
        help
          Support for Freescale MXS-based family of processors
@@ -528,28 +527,6 @@ config ARCH_IOP33X
        help
          Support for Intel's IOP33X (XScale) family of processors.
-config ARCH_IXP23XX
-        bool "IXP23XX-based"
-        depends on MMU
-        select CPU_XSC3
-        select PCI
-        select ARCH_USES_GETTIMEOFFSET
-        select NEED_MACH_IO_H
-        select NEED_MACH_MEMORY_H
-        help
-          Support for Intel's IXP23xx (XScale) family of processors.
-config ARCH_IXP2000
-        bool "IXP2400/2800-based"
-        depends on MMU
-        select CPU_XSCALE
-        select PCI
-        select ARCH_USES_GETTIMEOFFSET
-        select NEED_MACH_IO_H
-        select NEED_MACH_MEMORY_H
-        help
-          Support for Intel's IXP2400/2800 (XScale) family of processors.
 config ARCH_IXP4XX
        bool "IXP4xx-based"
        depends on MMU
@@ -597,6 +574,7 @@ config ARCH_LPC32XX
        select USB_ARCH_HAS_OHCI
        select CLKDEV_LOOKUP
        select GENERIC_CLOCKEVENTS
+        select USE_OF
        help
          Support for the NXP LPC32XX family of processors
@@ -632,7 +610,7 @@ config ARCH_MMP
        select CLKDEV_LOOKUP
        select GENERIC_CLOCKEVENTS
        select GPIO_PXA
-        select TICK_ONESHOT
+        select IRQ_DOMAIN
        select PLAT_PXA
        select SPARSE_IRQ
        select GENERIC_ALLOCATOR
@@ -716,7 +694,6 @@ config ARCH_PXA
        select ARCH_REQUIRE_GPIOLIB
        select GENERIC_CLOCKEVENTS
        select GPIO_PXA
-        select TICK_ONESHOT
        select PLAT_PXA
        select SPARSE_IRQ
        select AUTO_ZRELADDR
@@ -783,7 +760,6 @@ config ARCH_SA1100
        select CPU_FREQ
        select GENERIC_CLOCKEVENTS
        select CLKDEV_LOOKUP
-        select TICK_ONESHOT
        select ARCH_REQUIRE_GPIOLIB
        select HAVE_IDE
        select NEED_MACH_MEMORY_H
@@ -946,6 +922,7 @@ config ARCH_NOMADIK
        select CPU_ARM926T
        select CLKDEV_LOOKUP
        select GENERIC_CLOCKEVENTS
+        select PINCTRL
        select MIGHT_HAVE_CACHE_L2X0
        select ARCH_REQUIRE_GPIOLIB
        help
@@ -1046,10 +1023,6 @@ source "arch/arm/mach-iop13xx/Kconfig"
 source "arch/arm/mach-ixp4xx/Kconfig"
-source "arch/arm/mach-ixp2000/Kconfig"
-source "arch/arm/mach-ixp23xx/Kconfig"
 source "arch/arm/mach-kirkwood/Kconfig"
 source "arch/arm/mach-ks8695/Kconfig"
@@ -1186,6 +1159,15 @@ if !MMU
 source "arch/arm/Kconfig-nommu"
 endif
+config ARM_ERRATA_326103
+        bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
+        depends on CPU_V6
+        help
+          Executing a SWP instruction to read-only memory does not set bit 11
+          of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
+          treat the access as a read, preventing a COW from occurring and
+          causing the faulting task to livelock.
 config ARM_ERRATA_411920
        bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
        depends on CPU_V6 || CPU_V6K
@@ -1543,10 +1525,15 @@ config HAVE_ARM_SCU
        help
          This option enables support for the ARM system coherency unit
+config ARM_ARCH_TIMER
+        bool "Architected timer support"
+        depends on CPU_V7
+        help
+          This option enables support for the ARM architected timer
 config HAVE_ARM_TWD
        bool
        depends on SMP
-        select TICK_ONESHOT
        help
          This options enables support for the ARM timer and watchdog unit
@@ -2272,9 +2259,9 @@ menu "Power management options"
 source "kernel/power/Kconfig"
 config ARCH_SUSPEND_POSSIBLE
-        depends on !ARCH_S5PC100
+        depends on !ARCH_S5PC100 && !ARCH_TEGRA
        depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
-                CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
+                CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
        def_bool y
 config ARM_CPU_SUSPEND
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 047a20780fc1..157900da8782 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -70,8 +70,6 @@ arch-$(CONFIG_CPU_32v4)		:=-D__LINUX_ARM_ARCH__=4 -march=armv4
 arch-$(CONFIG_CPU_32v3)         :=-D__LINUX_ARM_ARCH__=3 -march=armv3
 # This selects how we optimise for the processor.
-tune-$(CONFIG_CPU_ARM610)       :=-mtune=arm610
-tune-$(CONFIG_CPU_ARM710)       :=-mtune=arm710
 tune-$(CONFIG_CPU_ARM7TDMI)     :=-mtune=arm7tdmi
 tune-$(CONFIG_CPU_ARM720T)      :=-mtune=arm7tdmi
 tune-$(CONFIG_CPU_ARM740T)      :=-mtune=arm7tdmi
@@ -119,7 +117,7 @@ KBUILD_AFLAGS	+=$(CFLAGS_ABI) $(AFLAGS_THUMB2) $(arch-y) $(tune-y) -include asm/
 CHECKFLAGS      += -D__arm__
 #Default value
-head-y          := arch/arm/kernel/head$(MMUEXT).o arch/arm/kernel/init_task.o
+head-y          := arch/arm/kernel/head$(MMUEXT).o
 textofs-y       := 0x00008000
 textofs-$(CONFIG_ARCH_CLPS711X) := 0x00028000
 # We don't want the htc bootloader to corrupt kernel during resume
@@ -149,8 +147,6 @@ machine-$(CONFIG_ARCH_INTEGRATOR)	:= integrator
 machine-$(CONFIG_ARCH_IOP13XX)          := iop13xx
 machine-$(CONFIG_ARCH_IOP32X)           := iop32x
 machine-$(CONFIG_ARCH_IOP33X)           := iop33x
-machine-$(CONFIG_ARCH_IXP2000)          := ixp2000
-machine-$(CONFIG_ARCH_IXP23XX)          := ixp23xx
 machine-$(CONFIG_ARCH_IXP4XX)           := ixp4xx
 machine-$(CONFIG_ARCH_KIRKWOOD)         := kirkwood
 machine-$(CONFIG_ARCH_KS8695)           := ks8695
diff --git a/arch/arm/boot/compressed/atags_to_fdt.c b/arch/arm/boot/compressed/atags_to_fdt.c
index 6ce11c481178..797f04bedb47 100644
--- a/arch/arm/boot/compressed/atags_to_fdt.c
+++ b/arch/arm/boot/compressed/atags_to_fdt.c
@@ -77,6 +77,8 @@ int atags_to_fdt(void *atag_list, void *fdt, int total_space)
                } else if (atag->hdr.tag == ATAG_MEM) {
                        if (memcount >= sizeof(mem_reg_property)/4)
                                continue;
+                        if (!atag->u.mem.size)
+                                continue;
                        mem_reg_property[memcount++] = cpu_to_fdt32(atag->u.mem.start);
                        mem_reg_property[memcount++] = cpu_to_fdt32(atag->u.mem.size);
                } else if (atag->hdr.tag == ATAG_INITRD2) {
diff --git a/arch/arm/boot/compressed/head-xscale.S b/arch/arm/boot/compressed/head-xscale.S
index aa5ee49c5c5a..6ab0599c02dd 100644
--- a/arch/arm/boot/compressed/head-xscale.S
+++ b/arch/arm/boot/compressed/head-xscale.S
@@ -32,10 +32,3 @@ __XScale_start:
                bic     r0, r0, #0x1000         @ clear Icache
                mcr     p15, 0, r0, c1, c0, 0
-#ifdef CONFIG_ARCH_IXP2000
-                mov     r1, #-1
-                mov     r0, #0xd6000000
-                str     r1, [r0, #0x14]
-                str     r1, [r0, #0x18]
-#endif
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 5f6045f1766c..b8c64b80bafc 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -273,7 +273,7 @@ restart:	adr	r0, LC0
                add     r0, r0, #0x100
                mov     r1, r6
                sub     r2, sp, r6
-                blne    atags_to_fdt
+                bleq    atags_to_fdt
                ldmfd   sp!, {r0-r3, ip, lr}
                sub     sp, sp, #0x10000
@@ -567,6 +567,12 @@ __armv3_mpu_cache_on:
                mcr     p15, 0, r0, c7, c0, 0   @ invalidate whole cache v3
                mov     pc, lr
+#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
+#define CB_BITS 0x08
+#else
+#define CB_BITS 0x0c
+#endif
 __setup_mmu:    sub     r3, r4, #16384          @ Page directory size
                bic     r3, r3, #0xff           @ Align the pointer
                bic     r3, r3, #0x3f00
@@ -578,17 +584,14 @@ __setup_mmu:	sub	r3, r4, #16384		@ Page directory size
                mov     r9, r0, lsr #18
                mov     r9, r9, lsl #18         @ start of RAM
                add     r10, r9, #0x10000000    @ a reasonable RAM size
-                mov     r1, #0x12
+                mov     r1, #0x12               @ XN|U + section mapping
-                orr     r1, r1, #3 << 10
+                orr     r1, r1, #3 << 10        @ AP=11
                add     r2, r3, #16384
 1:              cmp     r1, r9                  @ if virt > start of RAM
-#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
+                cmphs   r10, r1                 @   && end of RAM > virt
-                orrhs   r1, r1, #0x08           @ set cacheable
+                bic     r1, r1, #0x1c           @ clear XN|U + C + B
-#else
+                orrlo   r1, r1, #0x10           @ Set XN|U for non-RAM
-                orrhs   r1, r1, #0x0c           @ set cacheable, bufferable
+                orrhs   r1, r1, r6              @ set RAM section settings
-#endif
-                cmp     r1, r10                 @ if virt > end of RAM
-                bichs   r1, r1, #0x0c           @ clear cacheable, bufferable
                str     r1, [r0], #4            @ 1:1 mapping
                add     r1, r1, #1048576
                teq     r0, r2
@@ -599,7 +602,7 @@ __setup_mmu:	sub	r3, r4, #16384		@ Page directory size
 * so there is no map overlap problem for up to 1 MB compressed kernel.
 * If the execution is in RAM then we would only be duplicating the above.
 */
-                mov     r1, #0x1e
+                orr     r1, r6, #0x04           @ ensure B is set for this
                orr     r1, r1, #3 << 10
                mov     r2, pc
                mov     r2, r2, lsr #20
@@ -620,6 +623,7 @@ __arm926ejs_mmu_cache_on:
 __armv4_mmu_cache_on:
                mov     r12, lr
 #ifdef CONFIG_MMU
+                mov     r6, #CB_BITS | 0x12     @ U
                bl      __setup_mmu
                mov     r0, #0
                mcr     p15, 0, r0, c7, c10, 4  @ drain write buffer
@@ -641,6 +645,7 @@ __armv7_mmu_cache_on:
 #ifdef CONFIG_MMU
                mrc     p15, 0, r11, c0, c1, 4  @ read ID_MMFR0
                tst     r11, #0xf               @ VMSA
+                movne   r6, #CB_BITS | 0x02     @ !XN
                blne    __setup_mmu
                mov     r0, #0
                mcr     p15, 0, r0, c7, c10, 4  @ drain write buffer
@@ -655,7 +660,7 @@ __armv7_mmu_cache_on:
                orr     r0, r0, #1 << 25        @ big-endian page tables
 #endif
                orrne   r0, r0, #1              @ MMU enabled
-                movne   r1, #-1
+                movne   r1, #0xfffffffd         @ domain 0 = client
                mcrne   p15, 0, r3, c2, c0, 0   @ load page table pointer
                mcrne   p15, 0, r1, c3, c0, 0   @ load domain access control
 #endif
@@ -668,6 +673,7 @@ __armv7_mmu_cache_on:
 __fa526_cache_on:
                mov     r12, lr
+                mov     r6, #CB_BITS | 0x12     @ U
                bl      __setup_mmu
                mov     r0, #0
                mcr     p15, 0, r0, c7, c7, 0   @ Invalidate whole cache
@@ -680,18 +686,6 @@ __fa526_cache_on:
                mcr     p15, 0, r0, c8, c7, 0   @ flush UTLB
                mov     pc, r12
-__arm6_mmu_cache_on:
-                mov     r12, lr
-                bl      __setup_mmu
-                mov     r0, #0
-                mcr     p15, 0, r0, c7, c0, 0   @ invalidate whole cache v3
-                mcr     p15, 0, r0, c5, c0, 0   @ invalidate whole TLB v3
-                mov     r0, #0x30
-                bl      __common_mmu_cache_on
-                mov     r0, #0
-                mcr     p15, 0, r0, c5, c0, 0   @ invalidate whole TLB v3
-                mov     pc, r12
 __common_mmu_cache_on:
 #ifndef CONFIG_THUMB2_KERNEL
 #ifndef DEBUG
@@ -756,16 +750,6 @@ call_cache_fn:	adr	r12, proc_types
                .align  2
                .type   proc_types,#object
 proc_types:
-                .word   0x41560600              @ ARM6/610
-                .word   0xffffffe0
-                W(b)    __arm6_mmu_cache_off    @ works, but slow
-                W(b)    __arm6_mmu_cache_off
-                mov     pc, lr
- THUMB(         nop                             )
-@               b       __arm6_mmu_cache_on             @ untested
-@               b       __arm6_mmu_cache_off
-@               b       __armv3_mmu_cache_flush
                .word   0x00000000              @ old ARM ID
                .word   0x0000f000
                mov     pc, lr
@@ -777,8 +761,10 @@ proc_types:
                .word   0x41007000              @ ARM7/710
                .word   0xfff8fe00
-                W(b)    __arm7_mmu_cache_off
+                mov     pc, lr
-                W(b)    __arm7_mmu_cache_off
+ THUMB(         nop                             )
+                mov     pc, lr
+ THUMB(         nop                             )
                mov     pc, lr
 THUMB(         nop                             )
@@ -977,21 +963,6 @@ __armv7_mmu_cache_off:
                mcr     p15, 0, r0, c7, c5, 4   @ ISB
                mov     pc, r12
-__arm6_mmu_cache_off:
-                mov     r0, #0x00000030         @ ARM6 control reg.
-                b       __armv3_mmu_cache_off
-__arm7_mmu_cache_off:
-                mov     r0, #0x00000070         @ ARM7 control reg.
-                b       __armv3_mmu_cache_off
-__armv3_mmu_cache_off:
-                mcr     p15, 0, r0, c1, c0, 0   @ turn MMU and cache off
-                mov     r0, #0
-                mcr     p15, 0, r0, c7, c0, 0   @ invalidate whole cache v3
-                mcr     p15, 0, r0, c5, c0, 0   @ invalidate whole TLB v3
-                mov     pc, lr
 /*
 * Clean and flush the cache to maintain consistency.
 *
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
new file mode 100644
index 000000000000..f449efc9825f
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -0,0 +1,273 @@
+/*
+ * at91sam9260.dtsi - Device Tree Include file for AT91SAM9260 family SoC
+ *
+ *  Copyright (C) 2011 Atmel,
+ *                2011 Nicolas Ferre <nicolas.ferre@atmel.com>,
+ *                2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+/include/ "skeleton.dtsi"
+/ {
+        model = "Atmel AT91SAM9260 family SoC";
+        compatible = "atmel,at91sam9260";
+        interrupt-parent = <&aic>;
+        aliases {
+                serial0 = &dbgu;
+                serial1 = &usart0;
+                serial2 = &usart1;
+                serial3 = &usart2;
+                serial4 = &usart3;
+                serial5 = &usart4;
+                serial6 = &usart5;
+                gpio0 = &pioA;
+                gpio1 = &pioB;
+                gpio2 = &pioC;
+                tcb0 = &tcb0;
+                tcb1 = &tcb1;
+        };
+        cpus {
+                cpu@0 {
+                        compatible = "arm,arm926ejs";
+                };
+        };
+        memory {
+                reg = <0x20000000 0x04000000>;
+        };
+        ahb {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                apb {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+                        aic: interrupt-controller@fffff000 {
+                                #interrupt-cells = <2>;
+                                compatible = "atmel,at91rm9200-aic";
+                                interrupt-controller;
+                                reg = <0xfffff000 0x200>;
+                        };
+                        ramc0: ramc@ffffea00 {
+                                compatible = "atmel,at91sam9260-sdramc";
+                                reg = <0xffffea00 0x200>;
+                        };
+                        pmc: pmc@fffffc00 {
+                                compatible = "atmel,at91rm9200-pmc";
+                                reg = <0xfffffc00 0x100>;
+                        };
+                        rstc@fffffd00 {
+                                compatible = "atmel,at91sam9260-rstc";
+                                reg = <0xfffffd00 0x10>;
+                        };
+                        shdwc@fffffd10 {
+                                compatible = "atmel,at91sam9260-shdwc";
+                                reg = <0xfffffd10 0x10>;
+                        };
+                        pit: timer@fffffd30 {
+                                compatible = "atmel,at91sam9260-pit";
+                                reg = <0xfffffd30 0xf>;
+                                interrupts = <1 4>;
+                        };
+                        tcb0: timer@fffa0000 {
+                                compatible = "atmel,at91rm9200-tcb";
+                                reg = <0xfffa0000 0x100>;
+                                interrupts = <17 4 18 4 19 4>;
+                        };
+                        tcb1: timer@fffdc000 {
+                                compatible = "atmel,at91rm9200-tcb";
+                                reg = <0xfffdc000 0x100>;
+                                interrupts = <26 4 27 4 28 4>;
+                        };
+                        pioA: gpio@fffff400 {
+                                compatible = "atmel,at91rm9200-gpio";
+                                reg = <0xfffff400 0x100>;
+                                interrupts = <2 4>;
+                                #gpio-cells = <2>;
+                                gpio-controller;
+                                interrupt-controller;
+                        };
+                        pioB: gpio@fffff600 {
+                                compatible = "atmel,at91rm9200-gpio";
+                                reg = <0xfffff600 0x100>;
+                                interrupts = <3 4>;
+                                #gpio-cells = <2>;
+                                gpio-controller;
+                                interrupt-controller;
+                        };
+                        pioC: gpio@fffff800 {
+                                compatible = "atmel,at91rm9200-gpio";
+                                reg = <0xfffff800 0x100>;
+                                interrupts = <4 4>;
+                                #gpio-cells = <2>;
+                                gpio-controller;
+                                interrupt-controller;
+                        };
+                        dbgu: serial@fffff200 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xfffff200 0x200>;
+                                interrupts = <1 4>;
+                                status = "disabled";
+                        };
+                        usart0: serial@fffb0000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xfffb0000 0x200>;
+                                interrupts = <6 4>;
+                                atmel,use-dma-rx;
+                                atmel,use-dma-tx;
+                                status = "disabled";
+                        };
+                        usart1: serial@fffb4000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xfffb4000 0x200>;
+                                interrupts = <7 4>;
+                                atmel,use-dma-rx;
+                                atmel,use-dma-tx;
+                                status = "disabled";
+                        };
+                        usart2: serial@fffb8000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xfffb8000 0x200>;
+                                interrupts = <8 4>;
+                                atmel,use-dma-rx;
+                                atmel,use-dma-tx;
+                                status = "disabled";
+                        };
+                        usart3: serial@fffd0000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xfffd0000 0x200>;
+                                interrupts = <23 4>;
+                                atmel,use-dma-rx;
+                                atmel,use-dma-tx;
+                                status = "disabled";
+                        };
+                        usart4: serial@fffd4000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xfffd4000 0x200>;
+                                interrupts = <24 4>;
+                                atmel,use-dma-rx;
+                                atmel,use-dma-tx;
+                                status = "disabled";
+                        };
+                        usart5: serial@fffd8000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xfffd8000 0x200>;
+                                interrupts = <25 4>;
+                                atmel,use-dma-rx;
+                                atmel,use-dma-tx;
+                                status = "disabled";
+                        };
+                        macb0: ethernet@fffc4000 {
+                                compatible = "cdns,at32ap7000-macb", "cdns,macb";
+                                reg = <0xfffc4000 0x100>;
+                                interrupts = <21 4>;
+                                status = "disabled";
+                        };
+                        usb1: gadget@fffa4000 {
+                                compatible = "atmel,at91rm9200-udc";
+                                reg = <0xfffa4000 0x4000>;
+                                interrupts = <10 4>;
+                                status = "disabled";
+                        };
+                        adc0: adc@fffe0000 {
+                                compatible = "atmel,at91sam9260-adc";
+                                reg = <0xfffe0000 0x100>;
+                                interrupts = <5 4>;
+                                atmel,adc-use-external-triggers;
+                                atmel,adc-channels-used = <0xf>;
+                                atmel,adc-vref = <3300>;
+                                atmel,adc-num-channels = <4>;
+                                atmel,adc-startup-time = <15>;
+                                atmel,adc-channel-base = <0x30>;
+                                atmel,adc-drdy-mask = <0x10000>;
+                                atmel,adc-status-register = <0x1c>;
+                                atmel,adc-trigger-register = <0x04>;
+                                trigger@0 {
+                                        trigger-name = "timer-counter-0";
+                                        trigger-value = <0x1>;
+                                };
+                                trigger@1 {
+                                        trigger-name = "timer-counter-1";
+                                        trigger-value = <0x3>;
+                                };
+                                trigger@2 {
+                                        trigger-name = "timer-counter-2";
+                                        trigger-value = <0x5>;
+                                };
+                                trigger@3 {
+                                        trigger-name = "external";
+                                        trigger-value = <0x13>;
+                                        trigger-external;
+                                };
+                        };
+                };
+                nand0: nand@40000000 {
+                        compatible = "atmel,at91rm9200-nand";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x40000000 0x10000000
+                               0xffffe800 0x200
+                              >;
+                        atmel,nand-addr-offset = <21>;
+                        atmel,nand-cmd-offset = <22>;
+                        gpios = <&pioC 13 0
+                                 &pioC 14 0
+                                 0
+                                >;
+                        status = "disabled";
+                };
+                usb0: ohci@00500000 {
+                        compatible = "atmel,at91rm9200-ohci", "usb-ohci";
+                        reg = <0x00500000 0x100000>;
+                        interrupts = <20 4>;
+                        status = "disabled";
+                };
+        };
+        i2c@0 {
+                compatible = "i2c-gpio";
+                gpios = <&pioA 23 0 /* sda */
+                         &pioA 24 0 /* scl */
+                        >;
+                i2c-gpio,sda-open-drain;
+                i2c-gpio,scl-open-drain;
+                i2c-gpio,delay-us = <2>;        /* ~100 kHz */
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
+};
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
new file mode 100644
index 000000000000..0209913a65a2
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -0,0 +1,220 @@
+/*
+ * at91sam9263.dtsi - Device Tree Include file for AT91SAM9263 family SoC
+ *
+ *  Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Licensed under GPLv2 only.
+ */
+/include/ "skeleton.dtsi"
+/ {
+        model = "Atmel AT91SAM9263 family SoC";
+        compatible = "atmel,at91sam9263";
+        interrupt-parent = <&aic>;
+        aliases {
+                serial0 = &dbgu;
+                serial1 = &usart0;
+                serial2 = &usart1;
+                serial3 = &usart2;
+                gpio0 = &pioA;
+                gpio1 = &pioB;
+                gpio2 = &pioC;
+                gpio3 = &pioD;
+                gpio4 = &pioE;
+                tcb0 = &tcb0;
+        };
+        cpus {
+                cpu@0 {
+                        compatible = "arm,arm926ejs";
+                };
+        };
+        memory {
+                reg = <0x20000000 0x08000000>;
+        };
+        ahb {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                apb {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+                        aic: interrupt-controller@fffff000 {
+                                #interrupt-cells = <2>;
+                                compatible = "atmel,at91rm9200-aic";
+                                interrupt-controller;
+                                reg = <0xfffff000 0x200>;
+                        };
+                        pmc: pmc@fffffc00 {
+                                compatible = "atmel,at91rm9200-pmc";
+                                reg = <0xfffffc00 0x100>;
+                        };
+                        ramc: ramc@ffffe200 {
+                                compatible = "atmel,at91sam9260-sdramc";
+                                reg = <0xffffe200 0x200
+                                       0xffffe800 0x200>;
+                        };
+                        pit: timer@fffffd30 {
+                                compatible = "atmel,at91sam9260-pit";
+                                reg = <0xfffffd30 0xf>;
+                                interrupts = <1 4>;
+                        };
+                        tcb0: timer@fff7c000 {
+                                compatible = "atmel,at91rm9200-tcb";
+                                reg = <0xfff7c000 0x100>;
+                                interrupts = <19 4>;
+                        };
+                        rstc@fffffd00 {
+                                compatible = "atmel,at91sam9260-rstc";
+                                reg = <0xfffffd00 0x10>;
+                        };
+                        shdwc@fffffd10 {
+                                compatible = "atmel,at91sam9260-shdwc";
+                                reg = <0xfffffd10 0x10>;
+                        };
+                        pioA: gpio@fffff200 {
+                                compatible = "atmel,at91rm9200-gpio";
+                                reg = <0xfffff200 0x100>;
+                                interrupts = <2 4>;
+                                #gpio-cells = <2>;
+                                gpio-controller;
+                                interrupt-controller;
+                        };
+                        pioB: gpio@fffff400 {
+                                compatible = "atmel,at91rm9200-gpio";
+                                reg = <0xfffff400 0x100>;
+                                interrupts = <3 4>;
+                                #gpio-cells = <2>;
+                                gpio-controller;
+                                interrupt-controller;
+                        };
+                        pioC: gpio@fffff600 {
+                                compatible = "atmel,at91rm9200-gpio";
+                                reg = <0xfffff600 0x100>;
+                                interrupts = <4 4>;
+                                #gpio-cells = <2>;
+                                gpio-controller;
+                                interrupt-controller;
+                        };
+                        pioD: gpio@fffff800 {
+                                compatible = "atmel,at91rm9200-gpio";
+                                reg = <0xfffff800 0x100>;
+                                interrupts = <4 4>;
+                                #gpio-cells = <2>;
+                                gpio-controller;
+                                interrupt-controller;
+                        };
+                        pioE: gpio@fffffa00 {
+                                compatible = "atmel,at91rm9200-gpio";
+                                reg = <0xfffffa00 0x100>;
+                                interrupts = <4 4>;
+                                #gpio-cells = <2>;
+                                gpio-controller;
+                                interrupt-controller;
+                        };
+                        dbgu: serial@ffffee00 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xffffee00 0x200>;
+                                interrupts = <1 4>;
+                                status = "disabled";
+                        };
+                        usart0: serial@fff8c000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xfff8c000 0x200>;
+                                interrupts = <7 4>;
+                                atmel,use-dma-rx;
+                                atmel,use-dma-tx;
+                                status = "disabled";
+                        };
+                        usart1: serial@fff90000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xfff90000 0x200>;
+                                interrupts = <8 4>;
+                                atmel,use-dma-rx;
+                                atmel,use-dma-tx;
+                                status = "disabled";
+                        };
+                        usart2: serial@fff94000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xfff94000 0x200>;
+                                interrupts = <9 4>;
+                                atmel,use-dma-rx;
+                                atmel,use-dma-tx;
+                                status = "disabled";
+                        };
+                        macb0: ethernet@fffbc000 {
+                                compatible = "cdns,at32ap7000-macb", "cdns,macb";
+                                reg = <0xfffbc000 0x100>;
+                                interrupts = <21 4>;
+                                status = "disabled";
+                        };
+                        usb1: gadget@fff78000 {
+                                compatible = "atmel,at91rm9200-udc";
+                                reg = <0xfff78000 0x4000>;
+                                interrupts = <24 4>;
+                                status = "disabled";
+                        };
+                };
+                nand0: nand@40000000 {
+                        compatible = "atmel,at91rm9200-nand";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x40000000 0x10000000
+                               0xffffe000 0x200
+                              >;
+                        atmel,nand-addr-offset = <21>;
+                        atmel,nand-cmd-offset = <22>;
+                        gpios = <&pioA 22 0
+                                 &pioD 15 0
+                                 0
+                                >;
+                        status = "disabled";
+                };
+                usb0: ohci@00a00000 {
+                        compatible = "atmel,at91rm9200-ohci", "usb-ohci";
+                        reg = <0x00a00000 0x100000>;
+                        interrupts = <29 4>;
+                        status = "disabled";
+                };
+        };
+        i2c@0 {
+                compatible = "i2c-gpio";
+                gpios = <&pioB 4 0 /* sda */
+                         &pioB 5 0 /* scl */
+                        >;
+                i2c-gpio,sda-open-drain;
+                i2c-gpio,scl-open-drain;
+                i2c-gpio,delay-us = <2>;        /* ~100 kHz */
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
+};
diff --git a/arch/arm/boot/dts/at91sam9263ek.dts b/arch/arm/boot/dts/at91sam9263ek.dts
new file mode 100644
index 000000000000..f86ac4b609fc
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9263ek.dts
@@ -0,0 +1,156 @@
+/*
+ * at91sam9263ek.dts - Device Tree file for Atmel at91sam9263 reference board
+ *
+ *  Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Licensed under GPLv2 only
+ */
+/dts-v1/;
+/include/ "at91sam9263.dtsi"
+/ {
+        model = "Atmel at91sam9263ek";
+        compatible = "atmel,at91sam9263ek", "atmel,at91sam9263", "atmel,at91sam9";
+        chosen {
+                bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs";
+        };
+        memory {
+                reg = <0x20000000 0x4000000>;
+        };
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                main_clock: clock@0 {
+                        compatible = "atmel,osc", "fixed-clock";
+                        clock-frequency = <16367660>;
+                };
+        };
+        ahb {
+                apb {
+                        dbgu: serial@ffffee00 {
+                                status = "okay";
+                        };
+                        usart0: serial@fff8c000 {
+                                status = "okay";
+                        };
+                        macb0: ethernet@fffbc000 {
+                                phy-mode = "rmii";
+                                status = "okay";
+                        };
+                        usb1: gadget@fff78000 {
+                                atmel,vbus-gpio = <&pioA 25 0>;
+                                status = "okay";
+                        };
+                };
+                nand0: nand@40000000 {
+                        nand-bus-width = <8>;
+                        nand-ecc-mode = "soft";
+                        nand-on-flash-bbt = <1>;
+                        status = "okay";
+                        at91bootstrap@0 {
+                                label = "at91bootstrap";
+                                reg = <0x0 0x20000>;
+                        };
+                        barebox@20000 {
+                                label = "barebox";
+                                reg = <0x20000 0x40000>;
+                        };
+                        bareboxenv@60000 {
+                                label = "bareboxenv";
+                                reg = <0x60000 0x20000>;
+                        };
+                        bareboxenv2@80000 {
+                                label = "bareboxenv2";
+                                reg = <0x80000 0x20000>;
+                        };
+                        oftree@80000 {
+                                label = "oftree";
+                                reg = <0xa0000 0x20000>;
+                        };
+                        kernel@a0000 {
+                                label = "kernel";
+                                reg = <0xc0000 0x400000>;
+                        };
+                        rootfs@4a0000 {
+                                label = "rootfs";
+                                reg = <0x4c0000 0x7800000>;
+                        };
+                        data@7ca0000 {
+                                label = "data";
+                                reg = <0x7cc0000 0x8340000>;
+                        };
+                };
+                usb0: ohci@00a00000 {
+                        num-ports = <2>;
+                        status = "okay";
+                        atmel,vbus-gpio = <&pioA 24 0
+                                           &pioA 21 0
+                                          >;
+                };
+        };
+        leds {
+                compatible = "gpio-leds";
+                d3 {
+                        label = "d3";
+                        gpios = <&pioB 7 0>;
+                        linux,default-trigger = "heartbeat";
+                };
+                d2 {
+                        label = "d2";
+                        gpios = <&pioC 29 1>;
+                        linux,default-trigger = "nand-disk";
+                };
+        };
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                left_click {
+                        label = "left_click";
+                        gpios = <&pioC 5 1>;
+                        linux,code = <272>;
+                        gpio-key,wakeup;
+                };
+                right_click {
+                        label = "right_click";
+                        gpios = <&pioC 4 1>;
+                        linux,code = <273>;
+                        gpio-key,wakeup;
+                };
+        };
+        i2c@0 {
+                status = "okay";
+                24c512@50 {
+                        compatible = "24c512";
+                        reg = <0x50>;
+                        pagesize = <128>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi
index 799ad1889b51..2a1d1ca8bd86 100644
--- a/arch/arm/boot/dts/at91sam9g20.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20.dtsi
@@ -1,239 +1,26 @@
 /*
 * at91sam9g20.dtsi - Device Tree Include file for AT91SAM9G20 family SoC
 *
- *  Copyright (C) 2011 Atmel,
+ *  Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
- *                2011 Nicolas Ferre <nicolas.ferre@atmel.com>,
- *                2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
 *
- * Licensed under GPLv2 or later.
+ * Licensed under GPLv2.
 */
-/include/ "skeleton.dtsi"
+/include/ "at91sam9260.dtsi"
 / {
        model = "Atmel AT91SAM9G20 family SoC";
        compatible = "atmel,at91sam9g20";
-        interrupt-parent = <&aic>;
-        aliases {
-                serial0 = &dbgu;
-                serial1 = &usart0;
-                serial2 = &usart1;
-                serial3 = &usart2;
-                serial4 = &usart3;
-                serial5 = &usart4;
-                serial6 = &usart5;
-                gpio0 = &pioA;
-                gpio1 = &pioB;
-                gpio2 = &pioC;
-                tcb0 = &tcb0;
-                tcb1 = &tcb1;
-        };
-        cpus {
-                cpu@0 {
-                        compatible = "arm,arm926ejs";
-                };
-        };
        memory {
                reg = <0x20000000 0x08000000>;
        };
        ahb {
-                compatible = "simple-bus";
-                #address-cells = <1>;
-                #size-cells = <1>;
-                ranges;
                apb {
-                        compatible = "simple-bus";
+                        adc0: adc@fffe0000 {
-                        #address-cells = <1>;
+                                atmel,adc-startup-time = <40>;
-                        #size-cells = <1>;
-                        ranges;
-                        aic: interrupt-controller@fffff000 {
-                                #interrupt-cells = <2>;
-                                compatible = "atmel,at91rm9200-aic";
-                                interrupt-controller;
-                                interrupt-parent;
-                                reg = <0xfffff000 0x200>;
-                        };
-                        ramc0: ramc@ffffea00 {
-                                compatible = "atmel,at91sam9260-sdramc";
-                                reg = <0xffffea00 0x200>;
-                        };
-                        pmc: pmc@fffffc00 {
-                                compatible = "atmel,at91rm9200-pmc";
-                                reg = <0xfffffc00 0x100>;
-                        };
-                        rstc@fffffd00 {
-                                compatible = "atmel,at91sam9260-rstc";
-                                reg = <0xfffffd00 0x10>;
-                        };
-                        shdwc@fffffd10 {
-                                compatible = "atmel,at91sam9260-shdwc";
-                                reg = <0xfffffd10 0x10>;
-                        };
-                        pit: timer@fffffd30 {
-                                compatible = "atmel,at91sam9260-pit";
-                                reg = <0xfffffd30 0xf>;
-                                interrupts = <1 4>;
-                        };
-                        tcb0: timer@fffa0000 {
-                                compatible = "atmel,at91rm9200-tcb";
-                                reg = <0xfffa0000 0x100>;
-                                interrupts = <17 4 18 4 19 4>;
-                        };
-                        tcb1: timer@fffdc000 {
-                                compatible = "atmel,at91rm9200-tcb";
-                                reg = <0xfffdc000 0x100>;
-                                interrupts = <26 4 27 4 28 4>;
-                        };
-                        pioA: gpio@fffff400 {
-                                compatible = "atmel,at91rm9200-gpio";
-                                reg = <0xfffff400 0x100>;
-                                interrupts = <2 4>;
-                                #gpio-cells = <2>;
-                                gpio-controller;
-                                interrupt-controller;
-                        };
-                        pioB: gpio@fffff600 {
-                                compatible = "atmel,at91rm9200-gpio";
-                                reg = <0xfffff600 0x100>;
-                                interrupts = <3 4>;
-                                #gpio-cells = <2>;
-                                gpio-controller;
-                                interrupt-controller;
-                        };
-                        pioC: gpio@fffff800 {
-                                compatible = "atmel,at91rm9200-gpio";
-                                reg = <0xfffff800 0x100>;
-                                interrupts = <4 4>;
-                                #gpio-cells = <2>;
-                                gpio-controller;
-                                interrupt-controller;
-                        };
-                        dbgu: serial@fffff200 {
-                                compatible = "atmel,at91sam9260-usart";
-                                reg = <0xfffff200 0x200>;
-                                interrupts = <1 4>;
-                                status = "disabled";
-                        };
-                        usart0: serial@fffb0000 {
-                                compatible = "atmel,at91sam9260-usart";
-                                reg = <0xfffb0000 0x200>;
-                                interrupts = <6 4>;
-                                atmel,use-dma-rx;
-                                atmel,use-dma-tx;
-                                status = "disabled";
-                        };
-                        usart1: serial@fffb4000 {
-                                compatible = "atmel,at91sam9260-usart";
-                                reg = <0xfffb4000 0x200>;
-                                interrupts = <7 4>;
-                                atmel,use-dma-rx;
-                                atmel,use-dma-tx;
-                                status = "disabled";
-                        };
-                        usart2: serial@fffb8000 {
-                                compatible = "atmel,at91sam9260-usart";
-                                reg = <0xfffb8000 0x200>;
-                                interrupts = <8 4>;
-                                atmel,use-dma-rx;
-                                atmel,use-dma-tx;
-                                status = "disabled";
-                        };
-                        usart3: serial@fffd0000 {
-                                compatible = "atmel,at91sam9260-usart";
-                                reg = <0xfffd0000 0x200>;
-                                interrupts = <23 4>;
-                                atmel,use-dma-rx;
-                                atmel,use-dma-tx;
-                                status = "disabled";
-                        };
-                        usart4: serial@fffd4000 {
-                                compatible = "atmel,at91sam9260-usart";
-                                reg = <0xfffd4000 0x200>;
-                                interrupts = <24 4>;
-                                atmel,use-dma-rx;
-                                atmel,use-dma-tx;
-                                status = "disabled";
-                        };
-                        usart5: serial@fffd8000 {
-                                compatible = "atmel,at91sam9260-usart";
-                                reg = <0xfffd8000 0x200>;
-                                interrupts = <25 4>;
-                                atmel,use-dma-rx;
-                                atmel,use-dma-tx;
-                                status = "disabled";
-                        };
-                        macb0: ethernet@fffc4000 {
-                                compatible = "cdns,at32ap7000-macb", "cdns,macb";
-                                reg = <0xfffc4000 0x100>;
-                                interrupts = <21 4>;
-                                status = "disabled";
-                        };
-                        usb1: gadget@fffa4000 {
-                                compatible = "atmel,at91rm9200-udc";
-                                reg = <0xfffa4000 0x4000>;
-                                interrupts = <10 4>;
-                                status = "disabled";
                        };
                };
-                nand0: nand@40000000 {
-                        compatible = "atmel,at91rm9200-nand";
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        reg = <0x40000000 0x10000000
-                               0xffffe800 0x200
-                              >;
-                        atmel,nand-addr-offset = <21>;
-                        atmel,nand-cmd-offset = <22>;
-                        gpios = <&pioC 13 0
-                                 &pioC 14 0
-                                 0
-                                >;
-                        status = "disabled";
-                };
-                usb0: ohci@00500000 {
-                        compatible = "atmel,at91rm9200-ohci", "usb-ohci";
-                        reg = <0x00500000 0x100000>;
-                        interrupts = <20 4>;
-                        status = "disabled";
-                };
-        };
-        i2c@0 {
-                compatible = "i2c-gpio";
-                gpios = <&pioA 23 0 /* sda */
-                         &pioA 24 0 /* scl */
-                        >;
-                i2c-gpio,sda-open-drain;
-                i2c-gpio,scl-open-drain;
-                i2c-gpio,delay-us = <2>;        /* ~100 kHz */
-                #address-cells = <1>;
-                #size-cells = <0>;
-                status = "disabled";
        };
 };
diff --git a/arch/arm/boot/dts/at91sam9g20ek.dts b/arch/arm/boot/dts/at91sam9g20ek.dts
new file mode 100644
index 000000000000..e5324bf9d529
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9g20ek.dts
@@ -0,0 +1,29 @@
+/*
+ * at91sam9g20ek.dts - Device Tree file for Atmel at91sam9g20ek board
+ *
+ * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Licensed under GPLv2.
+ */
+/dts-v1/;
+/include/ "at91sam9g20ek_common.dtsi"
+/ {
+        model = "Atmel at91sam9g20ek";
+        compatible = "atmel,at91sam9g20ek", "atmel,at91sam9g20", "atmel,at91sam9";
+        leds {
+                compatible = "gpio-leds";
+                ds1 {
+                        label = "ds1";
+                        gpios = <&pioA 9 0>;
+                        linux,default-trigger = "heartbeat";
+                };
+                ds5 {
+                        label = "ds5";
+                        gpios = <&pioA 6 1>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/at91sam9g20ek_2mmc.dts b/arch/arm/boot/dts/at91sam9g20ek_2mmc.dts
new file mode 100644
index 000000000000..f1b2e148ac8c
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9g20ek_2mmc.dts
@@ -0,0 +1,29 @@
+/*
+ * at91sam9g20ek_2mmc.dts - Device Tree file for Atmel at91sam9g20ek 2 MMC board
+ *
+ * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Licensed under GPLv2.
+ */
+/dts-v1/;
+/include/ "at91sam9g20ek_common.dtsi"
+/ {
+        model = "Atmel at91sam9g20ek 2 mmc";
+        compatible = "atmel,at91sam9g20ek_2mmc", "atmel,at91sam9g20", "atmel,at91sam9";
+        leds {
+                compatible = "gpio-leds";
+                ds1 {
+                        label = "ds1";
+                        gpios = <&pioB 9 0>;
+                        linux,default-trigger = "heartbeat";
+                };
+                ds5 {
+                        label = "ds5";
+                        gpios = <&pioB 8 1>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
new file mode 100644
index 000000000000..b06c0db273b1
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
@@ -0,0 +1,142 @@
+/*
+ * at91sam9g20ek_common.dtsi - Device Tree file for Atmel at91sam9g20ek board
+ *
+ * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Licensed under GPLv2.
+ */
+/include/ "at91sam9g20.dtsi"
+/ {
+        chosen {
+                bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs";
+        };
+        memory {
+                reg = <0x20000000 0x4000000>;
+        };
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                main_clock: clock@0 {
+                        compatible = "atmel,osc", "fixed-clock";
+                        clock-frequency = <18432000>;
+                };
+        };
+        ahb {
+                apb {
+                        dbgu: serial@fffff200 {
+                                status = "okay";
+                        };
+                        usart0: serial@fffb0000 {
+                                status = "okay";
+                        };
+                        usart1: serial@fffb4000 {
+                                status = "okay";
+                        };
+                        macb0: ethernet@fffc4000 {
+                                phy-mode = "rmii";
+                                status = "okay";
+                        };
+                        usb1: gadget@fffa4000 {
+                                atmel,vbus-gpio = <&pioC 5 0>;
+                                status = "okay";
+                        };
+                };
+                nand0: nand@40000000 {
+                        nand-bus-width = <8>;
+                        nand-ecc-mode = "soft";
+                        nand-on-flash-bbt;
+                        status = "okay";
+                        at91bootstrap@0 {
+                                label = "at91bootstrap";
+                                reg = <0x0 0x20000>;
+                        };
+                        barebox@20000 {
+                                label = "barebox";
+                                reg = <0x20000 0x40000>;
+                        };
+                        bareboxenv@60000 {
+                                label = "bareboxenv";
+                                reg = <0x60000 0x20000>;
+                        };
+                        bareboxenv2@80000 {
+                                label = "bareboxenv2";
+                                reg = <0x80000 0x20000>;
+                        };
+                        oftree@80000 {
+                                label = "oftree";
+                                reg = <0xa0000 0x20000>;
+                        };
+                        kernel@a0000 {
+                                label = "kernel";
+                                reg = <0xc0000 0x400000>;
+                        };
+                        rootfs@4a0000 {
+                                label = "rootfs";
+                                reg = <0x4c0000 0x7800000>;
+                        };
+                        data@7ca0000 {
+                                label = "data";
+                                reg = <0x7cc0000 0x8340000>;
+                        };
+                };
+                usb0: ohci@00500000 {
+                        num-ports = <2>;
+                        status = "okay";
+                };
+        };
+        i2c@0 {
+                status = "okay";
+                24c512@50 {
+                        compatible = "24c512";
+                        reg = <0x50>;
+                };
+                wm8731@1b {
+                        compatible = "wm8731";
+                        reg = <0x1b>;
+                };
+        };
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                btn3 {
+                        label = "Buttin 3";
+                        gpios = <&pioA 30 1>;
+                        linux,code = <0x103>;
+                        gpio-key,wakeup;
+                };
+                btn4 {
+                        label = "Buttin 4";
+                        gpios = <&pioA 31 1>;
+                        linux,code = <0x104>;
+                        gpio-key,wakeup;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index 9e6eb6ecea0e..7dbccaf199f7 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -56,7 +56,6 @@
                                #interrupt-cells = <2>;
                                compatible = "atmel,at91rm9200-aic";
                                interrupt-controller;
-                                interrupt-parent;
                                reg = <0xfffff000 0x200>;
                        };
@@ -200,6 +199,43 @@
                                interrupts = <25 4>;
                                status = "disabled";
                        };
+                        adc0: adc@fffb0000 {
+                                compatible = "atmel,at91sam9260-adc";
+                                reg = <0xfffb0000 0x100>;
+                                interrupts = <20 4>;
+                                atmel,adc-use-external-triggers;
+                                atmel,adc-channels-used = <0xff>;
+                                atmel,adc-vref = <3300>;
+                                atmel,adc-num-channels = <8>;
+                                atmel,adc-startup-time = <40>;
+                                atmel,adc-channel-base = <0x30>;
+                                atmel,adc-drdy-mask = <0x10000>;
+                                atmel,adc-status-register = <0x1c>;
+                                atmel,adc-trigger-register = <0x08>;
+                                trigger@0 {
+                                        trigger-name = "external-rising";
+                                        trigger-value = <0x1>;
+                                        trigger-external;
+                                };
+                                trigger@1 {
+                                        trigger-name = "external-falling";
+                                        trigger-value = <0x2>;
+                                        trigger-external;
+                                };
+                                trigger@2 {
+                                        trigger-name = "external-any";
+                                        trigger-value = <0x3>;
+                                        trigger-external;
+                                };
+                                trigger@3 {
+                                        trigger-name = "continuous";
+                                        trigger-value = <0x6>;
+                                };
+                        };
                };
                nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
new file mode 100644
index 000000000000..cb84de791b5a
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -0,0 +1,221 @@
+/*
+ * at91sam9n12.dtsi - Device Tree include file for AT91SAM9N12 SoC
+ *
+ *  Copyright (C) 2012 Atmel,
+ *                2012 Hong Xu <hong.xu@atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+/include/ "skeleton.dtsi"
+/ {
+        model = "Atmel AT91SAM9N12 SoC";
+        compatible = "atmel,at91sam9n12";
+        interrupt-parent = <&aic>;
+        aliases {
+                serial0 = &dbgu;
+                serial1 = &usart0;
+                serial2 = &usart1;
+                serial3 = &usart2;
+                serial4 = &usart3;
+                gpio0 = &pioA;
+                gpio1 = &pioB;
+                gpio2 = &pioC;
+                gpio3 = &pioD;
+                tcb0 = &tcb0;
+                tcb1 = &tcb1;
+        };
+        cpus {
+                cpu@0 {
+                        compatible = "arm,arm926ejs";
+                };
+        };
+        memory {
+                reg = <0x20000000 0x10000000>;
+        };
+        ahb {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                apb {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+                        aic: interrupt-controller@fffff000 {
+                                #interrupt-cells = <2>;
+                                compatible = "atmel,at91rm9200-aic";
+                                interrupt-controller;
+                                reg = <0xfffff000 0x200>;
+                        };
+                        ramc0: ramc@ffffe800 {
+                                compatible = "atmel,at91sam9g45-ddramc";
+                                reg = <0xffffe800 0x200>;
+                        };
+                        pmc: pmc@fffffc00 {
+                                compatible = "atmel,at91rm9200-pmc";
+                                reg = <0xfffffc00 0x100>;
+                        };
+                        rstc@fffffe00 {
+                                compatible = "atmel,at91sam9g45-rstc";
+                                reg = <0xfffffe00 0x10>;
+                        };
+                        pit: timer@fffffe30 {
+                                compatible = "atmel,at91sam9260-pit";
+                                reg = <0xfffffe30 0xf>;
+                                interrupts = <1 4>;
+                        };
+                        shdwc@fffffe10 {
+                                compatible = "atmel,at91sam9x5-shdwc";
+                                reg = <0xfffffe10 0x10>;
+                        };
+                        tcb0: timer@f8008000 {
+                                compatible = "atmel,at91sam9x5-tcb";
+                                reg = <0xf8008000 0x100>;
+                                interrupts = <17 4>;
+                        };
+                        tcb1: timer@f800c000 {
+                                compatible = "atmel,at91sam9x5-tcb";
+                                reg = <0xf800c000 0x100>;
+                                interrupts = <17 4>;
+                        };
+                        dma: dma-controller@ffffec00 {
+                                compatible = "atmel,at91sam9g45-dma";
+                                reg = <0xffffec00 0x200>;
+                                interrupts = <20 4>;
+                        };
+                        pioA: gpio@fffff400 {
+                                compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+                                reg = <0xfffff400 0x100>;
+                                interrupts = <2 4>;
+                                #gpio-cells = <2>;
+                                gpio-controller;
+                                interrupt-controller;
+                        };
+                        pioB: gpio@fffff600 {
+                                compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+                                reg = <0xfffff600 0x100>;
+                                interrupts = <2 4>;
+                                #gpio-cells = <2>;
+                                gpio-controller;
+                                interrupt-controller;
+                        };
+                        pioC: gpio@fffff800 {
+                                compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+                                reg = <0xfffff800 0x100>;
+                                interrupts = <3 4>;
+                                #gpio-cells = <2>;
+                                gpio-controller;
+                                interrupt-controller;
+                        };
+                        pioD: gpio@fffffa00 {
+                                compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+                                reg = <0xfffffa00 0x100>;
+                                interrupts = <3 4>;
+                                #gpio-cells = <2>;
+                                gpio-controller;
+                                interrupt-controller;
+                        };
+                        dbgu: serial@fffff200 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xfffff200 0x200>;
+                                interrupts = <1 4>;
+                                status = "disabled";
+                        };
+                        usart0: serial@f801c000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xf801c000 0x4000>;
+                                interrupts = <5 4>;
+                                atmel,use-dma-rx;
+                                atmel,use-dma-tx;
+                                status = "disabled";
+                        };
+                        usart1: serial@f8020000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xf8020000 0x4000>;
+                                interrupts = <6 4>;
+                                atmel,use-dma-rx;
+                                atmel,use-dma-tx;
+                                status = "disabled";
+                        };
+                        usart2: serial@f8024000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xf8024000 0x4000>;
+                                interrupts = <7 4>;
+                                atmel,use-dma-rx;
+                                atmel,use-dma-tx;
+                                status = "disabled";
+                        };
+                        usart3: serial@f8028000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xf8028000 0x4000>;
+                                interrupts = <8 4>;
+                                atmel,use-dma-rx;
+                                atmel,use-dma-tx;
+                                status = "disabled";
+                        };
+                };
+                nand0: nand@40000000 {
+                        compatible = "atmel,at91rm9200-nand";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = < 0x40000000 0x10000000
+                                0xffffe000 0x00000600
+                                0xffffe600 0x00000200
+                                0x00100000 0x00100000
+                               >;
+                        atmel,nand-addr-offset = <21>;
+                        atmel,nand-cmd-offset = <22>;
+                        gpios = <&pioD 5 0
+                                 &pioD 4 0
+                                 0
+                                >;
+                        status = "disabled";
+                };
+                usb0: ohci@00500000 {
+                        compatible = "atmel,at91rm9200-ohci", "usb-ohci";
+                        reg = <0x00500000 0x00100000>;
+                        interrupts = <22 4>;
+                        status = "disabled";
+                };
+        };
+        i2c@0 {
+                compatible = "i2c-gpio";
+                gpios = <&pioA 30 0 /* sda */
+                         &pioA 31 0 /* scl */
+                        >;
+                i2c-gpio,sda-open-drain;
+                i2c-gpio,scl-open-drain;
+                i2c-gpio,delay-us = <2>;        /* ~100 kHz */
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
+};
diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts
new file mode 100644
index 000000000000..f4e43e38f3a1
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9n12ek.dts
@@ -0,0 +1,84 @@
+/*
+ * at91sam9n12ek.dts - Device Tree file for AT91SAM9N12-EK board
+ *
+ *  Copyright (C) 2012 Atmel,
+ *                2012 Hong Xu <hong.xu@atmel.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+/dts-v1/;
+/include/ "at91sam9n12.dtsi"
+/ {
+        model = "Atmel AT91SAM9N12-EK";
+        compatible = "atmel,at91sam9n12ek", "atmel,at91sam9n12", "atmel,at91sam9";
+        chosen {
+                bootargs = "mem=128M console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=jffs2";
+        };
+        memory {
+                reg = <0x20000000 0x10000000>;
+        };
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                main_clock: clock@0 {
+                        compatible = "atmel,osc", "fixed-clock";
+                        clock-frequency = <16000000>;
+                };
+        };
+        ahb {
+                apb {
+                        dbgu: serial@fffff200 {
+                                status = "okay";
+                        };
+                };
+                nand0: nand@40000000 {
+                        nand-bus-width = <8>;
+                        nand-ecc-mode = "soft";
+                        nand-on-flash-bbt;
+                        status = "okay";
+                };
+        };
+        leds {
+                compatible = "gpio-leds";
+                d8 {
+                        label = "d8";
+                        gpios = <&pioB 4 1>;
+                        linux,default-trigger = "mmc0";
+                };
+                d9 {
+                        label = "d6";
+                        gpios = <&pioB 5 1>;
+                        linux,default-trigger = "nand-disk";
+                };
+                d10 {
+                        label = "d7";
+                        gpios = <&pioB 6 0>;
+                        linux,default-trigger = "heartbeat";
+                };
+        };
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                enter {
+                        label = "Enter";
+                        gpios = <&pioB 4 1>;
+                        linux,code = <28>;
+                        gpio-key,wakeup;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 70ab3a4e026f..6b3ef4339ae7 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -54,7 +54,6 @@
                                #interrupt-cells = <2>;
                                compatible = "atmel,at91rm9200-aic";
                                interrupt-controller;
-                                interrupt-parent;
                                reg = <0xfffff000 0x200>;
                        };
@@ -191,6 +190,44 @@
                                interrupts = <27 4>;
                                status = "disabled";
                        };
+                        adc0: adc@f804c000 {
+                                compatible = "atmel,at91sam9260-adc";
+                                reg = <0xf804c000 0x100>;
+                                interrupts = <19 4>;
+                                atmel,adc-use-external;
+                                atmel,adc-channels-used = <0xffff>;
+                                atmel,adc-vref = <3300>;
+                                atmel,adc-num-channels = <12>;
+                                atmel,adc-startup-time = <40>;
+                                atmel,adc-channel-base = <0x50>;
+                                atmel,adc-drdy-mask = <0x1000000>;
+                                atmel,adc-status-register = <0x30>;
+                                atmel,adc-trigger-register = <0xc0>;
+                                trigger@0 {
+                                        trigger-name = "external-rising";
+                                        trigger-value = <0x1>;
+                                        trigger-external;
+                                };
+                                trigger@1 {
+                                        trigger-name = "external-falling";
+                                        trigger-value = <0x2>;
+                                        trigger-external;
+                                };
+                                trigger@2 {
+                                        trigger-name = "external-any";
+                                        trigger-value = <0x3>;
+                                        trigger-external;
+                                };
+                                trigger@3 {
+                                        trigger-name = "continuous";
+                                        trigger-value = <0x6>;
+                                };
+                        };
                };
                nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/db8500.dtsi b/arch/arm/boot/dts/db8500.dtsi
index d73dce645667..881bc3987844 100644
--- a/arch/arm/boot/dts/db8500.dtsi
+++ b/arch/arm/boot/dts/db8500.dtsi
@@ -24,7 +24,6 @@
                        #interrupt-cells = <3>;
                        #address-cells = <1>;
                        interrupt-controller;
-                        interrupt-parent;
                        reg = <0xa0411000 0x1000>,
                              <0xa0410100 0x100>;
                };
@@ -56,83 +55,101 @@
                gpio0: gpio@8012e000 {
                        compatible = "stericsson,db8500-gpio",
-                                "stmicroelectronics,nomadik-gpio";
+                                "st,nomadik-gpio";
                        reg =  <0x8012e000 0x80>;
                        interrupts = <0 119 0x4>;
                        supports-sleepmode;
                        gpio-controller;
+                        #gpio-cells = <2>;
+                        gpio-bank = <0>;
                };
                gpio1: gpio@8012e080 {
                        compatible = "stericsson,db8500-gpio",
-                                "stmicroelectronics,nomadik-gpio";
+                                "st,nomadik-gpio";
                        reg =  <0x8012e080 0x80>;
                        interrupts = <0 120 0x4>;
                        supports-sleepmode;
                        gpio-controller;
+                        #gpio-cells = <2>;
+                        gpio-bank = <1>;
                };
                gpio2: gpio@8000e000 {
                        compatible = "stericsson,db8500-gpio",
-                                "stmicroelectronics,nomadik-gpio";
+                                "st,nomadik-gpio";
                        reg =  <0x8000e000 0x80>;
                        interrupts = <0 121 0x4>;
                        supports-sleepmode;
                        gpio-controller;
+                        #gpio-cells = <2>;
+                        gpio-bank = <2>;
                };
                gpio3: gpio@8000e080 {
                        compatible = "stericsson,db8500-gpio",
-                                "stmicroelectronics,nomadik-gpio";
+                                "st,nomadik-gpio";
                        reg =  <0x8000e080 0x80>;
                        interrupts = <0 122 0x4>;
                        supports-sleepmode;
                        gpio-controller;
+                        #gpio-cells = <2>;
+                        gpio-bank = <3>;
                };
                gpio4: gpio@8000e100 {
                        compatible = "stericsson,db8500-gpio",
-                                "stmicroelectronics,nomadik-gpio";
+                                "st,nomadik-gpio";
                        reg =  <0x8000e100 0x80>;
                        interrupts = <0 123 0x4>;
                        supports-sleepmode;
                        gpio-controller;
+                        #gpio-cells = <2>;
+                        gpio-bank = <4>;
                };
                gpio5: gpio@8000e180 {
                        compatible = "stericsson,db8500-gpio",
-                                "stmicroelectronics,nomadik-gpio";
+                                "st,nomadik-gpio";
                        reg =  <0x8000e180 0x80>;
                        interrupts = <0 124 0x4>;
                        supports-sleepmode;
                        gpio-controller;
+                        #gpio-cells = <2>;
+                        gpio-bank = <5>;
                };
                gpio6: gpio@8011e000 {
                        compatible = "stericsson,db8500-gpio",
-                                "stmicroelectronics,nomadik-gpio";
+                                "st,nomadik-gpio";
                        reg =  <0x8011e000 0x80>;
                        interrupts = <0 125 0x4>;
                        supports-sleepmode;
                        gpio-controller;
+                        #gpio-cells = <2>;
+                        gpio-bank = <6>;
                };
                gpio7: gpio@8011e080 {
                        compatible = "stericsson,db8500-gpio",
-                                "stmicroelectronics,nomadik-gpio";
+                                "st,nomadik-gpio";
                        reg =  <0x8011e080 0x80>;
                        interrupts = <0 126 0x4>;
                        supports-sleepmode;
                        gpio-controller;
+                        #gpio-cells = <2>;
+                        gpio-bank = <7>;
                };
                gpio8: gpio@a03fe000 {
                        compatible = "stericsson,db8500-gpio",
-                                "stmicroelectronics,nomadik-gpio";
+                                "st,nomadik-gpio";
                        reg =  <0xa03fe000 0x80>;
                        interrupts = <0 127 0x4>;
                        supports-sleepmode;
                        gpio-controller;
+                        #gpio-cells = <2>;
+                        gpio-bank = <8>;
                };
                usb@a03e0000 {
@@ -154,7 +171,13 @@
                        reg = <0x80157000 0x1000>;
                        interrupts = <46 47>;
                        #address-cells = <1>;
-                        #size-cells = <0>;
+                        #size-cells = <1>;
+                        ranges;
+                                prcmu-timer-4@80157450 {
+                                compatible = "stericsson,db8500-prcmu-timer-4";
+                                reg = <0x80157450 0xC>;
+                        };
                        ab8500@5 {
                                compatible = "stericsson,ab8500";
@@ -164,7 +187,7 @@
                };
                i2c@80004000 {
-                        compatible = "stericsson,db8500-i2c", "stmicroelectronics,nomadik-i2c";
+                        compatible = "stericsson,db8500-i2c", "st,nomadik-i2c";
                        reg = <0x80004000 0x1000>;
                        interrupts = <0 21 0x4>;
                        #address-cells = <1>;
@@ -172,7 +195,7 @@
                };
                i2c@80122000 {
-                        compatible = "stericsson,db8500-i2c", "stmicroelectronics,nomadik-i2c";
+                        compatible = "stericsson,db8500-i2c", "st,nomadik-i2c";
                        reg = <0x80122000 0x1000>;
                        interrupts = <0 22 0x4>;
                        #address-cells = <1>;
@@ -180,7 +203,7 @@
                };
                i2c@80128000 {
-                        compatible = "stericsson,db8500-i2c", "stmicroelectronics,nomadik-i2c";
+                        compatible = "stericsson,db8500-i2c", "st,nomadik-i2c";
                        reg = <0x80128000 0x1000>;
                        interrupts = <0 55 0x4>;
                        #address-cells = <1>;
@@ -188,7 +211,7 @@
                };
                i2c@80110000 {
-                        compatible = "stericsson,db8500-i2c", "stmicroelectronics,nomadik-i2c";
+                        compatible = "stericsson,db8500-i2c", "st,nomadik-i2c";
                        reg = <0x80110000 0x1000>;
                        interrupts = <0 12 0x4>;
                        #address-cells = <1>;
@@ -196,7 +219,7 @@
                };
                i2c@8012a000 {
-                        compatible = "stericsson,db8500-i2c", "stmicroelectronics,nomadik-i2c";
+                        compatible = "stericsson,db8500-i2c", "st,nomadik-i2c";
                        reg = <0x8012a000 0x1000>;
                        interrupts = <0 51 0x4>;
                        #address-cells = <1>;
@@ -271,5 +294,14 @@
                        interrupts = <0 100 0x4>;
                        status = "disabled";
                };
+                external-bus@50000000 {
+                        compatible = "simple-bus";
+                        reg = <0x50000000 0x4000000>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 0x50000000 0x4000000>;
+                        status = "disabled";
+                };
        };
 };
diff --git a/arch/arm/boot/dts/emev2-kzm9d.dts b/arch/arm/boot/dts/emev2-kzm9d.dts
new file mode 100644
index 000000000000..297e3baba71c
--- /dev/null
+++ b/arch/arm/boot/dts/emev2-kzm9d.dts
@@ -0,0 +1,26 @@
+/*
+ * Device Tree Source for the KZM9D board
+ *
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+/dts-v1/;
+/include/ "emev2.dtsi"
+/ {
+        model = "EMEV2 KZM9D Board";
+        compatible = "renesas,kzm9d", "renesas,emev2";
+        memory {
+                device_type = "memory";
+                reg = <0x40000000 0x8000000>;
+        };
+        chosen {
+                bootargs = "console=ttyS1,115200n81";
+        };
+};
diff --git a/arch/arm/boot/dts/emev2.dtsi b/arch/arm/boot/dts/emev2.dtsi
new file mode 100644
index 000000000000..eb504a6c0f4a
--- /dev/null
+++ b/arch/arm/boot/dts/emev2.dtsi
@@ -0,0 +1,63 @@
+/*
+ * Device Tree Source for the EMEV2 SoC
+ *
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+/include/ "skeleton.dtsi"
+/ {
+        compatible = "renesas,emev2";
+        interrupt-parent = <&gic>;
+        cpus {
+                cpu@0 {
+                        compatible = "arm,cortex-a9";
+                };
+                cpu@1 {
+                        compatible = "arm,cortex-a9";
+                };
+        };
+        gic: interrupt-controller@e0020000 {
+                compatible = "arm,cortex-a9-gic";
+                interrupt-controller;
+                #interrupt-cells = <3>;
+                reg = <0xe0028000 0x1000>,
+                      <0xe0020000 0x0100>;
+        };
+        sti@e0180000 {
+                compatible = "renesas,em-sti";
+                reg = <0xe0180000 0x54>;
+                interrupts = <0 125 0>;
+        };
+        uart@e1020000 {
+                compatible = "renesas,em-uart";
+                reg = <0xe1020000 0x38>;
+                interrupts = <0 8 0>;
+        };
+        uart@e1030000 {
+                compatible = "renesas,em-uart";
+                reg = <0xe1030000 0x38>;
+                interrupts = <0 9 0>;
+        };
+        uart@e1040000 {
+                compatible = "renesas,em-uart";
+                reg = <0xe1040000 0x38>;
+                interrupts = <0 10 0>;
+        };
+        uart@e1050000 {
+                compatible = "renesas,em-uart";
+                reg = <0xe1050000 0x38>;
+                interrupts = <0 11 0>;
+        };
+};
diff --git a/arch/arm/boot/dts/ethernut5.dts b/arch/arm/boot/dts/ethernut5.dts
new file mode 100644
index 000000000000..1ea9d34460a4
--- /dev/null
+++ b/arch/arm/boot/dts/ethernut5.dts
@@ -0,0 +1,84 @@
+/*
+ * ethernut5.dts - Device Tree file for Ethernut 5 board
+ *
+ * Copyright (C) 2012 egnite GmbH <info@egnite.de>
+ *
+ * Licensed under GPLv2.
+ */
+/dts-v1/;
+/include/ "at91sam9260.dtsi"
+/ {
+        model = "Ethernut 5";
+        compatible = "egnite,ethernut5", "atmel,at91sam9260", "atmel,at91sam9";
+        chosen {
+                bootargs = "console=ttyS0,115200 root=/dev/mtdblock0 rw rootfstype=jffs2";
+        };
+        memory {
+                reg = <0x20000000 0x08000000>;
+        };
+        ahb {
+                apb {
+                        dbgu: serial@fffff200 {
+                                status = "okay";
+                        };
+                        usart0: serial@fffb0000 {
+                                status = "okay";
+                        };
+                        usart1: serial@fffb4000 {
+                                status = "okay";
+                        };
+                        macb0: ethernet@fffc4000 {
+                                phy-mode = "rmii";
+                                status = "okay";
+                        };
+                        usb1: gadget@fffa4000 {
+                                atmel,vbus-gpio = <&pioC 5 0>;
+                                status = "okay";
+                        };
+                };
+                nand0: nand@40000000 {
+                        nand-bus-width = <8>;
+                        nand-ecc-mode = "soft";
+                        nand-on-flash-bbt;
+                        status = "okay";
+                        gpios = <0
+                                 &pioC 14 0
+                                 0
+                                >;
+                        root@0 {
+                                label = "root";
+                                reg = <0x0 0x08000000>;
+                        };
+                        data@20000 {
+                                label = "data";
+                                reg = <0x08000000 0x38000000>;
+                        };
+                };
+                usb0: ohci@00500000 {
+                        num-ports = <2>;
+                        status = "okay";
+                };
+        };
+        i2c@0 {
+                status = "okay";
+                pcf8563@50 {
+                        compatible = "nxp,pcf8563";
+                        reg = <0x51>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/highbank.dts b/arch/arm/boot/dts/highbank.dts
index 37c0ff9c8b90..83e72294aefb 100644
--- a/arch/arm/boot/dts/highbank.dts
+++ b/arch/arm/boot/dts/highbank.dts
@@ -89,7 +89,6 @@
                        #size-cells = <0>;
                        #address-cells = <1>;
                        interrupt-controller;
-                        interrupt-parent;
                        reg = <0xfff11000 0x1000>,
                              <0xfff10100 0x100>;
                };
diff --git a/arch/arm/boot/dts/kirkwood-dns320.dts b/arch/arm/boot/dts/kirkwood-dns320.dts
new file mode 100644
index 000000000000..dc09a735b04a
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-dns320.dts
@@ -0,0 +1,64 @@
+/dts-v1/;
+/include/ "kirkwood.dtsi"
+/ {
+        model = "D-Link DNS-320 NAS (Rev A1)";
+        compatible = "dlink,dns-320-a1", "dlink,dns-320", "dlink,dns-kirkwood", "mrvl,kirkwood-88f6281", "mrvl,kirkwood";
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x8000000>;
+        };
+        chosen {
+                bootargs = "console=ttyS0,115200n8 earlyprintk";
+        };
+        ocp@f1000000 {
+                serial@12000 {
+                        clock-frequency = <166666667>;
+                        status = "okay";
+                };
+                serial@12100 {
+                        clock-frequency = <166666667>;
+                        status = "okay";
+                };
+                nand@3000000 {
+                        status = "okay";
+                        partition@0 {
+                                label = "u-boot";
+                                reg = <0x0000000 0x100000>;
+                                read-only;
+                        };
+                        partition@100000 {
+                                label = "uImage";
+                                reg = <0x0100000 0x500000>;
+                        };
+                        partition@600000 {
+                                label = "ramdisk";
+                                reg = <0x0600000 0x500000>;
+                        };
+                        partition@b00000 {
+                                label = "image";
+                                reg = <0x0b00000 0x6600000>;
+                        };
+                        partition@7100000 {
+                                label = "mini firmware";
+                                reg = <0x7100000 0xa00000>;
+                        };
+                        partition@7b00000 {
+                                label = "config";
+                                reg = <0x7b00000 0x500000>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-dns325.dts b/arch/arm/boot/dts/kirkwood-dns325.dts
new file mode 100644
index 000000000000..c2a5562525d2
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-dns325.dts
@@ -0,0 +1,59 @@
+/dts-v1/;
+/include/ "kirkwood.dtsi"
+/ {
+        model = "D-Link DNS-325 NAS (Rev A1)";
+        compatible = "dlink,dns-325-a1", "dlink,dns-325", "dlink,dns-kirkwood", "mrvl,kirkwood-88f6281", "mrvl,kirkwood";
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x10000000>;
+        };
+        chosen {
+                bootargs = "console=ttyS0,115200n8 earlyprintk";
+        };
+        ocp@f1000000 {
+                serial@12000 {
+                        clock-frequency = <200000000>;
+                        status = "okay";
+                };
+                nand@3000000 {
+                        status = "okay";
+                        partition@0 {
+                                label = "u-boot";
+                                reg = <0x0000000 0x100000>;
+                                read-only;
+                        };
+                        partition@100000 {
+                                label = "uImage";
+                                reg = <0x0100000 0x500000>;
+                        };
+                        partition@600000 {
+                                label = "ramdisk";
+                                reg = <0x0600000 0x500000>;
+                        };
+                        partition@b00000 {
+                                label = "image";
+                                reg = <0x0b00000 0x6600000>;
+                        };
+                        partition@7100000 {
+                                label = "mini firmware";
+                                reg = <0x7100000 0xa00000>;
+                        };
+                        partition@7b00000 {
+                                label = "config";
+                                reg = <0x7b00000 0x500000>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-ib62x0.dts b/arch/arm/boot/dts/kirkwood-ib62x0.dts
new file mode 100644
index 000000000000..ada0f0c23085
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-ib62x0.dts
@@ -0,0 +1,44 @@
+/dts-v1/;
+/include/ "kirkwood.dtsi"
+/ {
+        model = "RaidSonic ICY BOX IB-NAS62x0 (Rev B)";
+        compatible = "raidsonic,ib-nas6210-b", "raidsonic,ib-nas6220-b", "raidsonic,ib-nas6210", "raidsonic,ib-nas6220", "raidsonic,ib-nas62x0",  "mrvl,kirkwood-88f6281", "mrvl,kirkwood";
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x10000000>;
+        };
+        chosen {
+                bootargs = "console=ttyS0,115200n8 earlyprintk";
+        };
+        ocp@f1000000 {
+                serial@12000 {
+                        clock-frequency = <200000000>;
+                        status = "okay";
+                };
+                nand@3000000 {
+                        status = "okay";
+                        partition@0 {
+                                label = "u-boot";
+                                reg = <0x0000000 0x100000>;
+                        };
+                        partition@100000 {
+                                label = "uImage";
+                                reg = <0x0100000 0x600000>;
+                        };
+                        partition@700000 {
+                                label = "root";
+                                reg = <0x0700000 0xf900000>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-iconnect.dts b/arch/arm/boot/dts/kirkwood-iconnect.dts
new file mode 100644
index 000000000000..1ba75d4adecc
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-iconnect.dts
@@ -0,0 +1,26 @@
+/dts-v1/;
+/include/ "kirkwood.dtsi"
+/ {
+        model = "Iomega Iconnect";
+        compatible = "iom,iconnect-1.1", "iom,iconnect", "mrvl,kirkwood-88f6281", "mrvl,kirkwood";
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x10000000>;
+        };
+        chosen {
+                bootargs = "console=ttyS0,115200n8 earlyprintk mtdparts=orion_nand:0xc0000@0x0(uboot),0x20000@0xa0000(env),0x300000@0x100000(zImage),0x300000@0x540000(initrd),0x1f400000@0x980000(boot)";
+                linux,initrd-start = <0x4500040>;
+                linux,initrd-end   = <0x4800000>;
+        };
+        ocp@f1000000 {
+                serial@12000 {
+                        clock-frequency = <200000000>;
+                        status = "ok";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
index 3474ef890945..926528b81baa 100644
--- a/arch/arm/boot/dts/kirkwood.dtsi
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -5,7 +5,7 @@
        ocp@f1000000 {
                compatible = "simple-bus";
-                ranges = <0 0xf1000000 0x1000000>;
+                ranges = <0 0xf1000000 0x4000000>;
                #address-cells = <1>;
                #size-cells = <1>;
@@ -32,5 +32,18 @@
                        reg = <0x10300 0x20>;
                        interrupts = <53>;
                };
+                nand@3000000 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        cle = <0>;
+                        ale = <1>;
+                        bank-width = <1>;
+                        compatible = "mrvl,orion-nand";
+                        reg = <0x3000000 0x400>;
+                        chip-delay = <25>;
+                        /* set partition map and/or chip-delay in board dts */
+                        status = "disabled";
+                };
        };
 };
diff --git a/arch/arm/boot/dts/kizbox.dts b/arch/arm/boot/dts/kizbox.dts
new file mode 100644
index 000000000000..e8814fe0e277
--- /dev/null
+++ b/arch/arm/boot/dts/kizbox.dts
@@ -0,0 +1,138 @@
+/*
+ * kizbox.dts - Device Tree file for Overkiz Kizbox board
+ *
+ * Copyright (C) 2012 Boris BREZILLON <linux-arm@overkiz.com>
+ *
+ * Licensed under GPLv2.
+ */
+/dts-v1/;
+/include/ "at91sam9g20.dtsi"
+/ {
+        model = "Overkiz kizbox";
+        compatible = "overkiz,kizbox", "atmel,at91sam9g20", "atmel,at91sam9";
+        chosen {
+                bootargs = "panic=5 ubi.mtd=1 rootfstype=ubifs root=ubi0:root";
+        };
+        memory {
+                reg = <0x20000000 0x2000000>;
+        };
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                main_clock: clock@0 {
+                        compatible = "atmel,osc", "fixed-clock";
+                        clock-frequency = <18432000>;
+                };
+        };
+        ahb {
+                apb {
+                        dbgu: serial@fffff200 {
+                                status = "okay";
+                        };
+                        usart0: serial@fffb0000 {
+                                status = "okay";
+                        };
+                        usart1: serial@fffb4000 {
+                                status = "okay";
+                        };
+                        macb0: ethernet@fffc4000 {
+                                phy-mode = "mii";
+                                status = "okay";
+                        };
+                };
+                nand0: nand@40000000 {
+                        nand-bus-width = <8>;
+                        nand-ecc-mode = "soft";
+                        status = "okay";
+                        bootloaderkernel@0 {
+                                label = "bootloader-kernel";
+                                reg = <0x0 0xc0000>;
+                        };
+                        ubi@c0000 {
+                                label = "ubi";
+                                reg = <0xc0000 0x7f40000>;
+                        };
+                };
+                usb0: ohci@00500000 {
+                        num-ports = <1>;
+                        status = "okay";
+                };
+        };
+        i2c@0 {
+                status = "okay";
+                pcf8563@51 {
+                        /* nxp pcf8563 rtc */
+                        compatible = "nxp,pcf8563";
+                        reg = <0x51>;
+                };
+        };
+        leds {
+                compatible = "gpio-leds";
+                led1g {
+                        label = "led1:green";
+                        gpios = <&pioB 0 1>;
+                        linux,default-trigger = "none";
+                };
+                led1r {
+                        label = "led1:red";
+                        gpios = <&pioB 1 1>;
+                        linux,default-trigger = "none";
+                };
+                led2g {
+                        label = "led2:green";
+                        gpios = <&pioB 2 1>;
+                        linux,default-trigger = "none";
+                        default-state = "on";
+                };
+                led2r {
+                        label = "led2:red";
+                        gpios = <&pioB 3 1>;
+                        linux,default-trigger = "none";
+                };
+        };
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reset {
+                        label = "reset";
+                        gpios = <&pioB 30 1>;
+                        linux,code = <0x100>;
+                        gpio-key,wakeup;
+                };
+                mode {
+                        label = "mode";
+                        gpios = <&pioB 31 1>;
+                        linux,code = <0x101>;
+                        gpio-key,wakeup;
+                };
+        };
+};
+\ No newline at end of file
diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi
new file mode 100644
index 000000000000..2d696866f71c
--- /dev/null
+++ b/arch/arm/boot/dts/lpc32xx.dtsi
@@ -0,0 +1,292 @@
+/*
+ * NXP LPC32xx SoC
+ *
+ * Copyright 2012 Roland Stigge <stigge@antcom.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/include/ "skeleton.dtsi"
+/ {
+        compatible = "nxp,lpc3220";
+        interrupt-parent = <&mic>;
+        cpus {
+                cpu@0 {
+                        compatible = "arm,arm926ejs";
+                };
+        };
+        ahb {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                ranges = <0x20000000 0x20000000 0x30000000>;
+                /*
+                 * Enable either SLC or MLC
+                 */
+                slc: flash@20020000 {
+                        compatible = "nxp,lpc3220-slc";
+                        reg = <0x20020000 0x1000>;
+                        status = "disable";
+                };
+                mlc: flash@200B0000 {
+                        compatible = "nxp,lpc3220-mlc";
+                        reg = <0x200B0000 0x1000>;
+                        status = "disable";
+                };
+                dma@31000000 {
+                        compatible = "arm,pl080", "arm,primecell";
+                        reg = <0x31000000 0x1000>;
+                        interrupts = <0x1c 0>;
+                };
+                /*
+                 * Enable either ohci or usbd (gadget)!
+                 */
+                ohci@31020000 {
+                        compatible = "nxp,ohci-nxp", "usb-ohci";
+                        reg = <0x31020000 0x300>;
+                        interrupts = <0x3b 0>;
+                        status = "disable";
+                };
+                usbd@31020000 {
+                        compatible = "nxp,lpc3220-udc";
+                        reg = <0x31020000 0x300>;
+                        interrupts = <0x3d 0>, <0x3e 0>, <0x3c 0>, <0x3a 0>;
+                        status = "disable";
+                };
+                clcd@31040000 {
+                        compatible = "arm,pl110", "arm,primecell";
+                        reg = <0x31040000 0x1000>;
+                        interrupts = <0x0e 0>;
+                        status = "disable";
+                };
+                mac: ethernet@31060000 {
+                        compatible = "nxp,lpc-eth";
+                        reg = <0x31060000 0x1000>;
+                        interrupts = <0x1d 0>;
+                };
+                apb {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "simple-bus";
+                        ranges = <0x20000000 0x20000000 0x30000000>;
+                        ssp0: ssp@20084000 {
+                                compatible = "arm,pl022", "arm,primecell";
+                                reg = <0x20084000 0x1000>;
+                                interrupts = <0x14 0>;
+                        };
+                        spi1: spi@20088000 {
+                                compatible = "nxp,lpc3220-spi";
+                                reg = <0x20088000 0x1000>;
+                        };
+                        ssp1: ssp@2008c000 {
+                                compatible = "arm,pl022", "arm,primecell";
+                                reg = <0x2008c000 0x1000>;
+                                interrupts = <0x15 0>;
+                        };
+                        spi2: spi@20090000 {
+                                compatible = "nxp,lpc3220-spi";
+                                reg = <0x20090000 0x1000>;
+                        };
+                        i2s0: i2s@20094000 {
+                                compatible = "nxp,lpc3220-i2s";
+                                reg = <0x20094000 0x1000>;
+                        };
+                        sd@20098000 {
+                                compatible = "arm,pl180", "arm,primecell";
+                                reg = <0x20098000 0x1000>;
+                                interrupts = <0x0f 0>, <0x0d 0>;
+                        };
+                        i2s1: i2s@2009C000 {
+                                compatible = "nxp,lpc3220-i2s";
+                                reg = <0x2009C000 0x1000>;
+                        };
+                        uart3: serial@40080000 {
+                                compatible = "nxp,serial";
+                                reg = <0x40080000 0x1000>;
+                        };
+                        uart4: serial@40088000 {
+                                compatible = "nxp,serial";
+                                reg = <0x40088000 0x1000>;
+                        };
+                        uart5: serial@40090000 {
+                                compatible = "nxp,serial";
+                                reg = <0x40090000 0x1000>;
+                        };
+                        uart6: serial@40098000 {
+                                compatible = "nxp,serial";
+                                reg = <0x40098000 0x1000>;
+                        };
+                        i2c1: i2c@400A0000 {
+                                compatible = "nxp,pnx-i2c";
+                                reg = <0x400A0000 0x100>;
+                                interrupts = <0x33 0>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                pnx,timeout = <0x64>;
+                        };
+                        i2c2: i2c@400A8000 {
+                                compatible = "nxp,pnx-i2c";
+                                reg = <0x400A8000 0x100>;
+                                interrupts = <0x32 0>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                pnx,timeout = <0x64>;
+                        };
+                        i2cusb: i2c@31020300 {
+                                compatible = "nxp,pnx-i2c";
+                                reg = <0x31020300 0x100>;
+                                interrupts = <0x3f 0>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                pnx,timeout = <0x64>;
+                        };
+                };
+                fab {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "simple-bus";
+                        ranges = <0x20000000 0x20000000 0x30000000>;
+                        /*
+                         * MIC Interrupt controller includes:
+                         *   MIC @40008000
+                         *   SIC1 @4000C000
+                         *   SIC2 @40010000
+                         */
+                        mic: interrupt-controller@40008000 {
+                                compatible = "nxp,lpc3220-mic";
+                                interrupt-controller;
+                                reg = <0x40008000 0xC000>;
+                                #interrupt-cells = <2>;
+                        };
+                        uart1: serial@40014000 {
+                                compatible = "nxp,serial";
+                                reg = <0x40014000 0x1000>;
+                        };
+                        uart2: serial@40018000 {
+                                compatible = "nxp,serial";
+                                reg = <0x40018000 0x1000>;
+                        };
+                        uart7: serial@4001C000 {
+                                compatible = "nxp,serial";
+                                reg = <0x4001C000 0x1000>;
+                        };
+                        rtc@40024000 {
+                                compatible = "nxp,lpc3220-rtc";
+                                reg = <0x40024000 0x1000>;
+                                interrupts = <0x34 0>;
+                        };
+                        gpio: gpio@40028000 {
+                                compatible = "nxp,lpc3220-gpio";
+                                reg = <0x40028000 0x1000>;
+                                /* create a private address space for enumeration */
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                gpio_p0: gpio-bank@0 {
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                        reg = <0>;
+                                };
+                                gpio_p1: gpio-bank@1 {
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                        reg = <1>;
+                                };
+                                gpio_p2: gpio-bank@2 {
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                        reg = <2>;
+                                };
+                                gpio_p3: gpio-bank@3 {
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                        reg = <3>;
+                                };
+                                gpi_p3: gpio-bank@4 {
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                        reg = <4>;
+                                };
+                                gpo_p3: gpio-bank@5 {
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                        reg = <5>;
+                                };
+                        };
+                        watchdog@4003C000 {
+                                compatible = "nxp,pnx4008-wdt";
+                                reg = <0x4003C000 0x1000>;
+                        };
+                        /*
+                         * TSC vs. ADC: Since those two share the same
+                         * hardware, you need to choose from one of the
+                         * following two and do 'status = "okay";' for one of
+                         * them
+                         */
+                        adc@40048000 {
+                                compatible = "nxp,lpc3220-adc";
+                                reg = <0x40048000 0x1000>;
+                                interrupts = <0x27 0>;
+                                status = "disable";
+                        };
+                        tsc@40048000 {
+                                compatible = "nxp,lpc3220-tsc";
+                                reg = <0x40048000 0x1000>;
+                                interrupts = <0x27 0>;
+                                status = "disable";
+                        };
+                        key@40050000 {
+                                compatible = "nxp,lpc3220-key";
+                                reg = <0x40050000 0x1000>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/mmp2-brownstone.dts b/arch/arm/boot/dts/mmp2-brownstone.dts
new file mode 100644
index 000000000000..153a4b2d12b5
--- /dev/null
+++ b/arch/arm/boot/dts/mmp2-brownstone.dts
@@ -0,0 +1,38 @@
+/*
+ *  Copyright (C) 2012 Marvell Technology Group Ltd.
+ *  Author: Haojian Zhuang <haojian.zhuang@marvell.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+/dts-v1/;
+/include/ "mmp2.dtsi"
+/ {
+        model = "Marvell MMP2 Aspenite Development Board";
+        compatible = "mrvl,mmp2-brownstone", "mrvl,mmp2";
+        chosen {
+                bootargs = "console=ttyS2,38400 root=/dev/nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on";
+        };
+        memory {
+                reg = <0x00000000 0x04000000>;
+        };
+        soc {
+                apb@d4000000 {
+                        uart3: uart@d4018000 {
+                                status = "okay";
+                        };
+                        twsi1: i2c@d4011000 {
+                                status = "okay";
+                        };
+                        rtc: rtc@d4010000 {
+                                status = "okay";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/mmp2.dtsi b/arch/arm/boot/dts/mmp2.dtsi
new file mode 100644
index 000000000000..80f74e256408
--- /dev/null
+++ b/arch/arm/boot/dts/mmp2.dtsi
@@ -0,0 +1,220 @@
+/*
+ *  Copyright (C) 2012 Marvell Technology Group Ltd.
+ *  Author: Haojian Zhuang <haojian.zhuang@marvell.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+/include/ "skeleton.dtsi"
+/ {
+        aliases {
+                serial0 = &uart1;
+                serial1 = &uart2;
+                serial2 = &uart3;
+                serial3 = &uart4;
+                i2c0 = &twsi1;
+                i2c1 = &twsi2;
+        };
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                interrupt-parent = <&intc>;
+                ranges;
+                axi@d4200000 {  /* AXI */
+                        compatible = "mrvl,axi-bus", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0xd4200000 0x00200000>;
+                        ranges;
+                        intc: interrupt-controller@d4282000 {
+                                compatible = "mrvl,mmp2-intc";
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                                reg = <0xd4282000 0x1000>;
+                                mrvl,intc-nr-irqs = <64>;
+                        };
+                        intcmux4@d4282150 {
+                                compatible = "mrvl,mmp2-mux-intc";
+                                interrupts = <4>;
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                                reg = <0x150 0x4>, <0x168 0x4>;
+                                reg-names = "mux status", "mux mask";
+                                mrvl,intc-nr-irqs = <2>;
+                        };
+                        intcmux5: interrupt-controller@d4282154 {
+                                compatible = "mrvl,mmp2-mux-intc";
+                                interrupts = <5>;
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                                reg = <0x154 0x4>, <0x16c 0x4>;
+                                reg-names = "mux status", "mux mask";
+                                mrvl,intc-nr-irqs = <2>;
+                                mrvl,clr-mfp-irq = <1>;
+                        };
+                        intcmux9: interrupt-controller@d4282180 {
+                                compatible = "mrvl,mmp2-mux-intc";
+                                interrupts = <9>;
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                                reg = <0x180 0x4>, <0x17c 0x4>;
+                                reg-names = "mux status", "mux mask";
+                                mrvl,intc-nr-irqs = <3>;
+                        };
+                        intcmux17: interrupt-controller@d4282158 {
+                                compatible = "mrvl,mmp2-mux-intc";
+                                interrupts = <17>;
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                                reg = <0x158 0x4>, <0x170 0x4>;
+                                reg-names = "mux status", "mux mask";
+                                mrvl,intc-nr-irqs = <5>;
+                        };
+                        intcmux35: interrupt-controller@d428215c {
+                                compatible = "mrvl,mmp2-mux-intc";
+                                interrupts = <35>;
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                                reg = <0x15c 0x4>, <0x174 0x4>;
+                                reg-names = "mux status", "mux mask";
+                                mrvl,intc-nr-irqs = <15>;
+                        };
+                        intcmux51: interrupt-controller@d4282160 {
+                                compatible = "mrvl,mmp2-mux-intc";
+                                interrupts = <51>;
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                                reg = <0x160 0x4>, <0x178 0x4>;
+                                reg-names = "mux status", "mux mask";
+                                mrvl,intc-nr-irqs = <2>;
+                        };
+                        intcmux55: interrupt-controller@d4282188 {
+                                compatible = "mrvl,mmp2-mux-intc";
+                                interrupts = <55>;
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                                reg = <0x188 0x4>, <0x184 0x4>;
+                                reg-names = "mux status", "mux mask";
+                                mrvl,intc-nr-irqs = <2>;
+                        };
+                };
+                apb@d4000000 {  /* APB */
+                        compatible = "mrvl,apb-bus", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0xd4000000 0x00200000>;
+                        ranges;
+                        timer0: timer@d4014000 {
+                                compatible = "mrvl,mmp-timer";
+                                reg = <0xd4014000 0x100>;
+                                interrupts = <13>;
+                        };
+                        uart1: uart@d4030000 {
+                                compatible = "mrvl,mmp-uart";
+                                reg = <0xd4030000 0x1000>;
+                                interrupts = <27>;
+                                status = "disabled";
+                        };
+                        uart2: uart@d4017000 {
+                                compatible = "mrvl,mmp-uart";
+                                reg = <0xd4017000 0x1000>;
+                                interrupts = <28>;
+                                status = "disabled";
+                        };
+                        uart3: uart@d4018000 {
+                                compatible = "mrvl,mmp-uart";
+                                reg = <0xd4018000 0x1000>;
+                                interrupts = <24>;
+                                status = "disabled";
+                        };
+                        uart4: uart@d4016000 {
+                                compatible = "mrvl,mmp-uart";
+                                reg = <0xd4016000 0x1000>;
+                                interrupts = <46>;
+                                status = "disabled";
+                        };
+                        gpio@d4019000 {
+                                compatible = "mrvl,mmp-gpio";
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                reg = <0xd4019000 0x1000>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupts = <49>;
+                                interrupt-names = "gpio_mux";
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                                ranges;
+                                gcb0: gpio@d4019000 {
+                                        reg = <0xd4019000 0x4>;
+                                };
+                                gcb1: gpio@d4019004 {
+                                        reg = <0xd4019004 0x4>;
+                                };
+                                gcb2: gpio@d4019008 {
+                                        reg = <0xd4019008 0x4>;
+                                };
+                                gcb3: gpio@d4019100 {
+                                        reg = <0xd4019100 0x4>;
+                                };
+                                gcb4: gpio@d4019104 {
+                                        reg = <0xd4019104 0x4>;
+                                };
+                                gcb5: gpio@d4019108 {
+                                        reg = <0xd4019108 0x4>;
+                                };
+                        };
+                        twsi1: i2c@d4011000 {
+                                compatible = "mrvl,mmp-twsi";
+                                reg = <0xd4011000 0x1000>;
+                                interrupts = <7>;
+                                mrvl,i2c-fast-mode;
+                                status = "disabled";
+                        };
+                        twsi2: i2c@d4025000 {
+                                compatible = "mrvl,mmp-twsi";
+                                reg = <0xd4025000 0x1000>;
+                                interrupts = <58>;
+                                status = "disabled";
+                        };
+                        rtc: rtc@d4010000 {
+                                compatible = "mrvl,mmp-rtc";
+                                reg = <0xd4010000 0x1000>;
+                                interrupts = <1 0>;
+                                interrupt-names = "rtc 1Hz", "rtc alarm";
+                                interrupt-parent = <&intcmux5>;
+                                status = "disabled";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/msm8660-surf.dts b/arch/arm/boot/dts/msm8660-surf.dts
index 15ded0deaa79..45bc4bb04e57 100644
--- a/arch/arm/boot/dts/msm8660-surf.dts
+++ b/arch/arm/boot/dts/msm8660-surf.dts
@@ -10,7 +10,7 @@
        intc: interrupt-controller@02080000 {
                compatible = "qcom,msm-8660-qgic";
                interrupt-controller;
-                #interrupt-cells = <1>;
+                #interrupt-cells = <3>;
                reg = < 0x02080000 0x1000 >,
                      < 0x02081000 0x1000 >;
        };
@@ -19,6 +19,6 @@
                compatible = "qcom,msm-hsuart", "qcom,msm-uart";
                reg = <0x19c40000 0x1000>,
                      <0x19c00000 0x1000>;
-                interrupts = <195>;
+                interrupts = <0 195 0x0>;
        };
 };
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
index 9f72cd4cf308..8c756be4d7ad 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -18,3 +18,52 @@
                reg = <0x80000000 0x20000000>; /* 512 MB */
        };
 };
+&i2c1 {
+        clock-frequency = <2600000>;
+        twl: twl@48 {
+                reg = <0x48>;
+                interrupts = <7>; /* SYS_NIRQ cascaded to intc */
+                interrupt-parent = <&intc>;
+                vsim: regulator@10 {
+                        compatible = "ti,twl4030-vsim";
+                        regulator-min-microvolt = <1800000>;
+                        regulator-max-microvolt = <3000000>;
+                };
+        };
+};
+/include/ "twl4030.dtsi"
+&i2c2 {
+        clock-frequency = <400000>;
+};
+&i2c3 {
+        clock-frequency = <100000>;
+        /*
+         * Display monitor features are burnt in the EEPROM
+         * as EDID data.
+         */
+        eeprom@50 {
+                compatible = "ti,eeprom";
+                reg = <0x50>;
+        };
+};
+&mmc1 {
+        vmmc-supply = <&vmmc1>;
+        vmmc_aux-supply = <&vsim>;
+        ti,bus-width = <8>;
+};
+&mmc2 {
+        status = "disable";
+};
+&mmc3 {
+        status = "disable";
+};
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index c6121357c1eb..99474fa5fac4 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -69,6 +69,60 @@
                        reg = <0x48200000 0x1000>;
                };
+                gpio1: gpio@48310000 {
+                        compatible = "ti,omap3-gpio";
+                        ti,hwmods = "gpio1";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                };
+                gpio2: gpio@49050000 {
+                        compatible = "ti,omap3-gpio";
+                        ti,hwmods = "gpio2";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                };
+                gpio3: gpio@49052000 {
+                        compatible = "ti,omap3-gpio";
+                        ti,hwmods = "gpio3";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                };
+                gpio4: gpio@49054000 {
+                        compatible = "ti,omap3-gpio";
+                        ti,hwmods = "gpio4";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                };
+                gpio5: gpio@49056000 {
+                        compatible = "ti,omap3-gpio";
+                        ti,hwmods = "gpio5";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                };
+                gpio6: gpio@49058000 {
+                        compatible = "ti,omap3-gpio";
+                        ti,hwmods = "gpio6";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                };
                uart1: serial@4806a000 {
                        compatible = "ti,omap3-uart";
                        ti,hwmods = "uart1";
@@ -113,5 +167,53 @@
                        #size-cells = <0>;
                        ti,hwmods = "i2c3";
                };
+                mcspi1: spi@48098000 {
+                        compatible = "ti,omap2-mcspi";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        ti,hwmods = "mcspi1";
+                        ti,spi-num-cs = <4>;
+                };
+                mcspi2: spi@4809a000 {
+                        compatible = "ti,omap2-mcspi";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        ti,hwmods = "mcspi2";
+                        ti,spi-num-cs = <2>;
+                };
+                mcspi3: spi@480b8000 {
+                        compatible = "ti,omap2-mcspi";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        ti,hwmods = "mcspi3";
+                        ti,spi-num-cs = <2>;
+                };
+                mcspi4: spi@480ba000 {
+                        compatible = "ti,omap2-mcspi";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        ti,hwmods = "mcspi4";
+                        ti,spi-num-cs = <1>;
+                };
+                mmc1: mmc@4809c000 {
+                        compatible = "ti,omap3-hsmmc";
+                        ti,hwmods = "mmc1";
+                        ti,dual-volt;
+                };
+                mmc2: mmc@480b4000 {
+                        compatible = "ti,omap3-hsmmc";
+                        ti,hwmods = "mmc2";
+                };
+                mmc3: mmc@480ad000 {
+                        compatible = "ti,omap3-hsmmc";
+                        ti,hwmods = "mmc3";
+                };
        };
 };
diff --git a/arch/arm/boot/dts/omap4-panda.dts b/arch/arm/boot/dts/omap4-panda.dts
index 9755ad5917f8..e671361bc791 100644
--- a/arch/arm/boot/dts/omap4-panda.dts
+++ b/arch/arm/boot/dts/omap4-panda.dts
@@ -17,4 +17,75 @@
                device_type = "memory";
                reg = <0x80000000 0x40000000>; /* 1 GB */
        };
+        leds {
+                compatible = "gpio-leds";
+                heartbeat {
+                        label = "pandaboard::status1";
+                        gpios = <&gpio1 7 0>;
+                        linux,default-trigger = "heartbeat";
+                };
+                mmc {
+                        label = "pandaboard::status2";
+                        gpios = <&gpio1 8 0>;
+                        linux,default-trigger = "mmc0";
+                };
+        };
+};
+&i2c1 {
+        clock-frequency = <400000>;
+        twl: twl@48 {
+                reg = <0x48>;
+                /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */
+                interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */
+                interrupt-parent = <&gic>;
+        };
+};
+/include/ "twl6030.dtsi"
+&i2c2 {
+        clock-frequency = <400000>;
+};
+&i2c3 {
+        clock-frequency = <100000>;
+        /*
+         * Display monitor features are burnt in their EEPROM as EDID data.
+         * The EEPROM is connected as I2C slave device.
+         */
+        eeprom@50 {
+                compatible = "ti,eeprom";
+                reg = <0x50>;
+        };
+};
+&i2c4 {
+        clock-frequency = <400000>;
+};
+&mmc1 {
+        vmmc-supply = <&vmmc>;
+        ti,bus-width = <8>;
+};
+&mmc2 {
+        status = "disable";
+};
+&mmc3 {
+        status = "disable";
+};
+&mmc4 {
+        status = "disable";
+};
+&mmc5 {
+        ti,non-removable;
+        ti,bus-width = <4>;
 };
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index 63c6b2b2bf42..e5eeb6f9c6e6 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -17,4 +17,144 @@
                device_type = "memory";
                reg = <0x80000000 0x40000000>; /* 1 GB */
        };
+        vdd_eth: fixedregulator@0 {
+                compatible = "regulator-fixed";
+                regulator-name = "VDD_ETH";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&gpio2 16 0>;  /* gpio line 48 */
+                enable-active-high;
+                regulator-boot-on;
+        };
+        leds {
+                compatible = "gpio-leds";
+                debug0 {
+                        label = "omap4:green:debug0";
+                        gpios = <&gpio2 29 0>; /* 61 */
+                };
+                debug1 {
+                        label = "omap4:green:debug1";
+                        gpios = <&gpio1 30 0>; /* 30 */
+                };
+                debug2 {
+                        label = "omap4:green:debug2";
+                        gpios = <&gpio1 7 0>; /* 7 */
+                };
+                debug3 {
+                        label = "omap4:green:debug3";
+                        gpios = <&gpio1 8 0>; /* 8 */
+                };
+                debug4 {
+                        label = "omap4:green:debug4";
+                        gpios = <&gpio2 18 0>; /* 50 */
+                };
+                user1 {
+                        label = "omap4:blue:user";
+                        gpios = <&gpio6 9 0>; /* 169 */
+                };
+                user2 {
+                        label = "omap4:red:user";
+                        gpios = <&gpio6 10 0>; /* 170 */
+                };
+                user3 {
+                        label = "omap4:green:user";
+                        gpios = <&gpio5 11 0>; /* 139 */
+                };
+        };
+};
+&i2c1 {
+        clock-frequency = <400000>;
+        twl: twl@48 {
+                reg = <0x48>;
+                /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */
+                interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */
+                interrupt-parent = <&gic>;
+        };
+};
+/include/ "twl6030.dtsi"
+&i2c2 {
+        clock-frequency = <400000>;
+};
+&i2c3 {
+        clock-frequency = <400000>;
+        /*
+         * Temperature Sensor
+         * http://www.ti.com/lit/ds/symlink/tmp105.pdf
+         */
+        tmp105@48 {
+                compatible = "ti,tmp105";
+                reg = <0x48>;
+        };
+        /*
+         * Ambient Light Sensor
+         * http://www.rohm.com/products/databook/sensor/pdf/bh1780gli-e.pdf
+         */
+        bh1780@29 {
+                compatible = "rohm,bh1780";
+                reg = <0x29>;
+        };
+};
+&i2c4 {
+        clock-frequency = <400000>;
+        /*
+         * 3-Axis Digital Compass
+         * http://www.sparkfun.com/datasheets/Sensors/Magneto/HMC5843.pdf
+         */
+        hmc5843@1e {
+                compatible = "honeywell,hmc5843";
+                reg = <0x1e>;
+        };
+};
+&mcspi1 {
+        eth@0 {
+                compatible = "ks8851";
+                spi-max-frequency = <24000000>;
+                reg = <0>;
+                interrupt-parent = <&gpio2>;
+                interrupts = <2>; /* gpio line 34 */
+                vdd-supply = <&vdd_eth>;
+        };
+};
+&mmc1 {
+        vmmc-supply = <&vmmc>;
+        ti,bus-width = <8>;
+};
+&mmc2 {
+        vmmc-supply = <&vaux1>;
+        ti,bus-width = <8>;
+        ti,non-removable;
+};
+&mmc3 {
+        status = "disable";
+};
+&mmc4 {
+        status = "disable";
+};
+&mmc5 {
+        ti,bus-width = <4>;
+        ti,non-removable;
 };
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 3d35559e77bc..359c4979c8aa 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -104,6 +104,60 @@
                              <0x48240100 0x0100>;
                };
+                gpio1: gpio@4a310000 {
+                        compatible = "ti,omap4-gpio";
+                        ti,hwmods = "gpio1";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                };
+                gpio2: gpio@48055000 {
+                        compatible = "ti,omap4-gpio";
+                        ti,hwmods = "gpio2";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                };
+                gpio3: gpio@48057000 {
+                        compatible = "ti,omap4-gpio";
+                        ti,hwmods = "gpio3";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                };
+                gpio4: gpio@48059000 {
+                        compatible = "ti,omap4-gpio";
+                        ti,hwmods = "gpio4";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                };
+                gpio5: gpio@4805b000 {
+                        compatible = "ti,omap4-gpio";
+                        ti,hwmods = "gpio5";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                };
+                gpio6: gpio@4805d000 {
+                        compatible = "ti,omap4-gpio";
+                        ti,hwmods = "gpio6";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                };
                uart1: serial@4806a000 {
                        compatible = "ti,omap4-uart";
                        ti,hwmods = "uart1";
@@ -155,5 +209,68 @@
                        #size-cells = <0>;
                        ti,hwmods = "i2c4";
                };
+                mcspi1: spi@48098000 {
+                        compatible = "ti,omap4-mcspi";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        ti,hwmods = "mcspi1";
+                        ti,spi-num-cs = <4>;
+                };
+                mcspi2: spi@4809a000 {
+                        compatible = "ti,omap4-mcspi";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        ti,hwmods = "mcspi2";
+                        ti,spi-num-cs = <2>;
+                };
+                mcspi3: spi@480b8000 {
+                        compatible = "ti,omap4-mcspi";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        ti,hwmods = "mcspi3";
+                        ti,spi-num-cs = <2>;
+                };
+                mcspi4: spi@480ba000 {
+                        compatible = "ti,omap4-mcspi";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        ti,hwmods = "mcspi4";
+                        ti,spi-num-cs = <1>;
+                };
+                mmc1: mmc@4809c000 {
+                        compatible = "ti,omap4-hsmmc";
+                        ti,hwmods = "mmc1";
+                        ti,dual-volt;
+                        ti,needs-special-reset;
+                };
+                mmc2: mmc@480b4000 {
+                        compatible = "ti,omap4-hsmmc";
+                        ti,hwmods = "mmc2";
+                        ti,needs-special-reset;
+                };
+                mmc3: mmc@480ad000 {
+                        compatible = "ti,omap4-hsmmc";
+                        ti,hwmods = "mmc3";
+                        ti,needs-special-reset;
+                };
+                mmc4: mmc@480d1000 {
+                        compatible = "ti,omap4-hsmmc";
+                        ti,hwmods = "mmc4";
+                        ti,needs-special-reset;
+                };
+                mmc5: mmc@480d5000 {
+                        compatible = "ti,omap4-hsmmc";
+                        ti,hwmods = "mmc5";
+                        ti,needs-special-reset;
+                };
        };
 };
diff --git a/arch/arm/boot/dts/phy3250.dts b/arch/arm/boot/dts/phy3250.dts
new file mode 100644
index 000000000000..0167e86314c0
--- /dev/null
+++ b/arch/arm/boot/dts/phy3250.dts
@@ -0,0 +1,145 @@
+/*
+ * PHYTEC phyCORE-LPC3250 board
+ *
+ * Copyright 2012 Roland Stigge <stigge@antcom.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/dts-v1/;
+/include/ "lpc32xx.dtsi"
+/ {
+        model = "PHYTEC phyCORE-LPC3250 board based on NXP LPC3250";
+        compatible = "phytec,phy3250", "nxp,lpc3250";
+        #address-cells = <1>;
+        #size-cells = <1>;
+        memory {
+                device_type = "memory";
+                reg = <0 0x4000000>;
+        };
+        ahb {
+                mac: ethernet@31060000 {
+                        phy-mode = "rmii";
+                        use-iram;
+                };
+                /* Here, choose exactly one from: ohci, usbd */
+                ohci@31020000 {
+                        transceiver = <&isp1301>;
+                        status = "okay";
+                };
+/*
+                usbd@31020000 {
+                        transceiver = <&isp1301>;
+                        status = "okay";
+                };
+*/
+                clcd@31040000 {
+                        status = "okay";
+                };
+                /* 64MB Flash via SLC NAND controller */
+                slc: flash@20020000 {
+                        status = "okay";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        mtd0@00000000 {
+                                label = "phy3250-boot";
+                                reg = <0x00000000 0x00064000>;
+                                read-only;
+                        };
+                        mtd1@00064000 {
+                                label = "phy3250-uboot";
+                                reg = <0x00064000 0x00190000>;
+                                read-only;
+                        };
+                        mtd2@001f4000 {
+                                label = "phy3250-ubt-prms";
+                                reg = <0x001f4000 0x00010000>;
+                        };
+                        mtd3@00204000 {
+                                label = "phy3250-kernel";
+                                reg = <0x00204000 0x00400000>;
+                        };
+                        mtd4@00604000 {
+                                label = "phy3250-rootfs";
+                                reg = <0x00604000 0x039fc000>;
+                        };
+                };
+                apb {
+                        i2c1: i2c@400A0000 {
+                                clock-frequency = <100000>;
+                                pcf8563: rtc@51 {
+                                        compatible = "nxp,pcf8563";
+                                        reg = <0x51>;
+                                };
+                                uda1380: uda1380@18 {
+                                        compatible = "nxp,uda1380";
+                                        reg = <0x18>;
+                                        power-gpio = <&gpio 0x59 0>;
+                                        reset-gpio = <&gpio 0x51 0>;
+                                        dac-clk = "wspll";
+                                };
+                        };
+                        i2c2: i2c@400A8000 {
+                                clock-frequency = <100000>;
+                        };
+                        i2cusb: i2c@31020300 {
+                                clock-frequency = <100000>;
+                                isp1301: usb-transceiver@2c {
+                                        compatible = "nxp,isp1301";
+                                        reg = <0x2c>;
+                                };
+                        };
+                        ssp0: ssp@20084000 {
+                                eeprom: at25@0 {
+                                        compatible = "atmel,at25";
+                                };
+                        };
+                };
+                fab {
+                        tsc@40048000 {
+                                status = "okay";
+                        };
+                };
+        };
+        leds {
+                compatible = "gpio-leds";
+                led0 {
+                        gpios = <&gpo_p3 1 1>; /* GPO_P3 1, GPIO 80, active low */
+                        linux,default-trigger = "heartbeat";
+                        default-state = "off";
+                };
+                led1 {
+                        gpios = <&gpo_p3 14 1>; /* GPO_P3 14, GPIO 93, active low */
+                        linux,default-trigger = "timer";
+                        default-state = "off";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/pxa168.dtsi b/arch/arm/boot/dts/pxa168.dtsi
index d32d5128f225..31a718696080 100644
--- a/arch/arm/boot/dts/pxa168.dtsi
+++ b/arch/arm/boot/dts/pxa168.dtsi
@@ -18,13 +18,6 @@
                i2c1 = &twsi2;
        };
-        intc: intc-interrupt-controller@d4282000 {
-                compatible = "mrvl,mmp-intc", "mrvl,intc";
-                interrupt-controller;
-                #interrupt-cells = <1>;
-                reg = <0xd4282000 0x1000>;
-        };
        soc {
                #address-cells = <1>;
                #size-cells = <1>;
@@ -32,6 +25,23 @@
                interrupt-parent = <&intc>;
                ranges;
+                axi@d4200000 {  /* AXI */
+                        compatible = "mrvl,axi-bus", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0xd4200000 0x00200000>;
+                        ranges;
+                        intc: interrupt-controller@d4282000 {
+                                compatible = "mrvl,mmp-intc";
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                                reg = <0xd4282000 0x1000>;
+                                mrvl,intc-nr-irqs = <64>;
+                        };
+                };
                apb@d4000000 {  /* APB */
                        compatible = "mrvl,apb-bus", "simple-bus";
                        #address-cells = <1>;
@@ -39,40 +49,65 @@
                        reg = <0xd4000000 0x00200000>;
                        ranges;
+                        timer0: timer@d4014000 {
+                                compatible = "mrvl,mmp-timer";
+                                reg = <0xd4014000 0x100>;
+                                interrupts = <13>;
+                        };
                        uart1: uart@d4017000 {
-                                compatible = "mrvl,mmp-uart", "mrvl,pxa-uart";
+                                compatible = "mrvl,mmp-uart";
                                reg = <0xd4017000 0x1000>;
                                interrupts = <27>;
                                status = "disabled";
                        };
                        uart2: uart@d4018000 {
-                                compatible = "mrvl,mmp-uart", "mrvl,pxa-uart";
+                                compatible = "mrvl,mmp-uart";
                                reg = <0xd4018000 0x1000>;
                                interrupts = <28>;
                                status = "disabled";
                        };
                        uart3: uart@d4026000 {
-                                compatible = "mrvl,mmp-uart", "mrvl,pxa-uart";
+                                compatible = "mrvl,mmp-uart";
                                reg = <0xd4026000 0x1000>;
                                interrupts = <29>;
                                status = "disabled";
                        };
-                        gpio: gpio@d4019000 {
+                        gpio@d4019000 {
-                                compatible = "mrvl,mmp-gpio", "mrvl,pxa-gpio";
+                                compatible = "mrvl,mmp-gpio";
+                                #address-cells = <1>;
+                                #size-cells = <1>;
                                reg = <0xd4019000 0x1000>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
                                interrupts = <49>;
                                interrupt-names = "gpio_mux";
-                                gpio-controller;
-                                #gpio-cells = <1>;
                                interrupt-controller;
                                #interrupt-cells = <1>;
+                                ranges;
+                                gcb0: gpio@d4019000 {
+                                        reg = <0xd4019000 0x4>;
+                                };
+                                gcb1: gpio@d4019004 {
+                                        reg = <0xd4019004 0x4>;
+                                };
+                                gcb2: gpio@d4019008 {
+                                        reg = <0xd4019008 0x4>;
+                                };
+                                gcb3: gpio@d4019100 {
+                                        reg = <0xd4019100 0x4>;
+                                };
                        };
                        twsi1: i2c@d4011000 {
-                                compatible = "mrvl,mmp-twsi", "mrvl,pxa-i2c";
+                                compatible = "mrvl,mmp-twsi";
                                reg = <0xd4011000 0x1000>;
                                interrupts = <7>;
                                mrvl,i2c-fast-mode;
@@ -80,7 +115,7 @@
                        };
                        twsi2: i2c@d4025000 {
-                                compatible = "mrvl,mmp-twsi", "mrvl,pxa-i2c";
+                                compatible = "mrvl,mmp-twsi";
                                reg = <0xd4025000 0x1000>;
                                interrupts = <58>;
                                status = "disabled";
diff --git a/arch/arm/boot/dts/pxa910-dkb.dts b/arch/arm/boot/dts/pxa910-dkb.dts
new file mode 100644
index 000000000000..e92be5a474e7
--- /dev/null
+++ b/arch/arm/boot/dts/pxa910-dkb.dts
@@ -0,0 +1,38 @@
+/*
+ *  Copyright (C) 2012 Marvell Technology Group Ltd.
+ *  Author: Haojian Zhuang <haojian.zhuang@marvell.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+/dts-v1/;
+/include/ "pxa910.dtsi"
+/ {
+        model = "Marvell PXA910 DKB Development Board";
+        compatible = "mrvl,pxa910-dkb", "mrvl,pxa910";
+        chosen {
+                bootargs = "console=ttyS0,115200 root=/dev/nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on";
+        };
+        memory {
+                reg = <0x00000000 0x10000000>;
+        };
+        soc {
+                apb@d4000000 {
+                        uart1: uart@d4017000 {
+                                status = "okay";
+                        };
+                        twsi1: i2c@d4011000 {
+                                status = "okay";
+                        };
+                        rtc: rtc@d4010000 {
+                                status = "okay";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/pxa910.dtsi b/arch/arm/boot/dts/pxa910.dtsi
new file mode 100644
index 000000000000..aebf32de73b4
--- /dev/null
+++ b/arch/arm/boot/dts/pxa910.dtsi
@@ -0,0 +1,140 @@
+/*
+ *  Copyright (C) 2012 Marvell Technology Group Ltd.
+ *  Author: Haojian Zhuang <haojian.zhuang@marvell.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+/include/ "skeleton.dtsi"
+/ {
+        aliases {
+                serial0 = &uart1;
+                serial1 = &uart2;
+                serial2 = &uart3;
+                i2c0 = &twsi1;
+                i2c1 = &twsi2;
+        };
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                interrupt-parent = <&intc>;
+                ranges;
+                axi@d4200000 {  /* AXI */
+                        compatible = "mrvl,axi-bus", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0xd4200000 0x00200000>;
+                        ranges;
+                        intc: interrupt-controller@d4282000 {
+                                compatible = "mrvl,mmp-intc";
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                                reg = <0xd4282000 0x1000>;
+                                mrvl,intc-nr-irqs = <64>;
+                        };
+                };
+                apb@d4000000 {  /* APB */
+                        compatible = "mrvl,apb-bus", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0xd4000000 0x00200000>;
+                        ranges;
+                        timer0: timer@d4014000 {
+                                compatible = "mrvl,mmp-timer";
+                                reg = <0xd4014000 0x100>;
+                                interrupts = <13>;
+                        };
+                        timer1: timer@d4016000 {
+                                compatible = "mrvl,mmp-timer";
+                                reg = <0xd4016000 0x100>;
+                                interrupts = <29>;
+                                status = "disabled";
+                        };
+                        uart1: uart@d4017000 {
+                                compatible = "mrvl,mmp-uart";
+                                reg = <0xd4017000 0x1000>;
+                                interrupts = <27>;
+                                status = "disabled";
+                        };
+                        uart2: uart@d4018000 {
+                                compatible = "mrvl,mmp-uart";
+                                reg = <0xd4018000 0x1000>;
+                                interrupts = <28>;
+                                status = "disabled";
+                        };
+                        uart3: uart@d4036000 {
+                                compatible = "mrvl,mmp-uart";
+                                reg = <0xd4036000 0x1000>;
+                                interrupts = <59>;
+                                status = "disabled";
+                        };
+                        gpio@d4019000 {
+                                compatible = "mrvl,mmp-gpio";
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                reg = <0xd4019000 0x1000>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupts = <49>;
+                                interrupt-names = "gpio_mux";
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                                ranges;
+                                gcb0: gpio@d4019000 {
+                                        reg = <0xd4019000 0x4>;
+                                };
+                                gcb1: gpio@d4019004 {
+                                        reg = <0xd4019004 0x4>;
+                                };
+                                gcb2: gpio@d4019008 {
+                                        reg = <0xd4019008 0x4>;
+                                };
+                                gcb3: gpio@d4019100 {
+                                        reg = <0xd4019100 0x4>;
+                                };
+                        };
+                        twsi1: i2c@d4011000 {
+                                compatible = "mrvl,mmp-twsi";
+                                reg = <0xd4011000 0x1000>;
+                                interrupts = <7>;
+                                mrvl,i2c-fast-mode;
+                                status = "disabled";
+                        };
+                        twsi2: i2c@d4037000 {
+                                compatible = "mrvl,mmp-twsi";
+                                reg = <0xd4037000 0x1000>;
+                                interrupts = <54>;
+                                status = "disabled";
+                        };
+                        rtc: rtc@d4010000 {
+                                compatible = "mrvl,mmp-rtc";
+                                reg = <0xd4010000 0x1000>;
+                                interrupts = <5 6>;
+                                interrupt-names = "rtc 1Hz", "rtc alarm";
+                                status = "disabled";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
new file mode 100644
index 000000000000..a7505a95a3b7
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
@@ -0,0 +1,22 @@
+/*
+ * Device Tree Source for the armadillo 800 eva board
+ *
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+/dts-v1/;
+/include/ "skeleton.dtsi"
+/ {
+        model = "armadillo 800 eva";
+        compatible = "renesas,armadillo800eva";
+        memory {
+                device_type = "memory";
+                reg = <0x40000000 0x20000000>;
+        };
+};
diff --git a/arch/arm/boot/dts/sh7372.dtsi b/arch/arm/boot/dts/sh7372.dtsi
new file mode 100644
index 000000000000..677fc603f8b3
--- /dev/null
+++ b/arch/arm/boot/dts/sh7372.dtsi
@@ -0,0 +1,21 @@
+/*
+ * Device Tree Source for the sh7372 SoC
+ *
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+/include/ "skeleton.dtsi"
+/ {
+        compatible = "renesas,sh7372";
+        cpus {
+                cpu@0 {
+                        compatible = "arm,cortex-a8";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/sh73a0-kzm9g.dts b/arch/arm/boot/dts/sh73a0-kzm9g.dts
new file mode 100644
index 000000000000..bcb911951978
--- /dev/null
+++ b/arch/arm/boot/dts/sh73a0-kzm9g.dts
@@ -0,0 +1,22 @@
+/*
+ * Device Tree Source for the KZM-A9-GT board
+ *
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+/dts-v1/;
+/include/ "skeleton.dtsi"
+/ {
+        model = "KZM-A9-GT";
+        compatible = "renesas,kzm9g", "renesas,sh73a0";
+        memory {
+                device_type = "memory";
+                reg = <0x41000000 0x1e800000>;
+        };
+};
diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/snowball.dts
index 359c6d679156..d99dc04f0d91 100644
--- a/arch/arm/boot/dts/snowball.dts
+++ b/arch/arm/boot/dts/snowball.dts
@@ -30,35 +30,35 @@
                        wakeup = <1>;
                        linux,code = <2>;
                        label = "userpb";
-                        gpios = <&gpio1 0>;
+                        gpios = <&gpio1 0 0>;
                };
                button@2 {
                        debounce_interval = <50>;
                        wakeup = <1>;
                        linux,code = <3>;
-                        label = "userpb";
+                        label = "extkb1";
-                        gpios = <&gpio4 23>;
+                        gpios = <&gpio4 23 0>;
                };
                button@3 {
                        debounce_interval = <50>;
                        wakeup = <1>;
                        linux,code = <4>;
-                        label = "userpb";
+                        label = "extkb2";
-                        gpios = <&gpio4 23>;
+                        gpios = <&gpio4 24 0>;
                };
                button@4 {
                        debounce_interval = <50>;
                        wakeup = <1>;
                        linux,code = <5>;
-                        label = "userpb";
+                        label = "extkb3";
-                        gpios = <&gpio5 1>;
+                        gpios = <&gpio5 1 0>;
                };
                button@5 {
                        debounce_interval = <50>;
                        wakeup = <1>;
                        linux,code = <6>;
-                        label = "userpb";
+                        label = "extkb4";
-                        gpios = <&gpio5 2>;
+                        gpios = <&gpio5 2 0>;
                };
        };
@@ -73,17 +73,19 @@
        soc-u9500 {
                external-bus@50000000 {
-                        compatible = "simple-bus";
+                        status = "okay";
-                        reg = <0x50000000 0x10000000>;
-                        #address-cells = <1>;
+                        ethernet@0 {
-                        #size-cells = <1>;
+                                compatible = "smsc,lan9115";
-                        ranges;
+                                reg = <0 0x10000>;
+                                interrupts = <12 0x1>;
-                        ethernet@50000000 {
-                                compatible = "smsc,9111";
-                                reg = <0x50000000 0x10000>;
-                                interrupts = <12>;
                                interrupt-parent = <&gpio4>;
+                                reg-shift = <1>;
+                                reg-io-width = <2>;
+                                smsc,force-internal-phy;
+                                smsc,irq-active-high;
+                                smsc,irq-push-pull;
                        };
                };
diff --git a/arch/arm/boot/dts/spear300-evb.dts b/arch/arm/boot/dts/spear300-evb.dts
new file mode 100644
index 000000000000..910e264b87c0
--- /dev/null
+++ b/arch/arm/boot/dts/spear300-evb.dts
@@ -0,0 +1,221 @@
+/*
+ * DTS file for SPEAr300 Evaluation Baord
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/dts-v1/;
+/include/ "spear300.dtsi"
+/ {
+        model = "ST SPEAr300 Evaluation Board";
+        compatible = "st,spear300-evb", "st,spear300";
+        #address-cells = <1>;
+        #size-cells = <1>;
+        memory {
+                reg = <0 0x40000000>;
+        };
+        ahb {
+                pinmux@99000000 {
+                        st,pinmux-mode = <2>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&state_default>;
+                        state_default: pinmux {
+                                i2c0 {
+                                        st,pins = "i2c0_grp";
+                                        st,function = "i2c0";
+                                };
+                                ssp0 {
+                                        st,pins = "ssp0_grp";
+                                        st,function = "ssp0";
+                                };
+                                mii0 {
+                                        st,pins = "mii0_grp";
+                                        st,function = "mii0";
+                                };
+                                uart0 {
+                                        st,pins = "uart0_grp";
+                                        st,function = "uart0";
+                                };
+                                clcd {
+                                        st,pins = "clcd_pfmode_grp";
+                                        st,function = "clcd";
+                                };
+                                sdhci {
+                                        st,pins = "sdhci_4bit_grp";
+                                        st,function = "sdhci";
+                                };
+                                gpio1 {
+                                        st,pins = "gpio1_4_to_7_grp",
+                                                "gpio1_0_to_3_grp";
+                                        st,function = "gpio1";
+                                };
+                        };
+                };
+                clcd@60000000 {
+                        status = "okay";
+                };
+                dma@fc400000 {
+                        status = "okay";
+                };
+                fsmc: flash@94000000 {
+                        status = "okay";
+                };
+                gmac: eth@e0800000 {
+                        status = "okay";
+                };
+                sdhci@70000000 {
+                        int-gpio = <&gpio1 0 0>;
+                        power-gpio = <&gpio1 2 1>;
+                        status = "okay";
+                };
+                smi: flash@fc000000 {
+                        status = "okay";
+                };
+                spi0: spi@d0100000 {
+                        status = "okay";
+                };
+                ehci@e1800000 {
+                        status = "okay";
+                };
+                ohci@e1900000 {
+                        status = "okay";
+                };
+                ohci@e2100000 {
+                        status = "okay";
+                };
+                apb {
+                        gpio0: gpio@fc980000 {
+                               status = "okay";
+                        };
+                        gpio1: gpio@a9000000 {
+                               status = "okay";
+                        };
+                        i2c0: i2c@d0180000 {
+                               status = "okay";
+                        };
+                        kbd@a0000000 {
+                                linux,keymap = < 0x00000001
+                                                 0x00010002
+                                                 0x00020003
+                                                 0x00030004
+                                                 0x00040005
+                                                 0x00050006
+                                                 0x00060007
+                                                 0x00070008
+                                                 0x00080009
+                                                 0x0100000a
+                                                 0x0101000c
+                                                 0x0102000d
+                                                 0x0103000e
+                                                 0x0104000f
+                                                 0x01050010
+                                                 0x01060011
+                                                 0x01070012
+                                                 0x01080013
+                                                 0x02000014
+                                                 0x02010015
+                                                 0x02020016
+                                                 0x02030017
+                                                 0x02040018
+                                                 0x02050019
+                                                 0x0206001a
+                                                 0x0207001b
+                                                 0x0208001c
+                                                 0x0300001d
+                                                 0x0301001e
+                                                 0x0302001f
+                                                 0x03030020
+                                                 0x03040021
+                                                 0x03050022
+                                                 0x03060023
+                                                 0x03070024
+                                                 0x03080025
+                                                 0x04000026
+                                                 0x04010027
+                                                 0x04020028
+                                                 0x04030029
+                                                 0x0404002a
+                                                 0x0405002b
+                                                 0x0406002c
+                                                 0x0407002d
+                                                 0x0408002e
+                                                 0x0500002f
+                                                 0x05010030
+                                                 0x05020031
+                                                 0x05030032
+                                                 0x05040033
+                                                 0x05050034
+                                                 0x05060035
+                                                 0x05070036
+                                                 0x05080037
+                                                 0x06000038
+                                                 0x06010039
+                                                 0x0602003a
+                                                 0x0603003b
+                                                 0x0604003c
+                                                 0x0605003d
+                                                 0x0606003e
+                                                 0x0607003f
+                                                 0x06080040
+                                                 0x07000041
+                                                 0x07010042
+                                                 0x07020043
+                                                 0x07030044
+                                                 0x07040045
+                                                 0x07050046
+                                                 0x07060047
+                                                 0x07070048
+                                                 0x07080049
+                                                 0x0800004a
+                                                 0x0801004b
+                                                 0x0802004c
+                                                 0x0803004d
+                                                 0x0804004e
+                                                 0x0805004f
+                                                 0x08060050
+                                                 0x08070051
+                                                 0x08080052 >;
+                               autorepeat;
+                               st,mode = <0>;
+                               status = "okay";
+                        };
+                        rtc@fc900000 {
+                               status = "okay";
+                        };
+                        serial@d0000000 {
+                               status = "okay";
+                        };
+                        wdt@fc880000 {
+                               status = "okay";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/spear300.dtsi b/arch/arm/boot/dts/spear300.dtsi
new file mode 100644
index 000000000000..01c5e358fdb2
--- /dev/null
+++ b/arch/arm/boot/dts/spear300.dtsi
@@ -0,0 +1,77 @@
+/*
+ * DTS file for SPEAr300 SoC
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/include/ "spear3xx.dtsi"
+/ {
+        ahb {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                ranges = <0x60000000 0x60000000 0x50000000
+                          0xd0000000 0xd0000000 0x30000000>;
+                pinmux@99000000 {
+                        compatible = "st,spear300-pinmux";
+                        reg = <0x99000000 0x1000>;
+                };
+                clcd@60000000 {
+                        compatible = "arm,clcd-pl110", "arm,primecell";
+                        reg = <0x60000000 0x1000>;
+                        interrupts = <30>;
+                        status = "disabled";
+                };
+                fsmc: flash@94000000 {
+                        compatible = "st,spear600-fsmc-nand";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x94000000 0x1000        /* FSMC Register */
+                               0x80000000 0x0010>;      /* NAND Base */
+                        reg-names = "fsmc_regs", "nand_data";
+                        st,ale-off = <0x20000>;
+                        st,cle-off = <0x10000>;
+                        status = "disabled";
+                };
+                sdhci@70000000 {
+                        compatible = "st,sdhci-spear";
+                        reg = <0x70000000 0x100>;
+                        interrupts = <1>;
+                        status = "disabled";
+                };
+                apb {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "simple-bus";
+                        ranges = <0xa0000000 0xa0000000 0x10000000
+                                  0xd0000000 0xd0000000 0x30000000>;
+                        gpio1: gpio@a9000000 {
+                                #gpio-cells = <2>;
+                                compatible = "arm,pl061", "arm,primecell";
+                                gpio-controller;
+                                reg = <0xa9000000 0x1000>;
+                                status = "disabled";
+                        };
+                        kbd@a0000000 {
+                                compatible = "st,spear300-kbd";
+                                reg = <0xa0000000 0x1000>;
+                                status = "disabled";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/spear310-evb.dts b/arch/arm/boot/dts/spear310-evb.dts
new file mode 100644
index 000000000000..6d95317100ad
--- /dev/null
+++ b/arch/arm/boot/dts/spear310-evb.dts
@@ -0,0 +1,172 @@
+/*
+ * DTS file for SPEAr310 Evaluation Baord
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/dts-v1/;
+/include/ "spear310.dtsi"
+/ {
+        model = "ST SPEAr310 Evaluation Board";
+        compatible = "st,spear310-evb", "st,spear310";
+        #address-cells = <1>;
+        #size-cells = <1>;
+        memory {
+                reg = <0 0x40000000>;
+        };
+        ahb {
+                pinmux@b4000000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&state_default>;
+                        state_default: pinmux {
+                                gpio0 {
+                                        st,pins = "gpio0_pin0_grp",
+                                                "gpio0_pin1_grp",
+                                                "gpio0_pin2_grp",
+                                                "gpio0_pin3_grp",
+                                                "gpio0_pin4_grp",
+                                                "gpio0_pin5_grp";
+                                        st,function = "gpio0";
+                                };
+                                i2c0 {
+                                        st,pins = "i2c0_grp";
+                                        st,function = "i2c0";
+                                };
+                                mii0 {
+                                        st,pins = "mii0_grp";
+                                        st,function = "mii0";
+                                };
+                                ssp0 {
+                                        st,pins = "ssp0_grp";
+                                        st,function = "ssp0";
+                                };
+                                uart0 {
+                                        st,pins = "uart0_grp";
+                                        st,function = "uart0";
+                                };
+                                emi {
+                                        st,pins = "emi_cs_0_to_5_grp";
+                                        st,function = "emi";
+                                };
+                                fsmc {
+                                        st,pins = "fsmc_grp";
+                                        st,function = "fsmc";
+                                };
+                                uart1 {
+                                        st,pins = "uart1_grp";
+                                        st,function = "uart1";
+                                };
+                                uart2 {
+                                        st,pins = "uart2_grp";
+                                        st,function = "uart2";
+                                };
+                                uart3 {
+                                        st,pins = "uart3_grp";
+                                        st,function = "uart3";
+                                };
+                                uart4 {
+                                        st,pins = "uart4_grp";
+                                        st,function = "uart4";
+                                };
+                                uart5 {
+                                        st,pins = "uart5_grp";
+                                        st,function = "uart5";
+                                };
+                        };
+                };
+                dma@fc400000 {
+                        status = "okay";
+                };
+                fsmc: flash@44000000 {
+                        status = "okay";
+                };
+                gmac: eth@e0800000 {
+                        status = "okay";
+                };
+                smi: flash@fc000000 {
+                        status = "okay";
+                        clock-rate=<50000000>;
+                        flash@f8000000 {
+                                label = "m25p64";
+                                reg = <0xf8000000 0x800000>;
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                st,smi-fast-mode;
+                        };
+                };
+                spi0: spi@d0100000 {
+                        status = "okay";
+                };
+                ehci@e1800000 {
+                        status = "okay";
+                };
+                ohci@e1900000 {
+                        status = "okay";
+                };
+                ohci@e2100000 {
+                        status = "okay";
+                };
+                apb {
+                        gpio0: gpio@fc980000 {
+                               status = "okay";
+                        };
+                        i2c0: i2c@d0180000 {
+                               status = "okay";
+                        };
+                        rtc@fc900000 {
+                               status = "okay";
+                        };
+                        serial@d0000000 {
+                               status = "okay";
+                        };
+                        serial@b2000000 {
+                               status = "okay";
+                        };
+                        serial@b2080000 {
+                               status = "okay";
+                        };
+                        serial@b2100000 {
+                               status = "okay";
+                        };
+                        serial@b2180000 {
+                               status = "okay";
+                        };
+                        serial@b2200000 {
+                               status = "okay";
+                        };
+                        wdt@fc880000 {
+                               status = "okay";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/spear310.dtsi b/arch/arm/boot/dts/spear310.dtsi
new file mode 100644
index 000000000000..e47081c494d9
--- /dev/null
+++ b/arch/arm/boot/dts/spear310.dtsi
@@ -0,0 +1,80 @@
+/*
+ * DTS file for SPEAr310 SoC
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/include/ "spear3xx.dtsi"
+/ {
+        ahb {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                ranges = <0x40000000 0x40000000 0x10000000
+                          0xb0000000 0xb0000000 0x10000000
+                          0xd0000000 0xd0000000 0x30000000>;
+                pinmux@b4000000 {
+                        compatible = "st,spear310-pinmux";
+                        reg = <0xb4000000 0x1000>;
+                };
+                fsmc: flash@44000000 {
+                        compatible = "st,spear600-fsmc-nand";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x44000000 0x1000        /* FSMC Register */
+                               0x40000000 0x0010>;      /* NAND Base */
+                        reg-names = "fsmc_regs", "nand_data";
+                        st,ale-off = <0x10000>;
+                        st,cle-off = <0x20000>;
+                        status = "disabled";
+                };
+                apb {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "simple-bus";
+                        ranges = <0xb0000000 0xb0000000 0x10000000
+                                  0xd0000000 0xd0000000 0x30000000>;
+                        serial@b2000000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0xb2000000 0x1000>;
+                                status = "disabled";
+                        };
+                        serial@b2080000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0xb2080000 0x1000>;
+                                status = "disabled";
+                        };
+                        serial@b2100000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0xb2100000 0x1000>;
+                                status = "disabled";
+                        };
+                        serial@b2180000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0xb2180000 0x1000>;
+                                status = "disabled";
+                        };
+                        serial@b2200000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0xb2200000 0x1000>;
+                                status = "disabled";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/spear320-evb.dts b/arch/arm/boot/dts/spear320-evb.dts
new file mode 100644
index 000000000000..0c6463b71a37
--- /dev/null
+++ b/arch/arm/boot/dts/spear320-evb.dts
@@ -0,0 +1,173 @@
+/*
+ * DTS file for SPEAr320 Evaluation Baord
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/dts-v1/;
+/include/ "spear320.dtsi"
+/ {
+        model = "ST SPEAr300 Evaluation Board";
+        compatible = "st,spear300-evb", "st,spear300";
+        #address-cells = <1>;
+        #size-cells = <1>;
+        memory {
+                reg = <0 0x40000000>;
+        };
+        ahb {
+                pinmux@b3000000 {
+                        st,pinmux-mode = <3>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&state_default>;
+                        state_default: pinmux {
+                                i2c0 {
+                                        st,pins = "i2c0_grp";
+                                        st,function = "i2c0";
+                                };
+                                mii0 {
+                                        st,pins = "mii0_grp";
+                                        st,function = "mii0";
+                                };
+                                ssp0 {
+                                        st,pins = "ssp0_grp";
+                                        st,function = "ssp0";
+                                };
+                                uart0 {
+                                        st,pins = "uart0_grp";
+                                        st,function = "uart0";
+                                };
+                                sdhci {
+                                        st,pins = "sdhci_cd_51_grp";
+                                        st,function = "sdhci";
+                                };
+                                i2s {
+                                        st,pins = "i2s_grp";
+                                        st,function = "i2s";
+                                };
+                                uart1 {
+                                        st,pins = "uart1_grp";
+                                        st,function = "uart1";
+                                };
+                                uart2 {
+                                        st,pins = "uart2_grp";
+                                        st,function = "uart2";
+                                };
+                                can0 {
+                                        st,pins = "can0_grp";
+                                        st,function = "can0";
+                                };
+                                can1 {
+                                        st,pins = "can1_grp";
+                                        st,function = "can1";
+                                };
+                                mii2 {
+                                        st,pins = "mii2_grp";
+                                        st,function = "mii2";
+                                };
+                                pwm0_1 {
+                                        st,pins = "pwm0_1_pin_14_15_grp";
+                                        st,function = "pwm0_1";
+                                };
+                                pwm2 {
+                                        st,pins = "pwm2_pin_13_grp";
+                                        st,function = "pwm2";
+                                };
+                        };
+                };
+                clcd@90000000 {
+                        status = "okay";
+                };
+                dma@fc400000 {
+                        status = "okay";
+                };
+                fsmc: flash@4c000000 {
+                        status = "okay";
+                };
+                gmac: eth@e0800000 {
+                        status = "okay";
+                };
+                sdhci@70000000 {
+                        power-gpio = <&gpio0 2 1>;
+                        power_always_enb;
+                        status = "okay";
+                };
+                smi: flash@fc000000 {
+                        status = "okay";
+                };
+                spi0: spi@d0100000 {
+                        status = "okay";
+                };
+                spi1: spi@a5000000 {
+                        status = "okay";
+                };
+                spi2: spi@a6000000 {
+                        status = "okay";
+                };
+                ehci@e1800000 {
+                        status = "okay";
+                };
+                ohci@e1900000 {
+                        status = "okay";
+                };
+                ohci@e2100000 {
+                        status = "okay";
+                };
+                apb {
+                        gpio0: gpio@fc980000 {
+                               status = "okay";
+                        };
+                        i2c0: i2c@d0180000 {
+                               status = "okay";
+                        };
+                        i2c1: i2c@a7000000 {
+                               status = "okay";
+                        };
+                        rtc@fc900000 {
+                               status = "okay";
+                        };
+                        serial@d0000000 {
+                               status = "okay";
+                        };
+                        serial@a3000000 {
+                               status = "okay";
+                        };
+                        serial@a4000000 {
+                               status = "okay";
+                        };
+                        wdt@fc880000 {
+                               status = "okay";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/spear320.dtsi b/arch/arm/boot/dts/spear320.dtsi
new file mode 100644
index 000000000000..5372ca399b1f
--- /dev/null
+++ b/arch/arm/boot/dts/spear320.dtsi
@@ -0,0 +1,95 @@
+/*
+ * DTS file for SPEAr320 SoC
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/include/ "spear3xx.dtsi"
+/ {
+        ahb {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                ranges = <0x40000000 0x40000000 0x80000000
+                          0xd0000000 0xd0000000 0x30000000>;
+                pinmux@b3000000 {
+                        compatible = "st,spear320-pinmux";
+                        reg = <0xb3000000 0x1000>;
+                };
+                clcd@90000000 {
+                        compatible = "arm,clcd-pl110", "arm,primecell";
+                        reg = <0x90000000 0x1000>;
+                        interrupts = <33>;
+                        status = "disabled";
+                };
+                fsmc: flash@4c000000 {
+                        compatible = "st,spear600-fsmc-nand";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x4c000000 0x1000        /* FSMC Register */
+                               0x50000000 0x0010>;      /* NAND Base */
+                        reg-names = "fsmc_regs", "nand_data";
+                        st,ale-off = <0x20000>;
+                        st,cle-off = <0x10000>;
+                        status = "disabled";
+                };
+                sdhci@70000000 {
+                        compatible = "st,sdhci-spear";
+                        reg = <0x70000000 0x100>;
+                        interrupts = <29>;
+                        status = "disabled";
+                };
+                spi1: spi@a5000000 {
+                        compatible = "arm,pl022", "arm,primecell";
+                        reg = <0xa5000000 0x1000>;
+                        status = "disabled";
+                };
+                spi2: spi@a6000000 {
+                        compatible = "arm,pl022", "arm,primecell";
+                        reg = <0xa6000000 0x1000>;
+                        status = "disabled";
+                };
+                apb {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "simple-bus";
+                        ranges = <0xa0000000 0xa0000000 0x10000000
+                                  0xd0000000 0xd0000000 0x30000000>;
+                        i2c1: i2c@a7000000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "snps,designware-i2c";
+                                reg = <0xa7000000 0x1000>;
+                                status = "disabled";
+                        };
+                        serial@a3000000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0xa3000000 0x1000>;
+                                status = "disabled";
+                        };
+                        serial@a4000000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0xa4000000 0x1000>;
+                                status = "disabled";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/spear3xx.dtsi b/arch/arm/boot/dts/spear3xx.dtsi
new file mode 100644
index 000000000000..0ae7c8e86311
--- /dev/null
+++ b/arch/arm/boot/dts/spear3xx.dtsi
@@ -0,0 +1,144 @@
+/*
+ * DTS file for all SPEAr3xx SoCs
+ *
+ * Copyright 2012 Viresh Kumar <viresh.kumar@st.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/include/ "skeleton.dtsi"
+/ {
+        interrupt-parent = <&vic>;
+        cpus {
+                cpu@0 {
+                        compatible = "arm,arm926ejs";
+                };
+        };
+        memory {
+                device_type = "memory";
+                reg = <0 0x40000000>;
+        };
+        ahb {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                ranges = <0xd0000000 0xd0000000 0x30000000>;
+                vic: interrupt-controller@f1100000 {
+                        compatible = "arm,pl190-vic";
+                        interrupt-controller;
+                        reg = <0xf1100000 0x1000>;
+                        #interrupt-cells = <1>;
+                };
+                dma@fc400000 {
+                        compatible = "arm,pl080", "arm,primecell";
+                        reg = <0xfc400000 0x1000>;
+                        interrupt-parent = <&vic>;
+                        interrupts = <8>;
+                        status = "disabled";
+                };
+                gmac: eth@e0800000 {
+                        compatible = "st,spear600-gmac";
+                        reg = <0xe0800000 0x8000>;
+                        interrupts = <23 22>;
+                        interrupt-names = "macirq", "eth_wake_irq";
+                        status = "disabled";
+                };
+                smi: flash@fc000000 {
+                        compatible = "st,spear600-smi";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0xfc000000 0x1000>;
+                        interrupts = <9>;
+                        status = "disabled";
+                };
+                spi0: spi@d0100000 {
+                        compatible = "arm,pl022", "arm,primecell";
+                        reg = <0xd0100000 0x1000>;
+                        interrupts = <20>;
+                        status = "disabled";
+                };
+                ehci@e1800000 {
+                        compatible = "st,spear600-ehci", "usb-ehci";
+                        reg = <0xe1800000 0x1000>;
+                        interrupts = <26>;
+                        status = "disabled";
+                };
+                ohci@e1900000 {
+                        compatible = "st,spear600-ohci", "usb-ohci";
+                        reg = <0xe1900000 0x1000>;
+                        interrupts = <25>;
+                        status = "disabled";
+                };
+                ohci@e2100000 {
+                        compatible = "st,spear600-ohci", "usb-ohci";
+                        reg = <0xe2100000 0x1000>;
+                        interrupts = <27>;
+                        status = "disabled";
+                };
+                apb {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "simple-bus";
+                        ranges = <0xd0000000 0xd0000000 0x30000000>;
+                        gpio0: gpio@fc980000 {
+                                compatible = "arm,pl061", "arm,primecell";
+                                reg = <0xfc980000 0x1000>;
+                                interrupts = <11>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                status = "disabled";
+                        };
+                        i2c0: i2c@d0180000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "snps,designware-i2c";
+                                reg = <0xd0180000 0x1000>;
+                                interrupts = <21>;
+                                status = "disabled";
+                        };
+                        rtc@fc900000 {
+                                compatible = "st,spear-rtc";
+                                reg = <0xfc900000 0x1000>;
+                                interrupts = <10>;
+                                status = "disabled";
+                        };
+                        serial@d0000000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0xd0000000 0x1000>;
+                                interrupts = <19>;
+                                status = "disabled";
+                        };
+                        wdt@fc880000 {
+                                compatible = "arm,sp805", "arm,primecell";
+                                reg = <0xfc880000 0x1000>;
+                                interrupts = <12>;
+                                status = "disabled";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/spear600-evb.dts b/arch/arm/boot/dts/spear600-evb.dts
index 636292e18c90..790a7a8a5ccd 100644
--- a/arch/arm/boot/dts/spear600-evb.dts
+++ b/arch/arm/boot/dts/spear600-evb.dts
@@ -24,6 +24,10 @@
        };
        ahb {
+                dma@fc400000 {
+                        status = "okay";
+                };
                gmac: ethernet@e0800000 {
                        phy-mode = "gmii";
                        status = "okay";
diff --git a/arch/arm/boot/dts/spear600.dtsi b/arch/arm/boot/dts/spear600.dtsi
index ebe0885a2b98..d777e3a6f178 100644
--- a/arch/arm/boot/dts/spear600.dtsi
+++ b/arch/arm/boot/dts/spear600.dtsi
@@ -45,6 +45,14 @@
                        #interrupt-cells = <1>;
                };
+                dma@fc400000 {
+                        compatible = "arm,pl080", "arm,primecell";
+                        reg = <0xfc400000 0x1000>;
+                        interrupt-parent = <&vic1>;
+                        interrupts = <10>;
+                        status = "disabled";
+                };
                gmac: ethernet@e0800000 {
                        compatible = "st,spear600-gmac";
                        reg = <0xe0800000 0x8000>;
diff --git a/arch/arm/boot/dts/tegra-cardhu.dts b/arch/arm/boot/dts/tegra-cardhu.dts
index ac3fb7558459..0a9f34a2c3aa 100644
--- a/arch/arm/boot/dts/tegra-cardhu.dts
+++ b/arch/arm/boot/dts/tegra-cardhu.dts
@@ -10,6 +10,50 @@
                reg = < 0x80000000 0x40000000 >;
        };
+        pinmux@70000000 {
+                pinctrl-names = "default";
+                pinctrl-0 = <&state_default>;
+                state_default: pinmux {
+                        sdmmc1_clk_pz0 {
+                                nvidia,pins = "sdmmc1_clk_pz0";
+                                nvidia,function = "sdmmc1";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <0>;
+                        };
+                        sdmmc1_cmd_pz1 {
+                                nvidia,pins =   "sdmmc1_cmd_pz1",
+                                                "sdmmc1_dat0_py7",
+                                                "sdmmc1_dat1_py6",
+                                                "sdmmc1_dat2_py5",
+                                                "sdmmc1_dat3_py4";
+                                nvidia,function = "sdmmc1";
+                                nvidia,pull = <2>;
+                                nvidia,tristate = <0>;
+                        };
+                        sdmmc4_clk_pcc4 {
+                                nvidia,pins =   "sdmmc4_clk_pcc4",
+                                                "sdmmc4_rst_n_pcc3";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <0>;
+                        };
+                        sdmmc4_dat0_paa0 {
+                                nvidia,pins =   "sdmmc4_dat0_paa0",
+                                                "sdmmc4_dat1_paa1",
+                                                "sdmmc4_dat2_paa2",
+                                                "sdmmc4_dat3_paa3",
+                                                "sdmmc4_dat4_paa4",
+                                                "sdmmc4_dat5_paa5",
+                                                "sdmmc4_dat6_paa6",
+                                                "sdmmc4_dat7_paa7";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <2>;
+                                nvidia,tristate = <0>;
+                        };
+                };
+        };
        serial@70006000 {
                clock-frequency = < 408000000 >;
        };
diff --git a/arch/arm/boot/dts/tegra-harmony.dts b/arch/arm/boot/dts/tegra-harmony.dts
index 6e8447dc0202..1a0b1f182944 100644
--- a/arch/arm/boot/dts/tegra-harmony.dts
+++ b/arch/arm/boot/dts/tegra-harmony.dts
@@ -10,6 +10,230 @@
                reg = < 0x00000000 0x40000000 >;
        };
+        pinmux@70000000 {
+                pinctrl-names = "default";
+                pinctrl-0 = <&state_default>;
+                state_default: pinmux {
+                        ata {
+                                nvidia,pins = "ata";
+                                nvidia,function = "ide";
+                        };
+                        atb {
+                                nvidia,pins = "atb", "gma", "gme";
+                                nvidia,function = "sdio4";
+                        };
+                        atc {
+                                nvidia,pins = "atc";
+                                nvidia,function = "nand";
+                        };
+                        atd {
+                                nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
+                                        "spia", "spib", "spic";
+                                nvidia,function = "gmi";
+                        };
+                        cdev1 {
+                                nvidia,pins = "cdev1";
+                                nvidia,function = "plla_out";
+                        };
+                        cdev2 {
+                                nvidia,pins = "cdev2";
+                                nvidia,function = "pllp_out4";
+                        };
+                        crtp {
+                                nvidia,pins = "crtp";
+                                nvidia,function = "crt";
+                        };
+                        csus {
+                                nvidia,pins = "csus";
+                                nvidia,function = "vi_sensor_clk";
+                        };
+                        dap1 {
+                                nvidia,pins = "dap1";
+                                nvidia,function = "dap1";
+                        };
+                        dap2 {
+                                nvidia,pins = "dap2";
+                                nvidia,function = "dap2";
+                        };
+                        dap3 {
+                                nvidia,pins = "dap3";
+                                nvidia,function = "dap3";
+                        };
+                        dap4 {
+                                nvidia,pins = "dap4";
+                                nvidia,function = "dap4";
+                        };
+                        ddc {
+                                nvidia,pins = "ddc";
+                                nvidia,function = "i2c2";
+                        };
+                        dta {
+                                nvidia,pins = "dta", "dtd";
+                                nvidia,function = "sdio2";
+                        };
+                        dtb {
+                                nvidia,pins = "dtb", "dtc", "dte";
+                                nvidia,function = "rsvd1";
+                        };
+                        dtf {
+                                nvidia,pins = "dtf";
+                                nvidia,function = "i2c3";
+                        };
+                        gmc {
+                                nvidia,pins = "gmc";
+                                nvidia,function = "uartd";
+                        };
+                        gpu7 {
+                                nvidia,pins = "gpu7";
+                                nvidia,function = "rtck";
+                        };
+                        gpv {
+                                nvidia,pins = "gpv", "slxa", "slxk";
+                                nvidia,function = "pcie";
+                        };
+                        hdint {
+                                nvidia,pins = "hdint", "pta";
+                                nvidia,function = "hdmi";
+                        };
+                        i2cp {
+                                nvidia,pins = "i2cp";
+                                nvidia,function = "i2cp";
+                        };
+                        irrx {
+                                nvidia,pins = "irrx", "irtx";
+                                nvidia,function = "uarta";
+                        };
+                        kbca {
+                                nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
+                                        "kbce", "kbcf";
+                                nvidia,function = "kbc";
+                        };
+                        lcsn {
+                                nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
+                                        "ld3", "ld4", "ld5", "ld6", "ld7",
+                                        "ld8", "ld9", "ld10", "ld11", "ld12",
+                                        "ld13", "ld14", "ld15", "ld16", "ld17",
+                                        "ldc", "ldi", "lhp0", "lhp1", "lhp2",
+                                        "lhs", "lm0", "lm1", "lpp", "lpw0",
+                                        "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
+                                        "lsda", "lsdi", "lspi", "lvp0", "lvp1",
+                                        "lvs";
+                                nvidia,function = "displaya";
+                        };
+                        owc {
+                                nvidia,pins = "owc", "spdi", "spdo", "uac";
+                                nvidia,function = "rsvd2";
+                        };
+                        pmc {
+                                nvidia,pins = "pmc";
+                                nvidia,function = "pwr_on";
+                        };
+                        rm {
+                                nvidia,pins = "rm";
+                                nvidia,function = "i2c1";
+                        };
+                        sdb {
+                                nvidia,pins = "sdb", "sdc", "sdd";
+                                nvidia,function = "pwm";
+                        };
+                        sdio1 {
+                                nvidia,pins = "sdio1";
+                                nvidia,function = "sdio1";
+                        };
+                        slxc {
+                                nvidia,pins = "slxc", "slxd";
+                                nvidia,function = "spdif";
+                        };
+                        spid {
+                                nvidia,pins = "spid", "spie", "spif";
+                                nvidia,function = "spi1";
+                        };
+                        spig {
+                                nvidia,pins = "spig", "spih";
+                                nvidia,function = "spi2_alt";
+                        };
+                        uaa {
+                                nvidia,pins = "uaa", "uab", "uda";
+                                nvidia,function = "ulpi";
+                        };
+                        uad {
+                                nvidia,pins = "uad";
+                                nvidia,function = "irda";
+                        };
+                        uca {
+                                nvidia,pins = "uca", "ucb";
+                                nvidia,function = "uartc";
+                        };
+                        conf_ata {
+                                nvidia,pins = "ata", "atb", "atc", "atd", "ate",
+                                        "cdev1", "dap1", "dtb", "gma", "gmb",
+                                        "gmc", "gmd", "gme", "gpu7", "gpv",
+                                        "i2cp", "pta", "rm", "slxa", "slxk",
+                                        "spia", "spib";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <0>;
+                        };
+                        conf_cdev2 {
+                                nvidia,pins = "cdev2", "csus", "spid", "spif";
+                                nvidia,pull = <1>;
+                                nvidia,tristate = <1>;
+                        };
+                        conf_ck32 {
+                                nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
+                                        "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
+                                nvidia,pull = <0>;
+                        };
+                        conf_crtp {
+                                nvidia,pins = "crtp", "dap2", "dap3", "dap4",
+                                        "dtc", "dte", "dtf", "gpu", "sdio1",
+                                        "slxc", "slxd", "spdi", "spdo", "spig",
+                                        "uac", "uda";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <1>;
+                        };
+                        conf_ddc {
+                                nvidia,pins = "ddc", "dta", "dtd", "kbca",
+                                        "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
+                                        "sdc";
+                                nvidia,pull = <2>;
+                                nvidia,tristate = <0>;
+                        };
+                        conf_hdint {
+                                nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
+                                        "lpw1", "lsc1", "lsck", "lsda", "lsdi",
+                                        "lvp0", "owc", "sdb";
+                                nvidia,tristate = <1>;
+                        };
+                        conf_irrx {
+                                nvidia,pins = "irrx", "irtx", "sdd", "spic",
+                                        "spie", "spih", "uaa", "uab", "uad",
+                                        "uca", "ucb";
+                                nvidia,pull = <2>;
+                                nvidia,tristate = <1>;
+                        };
+                        conf_lc {
+                                nvidia,pins = "lc", "ls";
+                                nvidia,pull = <2>;
+                        };
+                        conf_ld0 {
+                                nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
+                                        "ld5", "ld6", "ld7", "ld8", "ld9",
+                                        "ld10", "ld11", "ld12", "ld13", "ld14",
+                                        "ld15", "ld16", "ld17", "ldi", "lhp0",
+                                        "lhp1", "lhp2", "lhs", "lm0", "lpp",
+                                        "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
+                                        "lvs", "pmc";
+                                nvidia,tristate = <0>;
+                        };
+                        conf_ld17_0 {
+                                nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
+                                        "ld23_22";
+                                nvidia,pull = <1>;
+                        };
+                };
+        };
        pmc@7000f400 {
                nvidia,invert-interrupt;
        };
diff --git a/arch/arm/boot/dts/tegra-paz00.dts b/arch/arm/boot/dts/tegra-paz00.dts
index 6c02abb469d4..10943fb2561c 100644
--- a/arch/arm/boot/dts/tegra-paz00.dts
+++ b/arch/arm/boot/dts/tegra-paz00.dts
@@ -10,6 +10,226 @@
                reg = <0x00000000 0x20000000>;
        };
+        pinmux@70000000 {
+                pinctrl-names = "default";
+                pinctrl-0 = <&state_default>;
+                state_default: pinmux {
+                        ata {
+                                nvidia,pins = "ata", "atc", "atd", "ate",
+                                        "dap2", "gmb", "gmc", "gmd", "spia",
+                                        "spib", "spic", "spid", "spie";
+                                nvidia,function = "gmi";
+                        };
+                        atb {
+                                nvidia,pins = "atb", "gma", "gme";
+                                nvidia,function = "sdio4";
+                        };
+                        cdev1 {
+                                nvidia,pins = "cdev1";
+                                nvidia,function = "plla_out";
+                        };
+                        cdev2 {
+                                nvidia,pins = "cdev2";
+                                nvidia,function = "pllp_out4";
+                        };
+                        crtp {
+                                nvidia,pins = "crtp";
+                                nvidia,function = "crt";
+                        };
+                        csus {
+                                nvidia,pins = "csus";
+                                nvidia,function = "pllc_out1";
+                        };
+                        dap1 {
+                                nvidia,pins = "dap1";
+                                nvidia,function = "dap1";
+                        };
+                        dap3 {
+                                nvidia,pins = "dap3";
+                                nvidia,function = "dap3";
+                        };
+                        dap4 {
+                                nvidia,pins = "dap4";
+                                nvidia,function = "dap4";
+                        };
+                        ddc {
+                                nvidia,pins = "ddc";
+                                nvidia,function = "i2c2";
+                        };
+                        dta {
+                                nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
+                                nvidia,function = "rsvd1";
+                        };
+                        dtf {
+                                nvidia,pins = "dtf";
+                                nvidia,function = "i2c3";
+                        };
+                        gpu {
+                                nvidia,pins = "gpu", "sdb", "sdd";
+                                nvidia,function = "pwm";
+                        };
+                        gpu7 {
+                                nvidia,pins = "gpu7";
+                                nvidia,function = "rtck";
+                        };
+                        gpv {
+                                nvidia,pins = "gpv", "slxa", "slxk";
+                                nvidia,function = "pcie";
+                        };
+                        hdint {
+                                nvidia,pins = "hdint", "pta";
+                                nvidia,function = "hdmi";
+                        };
+                        i2cp {
+                                nvidia,pins = "i2cp";
+                                nvidia,function = "i2cp";
+                        };
+                        irrx {
+                                nvidia,pins = "irrx", "irtx";
+                                nvidia,function = "uarta";
+                        };
+                        kbca {
+                                nvidia,pins = "kbca", "kbcc", "kbce", "kbcf";
+                                nvidia,function = "kbc";
+                        };
+                        kbcb {
+                                nvidia,pins = "kbcb", "kbcd";
+                                nvidia,function = "sdio2";
+                        };
+                        lcsn {
+                                nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
+                                        "ld3", "ld4", "ld5", "ld6", "ld7",
+                                        "ld8", "ld9", "ld10", "ld11", "ld12",
+                                        "ld13", "ld14", "ld15", "ld16", "ld17",
+                                        "ldc", "ldi", "lhp0", "lhp1", "lhp2",
+                                        "lhs", "lm0", "lm1", "lpp", "lpw0",
+                                        "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
+                                        "lsda", "lsdi", "lspi", "lvp0", "lvp1",
+                                        "lvs";
+                                nvidia,function = "displaya";
+                        };
+                        owc {
+                                nvidia,pins = "owc";
+                                nvidia,function = "owr";
+                        };
+                        pmc {
+                                nvidia,pins = "pmc";
+                                nvidia,function = "pwr_on";
+                        };
+                        rm {
+                                nvidia,pins = "rm";
+                                nvidia,function = "i2c1";
+                        };
+                        sdc {
+                                nvidia,pins = "sdc";
+                                nvidia,function = "twc";
+                        };
+                        sdio1 {
+                                nvidia,pins = "sdio1";
+                                nvidia,function = "sdio1";
+                        };
+                        slxc {
+                                nvidia,pins = "slxc", "slxd";
+                                nvidia,function = "spi4";
+                        };
+                        spdi {
+                                nvidia,pins = "spdi", "spdo";
+                                nvidia,function = "rsvd2";
+                        };
+                        spif {
+                                nvidia,pins = "spif", "uac";
+                                nvidia,function = "rsvd4";
+                        };
+                        spig {
+                                nvidia,pins = "spig", "spih";
+                                nvidia,function = "spi2_alt";
+                        };
+                        uaa {
+                                nvidia,pins = "uaa", "uab", "uda";
+                                nvidia,function = "ulpi";
+                        };
+                        uad {
+                                nvidia,pins = "uad";
+                                nvidia,function = "spdif";
+                        };
+                        uca {
+                                nvidia,pins = "uca", "ucb";
+                                nvidia,function = "uartc";
+                        };
+                        conf_ata {
+                                nvidia,pins = "ata", "atb", "atc", "atd", "ate",
+                                        "cdev1", "dap1", "dap2", "dtf", "gma",
+                                        "gmb", "gmc", "gmd", "gme", "gpu",
+                                        "gpu7", "gpv", "i2cp", "pta", "rm",
+                                        "sdio1", "slxk", "spdo", "uac", "uda";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <0>;
+                        };
+                        conf_cdev2 {
+                                nvidia,pins = "cdev2";
+                                nvidia,pull = <1>;
+                                nvidia,tristate = <0>;
+                        };
+                        conf_ck32 {
+                                nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
+                                        "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
+                                nvidia,pull = <0>;
+                        };
+                        conf_crtp {
+                                nvidia,pins = "crtp", "dap3", "dap4", "dtb",
+                                        "dtc", "dte", "slxa", "slxc", "slxd",
+                                        "spdi";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <1>;
+                        };
+                        conf_csus {
+                                nvidia,pins = "csus", "spia", "spib", "spid",
+                                        "spif";
+                                nvidia,pull = <1>;
+                                nvidia,tristate = <1>;
+                        };
+                        conf_ddc {
+                                nvidia,pins = "ddc", "irrx", "irtx", "kbca",
+                                        "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
+                                        "spic", "spig", "uaa", "uab";
+                                nvidia,pull = <2>;
+                                nvidia,tristate = <0>;
+                        };
+                        conf_dta {
+                                nvidia,pins = "dta", "dtd", "owc", "sdc", "sdd",
+                                        "spie", "spih", "uad", "uca", "ucb";
+                                nvidia,pull = <2>;
+                                nvidia,tristate = <1>;
+                        };
+                        conf_hdint {
+                                nvidia,pins = "hdint", "ld0", "ld1", "ld2",
+                                        "ld3", "ld4", "ld5", "ld6", "ld7",
+                                        "ld8", "ld9", "ld10", "ld11", "ld12",
+                                        "ld13", "ld14", "ld15", "ld16", "ld17",
+                                        "ldc", "ldi", "lhs", "lsc0", "lspi",
+                                        "lvs", "pmc";
+                                nvidia,tristate = <0>;
+                        };
+                        conf_lc {
+                                nvidia,pins = "lc", "ls";
+                                nvidia,pull = <2>;
+                        };
+                        conf_lcsn {
+                                nvidia,pins = "lcsn", "lhp0", "lhp1", "lhp2",
+                                        "lm0", "lm1", "lpp", "lpw0", "lpw1",
+                                        "lpw2", "lsc1", "lsck", "lsda", "lsdi",
+                                        "lvp0", "lvp1", "sdb";
+                                nvidia,tristate = <1>;
+                        };
+                        conf_ld17_0 {
+                                nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
+                                        "ld23_22";
+                                nvidia,pull = <1>;
+                        };
+                };
+        };
        i2c@7000c000 {
                clock-frequency = <400000>;
diff --git a/arch/arm/boot/dts/tegra-seaboard.dts b/arch/arm/boot/dts/tegra-seaboard.dts
index dbf1c5a171c2..ec33116f5df9 100644
--- a/arch/arm/boot/dts/tegra-seaboard.dts
+++ b/arch/arm/boot/dts/tegra-seaboard.dts
@@ -11,6 +11,249 @@
                reg = < 0x00000000 0x40000000 >;
        };
+        pinmux@70000000 {
+                pinctrl-names = "default";
+                pinctrl-0 = <&state_default>;
+                state_default: pinmux {
+                        ata {
+                                nvidia,pins = "ata";
+                                nvidia,function = "ide";
+                        };
+                        atb {
+                                nvidia,pins = "atb", "gma", "gme";
+                                nvidia,function = "sdio4";
+                        };
+                        atc {
+                                nvidia,pins = "atc";
+                                nvidia,function = "nand";
+                        };
+                        atd {
+                                nvidia,pins = "atd", "ate", "gmb", "spia",
+                                        "spib", "spic";
+                                nvidia,function = "gmi";
+                        };
+                        cdev1 {
+                                nvidia,pins = "cdev1";
+                                nvidia,function = "plla_out";
+                        };
+                        cdev2 {
+                                nvidia,pins = "cdev2";
+                                nvidia,function = "pllp_out4";
+                        };
+                        crtp {
+                                nvidia,pins = "crtp", "lm1";
+                                nvidia,function = "crt";
+                        };
+                        csus {
+                                nvidia,pins = "csus";
+                                nvidia,function = "vi_sensor_clk";
+                        };
+                        dap1 {
+                                nvidia,pins = "dap1";
+                                nvidia,function = "dap1";
+                        };
+                        dap2 {
+                                nvidia,pins = "dap2";
+                                nvidia,function = "dap2";
+                        };
+                        dap3 {
+                                nvidia,pins = "dap3";
+                                nvidia,function = "dap3";
+                        };
+                        dap4 {
+                                nvidia,pins = "dap4";
+                                nvidia,function = "dap4";
+                        };
+                        ddc {
+                                nvidia,pins = "ddc", "owc", "spdi", "spdo",
+                                        "uac";
+                                nvidia,function = "rsvd2";
+                        };
+                        dta {
+                                nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
+                                nvidia,function = "vi";
+                        };
+                        dtf {
+                                nvidia,pins = "dtf";
+                                nvidia,function = "i2c3";
+                        };
+                        gmc {
+                                nvidia,pins = "gmc";
+                                nvidia,function = "uartd";
+                        };
+                        gmd {
+                                nvidia,pins = "gmd";
+                                nvidia,function = "sflash";
+                        };
+                        gpu {
+                                nvidia,pins = "gpu";
+                                nvidia,function = "pwm";
+                        };
+                        gpu7 {
+                                nvidia,pins = "gpu7";
+                                nvidia,function = "rtck";
+                        };
+                        gpv {
+                                nvidia,pins = "gpv", "slxa", "slxk";
+                                nvidia,function = "pcie";
+                        };
+                        hdint {
+                                nvidia,pins = "hdint", "lpw0", "lpw2", "lsc1",
+                                        "lsck", "lsda", "pta";
+                                nvidia,function = "hdmi";
+                        };
+                        i2cp {
+                                nvidia,pins = "i2cp";
+                                nvidia,function = "i2cp";
+                        };
+                        irrx {
+                                nvidia,pins = "irrx", "irtx";
+                                nvidia,function = "uartb";
+                        };
+                        kbca {
+                                nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
+                                        "kbce", "kbcf";
+                                nvidia,function = "kbc";
+                        };
+                        lcsn {
+                                nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
+                                        "lsdi", "lvp0";
+                                nvidia,function = "rsvd4";
+                        };
+                        ld0 {
+                                nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
+                                        "ld5", "ld6", "ld7", "ld8", "ld9",
+                                        "ld10", "ld11", "ld12", "ld13", "ld14",
+                                        "ld15", "ld16", "ld17", "ldi", "lhp0",
+                                        "lhp1", "lhp2", "lhs", "lpp", "lsc0",
+                                        "lspi", "lvp1", "lvs";
+                                nvidia,function = "displaya";
+                        };
+                        pmc {
+                                nvidia,pins = "pmc";
+                                nvidia,function = "pwr_on";
+                        };
+                        rm {
+                                nvidia,pins = "rm";
+                                nvidia,function = "i2c1";
+                        };
+                        sdb {
+                                nvidia,pins = "sdb", "sdc", "sdd";
+                                nvidia,function = "sdio3";
+                        };
+                        sdio1 {
+                                nvidia,pins = "sdio1";
+                                nvidia,function = "sdio1";
+                        };
+                        slxc {
+                                nvidia,pins = "slxc", "slxd";
+                                nvidia,function = "spdif";
+                        };
+                        spid {
+                                nvidia,pins = "spid", "spie", "spif";
+                                nvidia,function = "spi1";
+                        };
+                        spig {
+                                nvidia,pins = "spig", "spih";
+                                nvidia,function = "spi2_alt";
+                        };
+                        uaa {
+                                nvidia,pins = "uaa", "uab", "uda";
+                                nvidia,function = "ulpi";
+                        };
+                        uad {
+                                nvidia,pins = "uad";
+                                nvidia,function = "irda";
+                        };
+                        uca {
+                                nvidia,pins = "uca", "ucb";
+                                nvidia,function = "uartc";
+                        };
+                        conf_ata {
+                                nvidia,pins = "ata", "atb", "atc", "atd",
+                                        "cdev1", "cdev2", "dap1", "dap2",
+                                        "dap4", "dtf", "gma", "gmc", "gmd",
+                                        "gme", "gpu", "gpu7", "i2cp", "irrx",
+                                        "irtx", "pta", "rm", "sdc", "sdd",
+                                        "slxd", "slxk", "spdi", "spdo", "uac",
+                                        "uad", "uca", "ucb", "uda";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <0>;
+                        };
+                        conf_ate {
+                                nvidia,pins = "ate", "csus", "dap3", "ddc",
+                                        "gpv", "owc", "slxc", "spib", "spid",
+                                        "spie";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <1>;
+                        };
+                        conf_ck32 {
+                                nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
+                                        "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
+                                nvidia,pull = <0>;
+                        };
+                        conf_crtp {
+                                nvidia,pins = "crtp", "gmb", "slxa", "spia",
+                                        "spig", "spih";
+                                nvidia,pull = <2>;
+                                nvidia,tristate = <1>;
+                        };
+                        conf_dta {
+                                nvidia,pins = "dta", "dtb", "dtc", "dtd";
+                                nvidia,pull = <1>;
+                                nvidia,tristate = <0>;
+                        };
+                        conf_dte {
+                                nvidia,pins = "dte", "spif";
+                                nvidia,pull = <1>;
+                                nvidia,tristate = <1>;
+                        };
+                        conf_hdint {
+                                nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
+                                        "lpw1", "lsc1", "lsck", "lsda", "lsdi",
+                                        "lvp0";
+                                nvidia,tristate = <1>;
+                        };
+                        conf_kbca {
+                                nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
+                                        "kbce", "kbcf", "sdio1", "spic", "uaa",
+                                        "uab";
+                                nvidia,pull = <2>;
+                                nvidia,tristate = <0>;
+                        };
+                        conf_lc {
+                                nvidia,pins = "lc", "ls";
+                                nvidia,pull = <2>;
+                        };
+                        conf_ld0 {
+                                nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
+                                        "ld5", "ld6", "ld7", "ld8", "ld9",
+                                        "ld10", "ld11", "ld12", "ld13", "ld14",
+                                        "ld15", "ld16", "ld17", "ldi", "lhp0",
+                                        "lhp1", "lhp2", "lhs", "lm0", "lpp",
+                                        "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
+                                        "lvs", "pmc", "sdb";
+                                nvidia,tristate = <0>;
+                        };
+                        conf_ld17_0 {
+                                nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
+                                        "ld23_22";
+                                nvidia,pull = <1>;
+                        };
+                        drive_sdio1 {
+                                nvidia,pins = "drive_sdio1";
+                                nvidia,high-speed-mode = <0>;
+                                nvidia,schmitt = <0>;
+                                nvidia,low-power-mode = <3>;
+                                nvidia,pull-down-strength = <31>;
+                                nvidia,pull-up-strength = <31>;
+                                nvidia,slew-rate-rising = <3>;
+                                nvidia,slew-rate-falling = <3>;
+                        };
+                };
+        };
        i2c@7000c000 {
                clock-frequency = <400000>;
diff --git a/arch/arm/boot/dts/tegra-trimslice.dts b/arch/arm/boot/dts/tegra-trimslice.dts
index 252476867b54..98efd5b0d7f9 100644
--- a/arch/arm/boot/dts/tegra-trimslice.dts
+++ b/arch/arm/boot/dts/tegra-trimslice.dts
@@ -10,6 +10,236 @@
                reg = < 0x00000000 0x40000000 >;
        };
+        pinmux@70000000 {
+                pinctrl-names = "default";
+                pinctrl-0 = <&state_default>;
+                state_default: pinmux {
+                        ata {
+                                nvidia,pins = "ata";
+                                nvidia,function = "ide";
+                        };
+                        atb {
+                                nvidia,pins = "atb", "gma";
+                                nvidia,function = "sdio4";
+                        };
+                        atc {
+                                nvidia,pins = "atc", "gmb";
+                                nvidia,function = "nand";
+                        };
+                        atd {
+                                nvidia,pins = "atd", "ate", "gme", "pta";
+                                nvidia,function = "gmi";
+                        };
+                        cdev1 {
+                                nvidia,pins = "cdev1";
+                                nvidia,function = "plla_out";
+                        };
+                        cdev2 {
+                                nvidia,pins = "cdev2";
+                                nvidia,function = "pllp_out4";
+                        };
+                        crtp {
+                                nvidia,pins = "crtp";
+                                nvidia,function = "crt";
+                        };
+                        csus {
+                                nvidia,pins = "csus";
+                                nvidia,function = "vi_sensor_clk";
+                        };
+                        dap1 {
+                                nvidia,pins = "dap1";
+                                nvidia,function = "dap1";
+                        };
+                        dap2 {
+                                nvidia,pins = "dap2";
+                                nvidia,function = "dap2";
+                        };
+                        dap3 {
+                                nvidia,pins = "dap3";
+                                nvidia,function = "dap3";
+                        };
+                        dap4 {
+                                nvidia,pins = "dap4";
+                                nvidia,function = "dap4";
+                        };
+                        ddc {
+                                nvidia,pins = "ddc";
+                                nvidia,function = "i2c2";
+                        };
+                        dta {
+                                nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
+                                nvidia,function = "vi";
+                        };
+                        dtf {
+                                nvidia,pins = "dtf";
+                                nvidia,function = "i2c3";
+                        };
+                        gmc {
+                                nvidia,pins = "gmc", "gmd";
+                                nvidia,function = "sflash";
+                        };
+                        gpu {
+                                nvidia,pins = "gpu";
+                                nvidia,function = "uarta";
+                        };
+                        gpu7 {
+                                nvidia,pins = "gpu7";
+                                nvidia,function = "rtck";
+                        };
+                        gpv {
+                                nvidia,pins = "gpv", "slxa", "slxk";
+                                nvidia,function = "pcie";
+                        };
+                        hdint {
+                                nvidia,pins = "hdint";
+                                nvidia,function = "hdmi";
+                        };
+                        i2cp {
+                                nvidia,pins = "i2cp";
+                                nvidia,function = "i2cp";
+                        };
+                        irrx {
+                                nvidia,pins = "irrx", "irtx";
+                                nvidia,function = "uartb";
+                        };
+                        kbca {
+                                nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
+                                        "kbce", "kbcf";
+                                nvidia,function = "kbc";
+                        };
+                        lcsn {
+                                nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
+                                        "ld3", "ld4", "ld5", "ld6", "ld7",
+                                        "ld8", "ld9", "ld10", "ld11", "ld12",
+                                        "ld13", "ld14", "ld15", "ld16", "ld17",
+                                        "ldc", "ldi", "lhp0", "lhp1", "lhp2",
+                                        "lhs", "lm0", "lm1", "lpp", "lpw0",
+                                        "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
+                                        "lsda", "lsdi", "lspi", "lvp0", "lvp1",
+                                        "lvs";
+                                nvidia,function = "displaya";
+                        };
+                        owc {
+                                nvidia,pins = "owc", "uac";
+                                nvidia,function = "rsvd2";
+                        };
+                        pmc {
+                                nvidia,pins = "pmc";
+                                nvidia,function = "pwr_on";
+                        };
+                        rm {
+                                nvidia,pins = "rm";
+                                nvidia,function = "i2c1";
+                        };
+                        sdb {
+                                nvidia,pins = "sdb", "sdc", "sdd";
+                                nvidia,function = "pwm";
+                        };
+                        sdio1 {
+                                nvidia,pins = "sdio1";
+                                nvidia,function = "sdio1";
+                        };
+                        slxc {
+                                nvidia,pins = "slxc", "slxd";
+                                nvidia,function = "sdio3";
+                        };
+                        spdi {
+                                nvidia,pins = "spdi", "spdo";
+                                nvidia,function = "spdif";
+                        };
+                        spia {
+                                nvidia,pins = "spia", "spib", "spic";
+                                nvidia,function = "spi2";
+                        };
+                        spid {
+                                nvidia,pins = "spid", "spie", "spif";
+                                nvidia,function = "spi1";
+                        };
+                        spig {
+                                nvidia,pins = "spig", "spih";
+                                nvidia,function = "spi2_alt";
+                        };
+                        uaa {
+                                nvidia,pins = "uaa", "uab", "uda";
+                                nvidia,function = "ulpi";
+                        };
+                        uad {
+                                nvidia,pins = "uad";
+                                nvidia,function = "irda";
+                        };
+                        uca {
+                                nvidia,pins = "uca", "ucb";
+                                nvidia,function = "uartc";
+                        };
+                        conf_ata {
+                                nvidia,pins = "ata", "atc", "atd", "ate",
+                                        "crtp", "dap2", "dap3", "dap4", "dta",
+                                        "dtb", "dtc", "dtd", "dte", "gmb",
+                                        "gme", "i2cp", "pta", "slxc", "slxd",
+                                        "spdi", "spdo", "uda";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <1>;
+                        };
+                        conf_atb {
+                                nvidia,pins = "atb", "cdev1", "dap1", "gma",
+                                        "gmc", "gmd", "gpu", "gpu7", "gpv",
+                                        "sdio1", "slxa", "slxk", "uac";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <0>;
+                        };
+                        conf_cdev2 {
+                                nvidia,pins = "cdev2", "csus", "spia", "spib",
+                                        "spid", "spif";
+                                nvidia,pull = <1>;
+                                nvidia,tristate = <1>;
+                        };
+                        conf_ck32 {
+                                nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
+                                        "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
+                                nvidia,pull = <0>;
+                        };
+                        conf_ddc {
+                                nvidia,pins = "ddc", "dtf", "rm", "sdc", "sdd";
+                                nvidia,pull = <2>;
+                                nvidia,tristate = <0>;
+                        };
+                        conf_hdint {
+                                nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
+                                        "lpw1", "lsc1", "lsck", "lsda", "lsdi",
+                                        "lvp0", "pmc";
+                                nvidia,tristate = <1>;
+                        };
+                        conf_irrx {
+                                nvidia,pins = "irrx", "irtx", "kbca", "kbcb",
+                                        "kbcc", "kbcd", "kbce", "kbcf", "owc",
+                                        "spic", "spie", "spig", "spih", "uaa",
+                                        "uab", "uad", "uca", "ucb";
+                                nvidia,pull = <2>;
+                                nvidia,tristate = <1>;
+                        };
+                        conf_lc {
+                                nvidia,pins = "lc", "ls";
+                                nvidia,pull = <2>;
+                        };
+                        conf_ld0 {
+                                nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
+                                        "ld5", "ld6", "ld7", "ld8", "ld9",
+                                        "ld10", "ld11", "ld12", "ld13", "ld14",
+                                        "ld15", "ld16", "ld17", "ldi", "lhp0",
+                                        "lhp1", "lhp2", "lhs", "lm0", "lpp",
+                                        "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
+                                        "lvs", "sdb";
+                                nvidia,tristate = <0>;
+                        };
+                        conf_ld17_0 {
+                                nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
+                                        "ld23_22";
+                                nvidia,pull = <1>;
+                        };
+                };
+        };
        i2c@7000c000 {
                clock-frequency = <400000>;
        };
diff --git a/arch/arm/boot/dts/tegra-ventana.dts b/arch/arm/boot/dts/tegra-ventana.dts
index 2dcff8728e90..71eb2e50a668 100644
--- a/arch/arm/boot/dts/tegra-ventana.dts
+++ b/arch/arm/boot/dts/tegra-ventana.dts
@@ -10,6 +10,236 @@
                reg = < 0x00000000 0x40000000 >;
        };
+        pinmux@70000000 {
+                pinctrl-names = "default";
+                pinctrl-0 = <&state_default>;
+                state_default: pinmux {
+                        ata {
+                                nvidia,pins = "ata";
+                                nvidia,function = "ide";
+                        };
+                        atb {
+                                nvidia,pins = "atb", "gma", "gme";
+                                nvidia,function = "sdio4";
+                        };
+                        atc {
+                                nvidia,pins = "atc";
+                                nvidia,function = "nand";
+                        };
+                        atd {
+                                nvidia,pins = "atd", "ate", "gmb", "spia",
+                                        "spib", "spic";
+                                nvidia,function = "gmi";
+                        };
+                        cdev1 {
+                                nvidia,pins = "cdev1";
+                                nvidia,function = "plla_out";
+                        };
+                        cdev2 {
+                                nvidia,pins = "cdev2";
+                                nvidia,function = "pllp_out4";
+                        };
+                        crtp {
+                                nvidia,pins = "crtp", "lm1";
+                                nvidia,function = "crt";
+                        };
+                        csus {
+                                nvidia,pins = "csus";
+                                nvidia,function = "vi_sensor_clk";
+                        };
+                        dap1 {
+                                nvidia,pins = "dap1";
+                                nvidia,function = "dap1";
+                        };
+                        dap2 {
+                                nvidia,pins = "dap2";
+                                nvidia,function = "dap2";
+                        };
+                        dap3 {
+                                nvidia,pins = "dap3";
+                                nvidia,function = "dap3";
+                        };
+                        dap4 {
+                                nvidia,pins = "dap4";
+                                nvidia,function = "dap4";
+                        };
+                        ddc {
+                                nvidia,pins = "ddc", "owc", "spdi", "spdo",
+                                        "uac";
+                                nvidia,function = "rsvd2";
+                        };
+                        dta {
+                                nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
+                                nvidia,function = "vi";
+                        };
+                        dtf {
+                                nvidia,pins = "dtf";
+                                nvidia,function = "i2c3";
+                        };
+                        gmc {
+                                nvidia,pins = "gmc";
+                                nvidia,function = "uartd";
+                        };
+                        gmd {
+                                nvidia,pins = "gmd";
+                                nvidia,function = "sflash";
+                        };
+                        gpu {
+                                nvidia,pins = "gpu";
+                                nvidia,function = "pwm";
+                        };
+                        gpu7 {
+                                nvidia,pins = "gpu7";
+                                nvidia,function = "rtck";
+                        };
+                        gpv {
+                                nvidia,pins = "gpv", "slxa", "slxk";
+                                nvidia,function = "pcie";
+                        };
+                        hdint {
+                                nvidia,pins = "hdint", "pta";
+                                nvidia,function = "hdmi";
+                        };
+                        i2cp {
+                                nvidia,pins = "i2cp";
+                                nvidia,function = "i2cp";
+                        };
+                        irrx {
+                                nvidia,pins = "irrx", "irtx";
+                                nvidia,function = "uartb";
+                        };
+                        kbca {
+                                nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
+                                        "kbce", "kbcf";
+                                nvidia,function = "kbc";
+                        };
+                        lcsn {
+                                nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
+                                        "lsdi", "lvp0";
+                                nvidia,function = "rsvd4";
+                        };
+                        ld0 {
+                                nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
+                                        "ld5", "ld6", "ld7", "ld8", "ld9",
+                                        "ld10", "ld11", "ld12", "ld13", "ld14",
+                                        "ld15", "ld16", "ld17", "ldi", "lhp0",
+                                        "lhp1", "lhp2", "lhs", "lpp", "lpw0",
+                                        "lpw2", "lsc0", "lsc1", "lsck", "lsda",
+                                        "lspi", "lvp1", "lvs";
+                                nvidia,function = "displaya";
+                        };
+                        pmc {
+                                nvidia,pins = "pmc";
+                                nvidia,function = "pwr_on";
+                        };
+                        rm {
+                                nvidia,pins = "rm";
+                                nvidia,function = "i2c1";
+                        };
+                        sdb {
+                                nvidia,pins = "sdb", "sdc", "sdd", "slxc";
+                                nvidia,function = "sdio3";
+                        };
+                        sdio1 {
+                                nvidia,pins = "sdio1";
+                                nvidia,function = "sdio1";
+                        };
+                        slxd {
+                                nvidia,pins = "slxd";
+                                nvidia,function = "spdif";
+                        };
+                        spid {
+                                nvidia,pins = "spid", "spie", "spif";
+                                nvidia,function = "spi1";
+                        };
+                        spig {
+                                nvidia,pins = "spig", "spih";
+                                nvidia,function = "spi2_alt";
+                        };
+                        uaa {
+                                nvidia,pins = "uaa", "uab", "uda";
+                                nvidia,function = "ulpi";
+                        };
+                        uad {
+                                nvidia,pins = "uad";
+                                nvidia,function = "irda";
+                        };
+                        uca {
+                                nvidia,pins = "uca", "ucb";
+                                nvidia,function = "uartc";
+                        };
+                        conf_ata {
+                                nvidia,pins = "ata", "atb", "atc", "atd",
+                                        "cdev1", "cdev2", "dap1", "dap2",
+                                        "dap4", "ddc", "dtf", "gma", "gmc",
+                                        "gme", "gpu", "gpu7", "i2cp", "irrx",
+                                        "irtx", "pta", "rm", "sdc", "sdd",
+                                        "slxc", "slxd", "slxk", "spdi", "spdo",
+                                        "uac", "uad", "uca", "ucb", "uda";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <0>;
+                        };
+                        conf_ate {
+                                nvidia,pins = "ate", "csus", "dap3", "gmd",
+                                        "gpv", "owc", "spia", "spib", "spic",
+                                        "spid", "spie", "spig";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <1>;
+                        };
+                        conf_ck32 {
+                                nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
+                                        "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
+                                nvidia,pull = <0>;
+                        };
+                        conf_crtp {
+                                nvidia,pins = "crtp", "gmb", "slxa", "spih";
+                                nvidia,pull = <2>;
+                                nvidia,tristate = <1>;
+                        };
+                        conf_dta {
+                                nvidia,pins = "dta", "dtb", "dtc", "dtd";
+                                nvidia,pull = <1>;
+                                nvidia,tristate = <0>;
+                        };
+                        conf_dte {
+                                nvidia,pins = "dte", "spif";
+                                nvidia,pull = <1>;
+                                nvidia,tristate = <1>;
+                        };
+                        conf_hdint {
+                                nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
+                                        "lpw1", "lsck", "lsda", "lsdi", "lvp0";
+                                nvidia,tristate = <1>;
+                        };
+                        conf_kbca {
+                                nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
+                                        "kbce", "kbcf", "sdio1", "uaa", "uab";
+                                nvidia,pull = <2>;
+                                nvidia,tristate = <0>;
+                        };
+                        conf_lc {
+                                nvidia,pins = "lc", "ls";
+                                nvidia,pull = <2>;
+                        };
+                        conf_ld0 {
+                                nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
+                                        "ld5", "ld6", "ld7", "ld8", "ld9",
+                                        "ld10", "ld11", "ld12", "ld13", "ld14",
+                                        "ld15", "ld16", "ld17", "ldi", "lhp0",
+                                        "lhp1", "lhp2", "lhs", "lm0", "lpp",
+                                        "lpw0", "lpw2", "lsc0", "lsc1", "lspi",
+                                        "lvp1", "lvs", "pmc", "sdb";
+                                nvidia,tristate = <0>;
+                        };
+                        conf_ld17_0 {
+                                nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
+                                        "ld23_22";
+                                nvidia,pull = <1>;
+                        };
+                };
+        };
        i2c@7000c000 {
                clock-frequency = <400000>;
diff --git a/arch/arm/boot/dts/tny_a9260.dts b/arch/arm/boot/dts/tny_a9260.dts
new file mode 100644
index 000000000000..367a16dcd5ef
--- /dev/null
+++ b/arch/arm/boot/dts/tny_a9260.dts
@@ -0,0 +1,15 @@
+/*
+ * tny_a9260.dts - Device Tree file for Caloa TNY A9260 board
+ *
+ * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Licensed under GPLv2.
+ */
+/dts-v1/;
+/include/ "at91sam9260.dtsi"
+/include/ "tny_a9260_common.dtsi"
+/ {
+        model = "Calao TNY A9260";
+        compatible = "calao,tny-a9260", "atmel,at91sam9260", "atmel,at91sam9";
+};
diff --git a/arch/arm/boot/dts/tny_a9260_common.dtsi b/arch/arm/boot/dts/tny_a9260_common.dtsi
new file mode 100644
index 000000000000..0e6d3de2e09e
--- /dev/null
+++ b/arch/arm/boot/dts/tny_a9260_common.dtsi
@@ -0,0 +1,83 @@
+/*
+ * tny_a9260_common.dtsi - Device Tree file for Caloa TNY A926x board
+ *
+ * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Licensed under GPLv2.
+ */
+/ {
+        chosen {
+                bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock6 rw rootfstype=ubifs";
+        };
+        memory {
+                reg = <0x20000000 0x4000000>;
+        };
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                main_clock: clock@0 {
+                        compatible = "atmel,osc", "fixed-clock";
+                        clock-frequency = <12000000>;
+                };
+        };
+        ahb {
+                apb {
+                        dbgu: serial@fffff200 {
+                                status = "okay";
+                        };
+                };
+                nand0: nand@40000000 {
+                        nand-bus-width = <8>;
+                        nand-ecc-mode = "soft";
+                        nand-on-flash-bbt;
+                        status = "okay";
+                        at91bootstrap@0 {
+                                label = "at91bootstrap";
+                                reg = <0x0 0x20000>;
+                        };
+                        barebox@20000 {
+                                label = "barebox";
+                                reg = <0x20000 0x40000>;
+                        };
+                        bareboxenv@60000 {
+                                label = "bareboxenv";
+                                reg = <0x60000 0x20000>;
+                        };
+                        bareboxenv2@80000 {
+                                label = "bareboxenv2";
+                                reg = <0x80000 0x20000>;
+                        };
+                        oftree@80000 {
+                                label = "oftree";
+                                reg = <0xa0000 0x20000>;
+                        };
+                        kernel@a0000 {
+                                label = "kernel";
+                                reg = <0xc0000 0x400000>;
+                        };
+                        rootfs@4a0000 {
+                                label = "rootfs";
+                                reg = <0x4c0000 0x7800000>;
+                        };
+                        data@7ca0000 {
+                                label = "data";
+                                reg = <0x7cc0000 0x8340000>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/tny_a9263.dts b/arch/arm/boot/dts/tny_a9263.dts
new file mode 100644
index 000000000000..dee9c571306b
--- /dev/null
+++ b/arch/arm/boot/dts/tny_a9263.dts
@@ -0,0 +1,97 @@
+/*
+ * usb_a9263.dts - Device Tree file for Caloa USB A9293 board
+ *
+ *  Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Licensed under GPLv2 only
+ */
+/dts-v1/;
+/include/ "at91sam9263.dtsi"
+/ {
+        model = "Calao TNY A9263";
+        compatible = "atmel,tny-a9263", "atmel,at91sam9263", "atmel,at91sam9";
+        chosen {
+                bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs";
+        };
+        memory {
+                reg = <0x20000000 0x4000000>;
+        };
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                main_clock: clock@0 {
+                        compatible = "atmel,osc", "fixed-clock";
+                        clock-frequency = <12000000>;
+                };
+        };
+        ahb {
+                apb {
+                        dbgu: serial@ffffee00 {
+                                status = "okay";
+                        };
+                        usb1: gadget@fff78000 {
+                                atmel,vbus-gpio = <&pioB 11 0>;
+                                status = "okay";
+                        };
+                };
+                nand0: nand@40000000 {
+                        nand-bus-width = <8>;
+                        nand-ecc-mode = "soft";
+                        nand-on-flash-bbt;
+                        status = "okay";
+                        at91bootstrap@0 {
+                                label = "at91bootstrap";
+                                reg = <0x0 0x20000>;
+                        };
+                        barebox@20000 {
+                                label = "barebox";
+                                reg = <0x20000 0x40000>;
+                        };
+                        bareboxenv@60000 {
+                                label = "bareboxenv";
+                                reg = <0x60000 0x20000>;
+                        };
+                        bareboxenv2@80000 {
+                                label = "bareboxenv2";
+                                reg = <0x80000 0x20000>;
+                        };
+                        oftree@80000 {
+                                label = "oftree";
+                                reg = <0xa0000 0x20000>;
+                        };
+                        kernel@a0000 {
+                                label = "kernel";
+                                reg = <0xc0000 0x400000>;
+                        };
+                        rootfs@4a0000 {
+                                label = "rootfs";
+                                reg = <0x4c0000 0x7800000>;
+                        };
+                        data@7ca0000 {
+                                label = "data";
+                                reg = <0x7cc0000 0x8340000>;
+                        };
+                };
+        };
+        i2c@0 {
+                status = "okay";
+        };
+};
diff --git a/arch/arm/boot/dts/tny_a9g20.dts b/arch/arm/boot/dts/tny_a9g20.dts
new file mode 100644
index 000000000000..e1ab64c72dba
--- /dev/null
+++ b/arch/arm/boot/dts/tny_a9g20.dts
@@ -0,0 +1,15 @@
+/*
+ * tny_a9g20.dts - Device Tree file for Caloa TNY A9G20 board
+ *
+ * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Licensed under GPLv2.
+ */
+/dts-v1/;
+/include/ "at91sam9g20.dtsi"
+/include/ "tny_a9260_common.dtsi"
+/ {
+        model = "Calao TNY A9G20";
+        compatible = "calao,tny-a9g20", "atmel,at91sam9g20", "atmel,at91sam9";
+};
diff --git a/arch/arm/boot/dts/twl4030.dtsi b/arch/arm/boot/dts/twl4030.dtsi
new file mode 100644
index 000000000000..22f4d1394ed3
--- /dev/null
+++ b/arch/arm/boot/dts/twl4030.dtsi
@@ -0,0 +1,47 @@
+/*
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/*
+ * Integrated Power Management Chip
+ */
+&twl {
+        compatible = "ti,twl4030";
+        interrupt-controller;
+        #interrupt-cells = <1>;
+        rtc {
+                compatible = "ti,twl4030-rtc";
+                interrupts = <11>;
+        };
+        vdac: regulator@0 {
+                compatible = "ti,twl4030-vdac";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <1800000>;
+        };
+        vpll2: regulator@1 {
+                compatible = "ti,twl4030-vpll2";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <1800000>;
+        };
+        vmmc1: regulator@2 {
+                compatible = "ti,twl4030-vmmc1";
+                regulator-min-microvolt = <1850000>;
+                regulator-max-microvolt = <3150000>;
+        };
+        twl_gpio: gpio {
+                compatible = "ti,twl4030-gpio";
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <1>;
+        };
+};
diff --git a/arch/arm/boot/dts/twl6030.dtsi b/arch/arm/boot/dts/twl6030.dtsi
new file mode 100644
index 000000000000..3b2f3510d7eb
--- /dev/null
+++ b/arch/arm/boot/dts/twl6030.dtsi
@@ -0,0 +1,86 @@
+/*
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/*
+ * Integrated Power Management Chip
+ * http://www.ti.com/lit/ds/symlink/twl6030.pdf
+ */
+&twl {
+        compatible = "ti,twl6030";
+        interrupt-controller;
+        #interrupt-cells = <1>;
+        rtc {
+                compatible = "ti,twl4030-rtc";
+                interrupts = <11>;
+        };
+        vaux1: regulator@0 {
+                compatible = "ti,twl6030-vaux1";
+                regulator-min-microvolt = <1000000>;
+                regulator-max-microvolt = <3000000>;
+        };
+        vaux2: regulator@1 {
+                compatible = "ti,twl6030-vaux2";
+                regulator-min-microvolt = <1200000>;
+                regulator-max-microvolt = <2800000>;
+        };
+        vaux3: regulator@2 {
+                compatible = "ti,twl6030-vaux3";
+                regulator-min-microvolt = <1000000>;
+                regulator-max-microvolt = <3000000>;
+        };
+        vmmc: regulator@3 {
+                compatible = "ti,twl6030-vmmc";
+                regulator-min-microvolt = <1200000>;
+                regulator-max-microvolt = <3000000>;
+        };
+        vpp: regulator@4 {
+                compatible = "ti,twl6030-vpp";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <2500000>;
+        };
+        vusim: regulator@5 {
+                compatible = "ti,twl6030-vusim";
+                regulator-min-microvolt = <1200000>;
+                regulator-max-microvolt = <2900000>;
+        };
+        vdac: regulator@6 {
+                compatible = "ti,twl6030-vdac";
+        };
+        vana: regulator@7 {
+                compatible = "ti,twl6030-vana";
+        };
+        vcxio: regulator@8 {
+                compatible = "ti,twl6030-vcxio";
+        };
+        vusb: regulator@9 {
+                compatible = "ti,twl6030-vusb";
+        };
+        v1v8: regulator@10 {
+                compatible = "ti,twl6030-v1v8";
+        };
+        v2v1: regulator@11 {
+                compatible = "ti,twl6030-v2v1";
+        };
+        clk32kg: regulator@12 {
+                compatible = "ti,twl6030-clk32kg";
+        };
+};
diff --git a/arch/arm/boot/dts/usb_a9260.dts b/arch/arm/boot/dts/usb_a9260.dts
new file mode 100644
index 000000000000..296216058c11
--- /dev/null
+++ b/arch/arm/boot/dts/usb_a9260.dts
@@ -0,0 +1,23 @@
+/*
+ * usb_a9260.dts - Device Tree file for Caloa USB A9260 board
+ *
+ *  Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+/dts-v1/;
+/include/ "at91sam9260.dtsi"
+/include/ "usb_a9260_common.dtsi"
+/ {
+        model = "Calao USB A9260";
+        compatible = "calao,usb-a9260", "atmel,at91sam9260", "atmel,at91sam9";
+        chosen {
+                bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs";
+        };
+        memory {
+                reg = <0x20000000 0x4000000>;
+        };
+};
diff --git a/arch/arm/boot/dts/usb_a9260_common.dtsi b/arch/arm/boot/dts/usb_a9260_common.dtsi
new file mode 100644
index 000000000000..e70d229baef5
--- /dev/null
+++ b/arch/arm/boot/dts/usb_a9260_common.dtsi
@@ -0,0 +1,117 @@
+/*
+ * usb_a926x.dts - Device Tree file for Caloa USB A926x board
+ *
+ *  Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+/ {
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                main_clock: clock@0 {
+                        compatible = "atmel,osc", "fixed-clock";
+                        clock-frequency = <12000000>;
+                };
+        };
+        ahb {
+                apb {
+                        dbgu: serial@fffff200 {
+                                status = "okay";
+                        };
+                        macb0: ethernet@fffc4000 {
+                                phy-mode = "rmii";
+                                status = "okay";
+                        };
+                        usb1: gadget@fffa4000 {
+                                atmel,vbus-gpio = <&pioC 5 0>;
+                                status = "okay";
+                        };
+                };
+                nand0: nand@40000000 {
+                        nand-bus-width = <8>;
+                        nand-ecc-mode = "soft";
+                        nand-on-flash-bbt;
+                        status = "okay";
+                        at91bootstrap@0 {
+                                label = "at91bootstrap";
+                                reg = <0x0 0x20000>;
+                        };
+                        barebox@20000 {
+                                label = "barebox";
+                                reg = <0x20000 0x40000>;
+                        };
+                        bareboxenv@60000 {
+                                label = "bareboxenv";
+                                reg = <0x60000 0x20000>;
+                        };
+                        bareboxenv2@80000 {
+                                label = "bareboxenv2";
+                                reg = <0x80000 0x20000>;
+                        };
+                        oftree@80000 {
+                                label = "oftree";
+                                reg = <0xa0000 0x20000>;
+                        };
+                        kernel@a0000 {
+                                label = "kernel";
+                                reg = <0xc0000 0x400000>;
+                        };
+                        rootfs@4a0000 {
+                                label = "rootfs";
+                                reg = <0x4c0000 0x7800000>;
+                        };
+                        data@7ca0000 {
+                                label = "data";
+                                reg = <0x7cc0000 0x8340000>;
+                        };
+                };
+                usb0: ohci@00500000 {
+                        num-ports = <2>;
+                        status = "okay";
+                };
+        };
+        leds {
+                compatible = "gpio-leds";
+                user_led {
+                        label = "user_led";
+                        gpios = <&pioB 21 1>;
+                        linux,default-trigger = "heartbeat";
+                };
+        };
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                user_pb {
+                        label = "user_pb";
+                        gpios = <&pioB 10 1>;
+                        linux,code = <28>;
+                        gpio-key,wakeup;
+                };
+        };
+        i2c@0 {
+                status = "okay";
+        };
+};
diff --git a/arch/arm/boot/dts/usb_a9263.dts b/arch/arm/boot/dts/usb_a9263.dts
new file mode 100644
index 000000000000..6fe05ccb6203
--- /dev/null
+++ b/arch/arm/boot/dts/usb_a9263.dts
@@ -0,0 +1,131 @@
+/*
+ * usb_a9263.dts - Device Tree file for Caloa USB A9293 board
+ *
+ *  Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Licensed under GPLv2 only
+ */
+/dts-v1/;
+/include/ "at91sam9263.dtsi"
+/ {
+        model = "Calao USB A9263";
+        compatible = "atmel,usb-a9263", "atmel,at91sam9263", "atmel,at91sam9";
+        chosen {
+                bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs";
+        };
+        memory {
+                reg = <0x20000000 0x4000000>;
+        };
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                main_clock: clock@0 {
+                        compatible = "atmel,osc", "fixed-clock";
+                        clock-frequency = <12000000>;
+                };
+        };
+        ahb {
+                apb {
+                        dbgu: serial@ffffee00 {
+                                status = "okay";
+                        };
+                        macb0: ethernet@fffbc000 {
+                                phy-mode = "rmii";
+                                status = "okay";
+                        };
+                        usb1: gadget@fff78000 {
+                                atmel,vbus-gpio = <&pioB 11 0>;
+                                status = "okay";
+                        };
+                };
+                nand0: nand@40000000 {
+                        nand-bus-width = <8>;
+                        nand-ecc-mode = "soft";
+                        nand-on-flash-bbt;
+                        status = "okay";
+                        at91bootstrap@0 {
+                                label = "at91bootstrap";
+                                reg = <0x0 0x20000>;
+                        };
+                        barebox@20000 {
+                                label = "barebox";
+                                reg = <0x20000 0x40000>;
+                        };
+                        bareboxenv@60000 {
+                                label = "bareboxenv";
+                                reg = <0x60000 0x20000>;
+                        };
+                        bareboxenv2@80000 {
+                                label = "bareboxenv2";
+                                reg = <0x80000 0x20000>;
+                        };
+                        oftree@80000 {
+                                label = "oftree";
+                                reg = <0xa0000 0x20000>;
+                        };
+                        kernel@a0000 {
+                                label = "kernel";
+                                reg = <0xc0000 0x400000>;
+                        };
+                        rootfs@4a0000 {
+                                label = "rootfs";
+                                reg = <0x4c0000 0x7800000>;
+                        };
+                        data@7ca0000 {
+                                label = "data";
+                                reg = <0x7cc0000 0x8340000>;
+                        };
+                };
+                usb0: ohci@00a00000 {
+                        num-ports = <2>;
+                        status = "okay";
+                };
+        };
+        leds {
+                compatible = "gpio-leds";
+                user_led {
+                        label = "user_led";
+                        gpios = <&pioB 21 0>;
+                        linux,default-trigger = "heartbeat";
+                };
+        };
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                user_pb {
+                        label = "user_pb";
+                        gpios = <&pioB 10 1>;
+                        linux,code = <28>;
+                        gpio-key,wakeup;
+                };
+        };
+        i2c@0 {
+                status = "okay";
+        };
+};
diff --git a/arch/arm/boot/dts/usb_a9g20.dts b/arch/arm/boot/dts/usb_a9g20.dts
index 7c2399c532e5..2dacb16ce4ae 100644
--- a/arch/arm/boot/dts/usb_a9g20.dts
+++ b/arch/arm/boot/dts/usb_a9g20.dts
@@ -7,6 +7,7 @@
 */
 /dts-v1/;
 /include/ "at91sam9g20.dtsi"
+/include/ "usb_a9260_common.dtsi"
 / {
        model = "Calao USB A9G20";
@@ -20,108 +21,7 @@
                reg = <0x20000000 0x4000000>;
        };
-        clocks {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                ranges;
-                main_clock: clock@0 {
-                        compatible = "atmel,osc", "fixed-clock";
-                        clock-frequency = <12000000>;
-                };
-        };
-        ahb {
-                apb {
-                        dbgu: serial@fffff200 {
-                                status = "okay";
-                        };
-                        macb0: ethernet@fffc4000 {
-                                phy-mode = "rmii";
-                                status = "okay";
-                        };
-                        usb1: gadget@fffa4000 {
-                                atmel,vbus-gpio = <&pioC 5 0>;
-                                status = "okay";
-                        };
-                };
-                nand0: nand@40000000 {
-                        nand-bus-width = <8>;
-                        nand-ecc-mode = "soft";
-                        nand-on-flash-bbt;
-                        status = "okay";
-                        at91bootstrap@0 {
-                                label = "at91bootstrap";
-                                reg = <0x0 0x20000>;
-                        };
-                        barebox@20000 {
-                                label = "barebox";
-                                reg = <0x20000 0x40000>;
-                        };
-                        bareboxenv@60000 {
-                                label = "bareboxenv";
-                                reg = <0x60000 0x20000>;
-                        };
-                        bareboxenv2@80000 {
-                                label = "bareboxenv2";
-                                reg = <0x80000 0x20000>;
-                        };
-                        kernel@a0000 {
-                                label = "kernel";
-                                reg = <0xa0000 0x400000>;
-                        };
-                        rootfs@4a0000 {
-                                label = "rootfs";
-                                reg = <0x4a0000 0x7800000>;
-                        };
-                        data@7ca0000 {
-                                label = "data";
-                                reg = <0x7ca0000 0x8360000>;
-                        };
-                };
-                usb0: ohci@00500000 {
-                        num-ports = <2>;
-                        status = "okay";
-                };
-        };
-        leds {
-                compatible = "gpio-leds";
-                user_led {
-                        label = "user_led";
-                        gpios = <&pioB 21 1>;
-                        linux,default-trigger = "heartbeat";
-                };
-        };
-        gpio_keys {
-                compatible = "gpio-keys";
-                #address-cells = <1>;
-                #size-cells = <0>;
-                user_pb {
-                        label = "user_pb";
-                        gpios = <&pioB 10 1>;
-                        linux,code = <28>;
-                        gpio-key,wakeup;
-                };
-        };
        i2c@0 {
-                status = "okay";
                rv3029c2@56 {
                        compatible = "rv3029c2";
                        reg = <0x56>;
diff --git a/arch/arm/boot/dts/versatile-ab.dts b/arch/arm/boot/dts/versatile-ab.dts
index 0b32925f2147..e2fe3195c0d1 100644
--- a/arch/arm/boot/dts/versatile-ab.dts
+++ b/arch/arm/boot/dts/versatile-ab.dts
@@ -173,7 +173,7 @@
                        mmc@5000 {
                                compatible = "arm,primecell";
                                reg = < 0x5000 0x1000>;
-                                interrupts = <22>;
+                                interrupts = <22 34>;
                        };
                        kmi@6000 {
                                compatible = "arm,pl050", "arm,primecell";
diff --git a/arch/arm/boot/dts/versatile-pb.dts b/arch/arm/boot/dts/versatile-pb.dts
index 166461073b78..7e8175269064 100644
--- a/arch/arm/boot/dts/versatile-pb.dts
+++ b/arch/arm/boot/dts/versatile-pb.dts
@@ -41,7 +41,7 @@
                        mmc@b000 {
                                compatible = "arm,primecell";
                                reg = <0xb000 0x1000>;
-                                interrupts = <23>;
+                                interrupts = <23 34>;
                        };
                };
        };
diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile
index 215816f1775f..e8a4e58f1b82 100644
--- a/arch/arm/common/Makefile
+++ b/arch/arm/common/Makefile
@@ -11,7 +11,5 @@ obj-$(CONFIG_DMABOUNCE)		+= dmabounce.o
 obj-$(CONFIG_SHARP_LOCOMO)      += locomo.o
 obj-$(CONFIG_SHARP_PARAM)       += sharpsl_param.o
 obj-$(CONFIG_SHARP_SCOOP)       += scoop.o
-obj-$(CONFIG_ARCH_IXP2000)      += uengine.o
-obj-$(CONFIG_ARCH_IXP23XX)      += uengine.o
 obj-$(CONFIG_PCI_HOST_ITE8152)  += it8152.o
 obj-$(CONFIG_ARM_TIMER_SP804)   += timer-sp.o
diff --git a/arch/arm/common/it8152.c b/arch/arm/common/it8152.c
index dcb13494ca0d..c4110d1b1f2d 100644
--- a/arch/arm/common/it8152.c
+++ b/arch/arm/common/it8152.c
@@ -222,7 +222,7 @@ static int it8152_pci_write_config(struct pci_bus *bus,
        return PCIBIOS_SUCCESSFUL;
 }
-static struct pci_ops it8152_ops = {
+struct pci_ops it8152_ops = {
        .read = it8152_pci_read_config,
        .write = it8152_pci_write_config,
 };
@@ -346,9 +346,4 @@ void pcibios_set_master(struct pci_dev *dev)
 }
-struct pci_bus * __init it8152_pci_scan_bus(int nr, struct pci_sys_data *sys)
-{
-        return pci_scan_root_bus(NULL, nr, &it8152_ops, sys, &sys->resources);
-}
 EXPORT_SYMBOL(dma_set_coherent_mask);
diff --git a/arch/arm/common/uengine.c b/arch/arm/common/uengine.c
deleted file mode 100644
index bef408f3d76c..000000000000
--- a/arch/arm/common/uengine.c
+++ /dev/null
@@ -1,507 +0,0 @@
-/*
- * Generic library functions for the microengines found on the Intel
- * IXP2000 series of network processors.
- *
- * Copyright (C) 2004, 2005 Lennert Buytenhek <buytenh@wantstofly.org>
- * Dedicated to Marija Kulikova.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as
- * published by the Free Software Foundation; either version 2.1 of the
- * License, or (at your option) any later version.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/slab.h>
-#include <linux/module.h>
-#include <linux/string.h>
-#include <linux/io.h>
-#include <mach/hardware.h>
-#include <asm/hardware/uengine.h>
-#if defined(CONFIG_ARCH_IXP2000)
-#define IXP_UENGINE_CSR_VIRT_BASE       IXP2000_UENGINE_CSR_VIRT_BASE
-#define IXP_PRODUCT_ID                  IXP2000_PRODUCT_ID
-#define IXP_MISC_CONTROL                IXP2000_MISC_CONTROL
-#define IXP_RESET1                      IXP2000_RESET1
-#else
-#if defined(CONFIG_ARCH_IXP23XX)
-#define IXP_UENGINE_CSR_VIRT_BASE       IXP23XX_UENGINE_CSR_VIRT_BASE
-#define IXP_PRODUCT_ID                  IXP23XX_PRODUCT_ID
-#define IXP_MISC_CONTROL                IXP23XX_MISC_CONTROL
-#define IXP_RESET1                      IXP23XX_RESET1
-#else
-#error unknown platform
-#endif
-#endif
-#define USTORE_ADDRESS                  0x000
-#define USTORE_DATA_LOWER               0x004
-#define USTORE_DATA_UPPER               0x008
-#define CTX_ENABLES                     0x018
-#define CC_ENABLE                       0x01c
-#define CSR_CTX_POINTER                 0x020
-#define INDIRECT_CTX_STS                0x040
-#define ACTIVE_CTX_STS                  0x044
-#define INDIRECT_CTX_SIG_EVENTS         0x048
-#define INDIRECT_CTX_WAKEUP_EVENTS      0x050
-#define NN_PUT                          0x080
-#define NN_GET                          0x084
-#define TIMESTAMP_LOW                   0x0c0
-#define TIMESTAMP_HIGH                  0x0c4
-#define T_INDEX_BYTE_INDEX              0x0f4
-#define LOCAL_CSR_STATUS                0x180
-u32 ixp2000_uengine_mask;
-static void *ixp2000_uengine_csr_area(int uengine)
-{
-        return ((void *)IXP_UENGINE_CSR_VIRT_BASE) + (uengine << 10);
-}
-/*
- * LOCAL_CSR_STATUS=1 after a read or write to a microengine's CSR
- * space means that the microengine we tried to access was also trying
- * to access its own CSR space on the same clock cycle as we did.  When
- * this happens, we lose the arbitration process by default, and the
- * read or write we tried to do was not actually performed, so we try
- * again until it succeeds.
- */
-u32 ixp2000_uengine_csr_read(int uengine, int offset)
-{
-        void *uebase;
-        u32 *local_csr_status;
-        u32 *reg;
-        u32 value;
-        uebase = ixp2000_uengine_csr_area(uengine);
-        local_csr_status = (u32 *)(uebase + LOCAL_CSR_STATUS);
-        reg = (u32 *)(uebase + offset);
-        do {
-                value = ixp2000_reg_read(reg);
-        } while (ixp2000_reg_read(local_csr_status) & 1);
-        return value;
-}
-EXPORT_SYMBOL(ixp2000_uengine_csr_read);
-void ixp2000_uengine_csr_write(int uengine, int offset, u32 value)
-{
-        void *uebase;
-        u32 *local_csr_status;
-        u32 *reg;
-        uebase = ixp2000_uengine_csr_area(uengine);
-        local_csr_status = (u32 *)(uebase + LOCAL_CSR_STATUS);
-        reg = (u32 *)(uebase + offset);
-        do {
-                ixp2000_reg_write(reg, value);
-        } while (ixp2000_reg_read(local_csr_status) & 1);
-}
-EXPORT_SYMBOL(ixp2000_uengine_csr_write);
-void ixp2000_uengine_reset(u32 uengine_mask)
-{
-        u32 value;
-        value = ixp2000_reg_read(IXP_RESET1) & ~ixp2000_uengine_mask;
-        uengine_mask &= ixp2000_uengine_mask;
-        ixp2000_reg_wrb(IXP_RESET1, value | uengine_mask);
-        ixp2000_reg_wrb(IXP_RESET1, value);
-}
-EXPORT_SYMBOL(ixp2000_uengine_reset);
-void ixp2000_uengine_set_mode(int uengine, u32 mode)
-{
-        /*
-         * CTL_STR_PAR_EN: unconditionally enable parity checking on
-         * control store.
-         */
-        mode |= 0x10000000;
-        ixp2000_uengine_csr_write(uengine, CTX_ENABLES, mode);
-        /*
-         * Enable updating of condition codes.
-         */
-        ixp2000_uengine_csr_write(uengine, CC_ENABLE, 0x00002000);
-        /*
-         * Initialise other per-microengine registers.
-         */
-        ixp2000_uengine_csr_write(uengine, NN_PUT, 0x00);
-        ixp2000_uengine_csr_write(uengine, NN_GET, 0x00);
-        ixp2000_uengine_csr_write(uengine, T_INDEX_BYTE_INDEX, 0);
-}
-EXPORT_SYMBOL(ixp2000_uengine_set_mode);
-static int make_even_parity(u32 x)
-{
-        return hweight32(x) & 1;
-}
-static void ustore_write(int uengine, u64 insn)
-{
-        /*
-         * Generate even parity for top and bottom 20 bits.
-         */
-        insn |= (u64)make_even_parity((insn >> 20) & 0x000fffff) << 41;
-        insn |= (u64)make_even_parity(insn & 0x000fffff) << 40;
-        /*
-         * Write to microstore.  The second write auto-increments
-         * the USTORE_ADDRESS index register.
-         */
-        ixp2000_uengine_csr_write(uengine, USTORE_DATA_LOWER, (u32)insn);
-        ixp2000_uengine_csr_write(uengine, USTORE_DATA_UPPER, (u32)(insn >> 32));
-}
-void ixp2000_uengine_load_microcode(int uengine, u8 *ucode, int insns)
-{
-        int i;
-        /*
-         * Start writing to microstore at address 0.
-         */
-        ixp2000_uengine_csr_write(uengine, USTORE_ADDRESS, 0x80000000);
-        for (i = 0; i < insns; i++) {
-                u64 insn;
-                insn = (((u64)ucode[0]) << 32) |
-                        (((u64)ucode[1]) << 24) |
-                        (((u64)ucode[2]) << 16) |
-                        (((u64)ucode[3]) << 8) |
-                        ((u64)ucode[4]);
-                ucode += 5;
-                ustore_write(uengine, insn);
-        }
-        /*
-         * Pad with a few NOPs at the end (to avoid the microengine
-         * aborting as it prefetches beyond the last instruction), unless
-         * we run off the end of the instruction store first, at which
-         * point the address register will wrap back to zero.
-         */
-        for (i = 0; i < 4; i++) {
-                u32 addr;
-                addr = ixp2000_uengine_csr_read(uengine, USTORE_ADDRESS);
-                if (addr == 0x80000000)
-                        break;
-                ustore_write(uengine, 0xf0000c0300ULL);
-        }
-        /*
-         * End programming.
-         */
-        ixp2000_uengine_csr_write(uengine, USTORE_ADDRESS, 0x00000000);
-}
-EXPORT_SYMBOL(ixp2000_uengine_load_microcode);
-void ixp2000_uengine_init_context(int uengine, int context, int pc)
-{
-        /*
-         * Select the right context for indirect access.
-         */
-        ixp2000_uengine_csr_write(uengine, CSR_CTX_POINTER, context);
-        /*
-         * Initialise signal masks to immediately go to Ready state.
-         */
-        ixp2000_uengine_csr_write(uengine, INDIRECT_CTX_SIG_EVENTS, 1);
-        ixp2000_uengine_csr_write(uengine, INDIRECT_CTX_WAKEUP_EVENTS, 1);
-        /*
-         * Set program counter.
-         */
-        ixp2000_uengine_csr_write(uengine, INDIRECT_CTX_STS, pc);
-}
-EXPORT_SYMBOL(ixp2000_uengine_init_context);
-void ixp2000_uengine_start_contexts(int uengine, u8 ctx_mask)
-{
-        u32 mask;
-        /*
-         * Enable the specified context to go to Executing state.
-         */
-        mask = ixp2000_uengine_csr_read(uengine, CTX_ENABLES);
-        mask |= ctx_mask << 8;
-        ixp2000_uengine_csr_write(uengine, CTX_ENABLES, mask);
-}
-EXPORT_SYMBOL(ixp2000_uengine_start_contexts);
-void ixp2000_uengine_stop_contexts(int uengine, u8 ctx_mask)
-{
-        u32 mask;
-        /*
-         * Disable the Ready->Executing transition.  Note that this
-         * does not stop the context until it voluntarily yields.
-         */
-        mask = ixp2000_uengine_csr_read(uengine, CTX_ENABLES);
-        mask &= ~(ctx_mask << 8);
-        ixp2000_uengine_csr_write(uengine, CTX_ENABLES, mask);
-}
-EXPORT_SYMBOL(ixp2000_uengine_stop_contexts);
-static int check_ixp_type(struct ixp2000_uengine_code *c)
-{
-        u32 product_id;
-        u32 rev;
-        product_id = ixp2000_reg_read(IXP_PRODUCT_ID);
-        if (((product_id >> 16) & 0x1f) != 0)
-                return 0;
-        switch ((product_id >> 8) & 0xff) {
-#ifdef CONFIG_ARCH_IXP2000
-        case 0:         /* IXP2800 */
-                if (!(c->cpu_model_bitmask & 4))
-                        return 0;
-                break;
-        case 1:         /* IXP2850 */
-                if (!(c->cpu_model_bitmask & 8))
-                        return 0;
-                break;
-        case 2:         /* IXP2400 */
-                if (!(c->cpu_model_bitmask & 2))
-                        return 0;
-                break;
-#endif
-#ifdef CONFIG_ARCH_IXP23XX
-        case 4:         /* IXP23xx */
-                if (!(c->cpu_model_bitmask & 0x3f0))
-                        return 0;
-                break;
-#endif
-        default:
-                return 0;
-        }
-        rev = product_id & 0xff;
-        if (rev < c->cpu_min_revision || rev > c->cpu_max_revision)
-                return 0;
-        return 1;
-}
-static void generate_ucode(u8 *ucode, u32 *gpr_a, u32 *gpr_b)
-{
-        int offset;
-        int i;
-        offset = 0;
-        for (i = 0; i < 128; i++) {
-                u8 b3;
-                u8 b2;
-                u8 b1;
-                u8 b0;
-                b3 = (gpr_a[i] >> 24) & 0xff;
-                b2 = (gpr_a[i] >> 16) & 0xff;
-                b1 = (gpr_a[i] >> 8) & 0xff;
-                b0 = gpr_a[i] & 0xff;
-                /* immed[@ai, (b1 << 8) | b0] */
-                /* 11110000 0000VVVV VVVV11VV VVVVVV00 1IIIIIII */
-                ucode[offset++] = 0xf0;
-                ucode[offset++] = (b1 >> 4);
-                ucode[offset++] = (b1 << 4) | 0x0c | (b0 >> 6);
-                ucode[offset++] = (b0 << 2);
-                ucode[offset++] = 0x80 | i;
-                /* immed_w1[@ai, (b3 << 8) | b2] */
-                /* 11110100 0100VVVV VVVV11VV VVVVVV00 1IIIIIII */
-                ucode[offset++] = 0xf4;
-                ucode[offset++] = 0x40 | (b3 >> 4);
-                ucode[offset++] = (b3 << 4) | 0x0c | (b2 >> 6);
-                ucode[offset++] = (b2 << 2);
-                ucode[offset++] = 0x80 | i;
-        }
-        for (i = 0; i < 128; i++) {
-                u8 b3;
-                u8 b2;
-                u8 b1;
-                u8 b0;
-                b3 = (gpr_b[i] >> 24) & 0xff;
-                b2 = (gpr_b[i] >> 16) & 0xff;
-                b1 = (gpr_b[i] >> 8) & 0xff;
-                b0 = gpr_b[i] & 0xff;
-                /* immed[@bi, (b1 << 8) | b0] */
-                /* 11110000 0000VVVV VVVV001I IIIIII11 VVVVVVVV */
-                ucode[offset++] = 0xf0;
-                ucode[offset++] = (b1 >> 4);
-                ucode[offset++] = (b1 << 4) | 0x02 | (i >> 6);
-                ucode[offset++] = (i << 2) | 0x03;
-                ucode[offset++] = b0;
-                /* immed_w1[@bi, (b3 << 8) | b2] */
-                /* 11110100 0100VVVV VVVV001I IIIIII11 VVVVVVVV */
-                ucode[offset++] = 0xf4;
-                ucode[offset++] = 0x40 | (b3 >> 4);
-                ucode[offset++] = (b3 << 4) | 0x02 | (i >> 6);
-                ucode[offset++] = (i << 2) | 0x03;
-                ucode[offset++] = b2;
-        }
-        /* ctx_arb[kill] */
-        ucode[offset++] = 0xe0;
-        ucode[offset++] = 0x00;
-        ucode[offset++] = 0x01;
-        ucode[offset++] = 0x00;
-        ucode[offset++] = 0x00;
-}
-static int set_initial_registers(int uengine, struct ixp2000_uengine_code *c)
-{
-        int per_ctx_regs;
-        u32 *gpr_a;
-        u32 *gpr_b;
-        u8 *ucode;
-        int i;
-        gpr_a = kzalloc(128 * sizeof(u32), GFP_KERNEL);
-        gpr_b = kzalloc(128 * sizeof(u32), GFP_KERNEL);
-        ucode = kmalloc(513 * 5, GFP_KERNEL);
-        if (gpr_a == NULL || gpr_b == NULL || ucode == NULL) {
-                kfree(ucode);
-                kfree(gpr_b);
-                kfree(gpr_a);
-                return 1;
-        }
-        per_ctx_regs = 16;
-        if (c->uengine_parameters & IXP2000_UENGINE_4_CONTEXTS)
-                per_ctx_regs = 32;
-        for (i = 0; i < 256; i++) {
-                struct ixp2000_reg_value *r = c->initial_reg_values + i;
-                u32 *bank;
-                int inc;
-                int j;
-                if (r->reg == -1)
-                        break;
-                bank = (r->reg & 0x400) ? gpr_b : gpr_a;
-                inc = (r->reg & 0x80) ? 128 : per_ctx_regs;
-                j = r->reg & 0x7f;
-                while (j < 128) {
-                        bank[j] = r->value;
-                        j += inc;
-                }
-        }
-        generate_ucode(ucode, gpr_a, gpr_b);
-        ixp2000_uengine_load_microcode(uengine, ucode, 513);
-        ixp2000_uengine_init_context(uengine, 0, 0);
-        ixp2000_uengine_start_contexts(uengine, 0x01);
-        for (i = 0; i < 100; i++) {
-                u32 status;
-                status = ixp2000_uengine_csr_read(uengine, ACTIVE_CTX_STS);
-                if (!(status & 0x80000000))
-                        break;
-        }
-        ixp2000_uengine_stop_contexts(uengine, 0x01);
-        kfree(ucode);
-        kfree(gpr_b);
-        kfree(gpr_a);
-        return !!(i == 100);
-}
-int ixp2000_uengine_load(int uengine, struct ixp2000_uengine_code *c)
-{
-        int ctx;
-        if (!check_ixp_type(c))
-                return 1;
-        if (!(ixp2000_uengine_mask & (1 << uengine)))
-                return 1;
-        ixp2000_uengine_reset(1 << uengine);
-        ixp2000_uengine_set_mode(uengine, c->uengine_parameters);
-        if (set_initial_registers(uengine, c))
-                return 1;
-        ixp2000_uengine_load_microcode(uengine, c->insns, c->num_insns);
-        for (ctx = 0; ctx < 8; ctx++)
-                ixp2000_uengine_init_context(uengine, ctx, 0);
-        return 0;
-}
-EXPORT_SYMBOL(ixp2000_uengine_load);
-static int __init ixp2000_uengine_init(void)
-{
-        int uengine;
-        u32 value;
-        /*
-         * Determine number of microengines present.
-         */
-        switch ((ixp2000_reg_read(IXP_PRODUCT_ID) >> 8) & 0x1fff) {
-#ifdef CONFIG_ARCH_IXP2000
-        case 0:         /* IXP2800 */
-        case 1:         /* IXP2850 */
-                ixp2000_uengine_mask = 0x00ff00ff;
-                break;
-        case 2:         /* IXP2400 */
-                ixp2000_uengine_mask = 0x000f000f;
-                break;
-#endif
-#ifdef CONFIG_ARCH_IXP23XX
-        case 4:         /* IXP23xx */
-                ixp2000_uengine_mask = (*IXP23XX_EXP_CFG_FUSE >> 8) & 0xf;
-                break;
-#endif
-        default:
-                printk(KERN_INFO "Detected unknown IXP2000 model (%.8x)\n",
-                        (unsigned int)ixp2000_reg_read(IXP_PRODUCT_ID));
-                ixp2000_uengine_mask = 0x00000000;
-                break;
-        }
-        /*
-         * Reset microengines.
-         */
-        ixp2000_uengine_reset(ixp2000_uengine_mask);
-        /*
-         * Synchronise timestamp counters across all microengines.
-         */
-        value = ixp2000_reg_read(IXP_MISC_CONTROL);
-        ixp2000_reg_wrb(IXP_MISC_CONTROL, value & ~0x80);
-        for (uengine = 0; uengine < 32; uengine++) {
-                if (ixp2000_uengine_mask & (1 << uengine)) {
-                        ixp2000_uengine_csr_write(uengine, TIMESTAMP_LOW, 0);
-                        ixp2000_uengine_csr_write(uengine, TIMESTAMP_HIGH, 0);
-                }
-        }
-        ixp2000_reg_wrb(IXP_MISC_CONTROL, value | 0x80);
-        return 0;
-}
-subsys_initcall(ixp2000_uengine_init);
diff --git a/arch/arm/common/via82c505.c b/arch/arm/common/via82c505.c
index 1171a5010aea..6cb362e56d29 100644
--- a/arch/arm/common/via82c505.c
+++ b/arch/arm/common/via82c505.c
@@ -51,7 +51,7 @@ via82c505_write_config(struct pci_bus *bus, unsigned int devfn, int where,
        return PCIBIOS_SUCCESSFUL;
 }
-static struct pci_ops via82c505_ops = {
+struct pci_ops via82c505_ops = {
        .read   = via82c505_read_config,
        .write  = via82c505_write_config,
 };
@@ -81,12 +81,3 @@ int __init via82c505_setup(int nr, struct pci_sys_data *sys)
 {
        return (nr == 0);
 }
-struct pci_bus * __init via82c505_scan_bus(int nr, struct pci_sys_data *sysdata)
-{
-        if (nr == 0)
-                return pci_scan_root_bus(NULL, 0, &via82c505_ops, sysdata,
-                                         &sysdata->resources);
-        return NULL;
-}
diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c
index 7a66311f3066..e0d538803cc3 100644
--- a/arch/arm/common/vic.c
+++ b/arch/arm/common/vic.c
@@ -39,6 +39,7 @@
 * struct vic_device - VIC PM device
 * @irq: The IRQ number for the base of the VIC.
 * @base: The register base for the VIC.
+ * @valid_sources: A bitmask of valid interrupts
 * @resume_sources: A bitmask of interrupts for resume.
 * @resume_irqs: The IRQs enabled for resume.
 * @int_select: Save for VIC_INT_SELECT.
@@ -50,6 +51,7 @@
 struct vic_device {
        void __iomem    *base;
        int             irq;
+        u32             valid_sources;
        u32             resume_sources;
        u32             resume_irqs;
        u32             int_select;
@@ -164,10 +166,32 @@ static int __init vic_pm_init(void)
 late_initcall(vic_pm_init);
 #endif /* CONFIG_PM */
+static struct irq_chip vic_chip;
+static int vic_irqdomain_map(struct irq_domain *d, unsigned int irq,
+                             irq_hw_number_t hwirq)
+{
+        struct vic_device *v = d->host_data;
+        /* Skip invalid IRQs, only register handlers for the real ones */
+        if (!(v->valid_sources & (1 << hwirq)))
+                return -ENOTSUPP;
+        irq_set_chip_and_handler(irq, &vic_chip, handle_level_irq);
+        irq_set_chip_data(irq, v->base);
+        set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+        return 0;
+}
+static struct irq_domain_ops vic_irqdomain_ops = {
+        .map = vic_irqdomain_map,
+        .xlate = irq_domain_xlate_onetwocell,
+};
 /**
 * vic_register() - Register a VIC.
 * @base: The base address of the VIC.
 * @irq: The base IRQ for the VIC.
+ * @valid_sources: bitmask of valid interrupts
 * @resume_sources: bitmask of interrupts allowed for resume sources.
 * @node: The device tree node associated with the VIC.
 *
@@ -178,7 +202,8 @@ late_initcall(vic_pm_init);
 * This also configures the IRQ domain for the VIC.
 */
 static void __init vic_register(void __iomem *base, unsigned int irq,
-                                u32 resume_sources, struct device_node *node)
+                                u32 valid_sources, u32 resume_sources,
+                                struct device_node *node)
 {
        struct vic_device *v;
@@ -189,11 +214,12 @@ static void __init vic_register(void __iomem *base, unsigned int irq,
        v = &vic_devices[vic_id];
        v->base = base;
+        v->valid_sources = valid_sources;
        v->resume_sources = resume_sources;
        v->irq = irq;
        vic_id++;
-        v->domain = irq_domain_add_legacy(node, 32, irq, 0,
+        v->domain = irq_domain_add_legacy(node, fls(valid_sources), irq, 0,
-                                          &irq_domain_simple_ops, v);
+                                          &vic_irqdomain_ops, v);
 }
 static void vic_ack_irq(struct irq_data *d)
@@ -287,23 +313,6 @@ static void __init vic_clear_interrupts(void __iomem *base)
        }
 }
-static void __init vic_set_irq_sources(void __iomem *base,
-                                unsigned int irq_start, u32 vic_sources)
-{
-        unsigned int i;
-        for (i = 0; i < 32; i++) {
-                if (vic_sources & (1 << i)) {
-                        unsigned int irq = irq_start + i;
-                        irq_set_chip_and_handler(irq, &vic_chip,
-                                                 handle_level_irq);
-                        irq_set_chip_data(irq, base);
-                        set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
-                }
-        }
-}
 /*
 * The PL190 cell from ARM has been modified by ST to handle 64 interrupts.
 * The original cell has 32 interrupts, while the modified one has 64,
@@ -338,8 +347,7 @@ static void __init vic_init_st(void __iomem *base, unsigned int irq_start,
                writel(32, base + VIC_PL190_DEF_VECT_ADDR);
        }
-        vic_set_irq_sources(base, irq_start, vic_sources);
+        vic_register(base, irq_start, vic_sources, 0, node);
-        vic_register(base, irq_start, 0, node);
 }
 void __init __vic_init(void __iomem *base, unsigned int irq_start,
@@ -379,9 +387,7 @@ void __init __vic_init(void __iomem *base, unsigned int irq_start,
        vic_init2(base);
-        vic_set_irq_sources(base, irq_start, vic_sources);
+        vic_register(base, irq_start, vic_sources, resume_sources, node);
-        vic_register(base, irq_start, resume_sources, node);
 }
 /**
@@ -427,19 +433,18 @@ int __init vic_of_init(struct device_node *node, struct device_node *parent)
 /*
 * Handle each interrupt in a single VIC.  Returns non-zero if we've
- * handled at least one interrupt.  This does a single read of the
+ * handled at least one interrupt.  This reads the status register
- * status register and handles all interrupts in order from LSB first.
+ * before handling each interrupt, which is necessary given that
+ * handle_IRQ may briefly re-enable interrupts for soft IRQ handling.
 */
 static int handle_one_vic(struct vic_device *vic, struct pt_regs *regs)
 {
        u32 stat, irq;
        int handled = 0;
-        stat = readl_relaxed(vic->base + VIC_IRQ_STATUS);
+        while ((stat = readl_relaxed(vic->base + VIC_IRQ_STATUS))) {
-        while (stat) {
                irq = ffs(stat) - 1;
                handle_IRQ(irq_find_mapping(vic->domain, irq), regs);
-                stat &= ~(1 << irq);
                handled = 1;
        }
diff --git a/arch/arm/configs/armadillo800eva_defconfig b/arch/arm/configs/armadillo800eva_defconfig
new file mode 100644
index 000000000000..ddc9fe6a78ac
--- /dev/null
+++ b/arch/arm/configs/armadillo800eva_defconfig
@@ -0,0 +1,142 @@
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=16
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_ARCH_SHMOBILE=y
+CONFIG_ARCH_R8A7740=y
+CONFIG_MACH_ARMADILLO800EVA=y
+# CONFIG_SH_TIMER_TMU is not set
+# CONFIG_ARM_THUMB is not set
+CONFIG_CPU_BPREDICT_DISABLE=y
+# CONFIG_CACHE_L2X0 is not set
+CONFIG_ARM_ERRATA_430973=y
+CONFIG_ARM_ERRATA_458693=y
+CONFIG_ARM_ERRATA_460075=y
+CONFIG_ARM_ERRATA_720789=y
+CONFIG_ARM_ERRATA_743622=y
+CONFIG_ARM_ERRATA_751472=y
+CONFIG_ARM_ERRATA_754322=y
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+CONFIG_FORCE_MAX_ZONEORDER=13
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="console=tty0 console=ttySC1,115200 earlyprintk=sh-sci.1,115200 ignore_loglevel root=/dev/nfs ip=dhcp nfsroot=,rsize=4096,wsize=4096"
+CONFIG_CMDLINE_FORCE=y
+CONFIG_KEXEC=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_SUSPEND is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_WIRELESS is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_MD=y
+CONFIG_BLK_DEV_DM=y
+CONFIG_NETDEVICES=y
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CHELSIO is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+CONFIG_SH_ETH=y
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_WLAN is not set
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_KEYBOARD_ATKBD is not set
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_ST1232=y
+# CONFIG_SERIO is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_SERIAL_SH_SCI=y
+CONFIG_SERIAL_SH_SCI_NR_UARTS=8
+CONFIG_SERIAL_SH_SCI_CONSOLE=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_I2C=y
+CONFIG_I2C_SH_MOBILE=y
+# CONFIG_HWMON is not set
+CONFIG_FB=y
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_SH_MOBILE_LCDC=y
+CONFIG_LCD_CLASS_DEVICE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+CONFIG_LOGO=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+CONFIG_SOUND=y
+CONFIG_SND=y
+# CONFIG_SND_SUPPORT_OLD_API is not set
+# CONFIG_SND_VERBOSE_PROCFS is not set
+# CONFIG_SND_DRIVERS is not set
+# CONFIG_SND_ARM is not set
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_SH4_FSI=y
+# CONFIG_HID_SUPPORT is not set
+CONFIG_USB=y
+# CONFIG_USB_DEVICE_CLASS is not set
+CONFIG_USB_RENESAS_USBHS=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_RENESAS_USBHS_UDC=y
+CONFIG_USB_ETH=m
+CONFIG_MMC=y
+CONFIG_MMC_SDHI=y
+CONFIG_MMC_SH_MMCIF=y
+CONFIG_UIO=y
+CONFIG_UIO_PDRV_GENIRQ=y
+# CONFIG_DNOTIFY is not set
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+# CONFIG_MISC_FILESYSTEMS is not set
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_NFS_V4_1=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+# CONFIG_ARM_UNWIND is not set
+CONFIG_CRYPTO=y
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_ANSI_CPRNG=y
+CONFIG_XZ_DEC=y
diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig
new file mode 100644
index 000000000000..67bc571ed0c3
--- /dev/null
+++ b/arch/arm/configs/at91_dt_defconfig
@@ -0,0 +1,196 @@
+CONFIG_EXPERIMENTAL=y
+# CONFIG_LOCALVERSION_AUTO is not set
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_LBDAF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_ARCH_AT91=y
+CONFIG_SOC_AT91SAM9260=y
+CONFIG_SOC_AT91SAM9263=y
+CONFIG_SOC_AT91SAM9G45=y
+CONFIG_SOC_AT91SAM9X5=y
+CONFIG_MACH_AT91SAM_DT=y
+CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
+CONFIG_AT91_TIMER_HZ=128
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+CONFIG_LEDS=y
+CONFIG_LEDS_CPU=y
+CONFIG_UACCESS_WITH_MEMCPY=y
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_ARM_ATAG_DTB_COMPAT=y
+CONFIG_CMDLINE="mem=128M console=ttyS0,115200 initrd=0x21100000,25165824 root=/dev/ram0 rw"
+CONFIG_KEXEC=y
+CONFIG_AUTO_ZRELADDR=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_DIAG is not set
+CONFIG_IPV6=y
+# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET6_XFRM_MODE_BEET is not set
+CONFIG_IPV6_SIT_6RD=y
+# CONFIG_WIRELESS is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_STANDALONE is not set
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_ATMEL=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_GLUEBI=y
+CONFIG_PROC_DEVICETREE=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=4
+CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_ATMEL_PWM=y
+CONFIG_ATMEL_TCLIB=y
+CONFIG_EEPROM_93CX6=m
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_LOWLEVEL is not set
+CONFIG_NETDEVICES=y
+CONFIG_MII=y
+CONFIG_MACB=y
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CHELSIO is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+CONFIG_DAVICOM_PHY=y
+CONFIG_MICREL_PHY=y
+# CONFIG_WLAN is not set
+CONFIG_INPUT_POLLDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=480
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=272
+CONFIG_INPUT_JOYDEV=y
+CONFIG_INPUT_EVDEV=y
+# CONFIG_KEYBOARD_ATKBD is not set
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_SERIO is not set
+CONFIG_LEGACY_PTY_COUNT=4
+CONFIG_SERIAL_ATMEL=y
+CONFIG_SERIAL_ATMEL_CONSOLE=y
+CONFIG_HW_RANDOM=y
+CONFIG_I2C=y
+CONFIG_I2C_GPIO=y
+CONFIG_SPI=y
+CONFIG_SPI_ATMEL=y
+# CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_AT91SAM9X_WATCHDOG=y
+CONFIG_SSB=m
+CONFIG_FB=y
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_ATMEL=y
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+# CONFIG_LCD_CLASS_DEVICE is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_ATMEL_LCDC=y
+# CONFIG_BACKLIGHT_GENERIC is not set
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+CONFIG_FONTS=y
+CONFIG_FONT_8x8=y
+CONFIG_FONT_ACORN_8x8=y
+CONFIG_FONT_MINI_4x6=y
+CONFIG_LOGO=y
+# CONFIG_HID_SUPPORT is not set
+CONFIG_USB=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_DEVICE_CLASS is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_ACM=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_SERIAL=y
+CONFIG_USB_SERIAL_GENERIC=y
+CONFIG_USB_SERIAL_FTDI_SIO=y
+CONFIG_USB_SERIAL_PL2303=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_AT91=m
+CONFIG_USB_ATMEL_USBA=m
+CONFIG_USB_ETH=m
+CONFIG_USB_GADGETFS=m
+CONFIG_USB_CDC_COMPOSITE=m
+CONFIG_USB_G_ACM_MS=m
+CONFIG_USB_G_MULTI=m
+CONFIG_USB_G_MULTI_CDC=y
+CONFIG_MMC=y
+CONFIG_MMC_ATMELMCI=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_GPIO=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_AT91RM9200=y
+CONFIG_RTC_DRV_AT91SAM9=y
+CONFIG_DMADEVICES=y
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_EXT2_FS=y
+CONFIG_FANOTIFY=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_STRIP_ASM_SYMS=y
+CONFIG_DEBUG_FS=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_FTRACE is not set
+CONFIG_DEBUG_USER=y
+CONFIG_CRYPTO=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_AES=y
+CONFIG_CRYPTO_ARC4=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_USER_API_HASH=m
+CONFIG_CRYPTO_USER_API_SKCIPHER=m
+# CONFIG_CRYPTO_HW is not set
+CONFIG_CRC_CCITT=m
+CONFIG_CRC_ITU_T=m
+CONFIG_CRC7=m
+CONFIG_AVERAGE=y
diff --git a/arch/arm/configs/at91rm9200_defconfig b/arch/arm/configs/at91rm9200_defconfig
index bbe4e1a1f5d8..d54e2acd3ab1 100644
--- a/arch/arm/configs/at91rm9200_defconfig
+++ b/arch/arm/configs/at91rm9200_defconfig
@@ -14,6 +14,7 @@ CONFIG_MODULE_SRCVERSION_ALL=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_CFQ is not set
 CONFIG_ARCH_AT91=y
+CONFIG_ARCH_AT91RM9200=y
 CONFIG_MACH_ONEARM=y
 CONFIG_ARCH_AT91RM9200DK=y
 CONFIG_MACH_AT91RM9200EK=y
diff --git a/arch/arm/configs/bcmring_defconfig b/arch/arm/configs/bcmring_defconfig
index 795374d48f81..9e6a8fe13164 100644
--- a/arch/arm/configs/bcmring_defconfig
+++ b/arch/arm/configs/bcmring_defconfig
@@ -11,7 +11,7 @@ CONFIG_KALLSYMS_EXTRA_PASS=y
 # CONFIG_TIMERFD is not set
 # CONFIG_EVENTFD is not set
 # CONFIG_AIO is not set
-CONFIG_PERF_COUNTERS=y
+CONFIG_PERF_EVENTS=y
 # CONFIG_VM_EVENT_COUNTERS is not set
 # CONFIG_SLUB_DEBUG is not set
 # CONFIG_COMPAT_BRK is not set
diff --git a/arch/arm/configs/imx_v4_v5_defconfig b/arch/arm/configs/imx_v4_v5_defconfig
index b5ac644e12af..09a02963cf58 100644
--- a/arch/arm/configs/imx_v4_v5_defconfig
+++ b/arch/arm/configs/imx_v4_v5_defconfig
@@ -92,6 +92,7 @@ CONFIG_INPUT_EVDEV=y
 # CONFIG_INPUT_MOUSE is not set
 CONFIG_INPUT_TOUCHSCREEN=y
 CONFIG_TOUCHSCREEN_ADS7846=m
+CONFIG_TOUCHSCREEN_MC13783=m
 # CONFIG_SERIO is not set
 # CONFIG_LEGACY_PTYS is not set
 CONFIG_SERIAL_8250=m
@@ -107,11 +108,13 @@ CONFIG_SPI_SPIDEV=y
 CONFIG_W1=y
 CONFIG_W1_MASTER_MXC=y
 CONFIG_W1_SLAVE_THERM=y
-# CONFIG_HWMON is not set
+CONFIG_HWMON=m
+CONFIG_SENSORS_MC13783_ADC=m
 CONFIG_WATCHDOG=y
 CONFIG_IMX2_WDT=y
 CONFIG_MFD_MC13XXX=y
 CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
 CONFIG_REGULATOR_MC13783=y
 CONFIG_REGULATOR_MC13892=y
 CONFIG_FB=y
diff --git a/arch/arm/configs/ixp2000_defconfig b/arch/arm/configs/ixp2000_defconfig
deleted file mode 100644
index 8405aded97a3..000000000000
--- a/arch/arm/configs/ixp2000_defconfig
+++ /dev/null
@@ -1,99 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-# CONFIG_HOTPLUG is not set
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_ARCH_IXP2000=y
-CONFIG_ARCH_ENP2611=y
-CONFIG_ARCH_IXDP2400=y
-CONFIG_ARCH_IXDP2800=y
-CONFIG_ARCH_IXDP2401=y
-CONFIG_ARCH_IXDP2801=y
-# CONFIG_IXP2000_SUPPORT_BROKEN_PCI_IO is not set
-# CONFIG_ARM_THUMB is not set
-CONFIG_CPU_BIG_ENDIAN=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyS0,57600 root=/dev/nfs ip=bootp mem=64M@0x0"
-CONFIG_FPE_NWFPE=y
-CONFIG_FPE_NWFPE_XP=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_SYN_COOKIES=y
-CONFIG_IPV6=y
-# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET6_XFRM_MODE_BEET is not set
-# CONFIG_IPV6_SIT is not set
-# CONFIG_PREVENT_FIRMWARE_BUILD is not set
-CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_REDBOOT_PARTS=y
-CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
-CONFIG_MTD_REDBOOT_PARTS_READONLY=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_IXP2000=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_NBD=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_EEPROM_LEGACY=y
-CONFIG_NETDEVICES=y
-CONFIG_DUMMY=y
-CONFIG_NET_ETHERNET=y
-CONFIG_NET_PCI=y
-CONFIG_CS89x0=y
-CONFIG_E100=y
-CONFIG_ENP2611_MSF_NET=y
-CONFIG_WAN=y
-CONFIG_HDLC=y
-CONFIG_HDLC_RAW=y
-CONFIG_HDLC_CISCO=y
-CONFIG_HDLC_FR=y
-CONFIG_HDLC_PPP=y
-CONFIG_DLCI=y
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_NR_UARTS=3
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_IXP2000=y
-CONFIG_WATCHDOG=y
-CONFIG_IXP2000_WATCHDOG=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT2_FS_POSIX_ACL=y
-CONFIG_EXT3_FS=y
-CONFIG_EXT3_FS_POSIX_ACL=y
-CONFIG_INOTIFY=y
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_ROOT_NFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_MUTEXES=y
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_ERRORS=y
-CONFIG_DEBUG_LL=y
diff --git a/arch/arm/configs/ixp23xx_defconfig b/arch/arm/configs/ixp23xx_defconfig
deleted file mode 100644
index 688717612e91..000000000000
--- a/arch/arm/configs/ixp23xx_defconfig
+++ /dev/null
@@ -1,105 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_ARCH_IXP23XX=y
-CONFIG_MACH_ESPRESSO=y
-CONFIG_MACH_IXDP2351=y
-CONFIG_MACH_ROADRUNNER=y
-# CONFIG_ARM_THUMB is not set
-CONFIG_CPU_BIG_ENDIAN=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyS0,115200 root=/dev/nfs ip=bootp"
-CONFIG_FPE_NWFPE=y
-CONFIG_FPE_NWFPE_XP=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_SYN_COOKIES=y
-CONFIG_IPV6=y
-# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET6_XFRM_MODE_BEET is not set
-# CONFIG_IPV6_SIT is not set
-# CONFIG_PREVENT_FIRMWARE_BUILD is not set
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_REDBOOT_PARTS=y
-CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
-CONFIG_MTD_REDBOOT_PARTS_READONLY=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_NBD=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_EEPROM_LEGACY=y
-CONFIG_IDE=y
-CONFIG_BLK_DEV_SIIMAGE=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_NETDEVICES=y
-CONFIG_DUMMY=y
-CONFIG_NET_ETHERNET=y
-CONFIG_NET_PCI=y
-CONFIG_E100=y
-CONFIG_E1000=y
-CONFIG_WAN=y
-CONFIG_HDLC=y
-CONFIG_HDLC_RAW=y
-CONFIG_HDLC_CISCO=y
-CONFIG_HDLC_FR=y
-CONFIG_HDLC_PPP=y
-CONFIG_DLCI=y
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_WATCHDOG=y
-# CONFIG_USB_HID is not set
-CONFIG_USB=y
-CONFIG_USB_MON=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_UHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT2_FS_POSIX_ACL=y
-CONFIG_EXT3_FS=y
-CONFIG_EXT3_FS_POSIX_ACL=y
-CONFIG_INOTIFY=y
-CONFIG_MSDOS_FS=y
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_ROOT_NFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_MUTEXES=y
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_ERRORS=y
-CONFIG_DEBUG_LL=y
diff --git a/arch/arm/configs/kzm9g_defconfig b/arch/arm/configs/kzm9g_defconfig
new file mode 100644
index 000000000000..e3ebc20ed0a7
--- /dev/null
+++ b/arch/arm/configs/kzm9g_defconfig
@@ -0,0 +1,139 @@
+# CONFIG_ARM_PATCH_PHYS_VIRT is not set
+CONFIG_EXPERIMENTAL=y
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SYSVIPC=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=16
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_NET_NS is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_ARCH_SHMOBILE=y
+CONFIG_KEYBOARD_GPIO_POLLED=y
+CONFIG_ARCH_SH73A0=y
+CONFIG_MACH_KZM9G=y
+CONFIG_MEMORY_START=0x41000000
+CONFIG_MEMORY_SIZE=0x1f000000
+CONFIG_ARM_ERRATA_743622=y
+CONFIG_ARM_ERRATA_754322=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_SMP=y
+CONFIG_SCHED_MC=y
+CONFIG_PREEMPT=y
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+CONFIG_HIGHMEM=y
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="console=tty0 console=ttySC4,115200 root=/dev/nfs ip=dhcp ignore_loglevel earlyprintk=sh-sci.4,115200"
+CONFIG_KEXEC=y
+CONFIG_VFP=y
+CONFIG_NEON=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_PM_RUNTIME=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_IPV6 is not set
+CONFIG_IRDA=y
+CONFIG_SH_IRDA=y
+# CONFIG_WIRELESS is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_NETDEVICES=y
+CONFIG_SMSC911X=y
+# CONFIG_WLAN is not set
+CONFIG_INPUT_SPARSEKMAP=y
+# CONFIG_INPUT_MOUSEDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_ST1232=y
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_SERIAL_SH_SCI=y
+CONFIG_SERIAL_SH_SCI_NR_UARTS=9
+CONFIG_SERIAL_SH_SCI_CONSOLE=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_SH_MOBILE=y
+CONFIG_GPIO_PCF857X=y
+# CONFIG_HWMON is not set
+CONFIG_FB=y
+CONFIG_FB_SH_MOBILE_LCDC=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_LOGO=y
+CONFIG_FB_SH_MOBILE_MERAM=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+# CONFIG_SND_SUPPORT_OLD_API is not set
+# CONFIG_SND_VERBOSE_PROCFS is not set
+# CONFIG_SND_DRIVERS is not set
+# CONFIG_SND_ARM is not set
+# CONFIG_SND_USB is not set
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_SH4_FSI=y
+# CONFIG_HID_SUPPORT is not set
+CONFIG_USB=y
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_R8A66597_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+# CONFIG_MMC_BLOCK_BOUNCE is not set
+CONFIG_MMC_SDHI=y
+CONFIG_MMC_SH_MMCIF=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_RTC_CLASS=y
+CONFIG_DMADEVICES=y
+CONFIG_SH_DMAE=y
+CONFIG_ASYNC_TX_DMA=y
+CONFIG_STAGING=y
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY_USER is not set
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+# CONFIG_MISC_FILESYSTEMS is not set
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_NFS_V4_1=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_DEBUG_PREEMPT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_FTRACE is not set
+# CONFIG_ARM_UNWIND is not set
+CONFIG_CRYPTO=y
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_DES=y
+CONFIG_CRC16=y
diff --git a/arch/arm/configs/lpc32xx_defconfig b/arch/arm/configs/lpc32xx_defconfig
index fb2088171ca9..4fa60547494a 100644
--- a/arch/arm/configs/lpc32xx_defconfig
+++ b/arch/arm/configs/lpc32xx_defconfig
@@ -2,7 +2,7 @@ CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
+CONFIG_LOG_BUF_SHIFT=16
 CONFIG_SYSFS_DEPRECATED=y
 CONFIG_SYSFS_DEPRECATED_V2=y
 CONFIG_BLK_DEV_INITRD=y
@@ -10,6 +10,7 @@ CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 CONFIG_SYSCTL_SYSCALL=y
 CONFIG_EMBEDDED=y
 CONFIG_SLAB=y
+CONFIG_JUMP_LABEL=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
@@ -21,6 +22,8 @@ CONFIG_PREEMPT=y
 CONFIG_AEABI=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_ARM_ATAG_DTB_COMPAT=y
 CONFIG_CMDLINE="console=ttyS0,115200n81 root=/dev/ram0"
 CONFIG_CPU_IDLE=y
 CONFIG_FPE_NWFPE=y
@@ -40,7 +43,8 @@ CONFIG_IP_PNP_BOOTP=y
 # CONFIG_INET_XFRM_MODE_BEET is not set
 # CONFIG_INET_LRO is not set
 # CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
+CONFIG_IPV6=y
+CONFIG_IPV6_PRIVACY=y
 # CONFIG_WIRELESS is not set
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 # CONFIG_FW_LOADER is not set
@@ -55,13 +59,24 @@ CONFIG_BLK_DEV_CRYPTOLOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=1
 CONFIG_BLK_DEV_RAM_SIZE=16384
-CONFIG_MISC_DEVICES=y
 CONFIG_EEPROM_AT25=y
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_NETDEVICES=y
 CONFIG_MII=y
-CONFIG_PHYLIB=y
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CHELSIO is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MICROCHIP is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+CONFIG_LPC_ENET=y
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
 CONFIG_SMSC_PHY=y
 # CONFIG_WLAN is not set
 # CONFIG_INPUT_MOUSEDEV_PSAUX is not set
@@ -97,16 +112,22 @@ CONFIG_SND_SEQUENCER=y
 CONFIG_SND_MIXER_OSS=y
 CONFIG_SND_PCM_OSS=y
 CONFIG_SND_SEQUENCER_OSS=y
-CONFIG_SND_DYNAMIC_MINORS=y
+# CONFIG_SND_SUPPORT_OLD_API is not set
 # CONFIG_SND_VERBOSE_PROCFS is not set
+CONFIG_SND_DEBUG=y
+CONFIG_SND_DEBUG_VERBOSE=y
 # CONFIG_SND_DRIVERS is not set
 # CONFIG_SND_ARM is not set
 # CONFIG_SND_SPI is not set
 CONFIG_SND_SOC=y
 # CONFIG_HID_SUPPORT is not set
 CONFIG_USB=y
+CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_STORAGE=y
-CONFIG_USB_LIBUSUAL=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_LPC32XX=y
+CONFIG_USB_MASS_STORAGE=m
+CONFIG_USB_G_SERIAL=m
 CONFIG_MMC=y
 # CONFIG_MMC_BLOCK_BOUNCE is not set
 CONFIG_MMC_ARMMMCI=y
@@ -114,10 +135,21 @@ CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_GPIO=y
 CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
 CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_BACKLIGHT=y
+CONFIG_LEDS_TRIGGER_GPIO=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_INTF_DEV_UIE_EMUL=y
+CONFIG_RTC_DRV_DS1374=y
+CONFIG_RTC_DRV_PCF8563=y
 CONFIG_RTC_DRV_LPC32XX=y
+CONFIG_DMADEVICES=y
+CONFIG_AMBA_PL08X=y
+CONFIG_STAGING=y
+CONFIG_IIO=y
+CONFIG_LPC32XX_ADC=y
 CONFIG_EXT2_FS=y
 CONFIG_AUTOFS4_FS=y
 CONFIG_MSDOS_FS=y
diff --git a/arch/arm/configs/mini2440_defconfig b/arch/arm/configs/mini2440_defconfig
index 42da9183acc8..082175c54e7c 100644
--- a/arch/arm/configs/mini2440_defconfig
+++ b/arch/arm/configs/mini2440_defconfig
@@ -14,6 +14,8 @@ CONFIG_MODULE_FORCE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 CONFIG_BLK_DEV_INTEGRITY=y
 CONFIG_ARCH_S3C24XX=y
+# CONFIG_CPU_S3C2410 is not set
+CONFIG_CPU_S3C2440=y
 CONFIG_S3C_ADC=y
 CONFIG_S3C24XX_PWM=y
 CONFIG_MACH_MINI2440=y
diff --git a/arch/arm/configs/nhk8815_defconfig b/arch/arm/configs/nhk8815_defconfig
index 37207d1bf44b..bf123c5384d4 100644
--- a/arch/arm/configs/nhk8815_defconfig
+++ b/arch/arm/configs/nhk8815_defconfig
@@ -97,6 +97,7 @@ CONFIG_I2C=y
 CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_GPIO=y
 CONFIG_DEBUG_GPIO=y
+CONFIG_PINCTRL_NOMADIK=y
 # CONFIG_HWMON is not set
 # CONFIG_VGA_CONSOLE is not set
 CONFIG_RTC_CLASS=y
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index d5f00d7eb075..9854ff4279e0 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -98,6 +98,7 @@ CONFIG_LIBERTAS_USB=m
 CONFIG_LIBERTAS_SDIO=m
 CONFIG_LIBERTAS_DEBUG=y
 CONFIG_USB_USBNET=y
+CONFIG_USB_NET_SMSC95XX=y
 CONFIG_USB_ALI_M5632=y
 CONFIG_USB_AN2720=y
 CONFIG_USB_EPSON2888=y
@@ -175,6 +176,7 @@ CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
 CONFIG_USB_DEVICEFS=y
 CONFIG_USB_SUSPEND=y
 CONFIG_USB_MON=y
+CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_WDM=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_LIBUSUAL=y
diff --git a/arch/arm/configs/rpc_defconfig b/arch/arm/configs/rpc_defconfig
index af278f7a2246..00515ef9782d 100644
--- a/arch/arm/configs/rpc_defconfig
+++ b/arch/arm/configs/rpc_defconfig
@@ -8,8 +8,6 @@ CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 CONFIG_ARCH_RPC=y
-CONFIG_CPU_ARM610=y
-CONFIG_CPU_ARM710=y
 CONFIG_CPU_SA110=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
diff --git a/arch/arm/configs/spear3xx_defconfig b/arch/arm/configs/spear3xx_defconfig
index fea7e1f026a3..7ed42912d69a 100644
--- a/arch/arm/configs/spear3xx_defconfig
+++ b/arch/arm/configs/spear3xx_defconfig
@@ -2,33 +2,67 @@ CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_BSD_PROCESS_ACCT=y
 CONFIG_BLK_DEV_INITRD=y
-CONFIG_KALLSYMS_EXTRA_PASS=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 CONFIG_MODVERSIONS=y
+CONFIG_PARTITION_ADVANCED=y
 CONFIG_PLAT_SPEAR=y
-CONFIG_BOARD_SPEAR300_EVB=y
+CONFIG_MACH_SPEAR300=y
-CONFIG_BOARD_SPEAR310_EVB=y
+CONFIG_MACH_SPEAR310=y
-CONFIG_BOARD_SPEAR320_EVB=y
+CONFIG_MACH_SPEAR320=y
 CONFIG_BINFMT_MISC=y
+CONFIG_NET=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_MTD=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_FSMC=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_NETDEVICES=y
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+CONFIG_STMMAC_ETH=y
+# CONFIG_WLAN is not set
 CONFIG_INPUT_FF_MEMLESS=y
 # CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_KEYBOARD_ATKBD is not set
+CONFIG_KEYBOARD_SPEAR=y
 # CONFIG_INPUT_MOUSE is not set
+# CONFIG_LEGACY_PTYS is not set
 CONFIG_SERIAL_AMBA_PL011=y
 CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
 # CONFIG_HW_RANDOM is not set
 CONFIG_RAW_DRIVER=y
 CONFIG_MAX_RAW_DEVS=8192
+CONFIG_I2C=y
+CONFIG_I2C_DESIGNWARE_PLATFORM=y
+CONFIG_SPI=y
+CONFIG_SPI_PL022=y
 CONFIG_GPIO_SYSFS=y
 CONFIG_GPIO_PL061=y
 # CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_ARM_SP805_WATCHDOG=y
+CONFIG_FB=y
+CONFIG_FB_ARMCLCD=y
 # CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
+CONFIG_USB=y
+# CONFIG_USB_DEVICE_CLASS is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SPEAR=y
+CONFIG_RTC_CLASS=y
+CONFIG_DMADEVICES=y
+CONFIG_AMBA_PL08X=y
+CONFIG_DMATEST=m
 CONFIG_EXT2_FS=y
 CONFIG_EXT2_FS_XATTR=y
 CONFIG_EXT2_FS_SECURITY=y
@@ -39,8 +73,6 @@ CONFIG_MSDOS_FS=m
 CONFIG_VFAT_FS=m
 CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
 CONFIG_TMPFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS=y
 CONFIG_NLS_DEFAULT="utf8"
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ASCII=m
@@ -48,6 +80,4 @@ CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_FS=y
 CONFIG_DEBUG_KERNEL=y
 CONFIG_DEBUG_SPINLOCK=y
-CONFIG_DEBUG_SPINLOCK_SLEEP=y
 CONFIG_DEBUG_INFO=y
-# CONFIG_CRC32 is not set
diff --git a/arch/arm/configs/spear6xx_defconfig b/arch/arm/configs/spear6xx_defconfig
index cef2e836afd2..cf94bc73a0e0 100644
--- a/arch/arm/configs/spear6xx_defconfig
+++ b/arch/arm/configs/spear6xx_defconfig
@@ -2,29 +2,58 @@ CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_BSD_PROCESS_ACCT=y
 CONFIG_BLK_DEV_INITRD=y
-CONFIG_KALLSYMS_EXTRA_PASS=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 CONFIG_MODVERSIONS=y
+CONFIG_PARTITION_ADVANCED=y
 CONFIG_PLAT_SPEAR=y
 CONFIG_ARCH_SPEAR6XX=y
-CONFIG_BOARD_SPEAR600_EVB=y
+CONFIG_BOARD_SPEAR600_DT=y
 CONFIG_BINFMT_MISC=y
+CONFIG_NET=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_MTD=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_FSMC=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_NETDEVICES=y
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+CONFIG_STMMAC_ETH=y
+# CONFIG_WLAN is not set
 CONFIG_INPUT_FF_MEMLESS=y
 # CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_LEGACY_PTYS is not set
 CONFIG_SERIAL_AMBA_PL011=y
 CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
 CONFIG_RAW_DRIVER=y
 CONFIG_MAX_RAW_DEVS=8192
+CONFIG_I2C=y
+CONFIG_I2C_DESIGNWARE_PLATFORM=y
+CONFIG_SPI=y
+CONFIG_SPI_PL022=y
 CONFIG_GPIO_SYSFS=y
 CONFIG_GPIO_PL061=y
 # CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_ARM_SP805_WATCHDOG=y
 # CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_RTC_CLASS=y
+CONFIG_DMADEVICES=y
+CONFIG_AMBA_PL08X=y
+CONFIG_DMATEST=m
 CONFIG_EXT2_FS=y
 CONFIG_EXT2_FS_XATTR=y
 CONFIG_EXT2_FS_SECURITY=y
@@ -35,8 +64,6 @@ CONFIG_MSDOS_FS=m
 CONFIG_VFAT_FS=m
 CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
 CONFIG_TMPFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS=y
 CONFIG_NLS_DEFAULT="utf8"
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ASCII=m
@@ -44,6 +71,4 @@ CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_FS=y
 CONFIG_DEBUG_KERNEL=y
 CONFIG_DEBUG_SPINLOCK=y
-CONFIG_DEBUG_SPINLOCK_SLEEP=y
 CONFIG_DEBUG_INFO=y
-# CONFIG_CRC32 is not set
diff --git a/arch/arm/configs/u8500_defconfig b/arch/arm/configs/u8500_defconfig
index 889d73ac1ae1..7e84f453e8a6 100644
--- a/arch/arm/configs/u8500_defconfig
+++ b/arch/arm/configs/u8500_defconfig
@@ -8,8 +8,6 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_LBDAF is not set
 # CONFIG_BLK_DEV_BSG is not set
 CONFIG_ARCH_U8500=y
-CONFIG_UX500_SOC_DB5500=y
-CONFIG_UX500_SOC_DB8500=y
 CONFIG_MACH_HREFV60=y
 CONFIG_MACH_SNOWBALL=y
 CONFIG_MACH_U5500=y
@@ -39,7 +37,6 @@ CONFIG_CAIF=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=65536
-CONFIG_MISC_DEVICES=y
 CONFIG_AB8500_PWM=y
 CONFIG_SENSORS_BH1780=y
 CONFIG_NETDEVICES=y
@@ -65,16 +62,18 @@ CONFIG_SERIAL_AMBA_PL011=y
 CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
 CONFIG_HW_RANDOM=y
 CONFIG_HW_RANDOM_NOMADIK=y
-CONFIG_I2C=y
-CONFIG_I2C_NOMADIK=y
 CONFIG_SPI=y
 CONFIG_SPI_PL022=y
 CONFIG_GPIO_STMPE=y
 CONFIG_GPIO_TC3589X=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_AB8500_BM=y
+CONFIG_AB8500_BATTERY_THERM_ON_BATCTRL=y
 CONFIG_MFD_STMPE=y
 CONFIG_MFD_TC3589X=y
 CONFIG_AB5500_CORE=y
 CONFIG_AB8500_CORE=y
+CONFIG_REGULATOR=y
 CONFIG_REGULATOR_AB8500=y
 # CONFIG_HID_SUPPORT is not set
 CONFIG_USB_GADGET=y
diff --git a/arch/arm/include/asm/arch_timer.h b/arch/arm/include/asm/arch_timer.h
new file mode 100644
index 000000000000..ed2e95d46e29
--- /dev/null
+++ b/arch/arm/include/asm/arch_timer.h
@@ -0,0 +1,19 @@
+#ifndef __ASMARM_ARCH_TIMER_H
+#define __ASMARM_ARCH_TIMER_H
+#ifdef CONFIG_ARM_ARCH_TIMER
+int arch_timer_of_register(void);
+int arch_timer_sched_clock_init(void);
+#else
+static inline int arch_timer_of_register(void)
+{
+        return -ENXIO;
+}
+static inline int arch_timer_sched_clock_init(void)
+{
+        return -ENXIO;
+}
+#endif
+#endif
diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index d5d8d5c72682..004c1bc95d2b 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -101,7 +101,7 @@ struct cpu_cache_fns {
        void (*flush_user_range)(unsigned long, unsigned long, unsigned int);
        void (*coherent_kern_range)(unsigned long, unsigned long);
-        void (*coherent_user_range)(unsigned long, unsigned long);
+        int  (*coherent_user_range)(unsigned long, unsigned long);
        void (*flush_kern_dcache_area)(void *, size_t);
        void (*dma_map_area)(const void *, size_t, int);
@@ -142,7 +142,7 @@ extern void __cpuc_flush_kern_all(void);
 extern void __cpuc_flush_user_all(void);
 extern void __cpuc_flush_user_range(unsigned long, unsigned long, unsigned int);
 extern void __cpuc_coherent_kern_range(unsigned long, unsigned long);
-extern void __cpuc_coherent_user_range(unsigned long, unsigned long);
+extern int  __cpuc_coherent_user_range(unsigned long, unsigned long);
 extern void __cpuc_flush_dcache_area(void *, size_t);
 /*
@@ -249,7 +249,7 @@ extern void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr
 * Harvard caches are synchronised for the user space address range.
 * This is used for the ARM private sys_cacheflush system call.
 */
-#define flush_cache_user_range(vma,start,end) \
+#define flush_cache_user_range(start,end) \
        __cpuc_coherent_user_range((start) & PAGE_MASK, PAGE_ALIGN(end))
 /*
diff --git a/arch/arm/include/asm/cmpxchg.h b/arch/arm/include/asm/cmpxchg.h
index d41d7cbf0ada..7eb18c1d8d6c 100644
--- a/arch/arm/include/asm/cmpxchg.h
+++ b/arch/arm/include/asm/cmpxchg.h
@@ -229,66 +229,19 @@ static inline unsigned long __cmpxchg_local(volatile void *ptr,
                                       (unsigned long)(n),              \
                                       sizeof(*(ptr))))
-#ifndef CONFIG_CPU_V6   /* min ARCH >= ARMv6K */
+#define cmpxchg64(ptr, o, n)                                            \
+        ((__typeof__(*(ptr)))atomic64_cmpxchg(container_of((ptr),       \
-/*
+                                                atomic64_t,             \
- * Note : ARMv7-M (currently unsupported by Linux) does not support
+                                                counter),               \
- * ldrexd/strexd. If ARMv7-M is ever supported by the Linux kernel, it should
+                                              (unsigned long)(o),       \
- * not be allowed to use __cmpxchg64.
+                                              (unsigned long)(n)))
- */
-static inline unsigned long long __cmpxchg64(volatile void *ptr,
+#define cmpxchg64_local(ptr, o, n)                                      \
-                                             unsigned long long old,
+        ((__typeof__(*(ptr)))local64_cmpxchg(container_of((ptr),        \
-                                             unsigned long long new)
+                                                local64_t,              \
-{
+                                                a),                     \
-        register unsigned long long oldval asm("r0");
+                                             (unsigned long)(o),        \
-        register unsigned long long __old asm("r2") = old;
+                                             (unsigned long)(n)))
-        register unsigned long long __new asm("r4") = new;
-        unsigned long res;
-        do {
-                asm volatile(
-                "       @ __cmpxchg8\n"
-                "       ldrexd  %1, %H1, [%2]\n"
-                "       mov     %0, #0\n"
-                "       teq     %1, %3\n"
-                "       teqeq   %H1, %H3\n"
-                "       strexdeq %0, %4, %H4, [%2]\n"
-                        : "=&r" (res), "=&r" (oldval)
-                        : "r" (ptr), "Ir" (__old), "r" (__new)
-                        : "memory", "cc");
-        } while (res);
-        return oldval;
-}
-static inline unsigned long long __cmpxchg64_mb(volatile void *ptr,
-                                                unsigned long long old,
-                                                unsigned long long new)
-{
-        unsigned long long ret;
-        smp_mb();
-        ret = __cmpxchg64(ptr, old, new);
-        smp_mb();
-        return ret;
-}
-#define cmpxchg64(ptr,o,n)                                              \
-        ((__typeof__(*(ptr)))__cmpxchg64_mb((ptr),                      \
-                                            (unsigned long long)(o),    \
-                                            (unsigned long long)(n)))
-#define cmpxchg64_local(ptr,o,n)                                        \
-        ((__typeof__(*(ptr)))__cmpxchg64((ptr),                         \
-                                         (unsigned long long)(o),       \
-                                         (unsigned long long)(n)))
-#else /* min ARCH = ARMv6 */
-#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
-#endif
 #endif  /* __LINUX_ARM_ARCH__ >= 6 */
diff --git a/arch/arm/include/asm/cpu.h b/arch/arm/include/asm/cpu.h
index 793968173bef..d797223b39d5 100644
--- a/arch/arm/include/asm/cpu.h
+++ b/arch/arm/include/asm/cpu.h
@@ -16,7 +16,6 @@
 struct cpuinfo_arm {
        struct cpu      cpu;
 #ifdef CONFIG_SMP
-        struct task_struct *idle;
        unsigned int    loops_per_jiffy;
 #endif
 };
diff --git a/arch/arm/include/asm/glue-df.h b/arch/arm/include/asm/glue-df.h
index 354d571e8bcc..8cacbcda76da 100644
--- a/arch/arm/include/asm/glue-df.h
+++ b/arch/arm/include/asm/glue-df.h
@@ -31,14 +31,6 @@
 #undef CPU_DABORT_HANDLER
 #undef MULTI_DABORT
-#if defined(CONFIG_CPU_ARM610)
-# ifdef CPU_DABORT_HANDLER
-#  define MULTI_DABORT 1
-# else
-#  define CPU_DABORT_HANDLER cpu_arm6_data_abort
-# endif
-#endif
 #if defined(CONFIG_CPU_ARM710)
 # ifdef CPU_DABORT_HANDLER
 #  define MULTI_DABORT 1
diff --git a/arch/arm/include/asm/glue-proc.h b/arch/arm/include/asm/glue-proc.h
index e2be7f142668..ac1dd54724b6 100644
--- a/arch/arm/include/asm/glue-proc.h
+++ b/arch/arm/include/asm/glue-proc.h
@@ -23,15 +23,6 @@
 * CPU_NAME - the prefix for CPU related functions
 */
-#ifdef CONFIG_CPU_ARM610
-# ifdef CPU_NAME
-#  undef  MULTI_CPU
-#  define MULTI_CPU
-# else
-#  define CPU_NAME cpu_arm6
-# endif
-#endif
 #ifdef CONFIG_CPU_ARM7TDMI
 # ifdef CPU_NAME
 #  undef  MULTI_CPU
@@ -41,15 +32,6 @@
 # endif
 #endif
-#ifdef CONFIG_CPU_ARM710
-# ifdef CPU_NAME
-#  undef  MULTI_CPU
-#  define MULTI_CPU
-# else
-#  define CPU_NAME cpu_arm7
-# endif
-#endif
 #ifdef CONFIG_CPU_ARM720T
 # ifdef CPU_NAME
 #  undef  MULTI_CPU
diff --git a/arch/arm/include/asm/hardware/cs89712.h b/arch/arm/include/asm/hardware/cs89712.h
deleted file mode 100644
index f75626933e94..000000000000
--- a/arch/arm/include/asm/hardware/cs89712.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- *  arch/arm/include/asm/hardware/cs89712.h
- *
- *  This file contains the hardware definitions of the CS89712
- *  additional internal registers.
- *
- *  Copyright (C) 2001 Thomas Gleixner autronix automation <gleixner@autronix.de>
- *                      
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_HARDWARE_CS89712_H
-#define __ASM_HARDWARE_CS89712_H
-/*
-*       CS89712 additional registers
-*/
-                                  
-#define PCDR                    0x0002  /* Port C Data register ---------------------------- */
-#define PCDDR                   0x0042  /* Port C Data Direction register ------------------ */
-#define SDCONF                  0x2300  /* SDRAM Configuration register ---------------------*/
-#define SDRFPR                  0x2340  /* SDRAM Refresh period register --------------------*/
-#define SDCONF_ACTIVE           (1 << 10)
-#define SDCONF_CLKCTL           (1 << 9)
-#define SDCONF_WIDTH_4          (0 << 7)
-#define SDCONF_WIDTH_8          (1 << 7)
-#define SDCONF_WIDTH_16         (2 << 7)
-#define SDCONF_WIDTH_32         (3 << 7)
-#define SDCONF_SIZE_16          (0 << 5)
-#define SDCONF_SIZE_64          (1 << 5)
-#define SDCONF_SIZE_128         (2 << 5)
-#define SDCONF_SIZE_256         (3 << 5)
-#define SDCONF_CASLAT_2         (2)
-#define SDCONF_CASLAT_3         (3)
-#endif /* __ASM_HARDWARE_CS89712_H */
diff --git a/arch/arm/include/asm/hardware/ep7211.h b/arch/arm/include/asm/hardware/ep7211.h
deleted file mode 100644
index 654d5f625c49..000000000000
--- a/arch/arm/include/asm/hardware/ep7211.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- *  arch/arm/include/asm/hardware/ep7211.h
- *
- *  This file contains the hardware definitions of the EP7211 internal
- *  registers.
- *
- *  Copyright (C) 2001 Blue Mug, Inc.  All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_HARDWARE_EP7211_H
-#define __ASM_HARDWARE_EP7211_H
-#include <asm/hardware/clps7111.h>
-/*
- * define EP7211_BASE to be the base address of the region
- * you want to access.
- */
-#define EP7211_PHYS_BASE        (0x80000000)
-/*
- * XXX miket@bluemug.com: need to introduce EP7211 registers (those not
- * present in 7212) here.
- */
-#endif /* __ASM_HARDWARE_EP7211_H */
diff --git a/arch/arm/include/asm/hardware/ep7212.h b/arch/arm/include/asm/hardware/ep7212.h
deleted file mode 100644
index 3b43bbeaf1db..000000000000
--- a/arch/arm/include/asm/hardware/ep7212.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- *  arch/arm/include/asm/hardware/ep7212.h
- *
- *  This file contains the hardware definitions of the EP7212 internal
- *  registers.
- *
- *  Copyright (C) 2000 Deep Blue Solutions Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_HARDWARE_EP7212_H
-#define __ASM_HARDWARE_EP7212_H
-/*
- * define EP7212_BASE to be the base address of the region
- * you want to access.
- */
-#define EP7212_PHYS_BASE        (0x80000000)
-#ifndef __ASSEMBLY__
-#define ep_readl(off)           __raw_readl(EP7212_BASE + (off))
-#define ep_writel(val,off)      __raw_writel(val, EP7212_BASE + (off))
-#endif
-/*
- * These registers are specific to the EP7212 only
- */
-#define DAIR                    0x2000
-#define DAIR0                   0x2040
-#define DAIDR1                  0x2080
-#define DAIDR2                  0x20c0
-#define DAISR                   0x2100
-#define SYSCON3                 0x2200
-#define INTSR3                  0x2240
-#define INTMR3                  0x2280
-#define LEDFLSH                 0x22c0
-#define DAIR_DAIEN              (1 << 16)
-#define DAIR_ECS                (1 << 17)
-#define DAIR_LCTM               (1 << 19)
-#define DAIR_LCRM               (1 << 20)
-#define DAIR_RCTM               (1 << 21)
-#define DAIR_RCRM               (1 << 22)
-#define DAIR_LBM                (1 << 23)
-#define DAIDR2_FIFOEN           (1 << 15)
-#define DAIDR2_FIFOLEFT         (0x0d << 16)
-#define DAIDR2_FIFORIGHT        (0x11 << 16)
-#define DAISR_RCTS              (1 << 0)
-#define DAISR_RCRS              (1 << 1)
-#define DAISR_LCTS              (1 << 2)
-#define DAISR_LCRS              (1 << 3)
-#define DAISR_RCTU              (1 << 4)
-#define DAISR_RCRO              (1 << 5)
-#define DAISR_LCTU              (1 << 6)
-#define DAISR_LCRO              (1 << 7)
-#define DAISR_RCNF              (1 << 8)
-#define DAISR_RCNE              (1 << 9)
-#define DAISR_LCNF              (1 << 10)
-#define DAISR_LCNE              (1 << 11)
-#define DAISR_FIFO              (1 << 12)
-#define SYSCON3_ADCCON          (1 << 0)
-#define SYSCON3_DAISEL          (1 << 3)
-#define SYSCON3_ADCCKNSEN       (1 << 4)
-#define SYSCON3_FASTWAKE        (1 << 8)
-#define SYSCON3_DAIEN           (1 << 9)
-#endif /* __ASM_HARDWARE_EP7212_H */
diff --git a/arch/arm/include/asm/hardware/it8152.h b/arch/arm/include/asm/hardware/it8152.h
index 73f84fa4f366..d36a73d7c0e8 100644
--- a/arch/arm/include/asm/hardware/it8152.h
+++ b/arch/arm/include/asm/hardware/it8152.h
@@ -110,6 +110,6 @@ extern void it8152_irq_demux(unsigned int irq, struct irq_desc *desc);
 extern void it8152_init_irq(void);
 extern int it8152_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
 extern int it8152_pci_setup(int nr, struct pci_sys_data *sys);
-extern struct pci_bus *it8152_pci_scan_bus(int nr, struct pci_sys_data *sys);
+extern struct pci_ops it8152_ops;
 #endif /* __ASM_HARDWARE_IT8152_H */
diff --git a/arch/arm/include/asm/hardware/uengine.h b/arch/arm/include/asm/hardware/uengine.h
deleted file mode 100644
index b442d65c6593..000000000000
--- a/arch/arm/include/asm/hardware/uengine.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * Generic library functions for the microengines found on the Intel
- * IXP2000 series of network processors.
- *
- * Copyright (C) 2004, 2005 Lennert Buytenhek <buytenh@wantstofly.org>
- * Dedicated to Marija Kulikova.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as
- * published by the Free Software Foundation; either version 2.1 of the
- * License, or (at your option) any later version.
- */
-#ifndef __IXP2000_UENGINE_H
-#define __IXP2000_UENGINE_H
-extern u32 ixp2000_uengine_mask;
-struct ixp2000_uengine_code
-{
-        u32     cpu_model_bitmask;
-        u8      cpu_min_revision;
-        u8      cpu_max_revision;
-        u32     uengine_parameters;
-        struct ixp2000_reg_value {
-                int     reg;
-                u32     value;
-        } *initial_reg_values;
-        int     num_insns;
-        u8      *insns;
-};
-u32 ixp2000_uengine_csr_read(int uengine, int offset);
-void ixp2000_uengine_csr_write(int uengine, int offset, u32 value);
-void ixp2000_uengine_reset(u32 uengine_mask);
-void ixp2000_uengine_set_mode(int uengine, u32 mode);
-void ixp2000_uengine_load_microcode(int uengine, u8 *ucode, int insns);
-void ixp2000_uengine_init_context(int uengine, int context, int pc);
-void ixp2000_uengine_start_contexts(int uengine, u8 ctx_mask);
-void ixp2000_uengine_stop_contexts(int uengine, u8 ctx_mask);
-int ixp2000_uengine_load(int uengine, struct ixp2000_uengine_code *c);
-#define IXP2000_UENGINE_8_CONTEXTS              0x00000000
-#define IXP2000_UENGINE_4_CONTEXTS              0x80000000
-#define IXP2000_UENGINE_PRN_UPDATE_EVERY        0x40000000
-#define IXP2000_UENGINE_PRN_UPDATE_ON_ACCESS    0x00000000
-#define IXP2000_UENGINE_NN_FROM_SELF            0x00100000
-#define IXP2000_UENGINE_NN_FROM_PREVIOUS        0x00000000
-#define IXP2000_UENGINE_ASSERT_EMPTY_AT_3       0x000c0000
-#define IXP2000_UENGINE_ASSERT_EMPTY_AT_2       0x00080000
-#define IXP2000_UENGINE_ASSERT_EMPTY_AT_1       0x00040000
-#define IXP2000_UENGINE_ASSERT_EMPTY_AT_0       0x00000000
-#define IXP2000_UENGINE_LM_ADDR1_GLOBAL         0x00020000
-#define IXP2000_UENGINE_LM_ADDR1_PER_CONTEXT    0x00000000
-#define IXP2000_UENGINE_LM_ADDR0_GLOBAL         0x00010000
-#define IXP2000_UENGINE_LM_ADDR0_PER_CONTEXT    0x00000000
-#endif
diff --git a/arch/arm/include/asm/jump_label.h b/arch/arm/include/asm/jump_label.h
index 5c5ca2ea62b0..bfc198c75913 100644
--- a/arch/arm/include/asm/jump_label.h
+++ b/arch/arm/include/asm/jump_label.h
@@ -14,7 +14,7 @@
 #define JUMP_LABEL_NOP  "nop"
 #endif
-static __always_inline bool arch_static_branch(struct jump_label_key *key)
+static __always_inline bool arch_static_branch(struct static_key *key)
 {
        asm goto("1:\n\t"
                 JUMP_LABEL_NOP "\n\t"
diff --git a/arch/arm/include/asm/mach/pci.h b/arch/arm/include/asm/mach/pci.h
index d943b7d20f11..26c511fddf8f 100644
--- a/arch/arm/include/asm/mach/pci.h
+++ b/arch/arm/include/asm/mach/pci.h
@@ -12,13 +12,14 @@
 #define __ASM_MACH_PCI_H
 struct pci_sys_data;
+struct pci_ops;
 struct pci_bus;
 struct hw_pci {
 #ifdef CONFIG_PCI_DOMAINS
        int             domain;
 #endif
-        struct list_head buses;
+        struct pci_ops  *ops;
        int             nr_controllers;
        int             (*setup)(int nr, struct pci_sys_data *);
        struct pci_bus *(*scan)(int nr, struct pci_sys_data *);
@@ -45,16 +46,10 @@ struct pci_sys_data {
        u8              (*swizzle)(struct pci_dev *, u8 *);
                                        /* IRQ mapping                          */
        int             (*map_irq)(const struct pci_dev *, u8, u8);
-        struct hw_pci   *hw;
        void            *private_data;  /* platform controller private data     */
 };
 /*
- * This is the standard PCI-PCI bridge swizzling algorithm.
- */
-#define pci_std_swizzle pci_common_swizzle
-/*
 * Call this with your hw_pci struct to initialise the PCI system.
 */
 void pci_common_init(struct hw_pci *);
@@ -62,22 +57,22 @@ void pci_common_init(struct hw_pci *);
 /*
 * PCI controllers
 */
+extern struct pci_ops iop3xx_ops;
 extern int iop3xx_pci_setup(int nr, struct pci_sys_data *);
-extern struct pci_bus *iop3xx_pci_scan_bus(int nr, struct pci_sys_data *);
 extern void iop3xx_pci_preinit(void);
 extern void iop3xx_pci_preinit_cond(void);
+extern struct pci_ops dc21285_ops;
 extern int dc21285_setup(int nr, struct pci_sys_data *);
-extern struct pci_bus *dc21285_scan_bus(int nr, struct pci_sys_data *);
 extern void dc21285_preinit(void);
 extern void dc21285_postinit(void);
+extern struct pci_ops via82c505_ops;
 extern int via82c505_setup(int nr, struct pci_sys_data *);
-extern struct pci_bus *via82c505_scan_bus(int nr, struct pci_sys_data *);
 extern void via82c505_init(void *sysdata);
+extern struct pci_ops pci_v3_ops;
 extern int pci_v3_setup(int nr, struct pci_sys_data *);
-extern struct pci_bus *pci_v3_scan_bus(int nr, struct pci_sys_data *);
 extern void pci_v3_preinit(void);
 extern void pci_v3_postinit(void);
diff --git a/arch/arm/include/asm/mach/time.h b/arch/arm/include/asm/mach/time.h
index f73c908b7fa0..6ca945f534ab 100644
--- a/arch/arm/include/asm/mach/time.h
+++ b/arch/arm/include/asm/mach/time.h
@@ -42,4 +42,9 @@ struct sys_timer {
 extern void timer_tick(void);
+struct timespec;
+typedef void (*clock_access_fn)(struct timespec *);
+extern int register_persistent_clock(clock_access_fn read_boot,
+                                     clock_access_fn read_persistent);
 #endif
diff --git a/arch/arm/include/asm/mmu.h b/arch/arm/include/asm/mmu.h
index b8e580a297e4..14965658a923 100644
--- a/arch/arm/include/asm/mmu.h
+++ b/arch/arm/include/asm/mmu.h
@@ -34,11 +34,4 @@ typedef struct {
 #endif
-/*
- * switch_mm() may do a full cache flush over the context switch,
- * so enable interrupts over the context switch to avoid high
- * latency.
- */
-#define __ARCH_WANT_INTERRUPTS_ON_CTXSW
 #endif
diff --git a/arch/arm/include/asm/mmu_context.h b/arch/arm/include/asm/mmu_context.h
index a0b3cac0547c..0306bc642c0d 100644
--- a/arch/arm/include/asm/mmu_context.h
+++ b/arch/arm/include/asm/mmu_context.h
@@ -43,45 +43,104 @@ void __check_kvm_seq(struct mm_struct *mm);
 #define ASID_FIRST_VERSION      (1 << ASID_BITS)
 extern unsigned int cpu_last_asid;
-#ifdef CONFIG_SMP
-DECLARE_PER_CPU(struct mm_struct *, current_mm);
-#endif
 void __init_new_context(struct task_struct *tsk, struct mm_struct *mm);
 void __new_context(struct mm_struct *mm);
+void cpu_set_reserved_ttbr0(void);
-static inline void check_context(struct mm_struct *mm)
+static inline void switch_new_context(struct mm_struct *mm)
 {
-        /*
+        unsigned long flags;
-         * This code is executed with interrupts enabled. Therefore,
-         * mm->context.id cannot be updated to the latest ASID version
+        __new_context(mm);
-         * on a different CPU (and condition below not triggered)
-         * without first getting an IPI to reset the context. The
+        local_irq_save(flags);
-         * alternative is to take a read_lock on mm->context.id_lock
+        cpu_switch_mm(mm->pgd, mm);
-         * (after changing its type to rwlock_t).
+        local_irq_restore(flags);
-         */
+}
-        if (unlikely((mm->context.id ^ cpu_last_asid) >> ASID_BITS))
-                __new_context(mm);
+static inline void check_and_switch_context(struct mm_struct *mm,
+                                            struct task_struct *tsk)
+{
        if (unlikely(mm->context.kvm_seq != init_mm.context.kvm_seq))
                __check_kvm_seq(mm);
+        /*
+         * Required during context switch to avoid speculative page table
+         * walking with the wrong TTBR.
+         */
+        cpu_set_reserved_ttbr0();
+        if (!((mm->context.id ^ cpu_last_asid) >> ASID_BITS))
+                /*
+                 * The ASID is from the current generation, just switch to the
+                 * new pgd. This condition is only true for calls from
+                 * context_switch() and interrupts are already disabled.
+                 */
+                cpu_switch_mm(mm->pgd, mm);
+        else if (irqs_disabled())
+                /*
+                 * Defer the new ASID allocation until after the context
+                 * switch critical region since __new_context() cannot be
+                 * called with interrupts disabled (it sends IPIs).
+                 */
+                set_ti_thread_flag(task_thread_info(tsk), TIF_SWITCH_MM);
+        else
+                /*
+                 * That is a direct call to switch_mm() or activate_mm() with
+                 * interrupts enabled and a new context.
+                 */
+                switch_new_context(mm);
 }
 #define init_new_context(tsk,mm)        (__init_new_context(tsk,mm),0)
-#else
+#define finish_arch_post_lock_switch \
+        finish_arch_post_lock_switch
-static inline void check_context(struct mm_struct *mm)
+static inline void finish_arch_post_lock_switch(void)
 {
+        if (test_and_clear_thread_flag(TIF_SWITCH_MM))
+                switch_new_context(current->mm);
+}
+#else   /* !CONFIG_CPU_HAS_ASID */
 #ifdef CONFIG_MMU
+static inline void check_and_switch_context(struct mm_struct *mm,
+                                            struct task_struct *tsk)
+{
        if (unlikely(mm->context.kvm_seq != init_mm.context.kvm_seq))
                __check_kvm_seq(mm);
-#endif
+        if (irqs_disabled())
+                /*
+                 * cpu_switch_mm() needs to flush the VIVT caches. To avoid
+                 * high interrupt latencies, defer the call and continue
+                 * running with the old mm. Since we only support UP systems
+                 * on non-ASID CPUs, the old mm will remain valid until the
+                 * finish_arch_post_lock_switch() call.
+                 */
+                set_ti_thread_flag(task_thread_info(tsk), TIF_SWITCH_MM);
+        else
+                cpu_switch_mm(mm->pgd, mm);
 }
+#define finish_arch_post_lock_switch \
+        finish_arch_post_lock_switch
+static inline void finish_arch_post_lock_switch(void)
+{
+        if (test_and_clear_thread_flag(TIF_SWITCH_MM)) {
+                struct mm_struct *mm = current->mm;
+                cpu_switch_mm(mm->pgd, mm);
+        }
+}
+#endif  /* CONFIG_MMU */
 #define init_new_context(tsk,mm)        0
-#endif
+#endif  /* CONFIG_CPU_HAS_ASID */
 #define destroy_context(mm)             do { } while(0)
@@ -119,12 +178,7 @@ switch_mm(struct mm_struct *prev, struct mm_struct *next,
                __flush_icache_all();
 #endif
        if (!cpumask_test_and_set_cpu(cpu, mm_cpumask(next)) || prev != next) {
-#ifdef CONFIG_SMP
+                check_and_switch_context(next, tsk);
-                struct mm_struct **crt_mm = &per_cpu(current_mm, cpu);
-                *crt_mm = next;
-#endif
-                check_context(next);
-                cpu_switch_mm(next->pgd, next);
                if (cache_is_vivt())
                        cpumask_clear_cpu(cpu, mm_cpumask(prev));
        }
diff --git a/arch/arm/include/asm/page.h b/arch/arm/include/asm/page.h
index 5838361c48b3..ecf901902e44 100644
--- a/arch/arm/include/asm/page.h
+++ b/arch/arm/include/asm/page.h
@@ -34,7 +34,6 @@
 *      processor(s) we're building for.
 *
 *      We have the following to choose from:
- *        v3            - ARMv3
 *        v4wt          - ARMv4 with writethrough cache, without minicache
 *        v4wb          - ARMv4 with writeback cache, without minicache
 *        v4_mc         - ARMv4 with minicache
@@ -44,14 +43,6 @@
 #undef _USER
 #undef MULTI_USER
-#ifdef CONFIG_CPU_COPY_V3
-# ifdef _USER
-#  define MULTI_USER 1
-# else
-#  define _USER v3
-# endif
-#endif
 #ifdef CONFIG_CPU_COPY_V4WT
 # ifdef _USER
 #  define MULTI_USER 1
diff --git a/arch/arm/include/asm/pgtable-3level.h b/arch/arm/include/asm/pgtable-3level.h
index 759af70f9a0a..b24903549d1c 100644
--- a/arch/arm/include/asm/pgtable-3level.h
+++ b/arch/arm/include/asm/pgtable-3level.h
@@ -69,8 +69,6 @@
 */
 #define L_PTE_PRESENT           (_AT(pteval_t, 3) << 0)         /* Valid */
 #define L_PTE_FILE              (_AT(pteval_t, 1) << 2)         /* only when !PRESENT */
-#define L_PTE_BUFFERABLE        (_AT(pteval_t, 1) << 2)         /* AttrIndx[0] */
-#define L_PTE_CACHEABLE         (_AT(pteval_t, 1) << 3)         /* AttrIndx[1] */
 #define L_PTE_USER              (_AT(pteval_t, 1) << 6)         /* AP[1] */
 #define L_PTE_RDONLY            (_AT(pteval_t, 1) << 7)         /* AP[2] */
 #define L_PTE_SHARED            (_AT(pteval_t, 3) << 8)         /* SH[1:0], inner shareable */
diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h
index 5ac8d3d3e025..d7038fa22343 100644
--- a/arch/arm/include/asm/processor.h
+++ b/arch/arm/include/asm/processor.h
@@ -88,8 +88,6 @@ unsigned long get_wchan(struct task_struct *p);
 #define cpu_relax()                     barrier()
 #endif
-void cpu_idle_wait(void);
 /*
 * Create a new kernel thread
 */
diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h
index 451808ba1211..355ece523f41 100644
--- a/arch/arm/include/asm/ptrace.h
+++ b/arch/arm/include/asm/ptrace.h
@@ -249,6 +249,11 @@ static inline unsigned long kernel_stack_pointer(struct pt_regs *regs)
        return regs->ARM_sp;
 }
+static inline unsigned long user_stack_pointer(struct pt_regs *regs)
+{
+        return regs->ARM_sp;
+}
 #endif /* __KERNEL__ */
 #endif /* __ASSEMBLY__ */
diff --git a/arch/arm/include/asm/syscall.h b/arch/arm/include/asm/syscall.h
new file mode 100644
index 000000000000..c334a23ddf75
--- /dev/null
+++ b/arch/arm/include/asm/syscall.h
@@ -0,0 +1,93 @@
+/*
+ * Access to user system call parameters and results
+ *
+ * See asm-generic/syscall.h for descriptions of what we must do here.
+ */
+#ifndef _ASM_ARM_SYSCALL_H
+#define _ASM_ARM_SYSCALL_H
+#include <linux/err.h>
+extern const unsigned long sys_call_table[];
+static inline int syscall_get_nr(struct task_struct *task,
+                                 struct pt_regs *regs)
+{
+        return task_thread_info(task)->syscall;
+}
+static inline void syscall_rollback(struct task_struct *task,
+                                    struct pt_regs *regs)
+{
+        regs->ARM_r0 = regs->ARM_ORIG_r0;
+}
+static inline long syscall_get_error(struct task_struct *task,
+                                     struct pt_regs *regs)
+{
+        unsigned long error = regs->ARM_r0;
+        return IS_ERR_VALUE(error) ? error : 0;
+}
+static inline long syscall_get_return_value(struct task_struct *task,
+                                            struct pt_regs *regs)
+{
+        return regs->ARM_r0;
+}
+static inline void syscall_set_return_value(struct task_struct *task,
+                                            struct pt_regs *regs,
+                                            int error, long val)
+{
+        regs->ARM_r0 = (long) error ? error : val;
+}
+#define SYSCALL_MAX_ARGS 7
+static inline void syscall_get_arguments(struct task_struct *task,
+                                         struct pt_regs *regs,
+                                         unsigned int i, unsigned int n,
+                                         unsigned long *args)
+{
+        if (i + n > SYSCALL_MAX_ARGS) {
+                unsigned long *args_bad = args + SYSCALL_MAX_ARGS - i;
+                unsigned int n_bad = n + i - SYSCALL_MAX_ARGS;
+                pr_warning("%s called with max args %d, handling only %d\n",
+                           __func__, i + n, SYSCALL_MAX_ARGS);
+                memset(args_bad, 0, n_bad * sizeof(args[0]));
+                n = SYSCALL_MAX_ARGS - i;
+        }
+        if (i == 0) {
+                args[0] = regs->ARM_ORIG_r0;
+                args++;
+                i++;
+                n--;
+        }
+        memcpy(args, &regs->ARM_r0 + i, n * sizeof(args[0]));
+}
+static inline void syscall_set_arguments(struct task_struct *task,
+                                         struct pt_regs *regs,
+                                         unsigned int i, unsigned int n,
+                                         const unsigned long *args)
+{
+        if (i + n > SYSCALL_MAX_ARGS) {
+                pr_warning("%s called with max args %d, handling only %d\n",
+                           __func__, i + n, SYSCALL_MAX_ARGS);
+                n = SYSCALL_MAX_ARGS - i;
+        }
+        if (i == 0) {
+                regs->ARM_ORIG_r0 = args[0];
+                args++;
+                i++;
+                n--;
+        }
+        memcpy(&regs->ARM_r0 + i, args, n * sizeof(args[0]));
+}
+#endif /* _ASM_ARM_SYSCALL_H */
diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h
index d4c24d412a8d..68388eb4946b 100644
--- a/arch/arm/include/asm/thread_info.h
+++ b/arch/arm/include/asm/thread_info.h
@@ -118,6 +118,13 @@ extern void iwmmxt_task_switch(struct thread_info *);
 extern void vfp_sync_hwstate(struct thread_info *);
 extern void vfp_flush_hwstate(struct thread_info *);
+struct user_vfp;
+struct user_vfp_exc;
+extern int vfp_preserve_user_clear_hwstate(struct user_vfp __user *,
+                                           struct user_vfp_exc __user *);
+extern int vfp_restore_user_hwstate(struct user_vfp __user *,
+                                    struct user_vfp_exc __user *);
 #endif
 /*
@@ -146,6 +153,7 @@ extern void vfp_flush_hwstate(struct thread_info *);
 #define TIF_MEMDIE              18      /* is terminating due to OOM killer */
 #define TIF_RESTORE_SIGMASK     20
 #define TIF_SECCOMP             21
+#define TIF_SWITCH_MM           22      /* deferred switch_mm */
 #define _TIF_SIGPENDING         (1 << TIF_SIGPENDING)
 #define _TIF_NEED_RESCHED       (1 << TIF_NEED_RESCHED)
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index 85fe61e73202..6e924d3a77eb 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -65,21 +65,6 @@
 #define MULTI_TLB 1
 #endif
-#define v3_tlb_flags    (TLB_V3_FULL | TLB_V3_PAGE)
-#ifdef CONFIG_CPU_TLB_V3
-# define v3_possible_flags      v3_tlb_flags
-# define v3_always_flags        v3_tlb_flags
-# ifdef _TLB
-#  define MULTI_TLB 1
-# else
-#  define _TLB v3
-# endif
-#else
-# define v3_possible_flags      0
-# define v3_always_flags        (-1UL)
-#endif
 #define v4_tlb_flags    (TLB_V4_U_FULL | TLB_V4_U_PAGE)
 #ifdef CONFIG_CPU_TLB_V4WT
@@ -298,8 +283,7 @@ extern struct cpu_tlb_fns cpu_tlb;
 * implemented the "%?" method, but this has been discontinued due to too
 * many people getting it wrong.
 */
-#define possible_tlb_flags      (v3_possible_flags | \
+#define possible_tlb_flags      (v4_possible_flags | \
-                                 v4_possible_flags | \
                                 v4wbi_possible_flags | \
                                 fr_possible_flags | \
                                 v4wb_possible_flags | \
@@ -307,8 +291,7 @@ extern struct cpu_tlb_fns cpu_tlb;
                                 v6wbi_possible_flags | \
                                 v7wbi_possible_flags)
-#define always_tlb_flags        (v3_always_flags & \
+#define always_tlb_flags        (v4_always_flags & \
-                                 v4_always_flags & \
                                 v4wbi_always_flags & \
                                 fr_always_flags & \
                                 v4wb_always_flags & \
diff --git a/arch/arm/include/asm/tls.h b/arch/arm/include/asm/tls.h
index 60843eb0f61c..73409e6c0251 100644
--- a/arch/arm/include/asm/tls.h
+++ b/arch/arm/include/asm/tls.h
@@ -7,6 +7,8 @@
        .macro set_tls_v6k, tp, tmp1, tmp2
        mcr     p15, 0, \tp, c13, c0, 3         @ set TLS register
+        mov     \tmp1, #0
+        mcr     p15, 0, \tmp1, c13, c0, 2       @ clear user r/w TLS register
        .endm
        .macro set_tls_v6, tp, tmp1, tmp2
@@ -15,6 +17,8 @@
        mov     \tmp2, #0xffff0fff
        tst     \tmp1, #HWCAP_TLS               @ hardware TLS available?
        mcrne   p15, 0, \tp, c13, c0, 3         @ yes, set TLS register
+        movne   \tmp1, #0
+        mcrne   p15, 0, \tmp1, c13, c0, 2       @ clear user r/w TLS register
        streq   \tp, [\tmp2, #-15]              @ set TLS value at 0xffff0ff0
        .endm
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 7b787d642af4..7ad2d5cf7008 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -34,6 +34,7 @@ obj-$(CONFIG_ARM_CPU_SUSPEND)	+= sleep.o suspend.o
 obj-$(CONFIG_SMP)               += smp.o smp_tlb.o
 obj-$(CONFIG_HAVE_ARM_SCU)      += smp_scu.o
 obj-$(CONFIG_HAVE_ARM_TWD)      += smp_twd.o
+obj-$(CONFIG_ARM_ARCH_TIMER)    += arch_timer.o
 obj-$(CONFIG_DYNAMIC_FTRACE)    += ftrace.o insn.o
 obj-$(CONFIG_FUNCTION_GRAPH_TRACER)     += ftrace.o insn.o
 obj-$(CONFIG_JUMP_LABEL)        += jump_label.o insn.o patch.o
@@ -81,4 +82,4 @@ head-y			:= head$(MMUEXT).o
 obj-$(CONFIG_DEBUG_LL)  += debug.o
 obj-$(CONFIG_EARLY_PRINTK)      += early_printk.o
-extra-y := $(head-y) init_task.o vmlinux.lds
+extra-y := $(head-y) vmlinux.lds
diff --git a/arch/arm/kernel/arch_timer.c b/arch/arm/kernel/arch_timer.c
new file mode 100644
index 000000000000..dd58035621f7
--- /dev/null
+++ b/arch/arm/kernel/arch_timer.c
@@ -0,0 +1,350 @@
+/*
+ *  linux/arch/arm/kernel/arch_timer.c
+ *
+ *  Copyright (C) 2011 ARM Ltd.
+ *  All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/smp.h>
+#include <linux/cpu.h>
+#include <linux/jiffies.h>
+#include <linux/clockchips.h>
+#include <linux/interrupt.h>
+#include <linux/of_irq.h>
+#include <linux/io.h>
+#include <asm/cputype.h>
+#include <asm/localtimer.h>
+#include <asm/arch_timer.h>
+#include <asm/system_info.h>
+#include <asm/sched_clock.h>
+static unsigned long arch_timer_rate;
+static int arch_timer_ppi;
+static int arch_timer_ppi2;
+static struct clock_event_device __percpu **arch_timer_evt;
+/*
+ * Architected system timer support.
+ */
+#define ARCH_TIMER_CTRL_ENABLE          (1 << 0)
+#define ARCH_TIMER_CTRL_IT_MASK         (1 << 1)
+#define ARCH_TIMER_CTRL_IT_STAT         (1 << 2)
+#define ARCH_TIMER_REG_CTRL             0
+#define ARCH_TIMER_REG_FREQ             1
+#define ARCH_TIMER_REG_TVAL             2
+static void arch_timer_reg_write(int reg, u32 val)
+{
+        switch (reg) {
+        case ARCH_TIMER_REG_CTRL:
+                asm volatile("mcr p15, 0, %0, c14, c2, 1" : : "r" (val));
+                break;
+        case ARCH_TIMER_REG_TVAL:
+                asm volatile("mcr p15, 0, %0, c14, c2, 0" : : "r" (val));
+                break;
+        }
+        isb();
+}
+static u32 arch_timer_reg_read(int reg)
+{
+        u32 val;
+        switch (reg) {
+        case ARCH_TIMER_REG_CTRL:
+                asm volatile("mrc p15, 0, %0, c14, c2, 1" : "=r" (val));
+                break;
+        case ARCH_TIMER_REG_FREQ:
+                asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (val));
+                break;
+        case ARCH_TIMER_REG_TVAL:
+                asm volatile("mrc p15, 0, %0, c14, c2, 0" : "=r" (val));
+                break;
+        default:
+                BUG();
+        }
+        return val;
+}
+static irqreturn_t arch_timer_handler(int irq, void *dev_id)
+{
+        struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
+        unsigned long ctrl;
+        ctrl = arch_timer_reg_read(ARCH_TIMER_REG_CTRL);
+        if (ctrl & ARCH_TIMER_CTRL_IT_STAT) {
+                ctrl |= ARCH_TIMER_CTRL_IT_MASK;
+                arch_timer_reg_write(ARCH_TIMER_REG_CTRL, ctrl);
+                evt->event_handler(evt);
+                return IRQ_HANDLED;
+        }
+        return IRQ_NONE;
+}
+static void arch_timer_disable(void)
+{
+        unsigned long ctrl;
+        ctrl = arch_timer_reg_read(ARCH_TIMER_REG_CTRL);
+        ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
+        arch_timer_reg_write(ARCH_TIMER_REG_CTRL, ctrl);
+}
+static void arch_timer_set_mode(enum clock_event_mode mode,
+                                struct clock_event_device *clk)
+{
+        switch (mode) {
+        case CLOCK_EVT_MODE_UNUSED:
+        case CLOCK_EVT_MODE_SHUTDOWN:
+                arch_timer_disable();
+                break;
+        default:
+                break;
+        }
+}
+static int arch_timer_set_next_event(unsigned long evt,
+                                     struct clock_event_device *unused)
+{
+        unsigned long ctrl;
+        ctrl = arch_timer_reg_read(ARCH_TIMER_REG_CTRL);
+        ctrl |= ARCH_TIMER_CTRL_ENABLE;
+        ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
+        arch_timer_reg_write(ARCH_TIMER_REG_TVAL, evt);
+        arch_timer_reg_write(ARCH_TIMER_REG_CTRL, ctrl);
+        return 0;
+}
+static int __cpuinit arch_timer_setup(struct clock_event_device *clk)
+{
+        /* Be safe... */
+        arch_timer_disable();
+        clk->features = CLOCK_EVT_FEAT_ONESHOT;
+        clk->name = "arch_sys_timer";
+        clk->rating = 450;
+        clk->set_mode = arch_timer_set_mode;
+        clk->set_next_event = arch_timer_set_next_event;
+        clk->irq = arch_timer_ppi;
+        clockevents_config_and_register(clk, arch_timer_rate,
+                                        0xf, 0x7fffffff);
+        *__this_cpu_ptr(arch_timer_evt) = clk;
+        enable_percpu_irq(clk->irq, 0);
+        if (arch_timer_ppi2)
+                enable_percpu_irq(arch_timer_ppi2, 0);
+        return 0;
+}
+/* Is the optional system timer available? */
+static int local_timer_is_architected(void)
+{
+        return (cpu_architecture() >= CPU_ARCH_ARMv7) &&
+               ((read_cpuid_ext(CPUID_EXT_PFR1) >> 16) & 0xf) == 1;
+}
+static int arch_timer_available(void)
+{
+        unsigned long freq;
+        if (!local_timer_is_architected())
+                return -ENXIO;
+        if (arch_timer_rate == 0) {
+                arch_timer_reg_write(ARCH_TIMER_REG_CTRL, 0);
+                freq = arch_timer_reg_read(ARCH_TIMER_REG_FREQ);
+                /* Check the timer frequency. */
+                if (freq == 0) {
+                        pr_warn("Architected timer frequency not available\n");
+                        return -EINVAL;
+                }
+                arch_timer_rate = freq;
+        }
+        pr_info_once("Architected local timer running at %lu.%02luMHz.\n",
+                     arch_timer_rate / 1000000, (arch_timer_rate / 10000) % 100);
+        return 0;
+}
+static inline cycle_t arch_counter_get_cntpct(void)
+{
+        u32 cvall, cvalh;
+        asm volatile("mrrc p15, 0, %0, %1, c14" : "=r" (cvall), "=r" (cvalh));
+        return ((cycle_t) cvalh << 32) | cvall;
+}
+static inline cycle_t arch_counter_get_cntvct(void)
+{
+        u32 cvall, cvalh;
+        asm volatile("mrrc p15, 1, %0, %1, c14" : "=r" (cvall), "=r" (cvalh));
+        return ((cycle_t) cvalh << 32) | cvall;
+}
+static u32 notrace arch_counter_get_cntvct32(void)
+{
+        cycle_t cntvct = arch_counter_get_cntvct();
+        /*
+         * The sched_clock infrastructure only knows about counters
+         * with at most 32bits. Forget about the upper 24 bits for the
+         * time being...
+         */
+        return (u32)(cntvct & (u32)~0);
+}
+static cycle_t arch_counter_read(struct clocksource *cs)
+{
+        return arch_counter_get_cntpct();
+}
+static struct clocksource clocksource_counter = {
+        .name   = "arch_sys_counter",
+        .rating = 400,
+        .read   = arch_counter_read,
+        .mask   = CLOCKSOURCE_MASK(56),
+        .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+static void __cpuinit arch_timer_stop(struct clock_event_device *clk)
+{
+        pr_debug("arch_timer_teardown disable IRQ%d cpu #%d\n",
+                 clk->irq, smp_processor_id());
+        disable_percpu_irq(clk->irq);
+        if (arch_timer_ppi2)
+                disable_percpu_irq(arch_timer_ppi2);
+        arch_timer_set_mode(CLOCK_EVT_MODE_UNUSED, clk);
+}
+static struct local_timer_ops arch_timer_ops __cpuinitdata = {
+        .setup  = arch_timer_setup,
+        .stop   = arch_timer_stop,
+};
+static struct clock_event_device arch_timer_global_evt;
+static int __init arch_timer_register(void)
+{
+        int err;
+        err = arch_timer_available();
+        if (err)
+                return err;
+        arch_timer_evt = alloc_percpu(struct clock_event_device *);
+        if (!arch_timer_evt)
+                return -ENOMEM;
+        clocksource_register_hz(&clocksource_counter, arch_timer_rate);
+        err = request_percpu_irq(arch_timer_ppi, arch_timer_handler,
+                                 "arch_timer", arch_timer_evt);
+        if (err) {
+                pr_err("arch_timer: can't register interrupt %d (%d)\n",
+                       arch_timer_ppi, err);
+                goto out_free;
+        }
+        if (arch_timer_ppi2) {
+                err = request_percpu_irq(arch_timer_ppi2, arch_timer_handler,
+                                         "arch_timer", arch_timer_evt);
+                if (err) {
+                        pr_err("arch_timer: can't register interrupt %d (%d)\n",
+                               arch_timer_ppi2, err);
+                        arch_timer_ppi2 = 0;
+                        goto out_free_irq;
+                }
+        }
+        err = local_timer_register(&arch_timer_ops);
+        if (err) {
+                /*
+                 * We couldn't register as a local timer (could be
+                 * because we're on a UP platform, or because some
+                 * other local timer is already present...). Try as a
+                 * global timer instead.
+                 */
+                arch_timer_global_evt.cpumask = cpumask_of(0);
+                err = arch_timer_setup(&arch_timer_global_evt);
+        }
+        if (err)
+                goto out_free_irq;
+        return 0;
+out_free_irq:
+        free_percpu_irq(arch_timer_ppi, arch_timer_evt);
+        if (arch_timer_ppi2)
+                free_percpu_irq(arch_timer_ppi2, arch_timer_evt);
+out_free:
+        free_percpu(arch_timer_evt);
+        return err;
+}
+static const struct of_device_id arch_timer_of_match[] __initconst = {
+        { .compatible   = "arm,armv7-timer",    },
+        {},
+};
+int __init arch_timer_of_register(void)
+{
+        struct device_node *np;
+        u32 freq;
+        np = of_find_matching_node(NULL, arch_timer_of_match);
+        if (!np) {
+                pr_err("arch_timer: can't find DT node\n");
+                return -ENODEV;
+        }
+        /* Try to determine the frequency from the device tree or CNTFRQ */
+        if (!of_property_read_u32(np, "clock-frequency", &freq))
+                arch_timer_rate = freq;
+        arch_timer_ppi = irq_of_parse_and_map(np, 0);
+        arch_timer_ppi2 = irq_of_parse_and_map(np, 1);
+        pr_info("arch_timer: found %s irqs %d %d\n",
+                np->name, arch_timer_ppi, arch_timer_ppi2);
+        return arch_timer_register();
+}
+int __init arch_timer_sched_clock_init(void)
+{
+        int err;
+        err = arch_timer_available();
+        if (err)
+                return err;
+        setup_sched_clock(arch_counter_get_cntvct32, 32, arch_timer_rate);
+        return 0;
+}
diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c
index ede5f7741c42..25552508c3fd 100644
--- a/arch/arm/kernel/bios32.c
+++ b/arch/arm/kernel/bios32.c
@@ -374,16 +374,29 @@ EXPORT_SYMBOL(pcibios_fixup_bus);
 #endif
 /*
- * Swizzle the device pin each time we cross a bridge.
+ * Swizzle the device pin each time we cross a bridge.  If a platform does
- * This might update pin and returns the slot number.
+ * not provide a swizzle function, we perform the standard PCI swizzling.
+ *
+ * The default swizzling walks up the bus tree one level at a time, applying
+ * the standard swizzle function at each step, stopping when it finds the PCI
+ * root bus.  This will return the slot number of the bridge device on the
+ * root bus and the interrupt pin on that device which should correspond
+ * with the downstream device interrupt.
+ *
+ * Platforms may override this, in which case the slot and pin returned
+ * depend entirely on the platform code.  However, please note that the
+ * PCI standard swizzle is implemented on plug-in cards and Cardbus based
+ * PCI extenders, so it can not be ignored.
 */
 static u8 __devinit pcibios_swizzle(struct pci_dev *dev, u8 *pin)
 {
        struct pci_sys_data *sys = dev->sysdata;
-        int slot = 0, oldpin = *pin;
+        int slot, oldpin = *pin;
        if (sys->swizzle)
                slot = sys->swizzle(dev, pin);
+        else
+                slot = pci_common_swizzle(dev, pin);
        if (debug_pci)
                printk("PCI: %s swizzling pin %d => pin %d slot %d\n",
@@ -410,7 +423,7 @@ static int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
        return irq;
 }
-static void __init pcibios_init_hw(struct hw_pci *hw)
+static void __init pcibios_init_hw(struct hw_pci *hw, struct list_head *head)
 {
        struct pci_sys_data *sys = NULL;
        int ret;
@@ -424,7 +437,6 @@ static void __init pcibios_init_hw(struct hw_pci *hw)
 #ifdef CONFIG_PCI_DOMAINS
                sys->domain  = hw->domain;
 #endif
-                sys->hw      = hw;
                sys->busnr   = busnr;
                sys->swizzle = hw->swizzle;
                sys->map_irq = hw->map_irq;
@@ -440,14 +452,18 @@ static void __init pcibios_init_hw(struct hw_pci *hw)
                                         &iomem_resource, sys->mem_offset);
                        }
-                        sys->bus = hw->scan(nr, sys);
+                        if (hw->scan)
+                                sys->bus = hw->scan(nr, sys);
+                        else
+                                sys->bus = pci_scan_root_bus(NULL, sys->busnr,
+                                                hw->ops, sys, &sys->resources);
                        if (!sys->bus)
                                panic("PCI: unable to scan bus!");
                        busnr = sys->bus->subordinate + 1;
-                        list_add(&sys->node, &hw->buses);
+                        list_add(&sys->node, head);
                } else {
                        kfree(sys);
                        if (ret < 0)
@@ -459,19 +475,18 @@ static void __init pcibios_init_hw(struct hw_pci *hw)
 void __init pci_common_init(struct hw_pci *hw)
 {
        struct pci_sys_data *sys;
+        LIST_HEAD(head);
-        INIT_LIST_HEAD(&hw->buses);
        pci_add_flags(PCI_REASSIGN_ALL_RSRC);
        if (hw->preinit)
                hw->preinit();
-        pcibios_init_hw(hw);
+        pcibios_init_hw(hw, &head);
        if (hw->postinit)
                hw->postinit();
        pci_fixup_irqs(pcibios_swizzle, pcibios_map_irq);
-        list_for_each_entry(sys, &hw->buses, node) {
+        list_for_each_entry(sys, &head, node) {
                struct pci_bus *bus = sys->bus;
                if (!pci_has_flag(PCI_PROBE_ONLY)) {
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 7fd3ad048da9..437f0c426517 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -556,10 +556,6 @@ call_fpe:
 #endif
        tst     r0, #0x08000000                 @ only CDP/CPRT/LDC/STC have bit 27
        tstne   r0, #0x04000000                 @ bit 26 set on both ARM and Thumb-2
-#if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710)
-        and     r8, r0, #0x0f000000             @ mask out op-code bits
-        teqne   r8, #0x0f000000                 @ SWI (ARM6/7 bug)?
-#endif
        moveq   pc, lr
        get_thread_info r10                     @ get current thread
        and     r8, r0, #0x00000f00             @ mask out CP number
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index 54ee265dd819..7bd2d3cb8957 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -335,20 +335,6 @@ ENDPROC(ftrace_stub)
 *-----------------------------------------------------------------------------
 */
-        /* If we're optimising for StrongARM the resulting code won't 
-           run on an ARM7 and we can save a couple of instructions.  
-                                                                --pb */
-#ifdef CONFIG_CPU_ARM710
-#define A710(code...) code
-.Larm710bug:
-        ldmia   sp, {r0 - lr}^                  @ Get calling r0 - lr
-        mov     r0, r0
-        add     sp, sp, #S_FRAME_SIZE
-        subs    pc, lr, #4
-#else
-#define A710(code...)
-#endif
        .align  5
 ENTRY(vector_swi)
        sub     sp, sp, #S_FRAME_SIZE
@@ -379,9 +365,6 @@ ENTRY(vector_swi)
        ldreq   r10, [lr, #-4]                  @ get SWI instruction
 #else
        ldr     r10, [lr, #-4]                  @ get SWI instruction
-  A710( and     ip, r10, #0x0f000000            @ check for SWI         )
-  A710( teq     ip, #0x0f000000                                         )
-  A710( bne     .Larm710bug                                             )
 #endif
 #ifdef CONFIG_CPU_ENDIAN_BE8
        rev     r10, r10                        @ little endian instruction
@@ -392,26 +375,15 @@ ENTRY(vector_swi)
        /*
         * Pure EABI user space always put syscall number into scno (r7).
         */
-  A710( ldr     ip, [lr, #-4]                   @ get SWI instruction   )
-  A710( and     ip, ip, #0x0f000000             @ check for SWI         )
-  A710( teq     ip, #0x0f000000                                         )
-  A710( bne     .Larm710bug                                             )
 #elif defined(CONFIG_ARM_THUMB)
        /* Legacy ABI only, possibly thumb mode. */
        tst     r8, #PSR_T_BIT                  @ this is SPSR from save_user_regs
        addne   scno, r7, #__NR_SYSCALL_BASE    @ put OS number in
        ldreq   scno, [lr, #-4]
 #else
        /* Legacy ABI only. */
        ldr     scno, [lr, #-4]                 @ get SWI instruction
-  A710( and     ip, scno, #0x0f000000           @ check for SWI         )
-  A710( teq     ip, #0x0f000000                                         )
-  A710( bne     .Larm710bug                                             )
 #endif
 #ifdef CONFIG_ALIGNMENT_TRAP
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 3bf0c7f8b043..835898e7d704 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -277,10 +277,6 @@ __create_page_tables:
        mov     r3, r3, lsl #PMD_ORDER
        add     r0, r4, r3
-        rsb     r3, r3, #0x4000                 @ PTRS_PER_PGD*sizeof(long)
-        cmp     r3, #0x0800                     @ limit to 512MB
-        movhi   r3, #0x0800
-        add     r6, r0, r3
        mov     r3, r7, lsr #SECTION_SHIFT
        ldr     r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
        orr     r3, r7, r3, lsl #SECTION_SHIFT
@@ -289,13 +285,10 @@ __create_page_tables:
 #else
        orr     r3, r3, #PMD_SECT_XN
 #endif
-1:      str     r3, [r0], #4
+        str     r3, [r0], #4
 #ifdef CONFIG_ARM_LPAE
        str     r7, [r0], #4
 #endif
-        add     r3, r3, #1 << SECTION_SHIFT
-        cmp     r0, r6
-        blo     1b
 #else /* CONFIG_DEBUG_ICEDCC || CONFIG_DEBUG_SEMIHOSTING */
        /* we don't need any serial debugging mappings */
diff --git a/arch/arm/kernel/init_task.c b/arch/arm/kernel/init_task.c
deleted file mode 100644
index e7cbb50dc356..000000000000
--- a/arch/arm/kernel/init_task.c
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- *  linux/arch/arm/kernel/init_task.c
- */
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/fs.h>
-#include <linux/sched.h>
-#include <linux/init.h>
-#include <linux/init_task.h>
-#include <linux/mqueue.h>
-#include <linux/uaccess.h>
-#include <asm/pgtable.h>
-static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
-static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
-/*
- * Initial thread structure.
- *
- * We need to make sure that this is 8192-byte aligned due to the
- * way process stacks are handled. This is done by making sure
- * the linker maps this in the .text segment right after head.S,
- * and making head.S ensure the proper alignment.
- *
- * The things we do for performance..
- */
-union thread_union init_thread_union __init_task_data =
-        { INIT_THREAD_INFO(init_task) };
-/*
- * Initial task structure.
- *
- * All other task structs will be allocated on slabs in fork.c
- */
-struct task_struct init_task = INIT_TASK(init_task);
-EXPORT_SYMBOL(init_task);
diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c
index 71ccdbfed662..8349d4e97e2b 100644
--- a/arch/arm/kernel/irq.c
+++ b/arch/arm/kernel/irq.c
@@ -155,10 +155,10 @@ static bool migrate_one_irq(struct irq_desc *desc)
        }
        c = irq_data_get_irq_chip(d);
-        if (c->irq_set_affinity)
+        if (!c->irq_set_affinity)
-                c->irq_set_affinity(d, affinity, true);
-        else
                pr_debug("IRQ%u: unable to set affinity\n", d->irq);
+        else if (c->irq_set_affinity(d, affinity, true) == IRQ_SET_MASK_OK && ret)
+                cpumask_copy(d->affinity, affinity);
        return ret;
 }
diff --git a/arch/arm/kernel/perf_event_v6.c b/arch/arm/kernel/perf_event_v6.c
index b78af0cc6ef3..ab627a740fa3 100644
--- a/arch/arm/kernel/perf_event_v6.c
+++ b/arch/arm/kernel/perf_event_v6.c
@@ -489,8 +489,6 @@ armv6pmu_handle_irq(int irq_num,
         */
        armv6_pmcr_write(pmcr);
-        perf_sample_data_init(&data, 0);
        cpuc = &__get_cpu_var(cpu_hw_events);
        for (idx = 0; idx < cpu_pmu->num_events; ++idx) {
                struct perf_event *event = cpuc->events[idx];
@@ -509,7 +507,7 @@ armv6pmu_handle_irq(int irq_num,
                hwc = &event->hw;
                armpmu_event_update(event, hwc, idx);
-                data.period = event->hw.last_period;
+                perf_sample_data_init(&data, 0, hwc->last_period);
                if (!armpmu_event_set_period(event, hwc, idx))
                        continue;
diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c
index 00755d82e2f2..d3c536068162 100644
--- a/arch/arm/kernel/perf_event_v7.c
+++ b/arch/arm/kernel/perf_event_v7.c
@@ -1077,8 +1077,6 @@ static irqreturn_t armv7pmu_handle_irq(int irq_num, void *dev)
         */
        regs = get_irq_regs();
-        perf_sample_data_init(&data, 0);
        cpuc = &__get_cpu_var(cpu_hw_events);
        for (idx = 0; idx < cpu_pmu->num_events; ++idx) {
                struct perf_event *event = cpuc->events[idx];
@@ -1097,7 +1095,7 @@ static irqreturn_t armv7pmu_handle_irq(int irq_num, void *dev)
                hwc = &event->hw;
                armpmu_event_update(event, hwc, idx);
-                data.period = event->hw.last_period;
+                perf_sample_data_init(&data, 0, hwc->last_period);
                if (!armpmu_event_set_period(event, hwc, idx))
                        continue;
diff --git a/arch/arm/kernel/perf_event_xscale.c b/arch/arm/kernel/perf_event_xscale.c
index 71a21e6712f5..e34e7254e652 100644
--- a/arch/arm/kernel/perf_event_xscale.c
+++ b/arch/arm/kernel/perf_event_xscale.c
@@ -248,8 +248,6 @@ xscale1pmu_handle_irq(int irq_num, void *dev)
        regs = get_irq_regs();
-        perf_sample_data_init(&data, 0);
        cpuc = &__get_cpu_var(cpu_hw_events);
        for (idx = 0; idx < cpu_pmu->num_events; ++idx) {
                struct perf_event *event = cpuc->events[idx];
@@ -263,7 +261,7 @@ xscale1pmu_handle_irq(int irq_num, void *dev)
                hwc = &event->hw;
                armpmu_event_update(event, hwc, idx);
-                data.period = event->hw.last_period;
+                perf_sample_data_init(&data, 0, hwc->last_period);
                if (!armpmu_event_set_period(event, hwc, idx))
                        continue;
@@ -588,8 +586,6 @@ xscale2pmu_handle_irq(int irq_num, void *dev)
        regs = get_irq_regs();
-        perf_sample_data_init(&data, 0);
        cpuc = &__get_cpu_var(cpu_hw_events);
        for (idx = 0; idx < cpu_pmu->num_events; ++idx) {
                struct perf_event *event = cpuc->events[idx];
@@ -603,7 +599,7 @@ xscale2pmu_handle_irq(int irq_num, void *dev)
                hwc = &event->hw;
                armpmu_event_update(event, hwc, idx);
-                data.period = event->hw.last_period;
+                perf_sample_data_init(&data, 0, hwc->last_period);
                if (!armpmu_event_set_period(event, hwc, idx))
                        continue;
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 2b7b017a20cd..19c95ea65b2f 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -157,26 +157,6 @@ EXPORT_SYMBOL(pm_power_off);
 void (*arm_pm_restart)(char str, const char *cmd) = null_restart;
 EXPORT_SYMBOL_GPL(arm_pm_restart);
-static void do_nothing(void *unused)
-{
-}
-/*
- * cpu_idle_wait - Used to ensure that all the CPUs discard old value of
- * pm_idle and update to new pm_idle value. Required while changing pm_idle
- * handler on SMP systems.
- *
- * Caller must have changed pm_idle to the new value before the call. Old
- * pm_idle value will not be used by any CPU after the return of this function.
- */
-void cpu_idle_wait(void)
-{
-        smp_mb();
-        /* kick all the CPUs so that they exit out of pm_idle */
-        smp_call_function(do_nothing, NULL, 1);
-}
-EXPORT_SYMBOL_GPL(cpu_idle_wait);
 /*
 * This is our default idle handler.
 */
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index 80abafb9bf33..14e38261cd31 100644
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -24,6 +24,7 @@
 #include <linux/hw_breakpoint.h>
 #include <linux/regset.h>
 #include <linux/audit.h>
+#include <linux/tracehook.h>
 #include <asm/pgtable.h>
 #include <asm/traps.h>
@@ -906,49 +907,33 @@ long arch_ptrace(struct task_struct *child, long request,
        return ret;
 }
-#ifdef __ARMEB__
-#define AUDIT_ARCH_NR AUDIT_ARCH_ARMEB
-#else
-#define AUDIT_ARCH_NR AUDIT_ARCH_ARM
-#endif
 asmlinkage int syscall_trace(int why, struct pt_regs *regs, int scno)
 {
        unsigned long ip;
-        /*
+        if (why)
-         * Save IP.  IP is used to denote syscall entry/exit:
-         *  IP = 0 -> entry, = 1 -> exit
-         */
-        ip = regs->ARM_ip;
-        regs->ARM_ip = why;
-        if (!ip)
                audit_syscall_exit(regs);
        else
-                audit_syscall_entry(AUDIT_ARCH_NR, scno, regs->ARM_r0,
+                audit_syscall_entry(AUDIT_ARCH_ARM, scno, regs->ARM_r0,
                                    regs->ARM_r1, regs->ARM_r2, regs->ARM_r3);
        if (!test_thread_flag(TIF_SYSCALL_TRACE))
                return scno;
-        if (!(current->ptrace & PT_PTRACED))
-                return scno;
        current_thread_info()->syscall = scno;
-        /* the 0x80 provides a way for the tracing parent to distinguish
-           between a syscall stop and SIGTRAP delivery */
-        ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD)
-                                 ? 0x80 : 0));
        /*
-         * this isn't the same as continuing with a signal, but it will do
+         * IP is used to denote syscall entry/exit:
-         * for normal use.  strace only continues with a signal if the
+         * IP = 0 -> entry, =1 -> exit
-         * stopping signal is not SIGTRAP.  -brl
         */
-        if (current->exit_code) {
+        ip = regs->ARM_ip;
-                send_sig(current->exit_code, current, 1);
+        regs->ARM_ip = why;
-                current->exit_code = 0;
-        }
+        if (why)
+                tracehook_report_syscall_exit(regs, 0);
+        else if (tracehook_report_syscall_entry(regs))
+                current_thread_info()->syscall = -1;
        regs->ARM_ip = ip;
        return current_thread_info()->syscall;
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index b91411371ae1..ebfac782593f 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -523,7 +523,21 @@ int __init arm_add_memory(phys_addr_t start, unsigned long size)
         */
        size -= start & ~PAGE_MASK;
        bank->start = PAGE_ALIGN(start);
-        bank->size  = size & PAGE_MASK;
+#ifndef CONFIG_LPAE
+        if (bank->start + size < bank->start) {
+                printk(KERN_CRIT "Truncating memory at 0x%08llx to fit in "
+                        "32-bit physical address space\n", (long long)start);
+                /*
+                 * To ensure bank->start + bank->size is representable in
+                 * 32 bits, we use ULONG_MAX as the upper limit rather than 4GB.
+                 * This means we lose a page after masking.
+                 */
+                size = ULONG_MAX - bank->start;
+        }
+#endif
+        bank->size = size & PAGE_MASK;
        /*
         * Check whether this memory region has non-zero size or
diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c
index 7cb532fc8aa4..73d9a420850d 100644
--- a/arch/arm/kernel/signal.c
+++ b/arch/arm/kernel/signal.c
@@ -180,44 +180,23 @@ static int restore_iwmmxt_context(struct iwmmxt_sigframe *frame)
 static int preserve_vfp_context(struct vfp_sigframe __user *frame)
 {
-        struct thread_info *thread = current_thread_info();
-        struct vfp_hard_struct *h = &thread->vfpstate.hard;
        const unsigned long magic = VFP_MAGIC;
        const unsigned long size = VFP_STORAGE_SIZE;
        int err = 0;
-        vfp_sync_hwstate(thread);
        __put_user_error(magic, &frame->magic, err);
        __put_user_error(size, &frame->size, err);
-        /*
+        if (err)
-         * Copy the floating point registers. There can be unused
+                return -EFAULT;
-         * registers see asm/hwcap.h for details.
-         */
-        err |= __copy_to_user(&frame->ufp.fpregs, &h->fpregs,
-                              sizeof(h->fpregs));
-        /*
-         * Copy the status and control register.
-         */
-        __put_user_error(h->fpscr, &frame->ufp.fpscr, err);
-        /*
-         * Copy the exception registers.
-         */
-        __put_user_error(h->fpexc, &frame->ufp_exc.fpexc, err);
-        __put_user_error(h->fpinst, &frame->ufp_exc.fpinst, err);
-        __put_user_error(h->fpinst2, &frame->ufp_exc.fpinst2, err);
-        return err ? -EFAULT : 0;
+        return vfp_preserve_user_clear_hwstate(&frame->ufp, &frame->ufp_exc);
 }
 static int restore_vfp_context(struct vfp_sigframe __user *frame)
 {
-        struct thread_info *thread = current_thread_info();
-        struct vfp_hard_struct *h = &thread->vfpstate.hard;
        unsigned long magic;
        unsigned long size;
-        unsigned long fpexc;
        int err = 0;
        __get_user_error(magic, &frame->magic, err);
@@ -228,33 +207,7 @@ static int restore_vfp_context(struct vfp_sigframe __user *frame)
        if (magic != VFP_MAGIC || size != VFP_STORAGE_SIZE)
                return -EINVAL;
-        vfp_flush_hwstate(thread);
+        return vfp_restore_user_hwstate(&frame->ufp, &frame->ufp_exc);
-        /*
-         * Copy the floating point registers. There can be unused
-         * registers see asm/hwcap.h for details.
-         */
-        err |= __copy_from_user(&h->fpregs, &frame->ufp.fpregs,
-                                sizeof(h->fpregs));
-        /*
-         * Copy the status and control register.
-         */
-        __get_user_error(h->fpscr, &frame->ufp.fpscr, err);
-        /*
-         * Sanitise and restore the exception registers.
-         */
-        __get_user_error(fpexc, &frame->ufp_exc.fpexc, err);
-        /* Ensure the VFP is enabled. */
-        fpexc |= FPEXC_EN;
-        /* Ensure FPINST2 is invalid and the exception flag is cleared. */
-        fpexc &= ~(FPEXC_EX | FPEXC_FP2V);
-        h->fpexc = fpexc;
-        __get_user_error(h->fpinst, &frame->ufp_exc.fpinst, err);
-        __get_user_error(h->fpinst2, &frame->ufp_exc.fpinst2, err);
-        return err ? -EFAULT : 0;
 }
 #endif
@@ -636,6 +589,8 @@ handle_signal(unsigned long sig, struct k_sigaction *ka,
         */
        block_sigmask(ka, sig);
+        tracehook_signal_handler(sig, info, ka, regs, 0);
        return 0;
 }
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index addbbe8028c2..b735521a4a54 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -60,32 +60,11 @@ enum ipi_msg_type {
 static DECLARE_COMPLETION(cpu_running);
-int __cpuinit __cpu_up(unsigned int cpu)
+int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *idle)
 {
-        struct cpuinfo_arm *ci = &per_cpu(cpu_data, cpu);
-        struct task_struct *idle = ci->idle;
        int ret;
        /*
-         * Spawn a new process manually, if not already done.
-         * Grab a pointer to its task struct so we can mess with it
-         */
-        if (!idle) {
-                idle = fork_idle(cpu);
-                if (IS_ERR(idle)) {
-                        printk(KERN_ERR "CPU%u: fork() failed\n", cpu);
-                        return PTR_ERR(idle);
-                }
-                ci->idle = idle;
-        } else {
-                /*
-                 * Since this idle thread is being re-used, call
-                 * init_idle() to reinitialize the thread structure.
-                 */
-                init_idle(idle, cpu);
-        }
-        /*
         * We need to tell the secondary core where to find
         * its stack and the page tables.
         */
@@ -251,8 +230,6 @@ asmlinkage void __cpuinit secondary_start_kernel(void)
        struct mm_struct *mm = &init_mm;
        unsigned int cpu = smp_processor_id();
-        printk("CPU%u: Booted secondary processor\n", cpu);
        /*
         * All kernel threads share the same mm context; grab a
         * reference and switch to it.
@@ -264,6 +241,8 @@ asmlinkage void __cpuinit secondary_start_kernel(void)
        enter_lazy_tlb(mm, current);
        local_flush_tlb_all();
+        printk("CPU%u: Booted secondary processor\n", cpu);
        cpu_init();
        preempt_disable();
        trace_hardirqs_off();
@@ -318,9 +297,6 @@ void __init smp_cpus_done(unsigned int max_cpus)
 void __init smp_prepare_boot_cpu(void)
 {
-        unsigned int cpu = smp_processor_id();
-        per_cpu(cpu_data, cpu).idle = current;
 }
 void __init smp_prepare_cpus(unsigned int max_cpus)
@@ -454,6 +430,9 @@ static struct local_timer_ops *lt_ops;
 #ifdef CONFIG_LOCAL_TIMERS
 int local_timer_register(struct local_timer_ops *ops)
 {
+        if (!is_smp() || !setup_max_cpus)
+                return -ENXIO;
        if (lt_ops)
                return -EBUSY;
@@ -510,10 +489,6 @@ static void ipi_cpu_stop(unsigned int cpu)
        local_fiq_disable();
        local_irq_disable();
-#ifdef CONFIG_HOTPLUG_CPU
-        platform_cpu_kill(cpu);
-#endif
        while (1)
                cpu_relax();
 }
@@ -576,17 +551,25 @@ void smp_send_reschedule(int cpu)
        smp_cross_call(cpumask_of(cpu), IPI_RESCHEDULE);
 }
+#ifdef CONFIG_HOTPLUG_CPU
+static void smp_kill_cpus(cpumask_t *mask)
+{
+        unsigned int cpu;
+        for_each_cpu(cpu, mask)
+                platform_cpu_kill(cpu);
+}
+#else
+static void smp_kill_cpus(cpumask_t *mask) { }
+#endif
 void smp_send_stop(void)
 {
        unsigned long timeout;
+        struct cpumask mask;
-        if (num_online_cpus() > 1) {
+        cpumask_copy(&mask, cpu_online_mask);
-                struct cpumask mask;
+        cpumask_clear_cpu(smp_processor_id(), &mask);
-                cpumask_copy(&mask, cpu_online_mask);
+        smp_cross_call(&mask, IPI_CPU_STOP);
-                cpumask_clear_cpu(smp_processor_id(), &mask);
-                smp_cross_call(&mask, IPI_CPU_STOP);
-        }
        /* Wait up to one second for other CPUs to stop */
        timeout = USEC_PER_SEC;
@@ -595,6 +578,8 @@ void smp_send_stop(void)
        if (num_online_cpus() > 1)
                pr_warning("SMP: failed to stop secondary CPUs\n");
+        smp_kill_cpus(&mask);
 }
 /*
diff --git a/arch/arm/kernel/smp_scu.c b/arch/arm/kernel/smp_scu.c
index 8f5dd7963356..b9f015e843d8 100644
--- a/arch/arm/kernel/smp_scu.c
+++ b/arch/arm/kernel/smp_scu.c
@@ -11,6 +11,7 @@
 #include <linux/init.h>
 #include <linux/io.h>
+#include <asm/smp_plat.h>
 #include <asm/smp_scu.h>
 #include <asm/cacheflush.h>
 #include <asm/cputype.h>
@@ -74,7 +75,7 @@ void scu_enable(void __iomem *scu_base)
 int scu_power_mode(void __iomem *scu_base, unsigned int mode)
 {
        unsigned int val;
-        int cpu = smp_processor_id();
+        int cpu = cpu_logical_map(smp_processor_id());
        if (mode > 3 || mode == 1 || cpu > 3)
                return -EINVAL;
diff --git a/arch/arm/kernel/sys_arm.c b/arch/arm/kernel/sys_arm.c
index d2b177905cdb..76cbb055dd05 100644
--- a/arch/arm/kernel/sys_arm.c
+++ b/arch/arm/kernel/sys_arm.c
@@ -115,7 +115,7 @@ int kernel_execve(const char *filename,
                  "Ir" (THREAD_START_SP - sizeof(regs)),
                  "r" (&regs),
                  "Ir" (sizeof(regs))
-                : "r0", "r1", "r2", "r3", "ip", "lr", "memory");
+                : "r0", "r1", "r2", "r3", "r8", "r9", "ip", "lr", "memory");
 out:
        return ret;
diff --git a/arch/arm/kernel/thumbee.c b/arch/arm/kernel/thumbee.c
index aab899764053..7b8403b76666 100644
--- a/arch/arm/kernel/thumbee.c
+++ b/arch/arm/kernel/thumbee.c
@@ -20,6 +20,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <asm/cputype.h>
 #include <asm/system_info.h>
 #include <asm/thread_notify.h>
@@ -67,8 +68,7 @@ static int __init thumbee_init(void)
        if (cpu_arch < CPU_ARCH_ARMv7)
                return 0;
-        /* processor feature register 0 */
+        pfr0 = read_cpuid_ext(CPUID_EXT_PFR0);
-        asm("mrc        p15, 0, %0, c0, c1, 0\n" : "=r" (pfr0));
        if ((pfr0 & 0x0000f000) != 0x00001000)
                return 0;
diff --git a/arch/arm/kernel/time.c b/arch/arm/kernel/time.c
index fe31b22f18fd..af2afb019672 100644
--- a/arch/arm/kernel/time.c
+++ b/arch/arm/kernel/time.c
@@ -110,6 +110,42 @@ void timer_tick(void)
 }
 #endif
+static void dummy_clock_access(struct timespec *ts)
+{
+        ts->tv_sec = 0;
+        ts->tv_nsec = 0;
+}
+static clock_access_fn __read_persistent_clock = dummy_clock_access;
+static clock_access_fn __read_boot_clock = dummy_clock_access;;
+void read_persistent_clock(struct timespec *ts)
+{
+        __read_persistent_clock(ts);
+}
+void read_boot_clock(struct timespec *ts)
+{
+        __read_boot_clock(ts);
+}
+int __init register_persistent_clock(clock_access_fn read_boot,
+                                     clock_access_fn read_persistent)
+{
+        /* Only allow the clockaccess functions to be registered once */
+        if (__read_persistent_clock == dummy_clock_access &&
+            __read_boot_clock == dummy_clock_access) {
+                if (read_boot)
+                        __read_boot_clock = read_boot;
+                if (read_persistent)
+                        __read_persistent_clock = read_persistent;
+                return 0;
+        }
+        return -EINVAL;
+}
 #if defined(CONFIG_PM) && !defined(CONFIG_GENERIC_CLOCKEVENTS)
 static int timer_suspend(void)
 {
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index 778454750a6c..3647170e9a16 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -479,14 +479,14 @@ static int bad_syscall(int n, struct pt_regs *regs)
        return regs->ARM_r0;
 }
-static inline void
+static inline int
 do_cache_op(unsigned long start, unsigned long end, int flags)
 {
        struct mm_struct *mm = current->active_mm;
        struct vm_area_struct *vma;
        if (end < start || flags)
-                return;
+                return -EINVAL;
        down_read(&mm->mmap_sem);
        vma = find_vma(mm, start);
@@ -496,9 +496,11 @@ do_cache_op(unsigned long start, unsigned long end, int flags)
                if (end > vma->vm_end)
                        end = vma->vm_end;
-                flush_cache_user_range(vma, start, end);
+                up_read(&mm->mmap_sem);
+                return flush_cache_user_range(start, end);
        }
        up_read(&mm->mmap_sem);
+        return -EINVAL;
 }
 /*
@@ -544,8 +546,7 @@ asmlinkage int arm_syscall(int no, struct pt_regs *regs)
         * the specified region).
         */
        case NR(cacheflush):
-                do_cache_op(regs->ARM_r0, regs->ARM_r1, regs->ARM_r2);
+                return do_cache_op(regs->ARM_r0, regs->ARM_r1, regs->ARM_r2);
-                return 0;
        case NR(usr26):
                if (!(elf_hwcap & HWCAP_26BIT))
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 0ade0acc1ed9..992769ae2599 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -17,30 +17,13 @@ lib-y		:= backtrace.o changebit.o csumipv6.o csumpartial.o   \
                   call_with_stack.o
 mmu-y   := clear_user.o copy_page.o getuser.o putuser.o
+mmu-y   += copy_from_user.o copy_to_user.o
-# the code in uaccess.S is not preemption safe and
-# probably faster on ARMv3 only
-ifeq ($(CONFIG_PREEMPT),y)
-  mmu-y += copy_from_user.o copy_to_user.o
-else
-ifneq ($(CONFIG_CPU_32v3),y)
-  mmu-y += copy_from_user.o copy_to_user.o
-else
-  mmu-y += uaccess.o
-endif
-endif
 # using lib_ here won't override already available weak symbols
 obj-$(CONFIG_UACCESS_WITH_MEMCPY) += uaccess_with_memcpy.o
-lib-$(CONFIG_MMU) += $(mmu-y)
+lib-$(CONFIG_MMU)               += $(mmu-y)
+lib-y                           += io-readsw-armv4.o io-writesw-armv4.o
-ifeq ($(CONFIG_CPU_32v3),y)
-  lib-y += io-readsw-armv3.o io-writesw-armv3.o
-else
-  lib-y += io-readsw-armv4.o io-writesw-armv4.o
-endif
 lib-$(CONFIG_ARCH_RPC)          += ecard.o io-acorn.o floppydma.o
 lib-$(CONFIG_ARCH_SHARK)        += io-shark.o
diff --git a/arch/arm/lib/io-readsw-armv3.S b/arch/arm/lib/io-readsw-armv3.S
deleted file mode 100644
index 88487c8c4f23..000000000000
--- a/arch/arm/lib/io-readsw-armv3.S
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
- *  linux/arch/arm/lib/io-readsw-armv3.S
- *
- *  Copyright (C) 1995-2000 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/linkage.h>
-#include <asm/assembler.h>
-.Linsw_bad_alignment:
-                adr     r0, .Linsw_bad_align_msg
-                mov     r2, lr
-                b       panic
-.Linsw_bad_align_msg:
-                .asciz  "insw: bad buffer alignment (0x%p, lr=0x%08lX)\n"
-                .align
-.Linsw_align:   tst     r1, #1
-                bne     .Linsw_bad_alignment
-                ldr     r3, [r0]
-                strb    r3, [r1], #1
-                mov     r3, r3, lsr #8
-                strb    r3, [r1], #1
-                subs    r2, r2, #1
-                moveq   pc, lr
-ENTRY(__raw_readsw)
-                teq     r2, #0          @ do we have to check for the zero len?
-                moveq   pc, lr
-                tst     r1, #3
-                bne     .Linsw_align
-.Linsw_aligned: mov     ip, #0xff
-                orr     ip, ip, ip, lsl #8
-                stmfd   sp!, {r4, r5, r6, lr}
-                subs    r2, r2, #8
-                bmi     .Lno_insw_8
-.Linsw_8_lp:    ldr     r3, [r0]
-                and     r3, r3, ip
-                ldr     r4, [r0]
-                orr     r3, r3, r4, lsl #16
-                ldr     r4, [r0]
-                and     r4, r4, ip
-                ldr     r5, [r0]
-                orr     r4, r4, r5, lsl #16
-                ldr     r5, [r0]
-                and     r5, r5, ip
-                ldr     r6, [r0]
-                orr     r5, r5, r6, lsl #16
-                ldr     r6, [r0]
-                and     r6, r6, ip
-                ldr     lr, [r0]
-                orr     r6, r6, lr, lsl #16
-                stmia   r1!, {r3 - r6}
-                subs    r2, r2, #8
-                bpl     .Linsw_8_lp
-                tst     r2, #7
-                ldmeqfd sp!, {r4, r5, r6, pc}
-.Lno_insw_8:    tst     r2, #4
-                beq     .Lno_insw_4
-                ldr     r3, [r0]
-                and     r3, r3, ip
-                ldr     r4, [r0]
-                orr     r3, r3, r4, lsl #16
-                ldr     r4, [r0]
-                and     r4, r4, ip
-                ldr     r5, [r0]
-                orr     r4, r4, r5, lsl #16
-                stmia   r1!, {r3, r4}
-.Lno_insw_4:    tst     r2, #2
-                beq     .Lno_insw_2
-                ldr     r3, [r0]
-                and     r3, r3, ip
-                ldr     r4, [r0]
-                orr     r3, r3, r4, lsl #16
-                str     r3, [r1], #4
-.Lno_insw_2:    tst     r2, #1
-                ldrne   r3, [r0]
-                strneb  r3, [r1], #1
-                movne   r3, r3, lsr #8
-                strneb  r3, [r1]
-                ldmfd   sp!, {r4, r5, r6, pc}
diff --git a/arch/arm/lib/io-writesw-armv3.S b/arch/arm/lib/io-writesw-armv3.S
deleted file mode 100644
index 49b800419e32..000000000000
--- a/arch/arm/lib/io-writesw-armv3.S
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- *  linux/arch/arm/lib/io-writesw-armv3.S
- *
- *  Copyright (C) 1995-2000 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/linkage.h>
-#include <asm/assembler.h>
-.Loutsw_bad_alignment:
-                adr     r0, .Loutsw_bad_align_msg
-                mov     r2, lr
-                b       panic
-.Loutsw_bad_align_msg:
-                .asciz  "outsw: bad buffer alignment (0x%p, lr=0x%08lX)\n"
-                .align
-.Loutsw_align:  tst     r1, #1
-                bne     .Loutsw_bad_alignment
-                add     r1, r1, #2
-                ldr     r3, [r1, #-4]
-                mov     r3, r3, lsr #16
-                orr     r3, r3, r3, lsl #16
-                str     r3, [r0]
-                subs    r2, r2, #1
-                moveq   pc, lr
-ENTRY(__raw_writesw)
-                teq     r2, #0          @ do we have to check for the zero len?
-                moveq   pc, lr
-                tst     r1, #3
-                bne     .Loutsw_align
-                stmfd   sp!, {r4, r5, r6, lr}
-                subs    r2, r2, #8
-                bmi     .Lno_outsw_8
-.Loutsw_8_lp:   ldmia   r1!, {r3, r4, r5, r6}
-                mov     ip, r3, lsl #16
-                orr     ip, ip, ip, lsr #16
-                str     ip, [r0]
-                mov     ip, r3, lsr #16
-                orr     ip, ip, ip, lsl #16
-                str     ip, [r0]
-                mov     ip, r4, lsl #16
-                orr     ip, ip, ip, lsr #16
-                str     ip, [r0]
-                mov     ip, r4, lsr #16
-                orr     ip, ip, ip, lsl #16
-                str     ip, [r0]
-                mov     ip, r5, lsl #16
-                orr     ip, ip, ip, lsr #16
-                str     ip, [r0]
-                mov     ip, r5, lsr #16
-                orr     ip, ip, ip, lsl #16
-                str     ip, [r0]
-                mov     ip, r6, lsl #16
-                orr     ip, ip, ip, lsr #16
-                str     ip, [r0]
-                mov     ip, r6, lsr #16
-                orr     ip, ip, ip, lsl #16
-                str     ip, [r0]
-                subs    r2, r2, #8
-                bpl     .Loutsw_8_lp
-                tst     r2, #7
-                ldmeqfd sp!, {r4, r5, r6, pc}
-.Lno_outsw_8:   tst     r2, #4
-                beq     .Lno_outsw_4
-                ldmia   r1!, {r3, r4}
-                mov     ip, r3, lsl #16
-                orr     ip, ip, ip, lsr #16
-                str     ip, [r0]
-                mov     ip, r3, lsr #16
-                orr     ip, ip, ip, lsl #16
-                str     ip, [r0]
-                mov     ip, r4, lsl #16
-                orr     ip, ip, ip, lsr #16
-                str     ip, [r0]
-                mov     ip, r4, lsr #16
-                orr     ip, ip, ip, lsl #16
-                str     ip, [r0]
-.Lno_outsw_4:   tst     r2, #2
-                beq     .Lno_outsw_2
-                ldr     r3, [r1], #4
-                mov     ip, r3, lsl #16
-                orr     ip, ip, ip, lsr #16
-                str     ip, [r0]
-                mov     ip, r3, lsr #16
-                orr     ip, ip, ip, lsl #16
-                str     ip, [r0]
-.Lno_outsw_2:   tst     r2, #1
-                ldrne   r3, [r1]
-                movne   ip, r3, lsl #16
-                orrne   ip, ip, ip, lsr #16
-                strne   ip, [r0]
-                ldmfd   sp!, {r4, r5, r6, pc}
diff --git a/arch/arm/lib/uaccess.S b/arch/arm/lib/uaccess.S
deleted file mode 100644
index 5c908b1cb8ed..000000000000
--- a/arch/arm/lib/uaccess.S
+++ /dev/null
@@ -1,564 +0,0 @@
-/*
- *  linux/arch/arm/lib/uaccess.S
- *
- *  Copyright (C) 1995, 1996,1997,1998 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- *  Routines to block copy data to/from user memory
- *   These are highly optimised both for the 4k page size
- *   and for various alignments.
- */
-#include <linux/linkage.h>
-#include <asm/assembler.h>
-#include <asm/errno.h>
-#include <asm/domain.h>
-                .text
-#define PAGE_SHIFT 12
-/* Prototype: int __copy_to_user(void *to, const char *from, size_t n)
- * Purpose  : copy a block to user memory from kernel memory
- * Params   : to   - user memory
- *          : from - kernel memory
- *          : n    - number of bytes to copy
- * Returns  : Number of bytes NOT copied.
- */
-.Lc2u_dest_not_aligned:
-                rsb     ip, ip, #4
-                cmp     ip, #2
-                ldrb    r3, [r1], #1
-USER(   TUSER(  strb)   r3, [r0], #1)                   @ May fault
-                ldrgeb  r3, [r1], #1
-USER(   TUSER(  strgeb) r3, [r0], #1)                   @ May fault
-                ldrgtb  r3, [r1], #1
-USER(   TUSER(  strgtb) r3, [r0], #1)                   @ May fault
-                sub     r2, r2, ip
-                b       .Lc2u_dest_aligned
-ENTRY(__copy_to_user)
-                stmfd   sp!, {r2, r4 - r7, lr}
-                cmp     r2, #4
-                blt     .Lc2u_not_enough
-                ands    ip, r0, #3
-                bne     .Lc2u_dest_not_aligned
-.Lc2u_dest_aligned:
-                ands    ip, r1, #3
-                bne     .Lc2u_src_not_aligned
-/*
- * Seeing as there has to be at least 8 bytes to copy, we can
- * copy one word, and force a user-mode page fault...
- */
-.Lc2u_0fupi:    subs    r2, r2, #4
-                addmi   ip, r2, #4
-                bmi     .Lc2u_0nowords
-                ldr     r3, [r1], #4
-USER(   TUSER(  str)    r3, [r0], #4)                   @ May fault
-                mov     ip, r0, lsl #32 - PAGE_SHIFT    @ On each page, use a ld/st??t instruction
-                rsb     ip, ip, #0
-                movs    ip, ip, lsr #32 - PAGE_SHIFT
-                beq     .Lc2u_0fupi
-/*
- * ip = max no. of bytes to copy before needing another "strt" insn
- */
-                cmp     r2, ip
-                movlt   ip, r2
-                sub     r2, r2, ip
-                subs    ip, ip, #32
-                blt     .Lc2u_0rem8lp
-.Lc2u_0cpy8lp:  ldmia   r1!, {r3 - r6}
-                stmia   r0!, {r3 - r6}                  @ Shouldnt fault
-                ldmia   r1!, {r3 - r6}
-                subs    ip, ip, #32
-                stmia   r0!, {r3 - r6}                  @ Shouldnt fault
-                bpl     .Lc2u_0cpy8lp
-.Lc2u_0rem8lp:  cmn     ip, #16
-                ldmgeia r1!, {r3 - r6}
-                stmgeia r0!, {r3 - r6}                  @ Shouldnt fault
-                tst     ip, #8
-                ldmneia r1!, {r3 - r4}
-                stmneia r0!, {r3 - r4}                  @ Shouldnt fault
-                tst     ip, #4
-                ldrne   r3, [r1], #4
-        TUSER(  strne) r3, [r0], #4                     @ Shouldnt fault
-                ands    ip, ip, #3
-                beq     .Lc2u_0fupi
-.Lc2u_0nowords: teq     ip, #0
-                beq     .Lc2u_finished
-.Lc2u_nowords:  cmp     ip, #2
-                ldrb    r3, [r1], #1
-USER(   TUSER(  strb)   r3, [r0], #1)                   @ May fault
-                ldrgeb  r3, [r1], #1
-USER(   TUSER(  strgeb) r3, [r0], #1)                   @ May fault
-                ldrgtb  r3, [r1], #1
-USER(   TUSER(  strgtb) r3, [r0], #1)                   @ May fault
-                b       .Lc2u_finished
-.Lc2u_not_enough:
-                movs    ip, r2
-                bne     .Lc2u_nowords
-.Lc2u_finished: mov     r0, #0
-                ldmfd   sp!, {r2, r4 - r7, pc}
-.Lc2u_src_not_aligned:
-                bic     r1, r1, #3
-                ldr     r7, [r1], #4
-                cmp     ip, #2
-                bgt     .Lc2u_3fupi
-                beq     .Lc2u_2fupi
-.Lc2u_1fupi:    subs    r2, r2, #4
-                addmi   ip, r2, #4
-                bmi     .Lc2u_1nowords
-                mov     r3, r7, pull #8
-                ldr     r7, [r1], #4
-                orr     r3, r3, r7, push #24
-USER(   TUSER(  str)    r3, [r0], #4)                   @ May fault
-                mov     ip, r0, lsl #32 - PAGE_SHIFT
-                rsb     ip, ip, #0
-                movs    ip, ip, lsr #32 - PAGE_SHIFT
-                beq     .Lc2u_1fupi
-                cmp     r2, ip
-                movlt   ip, r2
-                sub     r2, r2, ip
-                subs    ip, ip, #16
-                blt     .Lc2u_1rem8lp
-.Lc2u_1cpy8lp:  mov     r3, r7, pull #8
-                ldmia   r1!, {r4 - r7}
-                subs    ip, ip, #16
-                orr     r3, r3, r4, push #24
-                mov     r4, r4, pull #8
-                orr     r4, r4, r5, push #24
-                mov     r5, r5, pull #8
-                orr     r5, r5, r6, push #24
-                mov     r6, r6, pull #8
-                orr     r6, r6, r7, push #24
-                stmia   r0!, {r3 - r6}                  @ Shouldnt fault
-                bpl     .Lc2u_1cpy8lp
-.Lc2u_1rem8lp:  tst     ip, #8
-                movne   r3, r7, pull #8
-                ldmneia r1!, {r4, r7}
-                orrne   r3, r3, r4, push #24
-                movne   r4, r4, pull #8
-                orrne   r4, r4, r7, push #24
-                stmneia r0!, {r3 - r4}                  @ Shouldnt fault
-                tst     ip, #4
-                movne   r3, r7, pull #8
-                ldrne   r7, [r1], #4
-                orrne   r3, r3, r7, push #24
-        TUSER(  strne) r3, [r0], #4                     @ Shouldnt fault
-                ands    ip, ip, #3
-                beq     .Lc2u_1fupi
-.Lc2u_1nowords: mov     r3, r7, get_byte_1
-                teq     ip, #0
-                beq     .Lc2u_finished
-                cmp     ip, #2
-USER(   TUSER(  strb)   r3, [r0], #1)                   @ May fault
-                movge   r3, r7, get_byte_2
-USER(   TUSER(  strgeb) r3, [r0], #1)                   @ May fault
-                movgt   r3, r7, get_byte_3
-USER(   TUSER(  strgtb) r3, [r0], #1)                   @ May fault
-                b       .Lc2u_finished
-.Lc2u_2fupi:    subs    r2, r2, #4
-                addmi   ip, r2, #4
-                bmi     .Lc2u_2nowords
-                mov     r3, r7, pull #16
-                ldr     r7, [r1], #4
-                orr     r3, r3, r7, push #16
-USER(   TUSER(  str)    r3, [r0], #4)                   @ May fault
-                mov     ip, r0, lsl #32 - PAGE_SHIFT
-                rsb     ip, ip, #0
-                movs    ip, ip, lsr #32 - PAGE_SHIFT
-                beq     .Lc2u_2fupi
-                cmp     r2, ip
-                movlt   ip, r2
-                sub     r2, r2, ip
-                subs    ip, ip, #16
-                blt     .Lc2u_2rem8lp
-.Lc2u_2cpy8lp:  mov     r3, r7, pull #16
-                ldmia   r1!, {r4 - r7}
-                subs    ip, ip, #16
-                orr     r3, r3, r4, push #16
-                mov     r4, r4, pull #16
-                orr     r4, r4, r5, push #16
-                mov     r5, r5, pull #16
-                orr     r5, r5, r6, push #16
-                mov     r6, r6, pull #16
-                orr     r6, r6, r7, push #16
-                stmia   r0!, {r3 - r6}                  @ Shouldnt fault
-                bpl     .Lc2u_2cpy8lp
-.Lc2u_2rem8lp:  tst     ip, #8
-                movne   r3, r7, pull #16
-                ldmneia r1!, {r4, r7}
-                orrne   r3, r3, r4, push #16
-                movne   r4, r4, pull #16
-                orrne   r4, r4, r7, push #16
-                stmneia r0!, {r3 - r4}                  @ Shouldnt fault
-                tst     ip, #4
-                movne   r3, r7, pull #16
-                ldrne   r7, [r1], #4
-                orrne   r3, r3, r7, push #16
-        TUSER(  strne) r3, [r0], #4                     @ Shouldnt fault
-                ands    ip, ip, #3
-                beq     .Lc2u_2fupi
-.Lc2u_2nowords: mov     r3, r7, get_byte_2
-                teq     ip, #0
-                beq     .Lc2u_finished
-                cmp     ip, #2
-USER(   TUSER(  strb)   r3, [r0], #1)                   @ May fault
-                movge   r3, r7, get_byte_3
-USER(   TUSER(  strgeb) r3, [r0], #1)                   @ May fault
-                ldrgtb  r3, [r1], #0
-USER(   TUSER(  strgtb) r3, [r0], #1)                   @ May fault
-                b       .Lc2u_finished
-.Lc2u_3fupi:    subs    r2, r2, #4
-                addmi   ip, r2, #4
-                bmi     .Lc2u_3nowords
-                mov     r3, r7, pull #24
-                ldr     r7, [r1], #4
-                orr     r3, r3, r7, push #8
-USER(   TUSER(  str)    r3, [r0], #4)                   @ May fault
-                mov     ip, r0, lsl #32 - PAGE_SHIFT
-                rsb     ip, ip, #0
-                movs    ip, ip, lsr #32 - PAGE_SHIFT
-                beq     .Lc2u_3fupi
-                cmp     r2, ip
-                movlt   ip, r2
-                sub     r2, r2, ip
-                subs    ip, ip, #16
-                blt     .Lc2u_3rem8lp
-.Lc2u_3cpy8lp:  mov     r3, r7, pull #24
-                ldmia   r1!, {r4 - r7}
-                subs    ip, ip, #16
-                orr     r3, r3, r4, push #8
-                mov     r4, r4, pull #24
-                orr     r4, r4, r5, push #8
-                mov     r5, r5, pull #24
-                orr     r5, r5, r6, push #8
-                mov     r6, r6, pull #24
-                orr     r6, r6, r7, push #8
-                stmia   r0!, {r3 - r6}                  @ Shouldnt fault
-                bpl     .Lc2u_3cpy8lp
-.Lc2u_3rem8lp:  tst     ip, #8
-                movne   r3, r7, pull #24
-                ldmneia r1!, {r4, r7}
-                orrne   r3, r3, r4, push #8
-                movne   r4, r4, pull #24
-                orrne   r4, r4, r7, push #8
-                stmneia r0!, {r3 - r4}                  @ Shouldnt fault
-                tst     ip, #4
-                movne   r3, r7, pull #24
-                ldrne   r7, [r1], #4
-                orrne   r3, r3, r7, push #8
-        TUSER(  strne) r3, [r0], #4                     @ Shouldnt fault
-                ands    ip, ip, #3
-                beq     .Lc2u_3fupi
-.Lc2u_3nowords: mov     r3, r7, get_byte_3
-                teq     ip, #0
-                beq     .Lc2u_finished
-                cmp     ip, #2
-USER(   TUSER(  strb)   r3, [r0], #1)                   @ May fault
-                ldrgeb  r3, [r1], #1
-USER(   TUSER(  strgeb) r3, [r0], #1)                   @ May fault
-                ldrgtb  r3, [r1], #0
-USER(   TUSER(  strgtb) r3, [r0], #1)                   @ May fault
-                b       .Lc2u_finished
-ENDPROC(__copy_to_user)
-                .pushsection .fixup,"ax"
-                .align  0
-9001:           ldmfd   sp!, {r0, r4 - r7, pc}
-                .popsection
-/* Prototype: unsigned long __copy_from_user(void *to,const void *from,unsigned long n);
- * Purpose  : copy a block from user memory to kernel memory
- * Params   : to   - kernel memory
- *          : from - user memory
- *          : n    - number of bytes to copy
- * Returns  : Number of bytes NOT copied.
- */
-.Lcfu_dest_not_aligned:
-                rsb     ip, ip, #4
-                cmp     ip, #2
-USER(   TUSER(  ldrb)   r3, [r1], #1)                   @ May fault
-                strb    r3, [r0], #1
-USER(   TUSER(  ldrgeb) r3, [r1], #1)                   @ May fault
-                strgeb  r3, [r0], #1
-USER(   TUSER(  ldrgtb) r3, [r1], #1)                   @ May fault
-                strgtb  r3, [r0], #1
-                sub     r2, r2, ip
-                b       .Lcfu_dest_aligned
-ENTRY(__copy_from_user)
-                stmfd   sp!, {r0, r2, r4 - r7, lr}
-                cmp     r2, #4
-                blt     .Lcfu_not_enough
-                ands    ip, r0, #3
-                bne     .Lcfu_dest_not_aligned
-.Lcfu_dest_aligned:
-                ands    ip, r1, #3
-                bne     .Lcfu_src_not_aligned
-/*
- * Seeing as there has to be at least 8 bytes to copy, we can
- * copy one word, and force a user-mode page fault...
- */
-.Lcfu_0fupi:    subs    r2, r2, #4
-                addmi   ip, r2, #4
-                bmi     .Lcfu_0nowords
-USER(   TUSER(  ldr)    r3, [r1], #4)
-                str     r3, [r0], #4
-                mov     ip, r1, lsl #32 - PAGE_SHIFT    @ On each page, use a ld/st??t instruction
-                rsb     ip, ip, #0
-                movs    ip, ip, lsr #32 - PAGE_SHIFT
-                beq     .Lcfu_0fupi
-/*
- * ip = max no. of bytes to copy before needing another "strt" insn
- */
-                cmp     r2, ip
-                movlt   ip, r2
-                sub     r2, r2, ip
-                subs    ip, ip, #32
-                blt     .Lcfu_0rem8lp
-.Lcfu_0cpy8lp:  ldmia   r1!, {r3 - r6}                  @ Shouldnt fault
-                stmia   r0!, {r3 - r6}
-                ldmia   r1!, {r3 - r6}                  @ Shouldnt fault
-                subs    ip, ip, #32
-                stmia   r0!, {r3 - r6}
-                bpl     .Lcfu_0cpy8lp
-.Lcfu_0rem8lp:  cmn     ip, #16
-                ldmgeia r1!, {r3 - r6}                  @ Shouldnt fault
-                stmgeia r0!, {r3 - r6}
-                tst     ip, #8
-                ldmneia r1!, {r3 - r4}                  @ Shouldnt fault
-                stmneia r0!, {r3 - r4}
-                tst     ip, #4
-        TUSER(  ldrne) r3, [r1], #4                     @ Shouldnt fault
-                strne   r3, [r0], #4
-                ands    ip, ip, #3
-                beq     .Lcfu_0fupi
-.Lcfu_0nowords: teq     ip, #0
-                beq     .Lcfu_finished
-.Lcfu_nowords:  cmp     ip, #2
-USER(   TUSER(  ldrb)   r3, [r1], #1)                   @ May fault
-                strb    r3, [r0], #1
-USER(   TUSER(  ldrgeb) r3, [r1], #1)                   @ May fault
-                strgeb  r3, [r0], #1
-USER(   TUSER(  ldrgtb) r3, [r1], #1)                   @ May fault
-                strgtb  r3, [r0], #1
-                b       .Lcfu_finished
-.Lcfu_not_enough:
-                movs    ip, r2
-                bne     .Lcfu_nowords
-.Lcfu_finished: mov     r0, #0
-                add     sp, sp, #8
-                ldmfd   sp!, {r4 - r7, pc}
-.Lcfu_src_not_aligned:
-                bic     r1, r1, #3
-USER(   TUSER(  ldr)    r7, [r1], #4)                   @ May fault
-                cmp     ip, #2
-                bgt     .Lcfu_3fupi
-                beq     .Lcfu_2fupi
-.Lcfu_1fupi:    subs    r2, r2, #4
-                addmi   ip, r2, #4
-                bmi     .Lcfu_1nowords
-                mov     r3, r7, pull #8
-USER(   TUSER(  ldr)    r7, [r1], #4)                   @ May fault
-                orr     r3, r3, r7, push #24
-                str     r3, [r0], #4
-                mov     ip, r1, lsl #32 - PAGE_SHIFT
-                rsb     ip, ip, #0
-                movs    ip, ip, lsr #32 - PAGE_SHIFT
-                beq     .Lcfu_1fupi
-                cmp     r2, ip
-                movlt   ip, r2
-                sub     r2, r2, ip
-                subs    ip, ip, #16
-                blt     .Lcfu_1rem8lp
-.Lcfu_1cpy8lp:  mov     r3, r7, pull #8
-                ldmia   r1!, {r4 - r7}                  @ Shouldnt fault
-                subs    ip, ip, #16
-                orr     r3, r3, r4, push #24
-                mov     r4, r4, pull #8
-                orr     r4, r4, r5, push #24
-                mov     r5, r5, pull #8
-                orr     r5, r5, r6, push #24
-                mov     r6, r6, pull #8
-                orr     r6, r6, r7, push #24
-                stmia   r0!, {r3 - r6}
-                bpl     .Lcfu_1cpy8lp
-.Lcfu_1rem8lp:  tst     ip, #8
-                movne   r3, r7, pull #8
-                ldmneia r1!, {r4, r7}                   @ Shouldnt fault
-                orrne   r3, r3, r4, push #24
-                movne   r4, r4, pull #8
-                orrne   r4, r4, r7, push #24
-                stmneia r0!, {r3 - r4}
-                tst     ip, #4
-                movne   r3, r7, pull #8
-USER(   TUSER(  ldrne) r7, [r1], #4)                    @ May fault
-                orrne   r3, r3, r7, push #24
-                strne   r3, [r0], #4
-                ands    ip, ip, #3
-                beq     .Lcfu_1fupi
-.Lcfu_1nowords: mov     r3, r7, get_byte_1
-                teq     ip, #0
-                beq     .Lcfu_finished
-                cmp     ip, #2
-                strb    r3, [r0], #1
-                movge   r3, r7, get_byte_2
-                strgeb  r3, [r0], #1
-                movgt   r3, r7, get_byte_3
-                strgtb  r3, [r0], #1
-                b       .Lcfu_finished
-.Lcfu_2fupi:    subs    r2, r2, #4
-                addmi   ip, r2, #4
-                bmi     .Lcfu_2nowords
-                mov     r3, r7, pull #16
-USER(   TUSER(  ldr)    r7, [r1], #4)                   @ May fault
-                orr     r3, r3, r7, push #16
-                str     r3, [r0], #4
-                mov     ip, r1, lsl #32 - PAGE_SHIFT
-                rsb     ip, ip, #0
-                movs    ip, ip, lsr #32 - PAGE_SHIFT
-                beq     .Lcfu_2fupi
-                cmp     r2, ip
-                movlt   ip, r2
-                sub     r2, r2, ip
-                subs    ip, ip, #16
-                blt     .Lcfu_2rem8lp
-.Lcfu_2cpy8lp:  mov     r3, r7, pull #16
-                ldmia   r1!, {r4 - r7}                  @ Shouldnt fault
-                subs    ip, ip, #16
-                orr     r3, r3, r4, push #16
-                mov     r4, r4, pull #16
-                orr     r4, r4, r5, push #16
-                mov     r5, r5, pull #16
-                orr     r5, r5, r6, push #16
-                mov     r6, r6, pull #16
-                orr     r6, r6, r7, push #16
-                stmia   r0!, {r3 - r6}
-                bpl     .Lcfu_2cpy8lp
-.Lcfu_2rem8lp:  tst     ip, #8
-                movne   r3, r7, pull #16
-                ldmneia r1!, {r4, r7}                   @ Shouldnt fault
-                orrne   r3, r3, r4, push #16
-                movne   r4, r4, pull #16
-                orrne   r4, r4, r7, push #16
-                stmneia r0!, {r3 - r4}
-                tst     ip, #4
-                movne   r3, r7, pull #16
-USER(   TUSER(  ldrne) r7, [r1], #4)                    @ May fault
-                orrne   r3, r3, r7, push #16
-                strne   r3, [r0], #4
-                ands    ip, ip, #3
-                beq     .Lcfu_2fupi
-.Lcfu_2nowords: mov     r3, r7, get_byte_2
-                teq     ip, #0
-                beq     .Lcfu_finished
-                cmp     ip, #2
-                strb    r3, [r0], #1
-                movge   r3, r7, get_byte_3
-                strgeb  r3, [r0], #1
-USER(   TUSER(  ldrgtb) r3, [r1], #0)                   @ May fault
-                strgtb  r3, [r0], #1
-                b       .Lcfu_finished
-.Lcfu_3fupi:    subs    r2, r2, #4
-                addmi   ip, r2, #4
-                bmi     .Lcfu_3nowords
-                mov     r3, r7, pull #24
-USER(   TUSER(  ldr)    r7, [r1], #4)                   @ May fault
-                orr     r3, r3, r7, push #8
-                str     r3, [r0], #4
-                mov     ip, r1, lsl #32 - PAGE_SHIFT
-                rsb     ip, ip, #0
-                movs    ip, ip, lsr #32 - PAGE_SHIFT
-                beq     .Lcfu_3fupi
-                cmp     r2, ip
-                movlt   ip, r2
-                sub     r2, r2, ip
-                subs    ip, ip, #16
-                blt     .Lcfu_3rem8lp
-.Lcfu_3cpy8lp:  mov     r3, r7, pull #24
-                ldmia   r1!, {r4 - r7}                  @ Shouldnt fault
-                orr     r3, r3, r4, push #8
-                mov     r4, r4, pull #24
-                orr     r4, r4, r5, push #8
-                mov     r5, r5, pull #24
-                orr     r5, r5, r6, push #8
-                mov     r6, r6, pull #24
-                orr     r6, r6, r7, push #8
-                stmia   r0!, {r3 - r6}
-                subs    ip, ip, #16
-                bpl     .Lcfu_3cpy8lp
-.Lcfu_3rem8lp:  tst     ip, #8
-                movne   r3, r7, pull #24
-                ldmneia r1!, {r4, r7}                   @ Shouldnt fault
-                orrne   r3, r3, r4, push #8
-                movne   r4, r4, pull #24
-                orrne   r4, r4, r7, push #8
-                stmneia r0!, {r3 - r4}
-                tst     ip, #4
-                movne   r3, r7, pull #24
-USER(   TUSER(  ldrne) r7, [r1], #4)                    @ May fault
-                orrne   r3, r3, r7, push #8
-                strne   r3, [r0], #4
-                ands    ip, ip, #3
-                beq     .Lcfu_3fupi
-.Lcfu_3nowords: mov     r3, r7, get_byte_3
-                teq     ip, #0
-                beq     .Lcfu_finished
-                cmp     ip, #2
-                strb    r3, [r0], #1
-USER(   TUSER(  ldrgeb) r3, [r1], #1)                   @ May fault
-                strgeb  r3, [r0], #1
-USER(   TUSER(  ldrgtb) r3, [r1], #1)                   @ May fault
-                strgtb  r3, [r0], #1
-                b       .Lcfu_finished
-ENDPROC(__copy_from_user)
-                .pushsection .fixup,"ax"
-                .align  0
-                /*
-                 * We took an exception.  r0 contains a pointer to
-                 * the byte not copied.
-                 */
-9001:           ldr     r2, [sp], #4                    @ void *to
-                sub     r2, r0, r2                      @ bytes copied
-                ldr     r1, [sp], #4                    @ unsigned long count
-                subs    r4, r1, r2                      @ bytes left to copy
-                movne   r1, r4
-                blne    __memzero
-                mov     r0, r4
-                ldmfd   sp!, {r4 - r7, pc}
-                .popsection
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 45db05d8d94c..19505c0a3f01 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -9,15 +9,6 @@ config HAVE_AT91_DBGU0
 config HAVE_AT91_DBGU1
        bool
-config HAVE_AT91_USART3
-        bool
-config HAVE_AT91_USART4
-        bool
-config HAVE_AT91_USART5
-        bool
 config AT91_SAM9_ALT_RESET
        bool
        default !ARCH_AT91X40
@@ -26,87 +17,129 @@ config AT91_SAM9G45_RESET
        bool
        default !ARCH_AT91X40
+config SOC_AT91SAM9
+        bool
+        select GENERIC_CLOCKEVENTS
+        select CPU_ARM926T
 menu "Atmel AT91 System-on-Chip"
-choice
+comment "Atmel AT91 Processor"
-        prompt "Atmel AT91 Processor"
-config ARCH_AT91RM9200
+config SOC_AT91SAM9
+        bool
+        select CPU_ARM926T
+        select AT91_SAM9_TIME
+        select AT91_SAM9_SMC
+config SOC_AT91RM9200
        bool "AT91RM9200"
        select CPU_ARM920T
        select GENERIC_CLOCKEVENTS
        select HAVE_AT91_DBGU0
-        select HAVE_AT91_USART3
-config ARCH_AT91SAM9260
+config SOC_AT91SAM9260
-        bool "AT91SAM9260 or AT91SAM9XE"
+        bool "AT91SAM9260, AT91SAM9XE or AT91SAM9G20"
-        select CPU_ARM926T
+        select SOC_AT91SAM9
-        select GENERIC_CLOCKEVENTS
        select HAVE_AT91_DBGU0
-        select HAVE_AT91_USART3
-        select HAVE_AT91_USART4
-        select HAVE_AT91_USART5
        select HAVE_NET_MACB
+        help
+          Select this if you are using one of Atmel's AT91SAM9260, AT91SAM9XE
+          or AT91SAM9G20 SoC.
-config ARCH_AT91SAM9261
+config SOC_AT91SAM9261
-        bool "AT91SAM9261"
+        bool "AT91SAM9261 or AT91SAM9G10"
-        select CPU_ARM926T
+        select SOC_AT91SAM9
-        select GENERIC_CLOCKEVENTS
-        select HAVE_FB_ATMEL
-        select HAVE_AT91_DBGU0
-config ARCH_AT91SAM9G10
-        bool "AT91SAM9G10"
-        select CPU_ARM926T
-        select GENERIC_CLOCKEVENTS
        select HAVE_AT91_DBGU0
        select HAVE_FB_ATMEL
+        help
+          Select this if you are using one of Atmel's AT91SAM9261 or AT91SAM9G10 SoC.
-config ARCH_AT91SAM9263
+config SOC_AT91SAM9263
        bool "AT91SAM9263"
-        select CPU_ARM926T
+        select SOC_AT91SAM9
-        select GENERIC_CLOCKEVENTS
+        select HAVE_AT91_DBGU1
        select HAVE_FB_ATMEL
        select HAVE_NET_MACB
-        select HAVE_AT91_DBGU1
-config ARCH_AT91SAM9RL
+config SOC_AT91SAM9RL
        bool "AT91SAM9RL"
-        select CPU_ARM926T
+        select SOC_AT91SAM9
-        select GENERIC_CLOCKEVENTS
-        select HAVE_AT91_USART3
-        select HAVE_FB_ATMEL
-        select HAVE_AT91_DBGU0
-config ARCH_AT91SAM9G20
-        bool "AT91SAM9G20"
-        select CPU_ARM926T
-        select GENERIC_CLOCKEVENTS
        select HAVE_AT91_DBGU0
-        select HAVE_AT91_USART3
+        select HAVE_FB_ATMEL
-        select HAVE_AT91_USART4
-        select HAVE_AT91_USART5
-        select HAVE_NET_MACB
-config ARCH_AT91SAM9G45
+config SOC_AT91SAM9G45
-        bool "AT91SAM9G45"
+        bool "AT91SAM9G45 or AT91SAM9M10 families"
-        select CPU_ARM926T
+        select SOC_AT91SAM9
-        select GENERIC_CLOCKEVENTS
+        select HAVE_AT91_DBGU1
-        select HAVE_AT91_USART3
        select HAVE_FB_ATMEL
        select HAVE_NET_MACB
-        select HAVE_AT91_DBGU1
+        help
+          Select this if you are using one of Atmel's AT91SAM9G45 family SoC.
+          This support covers AT91SAM9G45, AT91SAM9G46, AT91SAM9M10 and AT91SAM9M11.
-config ARCH_AT91SAM9X5
+config SOC_AT91SAM9X5
        bool "AT91SAM9x5 family"
-        select CPU_ARM926T
+        select SOC_AT91SAM9
-        select GENERIC_CLOCKEVENTS
+        select HAVE_AT91_DBGU0
        select HAVE_FB_ATMEL
        select HAVE_NET_MACB
+        help
+          Select this if you are using one of Atmel's AT91SAM9x5 family SoC.
+          This means that your SAM9 name finishes with a '5' (except if it is
+          AT91SAM9G45!).
+          This support covers AT91SAM9G15, AT91SAM9G25, AT91SAM9X25, AT91SAM9G35
+          and AT91SAM9X35.
+config SOC_AT91SAM9N12
+        bool "AT91SAM9N12 family"
+        select SOC_AT91SAM9
        select HAVE_AT91_DBGU0
+        select HAVE_FB_ATMEL
+        help
+          Select this if you are using Atmel's AT91SAM9N12 SoC.
+choice
+        prompt "Atmel AT91 Processor Devices for non DT boards"
+config ARCH_AT91_NONE
+        bool "None"
+config ARCH_AT91RM9200
+        bool "AT91RM9200"
+        select SOC_AT91RM9200
+config ARCH_AT91SAM9260
+        bool "AT91SAM9260 or AT91SAM9XE"
+        select SOC_AT91SAM9260
+config ARCH_AT91SAM9261
+        bool "AT91SAM9261"
+        select SOC_AT91SAM9261
+config ARCH_AT91SAM9G10
+        bool "AT91SAM9G10"
+        select SOC_AT91SAM9261
+config ARCH_AT91SAM9263
+        bool "AT91SAM9263"
+        select SOC_AT91SAM9263
+config ARCH_AT91SAM9RL
+        bool "AT91SAM9RL"
+        select SOC_AT91SAM9RL
+config ARCH_AT91SAM9G20
+        bool "AT91SAM9G20"
+        select SOC_AT91SAM9260
+config ARCH_AT91SAM9G45
+        bool "AT91SAM9G45"
+        select SOC_AT91SAM9G45
 config ARCH_AT91X40
        bool "AT91x40"
+        depends on !MMU
        select ARCH_USES_GETTIMEOFFSET
 endchoice
@@ -364,6 +397,7 @@ config MACH_AT91SAM9G20EK_2MMC
          Select this if you are using an Atmel AT91SAM9G20-EK Evaluation Kit
          with 2 SD/MMC Slots. This is the case for AT91SAM9G20-EK rev. C and
          onwards.
+          <http://www.atmel.com/tools/SAM9G20-EK.aspx>
 config MACH_CPU9G20
        bool "Eukrea CPU9G20 board"
@@ -433,9 +467,10 @@ comment "AT91SAM9G45 Board Type"
 config MACH_AT91SAM9M10G45EK
        bool "Atmel AT91SAM9M10G45-EK Evaluation Kits"
        help
-          Select this if you are using Atmel's AT91SAM9G45-EKES Evaluation Kit.
+          Select this if you are using Atmel's AT91SAM9M10G45-EK Evaluation Kit.
-          "ES" at the end of the name means that this board is an
+          Those boards can be populated with any SoC of AT91SAM9G45 or AT91SAM9M10
-          Engineering Sample.
+          families: AT91SAM9G45, AT91SAM9G46, AT91SAM9M10 and AT91SAM9M11.
+          <http://www.atmel.com/tools/SAM9M10-G45-EK.aspx>
 endif
@@ -515,41 +550,6 @@ config AT91_TIMER_HZ
          system clock (of at least several MHz), rounding is less of a
          problem so it can be safer to use a decimal values like 100.
-choice
-        prompt "Select a UART for early kernel messages"
-config AT91_EARLY_DBGU0
-        bool "DBGU on rm9200, 9260/9g20, 9261/9g10 and 9rl"
-        depends on HAVE_AT91_DBGU0
-config AT91_EARLY_DBGU1
-        bool "DBGU on 9263 and 9g45"
-        depends on HAVE_AT91_DBGU1
-config AT91_EARLY_USART0
-        bool "USART0"
-config AT91_EARLY_USART1
-        bool "USART1"
-config AT91_EARLY_USART2
-        bool "USART2"
-        depends on ! ARCH_AT91X40
-config AT91_EARLY_USART3
-        bool "USART3"
-        depends on HAVE_AT91_USART3
-config AT91_EARLY_USART4
-        bool "USART4"
-        depends on HAVE_AT91_USART4
-config AT91_EARLY_USART5
-        bool "USART5"
-        depends on HAVE_AT91_USART5
-endchoice
 endmenu
 endif
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 8512e53bed93..3bb7a51efc9d 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -10,17 +10,26 @@ obj-		:=
 obj-$(CONFIG_AT91_PMC_UNIT)     += clock.o
 obj-$(CONFIG_AT91_SAM9_ALT_RESET) += at91sam9_alt_reset.o
 obj-$(CONFIG_AT91_SAM9G45_RESET) += at91sam9g45_reset.o
+obj-$(CONFIG_SOC_AT91SAM9)      += at91sam926x_time.o sam9_smc.o
 # CPU-specific support
-obj-$(CONFIG_ARCH_AT91RM9200)   += at91rm9200.o at91rm9200_time.o at91rm9200_devices.o
+obj-$(CONFIG_SOC_AT91RM9200)    += at91rm9200.o at91rm9200_time.o
-obj-$(CONFIG_ARCH_AT91SAM9260)  += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o
+obj-$(CONFIG_SOC_AT91SAM9260)   += at91sam9260.o
-obj-$(CONFIG_ARCH_AT91SAM9261)  += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o
+obj-$(CONFIG_SOC_AT91SAM9261)   += at91sam9261.o
-obj-$(CONFIG_ARCH_AT91SAM9G10)  += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o
+obj-$(CONFIG_SOC_AT91SAM9263)   += at91sam9263.o
-obj-$(CONFIG_ARCH_AT91SAM9263)  += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o sam9_smc.o
+obj-$(CONFIG_SOC_AT91SAM9G45)   += at91sam9g45.o
-obj-$(CONFIG_ARCH_AT91SAM9RL)   += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o
+obj-$(CONFIG_SOC_AT91SAM9N12)   += at91sam9n12.o
-obj-$(CONFIG_ARCH_AT91SAM9G20)  += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o
+obj-$(CONFIG_SOC_AT91SAM9X5)    += at91sam9x5.o
-obj-$(CONFIG_ARCH_AT91SAM9G45)  += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o
+obj-$(CONFIG_SOC_AT91SAM9RL)    += at91sam9rl.o
-obj-$(CONFIG_ARCH_AT91SAM9X5)   += at91sam9x5.o at91sam926x_time.o sam9_smc.o
+obj-$(CONFIG_ARCH_AT91RM9200)   += at91rm9200_devices.o
+obj-$(CONFIG_ARCH_AT91SAM9260)  += at91sam9260_devices.o
+obj-$(CONFIG_ARCH_AT91SAM9261)  += at91sam9261_devices.o
+obj-$(CONFIG_ARCH_AT91SAM9G10)  += at91sam9261_devices.o
+obj-$(CONFIG_ARCH_AT91SAM9263)  += at91sam9263_devices.o
+obj-$(CONFIG_ARCH_AT91SAM9RL)   += at91sam9rl_devices.o
+obj-$(CONFIG_ARCH_AT91SAM9G20)  += at91sam9260_devices.o
+obj-$(CONFIG_ARCH_AT91SAM9G45)  += at91sam9g45_devices.o
 obj-$(CONFIG_ARCH_AT91X40)      += at91x40.o at91x40_time.o
 # AT91RM9200 board-specific support
diff --git a/arch/arm/mach-at91/Makefile.boot b/arch/arm/mach-at91/Makefile.boot
index 0da66ca4a4f8..9e84fe4f2aaa 100644
--- a/arch/arm/mach-at91/Makefile.boot
+++ b/arch/arm/mach-at91/Makefile.boot
@@ -14,9 +14,23 @@ initrd_phys-y	:= 0x20410000
 endif
 # Keep dtb files sorted alphabetically for each SoC
+# sam9260
+dtb-$(CONFIG_MACH_AT91SAM_DT) += ethernut5.dtb
+dtb-$(CONFIG_MACH_AT91SAM_DT) += tny_a9260.dtb
+dtb-$(CONFIG_MACH_AT91SAM_DT) += usb_a9260.dtb
+# sam9263
+dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9263ek.dtb
+dtb-$(CONFIG_MACH_AT91SAM_DT) += tny_a9263.dtb
+dtb-$(CONFIG_MACH_AT91SAM_DT) += usb_a9263.dtb
 # sam9g20
+dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9g20ek.dtb
+dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9g20ek_2mmc.dtb
+dtb-$(CONFIG_MACH_AT91SAM_DT) += kizbox.dtb
+dtb-$(CONFIG_MACH_AT91SAM_DT) += tny_a9g20.dtb
 dtb-$(CONFIG_MACH_AT91SAM_DT) += usb_a9g20.dtb
 # sam9g45
 dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9m10g45ek.dtb
+# sam9n12
+dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9n12ek.dtb
 # sam9x5
 dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9g25ek.dtb
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index 364c19357e60..26917687fc30 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -26,15 +26,6 @@
 #include "clock.h"
 #include "sam9_smc.h"
-static struct map_desc at91rm9200_io_desc[] __initdata = {
-        {
-                .virtual        = AT91_VA_BASE_EMAC,
-                .pfn            = __phys_to_pfn(AT91RM9200_BASE_EMAC),
-                .length         = SZ_16K,
-                .type           = MT_DEVICE,
-        },
-};
 /* --------------------------------------------------------------------
 *  Clocks
 * -------------------------------------------------------------------- */
@@ -258,18 +249,6 @@ static void __init at91rm9200_register_clocks(void)
        clk_register(&pck3);
 }
-static struct clk_lookup console_clock_lookup;
-void __init at91rm9200_set_console_clock(int id)
-{
-        if (id >= ARRAY_SIZE(usart_clocks_lookups))
-                return;
-        console_clock_lookup.con_id = "usart";
-        console_clock_lookup.clk = usart_clocks_lookups[id].clk;
-        clkdev_add(&console_clock_lookup);
-}
 /* --------------------------------------------------------------------
 *  GPIO
 * -------------------------------------------------------------------- */
@@ -315,7 +294,6 @@ static void __init at91rm9200_map_io(void)
 {
        /* Map peripherals */
        at91_init_sram(0, AT91RM9200_SRAM_BASE, AT91RM9200_SRAM_SIZE);
-        iotable_init(at91rm9200_io_desc, ARRAY_SIZE(at91rm9200_io_desc));
 }
 static void __init at91rm9200_ioremap_registers(void)
diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c
index 99ce5c955e39..e6b7d0533dd7 100644
--- a/arch/arm/mach-at91/at91rm9200_devices.c
+++ b/arch/arm/mach-at91/at91rm9200_devices.c
@@ -140,8 +140,8 @@ static struct macb_platform_data eth_data;
 static struct resource eth_resources[] = {
        [0] = {
-                .start  = AT91_VA_BASE_EMAC,
+                .start  = AT91RM9200_BASE_EMAC,
-                .end    = AT91_VA_BASE_EMAC + SZ_16K - 1,
+                .end    = AT91RM9200_BASE_EMAC + SZ_16K - 1,
                .flags  = IORESOURCE_MEM,
        },
        [1] = {
@@ -1152,14 +1152,6 @@ void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
                at91_uarts[portnr] = pdev;
 }
-void __init at91_set_serial_console(unsigned portnr)
-{
-        if (portnr < ATMEL_MAX_UART) {
-                atmel_default_console_device = at91_uarts[portnr];
-                at91rm9200_set_console_clock(at91_uarts[portnr]->id);
-        }
-}
 void __init at91_add_device_serial(void)
 {
        int i;
@@ -1168,14 +1160,9 @@ void __init at91_add_device_serial(void)
                if (at91_uarts[i])
                        platform_device_register(at91_uarts[i]);
        }
-        if (!atmel_default_console_device)
-                printk(KERN_INFO "AT91: No default serial console defined.\n");
 }
 #else
-void __init __deprecated at91_init_serial(struct at91_uart_config *config) {}
 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
-void __init at91_set_serial_console(unsigned portnr) {}
 void __init at91_add_device_serial(void) {}
 #endif
diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c
index dd7f782b0b91..104ca40d8d18 100644
--- a/arch/arm/mach-at91/at91rm9200_time.c
+++ b/arch/arm/mach-at91/at91rm9200_time.c
@@ -23,6 +23,7 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/clockchips.h>
+#include <linux/export.h>
 #include <asm/mach/time.h>
@@ -176,6 +177,7 @@ static struct clock_event_device clkevt = {
 };
 void __iomem *at91_st_base;
+EXPORT_SYMBOL_GPL(at91_st_base);
 void __init at91rm9200_ioremap_st(u32 addr)
 {
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index 46f774233298..2b1e438ed878 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -55,6 +55,13 @@ static struct clk adc_clk = {
        .pmc_mask       = 1 << AT91SAM9260_ID_ADC,
        .type           = CLK_TYPE_PERIPHERAL,
 };
+static struct clk adc_op_clk = {
+        .name           = "adc_op_clk",
+        .type           = CLK_TYPE_PERIPHERAL,
+        .rate_hz        = 5000000,
+};
 static struct clk usart0_clk = {
        .name           = "usart0_clk",
        .pmc_mask       = 1 << AT91SAM9260_ID_US0,
@@ -166,6 +173,7 @@ static struct clk *periph_clocks[] __initdata = {
        &pioB_clk,
        &pioC_clk,
        &adc_clk,
+        &adc_op_clk,
        &usart0_clk,
        &usart1_clk,
        &usart2_clk,
@@ -268,18 +276,6 @@ static void __init at91sam9260_register_clocks(void)
        clk_register(&pck1);
 }
-static struct clk_lookup console_clock_lookup;
-void __init at91sam9260_set_console_clock(int id)
-{
-        if (id >= ARRAY_SIZE(usart_clocks_lookups))
-                return;
-        console_clock_lookup.con_id = "usart";
-        console_clock_lookup.clk = usart_clocks_lookups[id].clk;
-        clkdev_add(&console_clock_lookup);
-}
 /* --------------------------------------------------------------------
 *  GPIO
 * -------------------------------------------------------------------- */
diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c
index 5652dde4bbe2..0ded951f785a 100644
--- a/arch/arm/mach-at91/at91sam9260_devices.c
+++ b/arch/arm/mach-at91/at91sam9260_devices.c
@@ -17,12 +17,15 @@
 #include <linux/platform_device.h>
 #include <linux/i2c-gpio.h>
+#include <linux/platform_data/at91_adc.h>
 #include <mach/board.h>
 #include <mach/cpu.h>
 #include <mach/at91sam9260.h>
 #include <mach/at91sam9260_matrix.h>
 #include <mach/at91_matrix.h>
 #include <mach/at91sam9_smc.h>
+#include <mach/at91_adc.h>
 #include "generic.h"
@@ -702,25 +705,8 @@ static struct platform_device at91sam9260_tcb1_device = {
        .num_resources  = ARRAY_SIZE(tcb1_resources),
 };
-#if defined(CONFIG_OF)
-static struct of_device_id tcb_ids[] = {
-        { .compatible = "atmel,at91rm9200-tcb" },
-        { /*sentinel*/ }
-};
-#endif
 static void __init at91_add_device_tc(void)
 {
-#if defined(CONFIG_OF)
-        struct device_node *np;
-        np = of_find_matching_node(NULL, tcb_ids);
-        if (np) {
-                of_node_put(np);
-                return;
-        }
-#endif
        platform_device_register(&at91sam9260_tcb0_device);
        platform_device_register(&at91sam9260_tcb1_device);
 }
@@ -1229,14 +1215,6 @@ void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
                at91_uarts[portnr] = pdev;
 }
-void __init at91_set_serial_console(unsigned portnr)
-{
-        if (portnr < ATMEL_MAX_UART) {
-                atmel_default_console_device = at91_uarts[portnr];
-                at91sam9260_set_console_clock(at91_uarts[portnr]->id);
-        }
-}
 void __init at91_add_device_serial(void)
 {
        int i;
@@ -1245,13 +1223,9 @@ void __init at91_add_device_serial(void)
                if (at91_uarts[i])
                        platform_device_register(at91_uarts[i]);
        }
-        if (!atmel_default_console_device)
-                printk(KERN_INFO "AT91: No default serial console defined.\n");
 }
 #else
 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
-void __init at91_set_serial_console(unsigned portnr) {}
 void __init at91_add_device_serial(void) {}
 #endif
@@ -1369,6 +1343,93 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
 void __init at91_add_device_cf(struct at91_cf_data * data) {}
 #endif
+/* --------------------------------------------------------------------
+ *  ADCs
+ * -------------------------------------------------------------------- */
+#if IS_ENABLED(CONFIG_AT91_ADC)
+static struct at91_adc_data adc_data;
+static struct resource adc_resources[] = {
+        [0] = {
+                .start  = AT91SAM9260_BASE_ADC,
+                .end    = AT91SAM9260_BASE_ADC + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9260_ID_ADC,
+                .end    = AT91SAM9260_ID_ADC,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device at91_adc_device = {
+        .name           = "at91_adc",
+        .id             = -1,
+        .dev            = {
+                                .platform_data          = &adc_data,
+        },
+        .resource       = adc_resources,
+        .num_resources  = ARRAY_SIZE(adc_resources),
+};
+static struct at91_adc_trigger at91_adc_triggers[] = {
+        [0] = {
+                .name = "timer-counter-0",
+                .value = AT91_ADC_TRGSEL_TC0 | AT91_ADC_TRGEN,
+        },
+        [1] = {
+                .name = "timer-counter-1",
+                .value = AT91_ADC_TRGSEL_TC1 | AT91_ADC_TRGEN,
+        },
+        [2] = {
+                .name = "timer-counter-2",
+                .value = AT91_ADC_TRGSEL_TC2 | AT91_ADC_TRGEN,
+        },
+        [3] = {
+                .name = "external",
+                .value = AT91_ADC_TRGSEL_EXTERNAL | AT91_ADC_TRGEN,
+                .is_external = true,
+        },
+};
+static struct at91_adc_reg_desc at91_adc_register_g20 = {
+        .channel_base = AT91_ADC_CHR(0),
+        .drdy_mask = AT91_ADC_DRDY,
+        .status_register = AT91_ADC_SR,
+        .trigger_register = AT91_ADC_MR,
+};
+void __init at91_add_device_adc(struct at91_adc_data *data)
+{
+        if (!data)
+                return;
+        if (test_bit(0, &data->channels_used))
+                at91_set_A_periph(AT91_PIN_PC0, 0);
+        if (test_bit(1, &data->channels_used))
+                at91_set_A_periph(AT91_PIN_PC1, 0);
+        if (test_bit(2, &data->channels_used))
+                at91_set_A_periph(AT91_PIN_PC2, 0);
+        if (test_bit(3, &data->channels_used))
+                at91_set_A_periph(AT91_PIN_PC3, 0);
+        if (data->use_external_triggers)
+                at91_set_A_periph(AT91_PIN_PA22, 0);
+        data->num_channels = 4;
+        data->startup_time = 10;
+        data->registers = &at91_adc_register_g20;
+        data->trigger_number = 4;
+        data->trigger_list = at91_adc_triggers;
+        adc_data = *data;
+        platform_device_register(&at91_adc_device);
+}
+#else
+void __init at91_add_device_adc(struct at91_adc_data *data) {}
+#endif
 /* -------------------------------------------------------------------- */
 /*
 * These devices are always present and don't need any board-specific
@@ -1376,6 +1437,9 @@ void __init at91_add_device_cf(struct at91_cf_data * data) {}
 */
 static int __init at91_add_standard_devices(void)
 {
+        if (of_have_populated_dt())
+                return 0;
        at91_add_device_rtt();
        at91_add_device_watchdog();
        at91_add_device_tc();
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index 7de81e6222f1..c77d503d09d1 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -239,18 +239,6 @@ static void __init at91sam9261_register_clocks(void)
        clk_register(&hck1);
 }
-static struct clk_lookup console_clock_lookup;
-void __init at91sam9261_set_console_clock(int id)
-{
-        if (id >= ARRAY_SIZE(usart_clocks_lookups))
-                return;
-        console_clock_lookup.con_id = "usart";
-        console_clock_lookup.clk = usart_clocks_lookups[id].clk;
-        clkdev_add(&console_clock_lookup);
-}
 /* --------------------------------------------------------------------
 *  GPIO
 * -------------------------------------------------------------------- */
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
index 4db961a93085..9295e90b08ff 100644
--- a/arch/arm/mach-at91/at91sam9261_devices.c
+++ b/arch/arm/mach-at91/at91sam9261_devices.c
@@ -1051,14 +1051,6 @@ void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
                at91_uarts[portnr] = pdev;
 }
-void __init at91_set_serial_console(unsigned portnr)
-{
-        if (portnr < ATMEL_MAX_UART) {
-                atmel_default_console_device = at91_uarts[portnr];
-                at91sam9261_set_console_clock(at91_uarts[portnr]->id);
-        }
-}
 void __init at91_add_device_serial(void)
 {
        int i;
@@ -1067,13 +1059,9 @@ void __init at91_add_device_serial(void)
                if (at91_uarts[i])
                        platform_device_register(at91_uarts[i]);
        }
-        if (!atmel_default_console_device)
-                printk(KERN_INFO "AT91: No default serial console defined.\n");
 }
 #else
 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
-void __init at91_set_serial_console(unsigned portnr) {}
 void __init at91_add_device_serial(void) {}
 #endif
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index ef301be66575..ed91c7e9f7c2 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -199,6 +199,16 @@ static struct clk_lookup periph_clocks_lookups[] = {
        CLKDEV_CON_ID("pioC", &pioCDE_clk),
        CLKDEV_CON_ID("pioD", &pioCDE_clk),
        CLKDEV_CON_ID("pioE", &pioCDE_clk),
+        /* more usart lookup table for DT entries */
+        CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck),
+        CLKDEV_CON_DEV_ID("usart", "fff8c000.serial", &usart0_clk),
+        CLKDEV_CON_DEV_ID("usart", "fff90000.serial", &usart1_clk),
+        CLKDEV_CON_DEV_ID("usart", "fff94000.serial", &usart2_clk),
+        /* more tc lookup table for DT entries */
+        CLKDEV_CON_DEV_ID("t0_clk", "fff7c000.timer", &tcb_clk),
+        CLKDEV_CON_DEV_ID("hclk", "a00000.ohci", &ohci_clk),
+        CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk),
+        CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk),
 };
 static struct clk_lookup usart_clocks_lookups[] = {
@@ -255,18 +265,6 @@ static void __init at91sam9263_register_clocks(void)
        clk_register(&pck3);
 }
-static struct clk_lookup console_clock_lookup;
-void __init at91sam9263_set_console_clock(int id)
-{
-        if (id >= ARRAY_SIZE(usart_clocks_lookups))
-                return;
-        console_clock_lookup.con_id = "usart";
-        console_clock_lookup.clk = usart_clocks_lookups[id].clk;
-        clkdev_add(&console_clock_lookup);
-}
 /* --------------------------------------------------------------------
 *  GPIO
 * -------------------------------------------------------------------- */
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index fe99206de880..175e0009eaa9 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -953,8 +953,25 @@ static struct platform_device at91sam9263_tcb_device = {
        .num_resources  = ARRAY_SIZE(tcb_resources),
 };
+#if defined(CONFIG_OF)
+static struct of_device_id tcb_ids[] = {
+        { .compatible = "atmel,at91rm9200-tcb" },
+        { /*sentinel*/ }
+};
+#endif
 static void __init at91_add_device_tc(void)
 {
+#if defined(CONFIG_OF)
+        struct device_node *np;
+        np = of_find_matching_node(NULL, tcb_ids);
+        if (np) {
+                of_node_put(np);
+                return;
+        }
+#endif
        platform_device_register(&at91sam9263_tcb_device);
 }
 #else
@@ -1461,14 +1478,6 @@ void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
                at91_uarts[portnr] = pdev;
 }
-void __init at91_set_serial_console(unsigned portnr)
-{
-        if (portnr < ATMEL_MAX_UART) {
-                atmel_default_console_device = at91_uarts[portnr];
-                at91sam9263_set_console_clock(at91_uarts[portnr]->id);
-        }
-}
 void __init at91_add_device_serial(void)
 {
        int i;
@@ -1477,13 +1486,9 @@ void __init at91_add_device_serial(void)
                if (at91_uarts[i])
                        platform_device_register(at91_uarts[i]);
        }
-        if (!atmel_default_console_device)
-                printk(KERN_INFO "AT91: No default serial console defined.\n");
 }
 #else
 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
-void __init at91_set_serial_console(unsigned portnr) {}
 void __init at91_add_device_serial(void) {}
 #endif
@@ -1495,6 +1500,9 @@ void __init at91_add_device_serial(void) {}
 */
 static int __init at91_add_standard_devices(void)
 {
+        if (of_have_populated_dt())
+                return 0;
        at91_add_device_rtt();
        at91_add_device_watchdog();
        at91_add_device_tc();
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index d222f8333dab..4792682d52b9 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -176,6 +176,12 @@ static struct clk vdec_clk = {
        .type           = CLK_TYPE_PERIPHERAL,
 };
+static struct clk adc_op_clk = {
+        .name           = "adc_op_clk",
+        .type           = CLK_TYPE_PERIPHERAL,
+        .rate_hz        = 13200000,
+};
 static struct clk *periph_clocks[] __initdata = {
        &pioA_clk,
        &pioB_clk,
@@ -204,6 +210,7 @@ static struct clk *periph_clocks[] __initdata = {
        &isi_clk,
        &udphs_clk,
        &mmc1_clk,
+        &adc_op_clk,
        // irq0
 };
@@ -242,6 +249,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
        CLKDEV_CON_ID("pioC", &pioC_clk),
        CLKDEV_CON_ID("pioD", &pioDE_clk),
        CLKDEV_CON_ID("pioE", &pioDE_clk),
+        /* Fake adc clock */
+        CLKDEV_CON_ID("adc_clk", &tsc_clk),
 };
 static struct clk_lookup usart_clocks_lookups[] = {
@@ -288,18 +297,6 @@ static void __init at91sam9g45_register_clocks(void)
        clk_register(&pck1);
 }
-static struct clk_lookup console_clock_lookup;
-void __init at91sam9g45_set_console_clock(int id)
-{
-        if (id >= ARRAY_SIZE(usart_clocks_lookups))
-                return;
-        console_clock_lookup.con_id = "usart";
-        console_clock_lookup.clk = usart_clocks_lookups[id].clk;
-        clkdev_add(&console_clock_lookup);
-}
 /* --------------------------------------------------------------------
 *  GPIO
 * -------------------------------------------------------------------- */
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
index 6b008aee1dff..f6747246d649 100644
--- a/arch/arm/mach-at91/at91sam9g45_devices.c
+++ b/arch/arm/mach-at91/at91sam9g45_devices.c
@@ -19,9 +19,12 @@
 #include <linux/i2c-gpio.h>
 #include <linux/atmel-mci.h>
+#include <linux/platform_data/at91_adc.h>
 #include <linux/fb.h>
 #include <video/atmel_lcdc.h>
+#include <mach/at91_adc.h>
 #include <mach/board.h>
 #include <mach/at91sam9g45.h>
 #include <mach/at91sam9g45_matrix.h>
@@ -69,15 +72,7 @@ static struct platform_device at_hdmac_device = {
 void __init at91_add_device_hdmac(void)
 {
-#if defined(CONFIG_OF)
+        platform_device_register(&at_hdmac_device);
-        struct device_node *of_node =
-                of_find_node_by_name(NULL, "dma-controller");
-        if (of_node)
-                of_node_put(of_node);
-        else
-#endif
-                platform_device_register(&at_hdmac_device);
 }
 #else
 void __init at91_add_device_hdmac(void) {}
@@ -1094,25 +1089,8 @@ static struct platform_device at91sam9g45_tcb1_device = {
        .num_resources  = ARRAY_SIZE(tcb1_resources),
 };
-#if defined(CONFIG_OF)
-static struct of_device_id tcb_ids[] = {
-        { .compatible = "atmel,at91rm9200-tcb" },
-        { /*sentinel*/ }
-};
-#endif
 static void __init at91_add_device_tc(void)
 {
-#if defined(CONFIG_OF)
-        struct device_node *np;
-        np = of_find_matching_node(NULL, tcb_ids);
-        if (np) {
-                of_node_put(np);
-                return;
-        }
-#endif
        platform_device_register(&at91sam9g45_tcb0_device);
        platform_device_register(&at91sam9g45_tcb1_device);
 }
@@ -1207,6 +1185,104 @@ void __init at91_add_device_tsadcc(struct at91_tsadcc_data *data) {}
 /* --------------------------------------------------------------------
+ *  ADC
+ * -------------------------------------------------------------------- */
+#if IS_ENABLED(CONFIG_AT91_ADC)
+static struct at91_adc_data adc_data;
+static struct resource adc_resources[] = {
+        [0] = {
+                .start  = AT91SAM9G45_BASE_TSC,
+                .end    = AT91SAM9G45_BASE_TSC + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9G45_ID_TSC,
+                .end    = AT91SAM9G45_ID_TSC,
+                .flags  = IORESOURCE_IRQ,
+        }
+};
+static struct platform_device at91_adc_device = {
+        .name           = "at91_adc",
+        .id             = -1,
+        .dev            = {
+                                .platform_data  = &adc_data,
+        },
+        .resource       = adc_resources,
+        .num_resources  = ARRAY_SIZE(adc_resources),
+};
+static struct at91_adc_trigger at91_adc_triggers[] = {
+        [0] = {
+                .name = "external-rising",
+                .value = 1,
+                .is_external = true,
+        },
+        [1] = {
+                .name = "external-falling",
+                .value = 2,
+                .is_external = true,
+        },
+        [2] = {
+                .name = "external-any",
+                .value = 3,
+                .is_external = true,
+        },
+        [3] = {
+                .name = "continuous",
+                .value = 6,
+                .is_external = false,
+        },
+};
+static struct at91_adc_reg_desc at91_adc_register_g45 = {
+        .channel_base = AT91_ADC_CHR(0),
+        .drdy_mask = AT91_ADC_DRDY,
+        .status_register = AT91_ADC_SR,
+        .trigger_register = 0x08,
+};
+void __init at91_add_device_adc(struct at91_adc_data *data)
+{
+        if (!data)
+                return;
+        if (test_bit(0, &data->channels_used))
+                at91_set_gpio_input(AT91_PIN_PD20, 0);
+        if (test_bit(1, &data->channels_used))
+                at91_set_gpio_input(AT91_PIN_PD21, 0);
+        if (test_bit(2, &data->channels_used))
+                at91_set_gpio_input(AT91_PIN_PD22, 0);
+        if (test_bit(3, &data->channels_used))
+                at91_set_gpio_input(AT91_PIN_PD23, 0);
+        if (test_bit(4, &data->channels_used))
+                at91_set_gpio_input(AT91_PIN_PD24, 0);
+        if (test_bit(5, &data->channels_used))
+                at91_set_gpio_input(AT91_PIN_PD25, 0);
+        if (test_bit(6, &data->channels_used))
+                at91_set_gpio_input(AT91_PIN_PD26, 0);
+        if (test_bit(7, &data->channels_used))
+                at91_set_gpio_input(AT91_PIN_PD27, 0);
+        if (data->use_external_triggers)
+                at91_set_A_periph(AT91_PIN_PD28, 0);
+        data->num_channels = 8;
+        data->startup_time = 40;
+        data->registers = &at91_adc_register_g45;
+        data->trigger_number = 4;
+        data->trigger_list = at91_adc_triggers;
+        adc_data = *data;
+        platform_device_register(&at91_adc_device);
+}
+#else
+void __init at91_add_device_adc(struct at91_adc_data *data) {}
+#endif
+/* --------------------------------------------------------------------
 *  RTT
 * -------------------------------------------------------------------- */
@@ -1741,14 +1817,6 @@ void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
                at91_uarts[portnr] = pdev;
 }
-void __init at91_set_serial_console(unsigned portnr)
-{
-        if (portnr < ATMEL_MAX_UART) {
-                atmel_default_console_device = at91_uarts[portnr];
-                at91sam9g45_set_console_clock(at91_uarts[portnr]->id);
-        }
-}
 void __init at91_add_device_serial(void)
 {
        int i;
@@ -1757,13 +1825,9 @@ void __init at91_add_device_serial(void)
                if (at91_uarts[i])
                        platform_device_register(at91_uarts[i]);
        }
-        if (!atmel_default_console_device)
-                printk(KERN_INFO "AT91: No default serial console defined.\n");
 }
 #else
 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
-void __init at91_set_serial_console(unsigned portnr) {}
 void __init at91_add_device_serial(void) {}
 #endif
@@ -1775,6 +1839,9 @@ void __init at91_add_device_serial(void) {}
 */
 static int __init at91_add_standard_devices(void)
 {
+        if (of_have_populated_dt())
+                return 0;
        at91_add_device_hdmac();
        at91_add_device_rtc();
        at91_add_device_rtt();
diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c
new file mode 100644
index 000000000000..08494664ab78
--- /dev/null
+++ b/arch/arm/mach-at91/at91sam9n12.c
@@ -0,0 +1,233 @@
+/*
+ * SoC specific setup code for the AT91SAM9N12
+ *
+ * Copyright (C) 2012 Atmel Corporation.
+ *
+ * Licensed under GPLv2 or later.
+ */
+#include <linux/module.h>
+#include <linux/dma-mapping.h>
+#include <asm/irq.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <mach/at91sam9n12.h>
+#include <mach/at91_pmc.h>
+#include <mach/cpu.h>
+#include <mach/board.h>
+#include "soc.h"
+#include "generic.h"
+#include "clock.h"
+#include "sam9_smc.h"
+/* --------------------------------------------------------------------
+ *  Clocks
+ * -------------------------------------------------------------------- */
+/*
+ * The peripheral clocks.
+ */
+static struct clk pioAB_clk = {
+        .name           = "pioAB_clk",
+        .pmc_mask       = 1 << AT91SAM9N12_ID_PIOAB,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk pioCD_clk = {
+        .name           = "pioCD_clk",
+        .pmc_mask       = 1 << AT91SAM9N12_ID_PIOCD,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk usart0_clk = {
+        .name           = "usart0_clk",
+        .pmc_mask       = 1 << AT91SAM9N12_ID_USART0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk usart1_clk = {
+        .name           = "usart1_clk",
+        .pmc_mask       = 1 << AT91SAM9N12_ID_USART1,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk usart2_clk = {
+        .name           = "usart2_clk",
+        .pmc_mask       = 1 << AT91SAM9N12_ID_USART2,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk usart3_clk = {
+        .name           = "usart3_clk",
+        .pmc_mask       = 1 << AT91SAM9N12_ID_USART3,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk twi0_clk = {
+        .name           = "twi0_clk",
+        .pmc_mask       = 1 << AT91SAM9N12_ID_TWI0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk twi1_clk = {
+        .name           = "twi1_clk",
+        .pmc_mask       = 1 << AT91SAM9N12_ID_TWI1,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk mmc_clk = {
+        .name           = "mci_clk",
+        .pmc_mask       = 1 << AT91SAM9N12_ID_MCI,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk spi0_clk = {
+        .name           = "spi0_clk",
+        .pmc_mask       = 1 << AT91SAM9N12_ID_SPI0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk spi1_clk = {
+        .name           = "spi1_clk",
+        .pmc_mask       = 1 << AT91SAM9N12_ID_SPI1,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk uart0_clk = {
+        .name           = "uart0_clk",
+        .pmc_mask       = 1 << AT91SAM9N12_ID_UART0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk uart1_clk = {
+        .name           = "uart1_clk",
+        .pmc_mask       = 1 << AT91SAM9N12_ID_UART1,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk tcb_clk = {
+        .name           = "tcb_clk",
+        .pmc_mask       = 1 << AT91SAM9N12_ID_TCB,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk pwm_clk = {
+        .name           = "pwm_clk",
+        .pmc_mask       = 1 << AT91SAM9N12_ID_PWM,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk adc_clk = {
+        .name           = "adc_clk",
+        .pmc_mask       = 1 << AT91SAM9N12_ID_ADC,
+        .type   = CLK_TYPE_PERIPHERAL,
+};
+static struct clk dma_clk = {
+        .name           = "dma_clk",
+        .pmc_mask       = 1 << AT91SAM9N12_ID_DMA,
+        .type   = CLK_TYPE_PERIPHERAL,
+};
+static struct clk uhp_clk = {
+        .name           = "uhp",
+        .pmc_mask       = 1 << AT91SAM9N12_ID_UHP,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk udp_clk = {
+        .name           = "udp_clk",
+        .pmc_mask       = 1 << AT91SAM9N12_ID_UDP,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk lcdc_clk = {
+        .name           = "lcdc_clk",
+        .pmc_mask       = 1 << AT91SAM9N12_ID_LCDC,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk ssc_clk = {
+        .name           = "ssc_clk",
+        .pmc_mask       = 1 << AT91SAM9N12_ID_SSC,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk *periph_clocks[] __initdata = {
+        &pioAB_clk,
+        &pioCD_clk,
+        &usart0_clk,
+        &usart1_clk,
+        &usart2_clk,
+        &usart3_clk,
+        &twi0_clk,
+        &twi1_clk,
+        &mmc_clk,
+        &spi0_clk,
+        &spi1_clk,
+        &lcdc_clk,
+        &uart0_clk,
+        &uart1_clk,
+        &tcb_clk,
+        &pwm_clk,
+        &adc_clk,
+        &dma_clk,
+        &uhp_clk,
+        &udp_clk,
+        &ssc_clk,
+};
+static struct clk_lookup periph_clocks_lookups[] = {
+        /* lookup table for DT entries */
+        CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
+        CLKDEV_CON_DEV_ID("usart", "f801c000.serial", &usart0_clk),
+        CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart1_clk),
+        CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart2_clk),
+        CLKDEV_CON_DEV_ID("usart", "f8028000.serial", &usart3_clk),
+        CLKDEV_CON_DEV_ID("t0_clk", "f8008000.timer", &tcb_clk),
+        CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb_clk),
+        CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma_clk),
+        CLKDEV_CON_ID("pioA", &pioAB_clk),
+        CLKDEV_CON_ID("pioB", &pioAB_clk),
+        CLKDEV_CON_ID("pioC", &pioCD_clk),
+        CLKDEV_CON_ID("pioD", &pioCD_clk),
+        /* additional fake clock for macb_hclk */
+        CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &uhp_clk),
+        CLKDEV_CON_DEV_ID("ohci_clk", "500000.ohci", &uhp_clk),
+};
+/*
+ * The two programmable clocks.
+ * You must configure pin multiplexing to bring these signals out.
+ */
+static struct clk pck0 = {
+        .name           = "pck0",
+        .pmc_mask       = AT91_PMC_PCK0,
+        .type           = CLK_TYPE_PROGRAMMABLE,
+        .id             = 0,
+};
+static struct clk pck1 = {
+        .name           = "pck1",
+        .pmc_mask       = AT91_PMC_PCK1,
+        .type           = CLK_TYPE_PROGRAMMABLE,
+        .id             = 1,
+};
+static void __init at91sam9n12_register_clocks(void)
+{
+        int i;
+        for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
+                clk_register(periph_clocks[i]);
+        clk_register(&pck0);
+        clk_register(&pck1);
+        clkdev_add_table(periph_clocks_lookups,
+                         ARRAY_SIZE(periph_clocks_lookups));
+}
+/* --------------------------------------------------------------------
+ *  AT91SAM9N12 processor initialization
+ * -------------------------------------------------------------------- */
+static void __init at91sam9n12_map_io(void)
+{
+        at91_init_sram(0, AT91SAM9N12_SRAM_BASE, AT91SAM9N12_SRAM_SIZE);
+}
+void __init at91sam9n12_initialize(void)
+{
+        at91_extern_irq = (1 << AT91SAM9N12_ID_IRQ0);
+        /* Register GPIO subsystem (using DT) */
+        at91_gpio_init(NULL, 0);
+}
+struct at91_init_soc __initdata at91sam9n12_soc = {
+        .map_io = at91sam9n12_map_io,
+        .register_clocks = at91sam9n12_register_clocks,
+        .init = at91sam9n12_initialize,
+};
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index d9f2774f385e..e420085a57ef 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -232,18 +232,6 @@ static void __init at91sam9rl_register_clocks(void)
        clk_register(&pck1);
 }
-static struct clk_lookup console_clock_lookup;
-void __init at91sam9rl_set_console_clock(int id)
-{
-        if (id >= ARRAY_SIZE(usart_clocks_lookups))
-                return;
-        console_clock_lookup.con_id = "usart";
-        console_clock_lookup.clk = usart_clocks_lookups[id].clk;
-        clkdev_add(&console_clock_lookup);
-}
 /* --------------------------------------------------------------------
 *  GPIO
 * -------------------------------------------------------------------- */
diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c
index fe4ae22e8561..9c0b1481a9a7 100644
--- a/arch/arm/mach-at91/at91sam9rl_devices.c
+++ b/arch/arm/mach-at91/at91sam9rl_devices.c
@@ -1192,14 +1192,6 @@ void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
                at91_uarts[portnr] = pdev;
 }
-void __init at91_set_serial_console(unsigned portnr)
-{
-        if (portnr < ATMEL_MAX_UART) {
-                atmel_default_console_device = at91_uarts[portnr];
-                at91sam9rl_set_console_clock(at91_uarts[portnr]->id);
-        }
-}
 void __init at91_add_device_serial(void)
 {
        int i;
@@ -1208,13 +1200,9 @@ void __init at91_add_device_serial(void)
                if (at91_uarts[i])
                        platform_device_register(at91_uarts[i]);
        }
-        if (!atmel_default_console_device)
-                printk(KERN_INFO "AT91: No default serial console defined.\n");
 }
 #else
 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
-void __init at91_set_serial_console(unsigned portnr) {}
 void __init at91_add_device_serial(void) {}
 #endif
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index 13c8cae60462..1b144b4d3ce1 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -120,6 +120,11 @@ static struct clk adc_clk = {
        .pmc_mask       = 1 << AT91SAM9X5_ID_ADC,
        .type   = CLK_TYPE_PERIPHERAL,
 };
+static struct clk adc_op_clk = {
+        .name           = "adc_op_clk",
+        .type           = CLK_TYPE_PERIPHERAL,
+        .rate_hz        = 5000000,
+};
 static struct clk dma0_clk = {
        .name           = "dma0_clk",
        .pmc_mask       = 1 << AT91SAM9X5_ID_DMA0,
@@ -205,6 +210,7 @@ static struct clk *periph_clocks[] __initdata = {
        &tcb0_clk,
        &pwm_clk,
        &adc_clk,
+        &adc_op_clk,
        &dma0_clk,
        &dma1_clk,
        &uhphs_clk,
diff --git a/arch/arm/mach-at91/board-1arm.c b/arch/arm/mach-at91/board-1arm.c
index 2628384aaae1..271f994314a4 100644
--- a/arch/arm/mach-at91/board-1arm.c
+++ b/arch/arm/mach-at91/board-1arm.c
@@ -47,20 +47,6 @@ static void __init onearm_init_early(void)
        /* Initialize processor: 18.432 MHz crystal */
        at91_initialize(18432000);
-        /* DBGU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-        /* USART0 on ttyS1 (Rx, Tx, CTS, RTS) */
-        at91_register_uart(AT91RM9200_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS);
-        /* USART1 on ttyS2 (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
-        at91_register_uart(AT91RM9200_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS
-                           | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
-                           | ATMEL_UART_RI);
-        /* set serial console to ttyS0 (ie, DBGU) */
-        at91_set_serial_console(0);
 }
 static struct macb_platform_data __initdata onearm_eth_data = {
@@ -82,6 +68,16 @@ static struct at91_udc_data __initdata onearm_udc_data = {
 static void __init onearm_board_init(void)
 {
        /* Serial */
+        /* DBGU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
+        /* USART0 on ttyS1 (Rx, Tx, CTS, RTS) */
+        at91_register_uart(AT91RM9200_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS);
+        /* USART1 on ttyS2 (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
+        at91_register_uart(AT91RM9200_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS
+                           | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
+                           | ATMEL_UART_RI);
        at91_add_device_serial();
        /* Ethernet */
        at91_add_device_eth(&onearm_eth_data);
diff --git a/arch/arm/mach-at91/board-afeb-9260v1.c b/arch/arm/mach-at91/board-afeb-9260v1.c
index 161efbaa1029..b7d8aa7b81e6 100644
--- a/arch/arm/mach-at91/board-afeb-9260v1.c
+++ b/arch/arm/mach-at91/board-afeb-9260v1.c
@@ -52,22 +52,6 @@ static void __init afeb9260_init_early(void)
 {
        /* Initialize processor: 18.432 MHz crystal */
        at91_initialize(18432000);
-        /* DBGU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-        /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
-        at91_register_uart(AT91SAM9260_ID_US0, 1,
-                             ATMEL_UART_CTS | ATMEL_UART_RTS
-                           | ATMEL_UART_DTR | ATMEL_UART_DSR
-                           | ATMEL_UART_DCD | ATMEL_UART_RI);
-        /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */
-        at91_register_uart(AT91SAM9260_ID_US1, 2,
-                        ATMEL_UART_CTS | ATMEL_UART_RTS);
-        /* set serial console to ttyS0 (ie, DBGU) */
-        at91_set_serial_console(0);
 }
 /*
@@ -183,6 +167,18 @@ static struct at91_cf_data afeb9260_cf_data = {
 static void __init afeb9260_board_init(void)
 {
        /* Serial */
+        /* DBGU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
+        /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
+        at91_register_uart(AT91SAM9260_ID_US0, 1,
+                             ATMEL_UART_CTS | ATMEL_UART_RTS
+                           | ATMEL_UART_DTR | ATMEL_UART_DSR
+                           | ATMEL_UART_DCD | ATMEL_UART_RI);
+        /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */
+        at91_register_uart(AT91SAM9260_ID_US1, 2,
+                        ATMEL_UART_CTS | ATMEL_UART_RTS);
        at91_add_device_serial();
        /* USB Host */
        at91_add_device_usbh(&afeb9260_usbh_data);
diff --git a/arch/arm/mach-at91/board-cam60.c b/arch/arm/mach-at91/board-cam60.c
index c6d44ee0c77e..29d3ef0a50fb 100644
--- a/arch/arm/mach-at91/board-cam60.c
+++ b/arch/arm/mach-at91/board-cam60.c
@@ -49,12 +49,6 @@ static void __init cam60_init_early(void)
 {
        /* Initialize processor: 10 MHz crystal */
        at91_initialize(10000000);
-        /* DBGU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-        /* set serial console to ttyS0 (ie, DBGU) */
-        at91_set_serial_console(0);
 }
 /*
@@ -175,6 +169,8 @@ static void __init cam60_add_device_nand(void)
 static void __init cam60_board_init(void)
 {
        /* Serial */
+        /* DBGU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
        at91_add_device_serial();
        /* SPI */
        at91_add_device_spi(cam60_spi_devices, ARRAY_SIZE(cam60_spi_devices));
diff --git a/arch/arm/mach-at91/board-carmeva.c b/arch/arm/mach-at91/board-carmeva.c
index 59d9cf997537..44328a6d4609 100644
--- a/arch/arm/mach-at91/board-carmeva.c
+++ b/arch/arm/mach-at91/board-carmeva.c
@@ -44,17 +44,6 @@ static void __init carmeva_init_early(void)
 {
        /* Initialize processor: 20.000 MHz crystal */
        at91_initialize(20000000);
-        /* DBGU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-        /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
-        at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
-                           | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
-                           | ATMEL_UART_RI);
-        /* set serial console to ttyS0 (ie, DBGU) */
-        at91_set_serial_console(0);
 }
 static struct macb_platform_data __initdata carmeva_eth_data = {
@@ -139,6 +128,13 @@ static struct gpio_led carmeva_leds[] = {
 static void __init carmeva_board_init(void)
 {
        /* Serial */
+        /* DBGU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
+        /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
+        at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
+                           | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
+                           | ATMEL_UART_RI);
        at91_add_device_serial();
        /* Ethernet */
        at91_add_device_eth(&carmeva_eth_data);
diff --git a/arch/arm/mach-at91/board-cpu9krea.c b/arch/arm/mach-at91/board-cpu9krea.c
index 5f3680e7c883..69951ec7dbf3 100644
--- a/arch/arm/mach-at91/board-cpu9krea.c
+++ b/arch/arm/mach-at91/board-cpu9krea.c
@@ -52,34 +52,6 @@ static void __init cpu9krea_init_early(void)
 {
        /* Initialize processor: 18.432 MHz crystal */
        at91_initialize(18432000);
-        /* DGBU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-        /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
-        at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS |
-                ATMEL_UART_RTS | ATMEL_UART_DTR | ATMEL_UART_DSR |
-                ATMEL_UART_DCD | ATMEL_UART_RI);
-        /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */
-        at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS |
-                ATMEL_UART_RTS);
-        /* USART2 on ttyS3. (Rx, Tx, RTS, CTS) */
-        at91_register_uart(AT91SAM9260_ID_US2, 3, ATMEL_UART_CTS |
-                ATMEL_UART_RTS);
-        /* USART3 on ttyS4. (Rx, Tx) */
-        at91_register_uart(AT91SAM9260_ID_US3, 4, 0);
-        /* USART4 on ttyS5. (Rx, Tx) */
-        at91_register_uart(AT91SAM9260_ID_US4, 5, 0);
-        /* USART5 on ttyS6. (Rx, Tx) */
-        at91_register_uart(AT91SAM9260_ID_US5, 6, 0);
-        /* set serial console to ttyS0 (ie, DBGU) */
-        at91_set_serial_console(0);
 }
 /*
@@ -352,6 +324,30 @@ static void __init cpu9krea_board_init(void)
        /* NOR */
        cpu9krea_add_device_nor();
        /* Serial */
+        /* DGBU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
+        /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
+        at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS |
+                ATMEL_UART_RTS | ATMEL_UART_DTR | ATMEL_UART_DSR |
+                ATMEL_UART_DCD | ATMEL_UART_RI);
+        /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */
+        at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS |
+                ATMEL_UART_RTS);
+        /* USART2 on ttyS3. (Rx, Tx, RTS, CTS) */
+        at91_register_uart(AT91SAM9260_ID_US2, 3, ATMEL_UART_CTS |
+                ATMEL_UART_RTS);
+        /* USART3 on ttyS4. (Rx, Tx) */
+        at91_register_uart(AT91SAM9260_ID_US3, 4, 0);
+        /* USART4 on ttyS5. (Rx, Tx) */
+        at91_register_uart(AT91SAM9260_ID_US4, 5, 0);
+        /* USART5 on ttyS6. (Rx, Tx) */
+        at91_register_uart(AT91SAM9260_ID_US5, 6, 0);
        at91_add_device_serial();
        /* USB Host */
        at91_add_device_usbh(&cpu9krea_usbh_data);
diff --git a/arch/arm/mach-at91/board-cpuat91.c b/arch/arm/mach-at91/board-cpuat91.c
index e094cc81fe25..895cf2dba612 100644
--- a/arch/arm/mach-at91/board-cpuat91.c
+++ b/arch/arm/mach-at91/board-cpuat91.c
@@ -59,28 +59,6 @@ static void __init cpuat91_init_early(void)
        /* Initialize processor: 18.432 MHz crystal */
        at91_initialize(18432000);
-        /* DBGU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-        /* USART0 on ttyS1. (Rx, Tx, CTS, RTS) */
-        at91_register_uart(AT91RM9200_ID_US0, 1, ATMEL_UART_CTS |
-                ATMEL_UART_RTS);
-        /* USART1 on ttyS2. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
-        at91_register_uart(AT91RM9200_ID_US1, 2, ATMEL_UART_CTS |
-                ATMEL_UART_RTS | ATMEL_UART_DTR | ATMEL_UART_DSR |
-                ATMEL_UART_DCD | ATMEL_UART_RI);
-        /* USART2 on ttyS3 (Rx, Tx) */
-        at91_register_uart(AT91RM9200_ID_US2, 3, 0);
-        /* USART3 on ttyS4 (Rx, Tx, CTS, RTS) */
-        at91_register_uart(AT91RM9200_ID_US3, 4, ATMEL_UART_CTS |
-                ATMEL_UART_RTS);
-        /* set serial console to ttyS0 (ie, DBGU) */
-        at91_set_serial_console(0);
 }
 static struct macb_platform_data __initdata cpuat91_eth_data = {
@@ -161,6 +139,24 @@ static struct platform_device *platform_devices[] __initdata = {
 static void __init cpuat91_board_init(void)
 {
        /* Serial */
+        /* DBGU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
+        /* USART0 on ttyS1. (Rx, Tx, CTS, RTS) */
+        at91_register_uart(AT91RM9200_ID_US0, 1, ATMEL_UART_CTS |
+                ATMEL_UART_RTS);
+        /* USART1 on ttyS2. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
+        at91_register_uart(AT91RM9200_ID_US1, 2, ATMEL_UART_CTS |
+                ATMEL_UART_RTS | ATMEL_UART_DTR | ATMEL_UART_DSR |
+                ATMEL_UART_DCD | ATMEL_UART_RI);
+        /* USART2 on ttyS3 (Rx, Tx) */
+        at91_register_uart(AT91RM9200_ID_US2, 3, 0);
+        /* USART3 on ttyS4 (Rx, Tx, CTS, RTS) */
+        at91_register_uart(AT91RM9200_ID_US3, 4, ATMEL_UART_CTS |
+                ATMEL_UART_RTS);
        at91_add_device_serial();
        /* LEDs. */
        at91_gpio_leds(cpuat91_leds, ARRAY_SIZE(cpuat91_leds));
diff --git a/arch/arm/mach-at91/board-csb337.c b/arch/arm/mach-at91/board-csb337.c
index 1a1547b1ce4e..cd813361cd26 100644
--- a/arch/arm/mach-at91/board-csb337.c
+++ b/arch/arm/mach-at91/board-csb337.c
@@ -47,15 +47,6 @@ static void __init csb337_init_early(void)
 {
        /* Initialize processor: 3.6864 MHz crystal */
        at91_initialize(3686400);
-        /* Setup the LEDs */
-        at91_init_leds(AT91_PIN_PB0, AT91_PIN_PB1);
-        /* DBGU on ttyS0 */
-        at91_register_uart(0, 0, 0);
-        /* make console=ttyS0 the default */
-        at91_set_serial_console(0);
 }
 static struct macb_platform_data __initdata csb337_eth_data = {
@@ -228,7 +219,11 @@ static struct gpio_led csb_leds[] = {
 static void __init csb337_board_init(void)
 {
+        /* Setup the LEDs */
+        at91_init_leds(AT91_PIN_PB0, AT91_PIN_PB1);
        /* Serial */
+        /* DBGU on ttyS0 */
+        at91_register_uart(0, 0, 0);
        at91_add_device_serial();
        /* Ethernet */
        at91_add_device_eth(&csb337_eth_data);
diff --git a/arch/arm/mach-at91/board-csb637.c b/arch/arm/mach-at91/board-csb637.c
index f650bf39455d..7c8b05a57d7f 100644
--- a/arch/arm/mach-at91/board-csb637.c
+++ b/arch/arm/mach-at91/board-csb637.c
@@ -44,12 +44,6 @@ static void __init csb637_init_early(void)
 {
        /* Initialize processor: 3.6864 MHz crystal */
        at91_initialize(3686400);
-        /* DBGU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-        /* make console=ttyS0 (ie, DBGU) the default */
-        at91_set_serial_console(0);
 }
 static struct macb_platform_data __initdata csb637_eth_data = {
@@ -118,6 +112,8 @@ static void __init csb637_board_init(void)
        /* LED(s) */
        at91_gpio_leds(csb_leds, ARRAY_SIZE(csb_leds));
        /* Serial */
+        /* DBGU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
        at91_add_device_serial();
        /* Ethernet */
        at91_add_device_eth(&csb637_eth_data);
diff --git a/arch/arm/mach-at91/board-dt.c b/arch/arm/mach-at91/board-dt.c
index c18d4d307801..a1fce05aa7a5 100644
--- a/arch/arm/mach-at91/board-dt.c
+++ b/arch/arm/mach-at91/board-dt.c
@@ -1,10 +1,6 @@
 /*
 *  Setup code for AT91SAM Evaluation Kits with Device Tree support
 *
- *  Covers: * AT91SAM9G45-EKES  board
- *          * AT91SAM9M10-EKES  board
- *          * AT91SAM9M10G45-EK board
- *
 *  Copyright (C) 2011 Atmel,
 *                2011 Nicolas Ferre <nicolas.ferre@atmel.com>
 *
@@ -49,9 +45,7 @@ static void __init at91_dt_device_init(void)
 }
 static const char *at91_dt_board_compat[] __initdata = {
-        "atmel,at91sam9m10g45ek",
+        "atmel,at91sam9",
-        "atmel,at91sam9x5ek",
-        "calao,usb-a9g20",
        NULL
 };
diff --git a/arch/arm/mach-at91/board-eb9200.c b/arch/arm/mach-at91/board-eb9200.c
index d302ca3eeb64..bd1017297989 100644
--- a/arch/arm/mach-at91/board-eb9200.c
+++ b/arch/arm/mach-at91/board-eb9200.c
@@ -44,20 +44,6 @@ static void __init eb9200_init_early(void)
 {
        /* Initialize processor: 18.432 MHz crystal */
        at91_initialize(18432000);
-        /* DBGU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-        /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
-        at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
-                        | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
-                        | ATMEL_UART_RI);
-        /* USART2 on ttyS2. (Rx, Tx) - IRDA */
-        at91_register_uart(AT91RM9200_ID_US2, 2, 0);
-        /* set serial console to ttyS0 (ie, DBGU) */
-        at91_set_serial_console(0);
 }
 static struct macb_platform_data __initdata eb9200_eth_data = {
@@ -101,6 +87,16 @@ static struct i2c_board_info __initdata eb9200_i2c_devices[] = {
 static void __init eb9200_board_init(void)
 {
        /* Serial */
+        /* DBGU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
+        /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
+        at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
+                        | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
+                        | ATMEL_UART_RI);
+        /* USART2 on ttyS2. (Rx, Tx) - IRDA */
+        at91_register_uart(AT91RM9200_ID_US2, 2, 0);
        at91_add_device_serial();
        /* Ethernet */
        at91_add_device_eth(&eb9200_eth_data);
diff --git a/arch/arm/mach-at91/board-ecbat91.c b/arch/arm/mach-at91/board-ecbat91.c
index 69966ce4d776..89cc3726a9ce 100644
--- a/arch/arm/mach-at91/board-ecbat91.c
+++ b/arch/arm/mach-at91/board-ecbat91.c
@@ -50,18 +50,6 @@ static void __init ecb_at91init_early(void)
        /* Initialize processor: 18.432 MHz crystal */
        at91_initialize(18432000);
-        /* Setup the LEDs */
-        at91_init_leds(AT91_PIN_PC7, AT91_PIN_PC7);
-        /* DBGU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-        /* USART0 on ttyS1. (Rx & Tx only) */
-        at91_register_uart(AT91RM9200_ID_US0, 1, 0);
-        /* set serial console to ttyS0 (ie, DBGU) */
-        at91_set_serial_console(0);
 }
 static struct macb_platform_data __initdata ecb_at91eth_data = {
@@ -151,7 +139,15 @@ static struct spi_board_info __initdata ecb_at91spi_devices[] = {
 static void __init ecb_at91board_init(void)
 {
+        /* Setup the LEDs */
+        at91_init_leds(AT91_PIN_PC7, AT91_PIN_PC7);
        /* Serial */
+        /* DBGU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
+        /* USART0 on ttyS1. (Rx & Tx only) */
+        at91_register_uart(AT91RM9200_ID_US0, 1, 0);
        at91_add_device_serial();
        /* Ethernet */
diff --git a/arch/arm/mach-at91/board-eco920.c b/arch/arm/mach-at91/board-eco920.c
index f23aabef8551..558546cf63f4 100644
--- a/arch/arm/mach-at91/board-eco920.c
+++ b/arch/arm/mach-at91/board-eco920.c
@@ -37,15 +37,6 @@ static void __init eco920_init_early(void)
        at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
        at91_initialize(18432000);
-        /* Setup the LEDs */
-        at91_init_leds(AT91_PIN_PB0, AT91_PIN_PB1);
-        /* DBGU on ttyS0. (Rx & Tx only */
-        at91_register_uart(0, 0, 0);
-        /* set serial console to ttyS0 (ie, DBGU) */
-        at91_set_serial_console(0);
 }
 static struct macb_platform_data __initdata eco920_eth_data = {
@@ -103,6 +94,10 @@ static struct spi_board_info eco920_spi_devices[] = {
 static void __init eco920_board_init(void)
 {
+        /* Setup the LEDs */
+        at91_init_leds(AT91_PIN_PB0, AT91_PIN_PB1);
+        /* DBGU on ttyS0. (Rx & Tx only */
+        at91_register_uart(0, 0, 0);
        at91_add_device_serial();
        at91_add_device_eth(&eco920_eth_data);
        at91_add_device_usbh(&eco920_usbh_data);
diff --git a/arch/arm/mach-at91/board-flexibity.c b/arch/arm/mach-at91/board-flexibity.c
index 1815152001f7..47658f78105d 100644
--- a/arch/arm/mach-at91/board-flexibity.c
+++ b/arch/arm/mach-at91/board-flexibity.c
@@ -41,12 +41,6 @@ static void __init flexibity_init_early(void)
 {
        /* Initialize processor: 18.432 MHz crystal */
        at91_initialize(18432000);
-        /* DBGU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-        /* set serial console to ttyS0 (ie, DBGU) */
-        at91_set_serial_console(0);
 }
 /* USB Host port */
@@ -143,6 +137,8 @@ static struct gpio_led flexibity_leds[] = {
 static void __init flexibity_board_init(void)
 {
        /* Serial */
+        /* DBGU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
        at91_add_device_serial();
        /* USB Host */
        at91_add_device_usbh(&flexibity_usbh_data);
diff --git a/arch/arm/mach-at91/board-foxg20.c b/arch/arm/mach-at91/board-foxg20.c
index caf017f0f4ee..33411e6ecb1f 100644
--- a/arch/arm/mach-at91/board-foxg20.c
+++ b/arch/arm/mach-at91/board-foxg20.c
@@ -61,44 +61,6 @@ static void __init foxg20_init_early(void)
 {
        /* Initialize processor: 18.432 MHz crystal */
        at91_initialize(18432000);
-        /* DBGU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-        /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
-        at91_register_uart(AT91SAM9260_ID_US0, 1,
-                                ATMEL_UART_CTS
-                                | ATMEL_UART_RTS
-                                | ATMEL_UART_DTR
-                                | ATMEL_UART_DSR
-                                | ATMEL_UART_DCD
-                                | ATMEL_UART_RI);
-        /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */
-        at91_register_uart(AT91SAM9260_ID_US1, 2,
-                ATMEL_UART_CTS
-                | ATMEL_UART_RTS);
-        /* USART2 on ttyS3. (Rx & Tx only) */
-        at91_register_uart(AT91SAM9260_ID_US2, 3, 0);
-        /* USART3 on ttyS4. (Rx, Tx, RTS, CTS) */
-        at91_register_uart(AT91SAM9260_ID_US3, 4,
-                ATMEL_UART_CTS
-                | ATMEL_UART_RTS);
-        /* USART4 on ttyS5. (Rx & Tx only) */
-        at91_register_uart(AT91SAM9260_ID_US4, 5, 0);
-        /* USART5 on ttyS6. (Rx & Tx only) */
-        at91_register_uart(AT91SAM9260_ID_US5, 6, 0);
-        /* set serial console to ttyS0 (ie, DBGU) */
-        at91_set_serial_console(0);
-        /* Set the internal pull-up resistor on DRXD */
-        at91_set_A_periph(AT91_PIN_PB14, 1);
 }
 /*
@@ -241,6 +203,39 @@ static struct i2c_board_info __initdata foxg20_i2c_devices[] = {
 static void __init foxg20_board_init(void)
 {
        /* Serial */
+        /* DBGU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
+        /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
+        at91_register_uart(AT91SAM9260_ID_US0, 1,
+                                ATMEL_UART_CTS
+                                | ATMEL_UART_RTS
+                                | ATMEL_UART_DTR
+                                | ATMEL_UART_DSR
+                                | ATMEL_UART_DCD
+                                | ATMEL_UART_RI);
+        /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */
+        at91_register_uart(AT91SAM9260_ID_US1, 2,
+                ATMEL_UART_CTS
+                | ATMEL_UART_RTS);
+        /* USART2 on ttyS3. (Rx & Tx only) */
+        at91_register_uart(AT91SAM9260_ID_US2, 3, 0);
+        /* USART3 on ttyS4. (Rx, Tx, RTS, CTS) */
+        at91_register_uart(AT91SAM9260_ID_US3, 4,
+                ATMEL_UART_CTS
+                | ATMEL_UART_RTS);
+        /* USART4 on ttyS5. (Rx & Tx only) */
+        at91_register_uart(AT91SAM9260_ID_US4, 5, 0);
+        /* USART5 on ttyS6. (Rx & Tx only) */
+        at91_register_uart(AT91SAM9260_ID_US5, 6, 0);
+        /* Set the internal pull-up resistor on DRXD */
+        at91_set_A_periph(AT91_PIN_PB14, 1);
        at91_add_device_serial();
        /* USB Host */
        at91_add_device_usbh(&foxg20_usbh_data);
diff --git a/arch/arm/mach-at91/board-gsia18s.c b/arch/arm/mach-at91/board-gsia18s.c
index 230e71969fb7..3e0dfa643a86 100644
--- a/arch/arm/mach-at91/board-gsia18s.c
+++ b/arch/arm/mach-at91/board-gsia18s.c
@@ -41,38 +41,6 @@
 static void __init gsia18s_init_early(void)
 {
        stamp9g20_init_early();
-        /*
-         * USART0 on ttyS1 (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI).
-         * Used for Internal Analog Modem.
-         */
-        at91_register_uart(AT91SAM9260_ID_US0, 1,
-                                ATMEL_UART_CTS | ATMEL_UART_RTS |
-                                ATMEL_UART_DTR | ATMEL_UART_DSR |
-                                ATMEL_UART_DCD | ATMEL_UART_RI);
-        /*
-         * USART1 on ttyS2 (Rx, Tx, CTS, RTS).
-         * Used for GPS or WiFi or Data stream.
-         */
-        at91_register_uart(AT91SAM9260_ID_US1, 2,
-                                ATMEL_UART_CTS | ATMEL_UART_RTS);
-        /*
-         * USART2 on ttyS3 (Rx, Tx, CTS, RTS).
-         * Used for External Modem.
-         */
-        at91_register_uart(AT91SAM9260_ID_US2, 3,
-                                ATMEL_UART_CTS | ATMEL_UART_RTS);
-        /*
-         * USART3 on ttyS4 (Rx, Tx, RTS).
-         * Used for RS-485.
-         */
-        at91_register_uart(AT91SAM9260_ID_US3, 4, ATMEL_UART_RTS);
-        /*
-         * USART4 on ttyS5 (Rx, Tx).
-         * Used for TRX433 Radio Module.
-         */
-        at91_register_uart(AT91SAM9260_ID_US4, 5, 0);
 }
 /*
@@ -558,6 +526,37 @@ static int __init gsia18s_power_off_init(void)
 static void __init gsia18s_board_init(void)
 {
+        /*
+         * USART0 on ttyS1 (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI).
+         * Used for Internal Analog Modem.
+         */
+        at91_register_uart(AT91SAM9260_ID_US0, 1,
+                                ATMEL_UART_CTS | ATMEL_UART_RTS |
+                                ATMEL_UART_DTR | ATMEL_UART_DSR |
+                                ATMEL_UART_DCD | ATMEL_UART_RI);
+        /*
+         * USART1 on ttyS2 (Rx, Tx, CTS, RTS).
+         * Used for GPS or WiFi or Data stream.
+         */
+        at91_register_uart(AT91SAM9260_ID_US1, 2,
+                                ATMEL_UART_CTS | ATMEL_UART_RTS);
+        /*
+         * USART2 on ttyS3 (Rx, Tx, CTS, RTS).
+         * Used for External Modem.
+         */
+        at91_register_uart(AT91SAM9260_ID_US2, 3,
+                                ATMEL_UART_CTS | ATMEL_UART_RTS);
+        /*
+         * USART3 on ttyS4 (Rx, Tx, RTS).
+         * Used for RS-485.
+         */
+        at91_register_uart(AT91SAM9260_ID_US3, 4, ATMEL_UART_RTS);
+        /*
+         * USART4 on ttyS5 (Rx, Tx).
+         * Used for TRX433 Radio Module.
+         */
+        at91_register_uart(AT91SAM9260_ID_US4, 5, 0);
        stamp9g20_board_init();
        at91_add_device_usbh(&usbh_data);
        at91_add_device_udc(&udc_data);
diff --git a/arch/arm/mach-at91/board-kafa.c b/arch/arm/mach-at91/board-kafa.c
index efde1b2327c8..f260657f32bc 100644
--- a/arch/arm/mach-at91/board-kafa.c
+++ b/arch/arm/mach-at91/board-kafa.c
@@ -47,18 +47,6 @@ static void __init kafa_init_early(void)
        /* Initialize processor: 18.432 MHz crystal */
        at91_initialize(18432000);
-        /* Set up the LEDs */
-        at91_init_leds(AT91_PIN_PB4, AT91_PIN_PB4);
-        /* DBGU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-        /* USART0 on ttyS1 (Rx, Tx, CTS, RTS) */
-        at91_register_uart(AT91RM9200_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS);
-        /* set serial console to ttyS0 (ie, DBGU) */
-        at91_set_serial_console(0);
 }
 static struct macb_platform_data __initdata kafa_eth_data = {
@@ -79,7 +67,15 @@ static struct at91_udc_data __initdata kafa_udc_data = {
 static void __init kafa_board_init(void)
 {
+        /* Set up the LEDs */
+        at91_init_leds(AT91_PIN_PB4, AT91_PIN_PB4);
        /* Serial */
+        /* DBGU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
+        /* USART0 on ttyS1 (Rx, Tx, CTS, RTS) */
+        at91_register_uart(AT91RM9200_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS);
        at91_add_device_serial();
        /* Ethernet */
        at91_add_device_eth(&kafa_eth_data);
diff --git a/arch/arm/mach-at91/board-kb9202.c b/arch/arm/mach-at91/board-kb9202.c
index 59b92aab9bcf..ba39db5482b9 100644
--- a/arch/arm/mach-at91/board-kb9202.c
+++ b/arch/arm/mach-at91/board-kb9202.c
@@ -50,24 +50,6 @@ static void __init kb9202_init_early(void)
        /* Initialize processor: 10 MHz crystal */
        at91_initialize(10000000);
-        /* Set up the LEDs */
-        at91_init_leds(AT91_PIN_PC19, AT91_PIN_PC18);
-        /* DBGU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-        /* USART0 on ttyS1 (Rx & Tx only) */
-        at91_register_uart(AT91RM9200_ID_US0, 1, 0);
-        /* USART1 on ttyS2 (Rx & Tx only) - IRDA (optional) */
-        at91_register_uart(AT91RM9200_ID_US1, 2, 0);
-        /* USART3 on ttyS3 (Rx, Tx, CTS, RTS) - RS485 (optional) */
-        at91_register_uart(AT91RM9200_ID_US3, 3, ATMEL_UART_CTS | ATMEL_UART_RTS);
-        /* set serial console to ttyS0 (ie, DBGU) */
-        at91_set_serial_console(0);
 }
 static struct macb_platform_data __initdata kb9202_eth_data = {
@@ -115,7 +97,21 @@ static struct atmel_nand_data __initdata kb9202_nand_data = {
 static void __init kb9202_board_init(void)
 {
+        /* Set up the LEDs */
+        at91_init_leds(AT91_PIN_PC19, AT91_PIN_PC18);
        /* Serial */
+        /* DBGU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
+        /* USART0 on ttyS1 (Rx & Tx only) */
+        at91_register_uart(AT91RM9200_ID_US0, 1, 0);
+        /* USART1 on ttyS2 (Rx & Tx only) - IRDA (optional) */
+        at91_register_uart(AT91RM9200_ID_US1, 2, 0);
+        /* USART3 on ttyS3 (Rx, Tx, CTS, RTS) - RS485 (optional) */
+        at91_register_uart(AT91RM9200_ID_US3, 3, ATMEL_UART_CTS | ATMEL_UART_RTS);
        at91_add_device_serial();
        /* Ethernet */
        at91_add_device_eth(&kb9202_eth_data);
diff --git a/arch/arm/mach-at91/board-neocore926.c b/arch/arm/mach-at91/board-neocore926.c
index 57d5f6a4726a..d2f4cc161766 100644
--- a/arch/arm/mach-at91/board-neocore926.c
+++ b/arch/arm/mach-at91/board-neocore926.c
@@ -55,15 +55,6 @@ static void __init neocore926_init_early(void)
 {
        /* Initialize processor: 20 MHz crystal */
        at91_initialize(20000000);
-        /* DBGU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-        /* USART0 on ttyS1. (Rx, Tx, RTS, CTS) */
-        at91_register_uart(AT91SAM9263_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS);
-        /* set serial console to ttyS0 (ie, DBGU) */
-        at91_set_serial_console(0);
 }
 /*
@@ -341,6 +332,11 @@ static struct ac97c_platform_data neocore926_ac97_data = {
 static void __init neocore926_board_init(void)
 {
        /* Serial */
+        /* DBGU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
+        /* USART0 on ttyS1. (Rx, Tx, RTS, CTS) */
+        at91_register_uart(AT91SAM9263_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS);
        at91_add_device_serial();
        /* USB Host */
diff --git a/arch/arm/mach-at91/board-pcontrol-g20.c b/arch/arm/mach-at91/board-pcontrol-g20.c
index b4a12fc184c8..7fe638342421 100644
--- a/arch/arm/mach-at91/board-pcontrol-g20.c
+++ b/arch/arm/mach-at91/board-pcontrol-g20.c
@@ -40,17 +40,6 @@
 static void __init pcontrol_g20_init_early(void)
 {
        stamp9g20_init_early();
-        /* USART0 on ttyS1. (Rx, Tx, CTS, RTS) piggyback  A2 */
-        at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS
-                                                | ATMEL_UART_RTS);
-        /* USART1 on ttyS2. (Rx, Tx, CTS, RTS) isolated RS485  X5 */
-        at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS
-                                                | ATMEL_UART_RTS);
-        /* USART2 on ttyS3. (Rx, Tx)  9bit-Bus  Multidrop-mode  X4 */
-        at91_register_uart(AT91SAM9260_ID_US4, 3, 0);
 }
 static struct sam9_smc_config __initdata pcontrol_smc_config[2] = { {
@@ -199,6 +188,16 @@ static struct spi_board_info pcontrol_g20_spi_devices[] = {
 static void __init pcontrol_g20_board_init(void)
 {
+        /* USART0 on ttyS1. (Rx, Tx, CTS, RTS) piggyback  A2 */
+        at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS
+                                                | ATMEL_UART_RTS);
+        /* USART1 on ttyS2. (Rx, Tx, CTS, RTS) isolated RS485  X5 */
+        at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS
+                                                | ATMEL_UART_RTS);
+        /* USART2 on ttyS3. (Rx, Tx)  9bit-Bus  Multidrop-mode  X4 */
+        at91_register_uart(AT91SAM9260_ID_US4, 3, 0);
        stamp9g20_board_init();
        at91_add_device_usbh(&usbh_data);
        at91_add_device_eth(&macb_data);
diff --git a/arch/arm/mach-at91/board-picotux200.c b/arch/arm/mach-at91/board-picotux200.c
index 59e35dd14863..b45c0a5d5ca7 100644
--- a/arch/arm/mach-at91/board-picotux200.c
+++ b/arch/arm/mach-at91/board-picotux200.c
@@ -48,17 +48,6 @@ static void __init picotux200_init_early(void)
 {
        /* Initialize processor: 18.432 MHz crystal */
        at91_initialize(18432000);
-        /* DBGU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-        /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
-        at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
-                          | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
-                          | ATMEL_UART_RI);
-        /* set serial console to ttyS0 (ie, DBGU) */
-        at91_set_serial_console(0);
 }
 static struct macb_platform_data __initdata picotux200_eth_data = {
@@ -106,6 +95,13 @@ static struct platform_device picotux200_flash = {
 static void __init picotux200_board_init(void)
 {
        /* Serial */
+        /* DBGU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
+        /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
+        at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
+                          | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
+                          | ATMEL_UART_RI);
        at91_add_device_serial();
        /* Ethernet */
        at91_add_device_eth(&picotux200_eth_data);
diff --git a/arch/arm/mach-at91/board-qil-a9260.c b/arch/arm/mach-at91/board-qil-a9260.c
index b6ed5ed7081a..0c61bf0d272c 100644
--- a/arch/arm/mach-at91/board-qil-a9260.c
+++ b/arch/arm/mach-at91/board-qil-a9260.c
@@ -52,24 +52,6 @@ static void __init ek_init_early(void)
 {
        /* Initialize processor: 12.000 MHz crystal */
        at91_initialize(12000000);
-        /* DBGU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-        /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
-        at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
-                           | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
-                           | ATMEL_UART_RI);
-        /* USART1 on ttyS2. (Rx, Tx, CTS, RTS) */
-        at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS);
-        /* USART2 on ttyS3. (Rx, Tx, CTS, RTS) */
-        at91_register_uart(AT91SAM9260_ID_US2, 3, ATMEL_UART_CTS | ATMEL_UART_RTS);
-        /* set serial console to ttyS1 (ie, USART0) */
-        at91_set_serial_console(1);
 }
 /*
@@ -235,6 +217,19 @@ static struct gpio_led ek_leds[] = {
 static void __init ek_board_init(void)
 {
        /* Serial */
+        /* DBGU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
+        /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
+        at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
+                           | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
+                           | ATMEL_UART_RI);
+        /* USART1 on ttyS2. (Rx, Tx, CTS, RTS) */
+        at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS);
+        /* USART2 on ttyS3. (Rx, Tx, CTS, RTS) */
+        at91_register_uart(AT91SAM9260_ID_US2, 3, ATMEL_UART_CTS | ATMEL_UART_RTS);
        at91_add_device_serial();
        /* USB Host */
        at91_add_device_usbh(&ek_usbh_data);
diff --git a/arch/arm/mach-at91/board-rm9200dk.c b/arch/arm/mach-at91/board-rm9200dk.c
index 01332aa538b2..afd7a4713766 100644
--- a/arch/arm/mach-at91/board-rm9200dk.c
+++ b/arch/arm/mach-at91/board-rm9200dk.c
@@ -50,20 +50,6 @@ static void __init dk_init_early(void)
 {
        /* Initialize processor: 18.432 MHz crystal */
        at91_initialize(18432000);
-        /* Setup the LEDs */
-        at91_init_leds(AT91_PIN_PB2, AT91_PIN_PB2);
-        /* DBGU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-        /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
-        at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
-                           | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
-                           | ATMEL_UART_RI);
-        /* set serial console to ttyS0 (ie, DBGU) */
-        at91_set_serial_console(0);
 }
 static struct macb_platform_data __initdata dk_eth_data = {
@@ -190,7 +176,17 @@ static struct gpio_led dk_leds[] = {
 static void __init dk_board_init(void)
 {
+        /* Setup the LEDs */
+        at91_init_leds(AT91_PIN_PB2, AT91_PIN_PB2);
        /* Serial */
+        /* DBGU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
+        /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
+        at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
+                           | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
+                           | ATMEL_UART_RI);
        at91_add_device_serial();
        /* Ethernet */
        at91_add_device_eth(&dk_eth_data);
diff --git a/arch/arm/mach-at91/board-rm9200ek.c b/arch/arm/mach-at91/board-rm9200ek.c
index 11cbaa8946fe..2b15b8adec4c 100644
--- a/arch/arm/mach-at91/board-rm9200ek.c
+++ b/arch/arm/mach-at91/board-rm9200ek.c
@@ -50,20 +50,6 @@ static void __init ek_init_early(void)
 {
        /* Initialize processor: 18.432 MHz crystal */
        at91_initialize(18432000);
-        /* Setup the LEDs */
-        at91_init_leds(AT91_PIN_PB1, AT91_PIN_PB2);
-        /* DBGU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-        /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
-        at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
-                           | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
-                           | ATMEL_UART_RI);
-        /* set serial console to ttyS0 (ie, DBGU) */
-        at91_set_serial_console(0);
 }
 static struct macb_platform_data __initdata ek_eth_data = {
@@ -117,7 +103,7 @@ static struct i2c_board_info __initdata ek_i2c_devices[] = {
 };
 #define EK_FLASH_BASE   AT91_CHIPSELECT_0
-#define EK_FLASH_SIZE   SZ_2M
+#define EK_FLASH_SIZE   SZ_8M
 static struct physmap_flash_data ek_flash_data = {
        .width          = 2,
@@ -161,7 +147,17 @@ static struct gpio_led ek_leds[] = {
 static void __init ek_board_init(void)
 {
+        /* Setup the LEDs */
+        at91_init_leds(AT91_PIN_PB1, AT91_PIN_PB2);
        /* Serial */
+        /* DBGU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
+        /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
+        at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
+                           | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
+                           | ATMEL_UART_RI);
        at91_add_device_serial();
        /* Ethernet */
        at91_add_device_eth(&ek_eth_data);
diff --git a/arch/arm/mach-at91/board-rsi-ews.c b/arch/arm/mach-at91/board-rsi-ews.c
index af0750fafa29..24ab9be7510f 100644
--- a/arch/arm/mach-at91/board-rsi-ews.c
+++ b/arch/arm/mach-at91/board-rsi-ews.c
@@ -35,26 +35,6 @@ static void __init rsi_ews_init_early(void)
 {
        /* Initialize processor: 18.432 MHz crystal */
        at91_initialize(18432000);
-        /* Setup the LEDs */
-        at91_init_leds(AT91_PIN_PB6, AT91_PIN_PB9);
-        /* DBGU on ttyS0. (Rx & Tx only) */
-        /* This one is for debugging */
-        at91_register_uart(0, 0, 0);
-        /* USART1 on ttyS2. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
-        /* Dialin/-out modem interface */
-        at91_register_uart(AT91RM9200_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS
-                           | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
-                           | ATMEL_UART_RI);
-        /* USART3 on ttyS4. (Rx, Tx, RTS) */
-        /* RS485 communication */
-        at91_register_uart(AT91RM9200_ID_US3, 4, ATMEL_UART_RTS);
-        /* set serial console to ttyS0 (ie, DBGU) */
-        at91_set_serial_console(0);
 }
 /*
@@ -204,7 +184,23 @@ static struct platform_device rsiews_nor_flash = {
 */
 static void __init rsi_ews_board_init(void)
 {
+        /* Setup the LEDs */
+        at91_init_leds(AT91_PIN_PB6, AT91_PIN_PB9);
        /* Serial */
+        /* DBGU on ttyS0. (Rx & Tx only) */
+        /* This one is for debugging */
+        at91_register_uart(0, 0, 0);
+        /* USART1 on ttyS2. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
+        /* Dialin/-out modem interface */
+        at91_register_uart(AT91RM9200_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS
+                           | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
+                           | ATMEL_UART_RI);
+        /* USART3 on ttyS4. (Rx, Tx, RTS) */
+        /* RS485 communication */
+        at91_register_uart(AT91RM9200_ID_US3, 4, ATMEL_UART_RTS);
        at91_add_device_serial();
        at91_set_gpio_output(AT91_PIN_PA21, 0);
        /* Ethernet */
diff --git a/arch/arm/mach-at91/board-sam9-l9260.c b/arch/arm/mach-at91/board-sam9-l9260.c
index e8b116b6cba6..cdd21f2595d2 100644
--- a/arch/arm/mach-at91/board-sam9-l9260.c
+++ b/arch/arm/mach-at91/board-sam9-l9260.c
@@ -48,23 +48,6 @@ static void __init ek_init_early(void)
 {
        /* Initialize processor: 18.432 MHz crystal */
        at91_initialize(18432000);
-        /* Setup the LEDs */
-        at91_init_leds(AT91_PIN_PA9, AT91_PIN_PA6);
-        /* DBGU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-        /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
-        at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
-                           | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
-                           | ATMEL_UART_RI);
-        /* USART1 on ttyS2. (Rx, Tx, CTS, RTS) */
-        at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS);
-        /* set serial console to ttyS0 (ie, DBGU) */
-        at91_set_serial_console(0);
 }
 /*
@@ -184,7 +167,20 @@ static struct at91_mmc_data __initdata ek_mmc_data = {
 static void __init ek_board_init(void)
 {
+        /* Setup the LEDs */
+        at91_init_leds(AT91_PIN_PA9, AT91_PIN_PA6);
        /* Serial */
+        /* DBGU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
+        /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
+        at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
+                           | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
+                           | ATMEL_UART_RI);
+        /* USART1 on ttyS2. (Rx, Tx, CTS, RTS) */
+        at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS);
        at91_add_device_serial();
        /* USB Host */
        at91_add_device_usbh(&ek_usbh_data);
diff --git a/arch/arm/mach-at91/board-sam9260ek.c b/arch/arm/mach-at91/board-sam9260ek.c
index d5aec55b0eb4..7b3c3913551a 100644
--- a/arch/arm/mach-at91/board-sam9260ek.c
+++ b/arch/arm/mach-at91/board-sam9260ek.c
@@ -54,20 +54,6 @@ static void __init ek_init_early(void)
 {
        /* Initialize processor: 18.432 MHz crystal */
        at91_initialize(18432000);
-        /* DBGU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-        /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
-        at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
-                           | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
-                           | ATMEL_UART_RI);
-        /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */
-        at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS);
-        /* set serial console to ttyS0 (ie, DBGU) */
-        at91_set_serial_console(0);
 }
 /*
@@ -320,6 +306,16 @@ static void __init ek_add_device_buttons(void) {}
 static void __init ek_board_init(void)
 {
        /* Serial */
+        /* DBGU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
+        /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
+        at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
+                           | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
+                           | ATMEL_UART_RI);
+        /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */
+        at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS);
        at91_add_device_serial();
        /* USB Host */
        at91_add_device_usbh(&ek_usbh_data);
diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c
index c3f994462864..2736453821b0 100644
--- a/arch/arm/mach-at91/board-sam9261ek.c
+++ b/arch/arm/mach-at91/board-sam9261ek.c
@@ -58,15 +58,6 @@ static void __init ek_init_early(void)
 {
        /* Initialize processor: 18.432 MHz crystal */
        at91_initialize(18432000);
-        /* Setup the LEDs */
-        at91_init_leds(AT91_PIN_PA13, AT91_PIN_PA14);
-        /* DBGU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-        /* set serial console to ttyS0 (ie, DBGU) */
-        at91_set_serial_console(0);
 }
 /*
@@ -85,8 +76,6 @@ static struct resource dm9000_resource[] = {
                .flags  = IORESOURCE_MEM
        },
        [2] = {
-                .start  = AT91_PIN_PC11,
-                .end    = AT91_PIN_PC11,
                .flags  = IORESOURCE_IRQ
                        | IORESOURCE_IRQ_LOWEDGE | IORESOURCE_IRQ_HIGHEDGE,
        }
@@ -130,6 +119,8 @@ static struct sam9_smc_config __initdata dm9000_smc_config = {
 static void __init ek_add_device_dm9000(void)
 {
+        struct resource *r = &dm9000_resource[2];
        /* Configure chip-select 2 (DM9000) */
        sam9_smc_configure(0, 2, &dm9000_smc_config);
@@ -139,6 +130,7 @@ static void __init ek_add_device_dm9000(void)
        /* Configure Interrupt pin as input, no pull-up */
        at91_set_gpio_input(AT91_PIN_PC11, 0);
+        r->start = r->end = gpio_to_irq(AT91_PIN_PC11);
        platform_device_register(&dm9000_device);
 }
 #else
@@ -576,7 +568,12 @@ static struct gpio_led ek_leds[] = {
 static void __init ek_board_init(void)
 {
+        /* Setup the LEDs */
+        at91_init_leds(AT91_PIN_PA13, AT91_PIN_PA14);
        /* Serial */
+        /* DBGU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
        at91_add_device_serial();
        /* USB Host */
        at91_add_device_usbh(&ek_usbh_data);
diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c
index 2ffe50f3a9e9..983cb98d2465 100644
--- a/arch/arm/mach-at91/board-sam9263ek.c
+++ b/arch/arm/mach-at91/board-sam9263ek.c
@@ -57,15 +57,6 @@ static void __init ek_init_early(void)
 {
        /* Initialize processor: 16.367 MHz crystal */
        at91_initialize(16367660);
-        /* DBGU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-        /* USART0 on ttyS1. (Rx, Tx, RTS, CTS) */
-        at91_register_uart(AT91SAM9263_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS);
-        /* set serial console to ttyS0 (ie, DBGU) */
-        at91_set_serial_console(0);
 }
 /*
@@ -412,6 +403,11 @@ static struct at91_can_data ek_can_data = {
 static void __init ek_board_init(void)
 {
        /* Serial */
+        /* DBGU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
+        /* USART0 on ttyS1. (Rx, Tx, RTS, CTS) */
+        at91_register_uart(AT91SAM9263_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS);
        at91_add_device_serial();
        /* USB Host */
        at91_add_device_usbh(&ek_usbh_data);
diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c
index 8923ec9f5831..6860d3451100 100644
--- a/arch/arm/mach-at91/board-sam9g20ek.c
+++ b/arch/arm/mach-at91/board-sam9g20ek.c
@@ -32,6 +32,8 @@
 #include <linux/regulator/fixed.h>
 #include <linux/regulator/consumer.h>
+#include <linux/platform_data/at91_adc.h>
 #include <mach/hardware.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -65,20 +67,6 @@ static void __init ek_init_early(void)
 {
        /* Initialize processor: 18.432 MHz crystal */
        at91_initialize(18432000);
-        /* DBGU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-        /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
-        at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
-                           | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
-                           | ATMEL_UART_RI);
-        /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */
-        at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS);
-        /* set serial console to ttyS0 (ie, DBGU) */
-        at91_set_serial_console(0);
 }
 /*
@@ -318,6 +306,16 @@ static void __init ek_add_device_buttons(void)
 static void __init ek_add_device_buttons(void) {}
 #endif
+/*
+ * ADCs
+ */
+static struct at91_adc_data ek_adc_data = {
+        .channels_used = BIT(0) | BIT(1) | BIT(2) | BIT(3),
+        .use_external_triggers = true,
+        .vref = 3300,
+};
 #if defined(CONFIG_REGULATOR_FIXED_VOLTAGE) || defined(CONFIG_REGULATOR_FIXED_VOLTAGE_MODULE)
 static struct regulator_consumer_supply ek_audio_consumer_supplies[] = {
        REGULATOR_SUPPLY("AVDD", "0-001b"),
@@ -372,6 +370,16 @@ static struct i2c_board_info __initdata ek_i2c_devices[] = {
 static void __init ek_board_init(void)
 {
        /* Serial */
+        /* DBGU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
+        /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
+        at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
+                           | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
+                           | ATMEL_UART_RI);
+        /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */
+        at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS);
        at91_add_device_serial();
        /* USB Host */
        at91_add_device_usbh(&ek_usbh_data);
@@ -393,6 +401,8 @@ static void __init ek_board_init(void)
        ek_add_device_gpio_leds();
        /* Push Buttons */
        ek_add_device_buttons();
+        /* ADCs */
+        at91_add_device_adc(&ek_adc_data);
        /* PCK0 provides MCLK to the WM8731 */
        at91_set_B_periph(AT91_PIN_PC1, 0);
        /* SSC (for WM8731) */
diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c
index c88e908ddd82..63163dc7df46 100644
--- a/arch/arm/mach-at91/board-sam9m10g45ek.c
+++ b/arch/arm/mach-at91/board-sam9m10g45ek.c
@@ -27,6 +27,8 @@
 #include <linux/atmel-mci.h>
 #include <linux/delay.h>
+#include <linux/platform_data/at91_adc.h>
 #include <mach/hardware.h>
 #include <video/atmel_lcdc.h>
 #include <media/soc_camera.h>
@@ -53,16 +55,6 @@ static void __init ek_init_early(void)
 {
        /* Initialize processor: 12.000 MHz crystal */
        at91_initialize(12000000);
-        /* DGBU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-        /* USART0 not connected on the -EK board */
-        /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */
-        at91_register_uart(AT91SAM9G45_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS);
-        /* set serial console to ttyS0 (ie, DBGU) */
-        at91_set_serial_console(0);
 }
 /*
@@ -315,6 +307,14 @@ static struct at91_tsadcc_data ek_tsadcc_data = {
        .ts_sample_hold_time    = 0x0a,
 };
+/*
+ * ADCs
+ */
+static struct at91_adc_data ek_adc_data = {
+        .channels_used = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7),
+        .use_external_triggers = true,
+        .vref = 3300,
+};
 /*
 * GPIO Buttons
@@ -457,6 +457,12 @@ static struct platform_device *devices[] __initdata = {
 static void __init ek_board_init(void)
 {
        /* Serial */
+        /* DGBU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
+        /* USART0 not connected on the -EK board */
+        /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */
+        at91_register_uart(AT91SAM9G45_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS);
        at91_add_device_serial();
        /* USB HS Host */
        at91_add_device_usbh_ohci(&ek_usbh_hs_data);
@@ -480,6 +486,8 @@ static void __init ek_board_init(void)
        at91_add_device_lcdc(&ek_lcdc_data);
        /* Touch Screen */
        at91_add_device_tsadcc(&ek_tsadcc_data);
+        /* ADC */
+        at91_add_device_adc(&ek_adc_data);
        /* Push Buttons */
        ek_add_device_buttons();
        /* AC97 */
diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c
index b109ce2ba864..be3239f13daa 100644
--- a/arch/arm/mach-at91/board-sam9rlek.c
+++ b/arch/arm/mach-at91/board-sam9rlek.c
@@ -42,15 +42,6 @@ static void __init ek_init_early(void)
 {
        /* Initialize processor: 12.000 MHz crystal */
        at91_initialize(12000000);
-        /* DBGU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-        /* USART0 on ttyS1. (Rx, Tx, CTS, RTS) */
-        at91_register_uart(AT91SAM9RL_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS);
-        /* set serial console to ttyS0 (ie, DBGU) */
-        at91_set_serial_console(0);
 }
 /*
@@ -296,6 +287,11 @@ static void __init ek_add_device_buttons(void) {}
 static void __init ek_board_init(void)
 {
        /* Serial */
+        /* DBGU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
+        /* USART0 on ttyS1. (Rx, Tx, CTS, RTS) */
+        at91_register_uart(AT91SAM9RL_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS);
        at91_add_device_serial();
        /* USB HS */
        at91_add_device_usba(&ek_usba_udc_data);
diff --git a/arch/arm/mach-at91/board-snapper9260.c b/arch/arm/mach-at91/board-snapper9260.c
index ebc9d01ce742..9d446f1bb45f 100644
--- a/arch/arm/mach-at91/board-snapper9260.c
+++ b/arch/arm/mach-at91/board-snapper9260.c
@@ -43,16 +43,6 @@
 static void __init snapper9260_init_early(void)
 {
        at91_initialize(18432000);
-        /* Debug on ttyS0 */
-        at91_register_uart(0, 0, 0);
-        at91_set_serial_console(0);
-        at91_register_uart(AT91SAM9260_ID_US0, 1,
-                           ATMEL_UART_CTS | ATMEL_UART_RTS);
-        at91_register_uart(AT91SAM9260_ID_US1, 2,
-                           ATMEL_UART_CTS | ATMEL_UART_RTS);
-        at91_register_uart(AT91SAM9260_ID_US2, 3, 0);
 }
 static struct at91_usbh_data __initdata snapper9260_usbh_data = {
@@ -168,6 +158,14 @@ static void __init snapper9260_board_init(void)
        snapper9260_i2c_isl1208.irq = gpio_to_irq(AT91_PIN_PA31);
        i2c_register_board_info(0, &snapper9260_i2c_isl1208, 1);
+        /* Debug on ttyS0 */
+        at91_register_uart(0, 0, 0);
+        at91_register_uart(AT91SAM9260_ID_US0, 1,
+                           ATMEL_UART_CTS | ATMEL_UART_RTS);
+        at91_register_uart(AT91SAM9260_ID_US1, 2,
+                           ATMEL_UART_CTS | ATMEL_UART_RTS);
+        at91_register_uart(AT91SAM9260_ID_US2, 3, 0);
        at91_add_device_serial();
        at91_add_device_usbh(&snapper9260_usbh_data);
        at91_add_device_udc(&snapper9260_udc_data);
diff --git a/arch/arm/mach-at91/board-stamp9g20.c b/arch/arm/mach-at91/board-stamp9g20.c
index 7640049410a0..ee86f9d7ee72 100644
--- a/arch/arm/mach-at91/board-stamp9g20.c
+++ b/arch/arm/mach-at91/board-stamp9g20.c
@@ -36,44 +36,6 @@ void __init stamp9g20_init_early(void)
 {
        /* Initialize processor: 18.432 MHz crystal */
        at91_initialize(18432000);
-        /* DGBU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-        /* set serial console to ttyS0 (ie, DBGU) */
-        at91_set_serial_console(0);
-}
-static void __init stamp9g20evb_init_early(void)
-{
-        stamp9g20_init_early();
-        /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
-        at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
-                                                | ATMEL_UART_DTR | ATMEL_UART_DSR
-                                                | ATMEL_UART_DCD | ATMEL_UART_RI);
-}
-static void __init portuxg20_init_early(void)
-{
-        stamp9g20_init_early();
-        /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
-        at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
-                                                | ATMEL_UART_DTR | ATMEL_UART_DSR
-                                                | ATMEL_UART_DCD | ATMEL_UART_RI);
-        /* USART1 on ttyS2. (Rx, Tx, CTS, RTS) */
-        at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS);
-        /* USART2 on ttyS3. (Rx, Tx, CTS, RTS) */
-        at91_register_uart(AT91SAM9260_ID_US2, 3, ATMEL_UART_CTS | ATMEL_UART_RTS);
-        /* USART4 on ttyS5. (Rx, Tx only) */
-        at91_register_uart(AT91SAM9260_ID_US4, 5, 0);
-        /* USART5 on ttyS6. (Rx, Tx only) */
-        at91_register_uart(AT91SAM9260_ID_US5, 6, 0);
 }
 /*
@@ -254,6 +216,8 @@ void add_w1(void)
 void __init stamp9g20_board_init(void)
 {
        /* Serial */
+        /* DGBU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
        at91_add_device_serial();
        /* NAND */
        add_device_nand();
@@ -269,6 +233,22 @@ void __init stamp9g20_board_init(void)
 static void __init portuxg20_board_init(void)
 {
+        /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
+        at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
+                                                | ATMEL_UART_DTR | ATMEL_UART_DSR
+                                                | ATMEL_UART_DCD | ATMEL_UART_RI);
+        /* USART1 on ttyS2. (Rx, Tx, CTS, RTS) */
+        at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS);
+        /* USART2 on ttyS3. (Rx, Tx, CTS, RTS) */
+        at91_register_uart(AT91SAM9260_ID_US2, 3, ATMEL_UART_CTS | ATMEL_UART_RTS);
+        /* USART4 on ttyS5. (Rx, Tx only) */
+        at91_register_uart(AT91SAM9260_ID_US4, 5, 0);
+        /* USART5 on ttyS6. (Rx, Tx only) */
+        at91_register_uart(AT91SAM9260_ID_US5, 6, 0);
        stamp9g20_board_init();
        /* USB Host */
        at91_add_device_usbh(&usbh_data);
@@ -286,6 +266,10 @@ static void __init portuxg20_board_init(void)
 static void __init stamp9g20evb_board_init(void)
 {
+        /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
+        at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
+                                                | ATMEL_UART_DTR | ATMEL_UART_DSR
+                                                | ATMEL_UART_DCD | ATMEL_UART_RI);
        stamp9g20_board_init();
        /* USB Host */
        at91_add_device_usbh(&usbh_data);
@@ -303,7 +287,7 @@ MACHINE_START(PORTUXG20, "taskit PortuxG20")
        /* Maintainer: taskit GmbH */
        .timer          = &at91sam926x_timer,
        .map_io         = at91_map_io,
-        .init_early     = portuxg20_init_early,
+        .init_early     = stamp9g20_init_early,
        .init_irq       = at91_init_irq_default,
        .init_machine   = portuxg20_board_init,
 MACHINE_END
@@ -312,7 +296,7 @@ MACHINE_START(STAMP9G20, "taskit Stamp9G20")
        /* Maintainer: taskit GmbH */
        .timer          = &at91sam926x_timer,
        .map_io         = at91_map_io,
-        .init_early     = stamp9g20evb_init_early,
+        .init_early     = stamp9g20_init_early,
        .init_irq       = at91_init_irq_default,
        .init_machine   = stamp9g20evb_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-at91/board-usb-a926x.c b/arch/arm/mach-at91/board-usb-a926x.c
index b7483a3d0980..95393fcaf199 100644
--- a/arch/arm/mach-at91/board-usb-a926x.c
+++ b/arch/arm/mach-at91/board-usb-a926x.c
@@ -53,12 +53,6 @@ static void __init ek_init_early(void)
 {
        /* Initialize processor: 12.00 MHz crystal */
        at91_initialize(12000000);
-        /* DBGU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-        /* set serial console to ttyS0 (ie, DBGU) */
-        at91_set_serial_console(0);
 }
 /*
@@ -178,6 +172,10 @@ static struct mtd_partition __initdata ek_nand_partition[] = {
                .offset = MTDPART_OFS_NXTBLK,
                .size   = SZ_128K,
        }, {
+                .name   = "oftree",
+                .offset = MTDPART_OFS_NXTBLK,
+                .size   = SZ_128K,
+        }, {
                .name   = "kernel",
                .offset = MTDPART_OFS_NXTBLK,
                .size   = 4 * SZ_1M,
@@ -325,6 +323,8 @@ static void __init ek_add_device_leds(void)
 static void __init ek_board_init(void)
 {
        /* Serial */
+        /* DBGU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
        at91_add_device_serial();
        /* USB Host */
        at91_add_device_usbh(&ek_usbh_data);
diff --git a/arch/arm/mach-at91/board-yl-9200.c b/arch/arm/mach-at91/board-yl-9200.c
index 38dd279d30b2..d56665ea4b55 100644
--- a/arch/arm/mach-at91/board-yl-9200.c
+++ b/arch/arm/mach-at91/board-yl-9200.c
@@ -58,26 +58,6 @@ static void __init yl9200_init_early(void)
        /* Initialize processor: 18.432 MHz crystal */
        at91_initialize(18432000);
-        /* Setup the LEDs D2=PB17 (timer), D3=PB16 (cpu) */
-        at91_init_leds(AT91_PIN_PB16, AT91_PIN_PB17);
-        /* DBGU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-        /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
-        at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
-                        | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
-                        | ATMEL_UART_RI);
-        /* USART0 on ttyS2. (Rx & Tx only to JP3) */
-        at91_register_uart(AT91RM9200_ID_US0, 2, 0);
-        /* USART3 on ttyS3. (Rx, Tx, RTS - RS485 interface) */
-        at91_register_uart(AT91RM9200_ID_US3, 3, ATMEL_UART_RTS);
-        /* set serial console to ttyS0 (ie, DBGU) */
-        at91_set_serial_console(0);
 }
 /*
@@ -560,7 +540,23 @@ void __init yl9200_add_device_video(void) {}
 static void __init yl9200_board_init(void)
 {
+        /* Setup the LEDs D2=PB17 (timer), D3=PB16 (cpu) */
+        at91_init_leds(AT91_PIN_PB16, AT91_PIN_PB17);
        /* Serial */
+        /* DBGU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
+        /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
+        at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
+                        | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
+                        | ATMEL_UART_RI);
+        /* USART0 on ttyS2. (Rx & Tx only to JP3) */
+        at91_register_uart(AT91RM9200_ID_US0, 2, 0);
+        /* USART3 on ttyS3. (Rx, Tx, RTS - RS485 interface) */
+        at91_register_uart(AT91RM9200_ID_US3, 3, ATMEL_UART_RTS);
        at91_add_device_serial();
        /* Ethernet */
        at91_add_device_eth(&yl9200_eth_data);
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index a0f4d7424cdc..de2ec6b8fea7 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -35,6 +35,7 @@
 #include "generic.h"
 void __iomem *at91_pmc_base;
+EXPORT_SYMBOL_GPL(at91_pmc_base);
 /*
 * There's a lot more which can be done with clocks, including cpufreq
@@ -57,13 +58,15 @@ void __iomem *at91_pmc_base;
 #define cpu_has_800M_plla()     (  cpu_is_at91sam9g20() \
                                || cpu_is_at91sam9g45() \
-                                || cpu_is_at91sam9x5())
+                                || cpu_is_at91sam9x5() \
+                                || cpu_is_at91sam9n12())
 #define cpu_has_300M_plla()     (cpu_is_at91sam9g10())
 #define cpu_has_pllb()          (!(cpu_is_at91sam9rl() \
                                || cpu_is_at91sam9g45() \
-                                || cpu_is_at91sam9x5()))
+                                || cpu_is_at91sam9x5() \
+                                || cpu_is_at91sam9n12()))
 #define cpu_has_upll()          (cpu_is_at91sam9g45() \
                                || cpu_is_at91sam9x5())
@@ -77,12 +80,15 @@ void __iomem *at91_pmc_base;
                                || cpu_is_at91sam9x5()))
 #define cpu_has_plladiv2()      (cpu_is_at91sam9g45() \
-                                || cpu_is_at91sam9x5())
+                                || cpu_is_at91sam9x5() \
+                                || cpu_is_at91sam9n12())
 #define cpu_has_mdiv3()         (cpu_is_at91sam9g45() \
-                                || cpu_is_at91sam9x5())
+                                || cpu_is_at91sam9x5() \
+                                || cpu_is_at91sam9n12())
-#define cpu_has_alt_prescaler() (cpu_is_at91sam9x5())
+#define cpu_has_alt_prescaler() (cpu_is_at91sam9x5() \
+                                || cpu_is_at91sam9n12())
 static LIST_HEAD(clocks);
 static DEFINE_SPINLOCK(clk_lock);
diff --git a/arch/arm/mach-at91/cpuidle.c b/arch/arm/mach-at91/cpuidle.c
index ece1f9aefb47..0c6381516a5a 100644
--- a/arch/arm/mach-at91/cpuidle.c
+++ b/arch/arm/mach-at91/cpuidle.c
@@ -21,6 +21,7 @@
 #include <linux/export.h>
 #include <asm/proc-fns.h>
 #include <asm/cpuidle.h>
+#include <mach/cpu.h>
 #include "pm.h"
@@ -33,7 +34,12 @@ static int at91_enter_idle(struct cpuidle_device *dev,
                        struct cpuidle_driver *drv,
                               int index)
 {
-        at91_standby();
+        if (cpu_is_at91rm9200())
+                at91rm9200_standby();
+        else if (cpu_is_at91sam9g45())
+                at91sam9g45_standby();
+        else
+                at91sam9_standby();
        return index;
 }
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index dd9b346c451d..0a60bf837037 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -40,17 +40,6 @@ extern struct sys_timer at91sam926x_timer;
 extern struct sys_timer at91x40_timer;
 /* Clocks */
-/*
- * function to specify the clock of the default console. As we do not
- * use the device/driver bus, the dev_name is not intialize. So we need
- * to link the clock to a specific con_id only "usart"
- */
-extern void __init at91rm9200_set_console_clock(int id);
-extern void __init at91sam9260_set_console_clock(int id);
-extern void __init at91sam9261_set_console_clock(int id);
-extern void __init at91sam9263_set_console_clock(int id);
-extern void __init at91sam9rl_set_console_clock(int id);
-extern void __init at91sam9g45_set_console_clock(int id);
 #ifdef CONFIG_AT91_PMC_UNIT
 extern int __init at91_clock_init(unsigned long main_clock);
 extern int __init at91_dt_clock_init(void);
diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h
index 36604782a78f..ea2c57a86ca6 100644
--- a/arch/arm/mach-at91/include/mach/at91_pmc.h
+++ b/arch/arm/mach-at91/include/mach/at91_pmc.h
@@ -25,7 +25,7 @@ extern void __iomem *at91_pmc_base;
 #define at91_pmc_write(field, value) \
        __raw_writel(value, at91_pmc_base + field)
 #else
-.extern at91_aic_base
+.extern at91_pmc_base
 #endif
 #define AT91_PMC_SCER           0x00                    /* System Clock Enable Register */
diff --git a/arch/arm/mach-at91/include/mach/at91rm9200.h b/arch/arm/mach-at91/include/mach/at91rm9200.h
index 603e6aac2a4f..e67317c67761 100644
--- a/arch/arm/mach-at91/include/mach/at91rm9200.h
+++ b/arch/arm/mach-at91/include/mach/at91rm9200.h
@@ -88,11 +88,6 @@
 #define AT91RM9200_BASE_RTC     0xfffffe00      /* Real-Time Clock */
 #define AT91RM9200_BASE_MC      0xffffff00      /* Memory Controllers */
-#define AT91_USART0     AT91RM9200_BASE_US0
-#define AT91_USART1     AT91RM9200_BASE_US1
-#define AT91_USART2     AT91RM9200_BASE_US2
-#define AT91_USART3     AT91RM9200_BASE_US3
 /*
 * Internal Memory.
 */
diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h
index 08ae9afd00fe..416c7b6c56d3 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9260.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9260.h
@@ -95,13 +95,6 @@
 #define AT91SAM9260_BASE_WDT    0xfffffd40
 #define AT91SAM9260_BASE_GPBR   0xfffffd50
-#define AT91_USART0     AT91SAM9260_BASE_US0
-#define AT91_USART1     AT91SAM9260_BASE_US1
-#define AT91_USART2     AT91SAM9260_BASE_US2
-#define AT91_USART3     AT91SAM9260_BASE_US3
-#define AT91_USART4     AT91SAM9260_BASE_US4
-#define AT91_USART5     AT91SAM9260_BASE_US5
 /*
 * Internal Memory.
diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h
index 44fbdc12ee62..a041406d06ee 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9261.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9261.h
@@ -79,10 +79,6 @@
 #define AT91SAM9261_BASE_WDT    0xfffffd40
 #define AT91SAM9261_BASE_GPBR   0xfffffd50
-#define AT91_USART0     AT91SAM9261_BASE_US0
-#define AT91_USART1     AT91SAM9261_BASE_US1
-#define AT91_USART2     AT91SAM9261_BASE_US2
 /*
 * Internal Memory.
diff --git a/arch/arm/mach-at91/include/mach/at91sam9263.h b/arch/arm/mach-at91/include/mach/at91sam9263.h
index d96cbb2e03c4..d201029d60b3 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9263.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9263.h
@@ -95,10 +95,6 @@
 #define AT91SAM9263_BASE_RTT1   0xfffffd50
 #define AT91SAM9263_BASE_GPBR   0xfffffd60
-#define AT91_USART0     AT91SAM9263_BASE_US0
-#define AT91_USART1     AT91SAM9263_BASE_US1
-#define AT91_USART2     AT91SAM9263_BASE_US2
 #define AT91_SMC        AT91_SMC0
 /*
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h
index d052abcff852..3a4da24d5911 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9g45.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h
@@ -106,11 +106,6 @@
 #define AT91SAM9G45_BASE_RTC    0xfffffdb0
 #define AT91SAM9G45_BASE_GPBR   0xfffffd60
-#define AT91_USART0     AT91SAM9G45_BASE_US0
-#define AT91_USART1     AT91SAM9G45_BASE_US1
-#define AT91_USART2     AT91SAM9G45_BASE_US2
-#define AT91_USART3     AT91SAM9G45_BASE_US3
 /*
 * Internal Memory.
 */
diff --git a/arch/arm/mach-at91/include/mach/at91sam9n12.h b/arch/arm/mach-at91/include/mach/at91sam9n12.h
new file mode 100644
index 000000000000..d374b87c0459
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91sam9n12.h
@@ -0,0 +1,60 @@
+/*
+ * SoC specific header file for the AT91SAM9N12
+ *
+ * Copyright (C) 2012 Atmel Corporation
+ *
+ * Common definitions, based on AT91SAM9N12 SoC datasheet
+ *
+ * Licensed under GPLv2 or later
+ */
+#ifndef _AT91SAM9N12_H_
+#define _AT91SAM9N12_H_
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define AT91SAM9N12_ID_PIOAB    2       /* Parallel I/O Controller A and B */
+#define AT91SAM9N12_ID_PIOCD    3       /* Parallel I/O Controller C and D */
+#define AT91SAM9N12_ID_FUSE     4       /* FUSE Controller */
+#define AT91SAM9N12_ID_USART0   5       /* USART 0 */
+#define AT91SAM9N12_ID_USART1   6       /* USART 1 */
+#define AT91SAM9N12_ID_USART2   7       /* USART 2 */
+#define AT91SAM9N12_ID_USART3   8       /* USART 3 */
+#define AT91SAM9N12_ID_TWI0     9       /* Two-Wire Interface 0 */
+#define AT91SAM9N12_ID_TWI1     10      /* Two-Wire Interface 1 */
+#define AT91SAM9N12_ID_MCI      12      /* High Speed Multimedia Card Interface */
+#define AT91SAM9N12_ID_SPI0     13      /* Serial Peripheral Interface 0 */
+#define AT91SAM9N12_ID_SPI1     14      /* Serial Peripheral Interface 1 */
+#define AT91SAM9N12_ID_UART0    15      /* UART 0 */
+#define AT91SAM9N12_ID_UART1    16      /* UART 1 */
+#define AT91SAM9N12_ID_TCB      17      /* Timer Counter 0, 1, 2, 3, 4 and 5 */
+#define AT91SAM9N12_ID_PWM      18      /* Pulse Width Modulation Controller */
+#define AT91SAM9N12_ID_ADC      19      /* ADC Controller */
+#define AT91SAM9N12_ID_DMA      20      /* DMA Controller */
+#define AT91SAM9N12_ID_UHP      22      /* USB Host High Speed */
+#define AT91SAM9N12_ID_UDP      23      /* USB Device High Speed */
+#define AT91SAM9N12_ID_LCDC     25      /* LCD Controller */
+#define AT91SAM9N12_ID_ISI      25      /* Image Sensor Interface */
+#define AT91SAM9N12_ID_SSC      28      /* Synchronous Serial Controller */
+#define AT91SAM9N12_ID_TRNG     30      /* TRNG */
+#define AT91SAM9N12_ID_IRQ0     31      /* Advanced Interrupt Controller */
+/*
+ * User Peripheral physical base addresses.
+ */
+#define AT91SAM9N12_BASE_USART0 0xf801c000
+#define AT91SAM9N12_BASE_USART1 0xf8020000
+#define AT91SAM9N12_BASE_USART2 0xf8024000
+#define AT91SAM9N12_BASE_USART3 0xf8028000
+/*
+ * Internal Memory.
+ */
+#define AT91SAM9N12_SRAM_BASE   0x00300000      /* Internal SRAM base address */
+#define AT91SAM9N12_SRAM_SIZE   SZ_32K          /* Internal SRAM size (32Kb) */
+#define AT91SAM9N12_ROM_BASE    0x00100000      /* Internal ROM base address */
+#define AT91SAM9N12_ROM_SIZE    SZ_128K         /* Internal ROM size (128Kb) */
+#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9n12_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9n12_matrix.h
new file mode 100644
index 000000000000..40060cd62fa9
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91sam9n12_matrix.h
@@ -0,0 +1,53 @@
+/*
+ * Matrix-centric header file for the AT91SAM9N12
+ *
+ * Copyright (C) 2012 Atmel Corporation.
+ *
+ * Only EBI related registers.
+ * Write Protect register definitions may be useful.
+ *
+ * Licensed under GPLv2 or later.
+ */
+#ifndef _AT91SAM9N12_MATRIX_H_
+#define _AT91SAM9N12_MATRIX_H_
+#define AT91_MATRIX_EBICSA      (AT91_MATRIX + 0x118)   /* EBI Chip Select Assignment Register */
+#define         AT91_MATRIX_EBI_CS1A            (1 << 1)        /* Chip Select 1 Assignment */
+#define                 AT91_MATRIX_EBI_CS1A_SMC                (0 << 1)
+#define                 AT91_MATRIX_EBI_CS1A_SDRAMC             (1 << 1)
+#define         AT91_MATRIX_EBI_CS3A            (1 << 3)        /* Chip Select 3 Assignment */
+#define                 AT91_MATRIX_EBI_CS3A_SMC                (0 << 3)
+#define                 AT91_MATRIX_EBI_CS3A_SMC_NANDFLASH      (1 << 3)
+#define         AT91_MATRIX_EBI_DBPUC           (1 << 8)        /* Data Bus Pull-up Configuration */
+#define                 AT91_MATRIX_EBI_DBPU_ON                 (0 << 8)
+#define                 AT91_MATRIX_EBI_DBPU_OFF                (1 << 8)
+#define         AT91_MATRIX_EBI_VDDIOMSEL       (1 << 16)       /* Memory voltage selection */
+#define                 AT91_MATRIX_EBI_VDDIOMSEL_1_8V          (0 << 16)
+#define                 AT91_MATRIX_EBI_VDDIOMSEL_3_3V          (1 << 16)
+#define         AT91_MATRIX_EBI_EBI_IOSR        (1 << 17)       /* EBI I/O slew rate selection */
+#define                 AT91_MATRIX_EBI_EBI_IOSR_REDUCED        (0 << 17)
+#define                 AT91_MATRIX_EBI_EBI_IOSR_NORMAL         (1 << 17)
+#define         AT91_MATRIX_EBI_DDR_IOSR        (1 << 18)       /* DDR2 dedicated port I/O slew rate selection */
+#define                 AT91_MATRIX_EBI_DDR_IOSR_REDUCED        (0 << 18)
+#define                 AT91_MATRIX_EBI_DDR_IOSR_NORMAL         (1 << 18)
+#define         AT91_MATRIX_NFD0_SELECT         (1 << 24)       /* NAND Flash Data Bus Selection */
+#define                 AT91_MATRIX_NFD0_ON_D0                  (0 << 24)
+#define                 AT91_MATRIX_NFD0_ON_D16                 (1 << 24)
+#define         AT91_MATRIX_DDR_MP_EN           (1 << 25)       /* DDR Multi-port Enable */
+#define                 AT91_MATRIX_MP_OFF                      (0 << 25)
+#define                 AT91_MATRIX_MP_ON                       (1 << 25)
+#define AT91_MATRIX_WPMR        (AT91_MATRIX + 0x1E4)   /* Write Protect Mode Register */
+#define         AT91_MATRIX_WPMR_WPEN           (1 << 0)        /* Write Protect ENable */
+#define                 AT91_MATRIX_WPMR_WP_WPDIS               (0 << 0)
+#define                 AT91_MATRIX_WPMR_WP_WPEN                (1 << 0)
+#define         AT91_MATRIX_WPMR_WPKEY          (0xFFFFFF << 8) /* Write Protect KEY */
+#define AT91_MATRIX_WPSR        (AT91_MATRIX + 0x1E8)   /* Write Protect Status Register */
+#define         AT91_MATRIX_WPSR_WPVS           (1 << 0)        /* Write Protect Violation Status */
+#define                 AT91_MATRIX_WPSR_NO_WPV         (0 << 0)
+#define                 AT91_MATRIX_WPSR_WPV            (1 << 0)
+#define         AT91_MATRIX_WPSR_WPVSRC         (0xFFFF << 8)   /* Write Protect Violation Source */
+#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9rl.h b/arch/arm/mach-at91/include/mach/at91sam9rl.h
index e0073eb10144..a15db56d33fa 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9rl.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9rl.h
@@ -89,11 +89,6 @@
 #define AT91SAM9RL_BASE_GPBR    0xfffffd60
 #define AT91SAM9RL_BASE_RTC     0xfffffe00
-#define AT91_USART0     AT91SAM9RL_BASE_US0
-#define AT91_USART1     AT91SAM9RL_BASE_US1
-#define AT91_USART2     AT91SAM9RL_BASE_US2
-#define AT91_USART3     AT91SAM9RL_BASE_US3
 /*
 * Internal Memory.
diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h
index 88e43d534cdf..c75ee19b58d3 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9x5.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h
@@ -55,14 +55,6 @@
 #define AT91SAM9X5_BASE_USART2  0xf8024000
 /*
- * Base addresses for early serial code (uncompress.h)
- */
-#define AT91_DBGU       AT91_BASE_DBGU0
-#define AT91_USART0     AT91SAM9X5_BASE_USART0
-#define AT91_USART1     AT91SAM9X5_BASE_USART1
-#define AT91_USART2     AT91SAM9X5_BASE_USART2
-/*
 * Internal Memory.
 */
 #define AT91SAM9X5_SRAM_BASE    0x00300000      /* Internal SRAM base address */
diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h
index 49a821192c65..369afc2ffc5b 100644
--- a/arch/arm/mach-at91/include/mach/board.h
+++ b/arch/arm/mach-at91/include/mach/board.h
@@ -121,7 +121,6 @@ extern void __init at91_add_device_spi(struct spi_board_info *devices, int nr_de
 #define ATMEL_UART_RI   0x20
 extern void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins);
-extern void __init at91_set_serial_console(unsigned portnr);
 extern struct platform_device *atmel_default_console_device;
diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h
index 0118c3338552..b6504c19d55c 100644
--- a/arch/arm/mach-at91/include/mach/cpu.h
+++ b/arch/arm/mach-at91/include/mach/cpu.h
@@ -25,6 +25,7 @@
 #define ARCH_ID_AT91SAM9G45MRL  0x819b05a2      /* aka 9G45-ES2 & non ES lots */
 #define ARCH_ID_AT91SAM9G45ES   0x819b05a1      /* 9G45-ES (Engineering Sample) */
 #define ARCH_ID_AT91SAM9X5      0x819a05a0
+#define ARCH_ID_AT91SAM9N12     0x819a07a0
 #define ARCH_ID_AT91SAM9XE128   0x329973a0
 #define ARCH_ID_AT91SAM9XE256   0x329a93a0
@@ -54,6 +55,7 @@
 #define ARCH_REVISON_9200_BGA   (0 << 0)
 #define ARCH_REVISON_9200_PQFP  (1 << 0)
+#ifndef __ASSEMBLY__
 enum at91_soc_type {
        /* 920T */
        AT91_SOC_RM9200,
@@ -70,6 +72,9 @@ enum at91_soc_type {
        /* SAM9X5 */
        AT91_SOC_SAM9X5,
+        /* SAM9N12 */
+        AT91_SOC_SAM9N12,
        /* Unknown type */
        AT91_SOC_NONE
 };
@@ -106,7 +111,7 @@ static inline int at91_soc_is_detected(void)
        return at91_soc_initdata.type != AT91_SOC_NONE;
 }
-#ifdef CONFIG_ARCH_AT91RM9200
+#ifdef CONFIG_SOC_AT91RM9200
 #define cpu_is_at91rm9200()     (at91_soc_initdata.type == AT91_SOC_RM9200)
 #define cpu_is_at91rm9200_bga() (at91_soc_initdata.subtype == AT91_SOC_RM9200_BGA)
 #define cpu_is_at91rm9200_pqfp() (at91_soc_initdata.subtype == AT91_SOC_RM9200_PQFP)
@@ -116,45 +121,37 @@ static inline int at91_soc_is_detected(void)
 #define cpu_is_at91rm9200_pqfp() (0)
 #endif
-#ifdef CONFIG_ARCH_AT91SAM9260
+#ifdef CONFIG_SOC_AT91SAM9260
 #define cpu_is_at91sam9xe()     (at91_soc_initdata.subtype == AT91_SOC_SAM9XE)
 #define cpu_is_at91sam9260()    (at91_soc_initdata.type == AT91_SOC_SAM9260)
+#define cpu_is_at91sam9g20()    (at91_soc_initdata.type == AT91_SOC_SAM9G20)
 #else
 #define cpu_is_at91sam9xe()     (0)
 #define cpu_is_at91sam9260()    (0)
-#endif
-#ifdef CONFIG_ARCH_AT91SAM9G20
-#define cpu_is_at91sam9g20()    (at91_soc_initdata.type == AT91_SOC_SAM9G20)
-#else
 #define cpu_is_at91sam9g20()    (0)
 #endif
-#ifdef CONFIG_ARCH_AT91SAM9261
+#ifdef CONFIG_SOC_AT91SAM9261
 #define cpu_is_at91sam9261()    (at91_soc_initdata.type == AT91_SOC_SAM9261)
-#else
-#define cpu_is_at91sam9261()    (0)
-#endif
-#ifdef CONFIG_ARCH_AT91SAM9G10
 #define cpu_is_at91sam9g10()    (at91_soc_initdata.type == AT91_SOC_SAM9G10)
 #else
+#define cpu_is_at91sam9261()    (0)
 #define cpu_is_at91sam9g10()    (0)
 #endif
-#ifdef CONFIG_ARCH_AT91SAM9263
+#ifdef CONFIG_SOC_AT91SAM9263
 #define cpu_is_at91sam9263()    (at91_soc_initdata.type == AT91_SOC_SAM9263)
 #else
 #define cpu_is_at91sam9263()    (0)
 #endif
-#ifdef CONFIG_ARCH_AT91SAM9RL
+#ifdef CONFIG_SOC_AT91SAM9RL
 #define cpu_is_at91sam9rl()     (at91_soc_initdata.type == AT91_SOC_SAM9RL)
 #else
 #define cpu_is_at91sam9rl()     (0)
 #endif
-#ifdef CONFIG_ARCH_AT91SAM9G45
+#ifdef CONFIG_SOC_AT91SAM9G45
 #define cpu_is_at91sam9g45()    (at91_soc_initdata.type == AT91_SOC_SAM9G45)
 #define cpu_is_at91sam9g45es()  (at91_soc_initdata.subtype == AT91_SOC_SAM9G45ES)
 #define cpu_is_at91sam9m10()    (at91_soc_initdata.subtype == AT91_SOC_SAM9M10)
@@ -168,7 +165,7 @@ static inline int at91_soc_is_detected(void)
 #define cpu_is_at91sam9m11()    (0)
 #endif
-#ifdef CONFIG_ARCH_AT91SAM9X5
+#ifdef CONFIG_SOC_AT91SAM9X5
 #define cpu_is_at91sam9x5()     (at91_soc_initdata.type == AT91_SOC_SAM9X5)
 #define cpu_is_at91sam9g15()    (at91_soc_initdata.subtype == AT91_SOC_SAM9G15)
 #define cpu_is_at91sam9g35()    (at91_soc_initdata.subtype == AT91_SOC_SAM9G35)
@@ -184,10 +181,17 @@ static inline int at91_soc_is_detected(void)
 #define cpu_is_at91sam9x25()    (0)
 #endif
+#ifdef CONFIG_SOC_AT91SAM9N12
+#define cpu_is_at91sam9n12()    (at91_soc_initdata.type == AT91_SOC_SAM9N12)
+#else
+#define cpu_is_at91sam9n12()    (0)
+#endif
 /*
 * Since this is ARM, we will never run on any AVR32 CPU. But these
 * definitions may reduce clutter in common drivers.
 */
 #define cpu_is_at32ap7000()     (0)
+#endif /* __ASSEMBLY__ */
 #endif /* __MACH_CPU_H__ */
diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h
index e9e29a6c3868..09242b67d277 100644
--- a/arch/arm/mach-at91/include/mach/hardware.h
+++ b/arch/arm/mach-at91/include/mach/hardware.h
@@ -22,27 +22,18 @@
 /* 9263, 9g45 */
 #define AT91_BASE_DBGU1 0xffffee00
-#if defined(CONFIG_ARCH_AT91RM9200)
+#if defined(CONFIG_ARCH_AT91X40)
+#include <mach/at91x40.h>
+#else
 #include <mach/at91rm9200.h>
-#elif defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9G20)
 #include <mach/at91sam9260.h>
-#elif defined(CONFIG_ARCH_AT91SAM9261) || defined(CONFIG_ARCH_AT91SAM9G10)
 #include <mach/at91sam9261.h>
-#elif defined(CONFIG_ARCH_AT91SAM9263)
 #include <mach/at91sam9263.h>
-#elif defined(CONFIG_ARCH_AT91SAM9RL)
 #include <mach/at91sam9rl.h>
-#elif defined(CONFIG_ARCH_AT91SAM9G45)
 #include <mach/at91sam9g45.h>
-#elif defined(CONFIG_ARCH_AT91SAM9X5)
 #include <mach/at91sam9x5.h>
-#elif defined(CONFIG_ARCH_AT91X40)
+#include <mach/at91sam9n12.h>
-#include <mach/at91x40.h>
-#else
-#error "Unsupported AT91 processor"
-#endif
-#if !defined(CONFIG_ARCH_AT91X40)
 /*
 * On all at91 except rm9200 and x40 have the System Controller starts
 * at address 0xffffc000 and has a size of 16KiB.
@@ -94,7 +85,6 @@
 * Virtual to Physical Address mapping for IO devices.
 */
 #define AT91_VA_BASE_SYS        AT91_IO_P2V(AT91_BASE_SYS)
-#define AT91_VA_BASE_EMAC       AT91_IO_P2V(AT91RM9200_BASE_EMAC)
 /* Internal SRAM is mapped below the IO devices */
 #define AT91_SRAM_MAX           SZ_1M
diff --git a/arch/arm/mach-at91/include/mach/uncompress.h b/arch/arm/mach-at91/include/mach/uncompress.h
index 4218647c1fcd..6f6118d1576a 100644
--- a/arch/arm/mach-at91/include/mach/uncompress.h
+++ b/arch/arm/mach-at91/include/mach/uncompress.h
@@ -1,7 +1,8 @@
 /*
 * arch/arm/mach-at91/include/mach/uncompress.h
 *
- *  Copyright (C) 2003 SAN People
+ * Copyright (C) 2003 SAN People
+ * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
@@ -25,22 +26,147 @@
 #include <linux/atmel_serial.h>
 #include <mach/hardware.h>
-#if defined(CONFIG_AT91_EARLY_DBGU0)
+#include <mach/at91_dbgu.h>
-#define UART_OFFSET AT91_BASE_DBGU0
+#include <mach/cpu.h>
-#elif defined(CONFIG_AT91_EARLY_DBGU1)
-#define UART_OFFSET AT91_BASE_DBGU1
+void __iomem *at91_uart;
-#elif defined(CONFIG_AT91_EARLY_USART0)
-#define UART_OFFSET AT91_USART0
+#if !defined(CONFIG_ARCH_AT91X40)
-#elif defined(CONFIG_AT91_EARLY_USART1)
+static const u32 uarts_rm9200[] = {
-#define UART_OFFSET AT91_USART1
+        AT91_BASE_DBGU0,
-#elif defined(CONFIG_AT91_EARLY_USART2)
+        AT91RM9200_BASE_US0,
-#define UART_OFFSET AT91_USART2
+        AT91RM9200_BASE_US1,
-#elif defined(CONFIG_AT91_EARLY_USART3)
+        AT91RM9200_BASE_US2,
-#define UART_OFFSET AT91_USART3
+        AT91RM9200_BASE_US3,
-#elif defined(CONFIG_AT91_EARLY_USART4)
+        0,
-#define UART_OFFSET AT91_USART4
+};
-#elif defined(CONFIG_AT91_EARLY_USART5)
-#define UART_OFFSET AT91_USART5
+static const u32 uarts_sam9260[] = {
+        AT91_BASE_DBGU0,
+        AT91SAM9260_BASE_US0,
+        AT91SAM9260_BASE_US1,
+        AT91SAM9260_BASE_US2,
+        AT91SAM9260_BASE_US3,
+        AT91SAM9260_BASE_US4,
+        AT91SAM9260_BASE_US5,
+        0,
+};
+static const u32 uarts_sam9261[] = {
+        AT91_BASE_DBGU0,
+        AT91SAM9261_BASE_US0,
+        AT91SAM9261_BASE_US1,
+        AT91SAM9261_BASE_US2,
+        0,
+};
+static const u32 uarts_sam9263[] = {
+        AT91_BASE_DBGU1,
+        AT91SAM9263_BASE_US0,
+        AT91SAM9263_BASE_US1,
+        AT91SAM9263_BASE_US2,
+        0,
+};
+static const u32 uarts_sam9g45[] = {
+        AT91_BASE_DBGU1,
+        AT91SAM9G45_BASE_US0,
+        AT91SAM9G45_BASE_US1,
+        AT91SAM9G45_BASE_US2,
+        AT91SAM9G45_BASE_US3,
+        0,
+};
+static const u32 uarts_sam9rl[] = {
+        AT91_BASE_DBGU0,
+        AT91SAM9RL_BASE_US0,
+        AT91SAM9RL_BASE_US1,
+        AT91SAM9RL_BASE_US2,
+        AT91SAM9RL_BASE_US3,
+        0,
+};
+static const u32 uarts_sam9x5[] = {
+        AT91_BASE_DBGU0,
+        AT91SAM9X5_BASE_USART0,
+        AT91SAM9X5_BASE_USART1,
+        AT91SAM9X5_BASE_USART2,
+        0,
+};
+static inline const u32* decomp_soc_detect(u32 dbgu_base)
+{
+        u32 cidr, socid;
+        cidr = __raw_readl(dbgu_base + AT91_DBGU_CIDR);
+        socid = cidr & ~AT91_CIDR_VERSION;
+        switch (socid) {
+        case ARCH_ID_AT91RM9200:
+                return uarts_rm9200;
+        case ARCH_ID_AT91SAM9G20:
+        case ARCH_ID_AT91SAM9260:
+                return uarts_sam9260;
+        case ARCH_ID_AT91SAM9261:
+                return uarts_sam9261;
+        case ARCH_ID_AT91SAM9263:
+                return uarts_sam9263;
+        case ARCH_ID_AT91SAM9G45:
+                return uarts_sam9g45;
+        case ARCH_ID_AT91SAM9RL64:
+                return uarts_sam9rl;
+        case ARCH_ID_AT91SAM9X5:
+                return uarts_sam9x5;
+        }
+        /* at91sam9g10 */
+        if ((cidr & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) {
+                return uarts_sam9261;
+        }
+        /* at91sam9xe */
+        else if ((cidr & AT91_CIDR_ARCH) == ARCH_FAMILY_AT91SAM9XE) {
+                return uarts_sam9260;
+        }
+        return NULL;
+}
+static inline void arch_decomp_setup(void)
+{
+        int i = 0;
+        const u32* usarts;
+        usarts = decomp_soc_detect(AT91_BASE_DBGU0);
+        if (!usarts)
+                usarts = decomp_soc_detect(AT91_BASE_DBGU1);
+        if (!usarts) {
+                at91_uart = NULL;
+                return;
+        }
+        do {
+                /* physical address */
+                at91_uart = (void __iomem *)usarts[i];
+                if (__raw_readl(at91_uart + ATMEL_US_BRGR))
+                        return;
+                i++;
+        } while (usarts[i]);
+        at91_uart = NULL;
+}
+#else
+static inline void arch_decomp_setup(void)
+{
+        at91_uart = NULL;
+}
 #endif
 /*
@@ -52,28 +178,24 @@
 */
 static void putc(int c)
 {
-#ifdef UART_OFFSET
+        if (!at91_uart)
-        void __iomem *sys = (void __iomem *) UART_OFFSET;       /* physical address */
+                return;
-        while (!(__raw_readl(sys + ATMEL_US_CSR) & ATMEL_US_TXRDY))
+        while (!(__raw_readl(at91_uart + ATMEL_US_CSR) & ATMEL_US_TXRDY))
                barrier();
-        __raw_writel(c, sys + ATMEL_US_THR);
+        __raw_writel(c, at91_uart + ATMEL_US_THR);
-#endif
 }
 static inline void flush(void)
 {
-#ifdef UART_OFFSET
+        if (!at91_uart)
-        void __iomem *sys = (void __iomem *) UART_OFFSET;       /* physical address */
+                return;
        /* wait for transmission to complete */
-        while (!(__raw_readl(sys + ATMEL_US_CSR) & ATMEL_US_TXEMPTY))
+        while (!(__raw_readl(at91_uart + ATMEL_US_CSR) & ATMEL_US_TXEMPTY))
                barrier();
-#endif
 }
-#define arch_decomp_setup()
 #define arch_decomp_wdog()
 #endif
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index f630250c6b87..1bfaad628731 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -261,7 +261,12 @@ static int at91_pm_enter(suspend_state_t state)
                         * For ARM 926 based chips, this requirement is weaker
                         * as at91sam9 can access a RAM in self-refresh mode.
                         */
-                        at91_standby();
+                        if (cpu_is_at91rm9200())
+                                at91rm9200_standby();
+                        else if (cpu_is_at91sam9g45())
+                                at91sam9g45_standby();
+                        else
+                                at91sam9_standby();
                        break;
                case PM_SUSPEND_ON:
@@ -307,10 +312,9 @@ static int __init at91_pm_init(void)
        pr_info("AT91: Power Management%s\n", (slow_clock ? " (with slow clock mode)" : ""));
-#ifdef CONFIG_ARCH_AT91RM9200
        /* AT91RM9200 SDRAM low-power mode cannot be used with self-refresh. */
-        at91_ramc_write(0, AT91RM9200_SDRAMC_LPR, 0);
+        if (cpu_is_at91rm9200())
-#endif
+                at91_ramc_write(0, AT91RM9200_SDRAMC_LPR, 0);
        suspend_set_ops(&at91_pm_ops);
diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h
index 89f56f3a802e..38f467c6b710 100644
--- a/arch/arm/mach-at91/pm.h
+++ b/arch/arm/mach-at91/pm.h
@@ -12,7 +12,6 @@
 #define __ARCH_ARM_MACH_AT91_PM
 #include <mach/at91_ramc.h>
-#ifdef CONFIG_ARCH_AT91RM9200
 #include <mach/at91rm9200_sdramc.h>
 /*
@@ -43,10 +42,6 @@ static inline void at91rm9200_standby(void)
                  "r" (lpr));
 }
-#define at91_standby at91rm9200_standby
-#elif defined(CONFIG_ARCH_AT91SAM9G45)
 /* We manage both DDRAM/SDRAM controllers, we need more than one value to
 * remember.
 */
@@ -75,11 +70,7 @@ static inline void at91sam9g45_standby(void)
        at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
 }
-#define at91_standby at91sam9g45_standby
+#ifdef CONFIG_SOC_AT91SAM9263
-#else
-#ifdef CONFIG_ARCH_AT91SAM9263
 /*
 * FIXME either or both the SDRAM controllers (EB0, EB1) might be in use;
 * handle those cases both here and in the Suspend-To-RAM support.
@@ -102,8 +93,4 @@ static inline void at91sam9_standby(void)
        at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr);
 }
-#define at91_standby at91sam9_standby
-#endif
 #endif
diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S
index db5452123f17..098c28ddf025 100644
--- a/arch/arm/mach-at91/pm_slowclock.S
+++ b/arch/arm/mach-at91/pm_slowclock.S
@@ -18,7 +18,7 @@
 #include <mach/at91_ramc.h>
-#ifdef CONFIG_ARCH_AT91SAM9263
+#ifdef CONFIG_SOC_AT91SAM9263
 /*
 * FIXME either or both the SDRAM controllers (EB0, EB1) might be in use;
 * handle those cases both here and in the Suspend-To-RAM support.
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index 97cc04dc8073..944bffb08991 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -54,6 +54,7 @@ void __init at91_init_interrupts(unsigned int *priority)
 }
 void __iomem *at91_ramc_base[2];
+EXPORT_SYMBOL_GPL(at91_ramc_base);
 void __init at91_ioremap_ramc(int id, u32 addr, u32 size)
 {
@@ -142,6 +143,11 @@ static void __init soc_detect(u32 dbgu_base)
                at91_soc_initdata.type = AT91_SOC_SAM9X5;
                at91_boot_soc = at91sam9x5_soc;
                break;
+        case ARCH_ID_AT91SAM9N12:
+                at91_soc_initdata.type = AT91_SOC_SAM9N12;
+                at91_boot_soc = at91sam9n12_soc;
+                break;
        }
        /* at91sam9g10 */
@@ -209,6 +215,7 @@ static const char *soc_name[] = {
        [AT91_SOC_SAM9G45]      = "at91sam9g45",
        [AT91_SOC_SAM9RL]       = "at91sam9rl",
        [AT91_SOC_SAM9X5]       = "at91sam9x5",
+        [AT91_SOC_SAM9N12]      = "at91sam9n12",
        [AT91_SOC_NONE]         = "Unknown"
 };
@@ -292,6 +299,7 @@ void __init at91_ioremap_rstc(u32 base_addr)
 }
 void __iomem *at91_matrix_base;
+EXPORT_SYMBOL_GPL(at91_matrix_base);
 void __init at91_ioremap_matrix(u32 base_addr)
 {
diff --git a/arch/arm/mach-at91/soc.h b/arch/arm/mach-at91/soc.h
index 5db4aa45404a..a9cfeb153719 100644
--- a/arch/arm/mach-at91/soc.h
+++ b/arch/arm/mach-at91/soc.h
@@ -20,36 +20,41 @@ extern struct at91_init_soc at91sam9263_soc;
 extern struct at91_init_soc at91sam9g45_soc;
 extern struct at91_init_soc at91sam9rl_soc;
 extern struct at91_init_soc at91sam9x5_soc;
+extern struct at91_init_soc at91sam9n12_soc;
 static inline int at91_soc_is_enabled(void)
 {
        return at91_boot_soc.init != NULL;
 }
-#if !defined(CONFIG_ARCH_AT91RM9200)
+#if !defined(CONFIG_SOC_AT91RM9200)
 #define at91rm9200_soc  at91_boot_soc
 #endif
-#if !(defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9G20))
+#if !defined(CONFIG_SOC_AT91SAM9260)
 #define at91sam9260_soc at91_boot_soc
 #endif
-#if !(defined(CONFIG_ARCH_AT91SAM9261) || defined(CONFIG_ARCH_AT91SAM9G10))
+#if !defined(CONFIG_SOC_AT91SAM9261)
 #define at91sam9261_soc at91_boot_soc
 #endif
-#if !defined(CONFIG_ARCH_AT91SAM9263)
+#if !defined(CONFIG_SOC_AT91SAM9263)
 #define at91sam9263_soc at91_boot_soc
 #endif
-#if !defined(CONFIG_ARCH_AT91SAM9G45)
+#if !defined(CONFIG_SOC_AT91SAM9G45)
 #define at91sam9g45_soc at91_boot_soc
 #endif
-#if !defined(CONFIG_ARCH_AT91SAM9RL)
+#if !defined(CONFIG_SOC_AT91SAM9RL)
 #define at91sam9rl_soc  at91_boot_soc
 #endif
-#if !defined(CONFIG_ARCH_AT91SAM9X5)
+#if !defined(CONFIG_SOC_AT91SAM9X5)
 #define at91sam9x5_soc  at91_boot_soc
 #endif
+#if !defined(CONFIG_SOC_AT91SAM9N12)
+#define at91sam9n12_soc at91_boot_soc
+#endif
diff --git a/arch/arm/mach-bcmring/core.c b/arch/arm/mach-bcmring/core.c
index 22e4e0a28ad1..adbfb1994582 100644
--- a/arch/arm/mach-bcmring/core.c
+++ b/arch/arm/mach-bcmring/core.c
@@ -52,8 +52,8 @@
 #include <mach/csp/chipcHw_inline.h>
 #include <mach/csp/tmrHw_reg.h>
-static AMBA_APB_DEVICE(uartA, "uarta", MM_ADDR_IO_UARTA, { IRQ_UARTA }, NULL);
+static AMBA_APB_DEVICE(uartA, "uartA", 0, MM_ADDR_IO_UARTA, {IRQ_UARTA}, NULL);
-static AMBA_APB_DEVICE(uartB, "uartb", MM_ADDR_IO_UARTB, { IRQ_UARTB }, NULL);
+static AMBA_APB_DEVICE(uartB, "uartB", 0, MM_ADDR_IO_UARTB, {IRQ_UARTB}, NULL);
 static struct clk pll1_clk = {
        .name = "PLL1",
diff --git a/arch/arm/mach-clps711x/Kconfig b/arch/arm/mach-clps711x/Kconfig
index eb34bd1251d4..ea036d621581 100644
--- a/arch/arm/mach-clps711x/Kconfig
+++ b/arch/arm/mach-clps711x/Kconfig
@@ -1,6 +1,6 @@
 if ARCH_CLPS711X
-menu "CLPS711X/EP721X Implementations"
+menu "CLPS711X/EP721X/EP731X Implementations"
 config ARCH_AUTCPU12
        bool "AUTCPU12"
@@ -45,26 +45,13 @@ config ARCH_P720T
 config ARCH_FORTUNET
        bool "FORTUNET"
-# XXX Maybe these should indicate register compatibility
-# instead of being mutually exclusive.
-config ARCH_EP7211
-        bool
-        depends on ARCH_EDB7211
-        default y
-config ARCH_EP7212
-        bool
-        depends on ARCH_P720T || ARCH_CEIVA
-        default y
 config EP72XX_ROM_BOOT
-        bool "EP72xx ROM boot"
+        bool "EP721x/EP731x ROM boot"
-        depends on ARCH_EP7211 || ARCH_EP7212
+        help
-        ---help---
          If you say Y here, your CLPS711x-based kernel will use the bootstrap
          mode memory map instead of the normal memory map.
-          Processors derived from the Cirrus CLPS-711X core support two boot
+          Processors derived from the Cirrus CLPS711X core support two boot
          modes.  Normal mode boots from the external memory device at CS0.
          Bootstrap mode rearranges parts of the memory map, placing an
          internal 128 byte bootstrap ROM at CS0.  This option performs the
diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c
index 3c5b5bbf24e5..c965fd8eb31a 100644
--- a/arch/arm/mach-clps711x/common.c
+++ b/arch/arm/mach-clps711x/common.c
@@ -36,7 +36,6 @@
 #include <asm/page.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
-#include <asm/hardware/clps7111.h>
 #include <asm/system_misc.h>
 /*
@@ -44,8 +43,8 @@
 */
 static struct map_desc clps711x_io_desc[] __initdata = {
        {
-                .virtual        = CLPS7111_VIRT_BASE,
+                .virtual        = (unsigned long)CLPS711X_VIRT_BASE,
-                .pfn            = __phys_to_pfn(CLPS7111_PHYS_BASE),
+                .pfn            = __phys_to_pfn(CLPS711X_PHYS_BASE),
                .length         = SZ_1M,
                .type           = MT_DEVICE
        }
@@ -67,12 +66,6 @@ static void int1_mask(struct irq_data *d)
 static void int1_ack(struct irq_data *d)
 {
-        u32 intmr1;
-        intmr1 = clps_readl(INTMR1);
-        intmr1 &= ~(1 << d->irq);
-        clps_writel(intmr1, INTMR1);
        switch (d->irq) {
        case IRQ_CSINT:  clps_writel(0, COEOI);  break;
        case IRQ_TC1OI:  clps_writel(0, TC1EOI); break;
@@ -109,12 +102,6 @@ static void int2_mask(struct irq_data *d)
 static void int2_ack(struct irq_data *d)
 {
-        u32 intmr2;
-        intmr2 = clps_readl(INTMR2);
-        intmr2 &= ~(1 << (d->irq - 16));
-        clps_writel(intmr2, INTMR2);
        switch (d->irq) {
        case IRQ_KBDINT: clps_writel(0, KBDEOI); break;
        }
diff --git a/arch/arm/include/asm/hardware/clps7111.h b/arch/arm/mach-clps711x/include/mach/clps711x.h
index 44477225aed6..1dd806f2847e 100644
--- a/arch/arm/include/asm/hardware/clps7111.h
+++ b/arch/arm/mach-clps711x/include/mach/clps711x.h
@@ -1,8 +1,6 @@
 /*
- *  arch/arm/include/asm/hardware/clps7111.h
+ *  This file contains the hardware definitions of the Cirrus Logic
- *
+ *  ARM7 CLPS711X internal registers.
- *  This file contains the hardware definitions of the CLPS7111 internal
- *  registers.
 *
 *  Copyright (C) 2000 Deep Blue Solutions Ltd.
 *
@@ -20,25 +18,18 @@
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
-#ifndef __ASM_HARDWARE_CLPS7111_H
+#ifndef __MACH_CLPS711X_H
-#define __ASM_HARDWARE_CLPS7111_H
+#define __MACH_CLPS711X_H
-#define CLPS7111_PHYS_BASE      (0x80000000)
-#ifndef __ASSEMBLY__
+#define CLPS711X_PHYS_BASE      (0x80000000)
-#define clps_readb(off)         __raw_readb(CLPS7111_BASE + (off))
-#define clps_readw(off)         __raw_readw(CLPS7111_BASE + (off))
-#define clps_readl(off)         __raw_readl(CLPS7111_BASE + (off))
-#define clps_writeb(val,off)    __raw_writeb(val, CLPS7111_BASE + (off))
-#define clps_writew(val,off)    __raw_writew(val, CLPS7111_BASE + (off))
-#define clps_writel(val,off)    __raw_writel(val, CLPS7111_BASE + (off))
-#endif
 #define PADR            (0x0000)
 #define PBDR            (0x0001)
+#define PCDR            (0x0002)
 #define PDDR            (0x0003)
 #define PADDR           (0x0040)
 #define PBDDR           (0x0041)
+#define PCDDR           (0x0042)
 #define PDDDR           (0x0043)
 #define PEDR            (0x0080)
 #define PEDDR           (0x00c0)
@@ -50,7 +41,7 @@
 #define INTSR1          (0x0240)
 #define INTMR1          (0x0280)
 #define LCDCON          (0x02c0)
-#define TC1D            (0x0300)
+#define TC1D            (0x0300)
 #define TC2D            (0x0340)
 #define RTCDR           (0x0380)
 #define RTCMR           (0x03c0)
@@ -85,6 +76,26 @@
 #define SS2POP          (0x16c0)
 #define KBDEOI          (0x1700)
+#define DAIR            (0x2000)
+#define DAIR0           (0x2040)
+#define DAIDR1          (0x2080)
+#define DAIDR2          (0x20c0)
+#define DAISR           (0x2100)
+#define SYSCON3         (0x2200)
+#define INTSR3          (0x2240)
+#define INTMR3          (0x2280)
+#define LEDFLSH         (0x22c0)
+#define SDCONF          (0x2300)
+#define SDRFPR          (0x2340)
+#define UNIQID          (0x2440)
+#define DAI64FS         (0x2600)
+#define PLLW            (0x2610)
+#define PLLR            (0xa5a8)
+#define RANDID0         (0x2700)
+#define RANDID1         (0x2704)
+#define RANDID2         (0x2708)
+#define RANDID3         (0x270c)
 /* common bits: SYSCON1 / SYSCON2 */
 #define SYSCON_UARTEN           (1 << 8)
@@ -131,6 +142,8 @@
 #define SYSFLG1_CTXFF           (1 << 25)
 #define SYSFLG1_SSIBUSY         (1 << 26)
 #define SYSFLG1_ID              (1 << 29)
+#define SYSFLG1_VERID(x)        (((x) >> 30) & 3)
+#define SYSFLG1_VERID_MASK      (3 << 30)
 #define SYSFLG2_SSRXOF          (1 << 0)
 #define SYSFLG2_RESVAL          (1 << 1)
@@ -178,7 +191,88 @@
 #define UBRLCR_WRDLEN8          (3 << 17)
 #define UBRLCR_WRDLEN_MASK      (3 << 17)
+#define SYNCIO_FRMLEN(x)        (((x) & 0x3f) << 7)
+#define SYNCIO_CFGLEN(x)        ((x) & 0x7f)
 #define SYNCIO_SMCKEN           (1 << 13)
 #define SYNCIO_TXFRMEN          (1 << 14)
-#endif /* __ASM_HARDWARE_CLPS7111_H */
+#define DAIR_RESERVED           (0x0404)
+#define DAIR_DAIEN              (1 << 16)
+#define DAIR_ECS                (1 << 17)
+#define DAIR_LCTM               (1 << 19)
+#define DAIR_LCRM               (1 << 20)
+#define DAIR_RCTM               (1 << 21)
+#define DAIR_RCRM               (1 << 22)
+#define DAIR_LBM                (1 << 23)
+#define DAIDR2_FIFOEN           (1 << 15)
+#define DAIDR2_FIFOLEFT         (0x0d << 16)
+#define DAIDR2_FIFORIGHT        (0x11 << 16)
+#define DAISR_RCTS              (1 << 0)
+#define DAISR_RCRS              (1 << 1)
+#define DAISR_LCTS              (1 << 2)
+#define DAISR_LCRS              (1 << 3)
+#define DAISR_RCTU              (1 << 4)
+#define DAISR_RCRO              (1 << 5)
+#define DAISR_LCTU              (1 << 6)
+#define DAISR_LCRO              (1 << 7)
+#define DAISR_RCNF              (1 << 8)
+#define DAISR_RCNE              (1 << 9)
+#define DAISR_LCNF              (1 << 10)
+#define DAISR_LCNE              (1 << 11)
+#define DAISR_FIFO              (1 << 12)
+#define DAI64FS_I2SF64          (1 << 0)
+#define DAI64FS_AUDIOCLKEN      (1 << 1)
+#define DAI64FS_AUDIOCLKSRC     (1 << 2)
+#define DAI64FS_MCLK256EN       (1 << 3)
+#define DAI64FS_LOOPBACK        (1 << 5)
+#define SYSCON3_ADCCON          (1 << 0)
+#define SYSCON3_CLKCTL0         (1 << 1)
+#define SYSCON3_CLKCTL1         (1 << 2)
+#define SYSCON3_DAISEL          (1 << 3)
+#define SYSCON3_ADCCKNSEN       (1 << 4)
+#define SYSCON3_VERSN(x)        (((x) >> 5) & 7)
+#define SYSCON3_VERSN_MASK      (7 << 5)
+#define SYSCON3_FASTWAKE        (1 << 8)
+#define SYSCON3_DAIEN           (1 << 9)
+#define SYSCON3_128FS           SYSCON3_DAIEN
+#define SYSCON3_ENPD67          (1 << 10)
+#define SDCONF_ACTIVE           (1 << 10)
+#define SDCONF_CLKCTL           (1 << 9)
+#define SDCONF_WIDTH_4          (0 << 7)
+#define SDCONF_WIDTH_8          (1 << 7)
+#define SDCONF_WIDTH_16         (2 << 7)
+#define SDCONF_WIDTH_32         (3 << 7)
+#define SDCONF_SIZE_16          (0 << 5)
+#define SDCONF_SIZE_64          (1 << 5)
+#define SDCONF_SIZE_128         (2 << 5)
+#define SDCONF_SIZE_256         (3 << 5)
+#define SDCONF_CASLAT_2         (2)
+#define SDCONF_CASLAT_3         (3)
+#define MEMCFG_BUS_WIDTH_32     (1)
+#define MEMCFG_BUS_WIDTH_16     (0)
+#define MEMCFG_BUS_WIDTH_8      (3)
+#define MEMCFG_WAITSTATE_8_3    (0 << 2)
+#define MEMCFG_WAITSTATE_7_3    (1 << 2)
+#define MEMCFG_WAITSTATE_6_3    (2 << 2)
+#define MEMCFG_WAITSTATE_5_3    (3 << 2)
+#define MEMCFG_WAITSTATE_4_2    (4 << 2)
+#define MEMCFG_WAITSTATE_3_2    (5 << 2)
+#define MEMCFG_WAITSTATE_2_2    (6 << 2)
+#define MEMCFG_WAITSTATE_1_2    (7 << 2)
+#define MEMCFG_WAITSTATE_8_1    (8 << 2)
+#define MEMCFG_WAITSTATE_7_1    (9 << 2)
+#define MEMCFG_WAITSTATE_6_1    (10 << 2)
+#define MEMCFG_WAITSTATE_5_1    (11 << 2)
+#define MEMCFG_WAITSTATE_4_0    (12 << 2)
+#define MEMCFG_WAITSTATE_3_0    (13 << 2)
+#define MEMCFG_WAITSTATE_2_0    (14 << 2)
+#define MEMCFG_WAITSTATE_1_0    (15 << 2)
+#endif /* __MACH_CLPS711X_H */
diff --git a/arch/arm/mach-clps711x/include/mach/debug-macro.S b/arch/arm/mach-clps711x/include/mach/debug-macro.S
index b802e8a51831..118b3d930573 100644
--- a/arch/arm/mach-clps711x/include/mach/debug-macro.S
+++ b/arch/arm/mach-clps711x/include/mach/debug-macro.S
@@ -12,7 +12,6 @@
 */
 #include <mach/hardware.h>
-#include <asm/hardware/clps7111.h>
                .macro  addruart, rp, rv, tmp
 #ifndef CONFIG_DEBUG_CLPS711X_UART2
@@ -20,8 +19,8 @@
 #else
                mov     \rp, #0x1000    @ UART2
 #endif
-                orr     \rv, \rp, #CLPS7111_VIRT_BASE
+                orr     \rv, \rp, #CLPS711X_VIRT_BASE
-                orr     \rp, \rp, #CLPS7111_PHYS_BASE
+                orr     \rp, \rp, #CLPS711X_PHYS_BASE
                .endm
                .macro  senduart,rd,rx
diff --git a/arch/arm/mach-clps711x/include/mach/entry-macro.S b/arch/arm/mach-clps711x/include/mach/entry-macro.S
index 125af59d7a29..56e5c2c23504 100644
--- a/arch/arm/mach-clps711x/include/mach/entry-macro.S
+++ b/arch/arm/mach-clps711x/include/mach/entry-macro.S
@@ -8,7 +8,6 @@
 * warranty of any kind, whether express or implied.
 */
 #include <mach/hardware.h>
-#include <asm/hardware/clps7111.h>
                .macro  get_irqnr_preamble, base, tmp
                .endm
@@ -18,7 +17,7 @@
 #endif
                .macro  get_irqnr_and_base, irqnr, stat, base, mask
-                mov     \base, #CLPS7111_BASE
+                mov     \base, #CLPS711X_VIRT_BASE
                ldr     \stat, [\base, #INTSR1]
                ldr     \mask, [\base, #INTMR1]
                mov     \irqnr, #4
diff --git a/arch/arm/mach-clps711x/include/mach/hardware.h b/arch/arm/mach-clps711x/include/mach/hardware.h
index d0b7d870be9c..13a64fcd7dd1 100644
--- a/arch/arm/mach-clps711x/include/mach/hardware.h
+++ b/arch/arm/mach-clps711x/include/mach/hardware.h
@@ -19,12 +19,21 @@
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
-#ifndef __ASM_ARCH_HARDWARE_H
+#ifndef __MACH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
+#define __MACH_HARDWARE_H
+#include <mach/clps711x.h>
-#define CLPS7111_VIRT_BASE      0xff000000
+#define CLPS711X_VIRT_BASE      IOMEM(0xff000000)
-#define CLPS7111_BASE           CLPS7111_VIRT_BASE
+#ifndef __ASSEMBLY__
+#define clps_readb(off)         readb(CLPS711X_VIRT_BASE + (off))
+#define clps_readw(off)         readw(CLPS711X_VIRT_BASE + (off))
+#define clps_readl(off)         readl(CLPS711X_VIRT_BASE + (off))
+#define clps_writeb(val,off)    writeb(val, CLPS711X_VIRT_BASE + (off))
+#define clps_writew(val,off)    writew(val, CLPS711X_VIRT_BASE + (off))
+#define clps_writel(val,off)    writel(val, CLPS711X_VIRT_BASE + (off))
+#endif
 /*
 * The physical addresses that the external chip select signals map to is
@@ -52,46 +61,11 @@
 #define CS7_PHYS_BASE           (0x00000000)
 #endif
-#if defined (CONFIG_ARCH_EP7211)
-#define EP7211_VIRT_BASE        CLPS7111_VIRT_BASE
-#define EP7211_BASE             CLPS7111_VIRT_BASE
-#include <asm/hardware/ep7211.h>
-#elif defined (CONFIG_ARCH_EP7212)
-#define EP7212_VIRT_BASE        CLPS7111_VIRT_BASE
-#define EP7212_BASE             CLPS7111_VIRT_BASE
-#include <asm/hardware/ep7212.h>
-#endif
 #define SYSPLD_VIRT_BASE        0xfe000000
 #define SYSPLD_BASE             SYSPLD_VIRT_BASE
-#if  defined (CONFIG_ARCH_AUTCPU12)
-#define  CS89712_VIRT_BASE      CLPS7111_VIRT_BASE
-#define  CS89712_BASE           CLPS7111_VIRT_BASE
-#include <asm/hardware/clps7111.h>
-#include <asm/hardware/ep7212.h>
-#include <asm/hardware/cs89712.h>
-#endif
 #if defined (CONFIG_ARCH_CDB89712)
-#include <asm/hardware/clps7111.h>
-#include <asm/hardware/ep7212.h>
-#include <asm/hardware/cs89712.h>
-/* static cdb89712_map_io() areas */
-#define REGISTER_START   0x80000000
-#define REGISTER_SIZE    0x4000
-#define REGISTER_BASE    0xff000000
 #define ETHER_START      0x20000000
 #define ETHER_SIZE       0x1000
 #define ETHER_BASE       0xfe000000
@@ -154,13 +128,6 @@
 #if defined (CONFIG_ARCH_CEIVA)
-#define  CEIVA_VIRT_BASE        CLPS7111_VIRT_BASE
-#define  CEIVA_BASE             CLPS7111_VIRT_BASE
-#include <asm/hardware/clps7111.h>
-#include <asm/hardware/ep7212.h>
 /*
 * The two flash banks are wired to chip selects 0 and 1. This is the mapping
 * for them.
diff --git a/arch/arm/mach-clps711x/include/mach/irqs.h b/arch/arm/mach-clps711x/include/mach/irqs.h
index 30b7e97285a4..14d215f8ca81 100644
--- a/arch/arm/mach-clps711x/include/mach/irqs.h
+++ b/arch/arm/mach-clps711x/include/mach/irqs.h
@@ -35,7 +35,6 @@
 #define IRQ_SSEOTI                      15
 #define INT1_IRQS                       (0x0000fff0)
-#define INT1_ACK_IRQS                   (0x00004f10)
 /*
 * Interrupts from INTSR2
@@ -47,7 +46,5 @@
 #define IRQ_URXINT2                     (16+13) /* bit 13 */
 #define INT2_IRQS                       (0x30070000)
-#define INT2_ACK_IRQS                   (0x00010000)
-#define NR_IRQS                         30
+#define NR_IRQS                         30
diff --git a/arch/arm/mach-clps711x/include/mach/time.h b/arch/arm/mach-clps711x/include/mach/time.h
deleted file mode 100644
index 61fef9129c6a..000000000000
--- a/arch/arm/mach-clps711x/include/mach/time.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- *  arch/arm/mach-clps711x/include/mach/time.h
- *
- *  Copyright (C) 2000 Deep Blue Solutions Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <asm/leds.h>
-#include <asm/hardware/clps7111.h>
-extern void clps711x_setup_timer(void);
-/*
- * IRQ handler for the timer
- */
-static irqreturn_t
-p720t_timer_interrupt(int irq, void *dev_id)
-{
-        struct pt_regs *regs = get_irq_regs();
-        do_leds();
-        xtime_update(1);
-#ifndef CONFIG_SMP
-        update_process_times(user_mode(regs));
-#endif
-        do_profile(regs);
-        return IRQ_HANDLED;
-}
-/*
- * Set up timer interrupt, and return the current time in seconds.
- */
-void __init time_init(void)
-{
-        clps711x_setup_timer();
-        timer_irq.handler = p720t_timer_interrupt;
-        setup_irq(IRQ_TC2OI, &timer_irq);
-}
diff --git a/arch/arm/mach-clps711x/include/mach/uncompress.h b/arch/arm/mach-clps711x/include/mach/uncompress.h
index 35ed731b9f16..7b28d6a47690 100644
--- a/arch/arm/mach-clps711x/include/mach/uncompress.h
+++ b/arch/arm/mach-clps711x/include/mach/uncompress.h
@@ -17,14 +17,7 @@
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
-#include <mach/hardware.h>
+#include <mach/clps711x.h>
-#include <asm/hardware/clps7111.h>
-#undef CLPS7111_BASE
-#define CLPS7111_BASE CLPS7111_PHYS_BASE
-#define __raw_readl(p)          (*(unsigned long *)(p))
-#define __raw_writel(v,p)       (*(unsigned long *)(p) = (v))
 #ifdef CONFIG_DEBUG_CLPS711X_UART2
 #define SYSFLGx SYSFLG2
@@ -34,19 +27,25 @@
 #define UARTDRx UARTDR1
 #endif
+#define phys_reg(x)     (*(volatile u32 *)(CLPS711X_PHYS_BASE + (x)))
 /*
+ * The following code assumes the serial port has already been
+ * initialized by the bootloader.  If you didn't setup a port in
+ * your bootloader then nothing will appear (which might be desired).
+ *
 * This does not append a newline
 */
 static inline void putc(int c)
 {
-        while (clps_readl(SYSFLGx) & SYSFLG_UTXFF)
+        while (phys_reg(SYSFLGx) & SYSFLG_UTXFF)
                barrier();
-        clps_writel(c, UARTDRx);
+        phys_reg(UARTDRx) = c;
 }
 static inline void flush(void)
 {
-        while (clps_readl(SYSFLGx) & SYSFLG_UBUSY)
+        while (phys_reg(SYSFLGx) & SYSFLG_UBUSY)
                barrier();
 }
diff --git a/arch/arm/mach-clps711x/p720t-leds.c b/arch/arm/mach-clps711x/p720t-leds.c
index dd9a6cdbeb02..bbc449fbe14a 100644
--- a/arch/arm/mach-clps711x/p720t-leds.c
+++ b/arch/arm/mach-clps711x/p720t-leds.c
@@ -27,9 +27,6 @@
 #include <asm/leds.h>
 #include <asm/mach-types.h>
-#include <asm/hardware/clps7111.h>
-#include <asm/hardware/ep7212.h>
 static void p720t_leds_event(led_event_t ledevt)
 {
        unsigned long flags;
diff --git a/arch/arm/mach-cns3xxx/pcie.c b/arch/arm/mach-cns3xxx/pcie.c
index 79d001f831e0..311328314163 100644
--- a/arch/arm/mach-cns3xxx/pcie.c
+++ b/arch/arm/mach-cns3xxx/pcie.c
@@ -166,12 +166,6 @@ static struct pci_ops cns3xxx_pcie_ops = {
        .write = cns3xxx_pci_write_config,
 };
-static struct pci_bus *cns3xxx_pci_scan_bus(int nr, struct pci_sys_data *sys)
-{
-        return pci_scan_root_bus(NULL, sys->busnr, &cns3xxx_pcie_ops, sys,
-                                 &sys->resources);
-}
 static int cns3xxx_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 {
        struct cns3xxx_pcie *cnspci = pdev_to_cnspci(dev);
@@ -221,10 +215,9 @@ static struct cns3xxx_pcie cns3xxx_pcie[] = {
                .irqs = { IRQ_CNS3XXX_PCIE0_RC, IRQ_CNS3XXX_PCIE0_DEVICE, },
                .hw_pci = {
                        .domain = 0,
-                        .swizzle = pci_std_swizzle,
                        .nr_controllers = 1,
+                        .ops = &cns3xxx_pcie_ops,
                        .setup = cns3xxx_pci_setup,
-                        .scan = cns3xxx_pci_scan_bus,
                        .map_irq = cns3xxx_pcie_map_irq,
                },
        },
@@ -264,10 +257,9 @@ static struct cns3xxx_pcie cns3xxx_pcie[] = {
                .irqs = { IRQ_CNS3XXX_PCIE1_RC, IRQ_CNS3XXX_PCIE1_DEVICE, },
                .hw_pci = {
                        .domain = 1,
-                        .swizzle = pci_std_swizzle,
                        .nr_controllers = 1,
+                        .ops = &cns3xxx_pcie_ops,
                        .setup = cns3xxx_pci_setup,
-                        .scan = cns3xxx_pci_scan_bus,
                        .map_irq = cns3xxx_pcie_map_irq,
                },
        },
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index a70de24d1cbc..09f61073c8d9 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -284,7 +284,7 @@ static struct platform_device da850_evm_nandflash_device = {
        .resource       = da850_evm_nandflash_resource,
 };
-static struct platform_device *da850_evm_devices[] __initdata = {
+static struct platform_device *da850_evm_devices[] = {
        &da850_evm_nandflash_device,
        &da850_evm_norflash_device,
 };
diff --git a/arch/arm/mach-davinci/davinci.h b/arch/arm/mach-davinci/davinci.h
index 3e519dad5bb9..8db0fc6809dd 100644
--- a/arch/arm/mach-davinci/davinci.h
+++ b/arch/arm/mach-davinci/davinci.h
@@ -72,7 +72,7 @@ void davinci_map_sysmod(void);
 /* DM355 function declarations */
 void __init dm355_init(void);
 void dm355_init_spi0(unsigned chipselect_mask,
-                struct spi_board_info *info, unsigned len);
+                const struct spi_board_info *info, unsigned len);
 void __init dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata);
 void dm355_set_vpfe_config(struct vpfe_config *cfg);
@@ -83,7 +83,7 @@ void __init dm365_init_vc(struct snd_platform_data *pdata);
 void __init dm365_init_ks(struct davinci_ks_platform_data *pdata);
 void __init dm365_init_rtc(void);
 void dm365_init_spi0(unsigned chipselect_mask,
-                        struct spi_board_info *info, unsigned len);
+                        const struct spi_board_info *info, unsigned len);
 void dm365_set_vpfe_config(struct vpfe_config *cfg);
 /* DM644x function declarations */
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index 42dbf3dc11ab..d1624a315c9a 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -831,7 +831,7 @@ static struct platform_device da8xx_spi_device[] = {
        },
 };
-int __init da8xx_register_spi(int instance, struct spi_board_info *info,
+int __init da8xx_register_spi(int instance, const struct spi_board_info *info,
                              unsigned len)
 {
        int ret;
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index fd3d09aa6cde..678cd99b7336 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -424,7 +424,7 @@ static struct platform_device dm355_spi0_device = {
 };
 void __init dm355_init_spi0(unsigned chipselect_mask,
-                struct spi_board_info *info, unsigned len)
+                const struct spi_board_info *info, unsigned len)
 {
        /* for now, assume we need MISO */
        davinci_cfg_reg(DM355_SPI0_SDI);
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 1a2e953082b3..a50d49de1883 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -676,7 +676,7 @@ static struct platform_device dm365_spi0_device = {
 };
 void __init dm365_init_spi0(unsigned chipselect_mask,
-                struct spi_board_info *info, unsigned len)
+                const struct spi_board_info *info, unsigned len)
 {
        davinci_cfg_reg(DM365_SPI0_SCLK);
        davinci_cfg_reg(DM365_SPI0_SDI);
diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c
index fd33919c95d4..95ce019c9b98 100644
--- a/arch/arm/mach-davinci/dma.c
+++ b/arch/arm/mach-davinci/dma.c
@@ -557,9 +557,9 @@ static int reserve_contiguous_slots(int ctlr, unsigned int id,
        if (i == edma_cc[ctlr]->num_slots)
                stop_slot = i;
-        for (j = start_slot; j < stop_slot; j++)
+        j = start_slot;
-                if (test_bit(j, tmp_inuse))
+        for_each_set_bit_from(j, tmp_inuse, stop_slot)
-                        clear_bit(j, edma_cc[ctlr]->edma_inuse);
+                clear_bit(j, edma_cc[ctlr]->edma_inuse);
        if (count)
                return -EBUSY;
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index ee3461d7ec1b..a2f1f274f189 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -76,7 +76,8 @@ void __init da850_init(void);
 int da830_register_edma(struct edma_rsv_info *rsv);
 int da850_register_edma(struct edma_rsv_info *rsv[2]);
 int da8xx_register_i2c(int instance, struct davinci_i2c_platform_data *pdata);
-int da8xx_register_spi(int instance, struct spi_board_info *info, unsigned len);
+int da8xx_register_spi(int instance,
+                const struct spi_board_info *info, unsigned len);
 int da8xx_register_watchdog(void);
 int da8xx_register_usb20(unsigned mA, unsigned potpgt);
 int da8xx_register_usb11(struct da8xx_ohci_root_hub *pdata);
diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h
index 8bc3fc256171..405318e35bf6 100644
--- a/arch/arm/mach-davinci/include/mach/psc.h
+++ b/arch/arm/mach-davinci/include/mach/psc.h
@@ -246,7 +246,7 @@
 #define MDSTAT_STATE_MASK       0x3f
 #define PDSTAT_STATE_MASK       0x1f
 #define MDCTL_FORCE             BIT(31)
-#define PDCTL_NEXT              BIT(1)
+#define PDCTL_NEXT              BIT(0)
 #define PDCTL_EPCGOOD           BIT(8)
 #ifndef __ASSEMBLER__
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index bda7aca04ca0..42ab1e7c4ecc 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -181,7 +181,7 @@ static int get_tclk(void)
        return 166666667;
 }
-static void dove_timer_init(void)
+static void __init dove_timer_init(void)
 {
        orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
                        IRQ_DOVE_BRIDGE, get_tclk());
diff --git a/arch/arm/mach-dove/mpp.c b/arch/arm/mach-dove/mpp.c
index 51e0e411c9cb..7f70afc26f91 100644
--- a/arch/arm/mach-dove/mpp.c
+++ b/arch/arm/mach-dove/mpp.c
@@ -56,7 +56,7 @@ static void dove_mpp_gpio_mode(int start, int end, int gpio_mode)
 /* Dump all the extra MPP registers. The platform code will dump the
   registers for pins 0-23. */
-static void dove_mpp_dump_regs(void)
+static void __init dove_mpp_dump_regs(void)
 {
        pr_debug("PMU_CTRL4_CTRL: %08x\n",
                 readl(DOVE_MPP_CTRL4_VIRT_BASE));
@@ -67,7 +67,7 @@ static void dove_mpp_dump_regs(void)
        pr_debug("MPP_GENERAL: %08x\n", readl(DOVE_MPP_GENERAL_VIRT_BASE));
 }
-static void dove_mpp_cfg_nfc(int sel)
+static void __init dove_mpp_cfg_nfc(int sel)
 {
        u32 mpp_gen_cfg = readl(DOVE_MPP_GENERAL_VIRT_BASE);
@@ -78,7 +78,7 @@ static void dove_mpp_cfg_nfc(int sel)
        dove_mpp_gpio_mode(64, 71, GPIO_OUTPUT_OK);
 }
-static void dove_mpp_cfg_au1(int sel)
+static void __init dove_mpp_cfg_au1(int sel)
 {
        u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
        u32 ssp_ctrl1 = readl(DOVE_SSP_CTRL_STATUS_1);
@@ -118,7 +118,7 @@ static void dove_mpp_cfg_au1(int sel)
 /* Configure the group registers, enabling GPIO if sel indicates the
   pin is to be used for GPIO */
-static void dove_mpp_conf_grp(unsigned int *mpp_grp_list)
+static void __init dove_mpp_conf_grp(unsigned int *mpp_grp_list)
 {
        u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
        int gpio_mode;
diff --git a/arch/arm/mach-dove/pcie.c b/arch/arm/mach-dove/pcie.c
index 48a032005ea3..47921b0cdc65 100644
--- a/arch/arm/mach-dove/pcie.c
+++ b/arch/arm/mach-dove/pcie.c
@@ -43,6 +43,7 @@ static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys)
                return 0;
        pp = &pcie_port[nr];
+        sys->private_data = pp;
        pp->root_bus_nr = sys->busnr;
        /*
@@ -93,19 +94,6 @@ static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys)
        return 1;
 }
-static struct pcie_port *bus_to_port(int bus)
-{
-        int i;
-        for (i = num_pcie_ports - 1; i >= 0; i--) {
-                int rbus = pcie_port[i].root_bus_nr;
-                if (rbus != -1 && rbus <= bus)
-                        break;
-        }
-        return i >= 0 ? pcie_port + i : NULL;
-}
 static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
 {
        /*
@@ -121,7 +109,8 @@ static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
 static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
                        int size, u32 *val)
 {
-        struct pcie_port *pp = bus_to_port(bus->number);
+        struct pci_sys_data *sys = bus->sysdata;
+        struct pcie_port *pp = sys->private_data;
        unsigned long flags;
        int ret;
@@ -140,7 +129,8 @@ static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
 static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
                        int where, int size, u32 val)
 {
-        struct pcie_port *pp = bus_to_port(bus->number);
+        struct pci_sys_data *sys = bus->sysdata;
+        struct pcie_port *pp = sys->private_data;
        unsigned long flags;
        int ret;
@@ -194,14 +184,14 @@ dove_pcie_scan_bus(int nr, struct pci_sys_data *sys)
 static int __init dove_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 {
-        struct pcie_port *pp = bus_to_port(dev->bus->number);
+        struct pci_sys_data *sys = dev->sysdata;
+        struct pcie_port *pp = sys->private_data;
        return pp->index ? IRQ_DOVE_PCIE1 : IRQ_DOVE_PCIE0;
 }
 static struct hw_pci dove_pci __initdata = {
        .nr_controllers = 2,
-        .swizzle        = pci_std_swizzle,
        .setup          = dove_pcie_setup,
        .scan           = dove_pcie_scan_bus,
        .map_irq        = dove_pcie_map_irq,
diff --git a/arch/arm/mach-ep93xx/Kconfig b/arch/arm/mach-ep93xx/Kconfig
index 97a249395b5a..fe3c1fa5462b 100644
--- a/arch/arm/mach-ep93xx/Kconfig
+++ b/arch/arm/mach-ep93xx/Kconfig
@@ -2,6 +2,11 @@ if ARCH_EP93XX
 menu "Cirrus EP93xx Implementation Options"
+config EP93XX_SOC_COMMON
+        bool
+        default y
+        select LEDS_GPIO_REGISTER
 config CRUNCH
        bool "Support for MaverickCrunch"
        help
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index 8d2589588713..66b1494f23a6 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -241,11 +241,7 @@ unsigned int ep93xx_chip_revision(void)
 * EP93xx GPIO
 *************************************************************************/
 static struct resource ep93xx_gpio_resource[] = {
-        {
+        DEFINE_RES_MEM(EP93XX_GPIO_PHYS_BASE, 0xcc),
-                .start          = EP93XX_GPIO_PHYS_BASE,
-                .end            = EP93XX_GPIO_PHYS_BASE + 0xcc - 1,
-                .flags          = IORESOURCE_MEM,
-        },
 };
 static struct platform_device ep93xx_gpio_device = {
@@ -288,11 +284,7 @@ static AMBA_APB_DEVICE(uart3, "apb:uart3", 0x00041010, EP93XX_UART3_PHYS_BASE,
        { IRQ_EP93XX_UART3 }, &ep93xx_uart_data);
 static struct resource ep93xx_rtc_resource[] = {
-        {
+        DEFINE_RES_MEM(EP93XX_RTC_PHYS_BASE, 0x10c),
-                .start          = EP93XX_RTC_PHYS_BASE,
-                .end            = EP93XX_RTC_PHYS_BASE + 0x10c - 1,
-                .flags          = IORESOURCE_MEM,
-        },
 };
 static struct platform_device ep93xx_rtc_device = {
@@ -304,16 +296,8 @@ static struct platform_device ep93xx_rtc_device = {
 static struct resource ep93xx_ohci_resources[] = {
-        [0] = {
+        DEFINE_RES_MEM(EP93XX_USB_PHYS_BASE, 0x1000),
-                .start  = EP93XX_USB_PHYS_BASE,
+        DEFINE_RES_IRQ(IRQ_EP93XX_USB),
-                .end    = EP93XX_USB_PHYS_BASE + 0x0fff,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = IRQ_EP93XX_USB,
-                .end    = IRQ_EP93XX_USB,
-                .flags  = IORESOURCE_IRQ,
-        },
 };
@@ -372,15 +356,8 @@ void __init ep93xx_register_flash(unsigned int width,
 static struct ep93xx_eth_data ep93xx_eth_data;
 static struct resource ep93xx_eth_resource[] = {
-        {
+        DEFINE_RES_MEM(EP93XX_ETHERNET_PHYS_BASE, 0x10000),
-                .start  = EP93XX_ETHERNET_PHYS_BASE,
+        DEFINE_RES_IRQ(IRQ_EP93XX_ETHERNET),
-                .end    = EP93XX_ETHERNET_PHYS_BASE + 0xffff,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = IRQ_EP93XX_ETHERNET,
-                .end    = IRQ_EP93XX_ETHERNET,
-                .flags  = IORESOURCE_IRQ,
-        }
 };
 static u64 ep93xx_eth_dma_mask = DMA_BIT_MASK(32);
@@ -461,16 +438,8 @@ void __init ep93xx_register_i2c(struct i2c_gpio_platform_data *data,
 static struct ep93xx_spi_info ep93xx_spi_master_data;
 static struct resource ep93xx_spi_resources[] = {
-        {
+        DEFINE_RES_MEM(EP93XX_SPI_PHYS_BASE, 0x18),
-                .start  = EP93XX_SPI_PHYS_BASE,
+        DEFINE_RES_IRQ(IRQ_EP93XX_SSP),
-                .end    = EP93XX_SPI_PHYS_BASE + 0x18 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = IRQ_EP93XX_SSP,
-                .end    = IRQ_EP93XX_SSP,
-                .flags  = IORESOURCE_IRQ,
-        },
 };
 static u64 ep93xx_spi_dma_mask = DMA_BIT_MASK(32);
@@ -513,7 +482,7 @@ void __init ep93xx_register_spi(struct ep93xx_spi_info *info,
 /*************************************************************************
 * EP93xx LEDs
 *************************************************************************/
-static struct gpio_led ep93xx_led_pins[] = {
+static const struct gpio_led ep93xx_led_pins[] __initconst = {
        {
                .name   = "platform:grled",
                .gpio   = EP93XX_GPIO_LINE_GRLED,
@@ -523,29 +492,16 @@ static struct gpio_led ep93xx_led_pins[] = {
        },
 };
-static struct gpio_led_platform_data ep93xx_led_data = {
+static const struct gpio_led_platform_data ep93xx_led_data __initconst = {
        .num_leds       = ARRAY_SIZE(ep93xx_led_pins),
        .leds           = ep93xx_led_pins,
 };
-static struct platform_device ep93xx_leds = {
-        .name           = "leds-gpio",
-        .id             = -1,
-        .dev            = {
-                .platform_data  = &ep93xx_led_data,
-        },
-};
 /*************************************************************************
 * EP93xx pwm peripheral handling
 *************************************************************************/
 static struct resource ep93xx_pwm0_resource[] = {
-        {
+        DEFINE_RES_MEM(EP93XX_PWM_PHYS_BASE, 0x10),
-                .start  = EP93XX_PWM_PHYS_BASE,
-                .end    = EP93XX_PWM_PHYS_BASE + 0x10 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
 };
 static struct platform_device ep93xx_pwm0_device = {
@@ -556,11 +512,7 @@ static struct platform_device ep93xx_pwm0_device = {
 };
 static struct resource ep93xx_pwm1_resource[] = {
-        {
+        DEFINE_RES_MEM(EP93XX_PWM_PHYS_BASE + 0x20, 0x10),
-                .start  = EP93XX_PWM_PHYS_BASE + 0x20,
-                .end    = EP93XX_PWM_PHYS_BASE + 0x30 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
 };
 static struct platform_device ep93xx_pwm1_device = {
@@ -628,11 +580,7 @@ EXPORT_SYMBOL(ep93xx_pwm_release_gpio);
 static struct ep93xxfb_mach_info ep93xxfb_data;
 static struct resource ep93xx_fb_resource[] = {
-        {
+        DEFINE_RES_MEM(EP93XX_RASTER_PHYS_BASE, 0x800),
-                .start          = EP93XX_RASTER_PHYS_BASE,
-                .end            = EP93XX_RASTER_PHYS_BASE + 0x800 - 1,
-                .flags          = IORESOURCE_MEM,
-        },
 };
 static struct platform_device ep93xx_fb_device = {
@@ -680,15 +628,8 @@ void __init ep93xx_register_fb(struct ep93xxfb_mach_info *data)
 static struct ep93xx_keypad_platform_data ep93xx_keypad_data;
 static struct resource ep93xx_keypad_resource[] = {
-        {
+        DEFINE_RES_MEM(EP93XX_KEY_MATRIX_PHYS_BASE, 0x0c),
-                .start  = EP93XX_KEY_MATRIX_PHYS_BASE,
+        DEFINE_RES_IRQ(IRQ_EP93XX_KEY),
-                .end    = EP93XX_KEY_MATRIX_PHYS_BASE + 0x0c - 1,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = IRQ_EP93XX_KEY,
-                .end    = IRQ_EP93XX_KEY,
-                .flags  = IORESOURCE_IRQ,
-        },
 };
 static struct platform_device ep93xx_keypad_device = {
@@ -761,11 +702,7 @@ EXPORT_SYMBOL(ep93xx_keypad_release_gpio);
 * EP93xx I2S audio peripheral handling
 *************************************************************************/
 static struct resource ep93xx_i2s_resource[] = {
-        {
+        DEFINE_RES_MEM(EP93XX_I2S_PHYS_BASE, 0x100),
-                .start  = EP93XX_I2S_PHYS_BASE,
-                .end    = EP93XX_I2S_PHYS_BASE + 0x100 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
 };
 static struct platform_device ep93xx_i2s_device = {
@@ -824,16 +761,8 @@ EXPORT_SYMBOL(ep93xx_i2s_release);
 * EP93xx AC97 audio peripheral handling
 *************************************************************************/
 static struct resource ep93xx_ac97_resources[] = {
-        {
+        DEFINE_RES_MEM(EP93XX_AAC_PHYS_BASE, 0xac),
-                .start  = EP93XX_AAC_PHYS_BASE,
+        DEFINE_RES_IRQ(IRQ_EP93XX_AACINTR),
-                .end    = EP93XX_AAC_PHYS_BASE + 0xac - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = IRQ_EP93XX_AACINTR,
-                .end    = IRQ_EP93XX_AACINTR,
-                .flags  = IORESOURCE_IRQ,
-        },
 };
 static struct platform_device ep93xx_ac97_device = {
@@ -889,8 +818,9 @@ void __init ep93xx_init_devices(void)
        platform_device_register(&ep93xx_rtc_device);
        platform_device_register(&ep93xx_ohci_device);
-        platform_device_register(&ep93xx_leds);
        platform_device_register(&ep93xx_wdt_device);
+        gpio_led_register_device(-1, &ep93xx_led_data);
 }
 void ep93xx_restart(char mode, const char *cmd)
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 0491ceef1cda..15b05b89cc39 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -200,6 +200,7 @@ config MACH_SMDKV310
        select S3C_DEV_HSMMC2
        select S3C_DEV_HSMMC3
        select SAMSUNG_DEV_BACKLIGHT
+        select EXYNOS_DEV_DRM
        select EXYNOS4_DEV_AHCI
        select SAMSUNG_DEV_KEYPAD
        select EXYNOS4_DEV_DMA
@@ -232,6 +233,9 @@ config MACH_ARMLEX4210
 config MACH_UNIVERSAL_C210
        bool "Mobile UNIVERSAL_C210 Board"
        select CPU_EXYNOS4210
+        select S5P_HRT
+        select CLKSRC_MMIO
+        select HAVE_SCHED_CLOCK
        select S5P_GPIO_INT
        select S5P_DEV_FIMC0
        select S5P_DEV_FIMC1
@@ -247,11 +251,13 @@ config MACH_UNIVERSAL_C210
        select S3C_DEV_I2C1
        select S3C_DEV_I2C3
        select S3C_DEV_I2C5
+        select S3C_DEV_USB_HSOTG
        select S5P_DEV_I2C_HDMIPHY
        select S5P_DEV_MFC
        select S5P_DEV_ONENAND
        select S5P_DEV_TV
        select EXYNOS4_DEV_DMA
+        select EXYNOS_DEV_DRM
        select EXYNOS4_SETUP_FIMD0
        select EXYNOS4_SETUP_I2C1
        select EXYNOS4_SETUP_I2C3
@@ -259,6 +265,7 @@ config MACH_UNIVERSAL_C210
        select EXYNOS4_SETUP_SDHCI
        select EXYNOS4_SETUP_FIMC
        select S5P_SETUP_MIPIPHY
+        select EXYNOS4_SETUP_USB_PHY
        help
          Machine support for Samsung Mobile Universal S5PC210 Reference
          Board.
@@ -277,6 +284,7 @@ config MACH_NURI
        select S3C_DEV_I2C3
        select S3C_DEV_I2C5
        select S3C_DEV_I2C6
+        select S3C_DEV_USB_HSOTG
        select S5P_DEV_CSIS0
        select S5P_DEV_JPEG
        select S5P_DEV_FIMC0
@@ -288,6 +296,7 @@ config MACH_NURI
        select S5P_DEV_USB_EHCI
        select S5P_SETUP_MIPIPHY
        select EXYNOS4_DEV_DMA
+        select EXYNOS_DEV_DRM
        select EXYNOS4_SETUP_FIMC
        select EXYNOS4_SETUP_FIMD0
        select EXYNOS4_SETUP_I2C1
@@ -322,6 +331,7 @@ config MACH_ORIGEN
        select S5P_DEV_USB_EHCI
        select SAMSUNG_DEV_BACKLIGHT
        select SAMSUNG_DEV_PWM
+        select EXYNOS_DEV_DRM
        select EXYNOS4_DEV_DMA
        select EXYNOS4_DEV_USB_OHCI
        select EXYNOS4_SETUP_FIMD0
@@ -342,6 +352,11 @@ config MACH_SMDK4212
        select S3C_DEV_I2C7
        select S3C_DEV_RTC
        select S3C_DEV_WDT
+        select S5P_DEV_FIMC0
+        select S5P_DEV_FIMC1
+        select S5P_DEV_FIMC2
+        select S5P_DEV_FIMC3
+        select S5P_DEV_MFC
        select SAMSUNG_DEV_BACKLIGHT
        select SAMSUNG_DEV_KEYPAD
        select SAMSUNG_DEV_PWM
@@ -368,6 +383,7 @@ comment "Flattened Device Tree based board for EXYNOS SoCs"
 config MACH_EXYNOS4_DT
        bool "Samsung Exynos4 Machine using device tree"
+        depends on ARCH_EXYNOS4
        select CPU_EXYNOS4210
        select USE_OF
        select ARM_AMBA
@@ -380,6 +396,7 @@ config MACH_EXYNOS4_DT
 config MACH_EXYNOS5_DT
        bool "SAMSUNG EXYNOS5 Machine using device tree"
+        depends on ARCH_EXYNOS5
        select SOC_EXYNOS5250
        select USE_OF
        select ARM_AMBA
diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c
index df54c2a92225..6efd1e5919fd 100644
--- a/arch/arm/mach-exynos/clock-exynos4.c
+++ b/arch/arm/mach-exynos/clock-exynos4.c
@@ -497,25 +497,25 @@ static struct clk exynos4_init_clocks_off[] = {
                .ctrlbit        = (1 << 3),
        }, {
                .name           = "hsmmc",
-                .devname        = "s3c-sdhci.0",
+                .devname        = "exynos4-sdhci.0",
                .parent         = &exynos4_clk_aclk_133.clk,
                .enable         = exynos4_clk_ip_fsys_ctrl,
                .ctrlbit        = (1 << 5),
        }, {
                .name           = "hsmmc",
-                .devname        = "s3c-sdhci.1",
+                .devname        = "exynos4-sdhci.1",
                .parent         = &exynos4_clk_aclk_133.clk,
                .enable         = exynos4_clk_ip_fsys_ctrl,
                .ctrlbit        = (1 << 6),
        }, {
                .name           = "hsmmc",
-                .devname        = "s3c-sdhci.2",
+                .devname        = "exynos4-sdhci.2",
                .parent         = &exynos4_clk_aclk_133.clk,
                .enable         = exynos4_clk_ip_fsys_ctrl,
                .ctrlbit        = (1 << 7),
        }, {
                .name           = "hsmmc",
-                .devname        = "s3c-sdhci.3",
+                .devname        = "exynos4-sdhci.3",
                .parent         = &exynos4_clk_aclk_133.clk,
                .enable         = exynos4_clk_ip_fsys_ctrl,
                .ctrlbit        = (1 << 8),
@@ -1202,7 +1202,7 @@ static struct clksrc_clk exynos4_clk_sclk_uart3 = {
 static struct clksrc_clk exynos4_clk_sclk_mmc0 = {
        .clk    = {
                .name           = "sclk_mmc",
-                .devname        = "s3c-sdhci.0",
+                .devname        = "exynos4-sdhci.0",
                .parent         = &exynos4_clk_dout_mmc0.clk,
                .enable         = exynos4_clksrc_mask_fsys_ctrl,
                .ctrlbit        = (1 << 0),
@@ -1213,7 +1213,7 @@ static struct clksrc_clk exynos4_clk_sclk_mmc0 = {
 static struct clksrc_clk exynos4_clk_sclk_mmc1 = {
        .clk    = {
                .name           = "sclk_mmc",
-                .devname        = "s3c-sdhci.1",
+                .devname        = "exynos4-sdhci.1",
                .parent         = &exynos4_clk_dout_mmc1.clk,
                .enable         = exynos4_clksrc_mask_fsys_ctrl,
                .ctrlbit        = (1 << 4),
@@ -1224,7 +1224,7 @@ static struct clksrc_clk exynos4_clk_sclk_mmc1 = {
 static struct clksrc_clk exynos4_clk_sclk_mmc2 = {
        .clk    = {
                .name           = "sclk_mmc",
-                .devname        = "s3c-sdhci.2",
+                .devname        = "exynos4-sdhci.2",
                .parent         = &exynos4_clk_dout_mmc2.clk,
                .enable         = exynos4_clksrc_mask_fsys_ctrl,
                .ctrlbit        = (1 << 8),
@@ -1235,7 +1235,7 @@ static struct clksrc_clk exynos4_clk_sclk_mmc2 = {
 static struct clksrc_clk exynos4_clk_sclk_mmc3 = {
        .clk    = {
                .name           = "sclk_mmc",
-                .devname        = "s3c-sdhci.3",
+                .devname        = "exynos4-sdhci.3",
                .parent         = &exynos4_clk_dout_mmc3.clk,
                .enable         = exynos4_clksrc_mask_fsys_ctrl,
                .ctrlbit        = (1 << 12),
@@ -1340,10 +1340,10 @@ static struct clk_lookup exynos4_clk_lookup[] = {
        CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos4_clk_sclk_uart1.clk),
        CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos4_clk_sclk_uart2.clk),
        CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos4_clk_sclk_uart3.clk),
-        CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk),
+        CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk),
-        CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk),
+        CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk),
-        CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk),
+        CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk),
-        CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk),
+        CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk),
        CLKDEV_INIT("exynos4-fb.0", "lcd", &exynos4_clk_fimd0),
        CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0),
        CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1),
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
index d013982d0f8e..7ac6ff4c46bd 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -455,25 +455,25 @@ static struct clk exynos5_init_clocks_off[] = {
                .ctrlbit        = (1 << 20),
        }, {
                .name           = "hsmmc",
-                .devname        = "s3c-sdhci.0",
+                .devname        = "exynos4-sdhci.0",
                .parent         = &exynos5_clk_aclk_200.clk,
                .enable         = exynos5_clk_ip_fsys_ctrl,
                .ctrlbit        = (1 << 12),
        }, {
                .name           = "hsmmc",
-                .devname        = "s3c-sdhci.1",
+                .devname        = "exynos4-sdhci.1",
                .parent         = &exynos5_clk_aclk_200.clk,
                .enable         = exynos5_clk_ip_fsys_ctrl,
                .ctrlbit        = (1 << 13),
        }, {
                .name           = "hsmmc",
-                .devname        = "s3c-sdhci.2",
+                .devname        = "exynos4-sdhci.2",
                .parent         = &exynos5_clk_aclk_200.clk,
                .enable         = exynos5_clk_ip_fsys_ctrl,
                .ctrlbit        = (1 << 14),
        }, {
                .name           = "hsmmc",
-                .devname        = "s3c-sdhci.3",
+                .devname        = "exynos4-sdhci.3",
                .parent         = &exynos5_clk_aclk_200.clk,
                .enable         = exynos5_clk_ip_fsys_ctrl,
                .ctrlbit        = (1 << 15),
@@ -678,7 +678,7 @@ static struct clk exynos5_clk_pdma1 = {
        .name           = "dma",
        .devname        = "dma-pl330.1",
        .enable         = exynos5_clk_ip_fsys_ctrl,
-        .ctrlbit        = (1 << 1),
+        .ctrlbit        = (1 << 2),
 };
 static struct clk exynos5_clk_mdma1 = {
@@ -813,7 +813,7 @@ static struct clksrc_clk exynos5_clk_sclk_uart3 = {
 static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
        .clk    = {
                .name           = "sclk_mmc",
-                .devname        = "s3c-sdhci.0",
+                .devname        = "exynos4-sdhci.0",
                .parent         = &exynos5_clk_dout_mmc0.clk,
                .enable         = exynos5_clksrc_mask_fsys_ctrl,
                .ctrlbit        = (1 << 0),
@@ -824,7 +824,7 @@ static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
 static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
        .clk    = {
                .name           = "sclk_mmc",
-                .devname        = "s3c-sdhci.1",
+                .devname        = "exynos4-sdhci.1",
                .parent         = &exynos5_clk_dout_mmc1.clk,
                .enable         = exynos5_clksrc_mask_fsys_ctrl,
                .ctrlbit        = (1 << 4),
@@ -835,7 +835,7 @@ static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
 static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
        .clk    = {
                .name           = "sclk_mmc",
-                .devname        = "s3c-sdhci.2",
+                .devname        = "exynos4-sdhci.2",
                .parent         = &exynos5_clk_dout_mmc2.clk,
                .enable         = exynos5_clksrc_mask_fsys_ctrl,
                .ctrlbit        = (1 << 8),
@@ -846,7 +846,7 @@ static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
 static struct clksrc_clk exynos5_clk_sclk_mmc3 = {
        .clk    = {
                .name           = "sclk_mmc",
-                .devname        = "s3c-sdhci.3",
+                .devname        = "exynos4-sdhci.3",
                .parent         = &exynos5_clk_dout_mmc3.clk,
                .enable         = exynos5_clksrc_mask_fsys_ctrl,
                .ctrlbit        = (1 << 12),
@@ -990,10 +990,10 @@ static struct clk_lookup exynos5_clk_lookup[] = {
        CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos5_clk_sclk_uart1.clk),
        CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos5_clk_sclk_uart2.clk),
        CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos5_clk_sclk_uart3.clk),
-        CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk),
+        CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk),
-        CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk),
+        CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk),
-        CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk),
+        CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk),
-        CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk),
+        CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk),
        CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0),
        CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1),
        CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1),
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 8614aab47cc0..5ccd6e80a607 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -326,6 +326,11 @@ static void __init exynos4_map_io(void)
        s3c_fimc_setname(2, "exynos4-fimc");
        s3c_fimc_setname(3, "exynos4-fimc");
+        s3c_sdhci_setname(0, "exynos4-sdhci");
+        s3c_sdhci_setname(1, "exynos4-sdhci");
+        s3c_sdhci_setname(2, "exynos4-sdhci");
+        s3c_sdhci_setname(3, "exynos4-sdhci");
        /* The I2C bus controllers are directly compatible with s3c2440 */
        s3c_i2c0_setname("s3c2440-i2c");
        s3c_i2c1_setname("s3c2440-i2c");
@@ -344,6 +349,11 @@ static void __init exynos5_map_io(void)
        s3c_device_i2c0.resource[1].start = EXYNOS5_IRQ_IIC;
        s3c_device_i2c0.resource[1].end   = EXYNOS5_IRQ_IIC;
+        s3c_sdhci_setname(0, "exynos4-sdhci");
+        s3c_sdhci_setname(1, "exynos4-sdhci");
+        s3c_sdhci_setname(2, "exynos4-sdhci");
+        s3c_sdhci_setname(3, "exynos4-sdhci");
        /* The I2C bus controllers are directly compatible with s3c2440 */
        s3c_i2c0_setname("s3c2440-i2c");
        s3c_i2c1_setname("s3c2440-i2c");
@@ -537,7 +547,9 @@ void __init exynos5_init_irq(void)
 {
        int irq;
-        gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
+#ifdef CONFIG_OF
+        of_irq_init(exynos4_dt_irq_match);
+#endif
        for (irq = 0; irq < EXYNOS5_MAX_COMBINER_NR; irq++) {
                combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index 33ab4e7558af..26dac2893b8e 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -20,6 +20,7 @@
 #include <asm/smp_scu.h>
 #include <asm/suspend.h>
 #include <asm/unified.h>
+#include <asm/cpuidle.h>
 #include <mach/regs-pmu.h>
 #include <mach/pmu.h>
@@ -34,22 +35,12 @@
 #define S5P_CHECK_AFTR          0xFCBA0D10
-static int exynos4_enter_idle(struct cpuidle_device *dev,
-                        struct cpuidle_driver *drv,
-                              int index);
 static int exynos4_enter_lowpower(struct cpuidle_device *dev,
                                struct cpuidle_driver *drv,
                                int index);
 static struct cpuidle_state exynos4_cpuidle_set[] __initdata = {
-        [0] = {
+        [0] = ARM_CPUIDLE_WFI_STATE,
-                .enter                  = exynos4_enter_idle,
-                .exit_latency           = 1,
-                .target_residency       = 100000,
-                .flags                  = CPUIDLE_FLAG_TIME_VALID,
-                .name                   = "C0",
-                .desc                   = "ARM clock gating(WFI)",
-        },
        [1] = {
                .enter                  = exynos4_enter_lowpower,
                .exit_latency           = 300,
@@ -63,8 +54,9 @@ static struct cpuidle_state exynos4_cpuidle_set[] __initdata = {
 static DEFINE_PER_CPU(struct cpuidle_device, exynos4_cpuidle_device);
 static struct cpuidle_driver exynos4_idle_driver = {
-        .name           = "exynos4_idle",
+        .name                   = "exynos4_idle",
-        .owner          = THIS_MODULE,
+        .owner                  = THIS_MODULE,
+        .en_core_tk_irqen       = 1,
 };
 /* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
@@ -103,13 +95,8 @@ static int exynos4_enter_core0_aftr(struct cpuidle_device *dev,
                                struct cpuidle_driver *drv,
                                int index)
 {
-        struct timeval before, after;
-        int idle_time;
        unsigned long tmp;
-        local_irq_disable();
-        do_gettimeofday(&before);
        exynos4_set_wakeupmask();
        /* Set value of power down register for aftr mode */
@@ -150,34 +137,6 @@ static int exynos4_enter_core0_aftr(struct cpuidle_device *dev,
        /* Clear wakeup state register */
        __raw_writel(0x0, S5P_WAKEUP_STAT);
-        do_gettimeofday(&after);
-        local_irq_enable();
-        idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC +
-                    (after.tv_usec - before.tv_usec);
-        dev->last_residency = idle_time;
-        return index;
-}
-static int exynos4_enter_idle(struct cpuidle_device *dev,
-                                struct cpuidle_driver *drv,
-                                int index)
-{
-        struct timeval before, after;
-        int idle_time;
-        local_irq_disable();
-        do_gettimeofday(&before);
-        cpu_do_idle();
-        do_gettimeofday(&after);
-        local_irq_enable();
-        idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC +
-                    (after.tv_usec - before.tv_usec);
-        dev->last_residency = idle_time;
        return index;
 }
@@ -192,7 +151,7 @@ static int exynos4_enter_lowpower(struct cpuidle_device *dev,
                new_index = drv->safe_state_index;
        if (new_index == 0)
-                return exynos4_enter_idle(dev, drv, new_index);
+                return arm_cpuidle_simple_enter(dev, drv, new_index);
        else
                return exynos4_enter_core0_aftr(dev, drv, new_index);
 }
diff --git a/arch/arm/mach-exynos/dev-ahci.c b/arch/arm/mach-exynos/dev-ahci.c
index 50ce5b0adcf1..ce1aad3eeeb9 100644
--- a/arch/arm/mach-exynos/dev-ahci.c
+++ b/arch/arm/mach-exynos/dev-ahci.c
@@ -236,16 +236,8 @@ static struct ahci_platform_data exynos4_ahci_pdata = {
 };
 static struct resource exynos4_ahci_resource[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM(EXYNOS4_PA_SATA, SZ_64K),
-                .start  = EXYNOS4_PA_SATA,
+        [1] = DEFINE_RES_IRQ(EXYNOS4_IRQ_SATA),
-                .end    = EXYNOS4_PA_SATA + SZ_64K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = EXYNOS4_IRQ_SATA,
-                .end    = EXYNOS4_IRQ_SATA,
-                .flags  = IORESOURCE_IRQ,
-        },
 };
 static u64 exynos4_ahci_dmamask = DMA_BIT_MASK(32);
diff --git a/arch/arm/mach-exynos/dev-audio.c b/arch/arm/mach-exynos/dev-audio.c
index 7199e1ae79b4..b33a5b67b547 100644
--- a/arch/arm/mach-exynos/dev-audio.c
+++ b/arch/arm/mach-exynos/dev-audio.c
@@ -62,26 +62,10 @@ static struct s3c_audio_pdata i2sv5_pdata = {
 };
 static struct resource exynos4_i2s0_resource[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM(EXYNOS4_PA_I2S0, SZ_256),
-                .start  = EXYNOS4_PA_I2S0,
+        [1] = DEFINE_RES_DMA(DMACH_I2S0_TX),
-                .end    = EXYNOS4_PA_I2S0 + 0x100 - 1,
+        [2] = DEFINE_RES_DMA(DMACH_I2S0_RX),
-                .flags  = IORESOURCE_MEM,
+        [3] = DEFINE_RES_DMA(DMACH_I2S0S_TX),
-        },
-        [1] = {
-                .start  = DMACH_I2S0_TX,
-                .end    = DMACH_I2S0_TX,
-                .flags  = IORESOURCE_DMA,
-        },
-        [2] = {
-                .start  = DMACH_I2S0_RX,
-                .end    = DMACH_I2S0_RX,
-                .flags  = IORESOURCE_DMA,
-        },
-        [3] = {
-                .start  = DMACH_I2S0S_TX,
-                .end    = DMACH_I2S0S_TX,
-                .flags  = IORESOURCE_DMA,
-        },
 };
 struct platform_device exynos4_device_i2s0 = {
@@ -110,21 +94,9 @@ static struct s3c_audio_pdata i2sv3_pdata = {
 };
 static struct resource exynos4_i2s1_resource[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM(EXYNOS4_PA_I2S1, SZ_256),
-                .start  = EXYNOS4_PA_I2S1,
+        [1] = DEFINE_RES_DMA(DMACH_I2S1_TX),
-                .end    = EXYNOS4_PA_I2S1 + 0x100 - 1,
+        [2] = DEFINE_RES_DMA(DMACH_I2S1_RX),
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = DMACH_I2S1_TX,
-                .end    = DMACH_I2S1_TX,
-                .flags  = IORESOURCE_DMA,
-        },
-        [2] = {
-                .start  = DMACH_I2S1_RX,
-                .end    = DMACH_I2S1_RX,
-                .flags  = IORESOURCE_DMA,
-        },
 };
 struct platform_device exynos4_device_i2s1 = {
@@ -138,21 +110,9 @@ struct platform_device exynos4_device_i2s1 = {
 };
 static struct resource exynos4_i2s2_resource[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM(EXYNOS4_PA_I2S2, SZ_256),
-                .start  = EXYNOS4_PA_I2S2,
+        [1] = DEFINE_RES_DMA(DMACH_I2S2_TX),
-                .end    = EXYNOS4_PA_I2S2 + 0x100 - 1,
+        [2] = DEFINE_RES_DMA(DMACH_I2S2_RX),
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = DMACH_I2S2_TX,
-                .end    = DMACH_I2S2_TX,
-                .flags  = IORESOURCE_DMA,
-        },
-        [2] = {
-                .start  = DMACH_I2S2_RX,
-                .end    = DMACH_I2S2_RX,
-                .flags  = IORESOURCE_DMA,
-        },
 };
 struct platform_device exynos4_device_i2s2 = {
@@ -192,21 +152,9 @@ static struct s3c_audio_pdata s3c_pcm_pdata = {
 };
 static struct resource exynos4_pcm0_resource[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM(EXYNOS4_PA_PCM0, SZ_256),
-                .start  = EXYNOS4_PA_PCM0,
+        [1] = DEFINE_RES_DMA(DMACH_PCM0_TX),
-                .end    = EXYNOS4_PA_PCM0 + 0x100 - 1,
+        [2] = DEFINE_RES_DMA(DMACH_PCM0_RX),
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = DMACH_PCM0_TX,
-                .end    = DMACH_PCM0_TX,
-                .flags  = IORESOURCE_DMA,
-        },
-        [2] = {
-                .start  = DMACH_PCM0_RX,
-                .end    = DMACH_PCM0_RX,
-                .flags  = IORESOURCE_DMA,
-        },
 };
 struct platform_device exynos4_device_pcm0 = {
@@ -220,21 +168,9 @@ struct platform_device exynos4_device_pcm0 = {
 };
 static struct resource exynos4_pcm1_resource[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM(EXYNOS4_PA_PCM1, SZ_256),
-                .start  = EXYNOS4_PA_PCM1,
+        [1] = DEFINE_RES_DMA(DMACH_PCM1_TX),
-                .end    = EXYNOS4_PA_PCM1 + 0x100 - 1,
+        [2] = DEFINE_RES_DMA(DMACH_PCM1_RX),
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = DMACH_PCM1_TX,
-                .end    = DMACH_PCM1_TX,
-                .flags  = IORESOURCE_DMA,
-        },
-        [2] = {
-                .start  = DMACH_PCM1_RX,
-                .end    = DMACH_PCM1_RX,
-                .flags  = IORESOURCE_DMA,
-        },
 };
 struct platform_device exynos4_device_pcm1 = {
@@ -248,21 +184,9 @@ struct platform_device exynos4_device_pcm1 = {
 };
 static struct resource exynos4_pcm2_resource[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM(EXYNOS4_PA_PCM2, SZ_256),
-                .start  = EXYNOS4_PA_PCM2,
+        [1] = DEFINE_RES_DMA(DMACH_PCM2_TX),
-                .end    = EXYNOS4_PA_PCM2 + 0x100 - 1,
+        [2] = DEFINE_RES_DMA(DMACH_PCM2_RX),
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = DMACH_PCM2_TX,
-                .end    = DMACH_PCM2_TX,
-                .flags  = IORESOURCE_DMA,
-        },
-        [2] = {
-                .start  = DMACH_PCM2_RX,
-                .end    = DMACH_PCM2_RX,
-                .flags  = IORESOURCE_DMA,
-        },
 };
 struct platform_device exynos4_device_pcm2 = {
@@ -283,31 +207,11 @@ static int exynos4_ac97_cfg_gpio(struct platform_device *pdev)
 }
 static struct resource exynos4_ac97_resource[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM(EXYNOS4_PA_AC97, SZ_256),
-                .start  = EXYNOS4_PA_AC97,
+        [1] = DEFINE_RES_DMA(DMACH_AC97_PCMOUT),
-                .end    = EXYNOS4_PA_AC97 + 0x100 - 1,
+        [2] = DEFINE_RES_DMA(DMACH_AC97_PCMIN),
-                .flags  = IORESOURCE_MEM,
+        [3] = DEFINE_RES_DMA(DMACH_AC97_MICIN),
-        },
+        [4] = DEFINE_RES_IRQ(EXYNOS4_IRQ_AC97),
-        [1] = {
-                .start  = DMACH_AC97_PCMOUT,
-                .end    = DMACH_AC97_PCMOUT,
-                .flags  = IORESOURCE_DMA,
-        },
-        [2] = {
-                .start  = DMACH_AC97_PCMIN,
-                .end    = DMACH_AC97_PCMIN,
-                .flags  = IORESOURCE_DMA,
-        },
-        [3] = {
-                .start  = DMACH_AC97_MICIN,
-                .end    = DMACH_AC97_MICIN,
-                .flags  = IORESOURCE_DMA,
-        },
-        [4] = {
-                .start  = EXYNOS4_IRQ_AC97,
-                .end    = EXYNOS4_IRQ_AC97,
-                .flags  = IORESOURCE_IRQ,
-        },
 };
 static struct s3c_audio_pdata s3c_ac97_pdata = {
@@ -338,16 +242,8 @@ static int exynos4_spdif_cfg_gpio(struct platform_device *pdev)
 }
 static struct resource exynos4_spdif_resource[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM(EXYNOS4_PA_SPDIF, SZ_256),
-                .start  = EXYNOS4_PA_SPDIF,
+        [1] = DEFINE_RES_DMA(DMACH_SPDIF),
-                .end    = EXYNOS4_PA_SPDIF + 0x100 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = DMACH_SPDIF,
-                .end    = DMACH_SPDIF,
-                .flags  = IORESOURCE_DMA,
-        },
 };
 static struct s3c_audio_pdata samsung_spdif_pdata = {
diff --git a/arch/arm/mach-exynos/dev-dwmci.c b/arch/arm/mach-exynos/dev-dwmci.c
index b025db4bf602..79035018fb74 100644
--- a/arch/arm/mach-exynos/dev-dwmci.c
+++ b/arch/arm/mach-exynos/dev-dwmci.c
@@ -16,6 +16,7 @@
 #include <linux/dma-mapping.h>
 #include <linux/platform_device.h>
 #include <linux/interrupt.h>
+#include <linux/ioport.h>
 #include <linux/mmc/dw_mmc.h>
 #include <plat/devs.h>
@@ -33,16 +34,8 @@ static int exynos4_dwmci_init(u32 slot_id, irq_handler_t handler, void *data)
 }
 static struct resource exynos4_dwmci_resource[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM(EXYNOS4_PA_DWMCI, SZ_4K),
-                .start  = EXYNOS4_PA_DWMCI,
+        [1] = DEFINE_RES_IRQ(EXYNOS4_IRQ_DWMCI),
-                .end    = EXYNOS4_PA_DWMCI + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = IRQ_DWMCI,
-                .end    = IRQ_DWMCI,
-                .flags  = IORESOURCE_IRQ,
-        }
 };
 static struct dw_mci_board exynos4_dwci_pdata = {
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
index 9bee8535d9e0..c02dae7bf4a3 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -189,6 +189,7 @@
 #define IRQ_IIC7                        EXYNOS4_IRQ_IIC7
 #define IRQ_USB_HOST                    EXYNOS4_IRQ_USB_HOST
+#define IRQ_OTG                         EXYNOS4_IRQ_USB_HSOTG
 #define IRQ_HSMMC0                      EXYNOS4_IRQ_HSMMC0
 #define IRQ_HSMMC1                      EXYNOS4_IRQ_HSMMC1
@@ -212,6 +213,8 @@
 #define IRQ_MFC                         EXYNOS4_IRQ_MFC
 #define IRQ_SDO                         EXYNOS4_IRQ_SDO
+#define IRQ_I2S0                        EXYNOS4_IRQ_I2S0
 #define IRQ_ADC                         EXYNOS4_IRQ_ADC0
 #define IRQ_TC                          EXYNOS4_IRQ_PEN0
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 024d38ff1718..e009a66477f4 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -89,6 +89,10 @@
 #define EXYNOS4_PA_MDMA1                0x12840000
 #define EXYNOS4_PA_PDMA0                0x12680000
 #define EXYNOS4_PA_PDMA1                0x12690000
+#define EXYNOS5_PA_MDMA0                0x10800000
+#define EXYNOS5_PA_MDMA1                0x11C10000
+#define EXYNOS5_PA_PDMA0                0x121A0000
+#define EXYNOS5_PA_PDMA1                0x121B0000
 #define EXYNOS4_PA_SYSMMU_MDMA          0x10A40000
 #define EXYNOS4_PA_SYSMMU_SSS           0x10A50000
@@ -126,6 +130,9 @@
 #define EXYNOS4_PA_HSMMC(x)             (0x12510000 + ((x) * 0x10000))
 #define EXYNOS4_PA_DWMCI                0x12550000
+#define EXYNOS4_PA_HSOTG                0x12480000
+#define EXYNOS4_PA_USB_HSPHY            0x125B0000
 #define EXYNOS4_PA_SATA                 0x12560000
 #define EXYNOS4_PA_SATAPHY              0x125D0000
 #define EXYNOS4_PA_SATAPHY_CTRL         0x126B0000
@@ -182,6 +189,7 @@
 #define S3C_PA_SPI0                     EXYNOS4_PA_SPI0
 #define S3C_PA_SPI1                     EXYNOS4_PA_SPI1
 #define S3C_PA_SPI2                     EXYNOS4_PA_SPI2
+#define S3C_PA_USB_HSOTG                EXYNOS4_PA_HSOTG
 #define S5P_PA_EHCI                     EXYNOS4_PA_EHCI
 #define S5P_PA_FIMC0                    EXYNOS4_PA_FIMC0
diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h
index e141c1fd68d8..d9578a58ae7f 100644
--- a/arch/arm/mach-exynos/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos/include/mach/regs-clock.h
@@ -255,9 +255,15 @@
 /* For EXYNOS5250 */
+#define EXYNOS5_APLL_LOCK                       EXYNOS_CLKREG(0x00000)
 #define EXYNOS5_APLL_CON0                       EXYNOS_CLKREG(0x00100)
 #define EXYNOS5_CLKSRC_CPU                      EXYNOS_CLKREG(0x00200)
+#define EXYNOS5_CLKMUX_STATCPU                  EXYNOS_CLKREG(0x00400)
 #define EXYNOS5_CLKDIV_CPU0                     EXYNOS_CLKREG(0x00500)
+#define EXYNOS5_CLKDIV_CPU1                     EXYNOS_CLKREG(0x00504)
+#define EXYNOS5_CLKDIV_STATCPU0                 EXYNOS_CLKREG(0x00600)
+#define EXYNOS5_CLKDIV_STATCPU1                 EXYNOS_CLKREG(0x00604)
 #define EXYNOS5_MPLL_CON0                       EXYNOS_CLKREG(0x04100)
 #define EXYNOS5_CLKSRC_CORE1                    EXYNOS_CLKREG(0x04204)
diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h
index 4c53f38b5a9e..d457d052a420 100644
--- a/arch/arm/mach-exynos/include/mach/regs-pmu.h
+++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h
@@ -163,6 +163,9 @@
 #define S5P_CHECK_SLEEP                         0x00000BAD
 /* Only for EXYNOS4210 */
+#define S5P_USBDEVICE_PHY_CONTROL       S5P_PMUREG(0x0704)
+#define S5P_USBDEVICE_PHY_ENABLE        (1 << 0)
 #define S5P_USBHOST_PHY_CONTROL         S5P_PMUREG(0x0708)
 #define S5P_USBHOST_PHY_ENABLE          (1 << 0)
diff --git a/arch/arm/mach-exynos/mach-armlex4210.c b/arch/arm/mach-exynos/mach-armlex4210.c
index d726fcd3acf9..fed7116418eb 100644
--- a/arch/arm/mach-exynos/mach-armlex4210.c
+++ b/arch/arm/mach-exynos/mach-armlex4210.c
@@ -77,7 +77,6 @@ static struct s3c2410_uartcfg armlex4210_uartcfgs[] __initdata = {
 static struct s3c_sdhci_platdata armlex4210_hsmmc0_pdata __initdata = {
        .cd_type                = S3C_SDHCI_CD_PERMANENT,
-        .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
 #ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
        .max_width              = 8,
        .host_caps              = MMC_CAP_8_BIT_DATA,
@@ -88,13 +87,11 @@ static struct s3c_sdhci_platdata armlex4210_hsmmc2_pdata __initdata = {
        .cd_type                = S3C_SDHCI_CD_GPIO,
        .ext_cd_gpio            = EXYNOS4_GPX2(5),
        .ext_cd_gpio_invert     = 1,
-        .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
        .max_width              = 4,
 };
 static struct s3c_sdhci_platdata armlex4210_hsmmc3_pdata __initdata = {
        .cd_type                = S3C_SDHCI_CD_PERMANENT,
-        .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
        .max_width              = 4,
 };
@@ -121,16 +118,9 @@ static void __init armlex4210_wlan_init(void)
 }
 static struct resource armlex4210_smsc911x_resources[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM(EXYNOS4_PA_SROM_BANK(3), SZ_64K),
-                .start  = EXYNOS4_PA_SROM_BANK(3),
+        [1] = DEFINE_RES_NAMED(IRQ_EINT(27), 1, NULL, IORESOURCE_IRQ \
-                .end    = EXYNOS4_PA_SROM_BANK(3) + SZ_64K - 1,
+                                        | IRQF_TRIGGER_HIGH),
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = IRQ_EINT(27),
-                .end    = IRQ_EINT(27),
-                .flags  = IORESOURCE_IRQ | IRQF_TRIGGER_HIGH,
-        },
 };
 static struct smsc911x_platform_config smsc9215_config = {
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index 0d26f50081ad..4711c8920e37 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -45,7 +45,7 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
                                "exynos4210-uart.3", NULL),
        OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
        OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
-        OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.2", NULL),
+        OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
        {},
 };
diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
index b3982c867c9c..6c31f2ad765d 100644
--- a/arch/arm/mach-exynos/mach-nuri.c
+++ b/arch/arm/mach-exynos/mach-nuri.c
@@ -25,6 +25,8 @@
 #include <linux/mmc/host.h>
 #include <linux/fb.h>
 #include <linux/pwm_backlight.h>
+#include <linux/platform_data/s3c-hsotg.h>
+#include <drm/exynos_drm.h>
 #include <video/platform_lcd.h>
 #include <media/m5mols.h>
@@ -112,8 +114,8 @@ static struct s3c_sdhci_platdata nuri_hsmmc0_data __initdata = {
        .host_caps              = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
                                MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
                                MMC_CAP_ERASE),
+        .host_caps2             = MMC_CAP2_BROKEN_VOLTAGE,
        .cd_type                = S3C_SDHCI_CD_PERMANENT,
-        .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
 };
 static struct regulator_consumer_supply emmc_supplies[] = {
@@ -154,7 +156,6 @@ static struct s3c_sdhci_platdata nuri_hsmmc2_data __initdata = {
        .ext_cd_gpio            = EXYNOS4_GPX3(3),      /* XEINT_27 */
        .ext_cd_gpio_invert     = 1,
        .cd_type                = S3C_SDHCI_CD_GPIO,
-        .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
 };
 /* WLAN */
@@ -163,7 +164,6 @@ static struct s3c_sdhci_platdata nuri_hsmmc3_data __initdata = {
        .host_caps              = MMC_CAP_4_BIT_DATA |
                                MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
        .cd_type                = S3C_SDHCI_CD_EXTERNAL,
-        .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
 };
 static void __init nuri_sdhci_init(void)
@@ -212,6 +212,29 @@ static struct platform_device nuri_gpio_keys = {
        },
 };
+#ifdef CONFIG_DRM_EXYNOS
+static struct exynos_drm_fimd_pdata drm_fimd_pdata = {
+        .panel = {
+                .timing = {
+                        .xres           = 1024,
+                        .yres           = 600,
+                        .hsync_len      = 40,
+                        .left_margin    = 79,
+                        .right_margin   = 200,
+                        .vsync_len      = 10,
+                        .upper_margin   = 10,
+                        .lower_margin   = 11,
+                        .refresh        = 60,
+                },
+        },
+        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB |
+                          VIDCON0_CLKSEL_LCD,
+        .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+        .default_win    = 3,
+        .bpp            = 32,
+};
+#else
 /* Frame Buffer */
 static struct s3c_fb_pd_win nuri_fb_win0 = {
        .win_mode = {
@@ -238,6 +261,7 @@ static struct s3c_fb_platdata nuri_fb_pdata __initdata = {
        .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
        .setup_gpio     = exynos4_fimd0_gpio_setup_24bpp,
 };
+#endif
 static void nuri_lcd_power_on(struct plat_lcd_data *pd, unsigned int power)
 {
@@ -307,49 +331,7 @@ static struct i2c_board_info i2c1_devs[] __initdata = {
 };
 /* TSP */
-static u8 mxt_init_vals[] = {
-        /* MXT_GEN_COMMAND(6) */
-        0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-        /* MXT_GEN_POWER(7) */
-        0x20, 0xff, 0x32,
-        /* MXT_GEN_ACQUIRE(8) */
-        0x0a, 0x00, 0x05, 0x00, 0x00, 0x00, 0x09, 0x23,
-        /* MXT_TOUCH_MULTI(9) */
-        0x00, 0x00, 0x00, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x02, 0x00,
-        0x00, 0x01, 0x01, 0x0e, 0x0a, 0x0a, 0x0a, 0x0a, 0x00, 0x00,
-        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-        0x00,
-        /* MXT_TOUCH_KEYARRAY(15) */
-        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
-        0x00,
-        /* MXT_SPT_GPIOPWM(19) */
-        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-        0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-        /* MXT_PROCI_GRIPFACE(20) */
-        0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x28, 0x04,
-        0x0f, 0x0a,
-        /* MXT_PROCG_NOISE(22) */
-        0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x23, 0x00,
-        0x00, 0x05, 0x0f, 0x19, 0x23, 0x2d, 0x03,
-        /* MXT_TOUCH_PROXIMITY(23) */
-        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-        0x00, 0x00, 0x00, 0x00, 0x00,
-        /* MXT_PROCI_ONETOUCH(24) */
-        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-        /* MXT_SPT_SELFTEST(25) */
-        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-        0x00, 0x00, 0x00, 0x00,
-        /* MXT_PROCI_TWOTOUCH(27) */
-        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-        /* MXT_SPT_CTECONFIG(28) */
-        0x00, 0x00, 0x02, 0x08, 0x10, 0x00,
-};
 static struct mxt_platform_data mxt_platform_data = {
-        .config                 = mxt_init_vals,
-        .config_length          = ARRAY_SIZE(mxt_init_vals),
        .x_line                 = 18,
        .y_line                 = 11,
        .x_size                 = 1024,
@@ -392,6 +374,7 @@ static struct regulator_consumer_supply __initdata max8997_ldo1_[] = {
        REGULATOR_SUPPLY("vdd", "s5p-adc"), /* Used by CPU's ADC drv */
 };
 static struct regulator_consumer_supply __initdata max8997_ldo3_[] = {
+        REGULATOR_SUPPLY("vusb_d", "s3c-hsotg"), /* USB */
        REGULATOR_SUPPLY("vdd11", "s5p-mipi-csis.0"), /* MIPI */
 };
 static struct regulator_consumer_supply __initdata max8997_ldo4_[] = {
@@ -407,7 +390,7 @@ static struct regulator_consumer_supply __initdata max8997_ldo7_[] = {
        REGULATOR_SUPPLY("dig_18", "0-001f"), /* HCD803 */
 };
 static struct regulator_consumer_supply __initdata max8997_ldo8_[] = {
-        REGULATOR_SUPPLY("vusb_d", NULL), /* Used by CPU */
+        REGULATOR_SUPPLY("vusb_a", "s3c-hsotg"), /* USB */
        REGULATOR_SUPPLY("vdac", NULL), /* Used by CPU */
 };
 static struct regulator_consumer_supply __initdata max8997_ldo11_[] = {
@@ -571,7 +554,7 @@ static struct regulator_init_data __initdata max8997_ldo7_data = {
 static struct regulator_init_data __initdata max8997_ldo8_data = {
        .constraints    = {
-                .name           = "VUSB/VDAC_3.3V_C210",
+                .name           = "VUSB+VDAC_3.3V_C210",
                .min_uV         = 3300000,
                .max_uV         = 3300000,
                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
@@ -863,6 +846,7 @@ static struct regulator_init_data __initdata max8997_esafeout1_data = {
        .constraints    = {
                .name           = "SAFEOUT1",
                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+                .always_on      = 1,
                .state_mem      = {
                        .disabled       = 1,
                },
@@ -1120,6 +1104,9 @@ static void __init nuri_ehci_init(void)
        s5p_ehci_set_platdata(pdata);
 }
+/* USB OTG */
+static struct s3c_hsotg_plat nuri_hsotg_pdata;
 /* CAMERA */
 static struct regulator_consumer_supply cam_vt_cam15_supply =
        REGULATOR_SUPPLY("vdd_core", "6-003c");
@@ -1332,6 +1319,7 @@ static struct platform_device *nuri_devices[] __initdata = {
        &s5p_device_mfc_l,
        &s5p_device_mfc_r,
        &s5p_device_fimc_md,
+        &s3c_device_usb_hsotg,
        /* NURI Devices */
        &nuri_gpio_keys,
@@ -1343,10 +1331,14 @@ static struct platform_device *nuri_devices[] __initdata = {
        &cam_vdda_fixed_rdev,
        &cam_8m_12v_fixed_rdev,
        &exynos4_bus_devfreq,
+#ifdef CONFIG_DRM_EXYNOS
+        &exynos_device_drm,
+#endif
 };
 static void __init nuri_map_io(void)
 {
+        clk_xusbxti.rate = 24000000;
        exynos_init_io(NULL, 0);
        s3c24xx_init_clocks(24000000);
        s3c24xx_init_uarts(nuri_uartcfgs, ARRAY_SIZE(nuri_uartcfgs));
@@ -1374,12 +1366,17 @@ static void __init nuri_machine_init(void)
        i2c_register_board_info(9, i2c9_devs, ARRAY_SIZE(i2c9_devs));
        s3c_i2c6_set_platdata(&nuri_i2c6_platdata);
+#ifdef CONFIG_DRM_EXYNOS
+        s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata;
+        exynos4_fimd0_gpio_setup_24bpp();
+#else
        s5p_fimd0_set_platdata(&nuri_fb_pdata);
+#endif
        nuri_camera_init();
        nuri_ehci_init();
-        clk_xusbxti.rate = 24000000;
+        s3c_hsotg_set_platdata(&nuri_hsotg_pdata);
        /* Last */
        platform_add_devices(nuri_devices, ARRAY_SIZE(nuri_devices));
diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c
index 878d4c99142d..26124a38bcbd 100644
--- a/arch/arm/mach-exynos/mach-origen.c
+++ b/arch/arm/mach-exynos/mach-origen.c
@@ -45,6 +45,7 @@
 #include <mach/ohci.h>
 #include <mach/map.h>
+#include <drm/exynos_drm.h>
 #include "common.h"
 /* Following are default values for UCON, ULCON and UFCON UART registers */
@@ -472,12 +473,10 @@ static struct i2c_board_info i2c0_devs[] __initdata = {
 static struct s3c_sdhci_platdata origen_hsmmc0_pdata __initdata = {
        .cd_type                = S3C_SDHCI_CD_INTERNAL,
-        .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
 };
 static struct s3c_sdhci_platdata origen_hsmmc2_pdata __initdata = {
        .cd_type                = S3C_SDHCI_CD_INTERNAL,
-        .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
 };
 /* USB EHCI */
@@ -583,6 +582,27 @@ static struct platform_device origen_lcd_hv070wsa = {
        .dev.platform_data      = &origen_lcd_hv070wsa_data,
 };
+#ifdef CONFIG_DRM_EXYNOS
+static struct exynos_drm_fimd_pdata drm_fimd_pdata = {
+        .panel  = {
+                .timing = {
+                        .left_margin    = 64,
+                        .right_margin   = 16,
+                        .upper_margin   = 64,
+                        .lower_margin   = 16,
+                        .hsync_len      = 48,
+                        .vsync_len      = 3,
+                        .xres           = 1024,
+                        .yres           = 600,
+                },
+        },
+        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
+        .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC |
+                                VIDCON1_INV_VCLK,
+        .default_win    = 0,
+        .bpp            = 32,
+};
+#else
 static struct s3c_fb_pd_win origen_fb_win0 = {
        .win_mode = {
                .left_margin    = 64,
@@ -596,6 +616,8 @@ static struct s3c_fb_pd_win origen_fb_win0 = {
        },
        .max_bpp                = 32,
        .default_bpp            = 24,
+        .virtual_x              = 1024,
+        .virtual_y              = 2 * 600,
 };
 static struct s3c_fb_platdata origen_lcd_pdata __initdata = {
@@ -605,9 +627,10 @@ static struct s3c_fb_platdata origen_lcd_pdata __initdata = {
                                VIDCON1_INV_VCLK,
        .setup_gpio     = exynos4_fimd0_gpio_setup_24bpp,
 };
+#endif
 /* Bluetooth rfkill gpio platform data */
-struct rfkill_gpio_platform_data origen_bt_pdata = {
+static struct rfkill_gpio_platform_data origen_bt_pdata = {
        .reset_gpio     = EXYNOS4_GPX2(2),
        .shutdown_gpio  = -1,
        .type           = RFKILL_TYPE_BLUETOOTH,
@@ -644,6 +667,9 @@ static struct platform_device *origen_devices[] __initdata = {
        &s5p_device_mfc_l,
        &s5p_device_mfc_r,
        &s5p_device_mixer,
+#ifdef CONFIG_DRM_EXYNOS
+        &exynos_device_drm,
+#endif
        &exynos4_device_ohci,
        &origen_device_gpiokeys,
        &origen_lcd_hv070wsa,
@@ -719,7 +745,12 @@ static void __init origen_machine_init(void)
        s5p_tv_setup();
        s5p_i2c_hdmiphy_set_platdata(NULL);
+#ifdef CONFIG_DRM_EXYNOS
+        s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata;
+        exynos4_fimd0_gpio_setup_24bpp();
+#else
        s5p_fimd0_set_platdata(&origen_lcd_pdata);
+#endif
        platform_add_devices(origen_devices, ARRAY_SIZE(origen_devices));
diff --git a/arch/arm/mach-exynos/mach-smdk4x12.c b/arch/arm/mach-exynos/mach-smdk4x12.c
index d00e4f016a68..fe772d893cc9 100644
--- a/arch/arm/mach-exynos/mach-smdk4x12.c
+++ b/arch/arm/mach-exynos/mach-smdk4x12.c
@@ -31,6 +31,7 @@
 #include <plat/gpio-cfg.h>
 #include <plat/iic.h>
 #include <plat/keypad.h>
+#include <plat/mfc.h>
 #include <plat/regs-serial.h>
 #include <plat/sdhci.h>
@@ -85,7 +86,6 @@ static struct s3c2410_uartcfg smdk4x12_uartcfgs[] __initdata = {
 static struct s3c_sdhci_platdata smdk4x12_hsmmc2_pdata __initdata = {
        .cd_type                = S3C_SDHCI_CD_INTERNAL,
-        .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
 #ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
        .max_width              = 8,
        .host_caps              = MMC_CAP_8_BIT_DATA,
@@ -94,7 +94,6 @@ static struct s3c_sdhci_platdata smdk4x12_hsmmc2_pdata __initdata = {
 static struct s3c_sdhci_platdata smdk4x12_hsmmc3_pdata __initdata = {
        .cd_type                = S3C_SDHCI_CD_INTERNAL,
-        .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
 };
 static struct regulator_consumer_supply max8997_buck1 =
@@ -244,6 +243,14 @@ static struct platform_device *smdk4x12_devices[] __initdata = {
        &s3c_device_i2c7,
        &s3c_device_rtc,
        &s3c_device_wdt,
+        &s5p_device_fimc0,
+        &s5p_device_fimc1,
+        &s5p_device_fimc2,
+        &s5p_device_fimc3,
+        &s5p_device_fimc_md,
+        &s5p_device_mfc,
+        &s5p_device_mfc_l,
+        &s5p_device_mfc_r,
        &samsung_device_keypad,
 };
@@ -256,6 +263,11 @@ static void __init smdk4x12_map_io(void)
        s3c24xx_init_uarts(smdk4x12_uartcfgs, ARRAY_SIZE(smdk4x12_uartcfgs));
 }
+static void __init smdk4x12_reserve(void)
+{
+        s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
+}
 static void __init smdk4x12_machine_init(void)
 {
        s3c_i2c0_set_platdata(NULL);
@@ -293,6 +305,7 @@ MACHINE_START(SMDK4212, "SMDK4212")
        .init_machine   = smdk4x12_machine_init,
        .timer          = &exynos4_timer,
        .restart        = exynos4_restart,
+        .reserve        = &smdk4x12_reserve,
 MACHINE_END
 MACHINE_START(SMDK4412, "SMDK4412")
@@ -305,4 +318,5 @@ MACHINE_START(SMDK4412, "SMDK4412")
        .init_machine   = smdk4x12_machine_init,
        .timer          = &exynos4_timer,
        .restart        = exynos4_restart,
+        .reserve        = &smdk4x12_reserve,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c
index 83b91fa777c1..5af96064ca51 100644
--- a/arch/arm/mach-exynos/mach-smdkv310.c
+++ b/arch/arm/mach-exynos/mach-smdkv310.c
@@ -44,6 +44,7 @@
 #include <mach/map.h>
 #include <mach/ohci.h>
+#include <drm/exynos_drm.h>
 #include "common.h"
 /* Following are default values for UCON, ULCON and UFCON UART registers */
@@ -93,7 +94,6 @@ static struct s3c2410_uartcfg smdkv310_uartcfgs[] __initdata = {
 static struct s3c_sdhci_platdata smdkv310_hsmmc0_pdata __initdata = {
        .cd_type                = S3C_SDHCI_CD_INTERNAL,
-        .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
 #ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
        .max_width              = 8,
        .host_caps              = MMC_CAP_8_BIT_DATA,
@@ -104,12 +104,10 @@ static struct s3c_sdhci_platdata smdkv310_hsmmc1_pdata __initdata = {
        .cd_type                = S3C_SDHCI_CD_GPIO,
        .ext_cd_gpio            = EXYNOS4_GPK0(2),
        .ext_cd_gpio_invert     = 1,
-        .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
 };
 static struct s3c_sdhci_platdata smdkv310_hsmmc2_pdata __initdata = {
        .cd_type                = S3C_SDHCI_CD_INTERNAL,
-        .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
 #ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
        .max_width              = 8,
        .host_caps              = MMC_CAP_8_BIT_DATA,
@@ -120,7 +118,6 @@ static struct s3c_sdhci_platdata smdkv310_hsmmc3_pdata __initdata = {
        .cd_type                = S3C_SDHCI_CD_GPIO,
        .ext_cd_gpio            = EXYNOS4_GPK2(2),
        .ext_cd_gpio_invert     = 1,
-        .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
 };
 static void lcd_lte480wv_set_power(struct plat_lcd_data *pd,
@@ -160,6 +157,26 @@ static struct platform_device smdkv310_lcd_lte480wv = {
        .dev.platform_data      = &smdkv310_lcd_lte480wv_data,
 };
+#ifdef CONFIG_DRM_EXYNOS
+static struct exynos_drm_fimd_pdata drm_fimd_pdata = {
+        .panel  = {
+                .timing = {
+                        .left_margin    = 13,
+                        .right_margin   = 8,
+                        .upper_margin   = 7,
+                        .lower_margin   = 5,
+                        .hsync_len      = 3,
+                        .vsync_len      = 1,
+                        .xres           = 800,
+                        .yres           = 480,
+                },
+        },
+        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
+        .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+        .default_win    = 0,
+        .bpp            = 32,
+};
+#else
 static struct s3c_fb_pd_win smdkv310_fb_win0 = {
        .win_mode = {
                .left_margin    = 13,
@@ -181,18 +198,12 @@ static struct s3c_fb_platdata smdkv310_lcd0_pdata __initdata = {
        .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
        .setup_gpio     = exynos4_fimd0_gpio_setup_24bpp,
 };
+#endif
 static struct resource smdkv310_smsc911x_resources[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM(EXYNOS4_PA_SROM_BANK(1), SZ_64K),
-                .start  = EXYNOS4_PA_SROM_BANK(1),
+        [1] = DEFINE_RES_NAMED(IRQ_EINT(5), 1, NULL, IORESOURCE_IRQ \
-                .end    = EXYNOS4_PA_SROM_BANK(1) + SZ_64K - 1,
+                                                | IRQF_TRIGGER_LOW),
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = IRQ_EINT(5),
-                .end    = IRQ_EINT(5),
-                .flags  = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
-        },
 };
 static struct smsc911x_platform_config smsc9215_config = {
@@ -273,6 +284,9 @@ static struct platform_device *smdkv310_devices[] __initdata = {
        &s5p_device_fimc_md,
        &s5p_device_g2d,
        &s5p_device_jpeg,
+#ifdef CONFIG_DRM_EXYNOS
+        &exynos_device_drm,
+#endif
        &exynos4_device_ac97,
        &exynos4_device_i2s0,
        &exynos4_device_ohci,
@@ -364,7 +378,12 @@ static void __init smdkv310_machine_init(void)
        samsung_keypad_set_platdata(&smdkv310_keypad_data);
        samsung_bl_set(&smdkv310_bl_gpio_info, &smdkv310_bl_data);
+#ifdef CONFIG_DRM_EXYNOS
+        s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata;
+        exynos4_fimd0_gpio_setup_24bpp();
+#else
        s5p_fimd0_set_platdata(&smdkv310_lcd0_pdata);
+#endif
        smdkv310_ehci_init();
        smdkv310_ohci_init();
diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c
index 6bb9dbdd73fd..6b731b863275 100644
--- a/arch/arm/mach-exynos/mach-universal_c210.c
+++ b/arch/arm/mach-exynos/mach-universal_c210.c
@@ -23,12 +23,15 @@
 #include <linux/i2c-gpio.h>
 #include <linux/i2c/mcs.h>
 #include <linux/i2c/atmel_mxt_ts.h>
+#include <linux/platform_data/s3c-hsotg.h>
+#include <drm/exynos_drm.h>
 #include <asm/mach/arch.h>
 #include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 #include <plat/regs-serial.h>
+#include <plat/clock.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/iic.h>
@@ -39,6 +42,7 @@
 #include <plat/pd.h>
 #include <plat/regs-fb-v4.h>
 #include <plat/fimc-core.h>
+#include <plat/s5p-time.h>
 #include <plat/camport.h>
 #include <plat/mipi_csis.h>
@@ -203,6 +207,7 @@ static struct regulator_init_data lp3974_ldo2_data = {
 };
 static struct regulator_consumer_supply lp3974_ldo3_consumer[] = {
+        REGULATOR_SUPPLY("vusb_a", "s3c-hsotg"),
        REGULATOR_SUPPLY("vdd", "exynos4-hdmi"),
        REGULATOR_SUPPLY("vdd_pll", "exynos4-hdmi"),
        REGULATOR_SUPPLY("vdd11", "s5p-mipi-csis.0"),
@@ -288,6 +293,7 @@ static struct regulator_init_data lp3974_ldo7_data = {
 };
 static struct regulator_consumer_supply lp3974_ldo8_consumer[] = {
+        REGULATOR_SUPPLY("vusb_d", "s3c-hsotg"),
        REGULATOR_SUPPLY("vdd33a_dac", "s5p-sdo"),
 };
@@ -484,7 +490,10 @@ static struct regulator_init_data lp3974_vichg_data = {
 static struct regulator_init_data lp3974_esafeout1_data = {
        .constraints    = {
                .name           = "SAFEOUT1",
+                .min_uV         = 4800000,
+                .max_uV         = 4800000,
                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+                .always_on      = 1,
                .state_mem      = {
                        .enabled        = 1,
                },
@@ -746,8 +755,8 @@ static struct s3c_sdhci_platdata universal_hsmmc0_data __initdata = {
        .max_width              = 8,
        .host_caps              = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
                                MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
+        .host_caps2             = MMC_CAP2_BROKEN_VOLTAGE,
        .cd_type                = S3C_SDHCI_CD_PERMANENT,
-        .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
 };
 static struct regulator_consumer_supply mmc0_supplies[] = {
@@ -787,7 +796,6 @@ static struct s3c_sdhci_platdata universal_hsmmc2_data __initdata = {
        .ext_cd_gpio            = EXYNOS4_GPX3(4),      /* XEINT_28 */
        .ext_cd_gpio_invert     = 1,
        .cd_type                = S3C_SDHCI_CD_GPIO,
-        .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
 };
 /* WiFi */
@@ -810,6 +818,29 @@ static struct i2c_board_info i2c1_devs[] __initdata = {
        /* Gyro, To be updated */
 };
+#ifdef CONFIG_DRM_EXYNOS
+static struct exynos_drm_fimd_pdata drm_fimd_pdata = {
+        .panel = {
+                .timing = {
+                        .left_margin    = 16,
+                        .right_margin   = 16,
+                        .upper_margin   = 2,
+                        .lower_margin   = 28,
+                        .hsync_len      = 2,
+                        .vsync_len      = 1,
+                        .xres           = 480,
+                        .yres           = 800,
+                        .refresh        = 55,
+                },
+        },
+        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB |
+                          VIDCON0_CLKSEL_LCD,
+        .vidcon1        = VIDCON1_INV_VCLK | VIDCON1_INV_VDEN
+                          | VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+        .default_win    = 3,
+        .bpp            = 32,
+};
+#else
 /* Frame Buffer */
 static struct s3c_fb_pd_win universal_fb_win0 = {
        .win_mode = {
@@ -837,6 +868,7 @@ static struct s3c_fb_platdata universal_lcd_pdata __initdata = {
                          | VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
        .setup_gpio     = exynos4_fimd0_gpio_setup_24bpp,
 };
+#endif
 static struct regulator_consumer_supply cam_vt_dio_supply =
        REGULATOR_SUPPLY("vdd_core", "0-003c");
@@ -991,6 +1023,9 @@ static struct gpio universal_camera_gpios[] = {
        { GPIO_CAM_VGA_NSTBY,   GPIOF_OUT_INIT_LOW,  "CAM_VGA_NSTBY" },
 };
+/* USB OTG */
+static struct s3c_hsotg_plat universal_hsotg_pdata;
 static void __init universal_camera_init(void)
 {
        s3c_set_platdata(&mipi_csis_platdata, sizeof(mipi_csis_platdata),
@@ -1046,6 +1081,10 @@ static struct platform_device *universal_devices[] __initdata = {
        &s5p_device_onenand,
        &s5p_device_fimd0,
        &s5p_device_jpeg,
+#ifdef CONFIG_DRM_EXYNOS
+        &exynos_device_drm,
+#endif
+        &s3c_device_usb_hsotg,
        &s5p_device_mfc,
        &s5p_device_mfc_l,
        &s5p_device_mfc_r,
@@ -1057,9 +1096,11 @@ static struct platform_device *universal_devices[] __initdata = {
 static void __init universal_map_io(void)
 {
+        clk_xusbxti.rate = 24000000;
        exynos_init_io(NULL, 0);
        s3c24xx_init_clocks(24000000);
        s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
+        s5p_set_timer_source(S5P_PWM2, S5P_PWM4);
 }
 static void s5p_tv_setup(void)
@@ -1091,12 +1132,18 @@ static void __init universal_machine_init(void)
        s5p_i2c_hdmiphy_set_platdata(NULL);
        i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs));
+#ifdef CONFIG_DRM_EXYNOS
+        s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata;
+        exynos4_fimd0_gpio_setup_24bpp();
+#else
        s5p_fimd0_set_platdata(&universal_lcd_pdata);
+#endif
        universal_touchkey_init();
        i2c_register_board_info(I2C_GPIO_BUS_12, i2c_gpio12_devs,
                        ARRAY_SIZE(i2c_gpio12_devs));
+        s3c_hsotg_set_platdata(&universal_hsotg_pdata);
        universal_camera_init();
        /* Last */
@@ -1110,7 +1157,7 @@ MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
        .map_io         = universal_map_io,
        .handle_irq     = gic_handle_irq,
        .init_machine   = universal_machine_init,
-        .timer          = &exynos4_timer,
+        .timer          = &s5p_timer,
        .reserve        = &universal_reserve,
        .restart        = exynos4_restart,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/setup-usb-phy.c b/arch/arm/mach-exynos/setup-usb-phy.c
index 41743d21e8c6..1af0a7f44e00 100644
--- a/arch/arm/mach-exynos/setup-usb-phy.c
+++ b/arch/arm/mach-exynos/setup-usb-phy.c
@@ -26,11 +26,71 @@ static int exynos4_usb_host_phy_is_on(void)
        return (readl(EXYNOS4_PHYPWR) & PHY1_STD_ANALOG_POWERDOWN) ? 0 : 1;
 }
-static int exynos4_usb_phy1_init(struct platform_device *pdev)
+static void exynos4210_usb_phy_clkset(struct platform_device *pdev)
 {
-        struct clk *otg_clk;
        struct clk *xusbxti_clk;
        u32 phyclk;
+        /* set clock frequency for PLL */
+        phyclk = readl(EXYNOS4_PHYCLK) & ~CLKSEL_MASK;
+        xusbxti_clk = clk_get(&pdev->dev, "xusbxti");
+        if (xusbxti_clk && !IS_ERR(xusbxti_clk)) {
+                switch (clk_get_rate(xusbxti_clk)) {
+                case 12 * MHZ:
+                        phyclk |= CLKSEL_12M;
+                        break;
+                case 24 * MHZ:
+                        phyclk |= CLKSEL_24M;
+                        break;
+                default:
+                case 48 * MHZ:
+                        /* default reference clock */
+                        break;
+                }
+                clk_put(xusbxti_clk);
+        }
+        writel(phyclk, EXYNOS4_PHYCLK);
+}
+static int exynos4210_usb_phy0_init(struct platform_device *pdev)
+{
+        u32 rstcon;
+        writel(readl(S5P_USBDEVICE_PHY_CONTROL) | S5P_USBDEVICE_PHY_ENABLE,
+                        S5P_USBDEVICE_PHY_CONTROL);
+        exynos4210_usb_phy_clkset(pdev);
+        /* set to normal PHY0 */
+        writel((readl(EXYNOS4_PHYPWR) & ~PHY0_NORMAL_MASK), EXYNOS4_PHYPWR);
+        /* reset PHY0 and Link */
+        rstcon = readl(EXYNOS4_RSTCON) | PHY0_SWRST_MASK;
+        writel(rstcon, EXYNOS4_RSTCON);
+        udelay(10);
+        rstcon &= ~PHY0_SWRST_MASK;
+        writel(rstcon, EXYNOS4_RSTCON);
+        return 0;
+}
+static int exynos4210_usb_phy0_exit(struct platform_device *pdev)
+{
+        writel((readl(EXYNOS4_PHYPWR) | PHY0_ANALOG_POWERDOWN |
+                                PHY0_OTG_DISABLE), EXYNOS4_PHYPWR);
+        writel(readl(S5P_USBDEVICE_PHY_CONTROL) & ~S5P_USBDEVICE_PHY_ENABLE,
+                        S5P_USBDEVICE_PHY_CONTROL);
+        return 0;
+}
+static int exynos4210_usb_phy1_init(struct platform_device *pdev)
+{
+        struct clk *otg_clk;
        u32 rstcon;
        int err;
@@ -54,27 +114,7 @@ static int exynos4_usb_phy1_init(struct platform_device *pdev)
        writel(readl(S5P_USBHOST_PHY_CONTROL) | S5P_USBHOST_PHY_ENABLE,
                        S5P_USBHOST_PHY_CONTROL);
-        /* set clock frequency for PLL */
+        exynos4210_usb_phy_clkset(pdev);
-        phyclk = readl(EXYNOS4_PHYCLK) & ~CLKSEL_MASK;
-        xusbxti_clk = clk_get(&pdev->dev, "xusbxti");
-        if (xusbxti_clk && !IS_ERR(xusbxti_clk)) {
-                switch (clk_get_rate(xusbxti_clk)) {
-                case 12 * MHZ:
-                        phyclk |= CLKSEL_12M;
-                        break;
-                case 24 * MHZ:
-                        phyclk |= CLKSEL_24M;
-                        break;
-                default:
-                case 48 * MHZ:
-                        /* default reference clock */
-                        break;
-                }
-                clk_put(xusbxti_clk);
-        }
-        writel(phyclk, EXYNOS4_PHYCLK);
        /* floating prevention logic: disable */
        writel((readl(EXYNOS4_PHY1CON) | FPENABLEN), EXYNOS4_PHY1CON);
@@ -102,7 +142,7 @@ static int exynos4_usb_phy1_init(struct platform_device *pdev)
        return 0;
 }
-static int exynos4_usb_phy1_exit(struct platform_device *pdev)
+static int exynos4210_usb_phy1_exit(struct platform_device *pdev)
 {
        struct clk *otg_clk;
        int err;
@@ -136,16 +176,20 @@ static int exynos4_usb_phy1_exit(struct platform_device *pdev)
 int s5p_usb_phy_init(struct platform_device *pdev, int type)
 {
-        if (type == S5P_USB_PHY_HOST)
+        if (type == S5P_USB_PHY_DEVICE)
-                return exynos4_usb_phy1_init(pdev);
+                return exynos4210_usb_phy0_init(pdev);
+        else if (type == S5P_USB_PHY_HOST)
+                return exynos4210_usb_phy1_init(pdev);
        return -EINVAL;
 }
 int s5p_usb_phy_exit(struct platform_device *pdev, int type)
 {
-        if (type == S5P_USB_PHY_HOST)
+        if (type == S5P_USB_PHY_DEVICE)
-                return exynos4_usb_phy1_exit(pdev);
+                return exynos4210_usb_phy0_exit(pdev);
+        else if (type == S5P_USB_PHY_HOST)
+                return exynos4210_usb_phy1_exit(pdev);
        return -EINVAL;
 }
diff --git a/arch/arm/mach-footbridge/cats-pci.c b/arch/arm/mach-footbridge/cats-pci.c
index 32321f66dec4..5cec2567c9c5 100644
--- a/arch/arm/mach-footbridge/cats-pci.c
+++ b/arch/arm/mach-footbridge/cats-pci.c
@@ -16,6 +16,11 @@
 /* cats host-specific stuff */
 static int irqmap_cats[] __initdata = { IRQ_PCI, IRQ_IN0, IRQ_IN1, IRQ_IN3 };
+static u8 cats_no_swizzle(struct pci_dev *dev, u8 *pin)
+{
+        return 0;
+}
 static int __init cats_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 {
        if (dev->irq >= 255)
@@ -39,11 +44,11 @@ static int __init cats_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 * cards being used (ie, pci-pci bridge based cards)?
 */
 static struct hw_pci cats_pci __initdata = {
-        .swizzle                = NULL,
+        .swizzle                = cats_no_swizzle,
        .map_irq                = cats_map_irq,
        .nr_controllers         = 1,
+        .ops                    = &dc21285_ops,
        .setup                  = dc21285_setup,
-        .scan                   = dc21285_scan_bus,
        .preinit                = dc21285_preinit,
        .postinit               = dc21285_postinit,
 };
diff --git a/arch/arm/mach-footbridge/dc21285.c b/arch/arm/mach-footbridge/dc21285.c
index e17e11de4f5e..9d62e3381024 100644
--- a/arch/arm/mach-footbridge/dc21285.c
+++ b/arch/arm/mach-footbridge/dc21285.c
@@ -129,7 +129,7 @@ dc21285_write_config(struct pci_bus *bus, unsigned int devfn, int where,
        return PCIBIOS_SUCCESSFUL;
 }
-static struct pci_ops dc21285_ops = {
+struct pci_ops dc21285_ops = {
        .read   = dc21285_read_config,
        .write  = dc21285_write_config,
 };
@@ -284,11 +284,6 @@ int __init dc21285_setup(int nr, struct pci_sys_data *sys)
        return 1;
 }
-struct pci_bus * __init dc21285_scan_bus(int nr, struct pci_sys_data *sys)
-{
-        return pci_scan_root_bus(NULL, 0, &dc21285_ops, sys, &sys->resources);
-}
 #define dc21285_request_irq(_a, _b, _c, _d, _e) \
        WARN_ON(request_irq(_a, _b, _c, _d, _e) < 0)
diff --git a/arch/arm/mach-footbridge/ebsa285-pci.c b/arch/arm/mach-footbridge/ebsa285-pci.c
index 511c673ffa9d..fd12d8a36dc5 100644
--- a/arch/arm/mach-footbridge/ebsa285-pci.c
+++ b/arch/arm/mach-footbridge/ebsa285-pci.c
@@ -29,11 +29,10 @@ static int __init ebsa285_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 }
 static struct hw_pci ebsa285_pci __initdata = {
-        .swizzle                = pci_std_swizzle,
        .map_irq                = ebsa285_map_irq,
        .nr_controllers         = 1,
+        .ops                    = &dc21285_ops,
        .setup                  = dc21285_setup,
-        .scan                   = dc21285_scan_bus,
        .preinit                = dc21285_preinit,
        .postinit               = dc21285_postinit,
 };
diff --git a/arch/arm/mach-footbridge/netwinder-pci.c b/arch/arm/mach-footbridge/netwinder-pci.c
index 62187610e17e..0fba5134e4fe 100644
--- a/arch/arm/mach-footbridge/netwinder-pci.c
+++ b/arch/arm/mach-footbridge/netwinder-pci.c
@@ -43,11 +43,10 @@ static int __init netwinder_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 }
 static struct hw_pci netwinder_pci __initdata = {
-        .swizzle                = pci_std_swizzle,
        .map_irq                = netwinder_map_irq,
        .nr_controllers         = 1,
+        .ops                    = &dc21285_ops,
        .setup                  = dc21285_setup,
-        .scan                   = dc21285_scan_bus,
        .preinit                = dc21285_preinit,
        .postinit               = dc21285_postinit,
 };
diff --git a/arch/arm/mach-footbridge/personal-pci.c b/arch/arm/mach-footbridge/personal-pci.c
index aeb651d914a6..5c9ee54613b2 100644
--- a/arch/arm/mach-footbridge/personal-pci.c
+++ b/arch/arm/mach-footbridge/personal-pci.c
@@ -41,8 +41,8 @@ static int __init personal_server_map_irq(const struct pci_dev *dev, u8 slot,
 static struct hw_pci personal_server_pci __initdata = {
        .map_irq                = personal_server_map_irq,
        .nr_controllers         = 1,
+        .ops                    = &dc21285_ops,
        .setup                  = dc21285_setup,
-        .scan                   = dc21285_scan_bus,
        .preinit                = dc21285_preinit,
        .postinit               = dc21285_postinit,
 };
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 7561eca131b0..7d6322ce5223 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -163,6 +163,7 @@ config MACH_EUKREA_CPUIMX25SD
        select SOC_IMX25
        select IMX_HAVE_PLATFORM_FLEXCAN
        select IMX_HAVE_PLATFORM_FSL_USB2_UDC
+        select IMX_HAVE_PLATFORM_IMX2_WDT
        select IMX_HAVE_PLATFORM_IMXDI_RTC
        select IMX_HAVE_PLATFORM_IMX_FB
        select IMX_HAVE_PLATFORM_IMX_I2C
@@ -181,6 +182,7 @@ config MACH_EUKREA_MBIMXSD25_BASEBOARD
        bool "Eukrea MBIMXSD development board"
        select IMX_HAVE_PLATFORM_GPIO_KEYS
        select IMX_HAVE_PLATFORM_IMX_SSI
+        select IMX_HAVE_PLATFORM_SPI_IMX
        select LEDS_GPIO_REGISTER
        help
          This adds board specific devices that can be found on Eukrea's
@@ -571,8 +573,10 @@ config MACH_MX35_3DS
        select MXC_DEBUG_BOARD
        select IMX_HAVE_PLATFORM_FSL_USB2_UDC
        select IMX_HAVE_PLATFORM_IMX2_WDT
+        select IMX_HAVE_PLATFORM_IMX_FB
        select IMX_HAVE_PLATFORM_IMX_I2C
        select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_IPU_CORE
        select IMX_HAVE_PLATFORM_MXC_EHCI
        select IMX_HAVE_PLATFORM_MXC_NAND
        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
@@ -606,6 +610,7 @@ config MACH_EUKREA_MBIMXSD35_BASEBOARD
        select IMX_HAVE_PLATFORM_GPIO_KEYS
        select IMX_HAVE_PLATFORM_IMX_SSI
        select IMX_HAVE_PLATFORM_IPU_CORE
+        select IMX_HAVE_PLATFORM_SPI_IMX
        select LEDS_GPIO_REGISTER
        help
          This adds board specific devices that can be found on Eukrea's
@@ -682,42 +687,13 @@ config MACH_MX51_3DS
          Include support for MX51PDK (3DS) platform. This includes specific
          configurations for the board and its peripherals.
-config MACH_EUKREA_CPUIMX51
-        bool "Support Eukrea CPUIMX51 module"
-        select SOC_IMX51
-        select IMX_HAVE_PLATFORM_FSL_USB2_UDC
-        select IMX_HAVE_PLATFORM_IMX_I2C
-        select IMX_HAVE_PLATFORM_IMX_UART
-        select IMX_HAVE_PLATFORM_MXC_EHCI
-        select IMX_HAVE_PLATFORM_MXC_NAND
-        select IMX_HAVE_PLATFORM_SPI_IMX
-        help
-          Include support for Eukrea CPUIMX51 platform. This includes
-          specific configurations for the module and its peripherals.
-choice
-        prompt "Baseboard"
-        depends on MACH_EUKREA_CPUIMX51
-        default MACH_EUKREA_MBIMX51_BASEBOARD
-config MACH_EUKREA_MBIMX51_BASEBOARD
-        prompt "Eukrea MBIMX51 development board"
-        bool
-        select IMX_HAVE_PLATFORM_IMX_KEYPAD
-        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
-        select LEDS_GPIO_REGISTER
-        help
-          This adds board specific devices that can be found on Eukrea's
-          MBIMX51 evaluation board.
-endchoice
 config MACH_EUKREA_CPUIMX51SD
        bool "Support Eukrea CPUIMX51SD module"
        select SOC_IMX51
        select IMX_HAVE_PLATFORM_FSL_USB2_UDC
        select IMX_HAVE_PLATFORM_IMX_I2C
        select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_IMX2_WDT
        select IMX_HAVE_PLATFORM_MXC_EHCI
        select IMX_HAVE_PLATFORM_MXC_NAND
        select IMX_HAVE_PLATFORM_SPI_IMX
@@ -733,6 +709,7 @@ choice
 config MACH_EUKREA_MBIMXSD51_BASEBOARD
        prompt "Eukrea MBIMXSD development board"
        bool
+        select IMX_HAVE_PLATFORM_IMX_SSI
        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
        select LEDS_GPIO_REGISTER
        help
@@ -842,6 +819,8 @@ config SOC_IMX6Q
        select HAVE_IMX_MMDC
        select HAVE_IMX_SRC
        select HAVE_SMP
+        select PINCTRL
+        select PINCTRL_IMX6Q
        select USE_OF
        help
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index ab939c5046c3..4937c070a57e 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -83,10 +83,8 @@ obj-$(CONFIG_MACH_MX53_EVK) += mach-mx53_evk.o
 obj-$(CONFIG_MACH_MX53_SMD) += mach-mx53_smd.o
 obj-$(CONFIG_MACH_MX53_LOCO) += mach-mx53_loco.o
 obj-$(CONFIG_MACH_MX53_ARD) += mach-mx53_ard.o
-obj-$(CONFIG_MACH_EUKREA_CPUIMX51) += mach-cpuimx51.o
-obj-$(CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD) += eukrea_mbimx51-baseboard.o
 obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += mach-cpuimx51sd.o
-obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd-baseboard.o
+obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd51-baseboard.o
 obj-$(CONFIG_MX51_EFIKA_COMMON) += mx51_efika.o
 obj-$(CONFIG_MACH_MX51_EFIKAMX) += mach-mx51_efikamx.o
 obj-$(CONFIG_MACH_MX51_EFIKASB) += mach-mx51_efikasb.o
diff --git a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
index 5f2f91d1798b..b46cab0ced53 100644
--- a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
@@ -243,7 +243,7 @@ static const struct imxuart_platform_data uart_pdata __initconst = {
 static void __maybe_unused ads7846_dev_init(void)
 {
        if (gpio_request(ADS7846_PENDOWN, "ADS7846 pendown") < 0) {
-                printk(KERN_ERR "can't get ads746 pen down GPIO\n");
+                printk(KERN_ERR "can't get ads7846 pen down GPIO\n");
                return;
        }
        gpio_direction_input(ADS7846_PENDOWN);
diff --git a/arch/arm/mach-imx/eukrea_mbimx51-baseboard.c b/arch/arm/mach-imx/eukrea_mbimx51-baseboard.c
deleted file mode 100644
index a6a3ab8f1b1c..000000000000
--- a/arch/arm/mach-imx/eukrea_mbimx51-baseboard.c
+++ /dev/null
@@ -1,206 +0,0 @@
-/*
- *
- * Copyright (C) 2010 Eric Bénard <eric@eukrea.com>
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/serial_8250.h>
-#include <linux/i2c.h>
-#include <linux/gpio.h>
-#include <linux/io.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/i2c/tsc2007.h>
-#include <linux/leds.h>
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <mach/iomux-mx51.h>
-#include <asm/mach/arch.h>
-#include "devices-imx51.h"
-#define MBIMX51_TSC2007_GPIO    IMX_GPIO_NR(3, 30)
-#define MBIMX51_LED0            IMX_GPIO_NR(3, 5)
-#define MBIMX51_LED1            IMX_GPIO_NR(3, 6)
-#define MBIMX51_LED2            IMX_GPIO_NR(3, 7)
-#define MBIMX51_LED3            IMX_GPIO_NR(3, 8)
-static const struct gpio_led mbimx51_leds[] __initconst = {
-        {
-                .name                   = "led0",
-                .default_trigger        = "heartbeat",
-                .active_low             = 1,
-                .gpio                   = MBIMX51_LED0,
-        },
-        {
-                .name                   = "led1",
-                .default_trigger        = "nand-disk",
-                .active_low             = 1,
-                .gpio                   = MBIMX51_LED1,
-        },
-        {
-                .name                   = "led2",
-                .default_trigger        = "mmc0",
-                .active_low             = 1,
-                .gpio                   = MBIMX51_LED2,
-        },
-        {
-                .name                   = "led3",
-                .default_trigger        = "default-on",
-                .active_low             = 1,
-                .gpio                   = MBIMX51_LED3,
-        },
-};
-static const struct gpio_led_platform_data mbimx51_leds_info __initconst = {
-        .leds           = mbimx51_leds,
-        .num_leds       = ARRAY_SIZE(mbimx51_leds),
-};
-static iomux_v3_cfg_t mbimx51_pads[] = {
-        /* UART2 */
-        MX51_PAD_UART2_RXD__UART2_RXD,
-        MX51_PAD_UART2_TXD__UART2_TXD,
-        /* UART3 */
-        MX51_PAD_UART3_RXD__UART3_RXD,
-        MX51_PAD_UART3_TXD__UART3_TXD,
-        MX51_PAD_KEY_COL4__UART3_RTS,
-        MX51_PAD_KEY_COL5__UART3_CTS,
-        /* TSC2007 IRQ */
-        MX51_PAD_NANDF_D10__GPIO3_30,
-        /* LEDS */
-        MX51_PAD_DISPB2_SER_DIN__GPIO3_5,
-        MX51_PAD_DISPB2_SER_DIO__GPIO3_6,
-        MX51_PAD_DISPB2_SER_CLK__GPIO3_7,
-        MX51_PAD_DISPB2_SER_RS__GPIO3_8,
-        /* KPP */
-        MX51_PAD_KEY_ROW0__KEY_ROW0,
-        MX51_PAD_KEY_ROW1__KEY_ROW1,
-        MX51_PAD_KEY_ROW2__KEY_ROW2,
-        MX51_PAD_KEY_ROW3__KEY_ROW3,
-        MX51_PAD_KEY_COL0__KEY_COL0,
-        MX51_PAD_KEY_COL1__KEY_COL1,
-        MX51_PAD_KEY_COL2__KEY_COL2,
-        MX51_PAD_KEY_COL3__KEY_COL3,
-        /* SD 1 */
-        MX51_PAD_SD1_CMD__SD1_CMD,
-        MX51_PAD_SD1_CLK__SD1_CLK,
-        MX51_PAD_SD1_DATA0__SD1_DATA0,
-        MX51_PAD_SD1_DATA1__SD1_DATA1,
-        MX51_PAD_SD1_DATA2__SD1_DATA2,
-        MX51_PAD_SD1_DATA3__SD1_DATA3,
-        /* SD 2 */
-        MX51_PAD_SD2_CMD__SD2_CMD,
-        MX51_PAD_SD2_CLK__SD2_CLK,
-        MX51_PAD_SD2_DATA0__SD2_DATA0,
-        MX51_PAD_SD2_DATA1__SD2_DATA1,
-        MX51_PAD_SD2_DATA2__SD2_DATA2,
-        MX51_PAD_SD2_DATA3__SD2_DATA3,
-};
-static const struct imxuart_platform_data uart_pdata __initconst = {
-        .flags = IMXUART_HAVE_RTSCTS,
-};
-static int mbimx51_keymap[] = {
-        KEY(0, 0, KEY_1),
-        KEY(0, 1, KEY_2),
-        KEY(0, 2, KEY_3),
-        KEY(0, 3, KEY_UP),
-        KEY(1, 0, KEY_4),
-        KEY(1, 1, KEY_5),
-        KEY(1, 2, KEY_6),
-        KEY(1, 3, KEY_LEFT),
-        KEY(2, 0, KEY_7),
-        KEY(2, 1, KEY_8),
-        KEY(2, 2, KEY_9),
-        KEY(2, 3, KEY_RIGHT),
-        KEY(3, 0, KEY_0),
-        KEY(3, 1, KEY_DOWN),
-        KEY(3, 2, KEY_ESC),
-        KEY(3, 3, KEY_ENTER),
-};
-static const struct matrix_keymap_data mbimx51_map_data __initconst = {
-        .keymap         = mbimx51_keymap,
-        .keymap_size    = ARRAY_SIZE(mbimx51_keymap),
-};
-static int tsc2007_get_pendown_state(void)
-{
-        return !gpio_get_value(MBIMX51_TSC2007_GPIO);
-}
-struct tsc2007_platform_data tsc2007_data = {
-        .model = 2007,
-        .x_plate_ohms = 180,
-        .get_pendown_state = tsc2007_get_pendown_state,
-};
-static struct i2c_board_info mbimx51_i2c_devices[] = {
-        {
-                I2C_BOARD_INFO("tsc2007", 0x49),
-                .irq  = IMX_GPIO_TO_IRQ(MBIMX51_TSC2007_GPIO),
-                .platform_data = &tsc2007_data,
-        }, {
-                I2C_BOARD_INFO("tlv320aic23", 0x1a),
-        },
-};
-/*
- * baseboard initialization.
- */
-void __init eukrea_mbimx51_baseboard_init(void)
-{
-        mxc_iomux_v3_setup_multiple_pads(mbimx51_pads,
-                                        ARRAY_SIZE(mbimx51_pads));
-        imx51_add_imx_uart(1, NULL);
-        imx51_add_imx_uart(2, &uart_pdata);
-        gpio_request(MBIMX51_LED0, "LED0");
-        gpio_direction_output(MBIMX51_LED0, 1);
-        gpio_free(MBIMX51_LED0);
-        gpio_request(MBIMX51_LED1, "LED1");
-        gpio_direction_output(MBIMX51_LED1, 1);
-        gpio_free(MBIMX51_LED1);
-        gpio_request(MBIMX51_LED2, "LED2");
-        gpio_direction_output(MBIMX51_LED2, 1);
-        gpio_free(MBIMX51_LED2);
-        gpio_request(MBIMX51_LED3, "LED3");
-        gpio_direction_output(MBIMX51_LED3, 1);
-        gpio_free(MBIMX51_LED3);
-        gpio_led_register_device(-1, &mbimx51_leds_info);
-        imx51_add_imx_keypad(&mbimx51_map_data);
-        gpio_request(MBIMX51_TSC2007_GPIO, "tsc2007_irq");
-        gpio_direction_input(MBIMX51_TSC2007_GPIO);
-        irq_set_irq_type(gpio_to_irq(MBIMX51_TSC2007_GPIO),
-                                        IRQF_TRIGGER_FALLING);
-        i2c_register_board_info(1, mbimx51_i2c_devices,
-                                ARRAY_SIZE(mbimx51_i2c_devices));
-        imx51_add_sdhci_esdhc_imx(0, NULL);
-        imx51_add_sdhci_esdhc_imx(1, NULL);
-}
diff --git a/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
index 2cf603e11c4f..dfd2da87c2df 100644
--- a/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
@@ -23,6 +23,7 @@
 #include <linux/leds.h>
 #include <linux/platform_device.h>
 #include <linux/input.h>
+#include <linux/spi/spi.h>
 #include <video/platform_lcd.h>
 #include <mach/hardware.h>
@@ -87,12 +88,22 @@ static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = {
        /* CAN */
        MX25_PAD_GPIO_D__CAN2_RX,
        MX25_PAD_GPIO_C__CAN2_TX,
+        /* SPI1 */
+        MX25_PAD_CSPI1_MOSI__CSPI1_MOSI,
+        MX25_PAD_CSPI1_MISO__CSPI1_MISO,
+        MX25_PAD_CSPI1_SS0__GPIO_1_16,
+        MX25_PAD_CSPI1_SS1__GPIO_1_17,
+        MX25_PAD_CSPI1_SCLK__CSPI1_SCLK,
+        MX25_PAD_CSPI1_RDY__GPIO_2_22,
 };
-#define GPIO_LED1       83
+#define GPIO_LED1               IMX_GPIO_NR(3, 19)
-#define GPIO_SWITCH1    82
+#define GPIO_SWITCH1    IMX_GPIO_NR(3, 18)
-#define GPIO_SD1CD      52
+#define GPIO_SD1CD              IMX_GPIO_NR(2, 20)
-#define GPIO_LCDPWR     26
+#define GPIO_LCDPWR             IMX_GPIO_NR(1, 26)
+#define GPIO_SPI1_SS0   IMX_GPIO_NR(1, 16)
+#define GPIO_SPI1_SS1   IMX_GPIO_NR(1, 17)
+#define GPIO_SPI1_IRQ   IMX_GPIO_NR(2, 22)
 static struct imx_fb_videomode eukrea_mximxsd_modes[] = {
        {
@@ -228,6 +239,30 @@ static struct esdhc_platform_data sd1_pdata = {
        .wp_type = ESDHC_WP_NONE,
 };
+static struct spi_board_info eukrea_mbimxsd25_spi_board_info[] __initdata = {
+        {
+                .modalias = "spidev",
+                .max_speed_hz = 20000000,
+                .bus_num = 0,
+                .chip_select = 0,
+                .mode = SPI_MODE_0,
+        },
+        {
+                .modalias = "spidev",
+                .max_speed_hz = 20000000,
+                .bus_num = 0,
+                .chip_select = 1,
+                .mode = SPI_MODE_0,
+        },
+};
+static int eukrea_mbimxsd25_spi_cs[] = {GPIO_SPI1_SS0, GPIO_SPI1_SS1};
+static const struct spi_imx_master eukrea_mbimxsd25_spi0_data __initconst = {
+        .chipselect     = eukrea_mbimxsd25_spi_cs,
+        .num_chipselect = ARRAY_SIZE(eukrea_mbimxsd25_spi_cs),
+};
 /*
 * system init for baseboard usage. Will be called by cpuimx25 init.
 *
@@ -257,11 +292,17 @@ void __init eukrea_mbimxsd25_baseboard_init(void)
        gpio_request(GPIO_LCDPWR, "LCDPWR");
        gpio_direction_output(GPIO_LCDPWR, 1);
-        gpio_free(GPIO_SWITCH1);
        i2c_register_board_info(0, eukrea_mbimxsd_i2c_devices,
                                ARRAY_SIZE(eukrea_mbimxsd_i2c_devices));
+        gpio_request(GPIO_SPI1_IRQ, "SPI1_IRQ");
+        gpio_direction_input(GPIO_SPI1_IRQ);
+        gpio_free(GPIO_SPI1_IRQ);
+        imx25_add_spi_imx0(&eukrea_mbimxsd25_spi0_data);
+        spi_register_board_info(eukrea_mbimxsd25_spi_board_info,
+                ARRAY_SIZE(eukrea_mbimxsd25_spi_board_info));
        platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
        gpio_led_register_device(-1, &eukrea_mbimxsd_led_info);
        imx_add_gpio_keys(&eukrea_mbimxsd_button_data);
diff --git a/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
index fd8bf8a425a7..557f6c486053 100644
--- a/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
@@ -27,6 +27,7 @@
 #include <linux/leds.h>
 #include <linux/platform_device.h>
 #include <linux/input.h>
+#include <linux/spi/spi.h>
 #include <video/platform_lcd.h>
 #include <linux/i2c.h>
@@ -158,12 +159,22 @@ static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = {
        MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
        /* SD1 CD */
        MX35_PAD_LD18__GPIO3_24,
+        /* SPI */
+        MX35_PAD_CSPI1_MOSI__CSPI1_MOSI,
+        MX35_PAD_CSPI1_MISO__CSPI1_MISO,
+        MX35_PAD_CSPI1_SS0__GPIO1_18,
+        MX35_PAD_CSPI1_SS1__GPIO1_19,
+        MX35_PAD_CSPI1_SCLK__CSPI1_SCLK,
+        MX35_PAD_CSPI1_SPI_RDY__GPIO3_5,
 };
 #define GPIO_LED1       IMX_GPIO_NR(3, 29)
 #define GPIO_SWITCH1    IMX_GPIO_NR(3, 25)
 #define GPIO_LCDPWR     IMX_GPIO_NR(1, 4)
 #define GPIO_SD1CD      IMX_GPIO_NR(3, 24)
+#define GPIO_SPI1_SS0   IMX_GPIO_NR(1, 18)
+#define GPIO_SPI1_SS1   IMX_GPIO_NR(1, 19)
+#define GPIO_SPI1_IRQ   IMX_GPIO_NR(3, 5)
 static void eukrea_mbimxsd_lcd_power_set(struct plat_lcd_data *pd,
                                   unsigned int power)
@@ -239,6 +250,30 @@ static struct esdhc_platform_data sd1_pdata = {
        .wp_type = ESDHC_WP_NONE,
 };
+static struct spi_board_info eukrea_mbimxsd35_spi_board_info[] __initdata = {
+        {
+                .modalias = "spidev",
+                .max_speed_hz = 20000000,
+                .bus_num = 0,
+                .chip_select = 0,
+                .mode = SPI_MODE_0,
+        },
+        {
+                .modalias = "spidev",
+                .max_speed_hz = 20000000,
+                .bus_num = 0,
+                .chip_select = 1,
+                .mode = SPI_MODE_0,
+        },
+};
+static int eukrea_mbimxsd35_spi_cs[] = {GPIO_SPI1_SS0, GPIO_SPI1_SS1};
+static const struct spi_imx_master eukrea_mbimxsd35_spi0_data __initconst = {
+        .chipselect     = eukrea_mbimxsd35_spi_cs,
+        .num_chipselect = ARRAY_SIZE(eukrea_mbimxsd35_spi_cs),
+};
 /*
 * system init for baseboard usage. Will be called by cpuimx35 init.
 *
@@ -274,6 +309,13 @@ void __init eukrea_mbimxsd35_baseboard_init(void)
        i2c_register_board_info(0, eukrea_mbimxsd_i2c_devices,
                                ARRAY_SIZE(eukrea_mbimxsd_i2c_devices));
+        gpio_request(GPIO_SPI1_IRQ, "SPI1_IRQ");
+        gpio_direction_input(GPIO_SPI1_IRQ);
+        gpio_free(GPIO_SPI1_IRQ);
+        imx35_add_spi_imx0(&eukrea_mbimxsd35_spi0_data);
+        spi_register_board_info(eukrea_mbimxsd35_spi_board_info,
+                ARRAY_SIZE(eukrea_mbimxsd35_spi_board_info));
        platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
        gpio_led_register_device(-1, &eukrea_mbimxsd_led_info);
        imx_add_gpio_keys(&eukrea_mbimxsd_button_data);
diff --git a/arch/arm/mach-imx/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd51-baseboard.c
index aaa592fdb9ce..96a24b73dc23 100644
--- a/arch/arm/mach-imx/eukrea_mbimxsd-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimxsd51-baseboard.c
@@ -28,6 +28,8 @@
 #include <linux/platform_device.h>
 #include <linux/input.h>
 #include <linux/i2c.h>
+#include <video/platform_lcd.h>
+#include <linux/backlight.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -40,7 +42,7 @@
 #include "devices-imx51.h"
-static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = {
+static iomux_v3_cfg_t eukrea_mbimxsd51_pads[] = {
        /* LED */
        MX51_PAD_NANDF_D10__GPIO3_30,
        /* SWITCH */
@@ -66,12 +68,64 @@ static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = {
        NEW_PAD_CTRL(MX51_PAD_GPIO1_0__SD1_CD, PAD_CTL_PUS_22K_UP |
                        PAD_CTL_PKE | PAD_CTL_SRE_FAST |
                        PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
+        /* SSI */
+        MX51_PAD_AUD3_BB_TXD__AUD3_TXD,
+        MX51_PAD_AUD3_BB_RXD__AUD3_RXD,
+        MX51_PAD_AUD3_BB_CK__AUD3_TXC,
+        MX51_PAD_AUD3_BB_FS__AUD3_TXFS,
+        /* LCD Backlight */
+        MX51_PAD_DI1_D1_CS__GPIO3_4,
+        /* LCD RST */
+        MX51_PAD_CSI1_D9__GPIO3_13,
 };
 #define GPIO_LED1       IMX_GPIO_NR(3, 30)
 #define GPIO_SWITCH1    IMX_GPIO_NR(3, 31)
+#define GPIO_LCDRST     IMX_GPIO_NR(3, 13)
+#define GPIO_LCDBL      IMX_GPIO_NR(3, 4)
-static const struct gpio_led eukrea_mbimxsd_leds[] __initconst = {
+static void eukrea_mbimxsd51_lcd_power_set(struct plat_lcd_data *pd,
+                                   unsigned int power)
+{
+        if (power)
+                gpio_direction_output(GPIO_LCDRST, 1);
+        else
+                gpio_direction_output(GPIO_LCDRST, 0);
+}
+static struct plat_lcd_data eukrea_mbimxsd51_lcd_power_data = {
+        .set_power              = eukrea_mbimxsd51_lcd_power_set,
+};
+static struct platform_device eukrea_mbimxsd51_lcd_powerdev = {
+        .name                   = "platform-lcd",
+        .dev.platform_data      = &eukrea_mbimxsd51_lcd_power_data,
+};
+static void eukrea_mbimxsd51_bl_set_intensity(int intensity)
+{
+        if (intensity)
+                gpio_direction_output(GPIO_LCDBL, 1);
+        else
+                gpio_direction_output(GPIO_LCDBL, 0);
+}
+static struct generic_bl_info eukrea_mbimxsd51_bl_info = {
+        .name                   = "eukrea_mbimxsd51-bl",
+        .max_intensity          = 0xff,
+        .default_intensity      = 0xff,
+        .set_bl_intensity       = eukrea_mbimxsd51_bl_set_intensity,
+};
+static struct platform_device eukrea_mbimxsd51_bl_dev = {
+        .name                   = "generic-bl",
+        .id                     = 1,
+        .dev = {
+                .platform_data  = &eukrea_mbimxsd51_bl_info,
+        },
+};
+static const struct gpio_led eukrea_mbimxsd51_leds[] __initconst = {
        {
                .name                   = "led1",
                .default_trigger        = "heartbeat",
@@ -81,12 +135,12 @@ static const struct gpio_led eukrea_mbimxsd_leds[] __initconst = {
 };
 static const struct gpio_led_platform_data
-                eukrea_mbimxsd_led_info __initconst = {
+                eukrea_mbimxsd51_led_info __initconst = {
-        .leds           = eukrea_mbimxsd_leds,
+        .leds           = eukrea_mbimxsd51_leds,
-        .num_leds       = ARRAY_SIZE(eukrea_mbimxsd_leds),
+        .num_leds       = ARRAY_SIZE(eukrea_mbimxsd51_leds),
 };
-static struct gpio_keys_button eukrea_mbimxsd_gpio_buttons[] = {
+static struct gpio_keys_button eukrea_mbimxsd51_gpio_buttons[] = {
        {
                .gpio           = GPIO_SWITCH1,
                .code           = BTN_0,
@@ -97,21 +151,39 @@ static struct gpio_keys_button eukrea_mbimxsd_gpio_buttons[] = {
 };
 static const struct gpio_keys_platform_data
-                eukrea_mbimxsd_button_data __initconst = {
+                eukrea_mbimxsd51_button_data __initconst = {
-        .buttons        = eukrea_mbimxsd_gpio_buttons,
+        .buttons        = eukrea_mbimxsd51_gpio_buttons,
-        .nbuttons       = ARRAY_SIZE(eukrea_mbimxsd_gpio_buttons),
+        .nbuttons       = ARRAY_SIZE(eukrea_mbimxsd51_gpio_buttons),
 };
 static const struct imxuart_platform_data uart_pdata __initconst = {
        .flags = IMXUART_HAVE_RTSCTS,
 };
-static struct i2c_board_info eukrea_mbimxsd_i2c_devices[] = {
+static struct i2c_board_info eukrea_mbimxsd51_i2c_devices[] = {
        {
                I2C_BOARD_INFO("tlv320aic23", 0x1a),
        },
 };
+static const
+struct imx_ssi_platform_data eukrea_mbimxsd51_ssi_pdata __initconst = {
+        .flags = IMX_SSI_SYN | IMX_SSI_NET | IMX_SSI_USE_I2S_SLAVE,
+};
+static int screen_type;
+static int __init eukrea_mbimxsd51_screen_type(char *options)
+{
+        if (!strcmp(options, "dvi"))
+                screen_type = 1;
+        else if (!strcmp(options, "tft"))
+                screen_type = 0;
+        return 0;
+}
+__setup("screen_type=", eukrea_mbimxsd51_screen_type);
 /*
 * system init for baseboard usage. Will be called by cpuimx51sd init.
 *
@@ -120,8 +192,8 @@ static struct i2c_board_info eukrea_mbimxsd_i2c_devices[] = {
 */
 void __init eukrea_mbimxsd51_baseboard_init(void)
 {
-        if (mxc_iomux_v3_setup_multiple_pads(eukrea_mbimxsd_pads,
+        if (mxc_iomux_v3_setup_multiple_pads(eukrea_mbimxsd51_pads,
-                        ARRAY_SIZE(eukrea_mbimxsd_pads)))
+                        ARRAY_SIZE(eukrea_mbimxsd51_pads)))
                printk(KERN_ERR "error setting mbimxsd pads !\n");
        imx51_add_imx_uart(1, NULL);
@@ -129,6 +201,8 @@ void __init eukrea_mbimxsd51_baseboard_init(void)
        imx51_add_sdhci_esdhc_imx(0, NULL);
+        imx51_add_imx_ssi(0, &eukrea_mbimxsd51_ssi_pdata);
        gpio_request(GPIO_LED1, "LED1");
        gpio_direction_output(GPIO_LED1, 1);
        gpio_free(GPIO_LED1);
@@ -137,9 +211,21 @@ void __init eukrea_mbimxsd51_baseboard_init(void)
        gpio_direction_input(GPIO_SWITCH1);
        gpio_free(GPIO_SWITCH1);
-        i2c_register_board_info(0, eukrea_mbimxsd_i2c_devices,
+        gpio_request(GPIO_LCDRST, "LCDRST");
-                                ARRAY_SIZE(eukrea_mbimxsd_i2c_devices));
+        gpio_direction_output(GPIO_LCDRST, 0);
+        gpio_request(GPIO_LCDBL, "LCDBL");
-        gpio_led_register_device(-1, &eukrea_mbimxsd_led_info);
+        gpio_direction_output(GPIO_LCDBL, 0);
-        imx_add_gpio_keys(&eukrea_mbimxsd_button_data);
+        if (!screen_type) {
+                platform_device_register(&eukrea_mbimxsd51_bl_dev);
+                platform_device_register(&eukrea_mbimxsd51_lcd_powerdev);
+        } else {
+                gpio_free(GPIO_LCDRST);
+                gpio_free(GPIO_LCDBL);
+        }
+        i2c_register_board_info(0, eukrea_mbimxsd51_i2c_devices,
+                                ARRAY_SIZE(eukrea_mbimxsd51_i2c_devices));
+        gpio_led_register_device(-1, &eukrea_mbimxsd51_led_info);
+        imx_add_gpio_keys(&eukrea_mbimxsd51_button_data);
 }
diff --git a/arch/arm/mach-imx/imx27-dt.c b/arch/arm/mach-imx/imx27-dt.c
index 861ceb8232d6..ed38d03c61f2 100644
--- a/arch/arm/mach-imx/imx27-dt.c
+++ b/arch/arm/mach-imx/imx27-dt.c
@@ -35,7 +35,7 @@ static const struct of_dev_auxdata imx27_auxdata_lookup[] __initconst = {
 static int __init imx27_avic_add_irq_domain(struct device_node *np,
                                struct device_node *interrupt_parent)
 {
-        irq_domain_add_simple(np, 0);
+        irq_domain_add_legacy(np, 64, 0, 0, &irq_domain_simple_ops, NULL);
        return 0;
 }
@@ -44,7 +44,9 @@ static int __init imx27_gpio_add_irq_domain(struct device_node *np,
 {
        static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS;
-        irq_domain_add_simple(np, gpio_irq_base);
+        gpio_irq_base -= 32;
+        irq_domain_add_legacy(np, 32, gpio_irq_base, 0, &irq_domain_simple_ops,
+                                NULL);
        return 0;
 }
diff --git a/arch/arm/mach-imx/imx51-dt.c b/arch/arm/mach-imx/imx51-dt.c
index 5cca573964f0..5f577fbda2c8 100644
--- a/arch/arm/mach-imx/imx51-dt.c
+++ b/arch/arm/mach-imx/imx51-dt.c
@@ -14,6 +14,7 @@
 #include <linux/irqdomain.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
+#include <linux/pinctrl/machine.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <mach/common.h>
@@ -81,6 +82,8 @@ static void __init imx51_dt_init(void)
        of_irq_init(imx51_irq_match);
+        pinctrl_provide_dummies();
        node = of_find_matching_node(NULL, imx51_iomuxc_of_match);
        if (node) {
                of_id = of_match_node(imx51_iomuxc_of_match, node);
diff --git a/arch/arm/mach-imx/imx53-dt.c b/arch/arm/mach-imx/imx53-dt.c
index 4172279b3900..574eca4b89a5 100644
--- a/arch/arm/mach-imx/imx53-dt.c
+++ b/arch/arm/mach-imx/imx53-dt.c
@@ -15,6 +15,7 @@
 #include <linux/irqdomain.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
+#include <linux/pinctrl/machine.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <mach/common.h>
@@ -88,6 +89,8 @@ static void __init imx53_dt_init(void)
        of_irq_init(imx53_irq_match);
+        pinctrl_provide_dummies();
        node = of_find_matching_node(NULL, imx53_iomuxc_of_match);
        if (node) {
                of_id = of_match_node(imx53_iomuxc_of_match, node);
diff --git a/arch/arm/mach-imx/mach-cpuimx35.c b/arch/arm/mach-imx/mach-cpuimx35.c
index 8ecc872b2547..c515f8ede1a1 100644
--- a/arch/arm/mach-imx/mach-cpuimx35.c
+++ b/arch/arm/mach-imx/mach-cpuimx35.c
@@ -194,7 +194,7 @@ static void __init eukrea_cpuimx35_timer_init(void)
        mx35_clocks_init();
 }
-struct sys_timer eukrea_cpuimx35_timer = {
+static struct sys_timer eukrea_cpuimx35_timer = {
        .init   = eukrea_cpuimx35_timer_init,
 };
diff --git a/arch/arm/mach-imx/mach-cpuimx51.c b/arch/arm/mach-imx/mach-cpuimx51.c
deleted file mode 100644
index 944025da8333..000000000000
--- a/arch/arm/mach-imx/mach-cpuimx51.c
+++ /dev/null
@@ -1,301 +0,0 @@
-/*
- *
- * Copyright (C) 2010 Eric Bénard <eric@eukrea.com>
- *
- * based on board-mx51_babbage.c which is
- * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/serial_8250.h>
-#include <linux/i2c.h>
-#include <linux/gpio.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <linux/interrupt.h>
-#include <mach/eukrea-baseboards.h>
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <mach/iomux-mx51.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include "devices-imx51.h"
-#define CPUIMX51_USBH1_STP      IMX_GPIO_NR(1, 27)
-#define CPUIMX51_QUARTA_GPIO    IMX_GPIO_NR(3, 28)
-#define CPUIMX51_QUARTB_GPIO    IMX_GPIO_NR(3, 25)
-#define CPUIMX51_QUARTC_GPIO    IMX_GPIO_NR(3, 26)
-#define CPUIMX51_QUARTD_GPIO    IMX_GPIO_NR(3, 27)
-#define CPUIMX51_QUART_XTAL     14745600
-#define CPUIMX51_QUART_REGSHIFT 17
-/* USB_CTRL_1 */
-#define MX51_USB_CTRL_1_OFFSET          0x10
-#define MX51_USB_CTRL_UH1_EXT_CLK_EN    (1 << 25)
-#define MX51_USB_PLLDIV_12_MHZ          0x00
-#define MX51_USB_PLL_DIV_19_2_MHZ       0x01
-#define MX51_USB_PLL_DIV_24_MHZ         0x02
-static struct plat_serial8250_port serial_platform_data[] = {
-        {
-                .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x400000),
-                .irq = IMX_GPIO_TO_IRQ(CPUIMX51_QUARTA_GPIO),
-                .irqflags = IRQF_TRIGGER_HIGH,
-                .uartclk = CPUIMX51_QUART_XTAL,
-                .regshift = CPUIMX51_QUART_REGSHIFT,
-                .iotype = UPIO_MEM,
-                .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
-        }, {
-                .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x800000),
-                .irq = IMX_GPIO_TO_IRQ(CPUIMX51_QUARTB_GPIO),
-                .irqflags = IRQF_TRIGGER_HIGH,
-                .uartclk = CPUIMX51_QUART_XTAL,
-                .regshift = CPUIMX51_QUART_REGSHIFT,
-                .iotype = UPIO_MEM,
-                .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
-        }, {
-                .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x1000000),
-                .irq = IMX_GPIO_TO_IRQ(CPUIMX51_QUARTC_GPIO),
-                .irqflags = IRQF_TRIGGER_HIGH,
-                .uartclk = CPUIMX51_QUART_XTAL,
-                .regshift = CPUIMX51_QUART_REGSHIFT,
-                .iotype = UPIO_MEM,
-                .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
-        }, {
-                .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x2000000),
-                .irq = IMX_GPIO_TO_IRQ(CPUIMX51_QUARTD_GPIO),
-                .irqflags = IRQF_TRIGGER_HIGH,
-                .uartclk = CPUIMX51_QUART_XTAL,
-                .regshift = CPUIMX51_QUART_REGSHIFT,
-                .iotype = UPIO_MEM,
-                .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
-        }, {
-        }
-};
-static struct platform_device serial_device = {
-        .name = "serial8250",
-        .id = 0,
-        .dev = {
-                .platform_data = serial_platform_data,
-        },
-};
-static struct platform_device *devices[] __initdata = {
-        &serial_device,
-};
-static iomux_v3_cfg_t eukrea_cpuimx51_pads[] = {
-        /* UART1 */
-        MX51_PAD_UART1_RXD__UART1_RXD,
-        MX51_PAD_UART1_TXD__UART1_TXD,
-        MX51_PAD_UART1_RTS__UART1_RTS,
-        MX51_PAD_UART1_CTS__UART1_CTS,
-        /* I2C2 */
-        MX51_PAD_GPIO1_2__I2C2_SCL,
-        MX51_PAD_GPIO1_3__I2C2_SDA,
-        MX51_PAD_NANDF_D10__GPIO3_30,
-        /* QUART IRQ */
-        MX51_PAD_NANDF_D15__GPIO3_25,
-        MX51_PAD_NANDF_D14__GPIO3_26,
-        MX51_PAD_NANDF_D13__GPIO3_27,
-        MX51_PAD_NANDF_D12__GPIO3_28,
-        /* USB HOST1 */
-        MX51_PAD_USBH1_CLK__USBH1_CLK,
-        MX51_PAD_USBH1_DIR__USBH1_DIR,
-        MX51_PAD_USBH1_NXT__USBH1_NXT,
-        MX51_PAD_USBH1_DATA0__USBH1_DATA0,
-        MX51_PAD_USBH1_DATA1__USBH1_DATA1,
-        MX51_PAD_USBH1_DATA2__USBH1_DATA2,
-        MX51_PAD_USBH1_DATA3__USBH1_DATA3,
-        MX51_PAD_USBH1_DATA4__USBH1_DATA4,
-        MX51_PAD_USBH1_DATA5__USBH1_DATA5,
-        MX51_PAD_USBH1_DATA6__USBH1_DATA6,
-        MX51_PAD_USBH1_DATA7__USBH1_DATA7,
-        MX51_PAD_USBH1_STP__USBH1_STP,
-};
-static const struct mxc_nand_platform_data
-                eukrea_cpuimx51_nand_board_info __initconst = {
-        .width          = 1,
-        .hw_ecc         = 1,
-        .flash_bbt      = 1,
-};
-static const struct imxuart_platform_data uart_pdata __initconst = {
-        .flags = IMXUART_HAVE_RTSCTS,
-};
-static const
-struct imxi2c_platform_data eukrea_cpuimx51_i2c_data __initconst = {
-        .bitrate = 100000,
-};
-static struct i2c_board_info eukrea_cpuimx51_i2c_devices[] = {
-        {
-                I2C_BOARD_INFO("pcf8563", 0x51),
-        },
-};
-/* This function is board specific as the bit mask for the plldiv will also
-be different for other Freescale SoCs, thus a common bitmask is not
-possible and cannot get place in /plat-mxc/ehci.c.*/
-static int initialize_otg_port(struct platform_device *pdev)
-{
-        u32 v;
-        void __iomem *usb_base;
-        void __iomem *usbother_base;
-        usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
-        if (!usb_base)
-                return -ENOMEM;
-        usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
-        /* Set the PHY clock to 19.2MHz */
-        v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
-        v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
-        v |= MX51_USB_PLL_DIV_19_2_MHZ;
-        __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
-        iounmap(usb_base);
-        mdelay(10);
-        return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY);
-}
-static int initialize_usbh1_port(struct platform_device *pdev)
-{
-        u32 v;
-        void __iomem *usb_base;
-        void __iomem *usbother_base;
-        usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
-        if (!usb_base)
-                return -ENOMEM;
-        usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
-        /* The clock for the USBH1 ULPI port will come externally from the PHY. */
-        v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
-        __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET);
-        iounmap(usb_base);
-        mdelay(10);
-        return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED |
-                        MXC_EHCI_ITC_NO_THRESHOLD);
-}
-static const struct mxc_usbh_platform_data dr_utmi_config __initconst = {
-        .init           = initialize_otg_port,
-        .portsc = MXC_EHCI_UTMI_16BIT,
-};
-static const struct fsl_usb2_platform_data usb_pdata __initconst = {
-        .operating_mode = FSL_USB2_DR_DEVICE,
-        .phy_mode       = FSL_USB2_PHY_UTMI_WIDE,
-};
-static const struct mxc_usbh_platform_data usbh1_config __initconst = {
-        .init           = initialize_usbh1_port,
-        .portsc = MXC_EHCI_MODE_ULPI,
-};
-static int otg_mode_host;
-static int __init eukrea_cpuimx51_otg_mode(char *options)
-{
-        if (!strcmp(options, "host"))
-                otg_mode_host = 1;
-        else if (!strcmp(options, "device"))
-                otg_mode_host = 0;
-        else
-                pr_info("otg_mode neither \"host\" nor \"device\". "
-                        "Defaulting to device\n");
-        return 0;
-}
-__setup("otg_mode=", eukrea_cpuimx51_otg_mode);
-/*
- * Board specific initialization.
- */
-static void __init eukrea_cpuimx51_init(void)
-{
-        imx51_soc_init();
-        mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51_pads,
-                                        ARRAY_SIZE(eukrea_cpuimx51_pads));
-        imx51_add_imx_uart(0, &uart_pdata);
-        imx51_add_mxc_nand(&eukrea_cpuimx51_nand_board_info);
-        gpio_request(CPUIMX51_QUARTA_GPIO, "quarta_irq");
-        gpio_direction_input(CPUIMX51_QUARTA_GPIO);
-        gpio_free(CPUIMX51_QUARTA_GPIO);
-        gpio_request(CPUIMX51_QUARTB_GPIO, "quartb_irq");
-        gpio_direction_input(CPUIMX51_QUARTB_GPIO);
-        gpio_free(CPUIMX51_QUARTB_GPIO);
-        gpio_request(CPUIMX51_QUARTC_GPIO, "quartc_irq");
-        gpio_direction_input(CPUIMX51_QUARTC_GPIO);
-        gpio_free(CPUIMX51_QUARTC_GPIO);
-        gpio_request(CPUIMX51_QUARTD_GPIO, "quartd_irq");
-        gpio_direction_input(CPUIMX51_QUARTD_GPIO);
-        gpio_free(CPUIMX51_QUARTD_GPIO);
-        imx51_add_fec(NULL);
-        platform_add_devices(devices, ARRAY_SIZE(devices));
-        imx51_add_imx_i2c(1, &eukrea_cpuimx51_i2c_data);
-        i2c_register_board_info(1, eukrea_cpuimx51_i2c_devices,
-                                ARRAY_SIZE(eukrea_cpuimx51_i2c_devices));
-        if (otg_mode_host)
-                imx51_add_mxc_ehci_otg(&dr_utmi_config);
-        else {
-                initialize_otg_port(NULL);
-                imx51_add_fsl_usb2_udc(&usb_pdata);
-        }
-        imx51_add_mxc_ehci_hs(1, &usbh1_config);
-#ifdef CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD
-        eukrea_mbimx51_baseboard_init();
-#endif
-}
-static void __init eukrea_cpuimx51_timer_init(void)
-{
-        mx51_clocks_init(32768, 24000000, 22579200, 0);
-}
-static struct sys_timer mxc_timer = {
-        .init   = eukrea_cpuimx51_timer_init,
-};
-MACHINE_START(EUKREA_CPUIMX51, "Eukrea CPUIMX51 Module")
-        /* Maintainer: Eric Bénard <eric@eukrea.com> */
-        .atag_offset = 0x100,
-        .map_io = mx51_map_io,
-        .init_early = imx51_init_early,
-        .init_irq = mx51_init_irq,
-        .handle_irq = imx51_handle_irq,
-        .timer = &mxc_timer,
-        .init_machine = eukrea_cpuimx51_init,
-        .restart        = mxc_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/mach-cpuimx51sd.c b/arch/arm/mach-imx/mach-cpuimx51sd.c
index 9fbe923c8b08..ce341a6874fc 100644
--- a/arch/arm/mach-imx/mach-cpuimx51sd.c
+++ b/arch/arm/mach-imx/mach-cpuimx51sd.c
@@ -41,11 +41,13 @@
 #define USBH1_RST               IMX_GPIO_NR(2, 28)
 #define ETH_RST                 IMX_GPIO_NR(2, 31)
-#define TSC2007_IRQGPIO         IMX_GPIO_NR(3, 12)
+#define TSC2007_IRQGPIO_REV2    IMX_GPIO_NR(3, 12)
+#define TSC2007_IRQGPIO_REV3    IMX_GPIO_NR(4, 0)
 #define CAN_IRQGPIO             IMX_GPIO_NR(1, 1)
 #define CAN_RST                 IMX_GPIO_NR(4, 15)
 #define CAN_NCS                 IMX_GPIO_NR(4, 24)
-#define CAN_RXOBF               IMX_GPIO_NR(1, 4)
+#define CAN_RXOBF_REV2          IMX_GPIO_NR(1, 4)
+#define CAN_RXOBF_REV3          IMX_GPIO_NR(3, 12)
 #define CAN_RX1BF               IMX_GPIO_NR(1, 6)
 #define CAN_TXORTS              IMX_GPIO_NR(1, 7)
 #define CAN_TX1RTS              IMX_GPIO_NR(1, 8)
@@ -90,6 +92,10 @@ static iomux_v3_cfg_t eukrea_cpuimx51sd_pads[] = {
        MX51_PAD_I2C1_CLK__GPIO4_16,
        MX51_PAD_I2C1_DAT__GPIO4_17,
+        /* I2C1 */
+        MX51_PAD_SD2_CMD__I2C1_SCL,
+        MX51_PAD_SD2_CLK__I2C1_SDA,
        /* CAN */
        MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
        MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
@@ -108,15 +114,27 @@ static iomux_v3_cfg_t eukrea_cpuimx51sd_pads[] = {
        NEW_PAD_CTRL(MX51_PAD_GPIO_NAND__GPIO_NAND, PAD_CTL_PUS_22K_UP |
                        PAD_CTL_PKE | PAD_CTL_SRE_FAST |
                        PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
+        NEW_PAD_CTRL(MX51_PAD_NANDF_D8__GPIO4_0, PAD_CTL_PUS_22K_UP |
+                        PAD_CTL_PKE | PAD_CTL_SRE_FAST |
+                        PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
 };
 static const struct imxuart_platform_data uart_pdata __initconst = {
        .flags = IMXUART_HAVE_RTSCTS,
 };
+static int tsc2007_get_pendown_state(void)
+{
+        if (mx51_revision() < IMX_CHIP_REVISION_3_0)
+                return !gpio_get_value(TSC2007_IRQGPIO_REV2);
+        else
+                return !gpio_get_value(TSC2007_IRQGPIO_REV3);
+}
 static struct tsc2007_platform_data tsc2007_info = {
        .model                  = 2007,
        .x_plate_ohms           = 180,
+        .get_pendown_state      = tsc2007_get_pendown_state,
 };
 static struct i2c_board_info eukrea_cpuimx51sd_i2c_devices[] = {
@@ -126,7 +144,6 @@ static struct i2c_board_info eukrea_cpuimx51sd_i2c_devices[] = {
                I2C_BOARD_INFO("tsc2007", 0x49),
                .type           = "tsc2007",
                .platform_data  = &tsc2007_info,
-                .irq            = IMX_GPIO_TO_IRQ(TSC2007_IRQGPIO),
        },
 };
@@ -255,10 +272,14 @@ static const struct spi_imx_master cpuimx51sd_ecspi1_pdata __initconst = {
        .num_chipselect = ARRAY_SIZE(cpuimx51sd_spi1_cs),
 };
-static struct platform_device *platform_devices[] __initdata = {
+static struct platform_device *rev2_platform_devices[] __initdata = {
        &hsi2c_gpio_device,
 };
+static const struct imxi2c_platform_data cpuimx51sd_i2c_data __initconst = {
+        .bitrate = 100000,
+};
 static void __init eukrea_cpuimx51sd_init(void)
 {
        imx51_soc_init();
@@ -272,6 +293,7 @@ static void __init eukrea_cpuimx51sd_init(void)
        imx51_add_imx_uart(0, &uart_pdata);
        imx51_add_mxc_nand(&eukrea_cpuimx51sd_nand_board_info);
+        imx51_add_imx2_wdt(0, NULL);
        gpio_request(ETH_RST, "eth_rst");
        gpio_set_value(ETH_RST, 1);
@@ -291,13 +313,25 @@ static void __init eukrea_cpuimx51sd_init(void)
        spi_register_board_info(cpuimx51sd_spi_device,
                                ARRAY_SIZE(cpuimx51sd_spi_device));
-        gpio_request(TSC2007_IRQGPIO, "tsc2007_irq");
+        if (mx51_revision() < IMX_CHIP_REVISION_3_0) {
-        gpio_direction_input(TSC2007_IRQGPIO);
+                eukrea_cpuimx51sd_i2c_devices[1].irq =
-        gpio_free(TSC2007_IRQGPIO);
+                        gpio_to_irq(TSC2007_IRQGPIO_REV2),
+                platform_add_devices(rev2_platform_devices,
+                        ARRAY_SIZE(rev2_platform_devices));
+                gpio_request(TSC2007_IRQGPIO_REV2, "tsc2007_irq");
+                gpio_direction_input(TSC2007_IRQGPIO_REV2);
+                gpio_free(TSC2007_IRQGPIO_REV2);
+        } else {
+                eukrea_cpuimx51sd_i2c_devices[1].irq =
+                        gpio_to_irq(TSC2007_IRQGPIO_REV3),
+                imx51_add_imx_i2c(0, &cpuimx51sd_i2c_data);
+                gpio_request(TSC2007_IRQGPIO_REV3, "tsc2007_irq");
+                gpio_direction_input(TSC2007_IRQGPIO_REV3);
+                gpio_free(TSC2007_IRQGPIO_REV3);
+        }
        i2c_register_board_info(0, eukrea_cpuimx51sd_i2c_devices,
                        ARRAY_SIZE(eukrea_cpuimx51sd_i2c_devices));
-        platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
        if (otg_mode_host)
                imx51_add_mxc_ehci_otg(&dr_utmi_config);
diff --git a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
index 76a97a598b9e..d1e04e676e33 100644
--- a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
+++ b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
@@ -106,6 +106,7 @@ static const struct mxc_usbh_platform_data usbh2_pdata __initconst = {
 static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
        .operating_mode = FSL_USB2_DR_DEVICE,
        .phy_mode       = FSL_USB2_PHY_UTMI,
+        .workaround     = FLS_USB2_WORKAROUND_ENGCM09152,
 };
 static int otg_mode_host;
@@ -135,6 +136,7 @@ static void __init eukrea_cpuimx25_init(void)
        imx25_add_mxc_nand(&eukrea_cpuimx25_nand_board_info);
        imx25_add_imxdi_rtc(NULL);
        imx25_add_fec(&mx25_fec_pdata);
+        imx25_add_imx2_wdt(NULL);
        i2c_register_board_info(0, eukrea_cpuimx25_i2c_devices,
                                ARRAY_SIZE(eukrea_cpuimx25_i2c_devices));
diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
index f7b074f496f0..748ba2e311b5 100644
--- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
+++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
@@ -38,6 +38,7 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
+#include <asm/system.h>
 #include <mach/common.h>
 #include <mach/iomux-mx27.h>
@@ -48,6 +49,14 @@
 #define OTG_PHY_CS_GPIO (GPIO_PORTF + 17)
 #define SDHC1_IRQ IRQ_GPIOB(25)
+#define MOTHERBOARD_BIT2        (GPIO_PORTD + 31)
+#define MOTHERBOARD_BIT1        (GPIO_PORTD + 30)
+#define MOTHERBOARD_BIT0        (GPIO_PORTD + 29)
+#define EXPBOARD_BIT2           (GPIO_PORTD + 25)
+#define EXPBOARD_BIT1           (GPIO_PORTD + 27)
+#define EXPBOARD_BIT0           (GPIO_PORTD + 28)
 static const int visstrim_m10_pins[] __initconst = {
        /* UART1 (console) */
        PE12_PF_UART1_TXD,
@@ -119,6 +128,23 @@ static const int visstrim_m10_pins[] __initconst = {
        PB19_PF_CSI_D7,
        PB20_PF_CSI_VSYNC,
        PB21_PF_CSI_HSYNC,
+        /* mother board version */
+        MOTHERBOARD_BIT2 | GPIO_GPIO | GPIO_IN | GPIO_PUEN,
+        MOTHERBOARD_BIT1 | GPIO_GPIO | GPIO_IN | GPIO_PUEN,
+        MOTHERBOARD_BIT0 | GPIO_GPIO | GPIO_IN | GPIO_PUEN,
+        /* expansion board version */
+        EXPBOARD_BIT2 | GPIO_GPIO | GPIO_IN | GPIO_PUEN,
+        EXPBOARD_BIT1 | GPIO_GPIO | GPIO_IN | GPIO_PUEN,
+        EXPBOARD_BIT0 | GPIO_GPIO | GPIO_IN | GPIO_PUEN,
+};
+static struct gpio visstrim_m10_version_gpios[] = {
+        { EXPBOARD_BIT0, GPIOF_IN, "exp-version-0" },
+        { EXPBOARD_BIT1, GPIOF_IN, "exp-version-1" },
+        { EXPBOARD_BIT2, GPIOF_IN, "exp-version-2" },
+        { MOTHERBOARD_BIT0, GPIOF_IN, "mother-version-0" },
+        { MOTHERBOARD_BIT1, GPIOF_IN, "mother-version-1" },
+        { MOTHERBOARD_BIT2, GPIOF_IN, "mother-version-2" },
 };
 /* Camera */
@@ -369,11 +395,40 @@ static const struct imx_ssi_platform_data visstrim_m10_ssi_pdata __initconst = {
        .flags                  = IMX_SSI_DMA | IMX_SSI_SYN,
 };
+static void __init visstrim_m10_revision(void)
+{
+        int exp_version = 0;
+        int mo_version = 0;
+        int ret;
+        ret = gpio_request_array(visstrim_m10_version_gpios,
+                                 ARRAY_SIZE(visstrim_m10_version_gpios));
+        if (ret) {
+                pr_err("Failed to request version gpios");
+                return;
+        }
+        /* Get expansion board version (negative logic) */
+        exp_version |= !gpio_get_value(EXPBOARD_BIT2) << 2;
+        exp_version |= !gpio_get_value(EXPBOARD_BIT1) << 1;
+        exp_version |= !gpio_get_value(EXPBOARD_BIT0);
+        /* Get mother board version (negative logic) */
+        mo_version |= !gpio_get_value(MOTHERBOARD_BIT2) << 2;
+        mo_version |= !gpio_get_value(MOTHERBOARD_BIT1) << 1;
+        mo_version |= !gpio_get_value(MOTHERBOARD_BIT0);
+        system_rev = 0x27000;
+        system_rev |= (mo_version << 4);
+        system_rev |= exp_version;
+}
 static void __init visstrim_m10_board_init(void)
 {
        int ret;
        imx27_soc_init();
+        visstrim_m10_revision();
        ret = mxc_gpio_setup_multiple_pins(visstrim_m10_pins,
                        ARRAY_SIZE(visstrim_m10_pins), "VISSTRIM_M10");
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index da6c1d9af768..3df360a52c17 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -19,6 +19,7 @@
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
+#include <linux/pinctrl/machine.h>
 #include <linux/phy.h>
 #include <linux/micrel_phy.h>
 #include <asm/smp_twd.h>
@@ -77,6 +78,12 @@ static int ksz9021rn_phy_fixup(struct phy_device *phydev)
 static void __init imx6q_init_machine(void)
 {
+        /*
+         * This should be removed when all imx6q boards have pinctrl
+         * states for devices defined in device tree.
+         */
+        pinctrl_provide_dummies();
        if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
                phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
                                           ksz9021rn_phy_fixup);
diff --git a/arch/arm/mach-imx/mach-mx1ads.c b/arch/arm/mach-imx/mach-mx1ads.c
index 97046088ff1a..7274e7928136 100644
--- a/arch/arm/mach-imx/mach-mx1ads.c
+++ b/arch/arm/mach-imx/mach-mx1ads.c
@@ -134,7 +134,7 @@ static void __init mx1ads_timer_init(void)
        mx1_clocks_init(32000);
 }
-struct sys_timer mx1ads_timer = {
+static struct sys_timer mx1ads_timer = {
        .init   = mx1ads_timer_init,
 };
diff --git a/arch/arm/mach-imx/mach-mx21ads.c b/arch/arm/mach-imx/mach-mx21ads.c
index e432d4acee1f..d14bbe949a4f 100644
--- a/arch/arm/mach-imx/mach-mx21ads.c
+++ b/arch/arm/mach-imx/mach-mx21ads.c
@@ -304,8 +304,7 @@ static void __init mx21ads_board_init(void)
        imx21_add_mxc_nand(&mx21ads_nand_board_info);
        platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
-        platform_device_register_full(
+        platform_device_register_full(&mx21ads_cs8900_devinfo);
-                        (struct platform_device_info *)&mx21ads_cs8900_devinfo);
 }
 static void __init mx21ads_timer_init(void)
diff --git a/arch/arm/mach-imx/mach-mx31lite.c b/arch/arm/mach-imx/mach-mx31lite.c
index 0abef5f13df5..686c60587980 100644
--- a/arch/arm/mach-imx/mach-mx31lite.c
+++ b/arch/arm/mach-imx/mach-mx31lite.c
@@ -283,7 +283,7 @@ static void __init mx31lite_timer_init(void)
        mx31_clocks_init(26000000);
 }
-struct sys_timer mx31lite_timer = {
+static struct sys_timer mx31lite_timer = {
        .init   = mx31lite_timer_init,
 };
diff --git a/arch/arm/mach-imx/mach-mx31moboard.c b/arch/arm/mach-imx/mach-mx31moboard.c
index f17a15f28316..1dfe3c7a7be1 100644
--- a/arch/arm/mach-imx/mach-mx31moboard.c
+++ b/arch/arm/mach-imx/mach-mx31moboard.c
@@ -580,7 +580,7 @@ static void __init mx31moboard_timer_init(void)
        mx31_clocks_init(26000000);
 }
-struct sys_timer mx31moboard_timer = {
+static struct sys_timer mx31moboard_timer = {
        .init   = mx31moboard_timer_init,
 };
diff --git a/arch/arm/mach-imx/mach-mx35_3ds.c b/arch/arm/mach-imx/mach-mx35_3ds.c
index 6ae51c6b95b7..86284bba46d3 100644
--- a/arch/arm/mach-imx/mach-mx35_3ds.c
+++ b/arch/arm/mach-imx/mach-mx35_3ds.c
@@ -34,6 +34,8 @@
 #include <linux/usb/otg.h>
 #include <linux/mtd/physmap.h>
+#include <linux/mfd/mc13892.h>
+#include <linux/regulator/machine.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -253,6 +255,8 @@ static iomux_v3_cfg_t mx35pdk_pads[] = {
        MX35_PAD_CSI_MCLK__IPU_CSI_MCLK,
        MX35_PAD_CSI_PIXCLK__IPU_CSI_PIXCLK,
        MX35_PAD_CSI_VSYNC__IPU_CSI_VSYNC,
+        /*PMIC IRQ*/
+        MX35_PAD_GPIO2_0__GPIO2_0,
 };
 /*
@@ -317,6 +321,193 @@ static struct platform_device mx35_3ds_ov2640 = {
        },
 };
+static struct regulator_consumer_supply sw1_consumers[] = {
+        {
+                .supply = "cpu_vcc",
+        }
+};
+static struct regulator_consumer_supply vcam_consumers[] = {
+        /* sgtl5000 */
+        REGULATOR_SUPPLY("VDDA", "0-000a"),
+};
+static struct regulator_consumer_supply vaudio_consumers[] = {
+        REGULATOR_SUPPLY("cmos_vio", "soc-camera-pdrv.0"),
+};
+static struct regulator_init_data sw1_init = {
+        .constraints = {
+                .name = "SW1",
+                .min_uV = 600000,
+                .max_uV = 1375000,
+                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+                .valid_modes_mask = 0,
+                .always_on = 1,
+                .boot_on = 1,
+        },
+        .num_consumer_supplies = ARRAY_SIZE(sw1_consumers),
+        .consumer_supplies = sw1_consumers,
+};
+static struct regulator_init_data sw2_init = {
+        .constraints = {
+                .name = "SW2",
+                .always_on = 1,
+                .boot_on = 1,
+        }
+};
+static struct regulator_init_data sw3_init = {
+        .constraints = {
+                .name = "SW3",
+                .always_on = 1,
+                .boot_on = 1,
+        }
+};
+static struct regulator_init_data sw4_init = {
+        .constraints = {
+                .name = "SW4",
+                .always_on = 1,
+                .boot_on = 1,
+        }
+};
+static struct regulator_init_data viohi_init = {
+        .constraints = {
+                .name = "VIOHI",
+                .boot_on = 1,
+        }
+};
+static struct regulator_init_data vusb_init = {
+        .constraints = {
+                .name = "VUSB",
+                .boot_on = 1,
+        }
+};
+static struct regulator_init_data vdig_init = {
+        .constraints = {
+                .name = "VDIG",
+                .boot_on = 1,
+        }
+};
+static struct regulator_init_data vpll_init = {
+        .constraints = {
+                .name = "VPLL",
+                .boot_on = 1,
+        }
+};
+static struct regulator_init_data vusb2_init = {
+        .constraints = {
+                .name = "VUSB2",
+                .boot_on = 1,
+        }
+};
+static struct regulator_init_data vvideo_init = {
+        .constraints = {
+                .name = "VVIDEO",
+                .boot_on = 1
+        }
+};
+static struct regulator_init_data vaudio_init = {
+        .constraints = {
+                .name = "VAUDIO",
+                .min_uV = 2300000,
+                .max_uV = 3000000,
+                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+                .boot_on = 1
+        },
+        .num_consumer_supplies = ARRAY_SIZE(vaudio_consumers),
+        .consumer_supplies = vaudio_consumers,
+};
+static struct regulator_init_data vcam_init = {
+        .constraints = {
+                .name = "VCAM",
+                .min_uV = 2500000,
+                .max_uV = 3000000,
+                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+                                        REGULATOR_CHANGE_MODE,
+                .valid_modes_mask = REGULATOR_MODE_FAST | REGULATOR_MODE_NORMAL,
+                .boot_on = 1
+        },
+        .num_consumer_supplies = ARRAY_SIZE(vcam_consumers),
+        .consumer_supplies = vcam_consumers,
+};
+static struct regulator_init_data vgen1_init = {
+        .constraints = {
+                .name = "VGEN1",
+        }
+};
+static struct regulator_init_data vgen2_init = {
+        .constraints = {
+                .name = "VGEN2",
+                .boot_on = 1,
+        }
+};
+static struct regulator_init_data vgen3_init = {
+        .constraints = {
+                .name = "VGEN3",
+        }
+};
+static struct mc13xxx_regulator_init_data mx35_3ds_regulators[] = {
+        { .id = MC13892_SW1, .init_data = &sw1_init },
+        { .id = MC13892_SW2, .init_data = &sw2_init },
+        { .id = MC13892_SW3, .init_data = &sw3_init },
+        { .id = MC13892_SW4, .init_data = &sw4_init },
+        { .id = MC13892_VIOHI, .init_data = &viohi_init },
+        { .id = MC13892_VPLL, .init_data = &vpll_init },
+        { .id = MC13892_VDIG, .init_data = &vdig_init },
+        { .id = MC13892_VUSB2, .init_data = &vusb2_init },
+        { .id = MC13892_VVIDEO, .init_data = &vvideo_init },
+        { .id = MC13892_VAUDIO, .init_data = &vaudio_init },
+        { .id = MC13892_VCAM, .init_data = &vcam_init },
+        { .id = MC13892_VGEN1, .init_data = &vgen1_init },
+        { .id = MC13892_VGEN2, .init_data = &vgen2_init },
+        { .id = MC13892_VGEN3, .init_data = &vgen3_init },
+        { .id = MC13892_VUSB, .init_data = &vusb_init },
+};
+static struct mc13xxx_platform_data mx35_3ds_mc13892_data = {
+        .flags = MC13XXX_USE_RTC | MC13XXX_USE_TOUCHSCREEN,
+        .regulators = {
+                .num_regulators = ARRAY_SIZE(mx35_3ds_regulators),
+                .regulators = mx35_3ds_regulators,
+        },
+};
+#define GPIO_PMIC_INT IMX_GPIO_NR(2, 0)
+static struct i2c_board_info mx35_3ds_i2c_mc13892 = {
+        I2C_BOARD_INFO("mc13892", 0x08),
+        .platform_data = &mx35_3ds_mc13892_data,
+        .irq = IMX_GPIO_TO_IRQ(GPIO_PMIC_INT),
+};
+static void __init imx35_3ds_init_mc13892(void)
+{
+        int ret = gpio_request_one(GPIO_PMIC_INT, GPIOF_DIR_IN, "pmic irq");
+        if (ret) {
+                pr_err("failed to get pmic irq: %d\n", ret);
+                return;
+        }
+        i2c_register_board_info(0, &mx35_3ds_i2c_mc13892, 1);
+}
 static int mx35_3ds_otg_init(struct platform_device *pdev)
 {
        return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERNAL_PHY);
@@ -412,6 +603,8 @@ static void __init mx35_3ds_init(void)
        imx35_fb_pdev = imx35_add_mx3_sdc_fb(&mx3fb_pdata);
        mx35_3ds_lcd.dev.parent = &imx35_fb_pdev->dev;
        platform_device_register(&mx35_3ds_lcd);
+        imx35_3ds_init_mc13892();
 }
 static void __init mx35pdk_timer_init(void)
@@ -419,7 +612,7 @@ static void __init mx35pdk_timer_init(void)
        mx35_clocks_init();
 }
-struct sys_timer mx35pdk_timer = {
+static struct sys_timer mx35pdk_timer = {
        .init   = mx35pdk_timer_init,
 };
diff --git a/arch/arm/mach-imx/mach-mx51_efikamx.c b/arch/arm/mach-imx/mach-mx51_efikamx.c
index 586e9f822124..86e96ef11f9d 100644
--- a/arch/arm/mach-imx/mach-mx51_efikamx.c
+++ b/arch/arm/mach-imx/mach-mx51_efikamx.c
@@ -284,8 +284,7 @@ static struct sys_timer mx51_efikamx_timer = {
        .init = mx51_efikamx_timer_init,
 };
-MACHINE_START(MX51_EFIKAMX, "Genesi EfikaMX nettop")
+MACHINE_START(MX51_EFIKAMX, "Genesi Efika MX (Smarttop)")
-        /* Maintainer: Amit Kucheria <amit.kucheria@linaro.org> */
        .atag_offset = 0x100,
        .map_io = mx51_map_io,
        .init_early = imx51_init_early,
diff --git a/arch/arm/mach-imx/mach-mx51_efikasb.c b/arch/arm/mach-imx/mach-mx51_efikasb.c
index 24aded9e109f..88f837a6cc76 100644
--- a/arch/arm/mach-imx/mach-mx51_efikasb.c
+++ b/arch/arm/mach-imx/mach-mx51_efikasb.c
@@ -280,7 +280,7 @@ static struct sys_timer mx51_efikasb_timer = {
        .init   = mx51_efikasb_timer_init,
 };
-MACHINE_START(MX51_EFIKASB, "Genesi Efika Smartbook")
+MACHINE_START(MX51_EFIKASB, "Genesi Efika MX (Smartbook)")
        .atag_offset = 0x100,
        .map_io = mx51_map_io,
        .init_early = imx51_init_early,
diff --git a/arch/arm/mach-imx/mach-pcm037.c b/arch/arm/mach-imx/mach-pcm037.c
index 5fddf94cc969..10c9795934a3 100644
--- a/arch/arm/mach-imx/mach-pcm037.c
+++ b/arch/arm/mach-imx/mach-pcm037.c
@@ -683,7 +683,7 @@ static void __init pcm037_timer_init(void)
        mx31_clocks_init(26000000);
 }
-struct sys_timer pcm037_timer = {
+static struct sys_timer pcm037_timer = {
        .init   = pcm037_timer_init,
 };
diff --git a/arch/arm/mach-imx/mach-pcm043.c b/arch/arm/mach-imx/mach-pcm043.c
index 237474fcca23..73585f55cca0 100644
--- a/arch/arm/mach-imx/mach-pcm043.c
+++ b/arch/arm/mach-imx/mach-pcm043.c
@@ -399,7 +399,7 @@ static void __init pcm043_timer_init(void)
        mx35_clocks_init();
 }
-struct sys_timer pcm043_timer = {
+static struct sys_timer pcm043_timer = {
        .init   = pcm043_timer_init,
 };
diff --git a/arch/arm/mach-imx/mach-vpr200.c b/arch/arm/mach-imx/mach-vpr200.c
index 033257e553ef..add8c69c6c1a 100644
--- a/arch/arm/mach-imx/mach-vpr200.c
+++ b/arch/arm/mach-imx/mach-vpr200.c
@@ -310,7 +310,7 @@ static void __init vpr200_timer_init(void)
        mx35_clocks_init();
 }
-struct sys_timer vpr200_timer = {
+static struct sys_timer vpr200_timer = {
        .init   = vpr200_timer_init,
 };
diff --git a/arch/arm/mach-imx/mm-imx1.c b/arch/arm/mach-imx/mm-imx1.c
index 2bded591d5c2..fcafd3dafb8c 100644
--- a/arch/arm/mach-imx/mm-imx1.c
+++ b/arch/arm/mach-imx/mm-imx1.c
@@ -18,6 +18,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/io.h>
+#include <linux/pinctrl/machine.h>
 #include <asm/mach/map.h>
@@ -58,4 +59,5 @@ void __init imx1_soc_init(void)
                                                MX1_GPIO_INT_PORTC, 0);
        mxc_register_gpio("imx1-gpio", 3, MX1_GPIO4_BASE_ADDR, SZ_256,
                                                MX1_GPIO_INT_PORTD, 0);
+        pinctrl_provide_dummies();
 }
diff --git a/arch/arm/mach-imx/mm-imx21.c b/arch/arm/mach-imx/mm-imx21.c
index 14d540edfd1e..5f43905e5290 100644
--- a/arch/arm/mach-imx/mm-imx21.c
+++ b/arch/arm/mach-imx/mm-imx21.c
@@ -20,6 +20,7 @@
 #include <linux/mm.h>
 #include <linux/init.h>
+#include <linux/pinctrl/machine.h>
 #include <mach/hardware.h>
 #include <mach/common.h>
 #include <mach/devices-common.h>
@@ -88,6 +89,7 @@ void __init imx21_soc_init(void)
        mxc_register_gpio("imx21-gpio", 4, MX21_GPIO5_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
        mxc_register_gpio("imx21-gpio", 5, MX21_GPIO6_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
+        pinctrl_provide_dummies();
        imx_add_imx_dma();
        platform_device_register_simple("imx21-audmux", 0, imx21_audmux_res,
                                        ARRAY_SIZE(imx21_audmux_res));
diff --git a/arch/arm/mach-imx/mm-imx25.c b/arch/arm/mach-imx/mm-imx25.c
index 153b457acdc0..6ff37140a4f8 100644
--- a/arch/arm/mach-imx/mm-imx25.c
+++ b/arch/arm/mach-imx/mm-imx25.c
@@ -19,6 +19,7 @@
 #include <linux/mm.h>
 #include <linux/init.h>
 #include <linux/err.h>
+#include <linux/pinctrl/machine.h>
 #include <asm/pgtable.h>
 #include <asm/mach/map.h>
@@ -95,6 +96,7 @@ void __init imx25_soc_init(void)
        mxc_register_gpio("imx31-gpio", 2, MX25_GPIO3_BASE_ADDR, SZ_16K, MX25_INT_GPIO3, 0);
        mxc_register_gpio("imx31-gpio", 3, MX25_GPIO4_BASE_ADDR, SZ_16K, MX25_INT_GPIO4, 0);
+        pinctrl_provide_dummies();
        /* i.mx25 has the i.mx35 type sdma */
        imx_add_imx_sdma("imx35-sdma", MX25_SDMA_BASE_ADDR, MX25_INT_SDMA, &imx25_sdma_pdata);
        /* i.mx25 has the i.mx31 type audmux */
diff --git a/arch/arm/mach-imx/mm-imx27.c b/arch/arm/mach-imx/mm-imx27.c
index 8cb3f5e3e569..25662558e018 100644
--- a/arch/arm/mach-imx/mm-imx27.c
+++ b/arch/arm/mach-imx/mm-imx27.c
@@ -20,6 +20,7 @@
 #include <linux/mm.h>
 #include <linux/init.h>
+#include <linux/pinctrl/machine.h>
 #include <mach/hardware.h>
 #include <mach/common.h>
 #include <mach/devices-common.h>
@@ -89,6 +90,7 @@ void __init imx27_soc_init(void)
        mxc_register_gpio("imx21-gpio", 4, MX27_GPIO5_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0);
        mxc_register_gpio("imx21-gpio", 5, MX27_GPIO6_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0);
+        pinctrl_provide_dummies();
        imx_add_imx_dma();
        /* imx27 has the imx21 type audmux */
        platform_device_register_simple("imx21-audmux", 0, imx27_audmux_res,
diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c
index 74127389e7ab..9128d15b1eb7 100644
--- a/arch/arm/mach-imx/mm-imx3.c
+++ b/arch/arm/mach-imx/mm-imx3.c
@@ -19,6 +19,7 @@
 #include <linux/mm.h>
 #include <linux/init.h>
 #include <linux/err.h>
+#include <linux/pinctrl/machine.h>
 #include <asm/pgtable.h>
 #include <asm/system_misc.h>
@@ -267,6 +268,7 @@ void __init imx35_soc_init(void)
        mxc_register_gpio("imx31-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0);
        mxc_register_gpio("imx31-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0);
+        pinctrl_provide_dummies();
        if (to_version == 1) {
                strncpy(imx35_sdma_pdata.fw_name, "sdma-imx35-to1.bin",
                        strlen(imx35_sdma_pdata.fw_name));
diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c
index 05250aed61fb..ba91e6b31cf4 100644
--- a/arch/arm/mach-imx/mm-imx5.c
+++ b/arch/arm/mach-imx/mm-imx5.c
@@ -14,6 +14,7 @@
 #include <linux/mm.h>
 #include <linux/init.h>
 #include <linux/clk.h>
+#include <linux/pinctrl/machine.h>
 #include <asm/system_misc.h>
 #include <asm/mach/map.h>
@@ -35,7 +36,7 @@ static void imx5_idle(void)
        }
        clk_enable(gpc_dvfs_clk);
        mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
-        if (tzic_enable_wake() != 0)
+        if (!tzic_enable_wake())
                cpu_do_idle();
        clk_disable(gpc_dvfs_clk);
 }
@@ -223,6 +224,7 @@ void __init imx53_soc_init(void)
        mxc_register_gpio("imx31-gpio", 5, MX53_GPIO6_BASE_ADDR, SZ_16K, MX53_INT_GPIO6_LOW, MX53_INT_GPIO6_HIGH);
        mxc_register_gpio("imx31-gpio", 6, MX53_GPIO7_BASE_ADDR, SZ_16K, MX53_INT_GPIO7_LOW, MX53_INT_GPIO7_HIGH);
+        pinctrl_provide_dummies();
        /* i.mx53 has the i.mx35 type sdma */
        imx_add_imx_sdma("imx35-sdma", MX53_SDMA_BASE_ADDR, MX53_INT_SDMA, &imx53_sdma_pdata);
diff --git a/arch/arm/mach-integrator/impd1.c b/arch/arm/mach-integrator/impd1.c
index 3e538da6cb1f..e428f3ab15c7 100644
--- a/arch/arm/mach-integrator/impd1.c
+++ b/arch/arm/mach-integrator/impd1.c
@@ -398,24 +398,16 @@ static int impd1_probe(struct lm_device *dev)
                struct impd1_device *idev = impd1_devs + i;
                struct amba_device *d;
                unsigned long pc_base;
+                char devname[32];
                pc_base = dev->resource.start + idev->offset;
+                snprintf(devname, 32, "lm%x:%5.5lx", dev->id, idev->offset >> 12);
-                d = amba_device_alloc(NULL, pc_base, SZ_4K);
+                d = amba_ahb_device_add(&dev->dev, devname, pc_base, SZ_4K,
-                if (!d)
+                                        dev->irq, dev->irq,
+                                        idev->platform_data, idev->id);
+                if (IS_ERR(d)) {
+                        dev_err(&dev->dev, "unable to register device: %ld\n", PTR_ERR(d));
                        continue;
-                dev_set_name(&d->dev, "lm%x:%5.5lx", dev->id, idev->offset >> 12);
-                d->dev.parent   = &dev->dev;
-                d->irq[0]       = dev->irq;
-                d->irq[1]       = dev->irq;
-                d->periphid     = idev->id;
-                d->dev.platform_data = idev->platform_data;
-                ret = amba_device_add(d, &dev->resource);
-                if (ret) {
-                        dev_err(&d->dev, "unable to register device: %d\n", ret);
-                        amba_device_put(d);
                }
        }
diff --git a/arch/arm/mach-integrator/include/mach/entry-macro.S b/arch/arm/mach-integrator/include/mach/entry-macro.S
deleted file mode 100644
index 5cc7b85ad9df..000000000000
--- a/arch/arm/mach-integrator/include/mach/entry-macro.S
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * arch/arm/mach-integrator/include/mach/entry-macro.S
- *
- * Low-level IRQ helper macros for Integrator platforms
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <mach/hardware.h>
-#include <mach/platform.h>
-#include <mach/irqs.h>
-                .macro  get_irqnr_preamble, base, tmp
-                .endm
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-/* FIXME: should not be using soo many LDRs here */
-                ldr     \base, =IO_ADDRESS(INTEGRATOR_IC_BASE)
-                mov     \irqnr, #IRQ_PIC_START
-                ldr     \irqstat, [\base, #IRQ_STATUS]          @ get masked status
-                ldr     \base, =IO_ADDRESS(INTEGRATOR_HDR_BASE)
-                teq     \irqstat, #0
-                ldreq   \irqstat, [\base, #(INTEGRATOR_HDR_IC_OFFSET+IRQ_STATUS)]
-                moveq   \irqnr, #IRQ_CIC_START
-1001:           tst     \irqstat, #15
-                bne     1002f
-                add     \irqnr, \irqnr, #4
-                movs    \irqstat, \irqstat, lsr #4
-                bne     1001b
-1002:           tst     \irqstat, #1
-                bne     1003f
-                add     \irqnr, \irqnr, #1
-                movs    \irqstat, \irqstat, lsr #1
-                bne     1002b
-1003:           /* EQ will be set if no irqs pending */
-                .endm
diff --git a/arch/arm/mach-integrator/include/mach/irqs.h b/arch/arm/mach-integrator/include/mach/irqs.h
index a19a1a2fcf6b..7371018455d2 100644
--- a/arch/arm/mach-integrator/include/mach/irqs.h
+++ b/arch/arm/mach-integrator/include/mach/irqs.h
@@ -22,37 +22,37 @@
 /* 
 *  Interrupt numbers
 */
-#define IRQ_PIC_START                   0
+#define IRQ_PIC_START                   1
-#define IRQ_SOFTINT                     0
+#define IRQ_SOFTINT                     1
-#define IRQ_UARTINT0                    1
+#define IRQ_UARTINT0                    2
-#define IRQ_UARTINT1                    2
+#define IRQ_UARTINT1                    3
-#define IRQ_KMIINT0                     3
+#define IRQ_KMIINT0                     4
-#define IRQ_KMIINT1                     4
+#define IRQ_KMIINT1                     5
-#define IRQ_TIMERINT0                   5
+#define IRQ_TIMERINT0                   6
-#define IRQ_TIMERINT1                   6
+#define IRQ_TIMERINT1                   7
-#define IRQ_TIMERINT2                   7
+#define IRQ_TIMERINT2                   8
-#define IRQ_RTCINT                      8
+#define IRQ_RTCINT                      9
-#define IRQ_AP_EXPINT0                  9
+#define IRQ_AP_EXPINT0                  10
-#define IRQ_AP_EXPINT1                  10
+#define IRQ_AP_EXPINT1                  11
-#define IRQ_AP_EXPINT2                  11
+#define IRQ_AP_EXPINT2                  12
-#define IRQ_AP_EXPINT3                  12
+#define IRQ_AP_EXPINT3                  13
-#define IRQ_AP_PCIINT0                  13
+#define IRQ_AP_PCIINT0                  14
-#define IRQ_AP_PCIINT1                  14
+#define IRQ_AP_PCIINT1                  15
-#define IRQ_AP_PCIINT2                  15
+#define IRQ_AP_PCIINT2                  16
-#define IRQ_AP_PCIINT3                  16
+#define IRQ_AP_PCIINT3                  17
-#define IRQ_AP_V3INT                    17
+#define IRQ_AP_V3INT                    18
-#define IRQ_AP_CPINT0                   18
+#define IRQ_AP_CPINT0                   19
-#define IRQ_AP_CPINT1                   19
+#define IRQ_AP_CPINT1                   20
-#define IRQ_AP_LBUSTIMEOUT              20
+#define IRQ_AP_LBUSTIMEOUT              21
-#define IRQ_AP_APCINT                   21
+#define IRQ_AP_APCINT                   22
-#define IRQ_CP_CLCDCINT                 22
+#define IRQ_CP_CLCDCINT                 23
-#define IRQ_CP_MMCIINT0                 23
+#define IRQ_CP_MMCIINT0                 24
-#define IRQ_CP_MMCIINT1                 24
+#define IRQ_CP_MMCIINT1                 25
-#define IRQ_CP_AACIINT                  25
+#define IRQ_CP_AACIINT                  26
-#define IRQ_CP_CPPLDINT                 26
+#define IRQ_CP_CPPLDINT                 27
-#define IRQ_CP_ETHINT                   27
+#define IRQ_CP_ETHINT                   28
-#define IRQ_CP_TSPENINT                 28
+#define IRQ_CP_TSPENINT                 29
-#define IRQ_PIC_END                     31
+#define IRQ_PIC_END                     29
 #define IRQ_CIC_START                   32
 #define IRQ_CM_SOFTINT                  32
@@ -80,4 +80,3 @@
 #define NR_IRQS_INTEGRATOR_AP           34
 #define NR_IRQS_INTEGRATOR_CP           47
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index 871f148ffd72..c857501c5783 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -162,12 +162,6 @@ static void __init ap_map_io(void)
 #define INTEGRATOR_SC_VALID_INT 0x003fffff
-static struct fpga_irq_data sc_irq_data = {
-        .base           = VA_IC_BASE,
-        .irq_start      = 0,
-        .chip.name      = "SC",
-};
 static void __init ap_init_irq(void)
 {
        /* Disable all interrupts initially. */
@@ -178,7 +172,8 @@ static void __init ap_init_irq(void)
        writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
        writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
-        fpga_irq_init(-1, INTEGRATOR_SC_VALID_INT, &sc_irq_data);
+        fpga_irq_init(VA_IC_BASE, "SC", IRQ_PIC_START,
+                -1, INTEGRATOR_SC_VALID_INT, NULL);
 }
 #ifdef CONFIG_PM
@@ -478,6 +473,7 @@ MACHINE_START(INTEGRATOR, "ARM-Integrator")
        .nr_irqs        = NR_IRQS_INTEGRATOR_AP,
        .init_early     = integrator_init_early,
        .init_irq       = ap_init_irq,
+        .handle_irq     = fpga_handle_irq,
        .timer          = &ap_timer,
        .init_machine   = ap_init,
        .restart        = integrator_restart,
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index 48a115a91d9d..a56c53608939 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -143,30 +143,14 @@ static void __init intcp_map_io(void)
        iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc));
 }
-static struct fpga_irq_data cic_irq_data = {
-        .base           = INTCP_VA_CIC_BASE,
-        .irq_start      = IRQ_CIC_START,
-        .chip.name      = "CIC",
-};
-static struct fpga_irq_data pic_irq_data = {
-        .base           = INTCP_VA_PIC_BASE,
-        .irq_start      = IRQ_PIC_START,
-        .chip.name      = "PIC",
-};
-static struct fpga_irq_data sic_irq_data = {
-        .base           = INTCP_VA_SIC_BASE,
-        .irq_start      = IRQ_SIC_START,
-        .chip.name      = "SIC",
-};
 static void __init intcp_init_irq(void)
 {
-        u32 pic_mask, sic_mask;
+        u32 pic_mask, cic_mask, sic_mask;
+        /* These masks are for the HW IRQ registers */
        pic_mask = ~((~0u) << (11 - IRQ_PIC_START));
        pic_mask |= (~((~0u) << (29 - 22))) << 22;
+        cic_mask = ~((~0u) << (1 + IRQ_CIC_END - IRQ_CIC_START));
        sic_mask = ~((~0u) << (1 + IRQ_SIC_END - IRQ_SIC_START));
        /*
@@ -179,12 +163,14 @@ static void __init intcp_init_irq(void)
        writel(sic_mask, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
        writel(sic_mask, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR);
-        fpga_irq_init(-1, pic_mask, &pic_irq_data);
+        fpga_irq_init(INTCP_VA_PIC_BASE, "PIC", IRQ_PIC_START,
+                      -1, pic_mask, NULL);
-        fpga_irq_init(-1, ~((~0u) << (1 + IRQ_CIC_END - IRQ_CIC_START)),
+        fpga_irq_init(INTCP_VA_CIC_BASE, "CIC", IRQ_CIC_START,
-                &cic_irq_data);
+                      -1, cic_mask, NULL);
-        fpga_irq_init(IRQ_CP_CPPLDINT, sic_mask, &sic_irq_data);
+        fpga_irq_init(INTCP_VA_SIC_BASE, "SIC", IRQ_SIC_START,
+                      IRQ_CP_CPPLDINT, sic_mask, NULL);
 }
 /*
@@ -467,6 +453,7 @@ MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
        .nr_irqs        = NR_IRQS_INTEGRATOR_CP,
        .init_early     = intcp_init_early,
        .init_irq       = intcp_init_irq,
+        .handle_irq     = fpga_handle_irq,
        .timer          = &cp_timer,
        .init_machine   = intcp_init,
        .restart        = integrator_restart,
diff --git a/arch/arm/mach-integrator/pci.c b/arch/arm/mach-integrator/pci.c
index f1ca9c122861..6c1667e728f5 100644
--- a/arch/arm/mach-integrator/pci.c
+++ b/arch/arm/mach-integrator/pci.c
@@ -70,21 +70,10 @@
 */
 static u8 __init integrator_swizzle(struct pci_dev *dev, u8 *pinp)
 {
-        int pin = *pinp;
+        if (*pinp == 0)
+                *pinp = 1;
-        if (pin == 0)
+        return pci_common_swizzle(dev, pinp);
-                pin = 1;
-        while (dev->bus->self) {
-                pin = pci_swizzle_interrupt_pin(dev, pin);
-                /*
-                 * move up the chain of bridges, swizzling as we go.
-                 */
-                dev = dev->bus->self;
-        }
-        *pinp = pin;
-        return PCI_SLOT(dev->devfn);
 }
 static int irq_tab[4] __initdata = {
@@ -109,7 +98,7 @@ static struct hw_pci integrator_pci __initdata = {
        .map_irq                = integrator_map_irq,
        .setup                  = pci_v3_setup,
        .nr_controllers         = 1,
-        .scan                   = pci_v3_scan_bus,
+        .ops                    = &pci_v3_ops,
        .preinit                = pci_v3_preinit,
        .postinit               = pci_v3_postinit,
 };
diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c
index 67e6f9a9d1a0..b866880e82ac 100644
--- a/arch/arm/mach-integrator/pci_v3.c
+++ b/arch/arm/mach-integrator/pci_v3.c
@@ -340,7 +340,7 @@ static int v3_write_config(struct pci_bus *bus, unsigned int devfn, int where,
        return PCIBIOS_SUCCESSFUL;
 }
-static struct pci_ops pci_v3_ops = {
+struct pci_ops pci_v3_ops = {
        .read   = v3_read_config,
        .write  = v3_write_config,
 };
@@ -488,12 +488,6 @@ int __init pci_v3_setup(int nr, struct pci_sys_data *sys)
        return ret;
 }
-struct pci_bus * __init pci_v3_scan_bus(int nr, struct pci_sys_data *sys)
-{
-        return pci_scan_root_bus(NULL, sys->busnr, &pci_v3_ops, sys,
-                                 &sys->resources);
-}
 /*
 * V3_LB_BASE? - local bus address
 * V3_LB_MAP?  - pci bus address
diff --git a/arch/arm/mach-iop13xx/iq81340mc.c b/arch/arm/mach-iop13xx/iq81340mc.c
index 5c96b73e6964..e3f3e7daa79e 100644
--- a/arch/arm/mach-iop13xx/iq81340mc.c
+++ b/arch/arm/mach-iop13xx/iq81340mc.c
@@ -54,7 +54,6 @@ iq81340mc_pcix_map_irq(const struct pci_dev *dev, u8 idsel, u8 pin)
 }
 static struct hw_pci iq81340mc_pci __initdata = {
-        .swizzle        = pci_std_swizzle,
        .nr_controllers = 0,
        .setup          = iop13xx_pci_setup,
        .map_irq        = iq81340mc_pcix_map_irq,
diff --git a/arch/arm/mach-iop13xx/iq81340sc.c b/arch/arm/mach-iop13xx/iq81340sc.c
index aa4dd750135a..060cddde2fd4 100644
--- a/arch/arm/mach-iop13xx/iq81340sc.c
+++ b/arch/arm/mach-iop13xx/iq81340sc.c
@@ -56,7 +56,6 @@ iq81340sc_atux_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
 }
 static struct hw_pci iq81340sc_pci __initdata = {
-        .swizzle        = pci_std_swizzle,
        .nr_controllers = 0,
        .setup          = iop13xx_pci_setup,
        .scan           = iop13xx_scan_bus,
diff --git a/arch/arm/mach-iop32x/em7210.c b/arch/arm/mach-iop32x/em7210.c
index 24069e03fdc1..9f369f09c29d 100644
--- a/arch/arm/mach-iop32x/em7210.c
+++ b/arch/arm/mach-iop32x/em7210.c
@@ -103,11 +103,10 @@ em7210_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 }
 static struct hw_pci em7210_pci __initdata = {
-        .swizzle        = pci_std_swizzle,
        .nr_controllers = 1,
+        .ops            = &iop3xx_ops,
        .setup          = iop3xx_pci_setup,
        .preinit        = iop3xx_pci_preinit,
-        .scan           = iop3xx_pci_scan_bus,
        .map_irq        = em7210_pci_map_irq,
 };
diff --git a/arch/arm/mach-iop32x/glantank.c b/arch/arm/mach-iop32x/glantank.c
index 204e1d1cd766..c15a100ba779 100644
--- a/arch/arm/mach-iop32x/glantank.c
+++ b/arch/arm/mach-iop32x/glantank.c
@@ -96,11 +96,10 @@ glantank_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 }
 static struct hw_pci glantank_pci __initdata = {
-        .swizzle        = pci_std_swizzle,
        .nr_controllers = 1,
+        .ops            = &iop3xx_ops,
        .setup          = iop3xx_pci_setup,
        .preinit        = iop3xx_pci_preinit,
-        .scan           = iop3xx_pci_scan_bus,
        .map_irq        = glantank_pci_map_irq,
 };
diff --git a/arch/arm/mach-iop32x/iq31244.c b/arch/arm/mach-iop32x/iq31244.c
index 3eb642af1cdc..ddd1c7ecfe57 100644
--- a/arch/arm/mach-iop32x/iq31244.c
+++ b/arch/arm/mach-iop32x/iq31244.c
@@ -130,11 +130,10 @@ ep80219_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 }
 static struct hw_pci ep80219_pci __initdata = {
-        .swizzle        = pci_std_swizzle,
        .nr_controllers = 1,
+        .ops            = &iop3xx_ops,
        .setup          = iop3xx_pci_setup,
        .preinit        = iop3xx_pci_preinit,
-        .scan           = iop3xx_pci_scan_bus,
        .map_irq        = ep80219_pci_map_irq,
 };
@@ -166,11 +165,10 @@ iq31244_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 }
 static struct hw_pci iq31244_pci __initdata = {
-        .swizzle        = pci_std_swizzle,
        .nr_controllers = 1,
+        .ops            = &iop3xx_ops,
        .setup          = iop3xx_pci_setup,
        .preinit        = iop3xx_pci_preinit,
-        .scan           = iop3xx_pci_scan_bus,
        .map_irq        = iq31244_pci_map_irq,
 };
diff --git a/arch/arm/mach-iop32x/iq80321.c b/arch/arm/mach-iop32x/iq80321.c
index 2ec724b58a2c..bf155e6a3b45 100644
--- a/arch/arm/mach-iop32x/iq80321.c
+++ b/arch/arm/mach-iop32x/iq80321.c
@@ -101,11 +101,10 @@ iq80321_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 }
 static struct hw_pci iq80321_pci __initdata = {
-        .swizzle        = pci_std_swizzle,
        .nr_controllers = 1,
+        .ops            = &iop3xx_ops,
        .setup          = iop3xx_pci_setup,
        .preinit        = iop3xx_pci_preinit_cond,
-        .scan           = iop3xx_pci_scan_bus,
        .map_irq        = iq80321_pci_map_irq,
 };
diff --git a/arch/arm/mach-iop32x/n2100.c b/arch/arm/mach-iop32x/n2100.c
index 6b6d55912444..5a7ae91e8849 100644
--- a/arch/arm/mach-iop32x/n2100.c
+++ b/arch/arm/mach-iop32x/n2100.c
@@ -114,11 +114,10 @@ n2100_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 }
 static struct hw_pci n2100_pci __initdata = {
-        .swizzle        = pci_std_swizzle,
        .nr_controllers = 1,
+        .ops            = &iop3xx_ops,
        .setup          = iop3xx_pci_setup,
        .preinit        = iop3xx_pci_preinit,
-        .scan           = iop3xx_pci_scan_bus,
        .map_irq        = n2100_pci_map_irq,
 };
diff --git a/arch/arm/mach-iop33x/iq80331.c b/arch/arm/mach-iop33x/iq80331.c
index abce934f3816..e74a7debe793 100644
--- a/arch/arm/mach-iop33x/iq80331.c
+++ b/arch/arm/mach-iop33x/iq80331.c
@@ -84,11 +84,10 @@ iq80331_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 }
 static struct hw_pci iq80331_pci __initdata = {
-        .swizzle        = pci_std_swizzle,
        .nr_controllers = 1,
+        .ops            = &iop3xx_ops,
        .setup          = iop3xx_pci_setup,
        .preinit        = iop3xx_pci_preinit_cond,
-        .scan           = iop3xx_pci_scan_bus,
        .map_irq        = iq80331_pci_map_irq,
 };
diff --git a/arch/arm/mach-iop33x/iq80332.c b/arch/arm/mach-iop33x/iq80332.c
index 7513559e25bb..e2f5beece6e8 100644
--- a/arch/arm/mach-iop33x/iq80332.c
+++ b/arch/arm/mach-iop33x/iq80332.c
@@ -84,11 +84,10 @@ iq80332_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 }
 static struct hw_pci iq80332_pci __initdata = {
-        .swizzle        = pci_std_swizzle,
        .nr_controllers = 1,
+        .ops            = &iop3xx_ops,
        .setup          = iop3xx_pci_setup,
        .preinit        = iop3xx_pci_preinit_cond,
-        .scan           = iop3xx_pci_scan_bus,
        .map_irq        = iq80332_pci_map_irq,
 };
diff --git a/arch/arm/mach-ixp2000/Kconfig b/arch/arm/mach-ixp2000/Kconfig
deleted file mode 100644
index 08d2707f6ca8..000000000000
--- a/arch/arm/mach-ixp2000/Kconfig
+++ /dev/null
@@ -1,72 +0,0 @@
-if ARCH_IXP2000
-config ARCH_SUPPORTS_BIG_ENDIAN
-        bool
-        default y
-menu "Intel IXP2400/2800 Implementation Options"
-comment "IXP2400/2800 Platforms"
-config ARCH_ENP2611
-        bool "Support Radisys ENP-2611"
-        help
-          Say 'Y' here if you want your kernel to support the Radisys
-          ENP2611 PCI network processing card. For more information on
-          this card, see <file:Documentation/arm/IXP2000>.
-config ARCH_IXDP2400
-        bool "Support Intel IXDP2400"
-        help
-          Say 'Y' here if you want your kernel to support the Intel
-          IXDP2400 reference platform. For more information on
-          this platform, see <file:Documentation/arm/IXP2000>.
-config ARCH_IXDP2800
-        bool "Support Intel IXDP2800"
-        help
-          Say 'Y' here if you want your kernel to support the Intel
-          IXDP2800 reference platform. For more information on
-          this platform, see <file:Documentation/arm/IXP2000>.
-config ARCH_IXDP2X00
-        bool
-        depends on ARCH_IXDP2400 || ARCH_IXDP2800
-        default y       
-config ARCH_IXDP2401
-        bool "Support Intel IXDP2401"
-        help
-          Say 'Y' here if you want your kernel to support the Intel
-          IXDP2401 reference platform. For more information on
-          this platform, see <file:Documentation/arm/IXP2000>.
-config ARCH_IXDP2801
-        bool "Support Intel IXDP2801 and IXDP28x5"
-        help
-          Say 'Y' here if you want your kernel to support the Intel
-          IXDP2801/2805/2855 reference platforms. For more information on
-          this platform, see <file:Documentation/arm/IXP2000>.
-config MACH_IXDP28X5
-        bool
-        depends on ARCH_IXDP2801
-        default y
-config ARCH_IXDP2X01
-        bool
-        depends on ARCH_IXDP2401 || ARCH_IXDP2801
-        default y       
-config IXP2000_SUPPORT_BROKEN_PCI_IO
-        bool "Support broken PCI I/O on older IXP2000s"
-        default y
-        help
-          Say 'N' here if you only intend to run your kernel on an
-          IXP2000 B0 or later model and do not need the PCI I/O
-          byteswap workaround.  Say 'Y' otherwise.
-endmenu
-endif
diff --git a/arch/arm/mach-ixp2000/Makefile b/arch/arm/mach-ixp2000/Makefile
deleted file mode 100644
index 1e6139d42a92..000000000000
--- a/arch/arm/mach-ixp2000/Makefile
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# Makefile for the linux kernel.
-#
-obj-y                   := core.o pci.o
-obj-m                   :=
-obj-n                   :=
-obj-                    :=
-obj-$(CONFIG_ARCH_ENP2611)      += enp2611.o
-obj-$(CONFIG_ARCH_IXDP2400)     += ixdp2400.o
-obj-$(CONFIG_ARCH_IXDP2800)     += ixdp2800.o
-obj-$(CONFIG_ARCH_IXDP2X00)     += ixdp2x00.o
-obj-$(CONFIG_ARCH_IXDP2X01)     += ixdp2x01.o
diff --git a/arch/arm/mach-ixp2000/Makefile.boot b/arch/arm/mach-ixp2000/Makefile.boot
deleted file mode 100644
index 9c7af91d93da..000000000000
--- a/arch/arm/mach-ixp2000/Makefile.boot
+++ /dev/null
@@ -1,3 +0,0 @@
-   zreladdr-y   += 0x00008000
-params_phys-y   := 0x00000100
diff --git a/arch/arm/mach-ixp2000/core.c b/arch/arm/mach-ixp2000/core.c
deleted file mode 100644
index f214cdff01cb..000000000000
--- a/arch/arm/mach-ixp2000/core.c
+++ /dev/null
@@ -1,520 +0,0 @@
-/*
- * arch/arm/mach-ixp2000/core.c
- *
- * Common routines used by all IXP2400/2800 based platforms.
- *
- * Author: Deepak Saxena <dsaxena@plexity.net>
- *
- * Copyright 2004 (C) MontaVista Software, Inc. 
- *
- * Based on work Copyright (C) 2002-2003 Intel Corporation
- * 
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any 
- * warranty of any kind, whether express or implied.
- */
-#include <linux/gpio.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/spinlock.h>
-#include <linux/sched.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/serial.h>
-#include <linux/tty.h>
-#include <linux/bitops.h>
-#include <linux/serial_8250.h>
-#include <linux/mm.h>
-#include <linux/export.h>
-#include <asm/types.h>
-#include <asm/setup.h>
-#include <asm/memory.h>
-#include <mach/hardware.h>
-#include <asm/irq.h>
-#include <asm/tlbflush.h>
-#include <asm/pgtable.h>
-#include <asm/mach/map.h>
-#include <asm/mach/time.h>
-#include <asm/mach/irq.h>
-#include <mach/gpio-ixp2000.h>
-static DEFINE_SPINLOCK(ixp2000_slowport_lock);
-static unsigned long ixp2000_slowport_irq_flags;
-/*************************************************************************
- * Slowport access routines
- *************************************************************************/
-void ixp2000_acquire_slowport(struct slowport_cfg *new_cfg, struct slowport_cfg *old_cfg)
-{
-        spin_lock_irqsave(&ixp2000_slowport_lock, ixp2000_slowport_irq_flags);
-        old_cfg->CCR = *IXP2000_SLOWPORT_CCR;
-        old_cfg->WTC = *IXP2000_SLOWPORT_WTC2;
-        old_cfg->RTC = *IXP2000_SLOWPORT_RTC2;
-        old_cfg->PCR = *IXP2000_SLOWPORT_PCR;
-        old_cfg->ADC = *IXP2000_SLOWPORT_ADC;
-        ixp2000_reg_write(IXP2000_SLOWPORT_CCR, new_cfg->CCR);
-        ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, new_cfg->WTC);
-        ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, new_cfg->RTC);
-        ixp2000_reg_write(IXP2000_SLOWPORT_PCR, new_cfg->PCR);
-        ixp2000_reg_wrb(IXP2000_SLOWPORT_ADC, new_cfg->ADC);
-}
-void ixp2000_release_slowport(struct slowport_cfg *old_cfg)
-{
-        ixp2000_reg_write(IXP2000_SLOWPORT_CCR, old_cfg->CCR);
-        ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, old_cfg->WTC);
-        ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, old_cfg->RTC);
-        ixp2000_reg_write(IXP2000_SLOWPORT_PCR, old_cfg->PCR);
-        ixp2000_reg_wrb(IXP2000_SLOWPORT_ADC, old_cfg->ADC);
-        spin_unlock_irqrestore(&ixp2000_slowport_lock, 
-                                        ixp2000_slowport_irq_flags);
-}
-/*************************************************************************
- * Chip specific mappings shared by all IXP2000 systems
- *************************************************************************/
-static struct map_desc ixp2000_io_desc[] __initdata = {
-        {
-                .virtual        = IXP2000_CAP_VIRT_BASE,
-                .pfn            = __phys_to_pfn(IXP2000_CAP_PHYS_BASE),
-                .length         = IXP2000_CAP_SIZE,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = IXP2000_INTCTL_VIRT_BASE,
-                .pfn            = __phys_to_pfn(IXP2000_INTCTL_PHYS_BASE),
-                .length         = IXP2000_INTCTL_SIZE,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = IXP2000_PCI_CREG_VIRT_BASE,
-                .pfn            = __phys_to_pfn(IXP2000_PCI_CREG_PHYS_BASE),
-                .length         = IXP2000_PCI_CREG_SIZE,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = IXP2000_PCI_CSR_VIRT_BASE,
-                .pfn            = __phys_to_pfn(IXP2000_PCI_CSR_PHYS_BASE),
-                .length         = IXP2000_PCI_CSR_SIZE,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = IXP2000_MSF_VIRT_BASE,
-                .pfn            = __phys_to_pfn(IXP2000_MSF_PHYS_BASE),
-                .length         = IXP2000_MSF_SIZE,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = IXP2000_SCRATCH_RING_VIRT_BASE,
-                .pfn            = __phys_to_pfn(IXP2000_SCRATCH_RING_PHYS_BASE),
-                .length         = IXP2000_SCRATCH_RING_SIZE,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = IXP2000_SRAM0_VIRT_BASE,
-                .pfn            = __phys_to_pfn(IXP2000_SRAM0_PHYS_BASE),
-                .length         = IXP2000_SRAM0_SIZE,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = IXP2000_PCI_IO_VIRT_BASE,
-                .pfn            = __phys_to_pfn(IXP2000_PCI_IO_PHYS_BASE),
-                .length         = IXP2000_PCI_IO_SIZE,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = IXP2000_PCI_CFG0_VIRT_BASE,
-                .pfn            = __phys_to_pfn(IXP2000_PCI_CFG0_PHYS_BASE),
-                .length         = IXP2000_PCI_CFG0_SIZE,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = IXP2000_PCI_CFG1_VIRT_BASE,
-                .pfn            = __phys_to_pfn(IXP2000_PCI_CFG1_PHYS_BASE),
-                .length         = IXP2000_PCI_CFG1_SIZE,
-                .type           = MT_DEVICE,
-        }
-};
-void __init ixp2000_map_io(void)
-{
-        iotable_init(ixp2000_io_desc, ARRAY_SIZE(ixp2000_io_desc));
-        /* Set slowport to 8-bit mode.  */
-        ixp2000_reg_wrb(IXP2000_SLOWPORT_FRM, 1);
-}
-/*************************************************************************
- * Serial port support for IXP2000
- *************************************************************************/
-static struct plat_serial8250_port ixp2000_serial_port[] = {
-        {
-                .mapbase        = IXP2000_UART_PHYS_BASE,
-                .membase        = (char *)(IXP2000_UART_VIRT_BASE + 3),
-                .irq            = IRQ_IXP2000_UART,
-                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
-                .iotype         = UPIO_MEM,
-                .regshift       = 2,
-                .uartclk        = 50000000,
-        },
-        { },
-};
-static struct resource ixp2000_uart_resource = {
-        .start          = IXP2000_UART_PHYS_BASE,
-        .end            = IXP2000_UART_PHYS_BASE + 0x1f,
-        .flags          = IORESOURCE_MEM,
-};
-static struct platform_device ixp2000_serial_device = {
-        .name           = "serial8250",
-        .id             = PLAT8250_DEV_PLATFORM,
-        .dev            = {
-                .platform_data          = ixp2000_serial_port,
-        },
-        .num_resources  = 1,
-        .resource       = &ixp2000_uart_resource,
-};
-void __init ixp2000_uart_init(void)
-{
-        platform_device_register(&ixp2000_serial_device);
-}
-/*************************************************************************
- * Timer-tick functions for IXP2000
- *************************************************************************/
-static unsigned ticks_per_jiffy;
-static unsigned ticks_per_usec;
-static unsigned next_jiffy_time;
-static volatile unsigned long *missing_jiffy_timer_csr;
-unsigned long ixp2000_gettimeoffset (void)
-{
-        unsigned long offset;
-        offset = next_jiffy_time - *missing_jiffy_timer_csr;
-        return offset / ticks_per_usec;
-}
-static irqreturn_t ixp2000_timer_interrupt(int irq, void *dev_id)
-{
-        /* clear timer 1 */
-        ixp2000_reg_wrb(IXP2000_T1_CLR, 1);
-        while ((signed long)(next_jiffy_time - *missing_jiffy_timer_csr)
-                                                        >= ticks_per_jiffy) {
-                timer_tick();
-                next_jiffy_time -= ticks_per_jiffy;
-        }
-        return IRQ_HANDLED;
-}
-static struct irqaction ixp2000_timer_irq = {
-        .name           = "IXP2000 Timer Tick",
-        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-        .handler        = ixp2000_timer_interrupt,
-};
-void __init ixp2000_init_time(unsigned long tick_rate)
-{
-        ticks_per_jiffy = (tick_rate + HZ/2) / HZ;
-        ticks_per_usec = tick_rate / 1000000;
-        /*
-         * We use timer 1 as our timer interrupt.
-         */
-        ixp2000_reg_write(IXP2000_T1_CLR, 0);
-        ixp2000_reg_write(IXP2000_T1_CLD, ticks_per_jiffy - 1);
-        ixp2000_reg_write(IXP2000_T1_CTL, (1 << 7));
-        /*
-         * We use a second timer as a monotonic counter for tracking
-         * missed jiffies.  The IXP2000 has four timers, but if we're
-         * on an A-step IXP2800, timer 2 and 3 don't work, so on those
-         * chips we use timer 4.  Timer 4 is the only timer that can
-         * be used for the watchdog, so we use timer 2 if we're on a
-         * non-buggy chip.
-         */
-        if ((*IXP2000_PRODUCT_ID & 0x001ffef0) == 0x00000000) {
-                printk(KERN_INFO "Enabling IXP2800 erratum #25 workaround\n");
-                ixp2000_reg_write(IXP2000_T4_CLR, 0);
-                ixp2000_reg_write(IXP2000_T4_CLD, -1);
-                ixp2000_reg_wrb(IXP2000_T4_CTL, (1 << 7));
-                missing_jiffy_timer_csr = IXP2000_T4_CSR;
-        } else {
-                ixp2000_reg_write(IXP2000_T2_CLR, 0);
-                ixp2000_reg_write(IXP2000_T2_CLD, -1);
-                ixp2000_reg_wrb(IXP2000_T2_CTL, (1 << 7));
-                missing_jiffy_timer_csr = IXP2000_T2_CSR;
-        }
-        next_jiffy_time = 0xffffffff;
-        /* register for interrupt */
-        setup_irq(IRQ_IXP2000_TIMER1, &ixp2000_timer_irq);
-}
-/*************************************************************************
- * GPIO helpers
- *************************************************************************/
-static unsigned long GPIO_IRQ_falling_edge;
-static unsigned long GPIO_IRQ_rising_edge;
-static unsigned long GPIO_IRQ_level_low;
-static unsigned long GPIO_IRQ_level_high;
-static void update_gpio_int_csrs(void)
-{
-        ixp2000_reg_write(IXP2000_GPIO_FEDR, GPIO_IRQ_falling_edge);
-        ixp2000_reg_write(IXP2000_GPIO_REDR, GPIO_IRQ_rising_edge);
-        ixp2000_reg_write(IXP2000_GPIO_LSLR, GPIO_IRQ_level_low);
-        ixp2000_reg_wrb(IXP2000_GPIO_LSHR, GPIO_IRQ_level_high);
-}
-void gpio_line_config(int line, int direction)
-{
-        unsigned long flags;
-        local_irq_save(flags);
-        if (direction == GPIO_OUT) {
-                /* if it's an output, it ain't an interrupt anymore */
-                GPIO_IRQ_falling_edge &= ~(1 << line);
-                GPIO_IRQ_rising_edge &= ~(1 << line);
-                GPIO_IRQ_level_low &= ~(1 << line);
-                GPIO_IRQ_level_high &= ~(1 << line);
-                update_gpio_int_csrs();
-                ixp2000_reg_wrb(IXP2000_GPIO_PDSR, 1 << line);
-        } else if (direction == GPIO_IN) {
-                ixp2000_reg_wrb(IXP2000_GPIO_PDCR, 1 << line);
-        }
-        local_irq_restore(flags);
-}
-EXPORT_SYMBOL(gpio_line_config);
-/*************************************************************************
- * IRQ handling IXP2000
- *************************************************************************/
-static void ixp2000_GPIO_irq_handler(unsigned int irq, struct irq_desc *desc)
-{                               
-        int i;
-        unsigned long status = *IXP2000_GPIO_INST;
-                   
-        for (i = 0; i <= 7; i++) {
-                if (status & (1<<i)) {
-                        generic_handle_irq(i + IRQ_IXP2000_GPIO0);
-                }
-        }
-}
-static int ixp2000_GPIO_irq_type(struct irq_data *d, unsigned int type)
-{
-        int line = d->irq - IRQ_IXP2000_GPIO0;
-        /*
-         * First, configure this GPIO line as an input.
-         */
-        ixp2000_reg_write(IXP2000_GPIO_PDCR, 1 << line);
-        /*
-         * Then, set the proper trigger type.
-         */
-        if (type & IRQ_TYPE_EDGE_FALLING)
-                GPIO_IRQ_falling_edge |= 1 << line;
-        else
-                GPIO_IRQ_falling_edge &= ~(1 << line);
-        if (type & IRQ_TYPE_EDGE_RISING)
-                GPIO_IRQ_rising_edge |= 1 << line;
-        else
-                GPIO_IRQ_rising_edge &= ~(1 << line);
-        if (type & IRQ_TYPE_LEVEL_LOW)
-                GPIO_IRQ_level_low |= 1 << line;
-        else
-                GPIO_IRQ_level_low &= ~(1 << line);
-        if (type & IRQ_TYPE_LEVEL_HIGH)
-                GPIO_IRQ_level_high |= 1 << line;
-        else
-                GPIO_IRQ_level_high &= ~(1 << line);
-        update_gpio_int_csrs();
-        return 0;
-}
-static void ixp2000_GPIO_irq_mask_ack(struct irq_data *d)
-{
-        unsigned int irq = d->irq;
-        ixp2000_reg_write(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0)));
-        ixp2000_reg_write(IXP2000_GPIO_EDSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
-        ixp2000_reg_write(IXP2000_GPIO_LDSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
-        ixp2000_reg_wrb(IXP2000_GPIO_INST, (1 << (irq - IRQ_IXP2000_GPIO0)));
-}
-static void ixp2000_GPIO_irq_mask(struct irq_data *d)
-{
-        unsigned int irq = d->irq;
-        ixp2000_reg_wrb(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0)));
-}
-static void ixp2000_GPIO_irq_unmask(struct irq_data *d)
-{
-        unsigned int irq = d->irq;
-        ixp2000_reg_write(IXP2000_GPIO_INSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
-}
-static struct irq_chip ixp2000_GPIO_irq_chip = {
-        .irq_ack        = ixp2000_GPIO_irq_mask_ack,
-        .irq_mask       = ixp2000_GPIO_irq_mask,
-        .irq_unmask     = ixp2000_GPIO_irq_unmask,
-        .irq_set_type   = ixp2000_GPIO_irq_type,
-};
-static void ixp2000_pci_irq_mask(struct irq_data *d)
-{
-        unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE;
-        if (d->irq == IRQ_IXP2000_PCIA)
-                ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 26)));
-        else if (d->irq == IRQ_IXP2000_PCIB)
-                ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 27)));
-}
-static void ixp2000_pci_irq_unmask(struct irq_data *d)
-{
-        unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE;
-        if (d->irq == IRQ_IXP2000_PCIA)
-                ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp | (1 << 26)));
-        else if (d->irq == IRQ_IXP2000_PCIB)
-                ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp | (1 << 27)));
-}
-/*
- * Error interrupts. These are used extensively by the microengine drivers
- */
-static void ixp2000_err_irq_handler(unsigned int irq, struct irq_desc *desc)
-{
-        int i;
-        unsigned long status = *IXP2000_IRQ_ERR_STATUS;
-        for(i = 31; i >= 0; i--) {
-                if(status & (1 << i)) {
-                        generic_handle_irq(IRQ_IXP2000_DRAM0_MIN_ERR + i);
-                }
-        }
-}
-static void ixp2000_err_irq_mask(struct irq_data *d)
-{
-        ixp2000_reg_write(IXP2000_IRQ_ERR_ENABLE_CLR,
-                        (1 << (d->irq - IRQ_IXP2000_DRAM0_MIN_ERR)));
-}
-static void ixp2000_err_irq_unmask(struct irq_data *d)
-{
-        ixp2000_reg_write(IXP2000_IRQ_ERR_ENABLE_SET,
-                        (1 << (d->irq - IRQ_IXP2000_DRAM0_MIN_ERR)));
-}
-static struct irq_chip ixp2000_err_irq_chip = {
-        .irq_ack        = ixp2000_err_irq_mask,
-        .irq_mask       = ixp2000_err_irq_mask,
-        .irq_unmask     = ixp2000_err_irq_unmask
-};
-static struct irq_chip ixp2000_pci_irq_chip = {
-        .irq_ack        = ixp2000_pci_irq_mask,
-        .irq_mask       = ixp2000_pci_irq_mask,
-        .irq_unmask     = ixp2000_pci_irq_unmask
-};
-static void ixp2000_irq_mask(struct irq_data *d)
-{
-        ixp2000_reg_wrb(IXP2000_IRQ_ENABLE_CLR, (1 << d->irq));
-}
-static void ixp2000_irq_unmask(struct irq_data *d)
-{
-        ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << d->irq));
-}
-static struct irq_chip ixp2000_irq_chip = {
-        .irq_ack        = ixp2000_irq_mask,
-        .irq_mask       = ixp2000_irq_mask,
-        .irq_unmask     = ixp2000_irq_unmask
-};
-void __init ixp2000_init_irq(void)
-{
-        int irq;
-        /*
-         * Mask all sources
-         */
-        ixp2000_reg_write(IXP2000_IRQ_ENABLE_CLR, 0xffffffff);
-        ixp2000_reg_write(IXP2000_FIQ_ENABLE_CLR, 0xffffffff);
-        /* clear all GPIO edge/level detects */
-        ixp2000_reg_write(IXP2000_GPIO_REDR, 0);
-        ixp2000_reg_write(IXP2000_GPIO_FEDR, 0);
-        ixp2000_reg_write(IXP2000_GPIO_LSHR, 0);
-        ixp2000_reg_write(IXP2000_GPIO_LSLR, 0);
-        ixp2000_reg_write(IXP2000_GPIO_INCR, -1);
-        /* clear PCI interrupt sources */
-        ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, 0);
-        /*
-         * Certain bits in the IRQ status register of the 
-         * IXP2000 are reserved. Instead of trying to map
-         * things non 1:1 from bit position to IRQ number,
-         * we mark the reserved IRQs as invalid. This makes
-         * our mask/unmask code much simpler.
-         */
-        for (irq = IRQ_IXP2000_SOFT_INT; irq <= IRQ_IXP2000_THDB3; irq++) {
-                if ((1 << irq) & IXP2000_VALID_IRQ_MASK) {
-                        irq_set_chip_and_handler(irq, &ixp2000_irq_chip,
-                                                 handle_level_irq);
-                        set_irq_flags(irq, IRQF_VALID);
-                } else set_irq_flags(irq, 0);
-        }
-        for (irq = IRQ_IXP2000_DRAM0_MIN_ERR; irq <= IRQ_IXP2000_SP_INT; irq++) {
-                if((1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)) &
-                                IXP2000_VALID_ERR_IRQ_MASK) {
-                        irq_set_chip_and_handler(irq, &ixp2000_err_irq_chip,
-                                                 handle_level_irq);
-                        set_irq_flags(irq, IRQF_VALID);
-                }
-                else
-                        set_irq_flags(irq, 0);
-        }
-        irq_set_chained_handler(IRQ_IXP2000_ERRSUM, ixp2000_err_irq_handler);
-        for (irq = IRQ_IXP2000_GPIO0; irq <= IRQ_IXP2000_GPIO7; irq++) {
-                irq_set_chip_and_handler(irq, &ixp2000_GPIO_irq_chip,
-                                         handle_level_irq);
-                set_irq_flags(irq, IRQF_VALID);
-        }
-        irq_set_chained_handler(IRQ_IXP2000_GPIO, ixp2000_GPIO_irq_handler);
-        /*
-         * Enable PCI irqs.  The actual PCI[AB] decoding is done in
-         * entry-macro.S, so we don't need a chained handler for the
-         * PCI interrupt source.
-         */
-        ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << IRQ_IXP2000_PCI));
-        for (irq = IRQ_IXP2000_PCIA; irq <= IRQ_IXP2000_PCIB; irq++) {
-                irq_set_chip_and_handler(irq, &ixp2000_pci_irq_chip,
-                                         handle_level_irq);
-                set_irq_flags(irq, IRQF_VALID);
-        }
-}
-void ixp2000_restart(char mode, const char *cmd)
-{
-        ixp2000_reg_wrb(IXP2000_RESET0, RSTALL);
-}
diff --git a/arch/arm/mach-ixp2000/enp2611.c b/arch/arm/mach-ixp2000/enp2611.c
deleted file mode 100644
index 4867f408617c..000000000000
--- a/arch/arm/mach-ixp2000/enp2611.c
+++ /dev/null
@@ -1,265 +0,0 @@
-/*
- * arch/arm/mach-ixp2000/enp2611.c
- *
- * Radisys ENP-2611 support.
- *
- * Created 2004 by Lennert Buytenhek from the ixdp2x01 code.  The
- * original version carries the following notices:
- *
- * Original Author: Andrzej Mialkowski <andrzej.mialkowski@intel.com>
- * Maintainer: Deepak Saxena <dsaxena@plexity.net>
- *
- * Copyright (C) 2002-2003 Intel Corp.
- * Copyright (C) 2003-2004 MontaVista Software, Inc.
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/sched.h>
-#include <linux/interrupt.h>
-#include <linux/bitops.h>
-#include <linux/pci.h>
-#include <linux/ioport.h>
-#include <linux/delay.h>
-#include <linux/serial.h>
-#include <linux/tty.h>
-#include <linux/serial_core.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <asm/irq.h>
-#include <asm/pgtable.h>
-#include <asm/page.h>
-#include <mach/hardware.h>
-#include <asm/mach-types.h>
-#include <asm/mach/pci.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-#include <asm/mach/time.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/flash.h>
-/*************************************************************************
- * ENP-2611 timer tick configuration
- *************************************************************************/
-static void __init enp2611_timer_init(void)
-{
-        ixp2000_init_time(50 * 1000 * 1000);
-}
-static struct sys_timer enp2611_timer = {
-        .init           = enp2611_timer_init,
-        .offset         = ixp2000_gettimeoffset,
-};
-/*************************************************************************
- * ENP-2611 I/O
- *************************************************************************/
-static struct map_desc enp2611_io_desc[] __initdata = {
-        {
-                .virtual        = ENP2611_CALEB_VIRT_BASE,
-                .pfn            = __phys_to_pfn(ENP2611_CALEB_PHYS_BASE),
-                .length         = ENP2611_CALEB_SIZE,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = ENP2611_PM3386_0_VIRT_BASE,
-                .pfn            = __phys_to_pfn(ENP2611_PM3386_0_PHYS_BASE),
-                .length         = ENP2611_PM3386_0_SIZE,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = ENP2611_PM3386_1_VIRT_BASE,
-                .pfn            = __phys_to_pfn(ENP2611_PM3386_1_PHYS_BASE),
-                .length         = ENP2611_PM3386_1_SIZE,
-                .type           = MT_DEVICE,
-        }
-};
-void __init enp2611_map_io(void)
-{
-        ixp2000_map_io();
-        iotable_init(enp2611_io_desc, ARRAY_SIZE(enp2611_io_desc));
-}
-/*************************************************************************
- * ENP-2611 PCI
- *************************************************************************/
-static int enp2611_pci_setup(int nr, struct pci_sys_data *sys)
-{
-        sys->mem_offset = 0xe0000000;
-        ixp2000_pci_setup(nr, sys);
-        return 1;
-}
-static void __init enp2611_pci_preinit(void)
-{
-        ixp2000_reg_write(IXP2000_PCI_ADDR_EXT, 0x00100000);
-        ixp2000_pci_preinit();
-        pcibios_setup("firmware");
-}
-static inline int enp2611_pci_valid_device(struct pci_bus *bus,
-                                                unsigned int devfn)
-{
-        /* The 82559 ethernet controller appears at both PCI:1:0:0 and
-         * PCI:1:2:0, so let's pretend the second one isn't there.
-         */
-        if (bus->number == 0x01 && devfn == 0x10)
-                return 0;
-        return 1;
-}
-static int enp2611_pci_read_config(struct pci_bus *bus, unsigned int devfn,
-                                        int where, int size, u32 *value)
-{
-        if (enp2611_pci_valid_device(bus, devfn))
-                return ixp2000_pci_read_config(bus, devfn, where, size, value);
-        return PCIBIOS_DEVICE_NOT_FOUND;
-}
-static int enp2611_pci_write_config(struct pci_bus *bus, unsigned int devfn,
-                                        int where, int size, u32 value)
-{
-        if (enp2611_pci_valid_device(bus, devfn))
-                return ixp2000_pci_write_config(bus, devfn, where, size, value);
-        return PCIBIOS_DEVICE_NOT_FOUND;
-}
-static struct pci_ops enp2611_pci_ops = {
-        .read   = enp2611_pci_read_config,
-        .write  = enp2611_pci_write_config
-};
-static struct pci_bus * __init enp2611_pci_scan_bus(int nr,
-                                                struct pci_sys_data *sys)
-{
-        return pci_scan_root_bus(NULL, sys->busnr, &enp2611_pci_ops, sys,
-                                 &sys->resources);
-}
-static int __init enp2611_pci_map_irq(const struct pci_dev *dev, u8 slot,
-        u8 pin)
-{
-        int irq;
-        if (dev->bus->number == 0 && PCI_SLOT(dev->devfn) == 0) {
-                /* IXP2400. */
-                irq = IRQ_IXP2000_PCIA;
-        } else if (dev->bus->number == 0 && PCI_SLOT(dev->devfn) == 1) {
-                /* 21555 non-transparent bridge.  */
-                irq = IRQ_IXP2000_PCIB;
-        } else if (dev->bus->number == 0 && PCI_SLOT(dev->devfn) == 4) {
-                /* PCI2050B transparent bridge.  */
-                irq = -1;
-        } else if (dev->bus->number == 1 && PCI_SLOT(dev->devfn) == 0) {
-                /* 82559 ethernet.  */
-                irq = IRQ_IXP2000_PCIA;
-        } else if (dev->bus->number == 1 && PCI_SLOT(dev->devfn) == 1) {
-                /* SPI-3 option board.  */
-                irq = IRQ_IXP2000_PCIB;
-        } else {
-                printk(KERN_ERR "enp2611_pci_map_irq() called for unknown "
-                                "device PCI:%d:%d:%d\n", dev->bus->number,
-                                PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
-                irq = -1;
-        }
-        return irq;
-}
-struct hw_pci enp2611_pci __initdata = {
-        .nr_controllers = 1,
-        .setup          = enp2611_pci_setup,
-        .preinit        = enp2611_pci_preinit,
-        .scan           = enp2611_pci_scan_bus,
-        .map_irq        = enp2611_pci_map_irq,
-};
-int __init enp2611_pci_init(void)
-{
-        if (machine_is_enp2611())
-                pci_common_init(&enp2611_pci);
-        return 0;
-}
-subsys_initcall(enp2611_pci_init);
-/*************************************************************************
- * ENP-2611 Machine Initialization
- *************************************************************************/
-static struct flash_platform_data enp2611_flash_platform_data = {
-        .map_name       = "cfi_probe",
-        .width          = 1,
-};
-static struct ixp2000_flash_data enp2611_flash_data = {
-        .platform_data  = &enp2611_flash_platform_data,
-        .nr_banks       = 1
-};
-static struct resource enp2611_flash_resource = {
-        .start          = 0xc4000000,
-        .end            = 0xc4000000 + 0x00ffffff,
-        .flags          = IORESOURCE_MEM,
-};
-static struct platform_device enp2611_flash = {
-        .name           = "IXP2000-Flash",
-        .id             = 0,
-        .dev            = {
-                .platform_data = &enp2611_flash_data,
-        },
-        .num_resources  = 1,
-        .resource       = &enp2611_flash_resource,
-};
-static struct ixp2000_i2c_pins enp2611_i2c_gpio_pins = {
-        .sda_pin        = ENP2611_GPIO_SDA,
-        .scl_pin        = ENP2611_GPIO_SCL,
-};
-static struct platform_device enp2611_i2c_controller = {
-        .name           = "IXP2000-I2C",
-        .id             = 0,
-        .dev            = {
-                .platform_data = &enp2611_i2c_gpio_pins
-        },
-        .num_resources  = 0
-};
-static struct platform_device *enp2611_devices[] __initdata = {
-        &enp2611_flash,
-        &enp2611_i2c_controller
-};
-static void __init enp2611_init_machine(void)
-{
-        platform_add_devices(enp2611_devices, ARRAY_SIZE(enp2611_devices));
-        ixp2000_uart_init();
-}
-MACHINE_START(ENP2611, "Radisys ENP-2611 PCI network processor board")
-        /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
-        .atag_offset    = 0x100,
-        .map_io         = enp2611_map_io,
-        .init_irq       = ixp2000_init_irq,
-        .timer          = &enp2611_timer,
-        .init_machine   = enp2611_init_machine,
-        .restart        = ixp2000_restart,
-MACHINE_END
diff --git a/arch/arm/mach-ixp2000/include/mach/debug-macro.S b/arch/arm/mach-ixp2000/include/mach/debug-macro.S
deleted file mode 100644
index bdd3ccdc2890..000000000000
--- a/arch/arm/mach-ixp2000/include/mach/debug-macro.S
+++ /dev/null
@@ -1,25 +0,0 @@
-/* arch/arm/mach-ixp2000/include/mach/debug-macro.S
- *
- * Debugging macro include header
- *
- *  Copyright (C) 1994-1999 Russell King
- *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
-*/
-                .macro  addruart, rp, rv, tmp
-                mov     \rp, #0x00030000
-#ifdef  __ARMEB__
-                orr     \rp, \rp, #0x00000003
-#endif
-                orr     \rv, \rp, #0xfe000000   @ virtual base
-                orr     \rv, \rv, #0x00f00000
-                orr     \rp, \rp, #0xc0000000   @ Physical base
-                .endm
-#define UART_SHIFT      2
-#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/mach-ixp2000/include/mach/enp2611.h b/arch/arm/mach-ixp2000/include/mach/enp2611.h
deleted file mode 100644
index 9ce3690061d5..000000000000
--- a/arch/arm/mach-ixp2000/include/mach/enp2611.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * arch/arm/mach-ixp2000/include/mach/enp2611.h
- *
- * Register and other defines for Radisys ENP-2611
- *
- * Created 2004 by Lennert Buytenhek from the ixdp2x01 code.  The
- * original version carries the following notices:
- *
- * Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
- * Maintainer: Deepak Saxena <dsaxena@plexity.net>
- *
- * Copyright (C) 2002 Intel Corp.
- * Copyright (C) 2003-2004 MontaVista Software, Inc.
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- */
-#ifndef __ENP2611_H
-#define __ENP2611_H
-#define ENP2611_CALEB_PHYS_BASE         0xc5000000
-#define ENP2611_CALEB_VIRT_BASE         0xfe000000
-#define ENP2611_CALEB_SIZE              0x00100000
-#define ENP2611_PM3386_0_PHYS_BASE      0xc6000000
-#define ENP2611_PM3386_0_VIRT_BASE      0xfe100000
-#define ENP2611_PM3386_0_SIZE           0x00100000
-#define ENP2611_PM3386_1_PHYS_BASE      0xc6400000
-#define ENP2611_PM3386_1_VIRT_BASE      0xfe200000
-#define ENP2611_PM3386_1_SIZE           0x00100000
-#define ENP2611_GPIO_SCL                7
-#define ENP2611_GPIO_SDA                6
-#define IRQ_ENP2611_THERMAL             IRQ_IXP2000_GPIO4
-#define IRQ_ENP2611_OPTION_BOARD        IRQ_IXP2000_GPIO3
-#define IRQ_ENP2611_CALEB               IRQ_IXP2000_GPIO2
-#define IRQ_ENP2611_PM3386_1            IRQ_IXP2000_GPIO1
-#define IRQ_ENP2611_PM3386_0            IRQ_IXP2000_GPIO0
-#endif
diff --git a/arch/arm/mach-ixp2000/include/mach/entry-macro.S b/arch/arm/mach-ixp2000/include/mach/entry-macro.S
deleted file mode 100644
index c4444dff9202..000000000000
--- a/arch/arm/mach-ixp2000/include/mach/entry-macro.S
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * arch/arm/mach-ixp2000/include/mach/entry-macro.S
- *
- * Low-level IRQ helper macros for IXP2000-based platforms
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <mach/irqs.h>
-                .macro  get_irqnr_preamble, base, tmp
-                .endm
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                mov     \irqnr, #0x0              @clear out irqnr as default
-                mov     \base, #0xfe000000
-                orr     \base, \base, #0x00e00000
-                orr     \base, \base, #0x08
-                ldr     \irqstat, [\base]         @ get interrupts
-                cmp     \irqstat, #0
-                beq     1001f
-                clz     \irqnr, \irqstat
-                mov     \base, #31
-                subs    \irqnr, \base, \irqnr
-                /*
-                 * We handle PCIA and PCIB here so we don't have an
-                 * extra layer of code just to check these two bits.
-                 */
-                cmp     \irqnr, #IRQ_IXP2000_PCI
-                bne     1001f
-                mov     \base, #0xfe000000
-                orr     \base, \base, #0x00c00000
-                orr     \base, \base, #0x00000100
-                orr     \base, \base, #0x00000058
-                ldr     \irqstat, [\base]
-                mov     \tmp, #(1<<26)
-                tst     \irqstat, \tmp
-                movne   \irqnr, #IRQ_IXP2000_PCIA
-                bne     1001f
-                mov     \tmp, #(1<<27)
-                tst     \irqstat, \tmp
-                movne   \irqnr, #IRQ_IXP2000_PCIB
-1001:
-                .endm
diff --git a/arch/arm/mach-ixp2000/include/mach/gpio-ixp2000.h b/arch/arm/mach-ixp2000/include/mach/gpio-ixp2000.h
deleted file mode 100644
index af836c76c3f1..000000000000
--- a/arch/arm/mach-ixp2000/include/mach/gpio-ixp2000.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * arch/arm/mach-ixp2000/include/mach/gpio.h
- *
- * Copyright (C) 2002 Intel Corporation.
- *
- * This program is free software, you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-/*
- * IXP2000 GPIO in/out, edge/level detection for IRQs:
- * IRQs are generated on Falling-edge, Rising-Edge, Level-low, Level-High
- * or both Falling-edge and Rising-edge.
- * This must be called *before* the corresponding IRQ is registerd.
- * Use this instead of directly setting the GPIO registers.
- * GPIOs may also be used as GPIOs (e.g. for emulating i2c/smb)
- */
-#ifndef __ASM_ARCH_GPIO_H
-#define __ASM_ARCH_GPIO_H
-#ifndef __ASSEMBLY__
-#define GPIO_IN                         0
-#define GPIO_OUT                        1
-#define IXP2000_GPIO_LOW                0
-#define IXP2000_GPIO_HIGH               1
-extern void gpio_line_config(int line, int direction);
-static inline int gpio_line_get(int line)
-{
-        return (((*IXP2000_GPIO_PLR) >> line) & 1);
-}
-static inline void gpio_line_set(int line, int value)
-{
-        if (value == IXP2000_GPIO_HIGH) {
-                ixp2000_reg_write(IXP2000_GPIO_POSR, 1 << line);
-        } else if (value == IXP2000_GPIO_LOW) {
-                ixp2000_reg_write(IXP2000_GPIO_POCR, 1 << line);
-        }
-}
-#endif /* !__ASSEMBLY__ */
-#endif /* ASM_ARCH_IXP2000_GPIO_H_ */
diff --git a/arch/arm/mach-ixp2000/include/mach/hardware.h b/arch/arm/mach-ixp2000/include/mach/hardware.h
deleted file mode 100644
index cdaf1db84003..000000000000
--- a/arch/arm/mach-ixp2000/include/mach/hardware.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * arch/arm/mach-ixp2000/include/mach/hardware.h
- *
- * Hardware definitions for IXP2400/2800 based systems
- *
- * Original Author: Naeem M Afzal <naeem.m.afzal@intel.com>
- *
- * Maintainer: Deepak Saxena <dsaxena@mvista.com>
- *
- * Copyright (C) 2001-2002 Intel Corp.
- * Copyright (C) 2003-2004 MontaVista Software, Inc.
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- */
-#ifndef __ASM_ARCH_HARDWARE_H__
-#define __ASM_ARCH_HARDWARE_H__
-#include "ixp2000-regs.h"       /* Chipset Registers */
-/*
- * Platform helper functions
- */
-#include "platform.h"
-/*
- * Platform-specific bits
- */
-#include "enp2611.h"            /* ENP-2611 */
-#include "ixdp2x00.h"           /* IXDP2400/2800 */
-#include "ixdp2x01.h"           /* IXDP2401/2801 */
-#endif  /* _ASM_ARCH_HARDWARE_H__ */
diff --git a/arch/arm/mach-ixp2000/include/mach/io.h b/arch/arm/mach-ixp2000/include/mach/io.h
deleted file mode 100644
index f6552d6f35ab..000000000000
--- a/arch/arm/mach-ixp2000/include/mach/io.h
+++ /dev/null
@@ -1,133 +0,0 @@
-/*
- * arch/arm/mach-ixp2000/include/mach/io.h
- *
- * Original Author: Naeem M Afzal <naeem.m.afzal@intel.com>
- * Maintainer: Deepak Saxena <dsaxena@plexity.net>
- *
- * Copyright (C) 2002  Intel Corp.
- * Copyrgiht (C) 2003-2004 MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-#include <mach/hardware.h>
-#define IO_SPACE_LIMIT          0xffffffff
-/*
- * The A? revisions of the IXP2000s assert byte lanes for PCI I/O
- * transactions the other way round (MEM transactions don't have this
- * issue), so if we want to support those models, we need to override
- * the standard I/O functions.
- *
- * B0 and later have a bit that can be set to 1 to get the proper
- * behavior for I/O transactions, which then allows us to use the
- * standard I/O functions.  This is what we do if the user does not
- * explicitly ask for support for pre-B0.
- */
-#ifdef CONFIG_IXP2000_SUPPORT_BROKEN_PCI_IO
-#define ___io(p)                ((void __iomem *)((p)+IXP2000_PCI_IO_VIRT_BASE))
-#define alignb(addr)            (void __iomem *)((unsigned long)(addr) ^ 3)
-#define alignw(addr)            (void __iomem *)((unsigned long)(addr) ^ 2)
-#define outb(v,p)               __raw_writeb((v),alignb(___io(p)))
-#define outw(v,p)               __raw_writew((v),alignw(___io(p)))
-#define outl(v,p)               __raw_writel((v),___io(p))
-#define inb(p)          ({ unsigned int __v = __raw_readb(alignb(___io(p))); __v; })
-#define inw(p)          \
-        ({ unsigned int __v = (__raw_readw(alignw(___io(p)))); __v; })
-#define inl(p)          \
-        ({ unsigned int __v = (__raw_readl(___io(p))); __v; })
-#define outsb(p,d,l)            __raw_writesb(alignb(___io(p)),d,l)
-#define outsw(p,d,l)            __raw_writesw(alignw(___io(p)),d,l)
-#define outsl(p,d,l)            __raw_writesl(___io(p),d,l)
-#define insb(p,d,l)             __raw_readsb(alignb(___io(p)),d,l)
-#define insw(p,d,l)             __raw_readsw(alignw(___io(p)),d,l)
-#define insl(p,d,l)             __raw_readsl(___io(p),d,l)
-#define __is_io_address(p)      ((((unsigned long)(p)) & ~(IXP2000_PCI_IO_SIZE - 1)) == IXP2000_PCI_IO_VIRT_BASE)
-#define ioread8(p)                                              \
-        ({                                                      \
-                unsigned int __v;                               \
-                                                                \
-                if (__is_io_address(p)) {                       \
-                        __v = __raw_readb(alignb(p));           \
-                } else {                                        \
-                        __v = __raw_readb(p);                   \
-                }                                               \
-                                                                \
-                __v;                                            \
-        })                                                      \
-#define ioread16(p)                                             \
-        ({                                                      \
-                unsigned int __v;                               \
-                                                                \
-                if (__is_io_address(p)) {                       \
-                        __v = __raw_readw(alignw(p));           \
-                } else {                                        \
-                        __v = le16_to_cpu(__raw_readw(p));      \
-                }                                               \
-                                                                \
-                __v;                                            \
-        })
-#define ioread32(p)                                             \
-        ({                                                      \
-                unsigned int __v;                               \
-                                                                \
-                if (__is_io_address(p)) {                       \
-                        __v = __raw_readl(p);                   \
-                } else {                                        \
-                        __v = le32_to_cpu(__raw_readl(p));      \
-                }                                               \
-                                                                \
-                 __v;                                           \
-        })
-#define iowrite8(v,p)                                           \
-        ({                                                      \
-                if (__is_io_address(p)) {                       \
-                        __raw_writeb((v), alignb(p));           \
-                } else {                                        \
-                        __raw_writeb((v), p);                   \
-                }                                               \
-        })
-#define iowrite16(v,p)                                          \
-        ({                                                      \
-                if (__is_io_address(p)) {                       \
-                        __raw_writew((v), alignw(p));           \
-                } else {                                        \
-                        __raw_writew(cpu_to_le16(v), p);        \
-                }                                               \
-        })
-#define iowrite32(v,p)                                          \
-        ({                                                      \
-                if (__is_io_address(p)) {                       \
-                        __raw_writel((v), p);                   \
-                } else {                                        \
-                        __raw_writel(cpu_to_le32(v), p);        \
-                }                                               \
-        })
-#define ioport_map(port, nr)    ___io(port)
-#define ioport_unmap(addr)
-#else
-#define __io(p)                 ((void __iomem *)((p)+IXP2000_PCI_IO_VIRT_BASE))
-#endif
-#endif
diff --git a/arch/arm/mach-ixp2000/include/mach/irqs.h b/arch/arm/mach-ixp2000/include/mach/irqs.h
deleted file mode 100644
index bee96bcafdca..000000000000
--- a/arch/arm/mach-ixp2000/include/mach/irqs.h
+++ /dev/null
@@ -1,207 +0,0 @@
-/*
- * arch/arm/mach-ixp2000/include/mach/irqs.h
- *
- * Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
- * Maintainer: Deepak Saxena <dsaxena@plexity.net>
- *
- * Copyright (C) 2002 Intel Corp.
- * Copyright (C) 2003-2004 MontaVista Software, Inc.
- * 
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef _IRQS_H
-#define _IRQS_H
-/*
- * Do NOT add #ifdef MACHINE_FOO in here.
- * Simpy add your machine IRQs here and increase NR_IRQS if needed to
- * hold your machine's IRQ table.
- */
-/*
- * Some interrupt numbers go unused b/c the IRQ mask/ummask/status
- * register has those bit reserved. We just mark those interrupts
- * as invalid and this allows us to do mask/unmask with a single
- * shift operation instead of having to map the IRQ number to
- * a HW IRQ number.
- */
-#define IRQ_IXP2000_SOFT_INT            0 /* soft interrupt */
-#define IRQ_IXP2000_ERRSUM              1 /* OR of all bits in ErrorStatus reg*/
-#define IRQ_IXP2000_UART                2
-#define IRQ_IXP2000_GPIO                3
-#define IRQ_IXP2000_TIMER1              4
-#define IRQ_IXP2000_TIMER2              5
-#define IRQ_IXP2000_TIMER3              6
-#define IRQ_IXP2000_TIMER4              7
-#define IRQ_IXP2000_PMU                 8               
-#define IRQ_IXP2000_SPF                 9  /* Slow port framer IRQ */
-#define IRQ_IXP2000_DMA1                10
-#define IRQ_IXP2000_DMA2                11
-#define IRQ_IXP2000_DMA3                12
-#define IRQ_IXP2000_PCI_DOORBELL        13
-#define IRQ_IXP2000_ME_ATTN             14 
-#define IRQ_IXP2000_PCI                 15 /* PCI INTA or INTB */
-#define IRQ_IXP2000_THDA0               16 /* thread 0-31A */
-#define IRQ_IXP2000_THDA1               17 /* thread 32-63A, IXP2800 only */
-#define IRQ_IXP2000_THDA2               18 /* thread 64-95A */
-#define IRQ_IXP2000_THDA3               19 /* thread 96-127A, IXP2800 only */
-#define IRQ_IXP2000_THDB0               24 /* thread 0-31B */
-#define IRQ_IXP2000_THDB1               25 /* thread 32-63B, IXP2800 only */
-#define IRQ_IXP2000_THDB2               26 /* thread 64-95B */
-#define IRQ_IXP2000_THDB3               27 /* thread 96-127B, IXP2800 only */
-/* define generic GPIOs */
-#define IRQ_IXP2000_GPIO0               32
-#define IRQ_IXP2000_GPIO1               33
-#define IRQ_IXP2000_GPIO2               34
-#define IRQ_IXP2000_GPIO3               35
-#define IRQ_IXP2000_GPIO4               36
-#define IRQ_IXP2000_GPIO5               37
-#define IRQ_IXP2000_GPIO6               38
-#define IRQ_IXP2000_GPIO7               39
-/* split off the 2 PCI sources */
-#define IRQ_IXP2000_PCIA                40
-#define IRQ_IXP2000_PCIB                41
-/* Int sources from IRQ_ERROR_STATUS */
-#define IRQ_IXP2000_DRAM0_MIN_ERR       42
-#define IRQ_IXP2000_DRAM0_MAJ_ERR       43
-#define IRQ_IXP2000_DRAM1_MIN_ERR       44
-#define IRQ_IXP2000_DRAM1_MAJ_ERR       45
-#define IRQ_IXP2000_DRAM2_MIN_ERR       46
-#define IRQ_IXP2000_DRAM2_MAJ_ERR       47
-/* 48-57 reserved */
-#define IRQ_IXP2000_SRAM0_ERR           58
-#define IRQ_IXP2000_SRAM1_ERR           59
-#define IRQ_IXP2000_SRAM2_ERR           60
-#define IRQ_IXP2000_SRAM3_ERR           61
-/* 62-65 reserved */
-#define IRQ_IXP2000_MEDIA_ERR           66
-#define IRQ_IXP2000_PCI_ERR                     67
-#define IRQ_IXP2000_SP_INT                      68
-#define NR_IXP2000_IRQS                         69
-#define IXP2000_BOARD_IRQ(x)            (NR_IXP2000_IRQS + (x))
-#define IXP2000_BOARD_IRQ_MASK(irq)     (1 << (irq - NR_IXP2000_IRQS))  
-#define IXP2000_ERR_IRQ_MASK(irq) ( 1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR))
-#define IXP2000_VALID_ERR_IRQ_MASK (\
-                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM0_MIN_ERR) | \
-                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM0_MAJ_ERR) | \
-                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM1_MIN_ERR) | \
-                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM1_MAJ_ERR) | \
-                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM2_MIN_ERR) | \
-                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM2_MAJ_ERR) | \
-                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM0_ERR) | \
-                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM1_ERR) | \
-                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM2_ERR) | \
-                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM3_ERR) | \
-                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_MEDIA_ERR) | \
-                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_PCI_ERR) | \
-                IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SP_INT)        )
-/*
- * This allows for all the on-chip sources plus up to 32 CPLD based
- * IRQs. Should be more than enough.
- */
-#define IXP2000_BOARD_IRQS              32
-#define NR_IRQS                         (NR_IXP2000_IRQS + IXP2000_BOARD_IRQS)
-/* 
- * IXDP2400 specific IRQs
- */
-#define IRQ_IXDP2400_INGRESS_NPU        IXP2000_BOARD_IRQ(0) 
-#define IRQ_IXDP2400_ENET               IXP2000_BOARD_IRQ(1) 
-#define IRQ_IXDP2400_MEDIA_PCI          IXP2000_BOARD_IRQ(2) 
-#define IRQ_IXDP2400_MEDIA_SP           IXP2000_BOARD_IRQ(3) 
-#define IRQ_IXDP2400_SF_PCI             IXP2000_BOARD_IRQ(4) 
-#define IRQ_IXDP2400_SF_SP              IXP2000_BOARD_IRQ(5) 
-#define IRQ_IXDP2400_PMC                IXP2000_BOARD_IRQ(6) 
-#define IRQ_IXDP2400_TVM                IXP2000_BOARD_IRQ(7) 
-#define NR_IXDP2400_IRQS                ((IRQ_IXDP2400_TVM)+1)  
-#define IXDP2400_NR_IRQS                NR_IXDP2400_IRQS - NR_IXP2000_IRQS
-/* IXDP2800 specific IRQs */
-#define IRQ_IXDP2800_EGRESS_ENET        IXP2000_BOARD_IRQ(0)
-#define IRQ_IXDP2800_INGRESS_NPU        IXP2000_BOARD_IRQ(1)
-#define IRQ_IXDP2800_PMC                IXP2000_BOARD_IRQ(2)
-#define IRQ_IXDP2800_FABRIC_PCI         IXP2000_BOARD_IRQ(3)
-#define IRQ_IXDP2800_FABRIC             IXP2000_BOARD_IRQ(4)
-#define IRQ_IXDP2800_MEDIA              IXP2000_BOARD_IRQ(5)
-#define NR_IXDP2800_IRQS                ((IRQ_IXDP2800_MEDIA)+1)
-#define IXDP2800_NR_IRQS                NR_IXDP2800_IRQS - NR_IXP2000_IRQS
-/* 
- * IRQs on both IXDP2x01 boards
- */
-#define IRQ_IXDP2X01_SPCI_DB_0          IXP2000_BOARD_IRQ(2)
-#define IRQ_IXDP2X01_SPCI_DB_1          IXP2000_BOARD_IRQ(3)
-#define IRQ_IXDP2X01_SPCI_PMC_INTA      IXP2000_BOARD_IRQ(4)
-#define IRQ_IXDP2X01_SPCI_PMC_INTB      IXP2000_BOARD_IRQ(5)
-#define IRQ_IXDP2X01_SPCI_PMC_INTC      IXP2000_BOARD_IRQ(6)
-#define IRQ_IXDP2X01_SPCI_PMC_INTD      IXP2000_BOARD_IRQ(7)
-#define IRQ_IXDP2X01_SPCI_FIC_INT       IXP2000_BOARD_IRQ(8)
-#define IRQ_IXDP2X01_IPMI_FROM          IXP2000_BOARD_IRQ(16)
-#define IRQ_IXDP2X01_125US              IXP2000_BOARD_IRQ(17)
-#define IRQ_IXDP2X01_DB_0_ADD           IXP2000_BOARD_IRQ(18)
-#define IRQ_IXDP2X01_DB_1_ADD           IXP2000_BOARD_IRQ(19)
-#define IRQ_IXDP2X01_UART1              IXP2000_BOARD_IRQ(21)
-#define IRQ_IXDP2X01_UART2              IXP2000_BOARD_IRQ(22)
-#define IRQ_IXDP2X01_FIC_ADD_INT        IXP2000_BOARD_IRQ(24)
-#define IRQ_IXDP2X01_CS8900             IXP2000_BOARD_IRQ(25)
-#define IRQ_IXDP2X01_BBSRAM             IXP2000_BOARD_IRQ(26)
-#define IXDP2X01_VALID_IRQ_MASK ( \
-                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_DB_0) | \
-                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_DB_1) | \
-                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_PMC_INTA) | \
-                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_PMC_INTB) | \
-                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_PMC_INTC) | \
-                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_PMC_INTD) | \
-                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_FIC_INT) | \
-                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_IPMI_FROM) | \
-                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_125US) | \
-                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_DB_0_ADD) | \
-                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_DB_1_ADD) | \
-                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_UART1) | \
-                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_UART2) | \
-                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_FIC_ADD_INT) | \
-                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_CS8900) | \
-                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_BBSRAM) )
-/* 
- * IXDP2401 specific IRQs
- */
-#define IRQ_IXDP2401_INTA_82546         IXP2000_BOARD_IRQ(0)
-#define IRQ_IXDP2401_INTB_82546         IXP2000_BOARD_IRQ(1)
-#define IXDP2401_VALID_IRQ_MASK ( \
-                IXDP2X01_VALID_IRQ_MASK | \
-                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2401_INTA_82546) |\
-                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2401_INTB_82546))
-/*
- * IXDP2801-specific IRQs
- */
-#define IRQ_IXDP2801_RIV                IXP2000_BOARD_IRQ(0)
-#define IRQ_IXDP2801_CNFG_MEDIA         IXP2000_BOARD_IRQ(27)
-#define IRQ_IXDP2801_CLOCK_REF          IXP2000_BOARD_IRQ(28)
-#define IXDP2801_VALID_IRQ_MASK ( \
-                IXDP2X01_VALID_IRQ_MASK | \
-                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2801_RIV) |\
-                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2801_CNFG_MEDIA) |\
-                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2801_CLOCK_REF))
-#define NR_IXDP2X01_IRQS                ((IRQ_IXDP2801_CLOCK_REF) + 1)
-#endif /*_IRQS_H*/
diff --git a/arch/arm/mach-ixp2000/include/mach/ixdp2x00.h b/arch/arm/mach-ixp2000/include/mach/ixdp2x00.h
deleted file mode 100644
index 5df8479d9481..000000000000
--- a/arch/arm/mach-ixp2000/include/mach/ixdp2x00.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * arch/arm/mach-ixp2000/include/mach/ixdp2x00.h
- *
- * Register and other defines for IXDP2[48]00 platforms
- *
- * Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
- * Maintainer: Deepak Saxena <dsaxena@plexity.net>
- *
- * Copyright (C) 2002 Intel Corp.
- * Copyright (C) 2003-2004 MontaVista Software, Inc.
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- */
-#ifndef _IXDP2X00_H_
-#define _IXDP2X00_H_
-/*
- * On board CPLD memory map
- */
-#define IXDP2X00_PHYS_CPLD_BASE         0xc7000000
-#define IXDP2X00_VIRT_CPLD_BASE         0xfe000000
-#define IXDP2X00_CPLD_SIZE              0x00100000
-#define IXDP2X00_CPLD_REG(x)    \
-        (volatile unsigned long *)(IXDP2X00_VIRT_CPLD_BASE | x)
-/*
- * IXDP2400 CPLD registers
- */
-#define IXDP2400_CPLD_SYSLED            IXDP2X00_CPLD_REG(0x0)  
-#define IXDP2400_CPLD_DISP_DATA         IXDP2X00_CPLD_REG(0x4)
-#define IXDP2400_CPLD_CLOCK_SPEED       IXDP2X00_CPLD_REG(0x8)
-#define IXDP2400_CPLD_INT_STAT          IXDP2X00_CPLD_REG(0xc)
-#define IXDP2400_CPLD_REV               IXDP2X00_CPLD_REG(0x10)
-#define IXDP2400_CPLD_SYS_CLK_M         IXDP2X00_CPLD_REG(0x14)
-#define IXDP2400_CPLD_SYS_CLK_N         IXDP2X00_CPLD_REG(0x18)
-#define IXDP2400_CPLD_INT_MASK          IXDP2X00_CPLD_REG(0x48)
-/*
- * IXDP2800 CPLD registers
- */
-#define IXDP2800_CPLD_INT_STAT          IXDP2X00_CPLD_REG(0x0)
-#define IXDP2800_CPLD_INT_MASK          IXDP2X00_CPLD_REG(0x140)
-#define IXDP2X00_GPIO_I2C_ENABLE        0x02
-#define IXDP2X00_GPIO_SCL               0x07
-#define IXDP2X00_GPIO_SDA               0x06
-/*
- * PCI devfns for on-board devices. We need these to be able to
- * properly translate IRQs and for device removal.
- */
-#define IXDP2400_SLAVE_ENET_DEVFN       0x18    /* Bus 1 */
-#define IXDP2400_MASTER_ENET_DEVFN      0x20    /* Bus 1 */
-#define IXDP2400_MEDIA_DEVFN            0x28    /* Bus 1 */
-#define IXDP2400_SWITCH_FABRIC_DEVFN    0x30    /* Bus 1 */
-#define IXDP2800_SLAVE_ENET_DEVFN       0x20    /* Bus 1 */
-#define IXDP2800_MASTER_ENET_DEVFN      0x18    /* Bus 1 */
-#define IXDP2800_SWITCH_FABRIC_DEVFN    0x30    /* Bus 1 */
-#define IXDP2X00_P2P_DEVFN              0x20    /* Bus 0 */
-#define IXDP2X00_21555_DEVFN            0x30    /* Bus 0 */
-#define IXDP2X00_SLAVE_NPU_DEVFN        0x28    /* Bus 1 */
-#define IXDP2X00_PMC_DEVFN              0x38    /* Bus 1 */
-#define IXDP2X00_MASTER_NPU_DEVFN       0x38    /* Bus 1 */
-#ifndef __ASSEMBLY__
-/*
- * The master NPU is always PCI master.
- */
-static inline unsigned int ixdp2x00_master_npu(void)
-{
-        return !!ixp2000_is_pcimaster();
-}
-/*
- * Helper functions used by ixdp2400 and ixdp2800 specific code
- */
-void ixdp2x00_init_irq(volatile unsigned long*, volatile unsigned long *, unsigned long);
-void ixdp2x00_slave_pci_postinit(void);
-void ixdp2x00_init_machine(void);
-void ixdp2x00_map_io(void);
-#endif
-#endif /*_IXDP2X00_H_ */
diff --git a/arch/arm/mach-ixp2000/include/mach/ixdp2x01.h b/arch/arm/mach-ixp2000/include/mach/ixdp2x01.h
deleted file mode 100644
index 4c1f04083e54..000000000000
--- a/arch/arm/mach-ixp2000/include/mach/ixdp2x01.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * arch/arm/mach-ixp2000/include/mach/ixdp2x01.h
- *
- * Platform definitions for IXDP2X01 && IXDP2801 systems
- *
- * Author: Deepak Saxena <dsaxena@plexity.net>
- *
- * Copyright 2004 (c) MontaVista Software, Inc. 
- *
- * Based on original code Copyright (c) 2002-2003 Intel Corporation
- * 
- * This file is licensed under  the terms of the GNU General Public 
- * License version 2. This program is licensed "as is" without any 
- * warranty of any kind, whether express or implied.
- */
-#ifndef __IXDP2X01_H__
-#define __IXDP2X01_H__
-#define IXDP2X01_PHYS_CPLD_BASE         0xc6024000
-#define IXDP2X01_VIRT_CPLD_BASE         0xfe000000
-#define IXDP2X01_CPLD_REGION_SIZE       0x00100000
-#define IXDP2X01_CPLD_VIRT_REG(reg) (volatile unsigned long*)(IXDP2X01_VIRT_CPLD_BASE | reg)
-#define IXDP2X01_CPLD_PHYS_REG(reg) (IXDP2X01_PHYS_CPLD_BASE | reg)
-#define IXDP2X01_UART1_VIRT_BASE        IXDP2X01_CPLD_VIRT_REG(0x40)
-#define IXDP2X01_UART1_PHYS_BASE        IXDP2X01_CPLD_PHYS_REG(0x40)
-#define IXDP2X01_UART2_VIRT_BASE        IXDP2X01_CPLD_VIRT_REG(0x60)
-#define IXDP2X01_UART2_PHYS_BASE        IXDP2X01_CPLD_PHYS_REG(0x60)
-#define IXDP2X01_CS8900_VIRT_BASE       IXDP2X01_CPLD_VIRT_REG(0x80)
-#define IXDP2X01_CS8900_VIRT_END        (IXDP2X01_CS8900_VIRT_BASE + 16)
-#define IXDP2X01_CPLD_RESET_REG         IXDP2X01_CPLD_VIRT_REG(0x00)
-#define IXDP2X01_INT_MASK_SET_REG       IXDP2X01_CPLD_VIRT_REG(0x08)
-#define IXDP2X01_INT_STAT_REG           IXDP2X01_CPLD_VIRT_REG(0x0C)
-#define IXDP2X01_INT_RAW_REG            IXDP2X01_CPLD_VIRT_REG(0x10) 
-#define IXDP2X01_INT_MASK_CLR_REG       IXDP2X01_INT_RAW_REG
-#define IXDP2X01_INT_SIM_REG            IXDP2X01_CPLD_VIRT_REG(0x14)
-#define IXDP2X01_CPLD_FLASH_REG         IXDP2X01_CPLD_VIRT_REG(0x20)
-#define IXDP2X01_CPLD_FLASH_INTERN      0x8000
-#define IXDP2X01_CPLD_FLASH_BANK_MASK   0xF
-#define IXDP2X01_FLASH_WINDOW_BITS      25
-#define IXDP2X01_FLASH_WINDOW_SIZE      (1 << IXDP2X01_FLASH_WINDOW_BITS)
-#define IXDP2X01_FLASH_WINDOW_MASK      (IXDP2X01_FLASH_WINDOW_SIZE - 1)
-#define IXDP2X01_UART_CLK               1843200
-#define IXDP2X01_GPIO_I2C_ENABLE        0x02
-#define IXDP2X01_GPIO_SCL               0x07
-#define IXDP2X01_GPIO_SDA               0x06
-#endif /* __IXDP2x01_H__ */
diff --git a/arch/arm/mach-ixp2000/include/mach/ixp2000-regs.h b/arch/arm/mach-ixp2000/include/mach/ixp2000-regs.h
deleted file mode 100644
index 822f63f2f4a2..000000000000
--- a/arch/arm/mach-ixp2000/include/mach/ixp2000-regs.h
+++ /dev/null
@@ -1,451 +0,0 @@
-/*
- * arch/arm/mach-ixp2000/include/mach/ixp2000-regs.h
- *
- * Chipset register definitions for IXP2400/2800 based systems.
- *
- * Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
- *
- * Maintainer: Deepak Saxena <dsaxena@plexity.net>
- *
- * Copyright (C) 2002 Intel Corp.
- * Copyright (C) 2003-2004 MontaVista Software, Inc.
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- */
-#ifndef _IXP2000_REGS_H_
-#define _IXP2000_REGS_H_
-/*
- * IXP2000 linux memory map:
- *
- * virt         phys            size
- * fb000000     db000000        16M             PCI CFG1
- * fc000000     da000000        16M             PCI CFG0
- * fd000000     d8000000        16M             PCI I/O
- * fe[0-7]00000                 8M              per-platform mappings
- * fe900000     80000000        1M              SRAM #0 (first MB)
- * fea00000     cb400000        1M              SCRATCH ring get/put
- * feb00000     c8000000        1M              MSF
- * fec00000     df000000        1M              PCI CSRs
- * fed00000     de000000        1M              PCI CREG
- * fee00000     d6000000        1M              INTCTL
- * fef00000     c0000000        1M              CAP
- */
-/* 
- * Static I/O regions.
- *
- * Most of the registers are clumped in 4K regions spread throughout
- * the 0xc0000000 -> 0xc0100000 address range, but we just map in
- * the whole range using a single 1 MB section instead of small
- * 4K pages.
- *
- * CAP stands for CSR Access Proxy.
- *
- * If you change the virtual address of this mapping, please propagate
- * the change to arch/arm/kernel/debug.S, which hardcodes the virtual
- * address of the UART located in this region.
- */
-#define IXP2000_CAP_PHYS_BASE           0xc0000000
-#define IXP2000_CAP_VIRT_BASE           0xfef00000
-#define IXP2000_CAP_SIZE                0x00100000
-/*
- * Addresses for specific on-chip peripherals.
- */
-#define IXP2000_SLOWPORT_CSR_VIRT_BASE  0xfef80000
-#define IXP2000_GLOBAL_REG_VIRT_BASE    0xfef04000
-#define IXP2000_UART_PHYS_BASE          0xc0030000
-#define IXP2000_UART_VIRT_BASE          0xfef30000
-#define IXP2000_TIMER_VIRT_BASE         0xfef20000
-#define IXP2000_UENGINE_CSR_VIRT_BASE   0xfef18000
-#define IXP2000_GPIO_VIRT_BASE          0xfef10000
-/*
- * Devices outside of the 0xc0000000 -> 0xc0100000 range.  The virtual
- * addresses of the INTCTL and PCI_CSR mappings are hardcoded in
- * entry-macro.S, so if you ever change these please propagate
- * the change.
- */
-#define IXP2000_INTCTL_PHYS_BASE        0xd6000000
-#define IXP2000_INTCTL_VIRT_BASE        0xfee00000
-#define IXP2000_INTCTL_SIZE             0x00100000
-#define IXP2000_PCI_CREG_PHYS_BASE      0xde000000
-#define IXP2000_PCI_CREG_VIRT_BASE      0xfed00000
-#define IXP2000_PCI_CREG_SIZE           0x00100000
-#define IXP2000_PCI_CSR_PHYS_BASE       0xdf000000
-#define IXP2000_PCI_CSR_VIRT_BASE       0xfec00000
-#define IXP2000_PCI_CSR_SIZE            0x00100000
-#define IXP2000_MSF_PHYS_BASE           0xc8000000
-#define IXP2000_MSF_VIRT_BASE           0xfeb00000
-#define IXP2000_MSF_SIZE                0x00100000
-#define IXP2000_SCRATCH_RING_PHYS_BASE  0xcb400000
-#define IXP2000_SCRATCH_RING_VIRT_BASE  0xfea00000
-#define IXP2000_SCRATCH_RING_SIZE       0x00100000
-#define IXP2000_SRAM0_PHYS_BASE         0x80000000
-#define IXP2000_SRAM0_VIRT_BASE         0xfe900000
-#define IXP2000_SRAM0_SIZE              0x00100000
-#define IXP2000_PCI_IO_PHYS_BASE        0xd8000000
-#define IXP2000_PCI_IO_VIRT_BASE        0xfd000000
-#define IXP2000_PCI_IO_SIZE             0x01000000
-#define IXP2000_PCI_CFG0_PHYS_BASE      0xda000000
-#define IXP2000_PCI_CFG0_VIRT_BASE      0xfc000000
-#define IXP2000_PCI_CFG0_SIZE           0x01000000
-#define IXP2000_PCI_CFG1_PHYS_BASE      0xdb000000
-#define IXP2000_PCI_CFG1_VIRT_BASE      0xfb000000
-#define IXP2000_PCI_CFG1_SIZE           0x01000000
-/* 
- * Timers
- */
-#define IXP2000_TIMER_REG(x)            ((volatile unsigned long*)(IXP2000_TIMER_VIRT_BASE | (x)))
-/* Timer control */
-#define IXP2000_T1_CTL                  IXP2000_TIMER_REG(0x00)
-#define IXP2000_T2_CTL                  IXP2000_TIMER_REG(0x04)
-#define IXP2000_T3_CTL                  IXP2000_TIMER_REG(0x08)
-#define IXP2000_T4_CTL                  IXP2000_TIMER_REG(0x0c)
-/* Store initial value */
-#define IXP2000_T1_CLD                  IXP2000_TIMER_REG(0x10)
-#define IXP2000_T2_CLD                  IXP2000_TIMER_REG(0x14)
-#define IXP2000_T3_CLD                  IXP2000_TIMER_REG(0x18)
-#define IXP2000_T4_CLD                  IXP2000_TIMER_REG(0x1c)
-/* Read current value */
-#define IXP2000_T1_CSR                  IXP2000_TIMER_REG(0x20)
-#define IXP2000_T2_CSR                  IXP2000_TIMER_REG(0x24)
-#define IXP2000_T3_CSR                  IXP2000_TIMER_REG(0x28)
-#define IXP2000_T4_CSR                  IXP2000_TIMER_REG(0x2c)
-/* Clear associated timer interrupt */
-#define IXP2000_T1_CLR                  IXP2000_TIMER_REG(0x30)
-#define IXP2000_T2_CLR                  IXP2000_TIMER_REG(0x34)
-#define IXP2000_T3_CLR                  IXP2000_TIMER_REG(0x38)
-#define IXP2000_T4_CLR                  IXP2000_TIMER_REG(0x3c)
-/* Timer watchdog enable for T4 */
-#define IXP2000_TWDE                    IXP2000_TIMER_REG(0x40)
-#define WDT_ENABLE                      0x00000001
-#define TIMER_DIVIDER_256               0x00000008
-#define TIMER_ENABLE                    0x00000080
-#define IRQ_MASK_TIMER1                 (1 << 4)
-/*
- * Interrupt controller registers
- */
-#define IXP2000_INTCTL_REG(x)           (volatile unsigned long*)(IXP2000_INTCTL_VIRT_BASE | (x))
-#define IXP2000_IRQ_STATUS              IXP2000_INTCTL_REG(0x08)
-#define IXP2000_IRQ_ENABLE              IXP2000_INTCTL_REG(0x10)
-#define IXP2000_IRQ_ENABLE_SET          IXP2000_INTCTL_REG(0x10)
-#define IXP2000_IRQ_ENABLE_CLR          IXP2000_INTCTL_REG(0x18)
-#define IXP2000_FIQ_ENABLE_CLR          IXP2000_INTCTL_REG(0x14)
-#define IXP2000_IRQ_ERR_STATUS          IXP2000_INTCTL_REG(0x24)
-#define IXP2000_IRQ_ERR_ENABLE_SET      IXP2000_INTCTL_REG(0x2c)
-#define IXP2000_FIQ_ERR_ENABLE_CLR      IXP2000_INTCTL_REG(0x30)
-#define IXP2000_IRQ_ERR_ENABLE_CLR      IXP2000_INTCTL_REG(0x34)
-#define IXP2000_IRQ_THD_RAW_STATUS_A_0  IXP2000_INTCTL_REG(0x60)
-#define IXP2000_IRQ_THD_RAW_STATUS_A_1  IXP2000_INTCTL_REG(0x64)
-#define IXP2000_IRQ_THD_RAW_STATUS_A_2  IXP2000_INTCTL_REG(0x68)
-#define IXP2000_IRQ_THD_RAW_STATUS_A_3  IXP2000_INTCTL_REG(0x6c)
-#define IXP2000_IRQ_THD_RAW_STATUS_B_0  IXP2000_INTCTL_REG(0x80)
-#define IXP2000_IRQ_THD_RAW_STATUS_B_1  IXP2000_INTCTL_REG(0x84)
-#define IXP2000_IRQ_THD_RAW_STATUS_B_2  IXP2000_INTCTL_REG(0x88)
-#define IXP2000_IRQ_THD_RAW_STATUS_B_3  IXP2000_INTCTL_REG(0x8c)
-#define IXP2000_IRQ_THD_STATUS_A_0      IXP2000_INTCTL_REG(0xe0)
-#define IXP2000_IRQ_THD_STATUS_A_1      IXP2000_INTCTL_REG(0xe4)
-#define IXP2000_IRQ_THD_STATUS_A_2      IXP2000_INTCTL_REG(0xe8)
-#define IXP2000_IRQ_THD_STATUS_A_3      IXP2000_INTCTL_REG(0xec)
-#define IXP2000_IRQ_THD_STATUS_B_0      IXP2000_INTCTL_REG(0x100)
-#define IXP2000_IRQ_THD_STATUS_B_1      IXP2000_INTCTL_REG(0x104)
-#define IXP2000_IRQ_THD_STATUS_B_2      IXP2000_INTCTL_REG(0x108)
-#define IXP2000_IRQ_THD_STATUS_B_3      IXP2000_INTCTL_REG(0x10c)
-#define IXP2000_IRQ_THD_ENABLE_SET_A_0  IXP2000_INTCTL_REG(0x160)
-#define IXP2000_IRQ_THD_ENABLE_SET_A_1  IXP2000_INTCTL_REG(0x164)
-#define IXP2000_IRQ_THD_ENABLE_SET_A_2  IXP2000_INTCTL_REG(0x168)
-#define IXP2000_IRQ_THD_ENABLE_SET_A_3  IXP2000_INTCTL_REG(0x16c)
-#define IXP2000_IRQ_THD_ENABLE_SET_B_0  IXP2000_INTCTL_REG(0x180)
-#define IXP2000_IRQ_THD_ENABLE_SET_B_1  IXP2000_INTCTL_REG(0x184)
-#define IXP2000_IRQ_THD_ENABLE_SET_B_2  IXP2000_INTCTL_REG(0x188)
-#define IXP2000_IRQ_THD_ENABLE_SET_B_3  IXP2000_INTCTL_REG(0x18c)
-#define IXP2000_IRQ_THD_ENABLE_CLEAR_A_0        IXP2000_INTCTL_REG(0x1e0)
-#define IXP2000_IRQ_THD_ENABLE_CLEAR_A_1        IXP2000_INTCTL_REG(0x1e4)
-#define IXP2000_IRQ_THD_ENABLE_CLEAR_A_2        IXP2000_INTCTL_REG(0x1e8)
-#define IXP2000_IRQ_THD_ENABLE_CLEAR_A_3        IXP2000_INTCTL_REG(0x1ec)
-#define IXP2000_IRQ_THD_ENABLE_CLEAR_B_0        IXP2000_INTCTL_REG(0x200)
-#define IXP2000_IRQ_THD_ENABLE_CLEAR_B_1        IXP2000_INTCTL_REG(0x204)
-#define IXP2000_IRQ_THD_ENABLE_CLEAR_B_2        IXP2000_INTCTL_REG(0x208)
-#define IXP2000_IRQ_THD_ENABLE_CLEAR_B_3        IXP2000_INTCTL_REG(0x20c)
-/*
- * Mask of valid IRQs in the 32-bit IRQ register. We use
- * this to mark certain IRQs as being invalid.
- */
-#define IXP2000_VALID_IRQ_MASK  0x0f0fffff
-/*
- * PCI config register access from core
- */
-#define IXP2000_PCI_CREG(x)             (volatile unsigned long*)(IXP2000_PCI_CREG_VIRT_BASE | (x))
-#define IXP2000_PCI_CMDSTAT             IXP2000_PCI_CREG(0x04)
-#define IXP2000_PCI_CSR_BAR             IXP2000_PCI_CREG(0x10)
-#define IXP2000_PCI_SRAM_BAR            IXP2000_PCI_CREG(0x14)
-#define IXP2000_PCI_SDRAM_BAR           IXP2000_PCI_CREG(0x18)
-/*
- * PCI CSRs
- */
-#define IXP2000_PCI_CSR(x)              (volatile unsigned long*)(IXP2000_PCI_CSR_VIRT_BASE | (x))
-/*
- * PCI outbound interrupts
- */
-#define IXP2000_PCI_OUT_INT_STATUS      IXP2000_PCI_CSR(0x30)
-#define IXP2000_PCI_OUT_INT_MASK        IXP2000_PCI_CSR(0x34)
-/*
- * PCI communications
- */
-#define IXP2000_PCI_MAILBOX0            IXP2000_PCI_CSR(0x50)
-#define IXP2000_PCI_MAILBOX1            IXP2000_PCI_CSR(0x54)
-#define IXP2000_PCI_MAILBOX2            IXP2000_PCI_CSR(0x58)
-#define IXP2000_PCI_MAILBOX3            IXP2000_PCI_CSR(0x5C)
-#define IXP2000_XSCALE_DOORBELL         IXP2000_PCI_CSR(0x60)
-#define IXP2000_XSCALE_DOORBELL_SETUP   IXP2000_PCI_CSR(0x64)
-#define IXP2000_PCI_DOORBELL            IXP2000_PCI_CSR(0x70)
-#define IXP2000_PCI_DOORBELL_SETUP      IXP2000_PCI_CSR(0x74)
-/*
- * DMA engines
- */
-#define IXP2000_PCI_CH1_BYTE_CNT        IXP2000_PCI_CSR(0x80)
-#define IXP2000_PCI_CH1_ADDR            IXP2000_PCI_CSR(0x84)
-#define IXP2000_PCI_CH1_DRAM_ADDR       IXP2000_PCI_CSR(0x88)
-#define IXP2000_PCI_CH1_DESC_PTR        IXP2000_PCI_CSR(0x8C)
-#define IXP2000_PCI_CH1_CNTRL           IXP2000_PCI_CSR(0x90)
-#define IXP2000_PCI_CH1_ME_PARAM        IXP2000_PCI_CSR(0x94)
-#define IXP2000_PCI_CH2_BYTE_CNT        IXP2000_PCI_CSR(0xA0)
-#define IXP2000_PCI_CH2_ADDR            IXP2000_PCI_CSR(0xA4)
-#define IXP2000_PCI_CH2_DRAM_ADDR       IXP2000_PCI_CSR(0xA8)
-#define IXP2000_PCI_CH2_DESC_PTR        IXP2000_PCI_CSR(0xAC)
-#define IXP2000_PCI_CH2_CNTRL           IXP2000_PCI_CSR(0xB0)
-#define IXP2000_PCI_CH2_ME_PARAM        IXP2000_PCI_CSR(0xB4)
-#define IXP2000_PCI_CH3_BYTE_CNT        IXP2000_PCI_CSR(0xC0)
-#define IXP2000_PCI_CH3_ADDR            IXP2000_PCI_CSR(0xC4)
-#define IXP2000_PCI_CH3_DRAM_ADDR       IXP2000_PCI_CSR(0xC8)
-#define IXP2000_PCI_CH3_DESC_PTR        IXP2000_PCI_CSR(0xCC)
-#define IXP2000_PCI_CH3_CNTRL           IXP2000_PCI_CSR(0xD0)
-#define IXP2000_PCI_CH3_ME_PARAM        IXP2000_PCI_CSR(0xD4)
-#define IXP2000_DMA_INF_MODE            IXP2000_PCI_CSR(0xE0)
-/*
- * Size masks for BARs
- */
-#define IXP2000_PCI_SRAM_BASE_ADDR_MASK IXP2000_PCI_CSR(0xFC)
-#define IXP2000_PCI_DRAM_BASE_ADDR_MASK IXP2000_PCI_CSR(0x100)
-/*
- * Control and uEngine related
- */
-#define IXP2000_PCI_CONTROL             IXP2000_PCI_CSR(0x13C)
-#define IXP2000_PCI_ADDR_EXT            IXP2000_PCI_CSR(0x140)
-#define IXP2000_PCI_ME_PUSH_STATUS      IXP2000_PCI_CSR(0x148)
-#define IXP2000_PCI_ME_PUSH_EN          IXP2000_PCI_CSR(0x14C)
-#define IXP2000_PCI_ERR_STATUS          IXP2000_PCI_CSR(0x150)
-#define IXP2000_PCI_ERR_ENABLE          IXP2000_PCI_CSR(0x154)
-/*
- * Inbound PCI interrupt control
- */
-#define IXP2000_PCI_XSCALE_INT_STATUS   IXP2000_PCI_CSR(0x158)
-#define IXP2000_PCI_XSCALE_INT_ENABLE   IXP2000_PCI_CSR(0x15C)
-#define IXP2000_PCICNTL_PNR             (1<<17) /* PCI not Reset bit of PCI_CONTROL */
-#define IXP2000_PCICNTL_PCF             (1<<28) /* PCI Central function bit */
-#define IXP2000_XSCALE_INT              (1<<1)  /* Interrupt from XScale to PCI */
-/* These are from the IRQ register in the PCI ISR register */
-#define PCI_CONTROL_BE_DEO              (1 << 22)       /* Big Endian Data Enable Out */
-#define PCI_CONTROL_BE_DEI              (1 << 21)       /* Big Endian Data Enable In  */
-#define PCI_CONTROL_BE_BEO              (1 << 20)       /* Big Endian Byte Enable Out */
-#define PCI_CONTROL_BE_BEI              (1 << 19)       /* Big Endian Byte Enable In  */
-#define PCI_CONTROL_IEE                 (1 << 17)       /* I/O cycle Endian swap Enable */
-#define IXP2000_PCI_RST_REL             (1 << 2)
-#define CFG_RST_DIR                     (*IXP2000_PCI_CONTROL & IXP2000_PCICNTL_PCF)
-#define CFG_PCI_BOOT_HOST               (1 << 2)
-#define CFG_BOOT_PROM                   (1 << 1)
-/*
- * SlowPort CSRs
- *
- * The slowport is used to access things like flash, SONET framer control
- * ports, slave microprocessors, CPLDs, and others of chip memory mapped
- * peripherals.
- */
-#define SLOWPORT_CSR(x)         (volatile unsigned long*)(IXP2000_SLOWPORT_CSR_VIRT_BASE | (x))
-#define IXP2000_SLOWPORT_CCR            SLOWPORT_CSR(0x00)
-#define IXP2000_SLOWPORT_WTC1           SLOWPORT_CSR(0x04)
-#define IXP2000_SLOWPORT_WTC2           SLOWPORT_CSR(0x08)
-#define IXP2000_SLOWPORT_RTC1           SLOWPORT_CSR(0x0c)
-#define IXP2000_SLOWPORT_RTC2           SLOWPORT_CSR(0x10)
-#define IXP2000_SLOWPORT_FSR            SLOWPORT_CSR(0x14)
-#define IXP2000_SLOWPORT_PCR            SLOWPORT_CSR(0x18)
-#define IXP2000_SLOWPORT_ADC            SLOWPORT_CSR(0x1C)
-#define IXP2000_SLOWPORT_FAC            SLOWPORT_CSR(0x20)
-#define IXP2000_SLOWPORT_FRM            SLOWPORT_CSR(0x24)
-#define IXP2000_SLOWPORT_FIN            SLOWPORT_CSR(0x28)
-/*
- * CCR values.  
- * The CCR configures the clock division for the slowport interface.
- */
-#define SLOWPORT_CCR_DIV_1              0x00
-#define SLOWPORT_CCR_DIV_2              0x01
-#define SLOWPORT_CCR_DIV_4              0x02
-#define SLOWPORT_CCR_DIV_6              0x03
-#define SLOWPORT_CCR_DIV_8              0x04
-#define SLOWPORT_CCR_DIV_10             0x05
-#define SLOWPORT_CCR_DIV_12             0x06
-#define SLOWPORT_CCR_DIV_14             0x07
-#define SLOWPORT_CCR_DIV_16             0x08
-#define SLOWPORT_CCR_DIV_18             0x09
-#define SLOWPORT_CCR_DIV_20             0x0a
-#define SLOWPORT_CCR_DIV_22             0x0b
-#define SLOWPORT_CCR_DIV_24             0x0c
-#define SLOWPORT_CCR_DIV_26             0x0d
-#define SLOWPORT_CCR_DIV_28             0x0e
-#define SLOWPORT_CCR_DIV_30             0x0f
-/*
- * PCR values.  PCR configure the mode of the interface.
- */
-#define SLOWPORT_MODE_FLASH             0x00
-#define SLOWPORT_MODE_LUCENT            0x01
-#define SLOWPORT_MODE_PMC_SIERRA        0x02
-#define SLOWPORT_MODE_INTEL_UP          0x03
-#define SLOWPORT_MODE_MOTOROLA_UP       0x04
-/*
- * ADC values.  Defines data and address bus widths.
- */
-#define SLOWPORT_ADDR_WIDTH_8           0x00
-#define SLOWPORT_ADDR_WIDTH_16          0x01
-#define SLOWPORT_ADDR_WIDTH_24          0x02
-#define SLOWPORT_ADDR_WIDTH_32          0x03
-#define SLOWPORT_DATA_WIDTH_8           0x00
-#define SLOWPORT_DATA_WIDTH_16          0x10
-#define SLOWPORT_DATA_WIDTH_24          0x20
-#define SLOWPORT_DATA_WIDTH_32          0x30
-/*
- * Masks and shifts for various fields in the WTC and RTC registers.
- */
-#define SLOWPORT_WRTC_MASK_HD           0x0003
-#define SLOWPORT_WRTC_MASK_PW           0x003c
-#define SLOWPORT_WRTC_MASK_SU           0x03c0
-#define SLOWPORT_WRTC_SHIFT_HD          0x00
-#define SLOWPORT_WRTC_SHIFT_SU          0x02
-#define SLOWPORT_WRTC_SHFIT_PW          0x06
-/*
- * GPIO registers & GPIO interface.
- */
-#define IXP2000_GPIO_REG(x)             ((volatile unsigned long*)(IXP2000_GPIO_VIRT_BASE+(x)))
-#define IXP2000_GPIO_PLR                IXP2000_GPIO_REG(0x00)
-#define IXP2000_GPIO_PDPR               IXP2000_GPIO_REG(0x04)
-#define IXP2000_GPIO_PDSR               IXP2000_GPIO_REG(0x08)
-#define IXP2000_GPIO_PDCR               IXP2000_GPIO_REG(0x0c)
-#define IXP2000_GPIO_POPR               IXP2000_GPIO_REG(0x10)
-#define IXP2000_GPIO_POSR               IXP2000_GPIO_REG(0x14)
-#define IXP2000_GPIO_POCR               IXP2000_GPIO_REG(0x18)
-#define IXP2000_GPIO_REDR               IXP2000_GPIO_REG(0x1c)
-#define IXP2000_GPIO_FEDR               IXP2000_GPIO_REG(0x20)
-#define IXP2000_GPIO_EDSR               IXP2000_GPIO_REG(0x24)
-#define IXP2000_GPIO_LSHR               IXP2000_GPIO_REG(0x28)
-#define IXP2000_GPIO_LSLR               IXP2000_GPIO_REG(0x2c)
-#define IXP2000_GPIO_LDSR               IXP2000_GPIO_REG(0x30)
-#define IXP2000_GPIO_INER               IXP2000_GPIO_REG(0x34)
-#define IXP2000_GPIO_INSR               IXP2000_GPIO_REG(0x38)
-#define IXP2000_GPIO_INCR               IXP2000_GPIO_REG(0x3c)
-#define IXP2000_GPIO_INST               IXP2000_GPIO_REG(0x40)
-/*
- * "Global" registers...whatever that's supposed to mean.
- */
-#define GLOBAL_REG_BASE                 (IXP2000_GLOBAL_REG_VIRT_BASE + 0x0a00)
-#define GLOBAL_REG(x)                   (volatile unsigned long*)(GLOBAL_REG_BASE | (x))
-#define IXP2000_MAJ_PROD_TYPE_MASK      0x001F0000
-#define IXP2000_MAJ_PROD_TYPE_IXP2000   0x00000000
-#define IXP2000_MIN_PROD_TYPE_MASK      0x0000FF00
-#define IXP2000_MIN_PROD_TYPE_IXP2400   0x00000200
-#define IXP2000_MIN_PROD_TYPE_IXP2850   0x00000100
-#define IXP2000_MIN_PROD_TYPE_IXP2800   0x00000000
-#define IXP2000_MAJ_REV_MASK            0x000000F0
-#define IXP2000_MIN_REV_MASK            0x0000000F
-#define IXP2000_PROD_ID_MASK            0xFFFFFFFF
-#define IXP2000_PRODUCT_ID              GLOBAL_REG(0x00)
-#define IXP2000_MISC_CONTROL            GLOBAL_REG(0x04)
-#define IXP2000_MSF_CLK_CNTRL           GLOBAL_REG(0x08)
-#define IXP2000_RESET0                  GLOBAL_REG(0x0c)
-#define IXP2000_RESET1                  GLOBAL_REG(0x10)
-#define IXP2000_CCR                     GLOBAL_REG(0x14)
-#define IXP2000_STRAP_OPTIONS           GLOBAL_REG(0x18)
-#define RSTALL                          (1 << 16)
-#define WDT_RESET_ENABLE                0x01000000
-/*
- * MSF registers.  The IXP2400 and IXP2800 have somewhat different MSF
- * units, but the registers that differ between the two don't overlap,
- * so we can have one register list for both.
- */
-#define IXP2000_MSF_REG(x)                      ((volatile unsigned long*)(IXP2000_MSF_VIRT_BASE + (x)))
-#define IXP2000_MSF_RX_CONTROL                  IXP2000_MSF_REG(0x0000)
-#define IXP2000_MSF_TX_CONTROL                  IXP2000_MSF_REG(0x0004)
-#define IXP2000_MSF_INTERRUPT_STATUS            IXP2000_MSF_REG(0x0008)
-#define IXP2000_MSF_INTERRUPT_ENABLE            IXP2000_MSF_REG(0x000c)
-#define IXP2000_MSF_CSIX_TYPE_MAP               IXP2000_MSF_REG(0x0010)
-#define IXP2000_MSF_FC_EGRESS_STATUS            IXP2000_MSF_REG(0x0014)
-#define IXP2000_MSF_FC_INGRESS_STATUS           IXP2000_MSF_REG(0x0018)
-#define IXP2000_MSF_HWM_CONTROL                 IXP2000_MSF_REG(0x0024)
-#define IXP2000_MSF_FC_STATUS_OVERRIDE          IXP2000_MSF_REG(0x0028)
-#define IXP2000_MSF_CLOCK_CONTROL               IXP2000_MSF_REG(0x002c)
-#define IXP2000_MSF_RX_PORT_MAP                 IXP2000_MSF_REG(0x0040)
-#define IXP2000_MSF_RBUF_ELEMENT_DONE           IXP2000_MSF_REG(0x0044)
-#define IXP2000_MSF_RX_MPHY_POLL_LIMIT          IXP2000_MSF_REG(0x0048)
-#define IXP2000_MSF_RX_CALENDAR_LENGTH          IXP2000_MSF_REG(0x0048)
-#define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_0        IXP2000_MSF_REG(0x0050)
-#define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_1        IXP2000_MSF_REG(0x0054)
-#define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_2        IXP2000_MSF_REG(0x0058)
-#define IXP2000_MSF_TX_SEQUENCE_0               IXP2000_MSF_REG(0x0060)
-#define IXP2000_MSF_TX_SEQUENCE_1               IXP2000_MSF_REG(0x0064)
-#define IXP2000_MSF_TX_SEQUENCE_2               IXP2000_MSF_REG(0x0068)
-#define IXP2000_MSF_TX_MPHY_POLL_LIMIT          IXP2000_MSF_REG(0x0070)
-#define IXP2000_MSF_TX_CALENDAR_LENGTH          IXP2000_MSF_REG(0x0070)
-#define IXP2000_MSF_RX_UP_CONTROL_0             IXP2000_MSF_REG(0x0080)
-#define IXP2000_MSF_RX_UP_CONTROL_1             IXP2000_MSF_REG(0x0084)
-#define IXP2000_MSF_RX_UP_CONTROL_2             IXP2000_MSF_REG(0x0088)
-#define IXP2000_MSF_RX_UP_CONTROL_3             IXP2000_MSF_REG(0x008c)
-#define IXP2000_MSF_TX_UP_CONTROL_0             IXP2000_MSF_REG(0x0090)
-#define IXP2000_MSF_TX_UP_CONTROL_1             IXP2000_MSF_REG(0x0094)
-#define IXP2000_MSF_TX_UP_CONTROL_2             IXP2000_MSF_REG(0x0098)
-#define IXP2000_MSF_TX_UP_CONTROL_3             IXP2000_MSF_REG(0x009c)
-#define IXP2000_MSF_TRAIN_DATA                  IXP2000_MSF_REG(0x00a0)
-#define IXP2000_MSF_TRAIN_CALENDAR              IXP2000_MSF_REG(0x00a4)
-#define IXP2000_MSF_TRAIN_FLOW_CONTROL          IXP2000_MSF_REG(0x00a8)
-#define IXP2000_MSF_TX_CALENDAR_0               IXP2000_MSF_REG(0x1000)
-#define IXP2000_MSF_RX_PORT_CALENDAR_STATUS     IXP2000_MSF_REG(0x1400)
-#endif                          /* _IXP2000_H_ */
diff --git a/arch/arm/mach-ixp2000/include/mach/memory.h b/arch/arm/mach-ixp2000/include/mach/memory.h
deleted file mode 100644
index 5f0c4fd4076a..000000000000
--- a/arch/arm/mach-ixp2000/include/mach/memory.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * arch/arm/mach-ixp2000/include/mach/memory.h
- *
- * Copyright (c) 2002 Intel Corp.
- * Copyright (c) 2003-2004 MontaVista Software, Inc.
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- */
-#ifndef __ASM_ARCH_MEMORY_H
-#define __ASM_ARCH_MEMORY_H
-#define PLAT_PHYS_OFFSET        UL(0x00000000)
-#include <mach/ixp2000-regs.h>
-#define IXP2000_PCI_SDRAM_OFFSET        (*IXP2000_PCI_SDRAM_BAR & 0xfffffff0)
-#define __phys_to_bus(x)        ((x) + (IXP2000_PCI_SDRAM_OFFSET - PHYS_OFFSET))
-#define __bus_to_phys(x)        ((x) - (IXP2000_PCI_SDRAM_OFFSET - PHYS_OFFSET))
-#define __virt_to_bus(v)        __phys_to_bus(__virt_to_phys(v))
-#define __bus_to_virt(b)        __phys_to_virt(__bus_to_phys(b))
-#define __pfn_to_bus(p)         __phys_to_bus(__pfn_to_phys(p))
-#define __bus_to_pfn(b)         __phys_to_pfn(__bus_to_phys(b))
-#endif
diff --git a/arch/arm/mach-ixp2000/include/mach/platform.h b/arch/arm/mach-ixp2000/include/mach/platform.h
deleted file mode 100644
index bb0f8dcf9ee1..000000000000
--- a/arch/arm/mach-ixp2000/include/mach/platform.h
+++ /dev/null
@@ -1,153 +0,0 @@
-/*
- * arch/arm/mach-ixp2000/include/mach/platform.h
- *
- * Various bits of code used by platform-level code.
- *
- * Author: Deepak Saxena <dsaxena@plexity.net>
- *
- * Copyright 2004 (c) MontaVista Software, Inc. 
- * 
- * This file is licensed under  the terms of the GNU General Public 
- * License version 2. This program is licensed "as is" without any 
- * warranty of any kind, whether express or implied.
- */
-#ifndef __ASSEMBLY__
-static inline unsigned long ixp2000_reg_read(volatile void *reg)
-{
-        return *((volatile unsigned long *)reg);
-}
-static inline void ixp2000_reg_write(volatile void *reg, unsigned long val)
-{
-        *((volatile unsigned long *)reg) = val;
-}
-/*
- * On the IXP2400, we can't use XCB=000 due to chip bugs.  We use
- * XCB=101 instead, but that makes all I/O accesses bufferable.  This
- * is not a problem in general, but we do have to be slightly more
- * careful because I/O writes are no longer automatically flushed out
- * of the write buffer.
- *
- * In cases where we want to make sure that a write has been flushed
- * out of the write buffer before we proceed, for example when masking
- * a device interrupt before re-enabling IRQs in CPSR, we can use this
- * function, ixp2000_reg_wrb, which performs a write, a readback, and
- * issues a dummy instruction dependent on the value of the readback
- * (mov rX, rX) to make sure that the readback has completed before we
- * continue.
- */
-static inline void ixp2000_reg_wrb(volatile void *reg, unsigned long val)
-{
-        unsigned long dummy;
-        *((volatile unsigned long *)reg) = val;
-        dummy = *((volatile unsigned long *)reg);
-        __asm__ __volatile__("mov %0, %0" : "+r" (dummy));
-}
-/*
- * Boards may multiplex different devices on the 2nd channel of 
- * the slowport interface that each need different configuration 
- * settings.  For example, the IXDP2400 uses channel 2 on the interface 
- * to access the CPLD, the switch fabric card, and the media card.  Each
- * one needs a different mode so drivers must save/restore the mode 
- * before and after each operation.  
- *
- * acquire_slowport(&your_config);
- * ...
- * do slowport operations
- * ...
- * release_slowport();
- *
- * Note that while you have the slowport, you are holding a spinlock,
- * so your code should be written as if you explicitly acquired a lock.
- *
- * The configuration only affects device 2 on the slowport, so the
- * MTD map driver does not acquire/release the slowport.  
- */
-struct slowport_cfg {
-        unsigned long CCR;      /* Clock divide */
-        unsigned long WTC;      /* Write Timing Control */
-        unsigned long RTC;      /* Read Timing Control */
-        unsigned long PCR;      /* Protocol Control Register */
-        unsigned long ADC;      /* Address/Data Width Control */
-};
-void ixp2000_acquire_slowport(struct slowport_cfg *, struct slowport_cfg *);
-void ixp2000_release_slowport(struct slowport_cfg *);
-/*
- * IXP2400 A0/A1 and  IXP2800 A0/A1/A2 have broken slowport that requires
- * tweaking of addresses in the MTD driver.
- */
-static inline unsigned ixp2000_has_broken_slowport(void)
-{
-        unsigned long id = *IXP2000_PRODUCT_ID;
-        unsigned long id_prod = id & (IXP2000_MAJ_PROD_TYPE_MASK |
-                                      IXP2000_MIN_PROD_TYPE_MASK);
-        return (((id_prod ==
-                  /* fixed in IXP2400-B0 */
-                  (IXP2000_MAJ_PROD_TYPE_IXP2000 |
-                   IXP2000_MIN_PROD_TYPE_IXP2400)) &&
-                 ((id & IXP2000_MAJ_REV_MASK) == 0)) ||
-                ((id_prod ==
-                  /* fixed in IXP2800-B0 */
-                  (IXP2000_MAJ_PROD_TYPE_IXP2000 |
-                   IXP2000_MIN_PROD_TYPE_IXP2800)) &&
-                 ((id & IXP2000_MAJ_REV_MASK) == 0)) ||
-                ((id_prod ==
-                  /* fixed in IXP2850-B0 */
-                  (IXP2000_MAJ_PROD_TYPE_IXP2000 |
-                   IXP2000_MIN_PROD_TYPE_IXP2850)) &&
-                 ((id & IXP2000_MAJ_REV_MASK) == 0)));
-}
-static inline unsigned int ixp2000_has_flash(void)
-{
-        return ((*IXP2000_STRAP_OPTIONS) & (CFG_BOOT_PROM));
-}
-static inline unsigned int ixp2000_is_pcimaster(void)
-{
-        return ((*IXP2000_STRAP_OPTIONS) & (CFG_PCI_BOOT_HOST));
-}
-void ixp2000_map_io(void);
-void ixp2000_uart_init(void);
-void ixp2000_init_irq(void);
-void ixp2000_init_time(unsigned long);
-void ixp2000_restart(char, const char *);
-unsigned long ixp2000_gettimeoffset(void);
-struct pci_sys_data;
-u32 *ixp2000_pci_config_addr(unsigned int bus, unsigned int devfn, int where);
-void ixp2000_pci_preinit(void);
-int ixp2000_pci_setup(int, struct pci_sys_data*);
-struct pci_bus* ixp2000_pci_scan_bus(int, struct pci_sys_data*);
-int ixp2000_pci_read_config(struct pci_bus*, unsigned int, int, int, u32 *);
-int ixp2000_pci_write_config(struct pci_bus*, unsigned int, int, int, u32);
-/*
- * Several of the IXP2000 systems have banked flash so we need to extend the
- * flash_platform_data structure with some private pointers
- */
-struct ixp2000_flash_data {
-        struct flash_platform_data *platform_data;
-        int nr_banks;
-        unsigned long (*bank_setup)(unsigned long);
-};
-struct ixp2000_i2c_pins {
-        unsigned long sda_pin;
-        unsigned long scl_pin;
-};
-#endif /*  !__ASSEMBLY__ */
diff --git a/arch/arm/mach-ixp2000/include/mach/timex.h b/arch/arm/mach-ixp2000/include/mach/timex.h
deleted file mode 100644
index 835e659f93d4..000000000000
--- a/arch/arm/mach-ixp2000/include/mach/timex.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * arch/arm/mach-ixp2000/include/mach/timex.h
- *
- * IXP2000 architecture timex specifications
- */
-/*
- * Default clock is 50MHz APB, but platform code can override this
- */
-#define CLOCK_TICK_RATE 50000000
diff --git a/arch/arm/mach-ixp2000/include/mach/uncompress.h b/arch/arm/mach-ixp2000/include/mach/uncompress.h
deleted file mode 100644
index ce363087df78..000000000000
--- a/arch/arm/mach-ixp2000/include/mach/uncompress.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * arch/arm/mach-ixp2000/include/mach/uncompress.h
- *
- *
- * Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
- * Maintainer: Deepak Saxena <dsaxena@plexity.net>
- *
- * Copyright 2002 Intel Corp.
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- */
-#include <linux/serial_reg.h>
-#define UART_BASE       0xc0030000
-#define PHYS(x)          ((volatile unsigned long *)(UART_BASE + x))
-#define UARTDR          PHYS(0x00)      /* Transmit reg dlab=0 */
-#define UARTDLL         PHYS(0x00)      /* Divisor Latch reg dlab=1*/
-#define UARTDLM         PHYS(0x04)      /* Divisor Latch reg dlab=1*/
-#define UARTIER         PHYS(0x04)      /* Interrupt enable reg */
-#define UARTFCR         PHYS(0x08)      /* FIFO control reg dlab =0*/
-#define UARTLCR         PHYS(0x0c)      /* Control reg */
-#define UARTSR          PHYS(0x14)      /* Status reg */
-static inline void putc(int c)
-{
-        int j = 0x1000;
-        while (--j && !(*UARTSR & UART_LSR_THRE))
-                barrier();
-        *UARTDR = c;
-}
-static inline void flush(void)
-{
-}
-#define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-ixp2000/ixdp2400.c b/arch/arm/mach-ixp2000/ixdp2400.c
deleted file mode 100644
index 915ad49e3b8f..000000000000
--- a/arch/arm/mach-ixp2000/ixdp2400.c
+++ /dev/null
@@ -1,180 +0,0 @@
-/*
- * arch/arm/mach-ixp2000/ixdp2400.c
- *
- * IXDP2400 platform support
- *
- * Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
- * Maintainer: Deepak Saxena <dsaxena@plexity.net>
- *
- * Copyright (C) 2002 Intel Corp.
- * Copyright (C) 2003-2004 MontaVista Software, Inc.
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/sched.h>
-#include <linux/interrupt.h>
-#include <linux/device.h>
-#include <linux/bitops.h>
-#include <linux/pci.h>
-#include <linux/ioport.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <asm/irq.h>
-#include <asm/pgtable.h>
-#include <asm/page.h>
-#include <mach/hardware.h>
-#include <asm/mach-types.h>
-#include <asm/mach/pci.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-#include <asm/mach/time.h>
-#include <asm/mach/flash.h>
-#include <asm/mach/arch.h>
-/*************************************************************************
- * IXDP2400 timer tick
- *************************************************************************/
-static void __init ixdp2400_timer_init(void)
-{
-        int numerator, denominator;
-        int denom_array[] = {2, 4, 8, 16, 1, 2, 4, 8};
-        numerator = (*(IXDP2400_CPLD_SYS_CLK_M) & 0xFF) *2;
-        denominator = denom_array[(*(IXDP2400_CPLD_SYS_CLK_N) & 0x7)];
-        ixp2000_init_time(((3125000 * numerator) / (denominator)) / 2);
-}
-static struct sys_timer ixdp2400_timer = {
-        .init           = ixdp2400_timer_init,
-        .offset         = ixp2000_gettimeoffset,
-};
-/*************************************************************************
- * IXDP2400 PCI
- *************************************************************************/
-void __init ixdp2400_pci_preinit(void)
-{
-        ixp2000_reg_write(IXP2000_PCI_ADDR_EXT, 0x00100000);
-        ixp2000_pci_preinit();
-        pcibios_setup("firmware");
-}
-int ixdp2400_pci_setup(int nr, struct pci_sys_data *sys)
-{
-        sys->mem_offset = 0xe0000000;
-        ixp2000_pci_setup(nr, sys);
-        return 1;
-}
-static int __init ixdp2400_pci_map_irq(const struct pci_dev *dev, u8 slot,
-        u8 pin)
-{
-        if (ixdp2x00_master_npu()) {
-                /*
-                 * Root bus devices.  Slave NPU is only one with interrupt.
-                 * Everything else, we just return -1 b/c nothing else
-                 * on the root bus has interrupts.
-                 */
-                if(!dev->bus->self) {
-                        if(dev->devfn == IXDP2X00_SLAVE_NPU_DEVFN )
-                                return IRQ_IXDP2400_INGRESS_NPU;
-                        return -1;
-                }
-                /*
-                 * Bridge behind the PMC slot.
-                 * NOTE: Only INTA from the PMC slot is routed. VERY BAD.
-                 */
-                if(dev->bus->self->devfn == IXDP2X00_PMC_DEVFN &&
-                        dev->bus->parent->self->devfn == IXDP2X00_P2P_DEVFN &&
-                        !dev->bus->parent->self->bus->parent)
-                                  return IRQ_IXDP2400_PMC;
-                /*
-                 * Device behind the first bridge
-                 */
-                if(dev->bus->self->devfn == IXDP2X00_P2P_DEVFN) {
-                        switch(dev->devfn) {
-                                case IXDP2400_MASTER_ENET_DEVFN:        
-                                        return IRQ_IXDP2400_ENET;       
-                        
-                                case IXDP2400_MEDIA_DEVFN:
-                                        return IRQ_IXDP2400_MEDIA_PCI;
-                                case IXDP2400_SWITCH_FABRIC_DEVFN:
-                                        return IRQ_IXDP2400_SF_PCI;
-                                case IXDP2X00_PMC_DEVFN:
-                                        return IRQ_IXDP2400_PMC;
-                        }
-                }
-                return -1;
-        } else return IRQ_IXP2000_PCIB; /* Slave NIC interrupt */
-}
-static void ixdp2400_pci_postinit(void)
-{
-        struct pci_dev *dev;
-        if (ixdp2x00_master_npu()) {
-                dev = pci_get_bus_and_slot(1, IXDP2400_SLAVE_ENET_DEVFN);
-                pci_stop_and_remove_bus_device(dev);
-                pci_dev_put(dev);
-        } else {
-                dev = pci_get_bus_and_slot(1, IXDP2400_MASTER_ENET_DEVFN);
-                pci_stop_and_remove_bus_device(dev);
-                pci_dev_put(dev);
-                ixdp2x00_slave_pci_postinit();
-        }
-}
-static struct hw_pci ixdp2400_pci __initdata = {
-        .nr_controllers = 1,
-        .setup          = ixdp2400_pci_setup,
-        .preinit        = ixdp2400_pci_preinit,
-        .postinit       = ixdp2400_pci_postinit,
-        .scan           = ixp2000_pci_scan_bus,
-        .map_irq        = ixdp2400_pci_map_irq,
-};
-int __init ixdp2400_pci_init(void)
-{
-        if (machine_is_ixdp2400())
-                pci_common_init(&ixdp2400_pci);
-        return 0;
-}
-subsys_initcall(ixdp2400_pci_init);
-void __init ixdp2400_init_irq(void)
-{
-        ixdp2x00_init_irq(IXDP2400_CPLD_INT_STAT, IXDP2400_CPLD_INT_MASK, IXDP2400_NR_IRQS);
-}
-MACHINE_START(IXDP2400, "Intel IXDP2400 Development Platform")
-        /* Maintainer: MontaVista Software, Inc. */
-        .atag_offset    = 0x100,
-        .map_io         = ixdp2x00_map_io,
-        .init_irq       = ixdp2400_init_irq,
-        .timer          = &ixdp2400_timer,
-        .init_machine   = ixdp2x00_init_machine,
-        .restart        = ixp2000_restart,
-MACHINE_END
diff --git a/arch/arm/mach-ixp2000/ixdp2800.c b/arch/arm/mach-ixp2000/ixdp2800.c
deleted file mode 100644
index a9f1819ea049..000000000000
--- a/arch/arm/mach-ixp2000/ixdp2800.c
+++ /dev/null
@@ -1,295 +0,0 @@
-/*
- * arch/arm/mach-ixp2000/ixdp2800.c
- *
- * IXDP2800 platform support
- *
- * Original Author: Jeffrey Daly <jeffrey.daly@intel.com>
- * Maintainer: Deepak Saxena <dsaxena@plexity.net>
- *
- * Copyright (C) 2002 Intel Corp.
- * Copyright (C) 2003-2004 MontaVista Software, Inc.
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/sched.h>
-#include <linux/interrupt.h>
-#include <linux/device.h>
-#include <linux/bitops.h>
-#include <linux/pci.h>
-#include <linux/ioport.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <asm/irq.h>
-#include <asm/pgtable.h>
-#include <asm/page.h>
-#include <mach/hardware.h>
-#include <asm/mach-types.h>
-#include <asm/mach/pci.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-#include <asm/mach/time.h>
-#include <asm/mach/flash.h>
-#include <asm/mach/arch.h>
-/*************************************************************************
- * IXDP2800 timer tick
- *************************************************************************/
-static void __init ixdp2800_timer_init(void)
-{
-        ixp2000_init_time(50000000);
-}
-static struct sys_timer ixdp2800_timer = {
-        .init           = ixdp2800_timer_init,
-        .offset         = ixp2000_gettimeoffset,
-};
-/*************************************************************************
- * IXDP2800 PCI
- *************************************************************************/
-static void __init ixdp2800_slave_disable_pci_master(void)
-{
-        *IXP2000_PCI_CMDSTAT &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
-}
-static void __init ixdp2800_master_wait_for_slave(void)
-{
-        volatile u32 *addr;
-        printk(KERN_INFO "IXDP2800: waiting for slave NPU to configure "
-                         "its BAR sizes\n");
-        addr = ixp2000_pci_config_addr(0, IXDP2X00_SLAVE_NPU_DEVFN,
-                                        PCI_BASE_ADDRESS_1);
-        do {
-                *addr = 0xffffffff;
-                cpu_relax();
-        } while (*addr != 0xfe000008);
-        addr = ixp2000_pci_config_addr(0, IXDP2X00_SLAVE_NPU_DEVFN,
-                                        PCI_BASE_ADDRESS_2);
-        do {
-                *addr = 0xffffffff;
-                cpu_relax();
-        } while (*addr != 0xc0000008);
-        /*
-         * Configure the slave's SDRAM BAR by hand.
-         */
-        *addr = 0x40000008;
-}
-static void __init ixdp2800_slave_wait_for_master_enable(void)
-{
-        printk(KERN_INFO "IXDP2800: waiting for master NPU to enable us\n");
-        while ((*IXP2000_PCI_CMDSTAT & PCI_COMMAND_MASTER) == 0)
-                cpu_relax();
-}
-void __init ixdp2800_pci_preinit(void)
-{
-        printk("ixdp2x00_pci_preinit called\n");
-        *IXP2000_PCI_ADDR_EXT = 0x0001e000;
-        if (!ixdp2x00_master_npu())
-                ixdp2800_slave_disable_pci_master();
-        *IXP2000_PCI_SRAM_BASE_ADDR_MASK = (0x2000000 - 1) & ~0x3ffff;
-        *IXP2000_PCI_DRAM_BASE_ADDR_MASK = (0x40000000 - 1) & ~0xfffff;
-        ixp2000_pci_preinit();
-        if (ixdp2x00_master_npu()) {
-                /*
-                 * Wait until the slave set its SRAM/SDRAM BAR sizes
-                 * correctly before we proceed to scan and enumerate
-                 * the bus.
-                 */
-                ixdp2800_master_wait_for_slave();
-                /*
-                 * We configure the SDRAM BARs by hand because they
-                 * are 1G and fall outside of the regular allocated
-                 * PCI address space.
-                 */
-                *IXP2000_PCI_SDRAM_BAR = 0x00000008;
-        } else {
-                /*
-                 * Wait for the master to complete scanning the bus
-                 * and assigning resources before we proceed to scan
-                 * the bus ourselves.  Set pci=firmware to honor the
-                 * master's resource assignment.
-                 */
-                ixdp2800_slave_wait_for_master_enable();
-                pcibios_setup("firmware");
-        }
-}
-/*
- * We assign the SDRAM BARs for the two IXP2800 CPUs by hand, outside
- * of the regular PCI window, because there's only 512M of outbound PCI
- * memory window on each IXP, while we need 1G for each of the BARs.
- */
-static void __devinit ixp2800_pci_fixup(struct pci_dev *dev)
-{
-        if (machine_is_ixdp2800()) {
-                dev->resource[2].start = 0;
-                dev->resource[2].end   = 0;
-                dev->resource[2].flags = 0;
-        }
-}
-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IXP2800, ixp2800_pci_fixup);
-static int __init ixdp2800_pci_setup(int nr, struct pci_sys_data *sys)
-{
-        sys->mem_offset = 0x00000000;
-        ixp2000_pci_setup(nr, sys);
-        return 1;
-}
-static int __init ixdp2800_pci_map_irq(const struct pci_dev *dev, u8 slot,
-        u8 pin)
-{
-        if (ixdp2x00_master_npu()) {
-                /*
-                 * Root bus devices.  Slave NPU is only one with interrupt.
-                 * Everything else, we just return -1 which is invalid.
-                 */
-                if(!dev->bus->self) {
-                        if(dev->devfn == IXDP2X00_SLAVE_NPU_DEVFN )
-                                return IRQ_IXDP2800_INGRESS_NPU;
-                        return -1;
-                }
-                /*
-                 * Bridge behind the PMC slot.
-                 */
-                if(dev->bus->self->devfn == IXDP2X00_PMC_DEVFN &&
-                        dev->bus->parent->self->devfn == IXDP2X00_P2P_DEVFN &&
-                        !dev->bus->parent->self->bus->parent)
-                                  return IRQ_IXDP2800_PMC;
-                /*
-                 * Device behind the first bridge
-                 */
-                if(dev->bus->self->devfn == IXDP2X00_P2P_DEVFN) {
-                        switch(dev->devfn) {
-                                case IXDP2X00_PMC_DEVFN:
-                                        return IRQ_IXDP2800_PMC;        
-                        
-                                case IXDP2800_MASTER_ENET_DEVFN:
-                                        return IRQ_IXDP2800_EGRESS_ENET;
-                                case IXDP2800_SWITCH_FABRIC_DEVFN:
-                                        return IRQ_IXDP2800_FABRIC;
-                        }
-                }
-                return -1;
-        } else return IRQ_IXP2000_PCIB; /* Slave NIC interrupt */
-}
-static void __init ixdp2800_master_enable_slave(void)
-{
-        volatile u32 *addr;
-        printk(KERN_INFO "IXDP2800: enabling slave NPU\n");
-        addr = (volatile u32 *)ixp2000_pci_config_addr(0,
-                                        IXDP2X00_SLAVE_NPU_DEVFN,
-                                        PCI_COMMAND);
-        *addr |= PCI_COMMAND_MASTER;
-}
-static void __init ixdp2800_master_wait_for_slave_bus_scan(void)
-{
-        volatile u32 *addr;
-        printk(KERN_INFO "IXDP2800: waiting for slave to finish bus scan\n");
-        addr = (volatile u32 *)ixp2000_pci_config_addr(0,
-                                        IXDP2X00_SLAVE_NPU_DEVFN,
-                                        PCI_COMMAND);
-        while ((*addr & PCI_COMMAND_MEMORY) == 0)
-                cpu_relax();
-}
-static void __init ixdp2800_slave_signal_bus_scan_completion(void)
-{
-        printk(KERN_INFO "IXDP2800: bus scan done, signaling master\n");
-        *IXP2000_PCI_CMDSTAT |= PCI_COMMAND_MEMORY;
-}
-static void __init ixdp2800_pci_postinit(void)
-{
-        if (!ixdp2x00_master_npu()) {
-                ixdp2x00_slave_pci_postinit();
-                ixdp2800_slave_signal_bus_scan_completion();
-        }
-}
-struct __initdata hw_pci ixdp2800_pci __initdata = {
-        .nr_controllers = 1,
-        .setup          = ixdp2800_pci_setup,
-        .preinit        = ixdp2800_pci_preinit,
-        .postinit       = ixdp2800_pci_postinit,
-        .scan           = ixp2000_pci_scan_bus,
-        .map_irq        = ixdp2800_pci_map_irq,
-};
-int __init ixdp2800_pci_init(void)
-{
-        if (machine_is_ixdp2800()) {
-                struct pci_dev *dev;
-                pci_common_init(&ixdp2800_pci);
-                if (ixdp2x00_master_npu()) {
-                        dev = pci_get_bus_and_slot(1, IXDP2800_SLAVE_ENET_DEVFN);
-                        pci_stop_and_remove_bus_device(dev);
-                        pci_dev_put(dev);
-                        ixdp2800_master_enable_slave();
-                        ixdp2800_master_wait_for_slave_bus_scan();
-                } else {
-                        dev = pci_get_bus_and_slot(1, IXDP2800_MASTER_ENET_DEVFN);
-                        pci_stop_and_remove_bus_device(dev);
-                        pci_dev_put(dev);
-                }
-        }
-        return 0;
-}
-subsys_initcall(ixdp2800_pci_init);
-void __init ixdp2800_init_irq(void)
-{
-        ixdp2x00_init_irq(IXDP2800_CPLD_INT_STAT, IXDP2800_CPLD_INT_MASK, IXDP2800_NR_IRQS);
-}
-MACHINE_START(IXDP2800, "Intel IXDP2800 Development Platform")
-        /* Maintainer: MontaVista Software, Inc. */
-        .atag_offset    = 0x100,
-        .map_io         = ixdp2x00_map_io,
-        .init_irq       = ixdp2800_init_irq,
-        .timer          = &ixdp2800_timer,
-        .init_machine   = ixdp2x00_init_machine,
-        .restart        = ixp2000_restart,
-MACHINE_END
diff --git a/arch/arm/mach-ixp2000/ixdp2x00.c b/arch/arm/mach-ixp2000/ixdp2x00.c
deleted file mode 100644
index 421e38dc0fac..000000000000
--- a/arch/arm/mach-ixp2000/ixdp2x00.c
+++ /dev/null
@@ -1,306 +0,0 @@
-/*
- * arch/arm/mach-ixp2000/ixdp2x00.c
- *
- * Code common to IXDP2400 and IXDP2800 platforms.
- *
- * Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
- * Maintainer: Deepak Saxena <dsaxena@plexity.net>
- *
- * Copyright (C) 2002 Intel Corp.
- * Copyright (C) 2003-2004 MontaVista Software, Inc.
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- */
-#include <linux/gpio.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/sched.h>
-#include <linux/interrupt.h>
-#include <linux/platform_device.h>
-#include <linux/bitops.h>
-#include <linux/pci.h>
-#include <linux/ioport.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <asm/irq.h>
-#include <asm/pgtable.h>
-#include <asm/page.h>
-#include <mach/hardware.h>
-#include <asm/mach-types.h>
-#include <asm/mach/pci.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-#include <asm/mach/time.h>
-#include <asm/mach/flash.h>
-#include <asm/mach/arch.h>
-#include <mach/gpio-ixp2000.h>
-/*************************************************************************
- * IXDP2x00 IRQ Initialization
- *************************************************************************/
-static volatile unsigned long *board_irq_mask;
-static volatile unsigned long *board_irq_stat;
-static unsigned long board_irq_count;
-#ifdef CONFIG_ARCH_IXDP2400
-/*
- * Slowport configuration for accessing CPLD registers on IXDP2x00
- */
-static struct slowport_cfg slowport_cpld_cfg = {
-        .CCR =  SLOWPORT_CCR_DIV_2,
-        .WTC = 0x00000070,
-        .RTC = 0x00000070,
-        .PCR = SLOWPORT_MODE_FLASH,
-        .ADC = SLOWPORT_ADDR_WIDTH_24 | SLOWPORT_DATA_WIDTH_8
-};
-#endif
-static void ixdp2x00_irq_mask(struct irq_data *d)
-{
-        unsigned long dummy;
-        static struct slowport_cfg old_cfg;
-        /*
-         * This is ugly in common code but really don't know
-         * of a better way to handle it. :(
-         */
-#ifdef CONFIG_ARCH_IXDP2400
-        if (machine_is_ixdp2400())
-                ixp2000_acquire_slowport(&slowport_cpld_cfg, &old_cfg);
-#endif
-        dummy = *board_irq_mask;
-        dummy |=  IXP2000_BOARD_IRQ_MASK(d->irq);
-        ixp2000_reg_wrb(board_irq_mask, dummy);
-#ifdef CONFIG_ARCH_IXDP2400
-        if (machine_is_ixdp2400())
-                ixp2000_release_slowport(&old_cfg);
-#endif
-}
-static void ixdp2x00_irq_unmask(struct irq_data *d)
-{
-        unsigned long dummy;
-        static struct slowport_cfg old_cfg;
-#ifdef CONFIG_ARCH_IXDP2400
-        if (machine_is_ixdp2400())
-                ixp2000_acquire_slowport(&slowport_cpld_cfg, &old_cfg);
-#endif
-        dummy = *board_irq_mask;
-        dummy &=  ~IXP2000_BOARD_IRQ_MASK(d->irq);
-        ixp2000_reg_wrb(board_irq_mask, dummy);
-        if (machine_is_ixdp2400()) 
-                ixp2000_release_slowport(&old_cfg);
-}
-static void ixdp2x00_irq_handler(unsigned int irq, struct irq_desc *desc)
-{
-        volatile u32 ex_interrupt = 0;
-        static struct slowport_cfg old_cfg;
-        int i;
-        desc->irq_data.chip->irq_mask(&desc->irq_data);
-#ifdef CONFIG_ARCH_IXDP2400
-        if (machine_is_ixdp2400())
-                ixp2000_acquire_slowport(&slowport_cpld_cfg, &old_cfg);
-#endif
-        ex_interrupt = *board_irq_stat & 0xff;
-        if (machine_is_ixdp2400())
-                ixp2000_release_slowport(&old_cfg);
-        if(!ex_interrupt) {
-                printk(KERN_ERR "Spurious IXDP2x00 CPLD interrupt!\n");
-                return;
-        }
-        for(i = 0; i < board_irq_count; i++) {
-                if(ex_interrupt & (1 << i))  {
-                        int cpld_irq = IXP2000_BOARD_IRQ(0) + i;
-                        generic_handle_irq(cpld_irq);
-                }
-        }
-        desc->irq_data.chip->irq_unmask(&desc->irq_data);
-}
-static struct irq_chip ixdp2x00_cpld_irq_chip = {
-        .irq_ack        = ixdp2x00_irq_mask,
-        .irq_mask       = ixdp2x00_irq_mask,
-        .irq_unmask     = ixdp2x00_irq_unmask
-};
-void __init ixdp2x00_init_irq(volatile unsigned long *stat_reg, volatile unsigned long *mask_reg, unsigned long nr_of_irqs)
-{
-        unsigned int irq;
-        ixp2000_init_irq();
-        
-        if (!ixdp2x00_master_npu())
-                return;
-        board_irq_stat = stat_reg;
-        board_irq_mask = mask_reg;
-        board_irq_count = nr_of_irqs;
-        *board_irq_mask = 0xffffffff;
-        for(irq = IXP2000_BOARD_IRQ(0); irq < IXP2000_BOARD_IRQ(board_irq_count); irq++) {
-                irq_set_chip_and_handler(irq, &ixdp2x00_cpld_irq_chip,
-                                         handle_level_irq);
-                set_irq_flags(irq, IRQF_VALID);
-        }
-        /* Hook into PCI interrupt */
-        irq_set_chained_handler(IRQ_IXP2000_PCIB, ixdp2x00_irq_handler);
-}
-/*************************************************************************
- * IXDP2x00 memory map
- *************************************************************************/
-static struct map_desc ixdp2x00_io_desc __initdata = {
-        .virtual        = IXDP2X00_VIRT_CPLD_BASE, 
-        .pfn            = __phys_to_pfn(IXDP2X00_PHYS_CPLD_BASE),
-        .length         = IXDP2X00_CPLD_SIZE,
-        .type           = MT_DEVICE
-};
-void __init ixdp2x00_map_io(void)
-{
-        ixp2000_map_io();       
-        iotable_init(&ixdp2x00_io_desc, 1);
-}
-/*************************************************************************
- * IXDP2x00-common PCI init
- *
- * The IXDP2[48]00 has a horrid PCI bus layout. Basically the board 
- * contains two NPUs (ingress and egress) connected over PCI,  both running 
- * instances  of the kernel. So far so good. Peers on the PCI bus running 
- * Linux is a common design in telecom systems. The problem is that instead 
- * of all the devices being controlled by a single host, different
- * devices are controlled by different NPUs on the same bus, leading to
- * multiple hosts on the bus. The exact bus layout looks like:
- *
- *                   Bus 0
- *    Master NPU <-------------------+-------------------> Slave NPU
- *                                   |
- *                                   |
- *                                  P2P 
- *                                   |
- *
- *                  Bus 1            |
- *               <--+------+---------+---------+------+-->
- *                  |      |         |         |      |
- *                  |      |         |         |      |
- *             ... Dev    PMC       Media     Eth0   Eth1 ...
- *
- * The master controls all but Eth1, which is controlled by the
- * slave. What this means is that the both the master and the slave
- * have to scan the bus, but only one of them can enumerate the bus.
- * In addition, after the bus is scanned, each kernel must remove
- * the device(s) it does not control from the PCI dev list otherwise
- * a driver on each NPU will try to manage it and we will have horrible
- * conflicts. Oh..and the slave NPU needs to see the master NPU
- * for Intel's drivers to work properly. Closed source drivers...
- *
- * The way we deal with this is fairly simple but ugly:
- *
- * 1) Let master scan and enumerate the bus completely.
- * 2) Master deletes Eth1 from device list.
- * 3) Slave scans bus and then deletes all but Eth1 (Eth0 on slave)
- *    from device list.
- * 4) Find HW designers and LART them.
- *
- * The boards also do not do normal PCI IRQ routing, or any sort of 
- * sensical  swizzling, so we just need to check where on the  bus a
- * device sits and figure out to which CPLD pin the interrupt is routed.
- * See ixdp2[48]00.c files.
- *
- *************************************************************************/
-void ixdp2x00_slave_pci_postinit(void)
-{
-        struct pci_dev *dev;
-        /*
-         * Remove PMC device is there is one
-         */
-        if((dev = pci_get_bus_and_slot(1, IXDP2X00_PMC_DEVFN))) {
-                pci_stop_and_remove_bus_device(dev);
-                pci_dev_put(dev);
-        }
-        dev = pci_get_bus_and_slot(0, IXDP2X00_21555_DEVFN);
-        pci_stop_and_remove_bus_device(dev);
-        pci_dev_put(dev);
-}
-/**************************************************************************
- * IXDP2x00 Machine Setup
- *************************************************************************/
-static struct flash_platform_data ixdp2x00_platform_data = {
-        .map_name       = "cfi_probe",
-        .width          = 1,
-};
-static struct ixp2000_flash_data ixdp2x00_flash_data = {
-        .platform_data  = &ixdp2x00_platform_data,
-        .nr_banks       = 1
-};
-static struct resource ixdp2x00_flash_resource = {
-        .start          = 0xc4000000,
-        .end            = 0xc4000000 + 0x00ffffff,
-        .flags          = IORESOURCE_MEM,
-};
-static struct platform_device ixdp2x00_flash = {
-        .name           = "IXP2000-Flash",
-        .id             = 0,
-        .dev            = {
-                .platform_data = &ixdp2x00_flash_data,
-        },
-        .num_resources  = 1,
-        .resource       = &ixdp2x00_flash_resource,
-};
-static struct ixp2000_i2c_pins ixdp2x00_i2c_gpio_pins = {
-        .sda_pin        = IXDP2X00_GPIO_SDA,
-        .scl_pin        = IXDP2X00_GPIO_SCL,
-};
-static struct platform_device ixdp2x00_i2c_controller = {
-        .name           = "IXP2000-I2C",
-        .id             = 0,
-        .dev            = {
-                .platform_data = &ixdp2x00_i2c_gpio_pins,
-        },
-        .num_resources  = 0
-};
-static struct platform_device *ixdp2x00_devices[] __initdata = {
-        &ixdp2x00_flash,
-        &ixdp2x00_i2c_controller
-};
-void __init ixdp2x00_init_machine(void)
-{
-        gpio_line_set(IXDP2X00_GPIO_I2C_ENABLE, 1);
-        gpio_line_config(IXDP2X00_GPIO_I2C_ENABLE, GPIO_OUT);
-        platform_add_devices(ixdp2x00_devices, ARRAY_SIZE(ixdp2x00_devices));
-        ixp2000_uart_init();
-}
diff --git a/arch/arm/mach-ixp2000/ixdp2x01.c b/arch/arm/mach-ixp2000/ixdp2x01.c
deleted file mode 100644
index 5196c39cdba4..000000000000
--- a/arch/arm/mach-ixp2000/ixdp2x01.c
+++ /dev/null
@@ -1,483 +0,0 @@
-/*
- * arch/arm/mach-ixp2000/ixdp2x01.c
- *
- * Code common to Intel IXDP2401 and IXDP2801 platforms
- *
- * Original Author: Andrzej Mialkowski <andrzej.mialkowski@intel.com>
- * Maintainer: Deepak Saxena <dsaxena@plexity.net>
- *
- * Copyright (C) 2002-2003 Intel Corp.
- * Copyright (C) 2003-2004 MontaVista Software, Inc.
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/sched.h>
-#include <linux/interrupt.h>
-#include <linux/bitops.h>
-#include <linux/pci.h>
-#include <linux/ioport.h>
-#include <linux/delay.h>
-#include <linux/serial.h>
-#include <linux/tty.h>
-#include <linux/serial_core.h>
-#include <linux/platform_device.h>
-#include <linux/serial_8250.h>
-#include <linux/io.h>
-#include <asm/irq.h>
-#include <asm/pgtable.h>
-#include <asm/page.h>
-#include <mach/hardware.h>
-#include <asm/mach-types.h>
-#include <asm/mach/pci.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-#include <asm/mach/time.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/flash.h>
-/*************************************************************************
- * IXDP2x01 IRQ Handling
- *************************************************************************/
-static void ixdp2x01_irq_mask(struct irq_data *d)
-{
-        ixp2000_reg_wrb(IXDP2X01_INT_MASK_SET_REG,
-                                IXP2000_BOARD_IRQ_MASK(d->irq));
-}
-static void ixdp2x01_irq_unmask(struct irq_data *d)
-{
-        ixp2000_reg_write(IXDP2X01_INT_MASK_CLR_REG,
-                                IXP2000_BOARD_IRQ_MASK(d->irq));
-}
-static u32 valid_irq_mask;
-static void ixdp2x01_irq_handler(unsigned int irq, struct irq_desc *desc)
-{
-        u32 ex_interrupt;
-        int i;
-        desc->irq_data.chip->irq_mask(&desc->irq_data);
-        ex_interrupt = *IXDP2X01_INT_STAT_REG & valid_irq_mask;
-        if (!ex_interrupt) {
-                printk(KERN_ERR "Spurious IXDP2X01 CPLD interrupt!\n");
-                return;
-        }
-        for (i = 0; i < IXP2000_BOARD_IRQS; i++) {
-                if (ex_interrupt & (1 << i)) {
-                        int cpld_irq = IXP2000_BOARD_IRQ(0) + i;
-                        generic_handle_irq(cpld_irq);
-                }
-        }
-        desc->irq_data.chip->irq_unmask(&desc->irq_data);
-}
-static struct irq_chip ixdp2x01_irq_chip = {
-        .irq_mask       = ixdp2x01_irq_mask,
-        .irq_ack        = ixdp2x01_irq_mask,
-        .irq_unmask     = ixdp2x01_irq_unmask
-};
-/*
- * We only do anything if we are the master NPU on the board.
- * The slave NPU only has the ethernet chip going directly to
- * the PCIB interrupt input.
- */
-void __init ixdp2x01_init_irq(void)
-{
-        int irq = 0;
-        /* initialize chip specific interrupts */
-        ixp2000_init_irq();
-        if (machine_is_ixdp2401())
-                valid_irq_mask = IXDP2401_VALID_IRQ_MASK;
-        else
-                valid_irq_mask = IXDP2801_VALID_IRQ_MASK;
-        /* Mask all interrupts from CPLD, disable simulation */
-        ixp2000_reg_write(IXDP2X01_INT_MASK_SET_REG, 0xffffffff);
-        ixp2000_reg_wrb(IXDP2X01_INT_SIM_REG, 0);
-        for (irq = NR_IXP2000_IRQS; irq < NR_IXDP2X01_IRQS; irq++) {
-                if (irq & valid_irq_mask) {
-                        irq_set_chip_and_handler(irq, &ixdp2x01_irq_chip,
-                                                 handle_level_irq);
-                        set_irq_flags(irq, IRQF_VALID);
-                } else {
-                        set_irq_flags(irq, 0);
-                }
-        }
-        /* Hook into PCI interrupts */
-        irq_set_chained_handler(IRQ_IXP2000_PCIB, ixdp2x01_irq_handler);
-}
-/*************************************************************************
- * IXDP2x01 memory map
- *************************************************************************/
-static struct map_desc ixdp2x01_io_desc __initdata = {
-        .virtual        = IXDP2X01_VIRT_CPLD_BASE, 
-        .pfn            = __phys_to_pfn(IXDP2X01_PHYS_CPLD_BASE),
-        .length         = IXDP2X01_CPLD_REGION_SIZE,
-        .type           = MT_DEVICE
-};
-static void __init ixdp2x01_map_io(void)
-{
-        ixp2000_map_io();
-        iotable_init(&ixdp2x01_io_desc, 1);
-}
-/*************************************************************************
- * IXDP2x01 serial ports
- *************************************************************************/
-static struct plat_serial8250_port ixdp2x01_serial_port1[] = {
-        {
-                .mapbase        = (unsigned long)IXDP2X01_UART1_PHYS_BASE,
-                .membase        = (char *)IXDP2X01_UART1_VIRT_BASE,
-                .irq            = IRQ_IXDP2X01_UART1,
-                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
-                .iotype         = UPIO_MEM32,
-                .regshift       = 2,
-                .uartclk        = IXDP2X01_UART_CLK,
-        },
-        { }
-};
-static struct resource ixdp2x01_uart_resource1 = {
-        .start          = IXDP2X01_UART1_PHYS_BASE,
-        .end            = IXDP2X01_UART1_PHYS_BASE + 0xffff,
-        .flags          = IORESOURCE_MEM,
-};
-static struct platform_device ixdp2x01_serial_device1 = {
-        .name           = "serial8250",
-        .id             = PLAT8250_DEV_PLATFORM1,
-        .dev            = {
-                .platform_data          = ixdp2x01_serial_port1,
-        },
-        .num_resources  = 1,
-        .resource       = &ixdp2x01_uart_resource1,
-};
-static struct plat_serial8250_port ixdp2x01_serial_port2[] = {
-        {
-                .mapbase        = (unsigned long)IXDP2X01_UART2_PHYS_BASE,
-                .membase        = (char *)IXDP2X01_UART2_VIRT_BASE,
-                .irq            = IRQ_IXDP2X01_UART2,
-                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
-                .iotype         = UPIO_MEM32,
-                .regshift       = 2,
-                .uartclk        = IXDP2X01_UART_CLK,
-        }, 
-        { }
-};
-static struct resource ixdp2x01_uart_resource2 = {
-        .start          = IXDP2X01_UART2_PHYS_BASE,
-        .end            = IXDP2X01_UART2_PHYS_BASE + 0xffff,
-        .flags          = IORESOURCE_MEM,
-};
-static struct platform_device ixdp2x01_serial_device2 = {
-        .name           = "serial8250",
-        .id             = PLAT8250_DEV_PLATFORM2,
-        .dev            = {
-                .platform_data          = ixdp2x01_serial_port2,
-        },
-        .num_resources  = 1,
-        .resource       = &ixdp2x01_uart_resource2,
-};
-static void ixdp2x01_uart_init(void)
-{
-        platform_device_register(&ixdp2x01_serial_device1);
-        platform_device_register(&ixdp2x01_serial_device2);
-}
-/*************************************************************************
- * IXDP2x01 timer tick configuration
- *************************************************************************/
-static unsigned int ixdp2x01_clock;
-static int __init ixdp2x01_clock_setup(char *str)
-{
-        ixdp2x01_clock = simple_strtoul(str, NULL, 10);
-        return 1;
-}
-__setup("ixdp2x01_clock=", ixdp2x01_clock_setup);
-static void __init ixdp2x01_timer_init(void)
-{
-        if (!ixdp2x01_clock)
-                ixdp2x01_clock = 50000000;
-        ixp2000_init_time(ixdp2x01_clock);
-}
-static struct sys_timer ixdp2x01_timer = {
-        .init           = ixdp2x01_timer_init,
-        .offset         = ixp2000_gettimeoffset,
-};
-/*************************************************************************
- * IXDP2x01 PCI
- *************************************************************************/
-void __init ixdp2x01_pci_preinit(void)
-{
-        ixp2000_reg_write(IXP2000_PCI_ADDR_EXT, 0x00000000);
-        ixp2000_pci_preinit();
-        pcibios_setup("firmware");
-}
-#define DEVPIN(dev, pin) ((pin) | ((dev) << 3))
-static int __init ixdp2x01_pci_map_irq(const struct pci_dev *dev, u8 slot,
-        u8 pin)
-{
-        u8 bus = dev->bus->number;
-        u32 devpin = DEVPIN(PCI_SLOT(dev->devfn), pin);
-        struct pci_bus *tmp_bus = dev->bus;
-        /* Primary bus, no interrupts here */
-        if (bus == 0) {
-                return -1;
-        }
-        /* Lookup first leaf in bus tree */
-        while ((tmp_bus->parent != NULL) && (tmp_bus->parent->parent != NULL)) {
-                tmp_bus = tmp_bus->parent;
-        }
-        /* Select between known bridges */
-        switch (tmp_bus->self->devfn | (tmp_bus->self->bus->number << 8)) {
-        /* Device is located after first MB bridge */
-        case 0x0008:
-                if (tmp_bus == dev->bus) {
-                        /* Device is located directly after first MB bridge */
-                        switch (devpin) {
-                        case DEVPIN(1, 1):      /* Onboard 82546 ch 0 */
-                                if (machine_is_ixdp2401())
-                                        return IRQ_IXDP2401_INTA_82546;
-                                return -1;
-                        case DEVPIN(1, 2):      /* Onboard 82546 ch 1 */
-                                if (machine_is_ixdp2401())
-                                        return IRQ_IXDP2401_INTB_82546;
-                                return -1;
-                        case DEVPIN(0, 1):      /* PMC INTA# */
-                                return IRQ_IXDP2X01_SPCI_PMC_INTA;
-                        case DEVPIN(0, 2):      /* PMC INTB# */
-                                return IRQ_IXDP2X01_SPCI_PMC_INTB;
-                        case DEVPIN(0, 3):      /* PMC INTC# */
-                                return IRQ_IXDP2X01_SPCI_PMC_INTC;
-                        case DEVPIN(0, 4):      /* PMC INTD# */
-                                return IRQ_IXDP2X01_SPCI_PMC_INTD;
-                        }
-                }
-                break;
-        case 0x0010:
-                if (tmp_bus == dev->bus) {
-                        /* Device is located directly after second MB bridge */
-                        /* Secondary bus of second bridge */
-                        switch (devpin) {
-                        case DEVPIN(0, 1):      /* DB#0 */
-                                return IRQ_IXDP2X01_SPCI_DB_0;
-                        case DEVPIN(1, 1):      /* DB#1 */
-                                return IRQ_IXDP2X01_SPCI_DB_1;
-                        }
-                } else {
-                        /* Device is located indirectly after second MB bridge */
-                        /* Not supported now */
-                }
-                break;
-        }
-        return -1;
-}
-static int ixdp2x01_pci_setup(int nr, struct pci_sys_data *sys)
-{
-        sys->mem_offset = 0xe0000000;
-        if (machine_is_ixdp2801() || machine_is_ixdp28x5())
-                sys->mem_offset -= ((*IXP2000_PCI_ADDR_EXT & 0xE000) << 16);
-        return ixp2000_pci_setup(nr, sys);
-}
-struct hw_pci ixdp2x01_pci __initdata = {
-        .nr_controllers = 1,
-        .setup          = ixdp2x01_pci_setup,
-        .preinit        = ixdp2x01_pci_preinit,
-        .scan           = ixp2000_pci_scan_bus,
-        .map_irq        = ixdp2x01_pci_map_irq,
-};
-int __init ixdp2x01_pci_init(void)
-{
-        if (machine_is_ixdp2401() || machine_is_ixdp2801() ||\
-                machine_is_ixdp28x5())
-                pci_common_init(&ixdp2x01_pci);
-        return 0;
-}
-subsys_initcall(ixdp2x01_pci_init);
-/*************************************************************************
- * IXDP2x01 Machine Initialization
- *************************************************************************/
-static struct flash_platform_data ixdp2x01_flash_platform_data = {
-        .map_name       = "cfi_probe",
-        .width          = 1,
-};
-static unsigned long ixdp2x01_flash_bank_setup(unsigned long ofs)
-{
-        ixp2000_reg_wrb(IXDP2X01_CPLD_FLASH_REG,
-                ((ofs >> IXDP2X01_FLASH_WINDOW_BITS) | IXDP2X01_CPLD_FLASH_INTERN));
-        return (ofs & IXDP2X01_FLASH_WINDOW_MASK);
-}
-static struct ixp2000_flash_data ixdp2x01_flash_data = {
-        .platform_data  = &ixdp2x01_flash_platform_data,
-        .bank_setup     = ixdp2x01_flash_bank_setup
-};
-static struct resource ixdp2x01_flash_resource = {
-        .start          = 0xc4000000,
-        .end            = 0xc4000000 + 0x01ffffff,
-        .flags          = IORESOURCE_MEM,
-};
-static struct platform_device ixdp2x01_flash = {
-        .name           = "IXP2000-Flash",
-        .id             = 0,
-        .dev            = {
-                .platform_data = &ixdp2x01_flash_data,
-        },
-        .num_resources  = 1,
-        .resource       = &ixdp2x01_flash_resource,
-};
-static struct ixp2000_i2c_pins ixdp2x01_i2c_gpio_pins = {
-        .sda_pin        = IXDP2X01_GPIO_SDA,
-        .scl_pin        = IXDP2X01_GPIO_SCL,
-};
-static struct platform_device ixdp2x01_i2c_controller = {
-        .name           = "IXP2000-I2C",
-        .id             = 0,
-        .dev            = {
-                .platform_data = &ixdp2x01_i2c_gpio_pins,
-        },
-        .num_resources  = 0
-};
-static struct platform_device *ixdp2x01_devices[] __initdata = {
-        &ixdp2x01_flash,
-        &ixdp2x01_i2c_controller
-};
-static void __init ixdp2x01_init_machine(void)
-{
-        ixp2000_reg_wrb(IXDP2X01_CPLD_FLASH_REG,
-                (IXDP2X01_CPLD_FLASH_BANK_MASK | IXDP2X01_CPLD_FLASH_INTERN));
-        
-        ixdp2x01_flash_data.nr_banks =
-                ((*IXDP2X01_CPLD_FLASH_REG & IXDP2X01_CPLD_FLASH_BANK_MASK) + 1);
-        platform_add_devices(ixdp2x01_devices, ARRAY_SIZE(ixdp2x01_devices));
-        ixp2000_uart_init();
-        ixdp2x01_uart_init();
-}
-static void ixdp2401_restart(char mode, const char *cmd)
-{
-        /*
-         * Reset flash banking register so that we are pointing at
-         * RedBoot bank.
-         */
-        ixp2000_reg_write(IXDP2X01_CPLD_FLASH_REG,
-                                ((0 >> IXDP2X01_FLASH_WINDOW_BITS)
-                                        | IXDP2X01_CPLD_FLASH_INTERN));
-        ixp2000_reg_wrb(IXDP2X01_CPLD_RESET_REG, 0xffffffff);
-        ixp2000_restart(mode, cmd);
-}
-static void ixdp280x_restart(char mode, const char *cmd)
-{
-        /*
-         * On IXDP2801 we need to write this magic sequence to the CPLD
-         * to cause a complete reset of the CPU and all external devices
-         * and move the flash bank register back to 0.
-         */
-        unsigned long reset_reg = *IXDP2X01_CPLD_RESET_REG;
-        reset_reg = 0x55AA0000 | (reset_reg & 0x0000FFFF);
-        ixp2000_reg_write(IXDP2X01_CPLD_RESET_REG, reset_reg);
-        ixp2000_reg_wrb(IXDP2X01_CPLD_RESET_REG, 0x80000000);
-        ixp2000_restart(mode, cmd);
-}
-#ifdef CONFIG_ARCH_IXDP2401
-MACHINE_START(IXDP2401, "Intel IXDP2401 Development Platform")
-        /* Maintainer: MontaVista Software, Inc. */
-        .atag_offset    = 0x100,
-        .map_io         = ixdp2x01_map_io,
-        .init_irq       = ixdp2x01_init_irq,
-        .timer          = &ixdp2x01_timer,
-        .init_machine   = ixdp2x01_init_machine,
-        .restart        = ixdp2401_restart,
-MACHINE_END
-#endif
-#ifdef CONFIG_ARCH_IXDP2801
-MACHINE_START(IXDP2801, "Intel IXDP2801 Development Platform")
-        /* Maintainer: MontaVista Software, Inc. */
-        .atag_offset    = 0x100,
-        .map_io         = ixdp2x01_map_io,
-        .init_irq       = ixdp2x01_init_irq,
-        .timer          = &ixdp2x01_timer,
-        .init_machine   = ixdp2x01_init_machine,
-        .restart        = ixdp280x_restart,
-MACHINE_END
-/*
- * IXDP28x5 is basically an IXDP2801 with a different CPU but Intel
- * changed the machine ID in the bootloader
- */
-MACHINE_START(IXDP28X5, "Intel IXDP2805/2855 Development Platform")
-        /* Maintainer: MontaVista Software, Inc. */
-        .atag_offset    = 0x100,
-        .map_io         = ixdp2x01_map_io,
-        .init_irq       = ixdp2x01_init_irq,
-        .timer          = &ixdp2x01_timer,
-        .init_machine   = ixdp2x01_init_machine,
-        .restart        = ixdp280x_restart,
-MACHINE_END
-#endif
diff --git a/arch/arm/mach-ixp2000/pci.c b/arch/arm/mach-ixp2000/pci.c
deleted file mode 100644
index 9c02de932fac..000000000000
--- a/arch/arm/mach-ixp2000/pci.c
+++ /dev/null
@@ -1,252 +0,0 @@
-/*
- * arch/arm/mach-ixp2000/pci.c
- *
- * PCI routines for IXDP2400/IXDP2800 boards
- *
- * Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
- * Maintained by: Deepak Saxena <dsaxena@plexity.net>
- *
- * Copyright 2002 Intel Corp.
- * Copyright (C) 2003-2004 MontaVista Software, Inc.
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- */
-#include <linux/sched.h>
-#include <linux/kernel.h>
-#include <linux/pci.h>
-#include <linux/interrupt.h>
-#include <linux/mm.h>
-#include <linux/init.h>
-#include <linux/ioport.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <asm/irq.h>
-#include <mach/hardware.h>
-#include <asm/mach/pci.h>
-static volatile int pci_master_aborts = 0;
-static int clear_master_aborts(void);
-u32 *
-ixp2000_pci_config_addr(unsigned int bus_nr, unsigned int devfn, int where)
-{
-        u32 *paddress;
-        if (PCI_SLOT(devfn) > 7)
-                return 0;
-        /* Must be dword aligned */
-        where &= ~3;
-        /*
-         * For top bus, generate type 0, else type 1
-         */
-        if (!bus_nr) {
-                /* only bits[23:16] are used for IDSEL */
-                paddress = (u32 *) (IXP2000_PCI_CFG0_VIRT_BASE
-                                    | (1 << (PCI_SLOT(devfn) + 16))
-                                    | (PCI_FUNC(devfn) << 8) | where);
-        } else {
-                paddress = (u32 *) (IXP2000_PCI_CFG1_VIRT_BASE 
-                                    | (bus_nr << 16)
-                                    | (PCI_SLOT(devfn) << 11)
-                                    | (PCI_FUNC(devfn) << 8) | where);
-        }
-        return paddress;
-}
-/*
- * Mask table, bits to mask for quantity of size 1, 2 or 4 bytes.
- * 0 and 3 are not valid indexes...
- */
-static u32 bytemask[] = {
-        /*0*/   0,
-        /*1*/   0xff,
-        /*2*/   0xffff,
-        /*3*/   0,
-        /*4*/   0xffffffff,
-};
-int ixp2000_pci_read_config(struct pci_bus *bus, unsigned int devfn, int where,
-                                int size, u32 *value)
-{
-        u32 n;
-        u32 *addr;
-        n = where % 4;
-        addr = ixp2000_pci_config_addr(bus->number, devfn, where);
-        if (!addr)
-                return PCIBIOS_DEVICE_NOT_FOUND;
-        pci_master_aborts = 0;
-        *value = (*addr >> (8*n)) & bytemask[size];
-        if (pci_master_aborts) {
-                pci_master_aborts = 0;
-                *value = 0xffffffff;
-                return PCIBIOS_DEVICE_NOT_FOUND;
-        }
-        return PCIBIOS_SUCCESSFUL;
-}
-/*
- * We don't do error checks by calling clear_master_aborts() b/c the
- * assumption is that the caller did a read first to make sure a device
- * exists.
- */
-int ixp2000_pci_write_config(struct pci_bus *bus, unsigned int devfn, int where,
-                                int size, u32 value)
-{
-        u32 mask;
-        u32 *addr;
-        u32 temp;
-        mask = ~(bytemask[size] << ((where % 0x4) * 8));
-        addr = ixp2000_pci_config_addr(bus->number, devfn, where);
-        if (!addr)
-                return PCIBIOS_DEVICE_NOT_FOUND;
-        temp = (u32) (value) << ((where % 0x4) * 8);
-        *addr = (*addr & mask) | temp;
-        clear_master_aborts();
-        return PCIBIOS_SUCCESSFUL;
-}
-static struct pci_ops ixp2000_pci_ops = {
-        .read   = ixp2000_pci_read_config,
-        .write  = ixp2000_pci_write_config
-};
-struct pci_bus *ixp2000_pci_scan_bus(int nr, struct pci_sys_data *sysdata)
-{
-        return pci_scan_root_bus(NULL, sysdata->busnr, &ixp2000_pci_ops,
-                                 sysdata, &sysdata->resources);
-}
-int ixp2000_pci_abort_handler(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
-{
-        volatile u32 temp;
-        unsigned long flags;
-        pci_master_aborts = 1;
-        local_irq_save(flags);
-        temp = *(IXP2000_PCI_CONTROL);
-        if (temp & ((1 << 8) | (1 << 5))) {
-                ixp2000_reg_wrb(IXP2000_PCI_CONTROL, temp);
-        }
-        temp = *(IXP2000_PCI_CMDSTAT);
-        if (temp & (1 << 29)) {
-                while (temp & (1 << 29)) {      
-                        ixp2000_reg_write(IXP2000_PCI_CMDSTAT, temp);
-                        temp = *(IXP2000_PCI_CMDSTAT);
-                }
-        }
-        local_irq_restore(flags);
-        /*
-         * If it was an imprecise abort, then we need to correct the
-         * return address to be _after_ the instruction.
-         */
-        if (fsr & (1 << 10))
-                regs->ARM_pc += 4;
-        return 0;
-}
-int
-clear_master_aborts(void)
-{
-        volatile u32 temp;
-        unsigned long flags;
-        local_irq_save(flags);
-        temp = *(IXP2000_PCI_CONTROL);
-        if (temp & ((1 << 8) | (1 << 5))) {
-                ixp2000_reg_wrb(IXP2000_PCI_CONTROL, temp);
-        }
-        temp = *(IXP2000_PCI_CMDSTAT);
-        if (temp & (1 << 29)) {
-                while (temp & (1 << 29)) {
-                        ixp2000_reg_write(IXP2000_PCI_CMDSTAT, temp);
-                        temp = *(IXP2000_PCI_CMDSTAT);
-                }
-        }
-        local_irq_restore(flags);
-        return 0;
-}
-void __init
-ixp2000_pci_preinit(void)
-{
-        pci_set_flags(0);
-        pcibios_min_io = 0;
-        pcibios_min_mem = 0;
-#ifndef CONFIG_IXP2000_SUPPORT_BROKEN_PCI_IO
-        /*
-         * Configure the PCI unit to properly byteswap I/O transactions,
-         * and verify that it worked.
-         */
-        ixp2000_reg_write(IXP2000_PCI_CONTROL,
-                          (*IXP2000_PCI_CONTROL | PCI_CONTROL_IEE));
-        if ((*IXP2000_PCI_CONTROL & PCI_CONTROL_IEE) == 0)
-                panic("IXP2000: PCI I/O is broken on this ixp model, and "
-                        "the needed workaround has not been configured in");
-#endif
-        hook_fault_code(16+6, ixp2000_pci_abort_handler, SIGBUS, 0,
-                                "PCI config cycle to non-existent device");
-}
-/*
- * IXP2000 systems often have large resource requirements, so we just
- * use our own resource space.
- */
-static struct resource ixp2000_pci_mem_space = {
-        .start  = 0xe0000000,
-        .end    = 0xffffffff,
-        .flags  = IORESOURCE_MEM,
-        .name   = "PCI Mem Space"
-};
-static struct resource ixp2000_pci_io_space = {
-        .start  = 0x00010000,
-        .end    = 0x0001ffff,
-        .flags  = IORESOURCE_IO,
-        .name   = "PCI I/O Space"
-};
-int ixp2000_pci_setup(int nr, struct pci_sys_data *sys)
-{
-        if (nr >= 1)
-                return 0;
-        pci_add_resource_offset(&sys->resources,
-                                &ixp2000_pci_io_space, sys->io_offset);
-        pci_add_resource_offset(&sys->resources,
-                                &ixp2000_pci_mem_space, sys->mem_offset);
-        return 1;
-}
diff --git a/arch/arm/mach-ixp23xx/Kconfig b/arch/arm/mach-ixp23xx/Kconfig
deleted file mode 100644
index 982670ec3866..000000000000
--- a/arch/arm/mach-ixp23xx/Kconfig
+++ /dev/null
@@ -1,25 +0,0 @@
-if ARCH_IXP23XX
-config ARCH_SUPPORTS_BIG_ENDIAN
-        bool
-        default y
-menu "Intel IXP23xx Implementation Options"
-comment "IXP23xx Platforms"
-config MACH_ESPRESSO
-        bool "Support IP Fabrics Double Espresso platform"
-        help
-config MACH_IXDP2351
-        bool "Support Intel IXDP2351 platform"
-        help
-config MACH_ROADRUNNER
-        bool "Support ADI RoadRunner platform"
-        help
-endmenu
-endif
diff --git a/arch/arm/mach-ixp23xx/Makefile b/arch/arm/mach-ixp23xx/Makefile
deleted file mode 100644
index 288b371b6d03..000000000000
--- a/arch/arm/mach-ixp23xx/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Makefile for the linux kernel.
-#
-obj-y                   := core.o pci.o
-obj-m                   :=
-obj-n                   :=
-obj-                    :=
-obj-$(CONFIG_MACH_ESPRESSO)     += espresso.o
-obj-$(CONFIG_MACH_IXDP2351)     += ixdp2351.o
-obj-$(CONFIG_MACH_ROADRUNNER)   += roadrunner.o
diff --git a/arch/arm/mach-ixp23xx/Makefile.boot b/arch/arm/mach-ixp23xx/Makefile.boot
deleted file mode 100644
index 44fb4a717c3f..000000000000
--- a/arch/arm/mach-ixp23xx/Makefile.boot
+++ /dev/null
@@ -1,2 +0,0 @@
-   zreladdr-y   += 0x00008000
-params_phys-y   := 0x00000100
diff --git a/arch/arm/mach-ixp23xx/core.c b/arch/arm/mach-ixp23xx/core.c
deleted file mode 100644
index d34542425990..000000000000
--- a/arch/arm/mach-ixp23xx/core.c
+++ /dev/null
@@ -1,455 +0,0 @@
-/*
- * arch/arm/mach-ixp23xx/core.c
- *
- * Core routines for IXP23xx chips
- *
- * Author: Deepak Saxena <dsaxena@plexity.net>
- *
- * Copyright 2005 (c) MontaVista Software, Inc.
- *
- * Based on 2.4 code Copyright 2004 (c) Intel Corporation
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/spinlock.h>
-#include <linux/sched.h>
-#include <linux/interrupt.h>
-#include <linux/serial.h>
-#include <linux/tty.h>
-#include <linux/bitops.h>
-#include <linux/serial_8250.h>
-#include <linux/serial_core.h>
-#include <linux/device.h>
-#include <linux/mm.h>
-#include <linux/time.h>
-#include <linux/timex.h>
-#include <asm/types.h>
-#include <asm/setup.h>
-#include <asm/memory.h>
-#include <mach/hardware.h>
-#include <asm/irq.h>
-#include <asm/tlbflush.h>
-#include <asm/pgtable.h>
-#include <asm/system_misc.h>
-#include <asm/mach/map.h>
-#include <asm/mach/time.h>
-#include <asm/mach/irq.h>
-#include <asm/mach/arch.h>
-/*************************************************************************
- * Chip specific mappings shared by all IXP23xx systems
- *************************************************************************/
-static struct map_desc ixp23xx_io_desc[] __initdata = {
-        { /* XSI-CPP CSRs */
-                .virtual        = IXP23XX_XSI2CPP_CSR_VIRT,
-                .pfn            = __phys_to_pfn(IXP23XX_XSI2CPP_CSR_PHYS),
-                .length         = IXP23XX_XSI2CPP_CSR_SIZE,
-                .type           = MT_DEVICE,
-        }, { /* Expansion Bus Config */
-                .virtual        = IXP23XX_EXP_CFG_VIRT,
-                .pfn            = __phys_to_pfn(IXP23XX_EXP_CFG_PHYS),
-                .length         = IXP23XX_EXP_CFG_SIZE,
-                .type           = MT_DEVICE,
-        }, { /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACS,.... */
-                .virtual        = IXP23XX_PERIPHERAL_VIRT,
-                .pfn            = __phys_to_pfn(IXP23XX_PERIPHERAL_PHYS),
-                .length         = IXP23XX_PERIPHERAL_SIZE,
-                .type           = MT_DEVICE,
-        }, { /* CAP CSRs */
-                .virtual        = IXP23XX_CAP_CSR_VIRT,
-                .pfn            = __phys_to_pfn(IXP23XX_CAP_CSR_PHYS),
-                .length         = IXP23XX_CAP_CSR_SIZE,
-                .type           = MT_DEVICE,
-        }, { /* MSF CSRs */
-                .virtual        = IXP23XX_MSF_CSR_VIRT,
-                .pfn            = __phys_to_pfn(IXP23XX_MSF_CSR_PHYS),
-                .length         = IXP23XX_MSF_CSR_SIZE,
-                .type           = MT_DEVICE,
-        }, { /* PCI I/O Space */
-                .virtual        = IXP23XX_PCI_IO_VIRT,
-                .pfn            = __phys_to_pfn(IXP23XX_PCI_IO_PHYS),
-                .length         = IXP23XX_PCI_IO_SIZE,
-                .type           = MT_DEVICE,
-        }, { /* PCI Config Space */
-                .virtual        = IXP23XX_PCI_CFG_VIRT,
-                .pfn            = __phys_to_pfn(IXP23XX_PCI_CFG_PHYS),
-                .length         = IXP23XX_PCI_CFG_SIZE,
-                .type           = MT_DEVICE,
-        }, { /* PCI local CFG CSRs */
-                .virtual        = IXP23XX_PCI_CREG_VIRT,
-                .pfn            = __phys_to_pfn(IXP23XX_PCI_CREG_PHYS),
-                .length         = IXP23XX_PCI_CREG_SIZE,
-                .type           = MT_DEVICE,
-        }, { /* PCI MEM Space */
-                .virtual        = IXP23XX_PCI_MEM_VIRT,
-                .pfn            = __phys_to_pfn(IXP23XX_PCI_MEM_PHYS),
-                .length         = IXP23XX_PCI_MEM_SIZE,
-                .type           = MT_DEVICE,
-        }
-};
-void __init ixp23xx_map_io(void)
-{
-        iotable_init(ixp23xx_io_desc, ARRAY_SIZE(ixp23xx_io_desc));
-}
-/***************************************************************************
- * IXP23xx Interrupt Handling
- ***************************************************************************/
-enum ixp23xx_irq_type {
-        IXP23XX_IRQ_LEVEL, IXP23XX_IRQ_EDGE
-};
-static void ixp23xx_config_irq(unsigned int, enum ixp23xx_irq_type);
-static int ixp23xx_irq_set_type(struct irq_data *d, unsigned int type)
-{
-        int line = d->irq - IRQ_IXP23XX_GPIO6 + 6;
-        u32 int_style;
-        enum ixp23xx_irq_type irq_type;
-        volatile u32 *int_reg;
-        /*
-         * Only GPIOs 6-15 are wired to interrupts on IXP23xx
-         */
-        if (line < 6 || line > 15)
-                return -EINVAL;
-        switch (type) {
-        case IRQ_TYPE_EDGE_BOTH:
-                int_style = IXP23XX_GPIO_STYLE_TRANSITIONAL;
-                irq_type = IXP23XX_IRQ_EDGE;
-                break;
-        case IRQ_TYPE_EDGE_RISING:
-                int_style = IXP23XX_GPIO_STYLE_RISING_EDGE;
-                irq_type = IXP23XX_IRQ_EDGE;
-                break;
-        case IRQ_TYPE_EDGE_FALLING:
-                int_style = IXP23XX_GPIO_STYLE_FALLING_EDGE;
-                irq_type = IXP23XX_IRQ_EDGE;
-                break;
-        case IRQ_TYPE_LEVEL_HIGH:
-                int_style = IXP23XX_GPIO_STYLE_ACTIVE_HIGH;
-                irq_type = IXP23XX_IRQ_LEVEL;
-                break;
-        case IRQ_TYPE_LEVEL_LOW:
-                int_style = IXP23XX_GPIO_STYLE_ACTIVE_LOW;
-                irq_type = IXP23XX_IRQ_LEVEL;
-                break;
-        default:
-                return -EINVAL;
-        }
-        ixp23xx_config_irq(d->irq, irq_type);
-        if (line >= 8) {        /* pins 8-15 */
-                line -= 8;
-                int_reg = (volatile u32 *)IXP23XX_GPIO_GPIT2R;
-        } else {                /* pins 0-7 */
-                int_reg = (volatile u32 *)IXP23XX_GPIO_GPIT1R;
-        }
-        /*
-         * Clear pending interrupts
-         */
-        *IXP23XX_GPIO_GPISR = (1 << line);
-        /* Clear the style for the appropriate pin */
-        *int_reg &= ~(IXP23XX_GPIO_STYLE_MASK <<
-                        (line * IXP23XX_GPIO_STYLE_SIZE));
-        /* Set the new style */
-        *int_reg |= (int_style << (line * IXP23XX_GPIO_STYLE_SIZE));
-        return 0;
-}
-static void ixp23xx_irq_mask(struct irq_data *d)
-{
-        volatile unsigned long *intr_reg;
-        unsigned int irq = d->irq;
-        if (irq >= 56)
-                irq += 8;
-        intr_reg = IXP23XX_INTR_EN1 + (irq / 32);
-        *intr_reg &= ~(1 << (irq % 32));
-}
-static void ixp23xx_irq_ack(struct irq_data *d)
-{
-        int line = d->irq - IRQ_IXP23XX_GPIO6 + 6;
-        if ((line < 6) || (line > 15))
-                return;
-        *IXP23XX_GPIO_GPISR = (1 << line);
-}
-/*
- * Level triggered interrupts on GPIO lines can only be cleared when the
- * interrupt condition disappears.
- */
-static void ixp23xx_irq_level_unmask(struct irq_data *d)
-{
-        volatile unsigned long *intr_reg;
-        unsigned int irq = d->irq;
-        ixp23xx_irq_ack(d);
-        if (irq >= 56)
-                irq += 8;
-        intr_reg = IXP23XX_INTR_EN1 + (irq / 32);
-        *intr_reg |= (1 << (irq % 32));
-}
-static void ixp23xx_irq_edge_unmask(struct irq_data *d)
-{
-        volatile unsigned long *intr_reg;
-        unsigned int irq = d->irq;
-        if (irq >= 56)
-                irq += 8;
-        intr_reg = IXP23XX_INTR_EN1 + (irq / 32);
-        *intr_reg |= (1 << (irq % 32));
-}
-static struct irq_chip ixp23xx_irq_level_chip = {
-        .irq_ack        = ixp23xx_irq_mask,
-        .irq_mask       = ixp23xx_irq_mask,
-        .irq_unmask     = ixp23xx_irq_level_unmask,
-        .irq_set_type   = ixp23xx_irq_set_type
-};
-static struct irq_chip ixp23xx_irq_edge_chip = {
-        .irq_ack        = ixp23xx_irq_ack,
-        .irq_mask       = ixp23xx_irq_mask,
-        .irq_unmask     = ixp23xx_irq_edge_unmask,
-        .irq_set_type   = ixp23xx_irq_set_type
-};
-static void ixp23xx_pci_irq_mask(struct irq_data *d)
-{
-        unsigned int irq = d->irq;
-        *IXP23XX_PCI_XSCALE_INT_ENABLE &= ~(1 << (IRQ_IXP23XX_INTA + 27 - irq));
-}
-static void ixp23xx_pci_irq_unmask(struct irq_data *d)
-{
-        unsigned int irq = d->irq;
-        *IXP23XX_PCI_XSCALE_INT_ENABLE |= (1 << (IRQ_IXP23XX_INTA + 27 - irq));
-}
-/*
- * TODO: Should this just be done at ASM level?
- */
-static void pci_handler(unsigned int irq, struct irq_desc *desc)
-{
-        u32 pci_interrupt;
-        unsigned int irqno;
-        pci_interrupt = *IXP23XX_PCI_XSCALE_INT_STATUS;
-        desc->irq_data.chip->irq_ack(&desc->irq_data);
-        /* See which PCI_INTA, or PCI_INTB interrupted */
-        if (pci_interrupt & (1 << 26)) {
-                irqno = IRQ_IXP23XX_INTB;
-        } else if (pci_interrupt & (1 << 27)) {
-                irqno = IRQ_IXP23XX_INTA;
-        } else {
-                BUG();
-        }
-        generic_handle_irq(irqno);
-        desc->irq_data.chip->irq_unmask(&desc->irq_data);
-}
-static struct irq_chip ixp23xx_pci_irq_chip = {
-        .irq_ack        = ixp23xx_pci_irq_mask,
-        .irq_mask       = ixp23xx_pci_irq_mask,
-        .irq_unmask     = ixp23xx_pci_irq_unmask
-};
-static void ixp23xx_config_irq(unsigned int irq, enum ixp23xx_irq_type type)
-{
-        switch (type) {
-        case IXP23XX_IRQ_LEVEL:
-                irq_set_chip_and_handler(irq, &ixp23xx_irq_level_chip,
-                                         handle_level_irq);
-                break;
-        case IXP23XX_IRQ_EDGE:
-                irq_set_chip_and_handler(irq, &ixp23xx_irq_edge_chip,
-                                         handle_edge_irq);
-                break;
-        }
-        set_irq_flags(irq, IRQF_VALID);
-}
-void __init ixp23xx_init_irq(void)
-{
-        int irq;
-        /* Route everything to IRQ */
-        *IXP23XX_INTR_SEL1 = 0x0;
-        *IXP23XX_INTR_SEL2 = 0x0;
-        *IXP23XX_INTR_SEL3 = 0x0;
-        *IXP23XX_INTR_SEL4 = 0x0;
-        /* Mask all sources */
-        *IXP23XX_INTR_EN1 = 0x0;
-        *IXP23XX_INTR_EN2 = 0x0;
-        *IXP23XX_INTR_EN3 = 0x0;
-        *IXP23XX_INTR_EN4 = 0x0;
-        /*
-         * Configure all IRQs for level-sensitive operation
-         */
-        for (irq = 0; irq <= NUM_IXP23XX_RAW_IRQS; irq++) {
-                ixp23xx_config_irq(irq, IXP23XX_IRQ_LEVEL);
-        }
-        for (irq = IRQ_IXP23XX_INTA; irq <= IRQ_IXP23XX_INTB; irq++) {
-                irq_set_chip_and_handler(irq, &ixp23xx_pci_irq_chip,
-                                         handle_level_irq);
-                set_irq_flags(irq, IRQF_VALID);
-        }
-        irq_set_chained_handler(IRQ_IXP23XX_PCI_INT_RPH, pci_handler);
-}
-/*************************************************************************
- * Timer-tick functions for IXP23xx
- *************************************************************************/
-#define CLOCK_TICKS_PER_USEC    (CLOCK_TICK_RATE / USEC_PER_SEC)
-static unsigned long next_jiffy_time;
-static unsigned long
-ixp23xx_gettimeoffset(void)
-{
-        unsigned long elapsed;
-        elapsed = *IXP23XX_TIMER_CONT - (next_jiffy_time - LATCH);
-        return elapsed / CLOCK_TICKS_PER_USEC;
-}
-static irqreturn_t
-ixp23xx_timer_interrupt(int irq, void *dev_id)
-{
-        /* Clear Pending Interrupt by writing '1' to it */
-        *IXP23XX_TIMER_STATUS = IXP23XX_TIMER1_INT_PEND;
-        while ((signed long)(*IXP23XX_TIMER_CONT - next_jiffy_time) >= LATCH) {
-                timer_tick();
-                next_jiffy_time += LATCH;
-        }
-        return IRQ_HANDLED;
-}
-static struct irqaction ixp23xx_timer_irq = {
-        .name           = "IXP23xx Timer Tick",
-        .handler        = ixp23xx_timer_interrupt,
-        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-};
-void __init ixp23xx_init_timer(void)
-{
-        /* Clear Pending Interrupt by writing '1' to it */
-        *IXP23XX_TIMER_STATUS = IXP23XX_TIMER1_INT_PEND;
-        /* Setup the Timer counter value */
-        *IXP23XX_TIMER1_RELOAD =
-                (LATCH & ~IXP23XX_TIMER_RELOAD_MASK) | IXP23XX_TIMER_ENABLE;
-        *IXP23XX_TIMER_CONT = 0;
-        next_jiffy_time = LATCH;
-        /* Connect the interrupt handler and enable the interrupt */
-        setup_irq(IRQ_IXP23XX_TIMER1, &ixp23xx_timer_irq);
-}
-struct sys_timer ixp23xx_timer = {
-        .init           = ixp23xx_init_timer,
-        .offset         = ixp23xx_gettimeoffset,
-};
-/*************************************************************************
- * IXP23xx Platform Initialization
- *************************************************************************/
-static struct resource ixp23xx_uart_resources[] = {
-        {
-                .start          = IXP23XX_UART1_PHYS,
-                .end            = IXP23XX_UART1_PHYS + 0x0fff,
-                .flags          = IORESOURCE_MEM
-        }, {
-                .start          = IXP23XX_UART2_PHYS,
-                .end            = IXP23XX_UART2_PHYS + 0x0fff,
-                .flags          = IORESOURCE_MEM
-        }
-};
-static struct plat_serial8250_port ixp23xx_uart_data[] = {
-        {
-                .mapbase        = IXP23XX_UART1_PHYS,
-                .membase        = (char *)(IXP23XX_UART1_VIRT + 3),
-                .irq            = IRQ_IXP23XX_UART1,
-                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
-                .iotype         = UPIO_MEM,
-                .regshift       = 2,
-                .uartclk        = IXP23XX_UART_XTAL,
-        }, {
-                .mapbase        = IXP23XX_UART2_PHYS,
-                .membase        = (char *)(IXP23XX_UART2_VIRT + 3),
-                .irq            = IRQ_IXP23XX_UART2,
-                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
-                .iotype         = UPIO_MEM,
-                .regshift       = 2,
-                .uartclk        = IXP23XX_UART_XTAL,
-        },
-        { },
-};
-static struct platform_device ixp23xx_uart = {
-        .name                   = "serial8250",
-        .id                     = 0,
-        .dev.platform_data      = ixp23xx_uart_data,
-        .num_resources          = 2,
-        .resource               = ixp23xx_uart_resources,
-};
-static struct platform_device *ixp23xx_devices[] __initdata = {
-        &ixp23xx_uart,
-};
-void __init ixp23xx_sys_init(void)
-{
-        /* by default, the idle code is disabled */
-        disable_hlt();
-        *IXP23XX_EXP_UNIT_FUSE |= 0xf;
-        platform_add_devices(ixp23xx_devices, ARRAY_SIZE(ixp23xx_devices));
-}
-void ixp23xx_restart(char mode, const char *cmd)
-{
-        /* Use on-chip reset capability */
-        *IXP23XX_RESET0 |= IXP23XX_RST_ALL;
-}
diff --git a/arch/arm/mach-ixp23xx/espresso.c b/arch/arm/mach-ixp23xx/espresso.c
deleted file mode 100644
index d142d45dea12..000000000000
--- a/arch/arm/mach-ixp23xx/espresso.c
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * arch/arm/mach-ixp23xx/espresso.c
- *
- * Double Espresso-specific routines
- *
- * Author: Lennert Buytenhek <buytenh@wantstofly.org>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/spinlock.h>
-#include <linux/sched.h>
-#include <linux/interrupt.h>
-#include <linux/serial.h>
-#include <linux/tty.h>
-#include <linux/bitops.h>
-#include <linux/ioport.h>
-#include <linux/serial_8250.h>
-#include <linux/serial_core.h>
-#include <linux/device.h>
-#include <linux/mm.h>
-#include <linux/pci.h>
-#include <linux/mtd/physmap.h>
-#include <asm/types.h>
-#include <asm/setup.h>
-#include <asm/memory.h>
-#include <mach/hardware.h>
-#include <asm/mach-types.h>
-#include <asm/irq.h>
-#include <asm/tlbflush.h>
-#include <asm/pgtable.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/pci.h>
-static int __init espresso_pci_init(void)
-{
-        if (machine_is_espresso())
-                ixp23xx_pci_slave_init();
-        return 0;
-};
-subsys_initcall(espresso_pci_init);
-static struct physmap_flash_data espresso_flash_data = {
-        .width          = 2,
-};
-static struct resource espresso_flash_resource = {
-        .start          = 0x90000000,
-        .end            = 0x91ffffff,
-        .flags          = IORESOURCE_MEM,
-};
-static struct platform_device espresso_flash = {
-        .name           = "physmap-flash",
-        .id             = 0,
-        .dev            = {
-                .platform_data  = &espresso_flash_data,
-        },
-        .num_resources  = 1,
-        .resource       = &espresso_flash_resource,
-};
-static void __init espresso_init(void)
-{
-        platform_device_register(&espresso_flash);
-        /*
-         * Mark flash as writeable.
-         */
-        IXP23XX_EXP_CS0[0] |= IXP23XX_FLASH_WRITABLE;
-        IXP23XX_EXP_CS0[1] |= IXP23XX_FLASH_WRITABLE;
-        ixp23xx_sys_init();
-}
-MACHINE_START(ESPRESSO, "IP Fabrics Double Espresso")
-        /* Maintainer: Lennert Buytenhek */
-        .map_io         = ixp23xx_map_io,
-        .init_irq       = ixp23xx_init_irq,
-        .timer          = &ixp23xx_timer,
-        .atag_offset    = 0x100,
-        .init_machine   = espresso_init,
-        .restart        = ixp23xx_restart,
-MACHINE_END
diff --git a/arch/arm/mach-ixp23xx/include/mach/debug-macro.S b/arch/arm/mach-ixp23xx/include/mach/debug-macro.S
deleted file mode 100644
index 5ff524c13744..000000000000
--- a/arch/arm/mach-ixp23xx/include/mach/debug-macro.S
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * arch/arm/mach-ixp23xx/include/mach/debug-macro.S
- *
- * Debugging macro include header
- *
- * Copyright (C) 1994-1999 Russell King
- * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <mach/ixp23xx.h>
-                .macro  addruart, rp, rv, tmp
-                ldr     \rp, =IXP23XX_PERIPHERAL_PHYS   @ physical
-                ldr     \rv, =IXP23XX_PERIPHERAL_VIRT   @ virtual
-#ifdef __ARMEB__
-                orr     \rp, \rp, #0x00000003
-                orr     \rv, \rv, #0x00000003
-#endif
-                .endm
-#define UART_SHIFT      2
-#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/mach-ixp23xx/include/mach/entry-macro.S b/arch/arm/mach-ixp23xx/include/mach/entry-macro.S
deleted file mode 100644
index 3fd2cb984e42..000000000000
--- a/arch/arm/mach-ixp23xx/include/mach/entry-macro.S
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * arch/arm/mach-ixp23xx/include/mach/entry-macro.S
- */
-                .macro  get_irqnr_preamble, base, tmp
-                .endm
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                ldr     \irqnr, =(IXP23XX_INTC_VIRT + IXP23XX_INTR_IRQ_ENC_ST_OFFSET)
-                ldr     \irqnr, [\irqnr]        @ get interrupt number
-                cmp     \irqnr, #0x0            @ spurious interrupt ?
-                movne   \irqnr, \irqnr, lsr #2  @ skip unwanted low order bits
-                subne   \irqnr, \irqnr, #1      @ convert to 0 based
-#if 0
-                cmp     \irqnr, #IRQ_IXP23XX_PCI_INT_RPH
-                bne     1001f
-                mov     \irqnr, #IRQ_IXP23XX_INTA
-                ldr     \irqnr, =0xf5000030
-                mov     \tmp, #(1<<26)
-                tst     \irqnr, \tmp
-                movne   \irqnr, #IRQ_IXP23XX_INTB
-                mov     \tmp, #(1<<27)
-                tst     \irqnr, \tmp
-                movne   \irqnr, #IRQ_IXP23XX_INTA
-1001:
-#endif
-                .endm
diff --git a/arch/arm/mach-ixp23xx/include/mach/hardware.h b/arch/arm/mach-ixp23xx/include/mach/hardware.h
deleted file mode 100644
index 60e55fa10238..000000000000
--- a/arch/arm/mach-ixp23xx/include/mach/hardware.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * arch/arm/mach-ixp23xx/include/mach/hardware.h
- *
- * Copyright (C) 2002-2004 Intel Corporation.
- * Copyricht (C) 2005 MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Hardware definitions for IXP23XX based systems
- */
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-/* PCI IO info */
-#include "ixp23xx.h"
-/*
- * Platform helper functions
- */
-#include "platform.h"
-/*
- * Platform-specific headers
- */
-#include "ixdp2351.h"
-#endif
diff --git a/arch/arm/mach-ixp23xx/include/mach/io.h b/arch/arm/mach-ixp23xx/include/mach/io.h
deleted file mode 100644
index a7aceb55c130..000000000000
--- a/arch/arm/mach-ixp23xx/include/mach/io.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * arch/arm/mach-ixp23xx/include/mach/io.h
- *
- * Original Author: Naeem M Afzal <naeem.m.afzal@intel.com>
- * Maintainer: Deepak Saxena <dsaxena@plexity.net>
- *
- * Copyright (C) 2003-2005 Intel Corp.
- * Copyright (C) 2005 MontaVista Software, Inc
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __ASM_ARCH_IO_H
-#define __ASM_ARCH_IO_H
-#define IO_SPACE_LIMIT 0xffffffff
-#define __io(p)         ((void __iomem*)((p) + IXP23XX_PCI_IO_VIRT))
-#endif
diff --git a/arch/arm/mach-ixp23xx/include/mach/irqs.h b/arch/arm/mach-ixp23xx/include/mach/irqs.h
deleted file mode 100644
index 3af33a04b8a2..000000000000
--- a/arch/arm/mach-ixp23xx/include/mach/irqs.h
+++ /dev/null
@@ -1,223 +0,0 @@
-/*
- * arch/arm/mach-ixp23xx/include/mach/irqs.h
- *
- * IRQ definitions for IXP23XX based systems
- *
- * Author: Naeem Afzal <naeem.m.afzal@intel.com>
- *
- * Copyright (C) 2003-2004 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __ASM_ARCH_IRQS_H
-#define __ASM_ARCH_IRQS_H
-#define NR_IXP23XX_IRQS                 IRQ_IXP23XX_INTB+1
-#define IRQ_IXP23XX_EXTIRQS             NR_IXP23XX_IRQS
-#define IRQ_IXP23XX_DBG0                0       /* Debug/Execution/MBox */
-#define IRQ_IXP23XX_DBG1                1       /* Debug/Execution/MBox */
-#define IRQ_IXP23XX_NPE_TRG             2       /* npe_trigger */
-#define IRQ_IXP23XX_TIMER1              3       /* Timer[0] */
-#define IRQ_IXP23XX_TIMER2              4       /* Timer[1] */
-#define IRQ_IXP23XX_TIMESTAMP           5       /* Timer[2], Time-stamp */
-#define IRQ_IXP23XX_WDOG                6       /* Time[3], Watchdog Timer */
-#define IRQ_IXP23XX_PCI_DBELL           7       /* PCI Doorbell */
-#define IRQ_IXP23XX_PCI_DMA1            8       /* PCI DMA Channel 1 */
-#define IRQ_IXP23XX_PCI_DMA2            9       /* PCI DMA Channel 2 */
-#define IRQ_IXP23XX_PCI_DMA3            10      /* PCI DMA Channel 3 */
-#define IRQ_IXP23XX_PCI_INT_RPH         11      /* pcxg_pci_int_rph */
-#define IRQ_IXP23XX_CPP_PMU             12      /* xpxg_pm_int_rpl */
-#define IRQ_IXP23XX_SWINT0              13      /* S/W Interrupt0 */
-#define IRQ_IXP23XX_SWINT1              14      /* S/W Interrupt1 */
-#define IRQ_IXP23XX_UART2               15      /* UART1 Interrupt */
-#define IRQ_IXP23XX_UART1               16      /* UART0 Interrupt */
-#define IRQ_IXP23XX_XSI_PMU_ROLLOVER    17      /* AHB Performance M. Unit counter rollover */
-#define IRQ_IXP23XX_XSI_AHB_PM0         18      /* intr_pm_o */
-#define IRQ_IXP23XX_XSI_AHB_ECE0        19      /* intr_ece_o */
-#define IRQ_IXP23XX_XSI_AHB_GASKET      20      /* gas_intr_o */
-#define IRQ_IXP23XX_XSI_CPP             21      /* xsi2cpp_int */
-#define IRQ_IXP23XX_CPP_XSI             22      /* cpp2xsi_int */
-#define IRQ_IXP23XX_ME_ATTN0            23      /* ME_ATTN */
-#define IRQ_IXP23XX_ME_ATTN1            24      /* ME_ATTN */
-#define IRQ_IXP23XX_ME_ATTN2            25      /* ME_ATTN */
-#define IRQ_IXP23XX_ME_ATTN3            26      /* ME_ATTN */
-#define IRQ_IXP23XX_PCI_ERR_RPH         27      /* PCXG_PCI_ERR_RPH */
-#define IRQ_IXP23XX_D0XG_ECC_CORR       28      /* D0XG_DRAM_ECC_CORR */
-#define IRQ_IXP23XX_D0XG_ECC_UNCORR     29      /* D0XG_DRAM_ECC_UNCORR */
-#define IRQ_IXP23XX_SRAM_ERR1           30      /* SRAM1_ERR */
-#define IRQ_IXP23XX_SRAM_ERR0           31      /* SRAM0_ERR */
-#define IRQ_IXP23XX_MEDIA_ERR           32      /* MEDIA_ERR */
-#define IRQ_IXP23XX_STH_DRAM_ECC_MAJ    33      /* STH_DRAM0_ECC_MAJ */
-#define IRQ_IXP23XX_GPIO6               34      /* GPIO0 interrupts */
-#define IRQ_IXP23XX_GPIO7               35      /* GPIO1 interrupts */
-#define IRQ_IXP23XX_GPIO8               36      /* GPIO2 interrupts */
-#define IRQ_IXP23XX_GPIO9               37      /* GPIO3 interrupts */
-#define IRQ_IXP23XX_GPIO10              38      /* GPIO4 interrupts */
-#define IRQ_IXP23XX_GPIO11              39      /* GPIO5 interrupts */
-#define IRQ_IXP23XX_GPIO12              40      /* GPIO6 interrupts */
-#define IRQ_IXP23XX_GPIO13              41      /* GPIO7 interrupts */
-#define IRQ_IXP23XX_GPIO14              42      /* GPIO8 interrupts */
-#define IRQ_IXP23XX_GPIO15              43      /* GPIO9 interrupts */
-#define IRQ_IXP23XX_SHAC_RING0          44      /* SHAC Ring Full */
-#define IRQ_IXP23XX_SHAC_RING1          45      /* SHAC Ring Full */
-#define IRQ_IXP23XX_SHAC_RING2          46      /* SHAC Ring Full */
-#define IRQ_IXP23XX_SHAC_RING3          47      /* SHAC Ring Full */
-#define IRQ_IXP23XX_SHAC_RING4          48      /* SHAC Ring Full */
-#define IRQ_IXP23XX_SHAC_RING5          49      /* SHAC Ring Full */
-#define IRQ_IXP23XX_SHAC_RING6          50      /* SHAC RING Full */
-#define IRQ_IXP23XX_SHAC_RING7          51      /* SHAC Ring Full */
-#define IRQ_IXP23XX_SHAC_RING8          52      /* SHAC Ring Full */
-#define IRQ_IXP23XX_SHAC_RING9          53      /* SHAC Ring Full */
-#define IRQ_IXP23XX_SHAC_RING10         54      /* SHAC Ring Full */
-#define IRQ_IXP23XX_SHAC_RING11         55      /* SHAC Ring Full */
-#define IRQ_IXP23XX_ME_THREAD_A0_ME0    56      /* ME_THREAD_A */
-#define IRQ_IXP23XX_ME_THREAD_A1_ME0    57      /* ME_THREAD_A */
-#define IRQ_IXP23XX_ME_THREAD_A2_ME0    58      /* ME_THREAD_A */
-#define IRQ_IXP23XX_ME_THREAD_A3_ME0    59      /* ME_THREAD_A */
-#define IRQ_IXP23XX_ME_THREAD_A4_ME0    60      /* ME_THREAD_A */
-#define IRQ_IXP23XX_ME_THREAD_A5_ME0    61      /* ME_THREAD_A */
-#define IRQ_IXP23XX_ME_THREAD_A6_ME0    62      /* ME_THREAD_A */
-#define IRQ_IXP23XX_ME_THREAD_A7_ME0    63      /* ME_THREAD_A */
-#define IRQ_IXP23XX_ME_THREAD_A8_ME1    64      /* ME_THREAD_A */
-#define IRQ_IXP23XX_ME_THREAD_A9_ME1    65      /* ME_THREAD_A */
-#define IRQ_IXP23XX_ME_THREAD_A10_ME1   66      /* ME_THREAD_A */
-#define IRQ_IXP23XX_ME_THREAD_A11_ME1   67      /* ME_THREAD_A */
-#define IRQ_IXP23XX_ME_THREAD_A12_ME1   68      /* ME_THREAD_A */
-#define IRQ_IXP23XX_ME_THREAD_A13_ME1   69      /* ME_THREAD_A */
-#define IRQ_IXP23XX_ME_THREAD_A14_ME1   70      /* ME_THREAD_A */
-#define IRQ_IXP23XX_ME_THREAD_A15_ME1   71      /* ME_THREAD_A */
-#define IRQ_IXP23XX_ME_THREAD_A16_ME2   72      /* ME_THREAD_A */
-#define IRQ_IXP23XX_ME_THREAD_A17_ME2   73      /* ME_THREAD_A */
-#define IRQ_IXP23XX_ME_THREAD_A18_ME2   74      /* ME_THREAD_A */
-#define IRQ_IXP23XX_ME_THREAD_A19_ME2   75      /* ME_THREAD_A */
-#define IRQ_IXP23XX_ME_THREAD_A20_ME2   76      /* ME_THREAD_A */
-#define IRQ_IXP23XX_ME_THREAD_A21_ME2   77      /* ME_THREAD_A */
-#define IRQ_IXP23XX_ME_THREAD_A22_ME2   78      /* ME_THREAD_A */
-#define IRQ_IXP23XX_ME_THREAD_A23_ME2   79      /* ME_THREAD_A */
-#define IRQ_IXP23XX_ME_THREAD_A24_ME3   80      /* ME_THREAD_A */
-#define IRQ_IXP23XX_ME_THREAD_A25_ME3   81      /* ME_THREAD_A */
-#define IRQ_IXP23XX_ME_THREAD_A26_ME3   82      /* ME_THREAD_A */
-#define IRQ_IXP23XX_ME_THREAD_A27_ME3   83      /* ME_THREAD_A */
-#define IRQ_IXP23XX_ME_THREAD_A28_ME3   84      /* ME_THREAD_A */
-#define IRQ_IXP23XX_ME_THREAD_A29_ME3   85      /* ME_THREAD_A */
-#define IRQ_IXP23XX_ME_THREAD_A30_ME3   86      /* ME_THREAD_A */
-#define IRQ_IXP23XX_ME_THREAD_A31_ME3   87      /* ME_THREAD_A */
-#define IRQ_IXP23XX_ME_THREAD_B0_ME0    88      /* ME_THREAD_B */
-#define IRQ_IXP23XX_ME_THREAD_B1_ME0    89      /* ME_THREAD_B */
-#define IRQ_IXP23XX_ME_THREAD_B2_ME0    90      /* ME_THREAD_B */
-#define IRQ_IXP23XX_ME_THREAD_B3_ME0    91      /* ME_THREAD_B */
-#define IRQ_IXP23XX_ME_THREAD_B4_ME0    92      /* ME_THREAD_B */
-#define IRQ_IXP23XX_ME_THREAD_B5_ME0    93      /* ME_THREAD_B */
-#define IRQ_IXP23XX_ME_THREAD_B6_ME0    94      /* ME_THREAD_B */
-#define IRQ_IXP23XX_ME_THREAD_B7_ME0    95      /* ME_THREAD_B */
-#define IRQ_IXP23XX_ME_THREAD_B8_ME1    96      /* ME_THREAD_B */
-#define IRQ_IXP23XX_ME_THREAD_B9_ME1    97      /* ME_THREAD_B */
-#define IRQ_IXP23XX_ME_THREAD_B10_ME1   98      /* ME_THREAD_B */
-#define IRQ_IXP23XX_ME_THREAD_B11_ME1   99      /* ME_THREAD_B */
-#define IRQ_IXP23XX_ME_THREAD_B12_ME1   100     /* ME_THREAD_B */
-#define IRQ_IXP23XX_ME_THREAD_B13_ME1   101     /* ME_THREAD_B */
-#define IRQ_IXP23XX_ME_THREAD_B14_ME1   102     /* ME_THREAD_B */
-#define IRQ_IXP23XX_ME_THREAD_B15_ME1   103     /* ME_THREAD_B */
-#define IRQ_IXP23XX_ME_THREAD_B16_ME2   104     /* ME_THREAD_B */
-#define IRQ_IXP23XX_ME_THREAD_B17_ME2   105     /* ME_THREAD_B */
-#define IRQ_IXP23XX_ME_THREAD_B18_ME2   106     /* ME_THREAD_B */
-#define IRQ_IXP23XX_ME_THREAD_B19_ME2   107     /* ME_THREAD_B */
-#define IRQ_IXP23XX_ME_THREAD_B20_ME2   108     /* ME_THREAD_B */
-#define IRQ_IXP23XX_ME_THREAD_B21_ME2   109     /* ME_THREAD_B */
-#define IRQ_IXP23XX_ME_THREAD_B22_ME2   110     /* ME_THREAD_B */
-#define IRQ_IXP23XX_ME_THREAD_B23_ME2   111     /* ME_THREAD_B */
-#define IRQ_IXP23XX_ME_THREAD_B24_ME3   112     /* ME_THREAD_B */
-#define IRQ_IXP23XX_ME_THREAD_B25_ME3   113     /* ME_THREAD_B */
-#define IRQ_IXP23XX_ME_THREAD_B26_ME3   114     /* ME_THREAD_B */
-#define IRQ_IXP23XX_ME_THREAD_B27_ME3   115     /* ME_THREAD_B */
-#define IRQ_IXP23XX_ME_THREAD_B28_ME3   116     /* ME_THREAD_B */
-#define IRQ_IXP23XX_ME_THREAD_B29_ME3   117     /* ME_THREAD_B */
-#define IRQ_IXP23XX_ME_THREAD_B30_ME3   118     /* ME_THREAD_B */
-#define IRQ_IXP23XX_ME_THREAD_B31_ME3   119     /* ME_THREAD_B */
-#define NUM_IXP23XX_RAW_IRQS            120
-#define IRQ_IXP23XX_INTA                120     /* Indirect pcxg_pci_int_rph */
-#define IRQ_IXP23XX_INTB                121     /* Indirect pcxg_pci_int_rph */
-#define NR_IXP23XX_IRQ                  (IRQ_IXP23XX_INTB + 1)
-/*
- * We default to 32 per-board IRQs. Increase this number if you need
- * more, but keep it realistic.
- */
-#define NR_IXP23XX_MACH_IRQS            32
-#define NR_IRQS                         (NR_IXP23XX_IRQS + NR_IXP23XX_MACH_IRQS)
-#define IXP23XX_MACH_IRQ(irq)           (NR_IXP23XX_IRQ + (irq))
-/*
- * IXDP2351-specific interrupts
- */
-/*
- * External PCI interrupts signaled through INTB
- *
- */
-#define IXDP2351_INTB_IRQ_BASE          0
-#define IRQ_IXDP2351_INTA_82546         IXP23XX_MACH_IRQ(0)
-#define IRQ_IXDP2351_INTB_82546         IXP23XX_MACH_IRQ(1)
-#define IRQ_IXDP2351_SPCI_DB_0          IXP23XX_MACH_IRQ(2)
-#define IRQ_IXDP2351_SPCI_DB_1          IXP23XX_MACH_IRQ(3)
-#define IRQ_IXDP2351_SPCI_PMC_INTA      IXP23XX_MACH_IRQ(4)
-#define IRQ_IXDP2351_SPCI_PMC_INTB      IXP23XX_MACH_IRQ(5)
-#define IRQ_IXDP2351_SPCI_PMC_INTC      IXP23XX_MACH_IRQ(6)
-#define IRQ_IXDP2351_SPCI_PMC_INTD      IXP23XX_MACH_IRQ(7)
-#define IRQ_IXDP2351_SPCI_FIC           IXP23XX_MACH_IRQ(8)
-#define IXDP2351_INTB_IRQ_BIT(irq)      (irq - IXP23XX_MACH_IRQ(0))
-#define IXDP2351_INTB_IRQ_MASK(irq)     (1 << IXDP2351_INTB_IRQ_BIT(irq))
-#define IXDP2351_INTB_IRQ_VALID         0x01FF
-#define IXDP2351_INTB_IRQ_NUM           16
-/*
- * Other external interrupts signaled through INTA
- */
-#define IXDP2351_INTA_IRQ_BASE          16
-#define IRQ_IXDP2351_IPMI_FROM          IXP23XX_MACH_IRQ(16)
-#define IRQ_IXDP2351_125US              IXP23XX_MACH_IRQ(17)
-#define IRQ_IXDP2351_DB_0_ADD           IXP23XX_MACH_IRQ(18)
-#define IRQ_IXDP2351_DB_1_ADD           IXP23XX_MACH_IRQ(19)
-#define IRQ_IXDP2351_DEBUG1             IXP23XX_MACH_IRQ(20)
-#define IRQ_IXDP2351_ADD_UART           IXP23XX_MACH_IRQ(21)
-#define IRQ_IXDP2351_FIC_ADD            IXP23XX_MACH_IRQ(24)
-#define IRQ_IXDP2351_CS8900             IXP23XX_MACH_IRQ(25)
-#define IRQ_IXDP2351_BBSRAM             IXP23XX_MACH_IRQ(26)
-#define IRQ_IXDP2351_CONFIG_MEDIA       IXP23XX_MACH_IRQ(27)
-#define IRQ_IXDP2351_CLOCK_REF          IXP23XX_MACH_IRQ(28)
-#define IRQ_IXDP2351_A10_NP             IXP23XX_MACH_IRQ(29)
-#define IRQ_IXDP2351_A11_NP             IXP23XX_MACH_IRQ(30)
-#define IRQ_IXDP2351_DEBUG_NP           IXP23XX_MACH_IRQ(31)
-#define IXDP2351_INTA_IRQ_BIT(irq)      (irq - IXP23XX_MACH_IRQ(16))
-#define IXDP2351_INTA_IRQ_MASK(irq)     (1 << IXDP2351_INTA_IRQ_BIT(irq))
-#define IXDP2351_INTA_IRQ_VALID         0xFF3F
-#define IXDP2351_INTA_IRQ_NUM           16
-/*
- * ADI RoadRunner IRQs
- */
-#define IRQ_ROADRUNNER_PCI_INTA         IRQ_IXP23XX_INTA
-#define IRQ_ROADRUNNER_PCI_INTB         IRQ_IXP23XX_INTB
-#define IRQ_ROADRUNNER_PCI_INTC         IRQ_IXP23XX_GPIO11
-#define IRQ_ROADRUNNER_PCI_INTD         IRQ_IXP23XX_GPIO12
-/*
- * Put new board definitions here
- */
-#endif
diff --git a/arch/arm/mach-ixp23xx/include/mach/ixdp2351.h b/arch/arm/mach-ixp23xx/include/mach/ixdp2351.h
deleted file mode 100644
index 663951027de5..000000000000
--- a/arch/arm/mach-ixp23xx/include/mach/ixdp2351.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * arch/arm/mach-ixp23xx/include/mach/ixdp2351.h
- *
- * Register and other defines for IXDP2351
- *
- * Copyright (c) 2002-2004 Intel Corp.
- * Copytight (c) 2005 MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-#ifndef __ASM_ARCH_IXDP2351_H
-#define __ASM_ARCH_IXDP2351_H
-/*
- * NP module memory map
- */
-#define IXDP2351_NP_PHYS_BASE           (IXP23XX_EXP_BUS_CS4_BASE)
-#define IXDP2351_NP_PHYS_SIZE           0x00100000
-#define IXDP2351_NP_VIRT_BASE           0xeff00000
-#define IXDP2351_VIRT_CS8900_BASE       (IXDP2351_NP_VIRT_BASE)
-#define IXDP2351_VIRT_CS8900_END        (IXDP2351_VIRT_CS8900_BASE + 16)
-#define IXDP2351_VIRT_NP_CPLD_BASE      (IXP23XX_EXP_BUS_CS4_BASE_VIRT + 0x00010000)
-#define IXDP2351_NP_CPLD_REG(reg) ((volatile u16 *)(IXDP2351_VIRT_NP_CPLD_BASE + reg))
-#define IXDP2351_NP_CPLD_RESET1_REG     IXDP2351_NP_CPLD_REG(0x00)
-#define IXDP2351_NP_CPLD_LED_REG        IXDP2351_NP_CPLD_REG(0x02)
-#define IXDP2351_NP_CPLD_VERSION_REG    IXDP2351_NP_CPLD_REG(0x04)
-/*
- * Base board module memory map
- */
-#define IXDP2351_BB_BASE_PHYS           (IXP23XX_EXP_BUS_CS5_BASE)
-#define IXDP2351_BB_SIZE                0x01000000
-#define IXDP2351_BB_BASE_VIRT           (0xee000000)
-#define IXDP2351_BB_AREA_BASE(offset)   (IXDP2351_BB_BASE_VIRT + offset)
-#define IXDP2351_VIRT_NVRAM_BASE        IXDP2351_BB_AREA_BASE(0x0)
-#define IXDP2351_NVRAM_SIZE             (0x20000)
-#define IXDP2351_VIRT_MB_IXF1104_BASE   IXDP2351_BB_AREA_BASE(0x00020000)
-#define IXDP2351_VIRT_ADD_UART_BASE     IXDP2351_BB_AREA_BASE(0x000240C0)
-#define IXDP2351_VIRT_FIC_BASE          IXDP2351_BB_AREA_BASE(0x00200000)
-#define IXDP2351_VIRT_DB0_BASE          IXDP2351_BB_AREA_BASE(0x00400000)
-#define IXDP2351_VIRT_DB1_BASE          IXDP2351_BB_AREA_BASE(0x00600000)
-#define IXDP2351_VIRT_CPLD_BASE         IXDP2351_BB_AREA_BASE(0x00024000)
-/*
- * On board CPLD registers
- */
-#define IXDP2351_CPLD_BB_REG(reg) ((volatile u16 *)(IXDP2351_VIRT_CPLD_BASE + reg))
-#define IXDP2351_CPLD_RESET0_REG        IXDP2351_CPLD_BB_REG(0x00)
-#define IXDP2351_CPLD_RESET1_REG        IXDP2351_CPLD_BB_REG(0x04)
-#define IXDP2351_CPLD_RESET1_MAGIC      0x55AA
-#define IXDP2351_CPLD_RESET1_ENABLE     0x8000
-#define IXDP2351_CPLD_FPGA_CONFIG_REG   IXDP2351_CPLD_BB_REG(0x08)
-#define IXDP2351_CPLD_INTB_MASK_SET_REG IXDP2351_CPLD_BB_REG(0x10)
-#define IXDP2351_CPLD_INTA_MASK_SET_REG IXDP2351_CPLD_BB_REG(0x14)
-#define IXDP2351_CPLD_INTB_STAT_REG     IXDP2351_CPLD_BB_REG(0x18)
-#define IXDP2351_CPLD_INTA_STAT_REG     IXDP2351_CPLD_BB_REG(0x1C)
-#define IXDP2351_CPLD_INTB_RAW_REG      IXDP2351_CPLD_BB_REG(0x20)      /* read */
-#define IXDP2351_CPLD_INTA_RAW_REG      IXDP2351_CPLD_BB_REG(0x24)      /* read */
-#define IXDP2351_CPLD_INTB_MASK_CLR_REG IXDP2351_CPLD_INTB_RAW_REG      /* write */
-#define IXDP2351_CPLD_INTA_MASK_CLR_REG IXDP2351_CPLD_INTA_RAW_REG      /* write */
-#define IXDP2351_CPLD_INTB_SIM_REG      IXDP2351_CPLD_BB_REG(0x28)
-#define IXDP2351_CPLD_INTA_SIM_REG      IXDP2351_CPLD_BB_REG(0x2C)
-        /* Interrupt bits are defined in irqs.h */
-#define IXDP2351_CPLD_BB_GBE0_REG       IXDP2351_CPLD_BB_REG(0x30)
-#define IXDP2351_CPLD_BB_GBE1_REG       IXDP2351_CPLD_BB_REG(0x34)
-/* #define IXDP2351_CPLD_BB_MISC_REG    IXDP2351_CPLD_REG(0x1C) */
-/* #define IXDP2351_CPLD_BB_MISC_REV_MASK       0xFF            */
-/* #define IXDP2351_CPLD_BB_GDXCS0_REG  IXDP2351_CPLD_REG(0x24) */
-/* #define IXDP2351_CPLD_BB_GDXCS1_REG  IXDP2351_CPLD_REG(0x28) */
-/* #define IXDP2351_CPLD_BB_CLOCK_REG   IXDP2351_CPLD_REG(0x04) */
-#endif
diff --git a/arch/arm/mach-ixp23xx/include/mach/ixp23xx.h b/arch/arm/mach-ixp23xx/include/mach/ixp23xx.h
deleted file mode 100644
index 6d02481b1d6d..000000000000
--- a/arch/arm/mach-ixp23xx/include/mach/ixp23xx.h
+++ /dev/null
@@ -1,298 +0,0 @@
-/*
- * arch/arm/mach-ixp23xx/include/mach/ixp23xx.h
- *
- * Register definitions for IXP23XX
- *
- * Copyright (C) 2003-2005 Intel Corporation.
- * Copyright (C) 2005 MontaVista Software, Inc.
- *
- * Maintainer: Deepak Saxena <dsaxena@plexity.net>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __ASM_ARCH_IXP23XX_H
-#define __ASM_ARCH_IXP23XX_H
-/*
- * IXP2300 linux memory map:
- *
- * virt         phys            size
- * fffd0000     a0000000        64K             XSI2CPP_CSR
- * fffc0000     c4000000        4K              EXP_CFG
- * fff00000     c8000000        64K             PERIPHERAL
- * fe000000     1c0000000       16M             CAP_CSR
- * fd000000     1c8000000       16M             MSF_CSR
- * fb000000                     16M             ---
- * fa000000     1d8000000       32M             PCI_IO
- * f8000000     1da000000       32M             PCI_CFG
- * f6000000     1de000000       32M             PCI_CREG
- * f4000000                     32M             ---
- * f0000000     1e0000000       64M             PCI_MEM
- * e[c-f]000000                                 per-platform mappings
- */
-/****************************************************************************
- * Static mappings.
- ****************************************************************************/
-#define IXP23XX_XSI2CPP_CSR_PHYS        0xa0000000
-#define IXP23XX_XSI2CPP_CSR_VIRT        0xfffd0000
-#define IXP23XX_XSI2CPP_CSR_SIZE        0x00010000
-#define IXP23XX_EXP_CFG_PHYS            0xc4000000
-#define IXP23XX_EXP_CFG_VIRT            0xfffc0000
-#define IXP23XX_EXP_CFG_SIZE            0x00001000
-#define IXP23XX_PERIPHERAL_PHYS         0xc8000000
-#define IXP23XX_PERIPHERAL_VIRT         0xfff00000
-#define IXP23XX_PERIPHERAL_SIZE         0x00010000
-#define IXP23XX_CAP_CSR_PHYS            0x1c0000000ULL
-#define IXP23XX_CAP_CSR_VIRT            0xfe000000
-#define IXP23XX_CAP_CSR_SIZE            0x01000000
-#define IXP23XX_MSF_CSR_PHYS            0x1c8000000ULL
-#define IXP23XX_MSF_CSR_VIRT            0xfd000000
-#define IXP23XX_MSF_CSR_SIZE            0x01000000
-#define IXP23XX_PCI_IO_PHYS             0x1d8000000ULL
-#define IXP23XX_PCI_IO_VIRT             0xfa000000
-#define IXP23XX_PCI_IO_SIZE             0x02000000
-#define IXP23XX_PCI_CFG_PHYS            0x1da000000ULL
-#define IXP23XX_PCI_CFG_VIRT            0xf8000000
-#define IXP23XX_PCI_CFG_SIZE            0x02000000
-#define IXP23XX_PCI_CFG0_VIRT           IXP23XX_PCI_CFG_VIRT
-#define IXP23XX_PCI_CFG1_VIRT           (IXP23XX_PCI_CFG_VIRT + 0x01000000)
-#define IXP23XX_PCI_CREG_PHYS           0x1de000000ULL
-#define IXP23XX_PCI_CREG_VIRT           0xf6000000
-#define IXP23XX_PCI_CREG_SIZE           0x02000000
-#define IXP23XX_PCI_CSR_VIRT            (IXP23XX_PCI_CREG_VIRT + 0x01000000)
-#define IXP23XX_PCI_MEM_START           0xe0000000
-#define IXP23XX_PCI_MEM_PHYS            0x1e0000000ULL
-#define IXP23XX_PCI_MEM_VIRT            0xf0000000
-#define IXP23XX_PCI_MEM_SIZE            0x04000000
-/****************************************************************************
- * XSI2CPP CSRs.
- ****************************************************************************/
-#define IXP23XX_XSI2CPP_REG(x)          ((volatile unsigned long *)(IXP23XX_XSI2CPP_CSR_VIRT + (x)))
-#define IXP23XX_CPP2XSI_CURR_XFER_REG3  IXP23XX_XSI2CPP_REG(0xf8)
-#define IXP23XX_CPP2XSI_ADDR_31         (1 << 19)
-#define IXP23XX_CPP2XSI_PSH_OFF         (1 << 20)
-#define IXP23XX_CPP2XSI_COH_OFF         (1 << 21)
-/****************************************************************************
- * Expansion Bus Config.
- ****************************************************************************/
-#define IXP23XX_EXP_CFG_REG(x)          ((volatile unsigned long *)(IXP23XX_EXP_CFG_VIRT + (x)))
-#define IXP23XX_EXP_CS0                 IXP23XX_EXP_CFG_REG(0x00)
-#define IXP23XX_EXP_CS1                 IXP23XX_EXP_CFG_REG(0x04)
-#define IXP23XX_EXP_CS2                 IXP23XX_EXP_CFG_REG(0x08)
-#define IXP23XX_EXP_CS3                 IXP23XX_EXP_CFG_REG(0x0c)
-#define IXP23XX_EXP_CS4                 IXP23XX_EXP_CFG_REG(0x10)
-#define IXP23XX_EXP_CS5                 IXP23XX_EXP_CFG_REG(0x14)
-#define IXP23XX_EXP_CS6                 IXP23XX_EXP_CFG_REG(0x18)
-#define IXP23XX_EXP_CS7                 IXP23XX_EXP_CFG_REG(0x1c)
-#define IXP23XX_FLASH_WRITABLE          (0x2)
-#define IXP23XX_FLASH_BUS8              (0x1)
-#define IXP23XX_EXP_CFG0                IXP23XX_EXP_CFG_REG(0x20)
-#define IXP23XX_EXP_CFG1                IXP23XX_EXP_CFG_REG(0x24)
-#define IXP23XX_EXP_CFG0_MEM_MAP                (1 << 31)
-#define IXP23XX_EXP_CFG0_XSCALE_SPEED_SEL       (3 << 22)
-#define IXP23XX_EXP_CFG0_XSCALE_SPEED_EN        (1 << 21)
-#define IXP23XX_EXP_CFG0_CPP_SPEED_SEL          (3 << 19)
-#define IXP23XX_EXP_CFG0_CPP_SPEED_EN           (1 << 18)
-#define IXP23XX_EXP_CFG0_PCI_SWIN               (3 << 16)
-#define IXP23XX_EXP_CFG0_PCI_DWIN               (3 << 14)
-#define IXP23XX_EXP_CFG0_PCI33_MODE             (1 << 13)
-#define IXP23XX_EXP_CFG0_QDR_SPEED_SEL          (1 << 12)
-#define IXP23XX_EXP_CFG0_CPP_DIV_SEL            (1 << 5)
-#define IXP23XX_EXP_CFG0_XSI_NOT_PRES           (1 << 4)
-#define IXP23XX_EXP_CFG0_PROM_BOOT              (1 << 3)
-#define IXP23XX_EXP_CFG0_PCI_ARB                (1 << 2)
-#define IXP23XX_EXP_CFG0_PCI_HOST               (1 << 1)
-#define IXP23XX_EXP_CFG0_FLASH_WIDTH            (1 << 0)
-#define IXP23XX_EXP_UNIT_FUSE           IXP23XX_EXP_CFG_REG(0x28)
-#define IXP23XX_EXP_MSF_MUX             IXP23XX_EXP_CFG_REG(0x30)
-#define IXP23XX_EXP_CFG_FUSE            IXP23XX_EXP_CFG_REG(0x34)
-#define IXP23XX_EXP_BUS_PHYS            0x90000000
-#define IXP23XX_EXP_BUS_WINDOW_SIZE     0x01000000
-#define IXP23XX_EXP_BUS_CS0_BASE        (IXP23XX_EXP_BUS_PHYS + 0x00000000)
-#define IXP23XX_EXP_BUS_CS1_BASE        (IXP23XX_EXP_BUS_PHYS + 0x01000000)
-#define IXP23XX_EXP_BUS_CS2_BASE        (IXP23XX_EXP_BUS_PHYS + 0x02000000)
-#define IXP23XX_EXP_BUS_CS3_BASE        (IXP23XX_EXP_BUS_PHYS + 0x03000000)
-#define IXP23XX_EXP_BUS_CS4_BASE        (IXP23XX_EXP_BUS_PHYS + 0x04000000)
-#define IXP23XX_EXP_BUS_CS5_BASE        (IXP23XX_EXP_BUS_PHYS + 0x05000000)
-#define IXP23XX_EXP_BUS_CS6_BASE        (IXP23XX_EXP_BUS_PHYS + 0x06000000)
-#define IXP23XX_EXP_BUS_CS7_BASE        (IXP23XX_EXP_BUS_PHYS + 0x07000000)
-/****************************************************************************
- * Peripherals.
- ****************************************************************************/
-#define IXP23XX_UART1_VIRT              (IXP23XX_PERIPHERAL_VIRT + 0x0000)
-#define IXP23XX_UART2_VIRT              (IXP23XX_PERIPHERAL_VIRT + 0x1000)
-#define IXP23XX_PMU_VIRT                (IXP23XX_PERIPHERAL_VIRT + 0x2000)
-#define IXP23XX_INTC_VIRT               (IXP23XX_PERIPHERAL_VIRT + 0x3000)
-#define IXP23XX_GPIO_VIRT               (IXP23XX_PERIPHERAL_VIRT + 0x4000)
-#define IXP23XX_TIMER_VIRT              (IXP23XX_PERIPHERAL_VIRT + 0x5000)
-#define IXP23XX_NPE0_VIRT               (IXP23XX_PERIPHERAL_VIRT + 0x6000)
-#define IXP23XX_DSR_VIRT                (IXP23XX_PERIPHERAL_VIRT + 0x7000)
-#define IXP23XX_NPE1_VIRT               (IXP23XX_PERIPHERAL_VIRT + 0x8000)
-#define IXP23XX_ETH0_VIRT               (IXP23XX_PERIPHERAL_VIRT + 0x9000)
-#define IXP23XX_ETH1_VIRT               (IXP23XX_PERIPHERAL_VIRT + 0xA000)
-#define IXP23XX_GIG0_VIRT               (IXP23XX_PERIPHERAL_VIRT + 0xB000)
-#define IXP23XX_GIG1_VIRT               (IXP23XX_PERIPHERAL_VIRT + 0xC000)
-#define IXP23XX_DDRS_VIRT               (IXP23XX_PERIPHERAL_VIRT + 0xD000)
-#define IXP23XX_UART1_PHYS              (IXP23XX_PERIPHERAL_PHYS + 0x0000)
-#define IXP23XX_UART2_PHYS              (IXP23XX_PERIPHERAL_PHYS + 0x1000)
-#define IXP23XX_PMU_PHYS                (IXP23XX_PERIPHERAL_PHYS + 0x2000)
-#define IXP23XX_INTC_PHYS               (IXP23XX_PERIPHERAL_PHYS + 0x3000)
-#define IXP23XX_GPIO_PHYS               (IXP23XX_PERIPHERAL_PHYS + 0x4000)
-#define IXP23XX_TIMER_PHYS              (IXP23XX_PERIPHERAL_PHYS + 0x5000)
-#define IXP23XX_NPE0_PHYS               (IXP23XX_PERIPHERAL_PHYS + 0x6000)
-#define IXP23XX_DSR_PHYS                (IXP23XX_PERIPHERAL_PHYS + 0x7000)
-#define IXP23XX_NPE1_PHYS               (IXP23XX_PERIPHERAL_PHYS + 0x8000)
-#define IXP23XX_ETH0_PHYS               (IXP23XX_PERIPHERAL_PHYS + 0x9000)
-#define IXP23XX_ETH1_PHYS               (IXP23XX_PERIPHERAL_PHYS + 0xA000)
-#define IXP23XX_GIG0_PHYS               (IXP23XX_PERIPHERAL_PHYS + 0xB000)
-#define IXP23XX_GIG1_PHYS               (IXP23XX_PERIPHERAL_PHYS + 0xC000)
-#define IXP23XX_DDRS_PHYS               (IXP23XX_PERIPHERAL_PHYS + 0xD000)
-/****************************************************************************
- * Interrupt controller.
- ****************************************************************************/
-#define IXP23XX_INTC_REG(x)              ((volatile unsigned long *)(IXP23XX_INTC_VIRT + (x)))
-#define IXP23XX_INTR_ST1                IXP23XX_INTC_REG(0x00)
-#define IXP23XX_INTR_ST2                IXP23XX_INTC_REG(0x04)
-#define IXP23XX_INTR_ST3                IXP23XX_INTC_REG(0x08)
-#define IXP23XX_INTR_ST4                IXP23XX_INTC_REG(0x0c)
-#define IXP23XX_INTR_EN1                IXP23XX_INTC_REG(0x10)
-#define IXP23XX_INTR_EN2                IXP23XX_INTC_REG(0x14)
-#define IXP23XX_INTR_EN3                IXP23XX_INTC_REG(0x18)
-#define IXP23XX_INTR_EN4                IXP23XX_INTC_REG(0x1c)
-#define IXP23XX_INTR_SEL1               IXP23XX_INTC_REG(0x20)
-#define IXP23XX_INTR_SEL2               IXP23XX_INTC_REG(0x24)
-#define IXP23XX_INTR_SEL3               IXP23XX_INTC_REG(0x28)
-#define IXP23XX_INTR_SEL4               IXP23XX_INTC_REG(0x2c)
-#define IXP23XX_INTR_IRQ_ST1            IXP23XX_INTC_REG(0x30)
-#define IXP23XX_INTR_IRQ_ST2            IXP23XX_INTC_REG(0x34)
-#define IXP23XX_INTR_IRQ_ST3            IXP23XX_INTC_REG(0x38)
-#define IXP23XX_INTR_IRQ_ST4            IXP23XX_INTC_REG(0x3c)
-#define IXP23XX_INTR_IRQ_ENC_ST_OFFSET  0x54
-/****************************************************************************
- * GPIO.
- ****************************************************************************/
-#define IXP23XX_GPIO_REG(x)             ((volatile unsigned long *)(IXP23XX_GPIO_VIRT + (x)))
-#define IXP23XX_GPIO_GPOUTR             IXP23XX_GPIO_REG(0x00)
-#define IXP23XX_GPIO_GPOER              IXP23XX_GPIO_REG(0x04)
-#define IXP23XX_GPIO_GPINR              IXP23XX_GPIO_REG(0x08)
-#define IXP23XX_GPIO_GPISR              IXP23XX_GPIO_REG(0x0c)
-#define IXP23XX_GPIO_GPIT1R             IXP23XX_GPIO_REG(0x10)
-#define IXP23XX_GPIO_GPIT2R             IXP23XX_GPIO_REG(0x14)
-#define IXP23XX_GPIO_GPCLKR             IXP23XX_GPIO_REG(0x18)
-#define IXP23XX_GPIO_GPDBSELR           IXP23XX_GPIO_REG(0x1c)
-#define IXP23XX_GPIO_STYLE_MASK         0x7
-#define IXP23XX_GPIO_STYLE_ACTIVE_HIGH  0x0
-#define IXP23XX_GPIO_STYLE_ACTIVE_LOW   0x1
-#define IXP23XX_GPIO_STYLE_RISING_EDGE  0x2
-#define IXP23XX_GPIO_STYLE_FALLING_EDGE 0x3
-#define IXP23XX_GPIO_STYLE_TRANSITIONAL 0x4
-#define IXP23XX_GPIO_STYLE_SIZE         3
-/****************************************************************************
- * Timer.
- ****************************************************************************/
-#define IXP23XX_TIMER_REG(x)            ((volatile unsigned long *)(IXP23XX_TIMER_VIRT + (x)))
-#define IXP23XX_TIMER_CONT              IXP23XX_TIMER_REG(0x00)
-#define IXP23XX_TIMER1_TIMESTAMP        IXP23XX_TIMER_REG(0x04)
-#define IXP23XX_TIMER1_RELOAD           IXP23XX_TIMER_REG(0x08)
-#define IXP23XX_TIMER2_TIMESTAMP        IXP23XX_TIMER_REG(0x0c)
-#define IXP23XX_TIMER2_RELOAD           IXP23XX_TIMER_REG(0x10)
-#define IXP23XX_TIMER_WDOG              IXP23XX_TIMER_REG(0x14)
-#define IXP23XX_TIMER_WDOG_EN           IXP23XX_TIMER_REG(0x18)
-#define IXP23XX_TIMER_WDOG_KEY          IXP23XX_TIMER_REG(0x1c)
-#define IXP23XX_TIMER_WDOG_KEY_MAGIC    0x482e
-#define IXP23XX_TIMER_STATUS            IXP23XX_TIMER_REG(0x20)
-#define IXP23XX_TIMER_SOFT_RESET        IXP23XX_TIMER_REG(0x24)
-#define IXP23XX_TIMER_SOFT_RESET_EN     IXP23XX_TIMER_REG(0x28)
-#define IXP23XX_TIMER_ENABLE            (1 << 0)
-#define IXP23XX_TIMER_ONE_SHOT          (1 << 1)
-/* Low order bits of reload value ignored */
-#define IXP23XX_TIMER_RELOAD_MASK       (0x3)
-#define IXP23XX_TIMER_DISABLED          (0x0)
-#define IXP23XX_TIMER1_INT_PEND         (1 << 0)
-#define IXP23XX_TIMER2_INT_PEND         (1 << 1)
-#define IXP23XX_TIMER_STATUS_TS_PEND    (1 << 2)
-#define IXP23XX_TIMER_STATUS_WDOG_PEND  (1 << 3)
-#define IXP23XX_TIMER_STATUS_WARM_RESET (1 << 4)
-/****************************************************************************
- * CAP CSRs.
- ****************************************************************************/
-#define IXP23XX_GLOBAL_REG(x)           ((volatile unsigned long *)(IXP23XX_CAP_CSR_VIRT + 0x4a00 + (x)))
-#define IXP23XX_PRODUCT_ID              IXP23XX_GLOBAL_REG(0x00)
-#define IXP23XX_MISC_CONTROL            IXP23XX_GLOBAL_REG(0x04)
-#define IXP23XX_MSF_CLK_CNTRL           IXP23XX_GLOBAL_REG(0x08)
-#define IXP23XX_RESET0                  IXP23XX_GLOBAL_REG(0x0c)
-#define IXP23XX_RESET1                  IXP23XX_GLOBAL_REG(0x10)
-#define IXP23XX_STRAP_OPTIONS           IXP23XX_GLOBAL_REG(0x18)
-#define IXP23XX_ENABLE_WATCHDOG         (1 << 24)
-#define IXP23XX_SHPC_INIT_COMP          (1 << 21)
-#define IXP23XX_RST_ALL                 (1 << 16)
-#define IXP23XX_RESET_PCI               (1 << 2)
-#define IXP23XX_PCI_UNIT_RESET          (1 << 1)
-#define IXP23XX_XSCALE_RESET            (1 << 0)
-#define IXP23XX_UENGINE_CSR_VIRT_BASE   (IXP23XX_CAP_CSR_VIRT + 0x18000)
-/****************************************************************************
- * PCI CSRs.
- ****************************************************************************/
-#define IXP23XX_PCI_CREG(x)             ((volatile unsigned long *)(IXP23XX_PCI_CREG_VIRT + (x)))
-#define IXP23XX_PCI_CMDSTAT             IXP23XX_PCI_CREG(0x04)
-#define IXP23XX_PCI_SRAM_BAR            IXP23XX_PCI_CREG(0x14)
-#define IXP23XX_PCI_SDRAM_BAR           IXP23XX_PCI_CREG(0x18)
-#define IXP23XX_PCI_CSR(x)              ((volatile unsigned long *)(IXP23XX_PCI_CREG_VIRT + 0x01000000 + (x)))
-#define IXP23XX_PCI_OUT_INT_STATUS      IXP23XX_PCI_CSR(0x0030)
-#define IXP23XX_PCI_OUT_INT_MASK        IXP23XX_PCI_CSR(0x0034)
-#define IXP23XX_PCI_SRAM_BASE_ADDR_MASK IXP23XX_PCI_CSR(0x00fc)
-#define IXP23XX_PCI_DRAM_BASE_ADDR_MASK IXP23XX_PCI_CSR(0x0100)
-#define IXP23XX_PCI_CONTROL             IXP23XX_PCI_CSR(0x013c)
-#define IXP23XX_PCI_ADDR_EXT            IXP23XX_PCI_CSR(0x0140)
-#define IXP23XX_PCI_ME_PUSH_STATUS      IXP23XX_PCI_CSR(0x0148)
-#define IXP23XX_PCI_ME_PUSH_EN          IXP23XX_PCI_CSR(0x014c)
-#define IXP23XX_PCI_ERR_STATUS          IXP23XX_PCI_CSR(0x0150)
-#define IXP23XX_PCI_ERROR_STATUS        IXP23XX_PCI_CSR(0x0150)
-#define IXP23XX_PCI_ERR_ENABLE          IXP23XX_PCI_CSR(0x0154)
-#define IXP23XX_PCI_XSCALE_INT_STATUS   IXP23XX_PCI_CSR(0x0158)
-#define IXP23XX_PCI_XSCALE_INT_ENABLE   IXP23XX_PCI_CSR(0x015c)
-#define IXP23XX_PCI_CPP_ADDR_BITS       IXP23XX_PCI_CSR(0x0160)
-#endif
diff --git a/arch/arm/mach-ixp23xx/include/mach/memory.h b/arch/arm/mach-ixp23xx/include/mach/memory.h
deleted file mode 100644
index 6cf0704e946a..000000000000
--- a/arch/arm/mach-ixp23xx/include/mach/memory.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * arch/arm/mach-ixp23xx/include/mach/memory.h
- *
- * Copyright (c) 2003-2004 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-#ifndef __ASM_ARCH_MEMORY_H
-#define __ASM_ARCH_MEMORY_H
-#include <mach/hardware.h>
-/*
- * Physical DRAM offset.
- */
-#define PLAT_PHYS_OFFSET                (0x00000000)
-#define IXP23XX_PCI_SDRAM_OFFSET (*((volatile int *)IXP23XX_PCI_SDRAM_BAR) & 0xfffffff0)
-#define __phys_to_bus(x)        ((x) + (IXP23XX_PCI_SDRAM_OFFSET - PHYS_OFFSET))
-#define __bus_to_phys(x)        ((x) - (IXP23XX_PCI_SDRAM_OFFSET - PHYS_OFFSET))
-#define __virt_to_bus(v)        __phys_to_bus(__virt_to_phys(v))
-#define __bus_to_virt(b)        __phys_to_virt(__bus_to_phys(b))
-#define __pfn_to_bus(p)         __phys_to_bus(__pfn_to_phys(p))
-#define __bus_to_pfn(b)         __phys_to_pfn(__bus_to_phys(b))
-#define arch_is_coherent()      1
-#endif
diff --git a/arch/arm/mach-ixp23xx/include/mach/platform.h b/arch/arm/mach-ixp23xx/include/mach/platform.h
deleted file mode 100644
index 50de558e722e..000000000000
--- a/arch/arm/mach-ixp23xx/include/mach/platform.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * arch/arm/mach-ixp23xx/include/mach/platform.h
- *
- * Various bits of code used by platform-level code.
- *
- * Author: Deepak Saxena <dsaxena@plexity.net>
- *
- * Copyright 2005 (c) MontaVista Software, Inc.
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#ifndef __ASSEMBLY__
-static inline unsigned long ixp2000_reg_read(volatile void *reg)
-{
-        return *((volatile unsigned long *)reg);
-}
-static inline void ixp2000_reg_write(volatile void *reg, unsigned long val)
-{
-        *((volatile unsigned long *)reg) = val;
-}
-static inline void ixp2000_reg_wrb(volatile void *reg, unsigned long val)
-{
-        *((volatile unsigned long *)reg) = val;
-}
-struct pci_sys_data;
-void ixp23xx_map_io(void);
-void ixp23xx_init_irq(void);
-void ixp23xx_sys_init(void);
-void ixp23xx_restart(char, const char *);
-int ixp23xx_pci_setup(int, struct pci_sys_data *);
-void ixp23xx_pci_preinit(void);
-struct pci_bus *ixp23xx_pci_scan_bus(int, struct pci_sys_data*);
-void ixp23xx_pci_slave_init(void);
-extern struct sys_timer ixp23xx_timer;
-#define IXP23XX_UART_XTAL               14745600
-#ifndef __ASSEMBLY__
-/*
- * Is system memory on the XSI or CPP bus?
- */
-static inline unsigned ixp23xx_cpp_boot(void)
-{
-        return (*IXP23XX_EXP_CFG0 & IXP23XX_EXP_CFG0_XSI_NOT_PRES);
-}
-#endif
-#endif
diff --git a/arch/arm/mach-ixp23xx/include/mach/time.h b/arch/arm/mach-ixp23xx/include/mach/time.h
deleted file mode 100644
index b61dafc884ac..000000000000
--- a/arch/arm/mach-ixp23xx/include/mach/time.h
+++ /dev/null
@@ -1,3 +0,0 @@
-/*
- * arch/arm/mach-ixp23xx/include/mach/time.h
- */
diff --git a/arch/arm/mach-ixp23xx/include/mach/timex.h b/arch/arm/mach-ixp23xx/include/mach/timex.h
deleted file mode 100644
index e341e9cf9c37..000000000000
--- a/arch/arm/mach-ixp23xx/include/mach/timex.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/*
- * arch/arm/mach-ixp23xx/include/mach/timex.h
- *
- * XScale architecture timex specifications
- */
-#define CLOCK_TICK_RATE 75000000
diff --git a/arch/arm/mach-ixp23xx/include/mach/uncompress.h b/arch/arm/mach-ixp23xx/include/mach/uncompress.h
deleted file mode 100644
index 8b4c358d2c04..000000000000
--- a/arch/arm/mach-ixp23xx/include/mach/uncompress.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * arch/arm/mach-ixp23xx/include/mach/uncompress.h
- *
- * Copyright (C) 2002-2004 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __ASM_ARCH_UNCOMPRESS_H
-#define __ASM_ARCH_UNCOMPRESS_H
-#include <mach/ixp23xx.h>
-#include <linux/serial_reg.h>
-#define UART_BASE       ((volatile u32 *)IXP23XX_UART1_PHYS)
-static inline void putc(char c)
-{
-        int j;
-        for (j = 0; j < 0x1000; j++) {
-                if (UART_BASE[UART_LSR] & UART_LSR_THRE)
-                        break;
-                barrier();
-        }
-        UART_BASE[UART_TX] = c;
-}
-static inline void flush(void)
-{
-}
-#define arch_decomp_setup()
-#define arch_decomp_wdog()
-#endif
diff --git a/arch/arm/mach-ixp23xx/ixdp2351.c b/arch/arm/mach-ixp23xx/ixdp2351.c
deleted file mode 100644
index b0e07db5ceaf..000000000000
--- a/arch/arm/mach-ixp23xx/ixdp2351.c
+++ /dev/null
@@ -1,347 +0,0 @@
-/*
- * arch/arm/mach-ixp23xx/ixdp2351.c
- *
- * IXDP2351 board-specific routines
- *
- * Author: Deepak Saxena <dsaxena@plexity.net>
- *
- * Copyright 2005 (c) MontaVista Software, Inc.
- *
- * Based on 2.4 code Copyright 2004 (c) Intel Corporation
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/spinlock.h>
-#include <linux/sched.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/serial.h>
-#include <linux/tty.h>
-#include <linux/bitops.h>
-#include <linux/ioport.h>
-#include <linux/serial_8250.h>
-#include <linux/serial_core.h>
-#include <linux/device.h>
-#include <linux/mm.h>
-#include <linux/pci.h>
-#include <linux/mtd/physmap.h>
-#include <asm/types.h>
-#include <asm/setup.h>
-#include <asm/memory.h>
-#include <mach/hardware.h>
-#include <asm/mach-types.h>
-#include <asm/tlbflush.h>
-#include <asm/pgtable.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/pci.h>
-/*
- * IXDP2351 Interrupt Handling
- */
-static void ixdp2351_inta_mask(struct irq_data *d)
-{
-        *IXDP2351_CPLD_INTA_MASK_SET_REG = IXDP2351_INTA_IRQ_MASK(d->irq);
-}
-static void ixdp2351_inta_unmask(struct irq_data *d)
-{
-        *IXDP2351_CPLD_INTA_MASK_CLR_REG = IXDP2351_INTA_IRQ_MASK(d->irq);
-}
-static void ixdp2351_inta_handler(unsigned int irq, struct irq_desc *desc)
-{
-        u16 ex_interrupt =
-                *IXDP2351_CPLD_INTA_STAT_REG & IXDP2351_INTA_IRQ_VALID;
-        int i;
-        desc->irq_data.chip->irq_mask(&desc->irq_data);
-        for (i = 0; i < IXDP2351_INTA_IRQ_NUM; i++) {
-                if (ex_interrupt & (1 << i)) {
-                        int cpld_irq =
-                                IXP23XX_MACH_IRQ(IXDP2351_INTA_IRQ_BASE + i);
-                        generic_handle_irq(cpld_irq);
-                }
-        }
-        desc->irq_data.chip->irq_unmask(&desc->irq_data);
-}
-static struct irq_chip ixdp2351_inta_chip = {
-        .irq_ack        = ixdp2351_inta_mask,
-        .irq_mask       = ixdp2351_inta_mask,
-        .irq_unmask     = ixdp2351_inta_unmask
-};
-static void ixdp2351_intb_mask(struct irq_data *d)
-{
-        *IXDP2351_CPLD_INTB_MASK_SET_REG = IXDP2351_INTB_IRQ_MASK(d->irq);
-}
-static void ixdp2351_intb_unmask(struct irq_data *d)
-{
-        *IXDP2351_CPLD_INTB_MASK_CLR_REG = IXDP2351_INTB_IRQ_MASK(d->irq);
-}
-static void ixdp2351_intb_handler(unsigned int irq, struct irq_desc *desc)
-{
-        u16 ex_interrupt =
-                *IXDP2351_CPLD_INTB_STAT_REG & IXDP2351_INTB_IRQ_VALID;
-        int i;
-        desc->irq_data.chip->irq_ack(&desc->irq_data);
-        for (i = 0; i < IXDP2351_INTB_IRQ_NUM; i++) {
-                if (ex_interrupt & (1 << i)) {
-                        int cpld_irq =
-                                IXP23XX_MACH_IRQ(IXDP2351_INTB_IRQ_BASE + i);
-                        generic_handle_irq(cpld_irq);
-                }
-        }
-        desc->irq_data.chip->irq_unmask(&desc->irq_data);
-}
-static struct irq_chip ixdp2351_intb_chip = {
-        .irq_ack        = ixdp2351_intb_mask,
-        .irq_mask       = ixdp2351_intb_mask,
-        .irq_unmask     = ixdp2351_intb_unmask
-};
-void __init ixdp2351_init_irq(void)
-{
-        int irq;
-        /* Mask all interrupts from CPLD, disable simulation */
-        *IXDP2351_CPLD_INTA_MASK_SET_REG = (u16) -1;
-        *IXDP2351_CPLD_INTB_MASK_SET_REG = (u16) -1;
-        *IXDP2351_CPLD_INTA_SIM_REG = 0;
-        *IXDP2351_CPLD_INTB_SIM_REG = 0;
-        ixp23xx_init_irq();
-        for (irq = IXP23XX_MACH_IRQ(IXDP2351_INTA_IRQ_BASE);
-             irq <
-             IXP23XX_MACH_IRQ(IXDP2351_INTA_IRQ_BASE + IXDP2351_INTA_IRQ_NUM);
-             irq++) {
-                if (IXDP2351_INTA_IRQ_MASK(irq) & IXDP2351_INTA_IRQ_VALID) {
-                        set_irq_flags(irq, IRQF_VALID);
-                        irq_set_chip_and_handler(irq, &ixdp2351_inta_chip,
-                                                 handle_level_irq);
-                }
-        }
-        for (irq = IXP23XX_MACH_IRQ(IXDP2351_INTB_IRQ_BASE);
-             irq <
-             IXP23XX_MACH_IRQ(IXDP2351_INTB_IRQ_BASE + IXDP2351_INTB_IRQ_NUM);
-             irq++) {
-                if (IXDP2351_INTB_IRQ_MASK(irq) & IXDP2351_INTB_IRQ_VALID) {
-                        set_irq_flags(irq, IRQF_VALID);
-                        irq_set_chip_and_handler(irq, &ixdp2351_intb_chip,
-                                                 handle_level_irq);
-                }
-        }
-        irq_set_chained_handler(IRQ_IXP23XX_INTA, ixdp2351_inta_handler);
-        irq_set_chained_handler(IRQ_IXP23XX_INTB, ixdp2351_intb_handler);
-}
-/*
- * IXDP2351 PCI
- */
-/*
- * This board does not do normal PCI IRQ routing, or any
- * sort of swizzling, so we just need to check where on the
- * bus the device is and figure out what CPLD pin it is
- * being routed to.
- */
-#define DEVPIN(dev, pin) ((pin) | ((dev) << 3))
-static int __init ixdp2351_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
-        u8 bus = dev->bus->number;
-        u32 devpin = DEVPIN(PCI_SLOT(dev->devfn), pin);
-        struct pci_bus *tmp_bus = dev->bus;
-        /* Primary bus, no interrupts here */
-        if (!bus)
-                return -1;
-        /* Lookup first leaf in bus tree */
-        while ((tmp_bus->parent != NULL) && (tmp_bus->parent->parent != NULL))
-                tmp_bus = tmp_bus->parent;
-        /* Select between known bridges */
-        switch (tmp_bus->self->devfn | (tmp_bus->self->bus->number << 8)) {
-                /* Device is located after first bridge */
-        case 0x0008:
-                if (tmp_bus == dev->bus) {
-                        /* Device is located directy after first bridge */
-                        switch (devpin) {
-                                /* Onboard 82546 */
-                        case DEVPIN(1, 1):      /* Onboard 82546 ch 0 */
-                                return IRQ_IXDP2351_INTA_82546;
-                        case DEVPIN(1, 2):      /* Onboard 82546 ch 1 */
-                                return IRQ_IXDP2351_INTB_82546;
-                                /* PMC SLOT */
-                        case DEVPIN(0, 1):      /* PMCP INTA# */
-                        case DEVPIN(2, 4):      /* PMCS INTD# */
-                                return IRQ_IXDP2351_SPCI_PMC_INTA;
-                        case DEVPIN(0, 2):      /* PMCP INTB# */
-                        case DEVPIN(2, 1):      /* PMCS INTA# */
-                                return IRQ_IXDP2351_SPCI_PMC_INTB;
-                        case DEVPIN(0, 3):      /* PMCP INTC# */
-                        case DEVPIN(2, 2):      /* PMCS INTB# */
-                                return IRQ_IXDP2351_SPCI_PMC_INTC;
-                        case DEVPIN(0, 4):      /* PMCP INTD# */
-                        case DEVPIN(2, 3):      /* PMCS INTC# */
-                                return IRQ_IXDP2351_SPCI_PMC_INTD;
-                        }
-                } else {
-                        /* Device is located indirectly after first bridge */
-                        /* Not supported now */
-                        return -1;
-                }
-                break;
-        case 0x0010:
-                if (tmp_bus == dev->bus) {
-                        /* Device is located directy after second bridge */
-                        /* Secondary bus of second bridge */
-                        switch (devpin) {
-                        case DEVPIN(0, 1):      /* DB#0 */
-                        case DEVPIN(0, 2):
-                        case DEVPIN(0, 3):
-                        case DEVPIN(0, 4):
-                                return IRQ_IXDP2351_SPCI_DB_0;
-                        case DEVPIN(1, 1):      /* DB#1 */
-                        case DEVPIN(1, 2):
-                        case DEVPIN(1, 3):
-                        case DEVPIN(1, 4):
-                                return IRQ_IXDP2351_SPCI_DB_1;
-                        case DEVPIN(2, 1):      /* FIC1 */
-                        case DEVPIN(2, 2):
-                        case DEVPIN(2, 3):
-                        case DEVPIN(2, 4):
-                        case DEVPIN(3, 1):      /* FIC2 */
-                        case DEVPIN(3, 2):
-                        case DEVPIN(3, 3):
-                        case DEVPIN(3, 4):
-                                return IRQ_IXDP2351_SPCI_FIC;
-                        }
-                } else {
-                        /* Device is located indirectly after second bridge */
-                        /* Not supported now */
-                        return -1;
-                }
-                break;
-        }
-        return -1;
-}
-struct hw_pci ixdp2351_pci __initdata = {
-        .nr_controllers = 1,
-        .preinit        = ixp23xx_pci_preinit,
-        .setup          = ixp23xx_pci_setup,
-        .scan           = ixp23xx_pci_scan_bus,
-        .map_irq        = ixdp2351_map_irq,
-};
-int __init ixdp2351_pci_init(void)
-{
-        if (machine_is_ixdp2351())
-                pci_common_init(&ixdp2351_pci);
-        return 0;
-}
-subsys_initcall(ixdp2351_pci_init);
-/*
- * IXDP2351 Static Mapped I/O
- */
-static struct map_desc ixdp2351_io_desc[] __initdata = {
-        {
-                .virtual        = IXDP2351_NP_VIRT_BASE,
-                .pfn            = __phys_to_pfn((u64)IXDP2351_NP_PHYS_BASE),
-                .length         = IXDP2351_NP_PHYS_SIZE,
-                .type           = MT_DEVICE
-        }, {
-                .virtual        = IXDP2351_BB_BASE_VIRT,
-                .pfn            = __phys_to_pfn((u64)IXDP2351_BB_BASE_PHYS),
-                .length         = IXDP2351_BB_SIZE,
-                .type           = MT_DEVICE
-        }
-};
-static void __init ixdp2351_map_io(void)
-{
-        ixp23xx_map_io();
-        iotable_init(ixdp2351_io_desc, ARRAY_SIZE(ixdp2351_io_desc));
-}
-static struct physmap_flash_data ixdp2351_flash_data = {
-        .width          = 1,
-};
-static struct resource ixdp2351_flash_resource = {
-        .start          = 0x90000000,
-        .end            = 0x93ffffff,
-        .flags          = IORESOURCE_MEM,
-};
-static struct platform_device ixdp2351_flash = {
-        .name           = "physmap-flash",
-        .id             = 0,
-        .dev            = {
-                .platform_data  = &ixdp2351_flash_data,
-        },
-        .num_resources  = 1,
-        .resource       = &ixdp2351_flash_resource,
-};
-static void __init ixdp2351_init(void)
-{
-        platform_device_register(&ixdp2351_flash);
-        /*
-         * Mark flash as writeable
-         */
-        IXP23XX_EXP_CS0[0] |= IXP23XX_FLASH_WRITABLE;
-        IXP23XX_EXP_CS0[1] |= IXP23XX_FLASH_WRITABLE;
-        IXP23XX_EXP_CS0[2] |= IXP23XX_FLASH_WRITABLE;
-        IXP23XX_EXP_CS0[3] |= IXP23XX_FLASH_WRITABLE;
-        ixp23xx_sys_init();
-}
-static void ixdp2351_restart(char mode, const char *cmd)
-{
-        /* First try machine specific support */
-        *IXDP2351_CPLD_RESET1_REG = IXDP2351_CPLD_RESET1_MAGIC;
-        (void) *IXDP2351_CPLD_RESET1_REG;
-        *IXDP2351_CPLD_RESET1_REG = IXDP2351_CPLD_RESET1_ENABLE;
-        ixp23xx_restart(mode, cmd);
-}
-MACHINE_START(IXDP2351, "Intel IXDP2351 Development Platform")
-        /* Maintainer: MontaVista Software, Inc. */
-        .map_io         = ixdp2351_map_io,
-        .init_irq       = ixdp2351_init_irq,
-        .timer          = &ixp23xx_timer,
-        .atag_offset    = 0x100,
-        .init_machine   = ixdp2351_init,
-        .restart        = ixdp2351_restart,
-MACHINE_END
diff --git a/arch/arm/mach-ixp23xx/pci.c b/arch/arm/mach-ixp23xx/pci.c
deleted file mode 100644
index 911f5a58e006..000000000000
--- a/arch/arm/mach-ixp23xx/pci.c
+++ /dev/null
@@ -1,294 +0,0 @@
-/*
- * arch/arm/mach-ixp23xx/pci.c
- *
- * PCI routines for IXP23XX based systems
- *
- * Copyright (c) 2005 MontaVista Software, Inc.
- *
- * based on original code:
- *
- * Author: Naeem Afzal <naeem.m.afzal@intel.com>
- * Copyright 2002-2005 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-#include <linux/sched.h>
-#include <linux/kernel.h>
-#include <linux/pci.h>
-#include <linux/interrupt.h>
-#include <linux/mm.h>
-#include <linux/init.h>
-#include <linux/ioport.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <asm/irq.h>
-#include <asm/sizes.h>
-#include <asm/mach/pci.h>
-#include <mach/hardware.h>
-extern int (*external_fault) (unsigned long, struct pt_regs *);
-static volatile int pci_master_aborts = 0;
-#ifdef DEBUG
-#define DBG(x...)       printk(x)
-#else
-#define DBG(x...)
-#endif
-int clear_master_aborts(void);
-static u32
-*ixp23xx_pci_config_addr(unsigned int bus_nr, unsigned int devfn, int where)
-{
-        u32 *paddress;
-        /*
-         * Must be dword aligned
-         */
-        where &= ~3;
-        /*
-         * For top bus, generate type 0, else type 1
-         */
-        if (!bus_nr) {
-                if (PCI_SLOT(devfn) >= 8)
-                        return 0;
-                paddress = (u32 *) (IXP23XX_PCI_CFG0_VIRT
-                                    | (1 << (PCI_SLOT(devfn) + 16))
-                                    | (PCI_FUNC(devfn) << 8) | where);
-        } else {
-                paddress = (u32 *) (IXP23XX_PCI_CFG1_VIRT
-                                    | (bus_nr << 16)
-                                    | (PCI_SLOT(devfn) << 11)
-                                    | (PCI_FUNC(devfn) << 8) | where);
-        }
-        return paddress;
-}
-/*
- * Mask table, bits to mask for quantity of size 1, 2 or 4 bytes.
- * 0 and 3 are not valid indexes...
- */
-static u32 bytemask[] = {
-        /*0*/   0,
-        /*1*/   0xff,
-        /*2*/   0xffff,
-        /*3*/   0,
-        /*4*/   0xffffffff,
-};
-static int ixp23xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
-                                int where, int size, u32 *value)
-{
-        u32 n;
-        u32 *addr;
-        n = where % 4;
-        DBG("In config_read(%d) %d from dev %d:%d:%d\n", size, where,
-                bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
-        addr = ixp23xx_pci_config_addr(bus->number, devfn, where);
-        if (!addr)
-                return PCIBIOS_DEVICE_NOT_FOUND;
-        pci_master_aborts = 0;
-        *value = (*addr >> (8*n)) & bytemask[size];
-        if (pci_master_aborts) {
-                        pci_master_aborts = 0;
-                        *value = 0xffffffff;
-                        return PCIBIOS_DEVICE_NOT_FOUND;
-                }
-        return PCIBIOS_SUCCESSFUL;
-}
-/*
- * We don't do error checking on the address for writes.
- * It's assumed that the user checked for the device existing first
- * by doing a read first.
- */
-static int ixp23xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
-                                        int where, int size, u32 value)
-{
-        u32 mask;
-        u32 *addr;
-        u32 temp;
-        mask = ~(bytemask[size] << ((where % 0x4) * 8));
-        addr = ixp23xx_pci_config_addr(bus->number, devfn, where);
-        if (!addr)
-                return PCIBIOS_DEVICE_NOT_FOUND;
-        temp = (u32) (value) << ((where % 0x4) * 8);
-        *addr = (*addr & mask) | temp;
-        clear_master_aborts();
-        return PCIBIOS_SUCCESSFUL;
-}
-struct pci_ops ixp23xx_pci_ops = {
-        .read   = ixp23xx_pci_read_config,
-        .write  = ixp23xx_pci_write_config,
-};
-struct pci_bus *ixp23xx_pci_scan_bus(int nr, struct pci_sys_data *sysdata)
-{
-        return pci_scan_root_bus(NULL, sysdata->busnr, &ixp23xx_pci_ops,
-                                 sysdata, &sysdata->resources);
-}
-int ixp23xx_pci_abort_handler(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
-{
-        volatile unsigned long temp;
-        unsigned long flags;
-        pci_master_aborts = 1;
-        local_irq_save(flags);
-        temp = *IXP23XX_PCI_CONTROL;
-        /*
-         * master abort and cmd tgt err
-         */
-        if (temp & ((1 << 8) | (1 << 5)))
-                *IXP23XX_PCI_CONTROL = temp;
-        temp = *IXP23XX_PCI_CMDSTAT;
-        if (temp & (1 << 29))
-                *IXP23XX_PCI_CMDSTAT = temp;
-        local_irq_restore(flags);
-        /*
-         * If it was an imprecise abort, then we need to correct the
-         * return address to be _after_ the instruction.
-         */
-        if (fsr & (1 << 10))
-                regs->ARM_pc += 4;
-        return 0;
-}
-int clear_master_aborts(void)
-{
-        volatile u32 temp;
-        temp = *IXP23XX_PCI_CONTROL;
-        /*
-         * master abort and cmd tgt err
-         */
-        if (temp & ((1 << 8) | (1 << 5)))
-                *IXP23XX_PCI_CONTROL = temp;
-        temp = *IXP23XX_PCI_CMDSTAT;
-        if (temp & (1 << 29))
-                *IXP23XX_PCI_CMDSTAT = temp;
-        return 0;
-}
-static void __init ixp23xx_pci_common_init(void)
-{
-#ifdef __ARMEB__
-        *IXP23XX_PCI_CONTROL |= 0x20000;        /* set I/O swapping */
-#endif
-        /*
-         * ADDR_31 needs to be clear for PCI memory access to CPP memory
-         */
-        *IXP23XX_CPP2XSI_CURR_XFER_REG3 &= ~IXP23XX_CPP2XSI_ADDR_31;
-        *IXP23XX_CPP2XSI_CURR_XFER_REG3 |= IXP23XX_CPP2XSI_PSH_OFF;
-        /*
-         * Select correct memory for PCI inbound transactions
-         */
-        if (ixp23xx_cpp_boot()) {
-                *IXP23XX_PCI_CPP_ADDR_BITS &= ~(1 << 1);
-        } else {
-                *IXP23XX_PCI_CPP_ADDR_BITS |= (1 << 1);
-                /*
-                 * Enable coherency on A2 silicon.
-                 */
-                if (arch_is_coherent())
-                        *IXP23XX_CPP2XSI_CURR_XFER_REG3 &= ~IXP23XX_CPP2XSI_COH_OFF;
-        }
-}
-void __init ixp23xx_pci_preinit(void)
-{
-        pcibios_min_io = 0;
-        pcibios_min_mem = 0xe0000000;
-        pci_set_flags(0);
-        ixp23xx_pci_common_init();
-        hook_fault_code(16+6, ixp23xx_pci_abort_handler, SIGBUS, 0,
-                        "PCI config cycle to non-existent device");
-        *IXP23XX_PCI_ADDR_EXT = 0x0000e000;
-}
-/*
- * Prevent PCI layer from seeing the inbound host-bridge resources
- */
-static void __devinit pci_fixup_ixp23xx(struct pci_dev *dev)
-{
-        int i;
-        dev->class &= 0xff;
-        dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
-        for (i = 0; i < PCI_NUM_RESOURCES; i++) {
-                dev->resource[i].start = 0;
-                dev->resource[i].end   = 0;
-                dev->resource[i].flags = 0;
-        }
-}
-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9002, pci_fixup_ixp23xx);
-/*
- * IXP2300 systems often have large resource requirements, so we just
- * use our own resource space.
- */
-static struct resource ixp23xx_pci_mem_space = {
-        .start  = IXP23XX_PCI_MEM_START,
-        .end    = IXP23XX_PCI_MEM_START + IXP23XX_PCI_MEM_SIZE - 1,
-        .flags  = IORESOURCE_MEM,
-        .name   = "PCI Mem Space"
-};
-static struct resource ixp23xx_pci_io_space = {
-        .start  = 0x00000100,
-        .end    = 0x01ffffff,
-        .flags  = IORESOURCE_IO,
-        .name   = "PCI I/O Space"
-};
-int ixp23xx_pci_setup(int nr, struct pci_sys_data *sys)
-{
-        if (nr >= 1)
-                return 0;
-        pci_add_resource_offset(&sys->resources,
-                                &ixp23xx_pci_io_space, sys->io_offset);
-        pci_add_resource_offset(&sys->resources,
-                                &ixp23xx_pci_mem_space, sys->mem_offset);
-        return 1;
-}
-void __init ixp23xx_pci_slave_init(void)
-{
-        ixp23xx_pci_common_init();
-}
diff --git a/arch/arm/mach-ixp23xx/roadrunner.c b/arch/arm/mach-ixp23xx/roadrunner.c
deleted file mode 100644
index eaaa3fa9fd05..000000000000
--- a/arch/arm/mach-ixp23xx/roadrunner.c
+++ /dev/null
@@ -1,180 +0,0 @@
-/*
- * arch/arm/mach-ixp23xx/roadrunner.c
- *
- * RoadRunner board-specific routines
- *
- * Author: Deepak Saxena <dsaxena@plexity.net>
- *
- * Copyright 2005 (c) MontaVista Software, Inc.
- *
- * Based on 2.4 code Copyright 2005 (c) ADI Engineering Corporation
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/spinlock.h>
-#include <linux/sched.h>
-#include <linux/interrupt.h>
-#include <linux/serial.h>
-#include <linux/tty.h>
-#include <linux/bitops.h>
-#include <linux/ioport.h>
-#include <linux/serial_8250.h>
-#include <linux/serial_core.h>
-#include <linux/device.h>
-#include <linux/mm.h>
-#include <linux/pci.h>
-#include <linux/mtd/physmap.h>
-#include <asm/types.h>
-#include <asm/setup.h>
-#include <asm/memory.h>
-#include <mach/hardware.h>
-#include <asm/mach-types.h>
-#include <asm/irq.h>
-#include <asm/tlbflush.h>
-#include <asm/pgtable.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/pci.h>
-/*
- * Interrupt mapping
- */
-#define INTA            IRQ_ROADRUNNER_PCI_INTA
-#define INTB            IRQ_ROADRUNNER_PCI_INTB
-#define INTC            IRQ_ROADRUNNER_PCI_INTC
-#define INTD            IRQ_ROADRUNNER_PCI_INTD
-#define INTC_PIN        IXP23XX_GPIO_PIN_11
-#define INTD_PIN        IXP23XX_GPIO_PIN_12
-static int __init roadrunner_map_irq(const struct pci_dev *dev, u8 idsel,
-        u8 pin)
-{
-        static int pci_card_slot_irq[] = {INTB, INTC, INTD, INTA};
-        static int pmc_card_slot_irq[] = {INTA, INTB, INTC, INTD};
-        static int usb_irq[] = {INTB, INTC, INTD, -1};
-        static int mini_pci_1_irq[] = {INTB, INTC, -1, -1};
-        static int mini_pci_2_irq[] = {INTC, INTD, -1, -1};
-        switch(dev->bus->number) {
-                case 0:
-                        switch(dev->devfn) {
-                        case 0x0: // PCI-PCI bridge
-                                break;
-                        case 0x8: // PCI Card Slot
-                                return pci_card_slot_irq[pin - 1];
-                        case 0x10: // PMC Slot
-                                return pmc_card_slot_irq[pin - 1];
-                        case 0x18: // PMC Slot Secondary Agent
-                                break;
-                        case 0x20: // IXP Processor
-                                break;
-                        default:
-                                return NO_IRQ;
-                        }
-                        break;
-                case 1:
-                        switch(dev->devfn) {
-                        case 0x0: // IDE Controller
-                                return (pin == 1) ? INTC : -1;
-                        case 0x8: // USB fun 0
-                        case 0x9: // USB fun 1
-                        case 0xa: // USB fun 2
-                                return usb_irq[pin - 1];
-                        case 0x10: // Mini PCI 1
-                                return mini_pci_1_irq[pin-1];
-                        case 0x18: // Mini PCI 2
-                                return mini_pci_2_irq[pin-1];
-                        case 0x20: // MEM slot
-                                return (pin == 1) ? INTA : -1;
-                        default:
-                                return NO_IRQ;
-                        }
-                        break;
-                default:
-                        return NO_IRQ;
-        }
-        return NO_IRQ;
-}
-static void __init roadrunner_pci_preinit(void)
-{
-        irq_set_irq_type(IRQ_ROADRUNNER_PCI_INTC, IRQ_TYPE_LEVEL_LOW);
-        irq_set_irq_type(IRQ_ROADRUNNER_PCI_INTD, IRQ_TYPE_LEVEL_LOW);
-        ixp23xx_pci_preinit();
-}
-static struct hw_pci roadrunner_pci __initdata = {
-        .nr_controllers = 1,
-        .preinit        = roadrunner_pci_preinit,
-        .setup          = ixp23xx_pci_setup,
-        .scan           = ixp23xx_pci_scan_bus,
-        .map_irq        = roadrunner_map_irq,
-};
-static int __init roadrunner_pci_init(void)
-{
-        if (machine_is_roadrunner())
-                pci_common_init(&roadrunner_pci);
-        return 0;
-};
-subsys_initcall(roadrunner_pci_init);
-static struct physmap_flash_data roadrunner_flash_data = {
-        .width          = 2,
-};
-static struct resource roadrunner_flash_resource = {
-        .start          = 0x90000000,
-        .end            = 0x93ffffff,
-        .flags          = IORESOURCE_MEM,
-};
-static struct platform_device roadrunner_flash = {
-        .name           = "physmap-flash",
-        .id             = 0,
-        .dev            = {
-                .platform_data  = &roadrunner_flash_data,
-        },
-        .num_resources  = 1,
-        .resource       = &roadrunner_flash_resource,
-};
-static void __init roadrunner_init(void)
-{
-        platform_device_register(&roadrunner_flash);
-        /*
-         * Mark flash as writeable
-         */
-        IXP23XX_EXP_CS0[0] |= IXP23XX_FLASH_WRITABLE;
-        IXP23XX_EXP_CS0[1] |= IXP23XX_FLASH_WRITABLE;
-        IXP23XX_EXP_CS0[2] |= IXP23XX_FLASH_WRITABLE;
-        IXP23XX_EXP_CS0[3] |= IXP23XX_FLASH_WRITABLE;
-        ixp23xx_sys_init();
-}
-MACHINE_START(ROADRUNNER, "ADI Engineering RoadRunner Development Platform")
-        /* Maintainer: Deepak Saxena */
-        .map_io         = ixp23xx_map_io,
-        .init_irq       = ixp23xx_init_irq,
-        .timer          = &ixp23xx_timer,
-        .atag_offset    = 0x100,
-        .init_machine   = roadrunner_init,
-        .restart        = ixp23xx_restart,
-MACHINE_END
diff --git a/arch/arm/mach-ixp4xx/avila-pci.c b/arch/arm/mach-ixp4xx/avila-pci.c
index 8fea0a3c5246..548c7d43ade6 100644
--- a/arch/arm/mach-ixp4xx/avila-pci.c
+++ b/arch/arm/mach-ixp4xx/avila-pci.c
@@ -65,10 +65,9 @@ static int __init avila_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 struct hw_pci avila_pci __initdata = {
        .nr_controllers = 1,
+        .ops            = &ixp4xx_ops,
        .preinit        = avila_pci_preinit,
-        .swizzle        = pci_std_swizzle,
        .setup          = ixp4xx_setup,
-        .scan           = ixp4xx_scan_bus,
        .map_irq        = avila_map_irq,
 };
diff --git a/arch/arm/mach-ixp4xx/common-pci.c b/arch/arm/mach-ixp4xx/common-pci.c
index d5719eb42591..1694f01ce2b6 100644
--- a/arch/arm/mach-ixp4xx/common-pci.c
+++ b/arch/arm/mach-ixp4xx/common-pci.c
@@ -480,12 +480,6 @@ int ixp4xx_setup(int nr, struct pci_sys_data *sys)
        return 1;
 }
-struct pci_bus * __devinit ixp4xx_scan_bus(int nr, struct pci_sys_data *sys)
-{
-        return pci_scan_root_bus(NULL, sys->busnr, &ixp4xx_ops, sys,
-                                 &sys->resources);
-}
 int dma_set_coherent_mask(struct device *dev, u64 mask)
 {
        if (mask >= SZ_64M - 1)
diff --git a/arch/arm/mach-ixp4xx/coyote-pci.c b/arch/arm/mach-ixp4xx/coyote-pci.c
index 71f5c9c60fc3..5d14ce2aee6d 100644
--- a/arch/arm/mach-ixp4xx/coyote-pci.c
+++ b/arch/arm/mach-ixp4xx/coyote-pci.c
@@ -48,10 +48,9 @@ static int __init coyote_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 struct hw_pci coyote_pci __initdata = {
        .nr_controllers = 1,
+        .ops            = &ixp4xx_ops,
        .preinit =        coyote_pci_preinit,
-        .swizzle =        pci_std_swizzle,
        .setup =          ixp4xx_setup,
-        .scan =           ixp4xx_scan_bus,
        .map_irq =        coyote_map_irq,
 };
diff --git a/arch/arm/mach-ixp4xx/dsmg600-pci.c b/arch/arm/mach-ixp4xx/dsmg600-pci.c
index 0532510b5e8c..8dca76937723 100644
--- a/arch/arm/mach-ixp4xx/dsmg600-pci.c
+++ b/arch/arm/mach-ixp4xx/dsmg600-pci.c
@@ -62,10 +62,9 @@ static int __init dsmg600_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 struct hw_pci __initdata dsmg600_pci = {
        .nr_controllers = 1,
+        .ops            = &ixp4xx_ops,
        .preinit        = dsmg600_pci_preinit,
-        .swizzle        = pci_std_swizzle,
        .setup          = ixp4xx_setup,
-        .scan           = ixp4xx_scan_bus,
        .map_irq        = dsmg600_map_irq,
 };
diff --git a/arch/arm/mach-ixp4xx/fsg-pci.c b/arch/arm/mach-ixp4xx/fsg-pci.c
index d2ac803328f7..fd4a8625b4ae 100644
--- a/arch/arm/mach-ixp4xx/fsg-pci.c
+++ b/arch/arm/mach-ixp4xx/fsg-pci.c
@@ -59,10 +59,9 @@ static int __init fsg_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 struct hw_pci fsg_pci __initdata = {
        .nr_controllers = 1,
+        .ops            = &ixp4xx_ops,
        .preinit =        fsg_pci_preinit,
-        .swizzle =        pci_std_swizzle,
        .setup =          ixp4xx_setup,
-        .scan =           ixp4xx_scan_bus,
        .map_irq =        fsg_map_irq,
 };
diff --git a/arch/arm/mach-ixp4xx/gateway7001-pci.c b/arch/arm/mach-ixp4xx/gateway7001-pci.c
index 76581fb467c4..d9d6cc089707 100644
--- a/arch/arm/mach-ixp4xx/gateway7001-pci.c
+++ b/arch/arm/mach-ixp4xx/gateway7001-pci.c
@@ -47,10 +47,9 @@ static int __init gateway7001_map_irq(const struct pci_dev *dev, u8 slot,
 struct hw_pci gateway7001_pci __initdata = {
        .nr_controllers = 1,
+        .ops            = &ixp4xx_ops,
        .preinit =        gateway7001_pci_preinit,
-        .swizzle =        pci_std_swizzle,
        .setup =          ixp4xx_setup,
-        .scan =           ixp4xx_scan_bus,
        .map_irq =        gateway7001_map_irq,
 };
diff --git a/arch/arm/mach-ixp4xx/goramo_mlr.c b/arch/arm/mach-ixp4xx/goramo_mlr.c
index 46bb924962ee..b800a031207c 100644
--- a/arch/arm/mach-ixp4xx/goramo_mlr.c
+++ b/arch/arm/mach-ixp4xx/goramo_mlr.c
@@ -473,11 +473,10 @@ static int __init gmlr_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 static struct hw_pci gmlr_hw_pci __initdata = {
        .nr_controllers = 1,
+        .ops            = &ixp4xx_ops,
        .preinit        = gmlr_pci_preinit,
        .postinit       = gmlr_pci_postinit,
-        .swizzle        = pci_std_swizzle,
        .setup          = ixp4xx_setup,
-        .scan           = ixp4xx_scan_bus,
        .map_irq        = gmlr_map_irq,
 };
diff --git a/arch/arm/mach-ixp4xx/gtwx5715-pci.c b/arch/arm/mach-ixp4xx/gtwx5715-pci.c
index d68fc068c38d..551d114c9e14 100644
--- a/arch/arm/mach-ixp4xx/gtwx5715-pci.c
+++ b/arch/arm/mach-ixp4xx/gtwx5715-pci.c
@@ -67,10 +67,9 @@ static int __init gtwx5715_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 struct hw_pci gtwx5715_pci __initdata = {
        .nr_controllers = 1,
+        .ops            = &ixp4xx_ops,
        .preinit =        gtwx5715_pci_preinit,
-        .swizzle =        pci_std_swizzle,
        .setup =          ixp4xx_setup,
-        .scan =           ixp4xx_scan_bus,
        .map_irq =        gtwx5715_map_irq,
 };
diff --git a/arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h b/arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h
index 292d55ed2113..cf03614d250d 100644
--- a/arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h
+++ b/arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h
@@ -75,4 +75,7 @@ struct ixp46x_ts_regs {
 #define TX_SNAPSHOT_LOCKED (1<<0)
 #define RX_SNAPSHOT_LOCKED (1<<1)
+/* The ptp_ixp46x module will set this variable */
+extern int ixp46x_phc_index;
 #endif
diff --git a/arch/arm/mach-ixp4xx/include/mach/platform.h b/arch/arm/mach-ixp4xx/include/mach/platform.h
index b66bedc64de1..5bce94aacca9 100644
--- a/arch/arm/mach-ixp4xx/include/mach/platform.h
+++ b/arch/arm/mach-ixp4xx/include/mach/platform.h
@@ -130,7 +130,7 @@ extern void ixp4xx_restart(char, const char *);
 extern void ixp4xx_pci_preinit(void);
 struct pci_sys_data;
 extern int ixp4xx_setup(int nr, struct pci_sys_data *sys);
-extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys);
+extern struct pci_ops ixp4xx_ops;
 /*
 * GPIO-functions
diff --git a/arch/arm/mach-ixp4xx/ixdp425-pci.c b/arch/arm/mach-ixp4xx/ixdp425-pci.c
index fffd8c5e40bf..318424dd3c50 100644
--- a/arch/arm/mach-ixp4xx/ixdp425-pci.c
+++ b/arch/arm/mach-ixp4xx/ixdp425-pci.c
@@ -60,10 +60,9 @@ static int __init ixdp425_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 struct hw_pci ixdp425_pci __initdata = {
        .nr_controllers = 1,
+        .ops            = &ixp4xx_ops,
        .preinit        = ixdp425_pci_preinit,
-        .swizzle        = pci_std_swizzle,
        .setup          = ixp4xx_setup,
-        .scan           = ixp4xx_scan_bus,
        .map_irq        = ixdp425_map_irq,
 };
diff --git a/arch/arm/mach-ixp4xx/ixdpg425-pci.c b/arch/arm/mach-ixp4xx/ixdpg425-pci.c
index 34efe75015ec..1f8717ba13dc 100644
--- a/arch/arm/mach-ixp4xx/ixdpg425-pci.c
+++ b/arch/arm/mach-ixp4xx/ixdpg425-pci.c
@@ -42,10 +42,9 @@ static int __init ixdpg425_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 struct hw_pci ixdpg425_pci __initdata = {
        .nr_controllers = 1,
+        .ops            = &ixp4xx_ops,
        .preinit =        ixdpg425_pci_preinit,
-        .swizzle =        pci_std_swizzle,
        .setup =          ixp4xx_setup,
-        .scan =           ixp4xx_scan_bus,
        .map_irq =        ixdpg425_map_irq,
 };
diff --git a/arch/arm/mach-ixp4xx/miccpt-pci.c b/arch/arm/mach-ixp4xx/miccpt-pci.c
index ca0bae7fca90..d114ccd2017c 100644
--- a/arch/arm/mach-ixp4xx/miccpt-pci.c
+++ b/arch/arm/mach-ixp4xx/miccpt-pci.c
@@ -61,10 +61,9 @@ static int __init miccpt_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 struct hw_pci miccpt_pci __initdata = {
        .nr_controllers = 1,
+        .ops            = &ixp4xx_ops,
        .preinit        = miccpt_pci_preinit,
-        .swizzle        = pci_std_swizzle,
        .setup          = ixp4xx_setup,
-        .scan           = ixp4xx_scan_bus,
        .map_irq        = miccpt_map_irq,
 };
diff --git a/arch/arm/mach-ixp4xx/nas100d-pci.c b/arch/arm/mach-ixp4xx/nas100d-pci.c
index 5434ccf553eb..8f0eba0a6800 100644
--- a/arch/arm/mach-ixp4xx/nas100d-pci.c
+++ b/arch/arm/mach-ixp4xx/nas100d-pci.c
@@ -58,10 +58,9 @@ static int __init nas100d_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 struct hw_pci __initdata nas100d_pci = {
        .nr_controllers = 1,
+        .ops            = &ixp4xx_ops,
        .preinit        = nas100d_pci_preinit,
-        .swizzle        = pci_std_swizzle,
        .setup          = ixp4xx_setup,
-        .scan           = ixp4xx_scan_bus,
        .map_irq        = nas100d_map_irq,
 };
diff --git a/arch/arm/mach-ixp4xx/nslu2-pci.c b/arch/arm/mach-ixp4xx/nslu2-pci.c
index b57160535e47..032defe111aa 100644
--- a/arch/arm/mach-ixp4xx/nslu2-pci.c
+++ b/arch/arm/mach-ixp4xx/nslu2-pci.c
@@ -54,10 +54,9 @@ static int __init nslu2_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 struct hw_pci __initdata nslu2_pci = {
        .nr_controllers = 1,
+        .ops            = &ixp4xx_ops,
        .preinit        = nslu2_pci_preinit,
-        .swizzle        = pci_std_swizzle,
        .setup          = ixp4xx_setup,
-        .scan           = ixp4xx_scan_bus,
        .map_irq        = nslu2_map_irq,
 };
diff --git a/arch/arm/mach-ixp4xx/vulcan-pci.c b/arch/arm/mach-ixp4xx/vulcan-pci.c
index 0bc3f34c282f..a4220fa5e0c3 100644
--- a/arch/arm/mach-ixp4xx/vulcan-pci.c
+++ b/arch/arm/mach-ixp4xx/vulcan-pci.c
@@ -56,10 +56,9 @@ static int __init vulcan_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 struct hw_pci vulcan_pci __initdata = {
        .nr_controllers = 1,
+        .ops            = &ixp4xx_ops,
        .preinit        = vulcan_pci_preinit,
-        .swizzle        = pci_std_swizzle,
        .setup          = ixp4xx_setup,
-        .scan           = ixp4xx_scan_bus,
        .map_irq        = vulcan_map_irq,
 };
diff --git a/arch/arm/mach-ixp4xx/wg302v2-pci.c b/arch/arm/mach-ixp4xx/wg302v2-pci.c
index f27dfcfe811b..c92e5b82af36 100644
--- a/arch/arm/mach-ixp4xx/wg302v2-pci.c
+++ b/arch/arm/mach-ixp4xx/wg302v2-pci.c
@@ -46,10 +46,9 @@ static int __init wg302v2_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 struct hw_pci wg302v2_pci __initdata = {
        .nr_controllers = 1,
+        .ops = &ixp4xx_ops,
        .preinit =        wg302v2_pci_preinit,
-        .swizzle =        pci_std_swizzle,
        .setup =          ixp4xx_setup,
-        .scan =           ixp4xx_scan_bus,
        .map_irq =        wg302v2_map_irq,
 };
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 90ceab761929..199764fe0fb0 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -58,6 +58,28 @@ config MACH_DREAMPLUG_DT
          Say 'Y' here if you want your kernel to support the
          Marvell DreamPlug (Flattened Device Tree).
+config MACH_ICONNECT_DT
+        bool "Iomega Iconnect (Flattened Device Tree)"
+        select ARCH_KIRKWOOD_DT
+        help
+          Say 'Y' here to enable Iomega Iconnect support.
+config MACH_DLINK_KIRKWOOD_DT
+        bool "D-Link Kirkwood-based NAS (Flattened Device Tree)"
+        select ARCH_KIRKWOOD_DT
+        help
+          Say 'Y' here if you want your kernel to support the
+          Kirkwood-based D-Link NASes such as DNS-320 & DNS-325,
+          using Flattened Device Tree.
+config MACH_IB62X0_DT
+        bool "RaidSonic IB-NAS6210, IB-NAS6220 (Flattened Device Tree)"
+        select ARCH_KIRKWOOD_DT
+        help
+          Say 'Y' here if you want your kernel to support the
+          RaidSonic IB-NAS6210 & IB-NAS6220 devices, using
+          Flattened Device Tree.
 config MACH_TS219
        bool "QNAP TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and TS-219P+ Turbo NAS"
        help
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
index e299a9576bf0..d2b05907b10e 100644
--- a/arch/arm/mach-kirkwood/Makefile
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -22,3 +22,6 @@ obj-$(CONFIG_MACH_T5325)		+= t5325-setup.o
 obj-$(CONFIG_CPU_IDLE)                  += cpuidle.o
 obj-$(CONFIG_ARCH_KIRKWOOD_DT)          += board-dt.o
 obj-$(CONFIG_MACH_DREAMPLUG_DT)         += board-dreamplug.o
+obj-$(CONFIG_MACH_ICONNECT_DT)          += board-iconnect.o
+obj-$(CONFIG_MACH_DLINK_KIRKWOOD_DT)    += board-dnskw.o
+obj-$(CONFIG_MACH_IB62X0_DT)            += board-ib62x0.o
diff --git a/arch/arm/mach-kirkwood/Makefile.boot b/arch/arm/mach-kirkwood/Makefile.boot
index 16f938522304..02edbdf5b065 100644
--- a/arch/arm/mach-kirkwood/Makefile.boot
+++ b/arch/arm/mach-kirkwood/Makefile.boot
@@ -3,3 +3,7 @@ params_phys-y	:= 0x00000100
 initrd_phys-y   := 0x00800000
 dtb-$(CONFIG_MACH_DREAMPLUG_DT) += kirkwood-dreamplug.dtb
+dtb-$(CONFIG_MACH_DLINK_KIRKWOOD_DT) += kirkwood-dns320.dtb
+dtb-$(CONFIG_MACH_DLINK_KIRKWOOD_DT) += kirkwood-dns325.dtb
+dtb-$(CONFIG_MACH_ICONNECT_DT) += kirkwood-iconnect.dtb
+dtb-$(CONFIG_MACH_IB62X0_DT) += kirkwood-ib62x0.dtb
diff --git a/arch/arm/mach-kirkwood/board-dnskw.c b/arch/arm/mach-kirkwood/board-dnskw.c
new file mode 100644
index 000000000000..58c2d68f9443
--- /dev/null
+++ b/arch/arm/mach-kirkwood/board-dnskw.c
@@ -0,0 +1,275 @@
+/*
+ * Copyright 2012 (C), Jamie Lentin <jm@lentin.co.uk>
+ *
+ * arch/arm/mach-kirkwood/board-dnskw.c
+ *
+ * D-link DNS-320 & DNS-325 NAS Init for drivers not converted to
+ * flattened device tree yet.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/i2c.h>
+#include <linux/ata_platform.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/of.h>
+#include <linux/gpio.h>
+#include <linux/input.h>
+#include <linux/gpio_keys.h>
+#include <linux/gpio-fan.h>
+#include <linux/leds.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <mach/kirkwood.h>
+#include <mach/bridge-regs.h>
+#include "common.h"
+#include "mpp.h"
+static struct mv643xx_eth_platform_data dnskw_ge00_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(8),
+};
+static struct mv_sata_platform_data dnskw_sata_data = {
+        .n_ports        = 2,
+};
+static unsigned int dnskw_mpp_config[] __initdata = {
+        MPP13_UART1_TXD,        /* Custom ... */
+        MPP14_UART1_RXD,        /* ... Controller (DNS-320 only) */
+        MPP20_SATA1_ACTn,       /* LED: White Right HDD */
+        MPP21_SATA0_ACTn,       /* LED: White Left HDD */
+        MPP24_GPIO,
+        MPP25_GPIO,
+        MPP26_GPIO,     /* LED: Power */
+        MPP27_GPIO,     /* LED: Red Right HDD */
+        MPP28_GPIO,     /* LED: Red Left HDD */
+        MPP29_GPIO,     /* LED: Red USB (DNS-325 only) */
+        MPP30_GPIO,
+        MPP31_GPIO,
+        MPP32_GPIO,
+        MPP33_GPO,
+        MPP34_GPIO,     /* Button: Front power */
+        MPP35_GPIO,     /* LED: Red USB (DNS-320 only) */
+        MPP36_GPIO,     /* Power: Turn off board */
+        MPP37_GPIO,     /* Power: Turn back on after power failure */
+        MPP38_GPIO,
+        MPP39_GPIO,     /* Power: SATA0 */
+        MPP40_GPIO,     /* Power: SATA1 */
+        MPP41_GPIO,     /* SATA0 present */
+        MPP42_GPIO,     /* SATA1 present */
+        MPP43_GPIO,     /* LED: White USB */
+        MPP44_GPIO,     /* Fan: Tachometer Pin */
+        MPP45_GPIO,     /* Fan: high speed */
+        MPP46_GPIO,     /* Fan: low speed */
+        MPP47_GPIO,     /* Button: Back unmount */
+        MPP48_GPIO,     /* Button: Back reset */
+        MPP49_GPIO,     /* Temp Alarm (DNS-325) Pin of U5 (DNS-320) */
+        0
+};
+static struct gpio_led dns325_led_pins[] = {
+        {
+                .name   = "dns325:white:power",
+                .gpio   = 26,
+                .active_low = 1,
+                .default_trigger = "default-on",
+        },
+        {
+                .name   = "dns325:white:usb",
+                .gpio   = 43,
+                .active_low = 1,
+        },
+        {
+                .name   = "dns325:red:l_hdd",
+                .gpio   = 28,
+                .active_low = 1,
+        },
+        {
+                .name   = "dns325:red:r_hdd",
+                .gpio   = 27,
+                .active_low = 1,
+        },
+        {
+                .name   = "dns325:red:usb",
+                .gpio   = 29,
+                .active_low = 1,
+        },
+};
+static struct gpio_led_platform_data dns325_led_data = {
+        .num_leds       = ARRAY_SIZE(dns325_led_pins),
+        .leds           = dns325_led_pins,
+};
+static struct platform_device dns325_led_device = {
+        .name           = "leds-gpio",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &dns325_led_data,
+        },
+};
+static struct gpio_led dns320_led_pins[] = {
+        {
+                .name   = "dns320:blue:power",
+                .gpio   = 26,
+                .active_low = 1,
+                .default_trigger = "default-on",
+        },
+        {
+                .name   = "dns320:blue:usb",
+                .gpio   = 43,
+                .active_low = 1,
+        },
+        {
+                .name   = "dns320:orange:l_hdd",
+                .gpio   = 28,
+                .active_low = 1,
+        },
+        {
+                .name   = "dns320:orange:r_hdd",
+                .gpio   = 27,
+                .active_low = 1,
+        },
+        {
+                .name   = "dns320:orange:usb",
+                .gpio   = 35,
+                .active_low = 1,
+        },
+};
+static struct gpio_led_platform_data dns320_led_data = {
+        .num_leds       = ARRAY_SIZE(dns320_led_pins),
+        .leds           = dns320_led_pins,
+};
+static struct platform_device dns320_led_device = {
+        .name           = "leds-gpio",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &dns320_led_data,
+        },
+};
+static struct i2c_board_info dns325_i2c_board_info[] __initdata = {
+        {
+                I2C_BOARD_INFO("lm75", 0x48),
+        },
+        /* Something at 0x0c also */
+};
+static struct gpio_keys_button dnskw_button_pins[] = {
+        {
+                .code           = KEY_POWER,
+                .gpio           = 34,
+                .desc           = "Power button",
+                .active_low     = 1,
+        },
+        {
+                .code           = KEY_EJECTCD,
+                .gpio           = 47,
+                .desc           = "USB unmount button",
+                .active_low     = 1,
+        },
+        {
+                .code           = KEY_RESTART,
+                .gpio           = 48,
+                .desc           = "Reset button",
+                .active_low     = 1,
+        },
+};
+static struct gpio_keys_platform_data dnskw_button_data = {
+        .buttons        = dnskw_button_pins,
+        .nbuttons       = ARRAY_SIZE(dnskw_button_pins),
+};
+static struct platform_device dnskw_button_device = {
+        .name           = "gpio-keys",
+        .id             = -1,
+        .num_resources  = 0,
+        .dev            = {
+                .platform_data  = &dnskw_button_data,
+        }
+};
+/* Fan: ADDA AD045HB-G73 40mm 6000rpm@5v */
+static struct gpio_fan_speed dnskw_fan_speed[] = {
+        {    0,  0 },
+        { 3000,  1 },
+        { 6000,  2 },
+};
+static unsigned dnskw_fan_pins[] = {46, 45};
+static struct gpio_fan_platform_data dnskw_fan_data = {
+        .num_ctrl       = ARRAY_SIZE(dnskw_fan_pins),
+        .ctrl           = dnskw_fan_pins,
+        .num_speed      = ARRAY_SIZE(dnskw_fan_speed),
+        .speed          = dnskw_fan_speed,
+};
+static struct platform_device dnskw_fan_device = {
+        .name   = "gpio-fan",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &dnskw_fan_data,
+        },
+};
+static void dnskw_power_off(void)
+{
+        gpio_set_value(36, 1);
+}
+/* Register any GPIO for output and set the value */
+static void __init dnskw_gpio_register(unsigned gpio, char *name, int def)
+{
+        if (gpio_request(gpio, name) == 0 &&
+            gpio_direction_output(gpio, 0) == 0) {
+                gpio_set_value(gpio, def);
+                if (gpio_export(gpio, 0) != 0)
+                        pr_err("dnskw: Failed to export GPIO %s\n", name);
+        } else
+                pr_err("dnskw: Failed to register %s\n", name);
+}
+void __init dnskw_init(void)
+{
+        kirkwood_mpp_conf(dnskw_mpp_config);
+        kirkwood_ehci_init();
+        kirkwood_ge00_init(&dnskw_ge00_data);
+        kirkwood_sata_init(&dnskw_sata_data);
+        kirkwood_i2c_init();
+        platform_device_register(&dnskw_button_device);
+        platform_device_register(&dnskw_fan_device);
+        if (of_machine_is_compatible("dlink,dns-325")) {
+                i2c_register_board_info(0, dns325_i2c_board_info,
+                                        ARRAY_SIZE(dns325_i2c_board_info));
+                platform_device_register(&dns325_led_device);
+        } else if (of_machine_is_compatible("dlink,dns-320"))
+                platform_device_register(&dns320_led_device);
+        /* Register power-off GPIO. */
+        if (gpio_request(36, "dnskw:power:off") == 0
+            && gpio_direction_output(36, 0) == 0)
+                pm_power_off = dnskw_power_off;
+        else
+                pr_err("dnskw: failed to configure power-off GPIO\n");
+        /* Ensure power is supplied to both HDDs */
+        dnskw_gpio_register(39, "dnskw:power:sata0", 1);
+        dnskw_gpio_register(40, "dnskw:power:sata1", 1);
+        /* Set NAS to turn back on after a power failure */
+        dnskw_gpio_register(37, "dnskw:power:recover", 1);
+}
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index 1c672d9e6656..10d1969b9e3a 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -14,6 +14,7 @@
 #include <linux/init.h>
 #include <linux/of.h>
 #include <linux/of_platform.h>
+#include <linux/kexec.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <mach/bridge-regs.h>
@@ -55,11 +56,24 @@ static void __init kirkwood_dt_init(void)
        if (of_machine_is_compatible("globalscale,dreamplug"))
                dreamplug_init();
+        if (of_machine_is_compatible("dlink,dns-kirkwood"))
+                dnskw_init();
+        if (of_machine_is_compatible("iom,iconnect"))
+                iconnect_init();
+        if (of_machine_is_compatible("raidsonic,ib-nas62x0"))
+                ib62x0_init();
        of_platform_populate(NULL, kirkwood_dt_match_table, NULL, NULL);
 }
 static const char *kirkwood_dt_board_compat[] = {
        "globalscale,dreamplug",
+        "dlink,dns-320",
+        "dlink,dns-325",
+        "iom,iconnect",
+        "raidsonic,ib-nas62x0",
        NULL
 };
diff --git a/arch/arm/mach-kirkwood/board-ib62x0.c b/arch/arm/mach-kirkwood/board-ib62x0.c
new file mode 100644
index 000000000000..eddf1df8891f
--- /dev/null
+++ b/arch/arm/mach-kirkwood/board-ib62x0.c
@@ -0,0 +1,143 @@
+/*
+ * Copyright 2012 (C), Simon Baatz <gmbnomis@gmail.com>
+ *
+ * arch/arm/mach-kirkwood/board-ib62x0.c
+ *
+ * RaidSonic ICY BOX IB-NAS6210 & IB-NAS6220 init for drivers not
+ * converted to flattened device tree yet.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/partitions.h>
+#include <linux/ata_platform.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/gpio.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+#include <linux/leds.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/kirkwood.h>
+#include "common.h"
+#include "mpp.h"
+#define IB62X0_GPIO_POWER_OFF   24
+static struct mv643xx_eth_platform_data ib62x0_ge00_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(8),
+};
+static struct mv_sata_platform_data ib62x0_sata_data = {
+        .n_ports        = 2,
+};
+static unsigned int ib62x0_mpp_config[] __initdata = {
+        MPP0_NF_IO2,
+        MPP1_NF_IO3,
+        MPP2_NF_IO4,
+        MPP3_NF_IO5,
+        MPP4_NF_IO6,
+        MPP5_NF_IO7,
+        MPP18_NF_IO0,
+        MPP19_NF_IO1,
+        MPP22_GPIO,     /* OS LED red */
+        MPP24_GPIO,     /* Power off device */
+        MPP25_GPIO,     /* OS LED green */
+        MPP27_GPIO,     /* USB transfer LED */
+        MPP28_GPIO,     /* Reset button */
+        MPP29_GPIO,     /* USB Copy button */
+        0
+};
+static struct gpio_led ib62x0_led_pins[] = {
+        {
+                .name                   = "ib62x0:green:os",
+                .default_trigger        = "default-on",
+                .gpio                   = 25,
+                .active_low             = 0,
+        },
+        {
+                .name                   = "ib62x0:red:os",
+                .default_trigger        = "none",
+                .gpio                   = 22,
+                .active_low             = 0,
+        },
+        {
+                .name                   = "ib62x0:red:usb_copy",
+                .default_trigger        = "none",
+                .gpio                   = 27,
+                .active_low             = 0,
+        },
+};
+static struct gpio_led_platform_data ib62x0_led_data = {
+        .leds           = ib62x0_led_pins,
+        .num_leds       = ARRAY_SIZE(ib62x0_led_pins),
+};
+static struct platform_device ib62x0_led_device = {
+        .name   = "leds-gpio",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &ib62x0_led_data,
+        }
+};
+static struct gpio_keys_button ib62x0_button_pins[] = {
+        {
+                .code           = KEY_COPY,
+                .gpio           = 29,
+                .desc           = "USB Copy",
+                .active_low     = 1,
+        },
+        {
+                .code           = KEY_RESTART,
+                .gpio           = 28,
+                .desc           = "Reset",
+                .active_low     = 1,
+        },
+};
+static struct gpio_keys_platform_data ib62x0_button_data = {
+        .buttons        = ib62x0_button_pins,
+        .nbuttons       = ARRAY_SIZE(ib62x0_button_pins),
+};
+static struct platform_device ib62x0_button_device = {
+        .name           = "gpio-keys",
+        .id             = -1,
+        .num_resources  = 0,
+        .dev            = {
+                .platform_data  = &ib62x0_button_data,
+        }
+};
+static void ib62x0_power_off(void)
+{
+        gpio_set_value(IB62X0_GPIO_POWER_OFF, 1);
+}
+void __init ib62x0_init(void)
+{
+        /*
+         * Basic setup. Needs to be called early.
+         */
+        kirkwood_mpp_conf(ib62x0_mpp_config);
+        kirkwood_ehci_init();
+        kirkwood_ge00_init(&ib62x0_ge00_data);
+        kirkwood_sata_init(&ib62x0_sata_data);
+        platform_device_register(&ib62x0_led_device);
+        platform_device_register(&ib62x0_button_device);
+        if (gpio_request(IB62X0_GPIO_POWER_OFF, "ib62x0:power:off") == 0 &&
+            gpio_direction_output(IB62X0_GPIO_POWER_OFF, 0) == 0)
+                pm_power_off = ib62x0_power_off;
+        else
+                pr_err("board-ib62x0: failed to configure power-off GPIO\n");
+}
diff --git a/arch/arm/mach-kirkwood/board-iconnect.c b/arch/arm/mach-kirkwood/board-iconnect.c
new file mode 100644
index 000000000000..2222c5739519
--- /dev/null
+++ b/arch/arm/mach-kirkwood/board-iconnect.c
@@ -0,0 +1,165 @@
+/*
+ * arch/arm/mach-kirkwood/board-iconnect.c
+ *
+ * Iomega i-connect Board Setup
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_fdt.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/gpio.h>
+#include <linux/leds.h>
+#include <linux/spi/flash.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/orion_spi.h>
+#include <linux/i2c.h>
+#include <linux/input.h>
+#include <linux/gpio_keys.h>
+#include <asm/mach/arch.h>
+#include <mach/kirkwood.h>
+#include "common.h"
+#include "mpp.h"
+static struct mv643xx_eth_platform_data iconnect_ge00_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(11),
+};
+static struct gpio_led iconnect_led_pins[] = {
+        {
+                .name           = "led_level",
+                .gpio           = 41,
+                .default_trigger = "default-on",
+        }, {
+                .name           = "power:blue",
+                .gpio           = 42,
+                .default_trigger = "timer",
+        }, {
+                .name           = "power:red",
+                .gpio           = 43,
+        }, {
+                .name           = "usb1:blue",
+                .gpio           = 44,
+        }, {
+                .name           = "usb2:blue",
+                .gpio           = 45,
+        }, {
+                .name           = "usb3:blue",
+                .gpio           = 46,
+        }, {
+                .name           = "usb4:blue",
+                .gpio           = 47,
+        }, {
+                .name           = "otb:blue",
+                .gpio           = 48,
+        },
+};
+static struct gpio_led_platform_data iconnect_led_data = {
+        .leds           = iconnect_led_pins,
+        .num_leds       = ARRAY_SIZE(iconnect_led_pins),
+        .gpio_blink_set = orion_gpio_led_blink_set,
+};
+static struct platform_device iconnect_leds = {
+        .name   = "leds-gpio",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &iconnect_led_data,
+        }
+};
+static unsigned int iconnect_mpp_config[] __initdata = {
+        MPP12_GPIO,
+        MPP35_GPIO,
+        MPP41_GPIO,
+        MPP42_GPIO,
+        MPP43_GPIO,
+        MPP44_GPIO,
+        MPP45_GPIO,
+        MPP46_GPIO,
+        MPP47_GPIO,
+        MPP48_GPIO,
+        0
+};
+static struct i2c_board_info __initdata iconnect_board_info[] = {
+        {
+                I2C_BOARD_INFO("lm63", 0x4c),
+        },
+};
+static struct mtd_partition iconnect_nand_parts[] = {
+        {
+                .name = "flash",
+                .offset = 0,
+                .size = MTDPART_SIZ_FULL,
+        },
+};
+/* yikes... theses are the original input buttons */
+/* but I'm not convinced by the sw event choices  */
+static struct gpio_keys_button iconnect_buttons[] = {
+        {
+                .type           = EV_SW,
+                .code           = SW_LID,
+                .gpio           = 12,
+                .desc           = "Reset Button",
+                .active_low     = 1,
+                .debounce_interval = 100,
+        }, {
+                .type           = EV_SW,
+                .code           = SW_TABLET_MODE,
+                .gpio           = 35,
+                .desc           = "OTB Button",
+                .active_low     = 1,
+                .debounce_interval = 100,
+        },
+};
+static struct gpio_keys_platform_data iconnect_button_data = {
+        .buttons        = iconnect_buttons,
+        .nbuttons       = ARRAY_SIZE(iconnect_buttons),
+};
+static struct platform_device iconnect_button_device = {
+        .name           = "gpio-keys",
+        .id             = -1,
+        .num_resources  = 0,
+        .dev        = {
+                .platform_data  = &iconnect_button_data,
+        },
+};
+void __init iconnect_init(void)
+{
+        kirkwood_mpp_conf(iconnect_mpp_config);
+        kirkwood_nand_init(ARRAY_AND_SIZE(iconnect_nand_parts), 25);
+        kirkwood_i2c_init();
+        i2c_register_board_info(0, iconnect_board_info,
+                ARRAY_SIZE(iconnect_board_info));
+        kirkwood_ehci_init();
+        kirkwood_ge00_init(&iconnect_ge00_data);
+        platform_device_register(&iconnect_button_device);
+        platform_device_register(&iconnect_leds);
+}
+static int __init iconnect_pci_init(void)
+{
+        if (of_machine_is_compatible("iom,iconnect"))
+                kirkwood_pcie_init(KW_PCIE0);
+        return 0;
+}
+subsys_initcall(iconnect_pci_init);
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index a02cae881f2f..3ad037385a5e 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -15,6 +15,7 @@
 #include <linux/ata_platform.h>
 #include <linux/mtd/nand.h>
 #include <linux/dma-mapping.h>
+#include <linux/of.h>
 #include <net/dsa.h>
 #include <asm/page.h>
 #include <asm/timex.h>
@@ -482,6 +483,9 @@ static int __init kirkwood_clock_gate(void)
        unsigned int curr = readl(CLOCK_GATING_CTRL);
        u32 dev, rev;
+#ifdef CONFIG_OF
+        struct device_node *np;
+#endif
        kirkwood_pcie_id(&dev, &rev);
        printk(KERN_DEBUG "Gating clock of unused units\n");
        printk(KERN_DEBUG "before: 0x%08x\n", curr);
@@ -489,6 +493,14 @@ static int __init kirkwood_clock_gate(void)
        /* Make sure those units are accessible */
        writel(curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0 | CGC_PEX1, CLOCK_GATING_CTRL);
+#ifdef CONFIG_OF
+        np = of_find_compatible_node(NULL, NULL, "mrvl,orion-nand");
+        if (np && of_device_is_available(np)) {
+                kirkwood_clk_ctrl |= CGC_RUNIT;
+                of_node_put(np);
+        }
+#endif
        /* For SATA: first shutdown the phy */
        if (!(kirkwood_clk_ctrl & CGC_SATA0)) {
                /* Disable PLL and IVREF */
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index fa8e7689c436..a34c41a5172e 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -58,6 +58,24 @@ void dreamplug_init(void);
 static inline void dreamplug_init(void) {};
 #endif
+#ifdef CONFIG_MACH_DLINK_KIRKWOOD_DT
+void dnskw_init(void);
+#else
+static inline void dnskw_init(void) {};
+#endif
+#ifdef CONFIG_MACH_ICONNECT_DT
+void iconnect_init(void);
+#else
+static inline void iconnect_init(void) {};
+#endif
+#ifdef CONFIG_MACH_IB62X0_DT
+void ib62x0_init(void);
+#else
+static inline void ib62x0_init(void) {};
+#endif
 /* early init functions not converted to fdt yet */
 char *kirkwood_id(void);
 void kirkwood_l2_init(void);
diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
index f56a0118c1bb..de373176ee67 100644
--- a/arch/arm/mach-kirkwood/pcie.c
+++ b/arch/arm/mach-kirkwood/pcie.c
@@ -44,12 +44,6 @@ struct pcie_port {
 static int pcie_port_map[2];
 static int num_pcie_ports;
-static inline struct pcie_port *bus_to_port(struct pci_bus *bus)
-{
-        struct pci_sys_data *sys = bus->sysdata;
-        return sys->private_data;
-}
 static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
 {
        /*
@@ -79,7 +73,8 @@ static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
 static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
                        int size, u32 *val)
 {
-        struct pcie_port *pp = bus_to_port(bus);
+        struct pci_sys_data *sys = bus->sysdata;
+        struct pcie_port *pp = sys->private_data;
        unsigned long flags;
        int ret;
@@ -98,7 +93,8 @@ static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
 static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
                        int where, int size, u32 val)
 {
-        struct pcie_port *pp = bus_to_port(bus);
+        struct pci_sys_data *sys = bus->sysdata;
+        struct pcie_port *pp = sys->private_data;
        unsigned long flags;
        int ret;
@@ -248,13 +244,13 @@ kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys)
 static int __init kirkwood_pcie_map_irq(const struct pci_dev *dev, u8 slot,
        u8 pin)
 {
-        struct pcie_port *pp = bus_to_port(dev->bus);
+        struct pci_sys_data *sys = dev->sysdata;
+        struct pcie_port *pp = sys->private_data;
        return pp->irq;
 }
 static struct hw_pci kirkwood_pci __initdata = {
-        .swizzle        = pci_std_swizzle,
        .setup          = kirkwood_pcie_setup,
        .scan           = kirkwood_pcie_scan_bus,
        .map_irq        = kirkwood_pcie_map_irq,
diff --git a/arch/arm/mach-ks8695/pci.c b/arch/arm/mach-ks8695/pci.c
index acc701435817..bb18193b4bac 100644
--- a/arch/arm/mach-ks8695/pci.c
+++ b/arch/arm/mach-ks8695/pci.c
@@ -141,12 +141,6 @@ static struct pci_ops ks8695_pci_ops = {
        .write  = ks8695_pci_writeconfig,
 };
-static struct pci_bus* __init ks8695_pci_scan_bus(int nr, struct pci_sys_data *sys)
-{
-        return pci_scan_root_bus(NULL, sys->busnr, &ks8695_pci_ops, sys,
-                                 &sys->resources);
-}
 static struct resource pci_mem = {
        .name   = "PCI Memory space",
        .start  = KS8695_PCIMEM_PA,
@@ -302,11 +296,10 @@ static void ks8695_show_pciregs(void)
 static struct hw_pci ks8695_pci __initdata = {
        .nr_controllers = 1,
+        .ops            = &ks8695_pci_ops,
        .preinit        = ks8695_pci_preinit,
        .setup          = ks8695_pci_setup,
-        .scan           = ks8695_pci_scan_bus,
        .postinit       = NULL,
-        .swizzle        = pci_std_swizzle,
        .map_irq        = NULL,
 };
diff --git a/arch/arm/mach-lpc32xx/Kconfig b/arch/arm/mach-lpc32xx/Kconfig
index 75946ac89ee9..e0b3eee83834 100644
--- a/arch/arm/mach-lpc32xx/Kconfig
+++ b/arch/arm/mach-lpc32xx/Kconfig
@@ -29,30 +29,4 @@ config ARCH_LPC32XX_UART6_SELECT
 endmenu
-menu "LPC32XX chip components"
-config ARCH_LPC32XX_IRAM_FOR_NET
-        bool "Use IRAM for network buffers"
-        default y
-        help
-          Say Y here to use the LPC internal fast IRAM (i.e. 256KB SRAM) as
-          network buffer.  If the total combined required buffer sizes is
-          larger than the size of IRAM, then SDRAM will be used instead.
-          This can be enabled safely if the IRAM is not intended for other
-          uses.
-config ARCH_LPC32XX_MII_SUPPORT
-        bool "Check to enable MII support or leave disabled for RMII support"
-        help
-          Say Y here to enable MII support, or N for RMII support. Regardless of
-          which support is selected, the ethernet interface driver needs to be
-          selected in the device driver networking section.
-          The PHY3250 reference board uses RMII, so users of this board should
-          say N.
-endmenu
 endif
diff --git a/arch/arm/mach-lpc32xx/clock.c b/arch/arm/mach-lpc32xx/clock.c
index 2fc24ca12054..f6a3ffec1f4b 100644
--- a/arch/arm/mach-lpc32xx/clock.c
+++ b/arch/arm/mach-lpc32xx/clock.c
@@ -1095,49 +1095,42 @@ struct clk *clk_get_parent(struct clk *clk)
 }
 EXPORT_SYMBOL(clk_get_parent);
-#define _REGISTER_CLOCK(d, n, c) \
-        { \
-                .dev_id = (d), \
-                .con_id = (n), \
-                .clk = &(c), \
-        },
 static struct clk_lookup lookups[] = {
-        _REGISTER_CLOCK(NULL, "osc_32KHz", osc_32KHz)
+        CLKDEV_INIT(NULL, "osc_32KHz", &osc_32KHz),
-        _REGISTER_CLOCK(NULL, "osc_pll397", osc_pll397)
+        CLKDEV_INIT(NULL, "osc_pll397", &osc_pll397),
-        _REGISTER_CLOCK(NULL, "osc_main", osc_main)
+        CLKDEV_INIT(NULL, "osc_main", &osc_main),
-        _REGISTER_CLOCK(NULL, "sys_ck", clk_sys)
+        CLKDEV_INIT(NULL, "sys_ck", &clk_sys),
-        _REGISTER_CLOCK(NULL, "arm_pll_ck", clk_armpll)
+        CLKDEV_INIT(NULL, "arm_pll_ck", &clk_armpll),
-        _REGISTER_CLOCK(NULL, "ck_pll5", clk_usbpll)
+        CLKDEV_INIT(NULL, "ck_pll5", &clk_usbpll),
-        _REGISTER_CLOCK(NULL, "hclk_ck", clk_hclk)
+        CLKDEV_INIT(NULL, "hclk_ck", &clk_hclk),
-        _REGISTER_CLOCK(NULL, "pclk_ck", clk_pclk)
+        CLKDEV_INIT(NULL, "pclk_ck", &clk_pclk),
-        _REGISTER_CLOCK(NULL, "timer0_ck", clk_timer0)
+        CLKDEV_INIT(NULL, "timer0_ck", &clk_timer0),
-        _REGISTER_CLOCK(NULL, "timer1_ck", clk_timer1)
+        CLKDEV_INIT(NULL, "timer1_ck", &clk_timer1),
-        _REGISTER_CLOCK(NULL, "timer2_ck", clk_timer2)
+        CLKDEV_INIT(NULL, "timer2_ck", &clk_timer2),
-        _REGISTER_CLOCK(NULL, "timer3_ck", clk_timer3)
+        CLKDEV_INIT(NULL, "timer3_ck", &clk_timer3),
-        _REGISTER_CLOCK(NULL, "vfp9_ck", clk_vfp9)
+        CLKDEV_INIT(NULL, "vfp9_ck", &clk_vfp9),
-        _REGISTER_CLOCK(NULL, "clk_dmac", clk_dma)
+        CLKDEV_INIT("pl08xdmac", NULL, &clk_dma),
-        _REGISTER_CLOCK("pnx4008-watchdog", NULL, clk_wdt)
+        CLKDEV_INIT("4003c000.watchdog", NULL, &clk_wdt),
-        _REGISTER_CLOCK(NULL, "uart3_ck", clk_uart3)
+        CLKDEV_INIT(NULL, "uart3_ck", &clk_uart3),
-        _REGISTER_CLOCK(NULL, "uart4_ck", clk_uart4)
+        CLKDEV_INIT(NULL, "uart4_ck", &clk_uart4),
-        _REGISTER_CLOCK(NULL, "uart5_ck", clk_uart5)
+        CLKDEV_INIT(NULL, "uart5_ck", &clk_uart5),
-        _REGISTER_CLOCK(NULL, "uart6_ck", clk_uart6)
+        CLKDEV_INIT(NULL, "uart6_ck", &clk_uart6),
-        _REGISTER_CLOCK("pnx-i2c.0", NULL, clk_i2c0)
+        CLKDEV_INIT("400a0000.i2c", NULL, &clk_i2c0),
-        _REGISTER_CLOCK("pnx-i2c.1", NULL, clk_i2c1)
+        CLKDEV_INIT("400a8000.i2c", NULL, &clk_i2c1),
-        _REGISTER_CLOCK("pnx-i2c.2", NULL, clk_i2c2)
+        CLKDEV_INIT("31020300.i2c", NULL, &clk_i2c2),
-        _REGISTER_CLOCK("dev:ssp0", NULL, clk_ssp0)
+        CLKDEV_INIT("dev:ssp0", NULL, &clk_ssp0),
-        _REGISTER_CLOCK("dev:ssp1", NULL, clk_ssp1)
+        CLKDEV_INIT("dev:ssp1", NULL, &clk_ssp1),
-        _REGISTER_CLOCK("lpc32xx_keys.0", NULL, clk_kscan)
+        CLKDEV_INIT("lpc32xx_keys.0", NULL, &clk_kscan),
-        _REGISTER_CLOCK("lpc32xx-nand.0", "nand_ck", clk_nand)
+        CLKDEV_INIT("lpc32xx-nand.0", "nand_ck", &clk_nand),
-        _REGISTER_CLOCK("lpc32xx-adc", NULL, clk_adc)
+        CLKDEV_INIT("40048000.adc", NULL, &clk_adc),
-        _REGISTER_CLOCK(NULL, "i2s0_ck", clk_i2s0)
+        CLKDEV_INIT(NULL, "i2s0_ck", &clk_i2s0),
-        _REGISTER_CLOCK(NULL, "i2s1_ck", clk_i2s1)
+        CLKDEV_INIT(NULL, "i2s1_ck", &clk_i2s1),
-        _REGISTER_CLOCK("ts-lpc32xx", NULL, clk_tsc)
+        CLKDEV_INIT("40048000.tsc", NULL, &clk_tsc),
-        _REGISTER_CLOCK("dev:mmc0", NULL, clk_mmc)
+        CLKDEV_INIT("20098000.sd", NULL, &clk_mmc),
-        _REGISTER_CLOCK("lpc-eth.0", NULL, clk_net)
+        CLKDEV_INIT("31060000.ethernet", NULL, &clk_net),
-        _REGISTER_CLOCK("dev:clcd", NULL, clk_lcd)
+        CLKDEV_INIT("dev:clcd", NULL, &clk_lcd),
-        _REGISTER_CLOCK("lpc32xx_udc", "ck_usbd", clk_usbd)
+        CLKDEV_INIT("31020000.usbd", "ck_usbd", &clk_usbd),
-        _REGISTER_CLOCK("lpc32xx_rtc", NULL, clk_rtc)
+        CLKDEV_INIT("lpc32xx_rtc", NULL, &clk_rtc),
 };
 static int __init clk_init(void)
diff --git a/arch/arm/mach-lpc32xx/common.c b/arch/arm/mach-lpc32xx/common.c
index bbbf063a74c2..5c96057b6d78 100644
--- a/arch/arm/mach-lpc32xx/common.c
+++ b/arch/arm/mach-lpc32xx/common.c
@@ -27,186 +27,11 @@
 #include <asm/mach/map.h>
-#include <mach/i2c.h>
 #include <mach/hardware.h>
 #include <mach/platform.h>
 #include "common.h"
 /*
- * Watchdog timer
- */
-static struct resource watchdog_resources[] = {
-        [0] = {
-                .start = LPC32XX_WDTIM_BASE,
-                .end = LPC32XX_WDTIM_BASE + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        },
-};
-struct platform_device lpc32xx_watchdog_device = {
-        .name = "pnx4008-watchdog",
-        .id = -1,
-        .num_resources = ARRAY_SIZE(watchdog_resources),
-        .resource = watchdog_resources,
-};
-/*
- * I2C busses
- */
-static struct i2c_pnx_data i2c0_data = {
-        .name = I2C_CHIP_NAME "1",
-        .base = LPC32XX_I2C1_BASE,
-        .irq = IRQ_LPC32XX_I2C_1,
-};
-static struct i2c_pnx_data i2c1_data = {
-        .name = I2C_CHIP_NAME "2",
-        .base = LPC32XX_I2C2_BASE,
-        .irq = IRQ_LPC32XX_I2C_2,
-};
-static struct i2c_pnx_data i2c2_data = {
-        .name = "USB-I2C",
-        .base = LPC32XX_OTG_I2C_BASE,
-        .irq = IRQ_LPC32XX_USB_I2C,
-};
-struct platform_device lpc32xx_i2c0_device = {
-        .name = "pnx-i2c",
-        .id = 0,
-        .dev = {
-                .platform_data = &i2c0_data,
-        },
-};
-struct platform_device lpc32xx_i2c1_device = {
-        .name = "pnx-i2c",
-        .id = 1,
-        .dev = {
-                .platform_data = &i2c1_data,
-        },
-};
-struct platform_device lpc32xx_i2c2_device = {
-        .name = "pnx-i2c",
-        .id = 2,
-        .dev = {
-                .platform_data = &i2c2_data,
-        },
-};
-/* TSC (Touch Screen Controller) */
-static struct resource lpc32xx_tsc_resources[] = {
-        {
-                .start = LPC32XX_ADC_BASE,
-                .end = LPC32XX_ADC_BASE + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = IRQ_LPC32XX_TS_IRQ,
-                .end = IRQ_LPC32XX_TS_IRQ,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-struct platform_device lpc32xx_tsc_device = {
-        .name =  "ts-lpc32xx",
-        .id = -1,
-        .num_resources = ARRAY_SIZE(lpc32xx_tsc_resources),
-        .resource = lpc32xx_tsc_resources,
-};
-/* RTC */
-static struct resource lpc32xx_rtc_resources[] = {
-        {
-                .start = LPC32XX_RTC_BASE,
-                .end = LPC32XX_RTC_BASE + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        },{
-                .start = IRQ_LPC32XX_RTC,
-                .end = IRQ_LPC32XX_RTC,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-struct platform_device lpc32xx_rtc_device = {
-        .name =  "rtc-lpc32xx",
-        .id = -1,
-        .num_resources = ARRAY_SIZE(lpc32xx_rtc_resources),
-        .resource = lpc32xx_rtc_resources,
-};
-/*
- * ADC support
- */
-static struct resource adc_resources[] = {
-        {
-                .start = LPC32XX_ADC_BASE,
-                .end = LPC32XX_ADC_BASE + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = IRQ_LPC32XX_TS_IRQ,
-                .end = IRQ_LPC32XX_TS_IRQ,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-struct platform_device lpc32xx_adc_device = {
-        .name =  "lpc32xx-adc",
-        .id = -1,
-        .num_resources = ARRAY_SIZE(adc_resources),
-        .resource = adc_resources,
-};
-/*
- * USB support
- */
-/* The dmamask must be set for OHCI to work */
-static u64 ohci_dmamask = ~(u32) 0;
-static struct resource ohci_resources[] = {
-        {
-                .start = IO_ADDRESS(LPC32XX_USB_BASE),
-                .end = IO_ADDRESS(LPC32XX_USB_BASE + 0x100 - 1),
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = IRQ_LPC32XX_USB_HOST,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-struct platform_device lpc32xx_ohci_device = {
-        .name = "usb-ohci",
-        .id = -1,
-        .dev = {
-                .dma_mask = &ohci_dmamask,
-                .coherent_dma_mask = 0xFFFFFFFF,
-        },
-        .num_resources = ARRAY_SIZE(ohci_resources),
-        .resource = ohci_resources,
-};
-/*
- * Network Support
- */
-static struct resource net_resources[] = {
-        [0] = DEFINE_RES_MEM(LPC32XX_ETHERNET_BASE, SZ_4K),
-        [1] = DEFINE_RES_MEM(LPC32XX_IRAM_BASE, SZ_128K),
-        [2] = DEFINE_RES_IRQ(IRQ_LPC32XX_ETHERNET),
-};
-static u64 lpc32xx_mac_dma_mask = 0xffffffffUL;
-struct platform_device lpc32xx_net_device = {
-        .name = "lpc-eth",
-        .id = 0,
-        .dev = {
-                .dma_mask = &lpc32xx_mac_dma_mask,
-                .coherent_dma_mask = 0xffffffffUL,
-        },
-        .num_resources = ARRAY_SIZE(net_resources),
-        .resource = net_resources,
-};
-/*
 * Returns the unique ID for the device
 */
 void lpc32xx_get_uid(u32 devid[4])
@@ -398,3 +223,16 @@ void lpc23xx_restart(char mode, const char *cmd)
        while (1)
                ;
 }
+static int __init lpc32xx_display_uid(void)
+{
+        u32 uid[4];
+        lpc32xx_get_uid(uid);
+        printk(KERN_INFO "LPC32XX unique ID: %08x%08x%08x%08x\n",
+                uid[3], uid[2], uid[1], uid[0]);
+        return 1;
+}
+arch_initcall(lpc32xx_display_uid);
diff --git a/arch/arm/mach-lpc32xx/common.h b/arch/arm/mach-lpc32xx/common.h
index 68e45e8c9486..afeac3b1fae6 100644
--- a/arch/arm/mach-lpc32xx/common.h
+++ b/arch/arm/mach-lpc32xx/common.h
@@ -23,26 +23,12 @@
 #include <linux/platform_device.h>
 /*
- * Arch specific platform device structures
- */
-extern struct platform_device lpc32xx_watchdog_device;
-extern struct platform_device lpc32xx_i2c0_device;
-extern struct platform_device lpc32xx_i2c1_device;
-extern struct platform_device lpc32xx_i2c2_device;
-extern struct platform_device lpc32xx_tsc_device;
-extern struct platform_device lpc32xx_adc_device;
-extern struct platform_device lpc32xx_rtc_device;
-extern struct platform_device lpc32xx_ohci_device;
-extern struct platform_device lpc32xx_net_device;
-/*
 * Other arch specific structures and functions
 */
 extern struct sys_timer lpc32xx_timer;
 extern void __init lpc32xx_init_irq(void);
 extern void __init lpc32xx_map_io(void);
 extern void __init lpc32xx_serial_init(void);
-extern void __init lpc32xx_gpio_init(void);
 extern void lpc23xx_restart(char, const char *);
diff --git a/arch/arm/mach-lpc32xx/include/mach/i2c.h b/arch/arm/mach-lpc32xx/include/mach/i2c.h
deleted file mode 100644
index 034dc9286bcc..000000000000
--- a/arch/arm/mach-lpc32xx/include/mach/i2c.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * PNX4008-specific tweaks for I2C IP3204 block
- *
- * Author: Vitaly Wool <vwool@ru.mvista.com>
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef __ASM_ARCH_I2C_H
-#define __ASM_ARCH_I2C_H
-enum {
-        mstatus_tdi = 0x00000001,
-        mstatus_afi = 0x00000002,
-        mstatus_nai = 0x00000004,
-        mstatus_drmi = 0x00000008,
-        mstatus_active = 0x00000020,
-        mstatus_scl = 0x00000040,
-        mstatus_sda = 0x00000080,
-        mstatus_rff = 0x00000100,
-        mstatus_rfe = 0x00000200,
-        mstatus_tff = 0x00000400,
-        mstatus_tfe = 0x00000800,
-};
-enum {
-        mcntrl_tdie = 0x00000001,
-        mcntrl_afie = 0x00000002,
-        mcntrl_naie = 0x00000004,
-        mcntrl_drmie = 0x00000008,
-        mcntrl_daie = 0x00000020,
-        mcntrl_rffie = 0x00000040,
-        mcntrl_tffie = 0x00000080,
-        mcntrl_reset = 0x00000100,
-        mcntrl_cdbmode = 0x00000400,
-};
-enum {
-        rw_bit = 1 << 0,
-        start_bit = 1 << 8,
-        stop_bit = 1 << 9,
-};
-#define I2C_REG_RX(a)   ((a)->ioaddr)           /* Rx FIFO reg (RO) */
-#define I2C_REG_TX(a)   ((a)->ioaddr)           /* Tx FIFO reg (WO) */
-#define I2C_REG_STS(a)  ((a)->ioaddr + 0x04)    /* Status reg (RO) */
-#define I2C_REG_CTL(a)  ((a)->ioaddr + 0x08)    /* Ctl reg */
-#define I2C_REG_CKL(a)  ((a)->ioaddr + 0x0c)    /* Clock divider low */
-#define I2C_REG_CKH(a)  ((a)->ioaddr + 0x10)    /* Clock divider high */
-#define I2C_REG_ADR(a)  ((a)->ioaddr + 0x14)    /* I2C address */
-#define I2C_REG_RFL(a)  ((a)->ioaddr + 0x18)    /* Rx FIFO level (RO) */
-#define I2C_REG_TFL(a)  ((a)->ioaddr + 0x1c)    /* Tx FIFO level (RO) */
-#define I2C_REG_RXB(a)  ((a)->ioaddr + 0x20)    /* Num of bytes Rx-ed (RO) */
-#define I2C_REG_TXB(a)  ((a)->ioaddr + 0x24)    /* Num of bytes Tx-ed (RO) */
-#define I2C_REG_TXS(a)  ((a)->ioaddr + 0x28)    /* Tx slave FIFO (RO) */
-#define I2C_REG_STFL(a) ((a)->ioaddr + 0x2c)    /* Tx slave FIFO level (RO) */
-#define I2C_CHIP_NAME           "PNX4008-I2C"
-#endif                          /* __ASM_ARCH_I2C_H */
diff --git a/arch/arm/mach-lpc32xx/irq.c b/arch/arm/mach-lpc32xx/irq.c
index d080cb1123dd..5b1cc35e6fba 100644
--- a/arch/arm/mach-lpc32xx/irq.c
+++ b/arch/arm/mach-lpc32xx/irq.c
@@ -22,6 +22,11 @@
 #include <linux/irq.h>
 #include <linux/err.h>
 #include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/irqdomain.h>
+#include <linux/module.h>
 #include <mach/irqs.h>
 #include <mach/hardware.h>
@@ -44,6 +49,9 @@
 #define SIC1_ATR_DEFAULT        0x00026000
 #define SIC2_ATR_DEFAULT        0x00000000
+static struct irq_domain *lpc32xx_mic_domain;
+static struct device_node *lpc32xx_mic_np;
 struct lpc32xx_event_group_regs {
        void __iomem *enab_reg;
        void __iomem *edge_reg;
@@ -203,7 +211,7 @@ static void lpc32xx_mask_irq(struct irq_data *d)
 {
        unsigned int reg, ctrl, mask;
-        get_controller(d->irq, &ctrl, &mask);
+        get_controller(d->hwirq, &ctrl, &mask);
        reg = __raw_readl(LPC32XX_INTC_MASK(ctrl)) & ~mask;
        __raw_writel(reg, LPC32XX_INTC_MASK(ctrl));
@@ -213,7 +221,7 @@ static void lpc32xx_unmask_irq(struct irq_data *d)
 {
        unsigned int reg, ctrl, mask;
-        get_controller(d->irq, &ctrl, &mask);
+        get_controller(d->hwirq, &ctrl, &mask);
        reg = __raw_readl(LPC32XX_INTC_MASK(ctrl)) | mask;
        __raw_writel(reg, LPC32XX_INTC_MASK(ctrl));
@@ -223,14 +231,14 @@ static void lpc32xx_ack_irq(struct irq_data *d)
 {
        unsigned int ctrl, mask;
-        get_controller(d->irq, &ctrl, &mask);
+        get_controller(d->hwirq, &ctrl, &mask);
        __raw_writel(mask, LPC32XX_INTC_RAW_STAT(ctrl));
        /* Also need to clear pending wake event */
-        if (lpc32xx_events[d->irq].mask != 0)
+        if (lpc32xx_events[d->hwirq].mask != 0)
-                __raw_writel(lpc32xx_events[d->irq].mask,
+                __raw_writel(lpc32xx_events[d->hwirq].mask,
-                        lpc32xx_events[d->irq].event_group->rawstat_reg);
+                        lpc32xx_events[d->hwirq].event_group->rawstat_reg);
 }
 static void __lpc32xx_set_irq_type(unsigned int irq, int use_high_level,
@@ -274,22 +282,22 @@ static int lpc32xx_set_irq_type(struct irq_data *d, unsigned int type)
        switch (type) {
        case IRQ_TYPE_EDGE_RISING:
                /* Rising edge sensitive */
-                __lpc32xx_set_irq_type(d->irq, 1, 1);
+                __lpc32xx_set_irq_type(d->hwirq, 1, 1);
                break;
        case IRQ_TYPE_EDGE_FALLING:
                /* Falling edge sensitive */
-                __lpc32xx_set_irq_type(d->irq, 0, 1);
+                __lpc32xx_set_irq_type(d->hwirq, 0, 1);
                break;
        case IRQ_TYPE_LEVEL_LOW:
                /* Low level sensitive */
-                __lpc32xx_set_irq_type(d->irq, 0, 0);
+                __lpc32xx_set_irq_type(d->hwirq, 0, 0);
                break;
        case IRQ_TYPE_LEVEL_HIGH:
                /* High level sensitive */
-                __lpc32xx_set_irq_type(d->irq, 1, 0);
+                __lpc32xx_set_irq_type(d->hwirq, 1, 0);
                break;
        /* Other modes are not supported */
@@ -298,7 +306,7 @@ static int lpc32xx_set_irq_type(struct irq_data *d, unsigned int type)
        }
        /* Ok to use the level handler for all types */
-        irq_set_handler(d->irq, handle_level_irq);
+        irq_set_handler(d->hwirq, handle_level_irq);
        return 0;
 }
@@ -307,33 +315,33 @@ static int lpc32xx_irq_wake(struct irq_data *d, unsigned int state)
 {
        unsigned long eventreg;
-        if (lpc32xx_events[d->irq].mask != 0) {
+        if (lpc32xx_events[d->hwirq].mask != 0) {
-                eventreg = __raw_readl(lpc32xx_events[d->irq].
+                eventreg = __raw_readl(lpc32xx_events[d->hwirq].
                        event_group->enab_reg);
                if (state)
-                        eventreg |= lpc32xx_events[d->irq].mask;
+                        eventreg |= lpc32xx_events[d->hwirq].mask;
                else {
-                        eventreg &= ~lpc32xx_events[d->irq].mask;
+                        eventreg &= ~lpc32xx_events[d->hwirq].mask;
                        /*
                         * When disabling the wakeup, clear the latched
                         * event
                         */
-                        __raw_writel(lpc32xx_events[d->irq].mask,
+                        __raw_writel(lpc32xx_events[d->hwirq].mask,
-                                lpc32xx_events[d->irq].
+                                lpc32xx_events[d->hwirq].
                                event_group->rawstat_reg);
                }
                __raw_writel(eventreg,
-                        lpc32xx_events[d->irq].event_group->enab_reg);
+                        lpc32xx_events[d->hwirq].event_group->enab_reg);
                return 0;
        }
        /* Clear event */
-        __raw_writel(lpc32xx_events[d->irq].mask,
+        __raw_writel(lpc32xx_events[d->hwirq].mask,
-                lpc32xx_events[d->irq].event_group->rawstat_reg);
+                lpc32xx_events[d->hwirq].event_group->rawstat_reg);
        return -ENODEV;
 }
@@ -353,6 +361,7 @@ static void __init lpc32xx_set_default_mappings(unsigned int apr,
 }
 static struct irq_chip lpc32xx_irq_chip = {
+        .name = "MIC",
        .irq_ack = lpc32xx_ack_irq,
        .irq_mask = lpc32xx_mask_irq,
        .irq_unmask = lpc32xx_unmask_irq,
@@ -386,9 +395,23 @@ static void lpc32xx_sic2_handler(unsigned int irq, struct irq_desc *desc)
        }
 }
+static int __init __lpc32xx_mic_of_init(struct device_node *node,
+                                        struct device_node *parent)
+{
+        lpc32xx_mic_np = node;
+        return 0;
+}
+static const struct of_device_id mic_of_match[] __initconst = {
+        { .compatible = "nxp,lpc3220-mic", .data = __lpc32xx_mic_of_init },
+        { }
+};
 void __init lpc32xx_init_irq(void)
 {
        unsigned int i;
+        int irq_base;
        /* Setup MIC */
        __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_MIC_BASE));
@@ -448,4 +471,19 @@ void __init lpc32xx_init_irq(void)
                LPC32XX_CLKPWR_PIN_RS);
        __raw_writel(__raw_readl(LPC32XX_CLKPWR_INT_RS),
                LPC32XX_CLKPWR_INT_RS);
+        of_irq_init(mic_of_match);
+        irq_base = irq_alloc_descs(-1, 0, NR_IRQS, 0);
+        if (irq_base < 0) {
+                pr_warn("Cannot allocate irq_descs, assuming pre-allocated\n");
+                irq_base = 0;
+        }
+        lpc32xx_mic_domain = irq_domain_add_legacy(lpc32xx_mic_np, NR_IRQS,
+                                                   irq_base, 0,
+                                                   &irq_domain_simple_ops,
+                                                   NULL);
+        if (!lpc32xx_mic_domain)
+                panic("Unable to add MIC irq domain\n");
 }
diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c
index 7f7401ec7487..540106cdb9ec 100644
--- a/arch/arm/mach-lpc32xx/phy3250.c
+++ b/arch/arm/mach-lpc32xx/phy3250.c
@@ -1,8 +1,9 @@
 /*
- * arch/arm/mach-lpc32xx/phy3250.c
+ * Platform support for LPC32xx SoC
 *
 * Author: Kevin Wells <kevin.wells@nxp.com>
 *
+ * Copyright (C) 2012 Roland Stigge <stigge@antcom.de>
 * Copyright (C) 2010 NXP Semiconductors
 *
 * This program is free software; you can redistribute it and/or modify
@@ -25,11 +26,16 @@
 #include <linux/device.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/eeprom.h>
-#include <linux/leds.h>
 #include <linux/gpio.h>
 #include <linux/amba/bus.h>
 #include <linux/amba/clcd.h>
 #include <linux/amba/pl022.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/clk.h>
+#include <linux/amba/pl08x.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -47,7 +53,6 @@
 #define SPI0_CS_GPIO    LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5)
 #define LCD_POWER_GPIO  LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 0)
 #define BKL_POWER_GPIO  LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 4)
-#define LED_GPIO        LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 1)
 /*
 * AMBA LCD controller
@@ -150,9 +155,6 @@ static struct clcd_board lpc32xx_clcd_data = {
        .remove         = lpc32xx_clcd_remove,
 };
-static AMBA_AHB_DEVICE(lpc32xx_clcd, "dev:clcd", 0,
-        LPC32XX_LCD_BASE, { IRQ_LPC32XX_LCD }, &lpc32xx_clcd_data);
 /*
 * AMBA SSP (SPI)
 */
@@ -180,8 +182,11 @@ static struct pl022_ssp_controller lpc32xx_ssp0_data = {
        .enable_dma             = 0,
 };
-static AMBA_APB_DEVICE(lpc32xx_ssp0, "dev:ssp0", 0,
+static struct pl022_ssp_controller lpc32xx_ssp1_data = {
-        LPC32XX_SSP0_BASE, { IRQ_LPC32XX_SSP0 }, &lpc32xx_ssp0_data);
+        .bus_id                 = 1,
+        .num_chipselect         = 1,
+        .enable_dma             = 0,
+};
 /* AT25 driver registration */
 static int __init phy3250_spi_board_register(void)
@@ -221,73 +226,20 @@ static int __init phy3250_spi_board_register(void)
 }
 arch_initcall(phy3250_spi_board_register);
-static struct i2c_board_info __initdata phy3250_i2c_board_info[] = {
+static struct pl08x_platform_data pl08x_pd = {
-        {
-                I2C_BOARD_INFO("pcf8563", 0x51),
-        },
-};
-static struct gpio_led phy_leds[] = {
-        {
-                .name                   = "led0",
-                .gpio                   = LED_GPIO,
-                .active_low             = 1,
-                .default_trigger        = "heartbeat",
-        },
-};
-static struct gpio_led_platform_data led_data = {
-        .leds = phy_leds,
-        .num_leds = ARRAY_SIZE(phy_leds),
-};
-static struct platform_device lpc32xx_gpio_led_device = {
-        .name                   = "leds-gpio",
-        .id                     = -1,
-        .dev.platform_data      = &led_data,
 };
-static struct platform_device *phy3250_devs[] __initdata = {
+static const struct of_dev_auxdata lpc32xx_auxdata_lookup[] __initconst = {
-        &lpc32xx_rtc_device,
+        OF_DEV_AUXDATA("arm,pl022", 0x20084000, "dev:ssp0", &lpc32xx_ssp0_data),
-        &lpc32xx_tsc_device,
+        OF_DEV_AUXDATA("arm,pl022", 0x2008C000, "dev:ssp1", &lpc32xx_ssp1_data),
-        &lpc32xx_i2c0_device,
+        OF_DEV_AUXDATA("arm,pl110", 0x31040000, "dev:clcd", &lpc32xx_clcd_data),
-        &lpc32xx_i2c1_device,
+        OF_DEV_AUXDATA("arm,pl080", 0x31000000, "pl08xdmac", &pl08x_pd),
-        &lpc32xx_i2c2_device,
+        { }
-        &lpc32xx_watchdog_device,
-        &lpc32xx_gpio_led_device,
-        &lpc32xx_adc_device,
-        &lpc32xx_ohci_device,
-        &lpc32xx_net_device,
 };
-static struct amba_device *amba_devs[] __initdata = {
+static void __init lpc3250_machine_init(void)
-        &lpc32xx_clcd_device,
-        &lpc32xx_ssp0_device,
-};
-/*
- * Board specific functions
- */
-static void __init phy3250_board_init(void)
 {
        u32 tmp;
-        int i;
-        lpc32xx_gpio_init();
-        /* Register GPIOs used on this board */
-        if (gpio_request(SPI0_CS_GPIO, "spi0 cs"))
-                printk(KERN_ERR "Error requesting gpio %u",
-                        SPI0_CS_GPIO);
-        else if (gpio_direction_output(SPI0_CS_GPIO, 1))
-                printk(KERN_ERR "Error setting gpio %u to output",
-                        SPI0_CS_GPIO);
-        /* Setup network interface for RMII mode */
-        tmp = __raw_readl(LPC32XX_CLKPWR_MACCLK_CTRL);
-        tmp &= ~LPC32XX_CLKPWR_MACCTRL_PINS_MSK;
-        tmp |= LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS;
-        __raw_writel(tmp, LPC32XX_CLKPWR_MACCLK_CTRL);
        /* Setup SLC NAND controller muxing */
        __raw_writel(LPC32XX_CLKPWR_NANDCLK_SEL_SLC,
@@ -300,6 +252,12 @@ static void __init phy3250_board_init(void)
        tmp |= LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT16;
        __raw_writel(tmp, LPC32XX_CLKPWR_LCDCLK_CTRL);
+        /* Set up USB power */
+        tmp = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
+        tmp |= LPC32XX_CLKPWR_USBCTRL_HCLK_EN |
+                LPC32XX_CLKPWR_USBCTRL_USBI2C_EN;
+        __raw_writel(tmp, LPC32XX_CLKPWR_USB_CTRL);
        /* Set up I2C pull levels */
        tmp = __raw_readl(LPC32XX_CLKPWR_I2C_CLK_CTRL);
        tmp |= LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE |
@@ -321,54 +279,51 @@ static void __init phy3250_board_init(void)
        /*
         * AMBA peripheral clocks need to be enabled prior to AMBA device
         * detection or a data fault will occur, so enable the clocks
-         * here. However, we don't want to enable them if the peripheral
+         * here.
-         * isn't included in the image
         */
-#ifdef CONFIG_FB_ARMCLCD
        tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL);
        __raw_writel((tmp | LPC32XX_CLKPWR_LCDCTRL_CLK_EN),
                LPC32XX_CLKPWR_LCDCLK_CTRL);
-#endif
-#ifdef CONFIG_SPI_PL022
        tmp = __raw_readl(LPC32XX_CLKPWR_SSP_CLK_CTRL);
        __raw_writel((tmp | LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN),
                LPC32XX_CLKPWR_SSP_CLK_CTRL);
-#endif
-        platform_add_devices(phy3250_devs, ARRAY_SIZE(phy3250_devs));
+        tmp = __raw_readl(LPC32XX_CLKPWR_DMA_CLK_CTRL);
-        for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
+        __raw_writel((tmp | LPC32XX_CLKPWR_DMACLKCTRL_CLK_EN),
-                struct amba_device *d = amba_devs[i];
+                     LPC32XX_CLKPWR_DMA_CLK_CTRL);
-                amba_device_register(d, &iomem_resource);
-        }
        /* Test clock needed for UDA1380 initial init */
        __raw_writel(LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC |
                LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN,
                LPC32XX_CLKPWR_TEST_CLK_SEL);
-        i2c_register_board_info(0, phy3250_i2c_board_info,
+        of_platform_populate(NULL, of_default_bus_match_table,
-                ARRAY_SIZE(phy3250_i2c_board_info));
+                             lpc32xx_auxdata_lookup, NULL);
-}
-static int __init lpc32xx_display_uid(void)
-{
-        u32 uid[4];
-        lpc32xx_get_uid(uid);
-        printk(KERN_INFO "LPC32XX unique ID: %08x%08x%08x%08x\n",
-                uid[3], uid[2], uid[1], uid[0]);
-        return 1;
+        /* Register GPIOs used on this board */
+        if (gpio_request(SPI0_CS_GPIO, "spi0 cs"))
+                printk(KERN_ERR "Error requesting gpio %u",
+                        SPI0_CS_GPIO);
+        else if (gpio_direction_output(SPI0_CS_GPIO, 1))
+                printk(KERN_ERR "Error setting gpio %u to output",
+                        SPI0_CS_GPIO);
 }
-arch_initcall(lpc32xx_display_uid);
-MACHINE_START(PHY3250, "Phytec 3250 board with the LPC3250 Microcontroller")
+static char const *lpc32xx_dt_compat[] __initdata = {
-        /* Maintainer: Kevin Wells, NXP Semiconductors */
+        "nxp,lpc3220",
+        "nxp,lpc3230",
+        "nxp,lpc3240",
+        "nxp,lpc3250",
+        NULL
+};
+DT_MACHINE_START(LPC32XX_DT, "LPC32XX SoC (Flattened Device Tree)")
        .atag_offset    = 0x100,
        .map_io         = lpc32xx_map_io,
        .init_irq       = lpc32xx_init_irq,
        .timer          = &lpc32xx_timer,
-        .init_machine   = phy3250_board_init,
+        .init_machine   = lpc3250_machine_init,
+        .dt_compat      = lpc32xx_dt_compat,
        .restart        = lpc23xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig
index 5a90b9a3ab6e..7fddd01b85b9 100644
--- a/arch/arm/mach-mmp/Kconfig
+++ b/arch/arm/mach-mmp/Kconfig
@@ -2,16 +2,6 @@ if ARCH_MMP
 menu "Marvell PXA168/910/MMP2 Implmentations"
-config MACH_MMP_DT
-        bool "Support MMP2 platforms from device tree"
-        select CPU_PXA168
-        select CPU_PXA910
-        select USE_OF
-        help
-          Include support for Marvell MMP2 based platforms using
-          the device tree. Needn't select any other machine while
-          MACH_MMP_DT is enabled.
 config MACH_ASPENITE
        bool "Marvell's PXA168 Aspenite Development Board"
        select CPU_PXA168
@@ -94,6 +84,25 @@ config MACH_GPLUGD
          Say 'Y' here if you want to support the Marvell PXA168-based
          GuruPlug Display (gplugD) Board
+config MACH_MMP_DT
+        bool "Support MMP (ARMv5) platforms from device tree"
+        select CPU_PXA168
+        select CPU_PXA910
+        select USE_OF
+        help
+          Include support for Marvell MMP2 based platforms using
+          the device tree. Needn't select any other machine while
+          MACH_MMP_DT is enabled.
+config MACH_MMP2_DT
+        bool "Support MMP2 (ARMv7) platforms from device tree"
+        depends on !CPU_MOHAWK
+        select CPU_MMP2
+        select USE_OF
+        help
+          Include support for Marvell MMP2 based platforms using
+          the device tree.
 endmenu
 config CPU_PXA168
@@ -113,4 +122,11 @@ config CPU_MMP2
        select CPU_PJ4
        help
          Select code specific to MMP2. MMP2 is ARMv7 compatible.
+config USB_EHCI_MV_U2O
+        bool "EHCI support for PXA USB OTG controller"
+        depends on USB_EHCI_MV
+        help
+          Enables support for OTG controller which can be switched to host mode.
 endif
diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile
index 4fc0ff5dc96d..b786f7e6cd1f 100644
--- a/arch/arm/mach-mmp/Makefile
+++ b/arch/arm/mach-mmp/Makefile
@@ -2,12 +2,17 @@
 # Makefile for Marvell's PXA168 processors line
 #
-obj-y                           += common.o clock.o devices.o time.o
+obj-y                           += common.o clock.o devices.o time.o irq.o
 # SoC support
-obj-$(CONFIG_CPU_PXA168)        += pxa168.o irq-pxa168.o
+obj-$(CONFIG_CPU_PXA168)        += pxa168.o
-obj-$(CONFIG_CPU_PXA910)        += pxa910.o irq-pxa168.o
+obj-$(CONFIG_CPU_PXA910)        += pxa910.o
-obj-$(CONFIG_CPU_MMP2)          += mmp2.o irq-mmp2.o sram.o
+obj-$(CONFIG_CPU_MMP2)          += mmp2.o sram.o
+ifeq ($(CONFIG_PM),y)
+obj-$(CONFIG_CPU_PXA910)        += pm-pxa910.o
+obj-$(CONFIG_CPU_MMP2)          += pm-mmp2.o
+endif
 # board support
 obj-$(CONFIG_MACH_ASPENITE)     += aspenite.o
@@ -19,5 +24,6 @@ obj-$(CONFIG_MACH_BROWNSTONE)	+= brownstone.o
 obj-$(CONFIG_MACH_FLINT)        += flint.o
 obj-$(CONFIG_MACH_MARVELL_JASPER) += jasper.o
 obj-$(CONFIG_MACH_MMP_DT)       += mmp-dt.o
+obj-$(CONFIG_MACH_MMP2_DT)      += mmp2-dt.o
 obj-$(CONFIG_MACH_TETON_BGA)    += teton_bga.o
 obj-$(CONFIG_MACH_GPLUGD)       += gplugd.o
diff --git a/arch/arm/mach-mmp/aspenite.c b/arch/arm/mach-mmp/aspenite.c
index bf5d8e195c3e..223090b1444d 100644
--- a/arch/arm/mach-mmp/aspenite.c
+++ b/arch/arm/mach-mmp/aspenite.c
@@ -17,6 +17,7 @@
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/nand.h>
 #include <linux/interrupt.h>
+#include <linux/platform_data/mv_usb.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -221,6 +222,21 @@ static struct pxa27x_keypad_platform_data aspenite_keypad_info __initdata = {
        .debounce_interval      = 30,
 };
+#if defined(CONFIG_USB_EHCI_MV)
+static char *pxa168_sph_clock_name[] = {
+        [0] = "PXA168-USBCLK",
+};
+static struct mv_usb_platform_data pxa168_sph_pdata = {
+        .clknum         = 1,
+        .clkname        = pxa168_sph_clock_name,
+        .mode           = MV_USB_MODE_HOST,
+        .phy_init       = pxa_usb_phy_init,
+        .phy_deinit     = pxa_usb_phy_deinit,
+        .set_vbus       = NULL,
+};
+#endif
 static void __init common_init(void)
 {
        mfp_config(ARRAY_AND_SIZE(common_pin_config));
@@ -236,6 +252,10 @@ static void __init common_init(void)
        /* off-chip devices */
        platform_device_register(&smc91x_device);
+#if defined(CONFIG_USB_EHCI_MV)
+        pxa168_add_usb_host(&pxa168_sph_pdata);
+#endif
 }
 MACHINE_START(ASPENITE, "PXA168-based Aspenite Development Platform")
diff --git a/arch/arm/mach-mmp/devices.c b/arch/arm/mach-mmp/devices.c
index 191d9dea8731..dd2d8b103cc8 100644
--- a/arch/arm/mach-mmp/devices.c
+++ b/arch/arm/mach-mmp/devices.c
@@ -9,9 +9,13 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
+#include <linux/delay.h>
 #include <asm/irq.h>
+#include <mach/irqs.h>
 #include <mach/devices.h>
+#include <mach/cputype.h>
+#include <mach/regs-usb.h>
 int __init pxa_register_device(struct pxa_device_desc *desc,
                                void *data, size_t size)
@@ -67,3 +71,281 @@ int __init pxa_register_device(struct pxa_device_desc *desc,
        return platform_device_add(pdev);
 }
+#if defined(CONFIG_USB) || defined(CONFIG_USB_GADGET)
+/*****************************************************************************
+ * The registers read/write routines
+ *****************************************************************************/
+static unsigned int u2o_get(void __iomem *base, unsigned int offset)
+{
+        return readl_relaxed(base + offset);
+}
+static void u2o_set(void __iomem *base, unsigned int offset,
+                unsigned int value)
+{
+        u32 reg;
+        reg = readl_relaxed(base + offset);
+        reg |= value;
+        writel_relaxed(reg, base + offset);
+        readl_relaxed(base + offset);
+}
+static void u2o_clear(void __iomem *base, unsigned int offset,
+                unsigned int value)
+{
+        u32 reg;
+        reg = readl_relaxed(base + offset);
+        reg &= ~value;
+        writel_relaxed(reg, base + offset);
+        readl_relaxed(base + offset);
+}
+static void u2o_write(void __iomem *base, unsigned int offset,
+                unsigned int value)
+{
+        writel_relaxed(value, base + offset);
+        readl_relaxed(base + offset);
+}
+#if defined(CONFIG_USB_MV_UDC) || defined(CONFIG_USB_EHCI_MV)
+#if defined(CONFIG_CPU_PXA910) || defined(CONFIG_CPU_PXA168)
+static DEFINE_MUTEX(phy_lock);
+static int phy_init_cnt;
+static int usb_phy_init_internal(void __iomem *base)
+{
+        int loops;
+        pr_info("Init usb phy!!!\n");
+        /* Initialize the USB PHY power */
+        if (cpu_is_pxa910()) {
+                u2o_set(base, UTMI_CTRL, (1<<UTMI_CTRL_INPKT_DELAY_SOF_SHIFT)
+                        | (1<<UTMI_CTRL_PU_REF_SHIFT));
+        }
+        u2o_set(base, UTMI_CTRL, 1<<UTMI_CTRL_PLL_PWR_UP_SHIFT);
+        u2o_set(base, UTMI_CTRL, 1<<UTMI_CTRL_PWR_UP_SHIFT);
+        /* UTMI_PLL settings */
+        u2o_clear(base, UTMI_PLL, UTMI_PLL_PLLVDD18_MASK
+                | UTMI_PLL_PLLVDD12_MASK | UTMI_PLL_PLLCALI12_MASK
+                | UTMI_PLL_FBDIV_MASK | UTMI_PLL_REFDIV_MASK
+                | UTMI_PLL_ICP_MASK | UTMI_PLL_KVCO_MASK);
+        u2o_set(base, UTMI_PLL, 0xee<<UTMI_PLL_FBDIV_SHIFT
+                | 0xb<<UTMI_PLL_REFDIV_SHIFT | 3<<UTMI_PLL_PLLVDD18_SHIFT
+                | 3<<UTMI_PLL_PLLVDD12_SHIFT | 3<<UTMI_PLL_PLLCALI12_SHIFT
+                | 1<<UTMI_PLL_ICP_SHIFT | 3<<UTMI_PLL_KVCO_SHIFT);
+        /* UTMI_TX */
+        u2o_clear(base, UTMI_TX, UTMI_TX_REG_EXT_FS_RCAL_EN_MASK
+                | UTMI_TX_TXVDD12_MASK | UTMI_TX_CK60_PHSEL_MASK
+                | UTMI_TX_IMPCAL_VTH_MASK | UTMI_TX_REG_EXT_FS_RCAL_MASK
+                | UTMI_TX_AMP_MASK);
+        u2o_set(base, UTMI_TX, 3<<UTMI_TX_TXVDD12_SHIFT
+                | 4<<UTMI_TX_CK60_PHSEL_SHIFT | 4<<UTMI_TX_IMPCAL_VTH_SHIFT
+                | 8<<UTMI_TX_REG_EXT_FS_RCAL_SHIFT | 3<<UTMI_TX_AMP_SHIFT);
+        /* UTMI_RX */
+        u2o_clear(base, UTMI_RX, UTMI_RX_SQ_THRESH_MASK
+                | UTMI_REG_SQ_LENGTH_MASK);
+        u2o_set(base, UTMI_RX, 7<<UTMI_RX_SQ_THRESH_SHIFT
+                | 2<<UTMI_REG_SQ_LENGTH_SHIFT);
+        /* UTMI_IVREF */
+        if (cpu_is_pxa168())
+                /* fixing Microsoft Altair board interface with NEC hub issue -
+                 * Set UTMI_IVREF from 0x4a3 to 0x4bf */
+                u2o_write(base, UTMI_IVREF, 0x4bf);
+        /* toggle VCOCAL_START bit of UTMI_PLL */
+        udelay(200);
+        u2o_set(base, UTMI_PLL, VCOCAL_START);
+        udelay(40);
+        u2o_clear(base, UTMI_PLL, VCOCAL_START);
+        /* toggle REG_RCAL_START bit of UTMI_TX */
+        udelay(400);
+        u2o_set(base, UTMI_TX, REG_RCAL_START);
+        udelay(40);
+        u2o_clear(base, UTMI_TX, REG_RCAL_START);
+        udelay(400);
+        /* Make sure PHY PLL is ready */
+        loops = 0;
+        while ((u2o_get(base, UTMI_PLL) & PLL_READY) == 0) {
+                mdelay(1);
+                loops++;
+                if (loops > 100) {
+                        printk(KERN_WARNING "calibrate timeout, UTMI_PLL %x\n",
+                                u2o_get(base, UTMI_PLL));
+                        break;
+                }
+        }
+        if (cpu_is_pxa168()) {
+                u2o_set(base, UTMI_RESERVE, 1 << 5);
+                /* Turn on UTMI PHY OTG extension */
+                u2o_write(base, UTMI_OTG_ADDON, 1);
+        }
+        return 0;
+}
+static int usb_phy_deinit_internal(void __iomem *base)
+{
+        pr_info("Deinit usb phy!!!\n");
+        if (cpu_is_pxa168())
+                u2o_clear(base, UTMI_OTG_ADDON, UTMI_OTG_ADDON_OTG_ON);
+        u2o_clear(base, UTMI_CTRL, UTMI_CTRL_RXBUF_PDWN);
+        u2o_clear(base, UTMI_CTRL, UTMI_CTRL_TXBUF_PDWN);
+        u2o_clear(base, UTMI_CTRL, UTMI_CTRL_USB_CLK_EN);
+        u2o_clear(base, UTMI_CTRL, 1<<UTMI_CTRL_PWR_UP_SHIFT);
+        u2o_clear(base, UTMI_CTRL, 1<<UTMI_CTRL_PLL_PWR_UP_SHIFT);
+        return 0;
+}
+int pxa_usb_phy_init(void __iomem *phy_reg)
+{
+        mutex_lock(&phy_lock);
+        if (phy_init_cnt++ == 0)
+                usb_phy_init_internal(phy_reg);
+        mutex_unlock(&phy_lock);
+        return 0;
+}
+void pxa_usb_phy_deinit(void __iomem *phy_reg)
+{
+        WARN_ON(phy_init_cnt == 0);
+        mutex_lock(&phy_lock);
+        if (--phy_init_cnt == 0)
+                usb_phy_deinit_internal(phy_reg);
+        mutex_unlock(&phy_lock);
+}
+#endif
+#endif
+#endif
+#ifdef CONFIG_USB_SUPPORT
+static u64 usb_dma_mask = ~(u32)0;
+#ifdef CONFIG_USB_MV_UDC
+struct resource pxa168_u2o_resources[] = {
+        /* regbase */
+        [0] = {
+                .start  = PXA168_U2O_REGBASE + U2x_CAPREGS_OFFSET,
+                .end    = PXA168_U2O_REGBASE + USB_REG_RANGE,
+                .flags  = IORESOURCE_MEM,
+                .name   = "capregs",
+        },
+        /* phybase */
+        [1] = {
+                .start  = PXA168_U2O_PHYBASE,
+                .end    = PXA168_U2O_PHYBASE + USB_PHY_RANGE,
+                .flags  = IORESOURCE_MEM,
+                .name   = "phyregs",
+        },
+        [2] = {
+                .start  = IRQ_PXA168_USB1,
+                .end    = IRQ_PXA168_USB1,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+struct platform_device pxa168_device_u2o = {
+        .name           = "mv-udc",
+        .id             = -1,
+        .resource       = pxa168_u2o_resources,
+        .num_resources  = ARRAY_SIZE(pxa168_u2o_resources),
+        .dev            =  {
+                .dma_mask       = &usb_dma_mask,
+                .coherent_dma_mask = 0xffffffff,
+        }
+};
+#endif /* CONFIG_USB_MV_UDC */
+#ifdef CONFIG_USB_EHCI_MV_U2O
+struct resource pxa168_u2oehci_resources[] = {
+        /* regbase */
+        [0] = {
+                .start  = PXA168_U2O_REGBASE + U2x_CAPREGS_OFFSET,
+                .end    = PXA168_U2O_REGBASE + USB_REG_RANGE,
+                .flags  = IORESOURCE_MEM,
+                .name   = "capregs",
+        },
+        /* phybase */
+        [1] = {
+                .start  = PXA168_U2O_PHYBASE,
+                .end    = PXA168_U2O_PHYBASE + USB_PHY_RANGE,
+                .flags  = IORESOURCE_MEM,
+                .name   = "phyregs",
+        },
+        [2] = {
+                .start  = IRQ_PXA168_USB1,
+                .end    = IRQ_PXA168_USB1,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+struct platform_device pxa168_device_u2oehci = {
+        .name           = "pxa-u2oehci",
+        .id             = -1,
+        .dev            = {
+                .dma_mask               = &usb_dma_mask,
+                .coherent_dma_mask      = 0xffffffff,
+        },
+        .num_resources  = ARRAY_SIZE(pxa168_u2oehci_resources),
+        .resource       = pxa168_u2oehci_resources,
+};
+#endif
+#if defined(CONFIG_USB_MV_OTG)
+struct resource pxa168_u2ootg_resources[] = {
+        /* regbase */
+        [0] = {
+                .start  = PXA168_U2O_REGBASE + U2x_CAPREGS_OFFSET,
+                .end    = PXA168_U2O_REGBASE + USB_REG_RANGE,
+                .flags  = IORESOURCE_MEM,
+                .name   = "capregs",
+        },
+        /* phybase */
+        [1] = {
+                .start  = PXA168_U2O_PHYBASE,
+                .end    = PXA168_U2O_PHYBASE + USB_PHY_RANGE,
+                .flags  = IORESOURCE_MEM,
+                .name   = "phyregs",
+        },
+        [2] = {
+                .start  = IRQ_PXA168_USB1,
+                .end    = IRQ_PXA168_USB1,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+struct platform_device pxa168_device_u2ootg = {
+        .name           = "mv-otg",
+        .id             = -1,
+        .dev  = {
+                .dma_mask          = &usb_dma_mask,
+                .coherent_dma_mask = 0xffffffff,
+        },
+        .num_resources  = ARRAY_SIZE(pxa168_u2ootg_resources),
+        .resource      = pxa168_u2ootg_resources,
+};
+#endif /* CONFIG_USB_MV_OTG */
+#endif
diff --git a/arch/arm/mach-mmp/include/mach/addr-map.h b/arch/arm/mach-mmp/include/mach/addr-map.h
index b1ece08174e8..f88a44c0ef91 100644
--- a/arch/arm/mach-mmp/include/mach/addr-map.h
+++ b/arch/arm/mach-mmp/include/mach/addr-map.h
@@ -31,4 +31,16 @@
 #define SMC_CS1_PHYS_BASE       0x90000000
 #define SMC_CS1_PHYS_SIZE       0x10000000
+#define APMU_VIRT_BASE          (AXI_VIRT_BASE + 0x82800)
+#define APMU_REG(x)             (APMU_VIRT_BASE + (x))
+#define APBC_VIRT_BASE          (APB_VIRT_BASE + 0x015000)
+#define APBC_REG(x)             (APBC_VIRT_BASE + (x))
+#define MPMU_VIRT_BASE          (APB_VIRT_BASE + 0x50000)
+#define MPMU_REG(x)             (MPMU_VIRT_BASE + (x))
+#define CIU_VIRT_BASE           (AXI_VIRT_BASE + 0x82c00)
+#define CIU_REG(x)              (CIU_VIRT_BASE + (x))
 #endif /* __ASM_MACH_ADDR_MAP_H */
diff --git a/arch/arm/mach-mmp/include/mach/devices.h b/arch/arm/mach-mmp/include/mach/devices.h
index d0ec7dae88e4..21217ef11b64 100644
--- a/arch/arm/mach-mmp/include/mach/devices.h
+++ b/arch/arm/mach-mmp/include/mach/devices.h
@@ -50,4 +50,7 @@ struct pxa_device_desc mmp2_device_##_name __initdata = {		\
 }
 extern int pxa_register_device(struct pxa_device_desc *, void *, size_t);
+extern int pxa_usb_phy_init(void __iomem *phy_reg);
+extern void pxa_usb_phy_deinit(void __iomem *phy_reg);
 #endif /* __MACH_DEVICE_H */
diff --git a/arch/arm/mach-mmp/include/mach/entry-macro.S b/arch/arm/mach-mmp/include/mach/entry-macro.S
index 9cff9e7a2b26..bd152e24e6d7 100644
--- a/arch/arm/mach-mmp/include/mach/entry-macro.S
+++ b/arch/arm/mach-mmp/include/mach/entry-macro.S
@@ -6,13 +6,15 @@
 * published by the Free Software Foundation.
 */
+#include <asm/irq.h>
 #include <mach/regs-icu.h>
        .macro  get_irqnr_preamble, base, tmp
        mrc     p15, 0, \tmp, c0, c0, 0         @ CPUID
        and     \tmp, \tmp, #0xff00
        cmp     \tmp, #0x5800
-        ldr     \base, =ICU_VIRT_BASE
+        ldr     \base, =mmp_icu_base
+        ldr     \base, [\base, #0]
        addne   \base, \base, #0x10c            @ PJ1 AP INT SEL register
        addeq   \base, \base, #0x104            @ PJ4 IRQ SEL register
        .endm
diff --git a/arch/arm/mach-mmp/include/mach/irqs.h b/arch/arm/mach-mmp/include/mach/irqs.h
index d0e746626a3d..fb492a50a817 100644
--- a/arch/arm/mach-mmp/include/mach/irqs.h
+++ b/arch/arm/mach-mmp/include/mach/irqs.h
@@ -125,7 +125,7 @@
 #define IRQ_MMP2_RTC_MUX                5
 #define IRQ_MMP2_TWSI1                  7
 #define IRQ_MMP2_GPU                    8
-#define IRQ_MMP2_KEYPAD                 9
+#define IRQ_MMP2_KEYPAD_MUX             9
 #define IRQ_MMP2_ROTARY                 10
 #define IRQ_MMP2_TRACKBALL              11
 #define IRQ_MMP2_ONEWIRE                12
@@ -163,11 +163,11 @@
 #define IRQ_MMP2_DMA_FIQ                47
 #define IRQ_MMP2_DMA_RIQ                48
 #define IRQ_MMP2_GPIO                   49
-#define IRQ_MMP2_SSP_MUX                51
+#define IRQ_MMP2_MIPI_HSI1_MUX          51
 #define IRQ_MMP2_MMC2                   52
 #define IRQ_MMP2_MMC3                   53
 #define IRQ_MMP2_MMC4                   54
-#define IRQ_MMP2_MIPI_HSI               55
+#define IRQ_MMP2_MIPI_HSI0_MUX          55
 #define IRQ_MMP2_MSP                    58
 #define IRQ_MMP2_MIPI_SLIM_DMA          59
 #define IRQ_MMP2_PJ4_FREQ_CHG           60
@@ -186,8 +186,14 @@
 #define IRQ_MMP2_RTC_ALARM              (IRQ_MMP2_RTC_BASE + 0)
 #define IRQ_MMP2_RTC                    (IRQ_MMP2_RTC_BASE + 1)
+/* secondary interrupt of INT #9 */
+#define IRQ_MMP2_KEYPAD_BASE            (IRQ_MMP2_RTC_BASE + 2)
+#define IRQ_MMP2_KPC                    (IRQ_MMP2_KEYPAD_BASE + 0)
+#define IRQ_MMP2_ROTORY                 (IRQ_MMP2_KEYPAD_BASE + 1)
+#define IRQ_MMP2_TBALL                  (IRQ_MMP2_KEYPAD_BASE + 2)
 /* secondary interrupt of INT #17 */
-#define IRQ_MMP2_TWSI_BASE              (IRQ_MMP2_RTC_BASE + 2)
+#define IRQ_MMP2_TWSI_BASE              (IRQ_MMP2_KEYPAD_BASE + 3)
 #define IRQ_MMP2_TWSI2                  (IRQ_MMP2_TWSI_BASE + 0)
 #define IRQ_MMP2_TWSI3                  (IRQ_MMP2_TWSI_BASE + 1)
 #define IRQ_MMP2_TWSI4                  (IRQ_MMP2_TWSI_BASE + 2)
@@ -212,11 +218,16 @@
 #define IRQ_MMP2_COMMRX                 (IRQ_MMP2_MISC_BASE + 14)
 /* secondary interrupt of INT #51 */
-#define IRQ_MMP2_SSP_BASE               (IRQ_MMP2_MISC_BASE + 15)
+#define IRQ_MMP2_MIPI_HSI1_BASE         (IRQ_MMP2_MISC_BASE + 15)
-#define IRQ_MMP2_SSP1_SRDY              (IRQ_MMP2_SSP_BASE + 0)
+#define IRQ_MMP2_HSI1_CAWAKE            (IRQ_MMP2_MIPI_HSI1_BASE + 0)
-#define IRQ_MMP2_SSP3_SRDY              (IRQ_MMP2_SSP_BASE + 1)
+#define IRQ_MMP2_MIPI_HSI_INT1          (IRQ_MMP2_MIPI_HSI1_BASE + 1)
+/* secondary interrupt of INT #55 */
+#define IRQ_MMP2_MIPI_HSI0_BASE         (IRQ_MMP2_MIPI_HSI1_BASE + 2)
+#define IRQ_MMP2_HSI0_CAWAKE            (IRQ_MMP2_MIPI_HSI0_BASE + 0)
+#define IRQ_MMP2_MIPI_HSI_INT0          (IRQ_MMP2_MIPI_HSI0_BASE + 1)
-#define IRQ_MMP2_MUX_END                (IRQ_MMP2_SSP_BASE + 2)
+#define IRQ_MMP2_MUX_END                (IRQ_MMP2_MIPI_HSI0_BASE + 2)
 #define IRQ_GPIO_START                  128
 #define MMP_NR_BUILTIN_GPIO             192
diff --git a/arch/arm/mach-mmp/include/mach/pm-mmp2.h b/arch/arm/mach-mmp/include/mach/pm-mmp2.h
new file mode 100644
index 000000000000..98bd66ce8006
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/pm-mmp2.h
@@ -0,0 +1,61 @@
+/*
+ * MMP2 Power Management Routines
+ *
+ * This software program is licensed subject to the GNU General Public License
+ * (GPL).Version 2,June 1991, available at http://www.fsf.org/copyleft/gpl.html
+ *
+ * (C) Copyright 2010 Marvell International Ltd.
+ * All Rights Reserved
+ */
+#ifndef __MMP2_PM_H__
+#define __MMP2_PM_H__
+#include <mach/addr-map.h>
+#define APMU_PJ_IDLE_CFG                        APMU_REG(0x018)
+#define APMU_PJ_IDLE_CFG_PJ_IDLE                (1 << 1)
+#define APMU_PJ_IDLE_CFG_PJ_PWRDWN              (1 << 5)
+#define APMU_PJ_IDLE_CFG_PWR_SW(x)              ((x) << 16)
+#define APMU_PJ_IDLE_CFG_L2_PWR_SW              (1 << 19)
+#define APMU_PJ_IDLE_CFG_ISO_MODE_CNTRL_MASK    (3 << 28)
+#define APMU_SRAM_PWR_DWN                       APMU_REG(0x08c)
+#define MPMU_SCCR                               MPMU_REG(0x038)
+#define MPMU_PCR_PJ                             MPMU_REG(0x1000)
+#define MPMU_PCR_PJ_AXISD                       (1 << 31)
+#define MPMU_PCR_PJ_SLPEN                       (1 << 29)
+#define MPMU_PCR_PJ_SPSD                        (1 << 28)
+#define MPMU_PCR_PJ_DDRCORSD                    (1 << 27)
+#define MPMU_PCR_PJ_APBSD                       (1 << 26)
+#define MPMU_PCR_PJ_INTCLR                      (1 << 24)
+#define MPMU_PCR_PJ_SLPWP0                      (1 << 23)
+#define MPMU_PCR_PJ_SLPWP1                      (1 << 22)
+#define MPMU_PCR_PJ_SLPWP2                      (1 << 21)
+#define MPMU_PCR_PJ_SLPWP3                      (1 << 20)
+#define MPMU_PCR_PJ_VCTCXOSD                    (1 << 19)
+#define MPMU_PCR_PJ_SLPWP4                      (1 << 18)
+#define MPMU_PCR_PJ_SLPWP5                      (1 << 17)
+#define MPMU_PCR_PJ_SLPWP6                      (1 << 16)
+#define MPMU_PCR_PJ_SLPWP7                      (1 << 15)
+#define MPMU_PLL2_CTRL1                         MPMU_REG(0x0414)
+#define MPMU_CGR_PJ                             MPMU_REG(0x1024)
+#define MPMU_WUCRM_PJ                           MPMU_REG(0x104c)
+#define MPMU_WUCRM_PJ_WAKEUP(x)                 (1 << (x))
+#define MPMU_WUCRM_PJ_RTC_ALARM                 (1 << 17)
+enum {
+        POWER_MODE_ACTIVE = 0,
+        POWER_MODE_CORE_INTIDLE,
+        POWER_MODE_CORE_EXTIDLE,
+        POWER_MODE_APPS_IDLE,
+        POWER_MODE_APPS_SLEEP,
+        POWER_MODE_CHIP_SLEEP,
+        POWER_MODE_SYS_SLEEP,
+};
+extern void mmp2_pm_enter_lowpower_mode(int state);
+extern int mmp2_set_wake(struct irq_data *d, unsigned int on);
+#endif
diff --git a/arch/arm/mach-mmp/include/mach/pm-pxa910.h b/arch/arm/mach-mmp/include/mach/pm-pxa910.h
new file mode 100644
index 000000000000..8cac8ab5253d
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/pm-pxa910.h
@@ -0,0 +1,77 @@
+/*
+ * PXA910 Power Management Routines
+ *
+ * This software program is licensed subject to the GNU General Public License
+ * (GPL).Version 2,June 1991, available at http://www.fsf.org/copyleft/gpl.html
+ *
+ * (C) Copyright 2009 Marvell International Ltd.
+ * All Rights Reserved
+ */
+#ifndef __PXA910_PM_H__
+#define __PXA910_PM_H__
+#define APMU_MOH_IDLE_CFG                       APMU_REG(0x0018)
+#define APMU_MOH_IDLE_CFG_MOH_IDLE              (1 << 1)
+#define APMU_MOH_IDLE_CFG_MOH_PWRDWN            (1 << 5)
+#define APMU_MOH_IDLE_CFG_MOH_SRAM_PWRDWN       (1 << 6)
+#define APMU_MOH_IDLE_CFG_MOH_PWR_SW(x)         (((x) & 0x3) << 16)
+#define APMU_MOH_IDLE_CFG_MOH_L2_PWR_SW(x)      (((x) & 0x3) << 18)
+#define APMU_MOH_IDLE_CFG_MOH_DIS_MC_SW_REQ     (1 << 21)
+#define APMU_MOH_IDLE_CFG_MOH_MC_WAKE_EN        (1 << 20)
+#define APMU_SQU_CLK_GATE_CTRL                  APMU_REG(0x001c)
+#define APMU_MC_HW_SLP_TYPE                     APMU_REG(0x00b0)
+#define MPMU_FCCR                               MPMU_REG(0x0008)
+#define MPMU_APCR                               MPMU_REG(0x1000)
+#define MPMU_APCR_AXISD                         (1 << 31)
+#define MPMU_APCR_DSPSD                         (1 << 30)
+#define MPMU_APCR_SLPEN                         (1 << 29)
+#define MPMU_APCR_DTCMSD                        (1 << 28)
+#define MPMU_APCR_DDRCORSD                      (1 << 27)
+#define MPMU_APCR_APBSD                         (1 << 26)
+#define MPMU_APCR_BBSD                          (1 << 25)
+#define MPMU_APCR_SLPWP0                        (1 << 23)
+#define MPMU_APCR_SLPWP1                        (1 << 22)
+#define MPMU_APCR_SLPWP2                        (1 << 21)
+#define MPMU_APCR_SLPWP3                        (1 << 20)
+#define MPMU_APCR_VCTCXOSD                      (1 << 19)
+#define MPMU_APCR_SLPWP4                        (1 << 18)
+#define MPMU_APCR_SLPWP5                        (1 << 17)
+#define MPMU_APCR_SLPWP6                        (1 << 16)
+#define MPMU_APCR_SLPWP7                        (1 << 15)
+#define MPMU_APCR_MSASLPEN                      (1 << 14)
+#define MPMU_APCR_STBYEN                        (1 << 13)
+#define MPMU_AWUCRM                             MPMU_REG(0x104c)
+#define MPMU_AWUCRM_AP_ASYNC_INT                (1 << 25)
+#define MPMU_AWUCRM_AP_FULL_IDLE                (1 << 24)
+#define MPMU_AWUCRM_SDH1                        (1 << 23)
+#define MPMU_AWUCRM_SDH2                        (1 << 22)
+#define MPMU_AWUCRM_KEYPRESS                    (1 << 21)
+#define MPMU_AWUCRM_TRACKBALL                   (1 << 20)
+#define MPMU_AWUCRM_NEWROTARY                   (1 << 19)
+#define MPMU_AWUCRM_RTC_ALARM                   (1 << 17)
+#define MPMU_AWUCRM_AP2_TIMER_3                 (1 << 13)
+#define MPMU_AWUCRM_AP2_TIMER_2                 (1 << 12)
+#define MPMU_AWUCRM_AP2_TIMER_1                 (1 << 11)
+#define MPMU_AWUCRM_AP1_TIMER_3                 (1 << 10)
+#define MPMU_AWUCRM_AP1_TIMER_2                 (1 << 9)
+#define MPMU_AWUCRM_AP1_TIMER_1                 (1 << 8)
+#define MPMU_AWUCRM_WAKEUP(x)                   (1 << ((x) & 0x7))
+enum {
+        POWER_MODE_ACTIVE = 0,
+        POWER_MODE_CORE_INTIDLE,
+        POWER_MODE_CORE_EXTIDLE,
+        POWER_MODE_APPS_IDLE,
+        POWER_MODE_APPS_SLEEP,
+        POWER_MODE_SYS_SLEEP,
+        POWER_MODE_HIBERNATE,
+        POWER_MODE_UDR,
+};
+extern int pxa910_set_wake(struct irq_data *data, unsigned int on);
+#endif
diff --git a/arch/arm/mach-mmp/include/mach/pxa168.h b/arch/arm/mach-mmp/include/mach/pxa168.h
index dc03d580a06d..09dcd6e2b6a8 100644
--- a/arch/arm/mach-mmp/include/mach/pxa168.h
+++ b/arch/arm/mach-mmp/include/mach/pxa168.h
@@ -16,6 +16,7 @@ extern void pxa168_clear_keypad_wakeup(void);
 #include <plat/pxa27x_keypad.h>
 #include <mach/cputype.h>
 #include <linux/pxa168_eth.h>
+#include <linux/platform_data/mv_usb.h>
 extern struct pxa_device_desc pxa168_device_uart1;
 extern struct pxa_device_desc pxa168_device_uart2;
@@ -36,12 +37,9 @@ extern struct pxa_device_desc pxa168_device_fb;
 extern struct pxa_device_desc pxa168_device_keypad;
 extern struct pxa_device_desc pxa168_device_eth;
-struct pxa168_usb_pdata {
-        /* If NULL, default phy init routine for PXA168 would be called */
-        int (*phy_init)(void __iomem *usb_phy_reg_base);
-};
 /* pdata can be NULL */
-int __init pxa168_add_usb_host(struct pxa168_usb_pdata *pdata);
+extern int __init pxa168_add_usb_host(struct mv_usb_platform_data *pdata);
 extern struct platform_device pxa168_device_gpio;
diff --git a/arch/arm/mach-mmp/include/mach/pxa910.h b/arch/arm/mach-mmp/include/mach/pxa910.h
index e2e1f1e5e124..793634c837ef 100644
--- a/arch/arm/mach-mmp/include/mach/pxa910.h
+++ b/arch/arm/mach-mmp/include/mach/pxa910.h
@@ -20,6 +20,9 @@ extern struct pxa_device_desc pxa910_device_pwm2;
 extern struct pxa_device_desc pxa910_device_pwm3;
 extern struct pxa_device_desc pxa910_device_pwm4;
 extern struct pxa_device_desc pxa910_device_nand;
+extern struct platform_device pxa168_device_u2o;
+extern struct platform_device pxa168_device_u2ootg;
+extern struct platform_device pxa168_device_u2oehci;
 extern struct platform_device pxa910_device_gpio;
 extern struct platform_device pxa910_device_rtc;
diff --git a/arch/arm/mach-mmp/include/mach/regs-apbc.h b/arch/arm/mach-mmp/include/mach/regs-apbc.h
index 8a37fb003655..68b0c93ec6a1 100644
--- a/arch/arm/mach-mmp/include/mach/regs-apbc.h
+++ b/arch/arm/mach-mmp/include/mach/regs-apbc.h
@@ -13,9 +13,6 @@
 #include <mach/addr-map.h>
-#define APBC_VIRT_BASE  (APB_VIRT_BASE + 0x015000)
-#define APBC_REG(x)     (APBC_VIRT_BASE + (x))
 /*
 * APB clock register offsets for PXA168
 */
diff --git a/arch/arm/mach-mmp/include/mach/regs-apmu.h b/arch/arm/mach-mmp/include/mach/regs-apmu.h
index 8447ac63e28f..7af8deb63e83 100644
--- a/arch/arm/mach-mmp/include/mach/regs-apmu.h
+++ b/arch/arm/mach-mmp/include/mach/regs-apmu.h
@@ -13,9 +13,6 @@
 #include <mach/addr-map.h>
-#define APMU_VIRT_BASE  (AXI_VIRT_BASE + 0x82800)
-#define APMU_REG(x)     (APMU_VIRT_BASE + (x))
 /* Clock Reset Control */
 #define APMU_IRE        APMU_REG(0x048)
 #define APMU_LCD        APMU_REG(0x04c)
diff --git a/arch/arm/mach-mmp/include/mach/regs-usb.h b/arch/arm/mach-mmp/include/mach/regs-usb.h
new file mode 100644
index 000000000000..b047bf487506
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/regs-usb.h
@@ -0,0 +1,253 @@
+/*
+ * Copyright (C) 2011 Marvell International Ltd. All rights reserved.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+#ifndef __ASM_ARCH_REGS_USB_H
+#define __ASM_ARCH_REGS_USB_H
+#define PXA168_U2O_REGBASE      (0xd4208000)
+#define PXA168_U2O_PHYBASE      (0xd4207000)
+#define PXA168_U2H_REGBASE      (0xd4209000)
+#define PXA168_U2H_PHYBASE      (0xd4206000)
+#define MMP3_HSIC1_REGBASE      (0xf0001000)
+#define MMP3_HSIC1_PHYBASE      (0xf0001800)
+#define MMP3_HSIC2_REGBASE      (0xf0002000)
+#define MMP3_HSIC2_PHYBASE      (0xf0002800)
+#define MMP3_FSIC_REGBASE       (0xf0003000)
+#define MMP3_FSIC_PHYBASE       (0xf0003800)
+#define USB_REG_RANGE           (0x1ff)
+#define USB_PHY_RANGE           (0xff)
+/* registers */
+#define U2x_CAPREGS_OFFSET       0x100
+/* phy regs */
+#define UTMI_REVISION           0x0
+#define UTMI_CTRL               0x4
+#define UTMI_PLL                0x8
+#define UTMI_TX                 0xc
+#define UTMI_RX                 0x10
+#define UTMI_IVREF              0x14
+#define UTMI_T0                 0x18
+#define UTMI_T1                 0x1c
+#define UTMI_T2                 0x20
+#define UTMI_T3                 0x24
+#define UTMI_T4                 0x28
+#define UTMI_T5                 0x2c
+#define UTMI_RESERVE            0x30
+#define UTMI_USB_INT            0x34
+#define UTMI_DBG_CTL            0x38
+#define UTMI_OTG_ADDON          0x3c
+/* For UTMICTRL Register */
+#define UTMI_CTRL_USB_CLK_EN                    (1 << 31)
+/* pxa168 */
+#define UTMI_CTRL_SUSPEND_SET1                  (1 << 30)
+#define UTMI_CTRL_SUSPEND_SET2                  (1 << 29)
+#define UTMI_CTRL_RXBUF_PDWN                    (1 << 24)
+#define UTMI_CTRL_TXBUF_PDWN                    (1 << 11)
+#define UTMI_CTRL_INPKT_DELAY_SHIFT             30
+#define UTMI_CTRL_INPKT_DELAY_SOF_SHIFT         28
+#define UTMI_CTRL_PU_REF_SHIFT                  20
+#define UTMI_CTRL_ARC_PULLDN_SHIFT              12
+#define UTMI_CTRL_PLL_PWR_UP_SHIFT              1
+#define UTMI_CTRL_PWR_UP_SHIFT                  0
+/* For UTMI_PLL Register */
+#define UTMI_PLL_PLLCALI12_SHIFT                29
+#define UTMI_PLL_PLLCALI12_MASK                 (0x3 << 29)
+#define UTMI_PLL_PLLVDD18_SHIFT                 27
+#define UTMI_PLL_PLLVDD18_MASK                  (0x3 << 27)
+#define UTMI_PLL_PLLVDD12_SHIFT                 25
+#define UTMI_PLL_PLLVDD12_MASK                  (0x3 << 25)
+#define UTMI_PLL_CLK_BLK_EN_SHIFT               24
+#define CLK_BLK_EN                              (0x1 << 24)
+#define PLL_READY                               (0x1 << 23)
+#define KVCO_EXT                                (0x1 << 22)
+#define VCOCAL_START                            (0x1 << 21)
+#define UTMI_PLL_KVCO_SHIFT                     15
+#define UTMI_PLL_KVCO_MASK                      (0x7 << 15)
+#define UTMI_PLL_ICP_SHIFT                      12
+#define UTMI_PLL_ICP_MASK                       (0x7 << 12)
+#define UTMI_PLL_FBDIV_SHIFT                    4
+#define UTMI_PLL_FBDIV_MASK                     (0xFF << 4)
+#define UTMI_PLL_REFDIV_SHIFT                   0
+#define UTMI_PLL_REFDIV_MASK                    (0xF << 0)
+/* For UTMI_TX Register */
+#define UTMI_TX_REG_EXT_FS_RCAL_SHIFT           27
+#define UTMI_TX_REG_EXT_FS_RCAL_MASK            (0xf << 27)
+#define UTMI_TX_REG_EXT_FS_RCAL_EN_SHIFT        26
+#define UTMI_TX_REG_EXT_FS_RCAL_EN_MASK         (0x1 << 26)
+#define UTMI_TX_TXVDD12_SHIFT                   22
+#define UTMI_TX_TXVDD12_MASK                    (0x3 << 22)
+#define UTMI_TX_CK60_PHSEL_SHIFT                17
+#define UTMI_TX_CK60_PHSEL_MASK                 (0xf << 17)
+#define UTMI_TX_IMPCAL_VTH_SHIFT                14
+#define UTMI_TX_IMPCAL_VTH_MASK                 (0x7 << 14)
+#define REG_RCAL_START                          (0x1 << 12)
+#define UTMI_TX_LOW_VDD_EN_SHIFT                11
+#define UTMI_TX_AMP_SHIFT                       0
+#define UTMI_TX_AMP_MASK                        (0x7 << 0)
+/* For UTMI_RX Register */
+#define UTMI_REG_SQ_LENGTH_SHIFT                15
+#define UTMI_REG_SQ_LENGTH_MASK                 (0x3 << 15)
+#define UTMI_RX_SQ_THRESH_SHIFT                 4
+#define UTMI_RX_SQ_THRESH_MASK                  (0xf << 4)
+#define UTMI_OTG_ADDON_OTG_ON                   (1 << 0)
+/* For MMP3 USB Phy */
+#define USB2_PLL_REG0           0x4
+#define USB2_PLL_REG1           0x8
+#define USB2_TX_REG0            0x10
+#define USB2_TX_REG1            0x14
+#define USB2_TX_REG2            0x18
+#define USB2_RX_REG0            0x20
+#define USB2_RX_REG1            0x24
+#define USB2_RX_REG2            0x28
+#define USB2_ANA_REG0           0x30
+#define USB2_ANA_REG1           0x34
+#define USB2_ANA_REG2           0x38
+#define USB2_DIG_REG0           0x3C
+#define USB2_DIG_REG1           0x40
+#define USB2_DIG_REG2           0x44
+#define USB2_DIG_REG3           0x48
+#define USB2_TEST_REG0          0x4C
+#define USB2_TEST_REG1          0x50
+#define USB2_TEST_REG2          0x54
+#define USB2_CHARGER_REG0       0x58
+#define USB2_OTG_REG0           0x5C
+#define USB2_PHY_MON0           0x60
+#define USB2_RESETVE_REG0       0x64
+#define USB2_ICID_REG0          0x78
+#define USB2_ICID_REG1          0x7C
+/* USB2_PLL_REG0 */
+/* This is for Ax stepping */
+#define USB2_PLL_FBDIV_SHIFT_MMP3               0
+#define USB2_PLL_FBDIV_MASK_MMP3                (0xFF << 0)
+#define USB2_PLL_REFDIV_SHIFT_MMP3              8
+#define USB2_PLL_REFDIV_MASK_MMP3               (0xF << 8)
+#define USB2_PLL_VDD12_SHIFT_MMP3               12
+#define USB2_PLL_VDD18_SHIFT_MMP3               14
+/* This is for B0 stepping */
+#define USB2_PLL_FBDIV_SHIFT_MMP3_B0            0
+#define USB2_PLL_REFDIV_SHIFT_MMP3_B0           9
+#define USB2_PLL_VDD18_SHIFT_MMP3_B0            14
+#define USB2_PLL_FBDIV_MASK_MMP3_B0             0x01FF
+#define USB2_PLL_REFDIV_MASK_MMP3_B0            0x3E00
+#define USB2_PLL_CAL12_SHIFT_MMP3               0
+#define USB2_PLL_CALI12_MASK_MMP3               (0x3 << 0)
+#define USB2_PLL_VCOCAL_START_SHIFT_MMP3        2
+#define USB2_PLL_KVCO_SHIFT_MMP3                4
+#define USB2_PLL_KVCO_MASK_MMP3                 (0x7<<4)
+#define USB2_PLL_ICP_SHIFT_MMP3                 8
+#define USB2_PLL_ICP_MASK_MMP3                  (0x7<<8)
+#define USB2_PLL_LOCK_BYPASS_SHIFT_MMP3         12
+#define USB2_PLL_PU_PLL_SHIFT_MMP3              13
+#define USB2_PLL_PU_PLL_MASK                    (0x1 << 13)
+#define USB2_PLL_READY_MASK_MMP3                (0x1 << 15)
+/* USB2_TX_REG0 */
+#define USB2_TX_IMPCAL_VTH_SHIFT_MMP3           8
+#define USB2_TX_IMPCAL_VTH_MASK_MMP3            (0x7 << 8)
+#define USB2_TX_RCAL_START_SHIFT_MMP3           13
+/* USB2_TX_REG1 */
+#define USB2_TX_CK60_PHSEL_SHIFT_MMP3           0
+#define USB2_TX_CK60_PHSEL_MASK_MMP3            (0xf << 0)
+#define USB2_TX_AMP_SHIFT_MMP3                  4
+#define USB2_TX_AMP_MASK_MMP3                   (0x7 << 4)
+#define USB2_TX_VDD12_SHIFT_MMP3                8
+#define USB2_TX_VDD12_MASK_MMP3                 (0x3 << 8)
+/* USB2_TX_REG2 */
+#define USB2_TX_DRV_SLEWRATE_SHIFT              10
+/* USB2_RX_REG0 */
+#define USB2_RX_SQ_THRESH_SHIFT_MMP3            4
+#define USB2_RX_SQ_THRESH_MASK_MMP3             (0xf << 4)
+#define USB2_RX_SQ_LENGTH_SHIFT_MMP3            10
+#define USB2_RX_SQ_LENGTH_MASK_MMP3             (0x3 << 10)
+/* USB2_ANA_REG1*/
+#define USB2_ANA_PU_ANA_SHIFT_MMP3              14
+/* USB2_OTG_REG0 */
+#define USB2_OTG_PU_OTG_SHIFT_MMP3              3
+/* fsic registers */
+#define FSIC_MISC                       0x4
+#define FSIC_INT                        0x28
+#define FSIC_CTRL                       0x30
+/* HSIC registers */
+#define HSIC_PAD_CTRL                   0x4
+#define HSIC_CTRL                       0x8
+#define HSIC_CTRL_HSIC_ENABLE           (1<<7)
+#define HSIC_CTRL_PLL_BYPASS            (1<<4)
+#define TEST_GRP_0                      0xc
+#define TEST_GRP_1                      0x10
+#define HSIC_INT                        0x14
+#define HSIC_INT_READY_INT_EN           (1<<10)
+#define HSIC_INT_CONNECT_INT_EN         (1<<9)
+#define HSIC_INT_CORE_INT_EN            (1<<8)
+#define HSIC_INT_HS_READY               (1<<2)
+#define HSIC_INT_CONNECT                (1<<1)
+#define HSIC_INT_CORE                   (1<<0)
+#define HSIC_CONFIG                     0x18
+#define USBHSIC_CTRL                    0x20
+#define HSIC_USB_CTRL                   0x28
+#define HSIC_USB_CTRL_CLKEN             1
+#define HSIC_USB_CLK_PHY                0x0
+#define HSIC_USB_CLK_PMU                0x1
+#endif /* __ASM_ARCH_PXA_U2O_H */
diff --git a/arch/arm/mach-mmp/irq-mmp2.c b/arch/arm/mach-mmp/irq-mmp2.c
deleted file mode 100644
index 7895d277421e..000000000000
--- a/arch/arm/mach-mmp/irq-mmp2.c
+++ /dev/null
@@ -1,158 +0,0 @@
-/*
- *  linux/arch/arm/mach-mmp/irq-mmp2.c
- *
- *  Generic IRQ handling, GPIO IRQ demultiplexing, etc.
- *
- *  Author:     Haojian Zhuang <haojian.zhuang@marvell.com>
- *  Copyright:  Marvell International Ltd.
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License version 2 as
- *  published by the Free Software Foundation.
- */
-#include <linux/init.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <mach/irqs.h>
-#include <mach/regs-icu.h>
-#include <mach/mmp2.h>
-#include "common.h"
-static void icu_mask_irq(struct irq_data *d)
-{
-        uint32_t r = __raw_readl(ICU_INT_CONF(d->irq));
-        r &= ~ICU_INT_ROUTE_PJ4_IRQ;
-        __raw_writel(r, ICU_INT_CONF(d->irq));
-}
-static void icu_unmask_irq(struct irq_data *d)
-{
-        uint32_t r = __raw_readl(ICU_INT_CONF(d->irq));
-        r |= ICU_INT_ROUTE_PJ4_IRQ;
-        __raw_writel(r, ICU_INT_CONF(d->irq));
-}
-static struct irq_chip icu_irq_chip = {
-        .name           = "icu_irq",
-        .irq_mask       = icu_mask_irq,
-        .irq_mask_ack   = icu_mask_irq,
-        .irq_unmask     = icu_unmask_irq,
-};
-static void pmic_irq_ack(struct irq_data *d)
-{
-        if (d->irq == IRQ_MMP2_PMIC)
-                mmp2_clear_pmic_int();
-}
-#define SECOND_IRQ_MASK(_name_, irq_base, prefix)                       \
-static void _name_##_mask_irq(struct irq_data *d)                       \
-{                                                                       \
-        uint32_t r;                                                     \
-        r = __raw_readl(prefix##_MASK) | (1 << (d->irq - irq_base));    \
-        __raw_writel(r, prefix##_MASK);                                 \
-}
-#define SECOND_IRQ_UNMASK(_name_, irq_base, prefix)                     \
-static void _name_##_unmask_irq(struct irq_data *d)                     \
-{                                                                       \
-        uint32_t r;                                                     \
-        r = __raw_readl(prefix##_MASK) & ~(1 << (d->irq - irq_base));   \
-        __raw_writel(r, prefix##_MASK);                                 \
-}
-#define SECOND_IRQ_DEMUX(_name_, irq_base, prefix)                      \
-static void _name_##_irq_demux(unsigned int irq, struct irq_desc *desc) \
-{                                                                       \
-        unsigned long status, mask, n;                                  \
-        mask = __raw_readl(prefix##_MASK);                              \
-        while (1) {                                                     \
-                status = __raw_readl(prefix##_STATUS) & ~mask;          \
-                if (status == 0)                                        \
-                        break;                                          \
-                n = find_first_bit(&status, BITS_PER_LONG);             \
-                while (n < BITS_PER_LONG) {                             \
-                        generic_handle_irq(irq_base + n);               \
-                        n = find_next_bit(&status, BITS_PER_LONG, n+1); \
-                }                                                       \
-        }                                                               \
-}
-#define SECOND_IRQ_CHIP(_name_, irq_base, prefix)                       \
-SECOND_IRQ_MASK(_name_, irq_base, prefix)                               \
-SECOND_IRQ_UNMASK(_name_, irq_base, prefix)                             \
-SECOND_IRQ_DEMUX(_name_, irq_base, prefix)                              \
-static struct irq_chip _name_##_irq_chip = {                            \
-        .name           = #_name_,                                      \
-        .irq_mask       = _name_##_mask_irq,                            \
-        .irq_unmask     = _name_##_unmask_irq,                          \
-}
-SECOND_IRQ_CHIP(pmic, IRQ_MMP2_PMIC_BASE, MMP2_ICU_INT4);
-SECOND_IRQ_CHIP(rtc,  IRQ_MMP2_RTC_BASE,  MMP2_ICU_INT5);
-SECOND_IRQ_CHIP(twsi, IRQ_MMP2_TWSI_BASE, MMP2_ICU_INT17);
-SECOND_IRQ_CHIP(misc, IRQ_MMP2_MISC_BASE, MMP2_ICU_INT35);
-SECOND_IRQ_CHIP(ssp,  IRQ_MMP2_SSP_BASE,  MMP2_ICU_INT51);
-static void init_mux_irq(struct irq_chip *chip, int start, int num)
-{
-        int irq;
-        for (irq = start; num > 0; irq++, num--) {
-                struct irq_data *d = irq_get_irq_data(irq);
-                /* mask and clear the IRQ */
-                chip->irq_mask(d);
-                if (chip->irq_ack)
-                        chip->irq_ack(d);
-                irq_set_chip(irq, chip);
-                set_irq_flags(irq, IRQF_VALID);
-                irq_set_handler(irq, handle_level_irq);
-        }
-}
-void __init mmp2_init_icu(void)
-{
-        int irq;
-        for (irq = 0; irq < IRQ_MMP2_MUX_BASE; irq++) {
-                icu_mask_irq(irq_get_irq_data(irq));
-                irq_set_chip(irq, &icu_irq_chip);
-                set_irq_flags(irq, IRQF_VALID);
-                switch (irq) {
-                case IRQ_MMP2_PMIC_MUX:
-                case IRQ_MMP2_RTC_MUX:
-                case IRQ_MMP2_TWSI_MUX:
-                case IRQ_MMP2_MISC_MUX:
-                case IRQ_MMP2_SSP_MUX:
-                        break;
-                default:
-                        irq_set_handler(irq, handle_level_irq);
-                        break;
-                }
-        }
-        /* NOTE: IRQ_MMP2_PMIC requires the PMIC MFPR register
-         * to be written to clear the interrupt
-         */
-        pmic_irq_chip.irq_ack = pmic_irq_ack;
-        init_mux_irq(&pmic_irq_chip, IRQ_MMP2_PMIC_BASE, 2);
-        init_mux_irq(&rtc_irq_chip, IRQ_MMP2_RTC_BASE, 2);
-        init_mux_irq(&twsi_irq_chip, IRQ_MMP2_TWSI_BASE, 5);
-        init_mux_irq(&misc_irq_chip, IRQ_MMP2_MISC_BASE, 15);
-        init_mux_irq(&ssp_irq_chip, IRQ_MMP2_SSP_BASE, 2);
-        irq_set_chained_handler(IRQ_MMP2_PMIC_MUX, pmic_irq_demux);
-        irq_set_chained_handler(IRQ_MMP2_RTC_MUX, rtc_irq_demux);
-        irq_set_chained_handler(IRQ_MMP2_TWSI_MUX, twsi_irq_demux);
-        irq_set_chained_handler(IRQ_MMP2_MISC_MUX, misc_irq_demux);
-        irq_set_chained_handler(IRQ_MMP2_SSP_MUX, ssp_irq_demux);
-}
diff --git a/arch/arm/mach-mmp/irq-pxa168.c b/arch/arm/mach-mmp/irq-pxa168.c
deleted file mode 100644
index 89706a0d08f1..000000000000
--- a/arch/arm/mach-mmp/irq-pxa168.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- *  linux/arch/arm/mach-mmp/irq.c
- *
- *  Generic IRQ handling, GPIO IRQ demultiplexing, etc.
- *
- *  Author:     Bin Yang <bin.yang@marvell.com>
- *  Created:    Sep 30, 2008
- *  Copyright:  Marvell International Ltd.
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License version 2 as
- *  published by the Free Software Foundation.
- */
-#include <linux/init.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <mach/regs-icu.h>
-#include "common.h"
-#define IRQ_ROUTE_TO_AP         (ICU_INT_CONF_AP_INT | ICU_INT_CONF_IRQ)
-#define PRIORITY_DEFAULT        0x1
-#define PRIORITY_NONE           0x0     /* means IRQ disabled */
-static void icu_mask_irq(struct irq_data *d)
-{
-        __raw_writel(PRIORITY_NONE, ICU_INT_CONF(d->irq));
-}
-static void icu_unmask_irq(struct irq_data *d)
-{
-        __raw_writel(IRQ_ROUTE_TO_AP | PRIORITY_DEFAULT, ICU_INT_CONF(d->irq));
-}
-static struct irq_chip icu_irq_chip = {
-        .name           = "icu_irq",
-        .irq_ack        = icu_mask_irq,
-        .irq_mask       = icu_mask_irq,
-        .irq_unmask     = icu_unmask_irq,
-};
-void __init icu_init_irq(void)
-{
-        int irq;
-        for (irq = 0; irq < 64; irq++) {
-                icu_mask_irq(irq_get_irq_data(irq));
-                irq_set_chip_and_handler(irq, &icu_irq_chip, handle_level_irq);
-                set_irq_flags(irq, IRQF_VALID);
-        }
-}
diff --git a/arch/arm/mach-mmp/irq.c b/arch/arm/mach-mmp/irq.c
new file mode 100644
index 000000000000..fcfe0e3bd701
--- /dev/null
+++ b/arch/arm/mach-mmp/irq.c
@@ -0,0 +1,458 @@
+/*
+ *  linux/arch/arm/mach-mmp/irq.c
+ *
+ *  Generic IRQ handling, GPIO IRQ demultiplexing, etc.
+ *  Copyright (C) 2008 - 2012 Marvell Technology Group Ltd.
+ *
+ *  Author:     Bin Yang <bin.yang@marvell.com>
+ *              Haojian Zhuang <haojian.zhuang@gmail.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <mach/irqs.h>
+#ifdef CONFIG_CPU_MMP2
+#include <mach/pm-mmp2.h>
+#endif
+#ifdef CONFIG_CPU_PXA910
+#include <mach/pm-pxa910.h>
+#endif
+#include "common.h"
+#define MAX_ICU_NR              16
+struct icu_chip_data {
+        int                     nr_irqs;
+        unsigned int            virq_base;
+        unsigned int            cascade_irq;
+        void __iomem            *reg_status;
+        void __iomem            *reg_mask;
+        unsigned int            conf_enable;
+        unsigned int            conf_disable;
+        unsigned int            conf_mask;
+        unsigned int            clr_mfp_irq_base;
+        unsigned int            clr_mfp_hwirq;
+        struct irq_domain       *domain;
+};
+struct mmp_intc_conf {
+        unsigned int    conf_enable;
+        unsigned int    conf_disable;
+        unsigned int    conf_mask;
+};
+void __iomem *mmp_icu_base;
+static struct icu_chip_data icu_data[MAX_ICU_NR];
+static int max_icu_nr;
+extern void mmp2_clear_pmic_int(void);
+static void icu_mask_ack_irq(struct irq_data *d)
+{
+        struct irq_domain *domain = d->domain;
+        struct icu_chip_data *data = (struct icu_chip_data *)domain->host_data;
+        int hwirq;
+        u32 r;
+        hwirq = d->irq - data->virq_base;
+        if (data == &icu_data[0]) {
+                r = readl_relaxed(mmp_icu_base + (hwirq << 2));
+                r &= ~data->conf_mask;
+                r |= data->conf_disable;
+                writel_relaxed(r, mmp_icu_base + (hwirq << 2));
+        } else {
+#ifdef CONFIG_CPU_MMP2
+                if ((data->virq_base == data->clr_mfp_irq_base)
+                        && (hwirq == data->clr_mfp_hwirq))
+                        mmp2_clear_pmic_int();
+#endif
+                r = readl_relaxed(data->reg_mask) | (1 << hwirq);
+                writel_relaxed(r, data->reg_mask);
+        }
+}
+static void icu_mask_irq(struct irq_data *d)
+{
+        struct irq_domain *domain = d->domain;
+        struct icu_chip_data *data = (struct icu_chip_data *)domain->host_data;
+        int hwirq;
+        u32 r;
+        hwirq = d->irq - data->virq_base;
+        if (data == &icu_data[0]) {
+                r = readl_relaxed(mmp_icu_base + (hwirq << 2));
+                r &= ~data->conf_mask;
+                r |= data->conf_disable;
+                writel_relaxed(r, mmp_icu_base + (hwirq << 2));
+        } else {
+                r = readl_relaxed(data->reg_mask) | (1 << hwirq);
+                writel_relaxed(r, data->reg_mask);
+        }
+}
+static void icu_unmask_irq(struct irq_data *d)
+{
+        struct irq_domain *domain = d->domain;
+        struct icu_chip_data *data = (struct icu_chip_data *)domain->host_data;
+        int hwirq;
+        u32 r;
+        hwirq = d->irq - data->virq_base;
+        if (data == &icu_data[0]) {
+                r = readl_relaxed(mmp_icu_base + (hwirq << 2));
+                r &= ~data->conf_mask;
+                r |= data->conf_enable;
+                writel_relaxed(r, mmp_icu_base + (hwirq << 2));
+        } else {
+                r = readl_relaxed(data->reg_mask) & ~(1 << hwirq);
+                writel_relaxed(r, data->reg_mask);
+        }
+}
+static struct irq_chip icu_irq_chip = {
+        .name           = "icu_irq",
+        .irq_mask       = icu_mask_irq,
+        .irq_mask_ack   = icu_mask_ack_irq,
+        .irq_unmask     = icu_unmask_irq,
+};
+static void icu_mux_irq_demux(unsigned int irq, struct irq_desc *desc)
+{
+        struct irq_domain *domain;
+        struct icu_chip_data *data;
+        int i;
+        unsigned long mask, status, n;
+        for (i = 1; i < max_icu_nr; i++) {
+                if (irq == icu_data[i].cascade_irq) {
+                        domain = icu_data[i].domain;
+                        data = (struct icu_chip_data *)domain->host_data;
+                        break;
+                }
+        }
+        if (i >= max_icu_nr) {
+                pr_err("Spurious irq %d in MMP INTC\n", irq);
+                return;
+        }
+        mask = readl_relaxed(data->reg_mask);
+        while (1) {
+                status = readl_relaxed(data->reg_status) & ~mask;
+                if (status == 0)
+                        break;
+                n = find_first_bit(&status, BITS_PER_LONG);
+                while (n < BITS_PER_LONG) {
+                        generic_handle_irq(icu_data[i].virq_base + n);
+                        n = find_next_bit(&status, BITS_PER_LONG, n + 1);
+                }
+        }
+}
+static int mmp_irq_domain_map(struct irq_domain *d, unsigned int irq,
+                              irq_hw_number_t hw)
+{
+        irq_set_chip_and_handler(irq, &icu_irq_chip, handle_level_irq);
+        set_irq_flags(irq, IRQF_VALID);
+        return 0;
+}
+static int mmp_irq_domain_xlate(struct irq_domain *d, struct device_node *node,
+                                const u32 *intspec, unsigned int intsize,
+                                unsigned long *out_hwirq,
+                                unsigned int *out_type)
+{
+        *out_hwirq = intspec[0];
+        return 0;
+}
+const struct irq_domain_ops mmp_irq_domain_ops = {
+        .map            = mmp_irq_domain_map,
+        .xlate          = mmp_irq_domain_xlate,
+};
+static struct mmp_intc_conf mmp_conf = {
+        .conf_enable    = 0x51,
+        .conf_disable   = 0x0,
+        .conf_mask      = 0x7f,
+};
+static struct mmp_intc_conf mmp2_conf = {
+        .conf_enable    = 0x20,
+        .conf_disable   = 0x0,
+        .conf_mask      = 0x7f,
+};
+/* MMP (ARMv5) */
+void __init icu_init_irq(void)
+{
+        int irq;
+        max_icu_nr = 1;
+        mmp_icu_base = ioremap(0xd4282000, 0x1000);
+        icu_data[0].conf_enable = mmp_conf.conf_enable;
+        icu_data[0].conf_disable = mmp_conf.conf_disable;
+        icu_data[0].conf_mask = mmp_conf.conf_mask;
+        icu_data[0].nr_irqs = 64;
+        icu_data[0].virq_base = 0;
+        icu_data[0].domain = irq_domain_add_legacy(NULL, 64, 0, 0,
+                                                   &irq_domain_simple_ops,
+                                                   &icu_data[0]);
+        for (irq = 0; irq < 64; irq++) {
+                icu_mask_irq(irq_get_irq_data(irq));
+                irq_set_chip_and_handler(irq, &icu_irq_chip, handle_level_irq);
+                set_irq_flags(irq, IRQF_VALID);
+        }
+        irq_set_default_host(icu_data[0].domain);
+#ifdef CONFIG_CPU_PXA910
+        icu_irq_chip.irq_set_wake = pxa910_set_wake;
+#endif
+}
+/* MMP2 (ARMv7) */
+void __init mmp2_init_icu(void)
+{
+        int irq;
+        max_icu_nr = 8;
+        mmp_icu_base = ioremap(0xd4282000, 0x1000);
+        icu_data[0].conf_enable = mmp2_conf.conf_enable;
+        icu_data[0].conf_disable = mmp2_conf.conf_disable;
+        icu_data[0].conf_mask = mmp2_conf.conf_mask;
+        icu_data[0].nr_irqs = 64;
+        icu_data[0].virq_base = 0;
+        icu_data[0].domain = irq_domain_add_legacy(NULL, 64, 0, 0,
+                                                   &irq_domain_simple_ops,
+                                                   &icu_data[0]);
+        icu_data[1].reg_status = mmp_icu_base + 0x150;
+        icu_data[1].reg_mask = mmp_icu_base + 0x168;
+        icu_data[1].clr_mfp_irq_base = IRQ_MMP2_PMIC_BASE;
+        icu_data[1].clr_mfp_hwirq = IRQ_MMP2_PMIC - IRQ_MMP2_PMIC_BASE;
+        icu_data[1].nr_irqs = 2;
+        icu_data[1].virq_base = IRQ_MMP2_PMIC_BASE;
+        icu_data[1].domain = irq_domain_add_legacy(NULL, icu_data[1].nr_irqs,
+                                                   icu_data[1].virq_base, 0,
+                                                   &irq_domain_simple_ops,
+                                                   &icu_data[1]);
+        icu_data[2].reg_status = mmp_icu_base + 0x154;
+        icu_data[2].reg_mask = mmp_icu_base + 0x16c;
+        icu_data[2].nr_irqs = 2;
+        icu_data[2].virq_base = IRQ_MMP2_RTC_BASE;
+        icu_data[2].domain = irq_domain_add_legacy(NULL, icu_data[2].nr_irqs,
+                                                   icu_data[2].virq_base, 0,
+                                                   &irq_domain_simple_ops,
+                                                   &icu_data[2]);
+        icu_data[3].reg_status = mmp_icu_base + 0x180;
+        icu_data[3].reg_mask = mmp_icu_base + 0x17c;
+        icu_data[3].nr_irqs = 3;
+        icu_data[3].virq_base = IRQ_MMP2_KEYPAD_BASE;
+        icu_data[3].domain = irq_domain_add_legacy(NULL, icu_data[3].nr_irqs,
+                                                   icu_data[3].virq_base, 0,
+                                                   &irq_domain_simple_ops,
+                                                   &icu_data[3]);
+        icu_data[4].reg_status = mmp_icu_base + 0x158;
+        icu_data[4].reg_mask = mmp_icu_base + 0x170;
+        icu_data[4].nr_irqs = 5;
+        icu_data[4].virq_base = IRQ_MMP2_TWSI_BASE;
+        icu_data[4].domain = irq_domain_add_legacy(NULL, icu_data[4].nr_irqs,
+                                                   icu_data[4].virq_base, 0,
+                                                   &irq_domain_simple_ops,
+                                                   &icu_data[4]);
+        icu_data[5].reg_status = mmp_icu_base + 0x15c;
+        icu_data[5].reg_mask = mmp_icu_base + 0x174;
+        icu_data[5].nr_irqs = 15;
+        icu_data[5].virq_base = IRQ_MMP2_MISC_BASE;
+        icu_data[5].domain = irq_domain_add_legacy(NULL, icu_data[5].nr_irqs,
+                                                   icu_data[5].virq_base, 0,
+                                                   &irq_domain_simple_ops,
+                                                   &icu_data[5]);
+        icu_data[6].reg_status = mmp_icu_base + 0x160;
+        icu_data[6].reg_mask = mmp_icu_base + 0x178;
+        icu_data[6].nr_irqs = 2;
+        icu_data[6].virq_base = IRQ_MMP2_MIPI_HSI1_BASE;
+        icu_data[6].domain = irq_domain_add_legacy(NULL, icu_data[6].nr_irqs,
+                                                   icu_data[6].virq_base, 0,
+                                                   &irq_domain_simple_ops,
+                                                   &icu_data[6]);
+        icu_data[7].reg_status = mmp_icu_base + 0x188;
+        icu_data[7].reg_mask = mmp_icu_base + 0x184;
+        icu_data[7].nr_irqs = 2;
+        icu_data[7].virq_base = IRQ_MMP2_MIPI_HSI0_BASE;
+        icu_data[7].domain = irq_domain_add_legacy(NULL, icu_data[7].nr_irqs,
+                                                   icu_data[7].virq_base, 0,
+                                                   &irq_domain_simple_ops,
+                                                   &icu_data[7]);
+        for (irq = 0; irq < IRQ_MMP2_MUX_END; irq++) {
+                icu_mask_irq(irq_get_irq_data(irq));
+                switch (irq) {
+                case IRQ_MMP2_PMIC_MUX:
+                case IRQ_MMP2_RTC_MUX:
+                case IRQ_MMP2_KEYPAD_MUX:
+                case IRQ_MMP2_TWSI_MUX:
+                case IRQ_MMP2_MISC_MUX:
+                case IRQ_MMP2_MIPI_HSI1_MUX:
+                case IRQ_MMP2_MIPI_HSI0_MUX:
+                        irq_set_chip(irq, &icu_irq_chip);
+                        irq_set_chained_handler(irq, icu_mux_irq_demux);
+                        break;
+                default:
+                        irq_set_chip_and_handler(irq, &icu_irq_chip,
+                                                 handle_level_irq);
+                        break;
+                }
+                set_irq_flags(irq, IRQF_VALID);
+        }
+        irq_set_default_host(icu_data[0].domain);
+#ifdef CONFIG_CPU_MMP2
+        icu_irq_chip.irq_set_wake = mmp2_set_wake;
+#endif
+}
+#ifdef CONFIG_OF
+static const struct of_device_id intc_ids[] __initconst = {
+        { .compatible = "mrvl,mmp-intc", .data = &mmp_conf },
+        { .compatible = "mrvl,mmp2-intc", .data = &mmp2_conf },
+        {}
+};
+static const struct of_device_id mmp_mux_irq_match[] __initconst = {
+        { .compatible = "mrvl,mmp2-mux-intc" },
+        {}
+};
+int __init mmp2_mux_init(struct device_node *parent)
+{
+        struct device_node *node;
+        const struct of_device_id *of_id;
+        struct resource res;
+        int i, irq_base, ret, irq;
+        u32 nr_irqs, mfp_irq;
+        node = parent;
+        max_icu_nr = 1;
+        for (i = 1; i < MAX_ICU_NR; i++) {
+                node = of_find_matching_node(node, mmp_mux_irq_match);
+                if (!node)
+                        break;
+                of_id = of_match_node(&mmp_mux_irq_match[0], node);
+                ret = of_property_read_u32(node, "mrvl,intc-nr-irqs",
+                                           &nr_irqs);
+                if (ret) {
+                        pr_err("Not found mrvl,intc-nr-irqs property\n");
+                        ret = -EINVAL;
+                        goto err;
+                }
+                ret = of_address_to_resource(node, 0, &res);
+                if (ret < 0) {
+                        pr_err("Not found reg property\n");
+                        ret = -EINVAL;
+                        goto err;
+                }
+                icu_data[i].reg_status = mmp_icu_base + res.start;
+                ret = of_address_to_resource(node, 1, &res);
+                if (ret < 0) {
+                        pr_err("Not found reg property\n");
+                        ret = -EINVAL;
+                        goto err;
+                }
+                icu_data[i].reg_mask = mmp_icu_base + res.start;
+                icu_data[i].cascade_irq = irq_of_parse_and_map(node, 0);
+                if (!icu_data[i].cascade_irq) {
+                        ret = -EINVAL;
+                        goto err;
+                }
+                irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0);
+                if (irq_base < 0) {
+                        pr_err("Failed to allocate IRQ numbers for mux intc\n");
+                        ret = irq_base;
+                        goto err;
+                }
+                if (!of_property_read_u32(node, "mrvl,clr-mfp-irq",
+                                          &mfp_irq)) {
+                        icu_data[i].clr_mfp_irq_base = irq_base;
+                        icu_data[i].clr_mfp_hwirq = mfp_irq;
+                }
+                irq_set_chained_handler(icu_data[i].cascade_irq,
+                                        icu_mux_irq_demux);
+                icu_data[i].nr_irqs = nr_irqs;
+                icu_data[i].virq_base = irq_base;
+                icu_data[i].domain = irq_domain_add_legacy(node, nr_irqs,
+                                                           irq_base, 0,
+                                                           &mmp_irq_domain_ops,
+                                                           &icu_data[i]);
+                for (irq = irq_base; irq < irq_base + nr_irqs; irq++)
+                        icu_mask_irq(irq_get_irq_data(irq));
+        }
+        max_icu_nr = i;
+        return 0;
+err:
+        of_node_put(node);
+        max_icu_nr = i;
+        return ret;
+}
+void __init mmp_dt_irq_init(void)
+{
+        struct device_node *node;
+        const struct of_device_id *of_id;
+        struct mmp_intc_conf *conf;
+        int nr_irqs, irq_base, ret, irq;
+        node = of_find_matching_node(NULL, intc_ids);
+        if (!node) {
+                pr_err("Failed to find interrupt controller in arch-mmp\n");
+                return;
+        }
+        of_id = of_match_node(intc_ids, node);
+        conf = of_id->data;
+        ret = of_property_read_u32(node, "mrvl,intc-nr-irqs", &nr_irqs);
+        if (ret) {
+                pr_err("Not found mrvl,intc-nr-irqs property\n");
+                return;
+        }
+        mmp_icu_base = of_iomap(node, 0);
+        if (!mmp_icu_base) {
+                pr_err("Failed to get interrupt controller register\n");
+                return;
+        }
+        irq_base = irq_alloc_descs(-1, 0, nr_irqs - NR_IRQS_LEGACY, 0);
+        if (irq_base < 0) {
+                pr_err("Failed to allocate IRQ numbers\n");
+                goto err;
+        } else if (irq_base != NR_IRQS_LEGACY) {
+                pr_err("ICU's irqbase should be started from 0\n");
+                goto err;
+        }
+        icu_data[0].conf_enable = conf->conf_enable;
+        icu_data[0].conf_disable = conf->conf_disable;
+        icu_data[0].conf_mask = conf->conf_mask;
+        icu_data[0].nr_irqs = nr_irqs;
+        icu_data[0].virq_base = 0;
+        icu_data[0].domain = irq_domain_add_legacy(node, nr_irqs, 0, 0,
+                                                   &mmp_irq_domain_ops,
+                                                   &icu_data[0]);
+        irq_set_default_host(icu_data[0].domain);
+        for (irq = 0; irq < nr_irqs; irq++)
+                icu_mask_irq(irq_get_irq_data(irq));
+        mmp2_mux_init(node);
+        return;
+err:
+        iounmap(mmp_icu_base);
+}
+#endif
diff --git a/arch/arm/mach-mmp/mmp-dt.c b/arch/arm/mach-mmp/mmp-dt.c
index 67075395e400..033cc31b3c72 100644
--- a/arch/arm/mach-mmp/mmp-dt.c
+++ b/arch/arm/mach-mmp/mmp-dt.c
@@ -14,14 +14,19 @@
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <asm/mach/arch.h>
+#include <asm/mach/time.h>
 #include <mach/irqs.h>
 #include "common.h"
-extern struct sys_timer pxa168_timer;
+extern void __init mmp_dt_irq_init(void);
-extern void __init icu_init_irq(void);
+extern void __init mmp_dt_init_timer(void);
-static const struct of_dev_auxdata mmp_auxdata_lookup[] __initconst = {
+static struct sys_timer mmp_dt_timer = {
+        .init   = mmp_dt_init_timer,
+};
+static const struct of_dev_auxdata pxa168_auxdata_lookup[] __initconst = {
        OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4017000, "pxa2xx-uart.0", NULL),
        OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4018000, "pxa2xx-uart.1", NULL),
        OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4026000, "pxa2xx-uart.2", NULL),
@@ -32,44 +37,47 @@ static const struct of_dev_auxdata mmp_auxdata_lookup[] __initconst = {
        {}
 };
-static int __init mmp_intc_add_irq_domain(struct device_node *np,
+static const struct of_dev_auxdata pxa910_auxdata_lookup[] __initconst = {
-                                           struct device_node *parent)
+        OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4017000, "pxa2xx-uart.0", NULL),
-{
+        OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4018000, "pxa2xx-uart.1", NULL),
-        irq_domain_add_simple(np, 0);
+        OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4036000, "pxa2xx-uart.2", NULL),
-        return 0;
+        OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4011000, "pxa2xx-i2c.0", NULL),
-}
+        OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4037000, "pxa2xx-i2c.1", NULL),
+        OF_DEV_AUXDATA("mrvl,mmp-gpio", 0xd4019000, "pxa-gpio", NULL),
-static int __init mmp_gpio_add_irq_domain(struct device_node *np,
+        OF_DEV_AUXDATA("mrvl,mmp-rtc", 0xd4010000, "sa1100-rtc", NULL),
-                                           struct device_node *parent)
-{
-        irq_domain_add_simple(np, IRQ_GPIO_START);
-        return 0;
-}
-static const struct of_device_id mmp_irq_match[] __initconst = {
-        { .compatible = "mrvl,mmp-intc", .data = mmp_intc_add_irq_domain, },
-        { .compatible = "mrvl,mmp-gpio", .data = mmp_gpio_add_irq_domain, },
        {}
 };
-static void __init mmp_dt_init(void)
+static void __init pxa168_dt_init(void)
 {
+        of_platform_populate(NULL, of_default_bus_match_table,
+                             pxa168_auxdata_lookup, NULL);
+}
-        of_irq_init(mmp_irq_match);
+static void __init pxa910_dt_init(void)
+{
        of_platform_populate(NULL, of_default_bus_match_table,
-                             mmp_auxdata_lookup, NULL);
+                             pxa910_auxdata_lookup, NULL);
 }
-static const char *pxa168_dt_board_compat[] __initdata = {
+static const char *mmp_dt_board_compat[] __initdata = {
        "mrvl,pxa168-aspenite",
+        "mrvl,pxa910-dkb",
        NULL,
 };
 DT_MACHINE_START(PXA168_DT, "Marvell PXA168 (Device Tree Support)")
        .map_io         = mmp_map_io,
-        .init_irq       = icu_init_irq,
+        .init_irq       = mmp_dt_irq_init,
-        .timer          = &pxa168_timer,
+        .timer          = &mmp_dt_timer,
-        .init_machine   = mmp_dt_init,
+        .init_machine   = pxa168_dt_init,
-        .dt_compat      = pxa168_dt_board_compat,
+        .dt_compat      = mmp_dt_board_compat,
+MACHINE_END
+DT_MACHINE_START(PXA910_DT, "Marvell PXA910 (Device Tree Support)")
+        .map_io         = mmp_map_io,
+        .init_irq       = mmp_dt_irq_init,
+        .timer          = &mmp_dt_timer,
+        .init_machine   = pxa910_dt_init,
+        .dt_compat      = mmp_dt_board_compat,
 MACHINE_END
diff --git a/arch/arm/mach-mmp/mmp2-dt.c b/arch/arm/mach-mmp/mmp2-dt.c
new file mode 100644
index 000000000000..535a5ed5977b
--- /dev/null
+++ b/arch/arm/mach-mmp/mmp2-dt.c
@@ -0,0 +1,60 @@
+/*
+ *  linux/arch/arm/mach-mmp/mmp2-dt.c
+ *
+ *  Copyright (C) 2012 Marvell Technology Group Ltd.
+ *  Author: Haojian Zhuang <haojian.zhuang@marvell.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <mach/irqs.h>
+#include <mach/regs-apbc.h>
+#include "common.h"
+extern void __init mmp_dt_irq_init(void);
+extern void __init mmp_dt_init_timer(void);
+static struct sys_timer mmp_dt_timer = {
+        .init   = mmp_dt_init_timer,
+};
+static const struct of_dev_auxdata mmp2_auxdata_lookup[] __initconst = {
+        OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4030000, "pxa2xx-uart.0", NULL),
+        OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4017000, "pxa2xx-uart.1", NULL),
+        OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4018000, "pxa2xx-uart.2", NULL),
+        OF_DEV_AUXDATA("mrvl,mmp-uart", 0xd4016000, "pxa2xx-uart.3", NULL),
+        OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4011000, "pxa2xx-i2c.0", NULL),
+        OF_DEV_AUXDATA("mrvl,mmp-twsi", 0xd4025000, "pxa2xx-i2c.1", NULL),
+        OF_DEV_AUXDATA("mrvl,mmp-gpio", 0xd4019000, "pxa-gpio", NULL),
+        OF_DEV_AUXDATA("mrvl,mmp-rtc", 0xd4010000, "sa1100-rtc", NULL),
+        {}
+};
+static void __init mmp2_dt_init(void)
+{
+        of_platform_populate(NULL, of_default_bus_match_table,
+                             mmp2_auxdata_lookup, NULL);
+}
+static const char *mmp2_dt_board_compat[] __initdata = {
+        "mrvl,mmp2-brownstone",
+        NULL,
+};
+DT_MACHINE_START(MMP2_DT, "Marvell MMP2 (Device Tree Support)")
+        .map_io         = mmp_map_io,
+        .init_irq       = mmp_dt_irq_init,
+        .timer          = &mmp_dt_timer,
+        .init_machine   = mmp2_dt_init,
+        .dt_compat      = mmp2_dt_board_compat,
+MACHINE_END
diff --git a/arch/arm/mach-mmp/pm-mmp2.c b/arch/arm/mach-mmp/pm-mmp2.c
new file mode 100644
index 000000000000..461a191a32d2
--- /dev/null
+++ b/arch/arm/mach-mmp/pm-mmp2.c
@@ -0,0 +1,264 @@
+/*
+ * MMP2 Power Management Routines
+ *
+ * This software program is licensed subject to the GNU General Public License
+ * (GPL).Version 2,June 1991, available at http://www.fsf.org/copyleft/gpl.html
+ *
+ * (C) Copyright 2012 Marvell International Ltd.
+ * All Rights Reserved
+ */
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/time.h>
+#include <linux/delay.h>
+#include <linux/suspend.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/interrupt.h>
+#include <asm/mach-types.h>
+#include <mach/hardware.h>
+#include <mach/cputype.h>
+#include <mach/addr-map.h>
+#include <mach/pm-mmp2.h>
+#include <mach/regs-icu.h>
+#include <mach/irqs.h>
+int mmp2_set_wake(struct irq_data *d, unsigned int on)
+{
+        int irq = d->irq;
+        struct irq_desc *desc = irq_to_desc(irq);
+        unsigned long data = 0;
+        if (unlikely(irq >= nr_irqs)) {
+                pr_err("IRQ nubmers are out of boundary!\n");
+                return -EINVAL;
+        }
+        if (on) {
+                if (desc->action)
+                        desc->action->flags |= IRQF_NO_SUSPEND;
+        } else {
+                if (desc->action)
+                        desc->action->flags &= ~IRQF_NO_SUSPEND;
+        }
+        /* enable wakeup sources */
+        switch (irq) {
+        case IRQ_MMP2_RTC:
+        case IRQ_MMP2_RTC_ALARM:
+                data = MPMU_WUCRM_PJ_WAKEUP(4) | MPMU_WUCRM_PJ_RTC_ALARM;
+                break;
+        case IRQ_MMP2_PMIC:
+                data = MPMU_WUCRM_PJ_WAKEUP(7);
+                break;
+        case IRQ_MMP2_MMC2:
+                /* mmc use WAKEUP2, same as GPIO wakeup source */
+                data = MPMU_WUCRM_PJ_WAKEUP(2);
+                break;
+        }
+        if (on) {
+                if (data) {
+                        data |= __raw_readl(MPMU_WUCRM_PJ);
+                        __raw_writel(data, MPMU_WUCRM_PJ);
+                }
+        } else {
+                if (data) {
+                        data = ~data & __raw_readl(MPMU_WUCRM_PJ);
+                        __raw_writel(data, MPMU_WUCRM_PJ);
+                }
+        }
+        return 0;
+}
+static void pm_scu_clk_disable(void)
+{
+        unsigned int val;
+        /* close AXI fabric clock gate */
+        __raw_writel(0x0, CIU_REG(0x64));
+        __raw_writel(0x0, CIU_REG(0x68));
+        /* close MCB master clock gate */
+        val = __raw_readl(CIU_REG(0x1c));
+        val |= 0xf0;
+        __raw_writel(val, CIU_REG(0x1c));
+        return ;
+}
+static void pm_scu_clk_enable(void)
+{
+        unsigned int val;
+        /* open AXI fabric clock gate */
+        __raw_writel(0x03003003, CIU_REG(0x64));
+        __raw_writel(0x00303030, CIU_REG(0x68));
+        /* open MCB master clock gate */
+        val = __raw_readl(CIU_REG(0x1c));
+        val &= ~(0xf0);
+        __raw_writel(val, CIU_REG(0x1c));
+        return ;
+}
+static void pm_mpmu_clk_disable(void)
+{
+        /*
+         * disable clocks in MPMU_CGR_PJ register
+         * except clock for APMU_PLL1, APMU_PLL1_2 and AP_26M
+         */
+        __raw_writel(0x0000a010, MPMU_CGR_PJ);
+}
+static void pm_mpmu_clk_enable(void)
+{
+        unsigned int val;
+        __raw_writel(0xdffefffe, MPMU_CGR_PJ);
+        val = __raw_readl(MPMU_PLL2_CTRL1);
+        val |= (1 << 29);
+        __raw_writel(val, MPMU_PLL2_CTRL1);
+        return ;
+}
+void mmp2_pm_enter_lowpower_mode(int state)
+{
+        uint32_t idle_cfg, apcr;
+        idle_cfg = __raw_readl(APMU_PJ_IDLE_CFG);
+        apcr = __raw_readl(MPMU_PCR_PJ);
+        apcr &= ~(MPMU_PCR_PJ_SLPEN | MPMU_PCR_PJ_DDRCORSD | MPMU_PCR_PJ_APBSD
+                 | MPMU_PCR_PJ_AXISD | MPMU_PCR_PJ_VCTCXOSD | (1 << 13));
+        idle_cfg &= ~APMU_PJ_IDLE_CFG_PJ_IDLE;
+        switch (state) {
+        case POWER_MODE_SYS_SLEEP:
+                apcr |= MPMU_PCR_PJ_SLPEN;              /* set the SLPEN bit */
+                apcr |= MPMU_PCR_PJ_VCTCXOSD;           /* set VCTCXOSD */
+                /* fall through */
+        case POWER_MODE_CHIP_SLEEP:
+                apcr |= MPMU_PCR_PJ_SLPEN;
+                /* fall through */
+        case POWER_MODE_APPS_SLEEP:
+                apcr |= MPMU_PCR_PJ_APBSD;              /* set APBSD */
+                /* fall through */
+        case POWER_MODE_APPS_IDLE:
+                apcr |= MPMU_PCR_PJ_AXISD;              /* set AXISDD bit */
+                apcr |= MPMU_PCR_PJ_DDRCORSD;           /* set DDRCORSD bit */
+                idle_cfg |= APMU_PJ_IDLE_CFG_PJ_PWRDWN; /* PJ power down */
+                apcr |= MPMU_PCR_PJ_SPSD;
+                /* fall through */
+        case POWER_MODE_CORE_EXTIDLE:
+                idle_cfg |= APMU_PJ_IDLE_CFG_PJ_IDLE;   /* set the IDLE bit */
+                idle_cfg &= ~APMU_PJ_IDLE_CFG_ISO_MODE_CNTRL_MASK;
+                idle_cfg |= APMU_PJ_IDLE_CFG_PWR_SW(3)
+                        | APMU_PJ_IDLE_CFG_L2_PWR_SW;
+                break;
+        case POWER_MODE_CORE_INTIDLE:
+                apcr &= ~MPMU_PCR_PJ_SPSD;
+                break;
+        }
+        /* set reserve bits */
+        apcr |= (1 << 30) | (1 << 25);
+        /* finally write the registers back */
+        __raw_writel(idle_cfg, APMU_PJ_IDLE_CFG);
+        __raw_writel(apcr, MPMU_PCR_PJ);        /* 0xfe086000 */
+}
+static int mmp2_pm_enter(suspend_state_t state)
+{
+        int temp;
+        temp = __raw_readl(MMP2_ICU_INT4_MASK);
+        if (temp & (1 << 1)) {
+                printk(KERN_ERR "%s: PMIC interrupt is handling\n", __func__);
+                return -EAGAIN;
+        }
+        temp = __raw_readl(APMU_SRAM_PWR_DWN);
+        temp |= ((1 << 19) | (1 << 18));
+        __raw_writel(temp, APMU_SRAM_PWR_DWN);
+        pm_mpmu_clk_disable();
+        pm_scu_clk_disable();
+        printk(KERN_INFO "%s: before suspend\n", __func__);
+        cpu_do_idle();
+        printk(KERN_INFO "%s: after suspend\n", __func__);
+        pm_mpmu_clk_enable();           /* enable clocks in MPMU */
+        pm_scu_clk_enable();            /* enable clocks in SCU */
+        return 0;
+}
+/*
+ * Called after processes are frozen, but before we shut down devices.
+ */
+static int mmp2_pm_prepare(void)
+{
+        mmp2_pm_enter_lowpower_mode(POWER_MODE_SYS_SLEEP);
+        return 0;
+}
+/*
+ * Called after devices are re-setup, but before processes are thawed.
+ */
+static void mmp2_pm_finish(void)
+{
+        mmp2_pm_enter_lowpower_mode(POWER_MODE_CORE_INTIDLE);
+}
+static int mmp2_pm_valid(suspend_state_t state)
+{
+        return ((state == PM_SUSPEND_STANDBY) || (state == PM_SUSPEND_MEM));
+}
+/*
+ * Set to PM_DISK_FIRMWARE so we can quickly veto suspend-to-disk.
+ */
+static const struct platform_suspend_ops mmp2_pm_ops = {
+        .valid          = mmp2_pm_valid,
+        .prepare        = mmp2_pm_prepare,
+        .enter          = mmp2_pm_enter,
+        .finish         = mmp2_pm_finish,
+};
+static int __init mmp2_pm_init(void)
+{
+        uint32_t apcr;
+        if (!cpu_is_mmp2())
+                return -EIO;
+        suspend_set_ops(&mmp2_pm_ops);
+        /*
+         * Set bit 0, Slow clock Select 32K clock input instead of VCXO
+         * VCXO is chosen by default, which would be disabled in suspend
+         */
+        __raw_writel(0x5, MPMU_SCCR);
+        /*
+         * Clear bit 23 of CIU_CPU_CONF
+         * direct PJ4 to DDR access through Memory Controller slow queue
+         * fast queue has issue and cause lcd will flick
+         */
+        __raw_writel(__raw_readl(CIU_REG(0x8)) & ~(0x1 << 23), CIU_REG(0x8));
+        /* Clear default low power control bit */
+        apcr = __raw_readl(MPMU_PCR_PJ);
+        apcr &= ~(MPMU_PCR_PJ_SLPEN | MPMU_PCR_PJ_DDRCORSD
+                        | MPMU_PCR_PJ_APBSD | MPMU_PCR_PJ_AXISD | 1 << 13);
+        __raw_writel(apcr, MPMU_PCR_PJ);
+        return 0;
+}
+late_initcall(mmp2_pm_init);
diff --git a/arch/arm/mach-mmp/pm-pxa910.c b/arch/arm/mach-mmp/pm-pxa910.c
new file mode 100644
index 000000000000..48981ca801a5
--- /dev/null
+++ b/arch/arm/mach-mmp/pm-pxa910.c
@@ -0,0 +1,285 @@
+/*
+ * PXA910 Power Management Routines
+ *
+ * This software program is licensed subject to the GNU General Public License
+ * (GPL).Version 2,June 1991, available at http://www.fsf.org/copyleft/gpl.html
+ *
+ * (C) Copyright 2009 Marvell International Ltd.
+ * All Rights Reserved
+ */
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/time.h>
+#include <linux/delay.h>
+#include <linux/suspend.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <asm/mach-types.h>
+#include <mach/hardware.h>
+#include <mach/cputype.h>
+#include <mach/addr-map.h>
+#include <mach/pm-pxa910.h>
+#include <mach/regs-icu.h>
+#include <mach/irqs.h>
+int pxa910_set_wake(struct irq_data *data, unsigned int on)
+{
+        int irq = data->irq;
+        struct irq_desc *desc = irq_to_desc(data->irq);
+        uint32_t awucrm = 0, apcr = 0;
+        if (unlikely(irq >= nr_irqs)) {
+                pr_err("IRQ nubmers are out of boundary!\n");
+                return -EINVAL;
+        }
+        if (on) {
+                if (desc->action)
+                        desc->action->flags |= IRQF_NO_SUSPEND;
+        } else {
+                if (desc->action)
+                        desc->action->flags &= ~IRQF_NO_SUSPEND;
+        }
+        /* setting wakeup sources */
+        switch (irq) {
+        /* wakeup line 2 */
+        case IRQ_PXA910_AP_GPIO:
+                awucrm = MPMU_AWUCRM_WAKEUP(2);
+                apcr |= MPMU_APCR_SLPWP2;
+                break;
+        /* wakeup line 3 */
+        case IRQ_PXA910_KEYPAD:
+                awucrm = MPMU_AWUCRM_WAKEUP(3) | MPMU_AWUCRM_KEYPRESS;
+                apcr |= MPMU_APCR_SLPWP3;
+                break;
+        case IRQ_PXA910_ROTARY:
+                awucrm = MPMU_AWUCRM_WAKEUP(3) | MPMU_AWUCRM_NEWROTARY;
+                apcr |= MPMU_APCR_SLPWP3;
+                break;
+        case IRQ_PXA910_TRACKBALL:
+                awucrm = MPMU_AWUCRM_WAKEUP(3) | MPMU_AWUCRM_TRACKBALL;
+                apcr |= MPMU_APCR_SLPWP3;
+                break;
+        /* wakeup line 4 */
+        case IRQ_PXA910_AP1_TIMER1:
+                awucrm = MPMU_AWUCRM_WAKEUP(4) | MPMU_AWUCRM_AP1_TIMER_1;
+                apcr |= MPMU_APCR_SLPWP4;
+                break;
+        case IRQ_PXA910_AP1_TIMER2:
+                awucrm = MPMU_AWUCRM_WAKEUP(4) | MPMU_AWUCRM_AP1_TIMER_2;
+                apcr |= MPMU_APCR_SLPWP4;
+                break;
+        case IRQ_PXA910_AP1_TIMER3:
+                awucrm = MPMU_AWUCRM_WAKEUP(4) | MPMU_AWUCRM_AP1_TIMER_3;
+                apcr |= MPMU_APCR_SLPWP4;
+                break;
+        case IRQ_PXA910_AP2_TIMER1:
+                awucrm = MPMU_AWUCRM_WAKEUP(4) | MPMU_AWUCRM_AP2_TIMER_1;
+                apcr |= MPMU_APCR_SLPWP4;
+                break;
+        case IRQ_PXA910_AP2_TIMER2:
+                awucrm = MPMU_AWUCRM_WAKEUP(4) | MPMU_AWUCRM_AP2_TIMER_2;
+                apcr |= MPMU_APCR_SLPWP4;
+                break;
+        case IRQ_PXA910_AP2_TIMER3:
+                awucrm = MPMU_AWUCRM_WAKEUP(4) | MPMU_AWUCRM_AP2_TIMER_3;
+                apcr |= MPMU_APCR_SLPWP4;
+                break;
+        case IRQ_PXA910_RTC_ALARM:
+                awucrm = MPMU_AWUCRM_WAKEUP(4) | MPMU_AWUCRM_RTC_ALARM;
+                apcr |= MPMU_APCR_SLPWP4;
+                break;
+        /* wakeup line 5 */
+        case IRQ_PXA910_USB1:
+        case IRQ_PXA910_USB2:
+                awucrm = MPMU_AWUCRM_WAKEUP(5);
+                apcr |= MPMU_APCR_SLPWP5;
+                break;
+        /* wakeup line 6 */
+        case IRQ_PXA910_MMC:
+                awucrm = MPMU_AWUCRM_WAKEUP(6)
+                        | MPMU_AWUCRM_SDH1
+                        | MPMU_AWUCRM_SDH2;
+                apcr |= MPMU_APCR_SLPWP6;
+                break;
+        /* wakeup line 7 */
+        case IRQ_PXA910_PMIC_INT:
+                awucrm = MPMU_AWUCRM_WAKEUP(7);
+                apcr |= MPMU_APCR_SLPWP7;
+                break;
+        default:
+                if (irq >= IRQ_GPIO_START && irq < IRQ_BOARD_START) {
+                        awucrm = MPMU_AWUCRM_WAKEUP(2);
+                        apcr |= MPMU_APCR_SLPWP2;
+                } else
+                        printk(KERN_ERR "Error: no defined wake up source irq: %d\n",
+                                irq);
+        }
+        if (on) {
+                if (awucrm) {
+                        awucrm |= __raw_readl(MPMU_AWUCRM);
+                        __raw_writel(awucrm, MPMU_AWUCRM);
+                }
+                if (apcr) {
+                        apcr = ~apcr & __raw_readl(MPMU_APCR);
+                        __raw_writel(apcr, MPMU_APCR);
+                }
+        } else {
+                if (awucrm) {
+                        awucrm = ~awucrm & __raw_readl(MPMU_AWUCRM);
+                        __raw_writel(awucrm, MPMU_AWUCRM);
+                }
+                if (apcr) {
+                        apcr |= __raw_readl(MPMU_APCR);
+                        __raw_writel(apcr, MPMU_APCR);
+                }
+        }
+        return 0;
+}
+void pxa910_pm_enter_lowpower_mode(int state)
+{
+        uint32_t idle_cfg, apcr;
+        idle_cfg = __raw_readl(APMU_MOH_IDLE_CFG);
+        apcr = __raw_readl(MPMU_APCR);
+        apcr &= ~(MPMU_APCR_DDRCORSD | MPMU_APCR_APBSD | MPMU_APCR_AXISD
+                | MPMU_APCR_VCTCXOSD | MPMU_APCR_STBYEN);
+        idle_cfg &= ~(APMU_MOH_IDLE_CFG_MOH_IDLE
+                | APMU_MOH_IDLE_CFG_MOH_PWRDWN);
+        switch (state) {
+        case POWER_MODE_UDR:
+                /* only shutdown APB in UDR */
+                apcr |= MPMU_APCR_STBYEN | MPMU_APCR_APBSD;
+                /* fall through */
+        case POWER_MODE_SYS_SLEEP:
+                apcr |= MPMU_APCR_SLPEN;                /* set the SLPEN bit */
+                apcr |= MPMU_APCR_VCTCXOSD;             /* set VCTCXOSD */
+                /* fall through */
+        case POWER_MODE_APPS_SLEEP:
+                apcr |= MPMU_APCR_DDRCORSD;             /* set DDRCORSD */
+                /* fall through */
+        case POWER_MODE_APPS_IDLE:
+                apcr |= MPMU_APCR_AXISD;                /* set AXISDD bit */
+                /* fall through */
+        case POWER_MODE_CORE_EXTIDLE:
+                idle_cfg |= APMU_MOH_IDLE_CFG_MOH_IDLE;
+                idle_cfg |= APMU_MOH_IDLE_CFG_MOH_PWRDWN;
+                idle_cfg |= APMU_MOH_IDLE_CFG_MOH_PWR_SW(3)
+                        | APMU_MOH_IDLE_CFG_MOH_L2_PWR_SW(3);
+                /* fall through */
+        case POWER_MODE_CORE_INTIDLE:
+                break;
+        }
+        /* program the memory controller hardware sleep type and auto wakeup */
+        idle_cfg |= APMU_MOH_IDLE_CFG_MOH_DIS_MC_SW_REQ;
+        idle_cfg |= APMU_MOH_IDLE_CFG_MOH_MC_WAKE_EN;
+        __raw_writel(0x0, APMU_MC_HW_SLP_TYPE);         /* auto refresh */
+        /* set DSPSD, DTCMSD, BBSD, MSASLPEN */
+        apcr |= MPMU_APCR_DSPSD | MPMU_APCR_DTCMSD | MPMU_APCR_BBSD
+                | MPMU_APCR_MSASLPEN;
+        /*always set SLEPEN bit mainly for MSA*/
+        apcr |= MPMU_APCR_SLPEN;
+        /* finally write the registers back */
+        __raw_writel(idle_cfg, APMU_MOH_IDLE_CFG);
+        __raw_writel(apcr, MPMU_APCR);
+}
+static int pxa910_pm_enter(suspend_state_t state)
+{
+        unsigned int idle_cfg, reg = 0;
+        /*pmic thread not completed,exit;otherwise system can't be waked up*/
+        reg = __raw_readl(ICU_INT_CONF(IRQ_PXA910_PMIC_INT));
+        if ((reg & 0x3) == 0)
+                return -EAGAIN;
+        idle_cfg = __raw_readl(APMU_MOH_IDLE_CFG);
+        idle_cfg |= APMU_MOH_IDLE_CFG_MOH_PWRDWN
+                | APMU_MOH_IDLE_CFG_MOH_SRAM_PWRDWN;
+        __raw_writel(idle_cfg, APMU_MOH_IDLE_CFG);
+        /* disable L2 */
+        outer_disable();
+        /* wait for l2 idle */
+        while (!(readl(CIU_REG(0x8)) & (1 << 16)))
+                udelay(1);
+        cpu_do_idle();
+        /* enable L2 */
+        outer_resume();
+        /* wait for l2 idle */
+        while (!(readl(CIU_REG(0x8)) & (1 << 16)))
+                udelay(1);
+        idle_cfg = __raw_readl(APMU_MOH_IDLE_CFG);
+        idle_cfg &= ~(APMU_MOH_IDLE_CFG_MOH_PWRDWN
+                | APMU_MOH_IDLE_CFG_MOH_SRAM_PWRDWN);
+        __raw_writel(idle_cfg, APMU_MOH_IDLE_CFG);
+        return 0;
+}
+/*
+ * Called after processes are frozen, but before we shut down devices.
+ */
+static int pxa910_pm_prepare(void)
+{
+        pxa910_pm_enter_lowpower_mode(POWER_MODE_UDR);
+        return 0;
+}
+/*
+ * Called after devices are re-setup, but before processes are thawed.
+ */
+static void pxa910_pm_finish(void)
+{
+        pxa910_pm_enter_lowpower_mode(POWER_MODE_CORE_INTIDLE);
+}
+static int pxa910_pm_valid(suspend_state_t state)
+{
+        return ((state == PM_SUSPEND_STANDBY) || (state == PM_SUSPEND_MEM));
+}
+static const struct platform_suspend_ops pxa910_pm_ops = {
+        .valid          = pxa910_pm_valid,
+        .prepare        = pxa910_pm_prepare,
+        .enter          = pxa910_pm_enter,
+        .finish         = pxa910_pm_finish,
+};
+static int __init pxa910_pm_init(void)
+{
+        uint32_t awucrm = 0;
+        if (!cpu_is_pxa910())
+                return -EIO;
+        suspend_set_ops(&pxa910_pm_ops);
+        /* Set the following bits for MMP3 playback with VCTXO on */
+        __raw_writel(__raw_readl(APMU_SQU_CLK_GATE_CTRL) | (1 << 30),
+                APMU_SQU_CLK_GATE_CTRL);
+        __raw_writel(__raw_readl(MPMU_FCCR) | (1 << 28), MPMU_FCCR);
+        awucrm |= MPMU_AWUCRM_AP_ASYNC_INT | MPMU_AWUCRM_AP_FULL_IDLE;
+        __raw_writel(awucrm, MPMU_AWUCRM);
+        return 0;
+}
+late_initcall(pxa910_pm_init);
diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
index b24d2c32cba9..62d787c34475 100644
--- a/arch/arm/mach-mmp/pxa168.c
+++ b/arch/arm/mach-mmp/pxa168.c
@@ -14,6 +14,7 @@
 #include <linux/io.h>
 #include <linux/clk.h>
 #include <linux/platform_device.h>
+#include <linux/platform_data/mv_usb.h>
 #include <asm/mach/time.h>
 #include <asm/system_misc.h>
@@ -27,6 +28,7 @@
 #include <mach/mfp.h>
 #include <linux/dma-mapping.h>
 #include <mach/pxa168.h>
+#include <mach/regs-usb.h>
 #include "common.h"
 #include "clock.h"
@@ -93,7 +95,7 @@ static struct clk_lookup pxa168_clkregs[] = {
        INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
        INIT_CLKREG(&clk_keypad, "pxa27x-keypad", NULL),
        INIT_CLKREG(&clk_eth, "pxa168-eth", "MFUCLK"),
-        INIT_CLKREG(&clk_usb, "pxa168-ehci", "PXA168-USBCLK"),
+        INIT_CLKREG(&clk_usb, NULL, "PXA168-USBCLK"),
        INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL),
 };
@@ -184,17 +186,17 @@ struct platform_device pxa168_device_gpio = {
 struct resource pxa168_usb_host_resources[] = {
        /* USB Host conroller register base */
        [0] = {
-                .start  = 0xd4209000,
+                .start  = PXA168_U2H_REGBASE + U2x_CAPREGS_OFFSET,
-                .end    = 0xd4209000 + 0x200,
+                .end    = PXA168_U2H_REGBASE + USB_REG_RANGE,
                .flags  = IORESOURCE_MEM,
-                .name   = "pxa168-usb-host",
+                .name   = "capregs",
        },
        /* USB PHY register base */
        [1] = {
-                .start  = 0xd4206000,
+                .start  = PXA168_U2H_PHYBASE,
-                .end    = 0xd4206000 + 0xff,
+                .end    = PXA168_U2H_PHYBASE + USB_PHY_RANGE,
                .flags  = IORESOURCE_MEM,
-                .name   = "pxa168-usb-phy",
+                .name   = "phyregs",
        },
        [2] = {
                .start  = IRQ_PXA168_USB2,
@@ -205,7 +207,7 @@ struct resource pxa168_usb_host_resources[] = {
 static u64 pxa168_usb_host_dmamask = DMA_BIT_MASK(32);
 struct platform_device pxa168_device_usb_host = {
-        .name = "pxa168-ehci",
+        .name = "pxa-sph",
        .id   = -1,
        .dev  = {
                .dma_mask = &pxa168_usb_host_dmamask,
@@ -216,7 +218,7 @@ struct platform_device pxa168_device_usb_host = {
        .resource      = pxa168_usb_host_resources,
 };
-int __init pxa168_add_usb_host(struct pxa168_usb_pdata *pdata)
+int __init pxa168_add_usb_host(struct mv_usb_platform_data *pdata)
 {
        pxa168_device_usb_host.dev.platform_data = pdata;
        return platform_device_register(&pxa168_device_usb_host);
diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c
index 43f8bcc29b67..6da52e9f2bdc 100644
--- a/arch/arm/mach-mmp/pxa910.c
+++ b/arch/arm/mach-mmp/pxa910.c
@@ -109,7 +109,7 @@ static struct clk_lookup pxa910_clkregs[] = {
        INIT_CLKREG(&clk_pwm4, "pxa910-pwm.3", NULL),
        INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
        INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
-        INIT_CLKREG(&clk_u2o, "pxa-u2o", "U2OCLK"),
+        INIT_CLKREG(&clk_u2o, NULL, "U2OCLK"),
        INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL),
 };
diff --git a/arch/arm/mach-mmp/time.c b/arch/arm/mach-mmp/time.c
index 71fc4ee4602c..936447c70977 100644
--- a/arch/arm/mach-mmp/time.c
+++ b/arch/arm/mach-mmp/time.c
@@ -25,6 +25,9 @@
 #include <linux/io.h>
 #include <linux/irq.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
 #include <asm/sched_clock.h>
 #include <mach/addr-map.h>
@@ -41,6 +44,8 @@
 #define MAX_DELTA               (0xfffffffe)
 #define MIN_DELTA               (16)
+static void __iomem *mmp_timer_base = TIMERS_VIRT_BASE;
 /*
 * FIXME: the timer needs some delay to stablize the counter capture
 */
@@ -48,12 +53,12 @@ static inline uint32_t timer_read(void)
 {
        int delay = 100;
-        __raw_writel(1, TIMERS_VIRT_BASE + TMR_CVWR(1));
+        __raw_writel(1, mmp_timer_base + TMR_CVWR(1));
        while (delay--)
                cpu_relax();
-        return __raw_readl(TIMERS_VIRT_BASE + TMR_CVWR(1));
+        return __raw_readl(mmp_timer_base + TMR_CVWR(1));
 }
 static u32 notrace mmp_read_sched_clock(void)
@@ -68,12 +73,12 @@ static irqreturn_t timer_interrupt(int irq, void *dev_id)
        /*
         * Clear pending interrupt status.
         */
-        __raw_writel(0x01, TIMERS_VIRT_BASE + TMR_ICR(0));
+        __raw_writel(0x01, mmp_timer_base + TMR_ICR(0));
        /*
         * Disable timer 0.
         */
-        __raw_writel(0x02, TIMERS_VIRT_BASE + TMR_CER);
+        __raw_writel(0x02, mmp_timer_base + TMR_CER);
        c->event_handler(c);
@@ -90,23 +95,23 @@ static int timer_set_next_event(unsigned long delta,
        /*
         * Disable timer 0.
         */
-        __raw_writel(0x02, TIMERS_VIRT_BASE + TMR_CER);
+        __raw_writel(0x02, mmp_timer_base + TMR_CER);
        /*
         * Clear and enable timer match 0 interrupt.
         */
-        __raw_writel(0x01, TIMERS_VIRT_BASE + TMR_ICR(0));
+        __raw_writel(0x01, mmp_timer_base + TMR_ICR(0));
-        __raw_writel(0x01, TIMERS_VIRT_BASE + TMR_IER(0));
+        __raw_writel(0x01, mmp_timer_base + TMR_IER(0));
        /*
         * Setup new clockevent timer value.
         */
-        __raw_writel(delta - 1, TIMERS_VIRT_BASE + TMR_TN_MM(0, 0));
+        __raw_writel(delta - 1, mmp_timer_base + TMR_TN_MM(0, 0));
        /*
         * Enable timer 0.
         */
-        __raw_writel(0x03, TIMERS_VIRT_BASE + TMR_CER);
+        __raw_writel(0x03, mmp_timer_base + TMR_CER);
        local_irq_restore(flags);
@@ -124,7 +129,7 @@ static void timer_set_mode(enum clock_event_mode mode,
        case CLOCK_EVT_MODE_UNUSED:
        case CLOCK_EVT_MODE_SHUTDOWN:
                /* disable the matching interrupt */
-                __raw_writel(0x00, TIMERS_VIRT_BASE + TMR_IER(0));
+                __raw_writel(0x00, mmp_timer_base + TMR_IER(0));
                break;
        case CLOCK_EVT_MODE_RESUME:
        case CLOCK_EVT_MODE_PERIODIC:
@@ -157,27 +162,27 @@ static struct clocksource cksrc = {
 static void __init timer_config(void)
 {
-        uint32_t ccr = __raw_readl(TIMERS_VIRT_BASE + TMR_CCR);
+        uint32_t ccr = __raw_readl(mmp_timer_base + TMR_CCR);
-        __raw_writel(0x0, TIMERS_VIRT_BASE + TMR_CER); /* disable */
+        __raw_writel(0x0, mmp_timer_base + TMR_CER); /* disable */
        ccr &= (cpu_is_mmp2()) ? (TMR_CCR_CS_0(0) | TMR_CCR_CS_1(0)) :
                (TMR_CCR_CS_0(3) | TMR_CCR_CS_1(3));
-        __raw_writel(ccr, TIMERS_VIRT_BASE + TMR_CCR);
+        __raw_writel(ccr, mmp_timer_base + TMR_CCR);
        /* set timer 0 to periodic mode, and timer 1 to free-running mode */
-        __raw_writel(0x2, TIMERS_VIRT_BASE + TMR_CMR);
+        __raw_writel(0x2, mmp_timer_base + TMR_CMR);
-        __raw_writel(0x1, TIMERS_VIRT_BASE + TMR_PLCR(0)); /* periodic */
+        __raw_writel(0x1, mmp_timer_base + TMR_PLCR(0)); /* periodic */
-        __raw_writel(0x7, TIMERS_VIRT_BASE + TMR_ICR(0));  /* clear status */
+        __raw_writel(0x7, mmp_timer_base + TMR_ICR(0));  /* clear status */
-        __raw_writel(0x0, TIMERS_VIRT_BASE + TMR_IER(0));
+        __raw_writel(0x0, mmp_timer_base + TMR_IER(0));
-        __raw_writel(0x0, TIMERS_VIRT_BASE + TMR_PLCR(1)); /* free-running */
+        __raw_writel(0x0, mmp_timer_base + TMR_PLCR(1)); /* free-running */
-        __raw_writel(0x7, TIMERS_VIRT_BASE + TMR_ICR(1));  /* clear status */
+        __raw_writel(0x7, mmp_timer_base + TMR_ICR(1));  /* clear status */
-        __raw_writel(0x0, TIMERS_VIRT_BASE + TMR_IER(1));
+        __raw_writel(0x0, mmp_timer_base + TMR_IER(1));
        /* enable timer 1 counter */
-        __raw_writel(0x2, TIMERS_VIRT_BASE + TMR_CER);
+        __raw_writel(0x2, mmp_timer_base + TMR_CER);
 }
 static struct irqaction timer_irq = {
@@ -203,3 +208,37 @@ void __init timer_init(int irq)
        clocksource_register_hz(&cksrc, CLOCK_TICK_RATE);
        clockevents_register_device(&ckevt);
 }
+#ifdef CONFIG_OF
+static struct of_device_id mmp_timer_dt_ids[] = {
+        { .compatible = "mrvl,mmp-timer", },
+        {}
+};
+void __init mmp_dt_init_timer(void)
+{
+        struct device_node *np;
+        int irq, ret;
+        np = of_find_matching_node(NULL, mmp_timer_dt_ids);
+        if (!np) {
+                ret = -ENODEV;
+                goto out;
+        }
+        irq = irq_of_parse_and_map(np, 0);
+        if (!irq) {
+                ret = -EINVAL;
+                goto out;
+        }
+        mmp_timer_base = of_iomap(np, 0);
+        if (!mmp_timer_base) {
+                ret = -ENOMEM;
+                goto out;
+        }
+        timer_init(irq);
+        return;
+out:
+        pr_err("Failed to get timer from device tree with error:%d\n", ret);
+}
+#endif
diff --git a/arch/arm/mach-mmp/ttc_dkb.c b/arch/arm/mach-mmp/ttc_dkb.c
index 3fc9ed21f97d..7a7de2b12a62 100644
--- a/arch/arm/mach-mmp/ttc_dkb.c
+++ b/arch/arm/mach-mmp/ttc_dkb.c
@@ -17,6 +17,8 @@
 #include <linux/interrupt.h>
 #include <linux/i2c/pca953x.h>
 #include <linux/gpio.h>
+#include <linux/mfd/88pm860x.h>
+#include <linux/platform_data/mv_usb.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -25,6 +27,7 @@
 #include <mach/mfp-pxa910.h>
 #include <mach/pxa910.h>
 #include <mach/irqs.h>
+#include <mach/regs-usb.h>
 #include "common.h"
@@ -135,8 +138,18 @@ static struct pca953x_platform_data max7312_data[] = {
        },
 };
+static struct pm860x_platform_data ttc_dkb_pm8607_info = {
+        .irq_base       = IRQ_BOARD_START,
+};
 static struct i2c_board_info ttc_dkb_i2c_info[] = {
        {
+                .type           = "88PM860x",
+                .addr           = 0x34,
+                .platform_data  = &ttc_dkb_pm8607_info,
+                .irq            = IRQ_PXA910_PMIC_INT,
+        },
+        {
                .type           = "max7312",
                .addr           = 0x23,
                .irq            = MMP_GPIO_TO_IRQ(80),
@@ -144,6 +157,26 @@ static struct i2c_board_info ttc_dkb_i2c_info[] = {
        },
 };
+#ifdef CONFIG_USB_SUPPORT
+#if defined(CONFIG_USB_MV_UDC) || defined(CONFIG_USB_EHCI_MV_U2O)
+static char *pxa910_usb_clock_name[] = {
+        [0] = "U2OCLK",
+};
+static struct mv_usb_platform_data ttc_usb_pdata = {
+        .clknum         = 1,
+        .clkname        = pxa910_usb_clock_name,
+        .vbus           = NULL,
+        .mode           = MV_USB_MODE_OTG,
+        .otg_force_a_bus_req = 1,
+        .phy_init       = pxa_usb_phy_init,
+        .phy_deinit     = pxa_usb_phy_deinit,
+        .set_vbus       = NULL,
+};
+#endif
+#endif
 static void __init ttc_dkb_init(void)
 {
        mfp_config(ARRAY_AND_SIZE(ttc_dkb_pin_config));
@@ -154,6 +187,21 @@ static void __init ttc_dkb_init(void)
        /* off-chip devices */
        pxa910_add_twsi(0, NULL, ARRAY_AND_SIZE(ttc_dkb_i2c_info));
        platform_add_devices(ARRAY_AND_SIZE(ttc_dkb_devices));
+#ifdef CONFIG_USB_MV_UDC
+        pxa168_device_u2o.dev.platform_data = &ttc_usb_pdata;
+        platform_device_register(&pxa168_device_u2o);
+#endif
+#ifdef CONFIG_USB_EHCI_MV_U2O
+        pxa168_device_u2oehci.dev.platform_data = &ttc_usb_pdata;
+        platform_device_register(&pxa168_device_u2oehci);
+#endif
+#ifdef CONFIG_USB_MV_OTG
+        pxa168_device_u2ootg.dev.platform_data = &ttc_usb_pdata;
+        platform_device_register(&pxa168_device_u2ootg);
+#endif
 }
 MACHINE_START(TTC_DKB, "PXA910-based TTC_DKB Development Platform")
diff --git a/arch/arm/mach-msm/board-halibut.c b/arch/arm/mach-msm/board-halibut.c
index 3698a370d636..26aac363a064 100644
--- a/arch/arm/mach-msm/board-halibut.c
+++ b/arch/arm/mach-msm/board-halibut.c
@@ -86,9 +86,6 @@ static void __init halibut_init(void)
 static void __init halibut_fixup(struct tag *tags, char **cmdline,
                                 struct meminfo *mi)
 {
-        mi->nr_banks=1;
-        mi->bank[0].start = PHYS_OFFSET;
-        mi->bank[0].size = (101*1024*1024);
 }
 static void __init halibut_map_io(void)
diff --git a/arch/arm/mach-msm/board-msm7x30.c b/arch/arm/mach-msm/board-msm7x30.c
index db81ed531031..75b3cfcada6d 100644
--- a/arch/arm/mach-msm/board-msm7x30.c
+++ b/arch/arm/mach-msm/board-msm7x30.c
@@ -17,7 +17,6 @@
 #include <linux/gpio.h>
 #include <linux/kernel.h>
 #include <linux/irq.h>
-#include <linux/gpio.h>
 #include <linux/platform_device.h>
 #include <linux/delay.h>
 #include <linux/io.h>
diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c
index 962e71169750..fb3496a52ef4 100644
--- a/arch/arm/mach-msm/board-msm8x60.c
+++ b/arch/arm/mach-msm/board-msm8x60.c
@@ -17,6 +17,7 @@
 #include <linux/irqdomain.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
+#include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/memblock.h>
@@ -49,10 +50,22 @@ static void __init msm8x60_map_io(void)
        msm_map_msm8x60_io();
 }
+#ifdef CONFIG_OF
+static struct of_device_id msm_dt_gic_match[] __initdata = {
+        { .compatible = "qcom,msm-8660-qgic", .data = gic_of_init },
+        {}
+};
+#endif
 static void __init msm8x60_init_irq(void)
 {
-        gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
+        if (!of_have_populated_dt())
-                 (void *)MSM_QGIC_CPU_BASE);
+                gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
+                         (void *)MSM_QGIC_CPU_BASE);
+#ifdef CONFIG_OF
+        else
+                of_irq_init(msm_dt_gic_match);
+#endif
        /* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
        writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
@@ -73,16 +86,8 @@ static struct of_dev_auxdata msm_auxdata_lookup[] __initdata = {
        {}
 };
-static struct of_device_id msm_dt_gic_match[] __initdata = {
-        { .compatible = "qcom,msm-8660-qgic", },
-        {}
-};
 static void __init msm8x60_dt_init(void)
 {
-        irq_domain_generate_simple(msm_dt_gic_match, MSM8X60_QGIC_DIST_PHYS,
-                                GIC_SPI_START);
        if (of_machine_is_compatible("qcom,msm8660-surf")) {
                printk(KERN_INFO "Init surf UART registers\n");
                msm8x60_init_uart12dm();
diff --git a/arch/arm/mach-msm/board-qsd8x50.c b/arch/arm/mach-msm/board-qsd8x50.c
index 7e8909c978c3..fbaa4ed95a3c 100644
--- a/arch/arm/mach-msm/board-qsd8x50.c
+++ b/arch/arm/mach-msm/board-qsd8x50.c
@@ -17,7 +17,6 @@
 #include <linux/gpio.h>
 #include <linux/kernel.h>
 #include <linux/irq.h>
-#include <linux/gpio.h>
 #include <linux/platform_device.h>
 #include <linux/delay.h>
 #include <linux/usb/msm_hsusb.h>
diff --git a/arch/arm/mach-msm/board-trout-panel.c b/arch/arm/mach-msm/board-trout-panel.c
index 25105c1027fe..89bf6b426699 100644
--- a/arch/arm/mach-msm/board-trout-panel.c
+++ b/arch/arm/mach-msm/board-trout-panel.c
@@ -12,6 +12,7 @@
 #include <asm/io.h>
 #include <asm/mach-types.h>
+#include <asm/system_info.h>
 #include <mach/msm_fb.h>
 #include <mach/vreg.h>
diff --git a/arch/arm/mach-msm/board-trout.c b/arch/arm/mach-msm/board-trout.c
index 5414f76ec0a9..d4060a37e23d 100644
--- a/arch/arm/mach-msm/board-trout.c
+++ b/arch/arm/mach-msm/board-trout.c
@@ -19,6 +19,7 @@
 #include <linux/platform_device.h>
 #include <linux/clkdev.h>
+#include <asm/system_info.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
diff --git a/arch/arm/mach-msm/include/mach/debug-macro.S b/arch/arm/mach-msm/include/mach/debug-macro.S
index 3ffd8668c9a5..0e05f88abcd5 100644
--- a/arch/arm/mach-msm/include/mach/debug-macro.S
+++ b/arch/arm/mach-msm/include/mach/debug-macro.S
@@ -30,8 +30,7 @@
        @ Write the 1 character to UARTDM_TF
        str     \rd, [\rx, #0x70]
 #else
-        teq     \rx, #0
+        str     \rd, [\rx, #0x0C]
-        strne   \rd, [\rx, #0x0C]
 #endif
        .endm
diff --git a/arch/arm/mach-msm/proc_comm.c b/arch/arm/mach-msm/proc_comm.c
index 67e701c7f183..9980dc736e7b 100644
--- a/arch/arm/mach-msm/proc_comm.c
+++ b/arch/arm/mach-msm/proc_comm.c
@@ -121,7 +121,7 @@ int msm_proc_comm(unsigned cmd, unsigned *data1, unsigned *data2)
 * and unknown state. This function should be called early to
 * wait on the ARM9.
 */
-void __init proc_comm_boot_wait(void)
+void __devinit proc_comm_boot_wait(void)
 {
        void __iomem *base = MSM_SHARED_RAM_BASE;
 
diff --git a/arch/arm/mach-msm/scm.c b/arch/arm/mach-msm/scm.c
index bafabb502580..c536fd6bf827 100644
--- a/arch/arm/mach-msm/scm.c
+++ b/arch/arm/mach-msm/scm.c
@@ -282,6 +282,9 @@ u32 scm_get_version(void)
                        __asmeq("%1", "r1")
                        __asmeq("%2", "r0")
                        __asmeq("%3", "r1")
+#ifdef REQUIRES_SEC
+                        ".arch_extension sec\n"
+#endif
                        "smc    #0      @ switch to secure world\n"
                        : "=r" (r0), "=r" (r1)
                        : "r" (r0), "r" (r1)
diff --git a/arch/arm/mach-mv78xx0/pcie.c b/arch/arm/mach-mv78xx0/pcie.c
index df3e38055a24..2e56e86b6d68 100644
--- a/arch/arm/mach-mv78xx0/pcie.c
+++ b/arch/arm/mach-mv78xx0/pcie.c
@@ -147,6 +147,7 @@ static int __init mv78xx0_pcie_setup(int nr, struct pci_sys_data *sys)
                return 0;
        pp = &pcie_port[nr];
+        sys->private_data = pp;
        pp->root_bus_nr = sys->busnr;
        /*
@@ -161,19 +162,6 @@ static int __init mv78xx0_pcie_setup(int nr, struct pci_sys_data *sys)
        return 1;
 }
-static struct pcie_port *bus_to_port(int bus)
-{
-        int i;
-        for (i = num_pcie_ports - 1; i >= 0; i--) {
-                int rbus = pcie_port[i].root_bus_nr;
-                if (rbus != -1 && rbus <= bus)
-                        break;
-        }
-        return i >= 0 ? pcie_port + i : NULL;
-}
 static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
 {
        /*
@@ -189,7 +177,8 @@ static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
 static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
                        int size, u32 *val)
 {
-        struct pcie_port *pp = bus_to_port(bus->number);
+        struct pci_sys_data *sys = bus->sysdata;
+        struct pcie_port *pp = sys->private_data;
        unsigned long flags;
        int ret;
@@ -208,7 +197,8 @@ static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
 static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
                        int where, int size, u32 val)
 {
-        struct pcie_port *pp = bus_to_port(bus->number);
+        struct pci_sys_data *sys = bus->sysdata;
+        struct pcie_port *pp = sys->private_data;
        unsigned long flags;
        int ret;
@@ -263,7 +253,8 @@ mv78xx0_pcie_scan_bus(int nr, struct pci_sys_data *sys)
 static int __init mv78xx0_pcie_map_irq(const struct pci_dev *dev, u8 slot,
        u8 pin)
 {
-        struct pcie_port *pp = bus_to_port(dev->bus->number);
+        struct pci_sys_data *sys = dev->bus->sysdata;
+        struct pcie_port *pp = sys->private_data;
        return IRQ_MV78XX0_PCIE_00 + (pp->maj << 2) + pp->min;
 }
@@ -271,7 +262,6 @@ static int __init mv78xx0_pcie_map_irq(const struct pci_dev *dev, u8 slot,
 static struct hw_pci mv78xx0_pci __initdata = {
        .nr_controllers = 8,
        .preinit        = mv78xx0_pcie_preinit,
-        .swizzle        = pci_std_swizzle,
        .setup          = mv78xx0_pcie_setup,
        .scan           = mv78xx0_pcie_scan_bus,
        .map_irq        = mv78xx0_pcie_map_irq,
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
index c57f9964a713..07d5383d68ee 100644
--- a/arch/arm/mach-mxs/Kconfig
+++ b/arch/arm/mach-mxs/Kconfig
@@ -9,11 +9,13 @@ config SOC_IMX23
        bool
        select CPU_ARM926T
        select HAVE_PWM
+        select PINCTRL_IMX23
 config SOC_IMX28
        bool
        select CPU_ARM926T
        select HAVE_PWM
+        select PINCTRL_IMX28
 comment "MXS platforms:"
diff --git a/arch/arm/mach-mxs/devices-mx23.h b/arch/arm/mach-mxs/devices-mx23.h
index 4d1329d59287..9acdd6387047 100644
--- a/arch/arm/mach-mxs/devices-mx23.h
+++ b/arch/arm/mach-mxs/devices-mx23.h
@@ -11,10 +11,16 @@
 #include <mach/mx23.h>
 #include <mach/devices-common.h>
 #include <mach/mxsfb.h>
+#include <linux/amba/bus.h>
-extern const struct amba_device mx23_duart_device __initconst;
+static inline int mx23_add_duart(void)
-#define mx23_add_duart() \
+{
-        mxs_add_duart(&mx23_duart_device)
+        struct amba_device *d;
+        d = amba_ahb_device_add(NULL, "duart", MX23_DUART_BASE_ADDR, SZ_8K,
+                                MX23_INT_DUART, 0, 0, 0);
+        return IS_ERR(d) ? PTR_ERR(d) : 0;
+}
 extern const struct mxs_auart_data mx23_auart_data[] __initconst;
 #define mx23_add_auart(id)      mxs_add_auart(&mx23_auart_data[id])
diff --git a/arch/arm/mach-mxs/devices-mx28.h b/arch/arm/mach-mxs/devices-mx28.h
index 9dbeae130842..84b2960df117 100644
--- a/arch/arm/mach-mxs/devices-mx28.h
+++ b/arch/arm/mach-mxs/devices-mx28.h
@@ -11,10 +11,16 @@
 #include <mach/mx28.h>
 #include <mach/devices-common.h>
 #include <mach/mxsfb.h>
+#include <linux/amba/bus.h>
-extern const struct amba_device mx28_duart_device __initconst;
+static inline int mx28_add_duart(void)
-#define mx28_add_duart() \
+{
-        mxs_add_duart(&mx28_duart_device)
+        struct amba_device *d;
+        d = amba_ahb_device_add(NULL, "duart", MX28_DUART_BASE_ADDR, SZ_8K,
+                                MX28_INT_DUART, 0, 0, 0);
+        return IS_ERR(d) ? PTR_ERR(d) : 0;
+}
 extern const struct mxs_auart_data mx28_auart_data[] __initconst;
 #define mx28_add_auart(id)      mxs_add_auart(&mx28_auart_data[id])
diff --git a/arch/arm/mach-mxs/devices.c b/arch/arm/mach-mxs/devices.c
index 01faffec3064..cf50b5a66dda 100644
--- a/arch/arm/mach-mxs/devices.c
+++ b/arch/arm/mach-mxs/devices.c
@@ -75,22 +75,6 @@ err:
        return pdev;
 }
-int __init mxs_add_amba_device(const struct amba_device *dev)
-{
-        struct amba_device *adev = amba_device_alloc(dev->dev.init_name,
-                dev->res.start, resource_size(&dev->res));
-        if (!adev) {
-                pr_err("%s: failed to allocate memory", __func__);
-                return -ENOMEM;
-        }
-        adev->irq[0] = dev->irq[0];
-        adev->irq[1] = dev->irq[1];
-        return amba_device_add(adev, &iomem_resource);
-}
 struct device mxs_apbh_bus = {
        .init_name      = "mxs_apbh",
        .parent         = &platform_bus,
diff --git a/arch/arm/mach-mxs/devices/Makefile b/arch/arm/mach-mxs/devices/Makefile
index c8f5c9541a30..5f72d9787444 100644
--- a/arch/arm/mach-mxs/devices/Makefile
+++ b/arch/arm/mach-mxs/devices/Makefile
@@ -1,4 +1,3 @@
-obj-$(CONFIG_MXS_HAVE_AMBA_DUART) += amba-duart.o
 obj-$(CONFIG_MXS_HAVE_PLATFORM_AUART) += platform-auart.o
 obj-y += platform-dma.o
 obj-$(CONFIG_MXS_HAVE_PLATFORM_FEC) += platform-fec.o
diff --git a/arch/arm/mach-mxs/devices/amba-duart.c b/arch/arm/mach-mxs/devices/amba-duart.c
deleted file mode 100644
index a5479f766046..000000000000
--- a/arch/arm/mach-mxs/devices/amba-duart.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Copyright (C) 2009-2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- *
- * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <asm/irq.h>
-#include <mach/mx23.h>
-#include <mach/mx28.h>
-#include <mach/devices-common.h>
-#define MXS_AMBA_DUART_DEVICE(name, soc)                        \
-const struct amba_device name##_device __initconst = {          \
-        .dev = {                                                \
-                .init_name = "duart",                           \
-        },                                                      \
-        .res = {                                                \
-                .start = soc ## _DUART_BASE_ADDR,               \
-                .end = (soc ## _DUART_BASE_ADDR) + SZ_8K - 1,   \
-                .flags = IORESOURCE_MEM,                        \
-        },                                                      \
-        .irq = {soc ## _INT_DUART},                             \
-}
-#ifdef CONFIG_SOC_IMX23
-MXS_AMBA_DUART_DEVICE(mx23_duart, MX23);
-#endif
-#ifdef CONFIG_SOC_IMX28
-MXS_AMBA_DUART_DEVICE(mx28_duart, MX28);
-#endif
-int __init mxs_add_duart(const struct amba_device *dev)
-{
-        return mxs_add_amba_device(dev);
-}
diff --git a/arch/arm/mach-mxs/include/mach/common.h b/arch/arm/mach-mxs/include/mach/common.h
index c50c3ea28a9d..8d88399b73ef 100644
--- a/arch/arm/mach-mxs/include/mach/common.h
+++ b/arch/arm/mach-mxs/include/mach/common.h
@@ -19,11 +19,13 @@ extern void mxs_timer_init(struct clk *, int);
 extern void mxs_restart(char, const char *);
 extern int mxs_saif_clkmux_select(unsigned int clkmux);
+extern void mx23_soc_init(void);
 extern int mx23_register_gpios(void);
 extern int mx23_clocks_init(void);
 extern void mx23_map_io(void);
 extern void mx23_init_irq(void);
+extern void mx28_soc_init(void);
 extern int mx28_register_gpios(void);
 extern int mx28_clocks_init(void);
 extern void mx28_map_io(void);
diff --git a/arch/arm/mach-mxs/include/mach/devices-common.h b/arch/arm/mach-mxs/include/mach/devices-common.h
index f2e383955d88..21e45a70d344 100644
--- a/arch/arm/mach-mxs/include/mach/devices-common.h
+++ b/arch/arm/mach-mxs/include/mach/devices-common.h
@@ -27,11 +27,6 @@ static inline struct platform_device *mxs_add_platform_device(
                        name, id, res, num_resources, data, size_data, 0);
 }
-int __init mxs_add_amba_device(const struct amba_device *dev);
-/* duart */
-int __init mxs_add_duart(const struct amba_device *dev);
 /* auart */
 struct mxs_auart_data {
        int id;
diff --git a/arch/arm/mach-mxs/mach-apx4devkit.c b/arch/arm/mach-mxs/mach-apx4devkit.c
index 48a7fab571a6..5e90b9dcdef8 100644
--- a/arch/arm/mach-mxs/mach-apx4devkit.c
+++ b/arch/arm/mach-mxs/mach-apx4devkit.c
@@ -207,6 +207,8 @@ static int apx4devkit_phy_fixup(struct phy_device *phy)
 static void __init apx4devkit_init(void)
 {
+        mx28_soc_init();
        mxs_iomux_setup_multiple_pads(apx4devkit_pads,
                        ARRAY_SIZE(apx4devkit_pads));
diff --git a/arch/arm/mach-mxs/mach-m28evk.c b/arch/arm/mach-mxs/mach-m28evk.c
index 06d79963611c..4c00c879b893 100644
--- a/arch/arm/mach-mxs/mach-m28evk.c
+++ b/arch/arm/mach-mxs/mach-m28evk.c
@@ -319,6 +319,8 @@ static struct mxs_mmc_platform_data m28evk_mmc_pdata[] __initdata = {
 static void __init m28evk_init(void)
 {
+        mx28_soc_init();
        mxs_iomux_setup_multiple_pads(m28evk_pads, ARRAY_SIZE(m28evk_pads));
        mx28_add_duart();
diff --git a/arch/arm/mach-mxs/mach-mx23evk.c b/arch/arm/mach-mxs/mach-mx23evk.c
index 5ea1c57d2606..e7272a41939d 100644
--- a/arch/arm/mach-mxs/mach-mx23evk.c
+++ b/arch/arm/mach-mxs/mach-mx23evk.c
@@ -141,6 +141,8 @@ static void __init mx23evk_init(void)
 {
        int ret;
+        mx23_soc_init();
        mxs_iomux_setup_multiple_pads(mx23evk_pads, ARRAY_SIZE(mx23evk_pads));
        mx23_add_duart();
diff --git a/arch/arm/mach-mxs/mach-mx28evk.c b/arch/arm/mach-mxs/mach-mx28evk.c
index e386c142f93c..da4610ebe9e6 100644
--- a/arch/arm/mach-mxs/mach-mx28evk.c
+++ b/arch/arm/mach-mxs/mach-mx28evk.c
@@ -413,6 +413,8 @@ static void __init mx28evk_init(void)
 {
        int ret;
+        mx28_soc_init();
        mxs_iomux_setup_multiple_pads(mx28evk_pads, ARRAY_SIZE(mx28evk_pads));
        mx28_add_duart();
diff --git a/arch/arm/mach-mxs/mach-stmp378x_devb.c b/arch/arm/mach-mxs/mach-stmp378x_devb.c
index a626c07b8713..6548965e4a76 100644
--- a/arch/arm/mach-mxs/mach-stmp378x_devb.c
+++ b/arch/arm/mach-mxs/mach-stmp378x_devb.c
@@ -85,6 +85,8 @@ static void __init stmp378x_dvb_init(void)
 {
        int ret;
+        mx23_soc_init();
        mxs_iomux_setup_multiple_pads(stmp378x_dvb_pads,
                        ARRAY_SIZE(stmp378x_dvb_pads));
diff --git a/arch/arm/mach-mxs/mach-tx28.c b/arch/arm/mach-mxs/mach-tx28.c
index 2c0862e655ee..8837029de1a4 100644
--- a/arch/arm/mach-mxs/mach-tx28.c
+++ b/arch/arm/mach-mxs/mach-tx28.c
@@ -146,6 +146,8 @@ static struct mxs_mmc_platform_data tx28_mmc0_pdata __initdata = {
 static void __init tx28_stk5v3_init(void)
 {
+        mx28_soc_init();
        mxs_iomux_setup_multiple_pads(tx28_stk5v3_pads,
                        ARRAY_SIZE(tx28_stk5v3_pads));
diff --git a/arch/arm/mach-mxs/mm.c b/arch/arm/mach-mxs/mm.c
index 50af5ceebf6d..67a384edcf5b 100644
--- a/arch/arm/mach-mxs/mm.c
+++ b/arch/arm/mach-mxs/mm.c
@@ -13,6 +13,7 @@
 #include <linux/mm.h>
 #include <linux/init.h>
+#include <linux/pinctrl/machine.h>
 #include <asm/mach/map.h>
@@ -61,3 +62,13 @@ void __init mx28_init_irq(void)
 {
        icoll_init_irq();
 }
+void __init mx23_soc_init(void)
+{
+        pinctrl_provide_dummies();
+}
+void __init mx28_soc_init(void)
+{
+        pinctrl_provide_dummies();
+}
diff --git a/arch/arm/mach-nomadik/Kconfig b/arch/arm/mach-nomadik/Kconfig
index 3c5e0f522e9c..365879b47c0e 100644
--- a/arch/arm/mach-nomadik/Kconfig
+++ b/arch/arm/mach-nomadik/Kconfig
@@ -15,6 +15,7 @@ config NOMADIK_8815
 config I2C_BITBANG_8815NHK
        tristate "Driver for bit-bang busses found on the 8815 NHK"
        depends on I2C && MACH_NOMADIK_8815NHK
+        depends on PINCTRL_NOMADIK
        select I2C_ALGOBIT
        default y
diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig
index dfab466ebd1d..cba3f7191cfc 100644
--- a/arch/arm/mach-omap1/Kconfig
+++ b/arch/arm/mach-omap1/Kconfig
@@ -132,6 +132,7 @@ config MACH_OMAP_PALMTT
 config MACH_SX1
        bool "Siemens SX1"
+        select I2C
        depends on ARCH_OMAP1 && ARCH_OMAP15XX
        help
          Support for the Siemens SX1 phone. To boot the kernel,
diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile
index 9923f92b5450..398e9e53e189 100644
--- a/arch/arm/mach-omap1/Makefile
+++ b/arch/arm/mach-omap1/Makefile
@@ -12,6 +12,9 @@ endif
 obj-$(CONFIG_OMAP_32K_TIMER)    += timer32k.o
+# OCPI interconnect support for 1710, 1610 and 5912
+obj-$(CONFIG_ARCH_OMAP16XX) += ocpi.o
 # Power Management
 obj-$(CONFIG_PM) += pm.o sleep.o
@@ -28,13 +31,15 @@ usb-fs-$(CONFIG_USB)			:= usb.o
 obj-y                                   += $(usb-fs-m) $(usb-fs-y)
 # Specific board support
-obj-$(CONFIG_MACH_OMAP_H2)              += board-h2.o board-h2-mmc.o
+obj-$(CONFIG_MACH_OMAP_H2)              += board-h2.o board-h2-mmc.o \
+                                           board-nand.o
 obj-$(CONFIG_MACH_OMAP_INNOVATOR)       += board-innovator.o
 obj-$(CONFIG_MACH_OMAP_GENERIC)         += board-generic.o
-obj-$(CONFIG_MACH_OMAP_PERSEUS2)        += board-perseus2.o
+obj-$(CONFIG_MACH_OMAP_PERSEUS2)        += board-perseus2.o board-nand.o
-obj-$(CONFIG_MACH_OMAP_FSAMPLE)         += board-fsample.o
+obj-$(CONFIG_MACH_OMAP_FSAMPLE)         += board-fsample.o board-nand.o
 obj-$(CONFIG_MACH_OMAP_OSK)             += board-osk.o
-obj-$(CONFIG_MACH_OMAP_H3)              += board-h3.o board-h3-mmc.o
+obj-$(CONFIG_MACH_OMAP_H3)              += board-h3.o board-h3-mmc.o \
+                                           board-nand.o
 obj-$(CONFIG_MACH_VOICEBLUE)            += board-voiceblue.o
 obj-$(CONFIG_MACH_OMAP_PALMTE)          += board-palmte.o
 obj-$(CONFIG_MACH_OMAP_PALMZ71)         += board-palmz71.o
diff --git a/arch/arm/mach-omap1/ams-delta-fiq.c b/arch/arm/mach-omap1/ams-delta-fiq.c
index fcce7ff37630..68e8e5654c0a 100644
--- a/arch/arm/mach-omap1/ams-delta-fiq.c
+++ b/arch/arm/mach-omap1/ams-delta-fiq.c
@@ -48,7 +48,7 @@ static irqreturn_t deferred_fiq(int irq, void *dev_id)
        struct irq_chip *irq_chip = NULL;
        int gpio, irq_num, fiq_count;
-        irq_desc = irq_to_desc(IH_GPIO_BASE);
+        irq_desc = irq_to_desc(gpio_to_irq(AMS_DELTA_GPIO_PIN_KEYBRD_CLK));
        if (irq_desc)
                irq_chip = irq_desc->irq_data.chip;
@@ -102,7 +102,7 @@ void __init ams_delta_init_fiq(void)
        }
        retval = request_irq(INT_DEFERRED_FIQ, deferred_fiq,
-                        IRQ_TYPE_EDGE_RISING, "deferred_fiq", 0);
+                        IRQ_TYPE_EDGE_RISING, "deferred_fiq", NULL);
        if (retval < 0) {
                pr_err("Failed to get deferred_fiq IRQ, ret=%d\n", retval);
                release_fiq(&fh);
diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c
index 80bd43c7f4ec..4a4afb371022 100644
--- a/arch/arm/mach-omap1/board-fsample.c
+++ b/arch/arm/mach-omap1/board-fsample.c
@@ -185,20 +185,6 @@ static struct platform_device nor_device = {
        .resource       = &nor_resource,
 };
-static void nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
-{
-        struct nand_chip *this = mtd->priv;
-        unsigned long mask;
-        if (cmd == NAND_CMD_NONE)
-                return;
-        mask = (ctrl & NAND_CLE) ? 0x02 : 0;
-        if (ctrl & NAND_ALE)
-                mask |= 0x04;
-        writeb(cmd, (unsigned long)this->IO_ADDR_W | mask);
-}
 #define FSAMPLE_NAND_RB_GPIO_PIN        62
 static int nand_dev_ready(struct mtd_info *mtd)
@@ -216,7 +202,7 @@ static struct platform_nand_data nand_data = {
                .part_probe_types       = part_probes,
        },
        .ctrl   = {
-                .cmd_ctrl       = nand_cmd_ctl,
+                .cmd_ctrl       = omap1_nand_cmd_ctl,
                .dev_ready      = nand_dev_ready,
        },
 };
diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c
index 553a2e535764..057ec13f0649 100644
--- a/arch/arm/mach-omap1/board-h2.c
+++ b/arch/arm/mach-omap1/board-h2.c
@@ -179,20 +179,6 @@ static struct mtd_partition h2_nand_partitions[] = {
        },
 };
-static void h2_nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
-{
-        struct nand_chip *this = mtd->priv;
-        unsigned long mask;
-        if (cmd == NAND_CMD_NONE)
-                return;
-        mask = (ctrl & NAND_CLE) ? 0x02 : 0;
-        if (ctrl & NAND_ALE)
-                mask |= 0x04;
-        writeb(cmd, (unsigned long)this->IO_ADDR_W | mask);
-}
 #define H2_NAND_RB_GPIO_PIN     62
 static int h2_nand_dev_ready(struct mtd_info *mtd)
@@ -212,9 +198,8 @@ static struct platform_nand_data h2_nand_platdata = {
                .part_probe_types       = h2_part_probes,
        },
        .ctrl   = {
-                .cmd_ctrl       = h2_nand_cmd_ctl,
+                .cmd_ctrl       = omap1_nand_cmd_ctl,
                .dev_ready      = h2_nand_dev_ready,
        },
 };
diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c
index 4c19f4c06851..f6ddf8759657 100644
--- a/arch/arm/mach-omap1/board-h3.c
+++ b/arch/arm/mach-omap1/board-h3.c
@@ -181,20 +181,6 @@ static struct mtd_partition nand_partitions[] = {
        },
 };
-static void nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
-{
-        struct nand_chip *this = mtd->priv;
-        unsigned long mask;
-        if (cmd == NAND_CMD_NONE)
-                return;
-        mask = (ctrl & NAND_CLE) ? 0x02 : 0;
-        if (ctrl & NAND_ALE)
-                mask |= 0x04;
-        writeb(cmd, (unsigned long)this->IO_ADDR_W | mask);
-}
 #define H3_NAND_RB_GPIO_PIN     10
 static int nand_dev_ready(struct mtd_info *mtd)
@@ -214,7 +200,7 @@ static struct platform_nand_data nand_platdata = {
                .part_probe_types       = part_probes,
        },
        .ctrl   = {
-                .cmd_ctrl       = nand_cmd_ctl,
+                .cmd_ctrl       = omap1_nand_cmd_ctl,
                .dev_ready      = nand_dev_ready,
        },
diff --git a/arch/arm/mach-omap1/board-nand.c b/arch/arm/mach-omap1/board-nand.c
new file mode 100644
index 000000000000..4d0835327d20
--- /dev/null
+++ b/arch/arm/mach-omap1/board-nand.c
@@ -0,0 +1,37 @@
+/*
+ * linux/arch/arm/mach-omap1/board-nand.c
+ *
+ * Common OMAP1 board NAND code
+ *
+ * Copyright (C) 2004, 2012 Texas Instruments, Inc.
+ * Copyright (C) 2002 MontaVista Software, Inc.
+ * Copyright (C) 2001 RidgeRun, Inc.
+ * Author: RidgeRun, Inc.
+ *         Greg Lonnon (glonnon@ridgerun.com) or info@ridgerun.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include "common.h"
+void omap1_nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+{
+        struct nand_chip *this = mtd->priv;
+        unsigned long mask;
+        if (cmd == NAND_CMD_NONE)
+                return;
+        mask = (ctrl & NAND_CLE) ? 0x02 : 0;
+        if (ctrl & NAND_ALE)
+                mask |= 0x04;
+        writeb(cmd, this->IO_ADDR_W + mask);
+}
diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c
index a2c5abcd7c84..61ed4f0247ce 100644
--- a/arch/arm/mach-omap1/board-palmz71.c
+++ b/arch/arm/mach-omap1/board-palmz71.c
@@ -289,10 +289,10 @@ palmz71_gpio_setup(int early)
                gpio_direction_input(PALMZ71_USBDETECT_GPIO);
                if (request_irq(gpio_to_irq(PALMZ71_USBDETECT_GPIO),
                                palmz71_powercable, IRQF_SAMPLE_RANDOM,
-                                "palmz71-cable", 0))
+                                "palmz71-cable", NULL))
                        printk(KERN_ERR
                                        "IRQ request for power cable failed!\n");
-                palmz71_powercable(gpio_to_irq(PALMZ71_USBDETECT_GPIO), 0);
+                palmz71_powercable(gpio_to_irq(PALMZ71_USBDETECT_GPIO), NULL);
        }
 }
diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c
index 76d4ee05a814..a2c88890e767 100644
--- a/arch/arm/mach-omap1/board-perseus2.c
+++ b/arch/arm/mach-omap1/board-perseus2.c
@@ -143,20 +143,6 @@ static struct platform_device nor_device = {
        .resource       = &nor_resource,
 };
-static void nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
-{
-        struct nand_chip *this = mtd->priv;
-        unsigned long mask;
-        if (cmd == NAND_CMD_NONE)
-                return;
-        mask = (ctrl & NAND_CLE) ? 0x02 : 0;
-        if (ctrl & NAND_ALE)
-                mask |= 0x04;
-        writeb(cmd, (unsigned long)this->IO_ADDR_W | mask);
-}
 #define P2_NAND_RB_GPIO_PIN     62
 static int nand_dev_ready(struct mtd_info *mtd)
@@ -174,7 +160,7 @@ static struct platform_nand_data nand_data = {
                .part_probe_types       = part_probes,
        },
        .ctrl   = {
-                .cmd_ctrl       = nand_cmd_ctl,
+                .cmd_ctrl       = omap1_nand_cmd_ctl,
                .dev_ready      = nand_dev_ready,
        },
 };
diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c
index 67382ddd8c83..a9ee06b6cb42 100644
--- a/arch/arm/mach-omap1/clock.c
+++ b/arch/arm/mach-omap1/clock.c
@@ -194,9 +194,8 @@ int omap1_select_table_rate(struct clk *clk, unsigned long rate)
 {
        /* Find the highest supported frequency <= rate and switch to it */
        struct mpu_rate * ptr;
-        unsigned long dpll1_rate, ref_rate;
+        unsigned long ref_rate;
-        dpll1_rate = ck_dpll1_p->rate;
        ref_rate = ck_ref_p->rate;
        for (ptr = omap1_rate_table; ptr->rate; ptr++) {
diff --git a/arch/arm/mach-omap1/common.h b/arch/arm/mach-omap1/common.h
index af658ad338ec..bb7779b57795 100644
--- a/arch/arm/mach-omap1/common.h
+++ b/arch/arm/mach-omap1/common.h
@@ -27,6 +27,7 @@
 #define __ARCH_ARM_MACH_OMAP1_COMMON_H
 #include <plat/common.h>
+#include <linux/mtd/mtd.h>
 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
 void omap7xx_map_io(void);
@@ -56,8 +57,20 @@ void omap1_init_early(void);
 void omap1_init_irq(void);
 void omap1_restart(char, const char *);
+extern void __init omap_check_revision(void);
+extern void omap1_nand_cmd_ctl(struct mtd_info *mtd, int cmd,
+                               unsigned int ctrl);
 extern struct sys_timer omap1_timer;
 extern bool omap_32k_timer_init(void);
-extern void __init omap_init_consistent_dma_size(void);
+extern u32 omap_irq_flags;
+#ifdef CONFIG_ARCH_OMAP16XX
+extern int ocpi_enable(void);
+#else
+static inline int ocpi_enable(void) { return 0; }
+#endif
 #endif /* __ARCH_ARM_MACH_OMAP1_COMMON_H */
diff --git a/arch/arm/mach-omap1/fpga.c b/arch/arm/mach-omap1/fpga.c
index 76c67b3f9f61..29ec50fc688d 100644
--- a/arch/arm/mach-omap1/fpga.c
+++ b/arch/arm/mach-omap1/fpga.c
@@ -87,7 +87,7 @@ static void fpga_mask_ack_irq(struct irq_data *d)
        fpga_ack_irq(d);
 }
-void innovator_fpga_IRQ_demux(unsigned int irq, struct irq_desc *desc)
+static void innovator_fpga_IRQ_demux(unsigned int irq, struct irq_desc *desc)
 {
        u32 stat;
        int fpga_irq;
diff --git a/arch/arm/mach-omap1/id.c b/arch/arm/mach-omap1/id.c
index 2b28e1da14b0..a1b846aacdaf 100644
--- a/arch/arm/mach-omap1/id.c
+++ b/arch/arm/mach-omap1/id.c
@@ -21,6 +21,8 @@
 #include <mach/hardware.h>
+#include "common.h"
 #define OMAP_DIE_ID_0           0xfffe1800
 #define OMAP_DIE_ID_1           0xfffe1804
 #define OMAP_PRODUCTION_ID_0    0xfffe2000
diff --git a/arch/arm/mach-omap1/io.c b/arch/arm/mach-omap1/io.c
index d969a7203d14..71ce017bf5d8 100644
--- a/arch/arm/mach-omap1/io.c
+++ b/arch/arm/mach-omap1/io.c
@@ -18,13 +18,12 @@
 #include <plat/mux.h>
 #include <plat/tc.h>
+#include <plat/dma.h>
 #include "iomap.h"
 #include "common.h"
 #include "clock.h"
-extern void omap_check_revision(void);
 /*
 * The machine specific code may provide the extra mapping besides the
 * default mapping provided here.
diff --git a/arch/arm/mach-omap1/irq.c b/arch/arm/mach-omap1/irq.c
index 4448114fab72..6995fb6a3345 100644
--- a/arch/arm/mach-omap1/irq.c
+++ b/arch/arm/mach-omap1/irq.c
@@ -49,6 +49,8 @@
 #include <mach/hardware.h>
+#include "common.h"
 #define IRQ_BANK(irq) ((irq) >> 5)
 #define IRQ_BIT(irq)  ((irq) & 0x1f)
diff --git a/arch/arm/mach-omap1/lcd_dma.c b/arch/arm/mach-omap1/lcd_dma.c
index 86ace9aaa663..5769c71815b2 100644
--- a/arch/arm/mach-omap1/lcd_dma.c
+++ b/arch/arm/mach-omap1/lcd_dma.c
@@ -57,7 +57,7 @@ static struct lcd_dma_info {
        void *cb_data;
        int active;
-        unsigned long addr, size;
+        unsigned long addr;
        int rotate, data_type, xres, yres;
        int vxres;
        int mirror;
@@ -77,11 +77,6 @@ void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
 }
 EXPORT_SYMBOL(omap_set_lcd_dma_b1);
-void omap_set_lcd_dma_src_port(int port)
-{
-        lcd_dma.src_port = port;
-}
 void omap_set_lcd_dma_ext_controller(int external)
 {
        lcd_dma.ext_ctrl = external;
diff --git a/arch/arm/mach-omap1/mux.c b/arch/arm/mach-omap1/mux.c
index 087dba0df47e..e9cc52d4cb28 100644
--- a/arch/arm/mach-omap1/mux.c
+++ b/arch/arm/mach-omap1/mux.c
@@ -27,6 +27,7 @@
 #include <linux/io.h>
 #include <linux/spinlock.h>
+#include <mach/hardware.h>
 #include <plat/mux.h>
diff --git a/arch/arm/plat-omap/ocpi.c b/arch/arm/mach-omap1/ocpi.c
index ebe0c73c8901..238170cab5b7 100644
--- a/arch/arm/plat-omap/ocpi.c
+++ b/arch/arm/mach-omap1/ocpi.c
@@ -4,6 +4,7 @@
 * Minimal OCP bus support for omap16xx
 *
 * Copyright (C) 2003 - 2005 Nokia Corporation
+ * Copyright (C) 2012 Texas Instruments, Inc.
 * Written by Tony Lindgren <tony@atomide.com>
 *
 * Modified for clock framework by Paul Mundt <paul.mundt@nokia.com>.
@@ -35,6 +36,8 @@
 #include <mach/hardware.h>
+#include "common.h"
 #define OCPI_BASE               0xfffec320
 #define OCPI_FAULT              (OCPI_BASE + 0x00)
 #define OCPI_CMD_FAULT          (OCPI_BASE + 0x04)
@@ -64,7 +67,7 @@ int ocpi_enable(void)
        /* Enable access for OHCI in OCPI */
        val = omap_readl(OCPI_PROT);
        val &= ~0xff;
-        //val &= (1 << 0);      /* Allow access only to EMIFS */
+        /* val &= (1 << 0);      Allow access only to EMIFS */
        omap_writel(val, OCPI_PROT);
        val = omap_readl(OCPI_SEC);
@@ -86,7 +89,7 @@ static int __init omap_ocpi_init(void)
        clk_enable(ocpi_ck);
        ocpi_enable();
-        printk("OMAP OCPI interconnect driver loaded\n");
+        pr_info("OMAP OCPI interconnect driver loaded\n");
        return 0;
 }
diff --git a/arch/arm/mach-omap1/pm.c b/arch/arm/mach-omap1/pm.c
index f66c32912b22..b2560d32b3a0 100644
--- a/arch/arm/mach-omap1/pm.c
+++ b/arch/arm/mach-omap1/pm.c
@@ -569,11 +569,10 @@ static int omap_pm_read_proc(
 static void omap_pm_init_proc(void)
 {
-        struct proc_dir_entry *entry;
+        /* XXX Appears to leak memory */
+        create_proc_read_entry("driver/omap_pm",
-        entry = create_proc_read_entry("driver/omap_pm",
+                               S_IWUSR | S_IRUGO, NULL,
-                                       S_IWUSR | S_IRUGO, NULL,
+                               omap_pm_read_proc, NULL);
-                                       omap_pm_read_proc, NULL);
 }
 #endif /* DEBUG && CONFIG_PROC_FS */
diff --git a/arch/arm/mach-omap1/reset.c b/arch/arm/mach-omap1/reset.c
index f255b153b863..b17709103866 100644
--- a/arch/arm/mach-omap1/reset.c
+++ b/arch/arm/mach-omap1/reset.c
@@ -8,6 +8,8 @@
 #include <mach/hardware.h>
+#include "common.h"
 void omap1_restart(char mode, const char *cmd)
 {
        /*
diff --git a/arch/arm/mach-omap1/timer.c b/arch/arm/mach-omap1/timer.c
index 6e90665a7c47..64c65bcb2d67 100644
--- a/arch/arm/mach-omap1/timer.c
+++ b/arch/arm/mach-omap1/timer.c
@@ -47,15 +47,14 @@ static int omap1_dm_timer_set_src(struct platform_device *pdev,
        int n = (pdev->id - 1) << 1;
        u32 l;
-        l = __raw_readl(MOD_CONF_CTRL_1) & ~(0x03 << n);
+        l = omap_readl(MOD_CONF_CTRL_1) & ~(0x03 << n);
        l |= source << n;
-        __raw_writel(l, MOD_CONF_CTRL_1);
+        omap_writel(l, MOD_CONF_CTRL_1);
        return 0;
 }
+static int __init omap1_dm_timer_init(void)
-int __init omap1_dm_timer_init(void)
 {
        int i;
        int ret;
diff --git a/arch/arm/mach-omap1/usb.c b/arch/arm/mach-omap1/usb.c
index 19de03b074e3..e61afd922766 100644
--- a/arch/arm/mach-omap1/usb.c
+++ b/arch/arm/mach-omap1/usb.c
@@ -29,6 +29,8 @@
 #include <plat/mux.h>
 #include <plat/usb.h>
+#include "common.h"
 /* These routines should handle the standard chip-specific modes
 * for usb0/1/2 ports, covering basic mux and transceiver setup.
 *
@@ -138,6 +140,7 @@ static inline void ohci_device_init(struct omap_usb_config *pdata)
        if (cpu_is_omap7xx())
                ohci_resources[1].start = INT_7XX_USB_HHC_1;
        pdata->ohci_device = &ohci_device;
+        pdata->ocpi_enable = &ocpi_enable;
 }
 #else
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 8141b76283a6..964ee67a3b77 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -17,6 +17,7 @@ config ARCH_OMAP2PLUS_TYPICAL
        select MENELAUS if ARCH_OMAP2
        select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4
        select TWL4030_POWER if ARCH_OMAP3 || ARCH_OMAP4
+        select HIGHMEM
        help
          Compile a kernel suitable for booting most boards
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 49f92bc1c311..385c083d24b2 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -4,7 +4,7 @@
 # Common support
 obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer.o pm.o \
-         common.o gpio.o dma.o wd_timer.o display.o i2c.o
+         common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o
 omap-2-3-common                         = irq.o sdrc.o
 hwmod-common                            = omap_hwmod.o \
@@ -118,16 +118,18 @@ obj-$(CONFIG_ARCH_OMAP4)		+= $(powerdomain-common) \
                                           powerdomains44xx_data.o
 # PRCM clockdomain control
-obj-$(CONFIG_ARCH_OMAP2)                += clockdomain.o \
+clockdomain-common                      += clockdomain.o \
+                                           clockdomains_common_data.o
+obj-$(CONFIG_ARCH_OMAP2)                += $(clockdomain-common) \
                                           clockdomain2xxx_3xxx.o \
                                           clockdomains2xxx_3xxx_data.o
 obj-$(CONFIG_SOC_OMAP2420)              += clockdomains2420_data.o
 obj-$(CONFIG_SOC_OMAP2430)              += clockdomains2430_data.o
-obj-$(CONFIG_ARCH_OMAP3)                += clockdomain.o \
+obj-$(CONFIG_ARCH_OMAP3)                += $(clockdomain-common) \
                                           clockdomain2xxx_3xxx.o \
                                           clockdomains2xxx_3xxx_data.o \
                                           clockdomains3xxx_data.o
-obj-$(CONFIG_ARCH_OMAP4)                += clockdomain.o \
+obj-$(CONFIG_ARCH_OMAP4)                += $(clockdomain-common) \
                                           clockdomain44xx.o \
                                           clockdomains44xx_data.o
@@ -187,6 +189,9 @@ ifneq ($(CONFIG_TIDSPBRIDGE),)
 obj-y                                   += dsp.o
 endif
+# OMAP2420 MSDI controller integration support ("MMC")
+obj-$(CONFIG_SOC_OMAP2420)              += msdi.o
 # Specific board support
 obj-$(CONFIG_MACH_OMAP_GENERIC)         += board-generic.o
 obj-$(CONFIG_MACH_OMAP_H4)              += board-h4.o
diff --git a/arch/arm/mach-omap2/am35xx-emac.c b/arch/arm/mach-omap2/am35xx-emac.c
index 1f97e7475206..447682c4e11c 100644
--- a/arch/arm/mach-omap2/am35xx-emac.c
+++ b/arch/arm/mach-omap2/am35xx-emac.c
@@ -39,26 +39,23 @@ static struct platform_device am35xx_emac_mdio_device = {
 static void am35xx_enable_emac_int(void)
 {
-        u32 regval;
+        u32 v;
-        regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
+        v = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
-        regval = (regval | AM35XX_CPGMAC_C0_RX_PULSE_CLR |
+        v |= (AM35XX_CPGMAC_C0_RX_PULSE_CLR | AM35XX_CPGMAC_C0_TX_PULSE_CLR |
-                  AM35XX_CPGMAC_C0_TX_PULSE_CLR |
+              AM35XX_CPGMAC_C0_MISC_PULSE_CLR | AM35XX_CPGMAC_C0_RX_THRESH_CLR);
-                  AM35XX_CPGMAC_C0_MISC_PULSE_CLR |
+        omap_ctrl_writel(v, AM35XX_CONTROL_LVL_INTR_CLEAR);
-                  AM35XX_CPGMAC_C0_RX_THRESH_CLR);
+        omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); /* OCP barrier */
-        omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR);
-        regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
 }
 static void am35xx_disable_emac_int(void)
 {
-        u32 regval;
+        u32 v;
-        regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
+        v = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
-        regval = (regval | AM35XX_CPGMAC_C0_RX_PULSE_CLR |
+        v |= (AM35XX_CPGMAC_C0_RX_PULSE_CLR | AM35XX_CPGMAC_C0_TX_PULSE_CLR);
-                  AM35XX_CPGMAC_C0_TX_PULSE_CLR);
+        omap_ctrl_writel(v, AM35XX_CONTROL_LVL_INTR_CLEAR);
-        omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR);
+        omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); /* OCP barrier */
-        regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
 }
 static struct emac_platform_data am35xx_emac_pdata = {
@@ -92,7 +89,7 @@ static struct platform_device am35xx_emac_device = {
 void __init am35xx_emac_init(unsigned long mdio_bus_freq, u8 rmii_en)
 {
-        unsigned int regval;
+        u32 v;
        int err;
        am35xx_emac_pdata.rmii_en = rmii_en;
@@ -110,8 +107,8 @@ void __init am35xx_emac_init(unsigned long mdio_bus_freq, u8 rmii_en)
                return;
        }
-        regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
+        v = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
-        regval = regval & (~(AM35XX_CPGMACSS_SW_RST));
+        v &= ~AM35XX_CPGMACSS_SW_RST;
-        omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET);
+        omap_ctrl_writel(v, AM35XX_CONTROL_IP_SW_RESET);
-        regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
+        omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); /* OCP barrier */
 }
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index da75f239873e..37abb0d49b51 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -37,7 +37,7 @@
 #include <plat/dma.h>
 #include <plat/gpmc.h>
 #include <video/omapdss.h>
-#include <video/omap-panel-dvi.h>
+#include <video/omap-panel-tfp410.h>
 #include <plat/gpmc-smc91x.h>
@@ -113,9 +113,6 @@ static struct gpio sdp3430_dss_gpios[] __initdata = {
        {SDP3430_LCD_PANEL_BACKLIGHT_GPIO, GPIOF_OUT_INIT_LOW, "LCD Backlight"},
 };
-static int lcd_enabled;
-static int dvi_enabled;
 static void __init sdp3430_display_init(void)
 {
        int r;
@@ -129,44 +126,18 @@ static void __init sdp3430_display_init(void)
 static int sdp3430_panel_enable_lcd(struct omap_dss_device *dssdev)
 {
-        if (dvi_enabled) {
-                printk(KERN_ERR "cannot enable LCD, DVI is enabled\n");
-                return -EINVAL;
-        }
        gpio_direction_output(SDP3430_LCD_PANEL_ENABLE_GPIO, 1);
        gpio_direction_output(SDP3430_LCD_PANEL_BACKLIGHT_GPIO, 1);
-        lcd_enabled = 1;
        return 0;
 }
 static void sdp3430_panel_disable_lcd(struct omap_dss_device *dssdev)
 {
-        lcd_enabled = 0;
        gpio_direction_output(SDP3430_LCD_PANEL_ENABLE_GPIO, 0);
        gpio_direction_output(SDP3430_LCD_PANEL_BACKLIGHT_GPIO, 0);
 }
-static int sdp3430_panel_enable_dvi(struct omap_dss_device *dssdev)
-{
-        if (lcd_enabled) {
-                printk(KERN_ERR "cannot enable DVI, LCD is enabled\n");
-                return -EINVAL;
-        }
-        dvi_enabled = 1;
-        return 0;
-}
-static void sdp3430_panel_disable_dvi(struct omap_dss_device *dssdev)
-{
-        dvi_enabled = 0;
-}
 static int sdp3430_panel_enable_tv(struct omap_dss_device *dssdev)
 {
        return 0;
@@ -186,15 +157,14 @@ static struct omap_dss_device sdp3430_lcd_device = {
        .platform_disable       = sdp3430_panel_disable_lcd,
 };
-static struct panel_dvi_platform_data dvi_panel = {
+static struct tfp410_platform_data dvi_panel = {
-        .platform_enable        = sdp3430_panel_enable_dvi,
+        .power_down_gpio        = -1,
-        .platform_disable       = sdp3430_panel_disable_dvi,
 };
 static struct omap_dss_device sdp3430_dvi_device = {
        .name                   = "dvi",
        .type                   = OMAP_DISPLAY_TYPE_DPI,
-        .driver_name            = "dvi",
+        .driver_name            = "tfp410",
        .data                   = &dvi_panel,
        .phy.dpi.data_lines     = 24,
 };
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index a39fc4bbd2b8..94af6cde2e36 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -20,6 +20,7 @@
 #include <linux/usb/otg.h>
 #include <linux/spi/spi.h>
 #include <linux/i2c/twl.h>
+#include <linux/mfd/twl6040.h>
 #include <linux/gpio_keys.h>
 #include <linux/regulator/machine.h>
 #include <linux/regulator/fixed.h>
@@ -383,6 +384,11 @@ static struct platform_device sdp4430_dmic_codec = {
        .id     = -1,
 };
+static struct platform_device sdp4430_hdmi_audio_codec = {
+        .name   = "hdmi-audio-codec",
+        .id     = -1,
+};
 static struct omap_abe_twl6040_data sdp4430_abe_audio_data = {
        .card_name = "SDP4430",
        .has_hs         = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
@@ -417,6 +423,7 @@ static struct platform_device *sdp4430_devices[] __initdata = {
        &sdp4430_vbat,
        &sdp4430_dmic_codec,
        &sdp4430_abe_audio,
+        &sdp4430_hdmi_audio_codec,
 };
 static struct omap_musb_board_data musb_board_data = {
@@ -488,50 +495,6 @@ static struct platform_device omap_vwlan_device = {
        },
 };
-static int omap4_twl6030_hsmmc_late_init(struct device *dev)
-{
-        int irq = 0;
-        struct platform_device *pdev = container_of(dev,
-                                struct platform_device, dev);
-        struct omap_mmc_platform_data *pdata = dev->platform_data;
-        /* Setting MMC1 Card detect Irq */
-        if (pdev->id == 0) {
-                irq = twl6030_mmc_card_detect_config();
-                if (irq < 0) {
-                        pr_err("Failed configuring MMC1 card detect\n");
-                        return irq;
-                }
-                pdata->slots[0].card_detect_irq = irq;
-                pdata->slots[0].card_detect = twl6030_mmc_card_detect;
-        }
-        return 0;
-}
-static __init void omap4_twl6030_hsmmc_set_late_init(struct device *dev)
-{
-        struct omap_mmc_platform_data *pdata;
-        /* dev can be null if CONFIG_MMC_OMAP_HS is not set */
-        if (!dev) {
-                pr_err("Failed %s\n", __func__);
-                return;
-        }
-        pdata = dev->platform_data;
-        pdata->init =   omap4_twl6030_hsmmc_late_init;
-}
-static int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
-{
-        struct omap2_hsmmc_info *c;
-        omap_hsmmc_init(controllers);
-        for (c = controllers; c->mmc; c++)
-                omap4_twl6030_hsmmc_set_late_init(&c->pdev->dev);
-        return 0;
-}
 static struct regulator_init_data sdp4430_vaux1 = {
        .constraints = {
                .min_uV                 = 1000000,
@@ -560,7 +523,7 @@ static struct regulator_init_data sdp4430_vusim = {
        },
 };
-static struct twl4030_codec_data twl6040_codec = {
+static struct twl6040_codec_data twl6040_codec = {
        /* single-step ramp for headset and handsfree */
        .hs_left_step   = 0x0f,
        .hs_right_step  = 0x0f,
@@ -568,7 +531,7 @@ static struct twl4030_codec_data twl6040_codec = {
        .hf_right_step  = 0x1d,
 };
-static struct twl4030_vibra_data twl6040_vibra = {
+static struct twl6040_vibra_data twl6040_vibra = {
        .vibldrv_res = 8,
        .vibrdrv_res = 3,
        .viblmotor_res = 10,
@@ -577,16 +540,14 @@ static struct twl4030_vibra_data twl6040_vibra = {
        .vddvibr_uV = 0,        /* fixed volt supply - VBAT */
 };
-static struct twl4030_audio_data twl6040_audio = {
+static struct twl6040_platform_data twl6040_data = {
        .codec          = &twl6040_codec,
        .vibra          = &twl6040_vibra,
        .audpwron_gpio  = 127,
-        .naudint_irq    = OMAP44XX_IRQ_SYS_2N,
        .irq_base       = TWL6040_CODEC_IRQ_BASE,
 };
 static struct twl4030_platform_data sdp4430_twldata = {
-        .audio          = &twl6040_audio,
        /* Regulators */
        .vusim          = &sdp4430_vusim,
        .vaux1          = &sdp4430_vaux1,
@@ -616,8 +577,11 @@ static int __init omap4_i2c_init(void)
                        TWL_COMMON_REGULATOR_VANA |
                        TWL_COMMON_REGULATOR_VCXIO |
                        TWL_COMMON_REGULATOR_VUSB |
-                        TWL_COMMON_REGULATOR_CLK32KG);
+                        TWL_COMMON_REGULATOR_CLK32KG |
-        omap4_pmic_init("twl6030", &sdp4430_twldata);
+                        TWL_COMMON_REGULATOR_V1V8 |
+                        TWL_COMMON_REGULATOR_V2V1);
+        omap4_pmic_init("twl6030", &sdp4430_twldata,
+                        &twl6040_data, OMAP44XX_IRQ_SYS_2N);
        omap_register_i2c_bus(2, 400, NULL, 0);
        omap_register_i2c_bus(3, 400, sdp4430_i2c_3_boardinfo,
                                ARRAY_SIZE(sdp4430_i2c_3_boardinfo));
@@ -666,6 +630,10 @@ static struct nokia_dsi_panel_data dsi1_panel = {
                .use_ext_te     = false,
                .ext_te_gpio    = 101,
                .esd_interval   = 0,
+                .pin_config = {
+                        .num_pins       = 6,
+                        .pins           = { 0, 1, 2, 3, 4, 5 },
+                },
 };
 static struct omap_dss_device sdp4430_lcd_device = {
@@ -674,13 +642,6 @@ static struct omap_dss_device sdp4430_lcd_device = {
        .type                   = OMAP_DISPLAY_TYPE_DSI,
        .data                   = &dsi1_panel,
        .phy.dsi                = {
-                .clk_lane       = 1,
-                .clk_pol        = 0,
-                .data1_lane     = 2,
-                .data1_pol      = 0,
-                .data2_lane     = 3,
-                .data2_pol      = 0,
                .module         = 0,
        },
@@ -715,6 +676,10 @@ static struct nokia_dsi_panel_data dsi2_panel = {
                .use_ext_te     = false,
                .ext_te_gpio    = 103,
                .esd_interval   = 0,
+                .pin_config = {
+                        .num_pins       = 6,
+                        .pins           = { 0, 1, 2, 3, 4, 5 },
+                },
 };
 static struct omap_dss_device sdp4430_lcd2_device = {
@@ -723,12 +688,6 @@ static struct omap_dss_device sdp4430_lcd2_device = {
        .type                   = OMAP_DISPLAY_TYPE_DSI,
        .data                   = &dsi2_panel,
        .phy.dsi                = {
-                .clk_lane       = 1,
-                .clk_pol        = 0,
-                .data1_lane     = 2,
-                .data1_pol      = 0,
-                .data2_lane     = 3,
-                .data2_pol      = 0,
                .module         = 1,
        },
@@ -758,21 +717,6 @@ static struct omap_dss_device sdp4430_lcd2_device = {
        .channel                = OMAP_DSS_CHANNEL_LCD2,
 };
-static void sdp4430_lcd_init(void)
-{
-        int r;
-        r = gpio_request_one(dsi1_panel.reset_gpio, GPIOF_DIR_OUT,
-                "lcd1_reset_gpio");
-        if (r)
-                pr_err("%s: Could not get lcd1_reset_gpio\n", __func__);
-        r = gpio_request_one(dsi2_panel.reset_gpio, GPIOF_DIR_OUT,
-                "lcd2_reset_gpio");
-        if (r)
-                pr_err("%s: Could not get lcd2_reset_gpio\n", __func__);
-}
 static struct omap_dss_hdmi_data sdp4430_hdmi_data = {
        .hpd_gpio = HDMI_GPIO_HPD,
 };
@@ -858,7 +802,6 @@ static void __init omap_4430sdp_display_init(void)
        if (r)
                pr_err("%s: Could not get display_sel GPIO\n", __func__);
-        sdp4430_lcd_init();
        sdp4430_picodlp_init();
        omap_display_init(&sdp4430_dss_data);
        /*
diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c
index c3851e8de28b..3b8a53c1f2a8 100644
--- a/arch/arm/mach-omap2/board-am3517crane.c
+++ b/arch/arm/mach-omap2/board-am3517crane.c
@@ -30,6 +30,7 @@
 #include "common.h"
 #include <plat/usb.h>
+#include "am35xx-emac.h"
 #include "mux.h"
 #include "control.h"
@@ -90,6 +91,7 @@ static void __init am3517_crane_init(void)
        }
        usbhs_init(&usbhs_bdata);
+        am35xx_emac_init(AM35XX_DEFAULT_MDIO_FREQUENCY, 1);
 }
 MACHINE_START(CRANEBOARD, "AM3517/05 CRANEBOARD")
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index 3645285a3e2b..99790eb646e8 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -37,7 +37,7 @@
 #include <plat/usb.h>
 #include <video/omapdss.h>
 #include <video/omap-panel-generic-dpi.h>
-#include <video/omap-panel-dvi.h>
+#include <video/omap-panel-tfp410.h>
 #include "am35xx-emac.h"
 #include "mux.h"
@@ -207,31 +207,14 @@ static struct omap_dss_device am3517_evm_tv_device = {
        .platform_disable       = am3517_evm_panel_disable_tv,
 };
-static int am3517_evm_panel_enable_dvi(struct omap_dss_device *dssdev)
+static struct tfp410_platform_data dvi_panel = {
-{
+        .power_down_gpio        = -1,
-        if (lcd_enabled) {
-                printk(KERN_ERR "cannot enable DVI, LCD is enabled\n");
-                return -EINVAL;
-        }
-        dvi_enabled = 1;
-        return 0;
-}
-static void am3517_evm_panel_disable_dvi(struct omap_dss_device *dssdev)
-{
-        dvi_enabled = 0;
-}
-static struct panel_dvi_platform_data dvi_panel = {
-        .platform_enable        = am3517_evm_panel_enable_dvi,
-        .platform_disable       = am3517_evm_panel_disable_dvi,
 };
 static struct omap_dss_device am3517_evm_dvi_device = {
        .type                   = OMAP_DISPLAY_TYPE_DPI,
        .name                   = "dvi",
-        .driver_name            = "dvi",
+        .driver_name            = "tfp410",
        .data                   = &dvi_panel,
        .phy.dpi.data_lines     = 24,
 };
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index 909a8b91b564..c03df142ea67 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -44,7 +44,7 @@
 #include <plat/usb.h>
 #include <video/omapdss.h>
 #include <video/omap-panel-generic-dpi.h>
-#include <video/omap-panel-dvi.h>
+#include <video/omap-panel-tfp410.h>
 #include <plat/mcspi.h>
 #include <mach/hardware.h>
@@ -218,25 +218,6 @@ static void cm_t35_panel_disable_lcd(struct omap_dss_device *dssdev)
        gpio_set_value(CM_T35_LCD_EN_GPIO, 0);
 }
-static int cm_t35_panel_enable_dvi(struct omap_dss_device *dssdev)
-{
-        if (lcd_enabled) {
-                printk(KERN_ERR "cannot enable DVI, LCD is enabled\n");
-                return -EINVAL;
-        }
-        gpio_set_value(CM_T35_DVI_EN_GPIO, 0);
-        dvi_enabled = 1;
-        return 0;
-}
-static void cm_t35_panel_disable_dvi(struct omap_dss_device *dssdev)
-{
-        gpio_set_value(CM_T35_DVI_EN_GPIO, 1);
-        dvi_enabled = 0;
-}
 static int cm_t35_panel_enable_tv(struct omap_dss_device *dssdev)
 {
        return 0;
@@ -260,15 +241,14 @@ static struct omap_dss_device cm_t35_lcd_device = {
        .phy.dpi.data_lines     = 18,
 };
-static struct panel_dvi_platform_data dvi_panel = {
+static struct tfp410_platform_data dvi_panel = {
-        .platform_enable        = cm_t35_panel_enable_dvi,
+        .power_down_gpio        = CM_T35_DVI_EN_GPIO,
-        .platform_disable       = cm_t35_panel_disable_dvi,
 };
 static struct omap_dss_device cm_t35_dvi_device = {
        .name                   = "dvi",
        .type                   = OMAP_DISPLAY_TYPE_DPI,
-        .driver_name            = "dvi",
+        .driver_name            = "tfp410",
        .data                   = &dvi_panel,
        .phy.dpi.data_lines     = 24,
 };
@@ -316,7 +296,6 @@ static struct spi_board_info cm_t35_lcd_spi_board_info[] __initdata = {
 static struct gpio cm_t35_dss_gpios[] __initdata = {
        { CM_T35_LCD_EN_GPIO, GPIOF_OUT_INIT_LOW,  "lcd enable"    },
        { CM_T35_LCD_BL_GPIO, GPIOF_OUT_INIT_LOW,  "lcd bl enable" },
-        { CM_T35_DVI_EN_GPIO, GPIOF_OUT_INIT_HIGH, "dvi enable"    },
 };
 static void __init cm_t35_init_display(void)
@@ -335,7 +314,6 @@ static void __init cm_t35_init_display(void)
        gpio_export(CM_T35_LCD_EN_GPIO, 0);
        gpio_export(CM_T35_LCD_BL_GPIO, 0);
-        gpio_export(CM_T35_DVI_EN_GPIO, 0);
        msleep(50);
        gpio_set_value(CM_T35_LCD_EN_GPIO, 1);
@@ -498,6 +476,10 @@ static struct twl4030_gpio_platform_data cm_t35_gpio_data = {
        .setup          = cm_t35_twl_gpio_setup,
 };
+static struct twl4030_power_data cm_t35_power_data = {
+        .use_poweroff   = true,
+};
 static struct twl4030_platform_data cm_t35_twldata = {
        /* platform_data for children goes here */
        .keypad         = &cm_t35_kp_data,
@@ -505,6 +487,7 @@ static struct twl4030_platform_data cm_t35_twldata = {
        .vmmc1          = &cm_t35_vmmc1,
        .vsim           = &cm_t35_vsim,
        .vio            = &cm_t35_vio,
+        .power          = &cm_t35_power_data,
 };
 static void __init cm_t35_init_i2c(void)
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index a2010f07de31..b063f0d2faa6 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -47,7 +47,7 @@
 #include <plat/usb.h>
 #include <video/omapdss.h>
 #include <video/omap-panel-generic-dpi.h>
-#include <video/omap-panel-dvi.h>
+#include <video/omap-panel-tfp410.h>
 #include <plat/mcspi.h>
 #include <linux/input/matrix_keypad.h>
@@ -118,19 +118,6 @@ static void devkit8000_panel_disable_lcd(struct omap_dss_device *dssdev)
                gpio_set_value_cansleep(dssdev->reset_gpio, 0);
 }
-static int devkit8000_panel_enable_dvi(struct omap_dss_device *dssdev)
-{
-        if (gpio_is_valid(dssdev->reset_gpio))
-                gpio_set_value_cansleep(dssdev->reset_gpio, 1);
-        return 0;
-}
-static void devkit8000_panel_disable_dvi(struct omap_dss_device *dssdev)
-{
-        if (gpio_is_valid(dssdev->reset_gpio))
-                gpio_set_value_cansleep(dssdev->reset_gpio, 0);
-}
 static struct regulator_consumer_supply devkit8000_vmmc1_supply[] = {
        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
 };
@@ -154,15 +141,14 @@ static struct omap_dss_device devkit8000_lcd_device = {
        .phy.dpi.data_lines     = 24,
 };
-static struct panel_dvi_platform_data dvi_panel = {
+static struct tfp410_platform_data dvi_panel = {
-        .platform_enable        = devkit8000_panel_enable_dvi,
+        .power_down_gpio        = -1,
-        .platform_disable       = devkit8000_panel_disable_dvi,
 };
 static struct omap_dss_device devkit8000_dvi_device = {
        .name                   = "dvi",
        .type                   = OMAP_DISPLAY_TYPE_DPI,
-        .driver_name            = "dvi",
+        .driver_name            = "tfp410",
        .data                   = &dvi_panel,
        .phy.dpi.data_lines     = 24,
 };
@@ -244,13 +230,7 @@ static int devkit8000_twl_gpio_setup(struct device *dev,
        }
        /* gpio + 7 is "DVI_PD" (out, active low) */
-        devkit8000_dvi_device.reset_gpio = gpio + 7;
+        dvi_panel.power_down_gpio = gpio + 7;
-        ret = gpio_request_one(devkit8000_dvi_device.reset_gpio,
-                               GPIOF_OUT_INIT_LOW, "DVI PowerDown");
-        if (ret < 0) {
-                devkit8000_dvi_device.reset_gpio = -EINVAL;
-                printk(KERN_ERR "Failed to request GPIO for DVI PowerDown\n");
-        }
        return 0;
 }
diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c
index 0349fd2b68d8..70a81f900bb5 100644
--- a/arch/arm/mach-omap2/board-flash.c
+++ b/arch/arm/mach-omap2/board-flash.c
@@ -87,7 +87,7 @@ static struct omap_onenand_platform_data board_onenand_data = {
        .dma_channel    = -1,   /* disable DMA in OMAP OneNAND driver */
 };
-static void
+void
 __init board_onenand_init(struct mtd_partition *onenand_parts,
                                u8 nr_parts, u8 cs)
 {
@@ -98,7 +98,7 @@ __init board_onenand_init(struct mtd_partition *onenand_parts,
        gpmc_onenand_init(&board_onenand_data);
 }
 #else
-static void
+void
 __init board_onenand_init(struct mtd_partition *nor_parts, u8 nr_parts, u8 cs)
 {
 }
diff --git a/arch/arm/mach-omap2/board-flash.h b/arch/arm/mach-omap2/board-flash.h
index d25503a98417..c44b70d52021 100644
--- a/arch/arm/mach-omap2/board-flash.h
+++ b/arch/arm/mach-omap2/board-flash.h
@@ -47,3 +47,14 @@ static inline void board_nand_init(struct mtd_partition *nand_parts,
 {
 }
 #endif
+#if defined(CONFIG_MTD_ONENAND_OMAP2) || \
+                defined(CONFIG_MTD_ONENAND_OMAP2_MODULE)
+extern void board_onenand_init(struct mtd_partition *nand_parts,
+                                        u8 nr_parts, u8 cs);
+#else
+static inline void board_onenand_init(struct mtd_partition *nand_parts,
+                                        u8 nr_parts, u8 cs)
+{
+}
+#endif
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 74e1687b5170..7302ba7ff1b9 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -15,7 +15,6 @@
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/irqdomain.h>
-#include <linux/i2c/twl.h>
 #include <mach/hardware.h>
 #include <asm/hardware/gic.h>
@@ -95,22 +94,6 @@ MACHINE_END
 #endif
 #ifdef CONFIG_ARCH_OMAP3
-static struct twl4030_platform_data beagle_twldata = {
-        .irq_base       = TWL4030_IRQ_BASE,
-        .irq_end        = TWL4030_IRQ_END,
-};
-static void __init omap3_i2c_init(void)
-{
-        omap3_pmic_init("twl4030", &beagle_twldata);
-}
-static void __init omap3_init(void)
-{
-        omap3_i2c_init();
-        omap_generic_init();
-}
 static const char *omap3_boards_compat[] __initdata = {
        "ti,omap3",
        NULL,
@@ -122,7 +105,7 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)")
        .init_early     = omap3430_init_early,
        .init_irq       = omap_init_irq,
        .handle_irq     = omap3_intc_handle_irq,
-        .init_machine   = omap3_init,
+        .init_machine   = omap_generic_init,
        .timer          = &omap3_timer,
        .dt_compat      = omap3_boards_compat,
        .restart        = omap_prcm_restart,
@@ -130,22 +113,6 @@ MACHINE_END
 #endif
 #ifdef CONFIG_ARCH_OMAP4
-static struct twl4030_platform_data sdp4430_twldata = {
-        .irq_base       = TWL6030_IRQ_BASE,
-        .irq_end        = TWL6030_IRQ_END,
-};
-static void __init omap4_i2c_init(void)
-{
-        omap4_pmic_init("twl6030", &sdp4430_twldata);
-}
-static void __init omap4_init(void)
-{
-        omap4_i2c_init();
-        omap_generic_init();
-}
 static const char *omap4_boards_compat[] __initdata = {
        "ti,omap4",
        NULL,
@@ -157,7 +124,7 @@ DT_MACHINE_START(OMAP4_DT, "Generic OMAP4 (Flattened Device Tree)")
        .init_early     = omap4430_init_early,
        .init_irq       = omap_init_irq,
        .handle_irq     = gic_handle_irq,
-        .init_machine   = omap4_init,
+        .init_machine   = omap_generic_init,
        .timer          = &omap4_timer,
        .dt_compat      = omap4_boards_compat,
        .restart        = omap_prcm_restart,
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index 930c0d380435..7a274098f67b 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -24,6 +24,8 @@
 #include <linux/i2c/twl.h>
 #include <linux/mmc/host.h>
+#include <linux/mtd/nand.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -32,13 +34,15 @@
 #include <plat/gpmc.h>
 #include <plat/usb.h>
 #include <video/omapdss.h>
-#include <video/omap-panel-dvi.h>
+#include <video/omap-panel-tfp410.h>
 #include <plat/onenand.h>
 #include "mux.h"
 #include "hsmmc.h"
 #include "sdram-numonyx-m65kxxxxam.h"
 #include "common-board-devices.h"
+#include "board-flash.h"
+#include "control.h"
 #define IGEP2_SMSC911X_CS       5
 #define IGEP2_SMSC911X_GPIO     176
@@ -60,6 +64,10 @@
 #define IGEP3_GPIO_LED1_RED     16
 #define IGEP3_GPIO_USBH_NRESET  183
+#define IGEP_SYSBOOT_MASK           0x1f
+#define IGEP_SYSBOOT_NAND           0x0f
+#define IGEP_SYSBOOT_ONENAND        0x10
 /*
 * IGEP2 Hardware Revision Table
 *
@@ -110,8 +118,10 @@ static void __init igep2_get_revision(void)
        gpio_free(IGEP2_GPIO_LED1_RED);
 }
-#if defined(CONFIG_MTD_ONENAND_OMAP2) || \
+#if defined(CONFIG_MTD_ONENAND_OMAP2) ||                \
-        defined(CONFIG_MTD_ONENAND_OMAP2_MODULE)
+        defined(CONFIG_MTD_ONENAND_OMAP2_MODULE) ||     \
+        defined(CONFIG_MTD_NAND_OMAP2) ||               \
+        defined(CONFIG_MTD_NAND_OMAP2_MODULE)
 #define ONENAND_MAP             0x20000000
@@ -123,7 +133,7 @@ static void __init igep2_get_revision(void)
 * So MTD regards it as 4KiB page size and 256KiB block size 64*(2*2048)
 */
-static struct mtd_partition igep_onenand_partitions[] = {
+static struct mtd_partition igep_flash_partitions[] = {
        {
                .name           = "X-Loader",
                .offset         = 0,
@@ -151,50 +161,28 @@ static struct mtd_partition igep_onenand_partitions[] = {
        },
 };
-static struct omap_onenand_platform_data igep_onenand_data = {
+static inline u32 igep_get_sysboot_value(void)
-        .parts = igep_onenand_partitions,
+{
-        .nr_parts = ARRAY_SIZE(igep_onenand_partitions),
+        return omap_ctrl_readl(OMAP343X_CONTROL_STATUS) & IGEP_SYSBOOT_MASK;
-        .dma_channel    = -1,   /* disable DMA in OMAP OneNAND driver */
+}
-};
-static struct platform_device igep_onenand_device = {
-        .name           = "omap2-onenand",
-        .id             = -1,
-        .dev = {
-                .platform_data = &igep_onenand_data,
-        },
-};
 static void __init igep_flash_init(void)
 {
-        u8 cs = 0;
+        u32 mux;
-        u8 onenandcs = GPMC_CS_NUM + 1;
+        mux = igep_get_sysboot_value();
-        for (cs = 0; cs < GPMC_CS_NUM; cs++) {
+        if (mux == IGEP_SYSBOOT_NAND) {
-                u32 ret;
+                pr_info("IGEP: initializing NAND memory device\n");
-                ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
+                board_nand_init(igep_flash_partitions,
+                                ARRAY_SIZE(igep_flash_partitions),
-                /* Check if NAND/oneNAND is configured */
+                                0, NAND_BUSWIDTH_16);
-                if ((ret & 0xC00) == 0x800)
+        } else if (mux == IGEP_SYSBOOT_ONENAND) {
-                        /* NAND found */
+                pr_info("IGEP: initializing OneNAND memory device\n");
-                        pr_err("IGEP: Unsupported NAND found\n");
+                board_onenand_init(igep_flash_partitions,
-                else {
+                                   ARRAY_SIZE(igep_flash_partitions), 0);
-                        ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
+        } else {
-                        if ((ret & 0x3F) == (ONENAND_MAP >> 24))
+                pr_err("IGEP: Flash: unsupported sysboot sequence found\n");
-                                /* ONENAND found */
-                                onenandcs = cs;
-                }
-        }
-        if (onenandcs > GPMC_CS_NUM) {
-                pr_err("IGEP: Unable to find configuration in GPMC\n");
-                return;
        }
-        igep_onenand_data.cs = onenandcs;
-        if (platform_device_register(&igep_onenand_device) < 0)
-                pr_err("IGEP: Unable to register OneNAND device\n");
 }
 #else
@@ -444,28 +432,15 @@ static struct twl4030_gpio_platform_data igep_twl4030_gpio_pdata = {
        .setup          = igep_twl_gpio_setup,
 };
-static int igep2_enable_dvi(struct omap_dss_device *dssdev)
+static struct tfp410_platform_data dvi_panel = {
-{
+        .i2c_bus_num            = 3,
-        gpio_direction_output(IGEP2_GPIO_DVI_PUP, 1);
+        .power_down_gpio        = IGEP2_GPIO_DVI_PUP,
-        return 0;
-}
-static void igep2_disable_dvi(struct omap_dss_device *dssdev)
-{
-        gpio_direction_output(IGEP2_GPIO_DVI_PUP, 0);
-}
-static struct panel_dvi_platform_data dvi_panel = {
-        .platform_enable        = igep2_enable_dvi,
-        .platform_disable       = igep2_disable_dvi,
-        .i2c_bus_num = 3,
 };
 static struct omap_dss_device igep2_dvi_device = {
        .type                   = OMAP_DISPLAY_TYPE_DPI,
        .name                   = "dvi",
-        .driver_name            = "dvi",
+        .driver_name            = "tfp410",
        .data                   = &dvi_panel,
        .phy.dpi.data_lines     = 24,
 };
@@ -480,14 +455,6 @@ static struct omap_dss_board_info igep2_dss_data = {
        .default_device = &igep2_dvi_device,
 };
-static void __init igep2_display_init(void)
-{
-        int err = gpio_request_one(IGEP2_GPIO_DVI_PUP, GPIOF_OUT_INIT_HIGH,
-                                   "GPIO_DVI_PUP");
-        if (err)
-                pr_err("IGEP v2: Could not obtain gpio GPIO_DVI_PUP\n");
-}
 static struct platform_device *igep_devices[] __initdata = {
        &igep_vwlan_device,
 };
@@ -540,7 +507,10 @@ static void __init igep_i2c_init(void)
 {
        int ret;
-        omap3_pmic_get_config(&igep_twldata, TWL_COMMON_PDATA_USB, 0);
+        omap3_pmic_get_config(&igep_twldata, TWL_COMMON_PDATA_USB,
+                              TWL_COMMON_REGULATOR_VPLL2);
+        igep_twldata.vpll2->constraints.apply_uV = true;
+        igep_twldata.vpll2->constraints.name = "VDVI";
        if (machine_is_igep0020()) {
                /*
@@ -554,10 +524,7 @@ static void __init igep_i2c_init(void)
                igep_twldata.keypad     = &igep2_keypad_pdata;
                /* Get common pmic data */
-                omap3_pmic_get_config(&igep_twldata, TWL_COMMON_PDATA_AUDIO,
+                omap3_pmic_get_config(&igep_twldata, TWL_COMMON_PDATA_AUDIO, 0);
-                                      TWL_COMMON_REGULATOR_VPLL2);
-                igep_twldata.vpll2->constraints.apply_uV = true;
-                igep_twldata.vpll2->constraints.name = "VDVI";
        }
        omap3_pmic_init("twl4030", &igep_twldata);
@@ -641,7 +608,7 @@ static struct regulator_consumer_supply dummy_supplies[] = {
 static void __init igep_init(void)
 {
-        regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
+        regulator_register_fixed(1, dummy_supplies, ARRAY_SIZE(dummy_supplies));
        omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
        /* Get IGEP2 hardware revision */
@@ -668,7 +635,6 @@ static void __init igep_init(void)
        if (machine_is_igep0020()) {
                omap_display_init(&igep2_dss_data);
-                igep2_display_init();
                igep2_init_smsc911x();
                usbhs_init(&igep2_usbhs_bdata);
        } else {
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 7be8d659d91d..2a7b9a9da1db 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -42,7 +42,7 @@
 #include <plat/board.h>
 #include "common.h"
 #include <video/omapdss.h>
-#include <video/omap-panel-dvi.h>
+#include <video/omap-panel-tfp410.h>
 #include <plat/gpmc.h>
 #include <plat/nand.h>
 #include <plat/usb.h>
@@ -83,11 +83,13 @@ static struct {
        int usb_pwr_level;
        int reset_gpio;
        int usr_button_gpio;
+        int mmc_caps;
 } beagle_config = {
        .mmc1_gpio_wp = -EINVAL,
        .usb_pwr_level = GPIOF_OUT_INIT_LOW,
        .reset_gpio = 129,
        .usr_button_gpio = 4,
+        .mmc_caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
 };
 static struct gpio omap3_beagle_rev_gpios[] __initdata = {
@@ -145,10 +147,12 @@ static void __init omap3_beagle_init_rev(void)
                printk(KERN_INFO "OMAP3 Beagle Rev: xM Ax/Bx\n");
                omap3_beagle_version = OMAP3BEAGLE_BOARD_XM;
                beagle_config.usb_pwr_level = GPIOF_OUT_INIT_HIGH;
+                beagle_config.mmc_caps &= ~MMC_CAP_8_BIT_DATA;
                break;
        case 2:
                printk(KERN_INFO "OMAP3 Beagle Rev: xM C\n");
                omap3_beagle_version = OMAP3BEAGLE_BOARD_XMC;
+                beagle_config.mmc_caps &= ~MMC_CAP_8_BIT_DATA;
                break;
        default:
                printk(KERN_INFO "OMAP3 Beagle Rev: unknown %hd\n", beagle_rev);
@@ -189,33 +193,17 @@ static struct mtd_partition omap3beagle_nand_partitions[] = {
 /* DSS */
-static int beagle_enable_dvi(struct omap_dss_device *dssdev)
+static struct tfp410_platform_data dvi_panel = {
-{
-        if (gpio_is_valid(dssdev->reset_gpio))
-                gpio_set_value(dssdev->reset_gpio, 1);
-        return 0;
-}
-static void beagle_disable_dvi(struct omap_dss_device *dssdev)
-{
-        if (gpio_is_valid(dssdev->reset_gpio))
-                gpio_set_value(dssdev->reset_gpio, 0);
-}
-static struct panel_dvi_platform_data dvi_panel = {
-        .platform_enable = beagle_enable_dvi,
-        .platform_disable = beagle_disable_dvi,
        .i2c_bus_num = 3,
+        .power_down_gpio = -1,
 };
 static struct omap_dss_device beagle_dvi_device = {
        .type = OMAP_DISPLAY_TYPE_DPI,
        .name = "dvi",
-        .driver_name = "dvi",
+        .driver_name = "tfp410",
        .data = &dvi_panel,
        .phy.dpi.data_lines = 24,
-        .reset_gpio = -EINVAL,
 };
 static struct omap_dss_device beagle_tv_device = {
@@ -236,22 +224,12 @@ static struct omap_dss_board_info beagle_dss_data = {
        .default_device = &beagle_dvi_device,
 };
-static void __init beagle_display_init(void)
-{
-        int r;
-        r = gpio_request_one(beagle_dvi_device.reset_gpio, GPIOF_OUT_INIT_LOW,
-                             "DVI reset");
-        if (r < 0)
-                printk(KERN_ERR "Unable to get DVI reset GPIO\n");
-}
 #include "sdram-micron-mt46h32m32lf-6.h"
 static struct omap2_hsmmc_info mmc[] = {
        {
                .mmc            = 1,
-                .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
+                .caps           = MMC_CAP_4_BIT_DATA,
                .gpio_wp        = -EINVAL,
                .deferred       = true,
        },
@@ -309,7 +287,7 @@ static int beagle_twl_gpio_setup(struct device *dev,
                if (gpio_request_one(gpio + 1, GPIOF_IN, "EHCI_nOC"))
                        pr_err("%s: unable to configure EHCI_nOC\n", __func__);
        }
-        beagle_dvi_device.reset_gpio = beagle_config.reset_gpio;
+        dvi_panel.power_down_gpio = beagle_config.reset_gpio;
        gpio_request_one(gpio + TWL4030_GPIO_MAX, beagle_config.usb_pwr_level,
                        "nEN_USB_PWR");
@@ -523,6 +501,7 @@ static void __init omap3_beagle_init(void)
        if (beagle_config.mmc1_gpio_wp != -EINVAL)
                omap_mux_init_gpio(beagle_config.mmc1_gpio_wp, OMAP_PIN_INPUT);
+        mmc[0].caps = beagle_config.mmc_caps;
        omap_hsmmc_init(mmc);
        omap3_beagle_i2c_init();
@@ -552,7 +531,6 @@ static void __init omap3_beagle_init(void)
        omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
        omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
-        beagle_display_init();
        beagle_opp_init();
 }
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index 49df12735b41..ace3c675e9c2 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -46,7 +46,7 @@
 #include "common.h"
 #include <plat/mcspi.h>
 #include <video/omapdss.h>
-#include <video/omap-panel-dvi.h>
+#include <video/omap-panel-tfp410.h>
 #include "mux.h"
 #include "sdram-micron-mt46h32m32lf-6.h"
@@ -219,35 +219,14 @@ static struct omap_dss_device omap3_evm_tv_device = {
        .platform_disable       = omap3_evm_disable_tv,
 };
-static int omap3_evm_enable_dvi(struct omap_dss_device *dssdev)
+static struct tfp410_platform_data dvi_panel = {
-{
+        .power_down_gpio        = OMAP3EVM_DVI_PANEL_EN_GPIO,
-        if (lcd_enabled) {
-                printk(KERN_ERR "cannot enable DVI, LCD is enabled\n");
-                return -EINVAL;
-        }
-        gpio_set_value_cansleep(OMAP3EVM_DVI_PANEL_EN_GPIO, 1);
-        dvi_enabled = 1;
-        return 0;
-}
-static void omap3_evm_disable_dvi(struct omap_dss_device *dssdev)
-{
-        gpio_set_value_cansleep(OMAP3EVM_DVI_PANEL_EN_GPIO, 0);
-        dvi_enabled = 0;
-}
-static struct panel_dvi_platform_data dvi_panel = {
-        .platform_enable        = omap3_evm_enable_dvi,
-        .platform_disable       = omap3_evm_disable_dvi,
 };
 static struct omap_dss_device omap3_evm_dvi_device = {
        .name                   = "dvi",
        .type                   = OMAP_DISPLAY_TYPE_DPI,
-        .driver_name            = "dvi",
+        .driver_name            = "tfp410",
        .data                   = &dvi_panel,
        .phy.dpi.data_lines     = 24,
 };
@@ -630,13 +609,13 @@ static struct regulator_consumer_supply dummy_supplies[] = {
 static void __init omap3_evm_init(void)
 {
+        struct omap_board_mux *obm;
        omap3_evm_get_revision();
        regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
-        if (cpu_is_omap3630())
+        obm = (cpu_is_omap3630()) ? omap36x_board_mux : omap35x_board_mux;
-                omap3_mux_init(omap36x_board_mux, OMAP_PACKAGE_CBB);
+        omap3_mux_init(obm, OMAP_PACKAGE_CBB);
-        else
-                omap3_mux_init(omap35x_board_mux, OMAP_PACKAGE_CBB);
        omap_board_config = omap3_evm_config;
        omap_board_config_size = ARRAY_SIZE(omap3_evm_config);
diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c
index 9b3c141ff51b..c008bf8e1c36 100644
--- a/arch/arm/mach-omap2/board-omap3logic.c
+++ b/arch/arm/mach-omap2/board-omap3logic.c
@@ -4,8 +4,9 @@
 * Copyright (C) 2010 Li-Pro.Net
 * Stephan Linz <linz@li-pro.net>
 *
- * Copyright (C) 2010 Logic Product Development, Inc.
+ * Copyright (C) 2010-2012 Logic Product Development, Inc.
 * Peter Barada <peter.barada@logicpd.com>
+ * Ashwin BIhari <ashwin.bihari@logicpd.com>
 *
 * Modified from Beagle, EVM, and RX51
 *
@@ -45,6 +46,7 @@
 #include <plat/gpmc-smsc911x.h>
 #include <plat/gpmc.h>
 #include <plat/sdrc.h>
+#include <plat/usb.h>
 #define OMAP3LOGIC_SMSC911X_CS                  1
@@ -85,6 +87,11 @@ static struct twl4030_gpio_platform_data omap3logic_gpio_data = {
                        | BIT(13) | BIT(15) | BIT(16) | BIT(17),
 };
+static struct twl4030_usb_data omap3logic_usb_data = {
+        .usb_mode       = T2_USB_MODE_ULPI,
+};
 static struct twl4030_platform_data omap3logic_twldata = {
        .irq_base       = TWL4030_IRQ_BASE,
        .irq_end        = TWL4030_IRQ_END,
@@ -92,6 +99,7 @@ static struct twl4030_platform_data omap3logic_twldata = {
        /* platform_data for children goes here */
        .gpio           = &omap3logic_gpio_data,
        .vmmc1          = &omap3logic_vmmc1,
+        .usb            = &omap3logic_usb_data,
 };
 static int __init omap3logic_i2c_init(void)
@@ -185,6 +193,20 @@ static inline void __init board_smsc911x_init(void)
 #ifdef CONFIG_OMAP_MUX
 static struct omap_board_mux board_mux[] __initdata = {
+        /* mUSB */
+        OMAP3_MUX(HSUSB0_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP3_MUX(HSUSB0_STP, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
+        OMAP3_MUX(HSUSB0_DIR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP3_MUX(HSUSB0_NXT, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP3_MUX(HSUSB0_DATA0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP3_MUX(HSUSB0_DATA1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP3_MUX(HSUSB0_DATA2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP3_MUX(HSUSB0_DATA3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP3_MUX(HSUSB0_DATA4, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP3_MUX(HSUSB0_DATA5, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP3_MUX(HSUSB0_DATA6, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP3_MUX(HSUSB0_DATA7, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
        { .reg_offset = OMAP_MUX_TERMINATOR },
 };
 #endif
@@ -205,6 +227,8 @@ static void __init omap3logic_init(void)
        board_mmc_init();
        board_smsc911x_init();
+        usb_musb_init(NULL);
        /* Ensure SDRC pins are mux'd for self-refresh */
        omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
        omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
index 4dffc95bddd2..4396bae91677 100644
--- a/arch/arm/mach-omap2/board-omap3stalker.c
+++ b/arch/arm/mach-omap2/board-omap3stalker.c
@@ -42,7 +42,7 @@
 #include <plat/usb.h>
 #include <video/omapdss.h>
 #include <video/omap-panel-generic-dpi.h>
-#include <video/omap-panel-dvi.h>
+#include <video/omap-panel-tfp410.h>
 #include <plat/mcspi.h>
 #include <linux/input/matrix_keypad.h>
@@ -92,9 +92,6 @@ static inline void __init omap3stalker_init_eth(void)
 #define LCD_PANEL_BKLIGHT_GPIO  210
 #define ENABLE_VPLL2_DEV_GRP    0xE0
-static int lcd_enabled;
-static int dvi_enabled;
 static void __init omap3_stalker_display_init(void)
 {
        return;
@@ -122,32 +119,14 @@ static struct omap_dss_device omap3_stalker_tv_device = {
        .platform_disable       = omap3_stalker_disable_tv,
 };
-static int omap3_stalker_enable_dvi(struct omap_dss_device *dssdev)
+static struct tfp410_platform_data dvi_panel = {
-{
+        .power_down_gpio        = DSS_ENABLE_GPIO,
-        if (lcd_enabled) {
-                printk(KERN_ERR "cannot enable DVI, LCD is enabled\n");
-                return -EINVAL;
-        }
-        gpio_set_value(DSS_ENABLE_GPIO, 1);
-        dvi_enabled = 1;
-        return 0;
-}
-static void omap3_stalker_disable_dvi(struct omap_dss_device *dssdev)
-{
-        gpio_set_value(DSS_ENABLE_GPIO, 0);
-        dvi_enabled = 0;
-}
-static struct panel_dvi_platform_data dvi_panel = {
-        .platform_enable        = omap3_stalker_enable_dvi,
-        .platform_disable       = omap3_stalker_disable_dvi,
 };
 static struct omap_dss_device omap3_stalker_dvi_device = {
        .name                   = "dvi",
        .type                   = OMAP_DISPLAY_TYPE_DPI,
-        .driver_name            = "dvi",
+        .driver_name            = "tfp410",
        .data                   = &dvi_panel,
        .phy.dpi.data_lines     = 24,
 };
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index d8c0e89f0126..68b8fc9ff010 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -25,8 +25,10 @@
 #include <linux/gpio.h>
 #include <linux/usb/otg.h>
 #include <linux/i2c/twl.h>
+#include <linux/mfd/twl6040.h>
 #include <linux/regulator/machine.h>
 #include <linux/regulator/fixed.h>
+#include <linux/ti_wilink_st.h>
 #include <linux/wl12xx.h>
 #include <linux/platform_data/omap-abe-twl6040.h>
@@ -41,7 +43,7 @@
 #include "common.h"
 #include <plat/usb.h>
 #include <plat/mmc.h>
-#include <video/omap-panel-dvi.h>
+#include <video/omap-panel-tfp410.h>
 #include "hsmmc.h"
 #include "control.h"
@@ -57,12 +59,21 @@
 #define HDMI_GPIO_HPD  63 /* Hotplug detect */
 /* wl127x BT, FM, GPS connectivity chip */
-static int wl1271_gpios[] = {46, -1, -1};
+static struct ti_st_plat_data wilink_platform_data = {
+        .nshutdown_gpio = 46,
+        .dev_name       = "/dev/ttyO1",
+        .flow_cntrl     = 1,
+        .baud_rate      = 3000000,
+        .chip_enable    = NULL,
+        .suspend        = NULL,
+        .resume         = NULL,
+};
 static struct platform_device wl1271_device = {
        .name   = "kim",
        .id     = -1,
        .dev    = {
-                .platform_data  = &wl1271_gpios,
+                .platform_data  = &wilink_platform_data,
        },
 };
@@ -116,6 +127,11 @@ static struct platform_device panda_abe_audio = {
        },
 };
+static struct platform_device panda_hdmi_audio_codec = {
+        .name   = "hdmi-audio-codec",
+        .id     = -1,
+};
 static struct platform_device btwilink_device = {
        .name   = "btwilink",
        .id     = -1,
@@ -125,6 +141,7 @@ static struct platform_device *panda_devices[] __initdata = {
        &leds_gpio,
        &wl1271_device,
        &panda_abe_audio,
+        &panda_hdmi_audio_codec,
        &btwilink_device,
 };
@@ -230,61 +247,12 @@ static struct platform_device omap_vwlan_device = {
        },
 };
-struct wl12xx_platform_data omap_panda_wlan_data  __initdata = {
+static struct wl12xx_platform_data omap_panda_wlan_data  __initdata = {
        /* PANDA ref clock is 38.4 MHz */
        .board_ref_clock = 2,
 };
-static int omap4_twl6030_hsmmc_late_init(struct device *dev)
+static struct twl6040_codec_data twl6040_codec = {
-{
-        int irq = 0;
-        struct platform_device *pdev = container_of(dev,
-                                struct platform_device, dev);
-        struct omap_mmc_platform_data *pdata = dev->platform_data;
-        if (!pdata) {
-                dev_err(dev, "%s: NULL platform data\n", __func__);
-                return -EINVAL;
-        }
-        /* Setting MMC1 Card detect Irq */
-        if (pdev->id == 0) {
-                irq = twl6030_mmc_card_detect_config();
-                if (irq < 0) {
-                        dev_err(dev, "%s: Error card detect config(%d)\n",
-                                __func__, irq);
-                        return irq;
-                }
-                pdata->slots[0].card_detect = twl6030_mmc_card_detect;
-        }
-        return 0;
-}
-static __init void omap4_twl6030_hsmmc_set_late_init(struct device *dev)
-{
-        struct omap_mmc_platform_data *pdata;
-        /* dev can be null if CONFIG_MMC_OMAP_HS is not set */
-        if (!dev) {
-                pr_err("Failed omap4_twl6030_hsmmc_set_late_init\n");
-                return;
-        }
-        pdata = dev->platform_data;
-        pdata->init =   omap4_twl6030_hsmmc_late_init;
-}
-static int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
-{
-        struct omap2_hsmmc_info *c;
-        omap_hsmmc_init(controllers);
-        for (c = controllers; c->mmc; c++)
-                omap4_twl6030_hsmmc_set_late_init(&c->pdev->dev);
-        return 0;
-}
-static struct twl4030_codec_data twl6040_codec = {
        /* single-step ramp for headset and handsfree */
        .hs_left_step   = 0x0f,
        .hs_right_step  = 0x0f,
@@ -292,17 +260,14 @@ static struct twl4030_codec_data twl6040_codec = {
        .hf_right_step  = 0x1d,
 };
-static struct twl4030_audio_data twl6040_audio = {
+static struct twl6040_platform_data twl6040_data = {
        .codec          = &twl6040_codec,
        .audpwron_gpio  = 127,
-        .naudint_irq    = OMAP44XX_IRQ_SYS_2N,
        .irq_base       = TWL6040_CODEC_IRQ_BASE,
 };
 /* Panda board uses the common PMIC configuration */
-static struct twl4030_platform_data omap4_panda_twldata = {
+static struct twl4030_platform_data omap4_panda_twldata;
-        .audio          = &twl6040_audio,
-};
 /*
 * Display monitor features are burnt in their EEPROM as EDID data. The EEPROM
@@ -325,8 +290,11 @@ static int __init omap4_panda_i2c_init(void)
                        TWL_COMMON_REGULATOR_VANA |
                        TWL_COMMON_REGULATOR_VCXIO |
                        TWL_COMMON_REGULATOR_VUSB |
-                        TWL_COMMON_REGULATOR_CLK32KG);
+                        TWL_COMMON_REGULATOR_CLK32KG |
-        omap4_pmic_init("twl6030", &omap4_panda_twldata);
+                        TWL_COMMON_REGULATOR_V1V8 |
+                        TWL_COMMON_REGULATOR_V2V1);
+        omap4_pmic_init("twl6030", &omap4_panda_twldata,
+                        &twl6040_data, OMAP44XX_IRQ_SYS_2N);
        omap_register_i2c_bus(2, 400, NULL, 0);
        /*
         * Bus 3 is attached to the DVI port where devices like the pico DLP
@@ -421,47 +389,22 @@ static struct omap_board_mux board_mux[] __initdata = {
 /* Display DVI */
 #define PANDA_DVI_TFP410_POWER_DOWN_GPIO        0
-static int omap4_panda_enable_dvi(struct omap_dss_device *dssdev)
-{
-        gpio_set_value(dssdev->reset_gpio, 1);
-        return 0;
-}
-static void omap4_panda_disable_dvi(struct omap_dss_device *dssdev)
-{
-        gpio_set_value(dssdev->reset_gpio, 0);
-}
 /* Using generic display panel */
-static struct panel_dvi_platform_data omap4_dvi_panel = {
+static struct tfp410_platform_data omap4_dvi_panel = {
-        .platform_enable        = omap4_panda_enable_dvi,
+        .i2c_bus_num            = 3,
-        .platform_disable       = omap4_panda_disable_dvi,
+        .power_down_gpio        = PANDA_DVI_TFP410_POWER_DOWN_GPIO,
-        .i2c_bus_num = 3,
 };
-struct omap_dss_device omap4_panda_dvi_device = {
+static struct omap_dss_device omap4_panda_dvi_device = {
        .type                   = OMAP_DISPLAY_TYPE_DPI,
        .name                   = "dvi",
-        .driver_name            = "dvi",
+        .driver_name            = "tfp410",
        .data                   = &omap4_dvi_panel,
        .phy.dpi.data_lines     = 24,
        .reset_gpio             = PANDA_DVI_TFP410_POWER_DOWN_GPIO,
        .channel                = OMAP_DSS_CHANNEL_LCD2,
 };
-int __init omap4_panda_dvi_init(void)
-{
-        int r;
-        /* Requesting TFP410 DVI GPIO and disabling it, at bootup */
-        r = gpio_request_one(omap4_panda_dvi_device.reset_gpio,
-                                GPIOF_OUT_INIT_LOW, "DVI PD");
-        if (r)
-                pr_err("Failed to get DVI powerdown GPIO\n");
-        return r;
-}
 static struct gpio panda_hdmi_gpios[] = {
        { HDMI_GPIO_CT_CP_HPD, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_ct_cp_hpd" },
        { HDMI_GPIO_LS_OE,      GPIOF_OUT_INIT_HIGH, "hdmi_gpio_ls_oe" },
@@ -510,13 +453,8 @@ static struct omap_dss_board_info omap4_panda_dss_data = {
        .default_device = &omap4_panda_dvi_device,
 };
-void __init omap4_panda_display_init(void)
+static void __init omap4_panda_display_init(void)
 {
-        int r;
-        r = omap4_panda_dvi_init();
-        if (r)
-                pr_err("error initializing panda DVI\n");
        omap_display_init(&omap4_panda_dss_data);
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index 33aa3910b09e..5527c1979a16 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -46,7 +46,7 @@
 #include "common.h"
 #include <video/omapdss.h>
 #include <video/omap-panel-generic-dpi.h>
-#include <video/omap-panel-dvi.h>
+#include <video/omap-panel-tfp410.h>
 #include <plat/gpmc.h>
 #include <mach/hardware.h>
 #include <plat/nand.h>
@@ -167,32 +167,15 @@ static void __init overo_display_init(void)
        gpio_export(OVERO_GPIO_LCD_BL, 0);
 }
-static int overo_panel_enable_dvi(struct omap_dss_device *dssdev)
+static struct tfp410_platform_data dvi_panel = {
-{
-        if (lcd_enabled) {
-                printk(KERN_ERR "cannot enable DVI, LCD is enabled\n");
-                return -EINVAL;
-        }
-        dvi_enabled = 1;
-        return 0;
-}
-static void overo_panel_disable_dvi(struct omap_dss_device *dssdev)
-{
-        dvi_enabled = 0;
-}
-static struct panel_dvi_platform_data dvi_panel = {
-        .platform_enable        = overo_panel_enable_dvi,
-        .platform_disable       = overo_panel_disable_dvi,
        .i2c_bus_num            = 3,
+        .power_down_gpio        = -1,
 };
 static struct omap_dss_device overo_dvi_device = {
        .name                   = "dvi",
        .type                   = OMAP_DISPLAY_TYPE_DPI,
-        .driver_name            = "dvi",
+        .driver_name            = "tfp410",
        .data                   = &dvi_panel,
        .phy.dpi.data_lines     = 24,
 };
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index d87ee0612098..ff53deccecab 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -44,6 +44,7 @@
 #include <linux/leds-lp5523.h>
 #include <../drivers/staging/iio/light/tsl2563.h>
+#include <linux/lis3lv02d.h>
 #include "mux.h"
 #include "hsmmc.h"
@@ -63,6 +64,9 @@
 #define RX51_TSC2005_RESET_GPIO         104
 #define RX51_TSC2005_IRQ_GPIO           100
+#define LIS302_IRQ1_GPIO 181
+#define LIS302_IRQ2_GPIO 180  /* Not yet in use */
 /* list all spi devices here */
 enum {
        RX51_SPI_WL1251,
@@ -73,6 +77,77 @@ enum {
 static struct wl12xx_platform_data wl1251_pdata;
 static struct tsc2005_platform_data tsc2005_pdata;
+#if defined(CONFIG_SENSORS_LIS3_I2C) || defined(CONFIG_SENSORS_LIS3_I2C_MODULE)
+static int lis302_setup(void)
+{
+        int err;
+        int irq1 = LIS302_IRQ1_GPIO;
+        int irq2 = LIS302_IRQ2_GPIO;
+        /* gpio for interrupt pin 1 */
+        err = gpio_request(irq1, "lis3lv02dl_irq1");
+        if (err) {
+                printk(KERN_ERR "lis3lv02dl: gpio request failed\n");
+                goto out;
+        }
+        /* gpio for interrupt pin 2 */
+        err = gpio_request(irq2, "lis3lv02dl_irq2");
+        if (err) {
+                gpio_free(irq1);
+                printk(KERN_ERR "lis3lv02dl: gpio request failed\n");
+                goto out;
+        }
+        gpio_direction_input(irq1);
+        gpio_direction_input(irq2);
+out:
+        return err;
+}
+static int lis302_release(void)
+{
+        gpio_free(LIS302_IRQ1_GPIO);
+        gpio_free(LIS302_IRQ2_GPIO);
+        return 0;
+}
+static struct lis3lv02d_platform_data rx51_lis3lv02d_data = {
+        .click_flags    = LIS3_CLICK_SINGLE_X | LIS3_CLICK_SINGLE_Y |
+                          LIS3_CLICK_SINGLE_Z,
+        /* Limits are 0.5g * value */
+        .click_thresh_x = 8,
+        .click_thresh_y = 8,
+        .click_thresh_z = 10,
+        /* Click must be longer than time limit */
+        .click_time_limit = 9,
+        /* Kind of debounce filter */
+        .click_latency    = 50,
+        /* Limits for all axis. millig-value / 18 to get HW values */
+        .wakeup_flags = LIS3_WAKEUP_X_HI | LIS3_WAKEUP_Y_HI,
+        .wakeup_thresh = 800 / 18,
+        .wakeup_flags2 = LIS3_WAKEUP_Z_HI ,
+        .wakeup_thresh2 = 900 / 18,
+        .hipass_ctrl = LIS3_HIPASS1_DISABLE | LIS3_HIPASS2_DISABLE,
+        /* Interrupt line 2 for click detection, line 1 for thresholds */
+        .irq_cfg = LIS3_IRQ2_CLICK | LIS3_IRQ1_FF_WU_12,
+        .axis_x = LIS3_DEV_X,
+        .axis_y = LIS3_INV_DEV_Y,
+        .axis_z = LIS3_INV_DEV_Z,
+        .setup_resources = lis302_setup,
+        .release_resources = lis302_release,
+        .st_min_limits = {-32, 3, 3},
+        .st_max_limits = {-3, 32, 32},
+        .irq2 = OMAP_GPIO_IRQ(LIS302_IRQ2_GPIO),
+};
+#endif
 #if defined(CONFIG_SENSORS_TSL2563) || defined(CONFIG_SENSORS_TSL2563_MODULE)
 static struct tsl2563_platform_data rx51_tsl2563_platform_data = {
        .cover_comp_gain = 16,
@@ -872,11 +947,11 @@ static struct twl4030_power_data rx51_t2scripts_data __initdata = {
        .resource_config = twl4030_rconfig,
 };
-struct twl4030_vibra_data rx51_vibra_data __initdata = {
+static struct twl4030_vibra_data rx51_vibra_data __initdata = {
        .coexist        = 0,
 };
-struct twl4030_audio_data rx51_audio_data __initdata = {
+static struct twl4030_audio_data rx51_audio_data __initdata = {
        .audio_mclk     = 26000000,
        .vibra          = &rx51_vibra_data,
 };
@@ -950,6 +1025,16 @@ static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_2[] = {
        }
 };
+static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_3[] = {
+#if defined(CONFIG_SENSORS_LIS3_I2C) || defined(CONFIG_SENSORS_LIS3_I2C_MODULE)
+        {
+                I2C_BOARD_INFO("lis3lv02d", 0x1d),
+                .platform_data = &rx51_lis3lv02d_data,
+                .irq = OMAP_GPIO_IRQ(LIS302_IRQ1_GPIO),
+        },
+#endif
+};
 static int __init rx51_i2c_init(void)
 {
        if ((system_rev >= SYSTEM_REV_S_USES_VAUX3 && system_rev < 0x100) ||
@@ -971,7 +1056,8 @@ static int __init rx51_i2c_init(void)
        omap_pmic_init(1, 2200, "twl5030", INT_34XX_SYS_NIRQ, &rx51_twldata);
        omap_register_i2c_bus(2, 100, rx51_peripherals_i2c_board_info_2,
                              ARRAY_SIZE(rx51_peripherals_i2c_board_info_2));
-        omap_register_i2c_bus(3, 400, NULL, 0);
+        omap_register_i2c_bus(3, 400, rx51_peripherals_i2c_board_info_3,
+                              ARRAY_SIZE(rx51_peripherals_i2c_board_info_3));
        return 0;
 }
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
index 27f01f051dff..2da92a6ba40a 100644
--- a/arch/arm/mach-omap2/board-rx51.c
+++ b/arch/arm/mach-omap2/board-rx51.c
@@ -59,25 +59,24 @@ static struct platform_device leds_gpio = {
 };
 /*
- * cpuidle C-states definition override from the default values.
+ * cpuidle C-states definition for rx51.
- * The 'exit_latency' field is the sum of sleep and wake-up latencies.
+ *
- */
+ * The 'exit_latency' field is the sum of sleep
-static struct cpuidle_params rx51_cpuidle_params[] = {
+ * and wake-up latencies.
-        /* C1 */
-        {110 + 162, 5 , 1},
+    ---------------------------------------------
-        /* C2 */
+   | state |  exit_latency  |  target_residency  |
-        {106 + 180, 309, 1},
+    ---------------------------------------------
-        /* C3 */
+   |  C1   |    110 + 162   |            5       |
-        {107 + 410, 46057, 0},
+   |  C2   |    106 + 180   |          309       |
-        /* C4 */
+   |  C3   |    107 + 410   |        46057       |
-        {121 + 3374, 46057, 0},
+   |  C4   |    121 + 3374  |        46057       |
-        /* C5 */
+   |  C5   |    855 + 1146  |        46057       |
-        {855 + 1146, 46057, 1},
+   |  C6   |   7580 + 4134  |       484329       |
-        /* C6 */
+   |  C7   |   7505 + 15274 |       484329       |
-        {7580 + 4134, 484329, 0},
+    ---------------------------------------------
-        /* C7 */
-        {7505 + 15274, 484329, 1},
+*/
-};
 extern void __init rx51_peripherals_init(void);
@@ -98,7 +97,6 @@ static void __init rx51_init(void)
        struct omap_sdrc_params *sdrc_params;
        omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
-        omap3_pm_init_cpuidle(rx51_cpuidle_params);
        omap_serial_init();
        sdrc_params = nokia_get_sdram_timings();
diff --git a/arch/arm/mach-omap2/board-zoom-display.c b/arch/arm/mach-omap2/board-zoom-display.c
index a43a765dd092..28187f134fff 100644
--- a/arch/arm/mach-omap2/board-zoom-display.c
+++ b/arch/arm/mach-omap2/board-zoom-display.c
@@ -16,6 +16,7 @@
 #include <linux/spi/spi.h>
 #include <plat/mcspi.h>
 #include <video/omapdss.h>
+#include <mach/board-zoom.h>
 #define LCD_PANEL_RESET_GPIO_PROD       96
 #define LCD_PANEL_RESET_GPIO_PILOT      55
diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
index 7072e0d651b1..3d9d746b221a 100644
--- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
+++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
@@ -165,83 +165,3 @@ int omap2_select_table_rate(struct clk *clk, unsigned long rate)
        return 0;
 }
-#ifdef CONFIG_CPU_FREQ
-/*
- * Walk PRCM rate table and fillout cpufreq freq_table
- * XXX This should be replaced by an OPP layer in the near future
- */
-static struct cpufreq_frequency_table *freq_table;
-void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table)
-{
-        const struct prcm_config *prcm;
-        int i = 0;
-        int tbl_sz = 0;
-        if (!cpu_is_omap24xx())
-                return;
-        for (prcm = rate_table; prcm->mpu_speed; prcm++) {
-                if (!(prcm->flags & cpu_mask))
-                        continue;
-                if (prcm->xtal_speed != sclk->rate)
-                        continue;
-                /* don't put bypass rates in table */
-                if (prcm->dpll_speed == prcm->xtal_speed)
-                        continue;
-                tbl_sz++;
-        }
-        /*
-         * XXX Ensure that we're doing what CPUFreq expects for this error
-         * case and the following one
-         */
-        if (tbl_sz == 0) {
-                pr_warning("%s: no matching entries in rate_table\n",
-                           __func__);
-                return;
-        }
-        /* Include the CPUFREQ_TABLE_END terminator entry */
-        tbl_sz++;
-        freq_table = kzalloc(sizeof(struct cpufreq_frequency_table) * tbl_sz,
-                             GFP_ATOMIC);
-        if (!freq_table) {
-                pr_err("%s: could not kzalloc frequency table\n", __func__);
-                return;
-        }
-        for (prcm = rate_table; prcm->mpu_speed; prcm++) {
-                if (!(prcm->flags & cpu_mask))
-                        continue;
-                if (prcm->xtal_speed != sclk->rate)
-                        continue;
-                /* don't put bypass rates in table */
-                if (prcm->dpll_speed == prcm->xtal_speed)
-                        continue;
-                freq_table[i].index = i;
-                freq_table[i].frequency = prcm->mpu_speed / 1000;
-                i++;
-        }
-        freq_table[i].index = i;
-        freq_table[i].frequency = CPUFREQ_TABLE_END;
-        *table = &freq_table[0];
-}
-void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table)
-{
-        if (!cpu_is_omap24xx())
-                return;
-        kfree(freq_table);
-}
-#endif
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index f57ed5baeccf..5c4e66542169 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -439,7 +439,7 @@ void omap2_clk_disable_unused(struct clk *clk)
                clk->ops->disable(clk);
        }
        if (clk->clkdm != NULL)
-                pwrdm_clkdm_state_switch(clk->clkdm);
+                pwrdm_state_switch(clk->clkdm->pwrdm.ptr);
 }
 #endif
@@ -536,10 +536,5 @@ struct clk_functions omap2_clk_functions = {
        .clk_set_rate           = omap2_clk_set_rate,
        .clk_set_parent         = omap2_clk_set_parent,
        .clk_disable_unused     = omap2_clk_disable_unused,
-#ifdef CONFIG_CPU_FREQ
-        /* These will be removed when the OPP code is integrated */
-        .clk_init_cpufreq_table = omap2_clk_init_cpufreq_table,
-        .clk_exit_cpufreq_table = omap2_clk_exit_cpufreq_table,
-#endif
 };
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index b8c2a686481c..a1bb23a23351 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -146,14 +146,6 @@ extern const struct clksel_rate gpt_sys_rates[];
 extern const struct clksel_rate gfx_l3_rates[];
 extern const struct clksel_rate dsp_ick_rates[];
-#if defined(CONFIG_ARCH_OMAP2) && defined(CONFIG_CPU_FREQ)
-extern void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
-extern void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table);
-#else
-#define omap2_clk_init_cpufreq_table    0
-#define omap2_clk_exit_cpufreq_table    0
-#endif
 extern const struct clkops clkops_omap2_iclk_dflt_wait;
 extern const struct clkops clkops_omap2_iclk_dflt;
 extern const struct clkops clkops_omap2_iclk_idle_only;
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index f4a626f7c79e..4e1a3b0e8cc8 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -1,7 +1,7 @@
 /*
 * OMAP3 clock data
 *
- * Copyright (C) 2007-2010 Texas Instruments, Inc.
+ * Copyright (C) 2007-2010, 2012 Texas Instruments, Inc.
 * Copyright (C) 2007-2011 Nokia Corporation
 *
 * Written by Paul Walmsley
@@ -1640,6 +1640,7 @@ static struct clk hdq_fck = {
        .name           = "hdq_fck",
        .ops            = &clkops_omap2_dflt_wait,
        .parent         = &core_12m_fck,
+        .clkdm_name     = "core_l4_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
        .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
        .recalc         = &followparent_recalc,
@@ -3294,8 +3295,8 @@ static struct omap_clk omap3xxx_clks[] = {
        CLK(NULL,       "gfx_l3_ick",   &gfx_l3_ick,    CK_3430ES1),
        CLK(NULL,       "gfx_cg1_ck",   &gfx_cg1_ck,    CK_3430ES1),
        CLK(NULL,       "gfx_cg2_ck",   &gfx_cg2_ck,    CK_3430ES1),
-        CLK(NULL,       "sgx_fck",      &sgx_fck,       CK_3430ES2PLUS | CK_3517 | CK_36XX),
+        CLK(NULL,       "sgx_fck",      &sgx_fck,       CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK(NULL,       "sgx_ick",      &sgx_ick,       CK_3430ES2PLUS | CK_3517 | CK_36XX),
+        CLK(NULL,       "sgx_ick",      &sgx_ick,       CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
        CLK(NULL,       "d2d_26m_fck",  &d2d_26m_fck,   CK_3430ES1),
        CLK(NULL,       "modem_fck",    &modem_fck,     CK_34XX | CK_36XX),
        CLK(NULL,       "sad2d_ick",    &sad2d_ick,     CK_34XX | CK_36XX),
@@ -3419,7 +3420,7 @@ static struct omap_clk omap3xxx_clks[] = {
        CLK(NULL,       "per_48m_fck",  &per_48m_fck,   CK_3XXX),
        CLK(NULL,       "uart3_fck",    &uart3_fck,     CK_3XXX),
        CLK(NULL,       "uart4_fck",    &uart4_fck,     CK_36XX),
-        CLK(NULL,       "uart4_fck",    &uart4_fck_am35xx, CK_3505 | CK_3517),
+        CLK(NULL,       "uart4_fck",    &uart4_fck_am35xx, CK_AM35XX),
        CLK(NULL,       "gpt2_fck",     &gpt2_fck,      CK_3XXX),
        CLK(NULL,       "gpt3_fck",     &gpt3_fck,      CK_3XXX),
        CLK(NULL,       "gpt4_fck",     &gpt4_fck,      CK_3XXX),
@@ -3513,21 +3514,9 @@ int __init omap3xxx_clk_init(void)
        struct omap_clk *c;
        u32 cpu_clkflg = 0;
-        /*
+        if (cpu_is_omap3517()) {
-         * 3505 must be tested before 3517, since 3517 returns true
-         * for both AM3517 chips and AM3517 family chips, which
-         * includes 3505.  Unfortunately there's no obvious family
-         * test for 3517/3505 :-(
-         */
-        if (cpu_is_omap3505()) {
-                cpu_mask = RATE_IN_34XX;
-                cpu_clkflg = CK_3505;
-        } else if (cpu_is_omap3517()) {
-                cpu_mask = RATE_IN_34XX;
-                cpu_clkflg = CK_3517;
-        } else if (cpu_is_omap3505()) {
                cpu_mask = RATE_IN_34XX;
-                cpu_clkflg = CK_3505;
+                cpu_clkflg = CK_AM35XX;
        } else if (cpu_is_omap3630()) {
                cpu_mask = (RATE_IN_34XX | RATE_IN_36XX);
                cpu_clkflg = CK_36XX;
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index fa6ea65ad44b..2172f6603848 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -3355,17 +3355,6 @@ static struct omap_clk omap44xx_clks[] = {
        CLK(NULL,       "auxclk5_ck",                   &auxclk5_ck,    CK_443X),
        CLK(NULL,       "auxclkreq5_ck",                &auxclkreq5_ck, CK_443X),
        CLK(NULL,       "gpmc_ck",                      &dummy_ck,      CK_443X),
-        CLK(NULL,       "gpt1_ick",                     &dummy_ck,      CK_443X),
-        CLK(NULL,       "gpt2_ick",                     &dummy_ck,      CK_443X),
-        CLK(NULL,       "gpt3_ick",                     &dummy_ck,      CK_443X),
-        CLK(NULL,       "gpt4_ick",                     &dummy_ck,      CK_443X),
-        CLK(NULL,       "gpt5_ick",                     &dummy_ck,      CK_443X),
-        CLK(NULL,       "gpt6_ick",                     &dummy_ck,      CK_443X),
-        CLK(NULL,       "gpt7_ick",                     &dummy_ck,      CK_443X),
-        CLK(NULL,       "gpt8_ick",                     &dummy_ck,      CK_443X),
-        CLK(NULL,       "gpt9_ick",                     &dummy_ck,      CK_443X),
-        CLK(NULL,       "gpt10_ick",                    &dummy_ck,      CK_443X),
-        CLK(NULL,       "gpt11_ick",                    &dummy_ck,      CK_443X),
        CLK("omap_i2c.1",       "ick",                          &dummy_ck,      CK_443X),
        CLK("omap_i2c.2",       "ick",                          &dummy_ck,      CK_443X),
        CLK("omap_i2c.3",       "ick",                          &dummy_ck,      CK_443X),
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index ad07689e1563..8664f5a8bfb6 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -840,7 +840,7 @@ void clkdm_allow_idle(struct clockdomain *clkdm)
        spin_lock_irqsave(&clkdm->lock, flags);
        clkdm->_flags |= _CLKDM_FLAG_HWSUP_ENABLED;
        arch_clkdm->clkdm_allow_idle(clkdm);
-        pwrdm_clkdm_state_switch(clkdm);
+        pwrdm_state_switch(clkdm->pwrdm.ptr);
        spin_unlock_irqrestore(&clkdm->lock, flags);
 }
@@ -924,8 +924,7 @@ static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm)
        spin_lock_irqsave(&clkdm->lock, flags);
        arch_clkdm->clkdm_clk_enable(clkdm);
-        pwrdm_wait_transition(clkdm->pwrdm.ptr);
+        pwrdm_state_switch(clkdm->pwrdm.ptr);
-        pwrdm_clkdm_state_switch(clkdm);
        spin_unlock_irqrestore(&clkdm->lock, flags);
        pr_debug("clockdomain: clkdm %s: enabled\n", clkdm->name);
@@ -950,7 +949,7 @@ static int _clkdm_clk_hwmod_disable(struct clockdomain *clkdm)
        spin_lock_irqsave(&clkdm->lock, flags);
        arch_clkdm->clkdm_clk_disable(clkdm);
-        pwrdm_clkdm_state_switch(clkdm);
+        pwrdm_state_switch(clkdm->pwrdm.ptr);
        spin_unlock_irqrestore(&clkdm->lock, flags);
        pr_debug("clockdomain: clkdm %s: disabled\n", clkdm->name);
diff --git a/arch/arm/mach-omap2/clockdomain44xx.c b/arch/arm/mach-omap2/clockdomain44xx.c
index 935c7f03dab9..4f04dd11d655 100644
--- a/arch/arm/mach-omap2/clockdomain44xx.c
+++ b/arch/arm/mach-omap2/clockdomain44xx.c
@@ -51,6 +51,9 @@ static int omap4_clkdm_clear_all_wkup_sleep_deps(struct clockdomain *clkdm)
        struct clkdm_dep *cd;
        u32 mask = 0;
+        if (!clkdm->prcm_partition)
+                return 0;
        for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) {
                if (!cd->clkdm)
                        continue; /* only happens if data is erroneous */
@@ -103,6 +106,9 @@ static int omap4_clkdm_clk_disable(struct clockdomain *clkdm)
 {
        bool hwsup = false;
+        if (!clkdm->prcm_partition)
+                return 0;
        hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition,
                                        clkdm->cm_inst, clkdm->clkdm_offs);
diff --git a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
index 0a6a04897d89..839145e1cfbe 100644
--- a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
+++ b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
@@ -89,13 +89,3 @@ struct clockdomain wkup_common_clkdm = {
        .pwrdm          = { .name = "wkup_pwrdm" },
        .dep_bit        = OMAP_EN_WKUP_SHIFT,
 };
-struct clockdomain prm_common_clkdm = {
-        .name           = "prm_clkdm",
-        .pwrdm          = { .name = "wkup_pwrdm" },
-};
-struct clockdomain cm_common_clkdm = {
-        .name           = "cm_clkdm",
-        .pwrdm          = { .name = "core_pwrdm" },
-};
diff --git a/arch/arm/mach-omap2/clockdomains3xxx_data.c b/arch/arm/mach-omap2/clockdomains3xxx_data.c
index b84e138d99c8..6038adb97710 100644
--- a/arch/arm/mach-omap2/clockdomains3xxx_data.c
+++ b/arch/arm/mach-omap2/clockdomains3xxx_data.c
@@ -53,9 +53,9 @@
 * 3430ES2 PM_WKDEP_SGX: adds IVA2, removes CORE
 */
 static struct clkdm_dep gfx_sgx_3xxx_wkdeps[] = {
-        { .clkdm_name = "iva2_clkdm", },
+        { .clkdm_name = "iva2_clkdm" },
-        { .clkdm_name = "mpu_clkdm", },
+        { .clkdm_name = "mpu_clkdm" },
-        { .clkdm_name = "wkup_clkdm", },
+        { .clkdm_name = "wkup_clkdm" },
        { NULL },
 };
diff --git a/arch/arm/mach-omap2/clockdomains44xx_data.c b/arch/arm/mach-omap2/clockdomains44xx_data.c
index bd7ed13515cc..c53425847493 100644
--- a/arch/arm/mach-omap2/clockdomains44xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains44xx_data.c
@@ -430,6 +430,8 @@ static struct clockdomain *clockdomains_omap44xx[] __initdata = {
        &l4_wkup_44xx_clkdm,
        &emu_sys_44xx_clkdm,
        &l3_dma_44xx_clkdm,
+        &prm_common_clkdm,
+        &cm_common_clkdm,
        NULL
 };
diff --git a/arch/arm/mach-omap2/clockdomains_common_data.c b/arch/arm/mach-omap2/clockdomains_common_data.c
new file mode 100644
index 000000000000..615b1f04967d
--- /dev/null
+++ b/arch/arm/mach-omap2/clockdomains_common_data.c
@@ -0,0 +1,24 @@
+/*
+ * OMAP2+-common clockdomain data
+ *
+ * Copyright (C) 2008-2012 Texas Instruments, Inc.
+ * Copyright (C) 2008-2010 Nokia Corporation
+ *
+ * Paul Walmsley, Jouni Högander
+ */
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include "clockdomain.h"
+/* These are implicit clockdomains - they are never defined as such in TRM */
+struct clockdomain prm_common_clkdm = {
+        .name           = "prm_clkdm",
+        .pwrdm          = { .name = "wkup_pwrdm" },
+};
+struct clockdomain cm_common_clkdm = {
+        .name           = "cm_clkdm",
+        .pwrdm          = { .name = "core_pwrdm" },
+};
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
index b91275908f33..8083a8cdc55f 100644
--- a/arch/arm/mach-omap2/cm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
@@ -79,7 +79,7 @@
 /* CM_CLKSEL1_PLL_IVA2 */
 #define OMAP3430_IVA2_CLK_SRC_SHIFT                     19
-#define OMAP3430_IVA2_CLK_SRC_MASK                      (0x3 << 19)
+#define OMAP3430_IVA2_CLK_SRC_MASK                      (0x7 << 19)
 #define OMAP3430_IVA2_DPLL_MULT_SHIFT                   8
 #define OMAP3430_IVA2_DPLL_MULT_MASK                    (0x7ff << 8)
 #define OMAP3430_IVA2_DPLL_DIV_SHIFT                    0
@@ -124,7 +124,7 @@
 /* CM_CLKSEL1_PLL_MPU */
 #define OMAP3430_MPU_CLK_SRC_SHIFT                      19
-#define OMAP3430_MPU_CLK_SRC_MASK                       (0x3 << 19)
+#define OMAP3430_MPU_CLK_SRC_MASK                       (0x7 << 19)
 #define OMAP3430_MPU_DPLL_MULT_SHIFT                    8
 #define OMAP3430_MPU_DPLL_MULT_MASK                     (0x7ff << 8)
 #define OMAP3430_MPU_DPLL_DIV_SHIFT                     0
diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c
index bd8810c3753f..8c86d294b1a3 100644
--- a/arch/arm/mach-omap2/cminst44xx.c
+++ b/arch/arm/mach-omap2/cminst44xx.c
@@ -32,6 +32,7 @@
 #include "prcm44xx.h"
 #include "prm44xx.h"
 #include "prcm_mpu44xx.h"
+#include "prcm-common.h"
 /*
 * CLKCTRL_IDLEST_*: possible values for the CM_*_CLKCTRL.IDLEST bitfield:
@@ -49,14 +50,21 @@
 #define CLKCTRL_IDLEST_INTERFACE_IDLE           0x2
 #define CLKCTRL_IDLEST_DISABLED                 0x3
-static u32 _cm_bases[OMAP4_MAX_PRCM_PARTITIONS] = {
+static void __iomem *_cm_bases[OMAP4_MAX_PRCM_PARTITIONS];
-        [OMAP4430_INVALID_PRCM_PARTITION]       = 0,
-        [OMAP4430_PRM_PARTITION]                = OMAP4430_PRM_BASE,
+/**
-        [OMAP4430_CM1_PARTITION]                = OMAP4430_CM1_BASE,
+ * omap_cm_base_init - Populates the cm partitions
-        [OMAP4430_CM2_PARTITION]                = OMAP4430_CM2_BASE,
+ *
-        [OMAP4430_SCRM_PARTITION]               = 0,
+ * Populates the base addresses of the _cm_bases
-        [OMAP4430_PRCM_MPU_PARTITION]           = OMAP4430_PRCM_MPU_BASE,
+ * array used for read/write of cm module registers.
-};
+ */
+void omap_cm_base_init(void)
+{
+        _cm_bases[OMAP4430_PRM_PARTITION] = prm_base;
+        _cm_bases[OMAP4430_CM1_PARTITION] = cm_base;
+        _cm_bases[OMAP4430_CM2_PARTITION] = cm2_base;
+        _cm_bases[OMAP4430_PRCM_MPU_PARTITION] = prcm_mpu_base;
+}
 /* Private functions */
@@ -106,7 +114,7 @@ u32 omap4_cminst_read_inst_reg(u8 part, s16 inst, u16 idx)
        BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
               part == OMAP4430_INVALID_PRCM_PARTITION ||
               !_cm_bases[part]);
-        return __raw_readl(OMAP2_L4_IO_ADDRESS(_cm_bases[part] + inst + idx));
+        return __raw_readl(_cm_bases[part] + inst + idx);
 }
 /* Write into a register in a CM instance */
@@ -115,7 +123,7 @@ void omap4_cminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx)
        BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
               part == OMAP4430_INVALID_PRCM_PARTITION ||
               !_cm_bases[part]);
-        __raw_writel(val, OMAP2_L4_IO_ADDRESS(_cm_bases[part] + inst + idx));
+        __raw_writel(val, _cm_bases[part] + inst + idx);
 }
 /* Read-modify-write a register in CM1. Caller must lock */
diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c
index 1549c11000d3..8a6953a34fe2 100644
--- a/arch/arm/mach-omap2/common.c
+++ b/arch/arm/mach-omap2/common.c
@@ -166,6 +166,7 @@ static struct omap_globals omap4_globals = {
        .prm    = OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE),
        .cm     = OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE),
        .cm2    = OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE),
+        .prcm_mpu       = OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE),
 };
 void __init omap2_set_globals_443x(void)
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 57da7f406e28..d6c9e6180318 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -27,6 +27,7 @@
 #ifndef __ASSEMBLER__
 #include <linux/delay.h>
+#include <linux/i2c/twl.h>
 #include <plat/common.h>
 #include <asm/proc-fns.h>
@@ -111,6 +112,7 @@ struct omap_globals {
        void __iomem    *prm;            /* Power and Reset Management */
        void __iomem    *cm;             /* Clock Management */
        void __iomem    *cm2;
+        void __iomem    *prcm_mpu;
 };
 void omap2_set_globals_242x(void);
@@ -134,8 +136,6 @@ void omap4_map_io(void);
 void ti81xx_map_io(void);
 void omap_barriers_init(void);
-extern void __init omap_init_consistent_dma_size(void);
 /**
 * omap_test_timeout - busy-loop, testing a condition
 * @cond: condition to test until it evaluates to true
@@ -254,6 +254,8 @@ static inline u32 omap4_mpuss_read_prev_context_state(void)
 struct omap_sdrc_params;
 extern void omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
                                      struct omap_sdrc_params *sdrc_cs1);
+struct omap2_hsmmc_info;
+extern int omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers);
 #endif /* __ASSEMBLER__ */
 #endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
index 535866489ce3..207bc1c7759f 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -38,40 +38,44 @@
 #ifdef CONFIG_CPU_IDLE
-/*
- * The latencies/thresholds for various C states have
- * to be configured from the respective board files.
- * These are some default values (which might not provide
- * the best power savings) used on boards which do not
- * pass these details from the board file.
- */
-static struct cpuidle_params cpuidle_params_table[] = {
-        /* C1 */
-        {2 + 2, 5, 1},
-        /* C2 */
-        {10 + 10, 30, 1},
-        /* C3 */
-        {50 + 50, 300, 1},
-        /* C4 */
-        {1500 + 1800, 4000, 1},
-        /* C5 */
-        {2500 + 7500, 12000, 1},
-        /* C6 */
-        {3000 + 8500, 15000, 1},
-        /* C7 */
-        {10000 + 30000, 300000, 1},
-};
-#define OMAP3_NUM_STATES ARRAY_SIZE(cpuidle_params_table)
 /* Mach specific information to be recorded in the C-state driver_data */
 struct omap3_idle_statedata {
        u32 mpu_state;
        u32 core_state;
-        u8 valid;
 };
-struct omap3_idle_statedata omap3_idle_data[OMAP3_NUM_STATES];
-struct powerdomain *mpu_pd, *core_pd, *per_pd, *cam_pd;
+static struct omap3_idle_statedata omap3_idle_data[] = {
+        {
+                .mpu_state = PWRDM_POWER_ON,
+                .core_state = PWRDM_POWER_ON,
+        },
+        {
+                .mpu_state = PWRDM_POWER_ON,
+                .core_state = PWRDM_POWER_ON,
+        },
+        {
+                .mpu_state = PWRDM_POWER_RET,
+                .core_state = PWRDM_POWER_ON,
+        },
+        {
+                .mpu_state = PWRDM_POWER_OFF,
+                .core_state = PWRDM_POWER_ON,
+        },
+        {
+                .mpu_state = PWRDM_POWER_RET,
+                .core_state = PWRDM_POWER_RET,
+        },
+        {
+                .mpu_state = PWRDM_POWER_OFF,
+                .core_state = PWRDM_POWER_RET,
+        },
+        {
+                .mpu_state = PWRDM_POWER_OFF,
+                .core_state = PWRDM_POWER_OFF,
+        },
+};
+static struct powerdomain *mpu_pd, *core_pd, *per_pd, *cam_pd;
 static int _cpuidle_allow_idle(struct powerdomain *pwrdm,
                                struct clockdomain *clkdm)
@@ -91,8 +95,7 @@ static int __omap3_enter_idle(struct cpuidle_device *dev,
                                struct cpuidle_driver *drv,
                                int index)
 {
-        struct omap3_idle_statedata *cx =
+        struct omap3_idle_statedata *cx = &omap3_idle_data[index];
-                        cpuidle_get_statedata(&dev->states_usage[index]);
        u32 mpu_state = cx->mpu_state, core_state = cx->core_state;
        local_fiq_disable();
@@ -169,14 +172,12 @@ static inline int omap3_enter_idle(struct cpuidle_device *dev,
 * if it satisfies the enable_off_mode condition.
 */
 static int next_valid_state(struct cpuidle_device *dev,
-                        struct cpuidle_driver *drv,
+                            struct cpuidle_driver *drv, int index)
-                                int index)
 {
-        struct cpuidle_state_usage *curr_usage = &dev->states_usage[index];
+        struct omap3_idle_statedata *cx = &omap3_idle_data[index];
-        struct cpuidle_state *curr = &drv->states[index];
-        struct omap3_idle_statedata *cx = cpuidle_get_statedata(curr_usage);
        u32 mpu_deepest_state = PWRDM_POWER_RET;
        u32 core_deepest_state = PWRDM_POWER_RET;
+        int idx;
        int next_index = -1;
        if (enable_off_mode) {
@@ -191,45 +192,29 @@ static int next_valid_state(struct cpuidle_device *dev,
        }
        /* Check if current state is valid */
-        if ((cx->valid) &&
+        if ((cx->mpu_state >= mpu_deepest_state) &&
-            (cx->mpu_state >= mpu_deepest_state) &&
+            (cx->core_state >= core_deepest_state))
-            (cx->core_state >= core_deepest_state)) {
                return index;
-        } else {
-                int idx = OMAP3_NUM_STATES - 1;
-                /* Reach the current state starting at highest C-state */
-                for (; idx >= 0; idx--) {
-                        if (&drv->states[idx] == curr) {
-                                next_index = idx;
-                                break;
-                        }
-                }
-                /* Should never hit this condition */
-                WARN_ON(next_index == -1);
-                /*
+        /*
-                 * Drop to next valid state.
+         * Drop to next valid state.
-                 * Start search from the next (lower) state.
+         * Start search from the next (lower) state.
-                 */
+         */
-                idx--;
+        for (idx = index - 1; idx >= 0; idx--) {
-                for (; idx >= 0; idx--) {
+                cx =  &omap3_idle_data[idx];
-                        cx = cpuidle_get_statedata(&dev->states_usage[idx]);
+                if ((cx->mpu_state >= mpu_deepest_state) &&
-                        if ((cx->valid) &&
+                    (cx->core_state >= core_deepest_state)) {
-                            (cx->mpu_state >= mpu_deepest_state) &&
+                        next_index = idx;
-                            (cx->core_state >= core_deepest_state)) {
+                        break;
-                                next_index = idx;
-                                break;
-                        }
                }
-                /*
-                 * C1 is always valid.
-                 * So, no need to check for 'next_index == -1' outside
-                 * this loop.
-                 */
        }
+        /*
+         * C1 is always valid.
+         * So, no need to check for 'next_index == -1' outside
+         * this loop.
+         */
        return next_index;
 }
@@ -273,7 +258,7 @@ static int omap3_enter_idle_bm(struct cpuidle_device *dev,
         * Prevent PER off if CORE is not in retention or off as this
         * would disable PER wakeups completely.
         */
-        cx = cpuidle_get_statedata(&dev->states_usage[index]);
+        cx = &omap3_idle_data[index];
        core_next_state = cx->core_state;
        per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd);
        if ((per_next_state == PWRDM_POWER_OFF) &&
@@ -298,57 +283,71 @@ select_state:
 DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
-void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params)
-{
-        int i;
-        if (!cpuidle_board_params)
-                return;
-        for (i = 0; i < OMAP3_NUM_STATES; i++) {
-                cpuidle_params_table[i].valid = cpuidle_board_params[i].valid;
-                cpuidle_params_table[i].exit_latency =
-                        cpuidle_board_params[i].exit_latency;
-                cpuidle_params_table[i].target_residency =
-                        cpuidle_board_params[i].target_residency;
-        }
-        return;
-}
 struct cpuidle_driver omap3_idle_driver = {
        .name =         "omap3_idle",
        .owner =        THIS_MODULE,
+        .states = {
+                {
+                        .enter            = omap3_enter_idle,
+                        .exit_latency     = 2 + 2,
+                        .target_residency = 5,
+                        .flags            = CPUIDLE_FLAG_TIME_VALID,
+                        .name             = "C1",
+                        .desc             = "MPU ON + CORE ON",
+                },
+                {
+                        .enter            = omap3_enter_idle_bm,
+                        .exit_latency     = 10 + 10,
+                        .target_residency = 30,
+                        .flags            = CPUIDLE_FLAG_TIME_VALID,
+                        .name             = "C2",
+                        .desc             = "MPU ON + CORE ON",
+                },
+                {
+                        .enter            = omap3_enter_idle_bm,
+                        .exit_latency     = 50 + 50,
+                        .target_residency = 300,
+                        .flags            = CPUIDLE_FLAG_TIME_VALID,
+                        .name             = "C3",
+                        .desc             = "MPU RET + CORE ON",
+                },
+                {
+                        .enter            = omap3_enter_idle_bm,
+                        .exit_latency     = 1500 + 1800,
+                        .target_residency = 4000,
+                        .flags            = CPUIDLE_FLAG_TIME_VALID,
+                        .name             = "C4",
+                        .desc             = "MPU OFF + CORE ON",
+                },
+                {
+                        .enter            = omap3_enter_idle_bm,
+                        .exit_latency     = 2500 + 7500,
+                        .target_residency = 12000,
+                        .flags            = CPUIDLE_FLAG_TIME_VALID,
+                        .name             = "C5",
+                        .desc             = "MPU RET + CORE RET",
+                },
+                {
+                        .enter            = omap3_enter_idle_bm,
+                        .exit_latency     = 3000 + 8500,
+                        .target_residency = 15000,
+                        .flags            = CPUIDLE_FLAG_TIME_VALID,
+                        .name             = "C6",
+                        .desc             = "MPU OFF + CORE RET",
+                },
+                {
+                        .enter            = omap3_enter_idle_bm,
+                        .exit_latency     = 10000 + 30000,
+                        .target_residency = 30000,
+                        .flags            = CPUIDLE_FLAG_TIME_VALID,
+                        .name             = "C7",
+                        .desc             = "MPU OFF + CORE OFF",
+                },
+        },
+        .state_count = ARRAY_SIZE(omap3_idle_data),
+        .safe_state_index = 0,
 };
-/* Helper to fill the C-state common data*/
-static inline void _fill_cstate(struct cpuidle_driver *drv,
-                                        int idx, const char *descr)
-{
-        struct cpuidle_state *state = &drv->states[idx];
-        state->exit_latency     = cpuidle_params_table[idx].exit_latency;
-        state->target_residency = cpuidle_params_table[idx].target_residency;
-        state->flags            = CPUIDLE_FLAG_TIME_VALID;
-        state->enter            = omap3_enter_idle_bm;
-        sprintf(state->name, "C%d", idx + 1);
-        strncpy(state->desc, descr, CPUIDLE_DESC_LEN);
-}
-/* Helper to register the driver_data */
-static inline struct omap3_idle_statedata *_fill_cstate_usage(
-                                        struct cpuidle_device *dev,
-                                        int idx)
-{
-        struct omap3_idle_statedata *cx = &omap3_idle_data[idx];
-        struct cpuidle_state_usage *state_usage = &dev->states_usage[idx];
-        cx->valid               = cpuidle_params_table[idx].valid;
-        cpuidle_set_statedata(state_usage, cx);
-        return cx;
-}
 /**
 * omap3_idle_init - Init routine for OMAP3 idle
 *
@@ -358,77 +357,20 @@ static inline struct omap3_idle_statedata *_fill_cstate_usage(
 int __init omap3_idle_init(void)
 {
        struct cpuidle_device *dev;
-        struct cpuidle_driver *drv = &omap3_idle_driver;
-        struct omap3_idle_statedata *cx;
        mpu_pd = pwrdm_lookup("mpu_pwrdm");
        core_pd = pwrdm_lookup("core_pwrdm");
        per_pd = pwrdm_lookup("per_pwrdm");
        cam_pd = pwrdm_lookup("cam_pwrdm");
+        if (!mpu_pd || !core_pd || !per_pd || !cam_pd)
+                return -ENODEV;
-        drv->safe_state_index = -1;
-        dev = &per_cpu(omap3_idle_dev, smp_processor_id());
-        /* C1 . MPU WFI + Core active */
-        _fill_cstate(drv, 0, "MPU ON + CORE ON");
-        (&drv->states[0])->enter = omap3_enter_idle;
-        drv->safe_state_index = 0;
-        cx = _fill_cstate_usage(dev, 0);
-        cx->valid = 1;  /* C1 is always valid */
-        cx->mpu_state = PWRDM_POWER_ON;
-        cx->core_state = PWRDM_POWER_ON;
-        /* C2 . MPU WFI + Core inactive */
-        _fill_cstate(drv, 1, "MPU ON + CORE ON");
-        cx = _fill_cstate_usage(dev, 1);
-        cx->mpu_state = PWRDM_POWER_ON;
-        cx->core_state = PWRDM_POWER_ON;
-        /* C3 . MPU CSWR + Core inactive */
-        _fill_cstate(drv, 2, "MPU RET + CORE ON");
-        cx = _fill_cstate_usage(dev, 2);
-        cx->mpu_state = PWRDM_POWER_RET;
-        cx->core_state = PWRDM_POWER_ON;
-        /* C4 . MPU OFF + Core inactive */
-        _fill_cstate(drv, 3, "MPU OFF + CORE ON");
-        cx = _fill_cstate_usage(dev, 3);
-        cx->mpu_state = PWRDM_POWER_OFF;
-        cx->core_state = PWRDM_POWER_ON;
-        /* C5 . MPU RET + Core RET */
-        _fill_cstate(drv, 4, "MPU RET + CORE RET");
-        cx = _fill_cstate_usage(dev, 4);
-        cx->mpu_state = PWRDM_POWER_RET;
-        cx->core_state = PWRDM_POWER_RET;
-        /* C6 . MPU OFF + Core RET */
-        _fill_cstate(drv, 5, "MPU OFF + CORE RET");
-        cx = _fill_cstate_usage(dev, 5);
-        cx->mpu_state = PWRDM_POWER_OFF;
-        cx->core_state = PWRDM_POWER_RET;
-        /* C7 . MPU OFF + Core OFF */
-        _fill_cstate(drv, 6, "MPU OFF + CORE OFF");
-        cx = _fill_cstate_usage(dev, 6);
-        /*
-         * Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot
-         * enable OFF mode in a stable form for previous revisions.
-         * We disable C7 state as a result.
-         */
-        if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) {
-                cx->valid = 0;
-                pr_warn("%s: core off state C7 disabled due to i583\n",
-                        __func__);
-        }
-        cx->mpu_state = PWRDM_POWER_OFF;
-        cx->core_state = PWRDM_POWER_OFF;
-        drv->state_count = OMAP3_NUM_STATES;
        cpuidle_register_driver(&omap3_idle_driver);
-        dev->state_count = OMAP3_NUM_STATES;
+        dev = &per_cpu(omap3_idle_dev, smp_processor_id());
+        dev->cpu = 0;
        if (cpuidle_register_device(dev)) {
                printk(KERN_ERR "%s: CPUidle register device failed\n",
                       __func__);
diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c
index f386cbe9c889..be1617ca84bd 100644
--- a/arch/arm/mach-omap2/cpuidle44xx.c
+++ b/arch/arm/mach-omap2/cpuidle44xx.c
@@ -24,26 +24,31 @@
 #ifdef CONFIG_CPU_IDLE
-/* Machine specific information to be recorded in the C-state driver_data */
+/* Machine specific information */
 struct omap4_idle_statedata {
        u32 cpu_state;
        u32 mpu_logic_state;
        u32 mpu_state;
-        u8 valid;
 };
-static struct cpuidle_params cpuidle_params_table[] = {
+static struct omap4_idle_statedata omap4_idle_data[] = {
-        /* C1 - CPU0 ON + CPU1 ON + MPU ON */
+        {
-        {.exit_latency = 2 + 2 , .target_residency = 5, .valid = 1},
+                .cpu_state = PWRDM_POWER_ON,
-        /* C2- CPU0 OFF + CPU1 OFF + MPU CSWR */
+                .mpu_state = PWRDM_POWER_ON,
-        {.exit_latency = 328 + 440 , .target_residency = 960, .valid = 1},
+                .mpu_logic_state = PWRDM_POWER_RET,
-        /* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
+        },
-        {.exit_latency = 460 + 518 , .target_residency = 1100, .valid = 1},
+        {
+                .cpu_state = PWRDM_POWER_OFF,
+                .mpu_state = PWRDM_POWER_RET,
+                .mpu_logic_state = PWRDM_POWER_RET,
+        },
+        {
+                .cpu_state = PWRDM_POWER_OFF,
+                .mpu_state = PWRDM_POWER_RET,
+                .mpu_logic_state = PWRDM_POWER_OFF,
+        },
 };
-#define OMAP4_NUM_STATES ARRAY_SIZE(cpuidle_params_table)
-struct omap4_idle_statedata omap4_idle_data[OMAP4_NUM_STATES];
 static struct powerdomain *mpu_pd, *cpu0_pd, *cpu1_pd;
 /**
@@ -60,8 +65,7 @@ static int omap4_enter_idle(struct cpuidle_device *dev,
                        struct cpuidle_driver *drv,
                        int index)
 {
-        struct omap4_idle_statedata *cx =
+        struct omap4_idle_statedata *cx = &omap4_idle_data[index];
-                        cpuidle_get_statedata(&dev->states_usage[index]);
        u32 cpu1_state;
        int cpu_id = smp_processor_id();
@@ -78,7 +82,7 @@ static int omap4_enter_idle(struct cpuidle_device *dev,
        cpu1_state = pwrdm_read_pwrst(cpu1_pd);
        if (cpu1_state != PWRDM_POWER_OFF) {
                index = drv->safe_state_index;
-                cx = cpuidle_get_statedata(&dev->states_usage[index]);
+                cx = &omap4_idle_data[index];
        }
        if (index > 0)
@@ -133,36 +137,39 @@ struct cpuidle_driver omap4_idle_driver = {
        .name                           = "omap4_idle",
        .owner                          = THIS_MODULE,
        .en_core_tk_irqen               = 1,
+        .states = {
+                {
+                        /* C1 - CPU0 ON + CPU1 ON + MPU ON */
+                        .exit_latency = 2 + 2,
+                        .target_residency = 5,
+                        .flags = CPUIDLE_FLAG_TIME_VALID,
+                        .enter = omap4_enter_idle,
+                        .name = "C1",
+                        .desc = "MPUSS ON"
+                },
+                {
+                        /* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */
+                        .exit_latency = 328 + 440,
+                        .target_residency = 960,
+                        .flags = CPUIDLE_FLAG_TIME_VALID,
+                        .enter = omap4_enter_idle,
+                        .name = "C2",
+                        .desc = "MPUSS CSWR",
+                },
+                {
+                        /* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
+                        .exit_latency = 460 + 518,
+                        .target_residency = 1100,
+                        .flags = CPUIDLE_FLAG_TIME_VALID,
+                        .enter = omap4_enter_idle,
+                        .name = "C3",
+                        .desc = "MPUSS OSWR",
+                },
+        },
+        .state_count = ARRAY_SIZE(omap4_idle_data),
+        .safe_state_index = 0,
 };
-static inline void _fill_cstate(struct cpuidle_driver *drv,
-                                        int idx, const char *descr)
-{
-        struct cpuidle_state *state = &drv->states[idx];
-        state->exit_latency     = cpuidle_params_table[idx].exit_latency;
-        state->target_residency = cpuidle_params_table[idx].target_residency;
-        state->flags            = CPUIDLE_FLAG_TIME_VALID;
-        state->enter            = omap4_enter_idle;
-        sprintf(state->name, "C%d", idx + 1);
-        strncpy(state->desc, descr, CPUIDLE_DESC_LEN);
-}
-static inline struct omap4_idle_statedata *_fill_cstate_usage(
-                                        struct cpuidle_device *dev,
-                                        int idx)
-{
-        struct omap4_idle_statedata *cx = &omap4_idle_data[idx];
-        struct cpuidle_state_usage *state_usage = &dev->states_usage[idx];
-        cx->valid               = cpuidle_params_table[idx].valid;
-        cpuidle_set_statedata(state_usage, cx);
-        return cx;
-}
 /**
 * omap4_idle_init - Init routine for OMAP4 idle
 *
@@ -171,9 +178,7 @@ static inline struct omap4_idle_statedata *_fill_cstate_usage(
 */
 int __init omap4_idle_init(void)
 {
-        struct omap4_idle_statedata *cx;
        struct cpuidle_device *dev;
-        struct cpuidle_driver *drv = &omap4_idle_driver;
        unsigned int cpu_id = 0;
        mpu_pd = pwrdm_lookup("mpu_pwrdm");
@@ -182,42 +187,15 @@ int __init omap4_idle_init(void)
        if ((!mpu_pd) || (!cpu0_pd) || (!cpu1_pd))
                return -ENODEV;
-        drv->safe_state_index = -1;
        dev = &per_cpu(omap4_idle_dev, cpu_id);
        dev->cpu = cpu_id;
-        /* C1 - CPU0 ON + CPU1 ON + MPU ON */
-        _fill_cstate(drv, 0, "MPUSS ON");
-        drv->safe_state_index = 0;
-        cx = _fill_cstate_usage(dev, 0);
-        cx->valid = 1;  /* C1 is always valid */
-        cx->cpu_state = PWRDM_POWER_ON;
-        cx->mpu_state = PWRDM_POWER_ON;
-        cx->mpu_logic_state = PWRDM_POWER_RET;
-        /* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */
-        _fill_cstate(drv, 1, "MPUSS CSWR");
-        cx = _fill_cstate_usage(dev, 1);
-        cx->cpu_state = PWRDM_POWER_OFF;
-        cx->mpu_state = PWRDM_POWER_RET;
-        cx->mpu_logic_state = PWRDM_POWER_RET;
-        /* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
-        _fill_cstate(drv, 2, "MPUSS OSWR");
-        cx = _fill_cstate_usage(dev, 2);
-        cx->cpu_state = PWRDM_POWER_OFF;
-        cx->mpu_state = PWRDM_POWER_RET;
-        cx->mpu_logic_state = PWRDM_POWER_OFF;
-        drv->state_count = OMAP4_NUM_STATES;
        cpuidle_register_driver(&omap4_idle_driver);
-        dev->state_count = OMAP4_NUM_STATES;
        if (cpuidle_register_device(dev)) {
                pr_err("%s: CPUidle register device failed\n", __func__);
-                        return -EIO;
+                return -EIO;
-                }
+        }
        return 0;
 }
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index e4336035c0ea..ae62ece04ef9 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -42,7 +42,6 @@
 static int __init omap3_l3_init(void)
 {
-        int l;
        struct omap_hwmod *oh;
        struct platform_device *pdev;
        char oh_name[L3_MODULES_MAX_LEN];
@@ -54,7 +53,7 @@ static int __init omap3_l3_init(void)
        if (!(cpu_is_omap34xx()))
                return -ENODEV;
-        l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main");
+        snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main");
        oh = omap_hwmod_lookup(oh_name);
@@ -72,7 +71,7 @@ postcore_initcall(omap3_l3_init);
 static int __init omap4_l3_init(void)
 {
-        int l, i;
+        int i;
        struct omap_hwmod *oh[3];
        struct platform_device *pdev;
        char oh_name[L3_MODULES_MAX_LEN];
@@ -89,7 +88,7 @@ static int __init omap4_l3_init(void)
                return -ENODEV;
        for (i = 0; i < L3_MODULES; i++) {
-                l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main_%d", i+1);
+                snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main_%d", i+1);
                oh[i] = omap_hwmod_lookup(oh_name);
                if (!(oh[i]))
@@ -355,6 +354,36 @@ static void __init omap_init_dmic(void)
 static inline void omap_init_dmic(void) {}
 #endif
+#if defined(CONFIG_SND_OMAP_SOC_OMAP_HDMI) || \
+                defined(CONFIG_SND_OMAP_SOC_OMAP_HDMI_MODULE)
+static struct platform_device omap_hdmi_audio = {
+        .name   = "omap-hdmi-audio",
+        .id     = -1,
+};
+static void __init omap_init_hdmi_audio(void)
+{
+        struct omap_hwmod *oh;
+        struct platform_device *pdev;
+        oh = omap_hwmod_lookup("dss_hdmi");
+        if (!oh) {
+                printk(KERN_ERR "Could not look up dss_hdmi hw_mod\n");
+                return;
+        }
+        pdev = omap_device_build("omap-hdmi-audio-dai",
+                -1, oh, NULL, 0, NULL, 0, 0);
+        WARN(IS_ERR(pdev),
+             "Can't build omap_device for omap-hdmi-audio-dai.\n");
+        platform_device_register(&omap_hdmi_audio);
+}
+#else
+static inline void omap_init_hdmi_audio(void) {}
+#endif
 #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
 #include <plat/mcspi.h>
@@ -701,11 +730,15 @@ static int __init omap2_init_devices(void)
         * in alphabetical order so they're easier to sort through.
         */
        omap_init_audio();
-        omap_init_mcpdm();
-        omap_init_dmic();
        omap_init_camera();
+        omap_init_hdmi_audio();
        omap_init_mbox();
-        omap_init_mcspi();
+        /* If dtb is there, the devices will be created dynamically */
+        if (!of_have_populated_dt()) {
+                omap_init_dmic();
+                omap_init_mcpdm();
+                omap_init_mcspi();
+        }
        omap_init_pmu();
        omap_hdq_init();
        omap_init_sti();
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index fc56745676fa..f0f10beeffe8 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -142,7 +142,8 @@ static int _omap3_noncore_dpll_lock(struct clk *clk)
        ai = omap3_dpll_autoidle_read(clk);
-        omap3_dpll_deny_idle(clk);
+        if (ai)
+                omap3_dpll_deny_idle(clk);
        _omap3_dpll_write_clken(clk, DPLL_LOCKED);
@@ -186,8 +187,6 @@ static int _omap3_noncore_dpll_bypass(struct clk *clk)
        if (ai)
                omap3_dpll_allow_idle(clk);
-        else
-                omap3_dpll_deny_idle(clk);
        return r;
 }
@@ -216,8 +215,6 @@ static int _omap3_noncore_dpll_stop(struct clk *clk)
        if (ai)
                omap3_dpll_allow_idle(clk);
-        else
-                omap3_dpll_deny_idle(clk);
        return 0;
 }
@@ -519,6 +516,9 @@ u32 omap3_dpll_autoidle_read(struct clk *clk)
        dd = clk->dpll_data;
+        if (!dd->autoidle_reg)
+                return -EINVAL;
        v = __raw_readl(dd->autoidle_reg);
        v &= dd->autoidle_mask;
        v >>= __ffs(dd->autoidle_mask);
@@ -545,6 +545,12 @@ void omap3_dpll_allow_idle(struct clk *clk)
        dd = clk->dpll_data;
+        if (!dd->autoidle_reg) {
+                pr_debug("clock: DPLL %s: autoidle not supported\n",
+                        clk->name);
+                return;
+        }
        /*
         * REVISIT: CORE DPLL can optionally enter low-power bypass
         * by writing 0x5 instead of 0x1.  Add some mechanism to
@@ -554,6 +560,7 @@ void omap3_dpll_allow_idle(struct clk *clk)
        v &= ~dd->autoidle_mask;
        v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
        __raw_writel(v, dd->autoidle_reg);
 }
 /**
@@ -572,6 +579,12 @@ void omap3_dpll_deny_idle(struct clk *clk)
        dd = clk->dpll_data;
+        if (!dd->autoidle_reg) {
+                pr_debug("clock: DPLL %s: autoidle not supported\n",
+                        clk->name);
+                return;
+        }
        v = __raw_readl(dd->autoidle_reg);
        v &= ~dd->autoidle_mask;
        v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
diff --git a/arch/arm/mach-omap2/dsp.c b/arch/arm/mach-omap2/dsp.c
index 74f18f2952df..3376388b317a 100644
--- a/arch/arm/mach-omap2/dsp.c
+++ b/arch/arm/mach-omap2/dsp.c
@@ -57,8 +57,9 @@ static int __init omap_dsp_init(void)
        if (pdata->phys_mempool_base) {
                pdata->phys_mempool_size = CONFIG_TIDSPBRIDGE_MEMPOOL_SIZE;
-                pr_info("%s: %x bytes @ %x\n", __func__,
+                pr_info("%s: %llx bytes @ %llx\n", __func__,
-                        pdata->phys_mempool_size, pdata->phys_mempool_base);
+                        (unsigned long long)pdata->phys_mempool_size,
+                        (unsigned long long)pdata->phys_mempool_base);
        }
        pdev = platform_device_alloc("omap-dsp", -1);
diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c
index 2f994e5194e8..a80e093b039f 100644
--- a/arch/arm/mach-omap2/gpio.c
+++ b/arch/arm/mach-omap2/gpio.c
@@ -20,6 +20,7 @@
 #include <linux/err.h>
 #include <linux/slab.h>
 #include <linux/interrupt.h>
+#include <linux/of.h>
 #include <plat/omap_hwmod.h>
 #include <plat/omap_device.h>
@@ -58,7 +59,7 @@ static int __init omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
        pdata->virtual_irq_start = IH_GPIO_BASE + 32 * (id - 1);
        pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count;
        pdata->regs = kzalloc(sizeof(struct omap_gpio_reg_offs), GFP_KERNEL);
-        if (!pdata) {
+        if (!pdata->regs) {
                pr_err("gpio%d: Memory allocation failed\n", id);
                return -ENOMEM;
        }
@@ -146,7 +147,10 @@ static int __init omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
 */
 static int __init omap2_gpio_init(void)
 {
-        return omap_hwmod_for_each_by_class("gpio", omap2_gpio_dev_init,
+        /* If dtb is there, the devices will be created dynamically */
-                                                NULL);
+        if (of_have_populated_dt())
+                return -ENODEV;
+        return omap_hwmod_for_each_by_class("gpio", omap2_gpio_dev_init, NULL);
 }
 postcore_initcall(omap2_gpio_init);
diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c
index 385b3e02c4a6..a0fa9bb2bda5 100644
--- a/arch/arm/mach-omap2/gpmc-onenand.c
+++ b/arch/arm/mach-omap2/gpmc-onenand.c
@@ -176,7 +176,7 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
        const int t_wpl  = 40;
        const int t_wph  = 30;
        int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
-        int tick_ns, div, fclk_offset_ns, fclk_offset, gpmc_clk_ns, latency;
+        int div, fclk_offset_ns, fclk_offset, gpmc_clk_ns, latency;
        int first_time = 0, hf = 0, vhf = 0, sync_read = 0, sync_write = 0;
        int err, ticks_cez;
        int cs = cfg->cs, freq = *freq_ptr;
@@ -240,7 +240,6 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
                break;
        }
-        tick_ns = gpmc_ticks_to_ns(1);
        div = gpmc_cs_calc_divider(cs, min_gpmc_clk_period);
        gpmc_clk_ns = gpmc_ticks_to_ns(div);
        if (gpmc_clk_ns < 15) /* >66Mhz */
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 00d510858e28..580e684e8825 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -755,8 +755,7 @@ static int __init gpmc_init(void)
                irq++;
        }
-        ret = request_irq(gpmc_irq,
+        ret = request_irq(gpmc_irq, gpmc_handle_irq, IRQF_SHARED, "gpmc", NULL);
-                        gpmc_handle_irq, IRQF_SHARED, "gpmc", gpmc_base);
        if (ret)
                pr_err("gpmc: irq-%d could not claim: err %d\n",
                                                gpmc_irq, ret);
diff --git a/arch/arm/mach-omap2/hdq1w.c b/arch/arm/mach-omap2/hdq1w.c
new file mode 100644
index 000000000000..297ebe03f09c
--- /dev/null
+++ b/arch/arm/mach-omap2/hdq1w.c
@@ -0,0 +1,72 @@
+/*
+ * IP block integration code for the HDQ1W/1-wire IP block
+ *
+ * Copyright (C) 2012 Texas Instruments, Inc.
+ * Paul Walmsley
+ *
+ * Based on the I2C reset code in arch/arm/mach-omap2/i2c.c by
+ *     Avinash.H.M <avinashhm@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ */
+#include <plat/omap_hwmod.h>
+#include <plat/hdq1w.h>
+#include "common.h"
+/* Maximum microseconds to wait for OMAP module to softreset */
+#define MAX_MODULE_SOFTRESET_WAIT       10000
+/**
+ * omap_hdq1w_reset - reset the OMAP HDQ1W module
+ * @oh: struct omap_hwmod *
+ *
+ * OCP soft reset the HDQ1W IP block.  Section 20.6.1.4 "HDQ1W/1-Wire
+ * Software Reset" of the OMAP34xx Technical Reference Manual Revision
+ * ZR (SWPU223R) does not include the rather important fact that, for
+ * the reset to succeed, the HDQ1W module's internal clock gate must be
+ * programmed to allow the clock to propagate to the rest of the
+ * module.  In this sense, it's rather similar to the I2C custom reset
+ * function.  Returns 0.
+ */
+int omap_hdq1w_reset(struct omap_hwmod *oh)
+{
+        u32 v;
+        int c = 0;
+        /* Write to the SOFTRESET bit */
+        omap_hwmod_softreset(oh);
+        /* Enable the module's internal clocks */
+        v = omap_hwmod_read(oh, HDQ_CTRL_STATUS_OFFSET);
+        v |= 1 << HDQ_CTRL_STATUS_CLOCKENABLE_SHIFT;
+        omap_hwmod_write(v, oh, HDQ_CTRL_STATUS_OFFSET);
+        /* Poll on RESETDONE bit */
+        omap_test_timeout((omap_hwmod_read(oh,
+                                           oh->class->sysc->syss_offs)
+                           & SYSS_RESETDONE_MASK),
+                          MAX_MODULE_SOFTRESET_WAIT, c);
+        if (c == MAX_MODULE_SOFTRESET_WAIT)
+                pr_warning("%s: %s: softreset failed (waited %d usec)\n",
+                           __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT);
+        else
+                pr_debug("%s: %s: softreset in %d usec\n", __func__,
+                         oh->name, c);
+        return 0;
+}
diff --git a/arch/arm/mach-omap2/hwspinlock.c b/arch/arm/mach-omap2/hwspinlock.c
index 454dfce125ca..8763c8520dc2 100644
--- a/arch/arm/mach-omap2/hwspinlock.c
+++ b/arch/arm/mach-omap2/hwspinlock.c
@@ -28,7 +28,7 @@ static struct hwspinlock_pdata omap_hwspinlock_pdata __initdata = {
        .base_id = 0,
 };
-int __init hwspinlocks_init(void)
+static int __init hwspinlocks_init(void)
 {
        int retval = 0;
        struct omap_hwmod *oh;
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 0e79b7bc6aa4..f1398171d8a2 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -478,9 +478,12 @@ void __init omap4xxx_check_revision(void)
        case 0xb94e:
                switch (rev) {
                case 0:
-                default:
                        omap_revision = OMAP4460_REV_ES1_0;
                        break;
+                case 2:
+                default:
+                        omap_revision = OMAP4460_REV_ES1_1;
+                        break;
                }
                break;
        case 0xb975:
diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h
index 1e2d3322f33e..c88420de1151 100644
--- a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h
+++ b/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h
@@ -941,10 +941,10 @@
 #define OMAP4_DSI2_LANEENABLE_MASK                              (0x7 << 29)
 #define OMAP4_DSI1_LANEENABLE_SHIFT                             24
 #define OMAP4_DSI1_LANEENABLE_MASK                              (0x1f << 24)
-#define OMAP4_DSI2_PIPD_SHIFT                                   19
+#define OMAP4_DSI1_PIPD_SHIFT                                   19
-#define OMAP4_DSI2_PIPD_MASK                                    (0x1f << 19)
+#define OMAP4_DSI1_PIPD_MASK                                    (0x1f << 19)
-#define OMAP4_DSI1_PIPD_SHIFT                                   14
+#define OMAP4_DSI2_PIPD_SHIFT                                   14
-#define OMAP4_DSI1_PIPD_MASK                                    (0x1f << 14)
+#define OMAP4_DSI2_PIPD_MASK                                    (0x1f << 14)
 /* CONTROL_MCBSPLP */
 #define OMAP4_ALBCTRLRX_FSX_SHIFT                               31
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 065bd768987c..4b9491aa36fa 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -31,6 +31,7 @@
 #include <plat/omap-pm.h>
 #include <plat/omap_hwmod.h>
 #include <plat/multi.h>
+#include <plat/dma.h>
 #include "iomap.h"
 #include "voltage.h"
@@ -363,24 +364,6 @@ static void __init omap_hwmod_init_postsetup(void)
 #endif
        omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
-        /*
-         * Set the default postsetup state for unusual modules (like
-         * MPU WDT).
-         *
-         * The postsetup_state is not actually used until
-         * omap_hwmod_late_init(), so boards that desire full watchdog
-         * coverage of kernel initialization can reprogram the
-         * postsetup_state between the calls to
-         * omap2_init_common_infra() and omap_sdrc_init().
-         *
-         * XXX ideally we could detect whether the MPU WDT was currently
-         * enabled here and make this conditional
-         */
-        postsetup_state = _HWMOD_STATE_DISABLED;
-        omap_hwmod_for_each_by_class("wd_timer",
-                                     _set_hwmod_postsetup_state,
-                                     &postsetup_state);
        omap_pm_if_early_init();
 }
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index 65f0d2571c9a..1ecf54565fe2 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -25,6 +25,7 @@
 #include <mach/hardware.h>
 #include "iomap.h"
+#include "common.h"
 /* selected INTC register offsets */
@@ -149,7 +150,6 @@ omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
        ct->chip.irq_mask = irq_gc_mask_disable_reg;
        ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
-        ct->regs.ack = INTC_CONTROL;
        ct->regs.enable = INTC_MIR_CLEAR0;
        ct->regs.disable = INTC_MIR_SET0;
        irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
@@ -231,7 +231,7 @@ static inline void omap_intc_handle_irq(void __iomem *base_addr, struct pt_regs
                        goto out;
                irqnr = readl_relaxed(base_addr + 0xd8);
-#ifdef CONFIG_SOC_OMAPTI816X
+#ifdef CONFIG_SOC_OMAPTI81XX
                if (irqnr)
                        goto out;
                irqnr = readl_relaxed(base_addr + 0xf8);
@@ -334,7 +334,7 @@ void omap_intc_restore_context(void)
 void omap3_intc_suspend(void)
 {
        /* A pending interrupt would prevent OMAP from entering suspend */
-        omap_ack_irq(0);
+        omap_ack_irq(NULL);
 }
 void omap3_intc_prepare_idle(void)
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
index 415a6f1cf419..19b8b6774862 100644
--- a/arch/arm/mach-omap2/mailbox.c
+++ b/arch/arm/mach-omap2/mailbox.c
@@ -26,9 +26,9 @@
 #define MAILBOX_IRQSTATUS(u)            (0x100 + 8 * (u))
 #define MAILBOX_IRQENABLE(u)            (0x104 + 8 * (u))
-#define OMAP4_MAILBOX_IRQSTATUS(u)      (0x104 + 10 * (u))
+#define OMAP4_MAILBOX_IRQSTATUS(u)      (0x104 + 0x10 * (u))
-#define OMAP4_MAILBOX_IRQENABLE(u)      (0x108 + 10 * (u))
+#define OMAP4_MAILBOX_IRQENABLE(u)      (0x108 + 0x10 * (u))
-#define OMAP4_MAILBOX_IRQENABLE_CLR(u)  (0x10c + 10 * (u))
+#define OMAP4_MAILBOX_IRQENABLE_CLR(u)  (0x10c + 0x10 * (u))
 #define MAILBOX_IRQ_NEWMSG(m)           (1 << (2 * (m)))
 #define MAILBOX_IRQ_NOTFULL(m)          (1 << (2 * (m) + 1))
diff --git a/arch/arm/mach-omap2/msdi.c b/arch/arm/mach-omap2/msdi.c
new file mode 100644
index 000000000000..ef2a6924731a
--- /dev/null
+++ b/arch/arm/mach-omap2/msdi.c
@@ -0,0 +1,88 @@
+/*
+ * MSDI IP block reset
+ *
+ * Copyright (C) 2012 Texas Instruments, Inc.
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ * XXX What about pad muxing?
+ */
+#include <linux/kernel.h>
+#include <plat/omap_hwmod.h>
+#include <plat/mmc.h>
+#include "common.h"
+/*
+ * MSDI_CON_OFFSET: offset in bytes of the MSDI IP block's CON register
+ *     from the IP block's base address
+ */
+#define MSDI_CON_OFFSET                         0x0c
+/* Register bitfields in the CON register */
+#define MSDI_CON_POW_MASK                       BIT(11)
+#define MSDI_CON_CLKD_MASK                      (0x3f << 0)
+#define MSDI_CON_CLKD_SHIFT                     0
+/* Maximum microseconds to wait for OMAP module to softreset */
+#define MAX_MODULE_SOFTRESET_WAIT       10000
+/* MSDI_TARGET_RESET_CLKD: clock divisor to use throughout the reset */
+#define MSDI_TARGET_RESET_CLKD          0x3ff
+/**
+ * omap_msdi_reset - reset the MSDI IP block
+ * @oh: struct omap_hwmod *
+ *
+ * The MSDI IP block on OMAP2420 has to have both the POW and CLKD
+ * fields set inside its CON register for a reset to complete
+ * successfully.  This is not documented in the TRM.  For CLKD, we use
+ * the value that results in the lowest possible clock rate, to attempt
+ * to avoid disturbing any cards.
+ */
+int omap_msdi_reset(struct omap_hwmod *oh)
+{
+        u16 v = 0;
+        int c = 0;
+        /* Write to the SOFTRESET bit */
+        omap_hwmod_softreset(oh);
+        /* Enable the MSDI core and internal clock */
+        v |= MSDI_CON_POW_MASK;
+        v |= MSDI_TARGET_RESET_CLKD << MSDI_CON_CLKD_SHIFT;
+        omap_hwmod_write(v, oh, MSDI_CON_OFFSET);
+        /* Poll on RESETDONE bit */
+        omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs)
+                           & SYSS_RESETDONE_MASK),
+                          MAX_MODULE_SOFTRESET_WAIT, c);
+        if (c == MAX_MODULE_SOFTRESET_WAIT)
+                pr_warning("%s: %s: softreset failed (waited %d usec)\n",
+                           __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT);
+        else
+                pr_debug("%s: %s: softreset in %d usec\n", __func__,
+                         oh->name, c);
+        /* Disable the MSDI internal clock */
+        v &= ~MSDI_CON_CLKD_MASK;
+        omap_hwmod_write(v, oh, MSDI_CON_OFFSET);
+        return 0;
+}
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 65c33911341f..3268ee24eada 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -247,7 +247,7 @@ int __init omap_mux_init_signal(const char *muxname, int val)
        int mux_mode;
        mux_mode = omap_mux_get_by_name(muxname, &partition, &mux);
-        if (mux_mode < 0)
+        if (mux_mode < 0 || !mux)
                return mux_mode;
        old_mode = omap_mux_read(partition, mux->reg_offset);
diff --git a/arch/arm/mach-omap2/omap-secure.c b/arch/arm/mach-omap2/omap-secure.c
index d8f8ef40290f..d9ae4a53d818 100644
--- a/arch/arm/mach-omap2/omap-secure.c
+++ b/arch/arm/mach-omap2/omap-secure.c
@@ -18,6 +18,7 @@
 #include <asm/cacheflush.h>
 #include <asm/memblock.h>
+#include <plat/omap-secure.h>
 #include <mach/omap-secure.h>
 static phys_addr_t omap_secure_memblock_base;
diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c
index 42cd7fb52414..d811c7790350 100644
--- a/arch/arm/mach-omap2/omap-wakeupgen.c
+++ b/arch/arm/mach-omap2/omap-wakeupgen.c
@@ -259,7 +259,7 @@ static void irq_save_context(void)
 /*
 * Clear WakeupGen SAR backup status.
 */
-void irq_sar_clear(void)
+static void irq_sar_clear(void)
 {
        u32 val;
        val = __raw_readl(sar_base + SAR_BACKUP_STATUS_OFFSET);
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index 70de277f5c15..a8161e5f3204 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -25,11 +25,13 @@
 #include <plat/irqs.h>
 #include <plat/sram.h>
 #include <plat/omap-secure.h>
+#include <plat/mmc.h>
 #include <mach/hardware.h>
 #include <mach/omap-wakeupgen.h>
 #include "common.h"
+#include "hsmmc.h"
 #include "omap4-sar-layout.h"
 #include <linux/export.h>
@@ -207,3 +209,59 @@ static int __init omap4_sar_ram_init(void)
        return 0;
 }
 early_initcall(omap4_sar_ram_init);
+#if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
+static int omap4_twl6030_hsmmc_late_init(struct device *dev)
+{
+        int irq = 0;
+        struct platform_device *pdev = container_of(dev,
+                                struct platform_device, dev);
+        struct omap_mmc_platform_data *pdata = dev->platform_data;
+        /* Setting MMC1 Card detect Irq */
+        if (pdev->id == 0) {
+                irq = twl6030_mmc_card_detect_config();
+                if (irq < 0) {
+                        dev_err(dev, "%s: Error card detect config(%d)\n",
+                                __func__, irq);
+                        return irq;
+                }
+                pdata->slots[0].card_detect_irq = irq;
+                pdata->slots[0].card_detect = twl6030_mmc_card_detect;
+        }
+        return 0;
+}
+static __init void omap4_twl6030_hsmmc_set_late_init(struct device *dev)
+{
+        struct omap_mmc_platform_data *pdata;
+        /* dev can be null if CONFIG_MMC_OMAP_HS is not set */
+        if (!dev) {
+                pr_err("Failed %s\n", __func__);
+                return;
+        }
+        pdata = dev->platform_data;
+        pdata->init =   omap4_twl6030_hsmmc_late_init;
+}
+int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
+{
+        struct omap2_hsmmc_info *c;
+        omap_hsmmc_init(controllers);
+        for (c = controllers; c->mmc; c++) {
+                /* pdev can be null if CONFIG_MMC_OMAP_HS is not set */
+                if (!c->pdev)
+                        continue;
+                omap4_twl6030_hsmmc_set_late_init(&c->pdev->dev);
+        }
+        return 0;
+}
+#else
+int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
+{
+        return 0;
+}
+#endif
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 2c27fdb61e66..bf86f7e8f91f 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -2,7 +2,7 @@
 * omap_hwmod implementation for OMAP2/3/4
 *
 * Copyright (C) 2009-2011 Nokia Corporation
- * Copyright (C) 2011 Texas Instruments, Inc.
+ * Copyright (C) 2011-2012 Texas Instruments, Inc.
 *
 * Paul Walmsley, Benoît Cousson, Kevin Hilman
 *
@@ -137,6 +137,7 @@
 #include <linux/mutex.h>
 #include <linux/spinlock.h>
 #include <linux/slab.h>
+#include <linux/bootmem.h>
 #include "common.h"
 #include <plat/cpu.h>
@@ -159,16 +160,58 @@
 /* Name of the OMAP hwmod for the MPU */
 #define MPU_INITIATOR_NAME              "mpu"
+/*
+ * Number of struct omap_hwmod_link records per struct
+ * omap_hwmod_ocp_if record (master->slave and slave->master)
+ */
+#define LINKS_PER_OCP_IF                2
 /* omap_hwmod_list contains all registered struct omap_hwmods */
 static LIST_HEAD(omap_hwmod_list);
 /* mpu_oh: used to add/remove MPU initiator from sleepdep list */
 static struct omap_hwmod *mpu_oh;
+/*
+ * linkspace: ptr to a buffer that struct omap_hwmod_link records are
+ * allocated from - used to reduce the number of small memory
+ * allocations, which has a significant impact on performance
+ */
+static struct omap_hwmod_link *linkspace;
+/*
+ * free_ls, max_ls: array indexes into linkspace; representing the
+ * next free struct omap_hwmod_link index, and the maximum number of
+ * struct omap_hwmod_link records allocated (respectively)
+ */
+static unsigned short free_ls, max_ls, ls_supp;
 /* Private functions */
 /**
+ * _fetch_next_ocp_if - return the next OCP interface in a list
+ * @p: ptr to a ptr to the list_head inside the ocp_if to return
+ * @i: pointer to the index of the element pointed to by @p in the list
+ *
+ * Return a pointer to the struct omap_hwmod_ocp_if record
+ * containing the struct list_head pointed to by @p, and increment
+ * @p such that a future call to this routine will return the next
+ * record.
+ */
+static struct omap_hwmod_ocp_if *_fetch_next_ocp_if(struct list_head **p,
+                                                    int *i)
+{
+        struct omap_hwmod_ocp_if *oi;
+        oi = list_entry(*p, struct omap_hwmod_link, node)->ocp_if;
+        *p = (*p)->next;
+        *i = *i + 1;
+        return oi;
+}
+/**
 * _update_sysc_cache - return the module OCP_SYSCONFIG register, keep copy
 * @oh: struct omap_hwmod *
 *
@@ -582,16 +625,16 @@ static int _init_main_clk(struct omap_hwmod *oh)
 */
 static int _init_interface_clks(struct omap_hwmod *oh)
 {
+        struct omap_hwmod_ocp_if *os;
+        struct list_head *p;
        struct clk *c;
-        int i;
+        int i = 0;
        int ret = 0;
-        if (oh->slaves_cnt == 0)
+        p = oh->slave_ports.next;
-                return 0;
-        for (i = 0; i < oh->slaves_cnt; i++) {
-                struct omap_hwmod_ocp_if *os = oh->slaves[i];
+        while (i < oh->slaves_cnt) {
+                os = _fetch_next_ocp_if(&p, &i);
                if (!os->clk)
                        continue;
@@ -643,21 +686,22 @@ static int _init_opt_clks(struct omap_hwmod *oh)
 */
 static int _enable_clocks(struct omap_hwmod *oh)
 {
-        int i;
+        struct omap_hwmod_ocp_if *os;
+        struct list_head *p;
+        int i = 0;
        pr_debug("omap_hwmod: %s: enabling clocks\n", oh->name);
        if (oh->_clk)
                clk_enable(oh->_clk);
-        if (oh->slaves_cnt > 0) {
+        p = oh->slave_ports.next;
-                for (i = 0; i < oh->slaves_cnt; i++) {
-                        struct omap_hwmod_ocp_if *os = oh->slaves[i];
-                        struct clk *c = os->_clk;
-                        if (c && (os->flags & OCPIF_SWSUP_IDLE))
+        while (i < oh->slaves_cnt) {
-                                clk_enable(c);
+                os = _fetch_next_ocp_if(&p, &i);
-                }
+                if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE))
+                        clk_enable(os->_clk);
        }
        /* The opt clocks are controlled by the device driver. */
@@ -673,21 +717,22 @@ static int _enable_clocks(struct omap_hwmod *oh)
 */
 static int _disable_clocks(struct omap_hwmod *oh)
 {
-        int i;
+        struct omap_hwmod_ocp_if *os;
+        struct list_head *p;
+        int i = 0;
        pr_debug("omap_hwmod: %s: disabling clocks\n", oh->name);
        if (oh->_clk)
                clk_disable(oh->_clk);
-        if (oh->slaves_cnt > 0) {
+        p = oh->slave_ports.next;
-                for (i = 0; i < oh->slaves_cnt; i++) {
-                        struct omap_hwmod_ocp_if *os = oh->slaves[i];
-                        struct clk *c = os->_clk;
-                        if (c && (os->flags & OCPIF_SWSUP_IDLE))
+        while (i < oh->slaves_cnt) {
-                                clk_disable(c);
+                os = _fetch_next_ocp_if(&p, &i);
-                }
+                if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE))
+                        clk_disable(os->_clk);
        }
        /* The opt clocks are controlled by the device driver. */
@@ -781,39 +826,6 @@ static int _omap4_wait_target_disable(struct omap_hwmod *oh)
 }
 /**
- * _omap4_disable_module - enable CLKCTRL modulemode on OMAP4
- * @oh: struct omap_hwmod *
- *
- * Disable the PRCM module mode related to the hwmod @oh.
- * Return EINVAL if the modulemode is not supported and 0 in case of success.
- */
-static int _omap4_disable_module(struct omap_hwmod *oh)
-{
-        int v;
-        /* The module mode does not exist prior OMAP4 */
-        if (!cpu_is_omap44xx())
-                return -EINVAL;
-        if (!oh->clkdm || !oh->prcm.omap4.modulemode)
-                return -EINVAL;
-        pr_debug("omap_hwmod: %s: %s\n", oh->name, __func__);
-        omap4_cminst_module_disable(oh->clkdm->prcm_partition,
-                                    oh->clkdm->cm_inst,
-                                    oh->clkdm->clkdm_offs,
-                                    oh->prcm.omap4.clkctrl_offs);
-        v = _omap4_wait_target_disable(oh);
-        if (v)
-                pr_warn("omap_hwmod: %s: _wait_target_disable failed\n",
-                        oh->name);
-        return 0;
-}
-/**
 * _count_mpu_irqs - count the number of MPU IRQ lines associated with @oh
 * @oh: struct omap_hwmod *oh
 *
@@ -883,59 +895,220 @@ static int _count_ocp_if_addr_spaces(struct omap_hwmod_ocp_if *os)
 }
 /**
- * _find_mpu_port_index - find hwmod OCP slave port ID intended for MPU use
+ * _get_mpu_irq_by_name - fetch MPU interrupt line number by name
- * @oh: struct omap_hwmod *
+ * @oh: struct omap_hwmod * to operate on
+ * @name: pointer to the name of the MPU interrupt number to fetch (optional)
+ * @irq: pointer to an unsigned int to store the MPU IRQ number to
 *
- * Returns the array index of the OCP slave port that the MPU
+ * Retrieve a MPU hardware IRQ line number named by @name associated
- * addresses the device on, or -EINVAL upon error or not found.
+ * with the IP block pointed to by @oh.  The IRQ number will be filled
+ * into the address pointed to by @dma.  When @name is non-null, the
+ * IRQ line number associated with the named entry will be returned.
+ * If @name is null, the first matching entry will be returned.  Data
+ * order is not meaningful in hwmod data, so callers are strongly
+ * encouraged to use a non-null @name whenever possible to avoid
+ * unpredictable effects if hwmod data is later added that causes data
+ * ordering to change.  Returns 0 upon success or a negative error
+ * code upon error.
 */
-static int __init _find_mpu_port_index(struct omap_hwmod *oh)
+static int _get_mpu_irq_by_name(struct omap_hwmod *oh, const char *name,
+                                unsigned int *irq)
 {
        int i;
-        int found = 0;
+        bool found = false;
-        if (!oh || oh->slaves_cnt == 0)
+        if (!oh->mpu_irqs)
-                return -EINVAL;
+                return -ENOENT;
-        for (i = 0; i < oh->slaves_cnt; i++) {
+        i = 0;
-                struct omap_hwmod_ocp_if *os = oh->slaves[i];
+        while (oh->mpu_irqs[i].irq != -1) {
+                if (name == oh->mpu_irqs[i].name ||
+                    !strcmp(name, oh->mpu_irqs[i].name)) {
+                        found = true;
+                        break;
+                }
+                i++;
+        }
-                if (os->user & OCP_USER_MPU) {
+        if (!found)
-                        found = 1;
+                return -ENOENT;
+        *irq = oh->mpu_irqs[i].irq;
+        return 0;
+}
+/**
+ * _get_sdma_req_by_name - fetch SDMA request line ID by name
+ * @oh: struct omap_hwmod * to operate on
+ * @name: pointer to the name of the SDMA request line to fetch (optional)
+ * @dma: pointer to an unsigned int to store the request line ID to
+ *
+ * Retrieve an SDMA request line ID named by @name on the IP block
+ * pointed to by @oh.  The ID will be filled into the address pointed
+ * to by @dma.  When @name is non-null, the request line ID associated
+ * with the named entry will be returned.  If @name is null, the first
+ * matching entry will be returned.  Data order is not meaningful in
+ * hwmod data, so callers are strongly encouraged to use a non-null
+ * @name whenever possible to avoid unpredictable effects if hwmod
+ * data is later added that causes data ordering to change.  Returns 0
+ * upon success or a negative error code upon error.
+ */
+static int _get_sdma_req_by_name(struct omap_hwmod *oh, const char *name,
+                                 unsigned int *dma)
+{
+        int i;
+        bool found = false;
+        if (!oh->sdma_reqs)
+                return -ENOENT;
+        i = 0;
+        while (oh->sdma_reqs[i].dma_req != -1) {
+                if (name == oh->sdma_reqs[i].name ||
+                    !strcmp(name, oh->sdma_reqs[i].name)) {
+                        found = true;
                        break;
                }
+                i++;
        }
-        if (found)
+        if (!found)
-                pr_debug("omap_hwmod: %s: MPU OCP slave port ID  %d\n",
+                return -ENOENT;
-                         oh->name, i);
-        else
+        *dma = oh->sdma_reqs[i].dma_req;
-                pr_debug("omap_hwmod: %s: no MPU OCP slave port found\n",
-                         oh->name);
-        return (found) ? i : -EINVAL;
+        return 0;
 }
 /**
- * _find_mpu_rt_base - find hwmod register target base addr accessible by MPU
+ * _get_addr_space_by_name - fetch address space start & end by name
- * @oh: struct omap_hwmod *
+ * @oh: struct omap_hwmod * to operate on
+ * @name: pointer to the name of the address space to fetch (optional)
+ * @pa_start: pointer to a u32 to store the starting address to
+ * @pa_end: pointer to a u32 to store the ending address to
 *
- * Return the virtual address of the base of the register target of
+ * Retrieve address space start and end addresses for the IP block
- * device @oh, or NULL on error.
+ * pointed to by @oh.  The data will be filled into the addresses
+ * pointed to by @pa_start and @pa_end.  When @name is non-null, the
+ * address space data associated with the named entry will be
+ * returned.  If @name is null, the first matching entry will be
+ * returned.  Data order is not meaningful in hwmod data, so callers
+ * are strongly encouraged to use a non-null @name whenever possible
+ * to avoid unpredictable effects if hwmod data is later added that
+ * causes data ordering to change.  Returns 0 upon success or a
+ * negative error code upon error.
 */
-static void __iomem * __init _find_mpu_rt_base(struct omap_hwmod *oh, u8 index)
+static int _get_addr_space_by_name(struct omap_hwmod *oh, const char *name,
+                                   u32 *pa_start, u32 *pa_end)
 {
+        int i, j;
        struct omap_hwmod_ocp_if *os;
-        struct omap_hwmod_addr_space *mem;
+        struct list_head *p = NULL;
-        int i = 0, found = 0;
+        bool found = false;
-        void __iomem *va_start;
+        p = oh->slave_ports.next;
+        i = 0;
+        while (i < oh->slaves_cnt) {
+                os = _fetch_next_ocp_if(&p, &i);
+                if (!os->addr)
+                        return -ENOENT;
+                j = 0;
+                while (os->addr[j].pa_start != os->addr[j].pa_end) {
+                        if (name == os->addr[j].name ||
+                            !strcmp(name, os->addr[j].name)) {
+                                found = true;
+                                break;
+                        }
+                        j++;
+                }
+                if (found)
+                        break;
+        }
+        if (!found)
+                return -ENOENT;
-        if (!oh || oh->slaves_cnt == 0)
+        *pa_start = os->addr[j].pa_start;
+        *pa_end = os->addr[j].pa_end;
+        return 0;
+}
+/**
+ * _save_mpu_port_index - find and save the index to @oh's MPU port
+ * @oh: struct omap_hwmod *
+ *
+ * Determines the array index of the OCP slave port that the MPU uses
+ * to address the device, and saves it into the struct omap_hwmod.
+ * Intended to be called during hwmod registration only. No return
+ * value.
+ */
+static void __init _save_mpu_port_index(struct omap_hwmod *oh)
+{
+        struct omap_hwmod_ocp_if *os = NULL;
+        struct list_head *p;
+        int i = 0;
+        if (!oh)
+                return;
+        oh->_int_flags |= _HWMOD_NO_MPU_PORT;
+        p = oh->slave_ports.next;
+        while (i < oh->slaves_cnt) {
+                os = _fetch_next_ocp_if(&p, &i);
+                if (os->user & OCP_USER_MPU) {
+                        oh->_mpu_port = os;
+                        oh->_int_flags &= ~_HWMOD_NO_MPU_PORT;
+                        break;
+                }
+        }
+        return;
+}
+/**
+ * _find_mpu_rt_port - return omap_hwmod_ocp_if accessible by the MPU
+ * @oh: struct omap_hwmod *
+ *
+ * Given a pointer to a struct omap_hwmod record @oh, return a pointer
+ * to the struct omap_hwmod_ocp_if record that is used by the MPU to
+ * communicate with the IP block.  This interface need not be directly
+ * connected to the MPU (and almost certainly is not), but is directly
+ * connected to the IP block represented by @oh.  Returns a pointer
+ * to the struct omap_hwmod_ocp_if * upon success, or returns NULL upon
+ * error or if there does not appear to be a path from the MPU to this
+ * IP block.
+ */
+static struct omap_hwmod_ocp_if *_find_mpu_rt_port(struct omap_hwmod *oh)
+{
+        if (!oh || oh->_int_flags & _HWMOD_NO_MPU_PORT || oh->slaves_cnt == 0)
                return NULL;
-        os = oh->slaves[index];
+        return oh->_mpu_port;
+};
-        if (!os->addr)
+/**
+ * _find_mpu_rt_addr_space - return MPU register target address space for @oh
+ * @oh: struct omap_hwmod *
+ *
+ * Returns a pointer to the struct omap_hwmod_addr_space record representing
+ * the register target MPU address space; or returns NULL upon error.
+ */
+static struct omap_hwmod_addr_space * __init _find_mpu_rt_addr_space(struct omap_hwmod *oh)
+{
+        struct omap_hwmod_ocp_if *os;
+        struct omap_hwmod_addr_space *mem;
+        int found = 0, i = 0;
+        os = _find_mpu_rt_port(oh);
+        if (!os || !os->addr)
                return NULL;
        do {
@@ -944,20 +1117,7 @@ static void __iomem * __init _find_mpu_rt_base(struct omap_hwmod *oh, u8 index)
                        found = 1;
        } while (!found && mem->pa_start != mem->pa_end);
-        if (found) {
+        return (found) ? mem : NULL;
-                va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start);
-                if (!va_start) {
-                        pr_err("omap_hwmod: %s: Could not ioremap\n", oh->name);
-                        return NULL;
-                }
-                pr_debug("omap_hwmod: %s: MPU register target at va %p\n",
-                         oh->name, va_start);
-        } else {
-                pr_debug("omap_hwmod: %s: no MPU register target found\n",
-                         oh->name);
-        }
-        return (found) ? va_start : NULL;
 }
 /**
@@ -1205,12 +1365,11 @@ static int _wait_target_ready(struct omap_hwmod *oh)
        if (!oh)
                return -EINVAL;
-        if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
+        if (oh->flags & HWMOD_NO_IDLEST)
                return 0;
-        os = oh->slaves[oh->_mpu_port_index];
+        os = _find_mpu_rt_port(oh);
+        if (!os)
-        if (oh->flags & HWMOD_NO_IDLEST)
                return 0;
        /* XXX check module SIDLEMODE */
@@ -1378,13 +1537,73 @@ static int _read_hardreset(struct omap_hwmod *oh, const char *name)
 }
 /**
+ * _are_any_hardreset_lines_asserted - return true if part of @oh is hard-reset
+ * @oh: struct omap_hwmod *
+ *
+ * If any hardreset line associated with @oh is asserted, then return true.
+ * Otherwise, if @oh has no hardreset lines associated with it, or if
+ * no hardreset lines associated with @oh are asserted, then return false.
+ * This function is used to avoid executing some parts of the IP block
+ * enable/disable sequence if a hardreset line is set.
+ */
+static bool _are_any_hardreset_lines_asserted(struct omap_hwmod *oh)
+{
+        int i;
+        if (oh->rst_lines_cnt == 0)
+                return false;
+        for (i = 0; i < oh->rst_lines_cnt; i++)
+                if (_read_hardreset(oh, oh->rst_lines[i].name) > 0)
+                        return true;
+        return false;
+}
+/**
+ * _omap4_disable_module - enable CLKCTRL modulemode on OMAP4
+ * @oh: struct omap_hwmod *
+ *
+ * Disable the PRCM module mode related to the hwmod @oh.
+ * Return EINVAL if the modulemode is not supported and 0 in case of success.
+ */
+static int _omap4_disable_module(struct omap_hwmod *oh)
+{
+        int v;
+        /* The module mode does not exist prior OMAP4 */
+        if (!cpu_is_omap44xx())
+                return -EINVAL;
+        if (!oh->clkdm || !oh->prcm.omap4.modulemode)
+                return -EINVAL;
+        pr_debug("omap_hwmod: %s: %s\n", oh->name, __func__);
+        omap4_cminst_module_disable(oh->clkdm->prcm_partition,
+                                    oh->clkdm->cm_inst,
+                                    oh->clkdm->clkdm_offs,
+                                    oh->prcm.omap4.clkctrl_offs);
+        if (_are_any_hardreset_lines_asserted(oh))
+                return 0;
+        v = _omap4_wait_target_disable(oh);
+        if (v)
+                pr_warn("omap_hwmod: %s: _wait_target_disable failed\n",
+                        oh->name);
+        return 0;
+}
+/**
 * _ocp_softreset - reset an omap_hwmod via the OCP_SYSCONFIG bit
 * @oh: struct omap_hwmod *
 *
 * Resets an omap_hwmod @oh via the OCP_SYSCONFIG bit.  hwmod must be
- * enabled for this to work.  Returns -EINVAL if the hwmod cannot be
+ * enabled for this to work.  Returns -ENOENT if the hwmod cannot be
- * reset this way or if the hwmod is in the wrong state, -ETIMEDOUT if
+ * reset this way, -EINVAL if the hwmod is in the wrong state,
- * the module did not reset in time, or 0 upon success.
+ * -ETIMEDOUT if the module did not reset in time, or 0 upon success.
 *
 * In OMAP3 a specific SYSSTATUS register is used to get the reset status.
 * Starting in OMAP4, some IPs do not have SYSSTATUS registers and instead
@@ -1401,7 +1620,7 @@ static int _ocp_softreset(struct omap_hwmod *oh)
        if (!oh->class->sysc ||
            !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET))
-                return -EINVAL;
+                return -ENOENT;
        /* clocks must be on for this operation */
        if (oh->_state != _HWMOD_STATE_ENABLED) {
@@ -1422,6 +1641,9 @@ static int _ocp_softreset(struct omap_hwmod *oh)
                goto dis_opt_clks;
        _write_sysconfig(v, oh);
+        if (oh->class->sysc->srst_udelay)
+                udelay(oh->class->sysc->srst_udelay);
        if (oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)
                omap_test_timeout((omap_hwmod_read(oh,
                                                    oh->class->sysc->syss_offs)
@@ -1459,32 +1681,60 @@ dis_opt_clks:
 * _reset - reset an omap_hwmod
 * @oh: struct omap_hwmod *
 *
- * Resets an omap_hwmod @oh.  The default software reset mechanism for
+ * Resets an omap_hwmod @oh.  If the module has a custom reset
- * most OMAP IP blocks is triggered via the OCP_SYSCONFIG.SOFTRESET
+ * function pointer defined, then call it to reset the IP block, and
- * bit.  However, some hwmods cannot be reset via this method: some
+ * pass along its return value to the caller.  Otherwise, if the IP
- * are not targets and therefore have no OCP header registers to
+ * block has an OCP_SYSCONFIG register with a SOFTRESET bitfield
- * access; others (like the IVA) have idiosyncratic reset sequences.
+ * associated with it, call a function to reset the IP block via that
- * So for these relatively rare cases, custom reset code can be
+ * method, and pass along the return value to the caller.  Finally, if
- * supplied in the struct omap_hwmod_class .reset function pointer.
+ * the IP block has some hardreset lines associated with it, assert
- * Passes along the return value from either _reset() or the custom
+ * all of those, but do _not_ deassert them. (This is because driver
- * reset function - these must return -EINVAL if the hwmod cannot be
+ * authors have expressed an apparent requirement to control the
- * reset this way or if the hwmod is in the wrong state, -ETIMEDOUT if
+ * deassertion of the hardreset lines themselves.)
- * the module did not reset in time, or 0 upon success.
+ *
+ * The default software reset mechanism for most OMAP IP blocks is
+ * triggered via the OCP_SYSCONFIG.SOFTRESET bit.  However, some
+ * hwmods cannot be reset via this method.  Some are not targets and
+ * therefore have no OCP header registers to access.  Others (like the
+ * IVA) have idiosyncratic reset sequences.  So for these relatively
+ * rare cases, custom reset code can be supplied in the struct
+ * omap_hwmod_class .reset function pointer.  Passes along the return
+ * value from either _ocp_softreset() or the custom reset function -
+ * these must return -EINVAL if the hwmod cannot be reset this way or
+ * if the hwmod is in the wrong state, -ETIMEDOUT if the module did
+ * not reset in time, or 0 upon success.
 */
 static int _reset(struct omap_hwmod *oh)
 {
-        int ret;
+        int i, r;
        pr_debug("omap_hwmod: %s: resetting\n", oh->name);
-        ret = (oh->class->reset) ? oh->class->reset(oh) : _ocp_softreset(oh);
+        if (oh->class->reset) {
+                r = oh->class->reset(oh);
+        } else {
+                if (oh->rst_lines_cnt > 0) {
+                        for (i = 0; i < oh->rst_lines_cnt; i++)
+                                _assert_hardreset(oh, oh->rst_lines[i].name);
+                        return 0;
+                } else {
+                        r = _ocp_softreset(oh);
+                        if (r == -ENOENT)
+                                r = 0;
+                }
+        }
+        /*
+         * OCP_SYSCONFIG bits need to be reprogrammed after a
+         * softreset.  The _enable() function should be split to avoid
+         * the rewrite of the OCP_SYSCONFIG register.
+         */
        if (oh->class->sysc) {
                _update_sysc_cache(oh);
                _enable_sysc(oh);
        }
-        return ret;
+        return r;
 }
 /**
@@ -1503,10 +1753,9 @@ static int _enable(struct omap_hwmod *oh)
        pr_debug("omap_hwmod: %s: enabling\n", oh->name);
        /*
-         * hwmods with HWMOD_INIT_NO_IDLE flag set are left
+         * hwmods with HWMOD_INIT_NO_IDLE flag set are left in enabled
-         * in enabled state at init.
+         * state at init.  Now that someone is really trying to enable
-         * Now that someone is really trying to enable them,
+         * them, just ensure that the hwmod mux is set.
-         * just ensure that the hwmod mux is set.
         */
        if (oh->_int_flags & _HWMOD_SKIP_ENABLE) {
                /*
@@ -1529,15 +1778,17 @@ static int _enable(struct omap_hwmod *oh)
                return -EINVAL;
        }
        /*
-         * If an IP contains only one HW reset line, then de-assert it in order
+         * If an IP block contains HW reset lines and any of them are
-         * to allow the module state transition. Otherwise the PRCM will return
+         * asserted, we let integration code associated with that
-         * Intransition status, and the init will failed.
+         * block handle the enable.  We've received very little
+         * information on what those driver authors need, and until
+         * detailed information is provided and the driver code is
+         * posted to the public lists, this is probably the best we
+         * can do.
         */
-        if ((oh->_state == _HWMOD_STATE_INITIALIZED ||
+        if (_are_any_hardreset_lines_asserted(oh))
-             oh->_state == _HWMOD_STATE_DISABLED) && oh->rst_lines_cnt == 1)
+                return 0;
-                _deassert_hardreset(oh, oh->rst_lines[0].name);
        /* Mux pins for device runtime if populated */
        if (oh->mux && (!oh->mux->enabled ||
@@ -1612,6 +1863,9 @@ static int _idle(struct omap_hwmod *oh)
                return -EINVAL;
        }
+        if (_are_any_hardreset_lines_asserted(oh))
+                return 0;
        if (oh->class->sysc)
                _idle_sysc(oh);
        _del_initiator_dep(oh, mpu_oh);
@@ -1684,7 +1938,7 @@ int omap_hwmod_set_ocp_autoidle(struct omap_hwmod *oh, u8 autoidle)
 */
 static int _shutdown(struct omap_hwmod *oh)
 {
-        int ret;
+        int ret, i;
        u8 prev_state;
        if (oh->_state != _HWMOD_STATE_IDLE &&
@@ -1694,6 +1948,9 @@ static int _shutdown(struct omap_hwmod *oh)
                return -EINVAL;
        }
+        if (_are_any_hardreset_lines_asserted(oh))
+                return 0;
        pr_debug("omap_hwmod: %s: disabling\n", oh->name);
        if (oh->class->pre_shutdown) {
@@ -1725,12 +1982,8 @@ static int _shutdown(struct omap_hwmod *oh)
        }
        /* XXX Should this code also force-disable the optional clocks? */
-        /*
+        for (i = 0; i < oh->rst_lines_cnt; i++)
-         * If an IP contains only one HW reset line, then assert it
+                _assert_hardreset(oh, oh->rst_lines[i].name);
-         * after disabling the clocks and before shutting down the IP.
-         */
-        if (oh->rst_lines_cnt == 1)
-                _assert_hardreset(oh, oh->rst_lines[0].name);
        /* Mux pins to safe mode or use populated off mode values */
        if (oh->mux)
@@ -1742,59 +1995,186 @@ static int _shutdown(struct omap_hwmod *oh)
 }
 /**
- * _setup - do initial configuration of omap_hwmod
+ * _init_mpu_rt_base - populate the virtual address for a hwmod
- * @oh: struct omap_hwmod *
+ * @oh: struct omap_hwmod * to locate the virtual address
 *
- * Writes the CLOCKACTIVITY bits @clockact to the hwmod @oh
+ * Cache the virtual address used by the MPU to access this IP block's
- * OCP_SYSCONFIG register.  Returns 0.
+ * registers.  This address is needed early so the OCP registers that
+ * are part of the device's address space can be ioremapped properly.
+ * No return value.
 */
-static int _setup(struct omap_hwmod *oh, void *data)
+static void __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data)
 {
-        int i, r;
+        struct omap_hwmod_addr_space *mem;
-        u8 postsetup_state;
+        void __iomem *va_start;
+        if (!oh)
+                return;
+        _save_mpu_port_index(oh);
+        if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
+                return;
+        mem = _find_mpu_rt_addr_space(oh);
+        if (!mem) {
+                pr_debug("omap_hwmod: %s: no MPU register target found\n",
+                         oh->name);
+                return;
+        }
+        va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start);
+        if (!va_start) {
+                pr_err("omap_hwmod: %s: Could not ioremap\n", oh->name);
+                return;
+        }
+        pr_debug("omap_hwmod: %s: MPU register target at va %p\n",
+                 oh->name, va_start);
+        oh->_mpu_rt_va = va_start;
+}
+/**
+ * _init - initialize internal data for the hwmod @oh
+ * @oh: struct omap_hwmod *
+ * @n: (unused)
+ *
+ * Look up the clocks and the address space used by the MPU to access
+ * registers belonging to the hwmod @oh.  @oh must already be
+ * registered at this point.  This is the first of two phases for
+ * hwmod initialization.  Code called here does not touch any hardware
+ * registers, it simply prepares internal data structures.  Returns 0
+ * upon success or if the hwmod isn't registered, or -EINVAL upon
+ * failure.
+ */
+static int __init _init(struct omap_hwmod *oh, void *data)
+{
+        int r;
-        if (oh->_state != _HWMOD_STATE_CLKS_INITED)
+        if (oh->_state != _HWMOD_STATE_REGISTERED)
                return 0;
-        /* Set iclk autoidle mode */
+        _init_mpu_rt_base(oh, NULL);
-        if (oh->slaves_cnt > 0) {
-                for (i = 0; i < oh->slaves_cnt; i++) {
-                        struct omap_hwmod_ocp_if *os = oh->slaves[i];
-                        struct clk *c = os->_clk;
-                        if (!c)
+        r = _init_clocks(oh, NULL);
-                                continue;
+        if (IS_ERR_VALUE(r)) {
+                WARN(1, "omap_hwmod: %s: couldn't init clocks\n", oh->name);
+                return -EINVAL;
+        }
-                        if (os->flags & OCPIF_SWSUP_IDLE) {
+        oh->_state = _HWMOD_STATE_INITIALIZED;
-                                /* XXX omap_iclk_deny_idle(c); */
-                        } else {
+        return 0;
-                                /* XXX omap_iclk_allow_idle(c); */
+}
-                                clk_enable(c);
-                        }
+/**
+ * _setup_iclk_autoidle - configure an IP block's interface clocks
+ * @oh: struct omap_hwmod *
+ *
+ * Set up the module's interface clocks.  XXX This function is still mostly
+ * a stub; implementing this properly requires iclk autoidle usecounting in
+ * the clock code.   No return value.
+ */
+static void __init _setup_iclk_autoidle(struct omap_hwmod *oh)
+{
+        struct omap_hwmod_ocp_if *os;
+        struct list_head *p;
+        int i = 0;
+        if (oh->_state != _HWMOD_STATE_INITIALIZED)
+                return;
+        p = oh->slave_ports.next;
+        while (i < oh->slaves_cnt) {
+                os = _fetch_next_ocp_if(&p, &i);
+                if (!os->_clk)
+                        continue;
+                if (os->flags & OCPIF_SWSUP_IDLE) {
+                        /* XXX omap_iclk_deny_idle(c); */
+                } else {
+                        /* XXX omap_iclk_allow_idle(c); */
+                        clk_enable(os->_clk);
                }
        }
-        oh->_state = _HWMOD_STATE_INITIALIZED;
+        return;
+}
-        /*
+/**
-         * In the case of hwmod with hardreset that should not be
+ * _setup_reset - reset an IP block during the setup process
-         * de-assert at boot time, we have to keep the module
+ * @oh: struct omap_hwmod *
-         * initialized, because we cannot enable it properly with the
+ *
-         * reset asserted. Exit without warning because that behavior is
+ * Reset the IP block corresponding to the hwmod @oh during the setup
-         * expected.
+ * process.  The IP block is first enabled so it can be successfully
-         */
+ * reset.  Returns 0 upon success or a negative error code upon
-        if ((oh->flags & HWMOD_INIT_NO_RESET) && oh->rst_lines_cnt == 1)
+ * failure.
-                return 0;
+ */
+static int __init _setup_reset(struct omap_hwmod *oh)
+{
+        int r;
-        r = _enable(oh);
+        if (oh->_state != _HWMOD_STATE_INITIALIZED)
-        if (r) {
+                return -EINVAL;
-                pr_warning("omap_hwmod: %s: cannot be enabled (%d)\n",
-                           oh->name, oh->_state);
+        if (oh->rst_lines_cnt == 0) {
-                return 0;
+                r = _enable(oh);
+                if (r) {
+                        pr_warning("omap_hwmod: %s: cannot be enabled for reset (%d)\n",
+                                   oh->name, oh->_state);
+                        return -EINVAL;
+                }
        }
        if (!(oh->flags & HWMOD_INIT_NO_RESET))
-                _reset(oh);
+                r = _reset(oh);
+        return r;
+}
+/**
+ * _setup_postsetup - transition to the appropriate state after _setup
+ * @oh: struct omap_hwmod *
+ *
+ * Place an IP block represented by @oh into a "post-setup" state --
+ * either IDLE, ENABLED, or DISABLED.  ("post-setup" simply means that
+ * this function is called at the end of _setup().)  The postsetup
+ * state for an IP block can be changed by calling
+ * omap_hwmod_enter_postsetup_state() early in the boot process,
+ * before one of the omap_hwmod_setup*() functions are called for the
+ * IP block.
+ *
+ * The IP block stays in this state until a PM runtime-based driver is
+ * loaded for that IP block.  A post-setup state of IDLE is
+ * appropriate for almost all IP blocks with runtime PM-enabled
+ * drivers, since those drivers are able to enable the IP block.  A
+ * post-setup state of ENABLED is appropriate for kernels with PM
+ * runtime disabled.  The DISABLED state is appropriate for unusual IP
+ * blocks such as the MPU WDTIMER on kernels without WDTIMER drivers
+ * included, since the WDTIMER starts running on reset and will reset
+ * the MPU if left active.
+ *
+ * This post-setup mechanism is deprecated.  Once all of the OMAP
+ * drivers have been converted to use PM runtime, and all of the IP
+ * block data and interconnect data is available to the hwmod code, it
+ * should be possible to replace this mechanism with a "lazy reset"
+ * arrangement.  In a "lazy reset" setup, each IP block is enabled
+ * when the driver first probes, then all remaining IP blocks without
+ * drivers are either shut down or enabled after the drivers have
+ * loaded.  However, this cannot take place until the above
+ * preconditions have been met, since otherwise the late reset code
+ * has no way of knowing which IP blocks are in use by drivers, and
+ * which ones are unused.
+ *
+ * No return value.
+ */
+static void __init _setup_postsetup(struct omap_hwmod *oh)
+{
+        u8 postsetup_state;
+        if (oh->rst_lines_cnt > 0)
+                return;
        postsetup_state = oh->_postsetup_state;
        if (postsetup_state == _HWMOD_STATE_UNKNOWN)
@@ -1818,6 +2198,35 @@ static int _setup(struct omap_hwmod *oh, void *data)
                WARN(1, "hwmod: %s: unknown postsetup state %d! defaulting to enabled\n",
                     oh->name, postsetup_state);
+        return;
+}
+/**
+ * _setup - prepare IP block hardware for use
+ * @oh: struct omap_hwmod *
+ * @n: (unused, pass NULL)
+ *
+ * Configure the IP block represented by @oh.  This may include
+ * enabling the IP block, resetting it, and placing it into a
+ * post-setup state, depending on the type of IP block and applicable
+ * flags.  IP blocks are reset to prevent any previous configuration
+ * by the bootloader or previous operating system from interfering
+ * with power management or other parts of the system.  The reset can
+ * be avoided; see omap_hwmod_no_setup_reset().  This is the second of
+ * two phases for hwmod initialization.  Code called here generally
+ * affects the IP block hardware, or system integration hardware
+ * associated with the IP block.  Returns 0.
+ */
+static int __init _setup(struct omap_hwmod *oh, void *data)
+{
+        if (oh->_state != _HWMOD_STATE_INITIALIZED)
+                return 0;
+        _setup_iclk_autoidle(oh);
+        if (!_setup_reset(oh))
+                _setup_postsetup(oh);
        return 0;
 }
@@ -1840,8 +2249,6 @@ static int _setup(struct omap_hwmod *oh, void *data)
 */
 static int __init _register(struct omap_hwmod *oh)
 {
-        int ms_id;
        if (!oh || !oh->name || !oh->class || !oh->class->name ||
            (oh->_state != _HWMOD_STATE_UNKNOWN))
                return -EINVAL;
@@ -1851,14 +2258,10 @@ static int __init _register(struct omap_hwmod *oh)
        if (_lookup(oh->name))
                return -EEXIST;
-        ms_id = _find_mpu_port_index(oh);
-        if (!IS_ERR_VALUE(ms_id))
-                oh->_mpu_port_index = ms_id;
-        else
-                oh->_int_flags |= _HWMOD_NO_MPU_PORT;
        list_add_tail(&oh->node, &omap_hwmod_list);
+        INIT_LIST_HEAD(&oh->master_ports);
+        INIT_LIST_HEAD(&oh->slave_ports);
        spin_lock_init(&oh->_lock);
        oh->_state = _HWMOD_STATE_REGISTERED;
@@ -1873,6 +2276,160 @@ static int __init _register(struct omap_hwmod *oh)
        return 0;
 }
+/**
+ * _alloc_links - return allocated memory for hwmod links
+ * @ml: pointer to a struct omap_hwmod_link * for the master link
+ * @sl: pointer to a struct omap_hwmod_link * for the slave link
+ *
+ * Return pointers to two struct omap_hwmod_link records, via the
+ * addresses pointed to by @ml and @sl.  Will first attempt to return
+ * memory allocated as part of a large initial block, but if that has
+ * been exhausted, will allocate memory itself.  Since ideally this
+ * second allocation path will never occur, the number of these
+ * 'supplemental' allocations will be logged when debugging is
+ * enabled.  Returns 0.
+ */
+static int __init _alloc_links(struct omap_hwmod_link **ml,
+                               struct omap_hwmod_link **sl)
+{
+        unsigned int sz;
+        if ((free_ls + LINKS_PER_OCP_IF) <= max_ls) {
+                *ml = &linkspace[free_ls++];
+                *sl = &linkspace[free_ls++];
+                return 0;
+        }
+        sz = sizeof(struct omap_hwmod_link) * LINKS_PER_OCP_IF;
+        *sl = NULL;
+        *ml = alloc_bootmem(sz);
+        memset(*ml, 0, sz);
+        *sl = (void *)(*ml) + sizeof(struct omap_hwmod_link);
+        ls_supp++;
+        pr_debug("omap_hwmod: supplemental link allocations needed: %d\n",
+                 ls_supp * LINKS_PER_OCP_IF);
+        return 0;
+};
+/**
+ * _add_link - add an interconnect between two IP blocks
+ * @oi: pointer to a struct omap_hwmod_ocp_if record
+ *
+ * Add struct omap_hwmod_link records connecting the master IP block
+ * specified in @oi->master to @oi, and connecting the slave IP block
+ * specified in @oi->slave to @oi.  This code is assumed to run before
+ * preemption or SMP has been enabled, thus avoiding the need for
+ * locking in this code.  Changes to this assumption will require
+ * additional locking.  Returns 0.
+ */
+static int __init _add_link(struct omap_hwmod_ocp_if *oi)
+{
+        struct omap_hwmod_link *ml, *sl;
+        pr_debug("omap_hwmod: %s -> %s: adding link\n", oi->master->name,
+                 oi->slave->name);
+        _alloc_links(&ml, &sl);
+        ml->ocp_if = oi;
+        INIT_LIST_HEAD(&ml->node);
+        list_add(&ml->node, &oi->master->master_ports);
+        oi->master->masters_cnt++;
+        sl->ocp_if = oi;
+        INIT_LIST_HEAD(&sl->node);
+        list_add(&sl->node, &oi->slave->slave_ports);
+        oi->slave->slaves_cnt++;
+        return 0;
+}
+/**
+ * _register_link - register a struct omap_hwmod_ocp_if
+ * @oi: struct omap_hwmod_ocp_if *
+ *
+ * Registers the omap_hwmod_ocp_if record @oi.  Returns -EEXIST if it
+ * has already been registered; -EINVAL if @oi is NULL or if the
+ * record pointed to by @oi is missing required fields; or 0 upon
+ * success.
+ *
+ * XXX The data should be copied into bootmem, so the original data
+ * should be marked __initdata and freed after init.  This would allow
+ * unneeded omap_hwmods to be freed on multi-OMAP configurations.
+ */
+static int __init _register_link(struct omap_hwmod_ocp_if *oi)
+{
+        if (!oi || !oi->master || !oi->slave || !oi->user)
+                return -EINVAL;
+        if (oi->_int_flags & _OCPIF_INT_FLAGS_REGISTERED)
+                return -EEXIST;
+        pr_debug("omap_hwmod: registering link from %s to %s\n",
+                 oi->master->name, oi->slave->name);
+        /*
+         * Register the connected hwmods, if they haven't been
+         * registered already
+         */
+        if (oi->master->_state != _HWMOD_STATE_REGISTERED)
+                _register(oi->master);
+        if (oi->slave->_state != _HWMOD_STATE_REGISTERED)
+                _register(oi->slave);
+        _add_link(oi);
+        oi->_int_flags |= _OCPIF_INT_FLAGS_REGISTERED;
+        return 0;
+}
+/**
+ * _alloc_linkspace - allocate large block of hwmod links
+ * @ois: pointer to an array of struct omap_hwmod_ocp_if records to count
+ *
+ * Allocate a large block of struct omap_hwmod_link records.  This
+ * improves boot time significantly by avoiding the need to allocate
+ * individual records one by one.  If the number of records to
+ * allocate in the block hasn't been manually specified, this function
+ * will count the number of struct omap_hwmod_ocp_if records in @ois
+ * and use that to determine the allocation size.  For SoC families
+ * that require multiple list registrations, such as OMAP3xxx, this
+ * estimation process isn't optimal, so manual estimation is advised
+ * in those cases.  Returns -EEXIST if the allocation has already occurred
+ * or 0 upon success.
+ */
+static int __init _alloc_linkspace(struct omap_hwmod_ocp_if **ois)
+{
+        unsigned int i = 0;
+        unsigned int sz;
+        if (linkspace) {
+                WARN(1, "linkspace already allocated\n");
+                return -EEXIST;
+        }
+        if (max_ls == 0)
+                while (ois[i++])
+                        max_ls += LINKS_PER_OCP_IF;
+        sz = sizeof(struct omap_hwmod_link) * max_ls;
+        pr_debug("omap_hwmod: %s: allocating %d byte linkspace (%d links)\n",
+                 __func__, sz, max_ls);
+        linkspace = alloc_bootmem(sz);
+        memset(linkspace, 0, sz);
+        return 0;
+}
 /* Public functions */
@@ -1903,10 +2460,20 @@ void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs)
 */
 int omap_hwmod_softreset(struct omap_hwmod *oh)
 {
-        if (!oh)
+        u32 v;
+        int ret;
+        if (!oh || !(oh->_sysc_cache))
                return -EINVAL;
-        return _ocp_softreset(oh);
+        v = oh->_sysc_cache;
+        ret = _set_softreset(oh, &v);
+        if (ret)
+                goto error;
+        _write_sysconfig(v, oh);
+error:
+        return ret;
 }
 /**
@@ -1991,120 +2558,101 @@ int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data),
 }
 /**
- * omap_hwmod_register - register an array of hwmods
+ * omap_hwmod_register_links - register an array of hwmod links
- * @ohs: pointer to an array of omap_hwmods to register
+ * @ois: pointer to an array of omap_hwmod_ocp_if to register
 *
 * Intended to be called early in boot before the clock framework is
- * initialized.  If @ohs is not null, will register all omap_hwmods
+ * initialized.  If @ois is not null, will register all omap_hwmods
- * listed in @ohs that are valid for this chip.  Returns 0.
+ * listed in @ois that are valid for this chip.  Returns 0.
 */
-int __init omap_hwmod_register(struct omap_hwmod **ohs)
+int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois)
 {
        int r, i;
-        if (!ohs)
+        if (!ois)
                return 0;
+        if (!linkspace) {
+                if (_alloc_linkspace(ois)) {
+                        pr_err("omap_hwmod: could not allocate link space\n");
+                        return -ENOMEM;
+                }
+        }
        i = 0;
        do {
-                r = _register(ohs[i]);
+                r = _register_link(ois[i]);
-                WARN(r, "omap_hwmod: %s: _register returned %d\n", ohs[i]->name,
+                WARN(r && r != -EEXIST,
-                     r);
+                     "omap_hwmod: _register_link(%s -> %s) returned %d\n",
-        } while (ohs[++i]);
+                     ois[i]->master->name, ois[i]->slave->name, r);
+        } while (ois[++i]);
        return 0;
 }
-/*
+/**
- * _populate_mpu_rt_base - populate the virtual address for a hwmod
+ * _ensure_mpu_hwmod_is_setup - ensure the MPU SS hwmod is init'ed and set up
+ * @oh: pointer to the hwmod currently being set up (usually not the MPU)
 *
- * Must be called only from omap_hwmod_setup_*() so ioremap works properly.
+ * If the hwmod data corresponding to the MPU subsystem IP block
- * Assumes the caller takes care of locking if needed.
+ * hasn't been initialized and set up yet, do so now.  This must be
+ * done first since sleep dependencies may be added from other hwmods
+ * to the MPU.  Intended to be called only by omap_hwmod_setup*().  No
+ * return value.
 */
-static int __init _populate_mpu_rt_base(struct omap_hwmod *oh, void *data)
+static void __init _ensure_mpu_hwmod_is_setup(struct omap_hwmod *oh)
 {
-        if (oh->_state != _HWMOD_STATE_REGISTERED)
+        if (!mpu_oh || mpu_oh->_state == _HWMOD_STATE_UNKNOWN)
-                return 0;
+                pr_err("omap_hwmod: %s: MPU initiator hwmod %s not yet registered\n",
+                       __func__, MPU_INITIATOR_NAME);
-        if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
+        else if (mpu_oh->_state == _HWMOD_STATE_REGISTERED && oh != mpu_oh)
-                return 0;
+                omap_hwmod_setup_one(MPU_INITIATOR_NAME);
-        oh->_mpu_rt_va = _find_mpu_rt_base(oh, oh->_mpu_port_index);
-        return 0;
 }
 /**
 * omap_hwmod_setup_one - set up a single hwmod
 * @oh_name: const char * name of the already-registered hwmod to set up
 *
- * Must be called after omap2_clk_init().  Resolves the struct clk
+ * Initialize and set up a single hwmod.  Intended to be used for a
- * names to struct clk pointers for each registered omap_hwmod.  Also
+ * small number of early devices, such as the timer IP blocks used for
- * calls _setup() on each hwmod.  Returns -EINVAL upon error or 0 upon
+ * the scheduler clock.  Must be called after omap2_clk_init().
- * success.
+ * Resolves the struct clk names to struct clk pointers for each
+ * registered omap_hwmod.  Also calls _setup() on each hwmod.  Returns
+ * -EINVAL upon error or 0 upon success.
 */
 int __init omap_hwmod_setup_one(const char *oh_name)
 {
        struct omap_hwmod *oh;
-        int r;
        pr_debug("omap_hwmod: %s: %s\n", oh_name, __func__);
-        if (!mpu_oh) {
-                pr_err("omap_hwmod: %s: cannot setup_one: MPU initiator hwmod %s not yet registered\n",
-                       oh_name, MPU_INITIATOR_NAME);
-                return -EINVAL;
-        }
        oh = _lookup(oh_name);
        if (!oh) {
                WARN(1, "omap_hwmod: %s: hwmod not yet registered\n", oh_name);
                return -EINVAL;
        }
-        if (mpu_oh->_state == _HWMOD_STATE_REGISTERED && oh != mpu_oh)
+        _ensure_mpu_hwmod_is_setup(oh);
-                omap_hwmod_setup_one(MPU_INITIATOR_NAME);
-        r = _populate_mpu_rt_base(oh, NULL);
-        if (IS_ERR_VALUE(r)) {
-                WARN(1, "omap_hwmod: %s: couldn't set mpu_rt_base\n", oh_name);
-                return -EINVAL;
-        }
-        r = _init_clocks(oh, NULL);
-        if (IS_ERR_VALUE(r)) {
-                WARN(1, "omap_hwmod: %s: couldn't init clocks\n", oh_name);
-                return -EINVAL;
-        }
+        _init(oh, NULL);
        _setup(oh, NULL);
        return 0;
 }
 /**
- * omap_hwmod_setup - do some post-clock framework initialization
+ * omap_hwmod_setup_all - set up all registered IP blocks
 *
- * Must be called after omap2_clk_init().  Resolves the struct clk names
+ * Initialize and set up all IP blocks registered with the hwmod code.
- * to struct clk pointers for each registered omap_hwmod.  Also calls
+ * Must be called after omap2_clk_init().  Resolves the struct clk
- * _setup() on each hwmod.  Returns 0 upon success.
+ * names to struct clk pointers for each registered omap_hwmod.  Also
+ * calls _setup() on each hwmod.  Returns 0 upon success.
 */
 static int __init omap_hwmod_setup_all(void)
 {
-        int r;
+        _ensure_mpu_hwmod_is_setup(NULL);
-        if (!mpu_oh) {
-                pr_err("omap_hwmod: %s: MPU initiator hwmod %s not yet registered\n",
-                       __func__, MPU_INITIATOR_NAME);
-                return -EINVAL;
-        }
-        r = omap_hwmod_for_each(_populate_mpu_rt_base, NULL);
-        r = omap_hwmod_for_each(_init_clocks, NULL);
-        WARN(IS_ERR_VALUE(r),
-             "omap_hwmod: %s: _init_clocks failed\n", __func__);
+        omap_hwmod_for_each(_init, NULL);
        omap_hwmod_for_each(_setup, NULL);
        return 0;
@@ -2261,6 +2809,10 @@ int omap_hwmod_reset(struct omap_hwmod *oh)
        return r;
 }
+/*
+ * IP block data retrieval functions
+ */
 /**
 * omap_hwmod_count_resources - count number of struct resources needed by hwmod
 * @oh: struct omap_hwmod *
@@ -2279,12 +2831,19 @@ int omap_hwmod_reset(struct omap_hwmod *oh)
 */
 int omap_hwmod_count_resources(struct omap_hwmod *oh)
 {
-        int ret, i;
+        struct omap_hwmod_ocp_if *os;
+        struct list_head *p;
+        int ret;
+        int i = 0;
        ret = _count_mpu_irqs(oh) + _count_sdma_reqs(oh);
-        for (i = 0; i < oh->slaves_cnt; i++)
+        p = oh->slave_ports.next;
-                ret += _count_ocp_if_addr_spaces(oh->slaves[i]);
+        while (i < oh->slaves_cnt) {
+                os = _fetch_next_ocp_if(&p, &i);
+                ret += _count_ocp_if_addr_spaces(os);
+        }
        return ret;
 }
@@ -2301,7 +2860,9 @@ int omap_hwmod_count_resources(struct omap_hwmod *oh)
 */
 int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
 {
-        int i, j, mpu_irqs_cnt, sdma_reqs_cnt;
+        struct omap_hwmod_ocp_if *os;
+        struct list_head *p;
+        int i, j, mpu_irqs_cnt, sdma_reqs_cnt, addr_cnt;
        int r = 0;
        /* For each IRQ, DMA, memory area, fill in array.*/
@@ -2324,11 +2885,11 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
                r++;
        }
-        for (i = 0; i < oh->slaves_cnt; i++) {
+        p = oh->slave_ports.next;
-                struct omap_hwmod_ocp_if *os;
-                int addr_cnt;
-                os = oh->slaves[i];
+        i = 0;
+        while (i < oh->slaves_cnt) {
+                os = _fetch_next_ocp_if(&p, &i);
                addr_cnt = _count_ocp_if_addr_spaces(os);
                for (j = 0; j < addr_cnt; j++) {
@@ -2344,6 +2905,69 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
 }
 /**
+ * omap_hwmod_get_resource_byname - fetch IP block integration data by name
+ * @oh: struct omap_hwmod * to operate on
+ * @type: one of the IORESOURCE_* constants from include/linux/ioport.h
+ * @name: pointer to the name of the data to fetch (optional)
+ * @rsrc: pointer to a struct resource, allocated by the caller
+ *
+ * Retrieve MPU IRQ, SDMA request line, or address space start/end
+ * data for the IP block pointed to by @oh.  The data will be filled
+ * into a struct resource record pointed to by @rsrc.  The struct
+ * resource must be allocated by the caller.  When @name is non-null,
+ * the data associated with the matching entry in the IRQ/SDMA/address
+ * space hwmod data arrays will be returned.  If @name is null, the
+ * first array entry will be returned.  Data order is not meaningful
+ * in hwmod data, so callers are strongly encouraged to use a non-null
+ * @name whenever possible to avoid unpredictable effects if hwmod
+ * data is later added that causes data ordering to change.  This
+ * function is only intended for use by OMAP core code.  Device
+ * drivers should not call this function - the appropriate bus-related
+ * data accessor functions should be used instead.  Returns 0 upon
+ * success or a negative error code upon error.
+ */
+int omap_hwmod_get_resource_byname(struct omap_hwmod *oh, unsigned int type,
+                                   const char *name, struct resource *rsrc)
+{
+        int r;
+        unsigned int irq, dma;
+        u32 pa_start, pa_end;
+        if (!oh || !rsrc)
+                return -EINVAL;
+        if (type == IORESOURCE_IRQ) {
+                r = _get_mpu_irq_by_name(oh, name, &irq);
+                if (r)
+                        return r;
+                rsrc->start = irq;
+                rsrc->end = irq;
+        } else if (type == IORESOURCE_DMA) {
+                r = _get_sdma_req_by_name(oh, name, &dma);
+                if (r)
+                        return r;
+                rsrc->start = dma;
+                rsrc->end = dma;
+        } else if (type == IORESOURCE_MEM) {
+                r = _get_addr_space_by_name(oh, name, &pa_start, &pa_end);
+                if (r)
+                        return r;
+                rsrc->start = pa_start;
+                rsrc->end = pa_end;
+        } else {
+                return -EINVAL;
+        }
+        rsrc->flags = type;
+        rsrc->name = name;
+        return 0;
+}
+/**
 * omap_hwmod_get_pwrdm - return pointer to this module's main powerdomain
 * @oh: struct omap_hwmod *
 *
@@ -2357,6 +2981,7 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
 struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh)
 {
        struct clk *c;
+        struct omap_hwmod_ocp_if *oi;
        if (!oh)
                return NULL;
@@ -2364,9 +2989,10 @@ struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh)
        if (oh->_clk) {
                c = oh->_clk;
        } else {
-                if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
+                oi = _find_mpu_rt_port(oh);
+                if (!oi)
                        return NULL;
-                c = oh->slaves[oh->_mpu_port_index]->_clk;
+                c = oi->_clk;
        }
        if (!c->clkdm)
@@ -2640,10 +3266,10 @@ int omap_hwmod_for_each_by_class(const char *classname,
 * @state: state that _setup() should leave the hwmod in
 *
 * Sets the hwmod state that @oh will enter at the end of _setup()
- * (called by omap_hwmod_setup_*()).  Only valid to call between
+ * (called by omap_hwmod_setup_*()).  See also the documentation
- * calling omap_hwmod_register() and omap_hwmod_setup_*().  Returns
+ * for _setup_postsetup(), above.  Returns 0 upon success or
- * 0 upon success or -EINVAL if there is a problem with the arguments
+ * -EINVAL if there is a problem with the arguments or if the hwmod is
- * or if the hwmod is in the wrong state.
+ * in the wrong state.
 */
 int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state)
 {
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index a5409ce3f323..a7640d1b215e 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -2,6 +2,7 @@
 * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips
 *
 * Copyright (C) 2009-2011 Nokia Corporation
+ * Copyright (C) 2012 Texas Instruments, Inc.
 * Paul Walmsley
 *
 * This program is free software; you can redistribute it and/or modify
@@ -22,6 +23,7 @@
 #include <plat/dmtimer.h>
 #include <plat/l3_2xxx.h>
 #include <plat/l4_2xxx.h>
+#include <plat/mmc.h>
 #include "omap_hwmod_common_data.h"
@@ -32,707 +34,329 @@
 /*
 * OMAP2420 hardware module integration data
 *
- * ALl of the data in this section should be autogeneratable from the
+ * All of the data in this section should be autogeneratable from the
 * TI hardware database or other technical documentation.  Data that
 * is driver-specific or driver-kernel integration-specific belongs
 * elsewhere.
 */
-static struct omap_hwmod omap2420_mpu_hwmod;
-static struct omap_hwmod omap2420_iva_hwmod;
-static struct omap_hwmod omap2420_l3_main_hwmod;
-static struct omap_hwmod omap2420_l4_core_hwmod;
-static struct omap_hwmod omap2420_dss_core_hwmod;
-static struct omap_hwmod omap2420_dss_dispc_hwmod;
-static struct omap_hwmod omap2420_dss_rfbi_hwmod;
-static struct omap_hwmod omap2420_dss_venc_hwmod;
-static struct omap_hwmod omap2420_wd_timer2_hwmod;
-static struct omap_hwmod omap2420_gpio1_hwmod;
-static struct omap_hwmod omap2420_gpio2_hwmod;
-static struct omap_hwmod omap2420_gpio3_hwmod;
-static struct omap_hwmod omap2420_gpio4_hwmod;
-static struct omap_hwmod omap2420_dma_system_hwmod;
-static struct omap_hwmod omap2420_mcspi1_hwmod;
-static struct omap_hwmod omap2420_mcspi2_hwmod;
-/* L3 -> L4_CORE interface */
-static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = {
-        .master = &omap2420_l3_main_hwmod,
-        .slave  = &omap2420_l4_core_hwmod,
-        .user   = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* MPU -> L3 interface */
-static struct omap_hwmod_ocp_if omap2420_mpu__l3_main = {
-        .master = &omap2420_mpu_hwmod,
-        .slave  = &omap2420_l3_main_hwmod,
-        .user   = OCP_USER_MPU,
-};
-/* Slave interfaces on the L3 interconnect */
-static struct omap_hwmod_ocp_if *omap2420_l3_main_slaves[] = {
-        &omap2420_mpu__l3_main,
-};
-/* DSS -> l3 */
-static struct omap_hwmod_ocp_if omap2420_dss__l3 = {
-        .master         = &omap2420_dss_core_hwmod,
-        .slave          = &omap2420_l3_main_hwmod,
-        .fw = {
-                .omap2 = {
-                        .l3_perm_bit  = OMAP2_L3_CORE_FW_CONNID_DSS,
-                        .flags  = OMAP_FIREWALL_L3,
-                }
-        },
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* Master interfaces on the L3 interconnect */
-static struct omap_hwmod_ocp_if *omap2420_l3_main_masters[] = {
-        &omap2420_l3_main__l4_core,
-};
-/* L3 */
-static struct omap_hwmod omap2420_l3_main_hwmod = {
-        .name           = "l3_main",
-        .class          = &l3_hwmod_class,
-        .masters        = omap2420_l3_main_masters,
-        .masters_cnt    = ARRAY_SIZE(omap2420_l3_main_masters),
-        .slaves         = omap2420_l3_main_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_l3_main_slaves),
-        .flags          = HWMOD_NO_IDLEST,
-};
-static struct omap_hwmod omap2420_l4_wkup_hwmod;
-static struct omap_hwmod omap2420_uart1_hwmod;
-static struct omap_hwmod omap2420_uart2_hwmod;
-static struct omap_hwmod omap2420_uart3_hwmod;
-static struct omap_hwmod omap2420_i2c1_hwmod;
-static struct omap_hwmod omap2420_i2c2_hwmod;
-static struct omap_hwmod omap2420_mcbsp1_hwmod;
-static struct omap_hwmod omap2420_mcbsp2_hwmod;
-/* l4 core -> mcspi1 interface */
-static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi1 = {
-        .master         = &omap2420_l4_core_hwmod,
-        .slave          = &omap2420_mcspi1_hwmod,
-        .clk            = "mcspi1_ick",
-        .addr           = omap2_mcspi1_addr_space,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* l4 core -> mcspi2 interface */
-static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi2 = {
-        .master         = &omap2420_l4_core_hwmod,
-        .slave          = &omap2420_mcspi2_hwmod,
-        .clk            = "mcspi2_ick",
-        .addr           = omap2_mcspi2_addr_space,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* L4_CORE -> L4_WKUP interface */
-static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = {
-        .master = &omap2420_l4_core_hwmod,
-        .slave  = &omap2420_l4_wkup_hwmod,
-        .user   = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* L4 CORE -> UART1 interface */
-static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
-        .master         = &omap2420_l4_core_hwmod,
-        .slave          = &omap2420_uart1_hwmod,
-        .clk            = "uart1_ick",
-        .addr           = omap2xxx_uart1_addr_space,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* L4 CORE -> UART2 interface */
-static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
-        .master         = &omap2420_l4_core_hwmod,
-        .slave          = &omap2420_uart2_hwmod,
-        .clk            = "uart2_ick",
-        .addr           = omap2xxx_uart2_addr_space,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* L4 PER -> UART3 interface */
-static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
-        .master         = &omap2420_l4_core_hwmod,
-        .slave          = &omap2420_uart3_hwmod,
-        .clk            = "uart3_ick",
-        .addr           = omap2xxx_uart3_addr_space,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* L4 CORE -> I2C1 interface */
-static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
-        .master         = &omap2420_l4_core_hwmod,
-        .slave          = &omap2420_i2c1_hwmod,
-        .clk            = "i2c1_ick",
-        .addr           = omap2_i2c1_addr_space,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* L4 CORE -> I2C2 interface */
-static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
-        .master         = &omap2420_l4_core_hwmod,
-        .slave          = &omap2420_i2c2_hwmod,
-        .clk            = "i2c2_ick",
-        .addr           = omap2_i2c2_addr_space,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* Slave interfaces on the L4_CORE interconnect */
-static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = {
-        &omap2420_l3_main__l4_core,
-};
-/* Master interfaces on the L4_CORE interconnect */
-static struct omap_hwmod_ocp_if *omap2420_l4_core_masters[] = {
-        &omap2420_l4_core__l4_wkup,
-        &omap2_l4_core__uart1,
-        &omap2_l4_core__uart2,
-        &omap2_l4_core__uart3,
-        &omap2420_l4_core__i2c1,
-        &omap2420_l4_core__i2c2
-};
-/* L4 CORE */
-static struct omap_hwmod omap2420_l4_core_hwmod = {
-        .name           = "l4_core",
-        .class          = &l4_hwmod_class,
-        .masters        = omap2420_l4_core_masters,
-        .masters_cnt    = ARRAY_SIZE(omap2420_l4_core_masters),
-        .slaves         = omap2420_l4_core_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_l4_core_slaves),
-        .flags          = HWMOD_NO_IDLEST,
-};
-/* Slave interfaces on the L4_WKUP interconnect */
-static struct omap_hwmod_ocp_if *omap2420_l4_wkup_slaves[] = {
-        &omap2420_l4_core__l4_wkup,
-};
-/* Master interfaces on the L4_WKUP interconnect */
-static struct omap_hwmod_ocp_if *omap2420_l4_wkup_masters[] = {
-};
-/* L4 WKUP */
-static struct omap_hwmod omap2420_l4_wkup_hwmod = {
-        .name           = "l4_wkup",
-        .class          = &l4_hwmod_class,
-        .masters        = omap2420_l4_wkup_masters,
-        .masters_cnt    = ARRAY_SIZE(omap2420_l4_wkup_masters),
-        .slaves         = omap2420_l4_wkup_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_l4_wkup_slaves),
-        .flags          = HWMOD_NO_IDLEST,
-};
-/* Master interfaces on the MPU device */
-static struct omap_hwmod_ocp_if *omap2420_mpu_masters[] = {
-        &omap2420_mpu__l3_main,
-};
-/* MPU */
-static struct omap_hwmod omap2420_mpu_hwmod = {
-        .name           = "mpu",
-        .class          = &mpu_hwmod_class,
-        .main_clk       = "mpu_ck",
-        .masters        = omap2420_mpu_masters,
-        .masters_cnt    = ARRAY_SIZE(omap2420_mpu_masters),
-};
 /*
- * IVA1 interface data
+ * IP blocks
 */
-/* IVA <- L3 interface */
+/* IVA1 (IVA1) */
-static struct omap_hwmod_ocp_if omap2420_l3__iva = {
+static struct omap_hwmod_class iva1_hwmod_class = {
-        .master         = &omap2420_l3_main_hwmod,
+        .name           = "iva1",
-        .slave          = &omap2420_iva_hwmod,
-        .clk            = "iva1_ifck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-static struct omap_hwmod_ocp_if *omap2420_iva_masters[] = {
+static struct omap_hwmod_rst_info omap2420_iva_resets[] = {
-        &omap2420_l3__iva,
+        { .name = "iva", .rst_shift = 8 },
 };
-/*
- * IVA2 (IVA2)
- */
 static struct omap_hwmod omap2420_iva_hwmod = {
        .name           = "iva",
-        .class          = &iva_hwmod_class,
+        .class          = &iva1_hwmod_class,
-        .masters        = omap2420_iva_masters,
+        .clkdm_name     = "iva1_clkdm",
-        .masters_cnt    = ARRAY_SIZE(omap2420_iva_masters),
+        .rst_lines      = omap2420_iva_resets,
-};
+        .rst_lines_cnt  = ARRAY_SIZE(omap2420_iva_resets),
+        .main_clk       = "iva1_ifck",
-/* always-on timers dev attribute */
-static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
-        .timer_capability       = OMAP_TIMER_ALWON,
 };
-/* pwm timers dev attribute */
+/* DSP */
-static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
+static struct omap_hwmod_class dsp_hwmod_class = {
-        .timer_capability       = OMAP_TIMER_HAS_PWM,
+        .name           = "dsp",
-};
-/* timer1 */
-static struct omap_hwmod omap2420_timer1_hwmod;
-static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = {
-        {
-                .pa_start       = 0x48028000,
-                .pa_end         = 0x48028000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
 };
-/* l4_wkup -> timer1 */
+static struct omap_hwmod_rst_info omap2420_dsp_resets[] = {
-static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
+        { .name = "logic", .rst_shift = 0 },
-        .master         = &omap2420_l4_wkup_hwmod,
+        { .name = "mmu", .rst_shift = 1 },
-        .slave          = &omap2420_timer1_hwmod,
-        .clk            = "gpt1_ick",
-        .addr           = omap2420_timer1_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-/* timer1 slave port */
+static struct omap_hwmod omap2420_dsp_hwmod = {
-static struct omap_hwmod_ocp_if *omap2420_timer1_slaves[] = {
+        .name           = "dsp",
-        &omap2420_l4_wkup__timer1,
+        .class          = &dsp_hwmod_class,
+        .clkdm_name     = "dsp_clkdm",
+        .rst_lines      = omap2420_dsp_resets,
+        .rst_lines_cnt  = ARRAY_SIZE(omap2420_dsp_resets),
+        .main_clk       = "dsp_fck",
 };
-/* timer1 hwmod */
+/* I2C common */
-static struct omap_hwmod omap2420_timer1_hwmod = {
+static struct omap_hwmod_class_sysconfig i2c_sysc = {
-        .name           = "timer1",
+        .rev_offs       = 0x00,
-        .mpu_irqs       = omap2_timer1_mpu_irqs,
+        .sysc_offs      = 0x20,
-        .main_clk       = "gpt1_fck",
+        .syss_offs      = 0x10,
-        .prcm           = {
+        .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
-                .omap2 = {
+        .sysc_fields    = &omap_hwmod_sysc_type1,
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_GPT1_SHIFT,
-                        .module_offs = WKUP_MOD,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
-                },
-        },
-        .dev_attr       = &capability_alwon_dev_attr,
-        .slaves         = omap2420_timer1_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_timer1_slaves),
-        .class          = &omap2xxx_timer_hwmod_class,
 };
-/* timer2 */
+static struct omap_hwmod_class i2c_class = {
-static struct omap_hwmod omap2420_timer2_hwmod;
+        .name           = "i2c",
+        .sysc           = &i2c_sysc,
-/* l4_core -> timer2 */
+        .rev            = OMAP_I2C_IP_VERSION_1,
-static struct omap_hwmod_ocp_if omap2420_l4_core__timer2 = {
+        .reset          = &omap_i2c_reset,
-        .master         = &omap2420_l4_core_hwmod,
-        .slave          = &omap2420_timer2_hwmod,
-        .clk            = "gpt2_ick",
-        .addr           = omap2xxx_timer2_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-/* timer2 slave port */
+static struct omap_i2c_dev_attr i2c_dev_attr = {
-static struct omap_hwmod_ocp_if *omap2420_timer2_slaves[] = {
+        .flags          = OMAP_I2C_FLAG_NO_FIFO |
-        &omap2420_l4_core__timer2,
+                          OMAP_I2C_FLAG_SIMPLE_CLOCK |
+                          OMAP_I2C_FLAG_16BIT_DATA_REG |
+                          OMAP_I2C_FLAG_BUS_SHIFT_2,
 };
-/* timer2 hwmod */
+/* I2C1 */
-static struct omap_hwmod omap2420_timer2_hwmod = {
+static struct omap_hwmod omap2420_i2c1_hwmod = {
-        .name           = "timer2",
+        .name           = "i2c1",
-        .mpu_irqs       = omap2_timer2_mpu_irqs,
+        .mpu_irqs       = omap2_i2c1_mpu_irqs,
-        .main_clk       = "gpt2_fck",
+        .sdma_reqs      = omap2_i2c1_sdma_reqs,
+        .main_clk       = "i2c1_fck",
        .prcm           = {
                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_GPT2_SHIFT,
                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP2420_EN_I2C1_SHIFT,
                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
+                        .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,
                },
        },
-        .dev_attr       = &capability_alwon_dev_attr,
+        .class          = &i2c_class,
-        .slaves         = omap2420_timer2_slaves,
+        .dev_attr       = &i2c_dev_attr,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_timer2_slaves),
+        .flags          = HWMOD_16BIT_REG,
-        .class          = &omap2xxx_timer_hwmod_class,
-};
-/* timer3 */
-static struct omap_hwmod omap2420_timer3_hwmod;
-/* l4_core -> timer3 */
-static struct omap_hwmod_ocp_if omap2420_l4_core__timer3 = {
-        .master         = &omap2420_l4_core_hwmod,
-        .slave          = &omap2420_timer3_hwmod,
-        .clk            = "gpt3_ick",
-        .addr           = omap2xxx_timer3_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* timer3 slave port */
-static struct omap_hwmod_ocp_if *omap2420_timer3_slaves[] = {
-        &omap2420_l4_core__timer3,
 };
-/* timer3 hwmod */
+/* I2C2 */
-static struct omap_hwmod omap2420_timer3_hwmod = {
+static struct omap_hwmod omap2420_i2c2_hwmod = {
-        .name           = "timer3",
+        .name           = "i2c2",
-        .mpu_irqs       = omap2_timer3_mpu_irqs,
+        .mpu_irqs       = omap2_i2c2_mpu_irqs,
-        .main_clk       = "gpt3_fck",
+        .sdma_reqs      = omap2_i2c2_sdma_reqs,
+        .main_clk       = "i2c2_fck",
        .prcm           = {
                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_GPT3_SHIFT,
                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP2420_EN_I2C2_SHIFT,
                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
+                        .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,
                },
        },
-        .dev_attr       = &capability_alwon_dev_attr,
+        .class          = &i2c_class,
-        .slaves         = omap2420_timer3_slaves,
+        .dev_attr       = &i2c_dev_attr,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_timer3_slaves),
+        .flags          = HWMOD_16BIT_REG,
-        .class          = &omap2xxx_timer_hwmod_class,
 };
-/* timer4 */
+/* dma attributes */
-static struct omap_hwmod omap2420_timer4_hwmod;
+static struct omap_dma_dev_attr dma_dev_attr = {
+        .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
+                                                IS_CSSA_32 | IS_CDSA_32,
+        .lch_count = 32,
+};
-/* l4_core -> timer4 */
+static struct omap_hwmod omap2420_dma_system_hwmod = {
-static struct omap_hwmod_ocp_if omap2420_l4_core__timer4 = {
+        .name           = "dma",
-        .master         = &omap2420_l4_core_hwmod,
+        .class          = &omap2xxx_dma_hwmod_class,
-        .slave          = &omap2420_timer4_hwmod,
+        .mpu_irqs       = omap2_dma_system_irqs,
-        .clk            = "gpt4_ick",
+        .main_clk       = "core_l3_ck",
-        .addr           = omap2xxx_timer4_addrs,
+        .dev_attr       = &dma_dev_attr,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+        .flags          = HWMOD_NO_IDLEST,
 };
-/* timer4 slave port */
+/* mailbox */
-static struct omap_hwmod_ocp_if *omap2420_timer4_slaves[] = {
+static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
-        &omap2420_l4_core__timer4,
+        { .name = "dsp", .irq = 26 },
+        { .name = "iva", .irq = 34 },
+        { .irq = -1 }
 };
-/* timer4 hwmod */
+static struct omap_hwmod omap2420_mailbox_hwmod = {
-static struct omap_hwmod omap2420_timer4_hwmod = {
+        .name           = "mailbox",
-        .name           = "timer4",
+        .class          = &omap2xxx_mailbox_hwmod_class,
-        .mpu_irqs       = omap2_timer4_mpu_irqs,
+        .mpu_irqs       = omap2420_mailbox_irqs,
-        .main_clk       = "gpt4_fck",
+        .main_clk       = "mailboxes_ick",
        .prcm           = {
                .omap2 = {
                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_GPT4_SHIFT,
+                        .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
                        .module_offs = CORE_MOD,
                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
+                        .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
                },
        },
-        .dev_attr       = &capability_alwon_dev_attr,
-        .slaves         = omap2420_timer4_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_timer4_slaves),
-        .class          = &omap2xxx_timer_hwmod_class,
 };
-/* timer5 */
+/*
-static struct omap_hwmod omap2420_timer5_hwmod;
+ * 'mcbsp' class
+ * multi channel buffered serial port controller
+ */
-/* l4_core -> timer5 */
+static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
-static struct omap_hwmod_ocp_if omap2420_l4_core__timer5 = {
+        .name = "mcbsp",
-        .master         = &omap2420_l4_core_hwmod,
-        .slave          = &omap2420_timer5_hwmod,
-        .clk            = "gpt5_ick",
-        .addr           = omap2xxx_timer5_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-/* timer5 slave port */
+/* mcbsp1 */
-static struct omap_hwmod_ocp_if *omap2420_timer5_slaves[] = {
+static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = {
-        &omap2420_l4_core__timer5,
+        { .name = "tx", .irq = 59 },
+        { .name = "rx", .irq = 60 },
+        { .irq = -1 }
 };
-/* timer5 hwmod */
+static struct omap_hwmod omap2420_mcbsp1_hwmod = {
-static struct omap_hwmod omap2420_timer5_hwmod = {
+        .name           = "mcbsp1",
-        .name           = "timer5",
+        .class          = &omap2420_mcbsp_hwmod_class,
-        .mpu_irqs       = omap2_timer5_mpu_irqs,
+        .mpu_irqs       = omap2420_mcbsp1_irqs,
-        .main_clk       = "gpt5_fck",
+        .sdma_reqs      = omap2_mcbsp1_sdma_reqs,
+        .main_clk       = "mcbsp1_fck",
        .prcm           = {
                .omap2 = {
                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_GPT5_SHIFT,
+                        .module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
                        .module_offs = CORE_MOD,
                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
+                        .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
                },
        },
-        .dev_attr       = &capability_alwon_dev_attr,
-        .slaves         = omap2420_timer5_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_timer5_slaves),
-        .class          = &omap2xxx_timer_hwmod_class,
 };
+/* mcbsp2 */
-/* timer6 */
+static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = {
-static struct omap_hwmod omap2420_timer6_hwmod;
+        { .name = "tx", .irq = 62 },
+        { .name = "rx", .irq = 63 },
-/* l4_core -> timer6 */
+        { .irq = -1 }
-static struct omap_hwmod_ocp_if omap2420_l4_core__timer6 = {
-        .master         = &omap2420_l4_core_hwmod,
-        .slave          = &omap2420_timer6_hwmod,
-        .clk            = "gpt6_ick",
-        .addr           = omap2xxx_timer6_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* timer6 slave port */
-static struct omap_hwmod_ocp_if *omap2420_timer6_slaves[] = {
-        &omap2420_l4_core__timer6,
 };
-/* timer6 hwmod */
+static struct omap_hwmod omap2420_mcbsp2_hwmod = {
-static struct omap_hwmod omap2420_timer6_hwmod = {
+        .name           = "mcbsp2",
-        .name           = "timer6",
+        .class          = &omap2420_mcbsp_hwmod_class,
-        .mpu_irqs       = omap2_timer6_mpu_irqs,
+        .mpu_irqs       = omap2420_mcbsp2_irqs,
-        .main_clk       = "gpt6_fck",
+        .sdma_reqs      = omap2_mcbsp2_sdma_reqs,
+        .main_clk       = "mcbsp2_fck",
        .prcm           = {
                .omap2 = {
                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_GPT6_SHIFT,
+                        .module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
                        .module_offs = CORE_MOD,
                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
+                        .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
                },
        },
-        .dev_attr       = &capability_alwon_dev_attr,
-        .slaves         = omap2420_timer6_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_timer6_slaves),
-        .class          = &omap2xxx_timer_hwmod_class,
 };
-/* timer7 */
+static struct omap_hwmod_class_sysconfig omap2420_msdi_sysc = {
-static struct omap_hwmod omap2420_timer7_hwmod;
+        .rev_offs       = 0x3c,
+        .sysc_offs      = 0x64,
-/* l4_core -> timer7 */
+        .syss_offs      = 0x68,
-static struct omap_hwmod_ocp_if omap2420_l4_core__timer7 = {
+        .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
-        .master         = &omap2420_l4_core_hwmod,
+        .sysc_fields    = &omap_hwmod_sysc_type1,
-        .slave          = &omap2420_timer7_hwmod,
-        .clk            = "gpt7_ick",
-        .addr           = omap2xxx_timer7_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* timer7 slave port */
-static struct omap_hwmod_ocp_if *omap2420_timer7_slaves[] = {
-        &omap2420_l4_core__timer7,
 };
-/* timer7 hwmod */
+static struct omap_hwmod_class omap2420_msdi_hwmod_class = {
-static struct omap_hwmod omap2420_timer7_hwmod = {
+        .name   = "msdi",
-        .name           = "timer7",
+        .sysc   = &omap2420_msdi_sysc,
-        .mpu_irqs       = omap2_timer7_mpu_irqs,
+        .reset  = &omap_msdi_reset,
-        .main_clk       = "gpt7_fck",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_GPT7_SHIFT,
-                        .module_offs = CORE_MOD,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
-                },
-        },
-        .dev_attr       = &capability_alwon_dev_attr,
-        .slaves         = omap2420_timer7_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_timer7_slaves),
-        .class          = &omap2xxx_timer_hwmod_class,
 };
-/* timer8 */
+/* msdi1 */
-static struct omap_hwmod omap2420_timer8_hwmod;
+static struct omap_hwmod_irq_info omap2420_msdi1_irqs[] = {
+        { .irq = 83 },
-/* l4_core -> timer8 */
+        { .irq = -1 }
-static struct omap_hwmod_ocp_if omap2420_l4_core__timer8 = {
-        .master         = &omap2420_l4_core_hwmod,
-        .slave          = &omap2420_timer8_hwmod,
-        .clk            = "gpt8_ick",
-        .addr           = omap2xxx_timer8_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-/* timer8 slave port */
+static struct omap_hwmod_dma_info omap2420_msdi1_sdma_reqs[] = {
-static struct omap_hwmod_ocp_if *omap2420_timer8_slaves[] = {
+        { .name = "tx", .dma_req = 61 }, /* OMAP24XX_DMA_MMC1_TX */
-        &omap2420_l4_core__timer8,
+        { .name = "rx", .dma_req = 62 }, /* OMAP24XX_DMA_MMC1_RX */
+        { .dma_req = -1 }
 };
-/* timer8 hwmod */
+static struct omap_hwmod omap2420_msdi1_hwmod = {
-static struct omap_hwmod omap2420_timer8_hwmod = {
+        .name           = "msdi1",
-        .name           = "timer8",
+        .class          = &omap2420_msdi_hwmod_class,
-        .mpu_irqs       = omap2_timer8_mpu_irqs,
+        .mpu_irqs       = omap2420_msdi1_irqs,
-        .main_clk       = "gpt8_fck",
+        .sdma_reqs      = omap2420_msdi1_sdma_reqs,
+        .main_clk       = "mmc_fck",
        .prcm           = {
                .omap2 = {
                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_GPT8_SHIFT,
+                        .module_bit = OMAP2420_EN_MMC_SHIFT,
                        .module_offs = CORE_MOD,
                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
+                        .idlest_idle_bit = OMAP2420_ST_MMC_SHIFT,
                },
        },
-        .dev_attr       = &capability_alwon_dev_attr,
+        .flags          = HWMOD_16BIT_REG,
-        .slaves         = omap2420_timer8_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_timer8_slaves),
-        .class          = &omap2xxx_timer_hwmod_class,
-};
-/* timer9 */
-static struct omap_hwmod omap2420_timer9_hwmod;
-/* l4_core -> timer9 */
-static struct omap_hwmod_ocp_if omap2420_l4_core__timer9 = {
-        .master         = &omap2420_l4_core_hwmod,
-        .slave          = &omap2420_timer9_hwmod,
-        .clk            = "gpt9_ick",
-        .addr           = omap2xxx_timer9_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* timer9 slave port */
-static struct omap_hwmod_ocp_if *omap2420_timer9_slaves[] = {
-        &omap2420_l4_core__timer9,
 };
-/* timer9 hwmod */
+/* HDQ1W/1-wire */
-static struct omap_hwmod omap2420_timer9_hwmod = {
+static struct omap_hwmod omap2420_hdq1w_hwmod = {
-        .name           = "timer9",
+        .name           = "hdq1w",
-        .mpu_irqs       = omap2_timer9_mpu_irqs,
+        .mpu_irqs       = omap2_hdq1w_mpu_irqs,
-        .main_clk       = "gpt9_fck",
+        .main_clk       = "hdq_fck",
        .prcm           = {
                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_GPT9_SHIFT,
                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_HDQ_SHIFT,
                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
+                        .idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,
                },
        },
-        .dev_attr       = &capability_pwm_dev_attr,
+        .class          = &omap2_hdq1w_class,
-        .slaves         = omap2420_timer9_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_timer9_slaves),
-        .class          = &omap2xxx_timer_hwmod_class,
 };
-/* timer10 */
+/*
-static struct omap_hwmod omap2420_timer10_hwmod;
+ * interfaces
+ */
-/* l4_core -> timer10 */
+/* L4 CORE -> I2C1 interface */
-static struct omap_hwmod_ocp_if omap2420_l4_core__timer10 = {
+static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
-        .master         = &omap2420_l4_core_hwmod,
+        .master         = &omap2xxx_l4_core_hwmod,
-        .slave          = &omap2420_timer10_hwmod,
+        .slave          = &omap2420_i2c1_hwmod,
-        .clk            = "gpt10_ick",
+        .clk            = "i2c1_ick",
-        .addr           = omap2_timer10_addrs,
+        .addr           = omap2_i2c1_addr_space,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-/* timer10 slave port */
+/* L4 CORE -> I2C2 interface */
-static struct omap_hwmod_ocp_if *omap2420_timer10_slaves[] = {
+static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
-        &omap2420_l4_core__timer10,
+        .master         = &omap2xxx_l4_core_hwmod,
-};
+        .slave          = &omap2420_i2c2_hwmod,
+        .clk            = "i2c2_ick",
-/* timer10 hwmod */
+        .addr           = omap2_i2c2_addr_space,
-static struct omap_hwmod omap2420_timer10_hwmod = {
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-        .name           = "timer10",
-        .mpu_irqs       = omap2_timer10_mpu_irqs,
-        .main_clk       = "gpt10_fck",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_GPT10_SHIFT,
-                        .module_offs = CORE_MOD,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
-                },
-        },
-        .dev_attr       = &capability_pwm_dev_attr,
-        .slaves         = omap2420_timer10_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_timer10_slaves),
-        .class          = &omap2xxx_timer_hwmod_class,
 };
-/* timer11 */
+/* IVA <- L3 interface */
-static struct omap_hwmod omap2420_timer11_hwmod;
+static struct omap_hwmod_ocp_if omap2420_l3__iva = {
+        .master         = &omap2xxx_l3_main_hwmod,
-/* l4_core -> timer11 */
+        .slave          = &omap2420_iva_hwmod,
-static struct omap_hwmod_ocp_if omap2420_l4_core__timer11 = {
+        .clk            = "core_l3_ck",
-        .master         = &omap2420_l4_core_hwmod,
-        .slave          = &omap2420_timer11_hwmod,
-        .clk            = "gpt11_ick",
-        .addr           = omap2_timer11_addrs,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-/* timer11 slave port */
+/* DSP <- L3 interface */
-static struct omap_hwmod_ocp_if *omap2420_timer11_slaves[] = {
+static struct omap_hwmod_ocp_if omap2420_l3__dsp = {
-        &omap2420_l4_core__timer11,
+        .master         = &omap2xxx_l3_main_hwmod,
+        .slave          = &omap2420_dsp_hwmod,
+        .clk            = "dsp_ick",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-/* timer11 hwmod */
+static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = {
-static struct omap_hwmod omap2420_timer11_hwmod = {
+        {
-        .name           = "timer11",
+                .pa_start       = 0x48028000,
-        .mpu_irqs       = omap2_timer11_mpu_irqs,
+                .pa_end         = 0x48028000 + SZ_1K - 1,
-        .main_clk       = "gpt11_fck",
+                .flags          = ADDR_TYPE_RT
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_GPT11_SHIFT,
-                        .module_offs = CORE_MOD,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
-                },
        },
-        .dev_attr       = &capability_pwm_dev_attr,
+        { }
-        .slaves         = omap2420_timer11_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_timer11_slaves),
-        .class          = &omap2xxx_timer_hwmod_class,
 };
-/* timer12 */
+/* l4_wkup -> timer1 */
-static struct omap_hwmod omap2420_timer12_hwmod;
+static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
+        .master         = &omap2xxx_l4_wkup_hwmod,
-/* l4_core -> timer12 */
+        .slave          = &omap2xxx_timer1_hwmod,
-static struct omap_hwmod_ocp_if omap2420_l4_core__timer12 = {
+        .clk            = "gpt1_ick",
-        .master         = &omap2420_l4_core_hwmod,
+        .addr           = omap2420_timer1_addrs,
-        .slave          = &omap2420_timer12_hwmod,
-        .clk            = "gpt12_ick",
-        .addr           = omap2xxx_timer12_addrs,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-/* timer12 slave port */
-static struct omap_hwmod_ocp_if *omap2420_timer12_slaves[] = {
-        &omap2420_l4_core__timer12,
-};
-/* timer12 hwmod */
-static struct omap_hwmod omap2420_timer12_hwmod = {
-        .name           = "timer12",
-        .mpu_irqs       = omap2xxx_timer12_mpu_irqs,
-        .main_clk       = "gpt12_fck",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_GPT12_SHIFT,
-                        .module_offs = CORE_MOD,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
-                },
-        },
-        .dev_attr       = &capability_pwm_dev_attr,
-        .slaves         = omap2420_timer12_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_timer12_slaves),
-        .class          = &omap2xxx_timer_hwmod_class,
-};
 /* l4_wkup -> wd_timer2 */
 static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = {
        {
@@ -744,364 +368,13 @@ static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = {
 };
 static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
-        .master         = &omap2420_l4_wkup_hwmod,
+        .master         = &omap2xxx_l4_wkup_hwmod,
-        .slave          = &omap2420_wd_timer2_hwmod,
+        .slave          = &omap2xxx_wd_timer2_hwmod,
        .clk            = "mpu_wdt_ick",
        .addr           = omap2420_wd_timer2_addrs,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-/* wd_timer2 */
-static struct omap_hwmod_ocp_if *omap2420_wd_timer2_slaves[] = {
-        &omap2420_l4_wkup__wd_timer2,
-};
-static struct omap_hwmod omap2420_wd_timer2_hwmod = {
-        .name           = "wd_timer2",
-        .class          = &omap2xxx_wd_timer_hwmod_class,
-        .main_clk       = "mpu_wdt_fck",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
-                        .module_offs = WKUP_MOD,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
-                },
-        },
-        .slaves         = omap2420_wd_timer2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_wd_timer2_slaves),
-};
-/* UART1 */
-static struct omap_hwmod_ocp_if *omap2420_uart1_slaves[] = {
-        &omap2_l4_core__uart1,
-};
-static struct omap_hwmod omap2420_uart1_hwmod = {
-        .name           = "uart1",
-        .mpu_irqs       = omap2_uart1_mpu_irqs,
-        .sdma_reqs      = omap2_uart1_sdma_reqs,
-        .main_clk       = "uart1_fck",
-        .prcm           = {
-                .omap2 = {
-                        .module_offs = CORE_MOD,
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_UART1_SHIFT,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
-                },
-        },
-        .slaves         = omap2420_uart1_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_uart1_slaves),
-        .class          = &omap2_uart_class,
-};
-/* UART2 */
-static struct omap_hwmod_ocp_if *omap2420_uart2_slaves[] = {
-        &omap2_l4_core__uart2,
-};
-static struct omap_hwmod omap2420_uart2_hwmod = {
-        .name           = "uart2",
-        .mpu_irqs       = omap2_uart2_mpu_irqs,
-        .sdma_reqs      = omap2_uart2_sdma_reqs,
-        .main_clk       = "uart2_fck",
-        .prcm           = {
-                .omap2 = {
-                        .module_offs = CORE_MOD,
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_UART2_SHIFT,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
-                },
-        },
-        .slaves         = omap2420_uart2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_uart2_slaves),
-        .class          = &omap2_uart_class,
-};
-/* UART3 */
-static struct omap_hwmod_ocp_if *omap2420_uart3_slaves[] = {
-        &omap2_l4_core__uart3,
-};
-static struct omap_hwmod omap2420_uart3_hwmod = {
-        .name           = "uart3",
-        .mpu_irqs       = omap2_uart3_mpu_irqs,
-        .sdma_reqs      = omap2_uart3_sdma_reqs,
-        .main_clk       = "uart3_fck",
-        .prcm           = {
-                .omap2 = {
-                        .module_offs = CORE_MOD,
-                        .prcm_reg_id = 2,
-                        .module_bit = OMAP24XX_EN_UART3_SHIFT,
-                        .idlest_reg_id = 2,
-                        .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
-                },
-        },
-        .slaves         = omap2420_uart3_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_uart3_slaves),
-        .class          = &omap2_uart_class,
-};
-/* dss */
-/* dss master ports */
-static struct omap_hwmod_ocp_if *omap2420_dss_masters[] = {
-        &omap2420_dss__l3,
-};
-/* l4_core -> dss */
-static struct omap_hwmod_ocp_if omap2420_l4_core__dss = {
-        .master         = &omap2420_l4_core_hwmod,
-        .slave          = &omap2420_dss_core_hwmod,
-        .clk            = "dss_ick",
-        .addr           = omap2_dss_addrs,
-        .fw = {
-                .omap2 = {
-                        .l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
-                        .flags  = OMAP_FIREWALL_L4,
-                }
-        },
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* dss slave ports */
-static struct omap_hwmod_ocp_if *omap2420_dss_slaves[] = {
-        &omap2420_l4_core__dss,
-};
-static struct omap_hwmod_opt_clk dss_opt_clks[] = {
-        /*
-         * The DSS HW needs all DSS clocks enabled during reset. The dss_core
-         * driver does not use these clocks.
-         */
-        { .role = "tv_clk", .clk = "dss_54m_fck" },
-        { .role = "sys_clk", .clk = "dss2_fck" },
-};
-static struct omap_hwmod omap2420_dss_core_hwmod = {
-        .name           = "dss_core",
-        .class          = &omap2_dss_hwmod_class,
-        .main_clk       = "dss1_fck", /* instead of dss_fck */
-        .sdma_reqs      = omap2xxx_dss_sdma_chs,
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_DSS1_SHIFT,
-                        .module_offs = CORE_MOD,
-                        .idlest_reg_id = 1,
-                        .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
-                },
-        },
-        .opt_clks       = dss_opt_clks,
-        .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
-        .slaves         = omap2420_dss_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_dss_slaves),
-        .masters        = omap2420_dss_masters,
-        .masters_cnt    = ARRAY_SIZE(omap2420_dss_masters),
-        .flags          = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-};
-/* l4_core -> dss_dispc */
-static struct omap_hwmod_ocp_if omap2420_l4_core__dss_dispc = {
-        .master         = &omap2420_l4_core_hwmod,
-        .slave          = &omap2420_dss_dispc_hwmod,
-        .clk            = "dss_ick",
-        .addr           = omap2_dss_dispc_addrs,
-        .fw = {
-                .omap2 = {
-                        .l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION,
-                        .flags  = OMAP_FIREWALL_L4,
-                }
-        },
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* dss_dispc slave ports */
-static struct omap_hwmod_ocp_if *omap2420_dss_dispc_slaves[] = {
-        &omap2420_l4_core__dss_dispc,
-};
-static struct omap_hwmod omap2420_dss_dispc_hwmod = {
-        .name           = "dss_dispc",
-        .class          = &omap2_dispc_hwmod_class,
-        .mpu_irqs       = omap2_dispc_irqs,
-        .main_clk       = "dss1_fck",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_DSS1_SHIFT,
-                        .module_offs = CORE_MOD,
-                        .idlest_reg_id = 1,
-                        .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
-                },
-        },
-        .slaves         = omap2420_dss_dispc_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_dss_dispc_slaves),
-        .flags          = HWMOD_NO_IDLEST,
-        .dev_attr       = &omap2_3_dss_dispc_dev_attr
-};
-/* l4_core -> dss_rfbi */
-static struct omap_hwmod_ocp_if omap2420_l4_core__dss_rfbi = {
-        .master         = &omap2420_l4_core_hwmod,
-        .slave          = &omap2420_dss_rfbi_hwmod,
-        .clk            = "dss_ick",
-        .addr           = omap2_dss_rfbi_addrs,
-        .fw = {
-                .omap2 = {
-                        .l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
-                        .flags  = OMAP_FIREWALL_L4,
-                }
-        },
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* dss_rfbi slave ports */
-static struct omap_hwmod_ocp_if *omap2420_dss_rfbi_slaves[] = {
-        &omap2420_l4_core__dss_rfbi,
-};
-static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
-        { .role = "ick", .clk = "dss_ick" },
-};
-static struct omap_hwmod omap2420_dss_rfbi_hwmod = {
-        .name           = "dss_rfbi",
-        .class          = &omap2_rfbi_hwmod_class,
-        .main_clk       = "dss1_fck",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_DSS1_SHIFT,
-                        .module_offs = CORE_MOD,
-                },
-        },
-        .opt_clks       = dss_rfbi_opt_clks,
-        .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
-        .slaves         = omap2420_dss_rfbi_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_dss_rfbi_slaves),
-        .flags          = HWMOD_NO_IDLEST,
-};
-/* l4_core -> dss_venc */
-static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = {
-        .master         = &omap2420_l4_core_hwmod,
-        .slave          = &omap2420_dss_venc_hwmod,
-        .clk            = "dss_ick",
-        .addr           = omap2_dss_venc_addrs,
-        .fw = {
-                .omap2 = {
-                        .l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_VENC_REGION,
-                        .flags  = OMAP_FIREWALL_L4,
-                }
-        },
-        .flags          = OCPIF_SWSUP_IDLE,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* dss_venc slave ports */
-static struct omap_hwmod_ocp_if *omap2420_dss_venc_slaves[] = {
-        &omap2420_l4_core__dss_venc,
-};
-static struct omap_hwmod omap2420_dss_venc_hwmod = {
-        .name           = "dss_venc",
-        .class          = &omap2_venc_hwmod_class,
-        .main_clk       = "dss_54m_fck",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_DSS1_SHIFT,
-                        .module_offs = CORE_MOD,
-                },
-        },
-        .slaves         = omap2420_dss_venc_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_dss_venc_slaves),
-        .flags          = HWMOD_NO_IDLEST,
-};
-/* I2C common */
-static struct omap_hwmod_class_sysconfig i2c_sysc = {
-        .rev_offs       = 0x00,
-        .sysc_offs      = 0x20,
-        .syss_offs      = 0x10,
-        .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
-        .sysc_fields    = &omap_hwmod_sysc_type1,
-};
-static struct omap_hwmod_class i2c_class = {
-        .name           = "i2c",
-        .sysc           = &i2c_sysc,
-        .rev            = OMAP_I2C_IP_VERSION_1,
-        .reset          = &omap_i2c_reset,
-};
-static struct omap_i2c_dev_attr i2c_dev_attr = {
-        .flags          = OMAP_I2C_FLAG_NO_FIFO |
-                          OMAP_I2C_FLAG_SIMPLE_CLOCK |
-                          OMAP_I2C_FLAG_16BIT_DATA_REG |
-                          OMAP_I2C_FLAG_BUS_SHIFT_2,
-};
-/* I2C1 */
-static struct omap_hwmod_ocp_if *omap2420_i2c1_slaves[] = {
-        &omap2420_l4_core__i2c1,
-};
-static struct omap_hwmod omap2420_i2c1_hwmod = {
-        .name           = "i2c1",
-        .mpu_irqs       = omap2_i2c1_mpu_irqs,
-        .sdma_reqs      = omap2_i2c1_sdma_reqs,
-        .main_clk       = "i2c1_fck",
-        .prcm           = {
-                .omap2 = {
-                        .module_offs = CORE_MOD,
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP2420_EN_I2C1_SHIFT,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,
-                },
-        },
-        .slaves         = omap2420_i2c1_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_i2c1_slaves),
-        .class          = &i2c_class,
-        .dev_attr       = &i2c_dev_attr,
-        .flags          = HWMOD_16BIT_REG,
-};
-/* I2C2 */
-static struct omap_hwmod_ocp_if *omap2420_i2c2_slaves[] = {
-        &omap2420_l4_core__i2c2,
-};
-static struct omap_hwmod omap2420_i2c2_hwmod = {
-        .name           = "i2c2",
-        .mpu_irqs       = omap2_i2c2_mpu_irqs,
-        .sdma_reqs      = omap2_i2c2_sdma_reqs,
-        .main_clk       = "i2c2_fck",
-        .prcm           = {
-                .omap2 = {
-                        .module_offs = CORE_MOD,
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP2420_EN_I2C2_SHIFT,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,
-                },
-        },
-        .slaves         = omap2420_i2c2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_i2c2_slaves),
-        .class          = &i2c_class,
-        .dev_attr       = &i2c_dev_attr,
-        .flags          = HWMOD_16BIT_REG,
-};
 /* l4_wkup -> gpio1 */
 static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = {
        {
@@ -1113,8 +386,8 @@ static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = {
 };
 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
-        .master         = &omap2420_l4_wkup_hwmod,
+        .master         = &omap2xxx_l4_wkup_hwmod,
-        .slave          = &omap2420_gpio1_hwmod,
+        .slave          = &omap2xxx_gpio1_hwmod,
        .clk            = "gpios_ick",
        .addr           = omap2420_gpio1_addr_space,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
@@ -1131,8 +404,8 @@ static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = {
 };
 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
-        .master         = &omap2420_l4_wkup_hwmod,
+        .master         = &omap2xxx_l4_wkup_hwmod,
-        .slave          = &omap2420_gpio2_hwmod,
+        .slave          = &omap2xxx_gpio2_hwmod,
        .clk            = "gpios_ick",
        .addr           = omap2420_gpio2_addr_space,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
@@ -1149,8 +422,8 @@ static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = {
 };
 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
-        .master         = &omap2420_l4_wkup_hwmod,
+        .master         = &omap2xxx_l4_wkup_hwmod,
-        .slave          = &omap2420_gpio3_hwmod,
+        .slave          = &omap2xxx_gpio3_hwmod,
        .clk            = "gpios_ick",
        .addr           = omap2420_gpio3_addr_space,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
@@ -1167,408 +440,150 @@ static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = {
 };
 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
-        .master         = &omap2420_l4_wkup_hwmod,
+        .master         = &omap2xxx_l4_wkup_hwmod,
-        .slave          = &omap2420_gpio4_hwmod,
+        .slave          = &omap2xxx_gpio4_hwmod,
        .clk            = "gpios_ick",
        .addr           = omap2420_gpio4_addr_space,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-/* gpio dev_attr */
-static struct omap_gpio_dev_attr gpio_dev_attr = {
-        .bank_width = 32,
-        .dbck_flag = false,
-};
-/* gpio1 */
-static struct omap_hwmod_ocp_if *omap2420_gpio1_slaves[] = {
-        &omap2420_l4_wkup__gpio1,
-};
-static struct omap_hwmod omap2420_gpio1_hwmod = {
-        .name           = "gpio1",
-        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .mpu_irqs       = omap2_gpio1_irqs,
-        .main_clk       = "gpios_fck",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
-                        .module_offs = WKUP_MOD,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
-                },
-        },
-        .slaves         = omap2420_gpio1_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_gpio1_slaves),
-        .class          = &omap2xxx_gpio_hwmod_class,
-        .dev_attr       = &gpio_dev_attr,
-};
-/* gpio2 */
-static struct omap_hwmod_ocp_if *omap2420_gpio2_slaves[] = {
-        &omap2420_l4_wkup__gpio2,
-};
-static struct omap_hwmod omap2420_gpio2_hwmod = {
-        .name           = "gpio2",
-        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .mpu_irqs       = omap2_gpio2_irqs,
-        .main_clk       = "gpios_fck",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
-                        .module_offs = WKUP_MOD,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
-                },
-        },
-        .slaves         = omap2420_gpio2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_gpio2_slaves),
-        .class          = &omap2xxx_gpio_hwmod_class,
-        .dev_attr       = &gpio_dev_attr,
-};
-/* gpio3 */
-static struct omap_hwmod_ocp_if *omap2420_gpio3_slaves[] = {
-        &omap2420_l4_wkup__gpio3,
-};
-static struct omap_hwmod omap2420_gpio3_hwmod = {
-        .name           = "gpio3",
-        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .mpu_irqs       = omap2_gpio3_irqs,
-        .main_clk       = "gpios_fck",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
-                        .module_offs = WKUP_MOD,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
-                },
-        },
-        .slaves         = omap2420_gpio3_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_gpio3_slaves),
-        .class          = &omap2xxx_gpio_hwmod_class,
-        .dev_attr       = &gpio_dev_attr,
-};
-/* gpio4 */
-static struct omap_hwmod_ocp_if *omap2420_gpio4_slaves[] = {
-        &omap2420_l4_wkup__gpio4,
-};
-static struct omap_hwmod omap2420_gpio4_hwmod = {
-        .name           = "gpio4",
-        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .mpu_irqs       = omap2_gpio4_irqs,
-        .main_clk       = "gpios_fck",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
-                        .module_offs = WKUP_MOD,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
-                },
-        },
-        .slaves         = omap2420_gpio4_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_gpio4_slaves),
-        .class          = &omap2xxx_gpio_hwmod_class,
-        .dev_attr       = &gpio_dev_attr,
-};
-/* dma attributes */
-static struct omap_dma_dev_attr dma_dev_attr = {
-        .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
-                                                IS_CSSA_32 | IS_CDSA_32,
-        .lch_count = 32,
-};
 /* dma_system -> L3 */
 static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = {
        .master         = &omap2420_dma_system_hwmod,
-        .slave          = &omap2420_l3_main_hwmod,
+        .slave          = &omap2xxx_l3_main_hwmod,
        .clk            = "core_l3_ck",
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-/* dma_system master ports */
-static struct omap_hwmod_ocp_if *omap2420_dma_system_masters[] = {
-        &omap2420_dma_system__l3,
-};
 /* l4_core -> dma_system */
 static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
-        .master         = &omap2420_l4_core_hwmod,
+        .master         = &omap2xxx_l4_core_hwmod,
        .slave          = &omap2420_dma_system_hwmod,
        .clk            = "sdma_ick",
        .addr           = omap2_dma_system_addrs,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-/* dma_system slave ports */
-static struct omap_hwmod_ocp_if *omap2420_dma_system_slaves[] = {
-        &omap2420_l4_core__dma_system,
-};
-static struct omap_hwmod omap2420_dma_system_hwmod = {
-        .name           = "dma",
-        .class          = &omap2xxx_dma_hwmod_class,
-        .mpu_irqs       = omap2_dma_system_irqs,
-        .main_clk       = "core_l3_ck",
-        .slaves         = omap2420_dma_system_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_dma_system_slaves),
-        .masters        = omap2420_dma_system_masters,
-        .masters_cnt    = ARRAY_SIZE(omap2420_dma_system_masters),
-        .dev_attr       = &dma_dev_attr,
-        .flags          = HWMOD_NO_IDLEST,
-};
-/* mailbox */
-static struct omap_hwmod omap2420_mailbox_hwmod;
-static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
-        { .name = "dsp", .irq = 26 },
-        { .name = "iva", .irq = 34 },
-        { .irq = -1 }
-};
 /* l4_core -> mailbox */
 static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
-        .master         = &omap2420_l4_core_hwmod,
+        .master         = &omap2xxx_l4_core_hwmod,
        .slave          = &omap2420_mailbox_hwmod,
        .addr           = omap2_mailbox_addrs,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-/* mailbox slave ports */
-static struct omap_hwmod_ocp_if *omap2420_mailbox_slaves[] = {
-        &omap2420_l4_core__mailbox,
-};
-static struct omap_hwmod omap2420_mailbox_hwmod = {
-        .name           = "mailbox",
-        .class          = &omap2xxx_mailbox_hwmod_class,
-        .mpu_irqs       = omap2420_mailbox_irqs,
-        .main_clk       = "mailboxes_ick",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
-                        .module_offs = CORE_MOD,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
-                },
-        },
-        .slaves         = omap2420_mailbox_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_mailbox_slaves),
-};
-/* mcspi1 */
-static struct omap_hwmod_ocp_if *omap2420_mcspi1_slaves[] = {
-        &omap2420_l4_core__mcspi1,
-};
-static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
-        .num_chipselect = 4,
-};
-static struct omap_hwmod omap2420_mcspi1_hwmod = {
-        .name           = "mcspi1_hwmod",
-        .mpu_irqs       = omap2_mcspi1_mpu_irqs,
-        .sdma_reqs      = omap2_mcspi1_sdma_reqs,
-        .main_clk       = "mcspi1_fck",
-        .prcm           = {
-                .omap2 = {
-                        .module_offs = CORE_MOD,
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
-                },
-        },
-        .slaves         = omap2420_mcspi1_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_mcspi1_slaves),
-        .class          = &omap2xxx_mcspi_class,
-        .dev_attr       = &omap_mcspi1_dev_attr,
-};
-/* mcspi2 */
-static struct omap_hwmod_ocp_if *omap2420_mcspi2_slaves[] = {
-        &omap2420_l4_core__mcspi2,
-};
-static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
-        .num_chipselect = 2,
-};
-static struct omap_hwmod omap2420_mcspi2_hwmod = {
-        .name           = "mcspi2_hwmod",
-        .mpu_irqs       = omap2_mcspi2_mpu_irqs,
-        .sdma_reqs      = omap2_mcspi2_sdma_reqs,
-        .main_clk       = "mcspi2_fck",
-        .prcm           = {
-                .omap2 = {
-                        .module_offs = CORE_MOD,
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
-                },
-        },
-        .slaves         = omap2420_mcspi2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_mcspi2_slaves),
-        .class          = &omap2xxx_mcspi_class,
-        .dev_attr       = &omap_mcspi2_dev_attr,
-};
-/*
- * 'mcbsp' class
- * multi channel buffered serial port controller
- */
-static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
-        .name = "mcbsp",
-};
-/* mcbsp1 */
-static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = {
-        { .name = "tx", .irq = 59 },
-        { .name = "rx", .irq = 60 },
-        { .irq = -1 }
-};
 /* l4_core -> mcbsp1 */
 static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
-        .master         = &omap2420_l4_core_hwmod,
+        .master         = &omap2xxx_l4_core_hwmod,
        .slave          = &omap2420_mcbsp1_hwmod,
        .clk            = "mcbsp1_ick",
        .addr           = omap2_mcbsp1_addrs,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-/* mcbsp1 slave ports */
-static struct omap_hwmod_ocp_if *omap2420_mcbsp1_slaves[] = {
-        &omap2420_l4_core__mcbsp1,
-};
-static struct omap_hwmod omap2420_mcbsp1_hwmod = {
-        .name           = "mcbsp1",
-        .class          = &omap2420_mcbsp_hwmod_class,
-        .mpu_irqs       = omap2420_mcbsp1_irqs,
-        .sdma_reqs      = omap2_mcbsp1_sdma_reqs,
-        .main_clk       = "mcbsp1_fck",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
-                        .module_offs = CORE_MOD,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
-                },
-        },
-        .slaves         = omap2420_mcbsp1_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2420_mcbsp1_slaves),
-};
-/* mcbsp2 */
-static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = {
-        { .name = "tx", .irq = 62 },
-        { .name = "rx", .irq = 63 },
-        { .irq = -1 }
-};
 /* l4_core -> mcbsp2 */
 static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
-        .master         = &omap2420_l4_core_hwmod,
+        .master         = &omap2xxx_l4_core_hwmod,
        .slave          = &omap2420_mcbsp2_hwmod,
        .clk            = "mcbsp2_ick",
        .addr           = omap2xxx_mcbsp2_addrs,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-/* mcbsp2 slave ports */
+static struct omap_hwmod_addr_space omap2420_msdi1_addrs[] = {
-static struct omap_hwmod_ocp_if *omap2420_mcbsp2_slaves[] = {
+        {
-        &omap2420_l4_core__mcbsp2,
+                .pa_start       = 0x4809c000,
-};
+                .pa_end         = 0x4809c000 + SZ_128 - 1,
+                .flags          = ADDR_TYPE_RT,
-static struct omap_hwmod omap2420_mcbsp2_hwmod = {
-        .name           = "mcbsp2",
-        .class          = &omap2420_mcbsp_hwmod_class,
-        .mpu_irqs       = omap2420_mcbsp2_irqs,
-        .sdma_reqs      = omap2_mcbsp2_sdma_reqs,
-        .main_clk       = "mcbsp2_fck",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
-                        .module_offs = CORE_MOD,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
-                },
        },
-        .slaves         = omap2420_mcbsp2_slaves,
+        { }
-        .slaves_cnt     = ARRAY_SIZE(omap2420_mcbsp2_slaves),
 };
-static __initdata struct omap_hwmod *omap2420_hwmods[] = {
+/* l4_core -> msdi1 */
-        &omap2420_l3_main_hwmod,
+static struct omap_hwmod_ocp_if omap2420_l4_core__msdi1 = {
-        &omap2420_l4_core_hwmod,
+        .master         = &omap2xxx_l4_core_hwmod,
-        &omap2420_l4_wkup_hwmod,
+        .slave          = &omap2420_msdi1_hwmod,
-        &omap2420_mpu_hwmod,
+        .clk            = "mmc_ick",
-        &omap2420_iva_hwmod,
+        .addr           = omap2420_msdi1_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-        &omap2420_timer1_hwmod,
+};
-        &omap2420_timer2_hwmod,
-        &omap2420_timer3_hwmod,
-        &omap2420_timer4_hwmod,
-        &omap2420_timer5_hwmod,
-        &omap2420_timer6_hwmod,
-        &omap2420_timer7_hwmod,
-        &omap2420_timer8_hwmod,
-        &omap2420_timer9_hwmod,
-        &omap2420_timer10_hwmod,
-        &omap2420_timer11_hwmod,
-        &omap2420_timer12_hwmod,
-        &omap2420_wd_timer2_hwmod,
-        &omap2420_uart1_hwmod,
-        &omap2420_uart2_hwmod,
-        &omap2420_uart3_hwmod,
-        /* dss class */
-        &omap2420_dss_core_hwmod,
-        &omap2420_dss_dispc_hwmod,
-        &omap2420_dss_rfbi_hwmod,
-        &omap2420_dss_venc_hwmod,
-        /* i2c class */
-        &omap2420_i2c1_hwmod,
-        &omap2420_i2c2_hwmod,
-        /* gpio class */
+/* l4_core -> hdq1w interface */
-        &omap2420_gpio1_hwmod,
+static struct omap_hwmod_ocp_if omap2420_l4_core__hdq1w = {
-        &omap2420_gpio2_hwmod,
+        .master         = &omap2xxx_l4_core_hwmod,
-        &omap2420_gpio3_hwmod,
+        .slave          = &omap2420_hdq1w_hwmod,
-        &omap2420_gpio4_hwmod,
+        .clk            = "hdq_ick",
+        .addr           = omap2_hdq1w_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+        .flags          = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
+};
-        /* dma_system class*/
-        &omap2420_dma_system_hwmod,
-        /* mailbox class */
+/* l4_wkup -> 32ksync_counter */
-        &omap2420_mailbox_hwmod,
+static struct omap_hwmod_addr_space omap2420_counter_32k_addrs[] = {
+        {
+                .pa_start       = 0x48004000,
+                .pa_end         = 0x4800401f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
-        /* mcbsp class */
+static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = {
-        &omap2420_mcbsp1_hwmod,
+        .master         = &omap2xxx_l4_wkup_hwmod,
-        &omap2420_mcbsp2_hwmod,
+        .slave          = &omap2xxx_counter_32k_hwmod,
+        .clk            = "sync_32k_ick",
+        .addr           = omap2420_counter_32k_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
-        /* mcspi class */
+static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
-        &omap2420_mcspi1_hwmod,
+        &omap2xxx_l3_main__l4_core,
-        &omap2420_mcspi2_hwmod,
+        &omap2xxx_mpu__l3_main,
+        &omap2xxx_dss__l3,
+        &omap2xxx_l4_core__mcspi1,
+        &omap2xxx_l4_core__mcspi2,
+        &omap2xxx_l4_core__l4_wkup,
+        &omap2_l4_core__uart1,
+        &omap2_l4_core__uart2,
+        &omap2_l4_core__uart3,
+        &omap2420_l4_core__i2c1,
+        &omap2420_l4_core__i2c2,
+        &omap2420_l3__iva,
+        &omap2420_l3__dsp,
+        &omap2420_l4_wkup__timer1,
+        &omap2xxx_l4_core__timer2,
+        &omap2xxx_l4_core__timer3,
+        &omap2xxx_l4_core__timer4,
+        &omap2xxx_l4_core__timer5,
+        &omap2xxx_l4_core__timer6,
+        &omap2xxx_l4_core__timer7,
+        &omap2xxx_l4_core__timer8,
+        &omap2xxx_l4_core__timer9,
+        &omap2xxx_l4_core__timer10,
+        &omap2xxx_l4_core__timer11,
+        &omap2xxx_l4_core__timer12,
+        &omap2420_l4_wkup__wd_timer2,
+        &omap2xxx_l4_core__dss,
+        &omap2xxx_l4_core__dss_dispc,
+        &omap2xxx_l4_core__dss_rfbi,
+        &omap2xxx_l4_core__dss_venc,
+        &omap2420_l4_wkup__gpio1,
+        &omap2420_l4_wkup__gpio2,
+        &omap2420_l4_wkup__gpio3,
+        &omap2420_l4_wkup__gpio4,
+        &omap2420_dma_system__l3,
+        &omap2420_l4_core__dma_system,
+        &omap2420_l4_core__mailbox,
+        &omap2420_l4_core__mcbsp1,
+        &omap2420_l4_core__mcbsp2,
+        &omap2420_l4_core__msdi1,
+        &omap2420_l4_core__hdq1w,
+        &omap2420_l4_wkup__counter_32k,
        NULL,
 };
 int __init omap2420_hwmod_init(void)
 {
-        return omap_hwmod_register(omap2420_hwmods);
+        return omap_hwmod_register_links(omap2420_hwmod_ocp_ifs);
 }
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index c4f56cb60d7d..4d7264981230 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -2,6 +2,7 @@
 * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips
 *
 * Copyright (C) 2009-2011 Nokia Corporation
+ * Copyright (C) 2012 Texas Instruments, Inc.
 * Paul Walmsley
 *
 * This program is free software; you can redistribute it and/or modify
@@ -33,1045 +34,29 @@
 /*
 * OMAP2430 hardware module integration data
 *
- * ALl of the data in this section should be autogeneratable from the
+ * All of the data in this section should be autogeneratable from the
 * TI hardware database or other technical documentation.  Data that
 * is driver-specific or driver-kernel integration-specific belongs
 * elsewhere.
 */
-static struct omap_hwmod omap2430_mpu_hwmod;
-static struct omap_hwmod omap2430_iva_hwmod;
-static struct omap_hwmod omap2430_l3_main_hwmod;
-static struct omap_hwmod omap2430_l4_core_hwmod;
-static struct omap_hwmod omap2430_dss_core_hwmod;
-static struct omap_hwmod omap2430_dss_dispc_hwmod;
-static struct omap_hwmod omap2430_dss_rfbi_hwmod;
-static struct omap_hwmod omap2430_dss_venc_hwmod;
-static struct omap_hwmod omap2430_wd_timer2_hwmod;
-static struct omap_hwmod omap2430_gpio1_hwmod;
-static struct omap_hwmod omap2430_gpio2_hwmod;
-static struct omap_hwmod omap2430_gpio3_hwmod;
-static struct omap_hwmod omap2430_gpio4_hwmod;
-static struct omap_hwmod omap2430_gpio5_hwmod;
-static struct omap_hwmod omap2430_dma_system_hwmod;
-static struct omap_hwmod omap2430_mcbsp1_hwmod;
-static struct omap_hwmod omap2430_mcbsp2_hwmod;
-static struct omap_hwmod omap2430_mcbsp3_hwmod;
-static struct omap_hwmod omap2430_mcbsp4_hwmod;
-static struct omap_hwmod omap2430_mcbsp5_hwmod;
-static struct omap_hwmod omap2430_mcspi1_hwmod;
-static struct omap_hwmod omap2430_mcspi2_hwmod;
-static struct omap_hwmod omap2430_mcspi3_hwmod;
-static struct omap_hwmod omap2430_mmc1_hwmod;
-static struct omap_hwmod omap2430_mmc2_hwmod;
-/* L3 -> L4_CORE interface */
-static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = {
-        .master = &omap2430_l3_main_hwmod,
-        .slave  = &omap2430_l4_core_hwmod,
-        .user   = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* MPU -> L3 interface */
-static struct omap_hwmod_ocp_if omap2430_mpu__l3_main = {
-        .master = &omap2430_mpu_hwmod,
-        .slave  = &omap2430_l3_main_hwmod,
-        .user   = OCP_USER_MPU,
-};
-/* Slave interfaces on the L3 interconnect */
-static struct omap_hwmod_ocp_if *omap2430_l3_main_slaves[] = {
-        &omap2430_mpu__l3_main,
-};
-/* DSS -> l3 */
-static struct omap_hwmod_ocp_if omap2430_dss__l3 = {
-        .master         = &omap2430_dss_core_hwmod,
-        .slave          = &omap2430_l3_main_hwmod,
-        .fw = {
-                .omap2 = {
-                        .l3_perm_bit  = OMAP2_L3_CORE_FW_CONNID_DSS,
-                        .flags  = OMAP_FIREWALL_L3,
-                }
-        },
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* Master interfaces on the L3 interconnect */
-static struct omap_hwmod_ocp_if *omap2430_l3_main_masters[] = {
-        &omap2430_l3_main__l4_core,
-};
-/* L3 */
-static struct omap_hwmod omap2430_l3_main_hwmod = {
-        .name           = "l3_main",
-        .class          = &l3_hwmod_class,
-        .masters        = omap2430_l3_main_masters,
-        .masters_cnt    = ARRAY_SIZE(omap2430_l3_main_masters),
-        .slaves         = omap2430_l3_main_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_l3_main_slaves),
-        .flags          = HWMOD_NO_IDLEST,
-};
-static struct omap_hwmod omap2430_l4_wkup_hwmod;
-static struct omap_hwmod omap2430_uart1_hwmod;
-static struct omap_hwmod omap2430_uart2_hwmod;
-static struct omap_hwmod omap2430_uart3_hwmod;
-static struct omap_hwmod omap2430_i2c1_hwmod;
-static struct omap_hwmod omap2430_i2c2_hwmod;
-static struct omap_hwmod omap2430_usbhsotg_hwmod;
-/* l3_core -> usbhsotg  interface */
-static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = {
-        .master         = &omap2430_usbhsotg_hwmod,
-        .slave          = &omap2430_l3_main_hwmod,
-        .clk            = "core_l3_ck",
-        .user           = OCP_USER_MPU,
-};
-/* L4 CORE -> I2C1 interface */
-static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = {
-        .master         = &omap2430_l4_core_hwmod,
-        .slave          = &omap2430_i2c1_hwmod,
-        .clk            = "i2c1_ick",
-        .addr           = omap2_i2c1_addr_space,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* L4 CORE -> I2C2 interface */
-static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = {
-        .master         = &omap2430_l4_core_hwmod,
-        .slave          = &omap2430_i2c2_hwmod,
-        .clk            = "i2c2_ick",
-        .addr           = omap2_i2c2_addr_space,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* L4_CORE -> L4_WKUP interface */
-static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = {
-        .master = &omap2430_l4_core_hwmod,
-        .slave  = &omap2430_l4_wkup_hwmod,
-        .user   = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* L4 CORE -> UART1 interface */
-static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
-        .master         = &omap2430_l4_core_hwmod,
-        .slave          = &omap2430_uart1_hwmod,
-        .clk            = "uart1_ick",
-        .addr           = omap2xxx_uart1_addr_space,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* L4 CORE -> UART2 interface */
-static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
-        .master         = &omap2430_l4_core_hwmod,
-        .slave          = &omap2430_uart2_hwmod,
-        .clk            = "uart2_ick",
-        .addr           = omap2xxx_uart2_addr_space,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* L4 PER -> UART3 interface */
-static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
-        .master         = &omap2430_l4_core_hwmod,
-        .slave          = &omap2430_uart3_hwmod,
-        .clk            = "uart3_ick",
-        .addr           = omap2xxx_uart3_addr_space,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/*
-* usbhsotg interface data
-*/
-static struct omap_hwmod_addr_space omap2430_usbhsotg_addrs[] = {
-        {
-                .pa_start       = OMAP243X_HS_BASE,
-                .pa_end         = OMAP243X_HS_BASE + SZ_4K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/*  l4_core ->usbhsotg  interface */
-static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = {
-        .master         = &omap2430_l4_core_hwmod,
-        .slave          = &omap2430_usbhsotg_hwmod,
-        .clk            = "usb_l4_ick",
-        .addr           = omap2430_usbhsotg_addrs,
-        .user           = OCP_USER_MPU,
-};
-static struct omap_hwmod_ocp_if *omap2430_usbhsotg_masters[] = {
-        &omap2430_usbhsotg__l3,
-};
-static struct omap_hwmod_ocp_if *omap2430_usbhsotg_slaves[] = {
-        &omap2430_l4_core__usbhsotg,
-};
-/* L4 CORE -> MMC1 interface */
-static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = {
-        .master         = &omap2430_l4_core_hwmod,
-        .slave          = &omap2430_mmc1_hwmod,
-        .clk            = "mmchs1_ick",
-        .addr           = omap2430_mmc1_addr_space,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* L4 CORE -> MMC2 interface */
-static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = {
-        .master         = &omap2430_l4_core_hwmod,
-        .slave          = &omap2430_mmc2_hwmod,
-        .clk            = "mmchs2_ick",
-        .addr           = omap2430_mmc2_addr_space,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* Slave interfaces on the L4_CORE interconnect */
-static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = {
-        &omap2430_l3_main__l4_core,
-};
-/* Master interfaces on the L4_CORE interconnect */
-static struct omap_hwmod_ocp_if *omap2430_l4_core_masters[] = {
-        &omap2430_l4_core__l4_wkup,
-        &omap2430_l4_core__mmc1,
-        &omap2430_l4_core__mmc2,
-};
-/* L4 CORE */
-static struct omap_hwmod omap2430_l4_core_hwmod = {
-        .name           = "l4_core",
-        .class          = &l4_hwmod_class,
-        .masters        = omap2430_l4_core_masters,
-        .masters_cnt    = ARRAY_SIZE(omap2430_l4_core_masters),
-        .slaves         = omap2430_l4_core_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_l4_core_slaves),
-        .flags          = HWMOD_NO_IDLEST,
-};
-/* Slave interfaces on the L4_WKUP interconnect */
-static struct omap_hwmod_ocp_if *omap2430_l4_wkup_slaves[] = {
-        &omap2430_l4_core__l4_wkup,
-        &omap2_l4_core__uart1,
-        &omap2_l4_core__uart2,
-        &omap2_l4_core__uart3,
-};
-/* Master interfaces on the L4_WKUP interconnect */
-static struct omap_hwmod_ocp_if *omap2430_l4_wkup_masters[] = {
-};
-/* l4 core -> mcspi1 interface */
-static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi1 = {
-        .master         = &omap2430_l4_core_hwmod,
-        .slave          = &omap2430_mcspi1_hwmod,
-        .clk            = "mcspi1_ick",
-        .addr           = omap2_mcspi1_addr_space,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* l4 core -> mcspi2 interface */
-static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi2 = {
-        .master         = &omap2430_l4_core_hwmod,
-        .slave          = &omap2430_mcspi2_hwmod,
-        .clk            = "mcspi2_ick",
-        .addr           = omap2_mcspi2_addr_space,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* l4 core -> mcspi3 interface */
-static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = {
-        .master         = &omap2430_l4_core_hwmod,
-        .slave          = &omap2430_mcspi3_hwmod,
-        .clk            = "mcspi3_ick",
-        .addr           = omap2430_mcspi3_addr_space,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* L4 WKUP */
-static struct omap_hwmod omap2430_l4_wkup_hwmod = {
-        .name           = "l4_wkup",
-        .class          = &l4_hwmod_class,
-        .masters        = omap2430_l4_wkup_masters,
-        .masters_cnt    = ARRAY_SIZE(omap2430_l4_wkup_masters),
-        .slaves         = omap2430_l4_wkup_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_l4_wkup_slaves),
-        .flags          = HWMOD_NO_IDLEST,
-};
-/* Master interfaces on the MPU device */
-static struct omap_hwmod_ocp_if *omap2430_mpu_masters[] = {
-        &omap2430_mpu__l3_main,
-};
-/* MPU */
-static struct omap_hwmod omap2430_mpu_hwmod = {
-        .name           = "mpu",
-        .class          = &mpu_hwmod_class,
-        .main_clk       = "mpu_ck",
-        .masters        = omap2430_mpu_masters,
-        .masters_cnt    = ARRAY_SIZE(omap2430_mpu_masters),
-};
 /*
- * IVA2_1 interface data
+ * IP blocks
 */
-/* IVA2 <- L3 interface */
+/* IVA2 (IVA2) */
-static struct omap_hwmod_ocp_if omap2430_l3__iva = {
+static struct omap_hwmod_rst_info omap2430_iva_resets[] = {
-        .master         = &omap2430_l3_main_hwmod,
+        { .name = "logic", .rst_shift = 0 },
-        .slave          = &omap2430_iva_hwmod,
+        { .name = "mmu", .rst_shift = 1 },
-        .clk            = "dsp_fck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-static struct omap_hwmod_ocp_if *omap2430_iva_masters[] = {
-        &omap2430_l3__iva,
 };
-/*
- * IVA2 (IVA2)
- */
 static struct omap_hwmod omap2430_iva_hwmod = {
        .name           = "iva",
        .class          = &iva_hwmod_class,
-        .masters        = omap2430_iva_masters,
+        .clkdm_name     = "dsp_clkdm",
-        .masters_cnt    = ARRAY_SIZE(omap2430_iva_masters),
+        .rst_lines      = omap2430_iva_resets,
-};
+        .rst_lines_cnt  = ARRAY_SIZE(omap2430_iva_resets),
+        .main_clk       = "dsp_fck",
-/* always-on timers dev attribute */
-static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
-        .timer_capability       = OMAP_TIMER_ALWON,
-};
-/* pwm timers dev attribute */
-static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
-        .timer_capability       = OMAP_TIMER_HAS_PWM,
-};
-/* timer1 */
-static struct omap_hwmod omap2430_timer1_hwmod;
-static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = {
-        {
-                .pa_start       = 0x49018000,
-                .pa_end         = 0x49018000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_wkup -> timer1 */
-static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = {
-        .master         = &omap2430_l4_wkup_hwmod,
-        .slave          = &omap2430_timer1_hwmod,
-        .clk            = "gpt1_ick",
-        .addr           = omap2430_timer1_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* timer1 slave port */
-static struct omap_hwmod_ocp_if *omap2430_timer1_slaves[] = {
-        &omap2430_l4_wkup__timer1,
-};
-/* timer1 hwmod */
-static struct omap_hwmod omap2430_timer1_hwmod = {
-        .name           = "timer1",
-        .mpu_irqs       = omap2_timer1_mpu_irqs,
-        .main_clk       = "gpt1_fck",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_GPT1_SHIFT,
-                        .module_offs = WKUP_MOD,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
-                },
-        },
-        .dev_attr       = &capability_alwon_dev_attr,
-        .slaves         = omap2430_timer1_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_timer1_slaves),
-        .class          = &omap2xxx_timer_hwmod_class,
-};
-/* timer2 */
-static struct omap_hwmod omap2430_timer2_hwmod;
-/* l4_core -> timer2 */
-static struct omap_hwmod_ocp_if omap2430_l4_core__timer2 = {
-        .master         = &omap2430_l4_core_hwmod,
-        .slave          = &omap2430_timer2_hwmod,
-        .clk            = "gpt2_ick",
-        .addr           = omap2xxx_timer2_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* timer2 slave port */
-static struct omap_hwmod_ocp_if *omap2430_timer2_slaves[] = {
-        &omap2430_l4_core__timer2,
-};
-/* timer2 hwmod */
-static struct omap_hwmod omap2430_timer2_hwmod = {
-        .name           = "timer2",
-        .mpu_irqs       = omap2_timer2_mpu_irqs,
-        .main_clk       = "gpt2_fck",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_GPT2_SHIFT,
-                        .module_offs = CORE_MOD,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
-                },
-        },
-        .dev_attr       = &capability_alwon_dev_attr,
-        .slaves         = omap2430_timer2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_timer2_slaves),
-        .class          = &omap2xxx_timer_hwmod_class,
-};
-/* timer3 */
-static struct omap_hwmod omap2430_timer3_hwmod;
-/* l4_core -> timer3 */
-static struct omap_hwmod_ocp_if omap2430_l4_core__timer3 = {
-        .master         = &omap2430_l4_core_hwmod,
-        .slave          = &omap2430_timer3_hwmod,
-        .clk            = "gpt3_ick",
-        .addr           = omap2xxx_timer3_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* timer3 slave port */
-static struct omap_hwmod_ocp_if *omap2430_timer3_slaves[] = {
-        &omap2430_l4_core__timer3,
-};
-/* timer3 hwmod */
-static struct omap_hwmod omap2430_timer3_hwmod = {
-        .name           = "timer3",
-        .mpu_irqs       = omap2_timer3_mpu_irqs,
-        .main_clk       = "gpt3_fck",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_GPT3_SHIFT,
-                        .module_offs = CORE_MOD,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
-                },
-        },
-        .dev_attr       = &capability_alwon_dev_attr,
-        .slaves         = omap2430_timer3_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_timer3_slaves),
-        .class          = &omap2xxx_timer_hwmod_class,
-};
-/* timer4 */
-static struct omap_hwmod omap2430_timer4_hwmod;
-/* l4_core -> timer4 */
-static struct omap_hwmod_ocp_if omap2430_l4_core__timer4 = {
-        .master         = &omap2430_l4_core_hwmod,
-        .slave          = &omap2430_timer4_hwmod,
-        .clk            = "gpt4_ick",
-        .addr           = omap2xxx_timer4_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* timer4 slave port */
-static struct omap_hwmod_ocp_if *omap2430_timer4_slaves[] = {
-        &omap2430_l4_core__timer4,
-};
-/* timer4 hwmod */
-static struct omap_hwmod omap2430_timer4_hwmod = {
-        .name           = "timer4",
-        .mpu_irqs       = omap2_timer4_mpu_irqs,
-        .main_clk       = "gpt4_fck",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_GPT4_SHIFT,
-                        .module_offs = CORE_MOD,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
-                },
-        },
-        .dev_attr       = &capability_alwon_dev_attr,
-        .slaves         = omap2430_timer4_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_timer4_slaves),
-        .class          = &omap2xxx_timer_hwmod_class,
-};
-/* timer5 */
-static struct omap_hwmod omap2430_timer5_hwmod;
-/* l4_core -> timer5 */
-static struct omap_hwmod_ocp_if omap2430_l4_core__timer5 = {
-        .master         = &omap2430_l4_core_hwmod,
-        .slave          = &omap2430_timer5_hwmod,
-        .clk            = "gpt5_ick",
-        .addr           = omap2xxx_timer5_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* timer5 slave port */
-static struct omap_hwmod_ocp_if *omap2430_timer5_slaves[] = {
-        &omap2430_l4_core__timer5,
-};
-/* timer5 hwmod */
-static struct omap_hwmod omap2430_timer5_hwmod = {
-        .name           = "timer5",
-        .mpu_irqs       = omap2_timer5_mpu_irqs,
-        .main_clk       = "gpt5_fck",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_GPT5_SHIFT,
-                        .module_offs = CORE_MOD,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
-                },
-        },
-        .dev_attr       = &capability_alwon_dev_attr,
-        .slaves         = omap2430_timer5_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_timer5_slaves),
-        .class          = &omap2xxx_timer_hwmod_class,
-};
-/* timer6 */
-static struct omap_hwmod omap2430_timer6_hwmod;
-/* l4_core -> timer6 */
-static struct omap_hwmod_ocp_if omap2430_l4_core__timer6 = {
-        .master         = &omap2430_l4_core_hwmod,
-        .slave          = &omap2430_timer6_hwmod,
-        .clk            = "gpt6_ick",
-        .addr           = omap2xxx_timer6_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* timer6 slave port */
-static struct omap_hwmod_ocp_if *omap2430_timer6_slaves[] = {
-        &omap2430_l4_core__timer6,
-};
-/* timer6 hwmod */
-static struct omap_hwmod omap2430_timer6_hwmod = {
-        .name           = "timer6",
-        .mpu_irqs       = omap2_timer6_mpu_irqs,
-        .main_clk       = "gpt6_fck",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_GPT6_SHIFT,
-                        .module_offs = CORE_MOD,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
-                },
-        },
-        .dev_attr       = &capability_alwon_dev_attr,
-        .slaves         = omap2430_timer6_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_timer6_slaves),
-        .class          = &omap2xxx_timer_hwmod_class,
-};
-/* timer7 */
-static struct omap_hwmod omap2430_timer7_hwmod;
-/* l4_core -> timer7 */
-static struct omap_hwmod_ocp_if omap2430_l4_core__timer7 = {
-        .master         = &omap2430_l4_core_hwmod,
-        .slave          = &omap2430_timer7_hwmod,
-        .clk            = "gpt7_ick",
-        .addr           = omap2xxx_timer7_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* timer7 slave port */
-static struct omap_hwmod_ocp_if *omap2430_timer7_slaves[] = {
-        &omap2430_l4_core__timer7,
-};
-/* timer7 hwmod */
-static struct omap_hwmod omap2430_timer7_hwmod = {
-        .name           = "timer7",
-        .mpu_irqs       = omap2_timer7_mpu_irqs,
-        .main_clk       = "gpt7_fck",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_GPT7_SHIFT,
-                        .module_offs = CORE_MOD,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
-                },
-        },
-        .dev_attr       = &capability_alwon_dev_attr,
-        .slaves         = omap2430_timer7_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_timer7_slaves),
-        .class          = &omap2xxx_timer_hwmod_class,
-};
-/* timer8 */
-static struct omap_hwmod omap2430_timer8_hwmod;
-/* l4_core -> timer8 */
-static struct omap_hwmod_ocp_if omap2430_l4_core__timer8 = {
-        .master         = &omap2430_l4_core_hwmod,
-        .slave          = &omap2430_timer8_hwmod,
-        .clk            = "gpt8_ick",
-        .addr           = omap2xxx_timer8_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* timer8 slave port */
-static struct omap_hwmod_ocp_if *omap2430_timer8_slaves[] = {
-        &omap2430_l4_core__timer8,
-};
-/* timer8 hwmod */
-static struct omap_hwmod omap2430_timer8_hwmod = {
-        .name           = "timer8",
-        .mpu_irqs       = omap2_timer8_mpu_irqs,
-        .main_clk       = "gpt8_fck",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_GPT8_SHIFT,
-                        .module_offs = CORE_MOD,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
-                },
-        },
-        .dev_attr       = &capability_alwon_dev_attr,
-        .slaves         = omap2430_timer8_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_timer8_slaves),
-        .class          = &omap2xxx_timer_hwmod_class,
-};
-/* timer9 */
-static struct omap_hwmod omap2430_timer9_hwmod;
-/* l4_core -> timer9 */
-static struct omap_hwmod_ocp_if omap2430_l4_core__timer9 = {
-        .master         = &omap2430_l4_core_hwmod,
-        .slave          = &omap2430_timer9_hwmod,
-        .clk            = "gpt9_ick",
-        .addr           = omap2xxx_timer9_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* timer9 slave port */
-static struct omap_hwmod_ocp_if *omap2430_timer9_slaves[] = {
-        &omap2430_l4_core__timer9,
-};
-/* timer9 hwmod */
-static struct omap_hwmod omap2430_timer9_hwmod = {
-        .name           = "timer9",
-        .mpu_irqs       = omap2_timer9_mpu_irqs,
-        .main_clk       = "gpt9_fck",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_GPT9_SHIFT,
-                        .module_offs = CORE_MOD,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
-                },
-        },
-        .dev_attr       = &capability_pwm_dev_attr,
-        .slaves         = omap2430_timer9_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_timer9_slaves),
-        .class          = &omap2xxx_timer_hwmod_class,
-};
-/* timer10 */
-static struct omap_hwmod omap2430_timer10_hwmod;
-/* l4_core -> timer10 */
-static struct omap_hwmod_ocp_if omap2430_l4_core__timer10 = {
-        .master         = &omap2430_l4_core_hwmod,
-        .slave          = &omap2430_timer10_hwmod,
-        .clk            = "gpt10_ick",
-        .addr           = omap2_timer10_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* timer10 slave port */
-static struct omap_hwmod_ocp_if *omap2430_timer10_slaves[] = {
-        &omap2430_l4_core__timer10,
-};
-/* timer10 hwmod */
-static struct omap_hwmod omap2430_timer10_hwmod = {
-        .name           = "timer10",
-        .mpu_irqs       = omap2_timer10_mpu_irqs,
-        .main_clk       = "gpt10_fck",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_GPT10_SHIFT,
-                        .module_offs = CORE_MOD,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
-                },
-        },
-        .dev_attr       = &capability_pwm_dev_attr,
-        .slaves         = omap2430_timer10_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_timer10_slaves),
-        .class          = &omap2xxx_timer_hwmod_class,
-};
-/* timer11 */
-static struct omap_hwmod omap2430_timer11_hwmod;
-/* l4_core -> timer11 */
-static struct omap_hwmod_ocp_if omap2430_l4_core__timer11 = {
-        .master         = &omap2430_l4_core_hwmod,
-        .slave          = &omap2430_timer11_hwmod,
-        .clk            = "gpt11_ick",
-        .addr           = omap2_timer11_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* timer11 slave port */
-static struct omap_hwmod_ocp_if *omap2430_timer11_slaves[] = {
-        &omap2430_l4_core__timer11,
-};
-/* timer11 hwmod */
-static struct omap_hwmod omap2430_timer11_hwmod = {
-        .name           = "timer11",
-        .mpu_irqs       = omap2_timer11_mpu_irqs,
-        .main_clk       = "gpt11_fck",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_GPT11_SHIFT,
-                        .module_offs = CORE_MOD,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
-                },
-        },
-        .dev_attr       = &capability_pwm_dev_attr,
-        .slaves         = omap2430_timer11_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_timer11_slaves),
-        .class          = &omap2xxx_timer_hwmod_class,
-};
-/* timer12 */
-static struct omap_hwmod omap2430_timer12_hwmod;
-/* l4_core -> timer12 */
-static struct omap_hwmod_ocp_if omap2430_l4_core__timer12 = {
-        .master         = &omap2430_l4_core_hwmod,
-        .slave          = &omap2430_timer12_hwmod,
-        .clk            = "gpt12_ick",
-        .addr           = omap2xxx_timer12_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* timer12 slave port */
-static struct omap_hwmod_ocp_if *omap2430_timer12_slaves[] = {
-        &omap2430_l4_core__timer12,
-};
-/* timer12 hwmod */
-static struct omap_hwmod omap2430_timer12_hwmod = {
-        .name           = "timer12",
-        .mpu_irqs       = omap2xxx_timer12_mpu_irqs,
-        .main_clk       = "gpt12_fck",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_GPT12_SHIFT,
-                        .module_offs = CORE_MOD,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
-                },
-        },
-        .dev_attr       = &capability_pwm_dev_attr,
-        .slaves         = omap2430_timer12_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_timer12_slaves),
-        .class          = &omap2xxx_timer_hwmod_class,
-};
-/* l4_wkup -> wd_timer2 */
-static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = {
-        {
-                .pa_start       = 0x49016000,
-                .pa_end         = 0x4901607f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
-        .master         = &omap2430_l4_wkup_hwmod,
-        .slave          = &omap2430_wd_timer2_hwmod,
-        .clk            = "mpu_wdt_ick",
-        .addr           = omap2430_wd_timer2_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* wd_timer2 */
-static struct omap_hwmod_ocp_if *omap2430_wd_timer2_slaves[] = {
-        &omap2430_l4_wkup__wd_timer2,
-};
-static struct omap_hwmod omap2430_wd_timer2_hwmod = {
-        .name           = "wd_timer2",
-        .class          = &omap2xxx_wd_timer_hwmod_class,
-        .main_clk       = "mpu_wdt_fck",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
-                        .module_offs = WKUP_MOD,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
-                },
-        },
-        .slaves         = omap2430_wd_timer2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_wd_timer2_slaves),
-};
-/* UART1 */
-static struct omap_hwmod_ocp_if *omap2430_uart1_slaves[] = {
-        &omap2_l4_core__uart1,
-};
-static struct omap_hwmod omap2430_uart1_hwmod = {
-        .name           = "uart1",
-        .mpu_irqs       = omap2_uart1_mpu_irqs,
-        .sdma_reqs      = omap2_uart1_sdma_reqs,
-        .main_clk       = "uart1_fck",
-        .prcm           = {
-                .omap2 = {
-                        .module_offs = CORE_MOD,
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_UART1_SHIFT,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
-                },
-        },
-        .slaves         = omap2430_uart1_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_uart1_slaves),
-        .class          = &omap2_uart_class,
-};
-/* UART2 */
-static struct omap_hwmod_ocp_if *omap2430_uart2_slaves[] = {
-        &omap2_l4_core__uart2,
-};
-static struct omap_hwmod omap2430_uart2_hwmod = {
-        .name           = "uart2",
-        .mpu_irqs       = omap2_uart2_mpu_irqs,
-        .sdma_reqs      = omap2_uart2_sdma_reqs,
-        .main_clk       = "uart2_fck",
-        .prcm           = {
-                .omap2 = {
-                        .module_offs = CORE_MOD,
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_UART2_SHIFT,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
-                },
-        },
-        .slaves         = omap2430_uart2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_uart2_slaves),
-        .class          = &omap2_uart_class,
-};
-/* UART3 */
-static struct omap_hwmod_ocp_if *omap2430_uart3_slaves[] = {
-        &omap2_l4_core__uart3,
-};
-static struct omap_hwmod omap2430_uart3_hwmod = {
-        .name           = "uart3",
-        .mpu_irqs       = omap2_uart3_mpu_irqs,
-        .sdma_reqs      = omap2_uart3_sdma_reqs,
-        .main_clk       = "uart3_fck",
-        .prcm           = {
-                .omap2 = {
-                        .module_offs = CORE_MOD,
-                        .prcm_reg_id = 2,
-                        .module_bit = OMAP24XX_EN_UART3_SHIFT,
-                        .idlest_reg_id = 2,
-                        .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
-                },
-        },
-        .slaves         = omap2430_uart3_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_uart3_slaves),
-        .class          = &omap2_uart_class,
-};
-/* dss */
-/* dss master ports */
-static struct omap_hwmod_ocp_if *omap2430_dss_masters[] = {
-        &omap2430_dss__l3,
-};
-/* l4_core -> dss */
-static struct omap_hwmod_ocp_if omap2430_l4_core__dss = {
-        .master         = &omap2430_l4_core_hwmod,
-        .slave          = &omap2430_dss_core_hwmod,
-        .clk            = "dss_ick",
-        .addr           = omap2_dss_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* dss slave ports */
-static struct omap_hwmod_ocp_if *omap2430_dss_slaves[] = {
-        &omap2430_l4_core__dss,
-};
-static struct omap_hwmod_opt_clk dss_opt_clks[] = {
-        /*
-         * The DSS HW needs all DSS clocks enabled during reset. The dss_core
-         * driver does not use these clocks.
-         */
-        { .role = "tv_clk", .clk = "dss_54m_fck" },
-        { .role = "sys_clk", .clk = "dss2_fck" },
-};
-static struct omap_hwmod omap2430_dss_core_hwmod = {
-        .name           = "dss_core",
-        .class          = &omap2_dss_hwmod_class,
-        .main_clk       = "dss1_fck", /* instead of dss_fck */
-        .sdma_reqs      = omap2xxx_dss_sdma_chs,
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_DSS1_SHIFT,
-                        .module_offs = CORE_MOD,
-                        .idlest_reg_id = 1,
-                        .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
-                },
-        },
-        .opt_clks       = dss_opt_clks,
-        .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
-        .slaves         = omap2430_dss_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_dss_slaves),
-        .masters        = omap2430_dss_masters,
-        .masters_cnt    = ARRAY_SIZE(omap2430_dss_masters),
-        .flags          = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-};
-/* l4_core -> dss_dispc */
-static struct omap_hwmod_ocp_if omap2430_l4_core__dss_dispc = {
-        .master         = &omap2430_l4_core_hwmod,
-        .slave          = &omap2430_dss_dispc_hwmod,
-        .clk            = "dss_ick",
-        .addr           = omap2_dss_dispc_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* dss_dispc slave ports */
-static struct omap_hwmod_ocp_if *omap2430_dss_dispc_slaves[] = {
-        &omap2430_l4_core__dss_dispc,
-};
-static struct omap_hwmod omap2430_dss_dispc_hwmod = {
-        .name           = "dss_dispc",
-        .class          = &omap2_dispc_hwmod_class,
-        .mpu_irqs       = omap2_dispc_irqs,
-        .main_clk       = "dss1_fck",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_DSS1_SHIFT,
-                        .module_offs = CORE_MOD,
-                        .idlest_reg_id = 1,
-                        .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
-                },
-        },
-        .slaves         = omap2430_dss_dispc_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_dss_dispc_slaves),
-        .flags          = HWMOD_NO_IDLEST,
-        .dev_attr       = &omap2_3_dss_dispc_dev_attr
-};
-/* l4_core -> dss_rfbi */
-static struct omap_hwmod_ocp_if omap2430_l4_core__dss_rfbi = {
-        .master         = &omap2430_l4_core_hwmod,
-        .slave          = &omap2430_dss_rfbi_hwmod,
-        .clk            = "dss_ick",
-        .addr           = omap2_dss_rfbi_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* dss_rfbi slave ports */
-static struct omap_hwmod_ocp_if *omap2430_dss_rfbi_slaves[] = {
-        &omap2430_l4_core__dss_rfbi,
-};
-static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
-        { .role = "ick", .clk = "dss_ick" },
-};
-static struct omap_hwmod omap2430_dss_rfbi_hwmod = {
-        .name           = "dss_rfbi",
-        .class          = &omap2_rfbi_hwmod_class,
-        .main_clk       = "dss1_fck",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_DSS1_SHIFT,
-                        .module_offs = CORE_MOD,
-                },
-        },
-        .opt_clks       = dss_rfbi_opt_clks,
-        .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
-        .slaves         = omap2430_dss_rfbi_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_dss_rfbi_slaves),
-        .flags          = HWMOD_NO_IDLEST,
-};
-/* l4_core -> dss_venc */
-static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = {
-        .master         = &omap2430_l4_core_hwmod,
-        .slave          = &omap2430_dss_venc_hwmod,
-        .clk            = "dss_ick",
-        .addr           = omap2_dss_venc_addrs,
-        .flags          = OCPIF_SWSUP_IDLE,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* dss_venc slave ports */
-static struct omap_hwmod_ocp_if *omap2430_dss_venc_slaves[] = {
-        &omap2430_l4_core__dss_venc,
-};
-static struct omap_hwmod omap2430_dss_venc_hwmod = {
-        .name           = "dss_venc",
-        .class          = &omap2_venc_hwmod_class,
-        .main_clk       = "dss_54m_fck",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_DSS1_SHIFT,
-                        .module_offs = CORE_MOD,
-                },
-        },
-        .slaves         = omap2430_dss_venc_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_dss_venc_slaves),
-        .flags          = HWMOD_NO_IDLEST,
 };
 /* I2C common */
@@ -1099,11 +84,6 @@ static struct omap_i2c_dev_attr i2c_dev_attr = {
 };
 /* I2C1 */
-static struct omap_hwmod_ocp_if *omap2430_i2c1_slaves[] = {
-        &omap2430_l4_core__i2c1,
-};
 static struct omap_hwmod omap2430_i2c1_hwmod = {
        .name           = "i2c1",
        .flags          = HWMOD_16BIT_REG,
@@ -1127,18 +107,11 @@ static struct omap_hwmod omap2430_i2c1_hwmod = {
                        .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT,
                },
        },
-        .slaves         = omap2430_i2c1_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_i2c1_slaves),
        .class          = &i2c_class,
        .dev_attr       = &i2c_dev_attr,
 };
 /* I2C2 */
-static struct omap_hwmod_ocp_if *omap2430_i2c2_slaves[] = {
-        &omap2430_l4_core__i2c2,
-};
 static struct omap_hwmod omap2430_i2c2_hwmod = {
        .name           = "i2c2",
        .flags          = HWMOD_16BIT_REG,
@@ -1154,218 +127,16 @@ static struct omap_hwmod omap2430_i2c2_hwmod = {
                        .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT,
                },
        },
-        .slaves         = omap2430_i2c2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_i2c2_slaves),
        .class          = &i2c_class,
        .dev_attr       = &i2c_dev_attr,
 };
-/* l4_wkup -> gpio1 */
-static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = {
-        {
-                .pa_start       = 0x4900C000,
-                .pa_end         = 0x4900C1ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = {
-        .master         = &omap2430_l4_wkup_hwmod,
-        .slave          = &omap2430_gpio1_hwmod,
-        .clk            = "gpios_ick",
-        .addr           = omap2430_gpio1_addr_space,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* l4_wkup -> gpio2 */
-static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = {
-        {
-                .pa_start       = 0x4900E000,
-                .pa_end         = 0x4900E1ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = {
-        .master         = &omap2430_l4_wkup_hwmod,
-        .slave          = &omap2430_gpio2_hwmod,
-        .clk            = "gpios_ick",
-        .addr           = omap2430_gpio2_addr_space,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* l4_wkup -> gpio3 */
-static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = {
-        {
-                .pa_start       = 0x49010000,
-                .pa_end         = 0x490101ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = {
-        .master         = &omap2430_l4_wkup_hwmod,
-        .slave          = &omap2430_gpio3_hwmod,
-        .clk            = "gpios_ick",
-        .addr           = omap2430_gpio3_addr_space,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* l4_wkup -> gpio4 */
-static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = {
-        {
-                .pa_start       = 0x49012000,
-                .pa_end         = 0x490121ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = {
-        .master         = &omap2430_l4_wkup_hwmod,
-        .slave          = &omap2430_gpio4_hwmod,
-        .clk            = "gpios_ick",
-        .addr           = omap2430_gpio4_addr_space,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* l4_core -> gpio5 */
-static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = {
-        {
-                .pa_start       = 0x480B6000,
-                .pa_end         = 0x480B61ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = {
-        .master         = &omap2430_l4_core_hwmod,
-        .slave          = &omap2430_gpio5_hwmod,
-        .clk            = "gpio5_ick",
-        .addr           = omap2430_gpio5_addr_space,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* gpio dev_attr */
-static struct omap_gpio_dev_attr gpio_dev_attr = {
-        .bank_width = 32,
-        .dbck_flag = false,
-};
-/* gpio1 */
-static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = {
-        &omap2430_l4_wkup__gpio1,
-};
-static struct omap_hwmod omap2430_gpio1_hwmod = {
-        .name           = "gpio1",
-        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .mpu_irqs       = omap2_gpio1_irqs,
-        .main_clk       = "gpios_fck",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
-                        .module_offs = WKUP_MOD,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_EN_GPIOS_SHIFT,
-                },
-        },
-        .slaves         = omap2430_gpio1_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_gpio1_slaves),
-        .class          = &omap2xxx_gpio_hwmod_class,
-        .dev_attr       = &gpio_dev_attr,
-};
-/* gpio2 */
-static struct omap_hwmod_ocp_if *omap2430_gpio2_slaves[] = {
-        &omap2430_l4_wkup__gpio2,
-};
-static struct omap_hwmod omap2430_gpio2_hwmod = {
-        .name           = "gpio2",
-        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .mpu_irqs       = omap2_gpio2_irqs,
-        .main_clk       = "gpios_fck",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
-                        .module_offs = WKUP_MOD,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
-                },
-        },
-        .slaves         = omap2430_gpio2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_gpio2_slaves),
-        .class          = &omap2xxx_gpio_hwmod_class,
-        .dev_attr       = &gpio_dev_attr,
-};
-/* gpio3 */
-static struct omap_hwmod_ocp_if *omap2430_gpio3_slaves[] = {
-        &omap2430_l4_wkup__gpio3,
-};
-static struct omap_hwmod omap2430_gpio3_hwmod = {
-        .name           = "gpio3",
-        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .mpu_irqs       = omap2_gpio3_irqs,
-        .main_clk       = "gpios_fck",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
-                        .module_offs = WKUP_MOD,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
-                },
-        },
-        .slaves         = omap2430_gpio3_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_gpio3_slaves),
-        .class          = &omap2xxx_gpio_hwmod_class,
-        .dev_attr       = &gpio_dev_attr,
-};
-/* gpio4 */
-static struct omap_hwmod_ocp_if *omap2430_gpio4_slaves[] = {
-        &omap2430_l4_wkup__gpio4,
-};
-static struct omap_hwmod omap2430_gpio4_hwmod = {
-        .name           = "gpio4",
-        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .mpu_irqs       = omap2_gpio4_irqs,
-        .main_clk       = "gpios_fck",
-        .prcm           = {
-                .omap2 = {
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
-                        .module_offs = WKUP_MOD,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
-                },
-        },
-        .slaves         = omap2430_gpio4_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_gpio4_slaves),
-        .class          = &omap2xxx_gpio_hwmod_class,
-        .dev_attr       = &gpio_dev_attr,
-};
 /* gpio5 */
 static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = {
        { .irq = 33 }, /* INT_24XX_GPIO_BANK5 */
        { .irq = -1 }
 };
-static struct omap_hwmod_ocp_if *omap2430_gpio5_slaves[] = {
-        &omap2430_l4_core__gpio5,
-};
 static struct omap_hwmod omap2430_gpio5_hwmod = {
        .name           = "gpio5",
        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
@@ -1380,10 +151,8 @@ static struct omap_hwmod omap2430_gpio5_hwmod = {
                        .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT,
                },
        },
-        .slaves         = omap2430_gpio5_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_gpio5_slaves),
        .class          = &omap2xxx_gpio_hwmod_class,
-        .dev_attr       = &gpio_dev_attr,
+        .dev_attr       = &omap2xxx_gpio_dev_attr,
 };
 /* dma attributes */
@@ -1393,66 +162,21 @@ static struct omap_dma_dev_attr dma_dev_attr = {
        .lch_count = 32,
 };
-/* dma_system -> L3 */
-static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = {
-        .master         = &omap2430_dma_system_hwmod,
-        .slave          = &omap2430_l3_main_hwmod,
-        .clk            = "core_l3_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* dma_system master ports */
-static struct omap_hwmod_ocp_if *omap2430_dma_system_masters[] = {
-        &omap2430_dma_system__l3,
-};
-/* l4_core -> dma_system */
-static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = {
-        .master         = &omap2430_l4_core_hwmod,
-        .slave          = &omap2430_dma_system_hwmod,
-        .clk            = "sdma_ick",
-        .addr           = omap2_dma_system_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* dma_system slave ports */
-static struct omap_hwmod_ocp_if *omap2430_dma_system_slaves[] = {
-        &omap2430_l4_core__dma_system,
-};
 static struct omap_hwmod omap2430_dma_system_hwmod = {
        .name           = "dma",
        .class          = &omap2xxx_dma_hwmod_class,
        .mpu_irqs       = omap2_dma_system_irqs,
        .main_clk       = "core_l3_ck",
-        .slaves         = omap2430_dma_system_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_dma_system_slaves),
-        .masters        = omap2430_dma_system_masters,
-        .masters_cnt    = ARRAY_SIZE(omap2430_dma_system_masters),
        .dev_attr       = &dma_dev_attr,
        .flags          = HWMOD_NO_IDLEST,
 };
 /* mailbox */
-static struct omap_hwmod omap2430_mailbox_hwmod;
 static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = {
        { .irq = 26 },
        { .irq = -1 }
 };
-/* l4_core -> mailbox */
-static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = {
-        .master         = &omap2430_l4_core_hwmod,
-        .slave          = &omap2430_mailbox_hwmod,
-        .addr           = omap2_mailbox_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* mailbox slave ports */
-static struct omap_hwmod_ocp_if *omap2430_mailbox_slaves[] = {
-        &omap2430_l4_core__mailbox,
-};
 static struct omap_hwmod omap2430_mailbox_hwmod = {
        .name           = "mailbox",
        .class          = &omap2xxx_mailbox_hwmod_class,
@@ -1467,66 +191,6 @@ static struct omap_hwmod omap2430_mailbox_hwmod = {
                        .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
                },
        },
-        .slaves         = omap2430_mailbox_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_mailbox_slaves),
-};
-/* mcspi1 */
-static struct omap_hwmod_ocp_if *omap2430_mcspi1_slaves[] = {
-        &omap2430_l4_core__mcspi1,
-};
-static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
-        .num_chipselect = 4,
-};
-static struct omap_hwmod omap2430_mcspi1_hwmod = {
-        .name           = "mcspi1_hwmod",
-        .mpu_irqs       = omap2_mcspi1_mpu_irqs,
-        .sdma_reqs      = omap2_mcspi1_sdma_reqs,
-        .main_clk       = "mcspi1_fck",
-        .prcm           = {
-                .omap2 = {
-                        .module_offs = CORE_MOD,
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
-                },
-        },
-        .slaves         = omap2430_mcspi1_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_mcspi1_slaves),
-        .class          = &omap2xxx_mcspi_class,
-        .dev_attr       = &omap_mcspi1_dev_attr,
-};
-/* mcspi2 */
-static struct omap_hwmod_ocp_if *omap2430_mcspi2_slaves[] = {
-        &omap2430_l4_core__mcspi2,
-};
-static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
-        .num_chipselect = 2,
-};
-static struct omap_hwmod omap2430_mcspi2_hwmod = {
-        .name           = "mcspi2_hwmod",
-        .mpu_irqs       = omap2_mcspi2_mpu_irqs,
-        .sdma_reqs      = omap2_mcspi2_sdma_reqs,
-        .main_clk       = "mcspi2_fck",
-        .prcm           = {
-                .omap2 = {
-                        .module_offs = CORE_MOD,
-                        .prcm_reg_id = 1,
-                        .module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
-                        .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
-                },
-        },
-        .slaves         = omap2430_mcspi2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_mcspi2_slaves),
-        .class          = &omap2xxx_mcspi_class,
-        .dev_attr       = &omap_mcspi2_dev_attr,
 };
 /* mcspi3 */
@@ -1543,16 +207,12 @@ static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = {
        { .dma_req = -1 }
 };
-static struct omap_hwmod_ocp_if *omap2430_mcspi3_slaves[] = {
-        &omap2430_l4_core__mcspi3,
-};
 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
        .num_chipselect = 2,
 };
 static struct omap_hwmod omap2430_mcspi3_hwmod = {
-        .name           = "mcspi3_hwmod",
+        .name           = "mcspi3",
        .mpu_irqs       = omap2430_mcspi3_mpu_irqs,
        .sdma_reqs      = omap2430_mcspi3_sdma_reqs,
        .main_clk       = "mcspi3_fck",
@@ -1565,15 +225,11 @@ static struct omap_hwmod omap2430_mcspi3_hwmod = {
                        .idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT,
                },
        },
-        .slaves         = omap2430_mcspi3_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_mcspi3_slaves),
        .class          = &omap2xxx_mcspi_class,
        .dev_attr       = &omap_mcspi3_dev_attr,
 };
-/*
+/* usbhsotg */
- * usbhsotg
- */
 static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = {
        .rev_offs       = 0x0400,
        .sysc_offs      = 0x0404,
@@ -1612,10 +268,6 @@ static struct omap_hwmod omap2430_usbhsotg_hwmod = {
                        .idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT,
                },
        },
-        .masters        = omap2430_usbhsotg_masters,
-        .masters_cnt    = ARRAY_SIZE(omap2430_usbhsotg_masters),
-        .slaves         = omap2430_usbhsotg_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_usbhsotg_slaves),
        .class          = &usbotg_class,
        /*
         * Erratum ID: i479  idle_req / idle_ack mechanism potentially
@@ -1653,20 +305,6 @@ static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = {
        { .irq = -1 }
 };
-/* l4_core -> mcbsp1 */
-static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = {
-        .master         = &omap2430_l4_core_hwmod,
-        .slave          = &omap2430_mcbsp1_hwmod,
-        .clk            = "mcbsp1_ick",
-        .addr           = omap2_mcbsp1_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* mcbsp1 slave ports */
-static struct omap_hwmod_ocp_if *omap2430_mcbsp1_slaves[] = {
-        &omap2430_l4_core__mcbsp1,
-};
 static struct omap_hwmod omap2430_mcbsp1_hwmod = {
        .name           = "mcbsp1",
        .class          = &omap2430_mcbsp_hwmod_class,
@@ -1682,8 +320,6 @@ static struct omap_hwmod omap2430_mcbsp1_hwmod = {
                        .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
                },
        },
-        .slaves         = omap2430_mcbsp1_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp1_slaves),
 };
 /* mcbsp2 */
@@ -1694,20 +330,6 @@ static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = {
        { .irq = -1 }
 };
-/* l4_core -> mcbsp2 */
-static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = {
-        .master         = &omap2430_l4_core_hwmod,
-        .slave          = &omap2430_mcbsp2_hwmod,
-        .clk            = "mcbsp2_ick",
-        .addr           = omap2xxx_mcbsp2_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* mcbsp2 slave ports */
-static struct omap_hwmod_ocp_if *omap2430_mcbsp2_slaves[] = {
-        &omap2430_l4_core__mcbsp2,
-};
 static struct omap_hwmod omap2430_mcbsp2_hwmod = {
        .name           = "mcbsp2",
        .class          = &omap2430_mcbsp_hwmod_class,
@@ -1723,8 +345,6 @@ static struct omap_hwmod omap2430_mcbsp2_hwmod = {
                        .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
                },
        },
-        .slaves         = omap2430_mcbsp2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp2_slaves),
 };
 /* mcbsp3 */
@@ -1735,30 +355,6 @@ static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = {
        { .irq = -1 }
 };
-static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = {
-        {
-                .name           = "mpu",
-                .pa_start       = 0x4808C000,
-                .pa_end         = 0x4808C0ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_core -> mcbsp3 */
-static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = {
-        .master         = &omap2430_l4_core_hwmod,
-        .slave          = &omap2430_mcbsp3_hwmod,
-        .clk            = "mcbsp3_ick",
-        .addr           = omap2430_mcbsp3_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* mcbsp3 slave ports */
-static struct omap_hwmod_ocp_if *omap2430_mcbsp3_slaves[] = {
-        &omap2430_l4_core__mcbsp3,
-};
 static struct omap_hwmod omap2430_mcbsp3_hwmod = {
        .name           = "mcbsp3",
        .class          = &omap2430_mcbsp_hwmod_class,
@@ -1774,8 +370,6 @@ static struct omap_hwmod omap2430_mcbsp3_hwmod = {
                        .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT,
                },
        },
-        .slaves         = omap2430_mcbsp3_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp3_slaves),
 };
 /* mcbsp4 */
@@ -1792,30 +386,6 @@ static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = {
        { .dma_req = -1 }
 };
-static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = {
-        {
-                .name           = "mpu",
-                .pa_start       = 0x4808E000,
-                .pa_end         = 0x4808E0ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_core -> mcbsp4 */
-static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = {
-        .master         = &omap2430_l4_core_hwmod,
-        .slave          = &omap2430_mcbsp4_hwmod,
-        .clk            = "mcbsp4_ick",
-        .addr           = omap2430_mcbsp4_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* mcbsp4 slave ports */
-static struct omap_hwmod_ocp_if *omap2430_mcbsp4_slaves[] = {
-        &omap2430_l4_core__mcbsp4,
-};
 static struct omap_hwmod omap2430_mcbsp4_hwmod = {
        .name           = "mcbsp4",
        .class          = &omap2430_mcbsp_hwmod_class,
@@ -1831,8 +401,6 @@ static struct omap_hwmod omap2430_mcbsp4_hwmod = {
                        .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT,
                },
        },
-        .slaves         = omap2430_mcbsp4_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp4_slaves),
 };
 /* mcbsp5 */
@@ -1849,30 +417,6 @@ static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = {
        { .dma_req = -1 }
 };
-static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = {
-        {
-                .name           = "mpu",
-                .pa_start       = 0x48096000,
-                .pa_end         = 0x480960ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_core -> mcbsp5 */
-static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = {
-        .master         = &omap2430_l4_core_hwmod,
-        .slave          = &omap2430_mcbsp5_hwmod,
-        .clk            = "mcbsp5_ick",
-        .addr           = omap2430_mcbsp5_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* mcbsp5 slave ports */
-static struct omap_hwmod_ocp_if *omap2430_mcbsp5_slaves[] = {
-        &omap2430_l4_core__mcbsp5,
-};
 static struct omap_hwmod omap2430_mcbsp5_hwmod = {
        .name           = "mcbsp5",
        .class          = &omap2430_mcbsp_hwmod_class,
@@ -1888,12 +432,9 @@ static struct omap_hwmod omap2430_mcbsp5_hwmod = {
                        .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT,
                },
        },
-        .slaves         = omap2430_mcbsp5_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp5_slaves),
 };
 /* MMC/SD/SDIO common */
 static struct omap_hwmod_class_sysconfig omap2430_mmc_sysc = {
        .rev_offs       = 0x1fc,
        .sysc_offs      = 0x10,
@@ -1911,7 +452,6 @@ static struct omap_hwmod_class omap2430_mmc_class = {
 };
 /* MMC/SD/SDIO1 */
 static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = {
        { .irq = 83 },
        { .irq = -1 }
@@ -1927,10 +467,6 @@ static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = {
        { .role = "dbck", .clk = "mmchsdb1_fck" },
 };
-static struct omap_hwmod_ocp_if *omap2430_mmc1_slaves[] = {
-        &omap2430_l4_core__mmc1,
-};
 static struct omap_mmc_dev_attr mmc1_dev_attr = {
        .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
 };
@@ -1953,13 +489,10 @@ static struct omap_hwmod omap2430_mmc1_hwmod = {
                },
        },
        .dev_attr       = &mmc1_dev_attr,
-        .slaves         = omap2430_mmc1_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_mmc1_slaves),
        .class          = &omap2430_mmc_class,
 };
 /* MMC/SD/SDIO2 */
 static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = {
        { .irq = 86 },
        { .irq = -1 }
@@ -1975,10 +508,6 @@ static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = {
        { .role = "dbck", .clk = "mmchsdb2_fck" },
 };
-static struct omap_hwmod_ocp_if *omap2430_mmc2_slaves[] = {
-        &omap2430_l4_core__mmc2,
-};
 static struct omap_hwmod omap2430_mmc2_hwmod = {
        .name           = "mmc2",
        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
@@ -1996,78 +525,418 @@ static struct omap_hwmod omap2430_mmc2_hwmod = {
                        .idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT,
                },
        },
-        .slaves         = omap2430_mmc2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap2430_mmc2_slaves),
        .class          = &omap2430_mmc_class,
 };
-static __initdata struct omap_hwmod *omap2430_hwmods[] = {
+/* HDQ1W/1-wire */
-        &omap2430_l3_main_hwmod,
+static struct omap_hwmod omap2430_hdq1w_hwmod = {
-        &omap2430_l4_core_hwmod,
+        .name           = "hdq1w",
-        &omap2430_l4_wkup_hwmod,
+        .mpu_irqs       = omap2_hdq1w_mpu_irqs,
-        &omap2430_mpu_hwmod,
+        .main_clk       = "hdq_fck",
-        &omap2430_iva_hwmod,
+        .prcm           = {
+                .omap2 = {
-        &omap2430_timer1_hwmod,
+                        .module_offs = CORE_MOD,
-        &omap2430_timer2_hwmod,
+                        .prcm_reg_id = 1,
-        &omap2430_timer3_hwmod,
+                        .module_bit = OMAP24XX_EN_HDQ_SHIFT,
-        &omap2430_timer4_hwmod,
+                        .idlest_reg_id = 1,
-        &omap2430_timer5_hwmod,
+                        .idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,
-        &omap2430_timer6_hwmod,
+                },
-        &omap2430_timer7_hwmod,
+        },
-        &omap2430_timer8_hwmod,
+        .class          = &omap2_hdq1w_class,
-        &omap2430_timer9_hwmod,
+};
-        &omap2430_timer10_hwmod,
-        &omap2430_timer11_hwmod,
+/*
-        &omap2430_timer12_hwmod,
+ * interfaces
+ */
-        &omap2430_wd_timer2_hwmod,
-        &omap2430_uart1_hwmod,
+/* L3 -> L4_CORE interface */
-        &omap2430_uart2_hwmod,
+/* l3_core -> usbhsotg  interface */
-        &omap2430_uart3_hwmod,
+static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = {
-        /* dss class */
+        .master         = &omap2430_usbhsotg_hwmod,
-        &omap2430_dss_core_hwmod,
+        .slave          = &omap2xxx_l3_main_hwmod,
-        &omap2430_dss_dispc_hwmod,
+        .clk            = "core_l3_ck",
-        &omap2430_dss_rfbi_hwmod,
+        .user           = OCP_USER_MPU,
-        &omap2430_dss_venc_hwmod,
+};
-        /* i2c class */
-        &omap2430_i2c1_hwmod,
+/* L4 CORE -> I2C1 interface */
-        &omap2430_i2c2_hwmod,
+static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = {
-        &omap2430_mmc1_hwmod,
+        .master         = &omap2xxx_l4_core_hwmod,
-        &omap2430_mmc2_hwmod,
+        .slave          = &omap2430_i2c1_hwmod,
+        .clk            = "i2c1_ick",
-        /* gpio class */
+        .addr           = omap2_i2c1_addr_space,
-        &omap2430_gpio1_hwmod,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-        &omap2430_gpio2_hwmod,
+};
-        &omap2430_gpio3_hwmod,
-        &omap2430_gpio4_hwmod,
+/* L4 CORE -> I2C2 interface */
-        &omap2430_gpio5_hwmod,
+static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = {
+        .master         = &omap2xxx_l4_core_hwmod,
-        /* dma_system class*/
+        .slave          = &omap2430_i2c2_hwmod,
-        &omap2430_dma_system_hwmod,
+        .clk            = "i2c2_ick",
+        .addr           = omap2_i2c2_addr_space,
-        /* mcbsp class */
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-        &omap2430_mcbsp1_hwmod,
+};
-        &omap2430_mcbsp2_hwmod,
-        &omap2430_mcbsp3_hwmod,
+static struct omap_hwmod_addr_space omap2430_usbhsotg_addrs[] = {
-        &omap2430_mcbsp4_hwmod,
+        {
-        &omap2430_mcbsp5_hwmod,
+                .pa_start       = OMAP243X_HS_BASE,
+                .pa_end         = OMAP243X_HS_BASE + SZ_4K - 1,
-        /* mailbox class */
+                .flags          = ADDR_TYPE_RT
-        &omap2430_mailbox_hwmod,
+        },
+        { }
-        /* mcspi class */
+};
-        &omap2430_mcspi1_hwmod,
-        &omap2430_mcspi2_hwmod,
+/*  l4_core ->usbhsotg  interface */
-        &omap2430_mcspi3_hwmod,
+static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = {
+        .master         = &omap2xxx_l4_core_hwmod,
-        /* usbotg class*/
+        .slave          = &omap2430_usbhsotg_hwmod,
-        &omap2430_usbhsotg_hwmod,
+        .clk            = "usb_l4_ick",
+        .addr           = omap2430_usbhsotg_addrs,
+        .user           = OCP_USER_MPU,
+};
+/* L4 CORE -> MMC1 interface */
+static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2430_mmc1_hwmod,
+        .clk            = "mmchs1_ick",
+        .addr           = omap2430_mmc1_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* L4 CORE -> MMC2 interface */
+static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2430_mmc2_hwmod,
+        .clk            = "mmchs2_ick",
+        .addr           = omap2430_mmc2_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4 core -> mcspi3 interface */
+static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2430_mcspi3_hwmod,
+        .clk            = "mcspi3_ick",
+        .addr           = omap2430_mcspi3_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* IVA2 <- L3 interface */
+static struct omap_hwmod_ocp_if omap2430_l3__iva = {
+        .master         = &omap2xxx_l3_main_hwmod,
+        .slave          = &omap2430_iva_hwmod,
+        .clk            = "core_l3_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = {
+        {
+                .pa_start       = 0x49018000,
+                .pa_end         = 0x49018000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_wkup -> timer1 */
+static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = {
+        .master         = &omap2xxx_l4_wkup_hwmod,
+        .slave          = &omap2xxx_timer1_hwmod,
+        .clk            = "gpt1_ick",
+        .addr           = omap2430_timer1_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_wkup -> wd_timer2 */
+static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = {
+        {
+                .pa_start       = 0x49016000,
+                .pa_end         = 0x4901607f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
+        .master         = &omap2xxx_l4_wkup_hwmod,
+        .slave          = &omap2xxx_wd_timer2_hwmod,
+        .clk            = "mpu_wdt_ick",
+        .addr           = omap2430_wd_timer2_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_wkup -> gpio1 */
+static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = {
+        {
+                .pa_start       = 0x4900C000,
+                .pa_end         = 0x4900C1ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = {
+        .master         = &omap2xxx_l4_wkup_hwmod,
+        .slave          = &omap2xxx_gpio1_hwmod,
+        .clk            = "gpios_ick",
+        .addr           = omap2430_gpio1_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_wkup -> gpio2 */
+static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = {
+        {
+                .pa_start       = 0x4900E000,
+                .pa_end         = 0x4900E1ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = {
+        .master         = &omap2xxx_l4_wkup_hwmod,
+        .slave          = &omap2xxx_gpio2_hwmod,
+        .clk            = "gpios_ick",
+        .addr           = omap2430_gpio2_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_wkup -> gpio3 */
+static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = {
+        {
+                .pa_start       = 0x49010000,
+                .pa_end         = 0x490101ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = {
+        .master         = &omap2xxx_l4_wkup_hwmod,
+        .slave          = &omap2xxx_gpio3_hwmod,
+        .clk            = "gpios_ick",
+        .addr           = omap2430_gpio3_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_wkup -> gpio4 */
+static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = {
+        {
+                .pa_start       = 0x49012000,
+                .pa_end         = 0x490121ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = {
+        .master         = &omap2xxx_l4_wkup_hwmod,
+        .slave          = &omap2xxx_gpio4_hwmod,
+        .clk            = "gpios_ick",
+        .addr           = omap2430_gpio4_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_core -> gpio5 */
+static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = {
+        {
+                .pa_start       = 0x480B6000,
+                .pa_end         = 0x480B61ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2430_gpio5_hwmod,
+        .clk            = "gpio5_ick",
+        .addr           = omap2430_gpio5_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* dma_system -> L3 */
+static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = {
+        .master         = &omap2430_dma_system_hwmod,
+        .slave          = &omap2xxx_l3_main_hwmod,
+        .clk            = "core_l3_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_core -> dma_system */
+static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2430_dma_system_hwmod,
+        .clk            = "sdma_ick",
+        .addr           = omap2_dma_system_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_core -> mailbox */
+static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2430_mailbox_hwmod,
+        .addr           = omap2_mailbox_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_core -> mcbsp1 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2430_mcbsp1_hwmod,
+        .clk            = "mcbsp1_ick",
+        .addr           = omap2_mcbsp1_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_core -> mcbsp2 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2430_mcbsp2_hwmod,
+        .clk            = "mcbsp2_ick",
+        .addr           = omap2xxx_mcbsp2_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = {
+        {
+                .name           = "mpu",
+                .pa_start       = 0x4808C000,
+                .pa_end         = 0x4808C0ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_core -> mcbsp3 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2430_mcbsp3_hwmod,
+        .clk            = "mcbsp3_ick",
+        .addr           = omap2430_mcbsp3_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = {
+        {
+                .name           = "mpu",
+                .pa_start       = 0x4808E000,
+                .pa_end         = 0x4808E0ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_core -> mcbsp4 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2430_mcbsp4_hwmod,
+        .clk            = "mcbsp4_ick",
+        .addr           = omap2430_mcbsp4_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = {
+        {
+                .name           = "mpu",
+                .pa_start       = 0x48096000,
+                .pa_end         = 0x480960ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_core -> mcbsp5 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2430_mcbsp5_hwmod,
+        .clk            = "mcbsp5_ick",
+        .addr           = omap2430_mcbsp5_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_core -> hdq1w */
+static struct omap_hwmod_ocp_if omap2430_l4_core__hdq1w = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2430_hdq1w_hwmod,
+        .clk            = "hdq_ick",
+        .addr           = omap2_hdq1w_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+        .flags          = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
+};
+/* l4_wkup -> 32ksync_counter */
+static struct omap_hwmod_addr_space omap2430_counter_32k_addrs[] = {
+        {
+                .pa_start       = 0x49020000,
+                .pa_end         = 0x4902001f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if omap2430_l4_wkup__counter_32k = {
+        .master         = &omap2xxx_l4_wkup_hwmod,
+        .slave          = &omap2xxx_counter_32k_hwmod,
+        .clk            = "sync_32k_ick",
+        .addr           = omap2430_counter_32k_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = {
+        &omap2xxx_l3_main__l4_core,
+        &omap2xxx_mpu__l3_main,
+        &omap2xxx_dss__l3,
+        &omap2430_usbhsotg__l3,
+        &omap2430_l4_core__i2c1,
+        &omap2430_l4_core__i2c2,
+        &omap2xxx_l4_core__l4_wkup,
+        &omap2_l4_core__uart1,
+        &omap2_l4_core__uart2,
+        &omap2_l4_core__uart3,
+        &omap2430_l4_core__usbhsotg,
+        &omap2430_l4_core__mmc1,
+        &omap2430_l4_core__mmc2,
+        &omap2xxx_l4_core__mcspi1,
+        &omap2xxx_l4_core__mcspi2,
+        &omap2430_l4_core__mcspi3,
+        &omap2430_l3__iva,
+        &omap2430_l4_wkup__timer1,
+        &omap2xxx_l4_core__timer2,
+        &omap2xxx_l4_core__timer3,
+        &omap2xxx_l4_core__timer4,
+        &omap2xxx_l4_core__timer5,
+        &omap2xxx_l4_core__timer6,
+        &omap2xxx_l4_core__timer7,
+        &omap2xxx_l4_core__timer8,
+        &omap2xxx_l4_core__timer9,
+        &omap2xxx_l4_core__timer10,
+        &omap2xxx_l4_core__timer11,
+        &omap2xxx_l4_core__timer12,
+        &omap2430_l4_wkup__wd_timer2,
+        &omap2xxx_l4_core__dss,
+        &omap2xxx_l4_core__dss_dispc,
+        &omap2xxx_l4_core__dss_rfbi,
+        &omap2xxx_l4_core__dss_venc,
+        &omap2430_l4_wkup__gpio1,
+        &omap2430_l4_wkup__gpio2,
+        &omap2430_l4_wkup__gpio3,
+        &omap2430_l4_wkup__gpio4,
+        &omap2430_l4_core__gpio5,
+        &omap2430_dma_system__l3,
+        &omap2430_l4_core__dma_system,
+        &omap2430_l4_core__mailbox,
+        &omap2430_l4_core__mcbsp1,
+        &omap2430_l4_core__mcbsp2,
+        &omap2430_l4_core__mcbsp3,
+        &omap2430_l4_core__mcbsp4,
+        &omap2430_l4_core__mcbsp5,
+        &omap2430_l4_core__hdq1w,
+        &omap2430_l4_wkup__counter_32k,
        NULL,
 };
 int __init omap2430_hwmod_init(void)
 {
-        return omap_hwmod_register(omap2430_hwmods);
+        return omap_hwmod_register_links(omap2430_hwmod_ocp_ifs);
 }
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c
index 04637fabadd2..cbb4ef6544ad 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c
@@ -171,3 +171,12 @@ struct omap_hwmod_addr_space omap2_mcbsp1_addrs[] = {
        },
        { }
 };
+struct omap_hwmod_addr_space omap2_hdq1w_addr_space[] = {
+        {
+                .pa_start       = 0x480b2000,
+                .pa_end         = 0x480b2fff,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
index f08e442af397..102d76e9e9ea 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
@@ -2,6 +2,7 @@
 * omap_hwmod_2xxx_3xxx_ipblock_data.c - common IP block data for OMAP2/3
 *
 * Copyright (C) 2011 Nokia Corporation
+ * Copyright (C) 2012 Texas Instruments, Inc.
 * Paul Walmsley
 *
 * This program is free software; you can redistribute it and/or modify
@@ -12,6 +13,7 @@
 #include <plat/serial.h>
 #include <plat/dma.h>
 #include <plat/common.h>
+#include <plat/hdq1w.h>
 #include <mach/irqs.h>
@@ -302,3 +304,23 @@ struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[] = {
        { .irq = -1 }
 };
+struct omap_hwmod_class_sysconfig omap2_hdq1w_sysc = {
+        .rev_offs       = 0x0,
+        .sysc_offs      = 0x14,
+        .syss_offs      = 0x18,
+        .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+                           SYSS_HAS_RESET_STATUS),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+struct omap_hwmod_class omap2_hdq1w_class = {
+        .name   = "hdq1w",
+        .sysc   = &omap2_hdq1w_sysc,
+        .reset  = &omap_hdq1w_reset,
+};
+struct omap_hwmod_irq_info omap2_hdq1w_mpu_irqs[] = {
+        { .irq = 58, },
+        { .irq = -1 }
+};
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
index 4f3547c2a49e..5178e40e84f9 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
@@ -15,10 +15,12 @@
 #include <plat/omap_hwmod.h>
 #include <plat/serial.h>
+#include <plat/l3_2xxx.h>
+#include <plat/l4_2xxx.h>
 #include "omap_hwmod_common_data.h"
-struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[] = {
+static struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[] = {
        {
                .pa_start       = OMAP2_UART1_BASE,
                .pa_end         = OMAP2_UART1_BASE + SZ_8K - 1,
@@ -27,7 +29,7 @@ struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[] = {
        { }
 };
-struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[] = {
+static struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[] = {
        {
                .pa_start       = OMAP2_UART2_BASE,
                .pa_end         = OMAP2_UART2_BASE + SZ_1K - 1,
@@ -36,7 +38,7 @@ struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[] = {
        { }
 };
-struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[] = {
+static struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[] = {
        {
                .pa_start       = OMAP2_UART3_BASE,
                .pa_end         = OMAP2_UART3_BASE + SZ_1K - 1,
@@ -45,7 +47,7 @@ struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[] = {
        { }
 };
-struct omap_hwmod_addr_space omap2xxx_timer2_addrs[] = {
+static struct omap_hwmod_addr_space omap2xxx_timer2_addrs[] = {
        {
                .pa_start       = 0x4802a000,
                .pa_end         = 0x4802a000 + SZ_1K - 1,
@@ -54,7 +56,7 @@ struct omap_hwmod_addr_space omap2xxx_timer2_addrs[] = {
        { }
 };
-struct omap_hwmod_addr_space omap2xxx_timer3_addrs[] = {
+static struct omap_hwmod_addr_space omap2xxx_timer3_addrs[] = {
        {
                .pa_start       = 0x48078000,
                .pa_end         = 0x48078000 + SZ_1K - 1,
@@ -63,7 +65,7 @@ struct omap_hwmod_addr_space omap2xxx_timer3_addrs[] = {
        { }
 };
-struct omap_hwmod_addr_space omap2xxx_timer4_addrs[] = {
+static struct omap_hwmod_addr_space omap2xxx_timer4_addrs[] = {
        {
                .pa_start       = 0x4807a000,
                .pa_end         = 0x4807a000 + SZ_1K - 1,
@@ -72,7 +74,7 @@ struct omap_hwmod_addr_space omap2xxx_timer4_addrs[] = {
        { }
 };
-struct omap_hwmod_addr_space omap2xxx_timer5_addrs[] = {
+static struct omap_hwmod_addr_space omap2xxx_timer5_addrs[] = {
        {
                .pa_start       = 0x4807c000,
                .pa_end         = 0x4807c000 + SZ_1K - 1,
@@ -81,7 +83,7 @@ struct omap_hwmod_addr_space omap2xxx_timer5_addrs[] = {
        { }
 };
-struct omap_hwmod_addr_space omap2xxx_timer6_addrs[] = {
+static struct omap_hwmod_addr_space omap2xxx_timer6_addrs[] = {
        {
                .pa_start       = 0x4807e000,
                .pa_end         = 0x4807e000 + SZ_1K - 1,
@@ -90,7 +92,7 @@ struct omap_hwmod_addr_space omap2xxx_timer6_addrs[] = {
        { }
 };
-struct omap_hwmod_addr_space omap2xxx_timer7_addrs[] = {
+static struct omap_hwmod_addr_space omap2xxx_timer7_addrs[] = {
        {
                .pa_start       = 0x48080000,
                .pa_end         = 0x48080000 + SZ_1K - 1,
@@ -99,7 +101,7 @@ struct omap_hwmod_addr_space omap2xxx_timer7_addrs[] = {
        { }
 };
-struct omap_hwmod_addr_space omap2xxx_timer8_addrs[] = {
+static struct omap_hwmod_addr_space omap2xxx_timer8_addrs[] = {
        {
                .pa_start       = 0x48082000,
                .pa_end         = 0x48082000 + SZ_1K - 1,
@@ -108,7 +110,7 @@ struct omap_hwmod_addr_space omap2xxx_timer8_addrs[] = {
        { }
 };
-struct omap_hwmod_addr_space omap2xxx_timer9_addrs[] = {
+static struct omap_hwmod_addr_space omap2xxx_timer9_addrs[] = {
        {
                .pa_start       = 0x48084000,
                .pa_end         = 0x48084000 + SZ_1K - 1,
@@ -127,4 +129,246 @@ struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[] = {
        { }
 };
+/*
+ * Common interconnect data
+ */
+/* L3 -> L4_CORE interface */
+struct omap_hwmod_ocp_if omap2xxx_l3_main__l4_core = {
+        .master = &omap2xxx_l3_main_hwmod,
+        .slave  = &omap2xxx_l4_core_hwmod,
+        .user   = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* MPU -> L3 interface */
+struct omap_hwmod_ocp_if omap2xxx_mpu__l3_main = {
+        .master = &omap2xxx_mpu_hwmod,
+        .slave  = &omap2xxx_l3_main_hwmod,
+        .user   = OCP_USER_MPU,
+};
+/* DSS -> l3 */
+struct omap_hwmod_ocp_if omap2xxx_dss__l3 = {
+        .master         = &omap2xxx_dss_core_hwmod,
+        .slave          = &omap2xxx_l3_main_hwmod,
+        .fw = {
+                .omap2 = {
+                        .l3_perm_bit  = OMAP2_L3_CORE_FW_CONNID_DSS,
+                        .flags  = OMAP_FIREWALL_L3,
+                }
+        },
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* L4_CORE -> L4_WKUP interface */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__l4_wkup = {
+        .master = &omap2xxx_l4_core_hwmod,
+        .slave  = &omap2xxx_l4_wkup_hwmod,
+        .user   = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* L4 CORE -> UART1 interface */
+struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2xxx_uart1_hwmod,
+        .clk            = "uart1_ick",
+        .addr           = omap2xxx_uart1_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* L4 CORE -> UART2 interface */
+struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2xxx_uart2_hwmod,
+        .clk            = "uart2_ick",
+        .addr           = omap2xxx_uart2_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* L4 PER -> UART3 interface */
+struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2xxx_uart3_hwmod,
+        .clk            = "uart3_ick",
+        .addr           = omap2xxx_uart3_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4 core -> mcspi1 interface */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi1 = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2xxx_mcspi1_hwmod,
+        .clk            = "mcspi1_ick",
+        .addr           = omap2_mcspi1_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4 core -> mcspi2 interface */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi2 = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2xxx_mcspi2_hwmod,
+        .clk            = "mcspi2_ick",
+        .addr           = omap2_mcspi2_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_core -> timer2 */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__timer2 = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2xxx_timer2_hwmod,
+        .clk            = "gpt2_ick",
+        .addr           = omap2xxx_timer2_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_core -> timer3 */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__timer3 = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2xxx_timer3_hwmod,
+        .clk            = "gpt3_ick",
+        .addr           = omap2xxx_timer3_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_core -> timer4 */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__timer4 = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2xxx_timer4_hwmod,
+        .clk            = "gpt4_ick",
+        .addr           = omap2xxx_timer4_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_core -> timer5 */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__timer5 = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2xxx_timer5_hwmod,
+        .clk            = "gpt5_ick",
+        .addr           = omap2xxx_timer5_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_core -> timer6 */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__timer6 = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2xxx_timer6_hwmod,
+        .clk            = "gpt6_ick",
+        .addr           = omap2xxx_timer6_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_core -> timer7 */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__timer7 = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2xxx_timer7_hwmod,
+        .clk            = "gpt7_ick",
+        .addr           = omap2xxx_timer7_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_core -> timer8 */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__timer8 = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2xxx_timer8_hwmod,
+        .clk            = "gpt8_ick",
+        .addr           = omap2xxx_timer8_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_core -> timer9 */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__timer9 = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2xxx_timer9_hwmod,
+        .clk            = "gpt9_ick",
+        .addr           = omap2xxx_timer9_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_core -> timer10 */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__timer10 = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2xxx_timer10_hwmod,
+        .clk            = "gpt10_ick",
+        .addr           = omap2_timer10_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_core -> timer11 */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__timer11 = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2xxx_timer11_hwmod,
+        .clk            = "gpt11_ick",
+        .addr           = omap2_timer11_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_core -> timer12 */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__timer12 = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2xxx_timer12_hwmod,
+        .clk            = "gpt12_ick",
+        .addr           = omap2xxx_timer12_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_core -> dss */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__dss = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2xxx_dss_core_hwmod,
+        .clk            = "dss_ick",
+        .addr           = omap2_dss_addrs,
+        .fw = {
+                .omap2 = {
+                        .l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
+                        .flags  = OMAP_FIREWALL_L4,
+                }
+        },
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_core -> dss_dispc */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_dispc = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2xxx_dss_dispc_hwmod,
+        .clk            = "dss_ick",
+        .addr           = omap2_dss_dispc_addrs,
+        .fw = {
+                .omap2 = {
+                        .l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION,
+                        .flags  = OMAP_FIREWALL_L4,
+                }
+        },
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_core -> dss_rfbi */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2xxx_dss_rfbi_hwmod,
+        .clk            = "dss_ick",
+        .addr           = omap2_dss_rfbi_addrs,
+        .fw = {
+                .omap2 = {
+                        .l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
+                        .flags  = OMAP_FIREWALL_L4,
+                }
+        },
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_core -> dss_venc */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2xxx_dss_venc_hwmod,
+        .clk            = "dss_ick",
+        .addr           = omap2_dss_venc_addrs,
+        .fw = {
+                .omap2 = {
+                        .l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_VENC_REGION,
+                        .flags  = OMAP_FIREWALL_L4,
+                }
+        },
+        .flags          = OCPIF_SWSUP_IDLE,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
index 2a6729741b06..83eafd96ecaa 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
@@ -10,6 +10,7 @@
 */
 #include <plat/omap_hwmod.h>
 #include <plat/serial.h>
+#include <plat/gpio.h>
 #include <plat/dma.h>
 #include <plat/dmtimer.h>
 #include <plat/mcspi.h>
@@ -17,6 +18,8 @@
 #include <mach/irqs.h>
 #include "omap_hwmod_common_data.h"
+#include "cm-regbits-24xx.h"
+#include "prm-regbits-24xx.h"
 #include "wd_timer.h"
 struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[] = {
@@ -86,7 +89,8 @@ static struct omap_hwmod_class_sysconfig omap2xxx_wd_timer_sysc = {
 struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class = {
        .name           = "wd_timer",
        .sysc           = &omap2xxx_wd_timer_sysc,
-        .pre_shutdown   = &omap2_wd_timer_disable
+        .pre_shutdown   = &omap2_wd_timer_disable,
+        .reset          = &omap2_wd_timer_reset,
 };
 /*
@@ -170,3 +174,582 @@ struct omap_hwmod_class omap2xxx_mcspi_class = {
        .sysc   = &omap2xxx_mcspi_sysc,
        .rev    = OMAP2_MCSPI_REV,
 };
+/*
+ * IP blocks
+ */
+/* L3 */
+struct omap_hwmod omap2xxx_l3_main_hwmod = {
+        .name           = "l3_main",
+        .class          = &l3_hwmod_class,
+        .flags          = HWMOD_NO_IDLEST,
+};
+/* L4 CORE */
+struct omap_hwmod omap2xxx_l4_core_hwmod = {
+        .name           = "l4_core",
+        .class          = &l4_hwmod_class,
+        .flags          = HWMOD_NO_IDLEST,
+};
+/* L4 WKUP */
+struct omap_hwmod omap2xxx_l4_wkup_hwmod = {
+        .name           = "l4_wkup",
+        .class          = &l4_hwmod_class,
+        .flags          = HWMOD_NO_IDLEST,
+};
+/* MPU */
+struct omap_hwmod omap2xxx_mpu_hwmod = {
+        .name           = "mpu",
+        .class          = &mpu_hwmod_class,
+        .main_clk       = "mpu_ck",
+};
+/* IVA2 */
+struct omap_hwmod omap2xxx_iva_hwmod = {
+        .name           = "iva",
+        .class          = &iva_hwmod_class,
+};
+/* always-on timers dev attribute */
+static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
+        .timer_capability       = OMAP_TIMER_ALWON,
+};
+/* pwm timers dev attribute */
+static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
+        .timer_capability       = OMAP_TIMER_HAS_PWM,
+};
+/* timer1 */
+struct omap_hwmod omap2xxx_timer1_hwmod = {
+        .name           = "timer1",
+        .mpu_irqs       = omap2_timer1_mpu_irqs,
+        .main_clk       = "gpt1_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT1_SHIFT,
+                        .module_offs = WKUP_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
+                },
+        },
+        .dev_attr       = &capability_alwon_dev_attr,
+        .class          = &omap2xxx_timer_hwmod_class,
+};
+/* timer2 */
+struct omap_hwmod omap2xxx_timer2_hwmod = {
+        .name           = "timer2",
+        .mpu_irqs       = omap2_timer2_mpu_irqs,
+        .main_clk       = "gpt2_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT2_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
+                },
+        },
+        .dev_attr       = &capability_alwon_dev_attr,
+        .class          = &omap2xxx_timer_hwmod_class,
+};
+/* timer3 */
+struct omap_hwmod omap2xxx_timer3_hwmod = {
+        .name           = "timer3",
+        .mpu_irqs       = omap2_timer3_mpu_irqs,
+        .main_clk       = "gpt3_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT3_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
+                },
+        },
+        .dev_attr       = &capability_alwon_dev_attr,
+        .class          = &omap2xxx_timer_hwmod_class,
+};
+/* timer4 */
+struct omap_hwmod omap2xxx_timer4_hwmod = {
+        .name           = "timer4",
+        .mpu_irqs       = omap2_timer4_mpu_irqs,
+        .main_clk       = "gpt4_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT4_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
+                },
+        },
+        .dev_attr       = &capability_alwon_dev_attr,
+        .class          = &omap2xxx_timer_hwmod_class,
+};
+/* timer5 */
+struct omap_hwmod omap2xxx_timer5_hwmod = {
+        .name           = "timer5",
+        .mpu_irqs       = omap2_timer5_mpu_irqs,
+        .main_clk       = "gpt5_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT5_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
+                },
+        },
+        .dev_attr       = &capability_alwon_dev_attr,
+        .class          = &omap2xxx_timer_hwmod_class,
+};
+/* timer6 */
+struct omap_hwmod omap2xxx_timer6_hwmod = {
+        .name           = "timer6",
+        .mpu_irqs       = omap2_timer6_mpu_irqs,
+        .main_clk       = "gpt6_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT6_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
+                },
+        },
+        .dev_attr       = &capability_alwon_dev_attr,
+        .class          = &omap2xxx_timer_hwmod_class,
+};
+/* timer7 */
+struct omap_hwmod omap2xxx_timer7_hwmod = {
+        .name           = "timer7",
+        .mpu_irqs       = omap2_timer7_mpu_irqs,
+        .main_clk       = "gpt7_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT7_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
+                },
+        },
+        .dev_attr       = &capability_alwon_dev_attr,
+        .class          = &omap2xxx_timer_hwmod_class,
+};
+/* timer8 */
+struct omap_hwmod omap2xxx_timer8_hwmod = {
+        .name           = "timer8",
+        .mpu_irqs       = omap2_timer8_mpu_irqs,
+        .main_clk       = "gpt8_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT8_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
+                },
+        },
+        .dev_attr       = &capability_alwon_dev_attr,
+        .class          = &omap2xxx_timer_hwmod_class,
+};
+/* timer9 */
+struct omap_hwmod omap2xxx_timer9_hwmod = {
+        .name           = "timer9",
+        .mpu_irqs       = omap2_timer9_mpu_irqs,
+        .main_clk       = "gpt9_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT9_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
+                },
+        },
+        .dev_attr       = &capability_pwm_dev_attr,
+        .class          = &omap2xxx_timer_hwmod_class,
+};
+/* timer10 */
+struct omap_hwmod omap2xxx_timer10_hwmod = {
+        .name           = "timer10",
+        .mpu_irqs       = omap2_timer10_mpu_irqs,
+        .main_clk       = "gpt10_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT10_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
+                },
+        },
+        .dev_attr       = &capability_pwm_dev_attr,
+        .class          = &omap2xxx_timer_hwmod_class,
+};
+/* timer11 */
+struct omap_hwmod omap2xxx_timer11_hwmod = {
+        .name           = "timer11",
+        .mpu_irqs       = omap2_timer11_mpu_irqs,
+        .main_clk       = "gpt11_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT11_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
+                },
+        },
+        .dev_attr       = &capability_pwm_dev_attr,
+        .class          = &omap2xxx_timer_hwmod_class,
+};
+/* timer12 */
+struct omap_hwmod omap2xxx_timer12_hwmod = {
+        .name           = "timer12",
+        .mpu_irqs       = omap2xxx_timer12_mpu_irqs,
+        .main_clk       = "gpt12_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT12_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
+                },
+        },
+        .dev_attr       = &capability_pwm_dev_attr,
+        .class          = &omap2xxx_timer_hwmod_class,
+};
+/* wd_timer2 */
+struct omap_hwmod omap2xxx_wd_timer2_hwmod = {
+        .name           = "wd_timer2",
+        .class          = &omap2xxx_wd_timer_hwmod_class,
+        .main_clk       = "mpu_wdt_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
+                        .module_offs = WKUP_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
+                },
+        },
+};
+/* UART1 */
+struct omap_hwmod omap2xxx_uart1_hwmod = {
+        .name           = "uart1",
+        .mpu_irqs       = omap2_uart1_mpu_irqs,
+        .sdma_reqs      = omap2_uart1_sdma_reqs,
+        .main_clk       = "uart1_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_UART1_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
+                },
+        },
+        .class          = &omap2_uart_class,
+};
+/* UART2 */
+struct omap_hwmod omap2xxx_uart2_hwmod = {
+        .name           = "uart2",
+        .mpu_irqs       = omap2_uart2_mpu_irqs,
+        .sdma_reqs      = omap2_uart2_sdma_reqs,
+        .main_clk       = "uart2_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_UART2_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
+                },
+        },
+        .class          = &omap2_uart_class,
+};
+/* UART3 */
+struct omap_hwmod omap2xxx_uart3_hwmod = {
+        .name           = "uart3",
+        .mpu_irqs       = omap2_uart3_mpu_irqs,
+        .sdma_reqs      = omap2_uart3_sdma_reqs,
+        .main_clk       = "uart3_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 2,
+                        .module_bit = OMAP24XX_EN_UART3_SHIFT,
+                        .idlest_reg_id = 2,
+                        .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
+                },
+        },
+        .class          = &omap2_uart_class,
+};
+/* dss */
+static struct omap_hwmod_opt_clk dss_opt_clks[] = {
+        /*
+         * The DSS HW needs all DSS clocks enabled during reset. The dss_core
+         * driver does not use these clocks.
+         */
+        { .role = "tv_clk", .clk = "dss_54m_fck" },
+        { .role = "sys_clk", .clk = "dss2_fck" },
+};
+struct omap_hwmod omap2xxx_dss_core_hwmod = {
+        .name           = "dss_core",
+        .class          = &omap2_dss_hwmod_class,
+        .main_clk       = "dss1_fck", /* instead of dss_fck */
+        .sdma_reqs      = omap2xxx_dss_sdma_chs,
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_DSS1_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
+                },
+        },
+        .opt_clks       = dss_opt_clks,
+        .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
+        .flags          = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+};
+struct omap_hwmod omap2xxx_dss_dispc_hwmod = {
+        .name           = "dss_dispc",
+        .class          = &omap2_dispc_hwmod_class,
+        .mpu_irqs       = omap2_dispc_irqs,
+        .main_clk       = "dss1_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_DSS1_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
+                },
+        },
+        .flags          = HWMOD_NO_IDLEST,
+        .dev_attr       = &omap2_3_dss_dispc_dev_attr
+};
+static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
+        { .role = "ick", .clk = "dss_ick" },
+};
+struct omap_hwmod omap2xxx_dss_rfbi_hwmod = {
+        .name           = "dss_rfbi",
+        .class          = &omap2_rfbi_hwmod_class,
+        .main_clk       = "dss1_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_DSS1_SHIFT,
+                        .module_offs = CORE_MOD,
+                },
+        },
+        .opt_clks       = dss_rfbi_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
+        .flags          = HWMOD_NO_IDLEST,
+};
+struct omap_hwmod omap2xxx_dss_venc_hwmod = {
+        .name           = "dss_venc",
+        .class          = &omap2_venc_hwmod_class,
+        .main_clk       = "dss_54m_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_DSS1_SHIFT,
+                        .module_offs = CORE_MOD,
+                },
+        },
+        .flags          = HWMOD_NO_IDLEST,
+};
+/* gpio dev_attr */
+struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr = {
+        .bank_width = 32,
+        .dbck_flag = false,
+};
+/* gpio1 */
+struct omap_hwmod omap2xxx_gpio1_hwmod = {
+        .name           = "gpio1",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .mpu_irqs       = omap2_gpio1_irqs,
+        .main_clk       = "gpios_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
+                        .module_offs = WKUP_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
+                },
+        },
+        .class          = &omap2xxx_gpio_hwmod_class,
+        .dev_attr       = &omap2xxx_gpio_dev_attr,
+};
+/* gpio2 */
+struct omap_hwmod omap2xxx_gpio2_hwmod = {
+        .name           = "gpio2",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .mpu_irqs       = omap2_gpio2_irqs,
+        .main_clk       = "gpios_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
+                        .module_offs = WKUP_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
+                },
+        },
+        .class          = &omap2xxx_gpio_hwmod_class,
+        .dev_attr       = &omap2xxx_gpio_dev_attr,
+};
+/* gpio3 */
+struct omap_hwmod omap2xxx_gpio3_hwmod = {
+        .name           = "gpio3",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .mpu_irqs       = omap2_gpio3_irqs,
+        .main_clk       = "gpios_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
+                        .module_offs = WKUP_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
+                },
+        },
+        .class          = &omap2xxx_gpio_hwmod_class,
+        .dev_attr       = &omap2xxx_gpio_dev_attr,
+};
+/* gpio4 */
+struct omap_hwmod omap2xxx_gpio4_hwmod = {
+        .name           = "gpio4",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .mpu_irqs       = omap2_gpio4_irqs,
+        .main_clk       = "gpios_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
+                        .module_offs = WKUP_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
+                },
+        },
+        .class          = &omap2xxx_gpio_hwmod_class,
+        .dev_attr       = &omap2xxx_gpio_dev_attr,
+};
+/* mcspi1 */
+static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
+        .num_chipselect = 4,
+};
+struct omap_hwmod omap2xxx_mcspi1_hwmod = {
+        .name           = "mcspi1",
+        .mpu_irqs       = omap2_mcspi1_mpu_irqs,
+        .sdma_reqs      = omap2_mcspi1_sdma_reqs,
+        .main_clk       = "mcspi1_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
+                },
+        },
+        .class          = &omap2xxx_mcspi_class,
+        .dev_attr       = &omap_mcspi1_dev_attr,
+};
+/* mcspi2 */
+static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
+        .num_chipselect = 2,
+};
+struct omap_hwmod omap2xxx_mcspi2_hwmod = {
+        .name           = "mcspi2",
+        .mpu_irqs       = omap2_mcspi2_mpu_irqs,
+        .sdma_reqs      = omap2_mcspi2_sdma_reqs,
+        .main_clk       = "mcspi2_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
+                },
+        },
+        .class          = &omap2xxx_mcspi_class,
+        .dev_attr       = &omap_mcspi2_dev_attr,
+};
+static struct omap_hwmod_class omap2xxx_counter_hwmod_class = {
+        .name   = "counter",
+};
+struct omap_hwmod omap2xxx_counter_32k_hwmod = {
+        .name           = "counter_32k",
+        .main_clk       = "func_32k_ck",
+        .prcm           = {
+                .omap2  = {
+                        .module_offs = WKUP_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_ST_32KSYNC_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_32KSYNC_SHIFT,
+                },
+        },
+        .class          = &omap2xxx_counter_hwmod_class,
+};
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 34b9766d1d23..fd48797fa95a 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -2,6 +2,7 @@
 * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
 *
 * Copyright (C) 2009-2011 Nokia Corporation
+ * Copyright (C) 2012 Texas Instruments, Inc.
 * Paul Walmsley
 *
 * This program is free software; you can redistribute it and/or modify
@@ -38,491 +39,56 @@
 /*
 * OMAP3xxx hardware module integration data
 *
- * ALl of the data in this section should be autogeneratable from the
+ * All of the data in this section should be autogeneratable from the
 * TI hardware database or other technical documentation.  Data that
 * is driver-specific or driver-kernel integration-specific belongs
 * elsewhere.
 */
-static struct omap_hwmod omap3xxx_mpu_hwmod;
+/*
-static struct omap_hwmod omap3xxx_iva_hwmod;
+ * IP blocks
-static struct omap_hwmod omap3xxx_l3_main_hwmod;
+ */
-static struct omap_hwmod omap3xxx_l4_core_hwmod;
-static struct omap_hwmod omap3xxx_l4_per_hwmod;
-static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
-static struct omap_hwmod omap3430es1_dss_core_hwmod;
-static struct omap_hwmod omap3xxx_dss_core_hwmod;
-static struct omap_hwmod omap3xxx_dss_dispc_hwmod;
-static struct omap_hwmod omap3xxx_dss_dsi1_hwmod;
-static struct omap_hwmod omap3xxx_dss_rfbi_hwmod;
-static struct omap_hwmod omap3xxx_dss_venc_hwmod;
-static struct omap_hwmod omap3xxx_i2c1_hwmod;
-static struct omap_hwmod omap3xxx_i2c2_hwmod;
-static struct omap_hwmod omap3xxx_i2c3_hwmod;
-static struct omap_hwmod omap3xxx_gpio1_hwmod;
-static struct omap_hwmod omap3xxx_gpio2_hwmod;
-static struct omap_hwmod omap3xxx_gpio3_hwmod;
-static struct omap_hwmod omap3xxx_gpio4_hwmod;
-static struct omap_hwmod omap3xxx_gpio5_hwmod;
-static struct omap_hwmod omap3xxx_gpio6_hwmod;
-static struct omap_hwmod omap34xx_sr1_hwmod;
-static struct omap_hwmod omap34xx_sr2_hwmod;
-static struct omap_hwmod omap34xx_mcspi1;
-static struct omap_hwmod omap34xx_mcspi2;
-static struct omap_hwmod omap34xx_mcspi3;
-static struct omap_hwmod omap34xx_mcspi4;
-static struct omap_hwmod omap3xxx_mmc1_hwmod;
-static struct omap_hwmod omap3xxx_mmc2_hwmod;
-static struct omap_hwmod omap3xxx_mmc3_hwmod;
-static struct omap_hwmod am35xx_usbhsotg_hwmod;
-static struct omap_hwmod omap3xxx_dma_system_hwmod;
-static struct omap_hwmod omap3xxx_mcbsp1_hwmod;
-static struct omap_hwmod omap3xxx_mcbsp2_hwmod;
-static struct omap_hwmod omap3xxx_mcbsp3_hwmod;
-static struct omap_hwmod omap3xxx_mcbsp4_hwmod;
-static struct omap_hwmod omap3xxx_mcbsp5_hwmod;
-static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod;
-static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod;
-static struct omap_hwmod omap3xxx_usb_host_hs_hwmod;
-static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod;
-/* L3 -> L4_CORE interface */
-static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
-        .master = &omap3xxx_l3_main_hwmod,
-        .slave  = &omap3xxx_l4_core_hwmod,
-        .user   = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* L3 -> L4_PER interface */
-static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
-        .master = &omap3xxx_l3_main_hwmod,
-        .slave  = &omap3xxx_l4_per_hwmod,
-        .user   = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* L3 taret configuration and error log registers */
+/* L3 */
 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
        { .irq = INT_34XX_L3_DBG_IRQ },
        { .irq = INT_34XX_L3_APP_IRQ },
        { .irq = -1 }
 };
-static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
-        {
-                .pa_start       = 0x68000000,
-                .pa_end         = 0x6800ffff,
-                .flags          = ADDR_TYPE_RT,
-        },
-        { }
-};
-/* MPU -> L3 interface */
-static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
-        .master   = &omap3xxx_mpu_hwmod,
-        .slave    = &omap3xxx_l3_main_hwmod,
-        .addr     = omap3xxx_l3_main_addrs,
-        .user   = OCP_USER_MPU,
-};
-/* Slave interfaces on the L3 interconnect */
-static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = {
-        &omap3xxx_mpu__l3_main,
-};
-/* DSS -> l3 */
-static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
-        .master         = &omap3xxx_dss_core_hwmod,
-        .slave          = &omap3xxx_l3_main_hwmod,
-        .fw = {
-                .omap2 = {
-                        .l3_perm_bit  = OMAP3_L3_CORE_FW_INIT_ID_DSS,
-                        .flags  = OMAP_FIREWALL_L3,
-                }
-        },
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* Master interfaces on the L3 interconnect */
-static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
-        &omap3xxx_l3_main__l4_core,
-        &omap3xxx_l3_main__l4_per,
-};
-/* L3 */
 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
        .name           = "l3_main",
        .class          = &l3_hwmod_class,
        .mpu_irqs       = omap3xxx_l3_main_irqs,
-        .masters        = omap3xxx_l3_main_masters,
-        .masters_cnt    = ARRAY_SIZE(omap3xxx_l3_main_masters),
-        .slaves         = omap3xxx_l3_main_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_l3_main_slaves),
        .flags          = HWMOD_NO_IDLEST,
 };
-static struct omap_hwmod omap3xxx_l4_wkup_hwmod;
-static struct omap_hwmod omap3xxx_uart1_hwmod;
-static struct omap_hwmod omap3xxx_uart2_hwmod;
-static struct omap_hwmod omap3xxx_uart3_hwmod;
-static struct omap_hwmod omap3xxx_uart4_hwmod;
-static struct omap_hwmod am35xx_uart4_hwmod;
-static struct omap_hwmod omap3xxx_usbhsotg_hwmod;
-/* l3_core -> usbhsotg interface */
-static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
-        .master         = &omap3xxx_usbhsotg_hwmod,
-        .slave          = &omap3xxx_l3_main_hwmod,
-        .clk            = "core_l3_ick",
-        .user           = OCP_USER_MPU,
-};
-/* l3_core -> am35xx_usbhsotg interface */
-static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
-        .master         = &am35xx_usbhsotg_hwmod,
-        .slave          = &omap3xxx_l3_main_hwmod,
-        .clk            = "core_l3_ick",
-        .user           = OCP_USER_MPU,
-};
-/* L4_CORE -> L4_WKUP interface */
-static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
-        .master = &omap3xxx_l4_core_hwmod,
-        .slave  = &omap3xxx_l4_wkup_hwmod,
-        .user   = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* L4 CORE -> MMC1 interface */
-static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1 = {
-        .master         = &omap3xxx_l4_core_hwmod,
-        .slave          = &omap3xxx_mmc1_hwmod,
-        .clk            = "mmchs1_ick",
-        .addr           = omap2430_mmc1_addr_space,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-        .flags          = OMAP_FIREWALL_L4
-};
-/* L4 CORE -> MMC2 interface */
-static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2 = {
-        .master         = &omap3xxx_l4_core_hwmod,
-        .slave          = &omap3xxx_mmc2_hwmod,
-        .clk            = "mmchs2_ick",
-        .addr           = omap2430_mmc2_addr_space,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-        .flags          = OMAP_FIREWALL_L4
-};
-/* L4 CORE -> MMC3 interface */
-static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
-        {
-                .pa_start       = 0x480ad000,
-                .pa_end         = 0x480ad1ff,
-                .flags          = ADDR_TYPE_RT,
-        },
-        { }
-};
-static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
-        .master         = &omap3xxx_l4_core_hwmod,
-        .slave          = &omap3xxx_mmc3_hwmod,
-        .clk            = "mmchs3_ick",
-        .addr           = omap3xxx_mmc3_addr_space,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-        .flags          = OMAP_FIREWALL_L4
-};
-/* L4 CORE -> UART1 interface */
-static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
-        {
-                .pa_start       = OMAP3_UART1_BASE,
-                .pa_end         = OMAP3_UART1_BASE + SZ_8K - 1,
-                .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
-        },
-        { }
-};
-static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
-        .master         = &omap3xxx_l4_core_hwmod,
-        .slave          = &omap3xxx_uart1_hwmod,
-        .clk            = "uart1_ick",
-        .addr           = omap3xxx_uart1_addr_space,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* L4 CORE -> UART2 interface */
-static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
-        {
-                .pa_start       = OMAP3_UART2_BASE,
-                .pa_end         = OMAP3_UART2_BASE + SZ_1K - 1,
-                .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
-        },
-        { }
-};
-static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
-        .master         = &omap3xxx_l4_core_hwmod,
-        .slave          = &omap3xxx_uart2_hwmod,
-        .clk            = "uart2_ick",
-        .addr           = omap3xxx_uart2_addr_space,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* L4 PER -> UART3 interface */
-static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
-        {
-                .pa_start       = OMAP3_UART3_BASE,
-                .pa_end         = OMAP3_UART3_BASE + SZ_1K - 1,
-                .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
-        },
-        { }
-};
-static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
-        .master         = &omap3xxx_l4_per_hwmod,
-        .slave          = &omap3xxx_uart3_hwmod,
-        .clk            = "uart3_ick",
-        .addr           = omap3xxx_uart3_addr_space,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* L4 PER -> UART4 interface */
-static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = {
-        {
-                .pa_start       = OMAP3_UART4_BASE,
-                .pa_end         = OMAP3_UART4_BASE + SZ_1K - 1,
-                .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
-        },
-        { }
-};
-static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
-        .master         = &omap3xxx_l4_per_hwmod,
-        .slave          = &omap3xxx_uart4_hwmod,
-        .clk            = "uart4_ick",
-        .addr           = omap3xxx_uart4_addr_space,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* AM35xx: L4 CORE -> UART4 interface */
-static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = {
-        {
-                .pa_start       = OMAP3_UART4_AM35XX_BASE,
-                .pa_end         = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1,
-                .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
-        },
-};
-static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
-        .master         = &omap3xxx_l4_core_hwmod,
-        .slave          = &am35xx_uart4_hwmod,
-        .clk            = "uart4_ick",
-        .addr           = am35xx_uart4_addr_space,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* L4 CORE -> I2C1 interface */
-static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
-        .master         = &omap3xxx_l4_core_hwmod,
-        .slave          = &omap3xxx_i2c1_hwmod,
-        .clk            = "i2c1_ick",
-        .addr           = omap2_i2c1_addr_space,
-        .fw = {
-                .omap2 = {
-                        .l4_fw_region  = OMAP3_L4_CORE_FW_I2C1_REGION,
-                        .l4_prot_group = 7,
-                        .flags  = OMAP_FIREWALL_L4,
-                }
-        },
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* L4 CORE -> I2C2 interface */
-static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
-        .master         = &omap3xxx_l4_core_hwmod,
-        .slave          = &omap3xxx_i2c2_hwmod,
-        .clk            = "i2c2_ick",
-        .addr           = omap2_i2c2_addr_space,
-        .fw = {
-                .omap2 = {
-                        .l4_fw_region  = OMAP3_L4_CORE_FW_I2C2_REGION,
-                        .l4_prot_group = 7,
-                        .flags = OMAP_FIREWALL_L4,
-                }
-        },
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* L4 CORE -> I2C3 interface */
-static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
-        {
-                .pa_start       = 0x48060000,
-                .pa_end         = 0x48060000 + SZ_128 - 1,
-                .flags          = ADDR_TYPE_RT,
-        },
-        { }
-};
-static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
-        .master         = &omap3xxx_l4_core_hwmod,
-        .slave          = &omap3xxx_i2c3_hwmod,
-        .clk            = "i2c3_ick",
-        .addr           = omap3xxx_i2c3_addr_space,
-        .fw = {
-                .omap2 = {
-                        .l4_fw_region  = OMAP3_L4_CORE_FW_I2C3_REGION,
-                        .l4_prot_group = 7,
-                        .flags = OMAP_FIREWALL_L4,
-                }
-        },
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
-        { .irq = 18},
-        { .irq = -1 }
-};
-static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
-        { .irq = 19},
-        { .irq = -1 }
-};
-/* L4 CORE -> SR1 interface */
-static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
-        {
-                .pa_start       = OMAP34XX_SR1_BASE,
-                .pa_end         = OMAP34XX_SR1_BASE + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT,
-        },
-        { }
-};
-static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = {
-        .master         = &omap3xxx_l4_core_hwmod,
-        .slave          = &omap34xx_sr1_hwmod,
-        .clk            = "sr_l4_ick",
-        .addr           = omap3_sr1_addr_space,
-        .user           = OCP_USER_MPU,
-};
-/* L4 CORE -> SR1 interface */
-static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
-        {
-                .pa_start       = OMAP34XX_SR2_BASE,
-                .pa_end         = OMAP34XX_SR2_BASE + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT,
-        },
-        { }
-};
-static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = {
-        .master         = &omap3xxx_l4_core_hwmod,
-        .slave          = &omap34xx_sr2_hwmod,
-        .clk            = "sr_l4_ick",
-        .addr           = omap3_sr2_addr_space,
-        .user           = OCP_USER_MPU,
-};
-/*
-* usbhsotg interface data
-*/
-static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
-        {
-                .pa_start       = OMAP34XX_HSUSB_OTG_BASE,
-                .pa_end         = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_core -> usbhsotg  */
-static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
-        .master         = &omap3xxx_l4_core_hwmod,
-        .slave          = &omap3xxx_usbhsotg_hwmod,
-        .clk            = "l4_ick",
-        .addr           = omap3xxx_usbhsotg_addrs,
-        .user           = OCP_USER_MPU,
-};
-static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_masters[] = {
-        &omap3xxx_usbhsotg__l3,
-};
-static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_slaves[] = {
-        &omap3xxx_l4_core__usbhsotg,
-};
-static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
-        {
-                .pa_start       = AM35XX_IPSS_USBOTGSS_BASE,
-                .pa_end         = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_core -> usbhsotg  */
-static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
-        .master         = &omap3xxx_l4_core_hwmod,
-        .slave          = &am35xx_usbhsotg_hwmod,
-        .clk            = "l4_ick",
-        .addr           = am35xx_usbhsotg_addrs,
-        .user           = OCP_USER_MPU,
-};
-static struct omap_hwmod_ocp_if *am35xx_usbhsotg_masters[] = {
-        &am35xx_usbhsotg__l3,
-};
-static struct omap_hwmod_ocp_if *am35xx_usbhsotg_slaves[] = {
-        &am35xx_l4_core__usbhsotg,
-};
-/* Slave interfaces on the L4_CORE interconnect */
-static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
-        &omap3xxx_l3_main__l4_core,
-};
 /* L4 CORE */
 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
        .name           = "l4_core",
        .class          = &l4_hwmod_class,
-        .slaves         = omap3xxx_l4_core_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_core_slaves),
        .flags          = HWMOD_NO_IDLEST,
 };
-/* Slave interfaces on the L4_PER interconnect */
-static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = {
-        &omap3xxx_l3_main__l4_per,
-};
 /* L4 PER */
 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
        .name           = "l4_per",
        .class          = &l4_hwmod_class,
-        .slaves         = omap3xxx_l4_per_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_per_slaves),
        .flags          = HWMOD_NO_IDLEST,
 };
-/* Slave interfaces on the L4_WKUP interconnect */
-static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = {
-        &omap3xxx_l4_core__l4_wkup,
-};
 /* L4 WKUP */
 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
        .name           = "l4_wkup",
        .class          = &l4_hwmod_class,
-        .slaves         = omap3xxx_l4_wkup_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_wkup_slaves),
        .flags          = HWMOD_NO_IDLEST,
 };
-/* Master interfaces on the MPU device */
+/* L4 SEC */
-static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = {
+static struct omap_hwmod omap3xxx_l4_sec_hwmod = {
-        &omap3xxx_mpu__l3_main,
+        .name           = "l4_sec",
+        .class          = &l4_hwmod_class,
+        .flags          = HWMOD_NO_IDLEST,
 };
 /* MPU */
@@ -530,35 +96,22 @@ static struct omap_hwmod omap3xxx_mpu_hwmod = {
        .name           = "mpu",
        .class          = &mpu_hwmod_class,
        .main_clk       = "arm_fck",
-        .masters        = omap3xxx_mpu_masters,
-        .masters_cnt    = ARRAY_SIZE(omap3xxx_mpu_masters),
 };
-/*
+/* IVA2 (IVA2) */
- * IVA2_2 interface data
+static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = {
- */
+        { .name = "logic", .rst_shift = 0 },
+        { .name = "seq0", .rst_shift = 1 },
-/* IVA2 <- L3 interface */
+        { .name = "seq1", .rst_shift = 2 },
-static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
-        .master         = &omap3xxx_l3_main_hwmod,
-        .slave          = &omap3xxx_iva_hwmod,
-        .clk            = "iva2_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = {
-        &omap3xxx_l3__iva,
-};
-/*
- * IVA2 (IVA2)
- */
 static struct omap_hwmod omap3xxx_iva_hwmod = {
        .name           = "iva",
        .class          = &iva_hwmod_class,
-        .masters        = omap3xxx_iva_masters,
+        .clkdm_name     = "iva2_clkdm",
-        .masters_cnt    = ARRAY_SIZE(omap3xxx_iva_masters),
+        .rst_lines      = omap3xxx_iva_resets,
+        .rst_lines_cnt  = ARRAY_SIZE(omap3xxx_iva_resets),
+        .main_clk       = "iva2_ck",
 };
 /* timer class */
@@ -597,46 +150,20 @@ static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
 /* secure timers dev attribute */
 static struct omap_timer_capability_dev_attr capability_secure_dev_attr = {
-        .timer_capability       = OMAP_TIMER_SECURE,
+        .timer_capability       = OMAP_TIMER_SECURE,
 };
 /* always-on timers dev attribute */
 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
-        .timer_capability       = OMAP_TIMER_ALWON,
+        .timer_capability       = OMAP_TIMER_ALWON,
 };
 /* pwm timers dev attribute */
 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
-        .timer_capability       = OMAP_TIMER_HAS_PWM,
+        .timer_capability       = OMAP_TIMER_HAS_PWM,
 };
 /* timer1 */
-static struct omap_hwmod omap3xxx_timer1_hwmod;
-static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
-        {
-                .pa_start       = 0x48318000,
-                .pa_end         = 0x48318000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_wkup -> timer1 */
-static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
-        .master         = &omap3xxx_l4_wkup_hwmod,
-        .slave          = &omap3xxx_timer1_hwmod,
-        .clk            = "gpt1_ick",
-        .addr           = omap3xxx_timer1_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* timer1 slave port */
-static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = {
-        &omap3xxx_l4_wkup__timer1,
-};
-/* timer1 hwmod */
 static struct omap_hwmod omap3xxx_timer1_hwmod = {
        .name           = "timer1",
        .mpu_irqs       = omap2_timer1_mpu_irqs,
@@ -651,38 +178,10 @@ static struct omap_hwmod omap3xxx_timer1_hwmod = {
                },
        },
        .dev_attr       = &capability_alwon_dev_attr,
-        .slaves         = omap3xxx_timer1_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer1_slaves),
        .class          = &omap3xxx_timer_1ms_hwmod_class,
 };
 /* timer2 */
-static struct omap_hwmod omap3xxx_timer2_hwmod;
-static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
-        {
-                .pa_start       = 0x49032000,
-                .pa_end         = 0x49032000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_per -> timer2 */
-static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
-        .master         = &omap3xxx_l4_per_hwmod,
-        .slave          = &omap3xxx_timer2_hwmod,
-        .clk            = "gpt2_ick",
-        .addr           = omap3xxx_timer2_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* timer2 slave port */
-static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = {
-        &omap3xxx_l4_per__timer2,
-};
-/* timer2 hwmod */
 static struct omap_hwmod omap3xxx_timer2_hwmod = {
        .name           = "timer2",
        .mpu_irqs       = omap2_timer2_mpu_irqs,
@@ -697,38 +196,10 @@ static struct omap_hwmod omap3xxx_timer2_hwmod = {
                },
        },
        .dev_attr       = &capability_alwon_dev_attr,
-        .slaves         = omap3xxx_timer2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer2_slaves),
        .class          = &omap3xxx_timer_1ms_hwmod_class,
 };
 /* timer3 */
-static struct omap_hwmod omap3xxx_timer3_hwmod;
-static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
-        {
-                .pa_start       = 0x49034000,
-                .pa_end         = 0x49034000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_per -> timer3 */
-static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
-        .master         = &omap3xxx_l4_per_hwmod,
-        .slave          = &omap3xxx_timer3_hwmod,
-        .clk            = "gpt3_ick",
-        .addr           = omap3xxx_timer3_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* timer3 slave port */
-static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = {
-        &omap3xxx_l4_per__timer3,
-};
-/* timer3 hwmod */
 static struct omap_hwmod omap3xxx_timer3_hwmod = {
        .name           = "timer3",
        .mpu_irqs       = omap2_timer3_mpu_irqs,
@@ -743,38 +214,10 @@ static struct omap_hwmod omap3xxx_timer3_hwmod = {
                },
        },
        .dev_attr       = &capability_alwon_dev_attr,
-        .slaves         = omap3xxx_timer3_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer3_slaves),
        .class          = &omap3xxx_timer_hwmod_class,
 };
 /* timer4 */
-static struct omap_hwmod omap3xxx_timer4_hwmod;
-static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
-        {
-                .pa_start       = 0x49036000,
-                .pa_end         = 0x49036000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_per -> timer4 */
-static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
-        .master         = &omap3xxx_l4_per_hwmod,
-        .slave          = &omap3xxx_timer4_hwmod,
-        .clk            = "gpt4_ick",
-        .addr           = omap3xxx_timer4_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* timer4 slave port */
-static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = {
-        &omap3xxx_l4_per__timer4,
-};
-/* timer4 hwmod */
 static struct omap_hwmod omap3xxx_timer4_hwmod = {
        .name           = "timer4",
        .mpu_irqs       = omap2_timer4_mpu_irqs,
@@ -789,38 +232,10 @@ static struct omap_hwmod omap3xxx_timer4_hwmod = {
                },
        },
        .dev_attr       = &capability_alwon_dev_attr,
-        .slaves         = omap3xxx_timer4_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer4_slaves),
        .class          = &omap3xxx_timer_hwmod_class,
 };
 /* timer5 */
-static struct omap_hwmod omap3xxx_timer5_hwmod;
-static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
-        {
-                .pa_start       = 0x49038000,
-                .pa_end         = 0x49038000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_per -> timer5 */
-static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
-        .master         = &omap3xxx_l4_per_hwmod,
-        .slave          = &omap3xxx_timer5_hwmod,
-        .clk            = "gpt5_ick",
-        .addr           = omap3xxx_timer5_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* timer5 slave port */
-static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = {
-        &omap3xxx_l4_per__timer5,
-};
-/* timer5 hwmod */
 static struct omap_hwmod omap3xxx_timer5_hwmod = {
        .name           = "timer5",
        .mpu_irqs       = omap2_timer5_mpu_irqs,
@@ -835,38 +250,10 @@ static struct omap_hwmod omap3xxx_timer5_hwmod = {
                },
        },
        .dev_attr       = &capability_alwon_dev_attr,
-        .slaves         = omap3xxx_timer5_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer5_slaves),
        .class          = &omap3xxx_timer_hwmod_class,
 };
 /* timer6 */
-static struct omap_hwmod omap3xxx_timer6_hwmod;
-static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
-        {
-                .pa_start       = 0x4903A000,
-                .pa_end         = 0x4903A000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_per -> timer6 */
-static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
-        .master         = &omap3xxx_l4_per_hwmod,
-        .slave          = &omap3xxx_timer6_hwmod,
-        .clk            = "gpt6_ick",
-        .addr           = omap3xxx_timer6_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* timer6 slave port */
-static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = {
-        &omap3xxx_l4_per__timer6,
-};
-/* timer6 hwmod */
 static struct omap_hwmod omap3xxx_timer6_hwmod = {
        .name           = "timer6",
        .mpu_irqs       = omap2_timer6_mpu_irqs,
@@ -881,38 +268,10 @@ static struct omap_hwmod omap3xxx_timer6_hwmod = {
                },
        },
        .dev_attr       = &capability_alwon_dev_attr,
-        .slaves         = omap3xxx_timer6_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer6_slaves),
        .class          = &omap3xxx_timer_hwmod_class,
 };
 /* timer7 */
-static struct omap_hwmod omap3xxx_timer7_hwmod;
-static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
-        {
-                .pa_start       = 0x4903C000,
-                .pa_end         = 0x4903C000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_per -> timer7 */
-static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
-        .master         = &omap3xxx_l4_per_hwmod,
-        .slave          = &omap3xxx_timer7_hwmod,
-        .clk            = "gpt7_ick",
-        .addr           = omap3xxx_timer7_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* timer7 slave port */
-static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = {
-        &omap3xxx_l4_per__timer7,
-};
-/* timer7 hwmod */
 static struct omap_hwmod omap3xxx_timer7_hwmod = {
        .name           = "timer7",
        .mpu_irqs       = omap2_timer7_mpu_irqs,
@@ -927,38 +286,10 @@ static struct omap_hwmod omap3xxx_timer7_hwmod = {
                },
        },
        .dev_attr       = &capability_alwon_dev_attr,
-        .slaves         = omap3xxx_timer7_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer7_slaves),
        .class          = &omap3xxx_timer_hwmod_class,
 };
 /* timer8 */
-static struct omap_hwmod omap3xxx_timer8_hwmod;
-static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
-        {
-                .pa_start       = 0x4903E000,
-                .pa_end         = 0x4903E000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_per -> timer8 */
-static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
-        .master         = &omap3xxx_l4_per_hwmod,
-        .slave          = &omap3xxx_timer8_hwmod,
-        .clk            = "gpt8_ick",
-        .addr           = omap3xxx_timer8_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* timer8 slave port */
-static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = {
-        &omap3xxx_l4_per__timer8,
-};
-/* timer8 hwmod */
 static struct omap_hwmod omap3xxx_timer8_hwmod = {
        .name           = "timer8",
        .mpu_irqs       = omap2_timer8_mpu_irqs,
@@ -973,38 +304,10 @@ static struct omap_hwmod omap3xxx_timer8_hwmod = {
                },
        },
        .dev_attr       = &capability_pwm_dev_attr,
-        .slaves         = omap3xxx_timer8_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer8_slaves),
        .class          = &omap3xxx_timer_hwmod_class,
 };
 /* timer9 */
-static struct omap_hwmod omap3xxx_timer9_hwmod;
-static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
-        {
-                .pa_start       = 0x49040000,
-                .pa_end         = 0x49040000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_per -> timer9 */
-static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
-        .master         = &omap3xxx_l4_per_hwmod,
-        .slave          = &omap3xxx_timer9_hwmod,
-        .clk            = "gpt9_ick",
-        .addr           = omap3xxx_timer9_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* timer9 slave port */
-static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = {
-        &omap3xxx_l4_per__timer9,
-};
-/* timer9 hwmod */
 static struct omap_hwmod omap3xxx_timer9_hwmod = {
        .name           = "timer9",
        .mpu_irqs       = omap2_timer9_mpu_irqs,
@@ -1019,29 +322,10 @@ static struct omap_hwmod omap3xxx_timer9_hwmod = {
                },
        },
        .dev_attr       = &capability_pwm_dev_attr,
-        .slaves         = omap3xxx_timer9_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer9_slaves),
        .class          = &omap3xxx_timer_hwmod_class,
 };
 /* timer10 */
-static struct omap_hwmod omap3xxx_timer10_hwmod;
-/* l4_core -> timer10 */
-static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
-        .master         = &omap3xxx_l4_core_hwmod,
-        .slave          = &omap3xxx_timer10_hwmod,
-        .clk            = "gpt10_ick",
-        .addr           = omap2_timer10_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* timer10 slave port */
-static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = {
-        &omap3xxx_l4_core__timer10,
-};
-/* timer10 hwmod */
 static struct omap_hwmod omap3xxx_timer10_hwmod = {
        .name           = "timer10",
        .mpu_irqs       = omap2_timer10_mpu_irqs,
@@ -1056,29 +340,10 @@ static struct omap_hwmod omap3xxx_timer10_hwmod = {
                },
        },
        .dev_attr       = &capability_pwm_dev_attr,
-        .slaves         = omap3xxx_timer10_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer10_slaves),
        .class          = &omap3xxx_timer_1ms_hwmod_class,
 };
 /* timer11 */
-static struct omap_hwmod omap3xxx_timer11_hwmod;
-/* l4_core -> timer11 */
-static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
-        .master         = &omap3xxx_l4_core_hwmod,
-        .slave          = &omap3xxx_timer11_hwmod,
-        .clk            = "gpt11_ick",
-        .addr           = omap2_timer11_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* timer11 slave port */
-static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = {
-        &omap3xxx_l4_core__timer11,
-};
-/* timer11 hwmod */
 static struct omap_hwmod omap3xxx_timer11_hwmod = {
        .name           = "timer11",
        .mpu_irqs       = omap2_timer11_mpu_irqs,
@@ -1093,42 +358,15 @@ static struct omap_hwmod omap3xxx_timer11_hwmod = {
                },
        },
        .dev_attr       = &capability_pwm_dev_attr,
-        .slaves         = omap3xxx_timer11_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer11_slaves),
        .class          = &omap3xxx_timer_hwmod_class,
 };
-/* timer12*/
+/* timer12 */
-static struct omap_hwmod omap3xxx_timer12_hwmod;
 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
        { .irq = 95, },
        { .irq = -1 }
 };
-static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
-        {
-                .pa_start       = 0x48304000,
-                .pa_end         = 0x48304000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_core -> timer12 */
-static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer12 = {
-        .master         = &omap3xxx_l4_core_hwmod,
-        .slave          = &omap3xxx_timer12_hwmod,
-        .clk            = "gpt12_ick",
-        .addr           = omap3xxx_timer12_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* timer12 slave port */
-static struct omap_hwmod_ocp_if *omap3xxx_timer12_slaves[] = {
-        &omap3xxx_l4_core__timer12,
-};
-/* timer12 hwmod */
 static struct omap_hwmod omap3xxx_timer12_hwmod = {
        .name           = "timer12",
        .mpu_irqs       = omap3xxx_timer12_mpu_irqs,
@@ -1143,29 +381,9 @@ static struct omap_hwmod omap3xxx_timer12_hwmod = {
                },
        },
        .dev_attr       = &capability_secure_dev_attr,
-        .slaves         = omap3xxx_timer12_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer12_slaves),
        .class          = &omap3xxx_timer_hwmod_class,
 };
-/* l4_wkup -> wd_timer2 */
-static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
-        {
-                .pa_start       = 0x48314000,
-                .pa_end         = 0x4831407f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
-        .master         = &omap3xxx_l4_wkup_hwmod,
-        .slave          = &omap3xxx_wd_timer2_hwmod,
-        .clk            = "wdt2_ick",
-        .addr           = omap3xxx_wd_timer2_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
 /*
 * 'wd_timer' class
 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
@@ -1200,12 +418,8 @@ static struct omap_hwmod_class_sysconfig i2c_sysc = {
 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
        .name           = "wd_timer",
        .sysc           = &omap3xxx_wd_timer_sysc,
-        .pre_shutdown   = &omap2_wd_timer_disable
+        .pre_shutdown   = &omap2_wd_timer_disable,
-};
+        .reset          = &omap2_wd_timer_reset,
-/* wd_timer2 */
-static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = {
-        &omap3xxx_l4_wkup__wd_timer2,
 };
 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
@@ -1221,8 +435,6 @@ static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
                        .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
                },
        },
-        .slaves         = omap3xxx_wd_timer2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
        /*
         * XXX: Use software supervised mode, HW supervised smartidle seems to
         * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
@@ -1231,11 +443,6 @@ static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
 };
 /* UART1 */
-static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
-        &omap3_l4_core__uart1,
-};
 static struct omap_hwmod omap3xxx_uart1_hwmod = {
        .name           = "uart1",
        .mpu_irqs       = omap2_uart1_mpu_irqs,
@@ -1250,17 +457,10 @@ static struct omap_hwmod omap3xxx_uart1_hwmod = {
                        .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
                },
        },
-        .slaves         = omap3xxx_uart1_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart1_slaves),
        .class          = &omap2_uart_class,
 };
 /* UART2 */
-static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
-        &omap3_l4_core__uart2,
-};
 static struct omap_hwmod omap3xxx_uart2_hwmod = {
        .name           = "uart2",
        .mpu_irqs       = omap2_uart2_mpu_irqs,
@@ -1275,17 +475,10 @@ static struct omap_hwmod omap3xxx_uart2_hwmod = {
                        .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
                },
        },
-        .slaves         = omap3xxx_uart2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart2_slaves),
        .class          = &omap2_uart_class,
 };
 /* UART3 */
-static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
-        &omap3_l4_per__uart3,
-};
 static struct omap_hwmod omap3xxx_uart3_hwmod = {
        .name           = "uart3",
        .mpu_irqs       = omap2_uart3_mpu_irqs,
@@ -1300,13 +493,10 @@ static struct omap_hwmod omap3xxx_uart3_hwmod = {
                        .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
                },
        },
-        .slaves         = omap3xxx_uart3_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart3_slaves),
        .class          = &omap2_uart_class,
 };
 /* UART4 */
 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
        { .irq = INT_36XX_UART4_IRQ, },
        { .irq = -1 }
@@ -1318,11 +508,7 @@ static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
        { .dma_req = -1 }
 };
-static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
+static struct omap_hwmod omap36xx_uart4_hwmod = {
-        &omap3_l4_per__uart4,
-};
-static struct omap_hwmod omap3xxx_uart4_hwmod = {
        .name           = "uart4",
        .mpu_irqs       = uart4_mpu_irqs,
        .sdma_reqs      = uart4_sdma_reqs,
@@ -1336,8 +522,6 @@ static struct omap_hwmod omap3xxx_uart4_hwmod = {
                        .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
                },
        },
-        .slaves         = omap3xxx_uart4_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart4_slaves),
        .class          = &omap2_uart_class,
 };
@@ -1350,16 +534,12 @@ static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = {
        { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, },
 };
-static struct omap_hwmod_ocp_if *am35xx_uart4_slaves[] = {
-        &am35xx_l4_core__uart4,
-};
 static struct omap_hwmod am35xx_uart4_hwmod = {
-        .name           = "uart4",
+        .name           = "uart4",
-        .mpu_irqs       = am35xx_uart4_mpu_irqs,
+        .mpu_irqs       = am35xx_uart4_mpu_irqs,
-        .sdma_reqs      = am35xx_uart4_sdma_reqs,
+        .sdma_reqs      = am35xx_uart4_sdma_reqs,
-        .main_clk       = "uart4_fck",
+        .main_clk       = "uart4_fck",
-        .prcm           = {
+        .prcm           = {
                .omap2 = {
                        .module_offs = CORE_MOD,
                        .prcm_reg_id = 1,
@@ -1368,12 +548,9 @@ static struct omap_hwmod am35xx_uart4_hwmod = {
                        .idlest_idle_bit = OMAP3430_EN_UART4_SHIFT,
                },
        },
-        .slaves         = am35xx_uart4_slaves,
+        .class          = &omap2_uart_class,
-        .slaves_cnt     = ARRAY_SIZE(am35xx_uart4_slaves),
-        .class          = &omap2_uart_class,
 };
 static struct omap_hwmod_class i2c_class = {
        .name   = "i2c",
        .sysc   = &i2c_sysc,
@@ -1388,51 +565,6 @@ static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
 };
 /* dss */
-/* dss master ports */
-static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = {
-        &omap3xxx_dss__l3,
-};
-/* l4_core -> dss */
-static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
-        .master         = &omap3xxx_l4_core_hwmod,
-        .slave          = &omap3430es1_dss_core_hwmod,
-        .clk            = "dss_ick",
-        .addr           = omap2_dss_addrs,
-        .fw = {
-                .omap2 = {
-                        .l4_fw_region  = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
-                        .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
-                        .flags  = OMAP_FIREWALL_L4,
-                }
-        },
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
-        .master         = &omap3xxx_l4_core_hwmod,
-        .slave          = &omap3xxx_dss_core_hwmod,
-        .clk            = "dss_ick",
-        .addr           = omap2_dss_addrs,
-        .fw = {
-                .omap2 = {
-                        .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
-                        .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
-                        .flags  = OMAP_FIREWALL_L4,
-                }
-        },
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* dss slave ports */
-static struct omap_hwmod_ocp_if *omap3430es1_dss_slaves[] = {
-        &omap3430es1_l4_core__dss,
-};
-static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = {
-        &omap3xxx_l4_core__dss,
-};
 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
        /*
         * The DSS HW needs all DSS clocks enabled during reset. The dss_core
@@ -1460,10 +592,6 @@ static struct omap_hwmod omap3430es1_dss_core_hwmod = {
        },
        .opt_clks       = dss_opt_clks,
        .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
-        .slaves         = omap3430es1_dss_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3430es1_dss_slaves),
-        .masters        = omap3xxx_dss_masters,
-        .masters_cnt    = ARRAY_SIZE(omap3xxx_dss_masters),
        .flags          = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 };
@@ -1485,10 +613,6 @@ static struct omap_hwmod omap3xxx_dss_core_hwmod = {
        },
        .opt_clks       = dss_opt_clks,
        .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
-        .slaves         = omap3xxx_dss_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_slaves),
-        .masters        = omap3xxx_dss_masters,
-        .masters_cnt    = ARRAY_SIZE(omap3xxx_dss_masters),
 };
 /*
@@ -1513,27 +637,6 @@ static struct omap_hwmod_class omap3_dispc_hwmod_class = {
        .sysc   = &omap3_dispc_sysc,
 };
-/* l4_core -> dss_dispc */
-static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
-        .master         = &omap3xxx_l4_core_hwmod,
-        .slave          = &omap3xxx_dss_dispc_hwmod,
-        .clk            = "dss_ick",
-        .addr           = omap2_dss_dispc_addrs,
-        .fw = {
-                .omap2 = {
-                        .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
-                        .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
-                        .flags  = OMAP_FIREWALL_L4,
-                }
-        },
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* dss_dispc slave ports */
-static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = {
-        &omap3xxx_l4_core__dss_dispc,
-};
 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
        .name           = "dss_dispc",
        .class          = &omap3_dispc_hwmod_class,
@@ -1546,8 +649,6 @@ static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
                        .module_offs = OMAP3430_DSS_MOD,
                },
        },
-        .slaves         = omap3xxx_dss_dispc_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_dispc_slaves),
        .flags          = HWMOD_NO_IDLEST,
        .dev_attr       = &omap2_3_dss_dispc_dev_attr
 };
@@ -1567,36 +668,6 @@ static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
 };
 /* dss_dsi1 */
-static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
-        {
-                .pa_start       = 0x4804FC00,
-                .pa_end         = 0x4804FFFF,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_core -> dss_dsi1 */
-static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
-        .master         = &omap3xxx_l4_core_hwmod,
-        .slave          = &omap3xxx_dss_dsi1_hwmod,
-        .clk            = "dss_ick",
-        .addr           = omap3xxx_dss_dsi1_addrs,
-        .fw = {
-                .omap2 = {
-                        .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
-                        .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
-                        .flags  = OMAP_FIREWALL_L4,
-                }
-        },
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* dss_dsi1 slave ports */
-static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = {
-        &omap3xxx_l4_core__dss_dsi1,
-};
 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
        { .role = "sys_clk", .clk = "dss2_alwon_fck" },
 };
@@ -1615,32 +686,9 @@ static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
        },
        .opt_clks       = dss_dsi1_opt_clks,
        .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
-        .slaves         = omap3xxx_dss_dsi1_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves),
        .flags          = HWMOD_NO_IDLEST,
 };
-/* l4_core -> dss_rfbi */
-static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
-        .master         = &omap3xxx_l4_core_hwmod,
-        .slave          = &omap3xxx_dss_rfbi_hwmod,
-        .clk            = "dss_ick",
-        .addr           = omap2_dss_rfbi_addrs,
-        .fw = {
-                .omap2 = {
-                        .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
-                        .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
-                        .flags  = OMAP_FIREWALL_L4,
-                }
-        },
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* dss_rfbi slave ports */
-static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = {
-        &omap3xxx_l4_core__dss_rfbi,
-};
 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
        { .role = "ick", .clk = "dss_ick" },
 };
@@ -1658,33 +706,9 @@ static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
        },
        .opt_clks       = dss_rfbi_opt_clks,
        .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
-        .slaves         = omap3xxx_dss_rfbi_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves),
        .flags          = HWMOD_NO_IDLEST,
 };
-/* l4_core -> dss_venc */
-static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
-        .master         = &omap3xxx_l4_core_hwmod,
-        .slave          = &omap3xxx_dss_venc_hwmod,
-        .clk            = "dss_ick",
-        .addr           = omap2_dss_venc_addrs,
-        .fw = {
-                .omap2 = {
-                        .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
-                        .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
-                        .flags  = OMAP_FIREWALL_L4,
-                }
-        },
-        .flags          = OCPIF_SWSUP_IDLE,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* dss_venc slave ports */
-static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = {
-        &omap3xxx_l4_core__dss_venc,
-};
 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
        /* required only on OMAP3430 */
        { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
@@ -1703,13 +727,10 @@ static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
        },
        .opt_clks       = dss_venc_opt_clks,
        .opt_clks_cnt   = ARRAY_SIZE(dss_venc_opt_clks),
-        .slaves         = omap3xxx_dss_venc_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_venc_slaves),
        .flags          = HWMOD_NO_IDLEST,
 };
 /* I2C1 */
 static struct omap_i2c_dev_attr i2c1_dev_attr = {
        .fifo_depth     = 8, /* bytes */
        .flags          = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
@@ -1717,10 +738,6 @@ static struct omap_i2c_dev_attr i2c1_dev_attr = {
                          OMAP_I2C_FLAG_BUS_SHIFT_2,
 };
-static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
-        &omap3_l4_core__i2c1,
-};
 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
        .name           = "i2c1",
        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
@@ -1736,14 +753,11 @@ static struct omap_hwmod omap3xxx_i2c1_hwmod = {
                        .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
                },
        },
-        .slaves         = omap3xxx_i2c1_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c1_slaves),
        .class          = &i2c_class,
        .dev_attr       = &i2c1_dev_attr,
 };
 /* I2C2 */
 static struct omap_i2c_dev_attr i2c2_dev_attr = {
        .fifo_depth     = 8, /* bytes */
        .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
@@ -1751,10 +765,6 @@ static struct omap_i2c_dev_attr i2c2_dev_attr = {
                 OMAP_I2C_FLAG_BUS_SHIFT_2,
 };
-static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
-        &omap3_l4_core__i2c2,
-};
 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
        .name           = "i2c2",
        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
@@ -1770,14 +780,11 @@ static struct omap_hwmod omap3xxx_i2c2_hwmod = {
                        .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
                },
        },
-        .slaves         = omap3xxx_i2c2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c2_slaves),
        .class          = &i2c_class,
        .dev_attr       = &i2c2_dev_attr,
 };
 /* I2C3 */
 static struct omap_i2c_dev_attr i2c3_dev_attr = {
        .fifo_depth     = 64, /* bytes */
        .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
@@ -1796,10 +803,6 @@ static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
        { .dma_req = -1 }
 };
-static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
-        &omap3_l4_core__i2c3,
-};
 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
        .name           = "i2c3",
        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
@@ -1815,114 +818,10 @@ static struct omap_hwmod omap3xxx_i2c3_hwmod = {
                        .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
                },
        },
-        .slaves         = omap3xxx_i2c3_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c3_slaves),
        .class          = &i2c_class,
        .dev_attr       = &i2c3_dev_attr,
 };
-/* l4_wkup -> gpio1 */
-static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
-        {
-                .pa_start       = 0x48310000,
-                .pa_end         = 0x483101ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
-        .master         = &omap3xxx_l4_wkup_hwmod,
-        .slave          = &omap3xxx_gpio1_hwmod,
-        .addr           = omap3xxx_gpio1_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* l4_per -> gpio2 */
-static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
-        {
-                .pa_start       = 0x49050000,
-                .pa_end         = 0x490501ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
-        .master         = &omap3xxx_l4_per_hwmod,
-        .slave          = &omap3xxx_gpio2_hwmod,
-        .addr           = omap3xxx_gpio2_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* l4_per -> gpio3 */
-static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
-        {
-                .pa_start       = 0x49052000,
-                .pa_end         = 0x490521ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
-        .master         = &omap3xxx_l4_per_hwmod,
-        .slave          = &omap3xxx_gpio3_hwmod,
-        .addr           = omap3xxx_gpio3_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* l4_per -> gpio4 */
-static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
-        {
-                .pa_start       = 0x49054000,
-                .pa_end         = 0x490541ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
-        .master         = &omap3xxx_l4_per_hwmod,
-        .slave          = &omap3xxx_gpio4_hwmod,
-        .addr           = omap3xxx_gpio4_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* l4_per -> gpio5 */
-static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
-        {
-                .pa_start       = 0x49056000,
-                .pa_end         = 0x490561ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
-        .master         = &omap3xxx_l4_per_hwmod,
-        .slave          = &omap3xxx_gpio5_hwmod,
-        .addr           = omap3xxx_gpio5_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* l4_per -> gpio6 */
-static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
-        {
-                .pa_start       = 0x49058000,
-                .pa_end         = 0x490581ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
-        .master         = &omap3xxx_l4_per_hwmod,
-        .slave          = &omap3xxx_gpio6_hwmod,
-        .addr           = omap3xxx_gpio6_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
 /*
 * 'gpio' class
 * general purpose io module
@@ -1945,7 +844,7 @@ static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
        .rev = 1,
 };
-/* gpio_dev_attr*/
+/* gpio_dev_attr */
 static struct omap_gpio_dev_attr gpio_dev_attr = {
        .bank_width = 32,
        .dbck_flag = true,
@@ -1956,10 +855,6 @@ static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
        { .role = "dbclk", .clk = "gpio1_dbck", },
 };
-static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = {
-        &omap3xxx_l4_wkup__gpio1,
-};
 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
        .name           = "gpio1",
        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
@@ -1976,8 +871,6 @@ static struct omap_hwmod omap3xxx_gpio1_hwmod = {
                        .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
                },
        },
-        .slaves         = omap3xxx_gpio1_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio1_slaves),
        .class          = &omap3xxx_gpio_hwmod_class,
        .dev_attr       = &gpio_dev_attr,
 };
@@ -1987,10 +880,6 @@ static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
        { .role = "dbclk", .clk = "gpio2_dbck", },
 };
-static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = {
-        &omap3xxx_l4_per__gpio2,
-};
 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
        .name           = "gpio2",
        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
@@ -2007,8 +896,6 @@ static struct omap_hwmod omap3xxx_gpio2_hwmod = {
                        .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
                },
        },
-        .slaves         = omap3xxx_gpio2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio2_slaves),
        .class          = &omap3xxx_gpio_hwmod_class,
        .dev_attr       = &gpio_dev_attr,
 };
@@ -2018,10 +905,6 @@ static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
        { .role = "dbclk", .clk = "gpio3_dbck", },
 };
-static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = {
-        &omap3xxx_l4_per__gpio3,
-};
 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
        .name           = "gpio3",
        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
@@ -2038,8 +921,6 @@ static struct omap_hwmod omap3xxx_gpio3_hwmod = {
                        .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
                },
        },
-        .slaves         = omap3xxx_gpio3_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio3_slaves),
        .class          = &omap3xxx_gpio_hwmod_class,
        .dev_attr       = &gpio_dev_attr,
 };
@@ -2049,10 +930,6 @@ static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
        { .role = "dbclk", .clk = "gpio4_dbck", },
 };
-static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = {
-        &omap3xxx_l4_per__gpio4,
-};
 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
        .name           = "gpio4",
        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
@@ -2069,8 +946,6 @@ static struct omap_hwmod omap3xxx_gpio4_hwmod = {
                        .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
                },
        },
-        .slaves         = omap3xxx_gpio4_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio4_slaves),
        .class          = &omap3xxx_gpio_hwmod_class,
        .dev_attr       = &gpio_dev_attr,
 };
@@ -2085,10 +960,6 @@ static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
        { .role = "dbclk", .clk = "gpio5_dbck", },
 };
-static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = {
-        &omap3xxx_l4_per__gpio5,
-};
 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
        .name           = "gpio5",
        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
@@ -2105,8 +976,6 @@ static struct omap_hwmod omap3xxx_gpio5_hwmod = {
                        .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
                },
        },
-        .slaves         = omap3xxx_gpio5_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio5_slaves),
        .class          = &omap3xxx_gpio_hwmod_class,
        .dev_attr       = &gpio_dev_attr,
 };
@@ -2121,10 +990,6 @@ static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
        { .role = "dbclk", .clk = "gpio6_dbck", },
 };
-static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = {
-        &omap3xxx_l4_per__gpio6,
-};
 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
        .name           = "gpio6",
        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
@@ -2141,20 +1006,10 @@ static struct omap_hwmod omap3xxx_gpio6_hwmod = {
                        .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
                },
        },
-        .slaves         = omap3xxx_gpio6_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio6_slaves),
        .class          = &omap3xxx_gpio_hwmod_class,
        .dev_attr       = &gpio_dev_attr,
 };
-/* dma_system -> L3 */
-static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
-        .master         = &omap3xxx_dma_system_hwmod,
-        .slave          = &omap3xxx_l3_main_hwmod,
-        .clk            = "core_l3_ick",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
 /* dma attributes */
 static struct omap_dma_dev_attr dma_dev_attr = {
        .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
@@ -2181,34 +1036,6 @@ static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
 };
 /* dma_system */
-static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
-        {
-                .pa_start       = 0x48056000,
-                .pa_end         = 0x48056fff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* dma_system master ports */
-static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = {
-        &omap3xxx_dma_system__l3,
-};
-/* l4_cfg -> dma_system */
-static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
-        .master         = &omap3xxx_l4_core_hwmod,
-        .slave          = &omap3xxx_dma_system_hwmod,
-        .clk            = "core_l4_ick",
-        .addr           = omap3xxx_dma_system_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* dma_system slave ports */
-static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = {
-        &omap3xxx_l4_core__dma_system,
-};
 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
        .name           = "dma",
        .class          = &omap3xxx_dma_hwmod_class,
@@ -2223,10 +1050,6 @@ static struct omap_hwmod omap3xxx_dma_system_hwmod = {
                        .idlest_idle_bit        = OMAP3430_ST_SDMA_SHIFT,
                },
        },
-        .slaves         = omap3xxx_dma_system_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_dma_system_slaves),
-        .masters        = omap3xxx_dma_system_masters,
-        .masters_cnt    = ARRAY_SIZE(omap3xxx_dma_system_masters),
        .dev_attr       = &dma_dev_attr,
        .flags          = HWMOD_NO_IDLEST,
 };
@@ -2253,36 +1076,12 @@ static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
 /* mcbsp1 */
 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
-        { .name = "irq", .irq = 16 },
+        { .name = "common", .irq = 16 },
        { .name = "tx", .irq = 59 },
        { .name = "rx", .irq = 60 },
        { .irq = -1 }
 };
-static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
-        {
-                .name           = "mpu",
-                .pa_start       = 0x48074000,
-                .pa_end         = 0x480740ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_core -> mcbsp1 */
-static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
-        .master         = &omap3xxx_l4_core_hwmod,
-        .slave          = &omap3xxx_mcbsp1_hwmod,
-        .clk            = "mcbsp1_ick",
-        .addr           = omap3xxx_mcbsp1_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* mcbsp1 slave ports */
-static struct omap_hwmod_ocp_if *omap3xxx_mcbsp1_slaves[] = {
-        &omap3xxx_l4_core__mcbsp1,
-};
 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
        .name           = "mcbsp1",
        .class          = &omap3xxx_mcbsp_hwmod_class,
@@ -2298,42 +1097,16 @@ static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
                        .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
                },
        },
-        .slaves         = omap3xxx_mcbsp1_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp1_slaves),
 };
 /* mcbsp2 */
 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
-        { .name = "irq", .irq = 17 },
+        { .name = "common", .irq = 17 },
        { .name = "tx", .irq = 62 },
        { .name = "rx", .irq = 63 },
        { .irq = -1 }
 };
-static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
-        {
-                .name           = "mpu",
-                .pa_start       = 0x49022000,
-                .pa_end         = 0x490220ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_per -> mcbsp2 */
-static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
-        .master         = &omap3xxx_l4_per_hwmod,
-        .slave          = &omap3xxx_mcbsp2_hwmod,
-        .clk            = "mcbsp2_ick",
-        .addr           = omap3xxx_mcbsp2_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* mcbsp2 slave ports */
-static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_slaves[] = {
-        &omap3xxx_l4_per__mcbsp2,
-};
 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
        .sidetone       = "mcbsp2_sidetone",
 };
@@ -2353,45 +1126,19 @@ static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
                        .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
                },
        },
-        .slaves         = omap3xxx_mcbsp2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp2_slaves),
        .dev_attr       = &omap34xx_mcbsp2_dev_attr,
 };
 /* mcbsp3 */
 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
-        { .name = "irq", .irq = 22 },
+        { .name = "common", .irq = 22 },
        { .name = "tx", .irq = 89 },
        { .name = "rx", .irq = 90 },
        { .irq = -1 }
 };
-static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
-        {
-                .name           = "mpu",
-                .pa_start       = 0x49024000,
-                .pa_end         = 0x490240ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_per -> mcbsp3 */
-static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
-        .master         = &omap3xxx_l4_per_hwmod,
-        .slave          = &omap3xxx_mcbsp3_hwmod,
-        .clk            = "mcbsp3_ick",
-        .addr           = omap3xxx_mcbsp3_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* mcbsp3 slave ports */
-static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_slaves[] = {
-        &omap3xxx_l4_per__mcbsp3,
-};
 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
-        .sidetone       = "mcbsp3_sidetone",
+        .sidetone       = "mcbsp3_sidetone",
 };
 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
@@ -2409,14 +1156,12 @@ static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
                        .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
                },
        },
-        .slaves         = omap3xxx_mcbsp3_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp3_slaves),
        .dev_attr       = &omap34xx_mcbsp3_dev_attr,
 };
 /* mcbsp4 */
 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
-        { .name = "irq", .irq = 23 },
+        { .name = "common", .irq = 23 },
        { .name = "tx", .irq = 54 },
        { .name = "rx", .irq = 55 },
        { .irq = -1 }
@@ -2428,30 +1173,6 @@ static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
        { .dma_req = -1 }
 };
-static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
-        {
-                .name           = "mpu",
-                .pa_start       = 0x49026000,
-                .pa_end         = 0x490260ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_per -> mcbsp4 */
-static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
-        .master         = &omap3xxx_l4_per_hwmod,
-        .slave          = &omap3xxx_mcbsp4_hwmod,
-        .clk            = "mcbsp4_ick",
-        .addr           = omap3xxx_mcbsp4_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* mcbsp4 slave ports */
-static struct omap_hwmod_ocp_if *omap3xxx_mcbsp4_slaves[] = {
-        &omap3xxx_l4_per__mcbsp4,
-};
 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
        .name           = "mcbsp4",
        .class          = &omap3xxx_mcbsp_hwmod_class,
@@ -2467,13 +1188,11 @@ static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
                        .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
                },
        },
-        .slaves         = omap3xxx_mcbsp4_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp4_slaves),
 };
 /* mcbsp5 */
 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
-        { .name = "irq", .irq = 27 },
+        { .name = "common", .irq = 27 },
        { .name = "tx", .irq = 81 },
        { .name = "rx", .irq = 82 },
        { .irq = -1 }
@@ -2485,30 +1204,6 @@ static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
        { .dma_req = -1 }
 };
-static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
-        {
-                .name           = "mpu",
-                .pa_start       = 0x48096000,
-                .pa_end         = 0x480960ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_core -> mcbsp5 */
-static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
-        .master         = &omap3xxx_l4_core_hwmod,
-        .slave          = &omap3xxx_mcbsp5_hwmod,
-        .clk            = "mcbsp5_ick",
-        .addr           = omap3xxx_mcbsp5_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* mcbsp5 slave ports */
-static struct omap_hwmod_ocp_if *omap3xxx_mcbsp5_slaves[] = {
-        &omap3xxx_l4_core__mcbsp5,
-};
 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
        .name           = "mcbsp5",
        .class          = &omap3xxx_mcbsp_hwmod_class,
@@ -2524,11 +1219,9 @@ static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
                        .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
                },
        },
-        .slaves         = omap3xxx_mcbsp5_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp5_slaves),
 };
-/* 'mcbsp sidetone' class */
+/* 'mcbsp sidetone' class */
 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
        .sysc_offs      = 0x0010,
        .sysc_flags     = SYSC_HAS_AUTOIDLE,
@@ -2546,30 +1239,6 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
        { .irq = -1 }
 };
-static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
-        {
-                .name           = "sidetone",
-                .pa_start       = 0x49028000,
-                .pa_end         = 0x490280ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_per -> mcbsp2_sidetone */
-static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
-        .master         = &omap3xxx_l4_per_hwmod,
-        .slave          = &omap3xxx_mcbsp2_sidetone_hwmod,
-        .clk            = "mcbsp2_ick",
-        .addr           = omap3xxx_mcbsp2_sidetone_addrs,
-        .user           = OCP_USER_MPU,
-};
-/* mcbsp2_sidetone slave ports */
-static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_sidetone_slaves[] = {
-        &omap3xxx_l4_per__mcbsp2_sidetone,
-};
 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
        .name           = "mcbsp2_sidetone",
        .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
@@ -2584,8 +1253,6 @@ static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
                        .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
                },
        },
-        .slaves         = omap3xxx_mcbsp2_sidetone_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_slaves),
 };
 /* mcbsp3_sidetone */
@@ -2594,30 +1261,6 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
        { .irq = -1 }
 };
-static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
-        {
-                .name           = "sidetone",
-                .pa_start       = 0x4902A000,
-                .pa_end         = 0x4902A0ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_per -> mcbsp3_sidetone */
-static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
-        .master         = &omap3xxx_l4_per_hwmod,
-        .slave          = &omap3xxx_mcbsp3_sidetone_hwmod,
-        .clk            = "mcbsp3_ick",
-        .addr           = omap3xxx_mcbsp3_sidetone_addrs,
-        .user           = OCP_USER_MPU,
-};
-/* mcbsp3_sidetone slave ports */
-static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_sidetone_slaves[] = {
-        &omap3xxx_l4_per__mcbsp3_sidetone,
-};
 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
        .name           = "mcbsp3_sidetone",
        .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
@@ -2632,11 +1275,8 @@ static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
                        .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
                },
        },
-        .slaves         = omap3xxx_mcbsp3_sidetone_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_slaves),
 };
 /* SR common */
 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
        .clkact_shift   = 20,
@@ -2657,7 +1297,7 @@ static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
        .sidle_shift    = 24,
-        .enwkup_shift   = 26
+        .enwkup_shift   = 26,
 };
 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
@@ -2679,12 +1319,13 @@ static struct omap_smartreflex_dev_attr sr1_dev_attr = {
        .sensor_voltdm_name   = "mpu_iva",
 };
-static struct omap_hwmod_ocp_if *omap3_sr1_slaves[] = {
+static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
-        &omap3_l4_core__sr1,
+        { .irq = 18 },
+        { .irq = -1 }
 };
 static struct omap_hwmod omap34xx_sr1_hwmod = {
-        .name           = "sr1_hwmod",
+        .name           = "sr1",
        .class          = &omap34xx_smartreflex_hwmod_class,
        .main_clk       = "sr1_fck",
        .prcm           = {
@@ -2696,15 +1337,13 @@ static struct omap_hwmod omap34xx_sr1_hwmod = {
                        .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
                },
        },
-        .slaves         = omap3_sr1_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3_sr1_slaves),
        .dev_attr       = &sr1_dev_attr,
        .mpu_irqs       = omap3_smartreflex_mpu_irqs,
        .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 };
 static struct omap_hwmod omap36xx_sr1_hwmod = {
-        .name           = "sr1_hwmod",
+        .name           = "sr1",
        .class          = &omap36xx_smartreflex_hwmod_class,
        .main_clk       = "sr1_fck",
        .prcm           = {
@@ -2716,8 +1355,6 @@ static struct omap_hwmod omap36xx_sr1_hwmod = {
                        .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
                },
        },
-        .slaves         = omap3_sr1_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3_sr1_slaves),
        .dev_attr       = &sr1_dev_attr,
        .mpu_irqs       = omap3_smartreflex_mpu_irqs,
 };
@@ -2727,12 +1364,13 @@ static struct omap_smartreflex_dev_attr sr2_dev_attr = {
        .sensor_voltdm_name     = "core",
 };
-static struct omap_hwmod_ocp_if *omap3_sr2_slaves[] = {
+static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
-        &omap3_l4_core__sr2,
+        { .irq = 19 },
+        { .irq = -1 }
 };
 static struct omap_hwmod omap34xx_sr2_hwmod = {
-        .name           = "sr2_hwmod",
+        .name           = "sr2",
        .class          = &omap34xx_smartreflex_hwmod_class,
        .main_clk       = "sr2_fck",
        .prcm           = {
@@ -2744,15 +1382,13 @@ static struct omap_hwmod omap34xx_sr2_hwmod = {
                        .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
                },
        },
-        .slaves         = omap3_sr2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3_sr2_slaves),
        .dev_attr       = &sr2_dev_attr,
        .mpu_irqs       = omap3_smartreflex_core_irqs,
        .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 };
 static struct omap_hwmod omap36xx_sr2_hwmod = {
-        .name           = "sr2_hwmod",
+        .name           = "sr2",
        .class          = &omap36xx_smartreflex_hwmod_class,
        .main_clk       = "sr2_fck",
        .prcm           = {
@@ -2764,8 +1400,6 @@ static struct omap_hwmod omap36xx_sr2_hwmod = {
                        .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
                },
        },
-        .slaves         = omap3_sr2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3_sr2_slaves),
        .dev_attr       = &sr2_dev_attr,
        .mpu_irqs       = omap3_smartreflex_core_irqs,
 };
@@ -2791,34 +1425,11 @@ static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
        .sysc = &omap3xxx_mailbox_sysc,
 };
-static struct omap_hwmod omap3xxx_mailbox_hwmod;
 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
        { .irq = 26 },
        { .irq = -1 }
 };
-static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
-        {
-                .pa_start       = 0x48094000,
-                .pa_end         = 0x480941ff,
-                .flags          = ADDR_TYPE_RT,
-        },
-        { }
-};
-/* l4_core -> mailbox */
-static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
-        .master         = &omap3xxx_l4_core_hwmod,
-        .slave          = &omap3xxx_mailbox_hwmod,
-        .addr           = omap3xxx_mailbox_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* mailbox slave ports */
-static struct omap_hwmod_ocp_if *omap3xxx_mailbox_slaves[] = {
-        &omap3xxx_l4_core__mailbox,
-};
 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
        .name           = "mailbox",
        .class          = &omap3xxx_mailbox_hwmod_class,
@@ -2833,53 +1444,6 @@ static struct omap_hwmod omap3xxx_mailbox_hwmod = {
                        .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
                },
        },
-        .slaves         = omap3xxx_mailbox_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mailbox_slaves),
-};
-/* l4 core -> mcspi1 interface */
-static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
-        .master         = &omap3xxx_l4_core_hwmod,
-        .slave          = &omap34xx_mcspi1,
-        .clk            = "mcspi1_ick",
-        .addr           = omap2_mcspi1_addr_space,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* l4 core -> mcspi2 interface */
-static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
-        .master         = &omap3xxx_l4_core_hwmod,
-        .slave          = &omap34xx_mcspi2,
-        .clk            = "mcspi2_ick",
-        .addr           = omap2_mcspi2_addr_space,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* l4 core -> mcspi3 interface */
-static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
-        .master         = &omap3xxx_l4_core_hwmod,
-        .slave          = &omap34xx_mcspi3,
-        .clk            = "mcspi3_ick",
-        .addr           = omap2430_mcspi3_addr_space,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* l4 core -> mcspi4 interface */
-static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
-        {
-                .pa_start       = 0x480ba000,
-                .pa_end         = 0x480ba0ff,
-                .flags          = ADDR_TYPE_RT,
-        },
-        { }
-};
-static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
-        .master         = &omap3xxx_l4_core_hwmod,
-        .slave          = &omap34xx_mcspi4,
-        .clk            = "mcspi4_ick",
-        .addr           = omap34xx_mcspi4_addr_space,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 /*
@@ -2906,10 +1470,6 @@ static struct omap_hwmod_class omap34xx_mcspi_class = {
 };
 /* mcspi1 */
-static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = {
-        &omap34xx_l4_core__mcspi1,
-};
 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
        .num_chipselect = 4,
 };
@@ -2928,17 +1488,11 @@ static struct omap_hwmod omap34xx_mcspi1 = {
                        .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
                },
        },
-        .slaves         = omap34xx_mcspi1_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi1_slaves),
        .class          = &omap34xx_mcspi_class,
        .dev_attr       = &omap_mcspi1_dev_attr,
 };
 /* mcspi2 */
-static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = {
-        &omap34xx_l4_core__mcspi2,
-};
 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
        .num_chipselect = 2,
 };
@@ -2957,8 +1511,6 @@ static struct omap_hwmod omap34xx_mcspi2 = {
                        .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
                },
        },
-        .slaves         = omap34xx_mcspi2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi2_slaves),
        .class          = &omap34xx_mcspi_class,
        .dev_attr       = &omap_mcspi2_dev_attr,
 };
@@ -2977,10 +1529,6 @@ static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
        { .dma_req = -1 }
 };
-static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = {
-        &omap34xx_l4_core__mcspi3,
-};
 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
        .num_chipselect = 2,
 };
@@ -2999,13 +1547,11 @@ static struct omap_hwmod omap34xx_mcspi3 = {
                        .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
                },
        },
-        .slaves         = omap34xx_mcspi3_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi3_slaves),
        .class          = &omap34xx_mcspi_class,
        .dev_attr       = &omap_mcspi3_dev_attr,
 };
-/* SPI4 */
+/* mcspi4 */
 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
        { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
        { .irq = -1 }
@@ -3017,10 +1563,6 @@ static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
        { .dma_req = -1 }
 };
-static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = {
-        &omap34xx_l4_core__mcspi4,
-};
 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
        .num_chipselect = 1,
 };
@@ -3039,15 +1581,11 @@ static struct omap_hwmod omap34xx_mcspi4 = {
                        .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
                },
        },
-        .slaves         = omap34xx_mcspi4_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi4_slaves),
        .class          = &omap34xx_mcspi_class,
        .dev_attr       = &omap_mcspi4_dev_attr,
 };
-/*
+/* usbhsotg */
- * usbhsotg
- */
 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
        .rev_offs       = 0x0400,
        .sysc_offs      = 0x0404,
@@ -3064,6 +1602,7 @@ static struct omap_hwmod_class usbotg_class = {
        .name = "usbotg",
        .sysc = &omap3xxx_usbhsotg_sysc,
 };
 /* usb_otg_hs */
 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
@@ -3086,10 +1625,6 @@ static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
                        .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
                },
        },
-        .masters        = omap3xxx_usbhsotg_masters,
-        .masters_cnt    = ARRAY_SIZE(omap3xxx_usbhsotg_masters),
-        .slaves         = omap3xxx_usbhsotg_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_usbhsotg_slaves),
        .class          = &usbotg_class,
        /*
@@ -3121,15 +1656,10 @@ static struct omap_hwmod am35xx_usbhsotg_hwmod = {
                .omap2 = {
                },
        },
-        .masters        = am35xx_usbhsotg_masters,
-        .masters_cnt    = ARRAY_SIZE(am35xx_usbhsotg_masters),
-        .slaves         = am35xx_usbhsotg_slaves,
-        .slaves_cnt     = ARRAY_SIZE(am35xx_usbhsotg_slaves),
        .class          = &am35xx_usbotg_class,
 };
 /* MMC/SD/SDIO common */
 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
        .rev_offs       = 0x1fc,
        .sysc_offs      = 0x10,
@@ -3163,10 +1693,6 @@ static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
        { .role = "dbck", .clk = "omap_32k_fck", },
 };
-static struct omap_hwmod_ocp_if *omap3xxx_mmc1_slaves[] = {
-        &omap3xxx_l4_core__mmc1,
-};
 static struct omap_mmc_dev_attr mmc1_dev_attr = {
        .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
 };
@@ -3194,8 +1720,6 @@ static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
                },
        },
        .dev_attr       = &mmc1_pre_es3_dev_attr,
-        .slaves         = omap3xxx_mmc1_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc1_slaves),
        .class          = &omap34xx_mmc_class,
 };
@@ -3216,8 +1740,6 @@ static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
                },
        },
        .dev_attr       = &mmc1_dev_attr,
-        .slaves         = omap3xxx_mmc1_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc1_slaves),
        .class          = &omap34xx_mmc_class,
 };
@@ -3238,10 +1760,6 @@ static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
        { .role = "dbck", .clk = "omap_32k_fck", },
 };
-static struct omap_hwmod_ocp_if *omap3xxx_mmc2_slaves[] = {
-        &omap3xxx_l4_core__mmc2,
-};
 /* See 35xx errata 2.1.1.128 in SPRZ278F */
 static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = {
        .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
@@ -3264,8 +1782,6 @@ static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
                },
        },
        .dev_attr       = &mmc2_pre_es3_dev_attr,
-        .slaves         = omap3xxx_mmc2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc2_slaves),
        .class          = &omap34xx_mmc_class,
 };
@@ -3285,8 +1801,6 @@ static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
                        .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
                },
        },
-        .slaves         = omap3xxx_mmc2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc2_slaves),
        .class          = &omap34xx_mmc_class,
 };
@@ -3307,10 +1821,6 @@ static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
        { .role = "dbck", .clk = "omap_32k_fck", },
 };
-static struct omap_hwmod_ocp_if *omap3xxx_mmc3_slaves[] = {
-        &omap3xxx_l4_core__mmc3,
-};
 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
        .name           = "mmc3",
        .mpu_irqs       = omap34xx_mmc3_mpu_irqs,
@@ -3326,8 +1836,6 @@ static struct omap_hwmod omap3xxx_mmc3_hwmod = {
                        .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
                },
        },
-        .slaves         = omap3xxx_mmc3_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc3_slaves),
        .class          = &omap34xx_mmc_class,
 };
@@ -3335,12 +1843,6 @@ static struct omap_hwmod omap3xxx_mmc3_hwmod = {
 * 'usb_host_hs' class
 * high-speed multi-port usb host controller
 */
-static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = {
-        .master         = &omap3xxx_usb_host_hs_hwmod,
-        .slave          = &omap3xxx_l3_main_hwmod,
-        .clk            = "core_l3_ick",
-        .user           = OCP_USER_MPU,
-};
 static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = {
        .rev_offs       = 0x0000,
@@ -3359,42 +1861,6 @@ static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = {
        .sysc = &omap3xxx_usb_host_hs_sysc,
 };
-static struct omap_hwmod_ocp_if *omap3xxx_usb_host_hs_masters[] = {
-        &omap3xxx_usb_host_hs__l3_main_2,
-};
-static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = {
-        {
-                .name           = "uhh",
-                .pa_start       = 0x48064000,
-                .pa_end         = 0x480643ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        {
-                .name           = "ohci",
-                .pa_start       = 0x48064400,
-                .pa_end         = 0x480647ff,
-        },
-        {
-                .name           = "ehci",
-                .pa_start       = 0x48064800,
-                .pa_end         = 0x48064cff,
-        },
-        {}
-};
-static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = {
-        .master         = &omap3xxx_l4_core_hwmod,
-        .slave          = &omap3xxx_usb_host_hs_hwmod,
-        .clk            = "usbhost_ick",
-        .addr           = omap3xxx_usb_host_hs_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-static struct omap_hwmod_ocp_if *omap3xxx_usb_host_hs_slaves[] = {
-        &omap3xxx_l4_core__usb_host_hs,
-};
 static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = {
          { .role = "ehci_logic_fck", .clk = "usbhost_120m_fck", },
 };
@@ -3423,10 +1889,6 @@ static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
        },
        .opt_clks       = omap3xxx_usb_host_hs_opt_clks,
        .opt_clks_cnt   = ARRAY_SIZE(omap3xxx_usb_host_hs_opt_clks),
-        .slaves         = omap3xxx_usb_host_hs_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_usb_host_hs_slaves),
-        .masters        = omap3xxx_usb_host_hs_masters,
-        .masters_cnt    = ARRAY_SIZE(omap3xxx_usb_host_hs_masters),
        /*
         * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
@@ -3502,6 +1964,1134 @@ static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = {
        { .irq = -1 }
 };
+static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
+        .name           = "usb_tll_hs",
+        .class          = &omap3xxx_usb_tll_hs_hwmod_class,
+        .clkdm_name     = "l3_init_clkdm",
+        .mpu_irqs       = omap3xxx_usb_tll_hs_irqs,
+        .main_clk       = "usbtll_fck",
+        .prcm = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 3,
+                        .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
+                        .idlest_reg_id = 3,
+                        .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
+                },
+        },
+};
+static struct omap_hwmod omap3xxx_hdq1w_hwmod = {
+        .name           = "hdq1w",
+        .mpu_irqs       = omap2_hdq1w_mpu_irqs,
+        .main_clk       = "hdq_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_HDQ_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_HDQ_SHIFT,
+                },
+        },
+        .class          = &omap2_hdq1w_class,
+};
+/*
+ * '32K sync counter' class
+ * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
+ */
+static struct omap_hwmod_class_sysconfig omap3xxx_counter_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0004,
+        .sysc_flags     = SYSC_HAS_SIDLEMODE,
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+static struct omap_hwmod_class omap3xxx_counter_hwmod_class = {
+        .name   = "counter",
+        .sysc   = &omap3xxx_counter_sysc,
+};
+static struct omap_hwmod omap3xxx_counter_32k_hwmod = {
+        .name           = "counter_32k",
+        .class          = &omap3xxx_counter_hwmod_class,
+        .clkdm_name     = "wkup_clkdm",
+        .flags          = HWMOD_SWSUP_SIDLE,
+        .main_clk       = "wkup_32k_fck",
+        .prcm           = {
+                .omap2  = {
+                        .module_offs = WKUP_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_ST_32KSYNC_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_32KSYNC_SHIFT,
+                },
+        },
+};
+/*
+ * interfaces
+ */
+/* L3 -> L4_CORE interface */
+static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
+        .master = &omap3xxx_l3_main_hwmod,
+        .slave  = &omap3xxx_l4_core_hwmod,
+        .user   = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* L3 -> L4_PER interface */
+static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
+        .master = &omap3xxx_l3_main_hwmod,
+        .slave  = &omap3xxx_l4_per_hwmod,
+        .user   = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
+        {
+                .pa_start       = 0x68000000,
+                .pa_end         = 0x6800ffff,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+/* MPU -> L3 interface */
+static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
+        .master   = &omap3xxx_mpu_hwmod,
+        .slave    = &omap3xxx_l3_main_hwmod,
+        .addr     = omap3xxx_l3_main_addrs,
+        .user   = OCP_USER_MPU,
+};
+/* DSS -> l3 */
+static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = {
+        .master         = &omap3430es1_dss_core_hwmod,
+        .slave          = &omap3xxx_l3_main_hwmod,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
+        .master         = &omap3xxx_dss_core_hwmod,
+        .slave          = &omap3xxx_l3_main_hwmod,
+        .fw = {
+                .omap2 = {
+                        .l3_perm_bit  = OMAP3_L3_CORE_FW_INIT_ID_DSS,
+                        .flags  = OMAP_FIREWALL_L3,
+                }
+        },
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l3_core -> usbhsotg interface */
+static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
+        .master         = &omap3xxx_usbhsotg_hwmod,
+        .slave          = &omap3xxx_l3_main_hwmod,
+        .clk            = "core_l3_ick",
+        .user           = OCP_USER_MPU,
+};
+/* l3_core -> am35xx_usbhsotg interface */
+static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
+        .master         = &am35xx_usbhsotg_hwmod,
+        .slave          = &omap3xxx_l3_main_hwmod,
+        .clk            = "core_l3_ick",
+        .user           = OCP_USER_MPU,
+};
+/* L4_CORE -> L4_WKUP interface */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
+        .master = &omap3xxx_l4_core_hwmod,
+        .slave  = &omap3xxx_l4_wkup_hwmod,
+        .user   = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* L4 CORE -> MMC1 interface */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_pre_es3_mmc1_hwmod,
+        .clk            = "mmchs1_ick",
+        .addr           = omap2430_mmc1_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+        .flags          = OMAP_FIREWALL_L4
+};
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_es3plus_mmc1_hwmod,
+        .clk            = "mmchs1_ick",
+        .addr           = omap2430_mmc1_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+        .flags          = OMAP_FIREWALL_L4
+};
+/* L4 CORE -> MMC2 interface */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_pre_es3_mmc2_hwmod,
+        .clk            = "mmchs2_ick",
+        .addr           = omap2430_mmc2_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+        .flags          = OMAP_FIREWALL_L4
+};
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_es3plus_mmc2_hwmod,
+        .clk            = "mmchs2_ick",
+        .addr           = omap2430_mmc2_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+        .flags          = OMAP_FIREWALL_L4
+};
+/* L4 CORE -> MMC3 interface */
+static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
+        {
+                .pa_start       = 0x480ad000,
+                .pa_end         = 0x480ad1ff,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_mmc3_hwmod,
+        .clk            = "mmchs3_ick",
+        .addr           = omap3xxx_mmc3_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+        .flags          = OMAP_FIREWALL_L4
+};
+/* L4 CORE -> UART1 interface */
+static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
+        {
+                .pa_start       = OMAP3_UART1_BASE,
+                .pa_end         = OMAP3_UART1_BASE + SZ_8K - 1,
+                .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_uart1_hwmod,
+        .clk            = "uart1_ick",
+        .addr           = omap3xxx_uart1_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* L4 CORE -> UART2 interface */
+static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
+        {
+                .pa_start       = OMAP3_UART2_BASE,
+                .pa_end         = OMAP3_UART2_BASE + SZ_1K - 1,
+                .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_uart2_hwmod,
+        .clk            = "uart2_ick",
+        .addr           = omap3xxx_uart2_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* L4 PER -> UART3 interface */
+static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
+        {
+                .pa_start       = OMAP3_UART3_BASE,
+                .pa_end         = OMAP3_UART3_BASE + SZ_1K - 1,
+                .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_uart3_hwmod,
+        .clk            = "uart3_ick",
+        .addr           = omap3xxx_uart3_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* L4 PER -> UART4 interface */
+static struct omap_hwmod_addr_space omap36xx_uart4_addr_space[] = {
+        {
+                .pa_start       = OMAP3_UART4_BASE,
+                .pa_end         = OMAP3_UART4_BASE + SZ_1K - 1,
+                .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap36xx_uart4_hwmod,
+        .clk            = "uart4_ick",
+        .addr           = omap36xx_uart4_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* AM35xx: L4 CORE -> UART4 interface */
+static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = {
+        {
+                .pa_start       = OMAP3_UART4_AM35XX_BASE,
+                .pa_end         = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1,
+                .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+        },
+};
+static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &am35xx_uart4_hwmod,
+        .clk            = "uart4_ick",
+        .addr           = am35xx_uart4_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* L4 CORE -> I2C1 interface */
+static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_i2c1_hwmod,
+        .clk            = "i2c1_ick",
+        .addr           = omap2_i2c1_addr_space,
+        .fw = {
+                .omap2 = {
+                        .l4_fw_region  = OMAP3_L4_CORE_FW_I2C1_REGION,
+                        .l4_prot_group = 7,
+                        .flags  = OMAP_FIREWALL_L4,
+                }
+        },
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* L4 CORE -> I2C2 interface */
+static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_i2c2_hwmod,
+        .clk            = "i2c2_ick",
+        .addr           = omap2_i2c2_addr_space,
+        .fw = {
+                .omap2 = {
+                        .l4_fw_region  = OMAP3_L4_CORE_FW_I2C2_REGION,
+                        .l4_prot_group = 7,
+                        .flags = OMAP_FIREWALL_L4,
+                }
+        },
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* L4 CORE -> I2C3 interface */
+static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
+        {
+                .pa_start       = 0x48060000,
+                .pa_end         = 0x48060000 + SZ_128 - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_i2c3_hwmod,
+        .clk            = "i2c3_ick",
+        .addr           = omap3xxx_i2c3_addr_space,
+        .fw = {
+                .omap2 = {
+                        .l4_fw_region  = OMAP3_L4_CORE_FW_I2C3_REGION,
+                        .l4_prot_group = 7,
+                        .flags = OMAP_FIREWALL_L4,
+                }
+        },
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* L4 CORE -> SR1 interface */
+static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
+        {
+                .pa_start       = OMAP34XX_SR1_BASE,
+                .pa_end         = OMAP34XX_SR1_BASE + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap34xx_sr1_hwmod,
+        .clk            = "sr_l4_ick",
+        .addr           = omap3_sr1_addr_space,
+        .user           = OCP_USER_MPU,
+};
+static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap36xx_sr1_hwmod,
+        .clk            = "sr_l4_ick",
+        .addr           = omap3_sr1_addr_space,
+        .user           = OCP_USER_MPU,
+};
+/* L4 CORE -> SR1 interface */
+static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
+        {
+                .pa_start       = OMAP34XX_SR2_BASE,
+                .pa_end         = OMAP34XX_SR2_BASE + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap34xx_sr2_hwmod,
+        .clk            = "sr_l4_ick",
+        .addr           = omap3_sr2_addr_space,
+        .user           = OCP_USER_MPU,
+};
+static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap36xx_sr2_hwmod,
+        .clk            = "sr_l4_ick",
+        .addr           = omap3_sr2_addr_space,
+        .user           = OCP_USER_MPU,
+};
+static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
+        {
+                .pa_start       = OMAP34XX_HSUSB_OTG_BASE,
+                .pa_end         = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_core -> usbhsotg  */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_usbhsotg_hwmod,
+        .clk            = "l4_ick",
+        .addr           = omap3xxx_usbhsotg_addrs,
+        .user           = OCP_USER_MPU,
+};
+static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
+        {
+                .pa_start       = AM35XX_IPSS_USBOTGSS_BASE,
+                .pa_end         = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_core -> usbhsotg  */
+static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &am35xx_usbhsotg_hwmod,
+        .clk            = "l4_ick",
+        .addr           = am35xx_usbhsotg_addrs,
+        .user           = OCP_USER_MPU,
+};
+/* L4_WKUP -> L4_SEC interface */
+static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = {
+        .master = &omap3xxx_l4_wkup_hwmod,
+        .slave  = &omap3xxx_l4_sec_hwmod,
+        .user   = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* IVA2 <- L3 interface */
+static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
+        .master         = &omap3xxx_l3_main_hwmod,
+        .slave          = &omap3xxx_iva_hwmod,
+        .clk            = "core_l3_ick",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
+        {
+                .pa_start       = 0x48318000,
+                .pa_end         = 0x48318000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_wkup -> timer1 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
+        .master         = &omap3xxx_l4_wkup_hwmod,
+        .slave          = &omap3xxx_timer1_hwmod,
+        .clk            = "gpt1_ick",
+        .addr           = omap3xxx_timer1_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
+        {
+                .pa_start       = 0x49032000,
+                .pa_end         = 0x49032000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_per -> timer2 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_timer2_hwmod,
+        .clk            = "gpt2_ick",
+        .addr           = omap3xxx_timer2_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
+        {
+                .pa_start       = 0x49034000,
+                .pa_end         = 0x49034000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_per -> timer3 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_timer3_hwmod,
+        .clk            = "gpt3_ick",
+        .addr           = omap3xxx_timer3_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
+        {
+                .pa_start       = 0x49036000,
+                .pa_end         = 0x49036000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_per -> timer4 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_timer4_hwmod,
+        .clk            = "gpt4_ick",
+        .addr           = omap3xxx_timer4_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
+        {
+                .pa_start       = 0x49038000,
+                .pa_end         = 0x49038000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_per -> timer5 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_timer5_hwmod,
+        .clk            = "gpt5_ick",
+        .addr           = omap3xxx_timer5_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
+        {
+                .pa_start       = 0x4903A000,
+                .pa_end         = 0x4903A000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_per -> timer6 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_timer6_hwmod,
+        .clk            = "gpt6_ick",
+        .addr           = omap3xxx_timer6_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
+        {
+                .pa_start       = 0x4903C000,
+                .pa_end         = 0x4903C000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_per -> timer7 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_timer7_hwmod,
+        .clk            = "gpt7_ick",
+        .addr           = omap3xxx_timer7_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
+        {
+                .pa_start       = 0x4903E000,
+                .pa_end         = 0x4903E000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_per -> timer8 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_timer8_hwmod,
+        .clk            = "gpt8_ick",
+        .addr           = omap3xxx_timer8_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
+        {
+                .pa_start       = 0x49040000,
+                .pa_end         = 0x49040000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_per -> timer9 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_timer9_hwmod,
+        .clk            = "gpt9_ick",
+        .addr           = omap3xxx_timer9_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_core -> timer10 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_timer10_hwmod,
+        .clk            = "gpt10_ick",
+        .addr           = omap2_timer10_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_core -> timer11 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_timer11_hwmod,
+        .clk            = "gpt11_ick",
+        .addr           = omap2_timer11_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
+        {
+                .pa_start       = 0x48304000,
+                .pa_end         = 0x48304000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_core -> timer12 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = {
+        .master         = &omap3xxx_l4_sec_hwmod,
+        .slave          = &omap3xxx_timer12_hwmod,
+        .clk            = "gpt12_ick",
+        .addr           = omap3xxx_timer12_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_wkup -> wd_timer2 */
+static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
+        {
+                .pa_start       = 0x48314000,
+                .pa_end         = 0x4831407f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
+        .master         = &omap3xxx_l4_wkup_hwmod,
+        .slave          = &omap3xxx_wd_timer2_hwmod,
+        .clk            = "wdt2_ick",
+        .addr           = omap3xxx_wd_timer2_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_core -> dss */
+static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3430es1_dss_core_hwmod,
+        .clk            = "dss_ick",
+        .addr           = omap2_dss_addrs,
+        .fw = {
+                .omap2 = {
+                        .l4_fw_region  = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
+                        .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
+                        .flags  = OMAP_FIREWALL_L4,
+                }
+        },
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_dss_core_hwmod,
+        .clk            = "dss_ick",
+        .addr           = omap2_dss_addrs,
+        .fw = {
+                .omap2 = {
+                        .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
+                        .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
+                        .flags  = OMAP_FIREWALL_L4,
+                }
+        },
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_core -> dss_dispc */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_dss_dispc_hwmod,
+        .clk            = "dss_ick",
+        .addr           = omap2_dss_dispc_addrs,
+        .fw = {
+                .omap2 = {
+                        .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
+                        .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
+                        .flags  = OMAP_FIREWALL_L4,
+                }
+        },
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
+        {
+                .pa_start       = 0x4804FC00,
+                .pa_end         = 0x4804FFFF,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_core -> dss_dsi1 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_dss_dsi1_hwmod,
+        .clk            = "dss_ick",
+        .addr           = omap3xxx_dss_dsi1_addrs,
+        .fw = {
+                .omap2 = {
+                        .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
+                        .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
+                        .flags  = OMAP_FIREWALL_L4,
+                }
+        },
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_core -> dss_rfbi */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_dss_rfbi_hwmod,
+        .clk            = "dss_ick",
+        .addr           = omap2_dss_rfbi_addrs,
+        .fw = {
+                .omap2 = {
+                        .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
+                        .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
+                        .flags  = OMAP_FIREWALL_L4,
+                }
+        },
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_core -> dss_venc */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_dss_venc_hwmod,
+        .clk            = "dss_ick",
+        .addr           = omap2_dss_venc_addrs,
+        .fw = {
+                .omap2 = {
+                        .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
+                        .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
+                        .flags  = OMAP_FIREWALL_L4,
+                }
+        },
+        .flags          = OCPIF_SWSUP_IDLE,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_wkup -> gpio1 */
+static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
+        {
+                .pa_start       = 0x48310000,
+                .pa_end         = 0x483101ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
+        .master         = &omap3xxx_l4_wkup_hwmod,
+        .slave          = &omap3xxx_gpio1_hwmod,
+        .addr           = omap3xxx_gpio1_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_per -> gpio2 */
+static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
+        {
+                .pa_start       = 0x49050000,
+                .pa_end         = 0x490501ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_gpio2_hwmod,
+        .addr           = omap3xxx_gpio2_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_per -> gpio3 */
+static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
+        {
+                .pa_start       = 0x49052000,
+                .pa_end         = 0x490521ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_gpio3_hwmod,
+        .addr           = omap3xxx_gpio3_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_per -> gpio4 */
+static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
+        {
+                .pa_start       = 0x49054000,
+                .pa_end         = 0x490541ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_gpio4_hwmod,
+        .addr           = omap3xxx_gpio4_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_per -> gpio5 */
+static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
+        {
+                .pa_start       = 0x49056000,
+                .pa_end         = 0x490561ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_gpio5_hwmod,
+        .addr           = omap3xxx_gpio5_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_per -> gpio6 */
+static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
+        {
+                .pa_start       = 0x49058000,
+                .pa_end         = 0x490581ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_gpio6_hwmod,
+        .addr           = omap3xxx_gpio6_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* dma_system -> L3 */
+static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
+        .master         = &omap3xxx_dma_system_hwmod,
+        .slave          = &omap3xxx_l3_main_hwmod,
+        .clk            = "core_l3_ick",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
+        {
+                .pa_start       = 0x48056000,
+                .pa_end         = 0x48056fff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_cfg -> dma_system */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_dma_system_hwmod,
+        .clk            = "core_l4_ick",
+        .addr           = omap3xxx_dma_system_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
+        {
+                .name           = "mpu",
+                .pa_start       = 0x48074000,
+                .pa_end         = 0x480740ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_core -> mcbsp1 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_mcbsp1_hwmod,
+        .clk            = "mcbsp1_ick",
+        .addr           = omap3xxx_mcbsp1_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
+        {
+                .name           = "mpu",
+                .pa_start       = 0x49022000,
+                .pa_end         = 0x490220ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_per -> mcbsp2 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_mcbsp2_hwmod,
+        .clk            = "mcbsp2_ick",
+        .addr           = omap3xxx_mcbsp2_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
+        {
+                .name           = "mpu",
+                .pa_start       = 0x49024000,
+                .pa_end         = 0x490240ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_per -> mcbsp3 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_mcbsp3_hwmod,
+        .clk            = "mcbsp3_ick",
+        .addr           = omap3xxx_mcbsp3_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
+        {
+                .name           = "mpu",
+                .pa_start       = 0x49026000,
+                .pa_end         = 0x490260ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_per -> mcbsp4 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_mcbsp4_hwmod,
+        .clk            = "mcbsp4_ick",
+        .addr           = omap3xxx_mcbsp4_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
+        {
+                .name           = "mpu",
+                .pa_start       = 0x48096000,
+                .pa_end         = 0x480960ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_core -> mcbsp5 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_mcbsp5_hwmod,
+        .clk            = "mcbsp5_ick",
+        .addr           = omap3xxx_mcbsp5_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
+        {
+                .name           = "sidetone",
+                .pa_start       = 0x49028000,
+                .pa_end         = 0x490280ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_per -> mcbsp2_sidetone */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_mcbsp2_sidetone_hwmod,
+        .clk            = "mcbsp2_ick",
+        .addr           = omap3xxx_mcbsp2_sidetone_addrs,
+        .user           = OCP_USER_MPU,
+};
+static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
+        {
+                .name           = "sidetone",
+                .pa_start       = 0x4902A000,
+                .pa_end         = 0x4902A0ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_per -> mcbsp3_sidetone */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_mcbsp3_sidetone_hwmod,
+        .clk            = "mcbsp3_ick",
+        .addr           = omap3xxx_mcbsp3_sidetone_addrs,
+        .user           = OCP_USER_MPU,
+};
+static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
+        {
+                .pa_start       = 0x48094000,
+                .pa_end         = 0x480941ff,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+/* l4_core -> mailbox */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_mailbox_hwmod,
+        .addr           = omap3xxx_mailbox_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4 core -> mcspi1 interface */
+static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap34xx_mcspi1,
+        .clk            = "mcspi1_ick",
+        .addr           = omap2_mcspi1_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4 core -> mcspi2 interface */
+static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap34xx_mcspi2,
+        .clk            = "mcspi2_ick",
+        .addr           = omap2_mcspi2_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4 core -> mcspi3 interface */
+static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap34xx_mcspi3,
+        .clk            = "mcspi3_ick",
+        .addr           = omap2430_mcspi3_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4 core -> mcspi4 interface */
+static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
+        {
+                .pa_start       = 0x480ba000,
+                .pa_end         = 0x480ba0ff,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap34xx_mcspi4,
+        .clk            = "mcspi4_ick",
+        .addr           = omap34xx_mcspi4_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = {
+        .master         = &omap3xxx_usb_host_hs_hwmod,
+        .slave          = &omap3xxx_l3_main_hwmod,
+        .clk            = "core_l3_ick",
+        .user           = OCP_USER_MPU,
+};
+static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = {
+        {
+                .name           = "uhh",
+                .pa_start       = 0x48064000,
+                .pa_end         = 0x480643ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        {
+                .name           = "ohci",
+                .pa_start       = 0x48064400,
+                .pa_end         = 0x480647ff,
+        },
+        {
+                .name           = "ehci",
+                .pa_start       = 0x48064800,
+                .pa_end         = 0x48064cff,
+        },
+        {}
+};
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_usb_host_hs_hwmod,
+        .clk            = "usbhost_ick",
+        .addr           = omap3xxx_usb_host_hs_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
 static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = {
        {
                .name           = "tll",
@@ -3520,183 +3110,187 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = {
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-static struct omap_hwmod_ocp_if *omap3xxx_usb_tll_hs_slaves[] = {
+/* l4_core -> hdq1w interface */
-        &omap3xxx_l4_core__usb_tll_hs,
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_hdq1w_hwmod,
+        .clk            = "hdq_ick",
+        .addr           = omap2_hdq1w_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+        .flags          = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
 };
-static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
+/* l4_wkup -> 32ksync_counter */
-        .name           = "usb_tll_hs",
+static struct omap_hwmod_addr_space omap3xxx_counter_32k_addrs[] = {
-        .class          = &omap3xxx_usb_tll_hs_hwmod_class,
+        {
-        .clkdm_name     = "l3_init_clkdm",
+                .pa_start       = 0x48320000,
-        .mpu_irqs       = omap3xxx_usb_tll_hs_irqs,
+                .pa_end         = 0x4832001f,
-        .main_clk       = "usbtll_fck",
+                .flags          = ADDR_TYPE_RT
-        .prcm = {
-                .omap2 = {
-                        .module_offs = CORE_MOD,
-                        .prcm_reg_id = 3,
-                        .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
-                        .idlest_reg_id = 3,
-                        .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
-                },
        },
-        .slaves         = omap3xxx_usb_tll_hs_slaves,
+        { }
-        .slaves_cnt     = ARRAY_SIZE(omap3xxx_usb_tll_hs_slaves),
+};
-};
-static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
-        &omap3xxx_l3_main_hwmod,
-        &omap3xxx_l4_core_hwmod,
-        &omap3xxx_l4_per_hwmod,
-        &omap3xxx_l4_wkup_hwmod,
-        &omap3xxx_mmc3_hwmod,
-        &omap3xxx_mpu_hwmod,
-        &omap3xxx_timer1_hwmod,
-        &omap3xxx_timer2_hwmod,
-        &omap3xxx_timer3_hwmod,
-        &omap3xxx_timer4_hwmod,
-        &omap3xxx_timer5_hwmod,
-        &omap3xxx_timer6_hwmod,
-        &omap3xxx_timer7_hwmod,
-        &omap3xxx_timer8_hwmod,
-        &omap3xxx_timer9_hwmod,
-        &omap3xxx_timer10_hwmod,
-        &omap3xxx_timer11_hwmod,
-        &omap3xxx_wd_timer2_hwmod,
-        &omap3xxx_uart1_hwmod,
-        &omap3xxx_uart2_hwmod,
-        &omap3xxx_uart3_hwmod,
-        /* i2c class */
-        &omap3xxx_i2c1_hwmod,
-        &omap3xxx_i2c2_hwmod,
-        &omap3xxx_i2c3_hwmod,
-        /* gpio class */
-        &omap3xxx_gpio1_hwmod,
-        &omap3xxx_gpio2_hwmod,
-        &omap3xxx_gpio3_hwmod,
-        &omap3xxx_gpio4_hwmod,
-        &omap3xxx_gpio5_hwmod,
-        &omap3xxx_gpio6_hwmod,
-        /* dma_system class*/
-        &omap3xxx_dma_system_hwmod,
-        /* mcbsp class */
-        &omap3xxx_mcbsp1_hwmod,
-        &omap3xxx_mcbsp2_hwmod,
-        &omap3xxx_mcbsp3_hwmod,
-        &omap3xxx_mcbsp4_hwmod,
-        &omap3xxx_mcbsp5_hwmod,
-        &omap3xxx_mcbsp2_sidetone_hwmod,
-        &omap3xxx_mcbsp3_sidetone_hwmod,
-        /* mcspi class */
-        &omap34xx_mcspi1,
-        &omap34xx_mcspi2,
-        &omap34xx_mcspi3,
-        &omap34xx_mcspi4,
+static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = {
+        .master         = &omap3xxx_l4_wkup_hwmod,
+        .slave          = &omap3xxx_counter_32k_hwmod,
+        .clk            = "omap_32ksync_ick",
+        .addr           = omap3xxx_counter_32k_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
+        &omap3xxx_l3_main__l4_core,
+        &omap3xxx_l3_main__l4_per,
+        &omap3xxx_mpu__l3_main,
+        &omap3xxx_l4_core__l4_wkup,
+        &omap3xxx_l4_core__mmc3,
+        &omap3_l4_core__uart1,
+        &omap3_l4_core__uart2,
+        &omap3_l4_per__uart3,
+        &omap3_l4_core__i2c1,
+        &omap3_l4_core__i2c2,
+        &omap3_l4_core__i2c3,
+        &omap3xxx_l4_wkup__l4_sec,
+        &omap3xxx_l4_wkup__timer1,
+        &omap3xxx_l4_per__timer2,
+        &omap3xxx_l4_per__timer3,
+        &omap3xxx_l4_per__timer4,
+        &omap3xxx_l4_per__timer5,
+        &omap3xxx_l4_per__timer6,
+        &omap3xxx_l4_per__timer7,
+        &omap3xxx_l4_per__timer8,
+        &omap3xxx_l4_per__timer9,
+        &omap3xxx_l4_core__timer10,
+        &omap3xxx_l4_core__timer11,
+        &omap3xxx_l4_wkup__wd_timer2,
+        &omap3xxx_l4_wkup__gpio1,
+        &omap3xxx_l4_per__gpio2,
+        &omap3xxx_l4_per__gpio3,
+        &omap3xxx_l4_per__gpio4,
+        &omap3xxx_l4_per__gpio5,
+        &omap3xxx_l4_per__gpio6,
+        &omap3xxx_dma_system__l3,
+        &omap3xxx_l4_core__dma_system,
+        &omap3xxx_l4_core__mcbsp1,
+        &omap3xxx_l4_per__mcbsp2,
+        &omap3xxx_l4_per__mcbsp3,
+        &omap3xxx_l4_per__mcbsp4,
+        &omap3xxx_l4_core__mcbsp5,
+        &omap3xxx_l4_per__mcbsp2_sidetone,
+        &omap3xxx_l4_per__mcbsp3_sidetone,
+        &omap34xx_l4_core__mcspi1,
+        &omap34xx_l4_core__mcspi2,
+        &omap34xx_l4_core__mcspi3,
+        &omap34xx_l4_core__mcspi4,
+        &omap3xxx_l4_wkup__counter_32k,
        NULL,
 };
-/* GP-only hwmods */
+/* GP-only hwmod links */
-static __initdata struct omap_hwmod *omap3xxx_gp_hwmods[] = {
+static struct omap_hwmod_ocp_if *omap3xxx_gp_hwmod_ocp_ifs[] __initdata = {
-        &omap3xxx_timer12_hwmod,
+        &omap3xxx_l4_sec__timer12,
        NULL
 };
-/* 3430ES1-only hwmods */
+/* 3430ES1-only hwmod links */
-static __initdata struct omap_hwmod *omap3430es1_hwmods[] = {
+static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = {
-        &omap3430es1_dss_core_hwmod,
+        &omap3430es1_dss__l3,
+        &omap3430es1_l4_core__dss,
        NULL
 };
-/* 3430ES2+-only hwmods */
+/* 3430ES2+-only hwmod links */
-static __initdata struct omap_hwmod *omap3430es2plus_hwmods[] = {
+static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = {
-        &omap3xxx_dss_core_hwmod,
+        &omap3xxx_dss__l3,
-        &omap3xxx_usbhsotg_hwmod,
+        &omap3xxx_l4_core__dss,
-        &omap3xxx_usb_host_hs_hwmod,
+        &omap3xxx_usbhsotg__l3,
-        &omap3xxx_usb_tll_hs_hwmod,
+        &omap3xxx_l4_core__usbhsotg,
+        &omap3xxx_usb_host_hs__l3_main_2,
+        &omap3xxx_l4_core__usb_host_hs,
+        &omap3xxx_l4_core__usb_tll_hs,
        NULL
 };
-/* <= 3430ES3-only hwmods */
+/* <= 3430ES3-only hwmod links */
-static struct omap_hwmod *omap3430_pre_es3_hwmods[] __initdata = {
+static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = {
-        &omap3xxx_pre_es3_mmc1_hwmod,
+        &omap3xxx_l4_core__pre_es3_mmc1,
-        &omap3xxx_pre_es3_mmc2_hwmod,
+        &omap3xxx_l4_core__pre_es3_mmc2,
        NULL
 };
-/* 3430ES3+-only hwmods */
+/* 3430ES3+-only hwmod links */
-static struct omap_hwmod *omap3430_es3plus_hwmods[] __initdata = {
+static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = {
-        &omap3xxx_es3plus_mmc1_hwmod,
+        &omap3xxx_l4_core__es3plus_mmc1,
-        &omap3xxx_es3plus_mmc2_hwmod,
+        &omap3xxx_l4_core__es3plus_mmc2,
        NULL
 };
-/* 34xx-only hwmods (all ES revisions) */
+/* 34xx-only hwmod links (all ES revisions) */
-static __initdata struct omap_hwmod *omap34xx_hwmods[] = {
+static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = {
-        &omap3xxx_iva_hwmod,
+        &omap3xxx_l3__iva,
-        &omap34xx_sr1_hwmod,
+        &omap34xx_l4_core__sr1,
-        &omap34xx_sr2_hwmod,
+        &omap34xx_l4_core__sr2,
-        &omap3xxx_mailbox_hwmod,
+        &omap3xxx_l4_core__mailbox,
+        &omap3xxx_l4_core__hdq1w,
        NULL
 };
-/* 36xx-only hwmods (all ES revisions) */
+/* 36xx-only hwmod links (all ES revisions) */
-static __initdata struct omap_hwmod *omap36xx_hwmods[] = {
+static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = {
-        &omap3xxx_iva_hwmod,
+        &omap3xxx_l3__iva,
-        &omap3xxx_uart4_hwmod,
+        &omap36xx_l4_per__uart4,
-        &omap3xxx_dss_core_hwmod,
+        &omap3xxx_dss__l3,
-        &omap36xx_sr1_hwmod,
+        &omap3xxx_l4_core__dss,
-        &omap36xx_sr2_hwmod,
+        &omap36xx_l4_core__sr1,
-        &omap3xxx_usbhsotg_hwmod,
+        &omap36xx_l4_core__sr2,
-        &omap3xxx_mailbox_hwmod,
+        &omap3xxx_usbhsotg__l3,
-        &omap3xxx_usb_host_hs_hwmod,
+        &omap3xxx_l4_core__usbhsotg,
-        &omap3xxx_usb_tll_hs_hwmod,
+        &omap3xxx_l4_core__mailbox,
-        &omap3xxx_es3plus_mmc1_hwmod,
+        &omap3xxx_usb_host_hs__l3_main_2,
-        &omap3xxx_es3plus_mmc2_hwmod,
+        &omap3xxx_l4_core__usb_host_hs,
+        &omap3xxx_l4_core__usb_tll_hs,
+        &omap3xxx_l4_core__es3plus_mmc1,
+        &omap3xxx_l4_core__es3plus_mmc2,
+        &omap3xxx_l4_core__hdq1w,
        NULL
 };
-static __initdata struct omap_hwmod *am35xx_hwmods[] = {
+static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = {
-        &omap3xxx_dss_core_hwmod, /* XXX ??? */
+        &omap3xxx_dss__l3,
-        &am35xx_usbhsotg_hwmod,
+        &omap3xxx_l4_core__dss,
-        &am35xx_uart4_hwmod,
+        &am35xx_usbhsotg__l3,
-        &omap3xxx_usb_host_hs_hwmod,
+        &am35xx_l4_core__usbhsotg,
-        &omap3xxx_usb_tll_hs_hwmod,
+        &am35xx_l4_core__uart4,
-        &omap3xxx_es3plus_mmc1_hwmod,
+        &omap3xxx_usb_host_hs__l3_main_2,
-        &omap3xxx_es3plus_mmc2_hwmod,
+        &omap3xxx_l4_core__usb_host_hs,
+        &omap3xxx_l4_core__usb_tll_hs,
+        &omap3xxx_l4_core__es3plus_mmc1,
+        &omap3xxx_l4_core__es3plus_mmc2,
        NULL
 };
-static __initdata struct omap_hwmod *omap3xxx_dss_hwmods[] = {
+static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = {
-        /* dss class */
+        &omap3xxx_l4_core__dss_dispc,
-        &omap3xxx_dss_dispc_hwmod,
+        &omap3xxx_l4_core__dss_dsi1,
-        &omap3xxx_dss_dsi1_hwmod,
+        &omap3xxx_l4_core__dss_rfbi,
-        &omap3xxx_dss_rfbi_hwmod,
+        &omap3xxx_l4_core__dss_venc,
-        &omap3xxx_dss_venc_hwmod,
        NULL
 };
 int __init omap3xxx_hwmod_init(void)
 {
        int r;
-        struct omap_hwmod **h = NULL;
+        struct omap_hwmod_ocp_if **h = NULL;
        unsigned int rev;
-        /* Register hwmods common to all OMAP3 */
+        /* Register hwmod links common to all OMAP3 */
-        r = omap_hwmod_register(omap3xxx_hwmods);
+        r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs);
        if (r < 0)
                return r;
-        /* Register GP-only hwmods. */
+        /* Register GP-only hwmod links. */
        if (omap_type() == OMAP2_DEVICE_TYPE_GP) {
-                r = omap_hwmod_register(omap3xxx_gp_hwmods);
+                r = omap_hwmod_register_links(omap3xxx_gp_hwmod_ocp_ifs);
                if (r < 0)
                        return r;
        }
@@ -3704,43 +3298,43 @@ int __init omap3xxx_hwmod_init(void)
        rev = omap_rev();
        /*
-         * Register hwmods common to individual OMAP3 families, all
+         * Register hwmod links common to individual OMAP3 families, all
         * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx)
         * All possible revisions should be included in this conditional.
         */
        if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
            rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
            rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
-                h = omap34xx_hwmods;
+                h = omap34xx_hwmod_ocp_ifs;
        } else if (rev == OMAP3517_REV_ES1_0 || rev == OMAP3517_REV_ES1_1) {
-                h = am35xx_hwmods;
+                h = am35xx_hwmod_ocp_ifs;
        } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
                   rev == OMAP3630_REV_ES1_2) {
-                h = omap36xx_hwmods;
+                h = omap36xx_hwmod_ocp_ifs;
        } else {
                WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
                return -EINVAL;
        };
-        r = omap_hwmod_register(h);
+        r = omap_hwmod_register_links(h);
        if (r < 0)
                return r;
        /*
-         * Register hwmods specific to certain ES levels of a
+         * Register hwmod links specific to certain ES levels of a
         * particular family of silicon (e.g., 34xx ES1.0)
         */
        h = NULL;
        if (rev == OMAP3430_REV_ES1_0) {
-                h = omap3430es1_hwmods;
+                h = omap3430es1_hwmod_ocp_ifs;
        } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
                   rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
                   rev == OMAP3430_REV_ES3_1_2) {
-                h = omap3430es2plus_hwmods;
+                h = omap3430es2plus_hwmod_ocp_ifs;
        };
        if (h) {
-                r = omap_hwmod_register(h);
+                r = omap_hwmod_register_links(h);
                if (r < 0)
                        return r;
        }
@@ -3748,29 +3342,29 @@ int __init omap3xxx_hwmod_init(void)
        h = NULL;
        if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
            rev == OMAP3430_REV_ES2_1) {
-                h = omap3430_pre_es3_hwmods;
+                h = omap3430_pre_es3_hwmod_ocp_ifs;
        } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
                   rev == OMAP3430_REV_ES3_1_2) {
-                h = omap3430_es3plus_hwmods;
+                h = omap3430_es3plus_hwmod_ocp_ifs;
        };
        if (h)
-                r = omap_hwmod_register(h);
+                r = omap_hwmod_register_links(h);
        if (r < 0)
                return r;
        /*
         * DSS code presumes that dss_core hwmod is handled first,
         * _before_ any other DSS related hwmods so register common
-         * DSS hwmods last to ensure that dss_core is already registered.
+         * DSS hwmod links last to ensure that dss_core is already
-         * Otherwise some change things may happen, for ex. if dispc
+         * registered.  Otherwise some change things may happen, for
-         * is handled before dss_core and DSS is enabled in bootloader
+         * ex. if dispc is handled before dss_core and DSS is enabled
-         * DIPSC will be reset with outputs enabled which sometimes leads
+         * in bootloader DISPC will be reset with outputs enabled
-         * to unrecoverable L3 error.
+         * which sometimes leads to unrecoverable L3 error.  XXX The
-         * XXX The long-term fix to this is to ensure modules are set up
+         * long-term fix to this is to ensure hwmods are set up in
-         * in dependency order in the hwmod core code.
+         * dependency order in the hwmod core code.
         */
-        r = omap_hwmod_register(omap3xxx_dss_hwmods);
+        r = omap_hwmod_register_links(omap3xxx_dss_hwmod_ocp_ifs);
        return r;
 }
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index cc9bd106a854..950454a3fa31 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -1,7 +1,7 @@
 /*
 * Hardware modules present on the OMAP44xx chips
 *
- * Copyright (C) 2009-2011 Texas Instruments, Inc.
+ * Copyright (C) 2009-2012 Texas Instruments, Inc.
 * Copyright (C) 2009-2010 Nokia Corporation
 *
 * Paul Walmsley
@@ -44,41 +44,34 @@
 #define OMAP44XX_IRQ_GIC_START  32
 /* Base offset for all OMAP4 dma requests */
-#define OMAP44XX_DMA_REQ_START  1
+#define OMAP44XX_DMA_REQ_START  1
-/* Backward references (IPs with Bus Master capability) */
-static struct omap_hwmod omap44xx_aess_hwmod;
-static struct omap_hwmod omap44xx_dma_system_hwmod;
-static struct omap_hwmod omap44xx_dmm_hwmod;
-static struct omap_hwmod omap44xx_dsp_hwmod;
-static struct omap_hwmod omap44xx_dss_hwmod;
-static struct omap_hwmod omap44xx_emif_fw_hwmod;
-static struct omap_hwmod omap44xx_hsi_hwmod;
-static struct omap_hwmod omap44xx_ipu_hwmod;
-static struct omap_hwmod omap44xx_iss_hwmod;
-static struct omap_hwmod omap44xx_iva_hwmod;
-static struct omap_hwmod omap44xx_l3_instr_hwmod;
-static struct omap_hwmod omap44xx_l3_main_1_hwmod;
-static struct omap_hwmod omap44xx_l3_main_2_hwmod;
-static struct omap_hwmod omap44xx_l3_main_3_hwmod;
-static struct omap_hwmod omap44xx_l4_abe_hwmod;
-static struct omap_hwmod omap44xx_l4_cfg_hwmod;
-static struct omap_hwmod omap44xx_l4_per_hwmod;
-static struct omap_hwmod omap44xx_l4_wkup_hwmod;
-static struct omap_hwmod omap44xx_mmc1_hwmod;
-static struct omap_hwmod omap44xx_mmc2_hwmod;
-static struct omap_hwmod omap44xx_mpu_hwmod;
-static struct omap_hwmod omap44xx_mpu_private_hwmod;
-static struct omap_hwmod omap44xx_usb_otg_hs_hwmod;
-static struct omap_hwmod omap44xx_usb_host_hs_hwmod;
-static struct omap_hwmod omap44xx_usb_tll_hs_hwmod;
 /*
- * Interconnects omap_hwmod structures
+ * IP blocks
- * hwmods that compose the global OMAP interconnect
 */
 /*
+ * 'c2c_target_fw' class
+ * instance(s): c2c_target_fw
+ */
+static struct omap_hwmod_class omap44xx_c2c_target_fw_hwmod_class = {
+        .name   = "c2c_target_fw",
+};
+/* c2c_target_fw */
+static struct omap_hwmod omap44xx_c2c_target_fw_hwmod = {
+        .name           = "c2c_target_fw",
+        .class          = &omap44xx_c2c_target_fw_hwmod_class,
+        .clkdm_name     = "d2d_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET,
+                },
+        },
+};
+/*
 * 'dmm' class
 * instance(s): dmm
 */
@@ -92,51 +85,17 @@ static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
        { .irq = -1 }
 };
-/* l3_main_1 -> dmm */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
-        .master         = &omap44xx_l3_main_1_hwmod,
-        .slave          = &omap44xx_dmm_hwmod,
-        .clk            = "l3_div_ck",
-        .user           = OCP_USER_SDMA,
-};
-static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
-        {
-                .pa_start       = 0x4e000000,
-                .pa_end         = 0x4e0007ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* mpu -> dmm */
-static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
-        .master         = &omap44xx_mpu_hwmod,
-        .slave          = &omap44xx_dmm_hwmod,
-        .clk            = "l3_div_ck",
-        .addr           = omap44xx_dmm_addrs,
-        .user           = OCP_USER_MPU,
-};
-/* dmm slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
-        &omap44xx_l3_main_1__dmm,
-        &omap44xx_mpu__dmm,
-};
 static struct omap_hwmod omap44xx_dmm_hwmod = {
        .name           = "dmm",
        .class          = &omap44xx_dmm_hwmod_class,
        .clkdm_name     = "l3_emif_clkdm",
+        .mpu_irqs       = omap44xx_dmm_irqs,
        .prcm = {
                .omap4 = {
                        .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
                        .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
                },
        },
-        .slaves         = omap44xx_dmm_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_dmm_slaves),
-        .mpu_irqs       = omap44xx_dmm_irqs,
 };
 /*
@@ -148,38 +107,6 @@ static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
 };
 /* emif_fw */
-/* dmm -> emif_fw */
-static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
-        .master         = &omap44xx_dmm_hwmod,
-        .slave          = &omap44xx_emif_fw_hwmod,
-        .clk            = "l3_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
-        {
-                .pa_start       = 0x4a20c000,
-                .pa_end         = 0x4a20c0ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_cfg -> emif_fw */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
-        .master         = &omap44xx_l4_cfg_hwmod,
-        .slave          = &omap44xx_emif_fw_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_emif_fw_addrs,
-        .user           = OCP_USER_MPU,
-};
-/* emif_fw slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = {
-        &omap44xx_dmm__emif_fw,
-        &omap44xx_l4_cfg__emif_fw,
-};
 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
        .name           = "emif_fw",
        .class          = &omap44xx_emif_fw_hwmod_class,
@@ -190,8 +117,6 @@ static struct omap_hwmod omap44xx_emif_fw_hwmod = {
                        .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
                },
        },
-        .slaves         = omap44xx_emif_fw_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_emif_fw_slaves),
 };
 /*
@@ -203,28 +128,6 @@ static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
 };
 /* l3_instr */
-/* iva -> l3_instr */
-static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
-        .master         = &omap44xx_iva_hwmod,
-        .slave          = &omap44xx_l3_instr_hwmod,
-        .clk            = "l3_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* l3_main_3 -> l3_instr */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
-        .master         = &omap44xx_l3_main_3_hwmod,
-        .slave          = &omap44xx_l3_instr_hwmod,
-        .clk            = "l3_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* l3_instr slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
-        &omap44xx_iva__l3_instr,
-        &omap44xx_l3_main_3__l3_instr,
-};
 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
        .name           = "l3_instr",
        .class          = &omap44xx_l3_hwmod_class,
@@ -236,8 +139,6 @@ static struct omap_hwmod omap44xx_l3_instr_hwmod = {
                        .modulemode   = MODULEMODE_HWCTRL,
                },
        },
-        .slaves         = omap44xx_l3_instr_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_instr_slaves),
 };
 /* l3_main_1 */
@@ -247,83 +148,6 @@ static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
        { .irq = -1 }
 };
-/* dsp -> l3_main_1 */
-static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
-        .master         = &omap44xx_dsp_hwmod,
-        .slave          = &omap44xx_l3_main_1_hwmod,
-        .clk            = "l3_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* dss -> l3_main_1 */
-static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
-        .master         = &omap44xx_dss_hwmod,
-        .slave          = &omap44xx_l3_main_1_hwmod,
-        .clk            = "l3_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* l3_main_2 -> l3_main_1 */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
-        .master         = &omap44xx_l3_main_2_hwmod,
-        .slave          = &omap44xx_l3_main_1_hwmod,
-        .clk            = "l3_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* l4_cfg -> l3_main_1 */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
-        .master         = &omap44xx_l4_cfg_hwmod,
-        .slave          = &omap44xx_l3_main_1_hwmod,
-        .clk            = "l4_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* mmc1 -> l3_main_1 */
-static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
-        .master         = &omap44xx_mmc1_hwmod,
-        .slave          = &omap44xx_l3_main_1_hwmod,
-        .clk            = "l3_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* mmc2 -> l3_main_1 */
-static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
-        .master         = &omap44xx_mmc2_hwmod,
-        .slave          = &omap44xx_l3_main_1_hwmod,
-        .clk            = "l3_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
-        {
-                .pa_start       = 0x44000000,
-                .pa_end         = 0x44000fff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* mpu -> l3_main_1 */
-static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
-        .master         = &omap44xx_mpu_hwmod,
-        .slave          = &omap44xx_l3_main_1_hwmod,
-        .clk            = "l3_div_ck",
-        .addr           = omap44xx_l3_main_1_addrs,
-        .user           = OCP_USER_MPU,
-};
-/* l3_main_1 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
-        &omap44xx_dsp__l3_main_1,
-        &omap44xx_dss__l3_main_1,
-        &omap44xx_l3_main_2__l3_main_1,
-        &omap44xx_l4_cfg__l3_main_1,
-        &omap44xx_mmc1__l3_main_1,
-        &omap44xx_mmc2__l3_main_1,
-        &omap44xx_mpu__l3_main_1,
-};
 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
        .name           = "l3_main_1",
        .class          = &omap44xx_l3_hwmod_class,
@@ -335,97 +159,9 @@ static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
                        .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
                },
        },
-        .slaves         = omap44xx_l3_main_1_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
 };
 /* l3_main_2 */
-/* dma_system -> l3_main_2 */
-static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
-        .master         = &omap44xx_dma_system_hwmod,
-        .slave          = &omap44xx_l3_main_2_hwmod,
-        .clk            = "l3_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* hsi -> l3_main_2 */
-static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
-        .master         = &omap44xx_hsi_hwmod,
-        .slave          = &omap44xx_l3_main_2_hwmod,
-        .clk            = "l3_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* ipu -> l3_main_2 */
-static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
-        .master         = &omap44xx_ipu_hwmod,
-        .slave          = &omap44xx_l3_main_2_hwmod,
-        .clk            = "l3_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* iss -> l3_main_2 */
-static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
-        .master         = &omap44xx_iss_hwmod,
-        .slave          = &omap44xx_l3_main_2_hwmod,
-        .clk            = "l3_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* iva -> l3_main_2 */
-static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
-        .master         = &omap44xx_iva_hwmod,
-        .slave          = &omap44xx_l3_main_2_hwmod,
-        .clk            = "l3_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
-        {
-                .pa_start       = 0x44800000,
-                .pa_end         = 0x44801fff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l3_main_1 -> l3_main_2 */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
-        .master         = &omap44xx_l3_main_1_hwmod,
-        .slave          = &omap44xx_l3_main_2_hwmod,
-        .clk            = "l3_div_ck",
-        .addr           = omap44xx_l3_main_2_addrs,
-        .user           = OCP_USER_MPU,
-};
-/* l4_cfg -> l3_main_2 */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
-        .master         = &omap44xx_l4_cfg_hwmod,
-        .slave          = &omap44xx_l3_main_2_hwmod,
-        .clk            = "l4_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* usb_otg_hs -> l3_main_2 */
-static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
-        .master         = &omap44xx_usb_otg_hs_hwmod,
-        .slave          = &omap44xx_l3_main_2_hwmod,
-        .clk            = "l3_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* l3_main_2 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
-        &omap44xx_dma_system__l3_main_2,
-        &omap44xx_hsi__l3_main_2,
-        &omap44xx_ipu__l3_main_2,
-        &omap44xx_iss__l3_main_2,
-        &omap44xx_iva__l3_main_2,
-        &omap44xx_l3_main_1__l3_main_2,
-        &omap44xx_l4_cfg__l3_main_2,
-        &omap44xx_usb_otg_hs__l3_main_2,
-};
 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
        .name           = "l3_main_2",
        .class          = &omap44xx_l3_hwmod_class,
@@ -436,52 +172,9 @@ static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
                        .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
                },
        },
-        .slaves         = omap44xx_l3_main_2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
 };
 /* l3_main_3 */
-static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
-        {
-                .pa_start       = 0x45000000,
-                .pa_end         = 0x45000fff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l3_main_1 -> l3_main_3 */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
-        .master         = &omap44xx_l3_main_1_hwmod,
-        .slave          = &omap44xx_l3_main_3_hwmod,
-        .clk            = "l3_div_ck",
-        .addr           = omap44xx_l3_main_3_addrs,
-        .user           = OCP_USER_MPU,
-};
-/* l3_main_2 -> l3_main_3 */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
-        .master         = &omap44xx_l3_main_2_hwmod,
-        .slave          = &omap44xx_l3_main_3_hwmod,
-        .clk            = "l3_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* l4_cfg -> l3_main_3 */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
-        .master         = &omap44xx_l4_cfg_hwmod,
-        .slave          = &omap44xx_l3_main_3_hwmod,
-        .clk            = "l4_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* l3_main_3 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = {
-        &omap44xx_l3_main_1__l3_main_3,
-        &omap44xx_l3_main_2__l3_main_3,
-        &omap44xx_l4_cfg__l3_main_3,
-};
 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
        .name           = "l3_main_3",
        .class          = &omap44xx_l3_hwmod_class,
@@ -493,8 +186,6 @@ static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
                        .modulemode   = MODULEMODE_HWCTRL,
                },
        },
-        .slaves         = omap44xx_l3_main_3_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
 };
 /*
@@ -506,46 +197,6 @@ static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 };
 /* l4_abe */
-/* aess -> l4_abe */
-static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = {
-        .master         = &omap44xx_aess_hwmod,
-        .slave          = &omap44xx_l4_abe_hwmod,
-        .clk            = "ocp_abe_iclk",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* dsp -> l4_abe */
-static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
-        .master         = &omap44xx_dsp_hwmod,
-        .slave          = &omap44xx_l4_abe_hwmod,
-        .clk            = "ocp_abe_iclk",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* l3_main_1 -> l4_abe */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
-        .master         = &omap44xx_l3_main_1_hwmod,
-        .slave          = &omap44xx_l4_abe_hwmod,
-        .clk            = "l3_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* mpu -> l4_abe */
-static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
-        .master         = &omap44xx_mpu_hwmod,
-        .slave          = &omap44xx_l4_abe_hwmod,
-        .clk            = "ocp_abe_iclk",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* l4_abe slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
-        &omap44xx_aess__l4_abe,
-        &omap44xx_dsp__l4_abe,
-        &omap44xx_l3_main_1__l4_abe,
-        &omap44xx_mpu__l4_abe,
-};
 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
        .name           = "l4_abe",
        .class          = &omap44xx_l4_hwmod_class,
@@ -555,24 +206,9 @@ static struct omap_hwmod omap44xx_l4_abe_hwmod = {
                        .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
                },
        },
-        .slaves         = omap44xx_l4_abe_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_abe_slaves),
 };
 /* l4_cfg */
-/* l3_main_1 -> l4_cfg */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
-        .master         = &omap44xx_l3_main_1_hwmod,
-        .slave          = &omap44xx_l4_cfg_hwmod,
-        .clk            = "l3_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* l4_cfg slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = {
-        &omap44xx_l3_main_1__l4_cfg,
-};
 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
        .name           = "l4_cfg",
        .class          = &omap44xx_l4_hwmod_class,
@@ -583,24 +219,9 @@ static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
                        .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
                },
        },
-        .slaves         = omap44xx_l4_cfg_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
 };
 /* l4_per */
-/* l3_main_2 -> l4_per */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
-        .master         = &omap44xx_l3_main_2_hwmod,
-        .slave          = &omap44xx_l4_per_hwmod,
-        .clk            = "l3_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* l4_per slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = {
-        &omap44xx_l3_main_2__l4_per,
-};
 static struct omap_hwmod omap44xx_l4_per_hwmod = {
        .name           = "l4_per",
        .class          = &omap44xx_l4_hwmod_class,
@@ -611,24 +232,9 @@ static struct omap_hwmod omap44xx_l4_per_hwmod = {
                        .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
                },
        },
-        .slaves         = omap44xx_l4_per_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_per_slaves),
 };
 /* l4_wkup */
-/* l4_cfg -> l4_wkup */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
-        .master         = &omap44xx_l4_cfg_hwmod,
-        .slave          = &omap44xx_l4_wkup_hwmod,
-        .clk            = "l4_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* l4_wkup slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = {
-        &omap44xx_l4_cfg__l4_wkup,
-};
 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
        .name           = "l4_wkup",
        .class          = &omap44xx_l4_hwmod_class,
@@ -639,8 +245,6 @@ static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
                        .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
                },
        },
-        .slaves         = omap44xx_l4_wkup_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
 };
 /*
@@ -652,25 +256,32 @@ static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 };
 /* mpu_private */
-/* mpu -> mpu_private */
-static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
-        .master         = &omap44xx_mpu_hwmod,
-        .slave          = &omap44xx_mpu_private_hwmod,
-        .clk            = "l3_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* mpu_private slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
-        &omap44xx_mpu__mpu_private,
-};
 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
        .name           = "mpu_private",
        .class          = &omap44xx_mpu_bus_hwmod_class,
        .clkdm_name     = "mpuss_clkdm",
-        .slaves         = omap44xx_mpu_private_slaves,
+};
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_mpu_private_slaves),
+/*
+ * 'ocp_wp_noc' class
+ * instance(s): ocp_wp_noc
+ */
+static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
+        .name   = "ocp_wp_noc",
+};
+/* ocp_wp_noc */
+static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
+        .name           = "ocp_wp_noc",
+        .class          = &omap44xx_ocp_wp_noc_hwmod_class,
+        .clkdm_name     = "l3_instr_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
 };
 /*
@@ -681,41 +292,7 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 * - They still need to be validated with the driver
 *   properly adapted to omap_hwmod / omap_device
 *
- *  c2c
+ * usim
- *  c2c_target_fw
- *  cm_core
- *  cm_core_aon
- *  ctrl_module_core
- *  ctrl_module_pad_core
- *  ctrl_module_pad_wkup
- *  ctrl_module_wkup
- *  debugss
- *  efuse_ctrl_cust
- *  efuse_ctrl_std
- *  elm
- *  emif1
- *  emif2
- *  fdif
- *  gpmc
- *  gpu
- *  hdq1w
- *  mcasp
- *  mpu_c0
- *  mpu_c1
- *  ocmc_ram
- *  ocp2scp_usb_phy
- *  ocp_wp_noc
- *  prcm_mpu
- *  prm
- *  scrm
- *  sl2if
- *  slimbus1
- *  slimbus2
- *  usb_host_fs
- *  usb_host_hs
- *  usb_phy_cm
- *  usb_tll_hs
- *  usim
 */
 /*
@@ -756,53 +333,6 @@ static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
        { .dma_req = -1 }
 };
-/* aess master ports */
-static struct omap_hwmod_ocp_if *omap44xx_aess_masters[] = {
-        &omap44xx_aess__l4_abe,
-};
-static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
-        {
-                .pa_start       = 0x401f1000,
-                .pa_end         = 0x401f13ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_abe -> aess */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = {
-        .master         = &omap44xx_l4_abe_hwmod,
-        .slave          = &omap44xx_aess_hwmod,
-        .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_aess_addrs,
-        .user           = OCP_USER_MPU,
-};
-static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
-        {
-                .pa_start       = 0x490f1000,
-                .pa_end         = 0x490f13ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_abe -> aess (dma) */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = {
-        .master         = &omap44xx_l4_abe_hwmod,
-        .slave          = &omap44xx_aess_hwmod,
-        .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_aess_dma_addrs,
-        .user           = OCP_USER_SDMA,
-};
-/* aess slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_aess_slaves[] = {
-        &omap44xx_l4_abe__aess,
-        &omap44xx_l4_abe__aess_dma,
-};
 static struct omap_hwmod omap44xx_aess_hwmod = {
        .name           = "aess",
        .class          = &omap44xx_aess_hwmod_class,
@@ -817,37 +347,41 @@ static struct omap_hwmod omap44xx_aess_hwmod = {
                        .modulemode   = MODULEMODE_SWCTRL,
                },
        },
-        .slaves         = omap44xx_aess_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_aess_slaves),
-        .masters        = omap44xx_aess_masters,
-        .masters_cnt    = ARRAY_SIZE(omap44xx_aess_masters),
 };
 /*
- * 'bandgap' class
+ * 'c2c' class
- * bangap reference for ldo regulators
+ * chip 2 chip interface used to plug the ape soc (omap) with an external modem
+ * soc
 */
-static struct omap_hwmod_class omap44xx_bandgap_hwmod_class = {
+static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
-        .name   = "bandgap",
+        .name   = "c2c",
 };
-/* bandgap */
+/* c2c */
-static struct omap_hwmod_opt_clk bandgap_opt_clks[] = {
+static struct omap_hwmod_irq_info omap44xx_c2c_irqs[] = {
-        { .role = "fclk", .clk = "bandgap_fclk" },
+        { .irq = 88 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
 };
-static struct omap_hwmod omap44xx_bandgap_hwmod = {
+static struct omap_hwmod_dma_info omap44xx_c2c_sdma_reqs[] = {
-        .name           = "bandgap",
+        { .dma_req = 68 + OMAP44XX_DMA_REQ_START },
-        .class          = &omap44xx_bandgap_hwmod_class,
+        { .dma_req = -1 }
-        .clkdm_name     = "l4_wkup_clkdm",
+};
+static struct omap_hwmod omap44xx_c2c_hwmod = {
+        .name           = "c2c",
+        .class          = &omap44xx_c2c_hwmod_class,
+        .clkdm_name     = "d2d_clkdm",
+        .mpu_irqs       = omap44xx_c2c_irqs,
+        .sdma_reqs      = omap44xx_c2c_sdma_reqs,
        .prcm = {
                .omap4 = {
-                        .clkctrl_offs = OMAP4_CM_WKUP_BANDGAP_CLKCTRL_OFFSET,
+                        .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET,
                },
        },
-        .opt_clks       = bandgap_opt_clks,
-        .opt_clks_cnt   = ARRAY_SIZE(bandgap_opt_clks),
 };
 /*
@@ -870,30 +404,6 @@ static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
 };
 /* counter_32k */
-static struct omap_hwmod omap44xx_counter_32k_hwmod;
-static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
-        {
-                .pa_start       = 0x4a304000,
-                .pa_end         = 0x4a30401f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_wkup -> counter_32k */
-static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
-        .master         = &omap44xx_l4_wkup_hwmod,
-        .slave          = &omap44xx_counter_32k_hwmod,
-        .clk            = "l4_wkup_clk_mux_ck",
-        .addr           = omap44xx_counter_32k_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* counter_32k slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_counter_32k_slaves[] = {
-        &omap44xx_l4_wkup__counter_32k,
-};
 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
        .name           = "counter_32k",
        .class          = &omap44xx_counter_hwmod_class,
@@ -906,8 +416,83 @@ static struct omap_hwmod omap44xx_counter_32k_hwmod = {
                        .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
                },
        },
-        .slaves         = omap44xx_counter_32k_slaves,
+};
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_counter_32k_slaves),
+/*
+ * 'ctrl_module' class
+ * attila core control module + core pad control module + wkup pad control
+ * module + attila wkup control module
+ */
+static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = SYSC_HAS_SIDLEMODE,
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
+        .name   = "ctrl_module",
+        .sysc   = &omap44xx_ctrl_module_sysc,
+};
+/* ctrl_module_core */
+static struct omap_hwmod_irq_info omap44xx_ctrl_module_core_irqs[] = {
+        { .irq = 8 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
+};
+static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
+        .name           = "ctrl_module_core",
+        .class          = &omap44xx_ctrl_module_hwmod_class,
+        .clkdm_name     = "l4_cfg_clkdm",
+        .mpu_irqs       = omap44xx_ctrl_module_core_irqs,
+};
+/* ctrl_module_pad_core */
+static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
+        .name           = "ctrl_module_pad_core",
+        .class          = &omap44xx_ctrl_module_hwmod_class,
+        .clkdm_name     = "l4_cfg_clkdm",
+};
+/* ctrl_module_wkup */
+static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
+        .name           = "ctrl_module_wkup",
+        .class          = &omap44xx_ctrl_module_hwmod_class,
+        .clkdm_name     = "l4_wkup_clkdm",
+};
+/* ctrl_module_pad_wkup */
+static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
+        .name           = "ctrl_module_pad_wkup",
+        .class          = &omap44xx_ctrl_module_hwmod_class,
+        .clkdm_name     = "l4_wkup_clkdm",
+};
+/*
+ * 'debugss' class
+ * debug and emulation sub system
+ */
+static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
+        .name   = "debugss",
+};
+/* debugss */
+static struct omap_hwmod omap44xx_debugss_hwmod = {
+        .name           = "debugss",
+        .class          = &omap44xx_debugss_hwmod_class,
+        .clkdm_name     = "emu_sys_clkdm",
+        .main_clk       = "trace_clk_div_ck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
+                },
+        },
 };
 /*
@@ -950,34 +535,6 @@ static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
        { .irq = -1 }
 };
-/* dma_system master ports */
-static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = {
-        &omap44xx_dma_system__l3_main_2,
-};
-static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
-        {
-                .pa_start       = 0x4a056000,
-                .pa_end         = 0x4a056fff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_cfg -> dma_system */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
-        .master         = &omap44xx_l4_cfg_hwmod,
-        .slave          = &omap44xx_dma_system_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_dma_system_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* dma_system slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = {
-        &omap44xx_l4_cfg__dma_system,
-};
 static struct omap_hwmod omap44xx_dma_system_hwmod = {
        .name           = "dma_system",
        .class          = &omap44xx_dma_hwmod_class,
@@ -991,10 +548,6 @@ static struct omap_hwmod omap44xx_dma_system_hwmod = {
                },
        },
        .dev_attr       = &dma_dev_attr,
-        .slaves         = omap44xx_dma_system_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_dma_system_slaves),
-        .masters        = omap44xx_dma_system_masters,
-        .masters_cnt    = ARRAY_SIZE(omap44xx_dma_system_masters),
 };
 /*
@@ -1018,7 +571,6 @@ static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
 };
 /* dmic */
-static struct omap_hwmod omap44xx_dmic_hwmod;
 static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
        { .irq = 114 + OMAP44XX_IRQ_GIC_START },
        { .irq = -1 }
@@ -1029,50 +581,6 @@ static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
        { .dma_req = -1 }
 };
-static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
-        {
-                .name           = "mpu",
-                .pa_start       = 0x4012e000,
-                .pa_end         = 0x4012e07f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_abe -> dmic */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
-        .master         = &omap44xx_l4_abe_hwmod,
-        .slave          = &omap44xx_dmic_hwmod,
-        .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_dmic_addrs,
-        .user           = OCP_USER_MPU,
-};
-static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
-        {
-                .name           = "dma",
-                .pa_start       = 0x4902e000,
-                .pa_end         = 0x4902e07f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_abe -> dmic (dma) */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
-        .master         = &omap44xx_l4_abe_hwmod,
-        .slave          = &omap44xx_dmic_hwmod,
-        .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_dmic_dma_addrs,
-        .user           = OCP_USER_SDMA,
-};
-/* dmic slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_dmic_slaves[] = {
-        &omap44xx_l4_abe__dmic,
-        &omap44xx_l4_abe__dmic_dma,
-};
 static struct omap_hwmod omap44xx_dmic_hwmod = {
        .name           = "dmic",
        .class          = &omap44xx_dmic_hwmod_class,
@@ -1087,8 +595,6 @@ static struct omap_hwmod omap44xx_dmic_hwmod = {
                        .modulemode   = MODULEMODE_SWCTRL,
                },
        },
-        .slaves         = omap44xx_dmic_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_dmic_slaves),
 };
 /*
@@ -1107,53 +613,8 @@ static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
 };
 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
-        { .name = "mmu_cache", .rst_shift = 1 },
-};
-static struct omap_hwmod_rst_info omap44xx_dsp_c0_resets[] = {
        { .name = "dsp", .rst_shift = 0 },
-};
+        { .name = "mmu_cache", .rst_shift = 1 },
-/* dsp -> iva */
-static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
-        .master         = &omap44xx_dsp_hwmod,
-        .slave          = &omap44xx_iva_hwmod,
-        .clk            = "dpll_iva_m5x2_ck",
-};
-/* dsp master ports */
-static struct omap_hwmod_ocp_if *omap44xx_dsp_masters[] = {
-        &omap44xx_dsp__l3_main_1,
-        &omap44xx_dsp__l4_abe,
-        &omap44xx_dsp__iva,
-};
-/* l4_cfg -> dsp */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
-        .master         = &omap44xx_l4_cfg_hwmod,
-        .slave          = &omap44xx_dsp_hwmod,
-        .clk            = "l4_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* dsp slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = {
-        &omap44xx_l4_cfg__dsp,
-};
-/* Pseudo hwmod for reset control purpose only */
-static struct omap_hwmod omap44xx_dsp_c0_hwmod = {
-        .name           = "dsp_c0",
-        .class          = &omap44xx_dsp_hwmod_class,
-        .clkdm_name     = "tesla_clkdm",
-        .flags          = HWMOD_INIT_NO_RESET,
-        .rst_lines      = omap44xx_dsp_c0_resets,
-        .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_c0_resets),
-        .prcm = {
-                .omap4 = {
-                        .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
-                },
-        },
 };
 static struct omap_hwmod omap44xx_dsp_hwmod = {
@@ -1172,10 +633,6 @@ static struct omap_hwmod omap44xx_dsp_hwmod = {
                        .modulemode   = MODULEMODE_HWCTRL,
                },
        },
-        .slaves         = omap44xx_dsp_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_dsp_slaves),
-        .masters        = omap44xx_dsp_masters,
-        .masters_cnt    = ARRAY_SIZE(omap44xx_dsp_masters),
 };
 /*
@@ -1196,53 +653,6 @@ static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
 };
 /* dss */
-/* dss master ports */
-static struct omap_hwmod_ocp_if *omap44xx_dss_masters[] = {
-        &omap44xx_dss__l3_main_1,
-};
-static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
-        {
-                .pa_start       = 0x58000000,
-                .pa_end         = 0x5800007f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l3_main_2 -> dss */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
-        .master         = &omap44xx_l3_main_2_hwmod,
-        .slave          = &omap44xx_dss_hwmod,
-        .clk            = "dss_fck",
-        .addr           = omap44xx_dss_dma_addrs,
-        .user           = OCP_USER_SDMA,
-};
-static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
-        {
-                .pa_start       = 0x48040000,
-                .pa_end         = 0x4804007f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_per -> dss */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_dss_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_dss_addrs,
-        .user           = OCP_USER_MPU,
-};
-/* dss slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = {
-        &omap44xx_l3_main_2__dss,
-        &omap44xx_l4_per__dss,
-};
 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
        { .role = "sys_clk", .clk = "dss_sys_clk" },
        { .role = "tv_clk", .clk = "dss_tv_clk" },
@@ -1263,10 +673,6 @@ static struct omap_hwmod omap44xx_dss_hwmod = {
        },
        .opt_clks       = dss_opt_clks,
        .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
-        .slaves         = omap44xx_dss_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_slaves),
-        .masters        = omap44xx_dss_masters,
-        .masters_cnt    = ARRAY_SIZE(omap44xx_dss_masters),
 };
 /*
@@ -1293,7 +699,6 @@ static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
 };
 /* dss_dispc */
-static struct omap_hwmod omap44xx_dss_dispc_hwmod;
 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
        { .irq = 25 + OMAP44XX_IRQ_GIC_START },
        { .irq = -1 }
@@ -1304,53 +709,11 @@ static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
        { .dma_req = -1 }
 };
-static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
-        {
-                .pa_start       = 0x58001000,
-                .pa_end         = 0x58001fff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l3_main_2 -> dss_dispc */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
-        .master         = &omap44xx_l3_main_2_hwmod,
-        .slave          = &omap44xx_dss_dispc_hwmod,
-        .clk            = "dss_fck",
-        .addr           = omap44xx_dss_dispc_dma_addrs,
-        .user           = OCP_USER_SDMA,
-};
-static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
-        {
-                .pa_start       = 0x48041000,
-                .pa_end         = 0x48041fff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
        .manager_count          = 3,
        .has_framedonetv_irq    = 1
 };
-/* l4_per -> dss_dispc */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_dss_dispc_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_dss_dispc_addrs,
-        .user           = OCP_USER_MPU,
-};
-/* dss_dispc slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = {
-        &omap44xx_l3_main_2__dss_dispc,
-        &omap44xx_l4_per__dss_dispc,
-};
 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
        .name           = "dss_dispc",
        .class          = &omap44xx_dispc_hwmod_class,
@@ -1364,8 +727,6 @@ static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
                        .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
                },
        },
-        .slaves         = omap44xx_dss_dispc_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dispc_slaves),
        .dev_attr       = &omap44xx_dss_dispc_dev_attr
 };
@@ -1391,7 +752,6 @@ static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
 };
 /* dss_dsi1 */
-static struct omap_hwmod omap44xx_dss_dsi1_hwmod;
 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
        { .irq = 53 + OMAP44XX_IRQ_GIC_START },
        { .irq = -1 }
@@ -1402,48 +762,6 @@ static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
        { .dma_req = -1 }
 };
-static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
-        {
-                .pa_start       = 0x58004000,
-                .pa_end         = 0x580041ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l3_main_2 -> dss_dsi1 */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
-        .master         = &omap44xx_l3_main_2_hwmod,
-        .slave          = &omap44xx_dss_dsi1_hwmod,
-        .clk            = "dss_fck",
-        .addr           = omap44xx_dss_dsi1_dma_addrs,
-        .user           = OCP_USER_SDMA,
-};
-static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
-        {
-                .pa_start       = 0x48044000,
-                .pa_end         = 0x480441ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_per -> dss_dsi1 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_dss_dsi1_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_dss_dsi1_addrs,
-        .user           = OCP_USER_MPU,
-};
-/* dss_dsi1 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_dss_dsi1_slaves[] = {
-        &omap44xx_l3_main_2__dss_dsi1,
-        &omap44xx_l4_per__dss_dsi1,
-};
 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
        { .role = "sys_clk", .clk = "dss_sys_clk" },
 };
@@ -1463,12 +781,9 @@ static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
        },
        .opt_clks       = dss_dsi1_opt_clks,
        .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
-        .slaves         = omap44xx_dss_dsi1_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dsi1_slaves),
 };
 /* dss_dsi2 */
-static struct omap_hwmod omap44xx_dss_dsi2_hwmod;
 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
        { .irq = 84 + OMAP44XX_IRQ_GIC_START },
        { .irq = -1 }
@@ -1479,48 +794,6 @@ static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
        { .dma_req = -1 }
 };
-static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
-        {
-                .pa_start       = 0x58005000,
-                .pa_end         = 0x580051ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l3_main_2 -> dss_dsi2 */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
-        .master         = &omap44xx_l3_main_2_hwmod,
-        .slave          = &omap44xx_dss_dsi2_hwmod,
-        .clk            = "dss_fck",
-        .addr           = omap44xx_dss_dsi2_dma_addrs,
-        .user           = OCP_USER_SDMA,
-};
-static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
-        {
-                .pa_start       = 0x48045000,
-                .pa_end         = 0x480451ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_per -> dss_dsi2 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_dss_dsi2_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_dss_dsi2_addrs,
-        .user           = OCP_USER_MPU,
-};
-/* dss_dsi2 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_dss_dsi2_slaves[] = {
-        &omap44xx_l3_main_2__dss_dsi2,
-        &omap44xx_l4_per__dss_dsi2,
-};
 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
        { .role = "sys_clk", .clk = "dss_sys_clk" },
 };
@@ -1540,8 +813,6 @@ static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
        },
        .opt_clks       = dss_dsi2_opt_clks,
        .opt_clks_cnt   = ARRAY_SIZE(dss_dsi2_opt_clks),
-        .slaves         = omap44xx_dss_dsi2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dsi2_slaves),
 };
 /*
@@ -1565,7 +836,6 @@ static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
 };
 /* dss_hdmi */
-static struct omap_hwmod omap44xx_dss_hdmi_hwmod;
 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
        { .irq = 101 + OMAP44XX_IRQ_GIC_START },
        { .irq = -1 }
@@ -1576,48 +846,6 @@ static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
        { .dma_req = -1 }
 };
-static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
-        {
-                .pa_start       = 0x58006000,
-                .pa_end         = 0x58006fff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l3_main_2 -> dss_hdmi */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
-        .master         = &omap44xx_l3_main_2_hwmod,
-        .slave          = &omap44xx_dss_hdmi_hwmod,
-        .clk            = "dss_fck",
-        .addr           = omap44xx_dss_hdmi_dma_addrs,
-        .user           = OCP_USER_SDMA,
-};
-static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
-        {
-                .pa_start       = 0x48046000,
-                .pa_end         = 0x48046fff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_per -> dss_hdmi */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_dss_hdmi_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_dss_hdmi_addrs,
-        .user           = OCP_USER_MPU,
-};
-/* dss_hdmi slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_dss_hdmi_slaves[] = {
-        &omap44xx_l3_main_2__dss_hdmi,
-        &omap44xx_l4_per__dss_hdmi,
-};
 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
        { .role = "sys_clk", .clk = "dss_sys_clk" },
 };
@@ -1637,8 +865,6 @@ static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
        },
        .opt_clks       = dss_hdmi_opt_clks,
        .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
-        .slaves         = omap44xx_dss_hdmi_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_hdmi_slaves),
 };
 /*
@@ -1662,54 +888,11 @@ static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
 };
 /* dss_rfbi */
-static struct omap_hwmod omap44xx_dss_rfbi_hwmod;
 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
        { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
        { .dma_req = -1 }
 };
-static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
-        {
-                .pa_start       = 0x58002000,
-                .pa_end         = 0x580020ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l3_main_2 -> dss_rfbi */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
-        .master         = &omap44xx_l3_main_2_hwmod,
-        .slave          = &omap44xx_dss_rfbi_hwmod,
-        .clk            = "dss_fck",
-        .addr           = omap44xx_dss_rfbi_dma_addrs,
-        .user           = OCP_USER_SDMA,
-};
-static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
-        {
-                .pa_start       = 0x48042000,
-                .pa_end         = 0x480420ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_per -> dss_rfbi */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_dss_rfbi_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_dss_rfbi_addrs,
-        .user           = OCP_USER_MPU,
-};
-/* dss_rfbi slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_dss_rfbi_slaves[] = {
-        &omap44xx_l3_main_2__dss_rfbi,
-        &omap44xx_l4_per__dss_rfbi,
-};
 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
        { .role = "ick", .clk = "dss_fck" },
 };
@@ -1728,8 +911,6 @@ static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
        },
        .opt_clks       = dss_rfbi_opt_clks,
        .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
-        .slaves         = omap44xx_dss_rfbi_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_rfbi_slaves),
 };
 /*
@@ -1742,62 +923,165 @@ static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
 };
 /* dss_venc */
-static struct omap_hwmod omap44xx_dss_venc_hwmod;
+static struct omap_hwmod omap44xx_dss_venc_hwmod = {
-static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
+        .name           = "dss_venc",
-        {
+        .class          = &omap44xx_venc_hwmod_class,
-                .pa_start       = 0x58003000,
+        .clkdm_name     = "l3_dss_clkdm",
-                .pa_end         = 0x580030ff,
+        .main_clk       = "dss_tv_clk",
-                .flags          = ADDR_TYPE_RT
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
+                },
        },
-        { }
 };
-/* l3_main_2 -> dss_venc */
+/*
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
+ * 'elm' class
-        .master         = &omap44xx_l3_main_2_hwmod,
+ * bch error location module
-        .slave          = &omap44xx_dss_venc_hwmod,
+ */
-        .clk            = "dss_fck",
-        .addr           = omap44xx_dss_venc_dma_addrs,
+static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = {
-        .user           = OCP_USER_SDMA,
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+                           SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
 };
-static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
+static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
-        {
+        .name   = "elm",
-                .pa_start       = 0x48043000,
+        .sysc   = &omap44xx_elm_sysc,
-                .pa_end         = 0x480430ff,
+};
-                .flags          = ADDR_TYPE_RT
+/* elm */
+static struct omap_hwmod_irq_info omap44xx_elm_irqs[] = {
+        { .irq = 4 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
+};
+static struct omap_hwmod omap44xx_elm_hwmod = {
+        .name           = "elm",
+        .class          = &omap44xx_elm_hwmod_class,
+        .clkdm_name     = "l4_per_clkdm",
+        .mpu_irqs       = omap44xx_elm_irqs,
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET,
+                },
        },
-        { }
 };
-/* l4_per -> dss_venc */
+/*
-static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
+ * 'emif' class
-        .master         = &omap44xx_l4_per_hwmod,
+ * external memory interface no1
-        .slave          = &omap44xx_dss_venc_hwmod,
+ */
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_dss_venc_addrs,
+static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
-        .user           = OCP_USER_MPU,
+        .rev_offs       = 0x0000,
 };
-/* dss_venc slave ports */
+static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
-static struct omap_hwmod_ocp_if *omap44xx_dss_venc_slaves[] = {
+        .name   = "emif",
-        &omap44xx_l3_main_2__dss_venc,
+        .sysc   = &omap44xx_emif_sysc,
-        &omap44xx_l4_per__dss_venc,
 };
-static struct omap_hwmod omap44xx_dss_venc_hwmod = {
+/* emif1 */
-        .name           = "dss_venc",
+static struct omap_hwmod_irq_info omap44xx_emif1_irqs[] = {
-        .class          = &omap44xx_venc_hwmod_class,
+        { .irq = 110 + OMAP44XX_IRQ_GIC_START },
-        .clkdm_name     = "l3_dss_clkdm",
+        { .irq = -1 }
-        .main_clk       = "dss_tv_clk",
+};
+static struct omap_hwmod omap44xx_emif1_hwmod = {
+        .name           = "emif1",
+        .class          = &omap44xx_emif_hwmod_class,
+        .clkdm_name     = "l3_emif_clkdm",
+        .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
+        .mpu_irqs       = omap44xx_emif1_irqs,
+        .main_clk       = "ddrphy_ck",
        .prcm = {
                .omap4 = {
-                        .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
+                        .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
-                        .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
+                        .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+};
+/* emif2 */
+static struct omap_hwmod_irq_info omap44xx_emif2_irqs[] = {
+        { .irq = 111 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
+};
+static struct omap_hwmod omap44xx_emif2_hwmod = {
+        .name           = "emif2",
+        .class          = &omap44xx_emif_hwmod_class,
+        .clkdm_name     = "l3_emif_clkdm",
+        .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
+        .mpu_irqs       = omap44xx_emif2_irqs,
+        .main_clk       = "ddrphy_ck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+};
+/*
+ * 'fdif' class
+ * face detection hw accelerator module
+ */
+static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        /*
+         * FDIF needs 100 OCP clk cycles delay after a softreset before
+         * accessing sysconfig again.
+         * The lowest frequency at the moment for L3 bus is 100 MHz, so
+         * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
+         *
+         * TODO: Indicate errata when available.
+         */
+        .srst_udelay    = 2,
+        .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
+        .name   = "fdif",
+        .sysc   = &omap44xx_fdif_sysc,
+};
+/* fdif */
+static struct omap_hwmod_irq_info omap44xx_fdif_irqs[] = {
+        { .irq = 69 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
+};
+static struct omap_hwmod omap44xx_fdif_hwmod = {
+        .name           = "fdif",
+        .class          = &omap44xx_fdif_hwmod_class,
+        .clkdm_name     = "iss_clkdm",
+        .mpu_irqs       = omap44xx_fdif_irqs,
+        .main_clk       = "fdif_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
                },
        },
-        .slaves         = omap44xx_dss_venc_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_venc_slaves),
 };
 /*
@@ -1830,35 +1114,11 @@ static struct omap_gpio_dev_attr gpio_dev_attr = {
 };
 /* gpio1 */
-static struct omap_hwmod omap44xx_gpio1_hwmod;
 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
        { .irq = 29 + OMAP44XX_IRQ_GIC_START },
        { .irq = -1 }
 };
-static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
-        {
-                .pa_start       = 0x4a310000,
-                .pa_end         = 0x4a3101ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_wkup -> gpio1 */
-static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
-        .master         = &omap44xx_l4_wkup_hwmod,
-        .slave          = &omap44xx_gpio1_hwmod,
-        .clk            = "l4_wkup_clk_mux_ck",
-        .addr           = omap44xx_gpio1_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* gpio1 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = {
-        &omap44xx_l4_wkup__gpio1,
-};
 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
        { .role = "dbclk", .clk = "gpio1_dbclk" },
 };
@@ -1879,40 +1139,14 @@ static struct omap_hwmod omap44xx_gpio1_hwmod = {
        .opt_clks       = gpio1_opt_clks,
        .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
        .dev_attr       = &gpio_dev_attr,
-        .slaves         = omap44xx_gpio1_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio1_slaves),
 };
 /* gpio2 */
-static struct omap_hwmod omap44xx_gpio2_hwmod;
 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
        { .irq = 30 + OMAP44XX_IRQ_GIC_START },
        { .irq = -1 }
 };
-static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
-        {
-                .pa_start       = 0x48055000,
-                .pa_end         = 0x480551ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_per -> gpio2 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_gpio2_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_gpio2_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* gpio2 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = {
-        &omap44xx_l4_per__gpio2,
-};
 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
        { .role = "dbclk", .clk = "gpio2_dbclk" },
 };
@@ -1934,40 +1168,14 @@ static struct omap_hwmod omap44xx_gpio2_hwmod = {
        .opt_clks       = gpio2_opt_clks,
        .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
        .dev_attr       = &gpio_dev_attr,
-        .slaves         = omap44xx_gpio2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio2_slaves),
 };
 /* gpio3 */
-static struct omap_hwmod omap44xx_gpio3_hwmod;
 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
        { .irq = 31 + OMAP44XX_IRQ_GIC_START },
        { .irq = -1 }
 };
-static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
-        {
-                .pa_start       = 0x48057000,
-                .pa_end         = 0x480571ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_per -> gpio3 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_gpio3_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_gpio3_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* gpio3 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = {
-        &omap44xx_l4_per__gpio3,
-};
 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
        { .role = "dbclk", .clk = "gpio3_dbclk" },
 };
@@ -1989,40 +1197,14 @@ static struct omap_hwmod omap44xx_gpio3_hwmod = {
        .opt_clks       = gpio3_opt_clks,
        .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
        .dev_attr       = &gpio_dev_attr,
-        .slaves         = omap44xx_gpio3_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio3_slaves),
 };
 /* gpio4 */
-static struct omap_hwmod omap44xx_gpio4_hwmod;
 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
        { .irq = 32 + OMAP44XX_IRQ_GIC_START },
        { .irq = -1 }
 };
-static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
-        {
-                .pa_start       = 0x48059000,
-                .pa_end         = 0x480591ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_per -> gpio4 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_gpio4_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_gpio4_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* gpio4 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = {
-        &omap44xx_l4_per__gpio4,
-};
 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
        { .role = "dbclk", .clk = "gpio4_dbclk" },
 };
@@ -2044,40 +1226,14 @@ static struct omap_hwmod omap44xx_gpio4_hwmod = {
        .opt_clks       = gpio4_opt_clks,
        .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
        .dev_attr       = &gpio_dev_attr,
-        .slaves         = omap44xx_gpio4_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio4_slaves),
 };
 /* gpio5 */
-static struct omap_hwmod omap44xx_gpio5_hwmod;
 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
        { .irq = 33 + OMAP44XX_IRQ_GIC_START },
        { .irq = -1 }
 };
-static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
-        {
-                .pa_start       = 0x4805b000,
-                .pa_end         = 0x4805b1ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_per -> gpio5 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_gpio5_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_gpio5_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* gpio5 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = {
-        &omap44xx_l4_per__gpio5,
-};
 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
        { .role = "dbclk", .clk = "gpio5_dbclk" },
 };
@@ -2099,40 +1255,14 @@ static struct omap_hwmod omap44xx_gpio5_hwmod = {
        .opt_clks       = gpio5_opt_clks,
        .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
        .dev_attr       = &gpio_dev_attr,
-        .slaves         = omap44xx_gpio5_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio5_slaves),
 };
 /* gpio6 */
-static struct omap_hwmod omap44xx_gpio6_hwmod;
 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
        { .irq = 34 + OMAP44XX_IRQ_GIC_START },
        { .irq = -1 }
 };
-static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
-        {
-                .pa_start       = 0x4805d000,
-                .pa_end         = 0x4805d1ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_per -> gpio6 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_gpio6_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_gpio6_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* gpio6 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = {
-        &omap44xx_l4_per__gpio6,
-};
 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
        { .role = "dbclk", .clk = "gpio6_dbclk" },
 };
@@ -2154,8 +1284,135 @@ static struct omap_hwmod omap44xx_gpio6_hwmod = {
        .opt_clks       = gpio6_opt_clks,
        .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
        .dev_attr       = &gpio_dev_attr,
-        .slaves         = omap44xx_gpio6_slaves,
+};
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio6_slaves),
+/*
+ * 'gpmc' class
+ * general purpose memory controller
+ */
+static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
+        .name   = "gpmc",
+        .sysc   = &omap44xx_gpmc_sysc,
+};
+/* gpmc */
+static struct omap_hwmod_irq_info omap44xx_gpmc_irqs[] = {
+        { .irq = 20 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
+};
+static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs[] = {
+        { .dma_req = 3 + OMAP44XX_DMA_REQ_START },
+        { .dma_req = -1 }
+};
+static struct omap_hwmod omap44xx_gpmc_hwmod = {
+        .name           = "gpmc",
+        .class          = &omap44xx_gpmc_hwmod_class,
+        .clkdm_name     = "l3_2_clkdm",
+        .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
+        .mpu_irqs       = omap44xx_gpmc_irqs,
+        .sdma_reqs      = omap44xx_gpmc_sdma_reqs,
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+};
+/*
+ * 'gpu' class
+ * 2d/3d graphics accelerator
+ */
+static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = {
+        .rev_offs       = 0x1fc00,
+        .sysc_offs      = 0x1fc10,
+        .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+                           MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
+        .name   = "gpu",
+        .sysc   = &omap44xx_gpu_sysc,
+};
+/* gpu */
+static struct omap_hwmod_irq_info omap44xx_gpu_irqs[] = {
+        { .irq = 21 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
+};
+static struct omap_hwmod omap44xx_gpu_hwmod = {
+        .name           = "gpu",
+        .class          = &omap44xx_gpu_hwmod_class,
+        .clkdm_name     = "l3_gfx_clkdm",
+        .mpu_irqs       = omap44xx_gpu_irqs,
+        .main_clk       = "gpu_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/*
+ * 'hdq1w' class
+ * hdq / 1-wire serial interface controller
+ */
+static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0014,
+        .syss_offs      = 0x0018,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
+                           SYSS_HAS_RESET_STATUS),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
+        .name   = "hdq1w",
+        .sysc   = &omap44xx_hdq1w_sysc,
+};
+/* hdq1w */
+static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs[] = {
+        { .irq = 58 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
+};
+static struct omap_hwmod omap44xx_hdq1w_hwmod = {
+        .name           = "hdq1w",
+        .class          = &omap44xx_hdq1w_hwmod_class,
+        .clkdm_name     = "l4_per_clkdm",
+        .flags          = HWMOD_INIT_NO_RESET, /* XXX temporary */
+        .mpu_irqs       = omap44xx_hdq1w_irqs,
+        .main_clk       = "hdq1w_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
 };
 /*
@@ -2190,34 +1447,6 @@ static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
        { .irq = -1 }
 };
-/* hsi master ports */
-static struct omap_hwmod_ocp_if *omap44xx_hsi_masters[] = {
-        &omap44xx_hsi__l3_main_2,
-};
-static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
-        {
-                .pa_start       = 0x4a058000,
-                .pa_end         = 0x4a05bfff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_cfg -> hsi */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
-        .master         = &omap44xx_l4_cfg_hwmod,
-        .slave          = &omap44xx_hsi_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_hsi_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* hsi slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_hsi_slaves[] = {
-        &omap44xx_l4_cfg__hsi,
-};
 static struct omap_hwmod omap44xx_hsi_hwmod = {
        .name           = "hsi",
        .class          = &omap44xx_hsi_hwmod_class,
@@ -2231,10 +1460,6 @@ static struct omap_hwmod omap44xx_hsi_hwmod = {
                        .modulemode   = MODULEMODE_HWCTRL,
                },
        },
-        .slaves         = omap44xx_hsi_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_hsi_slaves),
-        .masters        = omap44xx_hsi_masters,
-        .masters_cnt    = ARRAY_SIZE(omap44xx_hsi_masters),
 };
 /*
@@ -2262,11 +1487,11 @@ static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
 };
 static struct omap_i2c_dev_attr i2c_dev_attr = {
-        .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
+        .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE |
+                        OMAP_I2C_FLAG_RESET_REGS_POSTIDLE,
 };
 /* i2c1 */
-static struct omap_hwmod omap44xx_i2c1_hwmod;
 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
        { .irq = 56 + OMAP44XX_IRQ_GIC_START },
        { .irq = -1 }
@@ -2278,29 +1503,6 @@ static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
        { .dma_req = -1 }
 };
-static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
-        {
-                .pa_start       = 0x48070000,
-                .pa_end         = 0x480700ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_per -> i2c1 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_i2c1_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_i2c1_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* i2c1 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
-        &omap44xx_l4_per__i2c1,
-};
 static struct omap_hwmod omap44xx_i2c1_hwmod = {
        .name           = "i2c1",
        .class          = &omap44xx_i2c_hwmod_class,
@@ -2316,13 +1518,10 @@ static struct omap_hwmod omap44xx_i2c1_hwmod = {
                        .modulemode   = MODULEMODE_SWCTRL,
                },
        },
-        .slaves         = omap44xx_i2c1_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c1_slaves),
        .dev_attr       = &i2c_dev_attr,
 };
 /* i2c2 */
-static struct omap_hwmod omap44xx_i2c2_hwmod;
 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
        { .irq = 57 + OMAP44XX_IRQ_GIC_START },
        { .irq = -1 }
@@ -2334,29 +1533,6 @@ static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
        { .dma_req = -1 }
 };
-static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
-        {
-                .pa_start       = 0x48072000,
-                .pa_end         = 0x480720ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_per -> i2c2 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_i2c2_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_i2c2_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* i2c2 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
-        &omap44xx_l4_per__i2c2,
-};
 static struct omap_hwmod omap44xx_i2c2_hwmod = {
        .name           = "i2c2",
        .class          = &omap44xx_i2c_hwmod_class,
@@ -2372,13 +1548,10 @@ static struct omap_hwmod omap44xx_i2c2_hwmod = {
                        .modulemode   = MODULEMODE_SWCTRL,
                },
        },
-        .slaves         = omap44xx_i2c2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c2_slaves),
        .dev_attr       = &i2c_dev_attr,
 };
 /* i2c3 */
-static struct omap_hwmod omap44xx_i2c3_hwmod;
 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
        { .irq = 61 + OMAP44XX_IRQ_GIC_START },
        { .irq = -1 }
@@ -2390,29 +1563,6 @@ static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
        { .dma_req = -1 }
 };
-static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
-        {
-                .pa_start       = 0x48060000,
-                .pa_end         = 0x480600ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_per -> i2c3 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_i2c3_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_i2c3_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* i2c3 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
-        &omap44xx_l4_per__i2c3,
-};
 static struct omap_hwmod omap44xx_i2c3_hwmod = {
        .name           = "i2c3",
        .class          = &omap44xx_i2c_hwmod_class,
@@ -2428,13 +1578,10 @@ static struct omap_hwmod omap44xx_i2c3_hwmod = {
                        .modulemode   = MODULEMODE_SWCTRL,
                },
        },
-        .slaves         = omap44xx_i2c3_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c3_slaves),
        .dev_attr       = &i2c_dev_attr,
 };
 /* i2c4 */
-static struct omap_hwmod omap44xx_i2c4_hwmod;
 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
        { .irq = 62 + OMAP44XX_IRQ_GIC_START },
        { .irq = -1 }
@@ -2446,29 +1593,6 @@ static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
        { .dma_req = -1 }
 };
-static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
-        {
-                .pa_start       = 0x48350000,
-                .pa_end         = 0x483500ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_per -> i2c4 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_i2c4_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_i2c4_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* i2c4 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
-        &omap44xx_l4_per__i2c4,
-};
 static struct omap_hwmod omap44xx_i2c4_hwmod = {
        .name           = "i2c4",
        .class          = &omap44xx_i2c_hwmod_class,
@@ -2484,8 +1608,6 @@ static struct omap_hwmod omap44xx_i2c4_hwmod = {
                        .modulemode   = MODULEMODE_SWCTRL,
                },
        },
-        .slaves         = omap44xx_i2c4_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c4_slaves),
        .dev_attr       = &i2c_dev_attr,
 };
@@ -2504,66 +1626,12 @@ static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
        { .irq = -1 }
 };
-static struct omap_hwmod_rst_info omap44xx_ipu_c0_resets[] = {
+static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
        { .name = "cpu0", .rst_shift = 0 },
-};
-static struct omap_hwmod_rst_info omap44xx_ipu_c1_resets[] = {
        { .name = "cpu1", .rst_shift = 1 },
-};
-static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
        { .name = "mmu_cache", .rst_shift = 2 },
 };
-/* ipu master ports */
-static struct omap_hwmod_ocp_if *omap44xx_ipu_masters[] = {
-        &omap44xx_ipu__l3_main_2,
-};
-/* l3_main_2 -> ipu */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
-        .master         = &omap44xx_l3_main_2_hwmod,
-        .slave          = &omap44xx_ipu_hwmod,
-        .clk            = "l3_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* ipu slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_ipu_slaves[] = {
-        &omap44xx_l3_main_2__ipu,
-};
-/* Pseudo hwmod for reset control purpose only */
-static struct omap_hwmod omap44xx_ipu_c0_hwmod = {
-        .name           = "ipu_c0",
-        .class          = &omap44xx_ipu_hwmod_class,
-        .clkdm_name     = "ducati_clkdm",
-        .flags          = HWMOD_INIT_NO_RESET,
-        .rst_lines      = omap44xx_ipu_c0_resets,
-        .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_c0_resets),
-        .prcm = {
-                .omap4 = {
-                        .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
-                },
-        },
-};
-/* Pseudo hwmod for reset control purpose only */
-static struct omap_hwmod omap44xx_ipu_c1_hwmod = {
-        .name           = "ipu_c1",
-        .class          = &omap44xx_ipu_hwmod_class,
-        .clkdm_name     = "ducati_clkdm",
-        .flags          = HWMOD_INIT_NO_RESET,
-        .rst_lines      = omap44xx_ipu_c1_resets,
-        .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_c1_resets),
-        .prcm = {
-                .omap4 = {
-                        .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
-                },
-        },
-};
 static struct omap_hwmod omap44xx_ipu_hwmod = {
        .name           = "ipu",
        .class          = &omap44xx_ipu_hwmod_class,
@@ -2580,10 +1648,6 @@ static struct omap_hwmod omap44xx_ipu_hwmod = {
                        .modulemode   = MODULEMODE_HWCTRL,
                },
        },
-        .slaves         = omap44xx_ipu_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_ipu_slaves),
-        .masters        = omap44xx_ipu_masters,
-        .masters_cnt    = ARRAY_SIZE(omap44xx_ipu_masters),
 };
 /*
@@ -2594,6 +1658,15 @@ static struct omap_hwmod omap44xx_ipu_hwmod = {
 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
        .rev_offs       = 0x0000,
        .sysc_offs      = 0x0010,
+        /*
+         * ISS needs 100 OCP clk cycles delay after a softreset before
+         * accessing sysconfig again.
+         * The lowest frequency at the moment for L3 bus is 100 MHz, so
+         * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
+         *
+         * TODO: Indicate errata when available.
+         */
+        .srst_udelay    = 2,
        .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
@@ -2621,34 +1694,6 @@ static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
        { .dma_req = -1 }
 };
-/* iss master ports */
-static struct omap_hwmod_ocp_if *omap44xx_iss_masters[] = {
-        &omap44xx_iss__l3_main_2,
-};
-static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
-        {
-                .pa_start       = 0x52000000,
-                .pa_end         = 0x520000ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l3_main_2 -> iss */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
-        .master         = &omap44xx_l3_main_2_hwmod,
-        .slave          = &omap44xx_iss_hwmod,
-        .clk            = "l3_div_ck",
-        .addr           = omap44xx_iss_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* iss slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_iss_slaves[] = {
-        &omap44xx_l3_main_2__iss,
-};
 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
        { .role = "ctrlclk", .clk = "iss_ctrlclk" },
 };
@@ -2669,10 +1714,6 @@ static struct omap_hwmod omap44xx_iss_hwmod = {
        },
        .opt_clks       = iss_opt_clks,
        .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
-        .slaves         = omap44xx_iss_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_iss_slaves),
-        .masters        = omap44xx_iss_masters,
-        .masters_cnt    = ARRAY_SIZE(omap44xx_iss_masters),
 };
 /*
@@ -2693,75 +1734,9 @@ static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
 };
 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
-        { .name = "logic", .rst_shift = 2 },
-};
-static struct omap_hwmod_rst_info omap44xx_iva_seq0_resets[] = {
        { .name = "seq0", .rst_shift = 0 },
-};
-static struct omap_hwmod_rst_info omap44xx_iva_seq1_resets[] = {
        { .name = "seq1", .rst_shift = 1 },
-};
+        { .name = "logic", .rst_shift = 2 },
-/* iva master ports */
-static struct omap_hwmod_ocp_if *omap44xx_iva_masters[] = {
-        &omap44xx_iva__l3_main_2,
-        &omap44xx_iva__l3_instr,
-};
-static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
-        {
-                .pa_start       = 0x5a000000,
-                .pa_end         = 0x5a07ffff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l3_main_2 -> iva */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
-        .master         = &omap44xx_l3_main_2_hwmod,
-        .slave          = &omap44xx_iva_hwmod,
-        .clk            = "l3_div_ck",
-        .addr           = omap44xx_iva_addrs,
-        .user           = OCP_USER_MPU,
-};
-/* iva slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = {
-        &omap44xx_dsp__iva,
-        &omap44xx_l3_main_2__iva,
-};
-/* Pseudo hwmod for reset control purpose only */
-static struct omap_hwmod omap44xx_iva_seq0_hwmod = {
-        .name           = "iva_seq0",
-        .class          = &omap44xx_iva_hwmod_class,
-        .clkdm_name     = "ivahd_clkdm",
-        .flags          = HWMOD_INIT_NO_RESET,
-        .rst_lines      = omap44xx_iva_seq0_resets,
-        .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_seq0_resets),
-        .prcm = {
-                .omap4 = {
-                        .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
-                },
-        },
-};
-/* Pseudo hwmod for reset control purpose only */
-static struct omap_hwmod omap44xx_iva_seq1_hwmod = {
-        .name           = "iva_seq1",
-        .class          = &omap44xx_iva_hwmod_class,
-        .clkdm_name     = "ivahd_clkdm",
-        .flags          = HWMOD_INIT_NO_RESET,
-        .rst_lines      = omap44xx_iva_seq1_resets,
-        .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_seq1_resets),
-        .prcm = {
-                .omap4 = {
-                        .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
-                },
-        },
 };
 static struct omap_hwmod omap44xx_iva_hwmod = {
@@ -2780,10 +1755,6 @@ static struct omap_hwmod omap44xx_iva_hwmod = {
                        .modulemode   = MODULEMODE_HWCTRL,
                },
        },
-        .slaves         = omap44xx_iva_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_iva_slaves),
-        .masters        = omap44xx_iva_masters,
-        .masters_cnt    = ARRAY_SIZE(omap44xx_iva_masters),
 };
 /*
@@ -2809,35 +1780,11 @@ static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
 };
 /* kbd */
-static struct omap_hwmod omap44xx_kbd_hwmod;
 static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
        { .irq = 120 + OMAP44XX_IRQ_GIC_START },
        { .irq = -1 }
 };
-static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
-        {
-                .pa_start       = 0x4a31c000,
-                .pa_end         = 0x4a31c07f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_wkup -> kbd */
-static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
-        .master         = &omap44xx_l4_wkup_hwmod,
-        .slave          = &omap44xx_kbd_hwmod,
-        .clk            = "l4_wkup_clk_mux_ck",
-        .addr           = omap44xx_kbd_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* kbd slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_kbd_slaves[] = {
-        &omap44xx_l4_wkup__kbd,
-};
 static struct omap_hwmod omap44xx_kbd_hwmod = {
        .name           = "kbd",
        .class          = &omap44xx_kbd_hwmod_class,
@@ -2851,8 +1798,6 @@ static struct omap_hwmod omap44xx_kbd_hwmod = {
                        .modulemode   = MODULEMODE_SWCTRL,
                },
        },
-        .slaves         = omap44xx_kbd_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_kbd_slaves),
 };
 /*
@@ -2876,35 +1821,11 @@ static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
 };
 /* mailbox */
-static struct omap_hwmod omap44xx_mailbox_hwmod;
 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
        { .irq = 26 + OMAP44XX_IRQ_GIC_START },
        { .irq = -1 }
 };
-static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
-        {
-                .pa_start       = 0x4a0f4000,
-                .pa_end         = 0x4a0f41ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_cfg -> mailbox */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
-        .master         = &omap44xx_l4_cfg_hwmod,
-        .slave          = &omap44xx_mailbox_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_mailbox_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* mailbox slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_mailbox_slaves[] = {
-        &omap44xx_l4_cfg__mailbox,
-};
 static struct omap_hwmod omap44xx_mailbox_hwmod = {
        .name           = "mailbox",
        .class          = &omap44xx_mailbox_hwmod_class,
@@ -2916,8 +1837,58 @@ static struct omap_hwmod omap44xx_mailbox_hwmod = {
                        .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
                },
        },
-        .slaves         = omap44xx_mailbox_slaves,
+};
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_mailbox_slaves),
+/*
+ * 'mcasp' class
+ * multi-channel audio serial port controller
+ */
+/* The IP is not compliant to type1 / type2 scheme */
+static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = {
+        .sidle_shift    = 0,
+};
+static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = {
+        .sysc_offs      = 0x0004,
+        .sysc_flags     = SYSC_HAS_SIDLEMODE,
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type_mcasp,
+};
+static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
+        .name   = "mcasp",
+        .sysc   = &omap44xx_mcasp_sysc,
+};
+/* mcasp */
+static struct omap_hwmod_irq_info omap44xx_mcasp_irqs[] = {
+        { .name = "arevt", .irq = 108 + OMAP44XX_IRQ_GIC_START },
+        { .name = "axevt", .irq = 109 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
+};
+static struct omap_hwmod_dma_info omap44xx_mcasp_sdma_reqs[] = {
+        { .name = "axevt", .dma_req = 7 + OMAP44XX_DMA_REQ_START },
+        { .name = "arevt", .dma_req = 10 + OMAP44XX_DMA_REQ_START },
+        { .dma_req = -1 }
+};
+static struct omap_hwmod omap44xx_mcasp_hwmod = {
+        .name           = "mcasp",
+        .class          = &omap44xx_mcasp_hwmod_class,
+        .clkdm_name     = "abe_clkdm",
+        .mpu_irqs       = omap44xx_mcasp_irqs,
+        .sdma_reqs      = omap44xx_mcasp_sdma_reqs,
+        .main_clk       = "mcasp_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
 };
 /*
@@ -2940,9 +1911,8 @@ static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
 };
 /* mcbsp1 */
-static struct omap_hwmod omap44xx_mcbsp1_hwmod;
 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
-        { .irq = 17 + OMAP44XX_IRQ_GIC_START },
+        { .name = "common", .irq = 17 + OMAP44XX_IRQ_GIC_START },
        { .irq = -1 }
 };
@@ -2952,50 +1922,6 @@ static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
        { .dma_req = -1 }
 };
-static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
-        {
-                .name           = "mpu",
-                .pa_start       = 0x40122000,
-                .pa_end         = 0x401220ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_abe -> mcbsp1 */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
-        .master         = &omap44xx_l4_abe_hwmod,
-        .slave          = &omap44xx_mcbsp1_hwmod,
-        .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_mcbsp1_addrs,
-        .user           = OCP_USER_MPU,
-};
-static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
-        {
-                .name           = "dma",
-                .pa_start       = 0x49022000,
-                .pa_end         = 0x490220ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_abe -> mcbsp1 (dma) */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
-        .master         = &omap44xx_l4_abe_hwmod,
-        .slave          = &omap44xx_mcbsp1_hwmod,
-        .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_mcbsp1_dma_addrs,
-        .user           = OCP_USER_SDMA,
-};
-/* mcbsp1 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_mcbsp1_slaves[] = {
-        &omap44xx_l4_abe__mcbsp1,
-        &omap44xx_l4_abe__mcbsp1_dma,
-};
 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
        { .role = "pad_fck", .clk = "pad_clks_ck" },
        { .role = "prcm_clk", .clk = "mcbsp1_sync_mux_ck" },
@@ -3015,16 +1941,13 @@ static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
                        .modulemode   = MODULEMODE_SWCTRL,
                },
        },
-        .slaves         = omap44xx_mcbsp1_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp1_slaves),
        .opt_clks       = mcbsp1_opt_clks,
        .opt_clks_cnt   = ARRAY_SIZE(mcbsp1_opt_clks),
 };
 /* mcbsp2 */
-static struct omap_hwmod omap44xx_mcbsp2_hwmod;
 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
-        { .irq = 22 + OMAP44XX_IRQ_GIC_START },
+        { .name = "common", .irq = 22 + OMAP44XX_IRQ_GIC_START },
        { .irq = -1 }
 };
@@ -3034,50 +1957,6 @@ static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
        { .dma_req = -1 }
 };
-static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
-        {
-                .name           = "mpu",
-                .pa_start       = 0x40124000,
-                .pa_end         = 0x401240ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_abe -> mcbsp2 */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
-        .master         = &omap44xx_l4_abe_hwmod,
-        .slave          = &omap44xx_mcbsp2_hwmod,
-        .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_mcbsp2_addrs,
-        .user           = OCP_USER_MPU,
-};
-static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
-        {
-                .name           = "dma",
-                .pa_start       = 0x49024000,
-                .pa_end         = 0x490240ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_abe -> mcbsp2 (dma) */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
-        .master         = &omap44xx_l4_abe_hwmod,
-        .slave          = &omap44xx_mcbsp2_hwmod,
-        .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_mcbsp2_dma_addrs,
-        .user           = OCP_USER_SDMA,
-};
-/* mcbsp2 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_mcbsp2_slaves[] = {
-        &omap44xx_l4_abe__mcbsp2,
-        &omap44xx_l4_abe__mcbsp2_dma,
-};
 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
        { .role = "pad_fck", .clk = "pad_clks_ck" },
        { .role = "prcm_clk", .clk = "mcbsp2_sync_mux_ck" },
@@ -3097,16 +1976,13 @@ static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
                        .modulemode   = MODULEMODE_SWCTRL,
                },
        },
-        .slaves         = omap44xx_mcbsp2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp2_slaves),
        .opt_clks       = mcbsp2_opt_clks,
        .opt_clks_cnt   = ARRAY_SIZE(mcbsp2_opt_clks),
 };
 /* mcbsp3 */
-static struct omap_hwmod omap44xx_mcbsp3_hwmod;
 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
-        { .irq = 23 + OMAP44XX_IRQ_GIC_START },
+        { .name = "common", .irq = 23 + OMAP44XX_IRQ_GIC_START },
        { .irq = -1 }
 };
@@ -3116,50 +1992,6 @@ static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
        { .dma_req = -1 }
 };
-static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
-        {
-                .name           = "mpu",
-                .pa_start       = 0x40126000,
-                .pa_end         = 0x401260ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_abe -> mcbsp3 */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
-        .master         = &omap44xx_l4_abe_hwmod,
-        .slave          = &omap44xx_mcbsp3_hwmod,
-        .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_mcbsp3_addrs,
-        .user           = OCP_USER_MPU,
-};
-static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
-        {
-                .name           = "dma",
-                .pa_start       = 0x49026000,
-                .pa_end         = 0x490260ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_abe -> mcbsp3 (dma) */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
-        .master         = &omap44xx_l4_abe_hwmod,
-        .slave          = &omap44xx_mcbsp3_hwmod,
-        .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_mcbsp3_dma_addrs,
-        .user           = OCP_USER_SDMA,
-};
-/* mcbsp3 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_mcbsp3_slaves[] = {
-        &omap44xx_l4_abe__mcbsp3,
-        &omap44xx_l4_abe__mcbsp3_dma,
-};
 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
        { .role = "pad_fck", .clk = "pad_clks_ck" },
        { .role = "prcm_clk", .clk = "mcbsp3_sync_mux_ck" },
@@ -3179,16 +2011,13 @@ static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
                        .modulemode   = MODULEMODE_SWCTRL,
                },
        },
-        .slaves         = omap44xx_mcbsp3_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp3_slaves),
        .opt_clks       = mcbsp3_opt_clks,
        .opt_clks_cnt   = ARRAY_SIZE(mcbsp3_opt_clks),
 };
 /* mcbsp4 */
-static struct omap_hwmod omap44xx_mcbsp4_hwmod;
 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
-        { .irq = 16 + OMAP44XX_IRQ_GIC_START },
+        { .name = "common", .irq = 16 + OMAP44XX_IRQ_GIC_START },
        { .irq = -1 }
 };
@@ -3198,29 +2027,6 @@ static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
        { .dma_req = -1 }
 };
-static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
-        {
-                .pa_start       = 0x48096000,
-                .pa_end         = 0x480960ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_per -> mcbsp4 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_mcbsp4_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_mcbsp4_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* mcbsp4 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_mcbsp4_slaves[] = {
-        &omap44xx_l4_per__mcbsp4,
-};
 static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
        { .role = "pad_fck", .clk = "pad_clks_ck" },
        { .role = "prcm_clk", .clk = "mcbsp4_sync_mux_ck" },
@@ -3240,8 +2046,6 @@ static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
                        .modulemode   = MODULEMODE_SWCTRL,
                },
        },
-        .slaves         = omap44xx_mcbsp4_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp4_slaves),
        .opt_clks       = mcbsp4_opt_clks,
        .opt_clks_cnt   = ARRAY_SIZE(mcbsp4_opt_clks),
 };
@@ -3268,7 +2072,6 @@ static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
 };
 /* mcpdm */
-static struct omap_hwmod omap44xx_mcpdm_hwmod;
 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
        { .irq = 112 + OMAP44XX_IRQ_GIC_START },
        { .irq = -1 }
@@ -3280,48 +2083,6 @@ static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
        { .dma_req = -1 }
 };
-static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
-        {
-                .pa_start       = 0x40132000,
-                .pa_end         = 0x4013207f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_abe -> mcpdm */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
-        .master         = &omap44xx_l4_abe_hwmod,
-        .slave          = &omap44xx_mcpdm_hwmod,
-        .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_mcpdm_addrs,
-        .user           = OCP_USER_MPU,
-};
-static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
-        {
-                .pa_start       = 0x49032000,
-                .pa_end         = 0x4903207f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_abe -> mcpdm (dma) */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
-        .master         = &omap44xx_l4_abe_hwmod,
-        .slave          = &omap44xx_mcpdm_hwmod,
-        .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_mcpdm_dma_addrs,
-        .user           = OCP_USER_SDMA,
-};
-/* mcpdm slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_mcpdm_slaves[] = {
-        &omap44xx_l4_abe__mcpdm,
-        &omap44xx_l4_abe__mcpdm_dma,
-};
 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
        .name           = "mcpdm",
        .class          = &omap44xx_mcpdm_hwmod_class,
@@ -3336,8 +2097,6 @@ static struct omap_hwmod omap44xx_mcpdm_hwmod = {
                        .modulemode   = MODULEMODE_SWCTRL,
                },
        },
-        .slaves         = omap44xx_mcpdm_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_mcpdm_slaves),
 };
 /*
@@ -3363,7 +2122,6 @@ static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
 };
 /* mcspi1 */
-static struct omap_hwmod omap44xx_mcspi1_hwmod;
 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
        { .irq = 65 + OMAP44XX_IRQ_GIC_START },
        { .irq = -1 }
@@ -3381,29 +2139,6 @@ static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
        { .dma_req = -1 }
 };
-static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
-        {
-                .pa_start       = 0x48098000,
-                .pa_end         = 0x480981ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_per -> mcspi1 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_mcspi1_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_mcspi1_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* mcspi1 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_mcspi1_slaves[] = {
-        &omap44xx_l4_per__mcspi1,
-};
 /* mcspi1 dev_attr */
 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
        .num_chipselect = 4,
@@ -3424,12 +2159,9 @@ static struct omap_hwmod omap44xx_mcspi1_hwmod = {
                },
        },
        .dev_attr       = &mcspi1_dev_attr,
-        .slaves         = omap44xx_mcspi1_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi1_slaves),
 };
 /* mcspi2 */
-static struct omap_hwmod omap44xx_mcspi2_hwmod;
 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
        { .irq = 66 + OMAP44XX_IRQ_GIC_START },
        { .irq = -1 }
@@ -3443,29 +2175,6 @@ static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
        { .dma_req = -1 }
 };
-static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
-        {
-                .pa_start       = 0x4809a000,
-                .pa_end         = 0x4809a1ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_per -> mcspi2 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_mcspi2_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_mcspi2_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* mcspi2 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_mcspi2_slaves[] = {
-        &omap44xx_l4_per__mcspi2,
-};
 /* mcspi2 dev_attr */
 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
        .num_chipselect = 2,
@@ -3486,12 +2195,9 @@ static struct omap_hwmod omap44xx_mcspi2_hwmod = {
                },
        },
        .dev_attr       = &mcspi2_dev_attr,
-        .slaves         = omap44xx_mcspi2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi2_slaves),
 };
 /* mcspi3 */
-static struct omap_hwmod omap44xx_mcspi3_hwmod;
 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
        { .irq = 91 + OMAP44XX_IRQ_GIC_START },
        { .irq = -1 }
@@ -3505,29 +2211,6 @@ static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
        { .dma_req = -1 }
 };
-static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
-        {
-                .pa_start       = 0x480b8000,
-                .pa_end         = 0x480b81ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_per -> mcspi3 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_mcspi3_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_mcspi3_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* mcspi3 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_mcspi3_slaves[] = {
-        &omap44xx_l4_per__mcspi3,
-};
 /* mcspi3 dev_attr */
 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
        .num_chipselect = 2,
@@ -3548,12 +2231,9 @@ static struct omap_hwmod omap44xx_mcspi3_hwmod = {
                },
        },
        .dev_attr       = &mcspi3_dev_attr,
-        .slaves         = omap44xx_mcspi3_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi3_slaves),
 };
 /* mcspi4 */
-static struct omap_hwmod omap44xx_mcspi4_hwmod;
 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
        { .irq = 48 + OMAP44XX_IRQ_GIC_START },
        { .irq = -1 }
@@ -3565,29 +2245,6 @@ static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
        { .dma_req = -1 }
 };
-static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
-        {
-                .pa_start       = 0x480ba000,
-                .pa_end         = 0x480ba1ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_per -> mcspi4 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_mcspi4_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_mcspi4_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* mcspi4 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_mcspi4_slaves[] = {
-        &omap44xx_l4_per__mcspi4,
-};
 /* mcspi4 dev_attr */
 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
        .num_chipselect = 1,
@@ -3608,8 +2265,6 @@ static struct omap_hwmod omap44xx_mcspi4_hwmod = {
                },
        },
        .dev_attr       = &mcspi4_dev_attr,
-        .slaves         = omap44xx_mcspi4_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi4_slaves),
 };
 /*
@@ -3646,34 +2301,6 @@ static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
        { .dma_req = -1 }
 };
-/* mmc1 master ports */
-static struct omap_hwmod_ocp_if *omap44xx_mmc1_masters[] = {
-        &omap44xx_mmc1__l3_main_1,
-};
-static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
-        {
-                .pa_start       = 0x4809c000,
-                .pa_end         = 0x4809c3ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_per -> mmc1 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_mmc1_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_mmc1_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* mmc1 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_mmc1_slaves[] = {
-        &omap44xx_l4_per__mmc1,
-};
 /* mmc1 dev_attr */
 static struct omap_mmc_dev_attr mmc1_dev_attr = {
        .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
@@ -3694,10 +2321,6 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = {
                },
        },
        .dev_attr       = &mmc1_dev_attr,
-        .slaves         = omap44xx_mmc1_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc1_slaves),
-        .masters        = omap44xx_mmc1_masters,
-        .masters_cnt    = ARRAY_SIZE(omap44xx_mmc1_masters),
 };
 /* mmc2 */
@@ -3712,34 +2335,6 @@ static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
        { .dma_req = -1 }
 };
-/* mmc2 master ports */
-static struct omap_hwmod_ocp_if *omap44xx_mmc2_masters[] = {
-        &omap44xx_mmc2__l3_main_1,
-};
-static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
-        {
-                .pa_start       = 0x480b4000,
-                .pa_end         = 0x480b43ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_per -> mmc2 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_mmc2_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_mmc2_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* mmc2 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_mmc2_slaves[] = {
-        &omap44xx_l4_per__mmc2,
-};
 static struct omap_hwmod omap44xx_mmc2_hwmod = {
        .name           = "mmc2",
        .class          = &omap44xx_mmc_hwmod_class,
@@ -3754,14 +2349,9 @@ static struct omap_hwmod omap44xx_mmc2_hwmod = {
                        .modulemode   = MODULEMODE_SWCTRL,
                },
        },
-        .slaves         = omap44xx_mmc2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc2_slaves),
-        .masters        = omap44xx_mmc2_masters,
-        .masters_cnt    = ARRAY_SIZE(omap44xx_mmc2_masters),
 };
 /* mmc3 */
-static struct omap_hwmod omap44xx_mmc3_hwmod;
 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
        { .irq = 94 + OMAP44XX_IRQ_GIC_START },
        { .irq = -1 }
@@ -3773,29 +2363,6 @@ static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
        { .dma_req = -1 }
 };
-static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
-        {
-                .pa_start       = 0x480ad000,
-                .pa_end         = 0x480ad3ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_per -> mmc3 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_mmc3_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_mmc3_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* mmc3 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_mmc3_slaves[] = {
-        &omap44xx_l4_per__mmc3,
-};
 static struct omap_hwmod omap44xx_mmc3_hwmod = {
        .name           = "mmc3",
        .class          = &omap44xx_mmc_hwmod_class,
@@ -3810,12 +2377,9 @@ static struct omap_hwmod omap44xx_mmc3_hwmod = {
                        .modulemode   = MODULEMODE_SWCTRL,
                },
        },
-        .slaves         = omap44xx_mmc3_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc3_slaves),
 };
 /* mmc4 */
-static struct omap_hwmod omap44xx_mmc4_hwmod;
 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
        { .irq = 96 + OMAP44XX_IRQ_GIC_START },
        { .irq = -1 }
@@ -3827,35 +2391,11 @@ static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
        { .dma_req = -1 }
 };
-static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
-        {
-                .pa_start       = 0x480d1000,
-                .pa_end         = 0x480d13ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_per -> mmc4 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_mmc4_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_mmc4_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* mmc4 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_mmc4_slaves[] = {
-        &omap44xx_l4_per__mmc4,
-};
 static struct omap_hwmod omap44xx_mmc4_hwmod = {
        .name           = "mmc4",
        .class          = &omap44xx_mmc_hwmod_class,
        .clkdm_name     = "l4_per_clkdm",
        .mpu_irqs       = omap44xx_mmc4_irqs,
        .sdma_reqs      = omap44xx_mmc4_sdma_reqs,
        .main_clk       = "mmc4_fck",
        .prcm = {
@@ -3865,12 +2405,9 @@ static struct omap_hwmod omap44xx_mmc4_hwmod = {
                        .modulemode   = MODULEMODE_SWCTRL,
                },
        },
-        .slaves         = omap44xx_mmc4_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc4_slaves),
 };
 /* mmc5 */
-static struct omap_hwmod omap44xx_mmc5_hwmod;
 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
        { .irq = 59 + OMAP44XX_IRQ_GIC_START },
        { .irq = -1 }
@@ -3882,29 +2419,6 @@ static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
        { .dma_req = -1 }
 };
-static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
-        {
-                .pa_start       = 0x480d5000,
-                .pa_end         = 0x480d53ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_per -> mmc5 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_mmc5_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_mmc5_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* mmc5 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_mmc5_slaves[] = {
-        &omap44xx_l4_per__mmc5,
-};
 static struct omap_hwmod omap44xx_mmc5_hwmod = {
        .name           = "mmc5",
        .class          = &omap44xx_mmc_hwmod_class,
@@ -3919,8 +2433,6 @@ static struct omap_hwmod omap44xx_mmc5_hwmod = {
                        .modulemode   = MODULEMODE_SWCTRL,
                },
        },
-        .slaves         = omap44xx_mmc5_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc5_slaves),
 };
 /*
@@ -3940,13 +2452,6 @@ static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
        { .irq = -1 }
 };
-/* mpu master ports */
-static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = {
-        &omap44xx_mpu__l3_main_1,
-        &omap44xx_mpu__l4_abe,
-        &omap44xx_mpu__dmm,
-};
 static struct omap_hwmod omap44xx_mpu_hwmod = {
        .name           = "mpu",
        .class          = &omap44xx_mpu_hwmod_class,
@@ -3960,8 +2465,252 @@ static struct omap_hwmod omap44xx_mpu_hwmod = {
                        .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
                },
        },
-        .masters        = omap44xx_mpu_masters,
+};
-        .masters_cnt    = ARRAY_SIZE(omap44xx_mpu_masters),
+/*
+ * 'ocmc_ram' class
+ * top-level core on-chip ram
+ */
+static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
+        .name   = "ocmc_ram",
+};
+/* ocmc_ram */
+static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
+        .name           = "ocmc_ram",
+        .class          = &omap44xx_ocmc_ram_hwmod_class,
+        .clkdm_name     = "l3_2_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
+                },
+        },
+};
+/*
+ * 'ocp2scp' class
+ * bridge to transform ocp interface protocol to scp (serial control port)
+ * protocol
+ */
+static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
+        .name   = "ocp2scp",
+};
+/* ocp2scp_usb_phy */
+static struct omap_hwmod_opt_clk ocp2scp_usb_phy_opt_clks[] = {
+        { .role = "phy_48m", .clk = "ocp2scp_usb_phy_phy_48m" },
+};
+static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
+        .name           = "ocp2scp_usb_phy",
+        .class          = &omap44xx_ocp2scp_hwmod_class,
+        .clkdm_name     = "l3_init_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+        .opt_clks       = ocp2scp_usb_phy_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(ocp2scp_usb_phy_opt_clks),
+};
+/*
+ * 'prcm' class
+ * power and reset manager (part of the prcm infrastructure) + clock manager 2
+ * + clock manager 1 (in always on power domain) + local prm in mpu
+ */
+static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
+        .name   = "prcm",
+};
+/* prcm_mpu */
+static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
+        .name           = "prcm_mpu",
+        .class          = &omap44xx_prcm_hwmod_class,
+        .clkdm_name     = "l4_wkup_clkdm",
+};
+/* cm_core_aon */
+static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
+        .name           = "cm_core_aon",
+        .class          = &omap44xx_prcm_hwmod_class,
+        .clkdm_name     = "cm_clkdm",
+};
+/* cm_core */
+static struct omap_hwmod omap44xx_cm_core_hwmod = {
+        .name           = "cm_core",
+        .class          = &omap44xx_prcm_hwmod_class,
+        .clkdm_name     = "cm_clkdm",
+};
+/* prm */
+static struct omap_hwmod_irq_info omap44xx_prm_irqs[] = {
+        { .irq = 11 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
+};
+static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
+        { .name = "rst_global_warm_sw", .rst_shift = 0 },
+        { .name = "rst_global_cold_sw", .rst_shift = 1 },
+};
+static struct omap_hwmod omap44xx_prm_hwmod = {
+        .name           = "prm",
+        .class          = &omap44xx_prcm_hwmod_class,
+        .clkdm_name     = "prm_clkdm",
+        .mpu_irqs       = omap44xx_prm_irqs,
+        .rst_lines      = omap44xx_prm_resets,
+        .rst_lines_cnt  = ARRAY_SIZE(omap44xx_prm_resets),
+};
+/*
+ * 'scrm' class
+ * system clock and reset manager
+ */
+static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
+        .name   = "scrm",
+};
+/* scrm */
+static struct omap_hwmod omap44xx_scrm_hwmod = {
+        .name           = "scrm",
+        .class          = &omap44xx_scrm_hwmod_class,
+        .clkdm_name     = "l4_wkup_clkdm",
+};
+/*
+ * 'sl2if' class
+ * shared level 2 memory interface
+ */
+static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
+        .name   = "sl2if",
+};
+/* sl2if */
+static struct omap_hwmod omap44xx_sl2if_hwmod = {
+        .name           = "sl2if",
+        .class          = &omap44xx_sl2if_hwmod_class,
+        .clkdm_name     = "ivahd_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+};
+/*
+ * 'slimbus' class
+ * bidirectional, multi-drop, multi-channel two-line serial interface between
+ * the device and external components
+ */
+static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
+        .name   = "slimbus",
+        .sysc   = &omap44xx_slimbus_sysc,
+};
+/* slimbus1 */
+static struct omap_hwmod_irq_info omap44xx_slimbus1_irqs[] = {
+        { .irq = 97 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
+};
+static struct omap_hwmod_dma_info omap44xx_slimbus1_sdma_reqs[] = {
+        { .name = "tx0", .dma_req = 84 + OMAP44XX_DMA_REQ_START },
+        { .name = "tx1", .dma_req = 85 + OMAP44XX_DMA_REQ_START },
+        { .name = "tx2", .dma_req = 86 + OMAP44XX_DMA_REQ_START },
+        { .name = "tx3", .dma_req = 87 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx0", .dma_req = 88 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx1", .dma_req = 89 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx2", .dma_req = 90 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx3", .dma_req = 91 + OMAP44XX_DMA_REQ_START },
+        { .dma_req = -1 }
+};
+static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
+        { .role = "fclk_1", .clk = "slimbus1_fclk_1" },
+        { .role = "fclk_0", .clk = "slimbus1_fclk_0" },
+        { .role = "fclk_2", .clk = "slimbus1_fclk_2" },
+        { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
+};
+static struct omap_hwmod omap44xx_slimbus1_hwmod = {
+        .name           = "slimbus1",
+        .class          = &omap44xx_slimbus_hwmod_class,
+        .clkdm_name     = "abe_clkdm",
+        .mpu_irqs       = omap44xx_slimbus1_irqs,
+        .sdma_reqs      = omap44xx_slimbus1_sdma_reqs,
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .opt_clks       = slimbus1_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(slimbus1_opt_clks),
+};
+/* slimbus2 */
+static struct omap_hwmod_irq_info omap44xx_slimbus2_irqs[] = {
+        { .irq = 98 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
+};
+static struct omap_hwmod_dma_info omap44xx_slimbus2_sdma_reqs[] = {
+        { .name = "tx0", .dma_req = 92 + OMAP44XX_DMA_REQ_START },
+        { .name = "tx1", .dma_req = 93 + OMAP44XX_DMA_REQ_START },
+        { .name = "tx2", .dma_req = 94 + OMAP44XX_DMA_REQ_START },
+        { .name = "tx3", .dma_req = 95 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx0", .dma_req = 96 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx1", .dma_req = 97 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx2", .dma_req = 98 + OMAP44XX_DMA_REQ_START },
+        { .name = "rx3", .dma_req = 99 + OMAP44XX_DMA_REQ_START },
+        { .dma_req = -1 }
+};
+static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
+        { .role = "fclk_1", .clk = "slimbus2_fclk_1" },
+        { .role = "fclk_0", .clk = "slimbus2_fclk_0" },
+        { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" },
+};
+static struct omap_hwmod omap44xx_slimbus2_hwmod = {
+        .name           = "slimbus2",
+        .class          = &omap44xx_slimbus_hwmod_class,
+        .clkdm_name     = "l4_per_clkdm",
+        .mpu_irqs       = omap44xx_slimbus2_irqs,
+        .sdma_reqs      = omap44xx_slimbus2_sdma_reqs,
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .opt_clks       = slimbus2_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(slimbus2_opt_clks),
 };
 /*
@@ -3995,35 +2744,11 @@ static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
        .sensor_voltdm_name   = "core",
 };
-static struct omap_hwmod omap44xx_smartreflex_core_hwmod;
 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
        { .irq = 19 + OMAP44XX_IRQ_GIC_START },
        { .irq = -1 }
 };
-static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
-        {
-                .pa_start       = 0x4a0dd000,
-                .pa_end         = 0x4a0dd03f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_cfg -> smartreflex_core */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
-        .master         = &omap44xx_l4_cfg_hwmod,
-        .slave          = &omap44xx_smartreflex_core_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_smartreflex_core_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* smartreflex_core slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = {
-        &omap44xx_l4_cfg__smartreflex_core,
-};
 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
        .name           = "smartreflex_core",
        .class          = &omap44xx_smartreflex_hwmod_class,
@@ -4038,8 +2763,6 @@ static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
                        .modulemode   = MODULEMODE_SWCTRL,
                },
        },
-        .slaves         = omap44xx_smartreflex_core_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_core_slaves),
        .dev_attr       = &smartreflex_core_dev_attr,
 };
@@ -4048,35 +2771,11 @@ static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
        .sensor_voltdm_name     = "iva",
 };
-static struct omap_hwmod omap44xx_smartreflex_iva_hwmod;
 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
        { .irq = 102 + OMAP44XX_IRQ_GIC_START },
        { .irq = -1 }
 };
-static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
-        {
-                .pa_start       = 0x4a0db000,
-                .pa_end         = 0x4a0db03f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_cfg -> smartreflex_iva */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
-        .master         = &omap44xx_l4_cfg_hwmod,
-        .slave          = &omap44xx_smartreflex_iva_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_smartreflex_iva_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* smartreflex_iva slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = {
-        &omap44xx_l4_cfg__smartreflex_iva,
-};
 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
        .name           = "smartreflex_iva",
        .class          = &omap44xx_smartreflex_hwmod_class,
@@ -4090,8 +2789,6 @@ static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
                        .modulemode   = MODULEMODE_SWCTRL,
                },
        },
-        .slaves         = omap44xx_smartreflex_iva_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),
        .dev_attr       = &smartreflex_iva_dev_attr,
 };
@@ -4100,35 +2797,11 @@ static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
        .sensor_voltdm_name     = "mpu",
 };
-static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod;
 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
        { .irq = 18 + OMAP44XX_IRQ_GIC_START },
        { .irq = -1 }
 };
-static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
-        {
-                .pa_start       = 0x4a0d9000,
-                .pa_end         = 0x4a0d903f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_cfg -> smartreflex_mpu */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
-        .master         = &omap44xx_l4_cfg_hwmod,
-        .slave          = &omap44xx_smartreflex_mpu_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_smartreflex_mpu_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* smartreflex_mpu slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = {
-        &omap44xx_l4_cfg__smartreflex_mpu,
-};
 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
        .name           = "smartreflex_mpu",
        .class          = &omap44xx_smartreflex_hwmod_class,
@@ -4142,8 +2815,6 @@ static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
                        .modulemode   = MODULEMODE_SWCTRL,
                },
        },
-        .slaves         = omap44xx_smartreflex_mpu_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves),
        .dev_attr       = &smartreflex_mpu_dev_attr,
 };
@@ -4171,30 +2842,6 @@ static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
 };
 /* spinlock */
-static struct omap_hwmod omap44xx_spinlock_hwmod;
-static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
-        {
-                .pa_start       = 0x4a0f6000,
-                .pa_end         = 0x4a0f6fff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_cfg -> spinlock */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
-        .master         = &omap44xx_l4_cfg_hwmod,
-        .slave          = &omap44xx_spinlock_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_spinlock_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* spinlock slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_spinlock_slaves[] = {
-        &omap44xx_l4_cfg__spinlock,
-};
 static struct omap_hwmod omap44xx_spinlock_hwmod = {
        .name           = "spinlock",
        .class          = &omap44xx_spinlock_hwmod_class,
@@ -4205,8 +2852,6 @@ static struct omap_hwmod omap44xx_spinlock_hwmod = {
                        .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
                },
        },
-        .slaves         = omap44xx_spinlock_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_spinlock_slaves),
 };
 /*
@@ -4258,35 +2903,11 @@ static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
 };
 /* timer1 */
-static struct omap_hwmod omap44xx_timer1_hwmod;
 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
        { .irq = 37 + OMAP44XX_IRQ_GIC_START },
        { .irq = -1 }
 };
-static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
-        {
-                .pa_start       = 0x4a318000,
-                .pa_end         = 0x4a31807f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_wkup -> timer1 */
-static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
-        .master         = &omap44xx_l4_wkup_hwmod,
-        .slave          = &omap44xx_timer1_hwmod,
-        .clk            = "l4_wkup_clk_mux_ck",
-        .addr           = omap44xx_timer1_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* timer1 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = {
-        &omap44xx_l4_wkup__timer1,
-};
 static struct omap_hwmod omap44xx_timer1_hwmod = {
        .name           = "timer1",
        .class          = &omap44xx_timer_1ms_hwmod_class,
@@ -4301,40 +2922,14 @@ static struct omap_hwmod omap44xx_timer1_hwmod = {
                },
        },
        .dev_attr       = &capability_alwon_dev_attr,
-        .slaves         = omap44xx_timer1_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_timer1_slaves),
 };
 /* timer2 */
-static struct omap_hwmod omap44xx_timer2_hwmod;
 static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
        { .irq = 38 + OMAP44XX_IRQ_GIC_START },
        { .irq = -1 }
 };
-static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
-        {
-                .pa_start       = 0x48032000,
-                .pa_end         = 0x4803207f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_per -> timer2 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_timer2_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_timer2_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* timer2 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_timer2_slaves[] = {
-        &omap44xx_l4_per__timer2,
-};
 static struct omap_hwmod omap44xx_timer2_hwmod = {
        .name           = "timer2",
        .class          = &omap44xx_timer_1ms_hwmod_class,
@@ -4349,40 +2944,14 @@ static struct omap_hwmod omap44xx_timer2_hwmod = {
                },
        },
        .dev_attr       = &capability_alwon_dev_attr,
-        .slaves         = omap44xx_timer2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_timer2_slaves),
 };
 /* timer3 */
-static struct omap_hwmod omap44xx_timer3_hwmod;
 static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
        { .irq = 39 + OMAP44XX_IRQ_GIC_START },
        { .irq = -1 }
 };
-static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
-        {
-                .pa_start       = 0x48034000,
-                .pa_end         = 0x4803407f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_per -> timer3 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_timer3_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_timer3_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* timer3 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_timer3_slaves[] = {
-        &omap44xx_l4_per__timer3,
-};
 static struct omap_hwmod omap44xx_timer3_hwmod = {
        .name           = "timer3",
        .class          = &omap44xx_timer_hwmod_class,
@@ -4397,40 +2966,14 @@ static struct omap_hwmod omap44xx_timer3_hwmod = {
                },
        },
        .dev_attr       = &capability_alwon_dev_attr,
-        .slaves         = omap44xx_timer3_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_timer3_slaves),
 };
 /* timer4 */
-static struct omap_hwmod omap44xx_timer4_hwmod;
 static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
        { .irq = 40 + OMAP44XX_IRQ_GIC_START },
        { .irq = -1 }
 };
-static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
-        {
-                .pa_start       = 0x48036000,
-                .pa_end         = 0x4803607f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_per -> timer4 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_timer4_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_timer4_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* timer4 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_timer4_slaves[] = {
-        &omap44xx_l4_per__timer4,
-};
 static struct omap_hwmod omap44xx_timer4_hwmod = {
        .name           = "timer4",
        .class          = &omap44xx_timer_hwmod_class,
@@ -4445,59 +2988,14 @@ static struct omap_hwmod omap44xx_timer4_hwmod = {
                },
        },
        .dev_attr       = &capability_alwon_dev_attr,
-        .slaves         = omap44xx_timer4_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_timer4_slaves),
 };
 /* timer5 */
-static struct omap_hwmod omap44xx_timer5_hwmod;
 static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
        { .irq = 41 + OMAP44XX_IRQ_GIC_START },
        { .irq = -1 }
 };
-static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
-        {
-                .pa_start       = 0x40138000,
-                .pa_end         = 0x4013807f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_abe -> timer5 */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
-        .master         = &omap44xx_l4_abe_hwmod,
-        .slave          = &omap44xx_timer5_hwmod,
-        .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_timer5_addrs,
-        .user           = OCP_USER_MPU,
-};
-static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
-        {
-                .pa_start       = 0x49038000,
-                .pa_end         = 0x4903807f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_abe -> timer5 (dma) */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
-        .master         = &omap44xx_l4_abe_hwmod,
-        .slave          = &omap44xx_timer5_hwmod,
-        .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_timer5_dma_addrs,
-        .user           = OCP_USER_SDMA,
-};
-/* timer5 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_timer5_slaves[] = {
-        &omap44xx_l4_abe__timer5,
-        &omap44xx_l4_abe__timer5_dma,
-};
 static struct omap_hwmod omap44xx_timer5_hwmod = {
        .name           = "timer5",
        .class          = &omap44xx_timer_hwmod_class,
@@ -4512,59 +3010,14 @@ static struct omap_hwmod omap44xx_timer5_hwmod = {
                },
        },
        .dev_attr       = &capability_alwon_dev_attr,
-        .slaves         = omap44xx_timer5_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_timer5_slaves),
 };
 /* timer6 */
-static struct omap_hwmod omap44xx_timer6_hwmod;
 static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
        { .irq = 42 + OMAP44XX_IRQ_GIC_START },
        { .irq = -1 }
 };
-static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
-        {
-                .pa_start       = 0x4013a000,
-                .pa_end         = 0x4013a07f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_abe -> timer6 */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
-        .master         = &omap44xx_l4_abe_hwmod,
-        .slave          = &omap44xx_timer6_hwmod,
-        .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_timer6_addrs,
-        .user           = OCP_USER_MPU,
-};
-static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
-        {
-                .pa_start       = 0x4903a000,
-                .pa_end         = 0x4903a07f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_abe -> timer6 (dma) */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
-        .master         = &omap44xx_l4_abe_hwmod,
-        .slave          = &omap44xx_timer6_hwmod,
-        .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_timer6_dma_addrs,
-        .user           = OCP_USER_SDMA,
-};
-/* timer6 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_timer6_slaves[] = {
-        &omap44xx_l4_abe__timer6,
-        &omap44xx_l4_abe__timer6_dma,
-};
 static struct omap_hwmod omap44xx_timer6_hwmod = {
        .name           = "timer6",
        .class          = &omap44xx_timer_hwmod_class,
@@ -4580,59 +3033,14 @@ static struct omap_hwmod omap44xx_timer6_hwmod = {
                },
        },
        .dev_attr       = &capability_alwon_dev_attr,
-        .slaves         = omap44xx_timer6_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_timer6_slaves),
 };
 /* timer7 */
-static struct omap_hwmod omap44xx_timer7_hwmod;
 static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
        { .irq = 43 + OMAP44XX_IRQ_GIC_START },
        { .irq = -1 }
 };
-static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
-        {
-                .pa_start       = 0x4013c000,
-                .pa_end         = 0x4013c07f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_abe -> timer7 */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
-        .master         = &omap44xx_l4_abe_hwmod,
-        .slave          = &omap44xx_timer7_hwmod,
-        .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_timer7_addrs,
-        .user           = OCP_USER_MPU,
-};
-static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
-        {
-                .pa_start       = 0x4903c000,
-                .pa_end         = 0x4903c07f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_abe -> timer7 (dma) */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
-        .master         = &omap44xx_l4_abe_hwmod,
-        .slave          = &omap44xx_timer7_hwmod,
-        .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_timer7_dma_addrs,
-        .user           = OCP_USER_SDMA,
-};
-/* timer7 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_timer7_slaves[] = {
-        &omap44xx_l4_abe__timer7,
-        &omap44xx_l4_abe__timer7_dma,
-};
 static struct omap_hwmod omap44xx_timer7_hwmod = {
        .name           = "timer7",
        .class          = &omap44xx_timer_hwmod_class,
@@ -4647,59 +3055,14 @@ static struct omap_hwmod omap44xx_timer7_hwmod = {
                },
        },
        .dev_attr       = &capability_alwon_dev_attr,
-        .slaves         = omap44xx_timer7_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_timer7_slaves),
 };
 /* timer8 */
-static struct omap_hwmod omap44xx_timer8_hwmod;
 static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
        { .irq = 44 + OMAP44XX_IRQ_GIC_START },
        { .irq = -1 }
 };
-static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
-        {
-                .pa_start       = 0x4013e000,
-                .pa_end         = 0x4013e07f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_abe -> timer8 */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
-        .master         = &omap44xx_l4_abe_hwmod,
-        .slave          = &omap44xx_timer8_hwmod,
-        .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_timer8_addrs,
-        .user           = OCP_USER_MPU,
-};
-static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
-        {
-                .pa_start       = 0x4903e000,
-                .pa_end         = 0x4903e07f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_abe -> timer8 (dma) */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
-        .master         = &omap44xx_l4_abe_hwmod,
-        .slave          = &omap44xx_timer8_hwmod,
-        .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_timer8_dma_addrs,
-        .user           = OCP_USER_SDMA,
-};
-/* timer8 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_timer8_slaves[] = {
-        &omap44xx_l4_abe__timer8,
-        &omap44xx_l4_abe__timer8_dma,
-};
 static struct omap_hwmod omap44xx_timer8_hwmod = {
        .name           = "timer8",
        .class          = &omap44xx_timer_hwmod_class,
@@ -4714,40 +3077,14 @@ static struct omap_hwmod omap44xx_timer8_hwmod = {
                },
        },
        .dev_attr       = &capability_pwm_dev_attr,
-        .slaves         = omap44xx_timer8_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_timer8_slaves),
 };
 /* timer9 */
-static struct omap_hwmod omap44xx_timer9_hwmod;
 static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
        { .irq = 45 + OMAP44XX_IRQ_GIC_START },
        { .irq = -1 }
 };
-static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
-        {
-                .pa_start       = 0x4803e000,
-                .pa_end         = 0x4803e07f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_per -> timer9 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_timer9_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_timer9_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* timer9 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_timer9_slaves[] = {
-        &omap44xx_l4_per__timer9,
-};
 static struct omap_hwmod omap44xx_timer9_hwmod = {
        .name           = "timer9",
        .class          = &omap44xx_timer_hwmod_class,
@@ -4762,40 +3099,14 @@ static struct omap_hwmod omap44xx_timer9_hwmod = {
                },
        },
        .dev_attr       = &capability_pwm_dev_attr,
-        .slaves         = omap44xx_timer9_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_timer9_slaves),
 };
 /* timer10 */
-static struct omap_hwmod omap44xx_timer10_hwmod;
 static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
        { .irq = 46 + OMAP44XX_IRQ_GIC_START },
        { .irq = -1 }
 };
-static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
-        {
-                .pa_start       = 0x48086000,
-                .pa_end         = 0x4808607f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_per -> timer10 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_timer10_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_timer10_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* timer10 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_timer10_slaves[] = {
-        &omap44xx_l4_per__timer10,
-};
 static struct omap_hwmod omap44xx_timer10_hwmod = {
        .name           = "timer10",
        .class          = &omap44xx_timer_1ms_hwmod_class,
@@ -4810,40 +3121,14 @@ static struct omap_hwmod omap44xx_timer10_hwmod = {
                },
        },
        .dev_attr       = &capability_pwm_dev_attr,
-        .slaves         = omap44xx_timer10_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_timer10_slaves),
 };
 /* timer11 */
-static struct omap_hwmod omap44xx_timer11_hwmod;
 static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
        { .irq = 47 + OMAP44XX_IRQ_GIC_START },
        { .irq = -1 }
 };
-static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
-        {
-                .pa_start       = 0x48088000,
-                .pa_end         = 0x4808807f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_per -> timer11 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_timer11_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_timer11_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* timer11 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_timer11_slaves[] = {
-        &omap44xx_l4_per__timer11,
-};
 static struct omap_hwmod omap44xx_timer11_hwmod = {
        .name           = "timer11",
        .class          = &omap44xx_timer_hwmod_class,
@@ -4858,8 +3143,6 @@ static struct omap_hwmod omap44xx_timer11_hwmod = {
                },
        },
        .dev_attr       = &capability_pwm_dev_attr,
-        .slaves         = omap44xx_timer11_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_timer11_slaves),
 };
 /*
@@ -4885,7 +3168,6 @@ static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
 };
 /* uart1 */
-static struct omap_hwmod omap44xx_uart1_hwmod;
 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
        { .irq = 72 + OMAP44XX_IRQ_GIC_START },
        { .irq = -1 }
@@ -4897,29 +3179,6 @@ static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
        { .dma_req = -1 }
 };
-static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
-        {
-                .pa_start       = 0x4806a000,
-                .pa_end         = 0x4806a0ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_per -> uart1 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_uart1_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_uart1_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* uart1 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = {
-        &omap44xx_l4_per__uart1,
-};
 static struct omap_hwmod omap44xx_uart1_hwmod = {
        .name           = "uart1",
        .class          = &omap44xx_uart_hwmod_class,
@@ -4934,12 +3193,9 @@ static struct omap_hwmod omap44xx_uart1_hwmod = {
                        .modulemode   = MODULEMODE_SWCTRL,
                },
        },
-        .slaves         = omap44xx_uart1_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_uart1_slaves),
 };
 /* uart2 */
-static struct omap_hwmod omap44xx_uart2_hwmod;
 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
        { .irq = 73 + OMAP44XX_IRQ_GIC_START },
        { .irq = -1 }
@@ -4951,29 +3207,6 @@ static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
        { .dma_req = -1 }
 };
-static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
-        {
-                .pa_start       = 0x4806c000,
-                .pa_end         = 0x4806c0ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_per -> uart2 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_uart2_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_uart2_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* uart2 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = {
-        &omap44xx_l4_per__uart2,
-};
 static struct omap_hwmod omap44xx_uart2_hwmod = {
        .name           = "uart2",
        .class          = &omap44xx_uart_hwmod_class,
@@ -4988,12 +3221,9 @@ static struct omap_hwmod omap44xx_uart2_hwmod = {
                        .modulemode   = MODULEMODE_SWCTRL,
                },
        },
-        .slaves         = omap44xx_uart2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_uart2_slaves),
 };
 /* uart3 */
-static struct omap_hwmod omap44xx_uart3_hwmod;
 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
        { .irq = 74 + OMAP44XX_IRQ_GIC_START },
        { .irq = -1 }
@@ -5005,29 +3235,6 @@ static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
        { .dma_req = -1 }
 };
-static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
-        {
-                .pa_start       = 0x48020000,
-                .pa_end         = 0x480200ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_per -> uart3 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_uart3_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_uart3_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* uart3 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = {
-        &omap44xx_l4_per__uart3,
-};
 static struct omap_hwmod omap44xx_uart3_hwmod = {
        .name           = "uart3",
        .class          = &omap44xx_uart_hwmod_class,
@@ -5043,12 +3250,9 @@ static struct omap_hwmod omap44xx_uart3_hwmod = {
                        .modulemode   = MODULEMODE_SWCTRL,
                },
        },
-        .slaves         = omap44xx_uart3_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_uart3_slaves),
 };
 /* uart4 */
-static struct omap_hwmod omap44xx_uart4_hwmod;
 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
        { .irq = 70 + OMAP44XX_IRQ_GIC_START },
        { .irq = -1 }
@@ -5060,29 +3264,6 @@ static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
        { .dma_req = -1 }
 };
-static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
-        {
-                .pa_start       = 0x4806e000,
-                .pa_end         = 0x4806e0ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_per -> uart4 */
-static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
-        .master         = &omap44xx_l4_per_hwmod,
-        .slave          = &omap44xx_uart4_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_uart4_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* uart4 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = {
-        &omap44xx_l4_per__uart4,
-};
 static struct omap_hwmod omap44xx_uart4_hwmod = {
        .name           = "uart4",
        .class          = &omap44xx_uart_hwmod_class,
@@ -5097,8 +3278,147 @@ static struct omap_hwmod omap44xx_uart4_hwmod = {
                        .modulemode   = MODULEMODE_SWCTRL,
                },
        },
-        .slaves         = omap44xx_uart4_slaves,
+};
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_uart4_slaves),
+/*
+ * 'usb_host_fs' class
+ * full-speed usb host controller
+ */
+/* The IP is not compliant to type1 / type2 scheme */
+static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = {
+        .midle_shift    = 4,
+        .sidle_shift    = 2,
+        .srst_shift     = 1,
+};
+static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0210,
+        .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type_usb_host_fs,
+};
+static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
+        .name   = "usb_host_fs",
+        .sysc   = &omap44xx_usb_host_fs_sysc,
+};
+/* usb_host_fs */
+static struct omap_hwmod_irq_info omap44xx_usb_host_fs_irqs[] = {
+        { .name = "std", .irq = 89 + OMAP44XX_IRQ_GIC_START },
+        { .name = "smi", .irq = 90 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
+};
+static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
+        .name           = "usb_host_fs",
+        .class          = &omap44xx_usb_host_fs_hwmod_class,
+        .clkdm_name     = "l3_init_clkdm",
+        .mpu_irqs       = omap44xx_usb_host_fs_irqs,
+        .main_clk       = "usb_host_fs_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/*
+ * 'usb_host_hs' class
+ * high-speed multi-port usb host controller
+ */
+static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+                           MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
+        .name   = "usb_host_hs",
+        .sysc   = &omap44xx_usb_host_hs_sysc,
+};
+/* usb_host_hs */
+static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = {
+        { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START },
+        { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
+};
+static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
+        .name           = "usb_host_hs",
+        .class          = &omap44xx_usb_host_hs_hwmod_class,
+        .clkdm_name     = "l3_init_clkdm",
+        .main_clk       = "usb_host_hs_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .mpu_irqs       = omap44xx_usb_host_hs_irqs,
+        /*
+         * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
+         * id: i660
+         *
+         * Description:
+         * In the following configuration :
+         * - USBHOST module is set to smart-idle mode
+         * - PRCM asserts idle_req to the USBHOST module ( This typically
+         *   happens when the system is going to a low power mode : all ports
+         *   have been suspended, the master part of the USBHOST module has
+         *   entered the standby state, and SW has cut the functional clocks)
+         * - an USBHOST interrupt occurs before the module is able to answer
+         *   idle_ack, typically a remote wakeup IRQ.
+         * Then the USB HOST module will enter a deadlock situation where it
+         * is no more accessible nor functional.
+         *
+         * Workaround:
+         * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
+         */
+        /*
+         * Errata: USB host EHCI may stall when entering smart-standby mode
+         * Id: i571
+         *
+         * Description:
+         * When the USBHOST module is set to smart-standby mode, and when it is
+         * ready to enter the standby state (i.e. all ports are suspended and
+         * all attached devices are in suspend mode), then it can wrongly assert
+         * the Mstandby signal too early while there are still some residual OCP
+         * transactions ongoing. If this condition occurs, the internal state
+         * machine may go to an undefined state and the USB link may be stuck
+         * upon the next resume.
+         *
+         * Workaround:
+         * Don't use smart standby; use only force standby,
+         * hence HWMOD_SWSUP_MSTANDBY
+         */
+        /*
+         * During system boot; If the hwmod framework resets the module
+         * the module will have smart idle settings; which can lead to deadlock
+         * (above Errata Id:i660); so, dont reset the module during boot;
+         * Use HWMOD_INIT_NO_RESET.
+         */
+        .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
+                          HWMOD_INIT_NO_RESET,
 };
 /*
@@ -5131,34 +3451,6 @@ static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
        { .irq = -1 }
 };
-/* usb_otg_hs master ports */
-static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_masters[] = {
-        &omap44xx_usb_otg_hs__l3_main_2,
-};
-static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
-        {
-                .pa_start       = 0x4a0ab000,
-                .pa_end         = 0x4a0ab003,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_cfg -> usb_otg_hs */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
-        .master         = &omap44xx_l4_cfg_hwmod,
-        .slave          = &omap44xx_usb_otg_hs_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_usb_otg_hs_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* usb_otg_hs slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_slaves[] = {
-        &omap44xx_l4_cfg__usb_otg_hs,
-};
 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
        { .role = "xclk", .clk = "usb_otg_hs_xclk" },
 };
@@ -5179,10 +3471,47 @@ static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
        },
        .opt_clks       = usb_otg_hs_opt_clks,
        .opt_clks_cnt   = ARRAY_SIZE(usb_otg_hs_opt_clks),
-        .slaves         = omap44xx_usb_otg_hs_slaves,
+};
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_usb_otg_hs_slaves),
-        .masters        = omap44xx_usb_otg_hs_masters,
+/*
-        .masters_cnt    = ARRAY_SIZE(omap44xx_usb_otg_hs_masters),
+ * 'usb_tll_hs' class
+ * usb_tll_hs module is the adapter on the usb_host_hs ports
+ */
+static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+                           SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
+        .name   = "usb_tll_hs",
+        .sysc   = &omap44xx_usb_tll_hs_sysc,
+};
+static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = {
+        { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
+};
+static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
+        .name           = "usb_tll_hs",
+        .class          = &omap44xx_usb_tll_hs_hwmod_class,
+        .clkdm_name     = "l3_init_clkdm",
+        .mpu_irqs       = omap44xx_usb_tll_hs_irqs,
+        .main_clk       = "usb_tll_hs_ick",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
 };
 /*
@@ -5206,38 +3535,15 @@ static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
        .name           = "wd_timer",
        .sysc           = &omap44xx_wd_timer_sysc,
        .pre_shutdown   = &omap2_wd_timer_disable,
+        .reset          = &omap2_wd_timer_reset,
 };
 /* wd_timer2 */
-static struct omap_hwmod omap44xx_wd_timer2_hwmod;
 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
        { .irq = 80 + OMAP44XX_IRQ_GIC_START },
        { .irq = -1 }
 };
-static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
-        {
-                .pa_start       = 0x4a314000,
-                .pa_end         = 0x4a31407f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-/* l4_wkup -> wd_timer2 */
-static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
-        .master         = &omap44xx_l4_wkup_hwmod,
-        .slave          = &omap44xx_wd_timer2_hwmod,
-        .clk            = "l4_wkup_clk_mux_ck",
-        .addr           = omap44xx_wd_timer2_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* wd_timer2 slave ports */
-static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = {
-        &omap44xx_l4_wkup__wd_timer2,
-};
 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
        .name           = "wd_timer2",
        .class          = &omap44xx_wd_timer_hwmod_class,
@@ -5251,106 +3557,2308 @@ static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
                        .modulemode   = MODULEMODE_SWCTRL,
                },
        },
-        .slaves         = omap44xx_wd_timer2_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer2_slaves),
 };
 /* wd_timer3 */
-static struct omap_hwmod omap44xx_wd_timer3_hwmod;
 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
        { .irq = 36 + OMAP44XX_IRQ_GIC_START },
        { .irq = -1 }
 };
-static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
+static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
+        .name           = "wd_timer3",
+        .class          = &omap44xx_wd_timer_hwmod_class,
+        .clkdm_name     = "abe_clkdm",
+        .mpu_irqs       = omap44xx_wd_timer3_irqs,
+        .main_clk       = "wd_timer3_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+/*
+ * interfaces
+ */
+static struct omap_hwmod_addr_space omap44xx_c2c_target_fw_addrs[] = {
        {
-                .pa_start       = 0x40130000,
+                .pa_start       = 0x4a204000,
-                .pa_end         = 0x4013007f,
+                .pa_end         = 0x4a2040ff,
                .flags          = ADDR_TYPE_RT
        },
        { }
 };
-/* l4_abe -> wd_timer3 */
+/* c2c -> c2c_target_fw */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
+static struct omap_hwmod_ocp_if omap44xx_c2c__c2c_target_fw = {
+        .master         = &omap44xx_c2c_hwmod,
+        .slave          = &omap44xx_c2c_target_fw_hwmod,
+        .clk            = "div_core_ck",
+        .addr           = omap44xx_c2c_target_fw_addrs,
+        .user           = OCP_USER_MPU,
+};
+/* l4_cfg -> c2c_target_fw */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__c2c_target_fw = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_c2c_target_fw_hwmod,
+        .clk            = "l4_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l3_main_1 -> dmm */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
+        .master         = &omap44xx_l3_main_1_hwmod,
+        .slave          = &omap44xx_dmm_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
+        {
+                .pa_start       = 0x4e000000,
+                .pa_end         = 0x4e0007ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* mpu -> dmm */
+static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
+        .master         = &omap44xx_mpu_hwmod,
+        .slave          = &omap44xx_dmm_hwmod,
+        .clk            = "l3_div_ck",
+        .addr           = omap44xx_dmm_addrs,
+        .user           = OCP_USER_MPU,
+};
+/* c2c -> emif_fw */
+static struct omap_hwmod_ocp_if omap44xx_c2c__emif_fw = {
+        .master         = &omap44xx_c2c_hwmod,
+        .slave          = &omap44xx_emif_fw_hwmod,
+        .clk            = "div_core_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* dmm -> emif_fw */
+static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
+        .master         = &omap44xx_dmm_hwmod,
+        .slave          = &omap44xx_emif_fw_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
+        {
+                .pa_start       = 0x4a20c000,
+                .pa_end         = 0x4a20c0ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_cfg -> emif_fw */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_emif_fw_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_emif_fw_addrs,
+        .user           = OCP_USER_MPU,
+};
+/* iva -> l3_instr */
+static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
+        .master         = &omap44xx_iva_hwmod,
+        .slave          = &omap44xx_l3_instr_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l3_main_3 -> l3_instr */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
+        .master         = &omap44xx_l3_main_3_hwmod,
+        .slave          = &omap44xx_l3_instr_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* ocp_wp_noc -> l3_instr */
+static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
+        .master         = &omap44xx_ocp_wp_noc_hwmod,
+        .slave          = &omap44xx_l3_instr_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* dsp -> l3_main_1 */
+static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
+        .master         = &omap44xx_dsp_hwmod,
+        .slave          = &omap44xx_l3_main_1_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* dss -> l3_main_1 */
+static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
+        .master         = &omap44xx_dss_hwmod,
+        .slave          = &omap44xx_l3_main_1_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l3_main_2 -> l3_main_1 */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
+        .master         = &omap44xx_l3_main_2_hwmod,
+        .slave          = &omap44xx_l3_main_1_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_cfg -> l3_main_1 */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_l3_main_1_hwmod,
+        .clk            = "l4_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* mmc1 -> l3_main_1 */
+static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
+        .master         = &omap44xx_mmc1_hwmod,
+        .slave          = &omap44xx_l3_main_1_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* mmc2 -> l3_main_1 */
+static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
+        .master         = &omap44xx_mmc2_hwmod,
+        .slave          = &omap44xx_l3_main_1_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
+        {
+                .pa_start       = 0x44000000,
+                .pa_end         = 0x44000fff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* mpu -> l3_main_1 */
+static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
+        .master         = &omap44xx_mpu_hwmod,
+        .slave          = &omap44xx_l3_main_1_hwmod,
+        .clk            = "l3_div_ck",
+        .addr           = omap44xx_l3_main_1_addrs,
+        .user           = OCP_USER_MPU,
+};
+/* c2c_target_fw -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_c2c_target_fw__l3_main_2 = {
+        .master         = &omap44xx_c2c_target_fw_hwmod,
+        .slave          = &omap44xx_l3_main_2_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* debugss -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
+        .master         = &omap44xx_debugss_hwmod,
+        .slave          = &omap44xx_l3_main_2_hwmod,
+        .clk            = "dbgclk_mux_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* dma_system -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
+        .master         = &omap44xx_dma_system_hwmod,
+        .slave          = &omap44xx_l3_main_2_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* fdif -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
+        .master         = &omap44xx_fdif_hwmod,
+        .slave          = &omap44xx_l3_main_2_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* gpu -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = {
+        .master         = &omap44xx_gpu_hwmod,
+        .slave          = &omap44xx_l3_main_2_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* hsi -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
+        .master         = &omap44xx_hsi_hwmod,
+        .slave          = &omap44xx_l3_main_2_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* ipu -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
+        .master         = &omap44xx_ipu_hwmod,
+        .slave          = &omap44xx_l3_main_2_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* iss -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
+        .master         = &omap44xx_iss_hwmod,
+        .slave          = &omap44xx_l3_main_2_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* iva -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
+        .master         = &omap44xx_iva_hwmod,
+        .slave          = &omap44xx_l3_main_2_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
+        {
+                .pa_start       = 0x44800000,
+                .pa_end         = 0x44801fff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l3_main_1 -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
+        .master         = &omap44xx_l3_main_1_hwmod,
+        .slave          = &omap44xx_l3_main_2_hwmod,
+        .clk            = "l3_div_ck",
+        .addr           = omap44xx_l3_main_2_addrs,
+        .user           = OCP_USER_MPU,
+};
+/* l4_cfg -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_l3_main_2_hwmod,
+        .clk            = "l4_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* usb_host_fs -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_usb_host_fs__l3_main_2 = {
+        .master         = &omap44xx_usb_host_fs_hwmod,
+        .slave          = &omap44xx_l3_main_2_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* usb_host_hs -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
+        .master         = &omap44xx_usb_host_hs_hwmod,
+        .slave          = &omap44xx_l3_main_2_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* usb_otg_hs -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
+        .master         = &omap44xx_usb_otg_hs_hwmod,
+        .slave          = &omap44xx_l3_main_2_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
+        {
+                .pa_start       = 0x45000000,
+                .pa_end         = 0x45000fff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l3_main_1 -> l3_main_3 */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
+        .master         = &omap44xx_l3_main_1_hwmod,
+        .slave          = &omap44xx_l3_main_3_hwmod,
+        .clk            = "l3_div_ck",
+        .addr           = omap44xx_l3_main_3_addrs,
+        .user           = OCP_USER_MPU,
+};
+/* l3_main_2 -> l3_main_3 */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
+        .master         = &omap44xx_l3_main_2_hwmod,
+        .slave          = &omap44xx_l3_main_3_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_cfg -> l3_main_3 */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_l3_main_3_hwmod,
+        .clk            = "l4_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* aess -> l4_abe */
+static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = {
+        .master         = &omap44xx_aess_hwmod,
+        .slave          = &omap44xx_l4_abe_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* dsp -> l4_abe */
+static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
+        .master         = &omap44xx_dsp_hwmod,
+        .slave          = &omap44xx_l4_abe_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l3_main_1 -> l4_abe */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
+        .master         = &omap44xx_l3_main_1_hwmod,
+        .slave          = &omap44xx_l4_abe_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* mpu -> l4_abe */
+static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
+        .master         = &omap44xx_mpu_hwmod,
+        .slave          = &omap44xx_l4_abe_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l3_main_1 -> l4_cfg */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
+        .master         = &omap44xx_l3_main_1_hwmod,
+        .slave          = &omap44xx_l4_cfg_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l3_main_2 -> l4_per */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
+        .master         = &omap44xx_l3_main_2_hwmod,
+        .slave          = &omap44xx_l4_per_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_cfg -> l4_wkup */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_l4_wkup_hwmod,
+        .clk            = "l4_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* mpu -> mpu_private */
+static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
+        .master         = &omap44xx_mpu_hwmod,
+        .slave          = &omap44xx_mpu_private_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_ocp_wp_noc_addrs[] = {
+        {
+                .pa_start       = 0x4a102000,
+                .pa_end         = 0x4a10207f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_cfg -> ocp_wp_noc */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_ocp_wp_noc_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_ocp_wp_noc_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
+        {
+                .pa_start       = 0x401f1000,
+                .pa_end         = 0x401f13ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_abe -> aess */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = {
        .master         = &omap44xx_l4_abe_hwmod,
-        .slave          = &omap44xx_wd_timer3_hwmod,
+        .slave          = &omap44xx_aess_hwmod,
        .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_wd_timer3_addrs,
+        .addr           = omap44xx_aess_addrs,
        .user           = OCP_USER_MPU,
 };
-static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
+static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
        {
-                .pa_start       = 0x49030000,
+                .pa_start       = 0x490f1000,
-                .pa_end         = 0x4903007f,
+                .pa_end         = 0x490f13ff,
                .flags          = ADDR_TYPE_RT
        },
        { }
 };
-/* l4_abe -> wd_timer3 (dma) */
+/* l4_abe -> aess (dma) */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = {
        .master         = &omap44xx_l4_abe_hwmod,
-        .slave          = &omap44xx_wd_timer3_hwmod,
+        .slave          = &omap44xx_aess_hwmod,
        .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_wd_timer3_dma_addrs,
+        .addr           = omap44xx_aess_dma_addrs,
        .user           = OCP_USER_SDMA,
 };
-/* wd_timer3 slave ports */
+/* l3_main_2 -> c2c */
-static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = {
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = {
-        &omap44xx_l4_abe__wd_timer3,
+        .master         = &omap44xx_l3_main_2_hwmod,
-        &omap44xx_l4_abe__wd_timer3_dma,
+        .slave          = &omap44xx_c2c_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
+static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
-        .name           = "wd_timer3",
+        {
-        .class          = &omap44xx_wd_timer_hwmod_class,
+                .pa_start       = 0x4a304000,
-        .clkdm_name     = "abe_clkdm",
+                .pa_end         = 0x4a30401f,
-        .mpu_irqs       = omap44xx_wd_timer3_irqs,
+                .flags          = ADDR_TYPE_RT
-        .main_clk       = "wd_timer3_fck",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
-                        .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_SWCTRL,
-                },
        },
-        .slaves         = omap44xx_wd_timer3_slaves,
+        { }
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer3_slaves),
 };
-/*
+/* l4_wkup -> counter_32k */
- * 'usb_host_hs' class
+static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
- * high-speed multi-port usb host controller
+        .master         = &omap44xx_l4_wkup_hwmod,
- */
+        .slave          = &omap44xx_counter_32k_hwmod,
-static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
+        .clk            = "l4_wkup_clk_mux_ck",
-        .master         = &omap44xx_usb_host_hs_hwmod,
+        .addr           = omap44xx_counter_32k_addrs,
-        .slave          = &omap44xx_l3_main_2_hwmod,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs[] = {
+        {
+                .pa_start       = 0x4a002000,
+                .pa_end         = 0x4a0027ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_cfg -> ctrl_module_core */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_ctrl_module_core_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_ctrl_module_core_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs[] = {
+        {
+                .pa_start       = 0x4a100000,
+                .pa_end         = 0x4a1007ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_cfg -> ctrl_module_pad_core */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_ctrl_module_pad_core_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_ctrl_module_pad_core_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs[] = {
+        {
+                .pa_start       = 0x4a30c000,
+                .pa_end         = 0x4a30c7ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_wkup -> ctrl_module_wkup */
+static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
+        .master         = &omap44xx_l4_wkup_hwmod,
+        .slave          = &omap44xx_ctrl_module_wkup_hwmod,
+        .clk            = "l4_wkup_clk_mux_ck",
+        .addr           = omap44xx_ctrl_module_wkup_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs[] = {
+        {
+                .pa_start       = 0x4a31e000,
+                .pa_end         = 0x4a31e7ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_wkup -> ctrl_module_pad_wkup */
+static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
+        .master         = &omap44xx_l4_wkup_hwmod,
+        .slave          = &omap44xx_ctrl_module_pad_wkup_hwmod,
+        .clk            = "l4_wkup_clk_mux_ck",
+        .addr           = omap44xx_ctrl_module_pad_wkup_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_debugss_addrs[] = {
+        {
+                .pa_start       = 0x54160000,
+                .pa_end         = 0x54167fff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l3_instr -> debugss */
+static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
+        .master         = &omap44xx_l3_instr_hwmod,
+        .slave          = &omap44xx_debugss_hwmod,
        .clk            = "l3_div_ck",
+        .addr           = omap44xx_debugss_addrs,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
+static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
-        .rev_offs       = 0x0000,
+        {
-        .sysc_offs      = 0x0010,
+                .pa_start       = 0x4a056000,
-        .syss_offs      = 0x0014,
+                .pa_end         = 0x4a056fff,
-        .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
+                .flags          = ADDR_TYPE_RT
-                           SYSC_HAS_SOFTRESET),
+        },
-        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+        { }
-                           SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
-                           MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
-        .sysc_fields    = &omap_hwmod_sysc_type2,
 };
-static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
+/* l4_cfg -> dma_system */
-        .name = "usb_host_hs",
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
-        .sysc = &omap44xx_usb_host_hs_sysc,
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_dma_system_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_dma_system_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-static struct omap_hwmod_ocp_if *omap44xx_usb_host_hs_masters[] = {
+static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
-        &omap44xx_usb_host_hs__l3_main_2,
+        {
+                .name           = "mpu",
+                .pa_start       = 0x4012e000,
+                .pa_end         = 0x4012e07f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_abe -> dmic */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_dmic_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_dmic_addrs,
+        .user           = OCP_USER_MPU,
+};
+static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
+        {
+                .name           = "dma",
+                .pa_start       = 0x4902e000,
+                .pa_end         = 0x4902e07f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_abe -> dmic (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_dmic_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_dmic_dma_addrs,
+        .user           = OCP_USER_SDMA,
+};
+/* dsp -> iva */
+static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
+        .master         = &omap44xx_dsp_hwmod,
+        .slave          = &omap44xx_iva_hwmod,
+        .clk            = "dpll_iva_m5x2_ck",
+        .user           = OCP_USER_DSP,
+};
+/* dsp -> sl2if */
+static struct omap_hwmod_ocp_if omap44xx_dsp__sl2if = {
+        .master         = &omap44xx_dsp_hwmod,
+        .slave          = &omap44xx_sl2if_hwmod,
+        .clk            = "dpll_iva_m5x2_ck",
+        .user           = OCP_USER_DSP,
+};
+/* l4_cfg -> dsp */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_dsp_hwmod,
+        .clk            = "l4_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
+        {
+                .pa_start       = 0x58000000,
+                .pa_end         = 0x5800007f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l3_main_2 -> dss */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
+        .master         = &omap44xx_l3_main_2_hwmod,
+        .slave          = &omap44xx_dss_hwmod,
+        .clk            = "dss_fck",
+        .addr           = omap44xx_dss_dma_addrs,
+        .user           = OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
+        {
+                .pa_start       = 0x48040000,
+                .pa_end         = 0x4804007f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_per -> dss */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_dss_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_dss_addrs,
+        .user           = OCP_USER_MPU,
+};
+static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
+        {
+                .pa_start       = 0x58001000,
+                .pa_end         = 0x58001fff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l3_main_2 -> dss_dispc */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
+        .master         = &omap44xx_l3_main_2_hwmod,
+        .slave          = &omap44xx_dss_dispc_hwmod,
+        .clk            = "dss_fck",
+        .addr           = omap44xx_dss_dispc_dma_addrs,
+        .user           = OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
+        {
+                .pa_start       = 0x48041000,
+                .pa_end         = 0x48041fff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_per -> dss_dispc */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_dss_dispc_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_dss_dispc_addrs,
+        .user           = OCP_USER_MPU,
+};
+static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
+        {
+                .pa_start       = 0x58004000,
+                .pa_end         = 0x580041ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l3_main_2 -> dss_dsi1 */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
+        .master         = &omap44xx_l3_main_2_hwmod,
+        .slave          = &omap44xx_dss_dsi1_hwmod,
+        .clk            = "dss_fck",
+        .addr           = omap44xx_dss_dsi1_dma_addrs,
+        .user           = OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
+        {
+                .pa_start       = 0x48044000,
+                .pa_end         = 0x480441ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_per -> dss_dsi1 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_dss_dsi1_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_dss_dsi1_addrs,
+        .user           = OCP_USER_MPU,
+};
+static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
+        {
+                .pa_start       = 0x58005000,
+                .pa_end         = 0x580051ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l3_main_2 -> dss_dsi2 */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
+        .master         = &omap44xx_l3_main_2_hwmod,
+        .slave          = &omap44xx_dss_dsi2_hwmod,
+        .clk            = "dss_fck",
+        .addr           = omap44xx_dss_dsi2_dma_addrs,
+        .user           = OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
+        {
+                .pa_start       = 0x48045000,
+                .pa_end         = 0x480451ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_per -> dss_dsi2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_dss_dsi2_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_dss_dsi2_addrs,
+        .user           = OCP_USER_MPU,
+};
+static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
+        {
+                .pa_start       = 0x58006000,
+                .pa_end         = 0x58006fff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l3_main_2 -> dss_hdmi */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
+        .master         = &omap44xx_l3_main_2_hwmod,
+        .slave          = &omap44xx_dss_hdmi_hwmod,
+        .clk            = "dss_fck",
+        .addr           = omap44xx_dss_hdmi_dma_addrs,
+        .user           = OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
+        {
+                .pa_start       = 0x48046000,
+                .pa_end         = 0x48046fff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_per -> dss_hdmi */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_dss_hdmi_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_dss_hdmi_addrs,
+        .user           = OCP_USER_MPU,
+};
+static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
+        {
+                .pa_start       = 0x58002000,
+                .pa_end         = 0x580020ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l3_main_2 -> dss_rfbi */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
+        .master         = &omap44xx_l3_main_2_hwmod,
+        .slave          = &omap44xx_dss_rfbi_hwmod,
+        .clk            = "dss_fck",
+        .addr           = omap44xx_dss_rfbi_dma_addrs,
+        .user           = OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
+        {
+                .pa_start       = 0x48042000,
+                .pa_end         = 0x480420ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_per -> dss_rfbi */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_dss_rfbi_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_dss_rfbi_addrs,
+        .user           = OCP_USER_MPU,
+};
+static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
+        {
+                .pa_start       = 0x58003000,
+                .pa_end         = 0x580030ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l3_main_2 -> dss_venc */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
+        .master         = &omap44xx_l3_main_2_hwmod,
+        .slave          = &omap44xx_dss_venc_hwmod,
+        .clk            = "dss_fck",
+        .addr           = omap44xx_dss_venc_dma_addrs,
+        .user           = OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
+        {
+                .pa_start       = 0x48043000,
+                .pa_end         = 0x480430ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_per -> dss_venc */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_dss_venc_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_dss_venc_addrs,
+        .user           = OCP_USER_MPU,
+};
+static struct omap_hwmod_addr_space omap44xx_elm_addrs[] = {
+        {
+                .pa_start       = 0x48078000,
+                .pa_end         = 0x48078fff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_per -> elm */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_elm_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_elm_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_emif1_addrs[] = {
+        {
+                .pa_start       = 0x4c000000,
+                .pa_end         = 0x4c0000ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* emif_fw -> emif1 */
+static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif1 = {
+        .master         = &omap44xx_emif_fw_hwmod,
+        .slave          = &omap44xx_emif1_hwmod,
+        .clk            = "l3_div_ck",
+        .addr           = omap44xx_emif1_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_emif2_addrs[] = {
+        {
+                .pa_start       = 0x4d000000,
+                .pa_end         = 0x4d0000ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* emif_fw -> emif2 */
+static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif2 = {
+        .master         = &omap44xx_emif_fw_hwmod,
+        .slave          = &omap44xx_emif2_hwmod,
+        .clk            = "l3_div_ck",
+        .addr           = omap44xx_emif2_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = {
+        {
+                .pa_start       = 0x4a10a000,
+                .pa_end         = 0x4a10a1ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_cfg -> fdif */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_fdif_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_fdif_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
+        {
+                .pa_start       = 0x4a310000,
+                .pa_end         = 0x4a3101ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_wkup -> gpio1 */
+static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
+        .master         = &omap44xx_l4_wkup_hwmod,
+        .slave          = &omap44xx_gpio1_hwmod,
+        .clk            = "l4_wkup_clk_mux_ck",
+        .addr           = omap44xx_gpio1_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
+        {
+                .pa_start       = 0x48055000,
+                .pa_end         = 0x480551ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_per -> gpio2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_gpio2_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_gpio2_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
+        {
+                .pa_start       = 0x48057000,
+                .pa_end         = 0x480571ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_per -> gpio3 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_gpio3_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_gpio3_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
+        {
+                .pa_start       = 0x48059000,
+                .pa_end         = 0x480591ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_per -> gpio4 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_gpio4_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_gpio4_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
+        {
+                .pa_start       = 0x4805b000,
+                .pa_end         = 0x4805b1ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_per -> gpio5 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_gpio5_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_gpio5_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
+        {
+                .pa_start       = 0x4805d000,
+                .pa_end         = 0x4805d1ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_per -> gpio6 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_gpio6_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_gpio6_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_gpmc_addrs[] = {
+        {
+                .pa_start       = 0x50000000,
+                .pa_end         = 0x500003ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l3_main_2 -> gpmc */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
+        .master         = &omap44xx_l3_main_2_hwmod,
+        .slave          = &omap44xx_gpmc_hwmod,
+        .clk            = "l3_div_ck",
+        .addr           = omap44xx_gpmc_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_gpu_addrs[] = {
+        {
+                .pa_start       = 0x56000000,
+                .pa_end         = 0x5600ffff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l3_main_2 -> gpu */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = {
+        .master         = &omap44xx_l3_main_2_hwmod,
+        .slave          = &omap44xx_gpu_hwmod,
+        .clk            = "l3_div_ck",
+        .addr           = omap44xx_gpu_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = {
+        {
+                .pa_start       = 0x480b2000,
+                .pa_end         = 0x480b201f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_per -> hdq1w */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_hdq1w_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_hdq1w_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
+        {
+                .pa_start       = 0x4a058000,
+                .pa_end         = 0x4a05bfff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_cfg -> hsi */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_hsi_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_hsi_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
+        {
+                .pa_start       = 0x48070000,
+                .pa_end         = 0x480700ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_per -> i2c1 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_i2c1_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_i2c1_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
+        {
+                .pa_start       = 0x48072000,
+                .pa_end         = 0x480720ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_per -> i2c2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_i2c2_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_i2c2_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
+        {
+                .pa_start       = 0x48060000,
+                .pa_end         = 0x480600ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_per -> i2c3 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_i2c3_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_i2c3_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
+        {
+                .pa_start       = 0x48350000,
+                .pa_end         = 0x483500ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_per -> i2c4 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_i2c4_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_i2c4_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l3_main_2 -> ipu */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
+        .master         = &omap44xx_l3_main_2_hwmod,
+        .slave          = &omap44xx_ipu_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
+        {
+                .pa_start       = 0x52000000,
+                .pa_end         = 0x520000ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l3_main_2 -> iss */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
+        .master         = &omap44xx_l3_main_2_hwmod,
+        .slave          = &omap44xx_iss_hwmod,
+        .clk            = "l3_div_ck",
+        .addr           = omap44xx_iss_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* iva -> sl2if */
+static struct omap_hwmod_ocp_if omap44xx_iva__sl2if = {
+        .master         = &omap44xx_iva_hwmod,
+        .slave          = &omap44xx_sl2if_hwmod,
+        .clk            = "dpll_iva_m5x2_ck",
+        .user           = OCP_USER_IVA,
+};
+static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
+        {
+                .pa_start       = 0x5a000000,
+                .pa_end         = 0x5a07ffff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l3_main_2 -> iva */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
+        .master         = &omap44xx_l3_main_2_hwmod,
+        .slave          = &omap44xx_iva_hwmod,
+        .clk            = "l3_div_ck",
+        .addr           = omap44xx_iva_addrs,
+        .user           = OCP_USER_MPU,
+};
+static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
+        {
+                .pa_start       = 0x4a31c000,
+                .pa_end         = 0x4a31c07f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_wkup -> kbd */
+static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
+        .master         = &omap44xx_l4_wkup_hwmod,
+        .slave          = &omap44xx_kbd_hwmod,
+        .clk            = "l4_wkup_clk_mux_ck",
+        .addr           = omap44xx_kbd_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
+        {
+                .pa_start       = 0x4a0f4000,
+                .pa_end         = 0x4a0f41ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_cfg -> mailbox */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_mailbox_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_mailbox_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_mcasp_addrs[] = {
+        {
+                .pa_start       = 0x40128000,
+                .pa_end         = 0x401283ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_abe -> mcasp */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_mcasp_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_mcasp_addrs,
+        .user           = OCP_USER_MPU,
+};
+static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs[] = {
+        {
+                .pa_start       = 0x49028000,
+                .pa_end         = 0x490283ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_abe -> mcasp (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_mcasp_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_mcasp_dma_addrs,
+        .user           = OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
+        {
+                .name           = "mpu",
+                .pa_start       = 0x40122000,
+                .pa_end         = 0x401220ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_abe -> mcbsp1 */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_mcbsp1_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_mcbsp1_addrs,
+        .user           = OCP_USER_MPU,
+};
+static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
+        {
+                .name           = "dma",
+                .pa_start       = 0x49022000,
+                .pa_end         = 0x490220ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_abe -> mcbsp1 (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_mcbsp1_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_mcbsp1_dma_addrs,
+        .user           = OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
+        {
+                .name           = "mpu",
+                .pa_start       = 0x40124000,
+                .pa_end         = 0x401240ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_abe -> mcbsp2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_mcbsp2_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_mcbsp2_addrs,
+        .user           = OCP_USER_MPU,
+};
+static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
+        {
+                .name           = "dma",
+                .pa_start       = 0x49024000,
+                .pa_end         = 0x490240ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_abe -> mcbsp2 (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_mcbsp2_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_mcbsp2_dma_addrs,
+        .user           = OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
+        {
+                .name           = "mpu",
+                .pa_start       = 0x40126000,
+                .pa_end         = 0x401260ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_abe -> mcbsp3 */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_mcbsp3_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_mcbsp3_addrs,
+        .user           = OCP_USER_MPU,
+};
+static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
+        {
+                .name           = "dma",
+                .pa_start       = 0x49026000,
+                .pa_end         = 0x490260ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_abe -> mcbsp3 (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_mcbsp3_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_mcbsp3_dma_addrs,
+        .user           = OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
+        {
+                .pa_start       = 0x48096000,
+                .pa_end         = 0x480960ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_per -> mcbsp4 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_mcbsp4_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_mcbsp4_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
+        {
+                .pa_start       = 0x40132000,
+                .pa_end         = 0x4013207f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_abe -> mcpdm */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_mcpdm_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_mcpdm_addrs,
+        .user           = OCP_USER_MPU,
+};
+static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
+        {
+                .pa_start       = 0x49032000,
+                .pa_end         = 0x4903207f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_abe -> mcpdm (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_mcpdm_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_mcpdm_dma_addrs,
+        .user           = OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
+        {
+                .pa_start       = 0x48098000,
+                .pa_end         = 0x480981ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_per -> mcspi1 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_mcspi1_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_mcspi1_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
+        {
+                .pa_start       = 0x4809a000,
+                .pa_end         = 0x4809a1ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_per -> mcspi2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_mcspi2_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_mcspi2_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
+        {
+                .pa_start       = 0x480b8000,
+                .pa_end         = 0x480b81ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_per -> mcspi3 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_mcspi3_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_mcspi3_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
+        {
+                .pa_start       = 0x480ba000,
+                .pa_end         = 0x480ba1ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_per -> mcspi4 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_mcspi4_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_mcspi4_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
+        {
+                .pa_start       = 0x4809c000,
+                .pa_end         = 0x4809c3ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_per -> mmc1 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_mmc1_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_mmc1_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
+        {
+                .pa_start       = 0x480b4000,
+                .pa_end         = 0x480b43ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_per -> mmc2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_mmc2_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_mmc2_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
+        {
+                .pa_start       = 0x480ad000,
+                .pa_end         = 0x480ad3ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_per -> mmc3 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_mmc3_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_mmc3_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
+        {
+                .pa_start       = 0x480d1000,
+                .pa_end         = 0x480d13ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_per -> mmc4 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_mmc4_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_mmc4_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
+        {
+                .pa_start       = 0x480d5000,
+                .pa_end         = 0x480d53ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_per -> mmc5 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_mmc5_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_mmc5_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l3_main_2 -> ocmc_ram */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
+        .master         = &omap44xx_l3_main_2_hwmod,
+        .slave          = &omap44xx_ocmc_ram_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l4_cfg -> ocp2scp_usb_phy */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_ocp2scp_usb_phy_hwmod,
+        .clk            = "l4_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_prcm_mpu_addrs[] = {
+        {
+                .pa_start       = 0x48243000,
+                .pa_end         = 0x48243fff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* mpu_private -> prcm_mpu */
+static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
+        .master         = &omap44xx_mpu_private_hwmod,
+        .slave          = &omap44xx_prcm_mpu_hwmod,
+        .clk            = "l3_div_ck",
+        .addr           = omap44xx_prcm_mpu_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_cm_core_aon_addrs[] = {
+        {
+                .pa_start       = 0x4a004000,
+                .pa_end         = 0x4a004fff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_wkup -> cm_core_aon */
+static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
+        .master         = &omap44xx_l4_wkup_hwmod,
+        .slave          = &omap44xx_cm_core_aon_hwmod,
+        .clk            = "l4_wkup_clk_mux_ck",
+        .addr           = omap44xx_cm_core_aon_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_cm_core_addrs[] = {
+        {
+                .pa_start       = 0x4a008000,
+                .pa_end         = 0x4a009fff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_cfg -> cm_core */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_cm_core_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_cm_core_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_prm_addrs[] = {
+        {
+                .pa_start       = 0x4a306000,
+                .pa_end         = 0x4a307fff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_wkup -> prm */
+static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
+        .master         = &omap44xx_l4_wkup_hwmod,
+        .slave          = &omap44xx_prm_hwmod,
+        .clk            = "l4_wkup_clk_mux_ck",
+        .addr           = omap44xx_prm_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_scrm_addrs[] = {
+        {
+                .pa_start       = 0x4a30a000,
+                .pa_end         = 0x4a30a7ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_wkup -> scrm */
+static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
+        .master         = &omap44xx_l4_wkup_hwmod,
+        .slave          = &omap44xx_scrm_hwmod,
+        .clk            = "l4_wkup_clk_mux_ck",
+        .addr           = omap44xx_scrm_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l3_main_2 -> sl2if */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__sl2if = {
+        .master         = &omap44xx_l3_main_2_hwmod,
+        .slave          = &omap44xx_sl2if_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs[] = {
+        {
+                .pa_start       = 0x4012c000,
+                .pa_end         = 0x4012c3ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_abe -> slimbus1 */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_slimbus1_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_slimbus1_addrs,
+        .user           = OCP_USER_MPU,
+};
+static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs[] = {
+        {
+                .pa_start       = 0x4902c000,
+                .pa_end         = 0x4902c3ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_abe -> slimbus1 (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_slimbus1_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_slimbus1_dma_addrs,
+        .user           = OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs[] = {
+        {
+                .pa_start       = 0x48076000,
+                .pa_end         = 0x480763ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_per -> slimbus2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_slimbus2_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_slimbus2_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
+        {
+                .pa_start       = 0x4a0dd000,
+                .pa_end         = 0x4a0dd03f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_cfg -> smartreflex_core */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_smartreflex_core_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_smartreflex_core_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
+        {
+                .pa_start       = 0x4a0db000,
+                .pa_end         = 0x4a0db03f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_cfg -> smartreflex_iva */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_smartreflex_iva_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_smartreflex_iva_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
+        {
+                .pa_start       = 0x4a0d9000,
+                .pa_end         = 0x4a0d903f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_cfg -> smartreflex_mpu */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_smartreflex_mpu_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_smartreflex_mpu_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
+        {
+                .pa_start       = 0x4a0f6000,
+                .pa_end         = 0x4a0f6fff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_cfg -> spinlock */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_spinlock_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_spinlock_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
+        {
+                .pa_start       = 0x4a318000,
+                .pa_end         = 0x4a31807f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_wkup -> timer1 */
+static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
+        .master         = &omap44xx_l4_wkup_hwmod,
+        .slave          = &omap44xx_timer1_hwmod,
+        .clk            = "l4_wkup_clk_mux_ck",
+        .addr           = omap44xx_timer1_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
+        {
+                .pa_start       = 0x48032000,
+                .pa_end         = 0x4803207f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_per -> timer2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_timer2_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_timer2_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
+        {
+                .pa_start       = 0x48034000,
+                .pa_end         = 0x4803407f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_per -> timer3 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_timer3_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_timer3_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
+        {
+                .pa_start       = 0x48036000,
+                .pa_end         = 0x4803607f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_per -> timer4 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_timer4_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_timer4_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
+        {
+                .pa_start       = 0x40138000,
+                .pa_end         = 0x4013807f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_abe -> timer5 */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_timer5_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_timer5_addrs,
+        .user           = OCP_USER_MPU,
+};
+static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
+        {
+                .pa_start       = 0x49038000,
+                .pa_end         = 0x4903807f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_abe -> timer5 (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_timer5_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_timer5_dma_addrs,
+        .user           = OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
+        {
+                .pa_start       = 0x4013a000,
+                .pa_end         = 0x4013a07f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_abe -> timer6 */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_timer6_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_timer6_addrs,
+        .user           = OCP_USER_MPU,
+};
+static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
+        {
+                .pa_start       = 0x4903a000,
+                .pa_end         = 0x4903a07f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_abe -> timer6 (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_timer6_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_timer6_dma_addrs,
+        .user           = OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
+        {
+                .pa_start       = 0x4013c000,
+                .pa_end         = 0x4013c07f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_abe -> timer7 */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_timer7_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_timer7_addrs,
+        .user           = OCP_USER_MPU,
+};
+static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
+        {
+                .pa_start       = 0x4903c000,
+                .pa_end         = 0x4903c07f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_abe -> timer7 (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_timer7_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_timer7_dma_addrs,
+        .user           = OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
+        {
+                .pa_start       = 0x4013e000,
+                .pa_end         = 0x4013e07f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_abe -> timer8 */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_timer8_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_timer8_addrs,
+        .user           = OCP_USER_MPU,
+};
+static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
+        {
+                .pa_start       = 0x4903e000,
+                .pa_end         = 0x4903e07f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_abe -> timer8 (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
+        .master         = &omap44xx_l4_abe_hwmod,
+        .slave          = &omap44xx_timer8_hwmod,
+        .clk            = "ocp_abe_iclk",
+        .addr           = omap44xx_timer8_dma_addrs,
+        .user           = OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
+        {
+                .pa_start       = 0x4803e000,
+                .pa_end         = 0x4803e07f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_per -> timer9 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_timer9_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_timer9_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
+        {
+                .pa_start       = 0x48086000,
+                .pa_end         = 0x4808607f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_per -> timer10 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_timer10_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_timer10_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
+        {
+                .pa_start       = 0x48088000,
+                .pa_end         = 0x4808807f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_per -> timer11 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_timer11_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_timer11_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
+        {
+                .pa_start       = 0x4806a000,
+                .pa_end         = 0x4806a0ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_per -> uart1 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_uart1_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_uart1_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
+        {
+                .pa_start       = 0x4806c000,
+                .pa_end         = 0x4806c0ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_per -> uart2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_uart2_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_uart2_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
+        {
+                .pa_start       = 0x48020000,
+                .pa_end         = 0x480200ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_per -> uart3 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_uart3_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_uart3_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
+        {
+                .pa_start       = 0x4806e000,
+                .pa_end         = 0x4806e0ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_per -> uart4 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
+        .master         = &omap44xx_l4_per_hwmod,
+        .slave          = &omap44xx_uart4_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_uart4_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_addr_space omap44xx_usb_host_fs_addrs[] = {
+        {
+                .pa_start       = 0x4a0a9000,
+                .pa_end         = 0x4a0a93ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+/* l4_cfg -> usb_host_fs */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_fs = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_usb_host_fs_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_usb_host_fs_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = {
@@ -5373,12 +5881,7 @@ static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = {
        {}
 };
-static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = {
+/* l4_cfg -> usb_host_hs */
-        { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START },
-        { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
        .master         = &omap44xx_l4_cfg_hwmod,
        .slave          = &omap44xx_usb_host_hs_hwmod,
@@ -5387,100 +5890,22 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-static struct omap_hwmod_ocp_if *omap44xx_usb_host_hs_slaves[] = {
+static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
-        &omap44xx_l4_cfg__usb_host_hs,
+        {
-};
+                .pa_start       = 0x4a0ab000,
+                .pa_end         = 0x4a0ab003,
-static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
+                .flags          = ADDR_TYPE_RT
-        .name           = "usb_host_hs",
-        .class          = &omap44xx_usb_host_hs_hwmod_class,
-        .clkdm_name     = "l3_init_clkdm",
-        .main_clk       = "usb_host_hs_fck",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
-                        .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_SWCTRL,
-                },
        },
-        .mpu_irqs       = omap44xx_usb_host_hs_irqs,
+        { }
-        .slaves         = omap44xx_usb_host_hs_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_usb_host_hs_slaves),
-        .masters        = omap44xx_usb_host_hs_masters,
-        .masters_cnt    = ARRAY_SIZE(omap44xx_usb_host_hs_masters),
-        /*
-         * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
-         * id: i660
-         *
-         * Description:
-         * In the following configuration :
-         * - USBHOST module is set to smart-idle mode
-         * - PRCM asserts idle_req to the USBHOST module ( This typically
-         *   happens when the system is going to a low power mode : all ports
-         *   have been suspended, the master part of the USBHOST module has
-         *   entered the standby state, and SW has cut the functional clocks)
-         * - an USBHOST interrupt occurs before the module is able to answer
-         *   idle_ack, typically a remote wakeup IRQ.
-         * Then the USB HOST module will enter a deadlock situation where it
-         * is no more accessible nor functional.
-         *
-         * Workaround:
-         * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
-         */
-        /*
-         * Errata: USB host EHCI may stall when entering smart-standby mode
-         * Id: i571
-         *
-         * Description:
-         * When the USBHOST module is set to smart-standby mode, and when it is
-         * ready to enter the standby state (i.e. all ports are suspended and
-         * all attached devices are in suspend mode), then it can wrongly assert
-         * the Mstandby signal too early while there are still some residual OCP
-         * transactions ongoing. If this condition occurs, the internal state
-         * machine may go to an undefined state and the USB link may be stuck
-         * upon the next resume.
-         *
-         * Workaround:
-         * Don't use smart standby; use only force standby,
-         * hence HWMOD_SWSUP_MSTANDBY
-         */
-        /*
-         * During system boot; If the hwmod framework resets the module
-         * the module will have smart idle settings; which can lead to deadlock
-         * (above Errata Id:i660); so, dont reset the module during boot;
-         * Use HWMOD_INIT_NO_RESET.
-         */
-        .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
-                          HWMOD_INIT_NO_RESET,
-};
-/*
- * 'usb_tll_hs' class
- * usb_tll_hs module is the adapter on the usb_host_hs ports
- */
-static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
-        .rev_offs       = 0x0000,
-        .sysc_offs      = 0x0010,
-        .syss_offs      = 0x0014,
-        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
-                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
-                           SYSC_HAS_AUTOIDLE),
-        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
-        .sysc_fields    = &omap_hwmod_sysc_type1,
-};
-static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
-        .name = "usb_tll_hs",
-        .sysc = &omap44xx_usb_tll_hs_sysc,
 };
-static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = {
+/* l4_cfg -> usb_otg_hs */
-        { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START },
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
-        { .irq = -1 }
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_usb_otg_hs_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_usb_otg_hs_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = {
@@ -5493,6 +5918,7 @@ static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = {
        {}
 };
+/* l4_cfg -> usb_tll_hs */
 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
        .master         = &omap44xx_l4_cfg_hwmod,
        .slave          = &omap44xx_usb_tll_hs_hwmod,
@@ -5501,181 +5927,223 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-static struct omap_hwmod_ocp_if *omap44xx_usb_tll_hs_slaves[] = {
+static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
-        &omap44xx_l4_cfg__usb_tll_hs,
+        {
+                .pa_start       = 0x4a314000,
+                .pa_end         = 0x4a31407f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
 };
-static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
+/* l4_wkup -> wd_timer2 */
-        .name           = "usb_tll_hs",
+static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
-        .class          = &omap44xx_usb_tll_hs_hwmod_class,
+        .master         = &omap44xx_l4_wkup_hwmod,
-        .clkdm_name     = "l3_init_clkdm",
+        .slave          = &omap44xx_wd_timer2_hwmod,
-        .main_clk       = "usb_tll_hs_ick",
+        .clk            = "l4_wkup_clk_mux_ck",
-        .prcm = {
+        .addr           = omap44xx_wd_timer2_addrs,
-                .omap4 = {
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-                        .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
+};
-                        .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
-                        .modulemode   = MODULEMODE_HWCTRL,
+static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
-                },
+        {
+                .pa_start       = 0x40130000,
+                .pa_end         = 0x4013007f,
+                .flags          = ADDR_TYPE_RT
        },
-        .mpu_irqs       = omap44xx_usb_tll_hs_irqs,
+        { }
-        .slaves         = omap44xx_usb_tll_hs_slaves,
-        .slaves_cnt     = ARRAY_SIZE(omap44xx_usb_tll_hs_slaves),
 };
-static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
+/* l4_abe -> wd_timer3 */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
-        /* dmm class */
+        .master         = &omap44xx_l4_abe_hwmod,
-        &omap44xx_dmm_hwmod,
+        .slave          = &omap44xx_wd_timer3_hwmod,
+        .clk            = "ocp_abe_iclk",
-        /* emif_fw class */
+        .addr           = omap44xx_wd_timer3_addrs,
-        &omap44xx_emif_fw_hwmod,
+        .user           = OCP_USER_MPU,
+};
-        /* l3 class */
-        &omap44xx_l3_instr_hwmod,
+static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
-        &omap44xx_l3_main_1_hwmod,
+        {
-        &omap44xx_l3_main_2_hwmod,
+                .pa_start       = 0x49030000,
-        &omap44xx_l3_main_3_hwmod,
+                .pa_end         = 0x4903007f,
+                .flags          = ADDR_TYPE_RT
-        /* l4 class */
+        },
-        &omap44xx_l4_abe_hwmod,
+        { }
-        &omap44xx_l4_cfg_hwmod,
+};
-        &omap44xx_l4_per_hwmod,
-        &omap44xx_l4_wkup_hwmod,
+/* l4_abe -> wd_timer3 (dma) */
+static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
-        /* mpu_bus class */
+        .master         = &omap44xx_l4_abe_hwmod,
-        &omap44xx_mpu_private_hwmod,
+        .slave          = &omap44xx_wd_timer3_hwmod,
+        .clk            = "ocp_abe_iclk",
-        /* aess class */
+        .addr           = omap44xx_wd_timer3_dma_addrs,
-/*      &omap44xx_aess_hwmod, */
+        .user           = OCP_USER_SDMA,
+};
-        /* bandgap class */
-        &omap44xx_bandgap_hwmod,
+static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
+        &omap44xx_c2c__c2c_target_fw,
-        /* counter class */
+        &omap44xx_l4_cfg__c2c_target_fw,
-/*      &omap44xx_counter_32k_hwmod, */
+        &omap44xx_l3_main_1__dmm,
+        &omap44xx_mpu__dmm,
-        /* dma class */
+        &omap44xx_c2c__emif_fw,
-        &omap44xx_dma_system_hwmod,
+        &omap44xx_dmm__emif_fw,
+        &omap44xx_l4_cfg__emif_fw,
-        /* dmic class */
+        &omap44xx_iva__l3_instr,
-        &omap44xx_dmic_hwmod,
+        &omap44xx_l3_main_3__l3_instr,
+        &omap44xx_ocp_wp_noc__l3_instr,
-        /* dsp class */
+        &omap44xx_dsp__l3_main_1,
-        &omap44xx_dsp_hwmod,
+        &omap44xx_dss__l3_main_1,
-        &omap44xx_dsp_c0_hwmod,
+        &omap44xx_l3_main_2__l3_main_1,
+        &omap44xx_l4_cfg__l3_main_1,
-        /* dss class */
+        &omap44xx_mmc1__l3_main_1,
-        &omap44xx_dss_hwmod,
+        &omap44xx_mmc2__l3_main_1,
-        &omap44xx_dss_dispc_hwmod,
+        &omap44xx_mpu__l3_main_1,
-        &omap44xx_dss_dsi1_hwmod,
+        &omap44xx_c2c_target_fw__l3_main_2,
-        &omap44xx_dss_dsi2_hwmod,
+        &omap44xx_debugss__l3_main_2,
-        &omap44xx_dss_hdmi_hwmod,
+        &omap44xx_dma_system__l3_main_2,
-        &omap44xx_dss_rfbi_hwmod,
+        &omap44xx_fdif__l3_main_2,
-        &omap44xx_dss_venc_hwmod,
+        &omap44xx_gpu__l3_main_2,
+        &omap44xx_hsi__l3_main_2,
-        /* gpio class */
+        &omap44xx_ipu__l3_main_2,
-        &omap44xx_gpio1_hwmod,
+        &omap44xx_iss__l3_main_2,
-        &omap44xx_gpio2_hwmod,
+        &omap44xx_iva__l3_main_2,
-        &omap44xx_gpio3_hwmod,
+        &omap44xx_l3_main_1__l3_main_2,
-        &omap44xx_gpio4_hwmod,
+        &omap44xx_l4_cfg__l3_main_2,
-        &omap44xx_gpio5_hwmod,
+        &omap44xx_usb_host_fs__l3_main_2,
-        &omap44xx_gpio6_hwmod,
+        &omap44xx_usb_host_hs__l3_main_2,
+        &omap44xx_usb_otg_hs__l3_main_2,
-        /* hsi class */
+        &omap44xx_l3_main_1__l3_main_3,
-/*      &omap44xx_hsi_hwmod, */
+        &omap44xx_l3_main_2__l3_main_3,
+        &omap44xx_l4_cfg__l3_main_3,
-        /* i2c class */
+        &omap44xx_aess__l4_abe,
-        &omap44xx_i2c1_hwmod,
+        &omap44xx_dsp__l4_abe,
-        &omap44xx_i2c2_hwmod,
+        &omap44xx_l3_main_1__l4_abe,
-        &omap44xx_i2c3_hwmod,
+        &omap44xx_mpu__l4_abe,
-        &omap44xx_i2c4_hwmod,
+        &omap44xx_l3_main_1__l4_cfg,
+        &omap44xx_l3_main_2__l4_per,
-        /* ipu class */
+        &omap44xx_l4_cfg__l4_wkup,
-        &omap44xx_ipu_hwmod,
+        &omap44xx_mpu__mpu_private,
-        &omap44xx_ipu_c0_hwmod,
+        &omap44xx_l4_cfg__ocp_wp_noc,
-        &omap44xx_ipu_c1_hwmod,
+        &omap44xx_l4_abe__aess,
+        &omap44xx_l4_abe__aess_dma,
-        /* iss class */
+        &omap44xx_l3_main_2__c2c,
-/*      &omap44xx_iss_hwmod, */
+        &omap44xx_l4_wkup__counter_32k,
+        &omap44xx_l4_cfg__ctrl_module_core,
-        /* iva class */
+        &omap44xx_l4_cfg__ctrl_module_pad_core,
-        &omap44xx_iva_hwmod,
+        &omap44xx_l4_wkup__ctrl_module_wkup,
-        &omap44xx_iva_seq0_hwmod,
+        &omap44xx_l4_wkup__ctrl_module_pad_wkup,
-        &omap44xx_iva_seq1_hwmod,
+        &omap44xx_l3_instr__debugss,
+        &omap44xx_l4_cfg__dma_system,
-        /* kbd class */
+        &omap44xx_l4_abe__dmic,
-        &omap44xx_kbd_hwmod,
+        &omap44xx_l4_abe__dmic_dma,
+        &omap44xx_dsp__iva,
-        /* mailbox class */
+        &omap44xx_dsp__sl2if,
-        &omap44xx_mailbox_hwmod,
+        &omap44xx_l4_cfg__dsp,
+        &omap44xx_l3_main_2__dss,
-        /* mcbsp class */
+        &omap44xx_l4_per__dss,
-        &omap44xx_mcbsp1_hwmod,
+        &omap44xx_l3_main_2__dss_dispc,
-        &omap44xx_mcbsp2_hwmod,
+        &omap44xx_l4_per__dss_dispc,
-        &omap44xx_mcbsp3_hwmod,
+        &omap44xx_l3_main_2__dss_dsi1,
-        &omap44xx_mcbsp4_hwmod,
+        &omap44xx_l4_per__dss_dsi1,
+        &omap44xx_l3_main_2__dss_dsi2,
-        /* mcpdm class */
+        &omap44xx_l4_per__dss_dsi2,
-        &omap44xx_mcpdm_hwmod,
+        &omap44xx_l3_main_2__dss_hdmi,
+        &omap44xx_l4_per__dss_hdmi,
-        /* mcspi class */
+        &omap44xx_l3_main_2__dss_rfbi,
-        &omap44xx_mcspi1_hwmod,
+        &omap44xx_l4_per__dss_rfbi,
-        &omap44xx_mcspi2_hwmod,
+        &omap44xx_l3_main_2__dss_venc,
-        &omap44xx_mcspi3_hwmod,
+        &omap44xx_l4_per__dss_venc,
-        &omap44xx_mcspi4_hwmod,
+        &omap44xx_l4_per__elm,
+        &omap44xx_emif_fw__emif1,
-        /* mmc class */
+        &omap44xx_emif_fw__emif2,
-        &omap44xx_mmc1_hwmod,
+        &omap44xx_l4_cfg__fdif,
-        &omap44xx_mmc2_hwmod,
+        &omap44xx_l4_wkup__gpio1,
-        &omap44xx_mmc3_hwmod,
+        &omap44xx_l4_per__gpio2,
-        &omap44xx_mmc4_hwmod,
+        &omap44xx_l4_per__gpio3,
-        &omap44xx_mmc5_hwmod,
+        &omap44xx_l4_per__gpio4,
+        &omap44xx_l4_per__gpio5,
-        /* mpu class */
+        &omap44xx_l4_per__gpio6,
-        &omap44xx_mpu_hwmod,
+        &omap44xx_l3_main_2__gpmc,
+        &omap44xx_l3_main_2__gpu,
-        /* smartreflex class */
+        &omap44xx_l4_per__hdq1w,
-        &omap44xx_smartreflex_core_hwmod,
+        &omap44xx_l4_cfg__hsi,
-        &omap44xx_smartreflex_iva_hwmod,
+        &omap44xx_l4_per__i2c1,
-        &omap44xx_smartreflex_mpu_hwmod,
+        &omap44xx_l4_per__i2c2,
+        &omap44xx_l4_per__i2c3,
-        /* spinlock class */
+        &omap44xx_l4_per__i2c4,
-        &omap44xx_spinlock_hwmod,
+        &omap44xx_l3_main_2__ipu,
+        &omap44xx_l3_main_2__iss,
-        /* timer class */
+        &omap44xx_iva__sl2if,
-        &omap44xx_timer1_hwmod,
+        &omap44xx_l3_main_2__iva,
-        &omap44xx_timer2_hwmod,
+        &omap44xx_l4_wkup__kbd,
-        &omap44xx_timer3_hwmod,
+        &omap44xx_l4_cfg__mailbox,
-        &omap44xx_timer4_hwmod,
+        &omap44xx_l4_abe__mcasp,
-        &omap44xx_timer5_hwmod,
+        &omap44xx_l4_abe__mcasp_dma,
-        &omap44xx_timer6_hwmod,
+        &omap44xx_l4_abe__mcbsp1,
-        &omap44xx_timer7_hwmod,
+        &omap44xx_l4_abe__mcbsp1_dma,
-        &omap44xx_timer8_hwmod,
+        &omap44xx_l4_abe__mcbsp2,
-        &omap44xx_timer9_hwmod,
+        &omap44xx_l4_abe__mcbsp2_dma,
-        &omap44xx_timer10_hwmod,
+        &omap44xx_l4_abe__mcbsp3,
-        &omap44xx_timer11_hwmod,
+        &omap44xx_l4_abe__mcbsp3_dma,
+        &omap44xx_l4_per__mcbsp4,
-        /* uart class */
+        &omap44xx_l4_abe__mcpdm,
-        &omap44xx_uart1_hwmod,
+        &omap44xx_l4_abe__mcpdm_dma,
-        &omap44xx_uart2_hwmod,
+        &omap44xx_l4_per__mcspi1,
-        &omap44xx_uart3_hwmod,
+        &omap44xx_l4_per__mcspi2,
-        &omap44xx_uart4_hwmod,
+        &omap44xx_l4_per__mcspi3,
+        &omap44xx_l4_per__mcspi4,
-        /* usb host class */
+        &omap44xx_l4_per__mmc1,
-        &omap44xx_usb_host_hs_hwmod,
+        &omap44xx_l4_per__mmc2,
-        &omap44xx_usb_tll_hs_hwmod,
+        &omap44xx_l4_per__mmc3,
+        &omap44xx_l4_per__mmc4,
-        /* usb_otg_hs class */
+        &omap44xx_l4_per__mmc5,
-        &omap44xx_usb_otg_hs_hwmod,
+        &omap44xx_l3_main_2__ocmc_ram,
+        &omap44xx_l4_cfg__ocp2scp_usb_phy,
-        /* wd_timer class */
+        &omap44xx_mpu_private__prcm_mpu,
-        &omap44xx_wd_timer2_hwmod,
+        &omap44xx_l4_wkup__cm_core_aon,
-        &omap44xx_wd_timer3_hwmod,
+        &omap44xx_l4_cfg__cm_core,
+        &omap44xx_l4_wkup__prm,
+        &omap44xx_l4_wkup__scrm,
+        &omap44xx_l3_main_2__sl2if,
+        &omap44xx_l4_abe__slimbus1,
+        &omap44xx_l4_abe__slimbus1_dma,
+        &omap44xx_l4_per__slimbus2,
+        &omap44xx_l4_cfg__smartreflex_core,
+        &omap44xx_l4_cfg__smartreflex_iva,
+        &omap44xx_l4_cfg__smartreflex_mpu,
+        &omap44xx_l4_cfg__spinlock,
+        &omap44xx_l4_wkup__timer1,
+        &omap44xx_l4_per__timer2,
+        &omap44xx_l4_per__timer3,
+        &omap44xx_l4_per__timer4,
+        &omap44xx_l4_abe__timer5,
+        &omap44xx_l4_abe__timer5_dma,
+        &omap44xx_l4_abe__timer6,
+        &omap44xx_l4_abe__timer6_dma,
+        &omap44xx_l4_abe__timer7,
+        &omap44xx_l4_abe__timer7_dma,
+        &omap44xx_l4_abe__timer8,
+        &omap44xx_l4_abe__timer8_dma,
+        &omap44xx_l4_per__timer9,
+        &omap44xx_l4_per__timer10,
+        &omap44xx_l4_per__timer11,
+        &omap44xx_l4_per__uart1,
+        &omap44xx_l4_per__uart2,
+        &omap44xx_l4_per__uart3,
+        &omap44xx_l4_per__uart4,
+        &omap44xx_l4_cfg__usb_host_fs,
+        &omap44xx_l4_cfg__usb_host_hs,
+        &omap44xx_l4_cfg__usb_otg_hs,
+        &omap44xx_l4_cfg__usb_tll_hs,
+        &omap44xx_l4_wkup__wd_timer2,
+        &omap44xx_l4_abe__wd_timer3,
+        &omap44xx_l4_abe__wd_timer3_dma,
        NULL,
 };
 int __init omap44xx_hwmod_init(void)
 {
-        return omap_hwmod_register(omap44xx_hwmods);
+        return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);
 }
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h
index ad5d8f04c0b8..e7e8eeae95e5 100644
--- a/arch/arm/mach-omap2/omap_hwmod_common_data.h
+++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h
@@ -19,18 +19,6 @@
 #include "display.h"
 /* Common address space across OMAP2xxx */
-extern struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[];
-extern struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[];
-extern struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[];
-extern struct omap_hwmod_addr_space omap2xxx_timer2_addrs[];
-extern struct omap_hwmod_addr_space omap2xxx_timer3_addrs[];
-extern struct omap_hwmod_addr_space omap2xxx_timer4_addrs[];
-extern struct omap_hwmod_addr_space omap2xxx_timer5_addrs[];
-extern struct omap_hwmod_addr_space omap2xxx_timer6_addrs[];
-extern struct omap_hwmod_addr_space omap2xxx_timer7_addrs[];
-extern struct omap_hwmod_addr_space omap2xxx_timer8_addrs[];
-extern struct omap_hwmod_addr_space omap2xxx_timer9_addrs[];
-extern struct omap_hwmod_addr_space omap2xxx_timer12_addrs[];
 extern struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[];
 /* Common address space across OMAP2xxx/3xxx */
@@ -50,10 +38,70 @@ extern struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[];
 extern struct omap_hwmod_addr_space omap2_dma_system_addrs[];
 extern struct omap_hwmod_addr_space omap2_mailbox_addrs[];
 extern struct omap_hwmod_addr_space omap2_mcbsp1_addrs[];
+extern struct omap_hwmod_addr_space omap2_hdq1w_addr_space[];
 /* Common IP block data across OMAP2xxx */
 extern struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[];
 extern struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[];
+extern struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr;
+extern struct omap_hwmod omap2xxx_l3_main_hwmod;
+extern struct omap_hwmod omap2xxx_l4_core_hwmod;
+extern struct omap_hwmod omap2xxx_l4_wkup_hwmod;
+extern struct omap_hwmod omap2xxx_mpu_hwmod;
+extern struct omap_hwmod omap2xxx_iva_hwmod;
+extern struct omap_hwmod omap2xxx_timer1_hwmod;
+extern struct omap_hwmod omap2xxx_timer2_hwmod;
+extern struct omap_hwmod omap2xxx_timer3_hwmod;
+extern struct omap_hwmod omap2xxx_timer4_hwmod;
+extern struct omap_hwmod omap2xxx_timer5_hwmod;
+extern struct omap_hwmod omap2xxx_timer6_hwmod;
+extern struct omap_hwmod omap2xxx_timer7_hwmod;
+extern struct omap_hwmod omap2xxx_timer8_hwmod;
+extern struct omap_hwmod omap2xxx_timer9_hwmod;
+extern struct omap_hwmod omap2xxx_timer10_hwmod;
+extern struct omap_hwmod omap2xxx_timer11_hwmod;
+extern struct omap_hwmod omap2xxx_timer12_hwmod;
+extern struct omap_hwmod omap2xxx_wd_timer2_hwmod;
+extern struct omap_hwmod omap2xxx_uart1_hwmod;
+extern struct omap_hwmod omap2xxx_uart2_hwmod;
+extern struct omap_hwmod omap2xxx_uart3_hwmod;
+extern struct omap_hwmod omap2xxx_dss_core_hwmod;
+extern struct omap_hwmod omap2xxx_dss_dispc_hwmod;
+extern struct omap_hwmod omap2xxx_dss_rfbi_hwmod;
+extern struct omap_hwmod omap2xxx_dss_venc_hwmod;
+extern struct omap_hwmod omap2xxx_gpio1_hwmod;
+extern struct omap_hwmod omap2xxx_gpio2_hwmod;
+extern struct omap_hwmod omap2xxx_gpio3_hwmod;
+extern struct omap_hwmod omap2xxx_gpio4_hwmod;
+extern struct omap_hwmod omap2xxx_mcspi1_hwmod;
+extern struct omap_hwmod omap2xxx_mcspi2_hwmod;
+extern struct omap_hwmod omap2xxx_counter_32k_hwmod;
+/* Common interface data across OMAP2xxx */
+extern struct omap_hwmod_ocp_if omap2xxx_l3_main__l4_core;
+extern struct omap_hwmod_ocp_if omap2xxx_mpu__l3_main;
+extern struct omap_hwmod_ocp_if omap2xxx_dss__l3;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__l4_wkup;
+extern struct omap_hwmod_ocp_if omap2_l4_core__uart1;
+extern struct omap_hwmod_ocp_if omap2_l4_core__uart2;
+extern struct omap_hwmod_ocp_if omap2_l4_core__uart3;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi1;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi2;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer2;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer3;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer4;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer5;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer6;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer7;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer8;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer9;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer10;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer11;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__timer12;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_dispc;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc;
 /* Common IP block data */
 extern struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[];
@@ -94,6 +142,8 @@ extern struct omap_hwmod_irq_info omap2_gpio4_irqs[];
 extern struct omap_hwmod_irq_info omap2_dma_system_irqs[];
 extern struct omap_hwmod_irq_info omap2_mcspi1_mpu_irqs[];
 extern struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[];
+extern struct omap_hwmod_addr_space omap2xxx_timer12_addrs[];
+extern struct omap_hwmod_irq_info omap2_hdq1w_mpu_irqs[];
 /* OMAP hwmod classes - forward declarations */
 extern struct omap_hwmod_class l3_hwmod_class;
@@ -105,6 +155,8 @@ extern struct omap_hwmod_class omap2_dss_hwmod_class;
 extern struct omap_hwmod_class omap2_dispc_hwmod_class;
 extern struct omap_hwmod_class omap2_rfbi_hwmod_class;
 extern struct omap_hwmod_class omap2_venc_hwmod_class;
+extern struct omap_hwmod_class_sysconfig omap2_hdq1w_sysc;
+extern struct omap_hwmod_class omap2_hdq1w_class;
 extern struct omap_hwmod_class omap2xxx_timer_hwmod_class;
 extern struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class;
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 36fa90b6ece8..78564895e914 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -38,27 +38,6 @@ static inline int omap4_opp_init(void)
 }
 #endif
-/*
- * cpuidle mach specific parameters
- *
- * The board code can override the default C-states definition using
- * omap3_pm_init_cpuidle
- */
-struct cpuidle_params {
-        u32 exit_latency;       /* exit_latency = sleep + wake-up latencies */
-        u32 target_residency;
-        u8 valid;               /* validates the C-state */
-};
-#if defined(CONFIG_PM) && defined(CONFIG_CPU_IDLE)
-extern void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params);
-#else
-static
-inline void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params)
-{
-}
-#endif
 extern int omap3_pm_get_suspend_state(struct powerdomain *pwrdm);
 extern int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state);
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index 95442b69ae27..facfffca9eac 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -171,8 +171,6 @@ static int omap2_allow_mpu_retention(void)
 static void omap2_enter_mpu_retention(void)
 {
-        int only_idle = 0;
        /* Putting MPU into the WFI state while a transfer is active
         * seems to cause the I2C block to timeout. Why? Good question. */
        if (omap2_i2c_active())
@@ -195,7 +193,6 @@ static void omap2_enter_mpu_retention(void)
                omap2_prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK, MPU_MOD,
                                                 OMAP2_PM_PWSTCTRL);
-                only_idle = 1;
        }
        omap2_sram_idle();
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 703bd1099259..8b43aefba0ea 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -273,7 +273,7 @@ void omap_sram_idle(void)
        int per_next_state = PWRDM_POWER_ON;
        int core_next_state = PWRDM_POWER_ON;
        int per_going_off;
-        int core_prev_state, per_prev_state;
+        int core_prev_state;
        u32 sdrc_pwr = 0;
        mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
@@ -375,10 +375,8 @@ void omap_sram_idle(void)
        pwrdm_post_transition();
        /* PER */
-        if (per_next_state < PWRDM_POWER_ON) {
+        if (per_next_state < PWRDM_POWER_ON)
-                per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm);
                omap2_gpio_resume_after_idle();
-        }
        /* Disable IO-PAD and IO-CHAIN wakeup */
        if (omap3_has_io_wakeup() &&
@@ -702,7 +700,7 @@ static void __init pm_errata_configure(void)
 static int __init omap3_pm_init(void)
 {
        struct power_state *pwrst, *tmp;
-        struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm;
+        struct clockdomain *neon_clkdm, *mpu_clkdm;
        int ret;
        if (!cpu_is_omap34xx())
@@ -757,8 +755,6 @@ static int __init omap3_pm_init(void)
        neon_clkdm = clkdm_lookup("neon_clkdm");
        mpu_clkdm = clkdm_lookup("mpu_clkdm");
-        per_clkdm = clkdm_lookup("per_clkdm");
-        core_clkdm = clkdm_lookup("core_clkdm");
 #ifdef CONFIG_SUSPEND
        omap_pm_suspend = omap3_pm_suspend;
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 96ad3dbeac34..96114901b932 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -981,16 +981,6 @@ int pwrdm_state_switch(struct powerdomain *pwrdm)
        return ret;
 }
-int pwrdm_clkdm_state_switch(struct clockdomain *clkdm)
-{
-        if (clkdm != NULL && clkdm->pwrdm.ptr != NULL) {
-                pwrdm_wait_transition(clkdm->pwrdm.ptr);
-                return pwrdm_state_switch(clkdm->pwrdm.ptr);
-        }
-        return -EINVAL;
-}
 int pwrdm_pre_transition(void)
 {
        pwrdm_for_each(_pwrdm_pre_transition_cb, NULL);
diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
index 0d72a8a8ce4d..8f88d65c46ea 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -213,7 +213,6 @@ bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm);
 int pwrdm_wait_transition(struct powerdomain *pwrdm);
 int pwrdm_state_switch(struct powerdomain *pwrdm);
-int pwrdm_clkdm_state_switch(struct clockdomain *clkdm);
 int pwrdm_pre_transition(void);
 int pwrdm_post_transition(void);
 int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm);
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index 5aa5435e3ff1..6da3ba483ad1 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -177,6 +177,8 @@
 /* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */
 #define OMAP24XX_ST_GPIOS_SHIFT                         2
 #define OMAP24XX_ST_GPIOS_MASK                          (1 << 2)
+#define OMAP24XX_ST_32KSYNC_SHIFT                       1
+#define OMAP24XX_ST_32KSYNC_MASK                        (1 << 1)
 #define OMAP24XX_ST_GPT1_SHIFT                          0
 #define OMAP24XX_ST_GPT1_MASK                           (1 << 0)
@@ -307,6 +309,8 @@
 #define OMAP3430_ST_SR1_MASK                            (1 << 6)
 #define OMAP3430_ST_GPIO1_SHIFT                         3
 #define OMAP3430_ST_GPIO1_MASK                          (1 << 3)
+#define OMAP3430_ST_32KSYNC_SHIFT                       2
+#define OMAP3430_ST_32KSYNC_MASK                        (1 << 2)
 #define OMAP3430_ST_GPT12_SHIFT                         1
 #define OMAP3430_ST_GPT12_MASK                          (1 << 1)
 #define OMAP3430_ST_GPT1_SHIFT                          0
@@ -410,6 +414,19 @@
 extern void __iomem *prm_base;
 extern void __iomem *cm_base;
 extern void __iomem *cm2_base;
+extern void __iomem *prcm_mpu_base;
+#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_ARCH_OMAP5)
+extern void omap_prm_base_init(void);
+extern void omap_cm_base_init(void);
+#else
+static inline void omap_prm_base_init(void)
+{
+}
+static inline void omap_cm_base_init(void)
+{
+}
+#endif
 /**
 * struct omap_prcm_irq - describes a PRCM interrupt bit
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index 626acfad7190..480f40a5ee42 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -42,6 +42,7 @@
 void __iomem *prm_base;
 void __iomem *cm_base;
 void __iomem *cm2_base;
+void __iomem *prcm_mpu_base;
 #define MAX_MODULE_ENABLE_WAIT          100000
@@ -155,4 +156,11 @@ void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
                cm_base = omap2_globals->cm;
        if (omap2_globals->cm2)
                cm2_base = omap2_globals->cm2;
+        if (omap2_globals->prcm_mpu)
+                prcm_mpu_base = omap2_globals->prcm_mpu;
+        if (cpu_is_omap44xx()) {
+                omap_prm_base_init();
+                omap_cm_base_init();
+        }
 }
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index d28f848897d6..dfe00ddb5c60 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -237,7 +237,7 @@ void omap_prcm_irq_complete(void)
 */
 int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup)
 {
-        int nr_regs = irq_setup->nr_regs;
+        int nr_regs;
        u32 mask[OMAP_PRCM_MAX_NR_PENDING_REG];
        int offset, i;
        struct irq_chip_generic *gc;
@@ -246,6 +246,8 @@ int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup)
        if (!irq_setup)
                return -EINVAL;
+        nr_regs = irq_setup->nr_regs;
        if (prcm_irq_setup) {
                pr_err("PRCM: already initialized; won't reinitialize\n");
                return -EINVAL;
diff --git a/arch/arm/mach-omap2/prminst44xx.c b/arch/arm/mach-omap2/prminst44xx.c
index 9b3898a3ac9b..c12320c0ae95 100644
--- a/arch/arm/mach-omap2/prminst44xx.c
+++ b/arch/arm/mach-omap2/prminst44xx.c
@@ -18,20 +18,26 @@
 #include "iomap.h"
 #include "common.h"
+#include "prcm-common.h"
 #include "prm44xx.h"
 #include "prminst44xx.h"
 #include "prm-regbits-44xx.h"
 #include "prcm44xx.h"
 #include "prcm_mpu44xx.h"
-static u32 _prm_bases[OMAP4_MAX_PRCM_PARTITIONS] = {
+static void __iomem *_prm_bases[OMAP4_MAX_PRCM_PARTITIONS];
-        [OMAP4430_INVALID_PRCM_PARTITION]       = 0,
-        [OMAP4430_PRM_PARTITION]                = OMAP4430_PRM_BASE,
+/**
-        [OMAP4430_CM1_PARTITION]                = 0,
+ * omap_prm_base_init - Populates the prm partitions
-        [OMAP4430_CM2_PARTITION]                = 0,
+ *
-        [OMAP4430_SCRM_PARTITION]               = 0,
+ * Populates the base addresses of the _prm_bases
-        [OMAP4430_PRCM_MPU_PARTITION]           = OMAP4430_PRCM_MPU_BASE,
+ * array used for read/write of prm module registers.
-};
+ */
+void omap_prm_base_init(void)
+{
+        _prm_bases[OMAP4430_PRM_PARTITION] = prm_base;
+        _prm_bases[OMAP4430_PRCM_MPU_PARTITION] = prcm_mpu_base;
+}
 /* Read a register in a PRM instance */
 u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx)
@@ -39,8 +45,7 @@ u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx)
        BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
               part == OMAP4430_INVALID_PRCM_PARTITION ||
               !_prm_bases[part]);
-        return __raw_readl(OMAP2_L4_IO_ADDRESS(_prm_bases[part] + inst +
+        return __raw_readl(_prm_bases[part] + inst + idx);
-                                               idx));
 }
 /* Write into a register in a PRM instance */
@@ -49,7 +54,7 @@ void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx)
        BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
               part == OMAP4430_INVALID_PRCM_PARTITION ||
               !_prm_bases[part]);
-        __raw_writel(val, OMAP2_L4_IO_ADDRESS(_prm_bases[part] + inst + idx));
+        __raw_writel(val, _prm_bases[part] + inst + idx);
 }
 /* Read-modify-write a register in PRM. Caller must lock */
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 0cdd359a128e..292d4aaca068 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -108,8 +108,14 @@ static void omap_uart_set_noidle(struct platform_device *pdev)
 static void omap_uart_set_smartidle(struct platform_device *pdev)
 {
        struct omap_device *od = to_omap_device(pdev);
+        u8 idlemode;
-        omap_hwmod_set_slave_idlemode(od->hwmods[0], HWMOD_IDLEMODE_SMART);
+        if (od->hwmods[0]->class->sysc->idlemodes & SIDLE_SMART_WKUP)
+                idlemode = HWMOD_IDLEMODE_SMART_WKUP;
+        else
+                idlemode = HWMOD_IDLEMODE_SMART;
+        omap_hwmod_set_slave_idlemode(od->hwmods[0], idlemode);
 }
 #else
@@ -120,130 +126,14 @@ static void omap_uart_set_smartidle(struct platform_device *pdev) {}
 #endif /* CONFIG_PM */
 #ifdef CONFIG_OMAP_MUX
-static struct omap_device_pad default_uart1_pads[] __initdata = {
-        {
-                .name   = "uart1_cts.uart1_cts",
-                .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
-        },
-        {
-                .name   = "uart1_rts.uart1_rts",
-                .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
-        },
-        {
-                .name   = "uart1_tx.uart1_tx",
-                .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
-        },
-        {
-                .name   = "uart1_rx.uart1_rx",
-                .flags  = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
-                .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
-                .idle   = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
-        },
-};
-static struct omap_device_pad default_uart2_pads[] __initdata = {
-        {
-                .name   = "uart2_cts.uart2_cts",
-                .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
-        },
-        {
-                .name   = "uart2_rts.uart2_rts",
-                .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
-        },
-        {
-                .name   = "uart2_tx.uart2_tx",
-                .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
-        },
-        {
-                .name   = "uart2_rx.uart2_rx",
-                .flags  = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
-                .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
-                .idle   = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
-        },
-};
-static struct omap_device_pad default_uart3_pads[] __initdata = {
-        {
-                .name   = "uart3_cts_rctx.uart3_cts_rctx",
-                .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
-        },
-        {
-                .name   = "uart3_rts_sd.uart3_rts_sd",
-                .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
-        },
-        {
-                .name   = "uart3_tx_irtx.uart3_tx_irtx",
-                .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
-        },
-        {
-                .name   = "uart3_rx_irrx.uart3_rx_irrx",
-                .flags  = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
-                .enable = OMAP_PIN_INPUT | OMAP_MUX_MODE0,
-                .idle   = OMAP_PIN_INPUT | OMAP_MUX_MODE0,
-        },
-};
-static struct omap_device_pad default_omap36xx_uart4_pads[] __initdata = {
-        {
-                .name   = "gpmc_wait2.uart4_tx",
-                .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
-        },
-        {
-                .name   = "gpmc_wait3.uart4_rx",
-                .flags  = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
-                .enable = OMAP_PIN_INPUT | OMAP_MUX_MODE2,
-                .idle   = OMAP_PIN_INPUT | OMAP_MUX_MODE2,
-        },
-};
-static struct omap_device_pad default_omap4_uart4_pads[] __initdata = {
-        {
-                .name   = "uart4_tx.uart4_tx",
-                .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
-        },
-        {
-                .name   = "uart4_rx.uart4_rx",
-                .flags  = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
-                .enable = OMAP_PIN_INPUT | OMAP_MUX_MODE0,
-                .idle   = OMAP_PIN_INPUT | OMAP_MUX_MODE0,
-        },
-};
 static void omap_serial_fill_default_pads(struct omap_board_data *bdata)
 {
-        switch (bdata->id) {
-        case 0:
-                bdata->pads = default_uart1_pads;
-                bdata->pads_cnt = ARRAY_SIZE(default_uart1_pads);
-                break;
-        case 1:
-                bdata->pads = default_uart2_pads;
-                bdata->pads_cnt = ARRAY_SIZE(default_uart2_pads);
-                break;
-        case 2:
-                bdata->pads = default_uart3_pads;
-                bdata->pads_cnt = ARRAY_SIZE(default_uart3_pads);
-                break;
-        case 3:
-                if (cpu_is_omap44xx()) {
-                        bdata->pads = default_omap4_uart4_pads;
-                        bdata->pads_cnt =
-                                ARRAY_SIZE(default_omap4_uart4_pads);
-                } else if (cpu_is_omap3630()) {
-                        bdata->pads = default_omap36xx_uart4_pads;
-                        bdata->pads_cnt =
-                                ARRAY_SIZE(default_omap36xx_uart4_pads);
-                }
-                break;
-        default:
-                break;
-        }
 }
 #else
 static void omap_serial_fill_default_pads(struct omap_board_data *bdata) {}
 #endif
-char *cmdline_find_option(char *str)
+static char *cmdline_find_option(char *str)
 {
        extern char *saved_command_line;
@@ -355,14 +245,6 @@ void __init omap_serial_init_port(struct omap_board_data *bdata,
        omap_up.dma_rx_poll_rate = info->dma_rx_poll_rate;
        omap_up.autosuspend_timeout = info->autosuspend_timeout;
-        /* Enable the MDR1 Errata i202 for OMAP2430/3xxx/44xx */
-        if (!cpu_is_omap2420() && !cpu_is_ti816x())
-                omap_up.errata |= UART_ERRATA_i202_MDR1_ACCESS;
-        /* Enable DMA Mode Force Idle Errata i291 for omap34xx/3630 */
-        if (cpu_is_omap34xx() || cpu_is_omap3630())
-                omap_up.errata |= UART_ERRATA_i291_DMA_FORCEIDLE;
        pdata = &omap_up;
        pdata_size = sizeof(struct omap_uart_port_info);
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index c512bac69ec5..1b7835865c83 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -145,8 +145,10 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
 {
        char name[10]; /* 10 = sizeof("gptXX_Xck0") */
        struct omap_hwmod *oh;
+        struct resource irq_rsrc, mem_rsrc;
        size_t size;
        int res = 0;
+        int r;
        sprintf(name, "timer%d", gptimer_id);
        omap_hwmod_setup_one(name);
@@ -154,9 +156,16 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
        if (!oh)
                return -ENODEV;
-        timer->irq = oh->mpu_irqs[0].irq;
+        r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL, &irq_rsrc);
-        timer->phys_base = oh->slaves[0]->addr->pa_start;
+        if (r)
-        size = oh->slaves[0]->addr->pa_end - timer->phys_base;
+                return -ENXIO;
+        timer->irq = irq_rsrc.start;
+        r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL, &mem_rsrc);
+        if (r)
+                return -ENXIO;
+        timer->phys_base = mem_rsrc.start;
+        size = mem_rsrc.end - mem_rsrc.start;
        /* Static mapping, never released */
        timer->io_base = ioremap(timer->phys_base, size);
@@ -169,13 +178,6 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
        if (IS_ERR(timer->fclk))
                return -ENODEV;
-        sprintf(name, "gpt%d_ick", gptimer_id);
-        timer->iclk = clk_get(NULL, name);
-        if (IS_ERR(timer->iclk)) {
-                clk_put(timer->fclk);
-                return -ENODEV;
-        }
        omap_hwmod_enable(oh);
        sys_timer_reserved |= (1 << (gptimer_id - 1));
diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c
index 4b57757bf9d1..119d5a910f3a 100644
--- a/arch/arm/mach-omap2/twl-common.c
+++ b/arch/arm/mach-omap2/twl-common.c
@@ -31,12 +31,35 @@
 #include "twl-common.h"
 #include "pm.h"
+#include "voltage.h"
 static struct i2c_board_info __initdata pmic_i2c_board_info = {
        .addr           = 0x48,
        .flags          = I2C_CLIENT_WAKE,
 };
+static struct i2c_board_info __initdata omap4_i2c1_board_info[] = {
+        {
+                .addr           = 0x48,
+                .flags          = I2C_CLIENT_WAKE,
+        },
+        {
+                I2C_BOARD_INFO("twl6040", 0x4b),
+        },
+};
+static int twl_set_voltage(void *data, int target_uV)
+{
+        struct voltagedomain *voltdm = (struct voltagedomain *)data;
+        return voltdm_scale(voltdm, target_uV);
+}
+static int twl_get_voltage(void *data)
+{
+        struct voltagedomain *voltdm = (struct voltagedomain *)data;
+        return voltdm_get_voltage(voltdm);
+}
 void __init omap_pmic_init(int bus, u32 clkrate,
                           const char *pmic_type, int pmic_irq,
                           struct twl4030_platform_data *pmic_data)
@@ -49,14 +72,31 @@ void __init omap_pmic_init(int bus, u32 clkrate,
        omap_register_i2c_bus(bus, clkrate, &pmic_i2c_board_info, 1);
 }
+void __init omap4_pmic_init(const char *pmic_type,
+                    struct twl4030_platform_data *pmic_data,
+                    struct twl6040_platform_data *twl6040_data, int twl6040_irq)
+{
+        /* PMIC part*/
+        strncpy(omap4_i2c1_board_info[0].type, pmic_type,
+                sizeof(omap4_i2c1_board_info[0].type));
+        omap4_i2c1_board_info[0].irq = OMAP44XX_IRQ_SYS_1N;
+        omap4_i2c1_board_info[0].platform_data = pmic_data;
+        /* TWL6040 audio IC part */
+        omap4_i2c1_board_info[1].irq = twl6040_irq;
+        omap4_i2c1_board_info[1].platform_data = twl6040_data;
+        omap_register_i2c_bus(1, 400, omap4_i2c1_board_info, 2);
+}
 void __init omap_pmic_late_init(void)
 {
        /* Init the OMAP TWL parameters (if PMIC has been registerd) */
-        if (!pmic_i2c_board_info.irq)
+        if (pmic_i2c_board_info.irq)
-                return;
+                omap3_twl_init();
+        if (omap4_i2c1_board_info[0].irq)
-        omap3_twl_init();
+                omap4_twl_init();
-        omap4_twl_init();
 }
 #if defined(CONFIG_ARCH_OMAP3)
@@ -126,6 +166,48 @@ static struct regulator_init_data omap3_vpll2_idata = {
        .consumer_supplies              = omap3_vpll2_supplies,
 };
+static struct regulator_consumer_supply omap3_vdd1_supply[] = {
+        REGULATOR_SUPPLY("vcc", "mpu.0"),
+};
+static struct regulator_consumer_supply omap3_vdd2_supply[] = {
+        REGULATOR_SUPPLY("vcc", "l3_main.0"),
+};
+static struct regulator_init_data omap3_vdd1 = {
+        .constraints = {
+                .name                   = "vdd_mpu_iva",
+                .min_uV                 = 600000,
+                .max_uV                 = 1450000,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL,
+                .valid_ops_mask         = REGULATOR_CHANGE_VOLTAGE,
+        },
+        .num_consumer_supplies          = ARRAY_SIZE(omap3_vdd1_supply),
+        .consumer_supplies              = omap3_vdd1_supply,
+};
+static struct regulator_init_data omap3_vdd2 = {
+        .constraints = {
+                .name                   = "vdd_core",
+                .min_uV                 = 600000,
+                .max_uV                 = 1450000,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL,
+                .valid_ops_mask         = REGULATOR_CHANGE_VOLTAGE,
+        },
+        .num_consumer_supplies          = ARRAY_SIZE(omap3_vdd2_supply),
+        .consumer_supplies              = omap3_vdd2_supply,
+};
+static struct twl_regulator_driver_data omap3_vdd1_drvdata = {
+        .get_voltage = twl_get_voltage,
+        .set_voltage = twl_set_voltage,
+};
+static struct twl_regulator_driver_data omap3_vdd2_drvdata = {
+        .get_voltage = twl_get_voltage,
+        .set_voltage = twl_set_voltage,
+};
 void __init omap3_pmic_get_config(struct twl4030_platform_data *pmic_data,
                                  u32 pdata_flags, u32 regulators_flags)
 {
@@ -133,6 +215,16 @@ void __init omap3_pmic_get_config(struct twl4030_platform_data *pmic_data,
                pmic_data->irq_base = TWL4030_IRQ_BASE;
        if (!pmic_data->irq_end)
                pmic_data->irq_end = TWL4030_IRQ_END;
+        if (!pmic_data->vdd1) {
+                omap3_vdd1.driver_data = &omap3_vdd1_drvdata;
+                omap3_vdd1_drvdata.data = voltdm_lookup("mpu_iva");
+                pmic_data->vdd1 = &omap3_vdd1;
+        }
+        if (!pmic_data->vdd2) {
+                omap3_vdd2.driver_data = &omap3_vdd2_drvdata;
+                omap3_vdd2_drvdata.data = voltdm_lookup("core");
+                pmic_data->vdd2 = &omap3_vdd2;
+        }
        /* Common platform data configurations */
        if (pdata_flags & TWL_COMMON_PDATA_USB && !pmic_data->usb)
@@ -174,6 +266,7 @@ static struct regulator_init_data omap4_vdac_idata = {
                .valid_ops_mask         = REGULATOR_CHANGE_MODE
                                        | REGULATOR_CHANGE_STATUS,
        },
+        .supply_regulator       = "V2V1",
 };
 static struct regulator_init_data omap4_vaux2_idata = {
@@ -264,6 +357,7 @@ static struct regulator_init_data omap4_vcxio_idata = {
        },
        .num_consumer_supplies  = ARRAY_SIZE(omap4_vcxio_supply),
        .consumer_supplies      = omap4_vcxio_supply,
+        .supply_regulator       = "V2V1",
 };
 static struct regulator_init_data omap4_vusb_idata = {
@@ -283,6 +377,105 @@ static struct regulator_init_data omap4_clk32kg_idata = {
        },
 };
+static struct regulator_consumer_supply omap4_vdd1_supply[] = {
+        REGULATOR_SUPPLY("vcc", "mpu.0"),
+};
+static struct regulator_consumer_supply omap4_vdd2_supply[] = {
+        REGULATOR_SUPPLY("vcc", "iva.0"),
+};
+static struct regulator_consumer_supply omap4_vdd3_supply[] = {
+        REGULATOR_SUPPLY("vcc", "l3_main.0"),
+};
+static struct regulator_init_data omap4_vdd1 = {
+        .constraints = {
+                .name                   = "vdd_mpu",
+                .min_uV                 = 500000,
+                .max_uV                 = 1500000,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL,
+                .valid_ops_mask         = REGULATOR_CHANGE_VOLTAGE,
+        },
+        .num_consumer_supplies          = ARRAY_SIZE(omap4_vdd1_supply),
+        .consumer_supplies              = omap4_vdd1_supply,
+};
+static struct regulator_init_data omap4_vdd2 = {
+        .constraints = {
+                .name                   = "vdd_iva",
+                .min_uV                 = 500000,
+                .max_uV                 = 1500000,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL,
+                .valid_ops_mask         = REGULATOR_CHANGE_VOLTAGE,
+        },
+        .num_consumer_supplies          = ARRAY_SIZE(omap4_vdd2_supply),
+        .consumer_supplies              = omap4_vdd2_supply,
+};
+static struct regulator_init_data omap4_vdd3 = {
+        .constraints = {
+                .name                   = "vdd_core",
+                .min_uV                 = 500000,
+                .max_uV                 = 1500000,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL,
+                .valid_ops_mask         = REGULATOR_CHANGE_VOLTAGE,
+        },
+        .num_consumer_supplies          = ARRAY_SIZE(omap4_vdd3_supply),
+        .consumer_supplies              = omap4_vdd3_supply,
+};
+static struct twl_regulator_driver_data omap4_vdd1_drvdata = {
+        .get_voltage = twl_get_voltage,
+        .set_voltage = twl_set_voltage,
+};
+static struct twl_regulator_driver_data omap4_vdd2_drvdata = {
+        .get_voltage = twl_get_voltage,
+        .set_voltage = twl_set_voltage,
+};
+static struct twl_regulator_driver_data omap4_vdd3_drvdata = {
+        .get_voltage = twl_get_voltage,
+        .set_voltage = twl_set_voltage,
+};
+static struct regulator_consumer_supply omap4_v1v8_supply[] = {
+        REGULATOR_SUPPLY("vio", "1-004b"),
+};
+static struct regulator_init_data omap4_v1v8_idata = {
+        .constraints = {
+                .min_uV                 = 1800000,
+                .max_uV                 = 1800000,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+                .always_on              = true,
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(omap4_v1v8_supply),
+        .consumer_supplies      = omap4_v1v8_supply,
+};
+static struct regulator_consumer_supply omap4_v2v1_supply[] = {
+        REGULATOR_SUPPLY("v2v1", "1-004b"),
+};
+static struct regulator_init_data omap4_v2v1_idata = {
+        .constraints = {
+                .min_uV                 = 2100000,
+                .max_uV                 = 2100000,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(omap4_v2v1_supply),
+        .consumer_supplies      = omap4_v2v1_supply,
+};
 void __init omap4_pmic_get_config(struct twl4030_platform_data *pmic_data,
                                  u32 pdata_flags, u32 regulators_flags)
 {
@@ -291,6 +484,24 @@ void __init omap4_pmic_get_config(struct twl4030_platform_data *pmic_data,
        if (!pmic_data->irq_end)
                pmic_data->irq_end = TWL6030_IRQ_END;
+        if (!pmic_data->vdd1) {
+                omap4_vdd1.driver_data = &omap4_vdd1_drvdata;
+                omap4_vdd1_drvdata.data = voltdm_lookup("mpu");
+                pmic_data->vdd1 = &omap4_vdd1;
+        }
+        if (!pmic_data->vdd2) {
+                omap4_vdd2.driver_data = &omap4_vdd2_drvdata;
+                omap4_vdd2_drvdata.data = voltdm_lookup("iva");
+                pmic_data->vdd2 = &omap4_vdd2;
+        }
+        if (!pmic_data->vdd3) {
+                omap4_vdd3.driver_data = &omap4_vdd3_drvdata;
+                omap4_vdd3_drvdata.data = voltdm_lookup("core");
+                pmic_data->vdd3 = &omap4_vdd3;
+        }
        /* Common platform data configurations */
        if (pdata_flags & TWL_COMMON_PDATA_USB && !pmic_data->usb)
                pmic_data->usb = &omap4_usb_pdata;
@@ -323,5 +534,11 @@ void __init omap4_pmic_get_config(struct twl4030_platform_data *pmic_data,
        if (regulators_flags & TWL_COMMON_REGULATOR_CLK32KG &&
            !pmic_data->clk32kg)
                pmic_data->clk32kg = &omap4_clk32kg_idata;
+        if (regulators_flags & TWL_COMMON_REGULATOR_V1V8 && !pmic_data->v1v8)
+                pmic_data->v1v8 = &omap4_v1v8_idata;
+        if (regulators_flags & TWL_COMMON_REGULATOR_V2V1 && !pmic_data->v2v1)
+                pmic_data->v2v1 = &omap4_v2v1_idata;
 }
 #endif /* CONFIG_ARCH_OMAP4 */
diff --git a/arch/arm/mach-omap2/twl-common.h b/arch/arm/mach-omap2/twl-common.h
index 275dde8cb27a..8fe71cfd002c 100644
--- a/arch/arm/mach-omap2/twl-common.h
+++ b/arch/arm/mach-omap2/twl-common.h
@@ -22,6 +22,8 @@
 #define TWL_COMMON_REGULATOR_VCXIO      (1 << 8)
 #define TWL_COMMON_REGULATOR_VUSB       (1 << 9)
 #define TWL_COMMON_REGULATOR_CLK32KG    (1 << 10)
+#define TWL_COMMON_REGULATOR_V1V8       (1 << 11)
+#define TWL_COMMON_REGULATOR_V2V1       (1 << 12)
 /* TWL4030 LDO regulators */
 #define TWL_COMMON_REGULATOR_VPLL1      (1 << 4)
@@ -29,6 +31,7 @@
 struct twl4030_platform_data;
+struct twl6040_platform_data;
 void omap_pmic_init(int bus, u32 clkrate, const char *pmic_type, int pmic_irq,
                    struct twl4030_platform_data *pmic_data);
@@ -46,12 +49,9 @@ static inline void omap3_pmic_init(const char *pmic_type,
        omap_pmic_init(1, 2600, pmic_type, INT_34XX_SYS_NIRQ, pmic_data);
 }
-static inline void omap4_pmic_init(const char *pmic_type,
+void omap4_pmic_init(const char *pmic_type,
-                                   struct twl4030_platform_data *pmic_data)
+                    struct twl4030_platform_data *pmic_data,
-{
+                    struct twl6040_platform_data *audio_data, int twl6040_irq);
-        /* Phoenix Audio IC needs I2C1 to start with 400 KHz or less */
-        omap_pmic_init(1, 400, pmic_type, OMAP44XX_IRQ_SYS_1N, pmic_data);
-}
 void omap3_pmic_get_config(struct twl4030_platform_data *pmic_data,
                           u32 pdata_flags, u32 regulators_flags);
diff --git a/arch/arm/mach-omap2/usb-tusb6010.c b/arch/arm/mach-omap2/usb-tusb6010.c
index 994d8f591a1d..db84a46ce7fd 100644
--- a/arch/arm/mach-omap2/usb-tusb6010.c
+++ b/arch/arm/mach-omap2/usb-tusb6010.c
@@ -126,7 +126,7 @@ static int tusb_set_sync_mode(unsigned sysclk_ps, unsigned fclk_ps)
        tmp = (t.sync_clk + fclk_ps - 1) / fclk_ps;
        if (tmp > 4)
                return -ERANGE;
-        if (tmp <= 0)
+        if (tmp == 0)
                tmp = 1;
        t.page_burst_access = (fclk_ps * tmp) / 1000;
diff --git a/arch/arm/mach-omap2/vc3xxx_data.c b/arch/arm/mach-omap2/vc3xxx_data.c
index a5ec7f8f2ea8..5d8eaf31569c 100644
--- a/arch/arm/mach-omap2/vc3xxx_data.c
+++ b/arch/arm/mach-omap2/vc3xxx_data.c
@@ -46,6 +46,7 @@ static struct omap_vc_common omap3_vc_common = {
 };
 struct omap_vc_channel omap3_vc_mpu = {
+        .flags = OMAP_VC_CHANNEL_DEFAULT,
        .common = &omap3_vc_common,
        .smps_sa_reg     = OMAP3_PRM_VC_SMPS_SA_OFFSET,
        .smps_volra_reg  = OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET,
diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
index 8a36342e60d2..4dc60e83e00d 100644
--- a/arch/arm/mach-omap2/voltage.c
+++ b/arch/arm/mach-omap2/voltage.c
@@ -73,7 +73,8 @@ unsigned long voltdm_get_voltage(struct voltagedomain *voltdm)
 int voltdm_scale(struct voltagedomain *voltdm,
                 unsigned long target_volt)
 {
-        int ret;
+        int ret, i;
+        unsigned long volt = 0;
        if (!voltdm || IS_ERR(voltdm)) {
                pr_warning("%s: VDD specified does not exist!\n", __func__);
@@ -86,9 +87,23 @@ int voltdm_scale(struct voltagedomain *voltdm,
                return -ENODATA;
        }
-        ret = voltdm->scale(voltdm, target_volt);
+        /* Adjust voltage to the exact voltage from the OPP table */
+        for (i = 0; voltdm->volt_data[i].volt_nominal != 0; i++) {
+                if (voltdm->volt_data[i].volt_nominal >= target_volt) {
+                        volt = voltdm->volt_data[i].volt_nominal;
+                        break;
+                }
+        }
+        if (!volt) {
+                pr_warning("%s: not scaling. OPP voltage for %lu, not found.\n",
+                           __func__, target_volt);
+                return -EINVAL;
+        }
+        ret = voltdm->scale(voltdm, volt);
        if (!ret)
-                voltdm->nominal_volt = target_volt;
+                voltdm->nominal_volt = volt;
        return ret;
 }
diff --git a/arch/arm/mach-omap2/wd_timer.c b/arch/arm/mach-omap2/wd_timer.c
index 4067669d96c4..b2f1c67043a2 100644
--- a/arch/arm/mach-omap2/wd_timer.c
+++ b/arch/arm/mach-omap2/wd_timer.c
@@ -14,6 +14,7 @@
 #include <plat/omap_hwmod.h>
 #include "wd_timer.h"
+#include "common.h"
 /*
 * In order to avoid any assumptions from bootloader regarding WDT
@@ -25,6 +26,8 @@
 #define OMAP_WDT_WPS            0x34
 #define OMAP_WDT_SPR            0x48
+/* Maximum microseconds to wait for OMAP module to softreset */
+#define MAX_MODULE_SOFTRESET_WAIT       10000
 int omap2_wd_timer_disable(struct omap_hwmod *oh)
 {
@@ -54,3 +57,45 @@ int omap2_wd_timer_disable(struct omap_hwmod *oh)
        return 0;
 }
+/**
+ * omap2_wdtimer_reset - reset and disable the WDTIMER IP block
+ * @oh: struct omap_hwmod *
+ *
+ * After the WDTIMER IP blocks are reset on OMAP2/3, we must also take
+ * care to execute the special watchdog disable sequence.  This is
+ * because the watchdog is re-armed upon OCP softreset.  (On OMAP4,
+ * this behavior was apparently changed and the watchdog is no longer
+ * re-armed after an OCP soft-reset.)  Returns -ETIMEDOUT if the reset
+ * did not complete, or 0 upon success.
+ *
+ * XXX Most of this code should be moved to the omap_hwmod.c layer
+ * during a normal merge window.  omap_hwmod_softreset() should be
+ * renamed to omap_hwmod_set_ocp_softreset(), and omap_hwmod_softreset()
+ * should call the hwmod _ocp_softreset() code.
+ */
+int omap2_wd_timer_reset(struct omap_hwmod *oh)
+{
+        int c = 0;
+        /* Write to the SOFTRESET bit */
+        omap_hwmod_softreset(oh);
+        /* Poll on RESETDONE bit */
+        omap_test_timeout((omap_hwmod_read(oh,
+                                           oh->class->sysc->syss_offs)
+                           & SYSS_RESETDONE_MASK),
+                          MAX_MODULE_SOFTRESET_WAIT, c);
+        if (oh->class->sysc->srst_udelay)
+                udelay(oh->class->sysc->srst_udelay);
+        if (c == MAX_MODULE_SOFTRESET_WAIT)
+                pr_warning("%s: %s: softreset failed (waited %d usec)\n",
+                           __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT);
+        else
+                pr_debug("%s: %s: softreset in %d usec\n", __func__,
+                         oh->name, c);
+        return (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT :
+                omap2_wd_timer_disable(oh);
+}
diff --git a/arch/arm/mach-omap2/wd_timer.h b/arch/arm/mach-omap2/wd_timer.h
index e0054a2d5505..f6bbba73b535 100644
--- a/arch/arm/mach-omap2/wd_timer.h
+++ b/arch/arm/mach-omap2/wd_timer.h
@@ -13,5 +13,6 @@
 #include <plat/omap_hwmod.h>
 extern int omap2_wd_timer_disable(struct omap_hwmod *oh);
+extern int omap2_wd_timer_reset(struct omap_hwmod *oh);
 #endif
diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig
index 6604fc6ca58a..0673f0c10432 100644
--- a/arch/arm/mach-orion5x/Kconfig
+++ b/arch/arm/mach-orion5x/Kconfig
@@ -86,7 +86,6 @@ config MACH_WRT350N_V2
 config MACH_TS78XX
        bool "Technologic Systems TS-78xx"
-        select PM
        help
          Say 'Y' here if you want your kernel to support the
          Technologic Systems TS-78xx platform.
diff --git a/arch/arm/mach-orion5x/addr-map.c b/arch/arm/mach-orion5x/addr-map.c
index 3638e5c12b7e..eaac83d1df6f 100644
--- a/arch/arm/mach-orion5x/addr-map.c
+++ b/arch/arm/mach-orion5x/addr-map.c
@@ -76,7 +76,7 @@ static int __init cpu_win_can_remap(const struct orion_addr_map_cfg *cfg,
 /*
 * Description of the windows needed by the platform code
 */
-static struct __initdata orion_addr_map_cfg addr_map_cfg = {
+static struct orion_addr_map_cfg addr_map_cfg __initdata = {
        .num_wins = 8,
        .cpu_win_can_remap = cpu_win_can_remap,
        .bridge_virt_base = ORION5X_BRIDGE_VIRT_BASE,
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index 24481666d2cd..e2e9db492d0c 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -205,7 +205,7 @@ int __init orion5x_find_tclk(void)
        return 166666667;
 }
-static void orion5x_timer_init(void)
+static void __init orion5x_timer_init(void)
 {
        orion5x_tclk = orion5x_find_tclk();
diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h
index 2e6454c8d4ba..31bab92ce038 100644
--- a/arch/arm/mach-orion5x/common.h
+++ b/arch/arm/mach-orion5x/common.h
@@ -45,6 +45,7 @@ void orion5x_restart(char, const char *);
 */
 struct pci_bus;
 struct pci_sys_data;
+struct pci_dev;
 void orion5x_pcie_id(u32 *dev, u32 *rev);
 void orion5x_pci_disable(void);
diff --git a/arch/arm/mach-orion5x/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c
index e52108c9aaea..49a3fd630313 100644
--- a/arch/arm/mach-orion5x/db88f5281-setup.c
+++ b/arch/arm/mach-orion5x/db88f5281-setup.c
@@ -265,7 +265,6 @@ static int __init db88f5281_pci_map_irq(const struct pci_dev *dev, u8 slot,
 static struct hw_pci db88f5281_pci __initdata = {
        .nr_controllers = 2,
        .preinit        = db88f5281_pci_preinit,
-        .swizzle        = pci_std_swizzle,
        .setup          = orion5x_pci_sys_setup,
        .scan           = orion5x_pci_sys_scan_bus,
        .map_irq        = db88f5281_pci_map_irq,
diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c
index c3ed15b8ea25..d470864b4e42 100644
--- a/arch/arm/mach-orion5x/dns323-setup.c
+++ b/arch/arm/mach-orion5x/dns323-setup.c
@@ -86,7 +86,6 @@ static int __init dns323_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 static struct hw_pci dns323_pci __initdata = {
        .nr_controllers = 2,
-        .swizzle        = pci_std_swizzle,
        .setup          = orion5x_pci_sys_setup,
        .scan           = orion5x_pci_sys_scan_bus,
        .map_irq        = dns323_pci_map_irq,
@@ -253,27 +252,6 @@ error_fail:
 * GPIO LEDs (simple - doesn't use hardware blinking support)
 */
-#define ORION_BLINK_HALF_PERIOD 100 /* ms */
-static int dns323_gpio_blink_set(unsigned gpio, int state,
-        unsigned long *delay_on, unsigned long *delay_off)
-{
-        if (delay_on && delay_off && !*delay_on && !*delay_off)
-                *delay_on = *delay_off = ORION_BLINK_HALF_PERIOD;
-        switch(state) {
-        case GPIO_LED_NO_BLINK_LOW:
-        case GPIO_LED_NO_BLINK_HIGH:
-                orion_gpio_set_blink(gpio, 0);
-                gpio_set_value(gpio, state);
-                break;
-        case GPIO_LED_BLINK:
-                orion_gpio_set_blink(gpio, 1);
-        }
-        return 0;
-}
 static struct gpio_led dns323ab_leds[] = {
        {
                .name = "power:blue",
@@ -312,13 +290,13 @@ static struct gpio_led dns323c_leds[] = {
 static struct gpio_led_platform_data dns323ab_led_data = {
        .num_leds       = ARRAY_SIZE(dns323ab_leds),
        .leds           = dns323ab_leds,
-        .gpio_blink_set = dns323_gpio_blink_set,
+        .gpio_blink_set = orion_gpio_led_blink_set,
 };
 static struct gpio_led_platform_data dns323c_led_data = {
        .num_leds       = ARRAY_SIZE(dns323c_leds),
        .leds           = dns323c_leds,
-        .gpio_blink_set = dns323_gpio_blink_set,
+        .gpio_blink_set = orion_gpio_led_blink_set,
 };
 static struct platform_device dns323_gpio_leds = {
diff --git a/arch/arm/mach-orion5x/kurobox_pro-setup.c b/arch/arm/mach-orion5x/kurobox_pro-setup.c
index 47587b832842..1e458efafb9a 100644
--- a/arch/arm/mach-orion5x/kurobox_pro-setup.c
+++ b/arch/arm/mach-orion5x/kurobox_pro-setup.c
@@ -138,7 +138,6 @@ static int __init kurobox_pro_pci_map_irq(const struct pci_dev *dev, u8 slot,
 static struct hw_pci kurobox_pro_pci __initdata = {
        .nr_controllers = 2,
-        .swizzle        = pci_std_swizzle,
        .setup          = orion5x_pci_sys_setup,
        .scan           = orion5x_pci_sys_scan_bus,
        .map_irq        = kurobox_pro_pci_map_irq,
diff --git a/arch/arm/mach-orion5x/mpp.h b/arch/arm/mach-orion5x/mpp.h
index eac68978a2c2..db70e79a1198 100644
--- a/arch/arm/mach-orion5x/mpp.h
+++ b/arch/arm/mach-orion5x/mpp.h
@@ -65,8 +65,8 @@
 #define MPP8_GIGE               MPP(8,  0x1, 0, 0, 1,   1,   1)
 #define MPP9_UNUSED             MPP(9,  0x0, 0, 0, 1,   1,   1)
-#define MPP9_GPIO               MPP(9,  0x0, 0, 0, 1,   1,   1)
+#define MPP9_GPIO               MPP(9,  0x0, 1, 1, 1,   1,   1)
-#define MPP9_GIGE               MPP(9,  0x1, 1, 1, 1,   1,   1)
+#define MPP9_GIGE               MPP(9,  0x1, 0, 0, 1,   1,   1)
 #define MPP10_UNUSED            MPP(10, 0x0, 0, 0, 1,   1,   1)
 #define MPP10_GPIO              MPP(10, 0x0, 1, 1, 1,   1,   1)
diff --git a/arch/arm/mach-orion5x/mss2-setup.c b/arch/arm/mach-orion5x/mss2-setup.c
index 65faaa34de61..1c16d045333e 100644
--- a/arch/arm/mach-orion5x/mss2-setup.c
+++ b/arch/arm/mach-orion5x/mss2-setup.c
@@ -89,7 +89,6 @@ static int __init mss2_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 static struct hw_pci mss2_pci __initdata = {
        .nr_controllers = 2,
-        .swizzle        = pci_std_swizzle,
        .setup          = orion5x_pci_sys_setup,
        .scan           = orion5x_pci_sys_scan_bus,
        .map_irq        = mss2_pci_map_irq,
diff --git a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
index 292038fc59fd..78a6a11d8216 100644
--- a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
@@ -149,7 +149,6 @@ rd88f5181l_fxo_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 static struct hw_pci rd88f5181l_fxo_pci __initdata = {
        .nr_controllers = 2,
-        .swizzle        = pci_std_swizzle,
        .setup          = orion5x_pci_sys_setup,
        .scan           = orion5x_pci_sys_scan_bus,
        .map_irq        = rd88f5181l_fxo_pci_map_irq,
diff --git a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
index c44eabaabc16..2f5dc54cd4cd 100644
--- a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
@@ -161,7 +161,6 @@ rd88f5181l_ge_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 static struct hw_pci rd88f5181l_ge_pci __initdata = {
        .nr_controllers = 2,
-        .swizzle        = pci_std_swizzle,
        .setup          = orion5x_pci_sys_setup,
        .scan           = orion5x_pci_sys_scan_bus,
        .map_irq        = rd88f5181l_ge_pci_map_irq,
diff --git a/arch/arm/mach-orion5x/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c
index e3ce61711478..399130fac0b6 100644
--- a/arch/arm/mach-orion5x/rd88f5182-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5182-setup.c
@@ -200,7 +200,6 @@ static int __init rd88f5182_pci_map_irq(const struct pci_dev *dev, u8 slot,
 static struct hw_pci rd88f5182_pci __initdata = {
        .nr_controllers = 2,
        .preinit        = rd88f5182_pci_preinit,
-        .swizzle        = pci_std_swizzle,
        .setup          = orion5x_pci_sys_setup,
        .scan           = orion5x_pci_sys_scan_bus,
        .map_irq        = rd88f5182_pci_map_irq,
diff --git a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
index 2c5fab00d205..e91bf0ba4e8e 100644
--- a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
+++ b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
@@ -102,7 +102,6 @@ static void __init rd88f6183ap_ge_init(void)
 static struct hw_pci rd88f6183ap_ge_pci __initdata = {
        .nr_controllers = 2,
-        .swizzle        = pci_std_swizzle,
        .setup          = orion5x_pci_sys_setup,
        .scan           = orion5x_pci_sys_scan_bus,
        .map_irq        = orion5x_pci_map_irq,
diff --git a/arch/arm/mach-orion5x/terastation_pro2-setup.c b/arch/arm/mach-orion5x/terastation_pro2-setup.c
index 632a861ef82b..90e571dc4deb 100644
--- a/arch/arm/mach-orion5x/terastation_pro2-setup.c
+++ b/arch/arm/mach-orion5x/terastation_pro2-setup.c
@@ -122,7 +122,6 @@ static int __init tsp2_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 static struct hw_pci tsp2_pci __initdata = {
        .nr_controllers = 2,
        .preinit        = tsp2_pci_preinit,
-        .swizzle        = pci_std_swizzle,
        .setup          = orion5x_pci_sys_setup,
        .scan           = orion5x_pci_sys_scan_bus,
        .map_irq        = tsp2_pci_map_irq,
diff --git a/arch/arm/mach-orion5x/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c
index 5d6408745582..b184f680e0db 100644
--- a/arch/arm/mach-orion5x/ts209-setup.c
+++ b/arch/arm/mach-orion5x/ts209-setup.c
@@ -170,7 +170,6 @@ static int __init qnap_ts209_pci_map_irq(const struct pci_dev *dev, u8 slot,
 static struct hw_pci qnap_ts209_pci __initdata = {
        .nr_controllers = 2,
        .preinit        = qnap_ts209_pci_preinit,
-        .swizzle        = pci_std_swizzle,
        .setup          = orion5x_pci_sys_setup,
        .scan           = orion5x_pci_sys_scan_bus,
        .map_irq        = qnap_ts209_pci_map_irq,
diff --git a/arch/arm/mach-orion5x/ts409-setup.c b/arch/arm/mach-orion5x/ts409-setup.c
index 4e6ff759cd32..a5c2e64c4ece 100644
--- a/arch/arm/mach-orion5x/ts409-setup.c
+++ b/arch/arm/mach-orion5x/ts409-setup.c
@@ -140,7 +140,6 @@ static int __init qnap_ts409_pci_map_irq(const struct pci_dev *dev, u8 slot,
 static struct hw_pci qnap_ts409_pci __initdata = {
        .nr_controllers = 2,
-        .swizzle        = pci_std_swizzle,
        .setup          = orion5x_pci_sys_setup,
        .scan           = orion5x_pci_sys_scan_bus,
        .map_irq        = qnap_ts409_pci_map_irq,
diff --git a/arch/arm/mach-orion5x/ts78xx-fpga.h b/arch/arm/mach-orion5x/ts78xx-fpga.h
index 151e89e1e676..97c393d39ae2 100644
--- a/arch/arm/mach-orion5x/ts78xx-fpga.h
+++ b/arch/arm/mach-orion5x/ts78xx-fpga.h
@@ -28,9 +28,9 @@ struct fpga_device {
 struct fpga_devices {
        /* Technologic Systems */
-        struct fpga_device      ts_rtc;
+        struct fpga_device      ts_rtc;
-        struct fpga_device      ts_nand;
+        struct fpga_device      ts_nand;
-        struct fpga_device      ts_rng;
+        struct fpga_device      ts_rng;
 };
 struct ts78xx_fpga_data {
diff --git a/arch/arm/mach-orion5x/ts78xx-setup.c b/arch/arm/mach-orion5x/ts78xx-setup.c
index c96f37472eda..a74f3cf54cc5 100644
--- a/arch/arm/mach-orion5x/ts78xx-setup.c
+++ b/arch/arm/mach-orion5x/ts78xx-setup.c
@@ -8,6 +8,8 @@
 * warranty of any kind, whether express or implied.
 */
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/sysfs.h>
@@ -115,7 +117,7 @@ static struct platform_device ts78xx_ts_rtc_device = {
 * I've used the method TS use in their rtc7800.c example for the detection
 *
 * TODO: track down a guinea pig without an RTC to see if we can work out a
- *              better RTC detection routine
+ *              better RTC detection routine
 */
 static int ts78xx_ts_rtc_load(void)
 {
@@ -141,10 +143,14 @@ static int ts78xx_ts_rtc_load(void)
                        } else
                                rc = platform_device_add(&ts78xx_ts_rtc_device);
+                        if (rc)
+                                pr_info("RTC could not be registered: %d\n",
+                                        rc);
                        return rc;
                }
        }
+        pr_info("RTC not found\n");
        return -ENODEV;
 };
@@ -292,11 +298,8 @@ static struct platform_nand_data ts78xx_ts_nand_data = {
        },
 };
-static struct resource ts78xx_ts_nand_resources = {
+static struct resource ts78xx_ts_nand_resources
-        .start          = TS_NAND_DATA,
+                        = DEFINE_RES_MEM(TS_NAND_DATA, 4);
-        .end            = TS_NAND_DATA + 4,
-        .flags          = IORESOURCE_MEM,
-};
 static struct platform_device ts78xx_ts_nand_device = {
        .name           = "gen_nand",
@@ -319,6 +322,8 @@ static int ts78xx_ts_nand_load(void)
        } else
                rc = platform_device_add(&ts78xx_ts_nand_device);
+        if (rc)
+                pr_info("NAND could not be registered: %d\n", rc);
        return rc;
 };
@@ -332,11 +337,8 @@ static void ts78xx_ts_nand_unload(void)
 ****************************************************************************/
 #define TS_RNG_DATA     (TS78XX_FPGA_REGS_PHYS_BASE | 0x044)
-static struct resource ts78xx_ts_rng_resource = {
+static struct resource ts78xx_ts_rng_resource
-        .flags          = IORESOURCE_MEM,
+                        = DEFINE_RES_MEM(TS_RNG_DATA, 4);
-        .start          = TS_RNG_DATA,
-        .end            = TS_RNG_DATA + 4 - 1,
-};
 static struct timeriomem_rng_data ts78xx_ts_rng_data = {
        .period         = 1000000, /* one second */
@@ -363,6 +365,8 @@ static int ts78xx_ts_rng_load(void)
        } else
                rc = platform_device_add(&ts78xx_ts_rng_device);
+        if (rc)
+                pr_info("RNG could not be registered: %d\n", rc);
        return rc;
 };
@@ -402,7 +406,7 @@ static void ts78xx_fpga_supports(void)
                /* enable devices if magic matches */
                switch ((ts78xx_fpga.id >> 8) & 0xffffff) {
                case TS7800_FPGA_MAGIC:
-                        pr_warning("TS-7800 FPGA: unrecognized revision 0x%.2x\n",
+                        pr_warning("unrecognised FPGA revision 0x%.2x\n",
                                        ts78xx_fpga.id & 0xff);
                        ts78xx_fpga.supports.ts_rtc.present = 1;
                        ts78xx_fpga.supports.ts_nand.present = 1;
@@ -422,26 +426,20 @@ static int ts78xx_fpga_load_devices(void)
        if (ts78xx_fpga.supports.ts_rtc.present == 1) {
                tmp = ts78xx_ts_rtc_load();
-                if (tmp) {
+                if (tmp)
-                        pr_info("TS-78xx: RTC not registered\n");
                        ts78xx_fpga.supports.ts_rtc.present = 0;
-                }
                ret |= tmp;
        }
        if (ts78xx_fpga.supports.ts_nand.present == 1) {
                tmp = ts78xx_ts_nand_load();
-                if (tmp) {
+                if (tmp)
-                        pr_info("TS-78xx: NAND not registered\n");
                        ts78xx_fpga.supports.ts_nand.present = 0;
-                }
                ret |= tmp;
        }
        if (ts78xx_fpga.supports.ts_rng.present == 1) {
                tmp = ts78xx_ts_rng_load();
-                if (tmp) {
+                if (tmp)
-                        pr_info("TS-78xx: RNG not registered\n");
                        ts78xx_fpga.supports.ts_rng.present = 0;
-                }
                ret |= tmp;
        }
@@ -466,7 +464,7 @@ static int ts78xx_fpga_load(void)
 {
        ts78xx_fpga.id = readl(TS78XX_FPGA_REGS_VIRT_BASE);
-        pr_info("TS-78xx FPGA: magic=0x%.6x, rev=0x%.2x\n",
+        pr_info("FPGA magic=0x%.6x, rev=0x%.2x\n",
                        (ts78xx_fpga.id >> 8) & 0xffffff,
                        ts78xx_fpga.id & 0xff);
@@ -494,7 +492,7 @@ static int ts78xx_fpga_unload(void)
         * UrJTAG SVN since r1381 can be used to reprogram the FPGA
         */
        if (ts78xx_fpga.id != fpga_id) {
-                pr_err("TS-78xx FPGA: magic/rev mismatch\n"
+                pr_err("FPGA magic/rev mismatch\n"
                        "TS-78xx FPGA: was 0x%.6x/%.2x but now 0x%.6x/%.2x\n",
                        (ts78xx_fpga.id >> 8) & 0xffffff, ts78xx_fpga.id & 0xff,
                        (fpga_id >> 8) & 0xffffff, fpga_id & 0xff);
@@ -525,7 +523,7 @@ static ssize_t ts78xx_fpga_store(struct kobject *kobj,
        int value, ret;
        if (ts78xx_fpga.state < 0) {
-                pr_err("TS-78xx FPGA: borked, you must powercycle asap\n");
+                pr_err("FPGA borked, you must powercycle ASAP\n");
                return -EBUSY;
        }
@@ -533,10 +531,8 @@ static ssize_t ts78xx_fpga_store(struct kobject *kobj,
                value = 1;
        else if (strncmp(buf, "offline", sizeof("offline") - 1) == 0)
                value = 0;
-        else {
+        else
-                pr_err("ts78xx_fpga_store: Invalid value\n");
                return -EINVAL;
-        }
        if (ts78xx_fpga.state == value)
                return n;
@@ -614,7 +610,7 @@ static void __init ts78xx_init(void)
        /* FPGA init */
        ts78xx_fpga_devices_zero_init();
        ret = ts78xx_fpga_load();
-        ret = sysfs_create_file(power_kobj, &ts78xx_fpga_attr.attr);
+        ret = sysfs_create_file(firmware_kobj, &ts78xx_fpga_attr.attr);
        if (ret)
                pr_err("sysfs_create_file failed: %d\n", ret);
 }
diff --git a/arch/arm/mach-orion5x/wnr854t-setup.c b/arch/arm/mach-orion5x/wnr854t-setup.c
index 078c03f7cd52..754c12b6abf0 100644
--- a/arch/arm/mach-orion5x/wnr854t-setup.c
+++ b/arch/arm/mach-orion5x/wnr854t-setup.c
@@ -155,7 +155,6 @@ static int __init wnr854t_pci_map_irq(const struct pci_dev *dev, u8 slot,
 static struct hw_pci wnr854t_pci __initdata = {
        .nr_controllers = 2,
-        .swizzle        = pci_std_swizzle,
        .setup          = orion5x_pci_sys_setup,
        .scan           = orion5x_pci_sys_scan_bus,
        .map_irq        = wnr854t_pci_map_irq,
diff --git a/arch/arm/mach-orion5x/wrt350n-v2-setup.c b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
index 46a9778171ce..45c21251eb1e 100644
--- a/arch/arm/mach-orion5x/wrt350n-v2-setup.c
+++ b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
@@ -243,7 +243,6 @@ static int __init wrt350n_v2_pci_map_irq(const struct pci_dev *dev, u8 slot,
 static struct hw_pci wrt350n_v2_pci __initdata = {
        .nr_controllers = 2,
-        .swizzle        = pci_std_swizzle,
        .setup          = orion5x_pci_sys_setup,
        .scan           = orion5x_pci_sys_scan_bus,
        .map_irq        = wrt350n_v2_pci_map_irq,
diff --git a/arch/arm/mach-pnx4008/i2c.c b/arch/arm/mach-pnx4008/i2c.c
index 8103f9644e2d..550cfc2a1f2e 100644
--- a/arch/arm/mach-pnx4008/i2c.c
+++ b/arch/arm/mach-pnx4008/i2c.c
@@ -16,48 +16,62 @@
 #include <linux/err.h>
 #include <mach/platform.h>
 #include <mach/irqs.h>
-#include <mach/i2c.h>
-static struct i2c_pnx_data i2c0_data = {
+static struct resource i2c0_resources[] = {
-        .name = I2C_CHIP_NAME "0",
+        {
-        .base = PNX4008_I2C1_BASE,
+                .start = PNX4008_I2C1_BASE,
-        .irq = I2C_1_INT,
+                .end = PNX4008_I2C1_BASE + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = I2C_1_INT,
+                .end = I2C_1_INT,
+                .flags = IORESOURCE_IRQ,
+        },
 };
-static struct i2c_pnx_data i2c1_data = {
+static struct resource i2c1_resources[] = {
-        .name = I2C_CHIP_NAME "1",
+        {
-        .base = PNX4008_I2C2_BASE,
+                .start = PNX4008_I2C2_BASE,
-        .irq = I2C_2_INT,
+                .end = PNX4008_I2C2_BASE + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = I2C_2_INT,
+                .end = I2C_2_INT,
+                .flags = IORESOURCE_IRQ,
+        },
 };
-static struct i2c_pnx_data i2c2_data = {
+static struct resource i2c2_resources[] = {
-        .name = "USB-I2C",
+        {
-        .base = (PNX4008_USB_CONFIG_BASE + 0x300),
+                .start = PNX4008_USB_CONFIG_BASE + 0x300,
-        .irq = USB_I2C_INT,
+                .end = PNX4008_USB_CONFIG_BASE + 0x300 + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = USB_I2C_INT,
+                .end = USB_I2C_INT,
+                .flags = IORESOURCE_IRQ,
+        },
 };
 static struct platform_device i2c0_device = {
-        .name = "pnx-i2c",
+        .name = "pnx-i2c.0",
        .id = 0,
-        .dev = {
+        .resource = i2c0_resources,
-                .platform_data = &i2c0_data,
+        .num_resources = ARRAY_SIZE(i2c0_resources),
-        },
 };
 static struct platform_device i2c1_device = {
-        .name = "pnx-i2c",
+        .name = "pnx-i2c.1",
        .id = 1,
-        .dev = {
+        .resource = i2c1_resources,
-                .platform_data = &i2c1_data,
+        .num_resources = ARRAY_SIZE(i2c1_resources),
-        },
 };
 static struct platform_device i2c2_device = {
-        .name = "pnx-i2c",
+        .name = "pnx-i2c.2",
        .id = 2,
-        .dev = {
+        .resource = i2c2_resources,
-                .platform_data = &i2c2_data,
+        .num_resources = ARRAY_SIZE(i2c2_resources),
-        },
 };
 static struct platform_device *devices[] __initdata = {
diff --git a/arch/arm/mach-pnx4008/include/mach/i2c.h b/arch/arm/mach-pnx4008/include/mach/i2c.h
deleted file mode 100644
index 259ac53abf40..000000000000
--- a/arch/arm/mach-pnx4008/include/mach/i2c.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * PNX4008-specific tweaks for I2C IP3204 block
- *
- * Author: Vitaly Wool <vwool@ru.mvista.com>
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef __ASM_ARCH_I2C_H__
-#define __ASM_ARCH_I2C_H__
-enum {
-        mstatus_tdi = 0x00000001,
-        mstatus_afi = 0x00000002,
-        mstatus_nai = 0x00000004,
-        mstatus_drmi = 0x00000008,
-        mstatus_active = 0x00000020,
-        mstatus_scl = 0x00000040,
-        mstatus_sda = 0x00000080,
-        mstatus_rff = 0x00000100,
-        mstatus_rfe = 0x00000200,
-        mstatus_tff = 0x00000400,
-        mstatus_tfe = 0x00000800,
-};
-enum {
-        mcntrl_tdie = 0x00000001,
-        mcntrl_afie = 0x00000002,
-        mcntrl_naie = 0x00000004,
-        mcntrl_drmie = 0x00000008,
-        mcntrl_daie = 0x00000020,
-        mcntrl_rffie = 0x00000040,
-        mcntrl_tffie = 0x00000080,
-        mcntrl_reset = 0x00000100,
-        mcntrl_cdbmode = 0x00000400,
-};
-enum {
-        rw_bit = 1 << 0,
-        start_bit = 1 << 8,
-        stop_bit = 1 << 9,
-};
-#define I2C_REG_RX(a)   ((a)->ioaddr)           /* Rx FIFO reg (RO) */
-#define I2C_REG_TX(a)   ((a)->ioaddr)           /* Tx FIFO reg (WO) */
-#define I2C_REG_STS(a)  ((a)->ioaddr + 0x04)    /* Status reg (RO) */
-#define I2C_REG_CTL(a)  ((a)->ioaddr + 0x08)    /* Ctl reg */
-#define I2C_REG_CKL(a)  ((a)->ioaddr + 0x0c)    /* Clock divider low */
-#define I2C_REG_CKH(a)  ((a)->ioaddr + 0x10)    /* Clock divider high */
-#define I2C_REG_ADR(a)  ((a)->ioaddr + 0x14)    /* I2C address */
-#define I2C_REG_RFL(a)  ((a)->ioaddr + 0x18)    /* Rx FIFO level (RO) */
-#define I2C_REG_TFL(a)  ((a)->ioaddr + 0x1c)    /* Tx FIFO level (RO) */
-#define I2C_REG_RXB(a)  ((a)->ioaddr + 0x20)    /* Num of bytes Rx-ed (RO) */
-#define I2C_REG_TXB(a)  ((a)->ioaddr + 0x24)    /* Num of bytes Tx-ed (RO) */
-#define I2C_REG_TXS(a)  ((a)->ioaddr + 0x28)    /* Tx slave FIFO (RO) */
-#define I2C_REG_STFL(a) ((a)->ioaddr + 0x2c)    /* Tx slave FIFO level (RO) */
-#define HCLK_MHZ                13
-#define I2C_CHIP_NAME           "PNX4008-I2C"
-#endif                          /* __ASM_ARCH_I2C_H___ */
diff --git a/arch/arm/mach-prima2/irq.c b/arch/arm/mach-prima2/irq.c
index 37c2de9b6f26..a7b9415d30f8 100644
--- a/arch/arm/mach-prima2/irq.c
+++ b/arch/arm/mach-prima2/irq.c
@@ -42,7 +42,8 @@ sirfsoc_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
 static __init void sirfsoc_irq_init(void)
 {
        sirfsoc_alloc_gc(sirfsoc_intc_base, 0, 32);
-        sirfsoc_alloc_gc(sirfsoc_intc_base + 4, 32, SIRFSOC_INTENAL_IRQ_END - 32);
+        sirfsoc_alloc_gc(sirfsoc_intc_base + 4, 32,
+                        SIRFSOC_INTENAL_IRQ_END + 1 - 32);
        writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0);
        writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1);
@@ -68,7 +69,8 @@ void __init sirfsoc_of_irq_init(void)
        if (!sirfsoc_intc_base)
                panic("unable to map intc cpu registers\n");
-        irq_domain_add_legacy(np, 32, 0, 0, &irq_domain_simple_ops, NULL);
+        irq_domain_add_legacy(np, SIRFSOC_INTENAL_IRQ_END + 1, 0, 0,
+                &irq_domain_simple_ops, NULL);
        of_node_put(np);
diff --git a/arch/arm/mach-pxa/balloon3.c b/arch/arm/mach-pxa/balloon3.c
index c35456f02acb..56e8cebeb7d5 100644
--- a/arch/arm/mach-pxa/balloon3.c
+++ b/arch/arm/mach-pxa/balloon3.c
@@ -732,9 +732,7 @@ static inline void balloon3_nand_init(void) {}
 #if defined(CONFIG_REGULATOR_MAX1586) || \
    defined(CONFIG_REGULATOR_MAX1586_MODULE)
 static struct regulator_consumer_supply balloon3_max1587a_consumers[] = {
-        {
+        REGULATOR_SUPPLY("vcc_core", NULL),
-                .supply = "vcc_core",
-        }
 };
 static struct regulator_init_data balloon3_max1587a_v3_info = {
diff --git a/arch/arm/mach-pxa/cm-x2xx-pci.c b/arch/arm/mach-pxa/cm-x2xx-pci.c
index ebd9259f5ac9..d8f816c24a2f 100644
--- a/arch/arm/mach-pxa/cm-x2xx-pci.c
+++ b/arch/arm/mach-pxa/cm-x2xx-pci.c
@@ -181,11 +181,10 @@ static void cmx2xx_pci_preinit(void)
 }
 static struct hw_pci cmx2xx_pci __initdata = {
-        .swizzle        = pci_std_swizzle,
        .map_irq        = cmx2xx_pci_map_irq,
        .nr_controllers = 1,
+        .ops            = &it8152_ops,
        .setup          = it8152_pci_setup,
-        .scan           = it8152_pci_scan_bus,
        .preinit        = cmx2xx_pci_preinit,
 };
diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c
index 313274016277..3e4e9fe2d462 100644
--- a/arch/arm/mach-pxa/cm-x300.c
+++ b/arch/arm/mach-pxa/cm-x300.c
@@ -713,9 +713,7 @@ struct da9030_battery_info cm_x300_battery_info = {
 };
 static struct regulator_consumer_supply buck2_consumers[] = {
-        {
+        REGULATOR_SUPPLY("vcc_core", NULL),
-                .supply = "vcc_core",
-        },
 };
 static struct regulator_init_data buck2_data = {
diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c
index 16ec557b8e43..a3a4a38d4972 100644
--- a/arch/arm/mach-pxa/em-x270.c
+++ b/arch/arm/mach-pxa/em-x270.c
@@ -1085,10 +1085,7 @@ static void __init em_x270_userspace_consumers_init(void)
 /* DA9030 related initializations */
 #define REGULATOR_CONSUMER(_name, _dev_name, _supply)                   \
        static struct regulator_consumer_supply _name##_consumers[] = { \
-                {                                                       \
+                REGULATOR_SUPPLY(_supply, _dev_name),                   \
-                        .dev_name = _dev_name,                          \
-                        .supply = _supply,                              \
-                },                                                      \
        }
 REGULATOR_CONSUMER(ldo3, "reg-userspace-consumer.0", "vcc gps");
diff --git a/arch/arm/mach-pxa/hx4700.c b/arch/arm/mach-pxa/hx4700.c
index b83b95a29503..d09da6a746b8 100644
--- a/arch/arm/mach-pxa/hx4700.c
+++ b/arch/arm/mach-pxa/hx4700.c
@@ -22,6 +22,7 @@
 #include <linux/gpio.h>
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
+#include <linux/input/navpoint.h>
 #include <linux/lcd.h>
 #include <linux/mfd/htc-egpio.h>
 #include <linux/mfd/asic3.h>
@@ -102,6 +103,10 @@ static unsigned long hx4700_pin_config[] __initdata = {
        GPIO44_BTUART_CTS,
        GPIO45_BTUART_RTS_LPM_LOW,
+        /* STUART (IRDA) */
+        GPIO46_STUART_RXD,
+        GPIO47_STUART_TXD,
        /* PWM 1 (Backlight) */
        GPIO17_PWM1_OUT,
@@ -113,7 +118,7 @@ static unsigned long hx4700_pin_config[] __initdata = {
        GPIO113_I2S_SYSCLK,
        /* SSP 1 (NavPoint) */
-        GPIO23_SSP1_SCLK,
+        GPIO23_SSP1_SCLK_IN,
        GPIO24_SSP1_SFRM,
        GPIO25_SSP1_TXD,
        GPIO26_SSP1_RXD,
@@ -125,10 +130,13 @@ static unsigned long hx4700_pin_config[] __initdata = {
        GPIO88_GPIO,
        /* HX4700 specific input GPIOs */
-        GPIO12_GPIO,    /* ASIC3_IRQ */
+        GPIO12_GPIO | WAKEUP_ON_EDGE_RISE,      /* ASIC3_IRQ */
        GPIO13_GPIO,    /* W3220_IRQ */
        GPIO14_GPIO,    /* nWLAN_IRQ */
+        /* HX4700 specific output GPIOs */
+        GPIO102_GPIO | MFP_LPM_DRIVE_LOW,       /* SYNAPTICS_POWER_ON */
        GPIO10_GPIO,    /* GSM_IRQ */
        GPIO13_GPIO,    /* CPLD_IRQ */
        GPIO107_GPIO,   /* DS1WM_IRQ */
@@ -183,6 +191,23 @@ static struct platform_device gpio_keys = {
 };
 /*
+ * Synaptics NavPoint connected to SSP1
+ */
+static struct navpoint_platform_data navpoint_platform_data = {
+        .port   = 1,
+        .gpio   = GPIO102_HX4700_SYNAPTICS_POWER_ON,
+};
+static struct platform_device navpoint = {
+        .name   = "navpoint",
+        .id     = -1,
+        .dev = {
+                .platform_data = &navpoint_platform_data,
+        },
+};
+/*
 * ASIC3
 */
@@ -227,7 +252,6 @@ static u16 asic3_gpio_config[] = {
        ASIC3_GPIOC0_LED0,              /* red */
        ASIC3_GPIOC1_LED1,              /* green */
        ASIC3_GPIOC2_LED2,              /* blue */
-        ASIC3_GPIOC4_CF_nCD,
        ASIC3_GPIOC5_nCIOW,
        ASIC3_GPIOC6_nCIOR,
        ASIC3_GPIOC7_nPCE_1,
@@ -241,6 +265,7 @@ static u16 asic3_gpio_config[] = {
        ASIC3_GPIOC15_nPIOR,
        /* GPIOD: input GPIOs, CF */
+        ASIC3_GPIOD4_CF_nCD,
        ASIC3_GPIOD11_nCIOIS16,
        ASIC3_GPIOD12_nCWAIT,
        ASIC3_GPIOD15_nPIOW,
@@ -291,6 +316,7 @@ static struct asic3_platform_data asic3_platform_data = {
        .gpio_config_num = ARRAY_SIZE(asic3_gpio_config),
        .irq_base        = IRQ_BOARD_START,
        .gpio_base       = HX4700_ASIC3_GPIO_BASE,
+        .clock_rate      = 4000000,
        .leds            = asic3_leds,
 };
@@ -680,12 +706,8 @@ static struct platform_device power_supply = {
 */
 static struct regulator_consumer_supply bq24022_consumers[] = {
-        {
+        REGULATOR_SUPPLY("vbus_draw", NULL),
-                .supply = "vbus_draw",
+        REGULATOR_SUPPLY("ac_draw", NULL),
-        },
-        {
-                .supply = "ac_draw",
-        },
 };
 static struct regulator_init_data bq24022_init_data = {
@@ -764,9 +786,8 @@ static struct platform_device strataflash = {
 * Maxim MAX1587A on PI2C
 */
-static struct regulator_consumer_supply max1587a_consumer = {
+static struct regulator_consumer_supply max1587a_consumer =
-        .supply = "vcc_core",
+        REGULATOR_SUPPLY("vcc_core", NULL);
-};
 static struct regulator_init_data max1587a_v3_info = {
        .constraints = {
@@ -828,6 +849,7 @@ static struct platform_device audio = {
 static struct platform_device *devices[] __initdata = {
        &asic3,
        &gpio_keys,
+        &navpoint,
        &backlight,
        &w3220,
        &hx4700_lcd,
@@ -859,6 +881,7 @@ static void __init hx4700_init(void)
        int ret;
        pxa2xx_mfp_config(ARRAY_AND_SIZE(hx4700_pin_config));
+        gpio_set_wake(GPIO12_HX4700_ASIC3_IRQ, 1);
        ret = gpio_request_array(ARRAY_AND_SIZE(global_gpios));
        if (ret)
                pr_err ("hx4700: Failed to request GPIOs.\n");
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h b/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h
index a65867209aa0..a611ad3153c7 100644
--- a/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h
+++ b/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h
@@ -208,6 +208,7 @@
 #define GPIO113_I2S_SYSCLK      MFP_CFG_OUT(GPIO113, AF1, DRIVE_LOW)
 /* SSP 1 */
+#define GPIO23_SSP1_SCLK_IN     MFP_CFG_IN(GPIO23, AF2)
 #define GPIO23_SSP1_SCLK        MFP_CFG_OUT(GPIO23, AF2, DRIVE_LOW)
 #define GPIO29_SSP1_SCLK        MFP_CFG_IN(GPIO29, AF3)
 #define GPIO27_SSP1_SYSCLK      MFP_CFG_OUT(GPIO27, AF1, DRIVE_LOW)
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h b/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h
index c54cef25895c..cbf51ae81855 100644
--- a/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h
+++ b/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h
@@ -17,6 +17,7 @@
 *
 * bit     23 - Input/Output (PXA2xx specific)
 * bit     24 - Wakeup Enable(PXA2xx specific)
+ * bit     25 - Keep Output  (PXA2xx specific)
 */
 #define MFP_DIR_IN              (0x0 << 23)
@@ -25,6 +26,12 @@
 #define MFP_DIR(x)              (((x) >> 23) & 0x1)
 #define MFP_LPM_CAN_WAKEUP      (0x1 << 24)
+/*
+ * MFP_LPM_KEEP_OUTPUT must be specified for pins that need to
+ * retain their last output level (low or high).
+ * Note: MFP_LPM_KEEP_OUTPUT has no effect on pins configured for input.
+ */
 #define MFP_LPM_KEEP_OUTPUT     (0x1 << 25)
 #define WAKEUP_ON_EDGE_RISE     (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_RISE)
diff --git a/arch/arm/mach-pxa/include/mach/mioa701.h b/arch/arm/mach-pxa/include/mach/mioa701.h
index 02868447b0b1..e57f5c724e8a 100644
--- a/arch/arm/mach-pxa/include/mach/mioa701.h
+++ b/arch/arm/mach-pxa/include/mach/mioa701.h
@@ -61,6 +61,9 @@
 #define GPIO93_KEY_VOLUME_UP                    93
 #define GPIO94_KEY_VOLUME_DOWN                  94
+/* Camera */
+#define GPIO56_MT9M111_nOE                      56
 extern struct input_dev *mioa701_evdev;
 extern void mioa701_gpio_lpm_set(unsigned long mfp_pin);
diff --git a/arch/arm/mach-pxa/include/mach/pcm990_baseboard.h b/arch/arm/mach-pxa/include/mach/pcm990_baseboard.h
index d72791695b26..0260aaa2fc17 100644
--- a/arch/arm/mach-pxa/include/mach/pcm990_baseboard.h
+++ b/arch/arm/mach-pxa/include/mach/pcm990_baseboard.h
@@ -31,7 +31,6 @@
 #define PCM990_CTRL_INT_IRQ             PXA_GPIO_TO_IRQ(PCM990_CTRL_INT_IRQ_GPIO)
 #define PCM990_CTRL_INT_IRQ_EDGE        IRQ_TYPE_EDGE_RISING
 #define PCM990_CTRL_PHYS                PXA_CS1_PHYS    /* 16-Bit */
-#define PCM990_CTRL_BASE                0xea000000
 #define PCM990_CTRL_SIZE                (1*1024*1024)
 #define PCM990_CTRL_PWR_IRQ_GPIO        14
@@ -69,13 +68,13 @@
 #define PCM990_CTRL_MMC2DE      0x0004  /* R MMC2 Card detect */
 #define PCM990_CTRL_MMC2WP      0x0008  /* R MMC2 Card write protect */
-#define PCM990_CTRL_REG6        0x000C  /* Interrupt Clear REGISTER */
+#define PCM990_CTRL_INTSETCLR   0x000C  /* Interrupt Clear REGISTER */
 #define PCM990_CTRL_INTC0       0x0001  /* Clear Reg BT Detect */
 #define PCM990_CTRL_INTC1       0x0002  /* Clear Reg FR RI */
 #define PCM990_CTRL_INTC2       0x0004  /* Clear Reg MMC1 Detect */
 #define PCM990_CTRL_INTC3       0x0008  /* Clear Reg PM_5V off */
-#define PCM990_CTRL_REG7        0x000E  /* Interrupt Enable REGISTER */
+#define PCM990_CTRL_INTMSKENA   0x000E  /* Interrupt Enable REGISTER */
 #define PCM990_CTRL_ENAINT0     0x0001  /* Enable Int BT Detect */
 #define PCM990_CTRL_ENAINT1     0x0002  /* Enable Int FR RI */
 #define PCM990_CTRL_ENAINT2     0x0004  /* Enable Int MMC1 Detect */
@@ -102,32 +101,6 @@
 #define PCM990_CTRL_ACPRES      0x0004  /* DC Present */
 #define PCM990_CTRL_ACALARM     0x0008  /* Error Akku */
-#define PCM990_CTRL_P2V(x)      ((x) - PCM990_CTRL_PHYS + PCM990_CTRL_BASE)
-#define PCM990_CTRL_V2P(x)      ((x) - PCM990_CTRL_BASE + PCM990_CTRL_PHYS)
-#ifndef __ASSEMBLY__
-#  define __PCM990_CTRL_REG(x) \
-                (*((volatile unsigned char *)PCM990_CTRL_P2V(x)))
-#else
-#  define __PCM990_CTRL_REG(x)  PCM990_CTRL_P2V(x)
-#endif
-#define PCM990_INTMSKENA __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG7)
-#define PCM990_INTSETCLR __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG6)
-#define PCM990_CTRL0    __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG0)
-#define PCM990_CTRL1    __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG1)
-#define PCM990_CTRL2    __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG2)
-#define PCM990_CTRL3    __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG3)
-#define PCM990_CTRL4    __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG4)
-#define PCM990_CTRL5    __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG5)
-#define PCM990_CTRL6    __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG6)
-#define PCM990_CTRL7    __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG7)
-#define PCM990_CTRL8    __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG8)
-#define PCM990_CTRL9    __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG9)
-#define PCM990_CTRL10   __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG10)
-#define PCM990_CTRL11   __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG11)
 /*
 * IDE
 */
@@ -166,24 +139,6 @@
 #define PCM990_IDE_PLD_P2V(x) ((x) - PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_BASE)
 #define PCM990_IDE_PLD_V2P(x) ((x) - PCM990_IDE_PLD_BASE + PCM990_IDE_PLD_PHYS)
-#ifndef __ASSEMBLY__
-# define  __PCM990_IDE_PLD_REG(x) \
-        (*((volatile unsigned char *)PCM990_IDE_PLD_P2V(x)))
-#else
-# define  __PCM990_IDE_PLD_REG(x)       PCM990_IDE_PLD_P2V(x)
-#endif
-#define PCM990_IDE0 \
-        __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG0)
-#define PCM990_IDE1 \
-        __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG1)
-#define PCM990_IDE2 \
-        __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG2)
-#define PCM990_IDE3 \
-        __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG3)
-#define PCM990_IDE4 \
-        __PCM990_IDE_PLD_REG(PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_REG4)
 /*
 * Compact Flash
 */
@@ -196,10 +151,6 @@
 #define PCM990_CF_CD_EDGE       IRQ_TYPE_EDGE_RISING
 #define PCM990_CF_PLD_PHYS      0x30000000      /* 16 bit wide */
-#define PCM990_CF_PLD_BASE      0xef000000
-#define PCM990_CF_PLD_SIZE      (1*1024*1024)
-#define PCM990_CF_PLD_P2V(x)    ((x) - PCM990_CF_PLD_PHYS + PCM990_CF_PLD_BASE)
-#define PCM990_CF_PLD_V2P(x)    ((x) - PCM990_CF_PLD_BASE + PCM990_CF_PLD_PHYS)
 /* visible CPLD (U6) registers */
 #define PCM990_CF_PLD_REG0      0x1000  /* OFFSET CF REGISTER 0 */
@@ -239,21 +190,6 @@
 #define PCM990_CF_REG6_CD1      0x0001  /* R CF Card_Detect1 */
 #define PCM990_CF_REG6_CD2      0x0002  /* R CF Card_Detect2 */
-#ifndef __ASSEMBLY__
-#  define  __PCM990_CF_PLD_REG(x) \
-        (*((volatile unsigned char *)PCM990_CF_PLD_P2V(x)))
-#else
-#  define  __PCM990_CF_PLD_REG(x)       PCM990_CF_PLD_P2V(x)
-#endif
-#define PCM990_CF0 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG0)
-#define PCM990_CF1 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG1)
-#define PCM990_CF2 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG2)
-#define PCM990_CF3 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG3)
-#define PCM990_CF4 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG4)
-#define PCM990_CF5 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG5)
-#define PCM990_CF6 __PCM990_CF_PLD_REG(PCM990_CF_PLD_PHYS + PCM990_CF_PLD_REG6)
 /*
 * Wolfson AC97 Touch
 */
diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c
index 8de0651d7efb..2db697cd2b4e 100644
--- a/arch/arm/mach-pxa/magician.c
+++ b/arch/arm/mach-pxa/magician.c
@@ -579,12 +579,8 @@ static struct platform_device power_supply = {
 */
 static struct regulator_consumer_supply bq24022_consumers[] = {
-        {
+        REGULATOR_SUPPLY("vbus_draw", NULL),
-                .supply = "vbus_draw",
+        REGULATOR_SUPPLY("ac_draw", NULL),
-        },
-        {
-                .supply = "ac_draw",
-        },
 };
 static struct regulator_init_data bq24022_init_data = {
diff --git a/arch/arm/mach-pxa/mfp-pxa2xx.c b/arch/arm/mach-pxa/mfp-pxa2xx.c
index b0a842887780..ef0426a159d4 100644
--- a/arch/arm/mach-pxa/mfp-pxa2xx.c
+++ b/arch/arm/mach-pxa/mfp-pxa2xx.c
@@ -33,6 +33,8 @@
 #define BANK_OFF(n)     (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
 #define GPLR(x)         __REG2(0x40E00000, BANK_OFF((x) >> 5))
 #define GPDR(x)         __REG2(0x40E00000, BANK_OFF((x) >> 5) + 0x0c)
+#define GPSR(x)         __REG2(0x40E00000, BANK_OFF((x) >> 5) + 0x18)
+#define GPCR(x)         __REG2(0x40E00000, BANK_OFF((x) >> 5) + 0x24)
 #define PWER_WE35       (1 << 24)
@@ -348,6 +350,7 @@ static inline void pxa27x_mfp_init(void) {}
 #ifdef CONFIG_PM
 static unsigned long saved_gafr[2][4];
 static unsigned long saved_gpdr[4];
+static unsigned long saved_gplr[4];
 static unsigned long saved_pgsr[4];
 static int pxa2xx_mfp_suspend(void)
@@ -366,14 +369,26 @@ static int pxa2xx_mfp_suspend(void)
        }
        for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) {
                saved_gafr[0][i] = GAFR_L(i);
                saved_gafr[1][i] = GAFR_U(i);
                saved_gpdr[i] = GPDR(i * 32);
+                saved_gplr[i] = GPLR(i * 32);
                saved_pgsr[i] = PGSR(i);
-                GPDR(i * 32) = gpdr_lpm[i];
+                GPSR(i * 32) = PGSR(i);
+                GPCR(i * 32) = ~PGSR(i);
+        }
+        /* set GPDR bits taking into account MFP_LPM_KEEP_OUTPUT */
+        for (i = 0; i < pxa_last_gpio; i++) {
+                if ((gpdr_lpm[gpio_to_bank(i)] & GPIO_bit(i)) ||
+                    ((gpio_desc[i].config & MFP_LPM_KEEP_OUTPUT) &&
+                     (saved_gpdr[gpio_to_bank(i)] & GPIO_bit(i))))
+                        GPDR(i) |= GPIO_bit(i);
+                else
+                        GPDR(i) &= ~GPIO_bit(i);
        }
        return 0;
 }
@@ -384,6 +399,8 @@ static void pxa2xx_mfp_resume(void)
        for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) {
                GAFR_L(i) = saved_gafr[0][i];
                GAFR_U(i) = saved_gafr[1][i];
+                GPSR(i * 32) = saved_gplr[i];
+                GPCR(i * 32) = ~saved_gplr[i];
                GPDR(i * 32) = saved_gpdr[i];
                PGSR(i) = saved_pgsr[i];
        }
diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c
index 061d57009cee..bf99022b021f 100644
--- a/arch/arm/mach-pxa/mioa701.c
+++ b/arch/arm/mach-pxa/mioa701.c
@@ -103,6 +103,7 @@ static unsigned long mioa701_pin_config[] = {
        GPIO82_CIF_DD_5,
        GPIO84_CIF_FV,
        GPIO85_CIF_LV,
+        MIO_CFG_OUT(GPIO56_MT9M111_nOE, AF0, DRIVE_LOW),
        /* Bluetooth */
        MIO_CFG_IN(GPIO14_BT_nACTIVITY, AF0),
@@ -581,9 +582,7 @@ static struct wm97xx_pdata mioa701_wm97xx_pdata = {
 * Voltage regulation
 */
 static struct regulator_consumer_supply max1586_consumers[] = {
-        {
+        REGULATOR_SUPPLY("vcc_core", NULL),
-                .supply = "vcc_core",
-        }
 };
 static struct regulator_init_data max1586_v3_info = {
@@ -705,6 +704,7 @@ static struct gpio global_gpios[] = {
        { GPIO9_CHARGE_EN, GPIOF_OUT_INIT_HIGH, "Charger enable" },
        { GPIO18_POWEROFF, GPIOF_OUT_INIT_LOW, "Power Off" },
        { GPIO87_LCD_POWER, GPIOF_OUT_INIT_LOW, "LCD Power" },
+        { GPIO56_MT9M111_nOE, GPIOF_OUT_INIT_LOW, "Camera nOE" },
 };
 static void __init mioa701_machine_init(void)
diff --git a/arch/arm/mach-pxa/palm27x.c b/arch/arm/mach-pxa/palm27x.c
index fbc10d7b95d1..dad71cfa34c8 100644
--- a/arch/arm/mach-pxa/palm27x.c
+++ b/arch/arm/mach-pxa/palm27x.c
@@ -429,9 +429,7 @@ void __init palm27x_power_init(int ac, int usb)
 #if defined(CONFIG_REGULATOR_MAX1586) || \
    defined(CONFIG_REGULATOR_MAX1586_MODULE)
 static struct regulator_consumer_supply palm27x_max1587a_consumers[] = {
-        {
+        REGULATOR_SUPPLY("vcc_core", NULL),
-                .supply = "vcc_core",
-        }
 };
 static struct regulator_init_data palm27x_max1587a_v3_info = {
diff --git a/arch/arm/mach-pxa/pcm990-baseboard.c b/arch/arm/mach-pxa/pcm990-baseboard.c
index abab4e2b122c..cb723e84bc27 100644
--- a/arch/arm/mach-pxa/pcm990-baseboard.c
+++ b/arch/arm/mach-pxa/pcm990-baseboard.c
@@ -65,6 +65,18 @@ static unsigned long pcm990_pin_config[] __initdata = {
        GPIO31_AC97_SYNC,
 };
+static void __iomem *pcm990_cpld_base;
+static u8 pcm990_cpld_readb(unsigned int reg)
+{
+        return readb(pcm990_cpld_base + reg);
+}
+static void pcm990_cpld_writeb(u8 value, unsigned int reg)
+{
+        writeb(value, pcm990_cpld_base + reg);
+}
 /*
 * pcm990_lcd_power - control power supply to the LCD
 * @on: 0 = switch off, 1 = switch on
@@ -78,13 +90,13 @@ static void pcm990_lcd_power(int on, struct fb_var_screeninfo *var)
                /* enable LCD-Latches
                 * power on LCD
                 */
-                __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG3) =
+                pcm990_cpld_writeb(PCM990_CTRL_LCDPWR + PCM990_CTRL_LCDON,
-                        PCM990_CTRL_LCDPWR + PCM990_CTRL_LCDON;
+                                PCM990_CTRL_REG3);
        } else {
                /* disable LCD-Latches
                 * power off LCD
                 */
-                __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG3) = 0x00;
+                pcm990_cpld_writeb(0, PCM990_CTRL_REG3);
        }
 }
 #endif
@@ -243,15 +255,26 @@ static unsigned long pcm990_irq_enabled;
 static void pcm990_mask_ack_irq(struct irq_data *d)
 {
        int pcm990_irq = (d->irq - PCM027_IRQ(0));
-        PCM990_INTMSKENA = (pcm990_irq_enabled &= ~(1 << pcm990_irq));
+        pcm990_irq_enabled &= ~(1 << pcm990_irq);
+        pcm990_cpld_writeb(pcm990_irq_enabled, PCM990_CTRL_INTMSKENA);
 }
 static void pcm990_unmask_irq(struct irq_data *d)
 {
        int pcm990_irq = (d->irq - PCM027_IRQ(0));
+        u8 val;
        /* the irq can be acknowledged only if deasserted, so it's done here */
-        PCM990_INTSETCLR |= 1 << pcm990_irq;
-        PCM990_INTMSKENA  = (pcm990_irq_enabled |= (1 << pcm990_irq));
+        pcm990_irq_enabled |= (1 << pcm990_irq);
+        val = pcm990_cpld_readb(PCM990_CTRL_INTSETCLR);
+        val |= 1 << pcm990_irq;
+        pcm990_cpld_writeb(val, PCM990_CTRL_INTSETCLR);
+        pcm990_cpld_writeb(pcm990_irq_enabled, PCM990_CTRL_INTMSKENA);
 }
 static struct irq_chip pcm990_irq_chip = {
@@ -261,7 +284,10 @@ static struct irq_chip pcm990_irq_chip = {
 static void pcm990_irq_handler(unsigned int irq, struct irq_desc *desc)
 {
-        unsigned long pending = (~PCM990_INTSETCLR) & pcm990_irq_enabled;
+        unsigned long pending;
+        pending = ~pcm990_cpld_readb(PCM990_CTRL_INTSETCLR);
+        pending &= pcm990_irq_enabled;
        do {
                /* clear our parent IRQ */
@@ -270,7 +296,8 @@ static void pcm990_irq_handler(unsigned int irq, struct irq_desc *desc)
                        irq = PCM027_IRQ(0) + __ffs(pending);
                        generic_handle_irq(irq);
                }
-                pending = (~PCM990_INTSETCLR) & pcm990_irq_enabled;
+                pending = ~pcm990_cpld_readb(PCM990_CTRL_INTSETCLR);
+                pending &= pcm990_irq_enabled;
        } while (pending);
 }
@@ -285,8 +312,9 @@ static void __init pcm990_init_irq(void)
                set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
        }
-        PCM990_INTMSKENA = 0x00;        /* disable all Interrupts */
+        /* disable all Interrupts */
-        PCM990_INTSETCLR = 0xFF;
+        pcm990_cpld_writeb(0x0, PCM990_CTRL_INTMSKENA);
+        pcm990_cpld_writeb(0xff, PCM990_CTRL_INTSETCLR);
        irq_set_chained_handler(PCM990_CTRL_INT_IRQ, pcm990_irq_handler);
        irq_set_irq_type(PCM990_CTRL_INT_IRQ, PCM990_CTRL_INT_IRQ_EDGE);
@@ -309,13 +337,16 @@ static int pcm990_mci_init(struct device *dev, irq_handler_t mci_detect_int,
 static void pcm990_mci_setpower(struct device *dev, unsigned int vdd)
 {
        struct pxamci_platform_data *p_d = dev->platform_data;
+        u8 val;
+        val = pcm990_cpld_readb(PCM990_CTRL_REG5);
        if ((1 << vdd) & p_d->ocr_mask)
-                __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG5) =
+                val |= PCM990_CTRL_MMC2PWR;
-                                                PCM990_CTRL_MMC2PWR;
        else
-                __PCM990_CTRL_REG(PCM990_CTRL_PHYS + PCM990_CTRL_REG5) =
+                val &= ~PCM990_CTRL_MMC2PWR;
-                                                ~PCM990_CTRL_MMC2PWR;
+        pcm990_cpld_writeb(PCM990_CTRL_MMC2PWR, PCM990_CTRL_REG5);
 }
 static void pcm990_mci_exit(struct device *dev, void *data)
@@ -481,23 +512,6 @@ static struct platform_device pcm990_camera[] = {
 #endif /* CONFIG_VIDEO_PXA27x ||CONFIG_VIDEO_PXA27x_MODULE */
 /*
- * enable generic access to the base board control CPLDs U6 and U7
- */
-static struct map_desc pcm990_io_desc[] __initdata = {
-        {
-                .virtual        = PCM990_CTRL_BASE,
-                .pfn            = __phys_to_pfn(PCM990_CTRL_PHYS),
-                .length         = PCM990_CTRL_SIZE,
-                .type           = MT_DEVICE     /* CPLD */
-        }, {
-                .virtual        = PCM990_CF_PLD_BASE,
-                .pfn            = __phys_to_pfn(PCM990_CF_PLD_PHYS),
-                .length         = PCM990_CF_PLD_SIZE,
-                .type           = MT_DEVICE     /* CPLD */
-        }
-};
-/*
 * system init for baseboard usage. Will be called by pcm027 init.
 *
 * Add platform devices present on this baseboard and init
@@ -507,8 +521,11 @@ void __init pcm990_baseboard_init(void)
 {
        pxa2xx_mfp_config(ARRAY_AND_SIZE(pcm990_pin_config));
-        /* register CPLD access */
+        pcm990_cpld_base = ioremap(PCM990_CTRL_PHYS, PCM990_CTRL_SIZE);
-        iotable_init(ARRAY_AND_SIZE(pcm990_io_desc));
+        if (!pcm990_cpld_base) {
+                pr_err("pcm990: failed to ioremap cpld\n");
+                return;
+        }
        /* register CPLD's IRQ controller */
        pcm990_init_irq();
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index 6bce78edce7a..4726c246dcdc 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -421,8 +421,11 @@ void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info)
        pxa_register_device(&pxa27x_device_i2c_power, info);
 }
+static struct pxa_gpio_platform_data pxa27x_gpio_info __initdata = {
+        .gpio_set_wake = gpio_set_wake,
+};
 static struct platform_device *devices[] __initdata = {
-        &pxa_device_gpio,
        &pxa27x_device_udc,
        &pxa_device_pmu,
        &pxa_device_i2s,
@@ -458,6 +461,7 @@ static int __init pxa27x_init(void)
                register_syscore_ops(&pxa2xx_mfp_syscore_ops);
                register_syscore_ops(&pxa2xx_clock_syscore_ops);
+                pxa_register_device(&pxa_device_gpio, &pxa27x_gpio_info);
                ret = platform_add_devices(devices, ARRAY_SIZE(devices));
        }
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index df2ab0fb2ace..363d91b44ecb 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -877,9 +877,7 @@ static struct i2c_board_info spitz_i2c_devs[] = {
 };
 static struct regulator_consumer_supply isl6271a_consumers[] = {
-        {
+        REGULATOR_SUPPLY("vcc_core", NULL),
-                .supply = "vcc_core",
-        }
 };
 static struct regulator_init_data isl6271a_info[] = {
diff --git a/arch/arm/mach-pxa/stargate2.c b/arch/arm/mach-pxa/stargate2.c
index 4cd645e29b64..30b1b0b3c7f7 100644
--- a/arch/arm/mach-pxa/stargate2.c
+++ b/arch/arm/mach-pxa/stargate2.c
@@ -151,10 +151,7 @@ static struct platform_device sht15 = {
 };
 static struct regulator_consumer_supply stargate2_sensor_3_con[] = {
-        {
+        REGULATOR_SUPPLY("vcc", "sht15"),
-                .dev_name = "sht15",
-                .supply = "vcc",
-        },
 };
 enum stargate2_ldos{
diff --git a/arch/arm/mach-pxa/vpac270.c b/arch/arm/mach-pxa/vpac270.c
index c57ab636ea9c..e1740acd15f1 100644
--- a/arch/arm/mach-pxa/vpac270.c
+++ b/arch/arm/mach-pxa/vpac270.c
@@ -640,9 +640,7 @@ static inline void vpac270_ide_init(void) {}
 #if defined(CONFIG_REGULATOR_MAX1586) || \
    defined(CONFIG_REGULATOR_MAX1586_MODULE)
 static struct regulator_consumer_supply vpac270_max1587a_consumers[] = {
-        {
+        REGULATOR_SUPPLY("vcc_core", NULL),
-                .supply = "vcc_core",
-        }
 };
 static struct regulator_init_data vpac270_max1587a_v3_info = {
diff --git a/arch/arm/mach-pxa/z2.c b/arch/arm/mach-pxa/z2.c
index fa8619970841..b9320cb8a11f 100644
--- a/arch/arm/mach-pxa/z2.c
+++ b/arch/arm/mach-pxa/z2.c
@@ -615,9 +615,7 @@ static inline void z2_spi_init(void) {}
 #if defined(CONFIG_REGULATOR_TPS65023) || \
        defined(CONFIG_REGULATOR_TPS65023_MODULE)
 static struct regulator_consumer_supply z2_tps65021_consumers[] = {
-        {
+        REGULATOR_SUPPLY("vcc_core", NULL),
-                .supply = "vcc_core",
-        }
 };
 static struct regulator_init_data z2_tps65021_info[] = {
diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index 0f3a327ebcaa..b34287ab5afd 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -111,10 +111,6 @@ config S3C24XX_SETUP_TS
        help
          Compile in platform device definition for Samsung TouchScreen.
-# cpu-specific sections
-if CPU_S3C2410
 config S3C2410_DMA
        bool
        depends on S3C24XX_DMA && (CPU_S3C2410 || CPU_S3C2442)
@@ -127,6 +123,10 @@ config S3C2410_PM
        help
          Power Management code common to S3C2410 and better
+# cpu-specific sections
+if CPU_S3C2410
 config S3C24XX_SIMTEC_NOR
        bool
        help
diff --git a/arch/arm/mach-s3c24xx/bast-ide.c b/arch/arm/mach-s3c24xx/bast-ide.c
index 298ececfa366..ba02cf8d80a2 100644
--- a/arch/arm/mach-s3c24xx/bast-ide.c
+++ b/arch/arm/mach-s3c24xx/bast-ide.c
@@ -37,21 +37,9 @@ static struct pata_platform_info bast_ide_platdata = {
 #define IDE_CS  S3C2410_CS5
 static struct resource bast_ide0_resource[] = {
-        [0]     = {
+        [0] = DEFINE_RES_MEM(IDE_CS + BAST_PA_IDEPRI, 8 * 0x20),
-                .start  = IDE_CS + BAST_PA_IDEPRI,
+        [1] = DEFINE_RES_MEM(IDE_CS + BAST_PA_IDEPRIAUX + (6 * 0x20), 0x20),
-                .end    = IDE_CS + BAST_PA_IDEPRI + (8 * 0x20) - 1,
+        [2] = DEFINE_RES_IRQ(IRQ_IDE0),
-                .flags  = IORESOURCE_MEM,
-        },
-        [1]     = {
-                .start  = IDE_CS + BAST_PA_IDEPRIAUX + (6 * 0x20) ,
-                .end    = IDE_CS + BAST_PA_IDEPRIAUX + (7 * 0x20) - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [2]     = {
-                .start  = IRQ_IDE0,
-                .end    = IRQ_IDE0,
-                .flags  = IORESOURCE_IRQ,
-        },
 };
 static struct platform_device bast_device_ide0 = {
@@ -67,21 +55,9 @@ static struct platform_device bast_device_ide0 = {
 };
 static struct resource bast_ide1_resource[] = {
-        [0]     = {
+        [0] = DEFINE_RES_MEM(IDE_CS + BAST_PA_IDESEC, 8 * 0x20),
-                .start  = IDE_CS + BAST_PA_IDESEC,
+        [1] = DEFINE_RES_MEM(IDE_CS + BAST_PA_IDESECAUX + (6 * 0x20), 0x20),
-                .end    = IDE_CS + BAST_PA_IDESEC + (8 * 0x20) - 1,
+        [2] = DEFINE_RES_IRQ(IRQ_IDE1),
-                .flags  = IORESOURCE_MEM,
-        },
-        [1]     = {
-                .start  = IDE_CS + BAST_PA_IDESECAUX + (6 * 0x20),
-                .end    = IDE_CS + BAST_PA_IDESECAUX + (7 * 0x20) - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [2]     = {
-                .start  = IRQ_IDE1,
-                .end    = IRQ_IDE1,
-                .flags  = IORESOURCE_IRQ,
-        },
 };
 static struct platform_device bast_device_ide1 = {
diff --git a/arch/arm/mach-s3c24xx/mach-amlm5900.c b/arch/arm/mach-s3c24xx/mach-amlm5900.c
index 4220cc60de3c..ea2c4b003d58 100644
--- a/arch/arm/mach-s3c24xx/mach-amlm5900.c
+++ b/arch/arm/mach-s3c24xx/mach-amlm5900.c
@@ -65,13 +65,8 @@
 #include "common.h"
-static struct resource amlm5900_nor_resource = {
+static struct resource amlm5900_nor_resource =
-                .start = 0x00000000,
+                        DEFINE_RES_MEM(0x00000000, SZ_16M);
-                .end   = 0x01000000 - 1,
-                .flags = IORESOURCE_MEM,
-};
 static struct mtd_partition amlm5900_mtd_partitions[] = {
        {
diff --git a/arch/arm/mach-s3c24xx/mach-anubis.c b/arch/arm/mach-s3c24xx/mach-anubis.c
index 60c72c54c21e..5a7d0c0010f7 100644
--- a/arch/arm/mach-s3c24xx/mach-anubis.c
+++ b/arch/arm/mach-s3c24xx/mach-anubis.c
@@ -235,19 +235,9 @@ static struct pata_platform_info anubis_ide_platdata = {
 };
 static struct resource anubis_ide0_resource[] = {
-        {
+        [0] = DEFINE_RES_MEM(S3C2410_CS3, 8 * 32),
-                .start  = S3C2410_CS3,
+        [2] = DEFINE_RES_MEM(S3C2410_CS3 + (1 << 26) + (6 * 32), 32),
-                .end    = S3C2410_CS3 + (8*32) - 1,
+        [3] = DEFINE_RES_IRQ(IRQ_IDE0),
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = S3C2410_CS3 + (1<<26) + (6*32),
-                .end    = S3C2410_CS3 + (1<<26) + (7*32) - 1,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = IRQ_IDE0,
-                .end    = IRQ_IDE0,
-                .flags  = IORESOURCE_IRQ,
-        },
 };
 static struct platform_device anubis_device_ide0 = {
@@ -262,19 +252,9 @@ static struct platform_device anubis_device_ide0 = {
 };
 static struct resource anubis_ide1_resource[] = {
-        {
+        [0] = DEFINE_RES_MEM(S3C2410_CS4, 8 * 32),
-                .start  = S3C2410_CS4,
+        [1] = DEFINE_RES_MEM(S3C2410_CS4 + (1 << 26) + (6 * 32), 32),
-                .end    = S3C2410_CS4 + (8*32) - 1,
+        [2] = DEFINE_RES_IRQ(IRQ_IDE0),
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = S3C2410_CS4 + (1<<26) + (6*32),
-                .end    = S3C2410_CS4 + (1<<26) + (7*32) - 1,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = IRQ_IDE0,
-                .end    = IRQ_IDE0,
-                .flags  = IORESOURCE_IRQ,
-        },
 };
 static struct platform_device anubis_device_ide1 = {
@@ -298,16 +278,8 @@ static struct ax_plat_data anubis_asix_platdata = {
 };
 static struct resource anubis_asix_resource[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM(S3C2410_CS5, 0x20 * 0x20),
-                .start = S3C2410_CS5,
+        [1] = DEFINE_RES_IRQ(IRQ_ASIX),
-                .end   = S3C2410_CS5 + (0x20 * 0x20) -1,
-                .flags = IORESOURCE_MEM
-        },
-        [1] = {
-                .start = IRQ_ASIX,
-                .end   = IRQ_ASIX,
-                .flags = IORESOURCE_IRQ
-        }
 };
 static struct platform_device anubis_device_asix = {
@@ -323,21 +295,9 @@ static struct platform_device anubis_device_asix = {
 /* SM501 */
 static struct resource anubis_sm501_resource[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM(S3C2410_CS2, SZ_8M),
-                .start  = S3C2410_CS2,
+        [1] = DEFINE_RES_MEM(S3C2410_CS2 + SZ_64M - SZ_2M, SZ_2M),
-                .end    = S3C2410_CS2 + SZ_8M,
+        [2] = DEFINE_RES_IRQ(IRQ_EINT0),
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = S3C2410_CS2 + SZ_64M - SZ_2M,
-                .end    = S3C2410_CS2 + SZ_64M - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [2] = {
-                .start  = IRQ_EINT0,
-                .end    = IRQ_EINT0,
-                .flags  = IORESOURCE_IRQ,
-        },
 };
 static struct sm501_initdata anubis_sm501_initdata = {
diff --git a/arch/arm/mach-s3c24xx/mach-at2440evb.c b/arch/arm/mach-s3c24xx/mach-at2440evb.c
index d7ae49c90118..7a05abf1270b 100644
--- a/arch/arm/mach-s3c24xx/mach-at2440evb.c
+++ b/arch/arm/mach-s3c24xx/mach-at2440evb.c
@@ -118,21 +118,10 @@ static struct s3c2410_platform_nand __initdata at2440evb_nand_info = {
 /* DM9000AEP 10/100 ethernet controller */
 static struct resource at2440evb_dm9k_resource[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM(S3C2410_CS3, 4),
-                .start = S3C2410_CS3,
+        [1] = DEFINE_RES_MEM(S3C2410_CS3 + 4, 4),
-                .end   = S3C2410_CS3 + 3,
+        [2] = DEFINE_RES_NAMED(IRQ_EINT7, 1, NULL, IORESOURCE_IRQ \
-                .flags = IORESOURCE_MEM
+                                        | IORESOURCE_IRQ_HIGHEDGE),
-        },
-        [1] = {
-                .start = S3C2410_CS3 + 4,
-                .end   = S3C2410_CS3 + 7,
-                .flags = IORESOURCE_MEM
-        },
-        [2] = {
-                .start = IRQ_EINT7,
-                .end   = IRQ_EINT7,
-                .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
-        }
 };
 static struct dm9000_plat_data at2440evb_dm9k_pdata = {
diff --git a/arch/arm/mach-s3c24xx/mach-bast.c b/arch/arm/mach-s3c24xx/mach-bast.c
index 53219c02eca0..1cf1720682d3 100644
--- a/arch/arm/mach-s3c24xx/mach-bast.c
+++ b/arch/arm/mach-s3c24xx/mach-bast.c
@@ -310,22 +310,10 @@ static struct s3c2410_platform_nand __initdata bast_nand_info = {
 /* DM9000 */
 static struct resource bast_dm9k_resource[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_DM9000, 4),
-                .start = S3C2410_CS5 + BAST_PA_DM9000,
+        [1] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_DM9000 + 0x40, 0x40),
-                .end   = S3C2410_CS5 + BAST_PA_DM9000 + 3,
+        [2] = DEFINE_RES_NAMED(IRQ_DM9000 , 1, NULL, IORESOURCE_IRQ \
-                .flags = IORESOURCE_MEM,
+                                        | IORESOURCE_IRQ_HIGHLEVEL),
-        },
-        [1] = {
-                .start = S3C2410_CS5 + BAST_PA_DM9000 + 0x40,
-                .end   = S3C2410_CS5 + BAST_PA_DM9000 + 0x40 + 0x3f,
-                .flags = IORESOURCE_MEM,
-        },
-        [2] = {
-                .start = IRQ_DM9000,
-                .end   = IRQ_DM9000,
-                .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
-        }
 };
 /* for the moment we limit ourselves to 16bit IO until some
@@ -400,21 +388,9 @@ static struct ax_plat_data bast_asix_platdata = {
 };
 static struct resource bast_asix_resource[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_ASIXNET, 0x18 * 0x20),
-                .start = S3C2410_CS5 + BAST_PA_ASIXNET,
+        [1] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20), 1),
-                .end   = S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20) - 1,
+        [2] = DEFINE_RES_IRQ(IRQ_ASIX),
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20),
-                .end   = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20),
-                .flags = IORESOURCE_MEM,
-        },
-        [2] = {
-                .start = IRQ_ASIX,
-                .end   = IRQ_ASIX,
-                .flags = IORESOURCE_IRQ
-        }
 };
 static struct platform_device bast_device_asix = {
@@ -430,11 +406,8 @@ static struct platform_device bast_device_asix = {
 /* Asix AX88796 10/100 ethernet controller parallel port */
 static struct resource bast_asixpp_resource[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20), \
-                .start = S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20),
+                                        0x30 * 0x20),
-                .end   = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1b * 0x20) - 1,
-                .flags = IORESOURCE_MEM,
-        }
 };
 static struct platform_device bast_device_axpp = {
diff --git a/arch/arm/mach-s3c24xx/mach-gta02.c b/arch/arm/mach-s3c24xx/mach-gta02.c
index ba5d85394105..0f29f64a3eeb 100644
--- a/arch/arm/mach-s3c24xx/mach-gta02.c
+++ b/arch/arm/mach-s3c24xx/mach-gta02.c
@@ -387,11 +387,8 @@ static struct physmap_flash_data gta02_nor_flash_data = {
        .width          = 2,
 };
-static struct resource gta02_nor_flash_resource = {
+static struct resource gta02_nor_flash_resource =
-        .start          = GTA02_FLASH_BASE,
+        DEFINE_RES_MEM(GTA02_FLASH_BASE, GTA02_FLASH_SIZE);
-        .end            = GTA02_FLASH_BASE + GTA02_FLASH_SIZE - 1,
-        .flags          = IORESOURCE_MEM,
-};
 static struct platform_device gta02_nor_flash = {
        .name           = "physmap-flash",
diff --git a/arch/arm/mach-s3c24xx/mach-h1940.c b/arch/arm/mach-s3c24xx/mach-h1940.c
index 6b21ba107eab..bb8d008d5a5c 100644
--- a/arch/arm/mach-s3c24xx/mach-h1940.c
+++ b/arch/arm/mach-s3c24xx/mach-h1940.c
@@ -253,13 +253,8 @@ static struct pda_power_pdata power_supply_info = {
 };
 static struct resource power_supply_resources[] = {
-        [0] = {
+        [0] = DEFINE_RES_NAMED(IRQ_EINT2, 1, "ac", IORESOURCE_IRQ \
-                        .name   = "ac",
+                        | IORESOURCE_IRQ_LOWEDGE | IORESOURCE_IRQ_HIGHEDGE),
-                        .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE |
-                                          IORESOURCE_IRQ_HIGHEDGE,
-                        .start  = IRQ_EINT2,
-                        .end    = IRQ_EINT2,
-        },
 };
 static struct platform_device power_supply = {
diff --git a/arch/arm/mach-s3c24xx/mach-mini2440.c b/arch/arm/mach-s3c24xx/mach-mini2440.c
index 5d66fb218a41..f092b188ab70 100644
--- a/arch/arm/mach-s3c24xx/mach-mini2440.c
+++ b/arch/arm/mach-s3c24xx/mach-mini2440.c
@@ -292,21 +292,10 @@ static struct s3c2410_platform_nand mini2440_nand_info __initdata = {
 /* DM9000AEP 10/100 ethernet controller */
 static struct resource mini2440_dm9k_resource[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM(MACH_MINI2440_DM9K_BASE, 4),
-                .start = MACH_MINI2440_DM9K_BASE,
+        [1] = DEFINE_RES_MEM(MACH_MINI2440_DM9K_BASE + 4, 4),
-                .end   = MACH_MINI2440_DM9K_BASE + 3,
+        [2] = DEFINE_RES_NAMED(IRQ_EINT7, 1, NULL, IORESOURCE_IRQ \
-                .flags = IORESOURCE_MEM
+                                                | IORESOURCE_IRQ_HIGHEDGE),
-        },
-        [1] = {
-                .start = MACH_MINI2440_DM9K_BASE + 4,
-                .end   = MACH_MINI2440_DM9K_BASE + 7,
-                .flags = IORESOURCE_MEM
-        },
-        [2] = {
-                .start = IRQ_EINT7,
-                .end   = IRQ_EINT7,
-                .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
-        }
 };
 /*
diff --git a/arch/arm/mach-s3c24xx/mach-nexcoder.c b/arch/arm/mach-s3c24xx/mach-nexcoder.c
index 5198e3e1c5be..5c05ba1c330f 100644
--- a/arch/arm/mach-s3c24xx/mach-nexcoder.c
+++ b/arch/arm/mach-s3c24xx/mach-nexcoder.c
@@ -84,11 +84,7 @@ static struct s3c2410_uartcfg nexcoder_uartcfgs[] __initdata = {
 /* NOR Flash on NexVision NexCoder 2440 board */
 static struct resource nexcoder_nor_resource[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM(S3C2410_CS0, SZ_8M),
-                .start = S3C2410_CS0,
-                .end   = S3C2410_CS0 + (8*1024*1024) - 1,
-                .flags = IORESOURCE_MEM,
-        }
 };
 static struct map_info nexcoder_nor_map = {
diff --git a/arch/arm/mach-s3c24xx/mach-osiris.c b/arch/arm/mach-s3c24xx/mach-osiris.c
index c5daeb612a88..95d077255024 100644
--- a/arch/arm/mach-s3c24xx/mach-osiris.c
+++ b/arch/arm/mach-s3c24xx/mach-osiris.c
@@ -244,16 +244,8 @@ static struct s3c2410_platform_nand __initdata osiris_nand_info = {
 /* PCMCIA control and configuration */
 static struct resource osiris_pcmcia_resource[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM(0x0f000000, SZ_1M),
-                .start  = 0x0f000000,
+        [1] = DEFINE_RES_MEM(0x0c000000, SZ_1M),
-                .end    = 0x0f100000,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = 0x0c000000,
-                .end    = 0x0c100000,
-                .flags  = IORESOURCE_MEM,
-        }
 };
 static struct platform_device osiris_pcmcia = {
diff --git a/arch/arm/mach-s3c24xx/mach-otom.c b/arch/arm/mach-s3c24xx/mach-otom.c
index 5f1e0eeb38a9..bc4b6efb3b27 100644
--- a/arch/arm/mach-s3c24xx/mach-otom.c
+++ b/arch/arm/mach-s3c24xx/mach-otom.c
@@ -77,11 +77,7 @@ static struct s3c2410_uartcfg otom11_uartcfgs[] __initdata = {
 /* NOR Flash on NexVision OTOM board */
 static struct resource otom_nor_resource[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM(S3C2410_CS0, SZ_4M),
-                .start = S3C2410_CS0,
-                .end   = S3C2410_CS0 + (4*1024*1024) - 1,
-                .flags = IORESOURCE_MEM,
-        }
 };
 static struct platform_device otom_device_nor = {
diff --git a/arch/arm/mach-s3c24xx/mach-qt2410.c b/arch/arm/mach-s3c24xx/mach-qt2410.c
index 91c16d9d2459..b868dddcb836 100644
--- a/arch/arm/mach-s3c24xx/mach-qt2410.c
+++ b/arch/arm/mach-s3c24xx/mach-qt2410.c
@@ -180,16 +180,8 @@ static struct s3c2410fb_mach_info qt2410_fb_info __initdata = {
 /* CS8900 */
 static struct resource qt2410_cs89x0_resources[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM(0x19000000, 17),
-                .start  = 0x19000000,
+        [1] = DEFINE_RES_IRQ(IRQ_EINT9),
-                .end    = 0x19000000 + 16,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = IRQ_EINT9,
-                .end    = IRQ_EINT9,
-                .flags  = IORESOURCE_IRQ,
-        },
 };
 static struct platform_device qt2410_cs89x0 = {
diff --git a/arch/arm/mach-s3c24xx/mach-rx1950.c b/arch/arm/mach-s3c24xx/mach-rx1950.c
index 200debb4c72d..a6762aae4727 100644
--- a/arch/arm/mach-s3c24xx/mach-rx1950.c
+++ b/arch/arm/mach-s3c24xx/mach-rx1950.c
@@ -152,13 +152,8 @@ static struct pda_power_pdata power_supply_info = {
 };
 static struct resource power_supply_resources[] = {
-        [0] = {
+        [0] = DEFINE_RES_NAMED(IRQ_EINT2, 1, "ac", IORESOURCE_IRQ \
-                        .name   = "ac",
+                        | IORESOURCE_IRQ_LOWEDGE | IORESOURCE_IRQ_HIGHEDGE),
-                        .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE |
-                                          IORESOURCE_IRQ_HIGHEDGE,
-                        .start  = IRQ_EINT2,
-                        .end    = IRQ_EINT2,
-        },
 };
 static struct platform_device power_supply = {
diff --git a/arch/arm/mach-s3c24xx/mach-tct_hammer.c b/arch/arm/mach-s3c24xx/mach-tct_hammer.c
index 1114666f0efb..fe990289ee7d 100644
--- a/arch/arm/mach-s3c24xx/mach-tct_hammer.c
+++ b/arch/arm/mach-s3c24xx/mach-tct_hammer.c
@@ -56,11 +56,8 @@
 #include "common.h"
-static struct resource tct_hammer_nor_resource = {
+static struct resource tct_hammer_nor_resource =
-                .start = 0x00000000,
+                        DEFINE_RES_MEM(0x00000000, SZ_16M);
-                .end   = 0x01000000 - 1,
-                .flags = IORESOURCE_MEM,
-};
 static struct mtd_partition tct_hammer_mtd_partitions[] = {
        {
diff --git a/arch/arm/mach-s3c24xx/mach-vr1000.c b/arch/arm/mach-s3c24xx/mach-vr1000.c
index 87608d45dac4..bd5f189f0424 100644
--- a/arch/arm/mach-s3c24xx/mach-vr1000.c
+++ b/arch/arm/mach-s3c24xx/mach-vr1000.c
@@ -187,40 +187,17 @@ static struct platform_device serial_device = {
 /* DM9000 ethernet devices */
 static struct resource vr1000_dm9k0_resource[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM(S3C2410_CS5 + VR1000_PA_DM9000, 4),
-                .start = S3C2410_CS5 + VR1000_PA_DM9000,
+        [1] = DEFINE_RES_MEM(S3C2410_CS5 + VR1000_PA_DM9000 + 0x40, 0x40),
-                .end   = S3C2410_CS5 + VR1000_PA_DM9000 + 3,
+        [2] = DEFINE_RES_NAMED(IRQ_VR1000_DM9000A, 1, NULL, IORESOURCE_IRQ \
-                .flags = IORESOURCE_MEM
+                                                | IORESOURCE_IRQ_HIGHLEVEL),
-        },
-        [1] = {
-                .start = S3C2410_CS5 + VR1000_PA_DM9000 + 0x40,
-                .end   = S3C2410_CS5 + VR1000_PA_DM9000 + 0x7f,
-                .flags = IORESOURCE_MEM
-        },
-        [2] = {
-                .start = IRQ_VR1000_DM9000A,
-                .end   = IRQ_VR1000_DM9000A,
-                .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
-        }
 };
 static struct resource vr1000_dm9k1_resource[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM(S3C2410_CS5 + VR1000_PA_DM9000 + 0x80, 4),
-                .start = S3C2410_CS5 + VR1000_PA_DM9000 + 0x80,
+        [1] = DEFINE_RES_MEM(S3C2410_CS5 + VR1000_PA_DM9000 + 0xC0, 0x40),
-                .end   = S3C2410_CS5 + VR1000_PA_DM9000 + 0x83,
+        [2] = DEFINE_RES_NAMED(IRQ_VR1000_DM9000N, 1, NULL, IORESOURCE_IRQ \
-                .flags = IORESOURCE_MEM
+                                                | IORESOURCE_IRQ_HIGHLEVEL),
-        },
-        [1] = {
-                .start = S3C2410_CS5 + VR1000_PA_DM9000 + 0xC0,
-                .end   = S3C2410_CS5 + VR1000_PA_DM9000 + 0xFF,
-                .flags = IORESOURCE_MEM
-        },
-        [2] = {
-                .start = IRQ_VR1000_DM9000N,
-                .end   = IRQ_VR1000_DM9000N,
-                .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
-        }
 };
 /* for the moment we limit ourselves to 16bit IO until some
diff --git a/arch/arm/mach-s3c24xx/simtec-nor.c b/arch/arm/mach-s3c24xx/simtec-nor.c
index b9d6d4f92c03..029744fcaacb 100644
--- a/arch/arm/mach-s3c24xx/simtec-nor.c
+++ b/arch/arm/mach-s3c24xx/simtec-nor.c
@@ -55,11 +55,7 @@ static struct physmap_flash_data simtec_nor_pdata = {
 };
 static struct resource simtec_nor_resource[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM(S3C2410_CS1 + 0x4000000, SZ_8M),
-                .start = S3C2410_CS1 + 0x4000000,
-                .end   = S3C2410_CS1 + 0x4000000 + SZ_8M - 1,
-                .flags = IORESOURCE_MEM,
-        }
 };
 static struct platform_device simtec_device_nor = {
diff --git a/arch/arm/mach-s3c64xx/dev-audio.c b/arch/arm/mach-s3c64xx/dev-audio.c
index 93470b158a4e..124fd5d63006 100644
--- a/arch/arm/mach-s3c64xx/dev-audio.c
+++ b/arch/arm/mach-s3c64xx/dev-audio.c
@@ -57,21 +57,9 @@ static int s3c64xx_i2s_cfg_gpio(struct platform_device *pdev)
 }
 static struct resource s3c64xx_iis0_resource[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM(S3C64XX_PA_IIS0, SZ_256),
-                .start = S3C64XX_PA_IIS0,
+        [1] = DEFINE_RES_DMA(DMACH_I2S0_OUT),
-                .end   = S3C64XX_PA_IIS0 + 0x100 - 1,
+        [2] = DEFINE_RES_DMA(DMACH_I2S0_IN),
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = DMACH_I2S0_OUT,
-                .end   = DMACH_I2S0_OUT,
-                .flags = IORESOURCE_DMA,
-        },
-        [2] = {
-                .start = DMACH_I2S0_IN,
-                .end   = DMACH_I2S0_IN,
-                .flags = IORESOURCE_DMA,
-        },
 };
 static struct s3c_audio_pdata i2sv3_pdata = {
@@ -95,21 +83,9 @@ struct platform_device s3c64xx_device_iis0 = {
 EXPORT_SYMBOL(s3c64xx_device_iis0);
 static struct resource s3c64xx_iis1_resource[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM(S3C64XX_PA_IIS1, SZ_256),
-                .start = S3C64XX_PA_IIS1,
+        [1] = DEFINE_RES_DMA(DMACH_I2S1_OUT),
-                .end   = S3C64XX_PA_IIS1 + 0x100 - 1,
+        [2] = DEFINE_RES_DMA(DMACH_I2S1_IN),
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = DMACH_I2S1_OUT,
-                .end   = DMACH_I2S1_OUT,
-                .flags = IORESOURCE_DMA,
-        },
-        [2] = {
-                .start = DMACH_I2S1_IN,
-                .end   = DMACH_I2S1_IN,
-                .flags = IORESOURCE_DMA,
-        },
 };
 struct platform_device s3c64xx_device_iis1 = {
@@ -124,21 +100,9 @@ struct platform_device s3c64xx_device_iis1 = {
 EXPORT_SYMBOL(s3c64xx_device_iis1);
 static struct resource s3c64xx_iisv4_resource[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM(S3C64XX_PA_IISV4, SZ_256),
-                .start = S3C64XX_PA_IISV4,
+        [1] = DEFINE_RES_DMA(DMACH_HSI_I2SV40_TX),
-                .end   = S3C64XX_PA_IISV4 + 0x100 - 1,
+        [2] = DEFINE_RES_DMA(DMACH_HSI_I2SV40_RX),
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = DMACH_HSI_I2SV40_TX,
-                .end   = DMACH_HSI_I2SV40_TX,
-                .flags = IORESOURCE_DMA,
-        },
-        [2] = {
-                .start = DMACH_HSI_I2SV40_RX,
-                .end   = DMACH_HSI_I2SV40_RX,
-                .flags = IORESOURCE_DMA,
-        },
 };
 static struct s3c_audio_pdata i2sv4_pdata = {
@@ -187,21 +151,9 @@ static int s3c64xx_pcm_cfg_gpio(struct platform_device *pdev)
 }
 static struct resource s3c64xx_pcm0_resource[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM(S3C64XX_PA_PCM0, SZ_256),
-                .start = S3C64XX_PA_PCM0,
+        [1] = DEFINE_RES_DMA(DMACH_PCM0_TX),
-                .end   = S3C64XX_PA_PCM0 + 0x100 - 1,
+        [2] = DEFINE_RES_DMA(DMACH_PCM0_RX),
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = DMACH_PCM0_TX,
-                .end   = DMACH_PCM0_TX,
-                .flags = IORESOURCE_DMA,
-        },
-        [2] = {
-                .start = DMACH_PCM0_RX,
-                .end   = DMACH_PCM0_RX,
-                .flags = IORESOURCE_DMA,
-        },
 };
 static struct s3c_audio_pdata s3c_pcm0_pdata = {
@@ -220,21 +172,9 @@ struct platform_device s3c64xx_device_pcm0 = {
 EXPORT_SYMBOL(s3c64xx_device_pcm0);
 static struct resource s3c64xx_pcm1_resource[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM(S3C64XX_PA_PCM1, SZ_256),
-                .start = S3C64XX_PA_PCM1,
+        [1] = DEFINE_RES_DMA(DMACH_PCM1_TX),
-                .end   = S3C64XX_PA_PCM1 + 0x100 - 1,
+        [2] = DEFINE_RES_DMA(DMACH_PCM1_RX),
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = DMACH_PCM1_TX,
-                .end   = DMACH_PCM1_TX,
-                .flags = IORESOURCE_DMA,
-        },
-        [2] = {
-                .start = DMACH_PCM1_RX,
-                .end   = DMACH_PCM1_RX,
-                .flags = IORESOURCE_DMA,
-        },
 };
 static struct s3c_audio_pdata s3c_pcm1_pdata = {
@@ -265,31 +205,11 @@ static int s3c64xx_ac97_cfg_gpe(struct platform_device *pdev)
 }
 static struct resource s3c64xx_ac97_resource[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM(S3C64XX_PA_AC97, SZ_256),
-                .start = S3C64XX_PA_AC97,
+        [1] = DEFINE_RES_DMA(DMACH_AC97_PCMOUT),
-                .end   = S3C64XX_PA_AC97 + 0x100 - 1,
+        [2] = DEFINE_RES_DMA(DMACH_AC97_PCMIN),
-                .flags = IORESOURCE_MEM,
+        [3] = DEFINE_RES_DMA(DMACH_AC97_MICIN),
-        },
+        [4] = DEFINE_RES_IRQ(IRQ_AC97),
-        [1] = {
-                .start = DMACH_AC97_PCMOUT,
-                .end   = DMACH_AC97_PCMOUT,
-                .flags = IORESOURCE_DMA,
-        },
-        [2] = {
-                .start = DMACH_AC97_PCMIN,
-                .end   = DMACH_AC97_PCMIN,
-                .flags = IORESOURCE_DMA,
-        },
-        [3] = {
-                .start = DMACH_AC97_MICIN,
-                .end   = DMACH_AC97_MICIN,
-                .flags = IORESOURCE_DMA,
-        },
-        [4] = {
-                .start = IRQ_AC97,
-                .end   = IRQ_AC97,
-                .flags = IORESOURCE_IRQ,
-        },
 };
 static struct s3c_audio_pdata s3c_ac97_pdata;
diff --git a/arch/arm/mach-s3c64xx/dev-uart.c b/arch/arm/mach-s3c64xx/dev-uart.c
index c681b99eda08..46e18d77ea93 100644
--- a/arch/arm/mach-s3c64xx/dev-uart.c
+++ b/arch/arm/mach-s3c64xx/dev-uart.c
@@ -31,55 +31,23 @@
 /* 64xx uarts are closer together */
 static struct resource s3c64xx_uart0_resource[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM(S3C_PA_UART0, SZ_256),
-                .start  = S3C_PA_UART0,
+        [1] = DEFINE_RES_IRQ(IRQ_UART0),
-                .end    = S3C_PA_UART0 + 0x100,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = IRQ_UART0,
-                .end    = IRQ_UART0,
-                .flags  = IORESOURCE_IRQ,
-        },
 };
 static struct resource s3c64xx_uart1_resource[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM(S3C_PA_UART1, SZ_256),
-                .start = S3C_PA_UART1,
+        [1] = DEFINE_RES_IRQ(IRQ_UART1),
-                .end   = S3C_PA_UART1 + 0x100,
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = IRQ_UART1,
-                .end    = IRQ_UART1,
-                .flags  = IORESOURCE_IRQ,
-        },
 };
 static struct resource s3c6xx_uart2_resource[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM(S3C_PA_UART2, SZ_256),
-                .start = S3C_PA_UART2,
+        [1] = DEFINE_RES_IRQ(IRQ_UART2),
-                .end   = S3C_PA_UART2 + 0x100,
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = IRQ_UART2,
-                .end    = IRQ_UART2,
-                .flags  = IORESOURCE_IRQ,
-        },
 };
 static struct resource s3c64xx_uart3_resource[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM(S3C_PA_UART3, SZ_256),
-                .start = S3C_PA_UART3,
+        [1] = DEFINE_RES_IRQ(IRQ_UART3),
-                .end   = S3C_PA_UART3 + 0x100,
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = IRQ_UART3,
-                .end    = IRQ_UART3,
-                .flags  = IORESOURCE_IRQ,
-        },
 };
diff --git a/arch/arm/mach-s3c64xx/mach-anw6410.c b/arch/arm/mach-s3c64xx/mach-anw6410.c
index b86f2779e4e6..f252691fb209 100644
--- a/arch/arm/mach-s3c64xx/mach-anw6410.c
+++ b/arch/arm/mach-s3c64xx/mach-anw6410.c
@@ -165,21 +165,10 @@ static void __init anw6410_dm9000_enable(void)
 }
 static struct resource anw6410_dm9000_resource[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM(ANW6410_PA_DM9000, 4),
-                .start = ANW6410_PA_DM9000,
+        [1] = DEFINE_RES_MEM(ANW6410_PA_DM9000 + 4, 501),
-                .end   = ANW6410_PA_DM9000 + 3,
+        [2] = DEFINE_RES_NAMED(IRQ_EINT(15), 1, NULL, IORESOURCE_IRQ \
-                .flags = IORESOURCE_MEM,
+                                        | IRQF_TRIGGER_HIGH),
-        },
-        [1] = {
-                .start = ANW6410_PA_DM9000 + 4,
-                .end   = ANW6410_PA_DM9000 + 4 + 500,
-                .flags = IORESOURCE_MEM,
-        },
-        [2] = {
-                .start = IRQ_EINT(15),
-                .end   = IRQ_EINT(15),
-                .flags = IORESOURCE_IRQ | IRQF_TRIGGER_HIGH,
-        },
 };
 static struct dm9000_plat_data anw6410_dm9000_pdata = {
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c
index e20bf5835365..aa1137fb47e6 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
@@ -31,6 +31,7 @@
 #include <linux/spi/spi.h>
 #include <linux/i2c/pca953x.h>
+#include <linux/platform_data/s3c-hsotg.h>
 #include <video/platform_lcd.h>
@@ -61,7 +62,6 @@
 #include <plat/sdhci.h>
 #include <plat/gpio-cfg.h>
 #include <plat/s3c64xx-spi.h>
-#include <plat/udc-hs.h>
 #include <plat/keypad.h>
 #include <plat/clock.h>
@@ -232,21 +232,10 @@ static struct platform_device crag6410_gpio_keydev = {
 };
 static struct resource crag6410_dm9k_resource[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM(S3C64XX_PA_XM0CSN5, 2),
-                .start  = S3C64XX_PA_XM0CSN5,
+        [1] = DEFINE_RES_MEM(S3C64XX_PA_XM0CSN5 + (1 << 8), 2),
-                .end    = S3C64XX_PA_XM0CSN5 + 1,
+        [2] = DEFINE_RES_NAMED(S3C_EINT(17), 1, NULL, IORESOURCE_IRQ \
-                .flags  = IORESOURCE_MEM,
+                                | IORESOURCE_IRQ_HIGHLEVEL),
-        },
-        [1] = {
-                .start  = S3C64XX_PA_XM0CSN5 + (1 << 8),
-                .end    = S3C64XX_PA_XM0CSN5 + (1 << 8) + 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [2] = {
-                .start  = S3C_EINT(17),
-                .end    = S3C_EINT(17),
-                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
-        },
 };
 static struct dm9000_plat_data mini6410_dm9k_pdata = {
@@ -262,12 +251,7 @@ static struct platform_device crag6410_dm9k_device = {
 };
 static struct resource crag6410_mmgpio_resource[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM_NAMED(S3C64XX_PA_XM0CSN4, 1, "dat"),
-                .name   = "dat",
-                .start  = S3C64XX_PA_XM0CSN4 + 1,
-                .end    = S3C64XX_PA_XM0CSN4 + 1,
-                .flags  = IORESOURCE_MEM,
-        },
 };
 static struct platform_device crag6410_mmgpio = {
@@ -306,6 +290,24 @@ static struct regulator_consumer_supply wallvdd_consumers[] = {
        REGULATOR_SUPPLY("SPKVDD2", "1-001a"),
        REGULATOR_SUPPLY("SPKVDDL", "1-001a"),
        REGULATOR_SUPPLY("SPKVDDR", "1-001a"),
+        REGULATOR_SUPPLY("DC1VDD", "0-0034"),
+        REGULATOR_SUPPLY("DC2VDD", "0-0034"),
+        REGULATOR_SUPPLY("DC3VDD", "0-0034"),
+        REGULATOR_SUPPLY("LDO1VDD", "0-0034"),
+        REGULATOR_SUPPLY("LDO2VDD", "0-0034"),
+        REGULATOR_SUPPLY("LDO4VDD", "0-0034"),
+        REGULATOR_SUPPLY("LDO5VDD", "0-0034"),
+        REGULATOR_SUPPLY("LDO6VDD", "0-0034"),
+        REGULATOR_SUPPLY("LDO7VDD", "0-0034"),
+        REGULATOR_SUPPLY("LDO8VDD", "0-0034"),
+        REGULATOR_SUPPLY("LDO9VDD", "0-0034"),
+        REGULATOR_SUPPLY("LDO10VDD", "0-0034"),
+        REGULATOR_SUPPLY("LDO11VDD", "0-0034"),
+        REGULATOR_SUPPLY("DC1VDD", "1-0034"),
+        REGULATOR_SUPPLY("DC2VDD", "1-0034"),
+        REGULATOR_SUPPLY("DC3VDD", "1-0034"),
 };
 static struct regulator_init_data wallvdd_data = {
diff --git a/arch/arm/mach-s3c64xx/mach-mini6410.c b/arch/arm/mach-s3c64xx/mach-mini6410.c
index c34c2ab22ead..b2166d4a5538 100644
--- a/arch/arm/mach-s3c64xx/mach-mini6410.c
+++ b/arch/arm/mach-s3c64xx/mach-mini6410.c
@@ -85,21 +85,10 @@ static struct s3c2410_uartcfg mini6410_uartcfgs[] __initdata = {
 /* DM9000AEP 10/100 ethernet controller */
 static struct resource mini6410_dm9k_resource[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM(S3C64XX_PA_XM0CSN1, 2),
-                .start  = S3C64XX_PA_XM0CSN1,
+        [1] = DEFINE_RES_MEM(S3C64XX_PA_XM0CSN1 + 4, 2),
-                .end    = S3C64XX_PA_XM0CSN1 + 1,
+        [2] = DEFINE_RES_NAMED(S3C_EINT(7), 1, NULL, IORESOURCE_IRQ \
-                .flags  = IORESOURCE_MEM
+                                        | IORESOURCE_IRQ_HIGHLEVEL),
-        },
-        [1] = {
-                .start  = S3C64XX_PA_XM0CSN1 + 4,
-                .end    = S3C64XX_PA_XM0CSN1 + 5,
-                .flags  = IORESOURCE_MEM
-        },
-        [2] = {
-                .start  = S3C_EINT(7),
-                .end    = S3C_EINT(7),
-                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL
-        }
 };
 static struct dm9000_plat_data mini6410_dm9k_pdata = {
diff --git a/arch/arm/mach-s3c64xx/mach-real6410.c b/arch/arm/mach-s3c64xx/mach-real6410.c
index be2a9a22ab74..5c08266cea21 100644
--- a/arch/arm/mach-s3c64xx/mach-real6410.c
+++ b/arch/arm/mach-s3c64xx/mach-real6410.c
@@ -86,21 +86,10 @@ static struct s3c2410_uartcfg real6410_uartcfgs[] __initdata = {
 /* DM9000AEP 10/100 ethernet controller */
 static struct resource real6410_dm9k_resource[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM(S3C64XX_PA_XM0CSN1, 2),
-                .start  = S3C64XX_PA_XM0CSN1,
+        [1] = DEFINE_RES_MEM(S3C64XX_PA_XM0CSN1 + 4, 2),
-                .end    = S3C64XX_PA_XM0CSN1 + 1,
+        [2] = DEFINE_RES_NAMED(S3C_EINT(7), 1, NULL, IORESOURCE_IRQ \
-                .flags  = IORESOURCE_MEM
+                                        | IORESOURCE_IRQ_HIGHLEVEL),
-        },
-        [1] = {
-                .start  = S3C64XX_PA_XM0CSN1 + 4,
-                .end    = S3C64XX_PA_XM0CSN1 + 5,
-                .flags  = IORESOURCE_MEM
-        },
-        [2] = {
-                .start  = S3C_EINT(7),
-                .end    = S3C_EINT(7),
-                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL
-        }
 };
 static struct dm9000_plat_data real6410_dm9k_pdata = {
diff --git a/arch/arm/mach-s3c64xx/mach-smartq.c b/arch/arm/mach-s3c64xx/mach-smartq.c
index ce745e19aa27..ceeb1de40376 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq.c
@@ -18,6 +18,7 @@
 #include <linux/serial_core.h>
 #include <linux/spi/spi_gpio.h>
 #include <linux/usb/gpio_vbus.h>
+#include <linux/platform_data/s3c-hsotg.h>
 #include <asm/mach-types.h>
 #include <asm/mach/map.h>
@@ -33,7 +34,6 @@
 #include <plat/gpio-cfg.h>
 #include <plat/hwmon.h>
 #include <plat/regs-serial.h>
-#include <plat/udc-hs.h>
 #include <plat/usb-control.h>
 #include <plat/sdhci.h>
 #include <plat/ts.h>
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index d55bc96d9582..7da044f738ac 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -30,6 +30,7 @@
 #include <linux/regulator/fixed.h>
 #include <linux/regulator/machine.h>
 #include <linux/pwm_backlight.h>
+#include <linux/platform_data/s3c-hsotg.h>
 #ifdef CONFIG_SMDK6410_WM1190_EV1
 #include <linux/mfd/wm8350/core.h>
@@ -72,7 +73,6 @@
 #include <plat/keypad.h>
 #include <plat/backlight.h>
 #include <plat/regs-fb-v4.h>
-#include <plat/udc-hs.h>
 #include "common.h"
@@ -182,16 +182,9 @@ static struct s3c_fb_platdata smdk6410_lcd_pdata __initdata = {
 */
 static struct resource smdk6410_smsc911x_resources[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM(S3C64XX_PA_XM0CSN1, SZ_64K),
-                .start = S3C64XX_PA_XM0CSN1,
+        [1] = DEFINE_RES_NAMED(S3C_EINT(10), 1, NULL, IORESOURCE_IRQ \
-                .end   = S3C64XX_PA_XM0CSN1 + SZ_64K - 1,
+                                        | IRQ_TYPE_LEVEL_LOW),
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = S3C_EINT(10),
-                .end   = S3C_EINT(10),
-                .flags = IORESOURCE_IRQ | IRQ_TYPE_LEVEL_LOW,
-        },
 };
 static struct smsc911x_platform_config smdk6410_smsc911x_pdata = {
diff --git a/arch/arm/mach-s5p64x0/dev-audio.c b/arch/arm/mach-s5p64x0/dev-audio.c
index 35f1f226dabb..91113ddc51da 100644
--- a/arch/arm/mach-s5p64x0/dev-audio.c
+++ b/arch/arm/mach-s5p64x0/dev-audio.c
@@ -51,21 +51,9 @@ static struct s3c_audio_pdata s5p6440_i2s_pdata = {
 };
 static struct resource s5p64x0_i2s0_resource[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM(S5P64X0_PA_I2S, SZ_256),
-                .start  = S5P64X0_PA_I2S,
+        [1] = DEFINE_RES_DMA(DMACH_I2S0_TX),
-                .end    = S5P64X0_PA_I2S + 0x100 - 1,
+        [2] = DEFINE_RES_DMA(DMACH_I2S0_RX),
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = DMACH_I2S0_TX,
-                .end    = DMACH_I2S0_TX,
-                .flags  = IORESOURCE_DMA,
-        },
-        [2] = {
-                .start  = DMACH_I2S0_RX,
-                .end    = DMACH_I2S0_RX,
-                .flags  = IORESOURCE_DMA,
-        },
 };
 struct platform_device s5p6440_device_iis = {
@@ -130,21 +118,9 @@ static struct s3c_audio_pdata s5p6450_i2s_pdata = {
 };
 static struct resource s5p6450_i2s1_resource[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM(S5P6450_PA_I2S1, SZ_256),
-                .start  = S5P6450_PA_I2S1,
+        [1] = DEFINE_RES_DMA(DMACH_I2S1_TX),
-                .end    = S5P6450_PA_I2S1 + 0x100 - 1,
+        [2] = DEFINE_RES_DMA(DMACH_I2S1_RX),
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = DMACH_I2S1_TX,
-                .end    = DMACH_I2S1_TX,
-                .flags  = IORESOURCE_DMA,
-        },
-        [2] = {
-                .start  = DMACH_I2S1_RX,
-                .end    = DMACH_I2S1_RX,
-                .flags  = IORESOURCE_DMA,
-        },
 };
 struct platform_device s5p6450_device_iis1 = {
@@ -158,21 +134,9 @@ struct platform_device s5p6450_device_iis1 = {
 };
 static struct resource s5p6450_i2s2_resource[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM(S5P6450_PA_I2S2, SZ_256),
-                .start  = S5P6450_PA_I2S2,
+        [1] = DEFINE_RES_DMA(DMACH_I2S2_TX),
-                .end    = S5P6450_PA_I2S2 + 0x100 - 1,
+        [2] = DEFINE_RES_DMA(DMACH_I2S2_RX),
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = DMACH_I2S2_TX,
-                .end    = DMACH_I2S2_TX,
-                .flags  = IORESOURCE_DMA,
-        },
-        [2] = {
-                .start  = DMACH_I2S2_RX,
-                .end    = DMACH_I2S2_RX,
-                .flags  = IORESOURCE_DMA,
-        },
 };
 struct platform_device s5p6450_device_iis2 = {
@@ -208,21 +172,9 @@ static struct s3c_audio_pdata s5p6440_pcm_pdata = {
 };
 static struct resource s5p6440_pcm0_resource[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM(S5P64X0_PA_PCM, SZ_256),
-                .start  = S5P64X0_PA_PCM,
+        [1] = DEFINE_RES_DMA(DMACH_PCM0_TX),
-                .end    = S5P64X0_PA_PCM + 0x100 - 1,
+        [2] = DEFINE_RES_DMA(DMACH_PCM0_RX),
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = DMACH_PCM0_TX,
-                .end    = DMACH_PCM0_TX,
-                .flags  = IORESOURCE_DMA,
-        },
-        [2] = {
-                .start  = DMACH_PCM0_RX,
-                .end    = DMACH_PCM0_RX,
-                .flags  = IORESOURCE_DMA,
-        },
 };
 struct platform_device s5p6440_device_pcm = {
diff --git a/arch/arm/mach-s5pc100/dev-audio.c b/arch/arm/mach-s5pc100/dev-audio.c
index ab2d27172cbc..9d4bde3f1110 100644
--- a/arch/arm/mach-s5pc100/dev-audio.c
+++ b/arch/arm/mach-s5pc100/dev-audio.c
@@ -56,26 +56,10 @@ static struct s3c_audio_pdata i2sv5_pdata = {
 };
 static struct resource s5pc100_iis0_resource[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM(S5PC100_PA_I2S0, SZ_256),
-                .start = S5PC100_PA_I2S0,
+        [1] = DEFINE_RES_DMA(DMACH_I2S0_TX),
-                .end   = S5PC100_PA_I2S0 + 0x100 - 1,
+        [2] = DEFINE_RES_DMA(DMACH_I2S0_RX),
-                .flags = IORESOURCE_MEM,
+        [3] = DEFINE_RES_DMA(DMACH_I2S0S_TX),
-        },
-        [1] = {
-                .start = DMACH_I2S0_TX,
-                .end   = DMACH_I2S0_TX,
-                .flags = IORESOURCE_DMA,
-        },
-        [2] = {
-                .start = DMACH_I2S0_RX,
-                .end   = DMACH_I2S0_RX,
-                .flags = IORESOURCE_DMA,
-        },
-        [3] = {
-                .start = DMACH_I2S0S_TX,
-                .end = DMACH_I2S0S_TX,
-                .flags = IORESOURCE_DMA,
-        },
 };
 struct platform_device s5pc100_device_iis0 = {
@@ -103,21 +87,9 @@ static struct s3c_audio_pdata i2sv3_pdata = {
 };
 static struct resource s5pc100_iis1_resource[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM(S5PC100_PA_I2S1, SZ_256),
-                .start = S5PC100_PA_I2S1,
+        [1] = DEFINE_RES_DMA(DMACH_I2S1_TX),
-                .end   = S5PC100_PA_I2S1 + 0x100 - 1,
+        [2] = DEFINE_RES_DMA(DMACH_I2S1_RX),
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = DMACH_I2S1_TX,
-                .end   = DMACH_I2S1_TX,
-                .flags = IORESOURCE_DMA,
-        },
-        [2] = {
-                .start = DMACH_I2S1_RX,
-                .end   = DMACH_I2S1_RX,
-                .flags = IORESOURCE_DMA,
-        },
 };
 struct platform_device s5pc100_device_iis1 = {
@@ -131,21 +103,9 @@ struct platform_device s5pc100_device_iis1 = {
 };
 static struct resource s5pc100_iis2_resource[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM(S5PC100_PA_I2S2, SZ_256),
-                .start = S5PC100_PA_I2S2,
+        [1] = DEFINE_RES_DMA(DMACH_I2S2_TX),
-                .end   = S5PC100_PA_I2S2 + 0x100 - 1,
+        [2] = DEFINE_RES_DMA(DMACH_I2S2_RX),
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = DMACH_I2S2_TX,
-                .end   = DMACH_I2S2_TX,
-                .flags = IORESOURCE_DMA,
-        },
-        [2] = {
-                .start = DMACH_I2S2_RX,
-                .end   = DMACH_I2S2_RX,
-                .flags = IORESOURCE_DMA,
-        },
 };
 struct platform_device s5pc100_device_iis2 = {
@@ -184,21 +144,9 @@ static struct s3c_audio_pdata s3c_pcm_pdata = {
 };
 static struct resource s5pc100_pcm0_resource[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM(S5PC100_PA_PCM0, SZ_256),
-                .start = S5PC100_PA_PCM0,
+        [1] = DEFINE_RES_DMA(DMACH_PCM0_TX),
-                .end   = S5PC100_PA_PCM0 + 0x100 - 1,
+        [2] = DEFINE_RES_DMA(DMACH_PCM0_RX),
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = DMACH_PCM0_TX,
-                .end   = DMACH_PCM0_TX,
-                .flags = IORESOURCE_DMA,
-        },
-        [2] = {
-                .start = DMACH_PCM0_RX,
-                .end   = DMACH_PCM0_RX,
-                .flags = IORESOURCE_DMA,
-        },
 };
 struct platform_device s5pc100_device_pcm0 = {
@@ -212,21 +160,9 @@ struct platform_device s5pc100_device_pcm0 = {
 };
 static struct resource s5pc100_pcm1_resource[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM(S5PC100_PA_PCM1, SZ_256),
-                .start = S5PC100_PA_PCM1,
+        [1] = DEFINE_RES_DMA(DMACH_PCM1_TX),
-                .end   = S5PC100_PA_PCM1 + 0x100 - 1,
+        [2] = DEFINE_RES_DMA(DMACH_PCM1_RX),
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = DMACH_PCM1_TX,
-                .end   = DMACH_PCM1_TX,
-                .flags = IORESOURCE_DMA,
-        },
-        [2] = {
-                .start = DMACH_PCM1_RX,
-                .end   = DMACH_PCM1_RX,
-                .flags = IORESOURCE_DMA,
-        },
 };
 struct platform_device s5pc100_device_pcm1 = {
@@ -247,31 +183,11 @@ static int s5pc100_ac97_cfg_gpio(struct platform_device *pdev)
 }
 static struct resource s5pc100_ac97_resource[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM(S5PC100_PA_AC97, SZ_256),
-                .start = S5PC100_PA_AC97,
+        [1] = DEFINE_RES_DMA(DMACH_AC97_PCMOUT),
-                .end   = S5PC100_PA_AC97 + 0x100 - 1,
+        [2] = DEFINE_RES_DMA(DMACH_AC97_PCMIN),
-                .flags = IORESOURCE_MEM,
+        [3] = DEFINE_RES_DMA(DMACH_AC97_MICIN),
-        },
+        [4] = DEFINE_RES_IRQ(IRQ_AC97),
-        [1] = {
-                .start = DMACH_AC97_PCMOUT,
-                .end   = DMACH_AC97_PCMOUT,
-                .flags = IORESOURCE_DMA,
-        },
-        [2] = {
-                .start = DMACH_AC97_PCMIN,
-                .end   = DMACH_AC97_PCMIN,
-                .flags = IORESOURCE_DMA,
-        },
-        [3] = {
-                .start = DMACH_AC97_MICIN,
-                .end   = DMACH_AC97_MICIN,
-                .flags = IORESOURCE_DMA,
-        },
-        [4] = {
-                .start = IRQ_AC97,
-                .end   = IRQ_AC97,
-                .flags = IORESOURCE_IRQ,
-        },
 };
 static struct s3c_audio_pdata s3c_ac97_pdata = {
@@ -308,16 +224,8 @@ static int s5pc100_spdif_cfg_gpg3(struct platform_device *pdev)
 }
 static struct resource s5pc100_spdif_resource[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM(S5PC100_PA_SPDIF, SZ_256),
-                .start  = S5PC100_PA_SPDIF,
+        [1] = DEFINE_RES_DMA(DMACH_SPDIF),
-                .end    = S5PC100_PA_SPDIF + 0x100 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = DMACH_SPDIF,
-                .end    = DMACH_SPDIF,
-                .flags  = IORESOURCE_DMA,
-        },
 };
 static struct s3c_audio_pdata s5p_spdif_pdata = {
diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index 29594fc4fdf4..88e983b0c82e 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -85,6 +85,7 @@ config MACH_AQUILA
        select S5P_DEV_ONENAND
        select S5PV210_SETUP_FB_24BPP
        select S5PV210_SETUP_SDHCI
+        select S5PV210_SETUP_USB_PHY
        help
          Machine support for the Samsung Aquila target based on S5PC110 SoC
diff --git a/arch/arm/mach-s5pv210/dev-audio.c b/arch/arm/mach-s5pv210/dev-audio.c
index 63f5d82004b5..8367749c3eec 100644
--- a/arch/arm/mach-s5pv210/dev-audio.c
+++ b/arch/arm/mach-s5pv210/dev-audio.c
@@ -59,26 +59,10 @@ static struct s3c_audio_pdata i2sv5_pdata = {
 };
 static struct resource s5pv210_iis0_resource[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM(S5PV210_PA_IIS0, SZ_256),
-                .start = S5PV210_PA_IIS0,
+        [1] = DEFINE_RES_DMA(DMACH_I2S0_TX),
-                .end   = S5PV210_PA_IIS0 + 0x100 - 1,
+        [2] = DEFINE_RES_DMA(DMACH_I2S0_RX),
-                .flags = IORESOURCE_MEM,
+        [3] = DEFINE_RES_DMA(DMACH_I2S0S_TX),
-        },
-        [1] = {
-                .start = DMACH_I2S0_TX,
-                .end   = DMACH_I2S0_TX,
-                .flags = IORESOURCE_DMA,
-        },
-        [2] = {
-                .start = DMACH_I2S0_RX,
-                .end   = DMACH_I2S0_RX,
-                .flags = IORESOURCE_DMA,
-        },
-        [3] = {
-                .start = DMACH_I2S0S_TX,
-                .end = DMACH_I2S0S_TX,
-                .flags = IORESOURCE_DMA,
-        },
 };
 struct platform_device s5pv210_device_iis0 = {
@@ -106,21 +90,9 @@ static struct s3c_audio_pdata i2sv3_pdata = {
 };
 static struct resource s5pv210_iis1_resource[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM(S5PV210_PA_IIS1, SZ_256),
-                .start = S5PV210_PA_IIS1,
+        [1] = DEFINE_RES_DMA(DMACH_I2S1_TX),
-                .end   = S5PV210_PA_IIS1 + 0x100 - 1,
+        [2] = DEFINE_RES_DMA(DMACH_I2S1_RX),
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = DMACH_I2S1_TX,
-                .end   = DMACH_I2S1_TX,
-                .flags = IORESOURCE_DMA,
-        },
-        [2] = {
-                .start = DMACH_I2S1_RX,
-                .end   = DMACH_I2S1_RX,
-                .flags = IORESOURCE_DMA,
-        },
 };
 struct platform_device s5pv210_device_iis1 = {
@@ -134,21 +106,9 @@ struct platform_device s5pv210_device_iis1 = {
 };
 static struct resource s5pv210_iis2_resource[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM(S5PV210_PA_IIS2, SZ_256),
-                .start = S5PV210_PA_IIS2,
+        [1] = DEFINE_RES_DMA(DMACH_I2S2_TX),
-                .end   = S5PV210_PA_IIS2 + 0x100 - 1,
+        [2] = DEFINE_RES_DMA(DMACH_I2S2_RX),
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = DMACH_I2S2_TX,
-                .end   = DMACH_I2S2_TX,
-                .flags = IORESOURCE_DMA,
-        },
-        [2] = {
-                .start = DMACH_I2S2_RX,
-                .end   = DMACH_I2S2_RX,
-                .flags = IORESOURCE_DMA,
-        },
 };
 struct platform_device s5pv210_device_iis2 = {
@@ -188,21 +148,9 @@ static struct s3c_audio_pdata s3c_pcm_pdata = {
 };
 static struct resource s5pv210_pcm0_resource[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM(S5PV210_PA_PCM0, SZ_256),
-                .start = S5PV210_PA_PCM0,
+        [1] = DEFINE_RES_DMA(DMACH_PCM0_TX),
-                .end   = S5PV210_PA_PCM0 + 0x100 - 1,
+        [2] = DEFINE_RES_DMA(DMACH_PCM0_RX),
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = DMACH_PCM0_TX,
-                .end   = DMACH_PCM0_TX,
-                .flags = IORESOURCE_DMA,
-        },
-        [2] = {
-                .start = DMACH_PCM0_RX,
-                .end   = DMACH_PCM0_RX,
-                .flags = IORESOURCE_DMA,
-        },
 };
 struct platform_device s5pv210_device_pcm0 = {
@@ -216,21 +164,9 @@ struct platform_device s5pv210_device_pcm0 = {
 };
 static struct resource s5pv210_pcm1_resource[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM(S5PV210_PA_PCM1, SZ_256),
-                .start = S5PV210_PA_PCM1,
+        [1] = DEFINE_RES_DMA(DMACH_PCM1_TX),
-                .end   = S5PV210_PA_PCM1 + 0x100 - 1,
+        [2] = DEFINE_RES_DMA(DMACH_PCM1_RX),
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = DMACH_PCM1_TX,
-                .end   = DMACH_PCM1_TX,
-                .flags = IORESOURCE_DMA,
-        },
-        [2] = {
-                .start = DMACH_PCM1_RX,
-                .end   = DMACH_PCM1_RX,
-                .flags = IORESOURCE_DMA,
-        },
 };
 struct platform_device s5pv210_device_pcm1 = {
@@ -244,21 +180,9 @@ struct platform_device s5pv210_device_pcm1 = {
 };
 static struct resource s5pv210_pcm2_resource[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM(S5PV210_PA_PCM2, SZ_256),
-                .start = S5PV210_PA_PCM2,
+        [1] = DEFINE_RES_DMA(DMACH_PCM2_TX),
-                .end   = S5PV210_PA_PCM2 + 0x100 - 1,
+        [2] = DEFINE_RES_DMA(DMACH_PCM2_RX),
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = DMACH_PCM2_TX,
-                .end   = DMACH_PCM2_TX,
-                .flags = IORESOURCE_DMA,
-        },
-        [2] = {
-                .start = DMACH_PCM2_RX,
-                .end   = DMACH_PCM2_RX,
-                .flags = IORESOURCE_DMA,
-        },
 };
 struct platform_device s5pv210_device_pcm2 = {
@@ -279,31 +203,11 @@ static int s5pv210_ac97_cfg_gpio(struct platform_device *pdev)
 }
 static struct resource s5pv210_ac97_resource[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM(S5PV210_PA_AC97, SZ_256),
-                .start = S5PV210_PA_AC97,
+        [1] = DEFINE_RES_DMA(DMACH_AC97_PCMOUT),
-                .end   = S5PV210_PA_AC97 + 0x100 - 1,
+        [2] = DEFINE_RES_DMA(DMACH_AC97_PCMIN),
-                .flags = IORESOURCE_MEM,
+        [3] = DEFINE_RES_DMA(DMACH_AC97_MICIN),
-        },
+        [4] = DEFINE_RES_IRQ(IRQ_AC97),
-        [1] = {
-                .start = DMACH_AC97_PCMOUT,
-                .end   = DMACH_AC97_PCMOUT,
-                .flags = IORESOURCE_DMA,
-        },
-        [2] = {
-                .start = DMACH_AC97_PCMIN,
-                .end   = DMACH_AC97_PCMIN,
-                .flags = IORESOURCE_DMA,
-        },
-        [3] = {
-                .start = DMACH_AC97_MICIN,
-                .end   = DMACH_AC97_MICIN,
-                .flags = IORESOURCE_DMA,
-        },
-        [4] = {
-                .start = IRQ_AC97,
-                .end   = IRQ_AC97,
-                .flags = IORESOURCE_IRQ,
-        },
 };
 static struct s3c_audio_pdata s3c_ac97_pdata = {
@@ -334,16 +238,8 @@ static int s5pv210_spdif_cfg_gpio(struct platform_device *pdev)
 }
 static struct resource s5pv210_spdif_resource[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM(S5PV210_PA_SPDIF, SZ_256),
-                .start  = S5PV210_PA_SPDIF,
+        [1] = DEFINE_RES_DMA(DMACH_SPDIF),
-                .end    = S5PV210_PA_SPDIF + 0x100 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = DMACH_SPDIF,
-                .end    = DMACH_SPDIF,
-                .flags  = IORESOURCE_DMA,
-        },
 };
 static struct s3c_audio_pdata samsung_spdif_pdata = {
diff --git a/arch/arm/mach-s5pv210/dma.c b/arch/arm/mach-s5pv210/dma.c
index 86ce62f66190..b8337e248b09 100644
--- a/arch/arm/mach-s5pv210/dma.c
+++ b/arch/arm/mach-s5pv210/dma.c
@@ -33,8 +33,6 @@
 #include <mach/irqs.h>
 #include <mach/dma.h>
-static u64 dma_dmamask = DMA_BIT_MASK(32);
 static u8 pdma0_peri[] = {
        DMACH_UART0_RX,
        DMACH_UART0_TX,
diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c
index a9ea64e0da0d..48d018f2332b 100644
--- a/arch/arm/mach-s5pv210/mach-aquila.c
+++ b/arch/arm/mach-s5pv210/mach-aquila.c
@@ -484,8 +484,8 @@ static struct wm8994_pdata wm8994_platform_data = {
        .gpio_defaults[8] = 0x0100,
        .gpio_defaults[9] = 0x0100,
        .gpio_defaults[10] = 0x0100,
-        .ldo[0] = { S5PV210_MP03(6), NULL, &wm8994_ldo1_data }, /* XM0FRNB_2 */
+        .ldo[0] = { S5PV210_MP03(6), &wm8994_ldo1_data },       /* XM0FRNB_2 */
-        .ldo[1] = { 0, NULL, &wm8994_ldo2_data },
+        .ldo[1] = { 0, &wm8994_ldo2_data },
 };
 /* GPIO I2C PMIC */
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
index 2cf5ed75f390..f20a97c8e411 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -25,7 +25,9 @@
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
 #include <linux/gpio.h>
+#include <linux/mmc/host.h>
 #include <linux/interrupt.h>
+#include <linux/platform_data/s3c-hsotg.h>
 #include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
@@ -277,6 +279,9 @@ static void __init goni_tsp_init(void)
        i2c2_devs[0].irq = gpio_to_irq(gpio);
 }
+/* USB OTG */
+static struct s3c_hsotg_plat goni_hsotg_pdata;
 static void goni_camera_init(void)
 {
        s5pv210_fimc_setup_gpio(S5P_CAMPORT_A);
@@ -674,8 +679,8 @@ static struct wm8994_pdata wm8994_platform_data = {
        .gpio_defaults[8] = 0x0100,
        .gpio_defaults[9] = 0x0100,
        .gpio_defaults[10] = 0x0100,
-        .ldo[0] = { S5PV210_MP03(6), NULL, &wm8994_ldo1_data }, /* XM0FRNB_2 */
+        .ldo[0] = { S5PV210_MP03(6), &wm8994_ldo1_data },       /* XM0FRNB_2 */
-        .ldo[1] = { 0, NULL, &wm8994_ldo2_data },
+        .ldo[1] = { 0, &wm8994_ldo2_data },
 };
 /* GPIO I2C PMIC */
@@ -765,6 +770,7 @@ static void __init goni_pmic_init(void)
 /* MoviNAND */
 static struct s3c_sdhci_platdata goni_hsmmc0_data __initdata = {
        .max_width              = 4,
+        .host_caps2             = MMC_CAP2_BROKEN_VOLTAGE,
        .cd_type                = S3C_SDHCI_CD_PERMANENT,
 };
@@ -939,6 +945,8 @@ static void __init goni_machine_init(void)
        s3c_set_platdata(&goni_fimc_md_platdata, sizeof(goni_fimc_md_platdata),
                         &s5p_device_fimc_md);
+        s3c_hsotg_set_platdata(&goni_hsotg_pdata);
        goni_camera_init();
        /* SPI */
diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
index 91d4ad8bcc73..fa1b61209fd9 100644
--- a/arch/arm/mach-s5pv210/mach-smdkv210.c
+++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
@@ -119,21 +119,10 @@ static struct samsung_keypad_platdata smdkv210_keypad_data __initdata = {
 };
 static struct resource smdkv210_dm9000_resources[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM(S5PV210_PA_SROM_BANK5, 1),
-                .start  = S5PV210_PA_SROM_BANK5,
+        [1] = DEFINE_RES_MEM(S5PV210_PA_SROM_BANK5 + 2, 1),
-                .end    = S5PV210_PA_SROM_BANK5,
+        [2] = DEFINE_RES_NAMED(IRQ_EINT(9), 1, NULL, IORESOURCE_IRQ \
-                .flags  = IORESOURCE_MEM,
+                                | IORESOURCE_IRQ_HIGHLEVEL),
-        },
-        [1] = {
-                .start  = S5PV210_PA_SROM_BANK5 + 2,
-                .end    = S5PV210_PA_SROM_BANK5 + 2,
-                .flags  = IORESOURCE_MEM,
-        },
-        [2] = {
-                .start  = IRQ_EINT(9),
-                .end    = IRQ_EINT(9),
-                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
-        },
 };
 static struct dm9000_plat_data smdkv210_dm9000_platdata = {
diff --git a/arch/arm/mach-sa1100/generic.c b/arch/arm/mach-sa1100/generic.c
index 7c524b4e415d..16be4c56abe3 100644
--- a/arch/arm/mach-sa1100/generic.c
+++ b/arch/arm/mach-sa1100/generic.c
@@ -306,7 +306,7 @@ void sa11x0_register_irda(struct irda_platform_data *irda)
 }
 static struct resource sa1100_rtc_resources[] = {
-        DEFINE_RES_MEM(0x90010000, 0x9001003f),
+        DEFINE_RES_MEM(0x90010000, 0x40),
        DEFINE_RES_IRQ_NAMED(IRQ_RTC1Hz, "rtc 1Hz"),
        DEFINE_RES_IRQ_NAMED(IRQ_RTCAlrm, "rtc alarm"),
 };
diff --git a/arch/arm/mach-sa1100/pci-nanoengine.c b/arch/arm/mach-sa1100/pci-nanoengine.c
index b49108b890a8..ff02e2da99f2 100644
--- a/arch/arm/mach-sa1100/pci-nanoengine.c
+++ b/arch/arm/mach-sa1100/pci-nanoengine.c
@@ -129,12 +129,6 @@ static int __init pci_nanoengine_map_irq(const struct pci_dev *dev, u8 slot,
        return NANOENGINE_IRQ_GPIO_PCI;
 }
-struct pci_bus * __init pci_nanoengine_scan_bus(int nr, struct pci_sys_data *sys)
-{
-        return pci_scan_root_bus(NULL, sys->busnr, &pci_nano_ops, sys,
-                                 &sys->resources);
-}
 static struct resource pci_io_ports =
        DEFINE_RES_IO_NAMED(0x400, 0x400, "PCI IO");
@@ -274,7 +268,7 @@ int __init pci_nanoengine_setup(int nr, struct pci_sys_data *sys)
 static struct hw_pci nanoengine_pci __initdata = {
        .map_irq                = pci_nanoengine_map_irq,
        .nr_controllers         = 1,
-        .scan                   = pci_nanoengine_scan_bus,
+        .ops                    = &pci_nano_ops,
        .setup                  = pci_nanoengine_setup,
 };
diff --git a/arch/arm/mach-shark/pci.c b/arch/arm/mach-shark/pci.c
index 7cb79a092f31..9089407d5326 100644
--- a/arch/arm/mach-shark/pci.c
+++ b/arch/arm/mach-shark/pci.c
@@ -29,10 +29,9 @@ extern void __init via82c505_preinit(void);
 static struct hw_pci shark_pci __initdata = {
        .setup          = via82c505_setup,
-        .swizzle        = pci_std_swizzle,
        .map_irq        = shark_map_irq,
        .nr_controllers = 1,
-        .scan           = via82c505_scan_bus,
+        .ops            = &via82c505_ops,
        .preinit        = via82c505_preinit,
 };
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 34560cab45d9..98327b7a503c 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -41,6 +41,12 @@ config ARCH_R8A7779
        select ARM_GIC
        select ARCH_WANT_OPTIONAL_GPIOLIB
+config ARCH_EMEV2
+        bool "Emma Mobile EV2"
+        select CPU_V7
+        select ARM_GIC
+        select ARCH_WANT_OPTIONAL_GPIOLIB
 comment "SH-Mobile Board Type"
 config MACH_G3EVM
@@ -93,11 +99,28 @@ config MACH_BONITO
        select ARCH_REQUIRE_GPIOLIB
        depends on ARCH_R8A7740
+config MACH_ARMADILLO800EVA
+        bool "Armadillo-800 EVA board"
+        depends on ARCH_R8A7740
+        select ARCH_REQUIRE_GPIOLIB
+        select USE_OF
 config MACH_MARZEN
        bool "MARZEN board"
        depends on ARCH_R8A7779
        select ARCH_REQUIRE_GPIOLIB
+config MACH_KZM9D
+        bool "KZM9D board"
+        depends on ARCH_EMEV2
+        select USE_OF
+config MACH_KZM9G
+        bool "KZM-A9-GT board"
+        depends on ARCH_SH73A0
+        select ARCH_REQUIRE_GPIOLIB
+        select USE_OF
 comment "SH-Mobile System Configuration"
 config CPU_HAS_INTEVT
@@ -110,7 +133,8 @@ config MEMORY_START
        hex "Physical memory start address"
        default "0x50000000" if MACH_G3EVM
        default "0x40000000" if MACH_G4EVM || MACH_AP4EVB || MACH_AG5EVM || \
-                                MACH_MACKEREL || MACH_BONITO
+                                MACH_MACKEREL || MACH_BONITO || \
+                                MACH_ARMADILLO800EVA
        default "0x41000000" if MACH_KOTA2
        default "0x00000000"
        ---help---
@@ -122,7 +146,8 @@ config MEMORY_SIZE
        hex "Physical memory size"
        default "0x08000000" if MACH_G3EVM
        default "0x08000000" if MACH_G4EVM
-        default "0x20000000" if MACH_AG5EVM || MACH_BONITO
+        default "0x20000000" if MACH_AG5EVM || MACH_BONITO || \
+                                MACH_ARMADILLO800EVA
        default "0x1e000000" if MACH_KOTA2
        default "0x10000000" if MACH_AP4EVB || MACH_MACKEREL
        default "0x04000000"
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index e7c2590b75d9..e6b177bc9410 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -12,12 +12,14 @@ obj-$(CONFIG_ARCH_SH7372)	+= setup-sh7372.o clock-sh7372.o intc-sh7372.o
 obj-$(CONFIG_ARCH_SH73A0)       += setup-sh73a0.o clock-sh73a0.o intc-sh73a0.o
 obj-$(CONFIG_ARCH_R8A7740)      += setup-r8a7740.o clock-r8a7740.o intc-r8a7740.o
 obj-$(CONFIG_ARCH_R8A7779)      += setup-r8a7779.o clock-r8a7779.o intc-r8a7779.o
+obj-$(CONFIG_ARCH_EMEV2)        += setup-emev2.o clock-emev2.o
 # SMP objects
 smp-y                           := platsmp.o headsmp.o
 smp-$(CONFIG_HOTPLUG_CPU)       += hotplug.o
 smp-$(CONFIG_ARCH_SH73A0)       += smp-sh73a0.o
 smp-$(CONFIG_ARCH_R8A7779)      += smp-r8a7779.o
+smp-$(CONFIG_ARCH_EMEV2)        += smp-emev2.o
 # Pinmux setup
 pfc-y                           :=
@@ -49,6 +51,9 @@ obj-$(CONFIG_MACH_MACKEREL)	+= board-mackerel.o
 obj-$(CONFIG_MACH_KOTA2)        += board-kota2.o
 obj-$(CONFIG_MACH_BONITO)       += board-bonito.o
 obj-$(CONFIG_MACH_MARZEN)       += board-marzen.o
+obj-$(CONFIG_MACH_ARMADILLO800EVA)      += board-armadillo800eva.o
+obj-$(CONFIG_MACH_KZM9D)        += board-kzm9d.o
+obj-$(CONFIG_MACH_KZM9G)        += board-kzm9g.o
 # Framework support
 obj-$(CONFIG_SMP)               += $(smp-y)
diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c
index cb224a344af0..0891ec6e27f5 100644
--- a/arch/arm/mach-shmobile/board-ag5evm.c
+++ b/arch/arm/mach-shmobile/board-ag5evm.c
@@ -365,23 +365,13 @@ static struct platform_device mipidsi0_device = {
 };
 /* SDHI0 */
-static irqreturn_t ag5evm_sdhi0_gpio_cd(int irq, void *arg)
-{
-        struct device *dev = arg;
-        struct sh_mobile_sdhi_info *info = dev->platform_data;
-        struct tmio_mmc_data *pdata = info->pdata;
-        tmio_mmc_cd_wakeup(pdata);
-        return IRQ_HANDLED;
-}
 static struct sh_mobile_sdhi_info sdhi0_info = {
        .dma_slave_tx   = SHDMA_SLAVE_SDHI0_TX,
        .dma_slave_rx   = SHDMA_SLAVE_SDHI0_RX,
-        .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT,
+        .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD,
        .tmio_caps      = MMC_CAP_SD_HIGHSPEED,
        .tmio_ocr_mask  = MMC_VDD_27_28 | MMC_VDD_28_29,
+        .cd_gpio        = GPIO_PORT251,
 };
 static struct resource sdhi0_resources[] = {
@@ -557,7 +547,6 @@ static void __init ag5evm_init(void)
        lcd_backlight_reset();
        /* enable SDHI0 on CN15 [SD I/F] */
-        gpio_request(GPIO_FN_SDHICD0, NULL);
        gpio_request(GPIO_FN_SDHIWP0, NULL);
        gpio_request(GPIO_FN_SDHICMD0, NULL);
        gpio_request(GPIO_FN_SDHICLK0, NULL);
@@ -566,13 +555,6 @@ static void __init ag5evm_init(void)
        gpio_request(GPIO_FN_SDHID0_1, NULL);
        gpio_request(GPIO_FN_SDHID0_0, NULL);
-        if (!request_irq(intcs_evt2irq(0x3c0), ag5evm_sdhi0_gpio_cd,
-                         IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
-                         "sdhi0 cd", &sdhi0_device.dev))
-                sdhi0_info.tmio_flags |= TMIO_MMC_HAS_COLD_CD;
-        else
-                pr_warn("Unable to setup SDHI0 GPIO IRQ\n");
        /* enable SDHI1 on CN4 [WLAN I/F] */
        gpio_request(GPIO_FN_SDHICLK1, NULL);
        gpio_request(GPIO_FN_SDHICMD1_PU, NULL);
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index b56dde2732bb..0c3caeba2f3e 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -997,6 +997,8 @@ static struct sh_mobile_ceu_companion csi2 = {
 static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
        .flags = SH_CEU_FLAG_USE_8BIT_BUS,
+        .max_width = 8188,
+        .max_height = 8188,
        .csi2 = &csi2,
 };
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c
new file mode 100644
index 000000000000..9e37026ef9dd
--- /dev/null
+++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -0,0 +1,784 @@
+/*
+ * armadillo 800 eva board support
+ *
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ *
+ */
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/kernel.h>
+#include <linux/input.h>
+#include <linux/irq.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/gpio_keys.h>
+#include <linux/sh_eth.h>
+#include <linux/videodev2.h>
+#include <linux/usb/renesas_usbhs.h>
+#include <linux/mfd/tmio.h>
+#include <linux/mmc/host.h>
+#include <linux/mmc/sh_mmcif.h>
+#include <linux/mmc/sh_mobile_sdhi.h>
+#include <mach/common.h>
+#include <mach/irqs.h>
+#include <asm/page.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/time.h>
+#include <asm/hardware/cache-l2x0.h>
+#include <mach/r8a7740.h>
+#include <video/sh_mobile_lcdc.h>
+/*
+ * CON1         Camera Module
+ * CON2         Extension Bus
+ * CON3         HDMI Output
+ * CON4         Composite Video Output
+ * CON5         H-UDI JTAG
+ * CON6         ARM JTAG
+ * CON7         SD1
+ * CON8         SD2
+ * CON9         RTC BackUp
+ * CON10        Monaural Mic Input
+ * CON11        Stereo Headphone Output
+ * CON12        Audio Line Output(L)
+ * CON13        Audio Line Output(R)
+ * CON14        AWL13 Module
+ * CON15        Extension
+ * CON16        LCD1
+ * CON17        LCD2
+ * CON19        Power Input
+ * CON20        USB1
+ * CON21        USB2
+ * CON22        Serial
+ * CON23        LAN
+ * CON24        USB3
+ * LED1         Camera LED(Yellow)
+ * LED2         Power LED (Green)
+ * ED3-LED6     User LED(Yellow)
+ * LED7         LAN link LED(Green)
+ * LED8         LAN activity LED(Yellow)
+ */
+/*
+ * DipSwitch
+ *
+ *                    SW1
+ *
+ * -12345678-+---------------+----------------------------
+ *  1        | boot          | hermit
+ *  0        | boot          | OS auto boot
+ * -12345678-+---------------+----------------------------
+ *   00      | boot device   | eMMC
+ *   10      | boot device   | SDHI0 (CON7)
+ *   01      | boot device   | -
+ *   11      | boot device   | Extension Buss (CS0)
+ * -12345678-+---------------+----------------------------
+ *     0     | Extension Bus | D8-D15 disable, eMMC enable
+ *     1     | Extension Bus | D8-D15 enable,  eMMC disable
+ * -12345678-+---------------+----------------------------
+ *      0    | SDHI1         | COM8 disable, COM14 enable
+ *      1    | SDHI1         | COM8 enable,  COM14 disable
+ * -12345678-+---------------+----------------------------
+ *       0   | USB0          | COM20 enable,  COM24 disable
+ *       1   | USB0          | COM20 disable, COM24 enable
+ * -12345678-+---------------+----------------------------
+ *        00 | JTAG          | SH-X2
+ *        10 | JTAG          | ARM
+ *        01 | JTAG          | -
+ *        11 | JTAG          | Boundary Scan
+ *-----------+---------------+----------------------------
+ */
+/*
+ * USB function
+ *
+ * When you use USB Function,
+ * set SW1.6 ON, and connect cable to CN24.
+ *
+ * USBF needs workaround on R8A7740 chip.
+ * These are a little bit complex.
+ * see
+ *      usbhsf_power_ctrl()
+ *
+ * CAUTION
+ *
+ * It uses autonomy mode for USB hotplug at this point
+ * (= usbhs_private.platform_callback.get_vbus is NULL),
+ * since we don't know what's happen on PM control
+ * on this workaround.
+ */
+#define USBCR1          0xe605810a
+#define USBH            0xC6700000
+#define USBH_USBCTR     0x10834
+struct usbhsf_private {
+        struct clk *phy;
+        struct clk *usb24;
+        struct clk *pci;
+        struct clk *func;
+        struct clk *host;
+        void __iomem *usbh_base;
+        struct renesas_usbhs_platform_info info;
+};
+#define usbhsf_get_priv(pdev)                           \
+        container_of(renesas_usbhs_get_info(pdev),      \
+                     struct usbhsf_private, info)
+static int usbhsf_get_id(struct platform_device *pdev)
+{
+        return USBHS_GADGET;
+}
+static void usbhsf_power_ctrl(struct platform_device *pdev,
+                              void __iomem *base, int enable)
+{
+        struct usbhsf_private *priv = usbhsf_get_priv(pdev);
+        /*
+         * Work around for USB Function.
+         * It needs USB host clock, and settings
+         */
+        if (enable) {
+                /*
+                 * enable all the related usb clocks
+                 * for usb workaround
+                 */
+                clk_enable(priv->usb24);
+                clk_enable(priv->pci);
+                clk_enable(priv->host);
+                clk_enable(priv->func);
+                clk_enable(priv->phy);
+                /*
+                 * set USBCR1
+                 *
+                 * Port1 is driven by USB function,
+                 * Port2 is driven by USB HOST
+                 * One HOST (Port1 or Port2 is HOST)
+                 * USB PLL input clock = 24MHz
+                 */
+                __raw_writew(0xd750, USBCR1);
+                mdelay(1);
+                /*
+                 * start USB Host
+                 */
+                __raw_writel(0x0000000c, priv->usbh_base + USBH_USBCTR);
+                __raw_writel(0x00000008, priv->usbh_base + USBH_USBCTR);
+                mdelay(10);
+                /*
+                 * USB PHY Power ON
+                 */
+                __raw_writew(0xd770, USBCR1);
+                __raw_writew(0x4000, base + 0x102); /* USBF :: SUSPMODE */
+        } else {
+                __raw_writel(0x0000010f, priv->usbh_base + USBH_USBCTR);
+                __raw_writew(0xd7c0, USBCR1); /* GPIO */
+                clk_disable(priv->phy);
+                clk_disable(priv->func);        /* usb work around */
+                clk_disable(priv->host);        /* usb work around */
+                clk_disable(priv->pci);         /* usb work around */
+                clk_disable(priv->usb24);       /* usb work around */
+        }
+}
+static void usbhsf_hardware_exit(struct platform_device *pdev)
+{
+        struct usbhsf_private *priv = usbhsf_get_priv(pdev);
+        if (!IS_ERR(priv->phy))
+                clk_put(priv->phy);
+        if (!IS_ERR(priv->usb24))
+                clk_put(priv->usb24);
+        if (!IS_ERR(priv->pci))
+                clk_put(priv->pci);
+        if (!IS_ERR(priv->host))
+                clk_put(priv->host);
+        if (!IS_ERR(priv->func))
+                clk_put(priv->func);
+        if (priv->usbh_base)
+                iounmap(priv->usbh_base);
+        priv->phy       = NULL;
+        priv->usb24     = NULL;
+        priv->pci       = NULL;
+        priv->host      = NULL;
+        priv->func      = NULL;
+        priv->usbh_base = NULL;
+}
+static int usbhsf_hardware_init(struct platform_device *pdev)
+{
+        struct usbhsf_private *priv = usbhsf_get_priv(pdev);
+        priv->phy       = clk_get(&pdev->dev, "phy");
+        priv->usb24     = clk_get(&pdev->dev, "usb24");
+        priv->pci       = clk_get(&pdev->dev, "pci");
+        priv->func      = clk_get(&pdev->dev, "func");
+        priv->host      = clk_get(&pdev->dev, "host");
+        priv->usbh_base = ioremap_nocache(USBH, 0x20000);
+        if (IS_ERR(priv->phy)           ||
+            IS_ERR(priv->usb24)         ||
+            IS_ERR(priv->pci)           ||
+            IS_ERR(priv->host)          ||
+            IS_ERR(priv->func)          ||
+            !priv->usbh_base) {
+                dev_err(&pdev->dev, "USB clock setting failed\n");
+                usbhsf_hardware_exit(pdev);
+                return -EIO;
+        }
+        /* usb24 use 1/1 of parent clock (= usb24s = 24MHz) */
+        clk_set_rate(priv->usb24,
+                     clk_get_rate(clk_get_parent(priv->usb24)));
+        return 0;
+}
+static struct usbhsf_private usbhsf_private = {
+        .info = {
+                .platform_callback = {
+                        .get_id         = usbhsf_get_id,
+                        .hardware_init  = usbhsf_hardware_init,
+                        .hardware_exit  = usbhsf_hardware_exit,
+                        .power_ctrl     = usbhsf_power_ctrl,
+                },
+                .driver_param = {
+                        .buswait_bwait          = 5,
+                        .detection_delay        = 5,
+                },
+        }
+};
+static struct resource usbhsf_resources[] = {
+        {
+                .name   = "USBHS",
+                .start  = 0xe6890000,
+                .end    = 0xe6890104 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = evt2irq(0x0A20),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device usbhsf_device = {
+        .name   = "renesas_usbhs",
+        .dev = {
+                .platform_data = &usbhsf_private.info,
+        },
+        .id = -1,
+        .num_resources  = ARRAY_SIZE(usbhsf_resources),
+        .resource       = usbhsf_resources,
+};
+/* Ether */
+static struct sh_eth_plat_data sh_eth_platdata = {
+        .phy                    = 0x00, /* LAN8710A */
+        .edmac_endian           = EDMAC_LITTLE_ENDIAN,
+        .register_type          = SH_ETH_REG_GIGABIT,
+        .phy_interface          = PHY_INTERFACE_MODE_MII,
+};
+static struct resource sh_eth_resources[] = {
+        {
+                .start  = 0xe9a00000,
+                .end    = 0xe9a00800 - 1,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = 0xe9a01800,
+                .end    = 0xe9a02000 - 1,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = evt2irq(0x0500),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device sh_eth_device = {
+        .name = "sh-eth",
+        .id = -1,
+        .dev = {
+                .platform_data = &sh_eth_platdata,
+        },
+        .resource = sh_eth_resources,
+        .num_resources = ARRAY_SIZE(sh_eth_resources),
+};
+/* LCDC */
+static struct fb_videomode lcdc0_mode = {
+        .name           = "AMPIER/AM-800480",
+        .xres           = 800,
+        .yres           = 480,
+        .left_margin    = 88,
+        .right_margin   = 40,
+        .hsync_len      = 128,
+        .upper_margin   = 20,
+        .lower_margin   = 5,
+        .vsync_len      = 5,
+        .sync           = 0,
+};
+static struct sh_mobile_lcdc_info lcdc0_info = {
+        .clock_source   = LCDC_CLK_BUS,
+        .ch[0] = {
+                .chan           = LCDC_CHAN_MAINLCD,
+                .fourcc         = V4L2_PIX_FMT_RGB565,
+                .interface_type = RGB24,
+                .clock_divider  = 5,
+                .flags          = 0,
+                .lcd_modes      = &lcdc0_mode,
+                .num_modes      = 1,
+                .panel_cfg = {
+                        .width  = 111,
+                        .height = 68,
+                },
+        },
+};
+static struct resource lcdc0_resources[] = {
+        [0] = {
+                .name   = "LCD0",
+                .start  = 0xfe940000,
+                .end    = 0xfe943fff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = intcs_evt2irq(0x580),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device lcdc0_device = {
+        .name           = "sh_mobile_lcdc_fb",
+        .num_resources  = ARRAY_SIZE(lcdc0_resources),
+        .resource       = lcdc0_resources,
+        .id             = 0,
+        .dev    = {
+                .platform_data  = &lcdc0_info,
+                .coherent_dma_mask = ~0,
+        },
+};
+/* GPIO KEY */
+#define GPIO_KEY(c, g, d) { .code = c, .gpio = g, .desc = d, .active_low = 1 }
+static struct gpio_keys_button gpio_buttons[] = {
+        GPIO_KEY(KEY_POWER,     GPIO_PORT99,    "SW1"),
+        GPIO_KEY(KEY_BACK,      GPIO_PORT100,   "SW2"),
+        GPIO_KEY(KEY_MENU,      GPIO_PORT97,    "SW3"),
+        GPIO_KEY(KEY_HOME,      GPIO_PORT98,    "SW4"),
+};
+static struct gpio_keys_platform_data gpio_key_info = {
+        .buttons        = gpio_buttons,
+        .nbuttons       = ARRAY_SIZE(gpio_buttons),
+};
+static struct platform_device gpio_keys_device = {
+        .name   = "gpio-keys",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &gpio_key_info,
+        },
+};
+/* SDHI0 */
+/*
+ * FIXME
+ *
+ * It use polling mode here, since
+ * CD (= Card Detect) pin is not connected to SDHI0_CD.
+ * We can use IRQ31 as card detect irq,
+ * but it needs chattering removal operation
+ */
+#define IRQ31   evt2irq(0x33E0)
+static struct sh_mobile_sdhi_info sdhi0_info = {
+        .tmio_caps      = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |\
+                          MMC_CAP_NEEDS_POLL,
+        .tmio_ocr_mask  = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
+        .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT,
+};
+static struct resource sdhi0_resources[] = {
+        {
+                .name   = "SDHI0",
+                .start  = 0xe6850000,
+                .end    = 0xe6850100 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        /*
+         * no SH_MOBILE_SDHI_IRQ_CARD_DETECT here
+         */
+        {
+                .name   = SH_MOBILE_SDHI_IRQ_SDCARD,
+                .start  = evt2irq(0x0E20),
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                .name   = SH_MOBILE_SDHI_IRQ_SDIO,
+                .start  = evt2irq(0x0E40),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device sdhi0_device = {
+        .name           = "sh_mobile_sdhi",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &sdhi0_info,
+        },
+        .num_resources  = ARRAY_SIZE(sdhi0_resources),
+        .resource       = sdhi0_resources,
+};
+/* SDHI1 */
+static struct sh_mobile_sdhi_info sdhi1_info = {
+        .tmio_caps      = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
+        .tmio_ocr_mask  = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
+        .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT,
+};
+static struct resource sdhi1_resources[] = {
+        [0] = {
+                .name   = "SDHI1",
+                .start  = 0xe6860000,
+                .end    = 0xe6860100 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = evt2irq(0x0E80),
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = evt2irq(0x0EA0),
+                .flags  = IORESOURCE_IRQ,
+        },
+        [3] = {
+                .start  = evt2irq(0x0EC0),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device sdhi1_device = {
+        .name           = "sh_mobile_sdhi",
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &sdhi1_info,
+        },
+        .num_resources  = ARRAY_SIZE(sdhi1_resources),
+        .resource       = sdhi1_resources,
+};
+/* MMCIF */
+static struct sh_mmcif_plat_data sh_mmcif_plat = {
+        .sup_pclk       = 0,
+        .ocr            = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
+        .caps           = MMC_CAP_4_BIT_DATA |
+                          MMC_CAP_8_BIT_DATA |
+                          MMC_CAP_NONREMOVABLE,
+};
+static struct resource sh_mmcif_resources[] = {
+        [0] = {
+                .name   = "MMCIF",
+                .start  = 0xe6bd0000,
+                .end    = 0xe6bd0100 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                /* MMC ERR */
+                .start  = evt2irq(0x1AC0),
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                /* MMC NOR */
+                .start  = evt2irq(0x1AE0),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device sh_mmcif_device = {
+        .name           = "sh_mmcif",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &sh_mmcif_plat,
+        },
+        .num_resources  = ARRAY_SIZE(sh_mmcif_resources),
+        .resource       = sh_mmcif_resources,
+};
+/* I2C */
+static struct i2c_board_info i2c0_devices[] = {
+        {
+                I2C_BOARD_INFO("st1232-ts", 0x55),
+                .irq = evt2irq(0x0340),
+        },
+};
+/*
+ * board devices
+ */
+static struct platform_device *eva_devices[] __initdata = {
+        &lcdc0_device,
+        &gpio_keys_device,
+        &sh_eth_device,
+        &sdhi0_device,
+        &sh_mmcif_device,
+};
+static void __init eva_clock_init(void)
+{
+        struct clk *system      = clk_get(NULL, "system_clk");
+        struct clk *xtal1       = clk_get(NULL, "extal1");
+        struct clk *usb24s      = clk_get(NULL, "usb24s");
+        if (IS_ERR(system)      ||
+            IS_ERR(xtal1)       ||
+            IS_ERR(usb24s)) {
+                pr_err("armadillo800eva board clock init failed\n");
+                goto clock_error;
+        }
+        /* armadillo 800 eva extal1 is 24MHz */
+        clk_set_rate(xtal1, 24000000);
+        /* usb24s use extal1 (= system) clock (= 24MHz) */
+        clk_set_parent(usb24s, system);
+clock_error:
+        if (!IS_ERR(system))
+                clk_put(system);
+        if (!IS_ERR(xtal1))
+                clk_put(xtal1);
+        if (!IS_ERR(usb24s))
+                clk_put(usb24s);
+}
+/*
+ * board init
+ */
+static void __init eva_init(void)
+{
+        eva_clock_init();
+        r8a7740_pinmux_init();
+        /* SCIFA1 */
+        gpio_request(GPIO_FN_SCIFA1_RXD, NULL);
+        gpio_request(GPIO_FN_SCIFA1_TXD, NULL);
+        /* LCDC0 */
+        gpio_request(GPIO_FN_LCDC0_SELECT,      NULL);
+        gpio_request(GPIO_FN_LCD0_D0,           NULL);
+        gpio_request(GPIO_FN_LCD0_D1,           NULL);
+        gpio_request(GPIO_FN_LCD0_D2,           NULL);
+        gpio_request(GPIO_FN_LCD0_D3,           NULL);
+        gpio_request(GPIO_FN_LCD0_D4,           NULL);
+        gpio_request(GPIO_FN_LCD0_D5,           NULL);
+        gpio_request(GPIO_FN_LCD0_D6,           NULL);
+        gpio_request(GPIO_FN_LCD0_D7,           NULL);
+        gpio_request(GPIO_FN_LCD0_D8,           NULL);
+        gpio_request(GPIO_FN_LCD0_D9,           NULL);
+        gpio_request(GPIO_FN_LCD0_D10,          NULL);
+        gpio_request(GPIO_FN_LCD0_D11,          NULL);
+        gpio_request(GPIO_FN_LCD0_D12,          NULL);
+        gpio_request(GPIO_FN_LCD0_D13,          NULL);
+        gpio_request(GPIO_FN_LCD0_D14,          NULL);
+        gpio_request(GPIO_FN_LCD0_D15,          NULL);
+        gpio_request(GPIO_FN_LCD0_D16,          NULL);
+        gpio_request(GPIO_FN_LCD0_D17,          NULL);
+        gpio_request(GPIO_FN_LCD0_D18_PORT40,   NULL);
+        gpio_request(GPIO_FN_LCD0_D19_PORT4,    NULL);
+        gpio_request(GPIO_FN_LCD0_D20_PORT3,    NULL);
+        gpio_request(GPIO_FN_LCD0_D21_PORT2,    NULL);
+        gpio_request(GPIO_FN_LCD0_D22_PORT0,    NULL);
+        gpio_request(GPIO_FN_LCD0_D23_PORT1,    NULL);
+        gpio_request(GPIO_FN_LCD0_DCK,          NULL);
+        gpio_request(GPIO_FN_LCD0_VSYN,         NULL);
+        gpio_request(GPIO_FN_LCD0_HSYN,         NULL);
+        gpio_request(GPIO_FN_LCD0_DISP,         NULL);
+        gpio_request(GPIO_FN_LCD0_LCLK_PORT165, NULL);
+        gpio_request(GPIO_PORT61, NULL); /* LCDDON */
+        gpio_direction_output(GPIO_PORT61, 1);
+        gpio_request(GPIO_PORT202, NULL); /* LCD0_LED_CONT */
+        gpio_direction_output(GPIO_PORT202, 0);
+        /* Touchscreen */
+        gpio_request(GPIO_FN_IRQ10,     NULL); /* TP_INT */
+        gpio_request(GPIO_PORT166,      NULL); /* TP_RST_B */
+        gpio_direction_output(GPIO_PORT166, 1);
+        /* GETHER */
+        gpio_request(GPIO_FN_ET_CRS,            NULL);
+        gpio_request(GPIO_FN_ET_MDC,            NULL);
+        gpio_request(GPIO_FN_ET_MDIO,           NULL);
+        gpio_request(GPIO_FN_ET_TX_ER,          NULL);
+        gpio_request(GPIO_FN_ET_RX_ER,          NULL);
+        gpio_request(GPIO_FN_ET_ERXD0,          NULL);
+        gpio_request(GPIO_FN_ET_ERXD1,          NULL);
+        gpio_request(GPIO_FN_ET_ERXD2,          NULL);
+        gpio_request(GPIO_FN_ET_ERXD3,          NULL);
+        gpio_request(GPIO_FN_ET_TX_CLK,         NULL);
+        gpio_request(GPIO_FN_ET_TX_EN,          NULL);
+        gpio_request(GPIO_FN_ET_ETXD0,          NULL);
+        gpio_request(GPIO_FN_ET_ETXD1,          NULL);
+        gpio_request(GPIO_FN_ET_ETXD2,          NULL);
+        gpio_request(GPIO_FN_ET_ETXD3,          NULL);
+        gpio_request(GPIO_FN_ET_PHY_INT,        NULL);
+        gpio_request(GPIO_FN_ET_COL,            NULL);
+        gpio_request(GPIO_FN_ET_RX_DV,          NULL);
+        gpio_request(GPIO_FN_ET_RX_CLK,         NULL);
+        gpio_request(GPIO_PORT18, NULL); /* PHY_RST */
+        gpio_direction_output(GPIO_PORT18, 1);
+        /* USB */
+        gpio_request(GPIO_PORT159, NULL); /* USB_DEVICE_MODE */
+        gpio_direction_input(GPIO_PORT159);
+        if (gpio_get_value(GPIO_PORT159)) {
+                /* USB Host */
+        } else {
+                /* USB Func */
+                gpio_request(GPIO_FN_VBUS, NULL);
+                platform_device_register(&usbhsf_device);
+        }
+        /* SDHI0 */
+        gpio_request(GPIO_FN_SDHI0_CMD, NULL);
+        gpio_request(GPIO_FN_SDHI0_CLK, NULL);
+        gpio_request(GPIO_FN_SDHI0_D0, NULL);
+        gpio_request(GPIO_FN_SDHI0_D1, NULL);
+        gpio_request(GPIO_FN_SDHI0_D2, NULL);
+        gpio_request(GPIO_FN_SDHI0_D3, NULL);
+        gpio_request(GPIO_FN_SDHI0_WP, NULL);
+        gpio_request(GPIO_PORT17, NULL);        /* SDHI0_18/33_B */
+        gpio_request(GPIO_PORT74, NULL);        /* SDHI0_PON */
+        gpio_request(GPIO_PORT75, NULL);        /* SDSLOT1_PON */
+        gpio_direction_output(GPIO_PORT17, 0);
+        gpio_direction_output(GPIO_PORT74, 1);
+        gpio_direction_output(GPIO_PORT75, 1);
+        /* we can use GPIO_FN_IRQ31_PORT167 here for SDHI0 CD irq */
+        /*
+         * MMCIF
+         *
+         * Here doesn't care SW1.4 status,
+         * since CON2 is not mounted.
+         */
+        gpio_request(GPIO_FN_MMC1_CLK_PORT103,  NULL);
+        gpio_request(GPIO_FN_MMC1_CMD_PORT104,  NULL);
+        gpio_request(GPIO_FN_MMC1_D0_PORT149,   NULL);
+        gpio_request(GPIO_FN_MMC1_D1_PORT148,   NULL);
+        gpio_request(GPIO_FN_MMC1_D2_PORT147,   NULL);
+        gpio_request(GPIO_FN_MMC1_D3_PORT146,   NULL);
+        gpio_request(GPIO_FN_MMC1_D4_PORT145,   NULL);
+        gpio_request(GPIO_FN_MMC1_D5_PORT144,   NULL);
+        gpio_request(GPIO_FN_MMC1_D6_PORT143,   NULL);
+        gpio_request(GPIO_FN_MMC1_D7_PORT142,   NULL);
+        /*
+         * CAUTION
+         *
+         * DBGMD/LCDC0/FSIA MUX
+         * DBGMD_SELECT_B should be set after setting PFC Function.
+         */
+        gpio_request(GPIO_PORT176, NULL);
+        gpio_direction_output(GPIO_PORT176, 1);
+        /*
+         * We can switch CON8/CON14 by SW1.5,
+         * but it needs after DBGMD_SELECT_B
+         */
+        gpio_request(GPIO_PORT6, NULL);
+        gpio_direction_input(GPIO_PORT6);
+        if (gpio_get_value(GPIO_PORT6)) {
+                /* CON14 enable */
+        } else {
+                /* CON8 (SDHI1) enable */
+                gpio_request(GPIO_FN_SDHI1_CLK, NULL);
+                gpio_request(GPIO_FN_SDHI1_CMD, NULL);
+                gpio_request(GPIO_FN_SDHI1_D0,  NULL);
+                gpio_request(GPIO_FN_SDHI1_D1,  NULL);
+                gpio_request(GPIO_FN_SDHI1_D2,  NULL);
+                gpio_request(GPIO_FN_SDHI1_D3,  NULL);
+                gpio_request(GPIO_FN_SDHI1_CD,  NULL);
+                gpio_request(GPIO_FN_SDHI1_WP,  NULL);
+                gpio_request(GPIO_PORT16, NULL); /* SDSLOT2_PON */
+                gpio_direction_output(GPIO_PORT16, 1);
+                platform_device_register(&sdhi1_device);
+        }
+#ifdef CONFIG_CACHE_L2X0
+        /* Early BRESP enable, Shared attribute override enable, 32K*8way */
+        l2x0_init(__io(0xf0002000), 0x40440000, 0x82000fff);
+#endif
+        i2c_register_board_info(0, i2c0_devices, ARRAY_SIZE(i2c0_devices));
+        r8a7740_add_standard_devices();
+        platform_add_devices(eva_devices,
+                             ARRAY_SIZE(eva_devices));
+}
+static void __init eva_earlytimer_init(void)
+{
+        r8a7740_clock_init(MD_CK0 | MD_CK2);
+        shmobile_earlytimer_init();
+}
+static void __init eva_add_early_devices(void)
+{
+        r8a7740_add_early_devices();
+        /* override timer setup with board-specific code */
+        shmobile_timer.init = eva_earlytimer_init;
+}
+static const char *eva_boards_compat_dt[] __initdata = {
+        "renesas,armadillo800eva",
+        NULL,
+};
+DT_MACHINE_START(ARMADILLO800EVA_DT, "armadillo800eva")
+        .map_io         = r8a7740_map_io,
+        .init_early     = eva_add_early_devices,
+        .init_irq       = r8a7740_init_irq,
+        .handle_irq     = shmobile_handle_irq_intc,
+        .init_machine   = eva_init,
+        .timer          = &shmobile_timer,
+        .dt_compat      = eva_boards_compat_dt,
+MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-bonito.c b/arch/arm/mach-shmobile/board-bonito.c
index 81fd95f7f52a..63ab7062bee3 100644
--- a/arch/arm/mach-shmobile/board-bonito.c
+++ b/arch/arm/mach-shmobile/board-bonito.c
@@ -486,7 +486,7 @@ static void __init bonito_earlytimer_init(void)
        shmobile_earlytimer_init();
 }
-void __init bonito_add_early_devices(void)
+static void __init bonito_add_early_devices(void)
 {
        r8a7740_add_early_devices();
diff --git a/arch/arm/mach-shmobile/board-kzm9d.c b/arch/arm/mach-shmobile/board-kzm9d.c
new file mode 100644
index 000000000000..7bc5e7d39f9b
--- /dev/null
+++ b/arch/arm/mach-shmobile/board-kzm9d.c
@@ -0,0 +1,85 @@
+/*
+ * kzm9d board support
+ *
+ * Copyright (C) 2012  Renesas Solutions Corp.
+ * Copyright (C) 2012  Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/smsc911x.h>
+#include <mach/common.h>
+#include <mach/emev2.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/hardware/gic.h>
+/* Ether */
+static struct resource smsc911x_resources[] = {
+        [0] = {
+                .start  = 0x20000000,
+                .end    = 0x2000ffff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = EMEV2_GPIO_IRQ(1),
+                .flags  = IORESOURCE_IRQ | IRQF_TRIGGER_HIGH,
+        },
+};
+static struct smsc911x_platform_config smsc911x_platdata = {
+        .flags          = SMSC911X_USE_32BIT,
+        .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
+        .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
+};
+static struct platform_device smsc91x_device = {
+        .name   = "smsc911x",
+        .id     = 0,
+        .dev    = {
+                  .platform_data = &smsc911x_platdata,
+                },
+        .num_resources  = ARRAY_SIZE(smsc911x_resources),
+        .resource       = smsc911x_resources,
+};
+static struct platform_device *kzm9d_devices[] __initdata = {
+        &smsc91x_device,
+};
+void __init kzm9d_add_standard_devices(void)
+{
+        emev2_add_standard_devices();
+        platform_add_devices(kzm9d_devices, ARRAY_SIZE(kzm9d_devices));
+}
+static const char *kzm9d_boards_compat_dt[] __initdata = {
+        "renesas,kzm9d",
+        NULL,
+};
+DT_MACHINE_START(KZM9D_DT, "kzm9d")
+        .map_io         = emev2_map_io,
+        .init_early     = emev2_add_early_devices,
+        .nr_irqs        = NR_IRQS_LEGACY,
+        .init_irq       = emev2_init_irq,
+        .handle_irq     = gic_handle_irq,
+        .init_machine   = kzm9d_add_standard_devices,
+        .timer          = &shmobile_timer,
+        .dt_compat      = kzm9d_boards_compat_dt,
+MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c
new file mode 100644
index 000000000000..d8e33b682832
--- /dev/null
+++ b/arch/arm/mach-shmobile/board-kzm9g.c
@@ -0,0 +1,460 @@
+/*
+ * KZM-A9-GT board support
+ *
+ * Copyright (C) 2012   Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/gpio_keys.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/i2c.h>
+#include <linux/i2c/pcf857x.h>
+#include <linux/input.h>
+#include <linux/mmc/host.h>
+#include <linux/mmc/sh_mmcif.h>
+#include <linux/mmc/sh_mobile_sdhi.h>
+#include <linux/mfd/tmio.h>
+#include <linux/platform_device.h>
+#include <linux/smsc911x.h>
+#include <linux/usb/r8a66597.h>
+#include <linux/videodev2.h>
+#include <mach/irqs.h>
+#include <mach/sh73a0.h>
+#include <mach/common.h>
+#include <asm/hardware/cache-l2x0.h>
+#include <asm/hardware/gic.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <video/sh_mobile_lcdc.h>
+/*
+ * external GPIO
+ */
+#define GPIO_PCF8575_BASE       (GPIO_NR)
+#define GPIO_PCF8575_PORT10     (GPIO_NR + 8)
+#define GPIO_PCF8575_PORT11     (GPIO_NR + 9)
+#define GPIO_PCF8575_PORT12     (GPIO_NR + 10)
+#define GPIO_PCF8575_PORT13     (GPIO_NR + 11)
+#define GPIO_PCF8575_PORT14     (GPIO_NR + 12)
+#define GPIO_PCF8575_PORT15     (GPIO_NR + 13)
+#define GPIO_PCF8575_PORT16     (GPIO_NR + 14)
+/* SMSC 9221 */
+static struct resource smsc9221_resources[] = {
+        [0] = {
+                .start  = 0x10000000, /* CS4 */
+                .end    = 0x100000ff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = intcs_evt2irq(0x260), /* IRQ3 */
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct smsc911x_platform_config smsc9221_platdata = {
+        .flags          = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS,
+        .phy_interface  = PHY_INTERFACE_MODE_MII,
+        .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
+        .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
+};
+static struct platform_device smsc_device = {
+        .name           = "smsc911x",
+        .dev  = {
+                .platform_data = &smsc9221_platdata,
+        },
+        .resource       = smsc9221_resources,
+        .num_resources  = ARRAY_SIZE(smsc9221_resources),
+};
+/* USB external chip */
+static struct r8a66597_platdata usb_host_data = {
+        .on_chip        = 0,
+        .xtal           = R8A66597_PLATDATA_XTAL_48MHZ,
+};
+static struct resource usb_resources[] = {
+        [0] = {
+                .start  = 0x10010000,
+                .end    = 0x1001ffff - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = intcs_evt2irq(0x220), /* IRQ1 */
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device usb_host_device = {
+        .name   = "r8a66597_hcd",
+        .dev = {
+                .platform_data          = &usb_host_data,
+                .dma_mask               = NULL,
+                .coherent_dma_mask      = 0xffffffff,
+        },
+        .num_resources  = ARRAY_SIZE(usb_resources),
+        .resource       = usb_resources,
+};
+/* LCDC */
+static struct fb_videomode kzm_lcdc_mode = {
+        .name           = "WVGA Panel",
+        .xres           = 800,
+        .yres           = 480,
+        .left_margin    = 220,
+        .right_margin   = 110,
+        .hsync_len      = 70,
+        .upper_margin   = 20,
+        .lower_margin   = 5,
+        .vsync_len      = 5,
+        .sync           = 0,
+};
+static struct sh_mobile_lcdc_info lcdc_info = {
+        .clock_source = LCDC_CLK_BUS,
+        .ch[0] = {
+                .chan           = LCDC_CHAN_MAINLCD,
+                .fourcc         = V4L2_PIX_FMT_RGB565,
+                .interface_type = RGB24,
+                .lcd_modes      = &kzm_lcdc_mode,
+                .num_modes      = 1,
+                .clock_divider  = 5,
+                .flags          = 0,
+                .panel_cfg = {
+                        .width  = 152,
+                        .height = 91,
+                },
+        }
+};
+static struct resource lcdc_resources[] = {
+        [0] = {
+                .name   = "LCDC",
+                .start  = 0xfe940000,
+                .end    = 0xfe943fff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = intcs_evt2irq(0x580),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device lcdc_device = {
+        .name           = "sh_mobile_lcdc_fb",
+        .num_resources  = ARRAY_SIZE(lcdc_resources),
+        .resource       = lcdc_resources,
+        .dev    = {
+                .platform_data  = &lcdc_info,
+                .coherent_dma_mask = ~0,
+        },
+};
+/* MMCIF */
+static struct resource sh_mmcif_resources[] = {
+        [0] = {
+                .name   = "MMCIF",
+                .start  = 0xe6bd0000,
+                .end    = 0xe6bd00ff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = gic_spi(141),
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = gic_spi(140),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct sh_mmcif_plat_data sh_mmcif_platdata = {
+        .ocr            = MMC_VDD_165_195,
+        .caps           = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE,
+};
+static struct platform_device mmc_device = {
+        .name           = "sh_mmcif",
+        .dev            = {
+                .dma_mask               = NULL,
+                .coherent_dma_mask      = 0xffffffff,
+                .platform_data          = &sh_mmcif_platdata,
+        },
+        .num_resources  = ARRAY_SIZE(sh_mmcif_resources),
+        .resource       = sh_mmcif_resources,
+};
+/* SDHI */
+static struct sh_mobile_sdhi_info sdhi0_info = {
+        .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT,
+        .tmio_caps      = MMC_CAP_SD_HIGHSPEED,
+        .tmio_ocr_mask  = MMC_VDD_27_28 | MMC_VDD_28_29,
+};
+static struct resource sdhi0_resources[] = {
+        [0] = {
+                .name   = "SDHI0",
+                .start  = 0xee100000,
+                .end    = 0xee1000ff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .name   = SH_MOBILE_SDHI_IRQ_CARD_DETECT,
+                .start  = gic_spi(83),
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .name   = SH_MOBILE_SDHI_IRQ_SDCARD,
+                .start  = gic_spi(84),
+                .flags  = IORESOURCE_IRQ,
+        },
+        [3] = {
+                .name   = SH_MOBILE_SDHI_IRQ_SDIO,
+                .start  = gic_spi(85),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device sdhi0_device = {
+        .name           = "sh_mobile_sdhi",
+        .num_resources  = ARRAY_SIZE(sdhi0_resources),
+        .resource       = sdhi0_resources,
+        .dev    = {
+                .platform_data  = &sdhi0_info,
+        },
+};
+/* KEY */
+#define GPIO_KEY(c, g, d) { .code = c, .gpio = g, .desc = d, .active_low = 1 }
+static struct gpio_keys_button gpio_buttons[] = {
+        GPIO_KEY(KEY_BACK,      GPIO_PCF8575_PORT10,    "SW3"),
+        GPIO_KEY(KEY_RIGHT,     GPIO_PCF8575_PORT11,    "SW2-R"),
+        GPIO_KEY(KEY_LEFT,      GPIO_PCF8575_PORT12,    "SW2-L"),
+        GPIO_KEY(KEY_ENTER,     GPIO_PCF8575_PORT13,    "SW2-P"),
+        GPIO_KEY(KEY_UP,        GPIO_PCF8575_PORT14,    "SW2-U"),
+        GPIO_KEY(KEY_DOWN,      GPIO_PCF8575_PORT15,    "SW2-D"),
+        GPIO_KEY(KEY_HOME,      GPIO_PCF8575_PORT16,    "SW1"),
+};
+static struct gpio_keys_platform_data gpio_key_info = {
+        .buttons        = gpio_buttons,
+        .nbuttons       = ARRAY_SIZE(gpio_buttons),
+        .poll_interval  = 250, /* poling at this point */
+};
+static struct platform_device gpio_keys_device = {
+        /* gpio-pcf857x.c driver doesn't support gpio_to_irq() */
+        .name   = "gpio-keys-polled",
+        .dev    = {
+                .platform_data  = &gpio_key_info,
+        },
+};
+/* I2C */
+static struct pcf857x_platform_data pcf8575_pdata = {
+        .gpio_base      = GPIO_PCF8575_BASE,
+};
+static struct i2c_board_info i2c1_devices[] = {
+        {
+                I2C_BOARD_INFO("st1232-ts", 0x55),
+                .irq = intcs_evt2irq(0x300), /* IRQ8 */
+        },
+};
+static struct i2c_board_info i2c3_devices[] = {
+        {
+                I2C_BOARD_INFO("pcf8575", 0x20),
+                .platform_data = &pcf8575_pdata,
+        },
+};
+static struct platform_device *kzm_devices[] __initdata = {
+        &smsc_device,
+        &usb_host_device,
+        &lcdc_device,
+        &mmc_device,
+        &sdhi0_device,
+        &gpio_keys_device,
+};
+/*
+ * FIXME
+ *
+ * This is quick hack for enabling LCDC backlight
+ */
+static int __init as3711_enable_lcdc_backlight(void)
+{
+        struct i2c_adapter *a = i2c_get_adapter(0);
+        struct i2c_msg msg;
+        int i, ret;
+        __u8 magic[] = {
+                0x40, 0x2a,
+                0x43, 0x3c,
+                0x44, 0x3c,
+                0x45, 0x3c,
+                0x54, 0x03,
+                0x51, 0x00,
+                0x51, 0x01,
+                0xff, 0x00, /* wait */
+                0x43, 0xf0,
+                0x44, 0xf0,
+                0x45, 0xf0,
+        };
+        if (!machine_is_kzm9g())
+                return 0;
+        if (!a)
+                return 0;
+        msg.addr        = 0x40;
+        msg.len         = 2;
+        msg.flags       = 0;
+        for (i = 0; i < ARRAY_SIZE(magic); i += 2) {
+                msg.buf = magic + i;
+                if (0xff == msg.buf[0]) {
+                        udelay(500);
+                        continue;
+                }
+                ret = i2c_transfer(a, &msg, 1);
+                if (ret < 0) {
+                        pr_err("i2c transfer fail\n");
+                        break;
+                }
+        }
+        return 0;
+}
+device_initcall(as3711_enable_lcdc_backlight);
+static void __init kzm_init(void)
+{
+        sh73a0_pinmux_init();
+        /* enable SCIFA4 */
+        gpio_request(GPIO_FN_SCIFA4_TXD, NULL);
+        gpio_request(GPIO_FN_SCIFA4_RXD, NULL);
+        gpio_request(GPIO_FN_SCIFA4_RTS_, NULL);
+        gpio_request(GPIO_FN_SCIFA4_CTS_, NULL);
+        /* CS4 for SMSC/USB */
+        gpio_request(GPIO_FN_CS4_, NULL); /* CS4 */
+        /* SMSC */
+        gpio_request(GPIO_PORT224, NULL); /* IRQ3 */
+        gpio_direction_input(GPIO_PORT224);
+        /* LCDC */
+        gpio_request(GPIO_FN_LCDD23,    NULL);
+        gpio_request(GPIO_FN_LCDD22,    NULL);
+        gpio_request(GPIO_FN_LCDD21,    NULL);
+        gpio_request(GPIO_FN_LCDD20,    NULL);
+        gpio_request(GPIO_FN_LCDD19,    NULL);
+        gpio_request(GPIO_FN_LCDD18,    NULL);
+        gpio_request(GPIO_FN_LCDD17,    NULL);
+        gpio_request(GPIO_FN_LCDD16,    NULL);
+        gpio_request(GPIO_FN_LCDD15,    NULL);
+        gpio_request(GPIO_FN_LCDD14,    NULL);
+        gpio_request(GPIO_FN_LCDD13,    NULL);
+        gpio_request(GPIO_FN_LCDD12,    NULL);
+        gpio_request(GPIO_FN_LCDD11,    NULL);
+        gpio_request(GPIO_FN_LCDD10,    NULL);
+        gpio_request(GPIO_FN_LCDD9,     NULL);
+        gpio_request(GPIO_FN_LCDD8,     NULL);
+        gpio_request(GPIO_FN_LCDD7,     NULL);
+        gpio_request(GPIO_FN_LCDD6,     NULL);
+        gpio_request(GPIO_FN_LCDD5,     NULL);
+        gpio_request(GPIO_FN_LCDD4,     NULL);
+        gpio_request(GPIO_FN_LCDD3,     NULL);
+        gpio_request(GPIO_FN_LCDD2,     NULL);
+        gpio_request(GPIO_FN_LCDD1,     NULL);
+        gpio_request(GPIO_FN_LCDD0,     NULL);
+        gpio_request(GPIO_FN_LCDDISP,   NULL);
+        gpio_request(GPIO_FN_LCDDCK,    NULL);
+        gpio_request(GPIO_PORT222,      NULL); /* LCDCDON */
+        gpio_request(GPIO_PORT226,      NULL); /* SC */
+        gpio_direction_output(GPIO_PORT222, 1);
+        gpio_direction_output(GPIO_PORT226, 1);
+        /* Touchscreen */
+        gpio_request(GPIO_PORT223, NULL); /* IRQ8 */
+        gpio_direction_input(GPIO_PORT223);
+        /* enable MMCIF */
+        gpio_request(GPIO_FN_MMCCLK0,           NULL);
+        gpio_request(GPIO_FN_MMCCMD0_PU,        NULL);
+        gpio_request(GPIO_FN_MMCD0_0_PU,        NULL);
+        gpio_request(GPIO_FN_MMCD0_1_PU,        NULL);
+        gpio_request(GPIO_FN_MMCD0_2_PU,        NULL);
+        gpio_request(GPIO_FN_MMCD0_3_PU,        NULL);
+        gpio_request(GPIO_FN_MMCD0_4_PU,        NULL);
+        gpio_request(GPIO_FN_MMCD0_5_PU,        NULL);
+        gpio_request(GPIO_FN_MMCD0_6_PU,        NULL);
+        gpio_request(GPIO_FN_MMCD0_7_PU,        NULL);
+        /* enable SD */
+        gpio_request(GPIO_FN_SDHIWP0,           NULL);
+        gpio_request(GPIO_FN_SDHICD0,           NULL);
+        gpio_request(GPIO_FN_SDHICMD0,          NULL);
+        gpio_request(GPIO_FN_SDHICLK0,          NULL);
+        gpio_request(GPIO_FN_SDHID0_3,          NULL);
+        gpio_request(GPIO_FN_SDHID0_2,          NULL);
+        gpio_request(GPIO_FN_SDHID0_1,          NULL);
+        gpio_request(GPIO_FN_SDHID0_0,          NULL);
+        gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON, NULL);
+        gpio_request(GPIO_PORT15, NULL);
+        gpio_direction_output(GPIO_PORT15, 1); /* power */
+        /* I2C 3 */
+        gpio_request(GPIO_FN_PORT27_I2C_SCL3, NULL);
+        gpio_request(GPIO_FN_PORT28_I2C_SDA3, NULL);
+#ifdef CONFIG_CACHE_L2X0
+        /* Early BRESP enable, Shared attribute override enable, 64K*8way */
+        l2x0_init(IOMEM(0xf0100000), 0x40460000, 0x82000fff);
+#endif
+        i2c_register_board_info(1, i2c1_devices, ARRAY_SIZE(i2c1_devices));
+        i2c_register_board_info(3, i2c3_devices, ARRAY_SIZE(i2c3_devices));
+        sh73a0_add_standard_devices();
+        platform_add_devices(kzm_devices, ARRAY_SIZE(kzm_devices));
+}
+static const char *kzm9g_boards_compat_dt[] __initdata = {
+        "renesas,kzm9g",
+        NULL,
+};
+DT_MACHINE_START(KZM9G_DT, "kzm9g")
+        .map_io         = sh73a0_map_io,
+        .init_early     = sh73a0_add_early_devices,
+        .nr_irqs        = NR_IRQS_LEGACY,
+        .init_irq       = sh73a0_init_irq,
+        .handle_irq     = gic_handle_irq,
+        .init_machine   = kzm_init,
+        .timer          = &shmobile_timer,
+        .dt_compat      = kzm9g_boards_compat_dt,
+MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index f49e28abe0ab..aae2e24fde46 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -908,6 +908,8 @@ fsi_set_rate_end:
 static struct sh_fsi_platform_info fsi_info = {
        .port_a = {
                .flags = SH_FSI_BRS_INV,
+                .tx_id = SHDMA_SLAVE_FSIA_TX,
+                .rx_id = SHDMA_SLAVE_FSIA_RX,
        },
        .port_b = {
                .flags = SH_FSI_BRS_INV |
@@ -920,9 +922,11 @@ static struct sh_fsi_platform_info fsi_info = {
 static struct resource fsi_resources[] = {
        [0] = {
+                /* we need 0xFE1F0000 to access DMA
+                 * instead of 0xFE3C0000 */
                .name   = "FSI",
-                .start  = 0xFE3C0000,
+                .start  = 0xFE1F0000,
-                .end    = 0xFE3C0400 - 1,
+                .end    = 0xFE1F0400 - 1,
                .flags  = IORESOURCE_MEM,
        },
        [1] = {
@@ -1011,21 +1015,12 @@ static int slot_cn7_get_cd(struct platform_device *pdev)
 }
 /* SDHI0 */
-static irqreturn_t mackerel_sdhi0_gpio_cd(int irq, void *arg)
-{
-        struct device *dev = arg;
-        struct sh_mobile_sdhi_info *info = dev->platform_data;
-        struct tmio_mmc_data *pdata = info->pdata;
-        tmio_mmc_cd_wakeup(pdata);
-        return IRQ_HANDLED;
-}
 static struct sh_mobile_sdhi_info sdhi0_info = {
        .dma_slave_tx   = SHDMA_SLAVE_SDHI0_TX,
        .dma_slave_rx   = SHDMA_SLAVE_SDHI0_RX,
+        .tmio_flags     = TMIO_MMC_USE_GPIO_CD,
        .tmio_caps      = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
+        .cd_gpio        = GPIO_PORT172,
 };
 static struct resource sdhi0_resources[] = {
@@ -1257,6 +1252,8 @@ static void mackerel_camera_del(struct soc_camera_device *icd)
 static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
        .flags = SH_CEU_FLAG_USE_8BIT_BUS,
+        .max_width = 8188,
+        .max_height = 8188,
 };
 static struct resource ceu_resources[] = {
@@ -1384,7 +1381,6 @@ static void __init mackerel_init(void)
 {
        u32 srcr4;
        struct clk *clk;
-        int ret;
        /* External clock source */
        clk_set_rate(&sh7372_dv_clki_clk, 27000000);
@@ -1481,7 +1477,6 @@ static void __init mackerel_init(void)
        irq_set_irq_type(IRQ21, IRQ_TYPE_LEVEL_HIGH);
        /* enable SDHI0 */
-        gpio_request(GPIO_FN_SDHICD0, NULL);
        gpio_request(GPIO_FN_SDHIWP0, NULL);
        gpio_request(GPIO_FN_SDHICMD0, NULL);
        gpio_request(GPIO_FN_SDHICLK0, NULL);
@@ -1490,13 +1485,6 @@ static void __init mackerel_init(void)
        gpio_request(GPIO_FN_SDHID0_1, NULL);
        gpio_request(GPIO_FN_SDHID0_0, NULL);
-        ret = request_irq(evt2irq(0x3340), mackerel_sdhi0_gpio_cd,
-                          IRQF_TRIGGER_FALLING, "sdhi0 cd", &sdhi0_device.dev);
-        if (!ret)
-                sdhi0_info.tmio_flags |= TMIO_MMC_HAS_COLD_CD;
-        else
-                pr_err("Cannot get IRQ #%d: %d\n", evt2irq(0x3340), ret);
 #if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
        /* enable SDHI1 */
        gpio_request(GPIO_FN_SDHICMD1, NULL);
diff --git a/arch/arm/mach-shmobile/clock-emev2.c b/arch/arm/mach-shmobile/clock-emev2.c
new file mode 100644
index 000000000000..4710f1847bb7
--- /dev/null
+++ b/arch/arm/mach-shmobile/clock-emev2.c
@@ -0,0 +1,249 @@
+/*
+ * Emma Mobile EV2 clock framework support
+ *
+ * Copyright (C) 2012  Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/sh_clk.h>
+#include <linux/clkdev.h>
+#include <mach/common.h>
+#define EMEV2_SMU_BASE 0xe0110000
+/* EMEV2 SMU registers */
+#define USIAU0_RSTCTRL 0x094
+#define USIBU1_RSTCTRL 0x0ac
+#define USIBU2_RSTCTRL 0x0b0
+#define USIBU3_RSTCTRL 0x0b4
+#define STI_RSTCTRL 0x124
+#define USIAU0GCLKCTRL 0x4a0
+#define USIBU1GCLKCTRL 0x4b8
+#define USIBU2GCLKCTRL 0x4bc
+#define USIBU3GCLKCTRL 0x04c0
+#define STIGCLKCTRL 0x528
+#define USIAU0SCLKDIV 0x61c
+#define USIB2SCLKDIV 0x65c
+#define USIB3SCLKDIV 0x660
+#define STI_CLKSEL 0x688
+#define SMU_GENERAL_REG0 0x7c0
+/* not pretty, but hey */
+static void __iomem *smu_base;
+static void emev2_smu_write(unsigned long value, int offs)
+{
+        BUG_ON(!smu_base || (offs >= PAGE_SIZE));
+        iowrite32(value, smu_base + offs);
+}
+void emev2_set_boot_vector(unsigned long value)
+{
+        emev2_smu_write(value, SMU_GENERAL_REG0);
+}
+static struct clk_mapping smu_mapping = {
+        .phys   = EMEV2_SMU_BASE,
+        .len    = PAGE_SIZE,
+};
+/* Fixed 32 KHz root clock from C32K pin */
+static struct clk c32k_clk = {
+        .rate           = 32768,
+        .mapping        = &smu_mapping,
+};
+/* PLL3 multiplies C32K with 7000 */
+static unsigned long pll3_recalc(struct clk *clk)
+{
+        return clk->parent->rate * 7000;
+}
+static struct sh_clk_ops pll3_clk_ops = {
+        .recalc         = pll3_recalc,
+};
+static struct clk pll3_clk = {
+        .ops            = &pll3_clk_ops,
+        .parent         = &c32k_clk,
+};
+static struct clk *main_clks[] = {
+        &c32k_clk,
+        &pll3_clk,
+};
+enum { SCLKDIV_USIAU0, SCLKDIV_USIBU2, SCLKDIV_USIBU1, SCLKDIV_USIBU3,
+        SCLKDIV_NR };
+#define SCLKDIV(_reg, _shift)                   \
+{                                                               \
+        .parent         = &pll3_clk,                            \
+        .enable_reg     = IOMEM(EMEV2_SMU_BASE + (_reg)),       \
+        .enable_bit     = _shift,                               \
+}
+static struct clk sclkdiv_clks[SCLKDIV_NR] = {
+        [SCLKDIV_USIAU0] = SCLKDIV(USIAU0SCLKDIV, 0),
+        [SCLKDIV_USIBU2] = SCLKDIV(USIB2SCLKDIV, 16),
+        [SCLKDIV_USIBU1] = SCLKDIV(USIB2SCLKDIV, 0),
+        [SCLKDIV_USIBU3] = SCLKDIV(USIB3SCLKDIV, 0),
+};
+enum { GCLK_USIAU0_SCLK, GCLK_USIBU1_SCLK, GCLK_USIBU2_SCLK, GCLK_USIBU3_SCLK,
+        GCLK_STI_SCLK,
+        GCLK_NR };
+#define GCLK_SCLK(_parent, _reg) \
+{                                                               \
+        .parent         = _parent,                              \
+        .enable_reg     = IOMEM(EMEV2_SMU_BASE + (_reg)),       \
+        .enable_bit     = 1, /* SCLK_GCC */                     \
+}
+static struct clk gclk_clks[GCLK_NR] = {
+        [GCLK_USIAU0_SCLK] = GCLK_SCLK(&sclkdiv_clks[SCLKDIV_USIAU0],
+                                       USIAU0GCLKCTRL),
+        [GCLK_USIBU1_SCLK] = GCLK_SCLK(&sclkdiv_clks[SCLKDIV_USIBU1],
+                                       USIBU1GCLKCTRL),
+        [GCLK_USIBU2_SCLK] = GCLK_SCLK(&sclkdiv_clks[SCLKDIV_USIBU2],
+                                       USIBU2GCLKCTRL),
+        [GCLK_USIBU3_SCLK] = GCLK_SCLK(&sclkdiv_clks[SCLKDIV_USIBU3],
+                                       USIBU3GCLKCTRL),
+        [GCLK_STI_SCLK] = GCLK_SCLK(&c32k_clk, STIGCLKCTRL),
+};
+static int emev2_gclk_enable(struct clk *clk)
+{
+        iowrite32(ioread32(clk->mapped_reg) | (1 << clk->enable_bit),
+                  clk->mapped_reg);
+        return 0;
+}
+static void emev2_gclk_disable(struct clk *clk)
+{
+        iowrite32(ioread32(clk->mapped_reg) & ~(1 << clk->enable_bit),
+                  clk->mapped_reg);
+}
+static struct sh_clk_ops emev2_gclk_clk_ops = {
+        .enable         = emev2_gclk_enable,
+        .disable        = emev2_gclk_disable,
+        .recalc         = followparent_recalc,
+};
+static int __init emev2_gclk_register(struct clk *clks, int nr)
+{
+        struct clk *clkp;
+        int ret = 0;
+        int k;
+        for (k = 0; !ret && (k < nr); k++) {
+                clkp = clks + k;
+                clkp->ops = &emev2_gclk_clk_ops;
+                ret |= clk_register(clkp);
+        }
+        return ret;
+}
+static unsigned long emev2_sclkdiv_recalc(struct clk *clk)
+{
+        unsigned int sclk_div;
+        sclk_div = (ioread32(clk->mapped_reg) >> clk->enable_bit) & 0xff;
+        return clk->parent->rate / (sclk_div + 1);
+}
+static struct sh_clk_ops emev2_sclkdiv_clk_ops = {
+        .recalc         = emev2_sclkdiv_recalc,
+};
+static int __init emev2_sclkdiv_register(struct clk *clks, int nr)
+{
+        struct clk *clkp;
+        int ret = 0;
+        int k;
+        for (k = 0; !ret && (k < nr); k++) {
+                clkp = clks + k;
+                clkp->ops = &emev2_sclkdiv_clk_ops;
+                ret |= clk_register(clkp);
+        }
+        return ret;
+}
+static struct clk_lookup lookups[] = {
+        CLKDEV_DEV_ID("serial8250-em.0", &gclk_clks[GCLK_USIAU0_SCLK]),
+        CLKDEV_DEV_ID("e1020000.uart", &gclk_clks[GCLK_USIAU0_SCLK]),
+        CLKDEV_DEV_ID("serial8250-em.1", &gclk_clks[GCLK_USIBU1_SCLK]),
+        CLKDEV_DEV_ID("e1030000.uart", &gclk_clks[GCLK_USIBU1_SCLK]),
+        CLKDEV_DEV_ID("serial8250-em.2", &gclk_clks[GCLK_USIBU2_SCLK]),
+        CLKDEV_DEV_ID("e1040000.uart", &gclk_clks[GCLK_USIBU2_SCLK]),
+        CLKDEV_DEV_ID("serial8250-em.3", &gclk_clks[GCLK_USIBU3_SCLK]),
+        CLKDEV_DEV_ID("e1050000.uart", &gclk_clks[GCLK_USIBU3_SCLK]),
+        CLKDEV_DEV_ID("em_sti.0", &gclk_clks[GCLK_STI_SCLK]),
+        CLKDEV_DEV_ID("e0180000.sti", &gclk_clks[GCLK_STI_SCLK]),
+};
+void __init emev2_clock_init(void)
+{
+        int k, ret = 0;
+        static int is_setup;
+        /* yuck, this is ugly as hell, but the non-smp case of clocks
+         * code is now designed to rely on ioremap() instead of static
+         * entity maps. in the case of smp we need access to the SMU
+         * register earlier than ioremap() is actually working without
+         * any static maps. to enable SMP in ugly but with dynamic
+         * mappings we have to call emev2_clock_init() from different
+         * places depending on UP and SMP...
+         */
+        if (is_setup++)
+                return;
+        smu_base = ioremap(EMEV2_SMU_BASE, PAGE_SIZE);
+        BUG_ON(!smu_base);
+        /* setup STI timer to run on 37.768 kHz and deassert reset */
+        emev2_smu_write(0, STI_CLKSEL);
+        emev2_smu_write(1, STI_RSTCTRL);
+        /* deassert reset for UART0->UART3 */
+        emev2_smu_write(2, USIAU0_RSTCTRL);
+        emev2_smu_write(2, USIBU1_RSTCTRL);
+        emev2_smu_write(2, USIBU2_RSTCTRL);
+        emev2_smu_write(2, USIBU3_RSTCTRL);
+        for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
+                ret = clk_register(main_clks[k]);
+        if (!ret)
+                ret = emev2_sclkdiv_register(sclkdiv_clks, SCLKDIV_NR);
+        if (!ret)
+                ret = emev2_gclk_register(gclk_clks, GCLK_NR);
+        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
+        if (!ret)
+                shmobile_clk_init();
+        else
+                panic("failed to setup emev2 clocks\n");
+}
diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c
index 99c4d743a99c..26eea5f21054 100644
--- a/arch/arm/mach-shmobile/clock-r8a7740.c
+++ b/arch/arm/mach-shmobile/clock-r8a7740.c
@@ -47,6 +47,7 @@
 #define PLLC01CR        0xe6150028
 #define SUBCKCR         0xe6150080
+#define USBCKCR         0xe615008c
 #define MSTPSR0         0xe6150030
 #define MSTPSR1         0xe6150038
@@ -181,6 +182,95 @@ static struct clk pllc1_div2_clk = {
        .parent         = &pllc1_clk,
 };
+/* USB clock */
+static struct clk *usb24s_parents[] = {
+        [0] = &system_clk,
+        [1] = &extal2_clk
+};
+static int usb24s_enable(struct clk *clk)
+{
+        __raw_writel(__raw_readl(USBCKCR) & ~(1 << 8), USBCKCR);
+        return 0;
+}
+static void usb24s_disable(struct clk *clk)
+{
+        __raw_writel(__raw_readl(USBCKCR) | (1 << 8), USBCKCR);
+}
+static int usb24s_set_parent(struct clk *clk, struct clk *parent)
+{
+        int i, ret;
+        u32 val;
+        if (!clk->parent_table || !clk->parent_num)
+                return -EINVAL;
+        /* Search the parent */
+        for (i = 0; i < clk->parent_num; i++)
+                if (clk->parent_table[i] == parent)
+                        break;
+        if (i == clk->parent_num)
+                return -ENODEV;
+        ret = clk_reparent(clk, parent);
+        if (ret < 0)
+                return ret;
+        val = __raw_readl(USBCKCR);
+        val &= ~(1 << 7);
+        val |= i << 7;
+        __raw_writel(val, USBCKCR);
+        return 0;
+}
+static struct sh_clk_ops usb24s_clk_ops = {
+        .recalc         = followparent_recalc,
+        .enable         = usb24s_enable,
+        .disable        = usb24s_disable,
+        .set_parent     = usb24s_set_parent,
+};
+static struct clk usb24s_clk = {
+        .ops            = &usb24s_clk_ops,
+        .parent_table   = usb24s_parents,
+        .parent_num     = ARRAY_SIZE(usb24s_parents),
+        .parent         = &system_clk,
+};
+static unsigned long usb24_recalc(struct clk *clk)
+{
+        return clk->parent->rate /
+                ((__raw_readl(USBCKCR) & (1 << 6)) ? 1 : 2);
+};
+static int usb24_set_rate(struct clk *clk, unsigned long rate)
+{
+        u32 val;
+        /* closer to which ? parent->rate or parent->rate/2 */
+        val = __raw_readl(USBCKCR);
+        val &= ~(1 << 6);
+        val |= (rate > (clk->parent->rate / 4) * 3) << 6;
+        __raw_writel(val, USBCKCR);
+        return 0;
+}
+static struct sh_clk_ops usb24_clk_ops = {
+        .recalc         = usb24_recalc,
+        .set_rate       = usb24_set_rate,
+};
+static struct clk usb24_clk = {
+        .ops            = &usb24_clk_ops,
+        .parent         = &usb24s_clk,
+};
 struct clk *main_clks[] = {
        &extalr_clk,
        &extal1_clk,
@@ -196,6 +286,8 @@ struct clk *main_clks[] = {
        &pllc0_clk,
        &pllc1_clk,
        &pllc1_div2_clk,
+        &usb24s_clk,
+        &usb24_clk,
 };
 static void div4_kick(struct clk *clk)
@@ -223,7 +315,7 @@ static struct clk_div4_table div4_table = {
 enum {
        DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_HP,
-        DIV4_HPP, DIV4_S, DIV4_ZB, DIV4_M3, DIV4_CP,
+        DIV4_HPP, DIV4_USBP, DIV4_S, DIV4_ZB, DIV4_M3, DIV4_CP,
        DIV4_NR
 };
@@ -234,6 +326,7 @@ struct clk div4_clks[DIV4_NR] = {
        [DIV4_M1]       = SH_CLK_DIV4(&pllc1_clk, FRQCRA,  4, 0x6fff, CLK_ENABLE_ON_INIT),
        [DIV4_HP]       = SH_CLK_DIV4(&pllc1_clk, FRQCRB,  4, 0x6fff, 0),
        [DIV4_HPP]      = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 20, 0x6fff, 0),
+        [DIV4_USBP]     = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 16, 0x6fff, 0),
        [DIV4_S]        = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 12, 0x6fff, 0),
        [DIV4_ZB]       = SH_CLK_DIV4(&pllc1_clk, FRQCRC,  8, 0x6fff, 0),
        [DIV4_M3]       = SH_CLK_DIV4(&pllc1_clk, FRQCRC,  4, 0x6fff, 0),
@@ -257,7 +350,11 @@ enum {
        MSTP222,
        MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
-        MSTP329, MSTP323,
+        MSTP329, MSTP328, MSTP323, MSTP320,
+        MSTP314, MSTP313, MSTP312,
+        MSTP309,
+        MSTP416, MSTP415, MSTP407, MSTP406,
        MSTP_NR
 };
@@ -280,7 +377,18 @@ static struct clk mstp_clks[MSTP_NR] = {
        [MSTP200] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2,  0, 0), /* SCIFA4 */
        [MSTP329] = SH_CLK_MSTP32(&r_clk,               SMSTPCR3, 29, 0), /* CMT10 */
+        [MSTP328] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR3, 28, 0), /* FSI */
        [MSTP323] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR3, 23, 0), /* IIC1 */
+        [MSTP320] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR3, 20, 0), /* USBF */
+        [MSTP314] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR3, 14, 0), /* SDHI0 */
+        [MSTP313] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR3, 13, 0), /* SDHI1 */
+        [MSTP312] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR3, 12, 0), /* MMC */
+        [MSTP309] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR3,  9, 0), /* GEther */
+        [MSTP416] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR4, 16, 0), /* USBHOST */
+        [MSTP415] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR4, 15, 0), /* SDHI2 */
+        [MSTP407] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR4,  7, 0), /* USB-Func */
+        [MSTP406] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR4,  6, 0), /* USB Phy */
 };
 static struct clk_lookup lookups[] = {
@@ -299,6 +407,7 @@ static struct clk_lookup lookups[] = {
        CLKDEV_CON_ID("pllc0_clk",              &pllc0_clk),
        CLKDEV_CON_ID("pllc1_clk",              &pllc1_clk),
        CLKDEV_CON_ID("pllc1_div2_clk",         &pllc1_div2_clk),
+        CLKDEV_CON_ID("usb24s",                 &usb24s_clk),
        /* DIV4 clocks */
        CLKDEV_CON_ID("i_clk",                  &div4_clks[DIV4_I]),
@@ -334,7 +443,22 @@ static struct clk_lookup lookups[] = {
        CLKDEV_DEV_ID("sh-sci.6",               &mstp_clks[MSTP230]),
        CLKDEV_DEV_ID("sh_cmt.10",              &mstp_clks[MSTP329]),
+        CLKDEV_DEV_ID("sh_fsi2",                &mstp_clks[MSTP328]),
        CLKDEV_DEV_ID("i2c-sh_mobile.1",        &mstp_clks[MSTP323]),
+        CLKDEV_DEV_ID("renesas_usbhs",          &mstp_clks[MSTP320]),
+        CLKDEV_DEV_ID("sh_mobile_sdhi.0",       &mstp_clks[MSTP314]),
+        CLKDEV_DEV_ID("sh_mobile_sdhi.1",       &mstp_clks[MSTP313]),
+        CLKDEV_DEV_ID("sh_mmcif",               &mstp_clks[MSTP312]),
+        CLKDEV_DEV_ID("sh-eth",                 &mstp_clks[MSTP309]),
+        CLKDEV_DEV_ID("sh_mobile_sdhi.2",       &mstp_clks[MSTP415]),
+        /* ICK */
+        CLKDEV_ICK_ID("host",   "renesas_usbhs",        &mstp_clks[MSTP416]),
+        CLKDEV_ICK_ID("func",   "renesas_usbhs",        &mstp_clks[MSTP407]),
+        CLKDEV_ICK_ID("phy",    "renesas_usbhs",        &mstp_clks[MSTP406]),
+        CLKDEV_ICK_ID("pci",    "renesas_usbhs",        &div4_clks[DIV4_USBP]),
+        CLKDEV_ICK_ID("usb24",  "renesas_usbhs",        &usb24_clk),
 };
 void __init r8a7740_clock_init(u8 md_ck)
diff --git a/arch/arm/mach-shmobile/headsmp.S b/arch/arm/mach-shmobile/headsmp.S
index 6ac015c89206..b202c1272526 100644
--- a/arch/arm/mach-shmobile/headsmp.S
+++ b/arch/arm/mach-shmobile/headsmp.S
@@ -16,6 +16,59 @@
        __CPUINIT
+/* Cache invalidation nicked from arch/arm/mach-imx/head-v7.S, thanks!
+ *
+ * The secondary kernel init calls v7_flush_dcache_all before it enables
+ * the L1; however, the L1 comes out of reset in an undefined state, so
+ * the clean + invalidate performed by v7_flush_dcache_all causes a bunch
+ * of cache lines with uninitialized data and uninitialized tags to get
+ * written out to memory, which does really unpleasant things to the main
+ * processor.  We fix this by performing an invalidate, rather than a
+ * clean + invalidate, before jumping into the kernel.
+ *
+ * This funciton is cloned from arch/arm/mach-tegra/headsmp.S, and needs
+ * to be called for both secondary cores startup and primary core resume
+ * procedures.  Ideally, it should be moved into arch/arm/mm/cache-v7.S.
+ */
+ENTRY(v7_invalidate_l1)
+        mov     r0, #0
+        mcr     p15, 0, r0, c7, c5, 0   @ invalidate I cache
+        mcr     p15, 2, r0, c0, c0, 0
+        mrc     p15, 1, r0, c0, c0, 0
+        ldr     r1, =0x7fff
+        and     r2, r1, r0, lsr #13
+        ldr     r1, =0x3ff
+        and     r3, r1, r0, lsr #3      @ NumWays - 1
+        add     r2, r2, #1              @ NumSets
+        and     r0, r0, #0x7
+        add     r0, r0, #4      @ SetShift
+        clz     r1, r3          @ WayShift
+        add     r4, r3, #1      @ NumWays
+1:      sub     r2, r2, #1      @ NumSets--
+        mov     r3, r4          @ Temp = NumWays
+2:      subs    r3, r3, #1      @ Temp--
+        mov     r5, r3, lsl r1
+        mov     r6, r2, lsl r0
+        orr     r5, r5, r6      @ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
+        mcr     p15, 0, r5, c7, c6, 2
+        bgt     2b
+        cmp     r2, #0
+        bgt     1b
+        dsb
+        isb
+        mov     pc, lr
+ENDPROC(v7_invalidate_l1)
+ENTRY(shmobile_invalidate_start)
+        bl      v7_invalidate_l1
+        b       secondary_startup
+ENDPROC(shmobile_invalidate_start)
 /*
 * Reset vector for secondary CPUs.
 * This will be mapped at address 0 by SBAR register.
@@ -24,4 +77,5 @@
        .align  12
 ENTRY(shmobile_secondary_vector)
        ldr     pc, 1f
-1:      .long   secondary_startup - PAGE_OFFSET + PLAT_PHYS_OFFSET
+1:      .long   shmobile_invalidate_start - PAGE_OFFSET + PLAT_PHYS_OFFSET
+ENDPROC(shmobile_secondary_vector)
diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h
index 83ad3fe0a75f..ff5f12fd742f 100644
--- a/arch/arm/mach-shmobile/include/mach/common.h
+++ b/arch/arm/mach-shmobile/include/mach/common.h
@@ -3,8 +3,9 @@
 extern void shmobile_earlytimer_init(void);
 extern struct sys_timer shmobile_timer;
+extern void shmobile_setup_delay(unsigned int max_cpu_core_mhz,
+                                 unsigned int mult, unsigned int div);
 struct twd_local_timer;
-void shmobile_twd_init(struct twd_local_timer *twd_local_timer);
 extern void shmobile_setup_console(void);
 extern void shmobile_secondary_vector(void);
 extern int shmobile_platform_cpu_kill(unsigned int cpu);
@@ -82,5 +83,6 @@ extern int r8a7779_platform_cpu_kill(unsigned int cpu);
 extern void r8a7779_secondary_init(unsigned int cpu);
 extern int r8a7779_boot_secondary(unsigned int cpu);
 extern void r8a7779_smp_prepare_cpus(void);
+extern void r8a7779_register_twd(void);
 #endif /* __ARCH_MACH_COMMON_H */
diff --git a/arch/arm/mach-shmobile/include/mach/emev2.h b/arch/arm/mach-shmobile/include/mach/emev2.h
new file mode 100644
index 000000000000..e6b0c1bf4b7e
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/emev2.h
@@ -0,0 +1,19 @@
+#ifndef __ASM_EMEV2_H__
+#define __ASM_EMEV2_H__
+extern void emev2_map_io(void);
+extern void emev2_init_irq(void);
+extern void emev2_add_early_devices(void);
+extern void emev2_add_standard_devices(void);
+extern void emev2_clock_init(void);
+extern void emev2_set_boot_vector(unsigned long value);
+extern unsigned int emev2_get_core_count(void);
+extern int emev2_platform_cpu_kill(unsigned int cpu);
+extern void emev2_secondary_init(unsigned int cpu);
+extern int emev2_boot_secondary(unsigned int cpu);
+extern void emev2_smp_prepare_cpus(void);
+#define EMEV2_GPIO_BASE 200
+#define EMEV2_GPIO_IRQ(n) (EMEV2_GPIO_BASE + (n))
+#endif /* __ASM_EMEV2_H__ */
diff --git a/arch/arm/mach-shmobile/include/mach/intc.h b/arch/arm/mach-shmobile/include/mach/intc.h
index 8b22258c8caa..a5603c76cfe0 100644
--- a/arch/arm/mach-shmobile/include/mach/intc.h
+++ b/arch/arm/mach-shmobile/include/mach/intc.h
@@ -142,6 +142,50 @@ static struct intc_desc p ## _desc __initdata = {			\
                             p ## _sense_registers, p ## _ack_registers) \
 }
+#define INTC_IRQ_PINS_16H(p, base, vect, str)                           \
+                                                                        \
+static struct resource p ## _resources[] __initdata = {                 \
+        [0] = {                                                         \
+                .start  = base,                                         \
+                .end    = base + 0x64,                                  \
+                .flags  = IORESOURCE_MEM,                               \
+        },                                                              \
+};                                                                      \
+                                                                        \
+enum {                                                                  \
+        p ## _UNUSED = 0,                                               \
+        INTC_IRQ_PINS_ENUM_16H(p),                                      \
+};                                                                      \
+                                                                        \
+static struct intc_vect p ## _vectors[] __initdata = {                  \
+        INTC_IRQ_PINS_VECT_16H(p, vect),                                \
+};                                                                      \
+                                                                        \
+static struct intc_mask_reg p ## _mask_registers[] __initdata = {       \
+        INTC_IRQ_PINS_MASK_16H(p, base),                                \
+};                                                                      \
+                                                                        \
+static struct intc_prio_reg p ## _prio_registers[] __initdata = {       \
+        INTC_IRQ_PINS_PRIO_16H(p, base),                                \
+};                                                                      \
+                                                                        \
+static struct intc_sense_reg p ## _sense_registers[] __initdata = {     \
+        INTC_IRQ_PINS_SENSE_16H(p, base),                               \
+};                                                                      \
+                                                                        \
+static struct intc_mask_reg p ## _ack_registers[] __initdata = {        \
+        INTC_IRQ_PINS_ACK_16H(p, base),                                 \
+};                                                                      \
+                                                                        \
+static struct intc_desc p ## _desc __initdata = {                       \
+        .name = str,                                                    \
+        .resource = p ## _resources,                                    \
+        .num_resources = ARRAY_SIZE(p ## _resources),                   \
+        .hw = INTC_HW_DESC(p ## _vectors, NULL,                         \
+                             p ## _mask_registers, p ## _prio_registers, \
+                             p ## _sense_registers, p ## _ack_registers) \
+}
 #define INTC_IRQ_PINS_32(p, base, vect, str)                            \
                                                                        \
 static struct resource p ## _resources[] __initdata = {                 \
diff --git a/arch/arm/mach-shmobile/include/mach/irqs.h b/arch/arm/mach-shmobile/include/mach/irqs.h
index 4e686cc201fc..06a5da3c3050 100644
--- a/arch/arm/mach-shmobile/include/mach/irqs.h
+++ b/arch/arm/mach-shmobile/include/mach/irqs.h
@@ -7,7 +7,7 @@
 #define gic_spi(nr)             ((nr) + 32)
 /* INTCS */
-#define INTCS_VECT_BASE         0x2200
+#define INTCS_VECT_BASE         0x3400
 #define INTCS_VECT(n, vect)     INTC_VECT((n), INTCS_VECT_BASE + (vect))
 #define intcs_evt2irq(evt)      evt2irq(INTCS_VECT_BASE + (evt))
diff --git a/arch/arm/mach-shmobile/include/mach/sh7372.h b/arch/arm/mach-shmobile/include/mach/sh7372.h
index 8254ab86f6cd..915d0093da08 100644
--- a/arch/arm/mach-shmobile/include/mach/sh7372.h
+++ b/arch/arm/mach-shmobile/include/mach/sh7372.h
@@ -457,6 +457,8 @@ enum {
        SHDMA_SLAVE_SDHI1_TX,
        SHDMA_SLAVE_SDHI2_RX,
        SHDMA_SLAVE_SDHI2_TX,
+        SHDMA_SLAVE_FSIA_RX,
+        SHDMA_SLAVE_FSIA_TX,
        SHDMA_SLAVE_MMCIF_RX,
        SHDMA_SLAVE_MMCIF_TX,
        SHDMA_SLAVE_USB0_TX,
diff --git a/arch/arm/mach-shmobile/include/mach/sh73a0.h b/arch/arm/mach-shmobile/include/mach/sh73a0.h
index cad57578ceed..398e2c10913b 100644
--- a/arch/arm/mach-shmobile/include/mach/sh73a0.h
+++ b/arch/arm/mach-shmobile/include/mach/sh73a0.h
@@ -482,6 +482,9 @@ enum {
        GPIO_FN_FSIAILR_PU,
        GPIO_FN_FSIAIBT_PU,
        GPIO_FN_FSIAISLD_PU,
+        /* end of GPIO */
+        GPIO_NR,
 };
 /* DMA slave IDs */
@@ -515,8 +518,36 @@ enum {
        SHDMA_SLAVE_MMCIF_RX,
 };
-/* PINT interrupts are located at Linux IRQ 800 and up */
+/*
-#define SH73A0_PINT0_IRQ(irq) ((irq) + 800)
+ *              SH73A0 IRQ LOCATION TABLE
-#define SH73A0_PINT1_IRQ(irq) ((irq) + 832)
+ *
+ * 416  -----------------------------------------
+ *              IRQ0-IRQ15
+ * 431  -----------------------------------------
+ * ...
+ * 448  -----------------------------------------
+ *              sh73a0-intcs
+ *              sh73a0-intca-irq-pins
+ * 680  -----------------------------------------
+ * ...
+ * 700  -----------------------------------------
+ *              sh73a0-pint0
+ * 731  -----------------------------------------
+ * 732  -----------------------------------------
+ *              sh73a0-pint1
+ * 739  -----------------------------------------
+ * ...
+ * 800  -----------------------------------------
+ *              IRQ16-IRQ31
+ * 815  -----------------------------------------
+ * ...
+ * 928  -----------------------------------------
+ *              sh73a0-intca-irq-pins
+ * 943  -----------------------------------------
+ */
+/* PINT interrupts are located at Linux IRQ 700 and up */
+#define SH73A0_PINT0_IRQ(irq) ((irq) + 700)
+#define SH73A0_PINT1_IRQ(irq) ((irq) + 732)
 #endif /* __ASM_SH73A0_H__ */
diff --git a/arch/arm/mach-shmobile/intc-sh7372.c b/arch/arm/mach-shmobile/intc-sh7372.c
index 6447e0af52d4..2587a22842f2 100644
--- a/arch/arm/mach-shmobile/intc-sh7372.c
+++ b/arch/arm/mach-shmobile/intc-sh7372.c
@@ -19,6 +19,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
+#include <linux/module.h>
 #include <linux/irq.h>
 #include <linux/io.h>
 #include <linux/sh_intc.h>
@@ -305,14 +306,16 @@ static DECLARE_INTC_DESC(intca_desc, "sh7372-intca",
                         intca_mask_registers, intca_prio_registers,
                         NULL);
-INTC_IRQ_PINS_32(intca_irq_pins, 0xe6900000,
+INTC_IRQ_PINS_16(intca_irq_pins_lo, 0xe6900000,
-                 INTC_VECT, "sh7372-intca-irq-pins");
+                 INTC_VECT, "sh7372-intca-irq-lo");
+INTC_IRQ_PINS_16H(intca_irq_pins_hi, 0xe6900000,
+                 INTC_VECT, "sh7372-intca-irq-hi");
 enum {
        UNUSED_INTCS = 0,
        ENABLED_INTCS,
-        INTCS,
        /* interrupt sources INTCS */
        /* IRQ0S - IRQ31S */
@@ -426,8 +429,6 @@ static struct intc_vect intcs_vectors[] = {
        INTCS_VECT(CPORTS2R, 0x1a20),
        /* CEC */
        INTCS_VECT(JPU6E, 0x1a80),
-        INTC_VECT(INTCS, 0xf80),
 };
 static struct intc_group intcs_groups[] __initdata = {
@@ -490,9 +491,6 @@ static struct intc_mask_reg intcs_mask_registers[] = {
        { 0xffd5019c, 0xffd501dc, 8, /* IMR7SA3 / IMCR7SA3 */
          { MFIS2_INTCS, CPORTS2R, 0, 0,
            JPU6E, 0, 0, 0 } },
-        { 0xffd20104, 0, 16, /* INTAMASK */
-          { 0, 0, 0, 0, 0, 0, 0, 0,
-            0, 0, 0, 0, 0, 0, 0, INTCS } },
 };
 /* Priority is needed for INTCA to receive the INTCS interrupt */
@@ -557,18 +555,30 @@ static void __iomem *intcs_ffd5;
 void __init sh7372_init_irq(void)
 {
        void __iomem *intevtsa;
+        int n;
        intcs_ffd2 = ioremap_nocache(0xffd20000, PAGE_SIZE);
        intevtsa = intcs_ffd2 + 0x100;
        intcs_ffd5 = ioremap_nocache(0xffd50000, PAGE_SIZE);
        register_intc_controller(&intca_desc);
-        register_intc_controller(&intca_irq_pins_desc);
+        register_intc_controller(&intca_irq_pins_lo_desc);
+        register_intc_controller(&intca_irq_pins_hi_desc);
        register_intc_controller(&intcs_desc);
+        /* setup dummy cascade chip for INTCS */
+        n = evt2irq(0xf80);
+        irq_alloc_desc_at(n, numa_node_id());
+        irq_set_chip_and_handler_name(n, &dummy_irq_chip,
+                                      handle_level_irq, "level");
+        set_irq_flags(n, IRQF_VALID); /* yuck */
        /* demux using INTEVTSA */
-        irq_set_handler_data(evt2irq(0xf80), (void *)intevtsa);
+        irq_set_handler_data(n, (void *)intevtsa);
-        irq_set_chained_handler(evt2irq(0xf80), intcs_demux);
+        irq_set_chained_handler(n, intcs_demux);
+        /* unmask INTCS in INTAMASK */
+        iowrite16(0, intcs_ffd2 + 0x104);
 }
 static unsigned short ffd2[0x200];
diff --git a/arch/arm/mach-shmobile/pfc-r8a7740.c b/arch/arm/mach-shmobile/pfc-r8a7740.c
index a4fff6950b03..670fe1869dbc 100644
--- a/arch/arm/mach-shmobile/pfc-r8a7740.c
+++ b/arch/arm/mach-shmobile/pfc-r8a7740.c
@@ -22,6 +22,7 @@
 #include <linux/kernel.h>
 #include <linux/gpio.h>
 #include <mach/r8a7740.h>
+#include <mach/irqs.h>
 #define CPU_ALL_PORT(fn, pfx, sfx)                                      \
        PORT_10(fn, pfx, sfx),          PORT_90(fn, pfx, sfx),          \
@@ -2527,6 +2528,41 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
        { },
 };
+static struct pinmux_irq pinmux_irqs[] = {
+        PINMUX_IRQ(evt2irq(0x0200), PORT2_FN0,   PORT13_FN0),   /* IRQ0A */
+        PINMUX_IRQ(evt2irq(0x0220), PORT20_FN0),                /* IRQ1A */
+        PINMUX_IRQ(evt2irq(0x0240), PORT11_FN0,  PORT12_FN0),   /* IRQ2A */
+        PINMUX_IRQ(evt2irq(0x0260), PORT10_FN0,  PORT14_FN0),   /* IRQ3A */
+        PINMUX_IRQ(evt2irq(0x0280), PORT15_FN0,  PORT172_FN0),  /* IRQ4A */
+        PINMUX_IRQ(evt2irq(0x02A0), PORT0_FN0,   PORT1_FN0),    /* IRQ5A */
+        PINMUX_IRQ(evt2irq(0x02C0), PORT121_FN0, PORT173_FN0),  /* IRQ6A */
+        PINMUX_IRQ(evt2irq(0x02E0), PORT120_FN0, PORT209_FN0),  /* IRQ7A */
+        PINMUX_IRQ(evt2irq(0x0300), PORT119_FN0),               /* IRQ8A */
+        PINMUX_IRQ(evt2irq(0x0320), PORT118_FN0, PORT210_FN0),  /* IRQ9A */
+        PINMUX_IRQ(evt2irq(0x0340), PORT19_FN0),                /* IRQ10A */
+        PINMUX_IRQ(evt2irq(0x0360), PORT104_FN0),               /* IRQ11A */
+        PINMUX_IRQ(evt2irq(0x0380), PORT42_FN0,  PORT97_FN0),   /* IRQ12A */
+        PINMUX_IRQ(evt2irq(0x03A0), PORT64_FN0,  PORT98_FN0),   /* IRQ13A */
+        PINMUX_IRQ(evt2irq(0x03C0), PORT63_FN0,  PORT99_FN0),   /* IRQ14A */
+        PINMUX_IRQ(evt2irq(0x03E0), PORT62_FN0,  PORT100_FN0),  /* IRQ15A */
+        PINMUX_IRQ(evt2irq(0x3200), PORT68_FN0,  PORT211_FN0),  /* IRQ16A */
+        PINMUX_IRQ(evt2irq(0x3220), PORT69_FN0),                /* IRQ17A */
+        PINMUX_IRQ(evt2irq(0x3240), PORT70_FN0),                /* IRQ18A */
+        PINMUX_IRQ(evt2irq(0x3260), PORT71_FN0),                /* IRQ19A */
+        PINMUX_IRQ(evt2irq(0x3280), PORT67_FN0),                /* IRQ20A */
+        PINMUX_IRQ(evt2irq(0x32A0), PORT202_FN0),               /* IRQ21A */
+        PINMUX_IRQ(evt2irq(0x32C0), PORT95_FN0),                /* IRQ22A */
+        PINMUX_IRQ(evt2irq(0x32E0), PORT96_FN0),                /* IRQ23A */
+        PINMUX_IRQ(evt2irq(0x3300), PORT180_FN0),               /* IRQ24A */
+        PINMUX_IRQ(evt2irq(0x3320), PORT38_FN0),                /* IRQ25A */
+        PINMUX_IRQ(evt2irq(0x3340), PORT58_FN0,  PORT81_FN0),   /* IRQ26A */
+        PINMUX_IRQ(evt2irq(0x3360), PORT57_FN0,  PORT168_FN0),  /* IRQ27A */
+        PINMUX_IRQ(evt2irq(0x3380), PORT56_FN0,  PORT169_FN0),  /* IRQ28A */
+        PINMUX_IRQ(evt2irq(0x33A0), PORT50_FN0,  PORT170_FN0),  /* IRQ29A */
+        PINMUX_IRQ(evt2irq(0x33C0), PORT49_FN0,  PORT171_FN0),  /* IRQ30A */
+        PINMUX_IRQ(evt2irq(0x33E0), PORT41_FN0,  PORT167_FN0),  /* IRQ31A */
+};
 static struct pinmux_info r8a7740_pinmux_info = {
        .name           = "r8a7740_pfc",
        .reserved_id    = PINMUX_RESERVED,
@@ -2554,6 +2590,9 @@ static struct pinmux_info r8a7740_pinmux_info = {
        .gpio_data      = pinmux_data,
        .gpio_data_size = ARRAY_SIZE(pinmux_data),
+        .gpio_irq       = pinmux_irqs,
+        .gpio_irq_size  = ARRAY_SIZE(pinmux_irqs),
 };
 void r8a7740_pinmux_init(void)
diff --git a/arch/arm/mach-shmobile/pfc-sh73a0.c b/arch/arm/mach-shmobile/pfc-sh73a0.c
index e05634ce2e0d..4a547b803268 100644
--- a/arch/arm/mach-shmobile/pfc-sh73a0.c
+++ b/arch/arm/mach-shmobile/pfc-sh73a0.c
@@ -829,14 +829,14 @@ static pinmux_enum_t pinmux_data[] = {
        PINMUX_DATA(PORT27_I2C_SCL2_MARK, PORT27_FN2, MSEL2CR_MSEL17_0,
                MSEL2CR_MSEL16_1), \
        PINMUX_DATA(PORT27_I2C_SCL3_MARK, PORT27_FN3, MSEL2CR_MSEL19_0,
-                MSEL2CR_MSEL18_0), \
+                MSEL2CR_MSEL18_1), \
        PINMUX_DATA(MFG0_OUT1_MARK, PORT27_FN4), \
        PINMUX_DATA(PORT27_IROUT_MARK, PORT27_FN7),
        PINMUX_DATA(XDVFS2_MARK, PORT28_FN1), \
        PINMUX_DATA(PORT28_I2C_SDA2_MARK, PORT28_FN2, MSEL2CR_MSEL17_0,
                MSEL2CR_MSEL16_1), \
        PINMUX_DATA(PORT28_I2C_SDA3_MARK, PORT28_FN3, MSEL2CR_MSEL19_0,
-                MSEL2CR_MSEL18_0), \
+                MSEL2CR_MSEL18_1), \
        PINMUX_DATA(PORT28_TPU1TO1_MARK, PORT28_FN7),
        PINMUX_DATA(SIM_RST_MARK, PORT29_FN1), \
        PINMUX_DATA(PORT29_TPU1TO1_MARK, PORT29_FN4),
diff --git a/arch/arm/mach-shmobile/platsmp.c b/arch/arm/mach-shmobile/platsmp.c
index 45fa3924c6a1..bacdd667e3b1 100644
--- a/arch/arm/mach-shmobile/platsmp.c
+++ b/arch/arm/mach-shmobile/platsmp.c
@@ -16,12 +16,16 @@
 #include <linux/device.h>
 #include <linux/smp.h>
 #include <linux/io.h>
+#include <linux/of.h>
 #include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 #include <mach/common.h>
+#include <mach/emev2.h>
-#define is_sh73a0() (machine_is_ag5evm() || machine_is_kota2())
+#define is_sh73a0() (machine_is_ag5evm() || machine_is_kota2() || \
+                        of_machine_is_compatible("renesas,sh73a0"))
 #define is_r8a7779() machine_is_marzen()
+#define is_emev2() of_machine_is_compatible("renesas,emev2")
 static unsigned int __init shmobile_smp_get_core_count(void)
 {
@@ -31,6 +35,9 @@ static unsigned int __init shmobile_smp_get_core_count(void)
        if (is_r8a7779())
                return r8a7779_get_core_count();
+        if (is_emev2())
+                return emev2_get_core_count();
        return 1;
 }
@@ -41,6 +48,9 @@ static void __init shmobile_smp_prepare_cpus(void)
        if (is_r8a7779())
                r8a7779_smp_prepare_cpus();
+        if (is_emev2())
+                emev2_smp_prepare_cpus();
 }
 int shmobile_platform_cpu_kill(unsigned int cpu)
@@ -48,6 +58,9 @@ int shmobile_platform_cpu_kill(unsigned int cpu)
        if (is_r8a7779())
                return r8a7779_platform_cpu_kill(cpu);
+        if (is_emev2())
+                return emev2_platform_cpu_kill(cpu);
        return 1;
 }
@@ -60,6 +73,9 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
        if (is_r8a7779())
                r8a7779_secondary_init(cpu);
+        if (is_emev2())
+                emev2_secondary_init(cpu);
 }
 int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
@@ -70,6 +86,9 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
        if (is_r8a7779())
                return r8a7779_boot_secondary(cpu);
+        if (is_emev2())
+                return emev2_boot_secondary(cpu);
        return -ENOSYS;
 }
diff --git a/arch/arm/mach-shmobile/setup-emev2.c b/arch/arm/mach-shmobile/setup-emev2.c
new file mode 100644
index 000000000000..dae9aa68bb09
--- /dev/null
+++ b/arch/arm/mach-shmobile/setup-emev2.c
@@ -0,0 +1,452 @@
+/*
+ * Emma Mobile EV2 processor support
+ *
+ * Copyright (C) 2012  Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/platform_device.h>
+#include <linux/platform_data/gpio-em.h>
+#include <linux/of_platform.h>
+#include <linux/delay.h>
+#include <linux/input.h>
+#include <linux/io.h>
+#include <linux/of_irq.h>
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/emev2.h>
+#include <mach/irqs.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/time.h>
+#include <asm/hardware/gic.h>
+static struct map_desc emev2_io_desc[] __initdata = {
+#ifdef CONFIG_SMP
+        /* 128K entity map for 0xe0100000 (SMU) */
+        {
+                .virtual        = 0xe0100000,
+                .pfn            = __phys_to_pfn(0xe0100000),
+                .length         = SZ_128K,
+                .type           = MT_DEVICE
+        },
+        /* 2M mapping for SCU + L2 controller */
+        {
+                .virtual        = 0xf0000000,
+                .pfn            = __phys_to_pfn(0x1e000000),
+                .length         = SZ_2M,
+                .type           = MT_DEVICE
+        },
+#endif
+};
+void __init emev2_map_io(void)
+{
+        iotable_init(emev2_io_desc, ARRAY_SIZE(emev2_io_desc));
+}
+/* UART */
+static struct resource uart0_resources[] = {
+        [0]     = {
+                .start  = 0xe1020000,
+                .end    = 0xe1020037,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1]     = {
+                .start  = 40,
+                .flags  = IORESOURCE_IRQ,
+        }
+};
+static struct platform_device uart0_device = {
+        .name           = "serial8250-em",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(uart0_resources),
+        .resource       = uart0_resources,
+};
+static struct resource uart1_resources[] = {
+        [0]     = {
+                .start  = 0xe1030000,
+                .end    = 0xe1030037,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1]     = {
+                .start  = 41,
+                .flags  = IORESOURCE_IRQ,
+        }
+};
+static struct platform_device uart1_device = {
+        .name           = "serial8250-em",
+        .id             = 1,
+        .num_resources  = ARRAY_SIZE(uart1_resources),
+        .resource       = uart1_resources,
+};
+static struct resource uart2_resources[] = {
+        [0]     = {
+                .start  = 0xe1040000,
+                .end    = 0xe1040037,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1]     = {
+                .start  = 42,
+                .flags  = IORESOURCE_IRQ,
+        }
+};
+static struct platform_device uart2_device = {
+        .name           = "serial8250-em",
+        .id             = 2,
+        .num_resources  = ARRAY_SIZE(uart2_resources),
+        .resource       = uart2_resources,
+};
+static struct resource uart3_resources[] = {
+        [0]     = {
+                .start  = 0xe1050000,
+                .end    = 0xe1050037,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1]     = {
+                .start  = 43,
+                .flags  = IORESOURCE_IRQ,
+        }
+};
+static struct platform_device uart3_device = {
+        .name           = "serial8250-em",
+        .id             = 3,
+        .num_resources  = ARRAY_SIZE(uart3_resources),
+        .resource       = uart3_resources,
+};
+/* STI */
+static struct resource sti_resources[] = {
+        [0] = {
+                .name   = "STI",
+                .start  = 0xe0180000,
+                .end    = 0xe0180053,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 157,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device sti_device = {
+        .name           = "em_sti",
+        .id             = 0,
+        .resource       = sti_resources,
+        .num_resources  = ARRAY_SIZE(sti_resources),
+};
+/* GIO */
+static struct gpio_em_config gio0_config = {
+        .gpio_base = 0,
+        .irq_base = EMEV2_GPIO_IRQ(0),
+        .number_of_pins = 32,
+};
+static struct resource gio0_resources[] = {
+        [0] = {
+                .name   = "GIO_000",
+                .start  = 0xe0050000,
+                .end    = 0xe005002b,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .name   = "GIO_000",
+                .start  = 0xe0050040,
+                .end    = 0xe005005f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [2] = {
+                .start  = 99,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [3] = {
+                .start  = 100,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device gio0_device = {
+        .name           = "em_gio",
+        .id             = 0,
+        .resource       = gio0_resources,
+        .num_resources  = ARRAY_SIZE(gio0_resources),
+        .dev            = {
+                .platform_data  = &gio0_config,
+        },
+};
+static struct gpio_em_config gio1_config = {
+        .gpio_base = 32,
+        .irq_base = EMEV2_GPIO_IRQ(32),
+        .number_of_pins = 32,
+};
+static struct resource gio1_resources[] = {
+        [0] = {
+                .name   = "GIO_032",
+                .start  = 0xe0050080,
+                .end    = 0xe00500ab,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .name   = "GIO_032",
+                .start  = 0xe00500c0,
+                .end    = 0xe00500df,
+                .flags  = IORESOURCE_MEM,
+        },
+        [2] = {
+                .start  = 101,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [3] = {
+                .start  = 102,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device gio1_device = {
+        .name           = "em_gio",
+        .id             = 1,
+        .resource       = gio1_resources,
+        .num_resources  = ARRAY_SIZE(gio1_resources),
+        .dev            = {
+                .platform_data  = &gio1_config,
+        },
+};
+static struct gpio_em_config gio2_config = {
+        .gpio_base = 64,
+        .irq_base = EMEV2_GPIO_IRQ(64),
+        .number_of_pins = 32,
+};
+static struct resource gio2_resources[] = {
+        [0] = {
+                .name   = "GIO_064",
+                .start  = 0xe0050100,
+                .end    = 0xe005012b,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .name   = "GIO_064",
+                .start  = 0xe0050140,
+                .end    = 0xe005015f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [2] = {
+                .start  = 103,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [3] = {
+                .start  = 104,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device gio2_device = {
+        .name           = "em_gio",
+        .id             = 2,
+        .resource       = gio2_resources,
+        .num_resources  = ARRAY_SIZE(gio2_resources),
+        .dev            = {
+                .platform_data  = &gio2_config,
+        },
+};
+static struct gpio_em_config gio3_config = {
+        .gpio_base = 96,
+        .irq_base = EMEV2_GPIO_IRQ(96),
+        .number_of_pins = 32,
+};
+static struct resource gio3_resources[] = {
+        [0] = {
+                .name   = "GIO_096",
+                .start  = 0xe0050100,
+                .end    = 0xe005012b,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .name   = "GIO_096",
+                .start  = 0xe0050140,
+                .end    = 0xe005015f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [2] = {
+                .start  = 105,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [3] = {
+                .start  = 106,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device gio3_device = {
+        .name           = "em_gio",
+        .id             = 3,
+        .resource       = gio3_resources,
+        .num_resources  = ARRAY_SIZE(gio3_resources),
+        .dev            = {
+                .platform_data  = &gio3_config,
+        },
+};
+static struct gpio_em_config gio4_config = {
+        .gpio_base = 128,
+        .irq_base = EMEV2_GPIO_IRQ(128),
+        .number_of_pins = 31,
+};
+static struct resource gio4_resources[] = {
+        [0] = {
+                .name   = "GIO_128",
+                .start  = 0xe0050200,
+                .end    = 0xe005022b,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .name   = "GIO_128",
+                .start  = 0xe0050240,
+                .end    = 0xe005025f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [2] = {
+                .start  = 107,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [3] = {
+                .start  = 108,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device gio4_device = {
+        .name           = "em_gio",
+        .id             = 4,
+        .resource       = gio4_resources,
+        .num_resources  = ARRAY_SIZE(gio4_resources),
+        .dev            = {
+                .platform_data  = &gio4_config,
+        },
+};
+static struct platform_device *emev2_early_devices[] __initdata = {
+        &uart0_device,
+        &uart1_device,
+        &uart2_device,
+        &uart3_device,
+};
+static struct platform_device *emev2_late_devices[] __initdata = {
+        &sti_device,
+        &gio0_device,
+        &gio1_device,
+        &gio2_device,
+        &gio3_device,
+        &gio4_device,
+};
+void __init emev2_add_standard_devices(void)
+{
+        emev2_clock_init();
+        platform_add_devices(emev2_early_devices,
+                             ARRAY_SIZE(emev2_early_devices));
+        platform_add_devices(emev2_late_devices,
+                             ARRAY_SIZE(emev2_late_devices));
+}
+void __init emev2_init_delay(void)
+{
+        shmobile_setup_delay(533, 1, 3); /* Cortex-A9 @ 533MHz */
+}
+void __init emev2_add_early_devices(void)
+{
+        emev2_init_delay();
+        early_platform_add_devices(emev2_early_devices,
+                                   ARRAY_SIZE(emev2_early_devices));
+        /* setup early console here as well */
+        shmobile_setup_console();
+}
+void __init emev2_init_irq(void)
+{
+        void __iomem *gic_dist_base;
+        void __iomem *gic_cpu_base;
+        /* Static mappings, never released */
+        gic_dist_base = ioremap(0xe0028000, PAGE_SIZE);
+        gic_cpu_base = ioremap(0xe0020000, PAGE_SIZE);
+        BUG_ON(!gic_dist_base || !gic_cpu_base);
+        /* Use GIC to handle interrupts */
+        gic_init(0, 29, gic_dist_base, gic_cpu_base);
+}
+#ifdef CONFIG_USE_OF
+static const struct of_dev_auxdata emev2_auxdata_lookup[] __initconst = {
+        { }
+};
+void __init emev2_add_standard_devices_dt(void)
+{
+        of_platform_populate(NULL, of_default_bus_match_table,
+                             emev2_auxdata_lookup, NULL);
+}
+static const struct of_device_id emev2_dt_irq_match[] = {
+        { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
+        {},
+};
+static const char *emev2_boards_compat_dt[] __initdata = {
+        "renesas,emev2",
+        NULL,
+};
+void __init emev2_init_irq_dt(void)
+{
+        of_irq_init(emev2_dt_irq_match);
+}
+DT_MACHINE_START(EMEV2_DT, "Generic Emma Mobile EV2 (Flattened Device Tree)")
+        .init_early     = emev2_init_delay,
+        .nr_irqs        = NR_IRQS_LEGACY,
+        .init_irq       = emev2_init_irq_dt,
+        .handle_irq     = gic_handle_irq,
+        .init_machine   = emev2_add_standard_devices_dt,
+        .timer          = &shmobile_timer,
+        .dt_compat      = emev2_boards_compat_dt,
+MACHINE_END
+#endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
index 14edb5cffa7f..ec4eb49c1693 100644
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -18,6 +18,7 @@
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
 #include <linux/delay.h>
+#include <linux/dma-mapping.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/io.h>
@@ -60,6 +61,12 @@ static struct map_desc r8a7740_io_desc[] __initdata = {
 void __init r8a7740_map_io(void)
 {
        iotable_init(r8a7740_io_desc, ARRAY_SIZE(r8a7740_io_desc));
+        /*
+         * DMA memory at 0xff200000 - 0xffdfffff. The default 2MB size isn't
+         * enough to allocate the frame buffer memory.
+         */
+        init_consistent_dma_size(12 << 20);
 }
 /* SCIFA0 */
@@ -350,19 +357,19 @@ static void r8a7740_i2c_workaround(struct platform_device *pdev)
        i2c_write(reg, ICSTART, i2c_read(reg, ICSTART) | 0x10);
        i2c_read(reg, ICSTART); /* dummy read */
-        mdelay(100);
+        udelay(10);
        i2c_write(reg, ICCR, 0x01);
-        i2c_read(reg, ICCR);
        i2c_write(reg, ICSTART, 0x00);
-        i2c_read(reg, ICSTART);
+        udelay(10);
        i2c_write(reg, ICCR, 0x10);
-        mdelay(100);
+        udelay(10);
        i2c_write(reg, ICCR, 0x00);
-        mdelay(100);
+        udelay(10);
        i2c_write(reg, ICCR, 0x10);
-        mdelay(100);
+        udelay(10);
        iounmap(reg);
 }
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index 12c6f529ab89..e98e46f6cf55 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -262,10 +262,14 @@ void __init r8a7779_add_standard_devices(void)
                            ARRAY_SIZE(r8a7779_late_devices));
 }
+/* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
+void __init __weak r8a7779_register_twd(void) { }
 static void __init r8a7779_earlytimer_init(void)
 {
        r8a7779_clock_init();
        shmobile_earlytimer_init();
+        r8a7779_register_twd();
 }
 void __init r8a7779_add_early_devices(void)
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c
index 2fe8f83ca124..6a4bd582c028 100644
--- a/arch/arm/mach-shmobile/setup-sh7372.c
+++ b/arch/arm/mach-shmobile/setup-sh7372.c
@@ -22,6 +22,7 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/platform_device.h>
+#include <linux/of_platform.h>
 #include <linux/uio_driver.h>
 #include <linux/delay.h>
 #include <linux/input.h>
@@ -461,6 +462,16 @@ static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = {
                .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
                .mid_rid        = 0xce,
        }, {
+                .slave_id       = SHDMA_SLAVE_FSIA_TX,
+                .addr           = 0xfe1f0024,
+                .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
+                .mid_rid        = 0xb1,
+        }, {
+                .slave_id       = SHDMA_SLAVE_FSIA_RX,
+                .addr           = 0xfe1f0020,
+                .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
+                .mid_rid        = 0xb2,
+        }, {
                .slave_id       = SHDMA_SLAVE_MMCIF_TX,
                .addr           = 0xe6bd0034,
                .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
@@ -1092,3 +1103,50 @@ void __init sh7372_add_early_devices(void)
        /* override timer setup with soc-specific code */
        shmobile_timer.init = sh7372_earlytimer_init;
 }
+#ifdef CONFIG_USE_OF
+void __init sh7372_add_early_devices_dt(void)
+{
+        shmobile_setup_delay(800, 1, 3); /* Cortex-A8 @ 800MHz */
+        early_platform_add_devices(sh7372_early_devices,
+                                   ARRAY_SIZE(sh7372_early_devices));
+        /* setup early console here as well */
+        shmobile_setup_console();
+}
+static const struct of_dev_auxdata sh7372_auxdata_lookup[] __initconst = {
+        { }
+};
+void __init sh7372_add_standard_devices_dt(void)
+{
+        /* clocks are setup late during boot in the case of DT */
+        sh7372_clock_init();
+        platform_add_devices(sh7372_early_devices,
+                            ARRAY_SIZE(sh7372_early_devices));
+        of_platform_populate(NULL, of_default_bus_match_table,
+                             sh7372_auxdata_lookup, NULL);
+}
+static const char *sh7372_boards_compat_dt[] __initdata = {
+        "renesas,sh7372",
+        NULL,
+};
+DT_MACHINE_START(SH7372_DT, "Generic SH7372 (Flattened Device Tree)")
+        .map_io         = sh7372_map_io,
+        .init_early     = sh7372_add_early_devices_dt,
+        .nr_irqs        = NR_IRQS_LEGACY,
+        .init_irq       = sh7372_init_irq,
+        .handle_irq     = shmobile_handle_irq_intc,
+        .init_machine   = sh7372_add_standard_devices_dt,
+        .timer          = &shmobile_timer,
+        .dt_compat      = sh7372_boards_compat_dt,
+MACHINE_END
+#endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index 5bebffc10455..04a0dfe75493 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -688,10 +688,14 @@ void __init sh73a0_add_standard_devices(void)
                            ARRAY_SIZE(sh73a0_late_devices));
 }
+/* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
+void __init __weak sh73a0_register_twd(void) { }
 static void __init sh73a0_earlytimer_init(void)
 {
        sh73a0_clock_init();
        shmobile_earlytimer_init();
+        sh73a0_register_twd();
 }
 void __init sh73a0_add_early_devices(void)
diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c
new file mode 100644
index 000000000000..6a35c4a31e6c
--- /dev/null
+++ b/arch/arm/mach-shmobile/smp-emev2.c
@@ -0,0 +1,97 @@
+/*
+ * SMP support for Emma Mobile EV2
+ *
+ * Copyright (C) 2012  Renesas Solutions Corp.
+ * Copyright (C) 2012  Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/smp.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <mach/common.h>
+#include <mach/emev2.h>
+#include <asm/smp_plat.h>
+#include <asm/smp_scu.h>
+#include <asm/hardware/gic.h>
+#include <asm/cacheflush.h>
+#define EMEV2_SCU_BASE 0x1e000000
+static DEFINE_SPINLOCK(scu_lock);
+static void __iomem *scu_base;
+static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
+{
+        unsigned long tmp;
+        /* we assume this code is running on a different cpu
+         * than the one that is changing coherency setting */
+        spin_lock(&scu_lock);
+        tmp = readl(scu_base + 8);
+        tmp &= ~clr;
+        tmp |= set;
+        writel(tmp, scu_base + 8);
+        spin_unlock(&scu_lock);
+}
+unsigned int __init emev2_get_core_count(void)
+{
+        if (!scu_base) {
+                scu_base = ioremap(EMEV2_SCU_BASE, PAGE_SIZE);
+                emev2_clock_init(); /* need ioremapped SMU */
+        }
+        WARN_ON_ONCE(!scu_base);
+        return scu_base ? scu_get_core_count(scu_base) : 1;
+}
+int emev2_platform_cpu_kill(unsigned int cpu)
+{
+        return 0; /* not supported yet */
+}
+void __cpuinit emev2_secondary_init(unsigned int cpu)
+{
+        gic_secondary_init(0);
+}
+int __cpuinit emev2_boot_secondary(unsigned int cpu)
+{
+        cpu = cpu_logical_map(cpu);
+        /* enable cache coherency */
+        modify_scu_cpu_psr(0, 3 << (cpu * 8));
+        /* Tell ROM loader about our vector (in headsmp.S) */
+        emev2_set_boot_vector(__pa(shmobile_secondary_vector));
+        gic_raise_softirq(cpumask_of(cpu), 1);
+        return 0;
+}
+void __init emev2_smp_prepare_cpus(void)
+{
+        int cpu = cpu_logical_map(0);
+        scu_enable(scu_base);
+        /* enable cache coherency on CPU0 */
+        modify_scu_cpu_psr(0, 3 << (cpu * 8));
+}
diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c
index b62e19d4c9af..6d1d0238cbf7 100644
--- a/arch/arm/mach-shmobile/smp-r8a7779.c
+++ b/arch/arm/mach-shmobile/smp-r8a7779.c
@@ -64,8 +64,15 @@ static void __iomem *scu_base_addr(void)
 static DEFINE_SPINLOCK(scu_lock);
 static unsigned long tmp;
+#ifdef CONFIG_HAVE_ARM_TWD
 static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 0xf0000600, 29);
+void __init r8a7779_register_twd(void)
+{
+        twd_local_timer_register(&twd_local_timer);
+}
+#endif
 static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
 {
        void __iomem *scu_base = scu_base_addr();
@@ -84,7 +91,6 @@ unsigned int __init r8a7779_get_core_count(void)
 {
        void __iomem *scu_base = scu_base_addr();
-        shmobile_twd_init(&twd_local_timer);
        return scu_get_core_count(scu_base);
 }
diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c
index 14ad8b052f1a..e36c41c4ab40 100644
--- a/arch/arm/mach-shmobile/smp-sh73a0.c
+++ b/arch/arm/mach-shmobile/smp-sh73a0.c
@@ -42,7 +42,13 @@ static void __iomem *scu_base_addr(void)
 static DEFINE_SPINLOCK(scu_lock);
 static unsigned long tmp;
+#ifdef CONFIG_HAVE_ARM_TWD
 static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 0xf0000600, 29);
+void __init sh73a0_register_twd(void)
+{
+        twd_local_timer_register(&twd_local_timer);
+}
+#endif
 static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
 {
@@ -62,7 +68,6 @@ unsigned int __init sh73a0_get_core_count(void)
 {
        void __iomem *scu_base = scu_base_addr();
-        shmobile_twd_init(&twd_local_timer);
        return scu_get_core_count(scu_base);
 }
diff --git a/arch/arm/mach-shmobile/timer.c b/arch/arm/mach-shmobile/timer.c
index 2fba5f3d1c8a..a68919727e24 100644
--- a/arch/arm/mach-shmobile/timer.c
+++ b/arch/arm/mach-shmobile/timer.c
@@ -19,9 +19,27 @@
 *
 */
 #include <linux/platform_device.h>
+#include <linux/delay.h>
 #include <asm/mach/time.h>
 #include <asm/smp_twd.h>
+void __init shmobile_setup_delay(unsigned int max_cpu_core_mhz,
+                                 unsigned int mult, unsigned int div)
+{
+        /* calculate a worst-case loops-per-jiffy value
+         * based on maximum cpu core mhz setting and the
+         * __delay() implementation in arch/arm/lib/delay.S
+         *
+         * this will result in a longer delay than expected
+         * when the cpu core runs on lower frequencies.
+         */
+        unsigned int value = (1000000 * mult) / (HZ * div);
+        if (!preset_lpj)
+                preset_lpj = max_cpu_core_mhz * value;
+}
 static void __init shmobile_late_time_init(void)
 {
        /*
@@ -46,15 +64,6 @@ static void __init shmobile_timer_init(void)
 {
 }
-void __init shmobile_twd_init(struct twd_local_timer *twd_local_timer)
-{
-#ifdef CONFIG_HAVE_ARM_TWD
-        int err = twd_local_timer_register(twd_local_timer);
-        if (err)
-                pr_err("twd_local_timer_register failed %d\n", err);
-#endif
-}
 struct sys_timer shmobile_timer = {
        .init           = shmobile_timer_init,
 };
diff --git a/arch/arm/mach-spear3xx/Kconfig b/arch/arm/mach-spear3xx/Kconfig
index 2cee6b0de371..8bd37291fa4f 100644
--- a/arch/arm/mach-spear3xx/Kconfig
+++ b/arch/arm/mach-spear3xx/Kconfig
@@ -5,39 +5,22 @@
 if ARCH_SPEAR3XX
 menu "SPEAr3xx Implementations"
-config BOARD_SPEAR300_EVB
-        bool "SPEAr300 Evaluation Board"
-        select MACH_SPEAR300
-        help
-          Supports ST SPEAr300 Evaluation Board
-config BOARD_SPEAR310_EVB
-        bool "SPEAr310 Evaluation Board"
-        select MACH_SPEAR310
-        help
-          Supports ST SPEAr310 Evaluation Board
-config BOARD_SPEAR320_EVB
-        bool "SPEAr320 Evaluation Board"
-        select MACH_SPEAR320
-        help
-          Supports ST SPEAr320 Evaluation Board
-endmenu
 config MACH_SPEAR300
-        bool "SPEAr300"
+        bool "SPEAr300 Machine support with Device Tree"
+        select PINCTRL_SPEAR300
        help
-          Supports ST SPEAr300 Machine
+          Supports ST SPEAr300 machine configured via the device-tree
 config MACH_SPEAR310
-        bool "SPEAr310"
+        bool "SPEAr310 Machine support with Device Tree"
+        select PINCTRL_SPEAR310
        help
-          Supports ST SPEAr310 Machine
+          Supports ST SPEAr310 machine configured via the device-tree
 config MACH_SPEAR320
-        bool "SPEAr320"
+        bool "SPEAr320 Machine support with Device Tree"
+        select PINCTRL_SPEAR320
        help
-          Supports ST SPEAr320 Machine
+          Supports ST SPEAr320 machine configured via the device-tree
+endmenu
 endif #ARCH_SPEAR3XX
diff --git a/arch/arm/mach-spear3xx/Makefile b/arch/arm/mach-spear3xx/Makefile
index b24862489704..17b5d83cf2d5 100644
--- a/arch/arm/mach-spear3xx/Makefile
+++ b/arch/arm/mach-spear3xx/Makefile
@@ -3,24 +3,13 @@
 #
 # common files
-obj-y   += spear3xx.o clock.o
+obj-$(CONFIG_ARCH_SPEAR3XX)     += spear3xx.o clock.o
 # spear300 specific files
 obj-$(CONFIG_MACH_SPEAR300) += spear300.o
-# spear300 boards files
-obj-$(CONFIG_BOARD_SPEAR300_EVB) += spear300_evb.o
 # spear310 specific files
 obj-$(CONFIG_MACH_SPEAR310) += spear310.o
-# spear310 boards files
-obj-$(CONFIG_BOARD_SPEAR310_EVB) += spear310_evb.o
 # spear320 specific files
 obj-$(CONFIG_MACH_SPEAR320) += spear320.o
-# spear320 boards files
-obj-$(CONFIG_BOARD_SPEAR320_EVB) += spear320_evb.o
diff --git a/arch/arm/mach-spear3xx/Makefile.boot b/arch/arm/mach-spear3xx/Makefile.boot
index 4674a4c221db..d93e2177e6ec 100644
--- a/arch/arm/mach-spear3xx/Makefile.boot
+++ b/arch/arm/mach-spear3xx/Makefile.boot
@@ -1,3 +1,7 @@
 zreladdr-y      += 0x00008000
 params_phys-y   := 0x00000100
 initrd_phys-y   := 0x00800000
+dtb-$(CONFIG_MACH_SPEAR300)     += spear300-evb.dtb
+dtb-$(CONFIG_MACH_SPEAR310)     += spear310-evb.dtb
+dtb-$(CONFIG_MACH_SPEAR320)     += spear320-evb.dtb
diff --git a/arch/arm/mach-spear3xx/clock.c b/arch/arm/mach-spear3xx/clock.c
index 6c4841f55223..cd6c11099083 100644
--- a/arch/arm/mach-spear3xx/clock.c
+++ b/arch/arm/mach-spear3xx/clock.c
@@ -11,12 +11,112 @@
 * warranty of any kind, whether express or implied.
 */
+#include <linux/clkdev.h>
 #include <linux/init.h>
 #include <linux/io.h>
 #include <linux/kernel.h>
+#include <linux/of_platform.h>
 #include <asm/mach-types.h>
 #include <plat/clock.h>
 #include <mach/misc_regs.h>
+#include <mach/spear.h>
+#define PLL1_CTR                (MISC_BASE + 0x008)
+#define PLL1_FRQ                (MISC_BASE + 0x00C)
+#define PLL1_MOD                (MISC_BASE + 0x010)
+#define PLL2_CTR                (MISC_BASE + 0x014)
+/* PLL_CTR register masks */
+#define PLL_ENABLE              2
+#define PLL_MODE_SHIFT          4
+#define PLL_MODE_MASK           0x3
+#define PLL_MODE_NORMAL         0
+#define PLL_MODE_FRACTION       1
+#define PLL_MODE_DITH_DSB       2
+#define PLL_MODE_DITH_SSB       3
+#define PLL2_FRQ                (MISC_BASE + 0x018)
+/* PLL FRQ register masks */
+#define PLL_DIV_N_SHIFT         0
+#define PLL_DIV_N_MASK          0xFF
+#define PLL_DIV_P_SHIFT         8
+#define PLL_DIV_P_MASK          0x7
+#define PLL_NORM_FDBK_M_SHIFT   24
+#define PLL_NORM_FDBK_M_MASK    0xFF
+#define PLL_DITH_FDBK_M_SHIFT   16
+#define PLL_DITH_FDBK_M_MASK    0xFFFF
+#define PLL2_MOD                (MISC_BASE + 0x01C)
+#define PLL_CLK_CFG             (MISC_BASE + 0x020)
+#define CORE_CLK_CFG            (MISC_BASE + 0x024)
+/* CORE CLK CFG register masks */
+#define PLL_HCLK_RATIO_SHIFT    10
+#define PLL_HCLK_RATIO_MASK     0x3
+#define HCLK_PCLK_RATIO_SHIFT   8
+#define HCLK_PCLK_RATIO_MASK    0x3
+#define PERIP_CLK_CFG           (MISC_BASE + 0x028)
+/* PERIP_CLK_CFG register masks */
+#define UART_CLK_SHIFT          4
+#define UART_CLK_MASK           0x1
+#define FIRDA_CLK_SHIFT         5
+#define FIRDA_CLK_MASK          0x3
+#define GPT0_CLK_SHIFT          8
+#define GPT1_CLK_SHIFT          11
+#define GPT2_CLK_SHIFT          12
+#define GPT_CLK_MASK            0x1
+#define AUX_CLK_PLL3_VAL        0
+#define AUX_CLK_PLL1_VAL        1
+#define PERIP1_CLK_ENB          (MISC_BASE + 0x02C)
+/* PERIP1_CLK_ENB register masks */
+#define UART_CLK_ENB            3
+#define SSP_CLK_ENB             5
+#define I2C_CLK_ENB             7
+#define JPEG_CLK_ENB            8
+#define FIRDA_CLK_ENB           10
+#define GPT1_CLK_ENB            11
+#define GPT2_CLK_ENB            12
+#define ADC_CLK_ENB             15
+#define RTC_CLK_ENB             17
+#define GPIO_CLK_ENB            18
+#define DMA_CLK_ENB             19
+#define SMI_CLK_ENB             21
+#define GMAC_CLK_ENB            23
+#define USBD_CLK_ENB            24
+#define USBH_CLK_ENB            25
+#define C3_CLK_ENB              31
+#define RAS_CLK_ENB             (MISC_BASE + 0x034)
+#define PRSC1_CLK_CFG           (MISC_BASE + 0x044)
+#define PRSC2_CLK_CFG           (MISC_BASE + 0x048)
+#define PRSC3_CLK_CFG           (MISC_BASE + 0x04C)
+/* gpt synthesizer register masks */
+#define GPT_MSCALE_SHIFT        0
+#define GPT_MSCALE_MASK         0xFFF
+#define GPT_NSCALE_SHIFT        12
+#define GPT_NSCALE_MASK         0xF
+#define AMEM_CLK_CFG            (MISC_BASE + 0x050)
+#define EXPI_CLK_CFG            (MISC_BASE + 0x054)
+#define CLCD_CLK_SYNT           (MISC_BASE + 0x05C)
+#define FIRDA_CLK_SYNT          (MISC_BASE + 0x060)
+#define UART_CLK_SYNT           (MISC_BASE + 0x064)
+#define GMAC_CLK_SYNT           (MISC_BASE + 0x068)
+#define RAS1_CLK_SYNT           (MISC_BASE + 0x06C)
+#define RAS2_CLK_SYNT           (MISC_BASE + 0x070)
+#define RAS3_CLK_SYNT           (MISC_BASE + 0x074)
+#define RAS4_CLK_SYNT           (MISC_BASE + 0x078)
+/* aux clk synthesiser register masks for irda to ras4 */
+#define AUX_SYNT_ENB            31
+#define AUX_EQ_SEL_SHIFT        30
+#define AUX_EQ_SEL_MASK         1
+#define AUX_EQ1_SEL             0
+#define AUX_EQ2_SEL             1
+#define AUX_XSCALE_SHIFT        16
+#define AUX_XSCALE_MASK         0xFFF
+#define AUX_YSCALE_SHIFT        0
+#define AUX_YSCALE_MASK         0xFFF
 /* root clks */
 /* 32 KHz oscillator clock */
@@ -411,6 +511,21 @@ static struct clk usbd_clk = {
        .recalc = &follow_parent,
 };
+/* clock derived from usbh clk */
+/* usbh0 clock */
+static struct clk usbh0_clk = {
+        .flags = ALWAYS_ENABLED,
+        .pclk = &usbh_clk,
+        .recalc = &follow_parent,
+};
+/* usbh1 clock */
+static struct clk usbh1_clk = {
+        .flags = ALWAYS_ENABLED,
+        .pclk = &usbh_clk,
+        .recalc = &follow_parent,
+};
 /* clock derived from ahb clk */
 /* apb masks structure */
 static struct bus_clk_masks apb_masks = {
@@ -652,109 +767,126 @@ static struct clk pwm_clk = {
 /* array of all spear 3xx clock lookups */
 static struct clk_lookup spear_clk_lookups[] = {
-        { .con_id = "apb_pclk",         .clk = &dummy_apb_pclk},
+        CLKDEV_INIT(NULL, "apb_pclk", &dummy_apb_pclk),
        /* root clks */
-        { .con_id = "osc_32k_clk",      .clk = &osc_32k_clk},
+        CLKDEV_INIT(NULL, "osc_32k_clk", &osc_32k_clk),
-        { .con_id = "osc_24m_clk",      .clk = &osc_24m_clk},
+        CLKDEV_INIT(NULL, "osc_24m_clk", &osc_24m_clk),
        /* clock derived from 32 KHz osc clk */
-        { .dev_id = "rtc-spear",        .clk = &rtc_clk},
+        CLKDEV_INIT("fc900000.rtc", NULL, &rtc_clk),
        /* clock derived from 24 MHz osc clk */
-        { .con_id = "pll1_clk",         .clk = &pll1_clk},
+        CLKDEV_INIT(NULL, "pll1_clk", &pll1_clk),
-        { .con_id = "pll3_48m_clk",     .clk = &pll3_48m_clk},
+        CLKDEV_INIT(NULL, "pll3_48m_clk", &pll3_48m_clk),
-        { .dev_id = "wdt",              .clk = &wdt_clk},
+        CLKDEV_INIT("fc880000.wdt", NULL, &wdt_clk),
        /* clock derived from pll1 clk */
-        { .con_id = "cpu_clk",          .clk = &cpu_clk},
+        CLKDEV_INIT(NULL, "cpu_clk", &cpu_clk),
-        { .con_id = "ahb_clk",          .clk = &ahb_clk},
+        CLKDEV_INIT(NULL, "ahb_clk", &ahb_clk),
-        { .con_id = "uart_synth_clk",   .clk = &uart_synth_clk},
+        CLKDEV_INIT(NULL, "uart_synth_clk", &uart_synth_clk),
-        { .con_id = "firda_synth_clk",  .clk = &firda_synth_clk},
+        CLKDEV_INIT(NULL, "firda_synth_clk", &firda_synth_clk),
-        { .con_id = "gpt0_synth_clk",   .clk = &gpt0_synth_clk},
+        CLKDEV_INIT(NULL, "gpt0_synth_clk", &gpt0_synth_clk),
-        { .con_id = "gpt1_synth_clk",   .clk = &gpt1_synth_clk},
+        CLKDEV_INIT(NULL, "gpt1_synth_clk", &gpt1_synth_clk),
-        { .con_id = "gpt2_synth_clk",   .clk = &gpt2_synth_clk},
+        CLKDEV_INIT(NULL, "gpt2_synth_clk", &gpt2_synth_clk),
-        { .dev_id = "uart",             .clk = &uart_clk},
+        CLKDEV_INIT("d0000000.serial", NULL, &uart_clk),
-        { .dev_id = "firda",            .clk = &firda_clk},
+        CLKDEV_INIT("firda", NULL, &firda_clk),
-        { .dev_id = "gpt0",             .clk = &gpt0_clk},
+        CLKDEV_INIT("gpt0", NULL, &gpt0_clk),
-        { .dev_id = "gpt1",             .clk = &gpt1_clk},
+        CLKDEV_INIT("gpt1", NULL, &gpt1_clk),
-        { .dev_id = "gpt2",             .clk = &gpt2_clk},
+        CLKDEV_INIT("gpt2", NULL, &gpt2_clk),
        /* clock derived from pll3 clk */
-        { .dev_id = "designware_udc",   .clk = &usbd_clk},
+        CLKDEV_INIT("designware_udc", NULL, &usbd_clk),
-        { .con_id = "usbh_clk",         .clk = &usbh_clk},
+        CLKDEV_INIT(NULL, "usbh_clk", &usbh_clk),
+        /* clock derived from usbh clk */
+        CLKDEV_INIT(NULL, "usbh.0_clk", &usbh0_clk),
+        CLKDEV_INIT(NULL, "usbh.1_clk", &usbh1_clk),
        /* clock derived from ahb clk */
-        { .con_id = "apb_clk",          .clk = &apb_clk},
+        CLKDEV_INIT(NULL, "apb_clk", &apb_clk),
-        { .dev_id = "i2c_designware.0", .clk = &i2c_clk},
+        CLKDEV_INIT("d0180000.i2c", NULL, &i2c_clk),
-        { .dev_id = "dma",              .clk = &dma_clk},
+        CLKDEV_INIT("fc400000.dma", NULL, &dma_clk),
-        { .dev_id = "jpeg",             .clk = &jpeg_clk},
+        CLKDEV_INIT("jpeg", NULL, &jpeg_clk),
-        { .dev_id = "gmac",             .clk = &gmac_clk},
+        CLKDEV_INIT("e0800000.eth", NULL, &gmac_clk),
-        { .dev_id = "smi",              .clk = &smi_clk},
+        CLKDEV_INIT("fc000000.flash", NULL, &smi_clk),
-        { .dev_id = "c3",               .clk = &c3_clk},
+        CLKDEV_INIT("c3", NULL, &c3_clk),
        /* clock derived from apb clk */
-        { .dev_id = "adc",              .clk = &adc_clk},
+        CLKDEV_INIT("adc", NULL, &adc_clk),
-        { .dev_id = "ssp-pl022.0",      .clk = &ssp0_clk},
+        CLKDEV_INIT("d0100000.spi", NULL, &ssp0_clk),
-        { .dev_id = "gpio",             .clk = &gpio_clk},
+        CLKDEV_INIT("fc980000.gpio", NULL, &gpio_clk),
 };
 /* array of all spear 300 clock lookups */
 #ifdef CONFIG_MACH_SPEAR300
 static struct clk_lookup spear300_clk_lookups[] = {
-        { .dev_id = "clcd",             .clk = &clcd_clk},
+        CLKDEV_INIT("60000000.clcd", NULL, &clcd_clk),
-        { .con_id = "fsmc",             .clk = &fsmc_clk},
+        CLKDEV_INIT("94000000.flash", NULL, &fsmc_clk),
-        { .dev_id = "gpio1",            .clk = &gpio1_clk},
+        CLKDEV_INIT("a9000000.gpio", NULL, &gpio1_clk),
-        { .dev_id = "keyboard",         .clk = &kbd_clk},
+        CLKDEV_INIT("a0000000.kbd", NULL, &kbd_clk),
-        { .dev_id = "sdhci",            .clk = &sdhci_clk},
+        CLKDEV_INIT("70000000.sdhci", NULL, &sdhci_clk),
 };
+void __init spear300_clk_init(void)
+{
+        int i;
+        for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
+                clk_register(&spear_clk_lookups[i]);
+        for (i = 0; i < ARRAY_SIZE(spear300_clk_lookups); i++)
+                clk_register(&spear300_clk_lookups[i]);
+        clk_init();
+}
 #endif
 /* array of all spear 310 clock lookups */
 #ifdef CONFIG_MACH_SPEAR310
 static struct clk_lookup spear310_clk_lookups[] = {
-        { .con_id = "fsmc",             .clk = &fsmc_clk},
+        CLKDEV_INIT("44000000.flash", NULL, &fsmc_clk),
-        { .con_id = "emi",              .clk = &emi_clk},
+        CLKDEV_INIT(NULL, "emi", &emi_clk),
-        { .dev_id = "uart1",            .clk = &uart1_clk},
+        CLKDEV_INIT("b2000000.serial", NULL, &uart1_clk),
-        { .dev_id = "uart2",            .clk = &uart2_clk},
+        CLKDEV_INIT("b2080000.serial", NULL, &uart2_clk),
-        { .dev_id = "uart3",            .clk = &uart3_clk},
+        CLKDEV_INIT("b2100000.serial", NULL, &uart3_clk),
-        { .dev_id = "uart4",            .clk = &uart4_clk},
+        CLKDEV_INIT("b2180000.serial", NULL, &uart4_clk),
-        { .dev_id = "uart5",            .clk = &uart5_clk},
+        CLKDEV_INIT("b2200000.serial", NULL, &uart5_clk),
 };
+void __init spear310_clk_init(void)
+{
+        int i;
+        for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
+                clk_register(&spear_clk_lookups[i]);
+        for (i = 0; i < ARRAY_SIZE(spear310_clk_lookups); i++)
+                clk_register(&spear310_clk_lookups[i]);
+        clk_init();
+}
 #endif
 /* array of all spear 320 clock lookups */
 #ifdef CONFIG_MACH_SPEAR320
 static struct clk_lookup spear320_clk_lookups[] = {
-        { .dev_id = "clcd",             .clk = &clcd_clk},
+        CLKDEV_INIT("90000000.clcd", NULL, &clcd_clk),
-        { .con_id = "fsmc",             .clk = &fsmc_clk},
+        CLKDEV_INIT("4c000000.flash", NULL, &fsmc_clk),
-        { .dev_id = "i2c_designware.1", .clk = &i2c1_clk},
+        CLKDEV_INIT("a7000000.i2c", NULL, &i2c1_clk),
-        { .con_id = "emi",              .clk = &emi_clk},
+        CLKDEV_INIT(NULL, "emi", &emi_clk),
-        { .dev_id = "pwm",              .clk = &pwm_clk},
+        CLKDEV_INIT("pwm", NULL, &pwm_clk),
-        { .dev_id = "sdhci",            .clk = &sdhci_clk},
+        CLKDEV_INIT("70000000.sdhci", NULL, &sdhci_clk),
-        { .dev_id = "c_can_platform.0", .clk = &can0_clk},
+        CLKDEV_INIT("c_can_platform.0", NULL, &can0_clk),
-        { .dev_id = "c_can_platform.1", .clk = &can1_clk},
+        CLKDEV_INIT("c_can_platform.1", NULL, &can1_clk),
-        { .dev_id = "ssp-pl022.1",      .clk = &ssp1_clk},
+        CLKDEV_INIT("a5000000.spi", NULL, &ssp1_clk),
-        { .dev_id = "ssp-pl022.2",      .clk = &ssp2_clk},
+        CLKDEV_INIT("a6000000.spi", NULL, &ssp2_clk),
-        { .dev_id = "uart1",            .clk = &uart1_clk},
+        CLKDEV_INIT("a3000000.serial", NULL, &uart1_clk),
-        { .dev_id = "uart2",            .clk = &uart2_clk},
+        CLKDEV_INIT("a4000000.serial", NULL, &uart2_clk),
-};
+};
-#endif
+void __init spear320_clk_init(void)
-void __init spear3xx_clk_init(void)
 {
-        int i, cnt;
+        int i;
-        struct clk_lookup *lookups;
-        if (machine_is_spear300()) {
-                cnt = ARRAY_SIZE(spear300_clk_lookups);
-                lookups = spear300_clk_lookups;
-        } else if (machine_is_spear310()) {
-                cnt = ARRAY_SIZE(spear310_clk_lookups);
-                lookups = spear310_clk_lookups;
-        } else {
-                cnt = ARRAY_SIZE(spear320_clk_lookups);
-                lookups = spear320_clk_lookups;
-        }
        for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
                clk_register(&spear_clk_lookups[i]);
-        for (i = 0; i < cnt; i++)
+        for (i = 0; i < ARRAY_SIZE(spear320_clk_lookups); i++)
-                clk_register(&lookups[i]);
+                clk_register(&spear320_clk_lookups[i]);
        clk_init();
 }
+#endif
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index 14276e5a98d2..bdb304551caf 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -14,188 +14,40 @@
 #ifndef __MACH_GENERIC_H
 #define __MACH_GENERIC_H
+#include <linux/amba/pl08x.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/amba/bus.h>
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
-#include <plat/padmux.h>
-/* spear3xx declarations */
-/*
- * Each GPT has 2 timer channels
- * Following GPT channels will be used as clock source and clockevent
- */
-#define SPEAR_GPT0_BASE         SPEAR3XX_ML1_TMR_BASE
-#define SPEAR_GPT0_CHAN0_IRQ    SPEAR3XX_IRQ_CPU_GPT1_1
-#define SPEAR_GPT0_CHAN1_IRQ    SPEAR3XX_IRQ_CPU_GPT1_2
 /* Add spear3xx family device structure declarations here */
-extern struct amba_device spear3xx_gpio_device;
-extern struct amba_device spear3xx_uart_device;
 extern struct sys_timer spear3xx_timer;
+extern struct pl022_ssp_controller pl022_plat_data;
+extern struct pl08x_platform_data pl080_plat_data;
 /* Add spear3xx family function declarations here */
-void __init spear3xx_clk_init(void);
+void __init spear_setup_timer(resource_size_t base, int irq);
-void __init spear_setup_timer(void);
 void __init spear3xx_map_io(void);
-void __init spear3xx_init_irq(void);
+void __init spear3xx_dt_init_irq(void);
-void __init spear3xx_init(void);
 void spear_restart(char, const char *);
-/* pad mux declarations */
-#define PMX_FIRDA_MASK          (1 << 14)
-#define PMX_I2C_MASK            (1 << 13)
-#define PMX_SSP_CS_MASK         (1 << 12)
-#define PMX_SSP_MASK            (1 << 11)
-#define PMX_MII_MASK            (1 << 10)
-#define PMX_GPIO_PIN0_MASK      (1 << 9)
-#define PMX_GPIO_PIN1_MASK      (1 << 8)
-#define PMX_GPIO_PIN2_MASK      (1 << 7)
-#define PMX_GPIO_PIN3_MASK      (1 << 6)
-#define PMX_GPIO_PIN4_MASK      (1 << 5)
-#define PMX_GPIO_PIN5_MASK      (1 << 4)
-#define PMX_UART0_MODEM_MASK    (1 << 3)
-#define PMX_UART0_MASK          (1 << 2)
-#define PMX_TIMER_3_4_MASK      (1 << 1)
-#define PMX_TIMER_1_2_MASK      (1 << 0)
-/* pad mux devices */
-extern struct pmx_dev spear3xx_pmx_firda;
-extern struct pmx_dev spear3xx_pmx_i2c;
-extern struct pmx_dev spear3xx_pmx_ssp_cs;
-extern struct pmx_dev spear3xx_pmx_ssp;
-extern struct pmx_dev spear3xx_pmx_mii;
-extern struct pmx_dev spear3xx_pmx_gpio_pin0;
-extern struct pmx_dev spear3xx_pmx_gpio_pin1;
-extern struct pmx_dev spear3xx_pmx_gpio_pin2;
-extern struct pmx_dev spear3xx_pmx_gpio_pin3;
-extern struct pmx_dev spear3xx_pmx_gpio_pin4;
-extern struct pmx_dev spear3xx_pmx_gpio_pin5;
-extern struct pmx_dev spear3xx_pmx_uart0_modem;
-extern struct pmx_dev spear3xx_pmx_uart0;
-extern struct pmx_dev spear3xx_pmx_timer_3_4;
-extern struct pmx_dev spear3xx_pmx_timer_1_2;
-#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
-/* padmux plgpio devices */
-extern struct pmx_dev spear3xx_pmx_plgpio_0_1;
-extern struct pmx_dev spear3xx_pmx_plgpio_2_3;
-extern struct pmx_dev spear3xx_pmx_plgpio_4_5;
-extern struct pmx_dev spear3xx_pmx_plgpio_6_9;
-extern struct pmx_dev spear3xx_pmx_plgpio_10_27;
-extern struct pmx_dev spear3xx_pmx_plgpio_28;
-extern struct pmx_dev spear3xx_pmx_plgpio_29;
-extern struct pmx_dev spear3xx_pmx_plgpio_30;
-extern struct pmx_dev spear3xx_pmx_plgpio_31;
-extern struct pmx_dev spear3xx_pmx_plgpio_32;
-extern struct pmx_dev spear3xx_pmx_plgpio_33;
-extern struct pmx_dev spear3xx_pmx_plgpio_34_36;
-extern struct pmx_dev spear3xx_pmx_plgpio_37_42;
-extern struct pmx_dev spear3xx_pmx_plgpio_43_44_47_48;
-extern struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50;
-#endif
 /* spear300 declarations */
 #ifdef CONFIG_MACH_SPEAR300
-/* Add spear300 machine device structure declarations here */
+void __init spear300_clk_init(void);
-extern struct amba_device spear300_gpio1_device;
-/* pad mux modes */
-extern struct pmx_mode spear300_nand_mode;
-extern struct pmx_mode spear300_nor_mode;
-extern struct pmx_mode spear300_photo_frame_mode;
-extern struct pmx_mode spear300_lend_ip_phone_mode;
-extern struct pmx_mode spear300_hend_ip_phone_mode;
-extern struct pmx_mode spear300_lend_wifi_phone_mode;
-extern struct pmx_mode spear300_hend_wifi_phone_mode;
-extern struct pmx_mode spear300_ata_pabx_wi2s_mode;
-extern struct pmx_mode spear300_ata_pabx_i2s_mode;
-extern struct pmx_mode spear300_caml_lcdw_mode;
-extern struct pmx_mode spear300_camu_lcd_mode;
-extern struct pmx_mode spear300_camu_wlcd_mode;
-extern struct pmx_mode spear300_caml_lcd_mode;
-/* pad mux devices */
-extern struct pmx_dev spear300_pmx_fsmc_2_chips;
-extern struct pmx_dev spear300_pmx_fsmc_4_chips;
-extern struct pmx_dev spear300_pmx_keyboard;
-extern struct pmx_dev spear300_pmx_clcd;
-extern struct pmx_dev spear300_pmx_telecom_gpio;
-extern struct pmx_dev spear300_pmx_telecom_tdm;
-extern struct pmx_dev spear300_pmx_telecom_spi_cs_i2c_clk;
-extern struct pmx_dev spear300_pmx_telecom_camera;
-extern struct pmx_dev spear300_pmx_telecom_dac;
-extern struct pmx_dev spear300_pmx_telecom_i2s;
-extern struct pmx_dev spear300_pmx_telecom_boot_pins;
-extern struct pmx_dev spear300_pmx_telecom_sdhci_4bit;
-extern struct pmx_dev spear300_pmx_telecom_sdhci_8bit;
-extern struct pmx_dev spear300_pmx_gpio1;
-/* Add spear300 machine function declarations here */
-void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
-                u8 pmx_dev_count);
 #endif /* CONFIG_MACH_SPEAR300 */
 /* spear310 declarations */
 #ifdef CONFIG_MACH_SPEAR310
-/* Add spear310 machine device structure declarations here */
+void __init spear310_clk_init(void);
-/* pad mux devices */
-extern struct pmx_dev spear310_pmx_emi_cs_0_1_4_5;
-extern struct pmx_dev spear310_pmx_emi_cs_2_3;
-extern struct pmx_dev spear310_pmx_uart1;
-extern struct pmx_dev spear310_pmx_uart2;
-extern struct pmx_dev spear310_pmx_uart3_4_5;
-extern struct pmx_dev spear310_pmx_fsmc;
-extern struct pmx_dev spear310_pmx_rs485_0_1;
-extern struct pmx_dev spear310_pmx_tdm0;
-/* Add spear310 machine function declarations here */
-void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
-                u8 pmx_dev_count);
 #endif /* CONFIG_MACH_SPEAR310 */
 /* spear320 declarations */
 #ifdef CONFIG_MACH_SPEAR320
-/* Add spear320 machine device structure declarations here */
+void __init spear320_clk_init(void);
-/* pad mux modes */
-extern struct pmx_mode spear320_auto_net_smii_mode;
-extern struct pmx_mode spear320_auto_net_mii_mode;
-extern struct pmx_mode spear320_auto_exp_mode;
-extern struct pmx_mode spear320_small_printers_mode;
-/* pad mux devices */
-extern struct pmx_dev spear320_pmx_clcd;
-extern struct pmx_dev spear320_pmx_emi;
-extern struct pmx_dev spear320_pmx_fsmc;
-extern struct pmx_dev spear320_pmx_spp;
-extern struct pmx_dev spear320_pmx_sdhci;
-extern struct pmx_dev spear320_pmx_i2s;
-extern struct pmx_dev spear320_pmx_uart1;
-extern struct pmx_dev spear320_pmx_uart1_modem;
-extern struct pmx_dev spear320_pmx_uart2;
-extern struct pmx_dev spear320_pmx_touchscreen;
-extern struct pmx_dev spear320_pmx_can;
-extern struct pmx_dev spear320_pmx_sdhci_led;
-extern struct pmx_dev spear320_pmx_pwm0;
-extern struct pmx_dev spear320_pmx_pwm1;
-extern struct pmx_dev spear320_pmx_pwm2;
-extern struct pmx_dev spear320_pmx_pwm3;
-extern struct pmx_dev spear320_pmx_ssp1;
-extern struct pmx_dev spear320_pmx_ssp2;
-extern struct pmx_dev spear320_pmx_mii1;
-extern struct pmx_dev spear320_pmx_smii0;
-extern struct pmx_dev spear320_pmx_smii1;
-extern struct pmx_dev spear320_pmx_i2c1;
-/* Add spear320 machine function declarations here */
-void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
-                u8 pmx_dev_count);
 #endif /* CONFIG_MACH_SPEAR320 */
diff --git a/arch/arm/mach-spear3xx/include/mach/hardware.h b/arch/arm/mach-spear3xx/include/mach/hardware.h
index 4660c0d8ec0d..40a8c178f10d 100644
--- a/arch/arm/mach-spear3xx/include/mach/hardware.h
+++ b/arch/arm/mach-spear3xx/include/mach/hardware.h
@@ -1,23 +1 @@
-/*
+/* empty */
- * arch/arm/mach-spear3xx/include/mach/hardware.h
- *
- * Hardware definitions for SPEAr3xx machine family
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#ifndef __MACH_HARDWARE_H
-#define __MACH_HARDWARE_H
-#include <plat/hardware.h>
-#include <mach/spear.h>
-/* Vitual to physical translation of statically mapped space */
-#define IO_ADDRESS(x)           (x | 0xF0000000)
-#endif /* __MACH_HARDWARE_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/irqs.h b/arch/arm/mach-spear3xx/include/mach/irqs.h
index 6e265442808e..319620a1afb4 100644
--- a/arch/arm/mach-spear3xx/include/mach/irqs.h
+++ b/arch/arm/mach-spear3xx/include/mach/irqs.h
@@ -14,141 +14,15 @@
 #ifndef __MACH_IRQS_H
 #define __MACH_IRQS_H
-/* SPEAr3xx IRQ definitions */
+/* FIXME: probe all these from DT */
-#define SPEAR3XX_IRQ_HW_ACCEL_MOD_0             0
 #define SPEAR3XX_IRQ_INTRCOMM_RAS_ARM           1
 #define SPEAR3XX_IRQ_CPU_GPT1_1                 2
-#define SPEAR3XX_IRQ_CPU_GPT1_2                 3
-#define SPEAR3XX_IRQ_BASIC_GPT1_1               4
-#define SPEAR3XX_IRQ_BASIC_GPT1_2               5
-#define SPEAR3XX_IRQ_BASIC_GPT2_1               6
-#define SPEAR3XX_IRQ_BASIC_GPT2_2               7
-#define SPEAR3XX_IRQ_BASIC_DMA                  8
-#define SPEAR3XX_IRQ_BASIC_SMI                  9
-#define SPEAR3XX_IRQ_BASIC_RTC                  10
-#define SPEAR3XX_IRQ_BASIC_GPIO                 11
-#define SPEAR3XX_IRQ_BASIC_WDT                  12
-#define SPEAR3XX_IRQ_DDR_CONTROLLER             13
-#define SPEAR3XX_IRQ_SYS_ERROR                  14
-#define SPEAR3XX_IRQ_WAKEUP_RCV                 15
-#define SPEAR3XX_IRQ_JPEG                       16
-#define SPEAR3XX_IRQ_IRDA                       17
-#define SPEAR3XX_IRQ_ADC                        18
-#define SPEAR3XX_IRQ_UART                       19
-#define SPEAR3XX_IRQ_SSP                        20
-#define SPEAR3XX_IRQ_I2C                        21
-#define SPEAR3XX_IRQ_MAC_1                      22
-#define SPEAR3XX_IRQ_MAC_2                      23
-#define SPEAR3XX_IRQ_USB_DEV                    24
-#define SPEAR3XX_IRQ_USB_H_OHCI_0               25
-#define SPEAR3XX_IRQ_USB_H_EHCI_0               26
-#define SPEAR3XX_IRQ_USB_H_EHCI_1               SPEAR3XX_IRQ_USB_H_EHCI_0
-#define SPEAR3XX_IRQ_USB_H_OHCI_1               27
 #define SPEAR3XX_IRQ_GEN_RAS_1                  28
 #define SPEAR3XX_IRQ_GEN_RAS_2                  29
 #define SPEAR3XX_IRQ_GEN_RAS_3                  30
-#define SPEAR3XX_IRQ_HW_ACCEL_MOD_1             31
 #define SPEAR3XX_IRQ_VIC_END                    32
 #define SPEAR3XX_VIRQ_START                     SPEAR3XX_IRQ_VIC_END
-/* SPEAr300 Virtual irq definitions */
+#define NR_IRQS                 160
-/* IRQs sharing IRQ_GEN_RAS_1 */
-#define SPEAR300_VIRQ_IT_PERS_S                 (SPEAR3XX_VIRQ_START + 0)
-#define SPEAR300_VIRQ_IT_CHANGE_S               (SPEAR3XX_VIRQ_START + 1)
-#define SPEAR300_VIRQ_I2S                       (SPEAR3XX_VIRQ_START + 2)
-#define SPEAR300_VIRQ_TDM                       (SPEAR3XX_VIRQ_START + 3)
-#define SPEAR300_VIRQ_CAMERA_L                  (SPEAR3XX_VIRQ_START + 4)
-#define SPEAR300_VIRQ_CAMERA_F                  (SPEAR3XX_VIRQ_START + 5)
-#define SPEAR300_VIRQ_CAMERA_V                  (SPEAR3XX_VIRQ_START + 6)
-#define SPEAR300_VIRQ_KEYBOARD                  (SPEAR3XX_VIRQ_START + 7)
-#define SPEAR300_VIRQ_GPIO1                     (SPEAR3XX_VIRQ_START + 8)
-/* IRQs sharing IRQ_GEN_RAS_3 */
-#define SPEAR300_IRQ_CLCD                       SPEAR3XX_IRQ_GEN_RAS_3
-/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
-#define SPEAR300_IRQ_SDHCI                      SPEAR3XX_IRQ_INTRCOMM_RAS_ARM
-/* SPEAr310 Virtual irq definitions */
-/* IRQs sharing IRQ_GEN_RAS_1 */
-#define SPEAR310_VIRQ_SMII0                     (SPEAR3XX_VIRQ_START + 0)
-#define SPEAR310_VIRQ_SMII1                     (SPEAR3XX_VIRQ_START + 1)
-#define SPEAR310_VIRQ_SMII2                     (SPEAR3XX_VIRQ_START + 2)
-#define SPEAR310_VIRQ_SMII3                     (SPEAR3XX_VIRQ_START + 3)
-#define SPEAR310_VIRQ_WAKEUP_SMII0              (SPEAR3XX_VIRQ_START + 4)
-#define SPEAR310_VIRQ_WAKEUP_SMII1              (SPEAR3XX_VIRQ_START + 5)
-#define SPEAR310_VIRQ_WAKEUP_SMII2              (SPEAR3XX_VIRQ_START + 6)
-#define SPEAR310_VIRQ_WAKEUP_SMII3              (SPEAR3XX_VIRQ_START + 7)
-/* IRQs sharing IRQ_GEN_RAS_2 */
-#define SPEAR310_VIRQ_UART1                     (SPEAR3XX_VIRQ_START + 8)
-#define SPEAR310_VIRQ_UART2                     (SPEAR3XX_VIRQ_START + 9)
-#define SPEAR310_VIRQ_UART3                     (SPEAR3XX_VIRQ_START + 10)
-#define SPEAR310_VIRQ_UART4                     (SPEAR3XX_VIRQ_START + 11)
-#define SPEAR310_VIRQ_UART5                     (SPEAR3XX_VIRQ_START + 12)
-/* IRQs sharing IRQ_GEN_RAS_3 */
-#define SPEAR310_VIRQ_EMI                       (SPEAR3XX_VIRQ_START + 13)
-#define SPEAR310_VIRQ_PLGPIO                    (SPEAR3XX_VIRQ_START + 14)
-/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
-#define SPEAR310_VIRQ_TDM_HDLC                  (SPEAR3XX_VIRQ_START + 15)
-#define SPEAR310_VIRQ_RS485_0                   (SPEAR3XX_VIRQ_START + 16)
-#define SPEAR310_VIRQ_RS485_1                   (SPEAR3XX_VIRQ_START + 17)
-/* SPEAr320 Virtual irq definitions */
-/* IRQs sharing IRQ_GEN_RAS_1 */
-#define SPEAR320_VIRQ_EMI                       (SPEAR3XX_VIRQ_START + 0)
-#define SPEAR320_VIRQ_CLCD                      (SPEAR3XX_VIRQ_START + 1)
-#define SPEAR320_VIRQ_SPP                       (SPEAR3XX_VIRQ_START + 2)
-/* IRQs sharing IRQ_GEN_RAS_2 */
-#define SPEAR320_IRQ_SDHCI                      SPEAR3XX_IRQ_GEN_RAS_2
-/* IRQs sharing IRQ_GEN_RAS_3 */
-#define SPEAR320_VIRQ_PLGPIO                    (SPEAR3XX_VIRQ_START + 3)
-#define SPEAR320_VIRQ_I2S_PLAY                  (SPEAR3XX_VIRQ_START + 4)
-#define SPEAR320_VIRQ_I2S_REC                   (SPEAR3XX_VIRQ_START + 5)
-/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
-#define SPEAR320_VIRQ_CANU                      (SPEAR3XX_VIRQ_START + 6)
-#define SPEAR320_VIRQ_CANL                      (SPEAR3XX_VIRQ_START + 7)
-#define SPEAR320_VIRQ_UART1                     (SPEAR3XX_VIRQ_START + 8)
-#define SPEAR320_VIRQ_UART2                     (SPEAR3XX_VIRQ_START + 9)
-#define SPEAR320_VIRQ_SSP1                      (SPEAR3XX_VIRQ_START + 10)
-#define SPEAR320_VIRQ_SSP2                      (SPEAR3XX_VIRQ_START + 11)
-#define SPEAR320_VIRQ_SMII0                     (SPEAR3XX_VIRQ_START + 12)
-#define SPEAR320_VIRQ_MII1_SMII1                (SPEAR3XX_VIRQ_START + 13)
-#define SPEAR320_VIRQ_WAKEUP_SMII0              (SPEAR3XX_VIRQ_START + 14)
-#define SPEAR320_VIRQ_WAKEUP_MII1_SMII1         (SPEAR3XX_VIRQ_START + 15)
-#define SPEAR320_VIRQ_I2C1                      (SPEAR3XX_VIRQ_START + 16)
-/*
- * GPIO pins virtual irqs
- * Use the lowest number for the GPIO virtual IRQs base on which subarchs
- * we have compiled in
- */
-#if defined(CONFIG_MACH_SPEAR310)
-#define SPEAR3XX_GPIO_INT_BASE                  (SPEAR3XX_VIRQ_START + 18)
-#elif defined(CONFIG_MACH_SPEAR320)
-#define SPEAR3XX_GPIO_INT_BASE                  (SPEAR3XX_VIRQ_START + 17)
-#else
-#define SPEAR3XX_GPIO_INT_BASE                  (SPEAR3XX_VIRQ_START + 9)
-#endif
-#define SPEAR300_GPIO1_INT_BASE                 (SPEAR3XX_GPIO_INT_BASE + 8)
-#define SPEAR3XX_PLGPIO_COUNT   102
-#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
-#define SPEAR3XX_PLGPIO_INT_BASE                (SPEAR3XX_GPIO_INT_BASE + 8)
-#define SPEAR3XX_GPIO_INT_END                   (SPEAR3XX_PLGPIO_INT_BASE + \
-                                                        SPEAR3XX_PLGPIO_COUNT)
-#else
-#define SPEAR3XX_GPIO_INT_END   (SPEAR300_GPIO1_INT_BASE + 8)
-#endif
-#define SPEAR3XX_VIRQ_END       SPEAR3XX_GPIO_INT_END
-#define NR_IRQS                 SPEAR3XX_VIRQ_END
 #endif /* __MACH_IRQS_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/misc_regs.h b/arch/arm/mach-spear3xx/include/mach/misc_regs.h
index 5bd8cd8d4852..e0ab72e61507 100644
--- a/arch/arm/mach-spear3xx/include/mach/misc_regs.h
+++ b/arch/arm/mach-spear3xx/include/mach/misc_regs.h
@@ -14,151 +14,7 @@
 #ifndef __MACH_MISC_REGS_H
 #define __MACH_MISC_REGS_H
-#include <mach/hardware.h>
 #define MISC_BASE               IOMEM(VA_SPEAR3XX_ICM3_MISC_REG_BASE)
-#define SOC_CFG_CTR             (MISC_BASE + 0x000)
-#define DIAG_CFG_CTR            (MISC_BASE + 0x004)
-#define PLL1_CTR                (MISC_BASE + 0x008)
-#define PLL1_FRQ                (MISC_BASE + 0x00C)
-#define PLL1_MOD                (MISC_BASE + 0x010)
-#define PLL2_CTR                (MISC_BASE + 0x014)
-/* PLL_CTR register masks */
-#define PLL_ENABLE              2
-#define PLL_MODE_SHIFT          4
-#define PLL_MODE_MASK           0x3
-#define PLL_MODE_NORMAL         0
-#define PLL_MODE_FRACTION       1
-#define PLL_MODE_DITH_DSB       2
-#define PLL_MODE_DITH_SSB       3
-#define PLL2_FRQ                (MISC_BASE + 0x018)
-/* PLL FRQ register masks */
-#define PLL_DIV_N_SHIFT         0
-#define PLL_DIV_N_MASK          0xFF
-#define PLL_DIV_P_SHIFT         8
-#define PLL_DIV_P_MASK          0x7
-#define PLL_NORM_FDBK_M_SHIFT   24
-#define PLL_NORM_FDBK_M_MASK    0xFF
-#define PLL_DITH_FDBK_M_SHIFT   16
-#define PLL_DITH_FDBK_M_MASK    0xFFFF
-#define PLL2_MOD                (MISC_BASE + 0x01C)
-#define PLL_CLK_CFG             (MISC_BASE + 0x020)
-#define CORE_CLK_CFG            (MISC_BASE + 0x024)
-/* CORE CLK CFG register masks */
-#define PLL_HCLK_RATIO_SHIFT    10
-#define PLL_HCLK_RATIO_MASK     0x3
-#define HCLK_PCLK_RATIO_SHIFT   8
-#define HCLK_PCLK_RATIO_MASK    0x3
-#define PERIP_CLK_CFG           (MISC_BASE + 0x028)
-/* PERIP_CLK_CFG register masks */
-#define UART_CLK_SHIFT          4
-#define UART_CLK_MASK           0x1
-#define FIRDA_CLK_SHIFT         5
-#define FIRDA_CLK_MASK          0x3
-#define GPT0_CLK_SHIFT          8
-#define GPT1_CLK_SHIFT          11
-#define GPT2_CLK_SHIFT          12
-#define GPT_CLK_MASK            0x1
-#define AUX_CLK_PLL3_VAL        0
-#define AUX_CLK_PLL1_VAL        1
-#define PERIP1_CLK_ENB          (MISC_BASE + 0x02C)
-/* PERIP1_CLK_ENB register masks */
-#define UART_CLK_ENB            3
-#define SSP_CLK_ENB             5
-#define I2C_CLK_ENB             7
-#define JPEG_CLK_ENB            8
-#define FIRDA_CLK_ENB           10
-#define GPT1_CLK_ENB            11
-#define GPT2_CLK_ENB            12
-#define ADC_CLK_ENB             15
-#define RTC_CLK_ENB             17
-#define GPIO_CLK_ENB            18
-#define DMA_CLK_ENB             19
-#define SMI_CLK_ENB             21
-#define GMAC_CLK_ENB            23
-#define USBD_CLK_ENB            24
-#define USBH_CLK_ENB            25
-#define C3_CLK_ENB              31
-#define SOC_CORE_ID             (MISC_BASE + 0x030)
-#define RAS_CLK_ENB             (MISC_BASE + 0x034)
-#define PERIP1_SOF_RST          (MISC_BASE + 0x038)
-/* PERIP1_SOF_RST register masks */
-#define JPEG_SOF_RST            8
-#define SOC_USER_ID             (MISC_BASE + 0x03C)
-#define RAS_SOF_RST             (MISC_BASE + 0x040)
-#define PRSC1_CLK_CFG           (MISC_BASE + 0x044)
-#define PRSC2_CLK_CFG           (MISC_BASE + 0x048)
-#define PRSC3_CLK_CFG           (MISC_BASE + 0x04C)
-/* gpt synthesizer register masks */
-#define GPT_MSCALE_SHIFT        0
-#define GPT_MSCALE_MASK         0xFFF
-#define GPT_NSCALE_SHIFT        12
-#define GPT_NSCALE_MASK         0xF
-#define AMEM_CLK_CFG            (MISC_BASE + 0x050)
-#define EXPI_CLK_CFG            (MISC_BASE + 0x054)
-#define CLCD_CLK_SYNT           (MISC_BASE + 0x05C)
-#define FIRDA_CLK_SYNT          (MISC_BASE + 0x060)
-#define UART_CLK_SYNT           (MISC_BASE + 0x064)
-#define GMAC_CLK_SYNT           (MISC_BASE + 0x068)
-#define RAS1_CLK_SYNT           (MISC_BASE + 0x06C)
-#define RAS2_CLK_SYNT           (MISC_BASE + 0x070)
-#define RAS3_CLK_SYNT           (MISC_BASE + 0x074)
-#define RAS4_CLK_SYNT           (MISC_BASE + 0x078)
-/* aux clk synthesiser register masks for irda to ras4 */
-#define AUX_SYNT_ENB            31
-#define AUX_EQ_SEL_SHIFT        30
-#define AUX_EQ_SEL_MASK         1
-#define AUX_EQ1_SEL             0
-#define AUX_EQ2_SEL             1
-#define AUX_XSCALE_SHIFT        16
-#define AUX_XSCALE_MASK         0xFFF
-#define AUX_YSCALE_SHIFT        0
-#define AUX_YSCALE_MASK         0xFFF
-#define ICM1_ARB_CFG            (MISC_BASE + 0x07C)
-#define ICM2_ARB_CFG            (MISC_BASE + 0x080)
-#define ICM3_ARB_CFG            (MISC_BASE + 0x084)
-#define ICM4_ARB_CFG            (MISC_BASE + 0x088)
-#define ICM5_ARB_CFG            (MISC_BASE + 0x08C)
-#define ICM6_ARB_CFG            (MISC_BASE + 0x090)
-#define ICM7_ARB_CFG            (MISC_BASE + 0x094)
-#define ICM8_ARB_CFG            (MISC_BASE + 0x098)
-#define ICM9_ARB_CFG            (MISC_BASE + 0x09C)
 #define DMA_CHN_CFG             (MISC_BASE + 0x0A0)
-#define USB2_PHY_CFG            (MISC_BASE + 0x0A4)
-#define GMAC_CFG_CTR            (MISC_BASE + 0x0A8)
-#define EXPI_CFG_CTR            (MISC_BASE + 0x0AC)
-#define PRC1_LOCK_CTR           (MISC_BASE + 0x0C0)
-#define PRC2_LOCK_CTR           (MISC_BASE + 0x0C4)
-#define PRC3_LOCK_CTR           (MISC_BASE + 0x0C8)
-#define PRC4_LOCK_CTR           (MISC_BASE + 0x0CC)
-#define PRC1_IRQ_CTR            (MISC_BASE + 0x0D0)
-#define PRC2_IRQ_CTR            (MISC_BASE + 0x0D4)
-#define PRC3_IRQ_CTR            (MISC_BASE + 0x0D8)
-#define PRC4_IRQ_CTR            (MISC_BASE + 0x0DC)
-#define PWRDOWN_CFG_CTR         (MISC_BASE + 0x0E0)
-#define COMPSSTL_1V8_CFG        (MISC_BASE + 0x0E4)
-#define COMPSSTL_2V5_CFG        (MISC_BASE + 0x0E8)
-#define COMPCOR_3V3_CFG         (MISC_BASE + 0x0EC)
-#define SSTLPAD_CFG_CTR         (MISC_BASE + 0x0F0)
-#define BIST1_CFG_CTR           (MISC_BASE + 0x0F4)
-#define BIST2_CFG_CTR           (MISC_BASE + 0x0F8)
-#define BIST3_CFG_CTR           (MISC_BASE + 0x0FC)
-#define BIST4_CFG_CTR           (MISC_BASE + 0x100)
-#define BIST5_CFG_CTR           (MISC_BASE + 0x104)
-#define BIST1_STS_RES           (MISC_BASE + 0x108)
-#define BIST2_STS_RES           (MISC_BASE + 0x10C)
-#define BIST3_STS_RES           (MISC_BASE + 0x110)
-#define BIST4_STS_RES           (MISC_BASE + 0x114)
-#define BIST5_STS_RES           (MISC_BASE + 0x118)
-#define SYSERR_CFG_CTR          (MISC_BASE + 0x11C)
 #endif /* __MACH_MISC_REGS_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear.h b/arch/arm/mach-spear3xx/include/mach/spear.h
index 63fd98356919..6d4dadc67633 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear.h
@@ -15,60 +15,27 @@
 #define __MACH_SPEAR3XX_H
 #include <asm/memory.h>
-#include <mach/spear300.h>
-#include <mach/spear310.h>
-#include <mach/spear320.h>
-#define SPEAR3XX_ML_SDRAM_BASE          UL(0x00000000)
-#define SPEAR3XX_ICM9_BASE              UL(0xC0000000)
 /* ICM1 - Low speed connection */
 #define SPEAR3XX_ICM1_2_BASE            UL(0xD0000000)
+#define VA_SPEAR3XX_ICM1_2_BASE         UL(0xFD000000)
 #define SPEAR3XX_ICM1_UART_BASE         UL(0xD0000000)
-#define VA_SPEAR3XX_ICM1_UART_BASE      IO_ADDRESS(SPEAR3XX_ICM1_UART_BASE)
+#define VA_SPEAR3XX_ICM1_UART_BASE      (VA_SPEAR3XX_ICM1_2_BASE | SPEAR3XX_ICM1_UART_BASE)
-#define SPEAR3XX_ICM1_ADC_BASE          UL(0xD0080000)
 #define SPEAR3XX_ICM1_SSP_BASE          UL(0xD0100000)
-#define SPEAR3XX_ICM1_I2C_BASE          UL(0xD0180000)
-#define SPEAR3XX_ICM1_JPEG_BASE         UL(0xD0800000)
-#define SPEAR3XX_ICM1_IRDA_BASE         UL(0xD1000000)
-#define SPEAR3XX_ICM1_SRAM_BASE         UL(0xD2800000)
-/* ICM2 - Application Subsystem */
-#define SPEAR3XX_ICM2_HWACCEL0_BASE     UL(0xD8800000)
-#define SPEAR3XX_ICM2_HWACCEL1_BASE     UL(0xD9000000)
-/* ICM4 - High Speed Connection */
-#define SPEAR3XX_ICM4_BASE              UL(0xE0000000)
-#define SPEAR3XX_ICM4_MII_BASE          UL(0xE0800000)
-#define SPEAR3XX_ICM4_USBD_FIFO_BASE    UL(0xE1000000)
-#define SPEAR3XX_ICM4_USBD_CSR_BASE     UL(0xE1100000)
-#define SPEAR3XX_ICM4_USBD_PLDT_BASE    UL(0xE1200000)
-#define SPEAR3XX_ICM4_USB_EHCI0_1_BASE  UL(0xE1800000)
-#define SPEAR3XX_ICM4_USB_OHCI0_BASE    UL(0xE1900000)
-#define SPEAR3XX_ICM4_USB_OHCI1_BASE    UL(0xE2100000)
-#define SPEAR3XX_ICM4_USB_ARB_BASE      UL(0xE2800000)
 /* ML1 - Multi Layer CPU Subsystem */
 #define SPEAR3XX_ICM3_ML1_2_BASE        UL(0xF0000000)
-#define SPEAR3XX_ML1_TMR_BASE           UL(0xF0000000)
+#define VA_SPEAR6XX_ML_CPU_BASE         UL(0xF0000000)
-#define SPEAR3XX_ML1_VIC_BASE           UL(0xF1100000)
+#define SPEAR3XX_CPU_TMR_BASE           UL(0xF0000000)
-#define VA_SPEAR3XX_ML1_VIC_BASE        IO_ADDRESS(SPEAR3XX_ML1_VIC_BASE)
 /* ICM3 - Basic Subsystem */
-#define SPEAR3XX_ICM3_SMEM_BASE         UL(0xF8000000)
 #define SPEAR3XX_ICM3_SMI_CTRL_BASE     UL(0xFC000000)
+#define VA_SPEAR3XX_ICM3_SMI_CTRL_BASE  UL(0xFC000000)
 #define SPEAR3XX_ICM3_DMA_BASE          UL(0xFC400000)
-#define SPEAR3XX_ICM3_SDRAM_CTRL_BASE   UL(0xFC600000)
-#define SPEAR3XX_ICM3_TMR0_BASE         UL(0xFC800000)
-#define SPEAR3XX_ICM3_WDT_BASE          UL(0xFC880000)
-#define SPEAR3XX_ICM3_RTC_BASE          UL(0xFC900000)
-#define SPEAR3XX_ICM3_GPIO_BASE         UL(0xFC980000)
 #define SPEAR3XX_ICM3_SYS_CTRL_BASE     UL(0xFCA00000)
-#define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE  IO_ADDRESS(SPEAR3XX_ICM3_SYS_CTRL_BASE)
+#define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE  (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_SYS_CTRL_BASE)
 #define SPEAR3XX_ICM3_MISC_REG_BASE     UL(0xFCA80000)
-#define VA_SPEAR3XX_ICM3_MISC_REG_BASE  IO_ADDRESS(SPEAR3XX_ICM3_MISC_REG_BASE)
+#define VA_SPEAR3XX_ICM3_MISC_REG_BASE  (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_MISC_REG_BASE)
-#define SPEAR3XX_ICM3_TMR1_BASE         UL(0xFCB00000)
 /* Debug uart for linux, will be used for debug and uncompress messages */
 #define SPEAR_DBG_UART_BASE             SPEAR3XX_ICM1_UART_BASE
diff --git a/arch/arm/mach-spear3xx/include/mach/spear300.h b/arch/arm/mach-spear3xx/include/mach/spear300.h
deleted file mode 100644
index 3b6ea0729040..000000000000
--- a/arch/arm/mach-spear3xx/include/mach/spear300.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/include/mach/spear300.h
- *
- * SPEAr300 Machine specific definition
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#ifdef  CONFIG_MACH_SPEAR300
-#ifndef __MACH_SPEAR300_H
-#define __MACH_SPEAR300_H
-/* Base address of various IPs */
-#define SPEAR300_TELECOM_BASE           UL(0x50000000)
-/* Interrupt registers offsets and masks */
-#define SPEAR300_INT_ENB_MASK_REG       0x54
-#define SPEAR300_INT_STS_MASK_REG       0x58
-#define SPEAR300_IT_PERS_S_IRQ_MASK     (1 << 0)
-#define SPEAR300_IT_CHANGE_S_IRQ_MASK   (1 << 1)
-#define SPEAR300_I2S_IRQ_MASK           (1 << 2)
-#define SPEAR300_TDM_IRQ_MASK           (1 << 3)
-#define SPEAR300_CAMERA_L_IRQ_MASK      (1 << 4)
-#define SPEAR300_CAMERA_F_IRQ_MASK      (1 << 5)
-#define SPEAR300_CAMERA_V_IRQ_MASK      (1 << 6)
-#define SPEAR300_KEYBOARD_IRQ_MASK      (1 << 7)
-#define SPEAR300_GPIO1_IRQ_MASK         (1 << 8)
-#define SPEAR300_SHIRQ_RAS1_MASK        0x1FF
-#define SPEAR300_CLCD_BASE              UL(0x60000000)
-#define SPEAR300_SDHCI_BASE             UL(0x70000000)
-#define SPEAR300_NAND_0_BASE            UL(0x80000000)
-#define SPEAR300_NAND_1_BASE            UL(0x84000000)
-#define SPEAR300_NAND_2_BASE            UL(0x88000000)
-#define SPEAR300_NAND_3_BASE            UL(0x8c000000)
-#define SPEAR300_NOR_0_BASE             UL(0x90000000)
-#define SPEAR300_NOR_1_BASE             UL(0x91000000)
-#define SPEAR300_NOR_2_BASE             UL(0x92000000)
-#define SPEAR300_NOR_3_BASE             UL(0x93000000)
-#define SPEAR300_FSMC_BASE              UL(0x94000000)
-#define SPEAR300_SOC_CONFIG_BASE        UL(0x99000000)
-#define SPEAR300_KEYBOARD_BASE          UL(0xA0000000)
-#define SPEAR300_GPIO_BASE              UL(0xA9000000)
-#endif /* __MACH_SPEAR300_H */
-#endif /* CONFIG_MACH_SPEAR300 */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear310.h b/arch/arm/mach-spear3xx/include/mach/spear310.h
deleted file mode 100644
index 1567d0da725f..000000000000
--- a/arch/arm/mach-spear3xx/include/mach/spear310.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/include/mach/spear310.h
- *
- * SPEAr310 Machine specific definition
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#ifdef  CONFIG_MACH_SPEAR310
-#ifndef __MACH_SPEAR310_H
-#define __MACH_SPEAR310_H
-#define SPEAR310_NAND_BASE              UL(0x40000000)
-#define SPEAR310_FSMC_BASE              UL(0x44000000)
-#define SPEAR310_UART1_BASE             UL(0xB2000000)
-#define SPEAR310_UART2_BASE             UL(0xB2080000)
-#define SPEAR310_UART3_BASE             UL(0xB2100000)
-#define SPEAR310_UART4_BASE             UL(0xB2180000)
-#define SPEAR310_UART5_BASE             UL(0xB2200000)
-#define SPEAR310_HDLC_BASE              UL(0xB2800000)
-#define SPEAR310_RS485_0_BASE           UL(0xB3000000)
-#define SPEAR310_RS485_1_BASE           UL(0xB3800000)
-#define SPEAR310_SOC_CONFIG_BASE        UL(0xB4000000)
-/* Interrupt registers offsets and masks */
-#define SPEAR310_INT_STS_MASK_REG       0x04
-#define SPEAR310_SMII0_IRQ_MASK         (1 << 0)
-#define SPEAR310_SMII1_IRQ_MASK         (1 << 1)
-#define SPEAR310_SMII2_IRQ_MASK         (1 << 2)
-#define SPEAR310_SMII3_IRQ_MASK         (1 << 3)
-#define SPEAR310_WAKEUP_SMII0_IRQ_MASK  (1 << 4)
-#define SPEAR310_WAKEUP_SMII1_IRQ_MASK  (1 << 5)
-#define SPEAR310_WAKEUP_SMII2_IRQ_MASK  (1 << 6)
-#define SPEAR310_WAKEUP_SMII3_IRQ_MASK  (1 << 7)
-#define SPEAR310_UART1_IRQ_MASK         (1 << 8)
-#define SPEAR310_UART2_IRQ_MASK         (1 << 9)
-#define SPEAR310_UART3_IRQ_MASK         (1 << 10)
-#define SPEAR310_UART4_IRQ_MASK         (1 << 11)
-#define SPEAR310_UART5_IRQ_MASK         (1 << 12)
-#define SPEAR310_EMI_IRQ_MASK           (1 << 13)
-#define SPEAR310_TDM_HDLC_IRQ_MASK      (1 << 14)
-#define SPEAR310_RS485_0_IRQ_MASK       (1 << 15)
-#define SPEAR310_RS485_1_IRQ_MASK       (1 << 16)
-#define SPEAR310_SHIRQ_RAS1_MASK        0x000FF
-#define SPEAR310_SHIRQ_RAS2_MASK        0x01F00
-#define SPEAR310_SHIRQ_RAS3_MASK        0x02000
-#define SPEAR310_SHIRQ_INTRCOMM_RAS_MASK        0x1C000
-#endif /* __MACH_SPEAR310_H */
-#endif /* CONFIG_MACH_SPEAR310 */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear320.h b/arch/arm/mach-spear3xx/include/mach/spear320.h
deleted file mode 100644
index 8cfa83fa1296..000000000000
--- a/arch/arm/mach-spear3xx/include/mach/spear320.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/include/mach/spear320.h
- *
- * SPEAr320 Machine specific definition
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#ifdef  CONFIG_MACH_SPEAR320
-#ifndef __MACH_SPEAR320_H
-#define __MACH_SPEAR320_H
-#define SPEAR320_EMI_CTRL_BASE          UL(0x40000000)
-#define SPEAR320_FSMC_BASE              UL(0x4C000000)
-#define SPEAR320_NAND_BASE              UL(0x50000000)
-#define SPEAR320_I2S_BASE               UL(0x60000000)
-#define SPEAR320_SDHCI_BASE             UL(0x70000000)
-#define SPEAR320_CLCD_BASE              UL(0x90000000)
-#define SPEAR320_PAR_PORT_BASE          UL(0xA0000000)
-#define SPEAR320_CAN0_BASE              UL(0xA1000000)
-#define SPEAR320_CAN1_BASE              UL(0xA2000000)
-#define SPEAR320_UART1_BASE             UL(0xA3000000)
-#define SPEAR320_UART2_BASE             UL(0xA4000000)
-#define SPEAR320_SSP0_BASE              UL(0xA5000000)
-#define SPEAR320_SSP1_BASE              UL(0xA6000000)
-#define SPEAR320_I2C_BASE               UL(0xA7000000)
-#define SPEAR320_PWM_BASE               UL(0xA8000000)
-#define SPEAR320_SMII0_BASE             UL(0xAA000000)
-#define SPEAR320_SMII1_BASE             UL(0xAB000000)
-#define SPEAR320_SOC_CONFIG_BASE        UL(0xB3000000)
-/* Interrupt registers offsets and masks */
-#define SPEAR320_INT_STS_MASK_REG               0x04
-#define SPEAR320_INT_CLR_MASK_REG               0x04
-#define SPEAR320_INT_ENB_MASK_REG               0x08
-#define SPEAR320_GPIO_IRQ_MASK                  (1 << 0)
-#define SPEAR320_I2S_PLAY_IRQ_MASK              (1 << 1)
-#define SPEAR320_I2S_REC_IRQ_MASK               (1 << 2)
-#define SPEAR320_EMI_IRQ_MASK                   (1 << 7)
-#define SPEAR320_CLCD_IRQ_MASK                  (1 << 8)
-#define SPEAR320_SPP_IRQ_MASK                   (1 << 9)
-#define SPEAR320_SDHCI_IRQ_MASK                 (1 << 10)
-#define SPEAR320_CAN_U_IRQ_MASK                 (1 << 11)
-#define SPEAR320_CAN_L_IRQ_MASK                 (1 << 12)
-#define SPEAR320_UART1_IRQ_MASK                 (1 << 13)
-#define SPEAR320_UART2_IRQ_MASK                 (1 << 14)
-#define SPEAR320_SSP1_IRQ_MASK                  (1 << 15)
-#define SPEAR320_SSP2_IRQ_MASK                  (1 << 16)
-#define SPEAR320_SMII0_IRQ_MASK                 (1 << 17)
-#define SPEAR320_MII1_SMII1_IRQ_MASK            (1 << 18)
-#define SPEAR320_WAKEUP_SMII0_IRQ_MASK          (1 << 19)
-#define SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK     (1 << 20)
-#define SPEAR320_I2C1_IRQ_MASK                  (1 << 21)
-#define SPEAR320_SHIRQ_RAS1_MASK                0x000380
-#define SPEAR320_SHIRQ_RAS3_MASK                0x000007
-#define SPEAR320_SHIRQ_INTRCOMM_RAS_MASK        0x3FF800
-#endif /* __MACH_SPEAR320_H */
-#endif /* CONFIG_MACH_SPEAR320 */
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
index f7db66812abb..f75fe25a620c 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -3,372 +3,62 @@
 *
 * SPEAr300 machine source file
 *
- * Copyright (C) 2009 ST Microelectronics
+ * Copyright (C) 2009-2012 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
+ * Viresh Kumar <viresh.kumar@st.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */
-#include <linux/types.h>
+#define pr_fmt(fmt) "SPEAr300: " fmt
-#include <linux/amba/pl061.h>
-#include <linux/ptrace.h>
+#include <linux/amba/pl08x.h>
-#include <asm/irq.h>
+#include <linux/of_platform.h>
+#include <asm/hardware/vic.h>
+#include <asm/mach/arch.h>
 #include <plat/shirq.h>
 #include <mach/generic.h>
-#include <mach/hardware.h>
+#include <mach/spear.h>
-/* pad multiplexing support */
+/* Base address of various IPs */
-/* muxing registers */
+#define SPEAR300_TELECOM_BASE           UL(0x50000000)
-#define PAD_MUX_CONFIG_REG      0x00
-#define MODE_CONFIG_REG         0x04
+/* Interrupt registers offsets and masks */
+#define SPEAR300_INT_ENB_MASK_REG       0x54
-/* modes */
+#define SPEAR300_INT_STS_MASK_REG       0x58
-#define NAND_MODE                       (1 << 0)
+#define SPEAR300_IT_PERS_S_IRQ_MASK     (1 << 0)
-#define NOR_MODE                        (1 << 1)
+#define SPEAR300_IT_CHANGE_S_IRQ_MASK   (1 << 1)
-#define PHOTO_FRAME_MODE                (1 << 2)
+#define SPEAR300_I2S_IRQ_MASK           (1 << 2)
-#define LEND_IP_PHONE_MODE              (1 << 3)
+#define SPEAR300_TDM_IRQ_MASK           (1 << 3)
-#define HEND_IP_PHONE_MODE              (1 << 4)
+#define SPEAR300_CAMERA_L_IRQ_MASK      (1 << 4)
-#define LEND_WIFI_PHONE_MODE            (1 << 5)
+#define SPEAR300_CAMERA_F_IRQ_MASK      (1 << 5)
-#define HEND_WIFI_PHONE_MODE            (1 << 6)
+#define SPEAR300_CAMERA_V_IRQ_MASK      (1 << 6)
-#define ATA_PABX_WI2S_MODE              (1 << 7)
+#define SPEAR300_KEYBOARD_IRQ_MASK      (1 << 7)
-#define ATA_PABX_I2S_MODE               (1 << 8)
+#define SPEAR300_GPIO1_IRQ_MASK         (1 << 8)
-#define CAML_LCDW_MODE                  (1 << 9)
-#define CAMU_LCD_MODE                   (1 << 10)
+#define SPEAR300_SHIRQ_RAS1_MASK        0x1FF
-#define CAMU_WLCD_MODE                  (1 << 11)
-#define CAML_LCD_MODE                   (1 << 12)
+#define SPEAR300_SOC_CONFIG_BASE        UL(0x99000000)
-#define ALL_MODES                       0x1FFF
-struct pmx_mode spear300_nand_mode = {
+/* SPEAr300 Virtual irq definitions */
-        .id = NAND_MODE,
+/* IRQs sharing IRQ_GEN_RAS_1 */
-        .name = "nand mode",
+#define SPEAR300_VIRQ_IT_PERS_S                 (SPEAR3XX_VIRQ_START + 0)
-        .mask = 0x00,
+#define SPEAR300_VIRQ_IT_CHANGE_S               (SPEAR3XX_VIRQ_START + 1)
-};
+#define SPEAR300_VIRQ_I2S                       (SPEAR3XX_VIRQ_START + 2)
+#define SPEAR300_VIRQ_TDM                       (SPEAR3XX_VIRQ_START + 3)
-struct pmx_mode spear300_nor_mode = {
+#define SPEAR300_VIRQ_CAMERA_L                  (SPEAR3XX_VIRQ_START + 4)
-        .id = NOR_MODE,
+#define SPEAR300_VIRQ_CAMERA_F                  (SPEAR3XX_VIRQ_START + 5)
-        .name = "nor mode",
+#define SPEAR300_VIRQ_CAMERA_V                  (SPEAR3XX_VIRQ_START + 6)
-        .mask = 0x01,
+#define SPEAR300_VIRQ_KEYBOARD                  (SPEAR3XX_VIRQ_START + 7)
-};
+#define SPEAR300_VIRQ_GPIO1                     (SPEAR3XX_VIRQ_START + 8)
-struct pmx_mode spear300_photo_frame_mode = {
+/* IRQs sharing IRQ_GEN_RAS_3 */
-        .id = PHOTO_FRAME_MODE,
+#define SPEAR300_IRQ_CLCD                       SPEAR3XX_IRQ_GEN_RAS_3
-        .name = "photo frame mode",
-        .mask = 0x02,
+/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
-};
+#define SPEAR300_IRQ_SDHCI                      SPEAR3XX_IRQ_INTRCOMM_RAS_ARM
-struct pmx_mode spear300_lend_ip_phone_mode = {
-        .id = LEND_IP_PHONE_MODE,
-        .name = "lend ip phone mode",
-        .mask = 0x03,
-};
-struct pmx_mode spear300_hend_ip_phone_mode = {
-        .id = HEND_IP_PHONE_MODE,
-        .name = "hend ip phone mode",
-        .mask = 0x04,
-};
-struct pmx_mode spear300_lend_wifi_phone_mode = {
-        .id = LEND_WIFI_PHONE_MODE,
-        .name = "lend wifi phone mode",
-        .mask = 0x05,
-};
-struct pmx_mode spear300_hend_wifi_phone_mode = {
-        .id = HEND_WIFI_PHONE_MODE,
-        .name = "hend wifi phone mode",
-        .mask = 0x06,
-};
-struct pmx_mode spear300_ata_pabx_wi2s_mode = {
-        .id = ATA_PABX_WI2S_MODE,
-        .name = "ata pabx wi2s mode",
-        .mask = 0x07,
-};
-struct pmx_mode spear300_ata_pabx_i2s_mode = {
-        .id = ATA_PABX_I2S_MODE,
-        .name = "ata pabx i2s mode",
-        .mask = 0x08,
-};
-struct pmx_mode spear300_caml_lcdw_mode = {
-        .id = CAML_LCDW_MODE,
-        .name = "caml lcdw mode",
-        .mask = 0x0C,
-};
-struct pmx_mode spear300_camu_lcd_mode = {
-        .id = CAMU_LCD_MODE,
-        .name = "camu lcd mode",
-        .mask = 0x0D,
-};
-struct pmx_mode spear300_camu_wlcd_mode = {
-        .id = CAMU_WLCD_MODE,
-        .name = "camu wlcd mode",
-        .mask = 0x0E,
-};
-struct pmx_mode spear300_caml_lcd_mode = {
-        .id = CAML_LCD_MODE,
-        .name = "caml lcd mode",
-        .mask = 0x0F,
-};
-/* devices */
-static struct pmx_dev_mode pmx_fsmc_2_chips_modes[] = {
-        {
-                .ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
-                        ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
-                .mask = PMX_FIRDA_MASK,
-        },
-};
-struct pmx_dev spear300_pmx_fsmc_2_chips = {
-        .name = "fsmc_2_chips",
-        .modes = pmx_fsmc_2_chips_modes,
-        .mode_count = ARRAY_SIZE(pmx_fsmc_2_chips_modes),
-        .enb_on_reset = 1,
-};
-static struct pmx_dev_mode pmx_fsmc_4_chips_modes[] = {
-        {
-                .ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
-                        ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
-                .mask = PMX_FIRDA_MASK | PMX_UART0_MASK,
-        },
-};
-struct pmx_dev spear300_pmx_fsmc_4_chips = {
-        .name = "fsmc_4_chips",
-        .modes = pmx_fsmc_4_chips_modes,
-        .mode_count = ARRAY_SIZE(pmx_fsmc_4_chips_modes),
-        .enb_on_reset = 1,
-};
-static struct pmx_dev_mode pmx_keyboard_modes[] = {
-        {
-                .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE |
-                        LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
-                        CAML_LCDW_MODE | CAMU_LCD_MODE | CAMU_WLCD_MODE |
-                        CAML_LCD_MODE,
-                .mask = 0x0,
-        },
-};
-struct pmx_dev spear300_pmx_keyboard = {
-        .name = "keyboard",
-        .modes = pmx_keyboard_modes,
-        .mode_count = ARRAY_SIZE(pmx_keyboard_modes),
-        .enb_on_reset = 1,
-};
-static struct pmx_dev_mode pmx_clcd_modes[] = {
-        {
-                .ids = PHOTO_FRAME_MODE,
-                .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK ,
-        }, {
-                .ids = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE |
-                        CAMU_LCD_MODE | CAML_LCD_MODE,
-                .mask = PMX_TIMER_3_4_MASK,
-        },
-};
-struct pmx_dev spear300_pmx_clcd = {
-        .name = "clcd",
-        .modes = pmx_clcd_modes,
-        .mode_count = ARRAY_SIZE(pmx_clcd_modes),
-        .enb_on_reset = 1,
-};
-static struct pmx_dev_mode pmx_telecom_gpio_modes[] = {
-        {
-                .ids = PHOTO_FRAME_MODE | CAMU_LCD_MODE | CAML_LCD_MODE,
-                .mask = PMX_MII_MASK,
-        }, {
-                .ids = LEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE,
-                .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
-        }, {
-                .ids = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_WLCD_MODE,
-                .mask = PMX_MII_MASK | PMX_TIMER_3_4_MASK,
-        }, {
-                .ids = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE,
-                .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK,
-        }, {
-                .ids = ATA_PABX_WI2S_MODE,
-                .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK
-                        | PMX_UART0_MODEM_MASK,
-        },
-};
-struct pmx_dev spear300_pmx_telecom_gpio = {
-        .name = "telecom_gpio",
-        .modes = pmx_telecom_gpio_modes,
-        .mode_count = ARRAY_SIZE(pmx_telecom_gpio_modes),
-        .enb_on_reset = 1,
-};
-static struct pmx_dev_mode pmx_telecom_tdm_modes[] = {
-        {
-                .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
-                        HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE
-                        | HEND_WIFI_PHONE_MODE | ATA_PABX_WI2S_MODE
-                        | ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
-                        | CAMU_WLCD_MODE | CAML_LCD_MODE,
-                .mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK,
-        },
-};
-struct pmx_dev spear300_pmx_telecom_tdm = {
-        .name = "telecom_tdm",
-        .modes = pmx_telecom_tdm_modes,
-        .mode_count = ARRAY_SIZE(pmx_telecom_tdm_modes),
-        .enb_on_reset = 1,
-};
-static struct pmx_dev_mode pmx_telecom_spi_cs_i2c_clk_modes[] = {
-        {
-                .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE |
-                        LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE
-                        | ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE |
-                        CAML_LCDW_MODE | CAML_LCD_MODE,
-                .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
-        },
-};
-struct pmx_dev spear300_pmx_telecom_spi_cs_i2c_clk = {
-        .name = "telecom_spi_cs_i2c_clk",
-        .modes = pmx_telecom_spi_cs_i2c_clk_modes,
-        .mode_count = ARRAY_SIZE(pmx_telecom_spi_cs_i2c_clk_modes),
-        .enb_on_reset = 1,
-};
-static struct pmx_dev_mode pmx_telecom_camera_modes[] = {
-        {
-                .ids = CAML_LCDW_MODE | CAML_LCD_MODE,
-                .mask = PMX_MII_MASK,
-        }, {
-                .ids = CAMU_LCD_MODE | CAMU_WLCD_MODE,
-                .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK | PMX_MII_MASK,
-        },
-};
-struct pmx_dev spear300_pmx_telecom_camera = {
-        .name = "telecom_camera",
-        .modes = pmx_telecom_camera_modes,
-        .mode_count = ARRAY_SIZE(pmx_telecom_camera_modes),
-        .enb_on_reset = 1,
-};
-static struct pmx_dev_mode pmx_telecom_dac_modes[] = {
-        {
-                .ids = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
-                        | CAMU_WLCD_MODE | CAML_LCD_MODE,
-                .mask = PMX_TIMER_1_2_MASK,
-        },
-};
-struct pmx_dev spear300_pmx_telecom_dac = {
-        .name = "telecom_dac",
-        .modes = pmx_telecom_dac_modes,
-        .mode_count = ARRAY_SIZE(pmx_telecom_dac_modes),
-        .enb_on_reset = 1,
-};
-static struct pmx_dev_mode pmx_telecom_i2s_modes[] = {
-        {
-                .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE
-                        | LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
-                        ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
-                        | CAMU_WLCD_MODE | CAML_LCD_MODE,
-                .mask = PMX_UART0_MODEM_MASK,
-        },
-};
-struct pmx_dev spear300_pmx_telecom_i2s = {
-        .name = "telecom_i2s",
-        .modes = pmx_telecom_i2s_modes,
-        .mode_count = ARRAY_SIZE(pmx_telecom_i2s_modes),
-        .enb_on_reset = 1,
-};
-static struct pmx_dev_mode pmx_telecom_boot_pins_modes[] = {
-        {
-                .ids = NAND_MODE | NOR_MODE,
-                .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK |
-                        PMX_TIMER_3_4_MASK,
-        },
-};
-struct pmx_dev spear300_pmx_telecom_boot_pins = {
-        .name = "telecom_boot_pins",
-        .modes = pmx_telecom_boot_pins_modes,
-        .mode_count = ARRAY_SIZE(pmx_telecom_boot_pins_modes),
-        .enb_on_reset = 1,
-};
-static struct pmx_dev_mode pmx_telecom_sdhci_4bit_modes[] = {
-        {
-                .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
-                        HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
-                        HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE |
-                        CAMU_WLCD_MODE | CAML_LCD_MODE | ATA_PABX_WI2S_MODE |
-                        ATA_PABX_I2S_MODE,
-                .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
-                        PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
-                        PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
-        },
-};
-struct pmx_dev spear300_pmx_telecom_sdhci_4bit = {
-        .name = "telecom_sdhci_4bit",
-        .modes = pmx_telecom_sdhci_4bit_modes,
-        .mode_count = ARRAY_SIZE(pmx_telecom_sdhci_4bit_modes),
-        .enb_on_reset = 1,
-};
-static struct pmx_dev_mode pmx_telecom_sdhci_8bit_modes[] = {
-        {
-                .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
-                        HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
-                        HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE |
-                        CAMU_WLCD_MODE | CAML_LCD_MODE,
-                .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
-                        PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
-                        PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK | PMX_MII_MASK,
-        },
-};
-struct pmx_dev spear300_pmx_telecom_sdhci_8bit = {
-        .name = "telecom_sdhci_8bit",
-        .modes = pmx_telecom_sdhci_8bit_modes,
-        .mode_count = ARRAY_SIZE(pmx_telecom_sdhci_8bit_modes),
-        .enb_on_reset = 1,
-};
-static struct pmx_dev_mode pmx_gpio1_modes[] = {
-        {
-                .ids = PHOTO_FRAME_MODE,
-                .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK |
-                        PMX_TIMER_3_4_MASK,
-        },
-};
-struct pmx_dev spear300_pmx_gpio1 = {
-        .name = "arm gpio1",
-        .modes = pmx_gpio1_modes,
-        .mode_count = ARRAY_SIZE(pmx_gpio1_modes),
-        .enb_on_reset = 1,
-};
-/* pmx driver structure */
-static struct pmx_driver pmx_driver = {
-        .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x0000000f},
-        .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
-};
 /* spear3xx shared irq */
 static struct shirq_dev_config shirq_ras1_config[] = {
@@ -423,45 +113,239 @@ static struct spear_shirq shirq_ras1 = {
        },
 };
-/* Add spear300 specific devices here */
+/* DMAC platform data's slave info */
-/* arm gpio1 device registration */
+struct pl08x_channel_data spear300_dma_info[] = {
-static struct pl061_platform_data gpio1_plat_data = {
+        {
-        .gpio_base      = 8,
+                .bus_id = "uart0_rx",
-        .irq_base       = SPEAR300_GPIO1_INT_BASE,
+                .min_signal = 2,
+                .max_signal = 2,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart0_tx",
+                .min_signal = 3,
+                .max_signal = 3,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ssp0_rx",
+                .min_signal = 8,
+                .max_signal = 8,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ssp0_tx",
+                .min_signal = 9,
+                .max_signal = 9,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "i2c_rx",
+                .min_signal = 10,
+                .max_signal = 10,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "i2c_tx",
+                .min_signal = 11,
+                .max_signal = 11,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "irda",
+                .min_signal = 12,
+                .max_signal = 12,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "adc",
+                .min_signal = 13,
+                .max_signal = 13,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "to_jpeg",
+                .min_signal = 14,
+                .max_signal = 14,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "from_jpeg",
+                .min_signal = 15,
+                .max_signal = 15,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras0_rx",
+                .min_signal = 0,
+                .max_signal = 0,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras0_tx",
+                .min_signal = 1,
+                .max_signal = 1,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras1_rx",
+                .min_signal = 2,
+                .max_signal = 2,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras1_tx",
+                .min_signal = 3,
+                .max_signal = 3,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras2_rx",
+                .min_signal = 4,
+                .max_signal = 4,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras2_tx",
+                .min_signal = 5,
+                .max_signal = 5,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras3_rx",
+                .min_signal = 6,
+                .max_signal = 6,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras3_tx",
+                .min_signal = 7,
+                .max_signal = 7,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras4_rx",
+                .min_signal = 8,
+                .max_signal = 8,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras4_tx",
+                .min_signal = 9,
+                .max_signal = 9,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras5_rx",
+                .min_signal = 10,
+                .max_signal = 10,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras5_tx",
+                .min_signal = 11,
+                .max_signal = 11,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras6_rx",
+                .min_signal = 12,
+                .max_signal = 12,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras6_tx",
+                .min_signal = 13,
+                .max_signal = 13,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras7_rx",
+                .min_signal = 14,
+                .max_signal = 14,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras7_tx",
+                .min_signal = 15,
+                .max_signal = 15,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        },
 };
-AMBA_APB_DEVICE(spear300_gpio1, "gpio1", 0, SPEAR300_GPIO_BASE,
+/* Add SPEAr300 auxdata to pass platform data */
-        {SPEAR300_VIRQ_GPIO1}, &gpio1_plat_data);
+static struct of_dev_auxdata spear300_auxdata_lookup[] __initdata = {
+        OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
+                        &pl022_plat_data),
+        OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
+                        &pl080_plat_data),
+        {}
+};
-/* spear300 routines */
+static void __init spear300_dt_init(void)
-void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
-                u8 pmx_dev_count)
 {
-        int ret = 0;
+        int ret;
+        pl080_plat_data.slave_channels = spear300_dma_info;
+        pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear300_dma_info);
-        /* call spear3xx family common init function */
+        of_platform_populate(NULL, of_default_bus_match_table,
-        spear3xx_init();
+                        spear300_auxdata_lookup, NULL);
        /* shared irq registration */
        shirq_ras1.regs.base = ioremap(SPEAR300_TELECOM_BASE, SZ_4K);
        if (shirq_ras1.regs.base) {
                ret = spear_shirq_register(&shirq_ras1);
                if (ret)
-                        printk(KERN_ERR "Error registering Shared IRQ\n");
+                        pr_err("Error registering Shared IRQ\n");
        }
+}
-        /* pmx initialization */
+static const char * const spear300_dt_board_compat[] = {
-        pmx_driver.mode = pmx_mode;
+        "st,spear300",
-        pmx_driver.devs = pmx_devs;
+        "st,spear300-evb",
-        pmx_driver.devs_count = pmx_dev_count;
+        NULL,
+};
-        pmx_driver.base = ioremap(SPEAR300_SOC_CONFIG_BASE, SZ_4K);
+static void __init spear300_map_io(void)
-        if (pmx_driver.base) {
+{
-                ret = pmx_register(&pmx_driver);
+        spear3xx_map_io();
-                if (ret)
+        spear300_clk_init();
-                        printk(KERN_ERR "padmux: registration failed. err no"
-                                        ": %d\n", ret);
-                /* Free Mapping, device selection already done */
-                iounmap(pmx_driver.base);
-        }
 }
+DT_MACHINE_START(SPEAR300_DT, "ST SPEAr300 SoC with Flattened Device Tree")
+        .map_io         =       spear300_map_io,
+        .init_irq       =       spear3xx_dt_init_irq,
+        .handle_irq     =       vic_handle_irq,
+        .timer          =       &spear3xx_timer,
+        .init_machine   =       spear300_dt_init,
+        .restart        =       spear_restart,
+        .dt_compat      =       spear300_dt_board_compat,
+MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear300_evb.c b/arch/arm/mach-spear3xx/spear300_evb.c
deleted file mode 100644
index 3462ab9d6122..000000000000
--- a/arch/arm/mach-spear3xx/spear300_evb.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/spear300_evb.c
- *
- * SPEAr300 evaluation board source file
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <asm/hardware/vic.h>
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-#include <mach/generic.h>
-#include <mach/hardware.h>
-/* padmux devices to enable */
-static struct pmx_dev *pmx_devs[] = {
-        /* spear3xx specific devices */
-        &spear3xx_pmx_i2c,
-        &spear3xx_pmx_ssp_cs,
-        &spear3xx_pmx_ssp,
-        &spear3xx_pmx_mii,
-        &spear3xx_pmx_uart0,
-        /* spear300 specific devices */
-        &spear300_pmx_fsmc_2_chips,
-        &spear300_pmx_clcd,
-        &spear300_pmx_telecom_sdhci_4bit,
-        &spear300_pmx_gpio1,
-};
-static struct amba_device *amba_devs[] __initdata = {
-        /* spear3xx specific devices */
-        &spear3xx_gpio_device,
-        &spear3xx_uart_device,
-        /* spear300 specific devices */
-        &spear300_gpio1_device,
-};
-static struct platform_device *plat_devs[] __initdata = {
-        /* spear3xx specific devices */
-        /* spear300 specific devices */
-};
-static void __init spear300_evb_init(void)
-{
-        unsigned int i;
-        /* call spear300 machine init function */
-        spear300_init(&spear300_photo_frame_mode, pmx_devs,
-                        ARRAY_SIZE(pmx_devs));
-        /* Add Platform Devices */
-        platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
-        /* Add Amba Devices */
-        for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
-                amba_device_register(amba_devs[i], &iomem_resource);
-}
-MACHINE_START(SPEAR300, "ST-SPEAR300-EVB")
-        .atag_offset    =       0x100,
-        .map_io         =       spear3xx_map_io,
-        .init_irq       =       spear3xx_init_irq,
-        .handle_irq     =       vic_handle_irq,
-        .timer          =       &spear3xx_timer,
-        .init_machine   =       spear300_evb_init,
-        .restart        =       spear_restart,
-MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c
index febaa6fcfb6a..f0842a58dc02 100644
--- a/arch/arm/mach-spear3xx/spear310.c
+++ b/arch/arm/mach-spear3xx/spear310.c
@@ -3,141 +3,84 @@
 *
 * SPEAr310 machine source file
 *
- * Copyright (C) 2009 ST Microelectronics
+ * Copyright (C) 2009-2012 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
+ * Viresh Kumar <viresh.kumar@st.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */
-#include <linux/ptrace.h>
+#define pr_fmt(fmt) "SPEAr310: " fmt
-#include <asm/irq.h>
+#include <linux/amba/pl08x.h>
+#include <linux/amba/serial.h>
+#include <linux/of_platform.h>
+#include <asm/hardware/vic.h>
+#include <asm/mach/arch.h>
 #include <plat/shirq.h>
 #include <mach/generic.h>
-#include <mach/hardware.h>
+#include <mach/spear.h>
-/* pad multiplexing support */
+#define SPEAR310_UART1_BASE             UL(0xB2000000)
-/* muxing registers */
+#define SPEAR310_UART2_BASE             UL(0xB2080000)
-#define PAD_MUX_CONFIG_REG      0x08
+#define SPEAR310_UART3_BASE             UL(0xB2100000)
+#define SPEAR310_UART4_BASE             UL(0xB2180000)
-/* devices */
+#define SPEAR310_UART5_BASE             UL(0xB2200000)
-static struct pmx_dev_mode pmx_emi_cs_0_1_4_5_modes[] = {
+#define SPEAR310_SOC_CONFIG_BASE        UL(0xB4000000)
-        {
-                .ids = 0x00,
+/* Interrupt registers offsets and masks */
-                .mask = PMX_TIMER_3_4_MASK,
+#define SPEAR310_INT_STS_MASK_REG       0x04
-        },
+#define SPEAR310_SMII0_IRQ_MASK         (1 << 0)
-};
+#define SPEAR310_SMII1_IRQ_MASK         (1 << 1)
+#define SPEAR310_SMII2_IRQ_MASK         (1 << 2)
-struct pmx_dev spear310_pmx_emi_cs_0_1_4_5 = {
+#define SPEAR310_SMII3_IRQ_MASK         (1 << 3)
-        .name = "emi_cs_0_1_4_5",
+#define SPEAR310_WAKEUP_SMII0_IRQ_MASK  (1 << 4)
-        .modes = pmx_emi_cs_0_1_4_5_modes,
+#define SPEAR310_WAKEUP_SMII1_IRQ_MASK  (1 << 5)
-        .mode_count = ARRAY_SIZE(pmx_emi_cs_0_1_4_5_modes),
+#define SPEAR310_WAKEUP_SMII2_IRQ_MASK  (1 << 6)
-        .enb_on_reset = 1,
+#define SPEAR310_WAKEUP_SMII3_IRQ_MASK  (1 << 7)
-};
+#define SPEAR310_UART1_IRQ_MASK         (1 << 8)
+#define SPEAR310_UART2_IRQ_MASK         (1 << 9)
-static struct pmx_dev_mode pmx_emi_cs_2_3_modes[] = {
+#define SPEAR310_UART3_IRQ_MASK         (1 << 10)
-        {
+#define SPEAR310_UART4_IRQ_MASK         (1 << 11)
-                .ids = 0x00,
+#define SPEAR310_UART5_IRQ_MASK         (1 << 12)
-                .mask = PMX_TIMER_1_2_MASK,
+#define SPEAR310_EMI_IRQ_MASK           (1 << 13)
-        },
+#define SPEAR310_TDM_HDLC_IRQ_MASK      (1 << 14)
-};
+#define SPEAR310_RS485_0_IRQ_MASK       (1 << 15)
+#define SPEAR310_RS485_1_IRQ_MASK       (1 << 16)
-struct pmx_dev spear310_pmx_emi_cs_2_3 = {
-        .name = "emi_cs_2_3",
+#define SPEAR310_SHIRQ_RAS1_MASK        0x000FF
-        .modes = pmx_emi_cs_2_3_modes,
+#define SPEAR310_SHIRQ_RAS2_MASK        0x01F00
-        .mode_count = ARRAY_SIZE(pmx_emi_cs_2_3_modes),
+#define SPEAR310_SHIRQ_RAS3_MASK        0x02000
-        .enb_on_reset = 1,
+#define SPEAR310_SHIRQ_INTRCOMM_RAS_MASK        0x1C000
-};
+/* SPEAr310 Virtual irq definitions */
-static struct pmx_dev_mode pmx_uart1_modes[] = {
+/* IRQs sharing IRQ_GEN_RAS_1 */
-        {
+#define SPEAR310_VIRQ_SMII0                     (SPEAR3XX_VIRQ_START + 0)
-                .ids = 0x00,
+#define SPEAR310_VIRQ_SMII1                     (SPEAR3XX_VIRQ_START + 1)
-                .mask = PMX_FIRDA_MASK,
+#define SPEAR310_VIRQ_SMII2                     (SPEAR3XX_VIRQ_START + 2)
-        },
+#define SPEAR310_VIRQ_SMII3                     (SPEAR3XX_VIRQ_START + 3)
-};
+#define SPEAR310_VIRQ_WAKEUP_SMII0              (SPEAR3XX_VIRQ_START + 4)
+#define SPEAR310_VIRQ_WAKEUP_SMII1              (SPEAR3XX_VIRQ_START + 5)
-struct pmx_dev spear310_pmx_uart1 = {
+#define SPEAR310_VIRQ_WAKEUP_SMII2              (SPEAR3XX_VIRQ_START + 6)
-        .name = "uart1",
+#define SPEAR310_VIRQ_WAKEUP_SMII3              (SPEAR3XX_VIRQ_START + 7)
-        .modes = pmx_uart1_modes,
-        .mode_count = ARRAY_SIZE(pmx_uart1_modes),
+/* IRQs sharing IRQ_GEN_RAS_2 */
-        .enb_on_reset = 1,
+#define SPEAR310_VIRQ_UART1                     (SPEAR3XX_VIRQ_START + 8)
-};
+#define SPEAR310_VIRQ_UART2                     (SPEAR3XX_VIRQ_START + 9)
+#define SPEAR310_VIRQ_UART3                     (SPEAR3XX_VIRQ_START + 10)
-static struct pmx_dev_mode pmx_uart2_modes[] = {
+#define SPEAR310_VIRQ_UART4                     (SPEAR3XX_VIRQ_START + 11)
-        {
+#define SPEAR310_VIRQ_UART5                     (SPEAR3XX_VIRQ_START + 12)
-                .ids = 0x00,
-                .mask = PMX_TIMER_1_2_MASK,
+/* IRQs sharing IRQ_GEN_RAS_3 */
-        },
+#define SPEAR310_VIRQ_EMI                       (SPEAR3XX_VIRQ_START + 13)
-};
+#define SPEAR310_VIRQ_PLGPIO                    (SPEAR3XX_VIRQ_START + 14)
-struct pmx_dev spear310_pmx_uart2 = {
+/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
-        .name = "uart2",
+#define SPEAR310_VIRQ_TDM_HDLC                  (SPEAR3XX_VIRQ_START + 15)
-        .modes = pmx_uart2_modes,
+#define SPEAR310_VIRQ_RS485_0                   (SPEAR3XX_VIRQ_START + 16)
-        .mode_count = ARRAY_SIZE(pmx_uart2_modes),
+#define SPEAR310_VIRQ_RS485_1                   (SPEAR3XX_VIRQ_START + 17)
-        .enb_on_reset = 1,
-};
-static struct pmx_dev_mode pmx_uart3_4_5_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_UART0_MODEM_MASK,
-        },
-};
-struct pmx_dev spear310_pmx_uart3_4_5 = {
-        .name = "uart3_4_5",
-        .modes = pmx_uart3_4_5_modes,
-        .mode_count = ARRAY_SIZE(pmx_uart3_4_5_modes),
-        .enb_on_reset = 1,
-};
-static struct pmx_dev_mode pmx_fsmc_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_SSP_CS_MASK,
-        },
-};
-struct pmx_dev spear310_pmx_fsmc = {
-        .name = "fsmc",
-        .modes = pmx_fsmc_modes,
-        .mode_count = ARRAY_SIZE(pmx_fsmc_modes),
-        .enb_on_reset = 1,
-};
-static struct pmx_dev_mode pmx_rs485_0_1_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_MII_MASK,
-        },
-};
-struct pmx_dev spear310_pmx_rs485_0_1 = {
-        .name = "rs485_0_1",
-        .modes = pmx_rs485_0_1_modes,
-        .mode_count = ARRAY_SIZE(pmx_rs485_0_1_modes),
-        .enb_on_reset = 1,
-};
-static struct pmx_dev_mode pmx_tdm0_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_MII_MASK,
-        },
-};
-struct pmx_dev spear310_pmx_tdm0 = {
-        .name = "tdm0",
-        .modes = pmx_tdm0_modes,
-        .mode_count = ARRAY_SIZE(pmx_tdm0_modes),
-        .enb_on_reset = 1,
-};
-/* pmx driver structure */
-static struct pmx_driver pmx_driver = {
-        .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
-};
 /* spear3xx shared irq */
 static struct shirq_dev_config shirq_ras1_config[] = {
@@ -255,17 +198,247 @@ static struct spear_shirq shirq_intrcomm_ras = {
        },
 };
-/* Add spear310 specific devices here */
+/* DMAC platform data's slave info */
+struct pl08x_channel_data spear310_dma_info[] = {
+        {
+                .bus_id = "uart0_rx",
+                .min_signal = 2,
+                .max_signal = 2,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart0_tx",
+                .min_signal = 3,
+                .max_signal = 3,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ssp0_rx",
+                .min_signal = 8,
+                .max_signal = 8,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ssp0_tx",
+                .min_signal = 9,
+                .max_signal = 9,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "i2c_rx",
+                .min_signal = 10,
+                .max_signal = 10,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "i2c_tx",
+                .min_signal = 11,
+                .max_signal = 11,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "irda",
+                .min_signal = 12,
+                .max_signal = 12,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "adc",
+                .min_signal = 13,
+                .max_signal = 13,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "to_jpeg",
+                .min_signal = 14,
+                .max_signal = 14,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "from_jpeg",
+                .min_signal = 15,
+                .max_signal = 15,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart1_rx",
+                .min_signal = 0,
+                .max_signal = 0,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart1_tx",
+                .min_signal = 1,
+                .max_signal = 1,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart2_rx",
+                .min_signal = 2,
+                .max_signal = 2,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart2_tx",
+                .min_signal = 3,
+                .max_signal = 3,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart3_rx",
+                .min_signal = 4,
+                .max_signal = 4,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart3_tx",
+                .min_signal = 5,
+                .max_signal = 5,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart4_rx",
+                .min_signal = 6,
+                .max_signal = 6,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart4_tx",
+                .min_signal = 7,
+                .max_signal = 7,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart5_rx",
+                .min_signal = 8,
+                .max_signal = 8,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart5_tx",
+                .min_signal = 9,
+                .max_signal = 9,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras5_rx",
+                .min_signal = 10,
+                .max_signal = 10,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras5_tx",
+                .min_signal = 11,
+                .max_signal = 11,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras6_rx",
+                .min_signal = 12,
+                .max_signal = 12,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras6_tx",
+                .min_signal = 13,
+                .max_signal = 13,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras7_rx",
+                .min_signal = 14,
+                .max_signal = 14,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras7_tx",
+                .min_signal = 15,
+                .max_signal = 15,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        },
+};
-/* spear310 routines */
+/* uart devices plat data */
-void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
+static struct amba_pl011_data spear310_uart_data[] = {
-                u8 pmx_dev_count)
+        {
+                .dma_filter = pl08x_filter_id,
+                .dma_tx_param = "uart1_tx",
+                .dma_rx_param = "uart1_rx",
+        }, {
+                .dma_filter = pl08x_filter_id,
+                .dma_tx_param = "uart2_tx",
+                .dma_rx_param = "uart2_rx",
+        }, {
+                .dma_filter = pl08x_filter_id,
+                .dma_tx_param = "uart3_tx",
+                .dma_rx_param = "uart3_rx",
+        }, {
+                .dma_filter = pl08x_filter_id,
+                .dma_tx_param = "uart4_tx",
+                .dma_rx_param = "uart4_rx",
+        }, {
+                .dma_filter = pl08x_filter_id,
+                .dma_tx_param = "uart5_tx",
+                .dma_rx_param = "uart5_rx",
+        },
+};
+/* Add SPEAr310 auxdata to pass platform data */
+static struct of_dev_auxdata spear310_auxdata_lookup[] __initdata = {
+        OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
+                        &pl022_plat_data),
+        OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
+                        &pl080_plat_data),
+        OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART1_BASE, NULL,
+                        &spear310_uart_data[0]),
+        OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART2_BASE, NULL,
+                        &spear310_uart_data[1]),
+        OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART3_BASE, NULL,
+                        &spear310_uart_data[2]),
+        OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART4_BASE, NULL,
+                        &spear310_uart_data[3]),
+        OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART5_BASE, NULL,
+                        &spear310_uart_data[4]),
+        {}
+};
+static void __init spear310_dt_init(void)
 {
        void __iomem *base;
-        int ret = 0;
+        int ret;
-        /* call spear3xx family common init function */
+        pl080_plat_data.slave_channels = spear310_dma_info;
-        spear3xx_init();
+        pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear310_dma_info);
+        of_platform_populate(NULL, of_default_bus_match_table,
+                        spear310_auxdata_lookup, NULL);
        /* shared irq registration */
        base = ioremap(SPEAR310_SOC_CONFIG_BASE, SZ_4K);
@@ -274,35 +447,46 @@ void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
                shirq_ras1.regs.base = base;
                ret = spear_shirq_register(&shirq_ras1);
                if (ret)
-                        printk(KERN_ERR "Error registering Shared IRQ 1\n");
+                        pr_err("Error registering Shared IRQ 1\n");
                /* shirq 2 */
                shirq_ras2.regs.base = base;
                ret = spear_shirq_register(&shirq_ras2);
                if (ret)
-                        printk(KERN_ERR "Error registering Shared IRQ 2\n");
+                        pr_err("Error registering Shared IRQ 2\n");
                /* shirq 3 */
                shirq_ras3.regs.base = base;
                ret = spear_shirq_register(&shirq_ras3);
                if (ret)
-                        printk(KERN_ERR "Error registering Shared IRQ 3\n");
+                        pr_err("Error registering Shared IRQ 3\n");
                /* shirq 4 */
                shirq_intrcomm_ras.regs.base = base;
                ret = spear_shirq_register(&shirq_intrcomm_ras);
                if (ret)
-                        printk(KERN_ERR "Error registering Shared IRQ 4\n");
+                        pr_err("Error registering Shared IRQ 4\n");
        }
+}
-        /* pmx initialization */
+static const char * const spear310_dt_board_compat[] = {
-        pmx_driver.base = base;
+        "st,spear310",
-        pmx_driver.mode = pmx_mode;
+        "st,spear310-evb",
-        pmx_driver.devs = pmx_devs;
+        NULL,
-        pmx_driver.devs_count = pmx_dev_count;
+};
-        ret = pmx_register(&pmx_driver);
+static void __init spear310_map_io(void)
-        if (ret)
+{
-                printk(KERN_ERR "padmux: registration failed. err no: %d\n",
+        spear3xx_map_io();
-                                ret);
+        spear310_clk_init();
 }
+DT_MACHINE_START(SPEAR310_DT, "ST SPEAr310 SoC with Flattened Device Tree")
+        .map_io         =       spear310_map_io,
+        .init_irq       =       spear3xx_dt_init_irq,
+        .handle_irq     =       vic_handle_irq,
+        .timer          =       &spear3xx_timer,
+        .init_machine   =       spear310_dt_init,
+        .restart        =       spear_restart,
+        .dt_compat      =       spear310_dt_board_compat,
+MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear310_evb.c b/arch/arm/mach-spear3xx/spear310_evb.c
deleted file mode 100644
index f92c4993f65a..000000000000
--- a/arch/arm/mach-spear3xx/spear310_evb.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/spear310_evb.c
- *
- * SPEAr310 evaluation board source file
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <asm/hardware/vic.h>
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-#include <mach/generic.h>
-#include <mach/hardware.h>
-/* padmux devices to enable */
-static struct pmx_dev *pmx_devs[] = {
-        /* spear3xx specific devices */
-        &spear3xx_pmx_i2c,
-        &spear3xx_pmx_ssp,
-        &spear3xx_pmx_gpio_pin0,
-        &spear3xx_pmx_gpio_pin1,
-        &spear3xx_pmx_gpio_pin2,
-        &spear3xx_pmx_gpio_pin3,
-        &spear3xx_pmx_gpio_pin4,
-        &spear3xx_pmx_gpio_pin5,
-        &spear3xx_pmx_uart0,
-        /* spear310 specific devices */
-        &spear310_pmx_emi_cs_0_1_4_5,
-        &spear310_pmx_emi_cs_2_3,
-        &spear310_pmx_uart1,
-        &spear310_pmx_uart2,
-        &spear310_pmx_uart3_4_5,
-        &spear310_pmx_fsmc,
-        &spear310_pmx_rs485_0_1,
-        &spear310_pmx_tdm0,
-};
-static struct amba_device *amba_devs[] __initdata = {
-        /* spear3xx specific devices */
-        &spear3xx_gpio_device,
-        &spear3xx_uart_device,
-        /* spear310 specific devices */
-};
-static struct platform_device *plat_devs[] __initdata = {
-        /* spear3xx specific devices */
-        /* spear310 specific devices */
-};
-static void __init spear310_evb_init(void)
-{
-        unsigned int i;
-        /* call spear310 machine init function */
-        spear310_init(NULL, pmx_devs, ARRAY_SIZE(pmx_devs));
-        /* Add Platform Devices */
-        platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
-        /* Add Amba Devices */
-        for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
-                amba_device_register(amba_devs[i], &iomem_resource);
-}
-MACHINE_START(SPEAR310, "ST-SPEAR310-EVB")
-        .atag_offset    =       0x100,
-        .map_io         =       spear3xx_map_io,
-        .init_irq       =       spear3xx_init_irq,
-        .handle_irq     =       vic_handle_irq,
-        .timer          =       &spear3xx_timer,
-        .init_machine   =       spear310_evb_init,
-        .restart        =       spear_restart,
-MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index deaaf199612c..e8caeef50a5c 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -3,386 +3,85 @@
 *
 * SPEAr320 machine source file
 *
- * Copyright (C) 2009 ST Microelectronics
+ * Copyright (C) 2009-2012 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
+ * Viresh Kumar <viresh.kumar@st.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */
-#include <linux/ptrace.h>
+#define pr_fmt(fmt) "SPEAr320: " fmt
-#include <asm/irq.h>
+#include <linux/amba/pl022.h>
+#include <linux/amba/pl08x.h>
+#include <linux/amba/serial.h>
+#include <linux/of_platform.h>
+#include <asm/hardware/vic.h>
+#include <asm/mach/arch.h>
 #include <plat/shirq.h>
 #include <mach/generic.h>
-#include <mach/hardware.h>
+#include <mach/spear.h>
-/* pad multiplexing support */
+#define SPEAR320_UART1_BASE             UL(0xA3000000)
-/* muxing registers */
+#define SPEAR320_UART2_BASE             UL(0xA4000000)
-#define PAD_MUX_CONFIG_REG      0x0C
+#define SPEAR320_SSP0_BASE              UL(0xA5000000)
-#define MODE_CONFIG_REG         0x10
+#define SPEAR320_SSP1_BASE              UL(0xA6000000)
+#define SPEAR320_SOC_CONFIG_BASE        UL(0xB3000000)
-/* modes */
-#define AUTO_NET_SMII_MODE      (1 << 0)
+/* Interrupt registers offsets and masks */
-#define AUTO_NET_MII_MODE       (1 << 1)
+#define SPEAR320_INT_STS_MASK_REG               0x04
-#define AUTO_EXP_MODE           (1 << 2)
+#define SPEAR320_INT_CLR_MASK_REG               0x04
-#define SMALL_PRINTERS_MODE     (1 << 3)
+#define SPEAR320_INT_ENB_MASK_REG               0x08
-#define ALL_MODES               0xF
+#define SPEAR320_GPIO_IRQ_MASK                  (1 << 0)
+#define SPEAR320_I2S_PLAY_IRQ_MASK              (1 << 1)
-struct pmx_mode spear320_auto_net_smii_mode = {
+#define SPEAR320_I2S_REC_IRQ_MASK               (1 << 2)
-        .id = AUTO_NET_SMII_MODE,
+#define SPEAR320_EMI_IRQ_MASK                   (1 << 7)
-        .name = "Automation Networking SMII Mode",
+#define SPEAR320_CLCD_IRQ_MASK                  (1 << 8)
-        .mask = 0x00,
+#define SPEAR320_SPP_IRQ_MASK                   (1 << 9)
-};
+#define SPEAR320_SDHCI_IRQ_MASK                 (1 << 10)
+#define SPEAR320_CAN_U_IRQ_MASK                 (1 << 11)
-struct pmx_mode spear320_auto_net_mii_mode = {
+#define SPEAR320_CAN_L_IRQ_MASK                 (1 << 12)
-        .id = AUTO_NET_MII_MODE,
+#define SPEAR320_UART1_IRQ_MASK                 (1 << 13)
-        .name = "Automation Networking MII Mode",
+#define SPEAR320_UART2_IRQ_MASK                 (1 << 14)
-        .mask = 0x01,
+#define SPEAR320_SSP1_IRQ_MASK                  (1 << 15)
-};
+#define SPEAR320_SSP2_IRQ_MASK                  (1 << 16)
+#define SPEAR320_SMII0_IRQ_MASK                 (1 << 17)
-struct pmx_mode spear320_auto_exp_mode = {
+#define SPEAR320_MII1_SMII1_IRQ_MASK            (1 << 18)
-        .id = AUTO_EXP_MODE,
+#define SPEAR320_WAKEUP_SMII0_IRQ_MASK          (1 << 19)
-        .name = "Automation Expanded Mode",
+#define SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK     (1 << 20)
-        .mask = 0x02,
+#define SPEAR320_I2C1_IRQ_MASK                  (1 << 21)
-};
+#define SPEAR320_SHIRQ_RAS1_MASK                0x000380
-struct pmx_mode spear320_small_printers_mode = {
+#define SPEAR320_SHIRQ_RAS3_MASK                0x000007
-        .id = SMALL_PRINTERS_MODE,
+#define SPEAR320_SHIRQ_INTRCOMM_RAS_MASK        0x3FF800
-        .name = "Small Printers Mode",
-        .mask = 0x03,
+/* SPEAr320 Virtual irq definitions */
-};
+/* IRQs sharing IRQ_GEN_RAS_1 */
+#define SPEAR320_VIRQ_EMI                       (SPEAR3XX_VIRQ_START + 0)
-/* devices */
+#define SPEAR320_VIRQ_CLCD                      (SPEAR3XX_VIRQ_START + 1)
-static struct pmx_dev_mode pmx_clcd_modes[] = {
+#define SPEAR320_VIRQ_SPP                       (SPEAR3XX_VIRQ_START + 2)
-        {
-                .ids = AUTO_NET_SMII_MODE,
+/* IRQs sharing IRQ_GEN_RAS_2 */
-                .mask = 0x0,
+#define SPEAR320_IRQ_SDHCI                      SPEAR3XX_IRQ_GEN_RAS_2
-        },
-};
+/* IRQs sharing IRQ_GEN_RAS_3 */
+#define SPEAR320_VIRQ_PLGPIO                    (SPEAR3XX_VIRQ_START + 3)
-struct pmx_dev spear320_pmx_clcd = {
+#define SPEAR320_VIRQ_I2S_PLAY                  (SPEAR3XX_VIRQ_START + 4)
-        .name = "clcd",
+#define SPEAR320_VIRQ_I2S_REC                   (SPEAR3XX_VIRQ_START + 5)
-        .modes = pmx_clcd_modes,
-        .mode_count = ARRAY_SIZE(pmx_clcd_modes),
+/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
-        .enb_on_reset = 1,
+#define SPEAR320_VIRQ_CANU                      (SPEAR3XX_VIRQ_START + 6)
-};
+#define SPEAR320_VIRQ_CANL                      (SPEAR3XX_VIRQ_START + 7)
+#define SPEAR320_VIRQ_UART1                     (SPEAR3XX_VIRQ_START + 8)
-static struct pmx_dev_mode pmx_emi_modes[] = {
+#define SPEAR320_VIRQ_UART2                     (SPEAR3XX_VIRQ_START + 9)
-        {
+#define SPEAR320_VIRQ_SSP1                      (SPEAR3XX_VIRQ_START + 10)
-                .ids = AUTO_EXP_MODE,
+#define SPEAR320_VIRQ_SSP2                      (SPEAR3XX_VIRQ_START + 11)
-                .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
+#define SPEAR320_VIRQ_SMII0                     (SPEAR3XX_VIRQ_START + 12)
-        },
+#define SPEAR320_VIRQ_MII1_SMII1                (SPEAR3XX_VIRQ_START + 13)
-};
+#define SPEAR320_VIRQ_WAKEUP_SMII0              (SPEAR3XX_VIRQ_START + 14)
+#define SPEAR320_VIRQ_WAKEUP_MII1_SMII1         (SPEAR3XX_VIRQ_START + 15)
-struct pmx_dev spear320_pmx_emi = {
+#define SPEAR320_VIRQ_I2C1                      (SPEAR3XX_VIRQ_START + 16)
-        .name = "emi",
-        .modes = pmx_emi_modes,
-        .mode_count = ARRAY_SIZE(pmx_emi_modes),
-        .enb_on_reset = 1,
-};
-static struct pmx_dev_mode pmx_fsmc_modes[] = {
-        {
-                .ids = ALL_MODES,
-                .mask = 0x0,
-        },
-};
-struct pmx_dev spear320_pmx_fsmc = {
-        .name = "fsmc",
-        .modes = pmx_fsmc_modes,
-        .mode_count = ARRAY_SIZE(pmx_fsmc_modes),
-        .enb_on_reset = 1,
-};
-static struct pmx_dev_mode pmx_spp_modes[] = {
-        {
-                .ids = SMALL_PRINTERS_MODE,
-                .mask = 0x0,
-        },
-};
-struct pmx_dev spear320_pmx_spp = {
-        .name = "spp",
-        .modes = pmx_spp_modes,
-        .mode_count = ARRAY_SIZE(pmx_spp_modes),
-        .enb_on_reset = 1,
-};
-static struct pmx_dev_mode pmx_sdhci_modes[] = {
-        {
-                .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE |
-                        SMALL_PRINTERS_MODE,
-                .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
-        },
-};
-struct pmx_dev spear320_pmx_sdhci = {
-        .name = "sdhci",
-        .modes = pmx_sdhci_modes,
-        .mode_count = ARRAY_SIZE(pmx_sdhci_modes),
-        .enb_on_reset = 1,
-};
-static struct pmx_dev_mode pmx_i2s_modes[] = {
-        {
-                .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
-                .mask = PMX_UART0_MODEM_MASK,
-        },
-};
-struct pmx_dev spear320_pmx_i2s = {
-        .name = "i2s",
-        .modes = pmx_i2s_modes,
-        .mode_count = ARRAY_SIZE(pmx_i2s_modes),
-        .enb_on_reset = 1,
-};
-static struct pmx_dev_mode pmx_uart1_modes[] = {
-        {
-                .ids = ALL_MODES,
-                .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK,
-        },
-};
-struct pmx_dev spear320_pmx_uart1 = {
-        .name = "uart1",
-        .modes = pmx_uart1_modes,
-        .mode_count = ARRAY_SIZE(pmx_uart1_modes),
-        .enb_on_reset = 1,
-};
-static struct pmx_dev_mode pmx_uart1_modem_modes[] = {
-        {
-                .ids = AUTO_EXP_MODE,
-                .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK |
-                        PMX_SSP_CS_MASK,
-        }, {
-                .ids = SMALL_PRINTERS_MODE,
-                .mask = PMX_GPIO_PIN3_MASK | PMX_GPIO_PIN4_MASK |
-                        PMX_GPIO_PIN5_MASK | PMX_SSP_CS_MASK,
-        },
-};
-struct pmx_dev spear320_pmx_uart1_modem = {
-        .name = "uart1_modem",
-        .modes = pmx_uart1_modem_modes,
-        .mode_count = ARRAY_SIZE(pmx_uart1_modem_modes),
-        .enb_on_reset = 1,
-};
-static struct pmx_dev_mode pmx_uart2_modes[] = {
-        {
-                .ids = ALL_MODES,
-                .mask = PMX_FIRDA_MASK,
-        },
-};
-struct pmx_dev spear320_pmx_uart2 = {
-        .name = "uart2",
-        .modes = pmx_uart2_modes,
-        .mode_count = ARRAY_SIZE(pmx_uart2_modes),
-        .enb_on_reset = 1,
-};
-static struct pmx_dev_mode pmx_touchscreen_modes[] = {
-        {
-                .ids = AUTO_NET_SMII_MODE,
-                .mask = PMX_SSP_CS_MASK,
-        },
-};
-struct pmx_dev spear320_pmx_touchscreen = {
-        .name = "touchscreen",
-        .modes = pmx_touchscreen_modes,
-        .mode_count = ARRAY_SIZE(pmx_touchscreen_modes),
-        .enb_on_reset = 1,
-};
-static struct pmx_dev_mode pmx_can_modes[] = {
-        {
-                .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE,
-                .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
-                        PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
-        },
-};
-struct pmx_dev spear320_pmx_can = {
-        .name = "can",
-        .modes = pmx_can_modes,
-        .mode_count = ARRAY_SIZE(pmx_can_modes),
-        .enb_on_reset = 1,
-};
-static struct pmx_dev_mode pmx_sdhci_led_modes[] = {
-        {
-                .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
-                .mask = PMX_SSP_CS_MASK,
-        },
-};
-struct pmx_dev spear320_pmx_sdhci_led = {
-        .name = "sdhci_led",
-        .modes = pmx_sdhci_led_modes,
-        .mode_count = ARRAY_SIZE(pmx_sdhci_led_modes),
-        .enb_on_reset = 1,
-};
-static struct pmx_dev_mode pmx_pwm0_modes[] = {
-        {
-                .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
-                .mask = PMX_UART0_MODEM_MASK,
-        }, {
-                .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
-                .mask = PMX_MII_MASK,
-        },
-};
-struct pmx_dev spear320_pmx_pwm0 = {
-        .name = "pwm0",
-        .modes = pmx_pwm0_modes,
-        .mode_count = ARRAY_SIZE(pmx_pwm0_modes),
-        .enb_on_reset = 1,
-};
-static struct pmx_dev_mode pmx_pwm1_modes[] = {
-        {
-                .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
-                .mask = PMX_UART0_MODEM_MASK,
-        }, {
-                .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
-                .mask = PMX_MII_MASK,
-        },
-};
-struct pmx_dev spear320_pmx_pwm1 = {
-        .name = "pwm1",
-        .modes = pmx_pwm1_modes,
-        .mode_count = ARRAY_SIZE(pmx_pwm1_modes),
-        .enb_on_reset = 1,
-};
-static struct pmx_dev_mode pmx_pwm2_modes[] = {
-        {
-                .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
-                .mask = PMX_SSP_CS_MASK,
-        }, {
-                .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
-                .mask = PMX_MII_MASK,
-        },
-};
-struct pmx_dev spear320_pmx_pwm2 = {
-        .name = "pwm2",
-        .modes = pmx_pwm2_modes,
-        .mode_count = ARRAY_SIZE(pmx_pwm2_modes),
-        .enb_on_reset = 1,
-};
-static struct pmx_dev_mode pmx_pwm3_modes[] = {
-        {
-                .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
-                .mask = PMX_MII_MASK,
-        },
-};
-struct pmx_dev spear320_pmx_pwm3 = {
-        .name = "pwm3",
-        .modes = pmx_pwm3_modes,
-        .mode_count = ARRAY_SIZE(pmx_pwm3_modes),
-        .enb_on_reset = 1,
-};
-static struct pmx_dev_mode pmx_ssp1_modes[] = {
-        {
-                .ids = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
-                .mask = PMX_MII_MASK,
-        },
-};
-struct pmx_dev spear320_pmx_ssp1 = {
-        .name = "ssp1",
-        .modes = pmx_ssp1_modes,
-        .mode_count = ARRAY_SIZE(pmx_ssp1_modes),
-        .enb_on_reset = 1,
-};
-static struct pmx_dev_mode pmx_ssp2_modes[] = {
-        {
-                .ids = AUTO_NET_SMII_MODE,
-                .mask = PMX_MII_MASK,
-        },
-};
-struct pmx_dev spear320_pmx_ssp2 = {
-        .name = "ssp2",
-        .modes = pmx_ssp2_modes,
-        .mode_count = ARRAY_SIZE(pmx_ssp2_modes),
-        .enb_on_reset = 1,
-};
-static struct pmx_dev_mode pmx_mii1_modes[] = {
-        {
-                .ids = AUTO_NET_MII_MODE,
-                .mask = 0x0,
-        },
-};
-struct pmx_dev spear320_pmx_mii1 = {
-        .name = "mii1",
-        .modes = pmx_mii1_modes,
-        .mode_count = ARRAY_SIZE(pmx_mii1_modes),
-        .enb_on_reset = 1,
-};
-static struct pmx_dev_mode pmx_smii0_modes[] = {
-        {
-                .ids = AUTO_NET_SMII_MODE | AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
-                .mask = PMX_MII_MASK,
-        },
-};
-struct pmx_dev spear320_pmx_smii0 = {
-        .name = "smii0",
-        .modes = pmx_smii0_modes,
-        .mode_count = ARRAY_SIZE(pmx_smii0_modes),
-        .enb_on_reset = 1,
-};
-static struct pmx_dev_mode pmx_smii1_modes[] = {
-        {
-                .ids = AUTO_NET_SMII_MODE | SMALL_PRINTERS_MODE,
-                .mask = PMX_MII_MASK,
-        },
-};
-struct pmx_dev spear320_pmx_smii1 = {
-        .name = "smii1",
-        .modes = pmx_smii1_modes,
-        .mode_count = ARRAY_SIZE(pmx_smii1_modes),
-        .enb_on_reset = 1,
-};
-static struct pmx_dev_mode pmx_i2c1_modes[] = {
-        {
-                .ids = AUTO_EXP_MODE,
-                .mask = 0x0,
-        },
-};
-struct pmx_dev spear320_pmx_i2c1 = {
-        .name = "i2c1",
-        .modes = pmx_i2c1_modes,
-        .mode_count = ARRAY_SIZE(pmx_i2c1_modes),
-        .enb_on_reset = 1,
-};
-/* pmx driver structure */
-static struct pmx_driver pmx_driver = {
-        .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x00000007},
-        .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
-};
 /* spear3xx shared irq */
 static struct shirq_dev_config shirq_ras1_config[] = {
@@ -508,17 +207,250 @@ static struct spear_shirq shirq_intrcomm_ras = {
        },
 };
-/* Add spear320 specific devices here */
+/* DMAC platform data's slave info */
+struct pl08x_channel_data spear320_dma_info[] = {
+        {
+                .bus_id = "uart0_rx",
+                .min_signal = 2,
+                .max_signal = 2,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart0_tx",
+                .min_signal = 3,
+                .max_signal = 3,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ssp0_rx",
+                .min_signal = 8,
+                .max_signal = 8,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ssp0_tx",
+                .min_signal = 9,
+                .max_signal = 9,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "i2c0_rx",
+                .min_signal = 10,
+                .max_signal = 10,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "i2c0_tx",
+                .min_signal = 11,
+                .max_signal = 11,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "irda",
+                .min_signal = 12,
+                .max_signal = 12,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "adc",
+                .min_signal = 13,
+                .max_signal = 13,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "to_jpeg",
+                .min_signal = 14,
+                .max_signal = 14,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "from_jpeg",
+                .min_signal = 15,
+                .max_signal = 15,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ssp1_rx",
+                .min_signal = 0,
+                .max_signal = 0,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ssp1_tx",
+                .min_signal = 1,
+                .max_signal = 1,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ssp2_rx",
+                .min_signal = 2,
+                .max_signal = 2,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ssp2_tx",
+                .min_signal = 3,
+                .max_signal = 3,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "uart1_rx",
+                .min_signal = 4,
+                .max_signal = 4,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "uart1_tx",
+                .min_signal = 5,
+                .max_signal = 5,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "uart2_rx",
+                .min_signal = 6,
+                .max_signal = 6,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "uart2_tx",
+                .min_signal = 7,
+                .max_signal = 7,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "i2c1_rx",
+                .min_signal = 8,
+                .max_signal = 8,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "i2c1_tx",
+                .min_signal = 9,
+                .max_signal = 9,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "i2c2_rx",
+                .min_signal = 10,
+                .max_signal = 10,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "i2c2_tx",
+                .min_signal = 11,
+                .max_signal = 11,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "i2s_rx",
+                .min_signal = 12,
+                .max_signal = 12,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "i2s_tx",
+                .min_signal = 13,
+                .max_signal = 13,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "rs485_rx",
+                .min_signal = 14,
+                .max_signal = 14,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "rs485_tx",
+                .min_signal = 15,
+                .max_signal = 15,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        },
+};
+static struct pl022_ssp_controller spear320_ssp_data[] = {
+        {
+                .bus_id = 1,
+                .enable_dma = 1,
+                .dma_filter = pl08x_filter_id,
+                .dma_tx_param = "ssp1_tx",
+                .dma_rx_param = "ssp1_rx",
+                .num_chipselect = 2,
+        }, {
+                .bus_id = 2,
+                .enable_dma = 1,
+                .dma_filter = pl08x_filter_id,
+                .dma_tx_param = "ssp2_tx",
+                .dma_rx_param = "ssp2_rx",
+                .num_chipselect = 2,
+        }
+};
+static struct amba_pl011_data spear320_uart_data[] = {
+        {
+                .dma_filter = pl08x_filter_id,
+                .dma_tx_param = "uart1_tx",
+                .dma_rx_param = "uart1_rx",
+        }, {
+                .dma_filter = pl08x_filter_id,
+                .dma_tx_param = "uart2_tx",
+                .dma_rx_param = "uart2_rx",
+        },
+};
-/* spear320 routines */
+/* Add SPEAr310 auxdata to pass platform data */
-void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
+static struct of_dev_auxdata spear320_auxdata_lookup[] __initdata = {
-                u8 pmx_dev_count)
+        OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
+                        &pl022_plat_data),
+        OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
+                        &pl080_plat_data),
+        OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP0_BASE, NULL,
+                        &spear320_ssp_data[0]),
+        OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP1_BASE, NULL,
+                        &spear320_ssp_data[1]),
+        OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART1_BASE, NULL,
+                        &spear320_uart_data[0]),
+        OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART2_BASE, NULL,
+                        &spear320_uart_data[1]),
+        {}
+};
+static void __init spear320_dt_init(void)
 {
        void __iomem *base;
-        int ret = 0;
+        int ret;
+        pl080_plat_data.slave_channels = spear320_dma_info;
+        pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear320_dma_info);
-        /* call spear3xx family common init function */
+        of_platform_populate(NULL, of_default_bus_match_table,
-        spear3xx_init();
+                        spear320_auxdata_lookup, NULL);
        /* shared irq registration */
        base = ioremap(SPEAR320_SOC_CONFIG_BASE, SZ_4K);
@@ -527,29 +459,40 @@ void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
                shirq_ras1.regs.base = base;
                ret = spear_shirq_register(&shirq_ras1);
                if (ret)
-                        printk(KERN_ERR "Error registering Shared IRQ 1\n");
+                        pr_err("Error registering Shared IRQ 1\n");
                /* shirq 3 */
                shirq_ras3.regs.base = base;
                ret = spear_shirq_register(&shirq_ras3);
                if (ret)
-                        printk(KERN_ERR "Error registering Shared IRQ 3\n");
+                        pr_err("Error registering Shared IRQ 3\n");
                /* shirq 4 */
                shirq_intrcomm_ras.regs.base = base;
                ret = spear_shirq_register(&shirq_intrcomm_ras);
                if (ret)
-                        printk(KERN_ERR "Error registering Shared IRQ 4\n");
+                        pr_err("Error registering Shared IRQ 4\n");
        }
+}
-        /* pmx initialization */
+static const char * const spear320_dt_board_compat[] = {
-        pmx_driver.base = base;
+        "st,spear320",
-        pmx_driver.mode = pmx_mode;
+        "st,spear320-evb",
-        pmx_driver.devs = pmx_devs;
+        NULL,
-        pmx_driver.devs_count = pmx_dev_count;
+};
-        ret = pmx_register(&pmx_driver);
+static void __init spear320_map_io(void)
-        if (ret)
+{
-                printk(KERN_ERR "padmux: registration failed. err no: %d\n",
+        spear3xx_map_io();
-                                ret);
+        spear320_clk_init();
 }
+DT_MACHINE_START(SPEAR320_DT, "ST SPEAr320 SoC with Flattened Device Tree")
+        .map_io         =       spear320_map_io,
+        .init_irq       =       spear3xx_dt_init_irq,
+        .handle_irq     =       vic_handle_irq,
+        .timer          =       &spear3xx_timer,
+        .init_machine   =       spear320_dt_init,
+        .restart        =       spear_restart,
+        .dt_compat      =       spear320_dt_board_compat,
+MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear320_evb.c b/arch/arm/mach-spear3xx/spear320_evb.c
deleted file mode 100644
index 105334ab7021..000000000000
--- a/arch/arm/mach-spear3xx/spear320_evb.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/spear320_evb.c
- *
- * SPEAr320 evaluation board source file
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <asm/hardware/vic.h>
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-#include <mach/generic.h>
-#include <mach/hardware.h>
-/* padmux devices to enable */
-static struct pmx_dev *pmx_devs[] = {
-        /* spear3xx specific devices */
-        &spear3xx_pmx_i2c,
-        &spear3xx_pmx_ssp,
-        &spear3xx_pmx_mii,
-        &spear3xx_pmx_uart0,
-        /* spear320 specific devices */
-        &spear320_pmx_fsmc,
-        &spear320_pmx_sdhci,
-        &spear320_pmx_i2s,
-        &spear320_pmx_uart1,
-        &spear320_pmx_uart2,
-        &spear320_pmx_can,
-        &spear320_pmx_pwm0,
-        &spear320_pmx_pwm1,
-        &spear320_pmx_pwm2,
-        &spear320_pmx_mii1,
-};
-static struct amba_device *amba_devs[] __initdata = {
-        /* spear3xx specific devices */
-        &spear3xx_gpio_device,
-        &spear3xx_uart_device,
-        /* spear320 specific devices */
-};
-static struct platform_device *plat_devs[] __initdata = {
-        /* spear3xx specific devices */
-        /* spear320 specific devices */
-};
-static void __init spear320_evb_init(void)
-{
-        unsigned int i;
-        /* call spear320 machine init function */
-        spear320_init(&spear320_auto_net_mii_mode, pmx_devs,
-                        ARRAY_SIZE(pmx_devs));
-        /* Add Platform Devices */
-        platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
-        /* Add Amba Devices */
-        for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
-                amba_device_register(amba_devs[i], &iomem_resource);
-}
-MACHINE_START(SPEAR320, "ST-SPEAR320-EVB")
-        .atag_offset    =       0x100,
-        .map_io         =       spear3xx_map_io,
-        .init_irq       =       spear3xx_init_irq,
-        .handle_irq     =       vic_handle_irq,
-        .timer          =       &spear3xx_timer,
-        .init_machine   =       spear320_evb_init,
-        .restart        =       spear_restart,
-MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index b1733c37f209..826ac20ef1e7 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -3,71 +3,78 @@
 *
 * SPEAr3XX machines common source file
 *
- * Copyright (C) 2009 ST Microelectronics
+ * Copyright (C) 2009-2012 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
+ * Viresh Kumar <viresh.kumar@st.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */
-#include <linux/types.h>
+#define pr_fmt(fmt) "SPEAr3xx: " fmt
-#include <linux/amba/pl061.h>
-#include <linux/ptrace.h>
+#include <linux/amba/pl022.h>
+#include <linux/amba/pl08x.h>
+#include <linux/of_irq.h>
 #include <linux/io.h>
+#include <asm/hardware/pl080.h>
 #include <asm/hardware/vic.h>
-#include <asm/irq.h>
+#include <plat/pl080.h>
-#include <asm/mach/arch.h>
 #include <mach/generic.h>
-#include <mach/hardware.h>
+#include <mach/spear.h>
-/* Add spear3xx machines common devices here */
+/* ssp device registration */
-/* gpio device registration */
+struct pl022_ssp_controller pl022_plat_data = {
-static struct pl061_platform_data gpio_plat_data = {
+        .bus_id = 0,
-        .gpio_base      = 0,
+        .enable_dma = 1,
-        .irq_base       = SPEAR3XX_GPIO_INT_BASE,
+        .dma_filter = pl08x_filter_id,
+        .dma_tx_param = "ssp0_tx",
+        .dma_rx_param = "ssp0_rx",
+        /*
+         * This is number of spi devices that can be connected to spi. There are
+         * two type of chipselects on which slave devices can work. One is chip
+         * select provided by spi masters other is controlled through external
+         * gpio's. We can't use chipselect provided from spi master (because as
+         * soon as FIFO becomes empty, CS is disabled and transfer ends). So
+         * this number now depends on number of gpios available for spi. each
+         * slave on each master requires a separate gpio pin.
+         */
+        .num_chipselect = 2,
+};
+/* dmac device registration */
+struct pl08x_platform_data pl080_plat_data = {
+        .memcpy_channel = {
+                .bus_id = "memcpy",
+                .cctl = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \
+                        PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \
+                        PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \
+                        PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \
+                        PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | \
+                        PL080_CONTROL_PROT_SYS),
+        },
+        .lli_buses = PL08X_AHB1,
+        .mem_buses = PL08X_AHB1,
+        .get_signal = pl080_get_signal,
+        .put_signal = pl080_put_signal,
 };
-AMBA_APB_DEVICE(spear3xx_gpio, "gpio", 0, SPEAR3XX_ICM3_GPIO_BASE,
+/*
-        {SPEAR3XX_IRQ_BASIC_GPIO}, &gpio_plat_data);
+ * Following will create 16MB static virtual/physical mappings
+ * PHYSICAL             VIRTUAL
-/* uart device registration */
+ * 0xD0000000           0xFD000000
-AMBA_APB_DEVICE(spear3xx_uart, "uart", 0, SPEAR3XX_ICM1_UART_BASE,
+ * 0xFC000000           0xFC000000
-        {SPEAR3XX_IRQ_UART}, NULL);
+ */
-/* Do spear3xx familiy common initialization part here */
-void __init spear3xx_init(void)
-{
-        /* nothing to do for now */
-}
-/* This will initialize vic */
-void __init spear3xx_init_irq(void)
-{
-        vic_init((void __iomem *)VA_SPEAR3XX_ML1_VIC_BASE, 0, ~0, 0);
-}
-/* Following will create static virtual/physical mappings */
 struct map_desc spear3xx_io_desc[] __initdata = {
        {
-                .virtual        = VA_SPEAR3XX_ICM1_UART_BASE,
+                .virtual        = VA_SPEAR3XX_ICM1_2_BASE,
-                .pfn            = __phys_to_pfn(SPEAR3XX_ICM1_UART_BASE),
+                .pfn            = __phys_to_pfn(SPEAR3XX_ICM1_2_BASE),
-                .length         = SZ_4K,
+                .length         = SZ_16M,
-                .type           = MT_DEVICE
-        }, {
-                .virtual        = VA_SPEAR3XX_ML1_VIC_BASE,
-                .pfn            = __phys_to_pfn(SPEAR3XX_ML1_VIC_BASE),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE
-        }, {
-                .virtual        = VA_SPEAR3XX_ICM3_SYS_CTRL_BASE,
-                .pfn            = __phys_to_pfn(SPEAR3XX_ICM3_SYS_CTRL_BASE),
-                .length         = SZ_4K,
                .type           = MT_DEVICE
        }, {
-                .virtual        = VA_SPEAR3XX_ICM3_MISC_REG_BASE,
+                .virtual        = VA_SPEAR3XX_ICM3_SMI_CTRL_BASE,
-                .pfn            = __phys_to_pfn(SPEAR3XX_ICM3_MISC_REG_BASE),
+                .pfn            = __phys_to_pfn(SPEAR3XX_ICM3_SMI_CTRL_BASE),
-                .length         = SZ_4K,
+                .length         = SZ_16M,
                .type           = MT_DEVICE
        },
 };
@@ -76,436 +83,8 @@ struct map_desc spear3xx_io_desc[] __initdata = {
 void __init spear3xx_map_io(void)
 {
        iotable_init(spear3xx_io_desc, ARRAY_SIZE(spear3xx_io_desc));
-        /* This will initialize clock framework */
-        spear3xx_clk_init();
 }
-/* pad multiplexing support */
-/* devices */
-static struct pmx_dev_mode pmx_firda_modes[] = {
-        {
-                .ids = 0xffffffff,
-                .mask = PMX_FIRDA_MASK,
-        },
-};
-struct pmx_dev spear3xx_pmx_firda = {
-        .name = "firda",
-        .modes = pmx_firda_modes,
-        .mode_count = ARRAY_SIZE(pmx_firda_modes),
-        .enb_on_reset = 0,
-};
-static struct pmx_dev_mode pmx_i2c_modes[] = {
-        {
-                .ids = 0xffffffff,
-                .mask = PMX_I2C_MASK,
-        },
-};
-struct pmx_dev spear3xx_pmx_i2c = {
-        .name = "i2c",
-        .modes = pmx_i2c_modes,
-        .mode_count = ARRAY_SIZE(pmx_i2c_modes),
-        .enb_on_reset = 0,
-};
-static struct pmx_dev_mode pmx_ssp_cs_modes[] = {
-        {
-                .ids = 0xffffffff,
-                .mask = PMX_SSP_CS_MASK,
-        },
-};
-struct pmx_dev spear3xx_pmx_ssp_cs = {
-        .name = "ssp_chip_selects",
-        .modes = pmx_ssp_cs_modes,
-        .mode_count = ARRAY_SIZE(pmx_ssp_cs_modes),
-        .enb_on_reset = 0,
-};
-static struct pmx_dev_mode pmx_ssp_modes[] = {
-        {
-                .ids = 0xffffffff,
-                .mask = PMX_SSP_MASK,
-        },
-};
-struct pmx_dev spear3xx_pmx_ssp = {
-        .name = "ssp",
-        .modes = pmx_ssp_modes,
-        .mode_count = ARRAY_SIZE(pmx_ssp_modes),
-        .enb_on_reset = 0,
-};
-static struct pmx_dev_mode pmx_mii_modes[] = {
-        {
-                .ids = 0xffffffff,
-                .mask = PMX_MII_MASK,
-        },
-};
-struct pmx_dev spear3xx_pmx_mii = {
-        .name = "mii",
-        .modes = pmx_mii_modes,
-        .mode_count = ARRAY_SIZE(pmx_mii_modes),
-        .enb_on_reset = 0,
-};
-static struct pmx_dev_mode pmx_gpio_pin0_modes[] = {
-        {
-                .ids = 0xffffffff,
-                .mask = PMX_GPIO_PIN0_MASK,
-        },
-};
-struct pmx_dev spear3xx_pmx_gpio_pin0 = {
-        .name = "gpio_pin0",
-        .modes = pmx_gpio_pin0_modes,
-        .mode_count = ARRAY_SIZE(pmx_gpio_pin0_modes),
-        .enb_on_reset = 0,
-};
-static struct pmx_dev_mode pmx_gpio_pin1_modes[] = {
-        {
-                .ids = 0xffffffff,
-                .mask = PMX_GPIO_PIN1_MASK,
-        },
-};
-struct pmx_dev spear3xx_pmx_gpio_pin1 = {
-        .name = "gpio_pin1",
-        .modes = pmx_gpio_pin1_modes,
-        .mode_count = ARRAY_SIZE(pmx_gpio_pin1_modes),
-        .enb_on_reset = 0,
-};
-static struct pmx_dev_mode pmx_gpio_pin2_modes[] = {
-        {
-                .ids = 0xffffffff,
-                .mask = PMX_GPIO_PIN2_MASK,
-        },
-};
-struct pmx_dev spear3xx_pmx_gpio_pin2 = {
-        .name = "gpio_pin2",
-        .modes = pmx_gpio_pin2_modes,
-        .mode_count = ARRAY_SIZE(pmx_gpio_pin2_modes),
-        .enb_on_reset = 0,
-};
-static struct pmx_dev_mode pmx_gpio_pin3_modes[] = {
-        {
-                .ids = 0xffffffff,
-                .mask = PMX_GPIO_PIN3_MASK,
-        },
-};
-struct pmx_dev spear3xx_pmx_gpio_pin3 = {
-        .name = "gpio_pin3",
-        .modes = pmx_gpio_pin3_modes,
-        .mode_count = ARRAY_SIZE(pmx_gpio_pin3_modes),
-        .enb_on_reset = 0,
-};
-static struct pmx_dev_mode pmx_gpio_pin4_modes[] = {
-        {
-                .ids = 0xffffffff,
-                .mask = PMX_GPIO_PIN4_MASK,
-        },
-};
-struct pmx_dev spear3xx_pmx_gpio_pin4 = {
-        .name = "gpio_pin4",
-        .modes = pmx_gpio_pin4_modes,
-        .mode_count = ARRAY_SIZE(pmx_gpio_pin4_modes),
-        .enb_on_reset = 0,
-};
-static struct pmx_dev_mode pmx_gpio_pin5_modes[] = {
-        {
-                .ids = 0xffffffff,
-                .mask = PMX_GPIO_PIN5_MASK,
-        },
-};
-struct pmx_dev spear3xx_pmx_gpio_pin5 = {
-        .name = "gpio_pin5",
-        .modes = pmx_gpio_pin5_modes,
-        .mode_count = ARRAY_SIZE(pmx_gpio_pin5_modes),
-        .enb_on_reset = 0,
-};
-static struct pmx_dev_mode pmx_uart0_modem_modes[] = {
-        {
-                .ids = 0xffffffff,
-                .mask = PMX_UART0_MODEM_MASK,
-        },
-};
-struct pmx_dev spear3xx_pmx_uart0_modem = {
-        .name = "uart0_modem",
-        .modes = pmx_uart0_modem_modes,
-        .mode_count = ARRAY_SIZE(pmx_uart0_modem_modes),
-        .enb_on_reset = 0,
-};
-static struct pmx_dev_mode pmx_uart0_modes[] = {
-        {
-                .ids = 0xffffffff,
-                .mask = PMX_UART0_MASK,
-        },
-};
-struct pmx_dev spear3xx_pmx_uart0 = {
-        .name = "uart0",
-        .modes = pmx_uart0_modes,
-        .mode_count = ARRAY_SIZE(pmx_uart0_modes),
-        .enb_on_reset = 0,
-};
-static struct pmx_dev_mode pmx_timer_3_4_modes[] = {
-        {
-                .ids = 0xffffffff,
-                .mask = PMX_TIMER_3_4_MASK,
-        },
-};
-struct pmx_dev spear3xx_pmx_timer_3_4 = {
-        .name = "timer_3_4",
-        .modes = pmx_timer_3_4_modes,
-        .mode_count = ARRAY_SIZE(pmx_timer_3_4_modes),
-        .enb_on_reset = 0,
-};
-static struct pmx_dev_mode pmx_timer_1_2_modes[] = {
-        {
-                .ids = 0xffffffff,
-                .mask = PMX_TIMER_1_2_MASK,
-        },
-};
-struct pmx_dev spear3xx_pmx_timer_1_2 = {
-        .name = "timer_1_2",
-        .modes = pmx_timer_1_2_modes,
-        .mode_count = ARRAY_SIZE(pmx_timer_1_2_modes),
-        .enb_on_reset = 0,
-};
-#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
-/* plgpios devices */
-static struct pmx_dev_mode pmx_plgpio_0_1_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_FIRDA_MASK,
-        },
-};
-struct pmx_dev spear3xx_pmx_plgpio_0_1 = {
-        .name = "plgpio 0 and 1",
-        .modes = pmx_plgpio_0_1_modes,
-        .mode_count = ARRAY_SIZE(pmx_plgpio_0_1_modes),
-        .enb_on_reset = 1,
-};
-static struct pmx_dev_mode pmx_plgpio_2_3_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_UART0_MASK,
-        },
-};
-struct pmx_dev spear3xx_pmx_plgpio_2_3 = {
-        .name = "plgpio 2 and 3",
-        .modes = pmx_plgpio_2_3_modes,
-        .mode_count = ARRAY_SIZE(pmx_plgpio_2_3_modes),
-        .enb_on_reset = 1,
-};
-static struct pmx_dev_mode pmx_plgpio_4_5_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_I2C_MASK,
-        },
-};
-struct pmx_dev spear3xx_pmx_plgpio_4_5 = {
-        .name = "plgpio 4 and 5",
-        .modes = pmx_plgpio_4_5_modes,
-        .mode_count = ARRAY_SIZE(pmx_plgpio_4_5_modes),
-        .enb_on_reset = 1,
-};
-static struct pmx_dev_mode pmx_plgpio_6_9_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_SSP_MASK,
-        },
-};
-struct pmx_dev spear3xx_pmx_plgpio_6_9 = {
-        .name = "plgpio 6 to 9",
-        .modes = pmx_plgpio_6_9_modes,
-        .mode_count = ARRAY_SIZE(pmx_plgpio_6_9_modes),
-        .enb_on_reset = 1,
-};
-static struct pmx_dev_mode pmx_plgpio_10_27_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_MII_MASK,
-        },
-};
-struct pmx_dev spear3xx_pmx_plgpio_10_27 = {
-        .name = "plgpio 10 to 27",
-        .modes = pmx_plgpio_10_27_modes,
-        .mode_count = ARRAY_SIZE(pmx_plgpio_10_27_modes),
-        .enb_on_reset = 1,
-};
-static struct pmx_dev_mode pmx_plgpio_28_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_GPIO_PIN0_MASK,
-        },
-};
-struct pmx_dev spear3xx_pmx_plgpio_28 = {
-        .name = "plgpio 28",
-        .modes = pmx_plgpio_28_modes,
-        .mode_count = ARRAY_SIZE(pmx_plgpio_28_modes),
-        .enb_on_reset = 1,
-};
-static struct pmx_dev_mode pmx_plgpio_29_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_GPIO_PIN1_MASK,
-        },
-};
-struct pmx_dev spear3xx_pmx_plgpio_29 = {
-        .name = "plgpio 29",
-        .modes = pmx_plgpio_29_modes,
-        .mode_count = ARRAY_SIZE(pmx_plgpio_29_modes),
-        .enb_on_reset = 1,
-};
-static struct pmx_dev_mode pmx_plgpio_30_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_GPIO_PIN2_MASK,
-        },
-};
-struct pmx_dev spear3xx_pmx_plgpio_30 = {
-        .name = "plgpio 30",
-        .modes = pmx_plgpio_30_modes,
-        .mode_count = ARRAY_SIZE(pmx_plgpio_30_modes),
-        .enb_on_reset = 1,
-};
-static struct pmx_dev_mode pmx_plgpio_31_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_GPIO_PIN3_MASK,
-        },
-};
-struct pmx_dev spear3xx_pmx_plgpio_31 = {
-        .name = "plgpio 31",
-        .modes = pmx_plgpio_31_modes,
-        .mode_count = ARRAY_SIZE(pmx_plgpio_31_modes),
-        .enb_on_reset = 1,
-};
-static struct pmx_dev_mode pmx_plgpio_32_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_GPIO_PIN4_MASK,
-        },
-};
-struct pmx_dev spear3xx_pmx_plgpio_32 = {
-        .name = "plgpio 32",
-        .modes = pmx_plgpio_32_modes,
-        .mode_count = ARRAY_SIZE(pmx_plgpio_32_modes),
-        .enb_on_reset = 1,
-};
-static struct pmx_dev_mode pmx_plgpio_33_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_GPIO_PIN5_MASK,
-        },
-};
-struct pmx_dev spear3xx_pmx_plgpio_33 = {
-        .name = "plgpio 33",
-        .modes = pmx_plgpio_33_modes,
-        .mode_count = ARRAY_SIZE(pmx_plgpio_33_modes),
-        .enb_on_reset = 1,
-};
-static struct pmx_dev_mode pmx_plgpio_34_36_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_SSP_CS_MASK,
-        },
-};
-struct pmx_dev spear3xx_pmx_plgpio_34_36 = {
-        .name = "plgpio 34 to 36",
-        .modes = pmx_plgpio_34_36_modes,
-        .mode_count = ARRAY_SIZE(pmx_plgpio_34_36_modes),
-        .enb_on_reset = 1,
-};
-static struct pmx_dev_mode pmx_plgpio_37_42_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_UART0_MODEM_MASK,
-        },
-};
-struct pmx_dev spear3xx_pmx_plgpio_37_42 = {
-        .name = "plgpio 37 to 42",
-        .modes = pmx_plgpio_37_42_modes,
-        .mode_count = ARRAY_SIZE(pmx_plgpio_37_42_modes),
-        .enb_on_reset = 1,
-};
-static struct pmx_dev_mode pmx_plgpio_43_44_47_48_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_TIMER_1_2_MASK,
-        },
-};
-struct pmx_dev spear3xx_pmx_plgpio_43_44_47_48 = {
-        .name = "plgpio 43, 44, 47 and 48",
-        .modes = pmx_plgpio_43_44_47_48_modes,
-        .mode_count = ARRAY_SIZE(pmx_plgpio_43_44_47_48_modes),
-        .enb_on_reset = 1,
-};
-static struct pmx_dev_mode pmx_plgpio_45_46_49_50_modes[] = {
-        {
-                .ids = 0x00,
-                .mask = PMX_TIMER_3_4_MASK,
-        },
-};
-struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50 = {
-        .name = "plgpio 45, 46, 49 and 50",
-        .modes = pmx_plgpio_45_46_49_50_modes,
-        .mode_count = ARRAY_SIZE(pmx_plgpio_45_46_49_50_modes),
-        .enb_on_reset = 1,
-};
-#endif /* CONFIG_MACH_SPEAR310 || CONFIG_MACH_SPEAR320 */
 static void __init spear3xx_timer_init(void)
 {
        char pclk_name[] = "pll3_48m_clk";
@@ -530,9 +109,19 @@ static void __init spear3xx_timer_init(void)
        clk_put(gpt_clk);
        clk_put(pclk);
-        spear_setup_timer();
+        spear_setup_timer(SPEAR3XX_CPU_TMR_BASE, SPEAR3XX_IRQ_CPU_GPT1_1);
 }
 struct sys_timer spear3xx_timer = {
        .init = spear3xx_timer_init,
 };
+static const struct of_device_id vic_of_match[] __initconst = {
+        { .compatible = "arm,pl190-vic", .data = vic_of_init, },
+        { /* Sentinel */ }
+};
+void __init spear3xx_dt_init_irq(void)
+{
+        of_irq_init(vic_of_match);
+}
diff --git a/arch/arm/mach-spear6xx/Kconfig b/arch/arm/mach-spear6xx/Kconfig
index fbe298bd1d92..339f397dea70 100644
--- a/arch/arm/mach-spear6xx/Kconfig
+++ b/arch/arm/mach-spear6xx/Kconfig
@@ -2,21 +2,9 @@
 # SPEAr6XX Machine configuration file
 #
-if ARCH_SPEAR6XX
+config MACH_SPEAR600
+        def_bool y
-menu "SPEAr6xx Implementations"
+        depends on ARCH_SPEAR6XX
-config BOARD_SPEAR600_DT
-        bool "SPEAr600 generic board configured via device-tree"
-        select MACH_SPEAR600
        select USE_OF
        help
          Supports ST SPEAr600 boards configured via the device-tree
-endmenu
-config MACH_SPEAR600
-        bool "SPEAr600"
-        help
-          Supports ST SPEAr600 Machine
-endif #ARCH_SPEAR6XX
diff --git a/arch/arm/mach-spear6xx/Makefile.boot b/arch/arm/mach-spear6xx/Makefile.boot
index 4674a4c221db..af493da37ab6 100644
--- a/arch/arm/mach-spear6xx/Makefile.boot
+++ b/arch/arm/mach-spear6xx/Makefile.boot
@@ -1,3 +1,5 @@
 zreladdr-y      += 0x00008000
 params_phys-y   := 0x00000100
 initrd_phys-y   := 0x00800000
+dtb-$(CONFIG_BOARD_SPEAR600_DT) += spear600-evb.dtb
diff --git a/arch/arm/mach-spear6xx/clock.c b/arch/arm/mach-spear6xx/clock.c
index a86499a8a15f..bef77d43db87 100644
--- a/arch/arm/mach-spear6xx/clock.c
+++ b/arch/arm/mach-spear6xx/clock.c
@@ -16,6 +16,112 @@
 #include <linux/kernel.h>
 #include <plat/clock.h>
 #include <mach/misc_regs.h>
+#include <mach/spear.h>
+#define PLL1_CTR                (MISC_BASE + 0x008)
+#define PLL1_FRQ                (MISC_BASE + 0x00C)
+#define PLL1_MOD                (MISC_BASE + 0x010)
+#define PLL2_CTR                (MISC_BASE + 0x014)
+/* PLL_CTR register masks */
+#define PLL_ENABLE              2
+#define PLL_MODE_SHIFT          4
+#define PLL_MODE_MASK           0x3
+#define PLL_MODE_NORMAL         0
+#define PLL_MODE_FRACTION       1
+#define PLL_MODE_DITH_DSB       2
+#define PLL_MODE_DITH_SSB       3
+#define PLL2_FRQ                (MISC_BASE + 0x018)
+/* PLL FRQ register masks */
+#define PLL_DIV_N_SHIFT         0
+#define PLL_DIV_N_MASK          0xFF
+#define PLL_DIV_P_SHIFT         8
+#define PLL_DIV_P_MASK          0x7
+#define PLL_NORM_FDBK_M_SHIFT   24
+#define PLL_NORM_FDBK_M_MASK    0xFF
+#define PLL_DITH_FDBK_M_SHIFT   16
+#define PLL_DITH_FDBK_M_MASK    0xFFFF
+#define PLL2_MOD                (MISC_BASE + 0x01C)
+#define PLL_CLK_CFG             (MISC_BASE + 0x020)
+#define CORE_CLK_CFG            (MISC_BASE + 0x024)
+/* CORE CLK CFG register masks */
+#define PLL_HCLK_RATIO_SHIFT    10
+#define PLL_HCLK_RATIO_MASK     0x3
+#define HCLK_PCLK_RATIO_SHIFT   8
+#define HCLK_PCLK_RATIO_MASK    0x3
+#define PERIP_CLK_CFG           (MISC_BASE + 0x028)
+/* PERIP_CLK_CFG register masks */
+#define CLCD_CLK_SHIFT          2
+#define CLCD_CLK_MASK           0x3
+#define UART_CLK_SHIFT          4
+#define UART_CLK_MASK           0x1
+#define FIRDA_CLK_SHIFT         5
+#define FIRDA_CLK_MASK          0x3
+#define GPT0_CLK_SHIFT          8
+#define GPT1_CLK_SHIFT          10
+#define GPT2_CLK_SHIFT          11
+#define GPT3_CLK_SHIFT          12
+#define GPT_CLK_MASK            0x1
+#define AUX_CLK_PLL3_VAL        0
+#define AUX_CLK_PLL1_VAL        1
+#define PERIP1_CLK_ENB          (MISC_BASE + 0x02C)
+/* PERIP1_CLK_ENB register masks */
+#define UART0_CLK_ENB           3
+#define UART1_CLK_ENB           4
+#define SSP0_CLK_ENB            5
+#define SSP1_CLK_ENB            6
+#define I2C_CLK_ENB             7
+#define JPEG_CLK_ENB            8
+#define FSMC_CLK_ENB            9
+#define FIRDA_CLK_ENB           10
+#define GPT2_CLK_ENB            11
+#define GPT3_CLK_ENB            12
+#define GPIO2_CLK_ENB           13
+#define SSP2_CLK_ENB            14
+#define ADC_CLK_ENB             15
+#define GPT1_CLK_ENB            11
+#define RTC_CLK_ENB             17
+#define GPIO1_CLK_ENB           18
+#define DMA_CLK_ENB             19
+#define SMI_CLK_ENB             21
+#define CLCD_CLK_ENB            22
+#define GMAC_CLK_ENB            23
+#define USBD_CLK_ENB            24
+#define USBH0_CLK_ENB           25
+#define USBH1_CLK_ENB           26
+#define PRSC1_CLK_CFG           (MISC_BASE + 0x044)
+#define PRSC2_CLK_CFG           (MISC_BASE + 0x048)
+#define PRSC3_CLK_CFG           (MISC_BASE + 0x04C)
+/* gpt synthesizer register masks */
+#define GPT_MSCALE_SHIFT        0
+#define GPT_MSCALE_MASK         0xFFF
+#define GPT_NSCALE_SHIFT        12
+#define GPT_NSCALE_MASK         0xF
+#define AMEM_CLK_CFG            (MISC_BASE + 0x050)
+#define EXPI_CLK_CFG            (MISC_BASE + 0x054)
+#define CLCD_CLK_SYNT           (MISC_BASE + 0x05C)
+#define FIRDA_CLK_SYNT          (MISC_BASE + 0x060)
+#define UART_CLK_SYNT           (MISC_BASE + 0x064)
+#define GMAC_CLK_SYNT           (MISC_BASE + 0x068)
+#define RAS1_CLK_SYNT           (MISC_BASE + 0x06C)
+#define RAS2_CLK_SYNT           (MISC_BASE + 0x070)
+#define RAS3_CLK_SYNT           (MISC_BASE + 0x074)
+#define RAS4_CLK_SYNT           (MISC_BASE + 0x078)
+/* aux clk synthesiser register masks for irda to ras4 */
+#define AUX_SYNT_ENB            31
+#define AUX_EQ_SEL_SHIFT        30
+#define AUX_EQ_SEL_MASK         1
+#define AUX_EQ1_SEL             0
+#define AUX_EQ2_SEL             1
+#define AUX_XSCALE_SHIFT        16
+#define AUX_XSCALE_MASK         0xFFF
+#define AUX_YSCALE_SHIFT        0
+#define AUX_YSCALE_MASK         0xFFF
 /* root clks */
 /* 32 KHz oscillator clock */
@@ -623,53 +729,53 @@ static struct clk dummy_apb_pclk;
 /* array of all spear 6xx clock lookups */
 static struct clk_lookup spear_clk_lookups[] = {
-        { .con_id = "apb_pclk",         .clk = &dummy_apb_pclk},
+        CLKDEV_INIT(NULL, "apb_pclk", &dummy_apb_pclk),
        /* root clks */
-        { .con_id = "osc_32k_clk",      .clk = &osc_32k_clk},
+        CLKDEV_INIT(NULL, "osc_32k_clk", &osc_32k_clk),
-        { .con_id = "osc_30m_clk",      .clk = &osc_30m_clk},
+        CLKDEV_INIT(NULL, "osc_30m_clk", &osc_30m_clk),
        /* clock derived from 32 KHz os          clk */
-        { .dev_id = "rtc-spear",        .clk = &rtc_clk},
+        CLKDEV_INIT("rtc-spear", NULL, &rtc_clk),
        /* clock derived from 30 MHz os          clk */
-        { .con_id = "pll1_clk",         .clk = &pll1_clk},
+        CLKDEV_INIT(NULL, "pll1_clk", &pll1_clk),
-        { .con_id = "pll3_48m_clk",     .clk = &pll3_48m_clk},
+        CLKDEV_INIT(NULL, "pll3_48m_clk", &pll3_48m_clk),
-        { .dev_id = "wdt",              .clk = &wdt_clk},
+        CLKDEV_INIT("wdt", NULL, &wdt_clk),
        /* clock derived from pll1 clk */
-        { .con_id = "cpu_clk",          .clk = &cpu_clk},
+        CLKDEV_INIT(NULL, "cpu_clk", &cpu_clk),
-        { .con_id = "ahb_clk",          .clk = &ahb_clk},
+        CLKDEV_INIT(NULL, "ahb_clk", &ahb_clk),
-        { .con_id = "uart_synth_clk",   .clk = &uart_synth_clk},
+        CLKDEV_INIT(NULL, "uart_synth_clk", &uart_synth_clk),
-        { .con_id = "firda_synth_clk",  .clk = &firda_synth_clk},
+        CLKDEV_INIT(NULL, "firda_synth_clk", &firda_synth_clk),
-        { .con_id = "clcd_synth_clk",   .clk = &clcd_synth_clk},
+        CLKDEV_INIT(NULL, "clcd_synth_clk", &clcd_synth_clk),
-        { .con_id = "gpt0_synth_clk",   .clk = &gpt0_synth_clk},
+        CLKDEV_INIT(NULL, "gpt0_synth_clk", &gpt0_synth_clk),
-        { .con_id = "gpt2_synth_clk",   .clk = &gpt2_synth_clk},
+        CLKDEV_INIT(NULL, "gpt2_synth_clk", &gpt2_synth_clk),
-        { .con_id = "gpt3_synth_clk",   .clk = &gpt3_synth_clk},
+        CLKDEV_INIT(NULL, "gpt3_synth_clk", &gpt3_synth_clk),
-        { .dev_id = "d0000000.serial",  .clk = &uart0_clk},
+        CLKDEV_INIT("d0000000.serial", NULL, &uart0_clk),
-        { .dev_id = "d0080000.serial",  .clk = &uart1_clk},
+        CLKDEV_INIT("d0080000.serial", NULL, &uart1_clk),
-        { .dev_id = "firda",            .clk = &firda_clk},
+        CLKDEV_INIT("firda", NULL, &firda_clk),
-        { .dev_id = "clcd",             .clk = &clcd_clk},
+        CLKDEV_INIT("clcd", NULL, &clcd_clk),
-        { .dev_id = "gpt0",             .clk = &gpt0_clk},
+        CLKDEV_INIT("gpt0", NULL, &gpt0_clk),
-        { .dev_id = "gpt1",             .clk = &gpt1_clk},
+        CLKDEV_INIT("gpt1", NULL, &gpt1_clk),
-        { .dev_id = "gpt2",             .clk = &gpt2_clk},
+        CLKDEV_INIT("gpt2", NULL, &gpt2_clk),
-        { .dev_id = "gpt3",             .clk = &gpt3_clk},
+        CLKDEV_INIT("gpt3", NULL, &gpt3_clk),
        /* clock derived from pll3 clk */
-        { .dev_id = "designware_udc",   .clk = &usbd_clk},
+        CLKDEV_INIT("designware_udc", NULL, &usbd_clk),
-        { .con_id = "usbh.0_clk",       .clk = &usbh0_clk},
+        CLKDEV_INIT(NULL, "usbh.0_clk", &usbh0_clk),
-        { .con_id = "usbh.1_clk",       .clk = &usbh1_clk},
+        CLKDEV_INIT(NULL, "usbh.1_clk", &usbh1_clk),
        /* clock derived from ahb clk */
-        { .con_id = "apb_clk",          .clk = &apb_clk},
+        CLKDEV_INIT(NULL, "apb_clk", &apb_clk),
-        { .dev_id = "d0200000.i2c",     .clk = &i2c_clk},
+        CLKDEV_INIT("d0200000.i2c", NULL, &i2c_clk),
-        { .dev_id = "dma",              .clk = &dma_clk},
+        CLKDEV_INIT("fc400000.dma", NULL, &dma_clk),
-        { .dev_id = "jpeg",             .clk = &jpeg_clk},
+        CLKDEV_INIT("jpeg", NULL, &jpeg_clk),
-        { .dev_id = "gmac",             .clk = &gmac_clk},
+        CLKDEV_INIT("gmac", NULL, &gmac_clk),
-        { .dev_id = "smi",              .clk = &smi_clk},
+        CLKDEV_INIT("fc000000.flash", NULL, &smi_clk),
-        { .dev_id = "fsmc-nand",        .clk = &fsmc_clk},
+        CLKDEV_INIT("d1800000.flash", NULL, &fsmc_clk),
        /* clock derived from apb clk */
-        { .dev_id = "adc",              .clk = &adc_clk},
+        CLKDEV_INIT("adc", NULL, &adc_clk),
-        { .dev_id = "ssp-pl022.0",      .clk = &ssp0_clk},
+        CLKDEV_INIT("ssp-pl022.0", NULL, &ssp0_clk),
-        { .dev_id = "ssp-pl022.1",      .clk = &ssp1_clk},
+        CLKDEV_INIT("ssp-pl022.1", NULL, &ssp1_clk),
-        { .dev_id = "ssp-pl022.2",      .clk = &ssp2_clk},
+        CLKDEV_INIT("ssp-pl022.2", NULL, &ssp2_clk),
-        { .dev_id = "f0100000.gpio",    .clk = &gpio0_clk},
+        CLKDEV_INIT("f0100000.gpio", NULL, &gpio0_clk),
-        { .dev_id = "fc980000.gpio",    .clk = &gpio1_clk},
+        CLKDEV_INIT("fc980000.gpio", NULL, &gpio1_clk),
-        { .dev_id = "d8100000.gpio",    .clk = &gpio2_clk},
+        CLKDEV_INIT("d8100000.gpio", NULL, &gpio2_clk),
 };
 void __init spear6xx_clk_init(void)
diff --git a/arch/arm/mach-spear6xx/include/mach/generic.h b/arch/arm/mach-spear6xx/include/mach/generic.h
index 116b99301cf5..7167fd331d86 100644
--- a/arch/arm/mach-spear6xx/include/mach/generic.h
+++ b/arch/arm/mach-spear6xx/include/mach/generic.h
@@ -15,34 +15,9 @@
 #define __MACH_GENERIC_H
 #include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/amba/bus.h>
-#include <asm/mach/time.h>
-#include <asm/mach/map.h>
-/*
- * Each GPT has 2 timer channels
- * Following GPT channels will be used as clock source and clockevent
- */
-#define SPEAR_GPT0_BASE         SPEAR6XX_CPU_TMR_BASE
-#define SPEAR_GPT0_CHAN0_IRQ    IRQ_CPU_GPT1_1
-#define SPEAR_GPT0_CHAN1_IRQ    IRQ_CPU_GPT1_2
-/* Add spear6xx family device structure declarations here */
-extern struct amba_device gpio_device[];
-extern struct amba_device uart_device[];
-extern struct sys_timer spear6xx_timer;
-/* Add spear6xx family function declarations here */
-void __init spear_setup_timer(void);
-void __init spear6xx_map_io(void);
-void __init spear6xx_init_irq(void);
-void __init spear6xx_init(void);
-void __init spear600_init(void);
-void __init spear6xx_clk_init(void);
+void __init spear_setup_timer(resource_size_t base, int irq);
 void spear_restart(char, const char *);
+void __init spear6xx_clk_init(void);
-/* Add spear600 machine device structure declarations here */
 #endif /* __MACH_GENERIC_H */
diff --git a/arch/arm/mach-spear6xx/include/mach/hardware.h b/arch/arm/mach-spear6xx/include/mach/hardware.h
index 0b3f96ae2848..40a8c178f10d 100644
--- a/arch/arm/mach-spear6xx/include/mach/hardware.h
+++ b/arch/arm/mach-spear6xx/include/mach/hardware.h
@@ -1,23 +1 @@
-/*
+/* empty */
- * arch/arm/mach-spear6xx/include/mach/hardware.h
- *
- * Hardware definitions for SPEAr6xx machine family
- *
- * Copyright (C) 2009 ST Microelectronics
- * Rajeev Kumar<rajeev-dlh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#ifndef __MACH_HARDWARE_H
-#define __MACH_HARDWARE_H
-#include <plat/hardware.h>
-#include <mach/spear.h>
-/* Vitual to physical translation of statically mapped space */
-#define IO_ADDRESS(x)           (x | 0xF0000000)
-#endif /* __MACH_HARDWARE_H */
diff --git a/arch/arm/mach-spear6xx/include/mach/irqs.h b/arch/arm/mach-spear6xx/include/mach/irqs.h
index 8f214b03d75d..2b735389e74b 100644
--- a/arch/arm/mach-spear6xx/include/mach/irqs.h
+++ b/arch/arm/mach-spear6xx/include/mach/irqs.h
@@ -16,82 +16,13 @@
 /* IRQ definitions */
 /* VIC 1 */
-#define IRQ_INTRCOMM_SW_IRQ                     0
+/* FIXME: probe this from DT */
-#define IRQ_INTRCOMM_CPU_1                      1
-#define IRQ_INTRCOMM_CPU_2                      2
-#define IRQ_INTRCOMM_RAS2A11_1                  3
-#define IRQ_INTRCOMM_RAS2A11_2                  4
-#define IRQ_INTRCOMM_RAS2A12_1                  5
-#define IRQ_INTRCOMM_RAS2A12_2                  6
-#define IRQ_GEN_RAS_0                           7
-#define IRQ_GEN_RAS_1                           8
-#define IRQ_GEN_RAS_2                           9
-#define IRQ_GEN_RAS_3                           10
-#define IRQ_GEN_RAS_4                           11
-#define IRQ_GEN_RAS_5                           12
-#define IRQ_GEN_RAS_6                           13
-#define IRQ_GEN_RAS_7                           14
-#define IRQ_GEN_RAS_8                           15
 #define IRQ_CPU_GPT1_1                          16
-#define IRQ_CPU_GPT1_2                          17
-#define IRQ_LOCAL_GPIO                          18
-#define IRQ_PLL_UNLOCK                          19
-#define IRQ_JPEG                                20
-#define IRQ_FSMC                                21
-#define IRQ_IRDA                                22
-#define IRQ_RESERVED                            23
-#define IRQ_UART_0                              24
-#define IRQ_UART_1                              25
-#define IRQ_SSP_1                               26
-#define IRQ_SSP_2                               27
-#define IRQ_I2C                                 28
-#define IRQ_GEN_RAS_9                           29
-#define IRQ_GEN_RAS_10                          30
-#define IRQ_GEN_RAS_11                          31
-/* VIC 2 */
-#define IRQ_APPL_GPT1_1                         32
-#define IRQ_APPL_GPT1_2                         33
-#define IRQ_APPL_GPT2_1                         34
-#define IRQ_APPL_GPT2_2                         35
-#define IRQ_APPL_GPIO                           36
-#define IRQ_APPL_SSP                            37
-#define IRQ_APPL_ADC                            38
-#define IRQ_APPL_RESERVED                       39
-#define IRQ_AHB_EXP_MASTER                      40
-#define IRQ_DDR_CONTROLLER                      41
-#define IRQ_BASIC_DMA                           42
-#define IRQ_BASIC_RESERVED1                     43
-#define IRQ_BASIC_SMI                           44
-#define IRQ_BASIC_CLCD                          45
-#define IRQ_EXP_AHB_1                           46
-#define IRQ_EXP_AHB_2                           47
-#define IRQ_BASIC_GPT1_1                        48
-#define IRQ_BASIC_GPT1_2                        49
-#define IRQ_BASIC_RTC                           50
-#define IRQ_BASIC_GPIO                          51
-#define IRQ_BASIC_WDT                           52
-#define IRQ_BASIC_RESERVED                      53
-#define IRQ_AHB_EXP_SLAVE                       54
-#define IRQ_GMAC_1                              55
-#define IRQ_GMAC_2                              56
-#define IRQ_USB_DEV                             57
-#define IRQ_USB_H_OHCI_0                        58
-#define IRQ_USB_H_EHCI_0                        59
-#define IRQ_USB_H_OHCI_1                        60
-#define IRQ_USB_H_EHCI_1                        61
-#define IRQ_EXP_AHB_3                           62
-#define IRQ_EXP_AHB_4                           63
 #define IRQ_VIC_END                             64
 /* GPIO pins virtual irqs */
-#define SPEAR_GPIO_INT_BASE     IRQ_VIC_END
+#define VIRTUAL_IRQS                            24
-#define SPEAR_GPIO0_INT_BASE    SPEAR_GPIO_INT_BASE
+#define NR_IRQS                                 (IRQ_VIC_END + VIRTUAL_IRQS)
-#define SPEAR_GPIO1_INT_BASE    (SPEAR_GPIO0_INT_BASE + 8)
-#define SPEAR_GPIO2_INT_BASE    (SPEAR_GPIO1_INT_BASE + 8)
-#define SPEAR_GPIO_INT_END      (SPEAR_GPIO2_INT_BASE + 8)
-#define VIRTUAL_IRQS            (SPEAR_GPIO_INT_END - IRQ_VIC_END)
-#define NR_IRQS                 (IRQ_VIC_END + VIRTUAL_IRQS)
 #endif  /* __MACH_IRQS_H */
diff --git a/arch/arm/mach-spear6xx/include/mach/misc_regs.h b/arch/arm/mach-spear6xx/include/mach/misc_regs.h
index 68c20a007b0d..2b9aaa6cdd11 100644
--- a/arch/arm/mach-spear6xx/include/mach/misc_regs.h
+++ b/arch/arm/mach-spear6xx/include/mach/misc_regs.h
@@ -14,161 +14,7 @@
 #ifndef __MACH_MISC_REGS_H
 #define __MACH_MISC_REGS_H
-#include <mach/hardware.h>
 #define MISC_BASE               IOMEM(VA_SPEAR6XX_ICM3_MISC_REG_BASE)
-#define SOC_CFG_CTR             (MISC_BASE + 0x000)
-#define DIAG_CFG_CTR            (MISC_BASE + 0x004)
-#define PLL1_CTR                (MISC_BASE + 0x008)
-#define PLL1_FRQ                (MISC_BASE + 0x00C)
-#define PLL1_MOD                (MISC_BASE + 0x010)
-#define PLL2_CTR                (MISC_BASE + 0x014)
-/* PLL_CTR register masks */
-#define PLL_ENABLE              2
-#define PLL_MODE_SHIFT          4
-#define PLL_MODE_MASK           0x3
-#define PLL_MODE_NORMAL         0
-#define PLL_MODE_FRACTION       1
-#define PLL_MODE_DITH_DSB       2
-#define PLL_MODE_DITH_SSB       3
-#define PLL2_FRQ                (MISC_BASE + 0x018)
-/* PLL FRQ register masks */
-#define PLL_DIV_N_SHIFT         0
-#define PLL_DIV_N_MASK          0xFF
-#define PLL_DIV_P_SHIFT         8
-#define PLL_DIV_P_MASK          0x7
-#define PLL_NORM_FDBK_M_SHIFT   24
-#define PLL_NORM_FDBK_M_MASK    0xFF
-#define PLL_DITH_FDBK_M_SHIFT   16
-#define PLL_DITH_FDBK_M_MASK    0xFFFF
-#define PLL2_MOD                (MISC_BASE + 0x01C)
-#define PLL_CLK_CFG             (MISC_BASE + 0x020)
-#define CORE_CLK_CFG            (MISC_BASE + 0x024)
-/* CORE CLK CFG register masks */
-#define PLL_HCLK_RATIO_SHIFT    10
-#define PLL_HCLK_RATIO_MASK     0x3
-#define HCLK_PCLK_RATIO_SHIFT   8
-#define HCLK_PCLK_RATIO_MASK    0x3
-#define PERIP_CLK_CFG           (MISC_BASE + 0x028)
-/* PERIP_CLK_CFG register masks */
-#define CLCD_CLK_SHIFT          2
-#define CLCD_CLK_MASK           0x3
-#define UART_CLK_SHIFT          4
-#define UART_CLK_MASK           0x1
-#define FIRDA_CLK_SHIFT         5
-#define FIRDA_CLK_MASK          0x3
-#define GPT0_CLK_SHIFT          8
-#define GPT1_CLK_SHIFT          10
-#define GPT2_CLK_SHIFT          11
-#define GPT3_CLK_SHIFT          12
-#define GPT_CLK_MASK            0x1
-#define AUX_CLK_PLL3_VAL        0
-#define AUX_CLK_PLL1_VAL        1
-#define PERIP1_CLK_ENB          (MISC_BASE + 0x02C)
-/* PERIP1_CLK_ENB register masks */
-#define UART0_CLK_ENB           3
-#define UART1_CLK_ENB           4
-#define SSP0_CLK_ENB            5
-#define SSP1_CLK_ENB            6
-#define I2C_CLK_ENB             7
-#define JPEG_CLK_ENB            8
-#define FSMC_CLK_ENB            9
-#define FIRDA_CLK_ENB           10
-#define GPT2_CLK_ENB            11
-#define GPT3_CLK_ENB            12
-#define GPIO2_CLK_ENB           13
-#define SSP2_CLK_ENB            14
-#define ADC_CLK_ENB             15
-#define GPT1_CLK_ENB            11
-#define RTC_CLK_ENB             17
-#define GPIO1_CLK_ENB           18
-#define DMA_CLK_ENB             19
-#define SMI_CLK_ENB             21
-#define CLCD_CLK_ENB            22
-#define GMAC_CLK_ENB            23
-#define USBD_CLK_ENB            24
-#define USBH0_CLK_ENB           25
-#define USBH1_CLK_ENB           26
-#define SOC_CORE_ID             (MISC_BASE + 0x030)
-#define RAS_CLK_ENB             (MISC_BASE + 0x034)
-#define PERIP1_SOF_RST          (MISC_BASE + 0x038)
-/* PERIP1_SOF_RST register masks */
-#define JPEG_SOF_RST            8
-#define SOC_USER_ID             (MISC_BASE + 0x03C)
-#define RAS_SOF_RST             (MISC_BASE + 0x040)
-#define PRSC1_CLK_CFG           (MISC_BASE + 0x044)
-#define PRSC2_CLK_CFG           (MISC_BASE + 0x048)
-#define PRSC3_CLK_CFG           (MISC_BASE + 0x04C)
-/* gpt synthesizer register masks */
-#define GPT_MSCALE_SHIFT        0
-#define GPT_MSCALE_MASK         0xFFF
-#define GPT_NSCALE_SHIFT        12
-#define GPT_NSCALE_MASK         0xF
-#define AMEM_CLK_CFG            (MISC_BASE + 0x050)
-#define EXPI_CLK_CFG            (MISC_BASE + 0x054)
-#define CLCD_CLK_SYNT           (MISC_BASE + 0x05C)
-#define FIRDA_CLK_SYNT          (MISC_BASE + 0x060)
-#define UART_CLK_SYNT           (MISC_BASE + 0x064)
-#define GMAC_CLK_SYNT           (MISC_BASE + 0x068)
-#define RAS1_CLK_SYNT           (MISC_BASE + 0x06C)
-#define RAS2_CLK_SYNT           (MISC_BASE + 0x070)
-#define RAS3_CLK_SYNT           (MISC_BASE + 0x074)
-#define RAS4_CLK_SYNT           (MISC_BASE + 0x078)
-/* aux clk synthesiser register masks for irda to ras4 */
-#define AUX_SYNT_ENB            31
-#define AUX_EQ_SEL_SHIFT        30
-#define AUX_EQ_SEL_MASK         1
-#define AUX_EQ1_SEL             0
-#define AUX_EQ2_SEL             1
-#define AUX_XSCALE_SHIFT        16
-#define AUX_XSCALE_MASK         0xFFF
-#define AUX_YSCALE_SHIFT        0
-#define AUX_YSCALE_MASK         0xFFF
-#define ICM1_ARB_CFG            (MISC_BASE + 0x07C)
-#define ICM2_ARB_CFG            (MISC_BASE + 0x080)
-#define ICM3_ARB_CFG            (MISC_BASE + 0x084)
-#define ICM4_ARB_CFG            (MISC_BASE + 0x088)
-#define ICM5_ARB_CFG            (MISC_BASE + 0x08C)
-#define ICM6_ARB_CFG            (MISC_BASE + 0x090)
-#define ICM7_ARB_CFG            (MISC_BASE + 0x094)
-#define ICM8_ARB_CFG            (MISC_BASE + 0x098)
-#define ICM9_ARB_CFG            (MISC_BASE + 0x09C)
 #define DMA_CHN_CFG             (MISC_BASE + 0x0A0)
-#define USB2_PHY_CFG            (MISC_BASE + 0x0A4)
-#define GMAC_CFG_CTR            (MISC_BASE + 0x0A8)
-#define EXPI_CFG_CTR            (MISC_BASE + 0x0AC)
-#define PRC1_LOCK_CTR           (MISC_BASE + 0x0C0)
-#define PRC2_LOCK_CTR           (MISC_BASE + 0x0C4)
-#define PRC3_LOCK_CTR           (MISC_BASE + 0x0C8)
-#define PRC4_LOCK_CTR           (MISC_BASE + 0x0CC)
-#define PRC1_IRQ_CTR            (MISC_BASE + 0x0D0)
-#define PRC2_IRQ_CTR            (MISC_BASE + 0x0D4)
-#define PRC3_IRQ_CTR            (MISC_BASE + 0x0D8)
-#define PRC4_IRQ_CTR            (MISC_BASE + 0x0DC)
-#define PWRDOWN_CFG_CTR         (MISC_BASE + 0x0E0)
-#define COMPSSTL_1V8_CFG        (MISC_BASE + 0x0E4)
-#define COMPSSTL_2V5_CFG        (MISC_BASE + 0x0E8)
-#define COMPCOR_3V3_CFG         (MISC_BASE + 0x0EC)
-#define SSTLPAD_CFG_CTR         (MISC_BASE + 0x0F0)
-#define BIST1_CFG_CTR           (MISC_BASE + 0x0F4)
-#define BIST2_CFG_CTR           (MISC_BASE + 0x0F8)
-#define BIST3_CFG_CTR           (MISC_BASE + 0x0FC)
-#define BIST4_CFG_CTR           (MISC_BASE + 0x100)
-#define BIST5_CFG_CTR           (MISC_BASE + 0x104)
-#define BIST1_STS_RES           (MISC_BASE + 0x108)
-#define BIST2_STS_RES           (MISC_BASE + 0x10C)
-#define BIST3_STS_RES           (MISC_BASE + 0x110)
-#define BIST4_STS_RES           (MISC_BASE + 0x114)
-#define BIST5_STS_RES           (MISC_BASE + 0x118)
-#define SYSERR_CFG_CTR          (MISC_BASE + 0x11C)
 #endif /* __MACH_MISC_REGS_H */
diff --git a/arch/arm/mach-spear6xx/include/mach/spear.h b/arch/arm/mach-spear6xx/include/mach/spear.h
index 7fd621532def..d278ed047a53 100644
--- a/arch/arm/mach-spear6xx/include/mach/spear.h
+++ b/arch/arm/mach-spear6xx/include/mach/spear.h
@@ -15,69 +15,26 @@
 #define __MACH_SPEAR6XX_H
 #include <asm/memory.h>
-#include <mach/spear600.h>
-#define SPEAR6XX_ML_SDRAM_BASE          UL(0x00000000)
 /* ICM1 - Low speed connection */
 #define SPEAR6XX_ICM1_BASE              UL(0xD0000000)
+#define VA_SPEAR6XX_ICM1_BASE           UL(0xFD000000)
 #define SPEAR6XX_ICM1_UART0_BASE        UL(0xD0000000)
-#define VA_SPEAR6XX_ICM1_UART0_BASE     IO_ADDRESS(SPEAR6XX_ICM1_UART0_BASE)
+#define VA_SPEAR6XX_ICM1_UART0_BASE     (VA_SPEAR6XX_ICM1_2_BASE | SPEAR6XX_ICM1_UART0_BASE)
-#define SPEAR6XX_ICM1_UART1_BASE        UL(0xD0080000)
-#define SPEAR6XX_ICM1_SSP0_BASE         UL(0xD0100000)
-#define SPEAR6XX_ICM1_SSP1_BASE         UL(0xD0180000)
-#define SPEAR6XX_ICM1_I2C_BASE          UL(0xD0200000)
-#define SPEAR6XX_ICM1_JPEG_BASE         UL(0xD0800000)
-#define SPEAR6XX_ICM1_IRDA_BASE         UL(0xD1000000)
-#define SPEAR6XX_ICM1_FSMC_BASE         UL(0xD1800000)
-#define SPEAR6XX_ICM1_NAND_BASE         UL(0xD2000000)
-#define SPEAR6XX_ICM1_SRAM_BASE         UL(0xD2800000)
-/* ICM2 - Application Subsystem */
-#define SPEAR6XX_ICM2_BASE              UL(0xD8000000)
-#define SPEAR6XX_ICM2_TMR0_BASE         UL(0xD8000000)
-#define SPEAR6XX_ICM2_TMR1_BASE         UL(0xD8080000)
-#define SPEAR6XX_ICM2_GPIO_BASE         UL(0xD8100000)
-#define SPEAR6XX_ICM2_SSP2_BASE         UL(0xD8180000)
-#define SPEAR6XX_ICM2_ADC_BASE          UL(0xD8200000)
 /* ML-1, 2 - Multi Layer CPU Subsystem */
 #define SPEAR6XX_ML_CPU_BASE            UL(0xF0000000)
+#define VA_SPEAR6XX_ML_CPU_BASE         UL(0xF0000000)
 #define SPEAR6XX_CPU_TMR_BASE           UL(0xF0000000)
-#define SPEAR6XX_CPU_GPIO_BASE          UL(0xF0100000)
-#define SPEAR6XX_CPU_VIC_SEC_BASE       UL(0xF1000000)
-#define VA_SPEAR6XX_CPU_VIC_SEC_BASE    IO_ADDRESS(SPEAR6XX_CPU_VIC_SEC_BASE)
-#define SPEAR6XX_CPU_VIC_PRI_BASE       UL(0xF1100000)
-#define VA_SPEAR6XX_CPU_VIC_PRI_BASE    IO_ADDRESS(SPEAR6XX_CPU_VIC_PRI_BASE)
 /* ICM3 - Basic Subsystem */
-#define SPEAR6XX_ICM3_BASE              UL(0xF8000000)
-#define SPEAR6XX_ICM3_SMEM_BASE         UL(0xF8000000)
 #define SPEAR6XX_ICM3_SMI_CTRL_BASE     UL(0xFC000000)
-#define SPEAR6XX_ICM3_CLCD_BASE         UL(0xFC200000)
+#define VA_SPEAR6XX_ICM3_SMI_CTRL_BASE  UL(0xFC000000)
 #define SPEAR6XX_ICM3_DMA_BASE          UL(0xFC400000)
-#define SPEAR6XX_ICM3_SDRAM_CTRL_BASE   UL(0xFC600000)
-#define SPEAR6XX_ICM3_TMR_BASE          UL(0xFC800000)
-#define SPEAR6XX_ICM3_WDT_BASE          UL(0xFC880000)
-#define SPEAR6XX_ICM3_RTC_BASE          UL(0xFC900000)
-#define SPEAR6XX_ICM3_GPIO_BASE         UL(0xFC980000)
 #define SPEAR6XX_ICM3_SYS_CTRL_BASE     UL(0xFCA00000)
-#define VA_SPEAR6XX_ICM3_SYS_CTRL_BASE  IO_ADDRESS(SPEAR6XX_ICM3_SYS_CTRL_BASE)
+#define VA_SPEAR6XX_ICM3_SYS_CTRL_BASE  (VA_SPEAR6XX_ICM3_SMI_CTRL_BASE | SPEAR6XX_ICM3_SYS_CTRL_BASE)
 #define SPEAR6XX_ICM3_MISC_REG_BASE     UL(0xFCA80000)
-#define VA_SPEAR6XX_ICM3_MISC_REG_BASE  IO_ADDRESS(SPEAR6XX_ICM3_MISC_REG_BASE)
+#define VA_SPEAR6XX_ICM3_MISC_REG_BASE  (VA_SPEAR6XX_ICM3_SMI_CTRL_BASE | SPEAR6XX_ICM3_MISC_REG_BASE)
-/* ICM4 - High Speed Connection */
-#define SPEAR6XX_ICM4_BASE              UL(0xE0000000)
-#define SPEAR6XX_ICM4_GMAC_BASE         UL(0xE0800000)
-#define SPEAR6XX_ICM4_USBD_FIFO_BASE    UL(0xE1000000)
-#define SPEAR6XX_ICM4_USBD_CSR_BASE     UL(0xE1100000)
-#define SPEAR6XX_ICM4_USBD_PLDT_BASE    UL(0xE1200000)
-#define SPEAR6XX_ICM4_USB_EHCI0_BASE    UL(0xE1800000)
-#define SPEAR6XX_ICM4_USB_OHCI0_BASE    UL(0xE1900000)
-#define SPEAR6XX_ICM4_USB_EHCI1_BASE    UL(0xE2000000)
-#define SPEAR6XX_ICM4_USB_OHCI1_BASE    UL(0xE2100000)
-#define SPEAR6XX_ICM4_USB_ARB_BASE      UL(0xE2800000)
 /* Debug uart for linux, will be used for debug and uncompress messages */
 #define SPEAR_DBG_UART_BASE             SPEAR6XX_ICM1_UART0_BASE
diff --git a/arch/arm/mach-spear6xx/include/mach/spear600.h b/arch/arm/mach-spear6xx/include/mach/spear600.h
deleted file mode 100644
index c068cc50b0fb..000000000000
--- a/arch/arm/mach-spear6xx/include/mach/spear600.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * arch/arm/mach-spear66xx/include/mach/spear600.h
- *
- * SPEAr600 Machine specific definition
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#ifdef  CONFIG_MACH_SPEAR600
-#ifndef __MACH_SPEAR600_H
-#define __MACH_SPEAR600_H
-#endif /* __MACH_SPEAR600_H */
-#endif /* CONFIG_MACH_SPEAR600 */
diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c
index 2ed8b14c82c8..de194dbb8371 100644
--- a/arch/arm/mach-spear6xx/spear6xx.c
+++ b/arch/arm/mach-spear6xx/spear6xx.c
@@ -13,41 +13,404 @@
 * warranty of any kind, whether express or implied.
 */
+#include <linux/amba/pl08x.h>
+#include <linux/clk.h>
+#include <linux/err.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
+#include <asm/hardware/pl080.h>
 #include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+#include <plat/pl080.h>
 #include <mach/generic.h>
-#include <mach/hardware.h>
+#include <mach/spear.h>
-/* Following will create static virtual/physical mappings */
+/* dmac device registration */
-static struct map_desc spear6xx_io_desc[] __initdata = {
+static struct pl08x_channel_data spear600_dma_info[] = {
        {
-                .virtual        = VA_SPEAR6XX_ICM1_UART0_BASE,
+                .bus_id = "ssp1_rx",
-                .pfn            = __phys_to_pfn(SPEAR6XX_ICM1_UART0_BASE),
+                .min_signal = 0,
-                .length         = SZ_4K,
+                .max_signal = 0,
-                .type           = MT_DEVICE
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
        }, {
-                .virtual        = VA_SPEAR6XX_CPU_VIC_PRI_BASE,
+                .bus_id = "ssp1_tx",
-                .pfn            = __phys_to_pfn(SPEAR6XX_CPU_VIC_PRI_BASE),
+                .min_signal = 1,
-                .length         = SZ_4K,
+                .max_signal = 1,
-                .type           = MT_DEVICE
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
        }, {
-                .virtual        = VA_SPEAR6XX_CPU_VIC_SEC_BASE,
+                .bus_id = "uart0_rx",
-                .pfn            = __phys_to_pfn(SPEAR6XX_CPU_VIC_SEC_BASE),
+                .min_signal = 2,
-                .length         = SZ_4K,
+                .max_signal = 2,
-                .type           = MT_DEVICE
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart0_tx",
+                .min_signal = 3,
+                .max_signal = 3,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart1_rx",
+                .min_signal = 4,
+                .max_signal = 4,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "uart1_tx",
+                .min_signal = 5,
+                .max_signal = 5,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ssp2_rx",
+                .min_signal = 6,
+                .max_signal = 6,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ssp2_tx",
+                .min_signal = 7,
+                .max_signal = 7,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ssp0_rx",
+                .min_signal = 8,
+                .max_signal = 8,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ssp0_tx",
+                .min_signal = 9,
+                .max_signal = 9,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "i2c_rx",
+                .min_signal = 10,
+                .max_signal = 10,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "i2c_tx",
+                .min_signal = 11,
+                .max_signal = 11,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "irda",
+                .min_signal = 12,
+                .max_signal = 12,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "adc",
+                .min_signal = 13,
+                .max_signal = 13,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "to_jpeg",
+                .min_signal = 14,
+                .max_signal = 14,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "from_jpeg",
+                .min_signal = 15,
+                .max_signal = 15,
+                .muxval = 0,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras0_rx",
+                .min_signal = 0,
+                .max_signal = 0,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras0_tx",
+                .min_signal = 1,
+                .max_signal = 1,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras1_rx",
+                .min_signal = 2,
+                .max_signal = 2,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras1_tx",
+                .min_signal = 3,
+                .max_signal = 3,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras2_rx",
+                .min_signal = 4,
+                .max_signal = 4,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras2_tx",
+                .min_signal = 5,
+                .max_signal = 5,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras3_rx",
+                .min_signal = 6,
+                .max_signal = 6,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras3_tx",
+                .min_signal = 7,
+                .max_signal = 7,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras4_rx",
+                .min_signal = 8,
+                .max_signal = 8,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras4_tx",
+                .min_signal = 9,
+                .max_signal = 9,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras5_rx",
+                .min_signal = 10,
+                .max_signal = 10,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras5_tx",
+                .min_signal = 11,
+                .max_signal = 11,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras6_rx",
+                .min_signal = 12,
+                .max_signal = 12,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras6_tx",
+                .min_signal = 13,
+                .max_signal = 13,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
        }, {
-                .virtual        = VA_SPEAR6XX_ICM3_SYS_CTRL_BASE,
+                .bus_id = "ras7_rx",
-                .pfn            = __phys_to_pfn(SPEAR6XX_ICM3_SYS_CTRL_BASE),
+                .min_signal = 14,
-                .length         = SZ_4K,
+                .max_signal = 14,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ras7_tx",
+                .min_signal = 15,
+                .max_signal = 15,
+                .muxval = 1,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB1,
+        }, {
+                .bus_id = "ext0_rx",
+                .min_signal = 0,
+                .max_signal = 0,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext0_tx",
+                .min_signal = 1,
+                .max_signal = 1,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext1_rx",
+                .min_signal = 2,
+                .max_signal = 2,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext1_tx",
+                .min_signal = 3,
+                .max_signal = 3,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext2_rx",
+                .min_signal = 4,
+                .max_signal = 4,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext2_tx",
+                .min_signal = 5,
+                .max_signal = 5,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext3_rx",
+                .min_signal = 6,
+                .max_signal = 6,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext3_tx",
+                .min_signal = 7,
+                .max_signal = 7,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext4_rx",
+                .min_signal = 8,
+                .max_signal = 8,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext4_tx",
+                .min_signal = 9,
+                .max_signal = 9,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext5_rx",
+                .min_signal = 10,
+                .max_signal = 10,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext5_tx",
+                .min_signal = 11,
+                .max_signal = 11,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext6_rx",
+                .min_signal = 12,
+                .max_signal = 12,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext6_tx",
+                .min_signal = 13,
+                .max_signal = 13,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext7_rx",
+                .min_signal = 14,
+                .max_signal = 14,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        }, {
+                .bus_id = "ext7_tx",
+                .min_signal = 15,
+                .max_signal = 15,
+                .muxval = 2,
+                .cctl = 0,
+                .periph_buses = PL08X_AHB2,
+        },
+};
+struct pl08x_platform_data pl080_plat_data = {
+        .memcpy_channel = {
+                .bus_id = "memcpy",
+                .cctl = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \
+                        PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \
+                        PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \
+                        PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \
+                        PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | \
+                        PL080_CONTROL_PROT_SYS),
+        },
+        .lli_buses = PL08X_AHB1,
+        .mem_buses = PL08X_AHB1,
+        .get_signal = pl080_get_signal,
+        .put_signal = pl080_put_signal,
+        .slave_channels = spear600_dma_info,
+        .num_slave_channels = ARRAY_SIZE(spear600_dma_info),
+};
+/*
+ * Following will create 16MB static virtual/physical mappings
+ * PHYSICAL             VIRTUAL
+ * 0xF0000000           0xF0000000
+ * 0xF1000000           0xF1000000
+ * 0xD0000000           0xFD000000
+ * 0xFC000000           0xFC000000
+ */
+struct map_desc spear6xx_io_desc[] __initdata = {
+        {
+                .virtual        = VA_SPEAR6XX_ML_CPU_BASE,
+                .pfn            = __phys_to_pfn(SPEAR6XX_ML_CPU_BASE),
+                .length         = 2 * SZ_16M,
+                .type           = MT_DEVICE
+        },      {
+                .virtual        = VA_SPEAR6XX_ICM1_BASE,
+                .pfn            = __phys_to_pfn(SPEAR6XX_ICM1_BASE),
+                .length         = SZ_16M,
                .type           = MT_DEVICE
        }, {
-                .virtual        = VA_SPEAR6XX_ICM3_MISC_REG_BASE,
+                .virtual        = VA_SPEAR6XX_ICM3_SMI_CTRL_BASE,
-                .pfn            = __phys_to_pfn(SPEAR6XX_ICM3_MISC_REG_BASE),
+                .pfn            = __phys_to_pfn(SPEAR6XX_ICM3_SMI_CTRL_BASE),
-                .length         = SZ_4K,
+                .length         = SZ_16M,
                .type           = MT_DEVICE
        },
 };
@@ -85,16 +448,24 @@ static void __init spear6xx_timer_init(void)
        clk_put(gpt_clk);
        clk_put(pclk);
-        spear_setup_timer();
+        spear_setup_timer(SPEAR6XX_CPU_TMR_BASE, IRQ_CPU_GPT1_1);
 }
 struct sys_timer spear6xx_timer = {
        .init = spear6xx_timer_init,
 };
+/* Add auxdata to pass platform data */
+struct of_dev_auxdata spear6xx_auxdata_lookup[] __initdata = {
+        OF_DEV_AUXDATA("arm,pl080", SPEAR6XX_ICM3_DMA_BASE, NULL,
+                        &pl080_plat_data),
+        {}
+};
 static void __init spear600_dt_init(void)
 {
-        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+        of_platform_populate(NULL, of_default_bus_match_table,
+                        spear6xx_auxdata_lookup, NULL);
 }
 static const char *spear600_dt_board_compat[] = {
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index d87d968115ec..2eb4445ddb14 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -5,7 +5,6 @@ obj-y                                   += io.o
 obj-y                                   += irq.o
 obj-y                                   += clock.o
 obj-y                                   += timer.o
-obj-y                                   += pinmux.o
 obj-y                                   += fuse.o
 obj-y                                   += pmc.o
 obj-y                                   += flowctrl.o
@@ -14,8 +13,6 @@ obj-$(CONFIG_CPU_IDLE)			+= sleep.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += powergate.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_clocks.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_emc.o
-obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += pinmux-tegra20-tables.o
-obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += pinmux-tegra30-tables.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += board-dt-tegra30.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += tegra30_clocks.o
 obj-$(CONFIG_SMP)                       += platsmp.o headsmp.o
diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c
index 0952494f481a..8351c4c147ad 100644
--- a/arch/arm/mach-tegra/board-dt-tegra20.c
+++ b/arch/arm/mach-tegra/board-dt-tegra20.c
@@ -37,7 +37,6 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/setup.h>
-#include <asm/hardware/gic.h>
 #include <mach/iomap.h>
 #include <mach/irqs.h>
@@ -47,15 +46,7 @@
 #include "clock.h"
 #include "devices.h"
-void harmony_pinmux_init(void);
-void paz00_pinmux_init(void);
-void seaboard_pinmux_init(void);
-void trimslice_pinmux_init(void);
-void ventana_pinmux_init(void);
 struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
-        OF_DEV_AUXDATA("nvidia,tegra20-pinmux", TEGRA_APB_MISC_BASE + 0x14, "tegra-pinmux", NULL),
-        OF_DEV_AUXDATA("nvidia,tegra20-gpio", TEGRA_GPIO_BASE, "tegra-gpio", NULL),
        OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC1_BASE, "sdhci-tegra.0", NULL),
        OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC2_BASE, "sdhci-tegra.1", NULL),
        OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC3_BASE, "sdhci-tegra.2", NULL),
@@ -95,33 +86,10 @@ static struct of_device_id tegra_dt_match_table[] __initdata = {
        {}
 };
-static struct {
-        char *machine;
-        void (*init)(void);
-} pinmux_configs[] = {
-        { "compulab,trimslice", trimslice_pinmux_init },
-        { "nvidia,harmony", harmony_pinmux_init },
-        { "compal,paz00", paz00_pinmux_init },
-        { "nvidia,seaboard", seaboard_pinmux_init },
-        { "nvidia,ventana", ventana_pinmux_init },
-};
 static void __init tegra_dt_init(void)
 {
-        int i;
        tegra_clk_init_from_table(tegra_dt_clk_init_table);
-        for (i = 0; i < ARRAY_SIZE(pinmux_configs); i++) {
-                if (of_machine_is_compatible(pinmux_configs[i].machine)) {
-                        pinmux_configs[i].init();
-                        break;
-                }
-        }
-        WARN(i == ARRAY_SIZE(pinmux_configs),
-                "Unknown platform! Pinmuxing not initialized\n");
        /*
         * Finished with the static registrations now; fill in the missing
         * devices
diff --git a/arch/arm/mach-tegra/board-harmony-pinmux.c b/arch/arm/mach-tegra/board-harmony-pinmux.c
index 1af85bccc0f1..83d420fbc58c 100644
--- a/arch/arm/mach-tegra/board-harmony-pinmux.c
+++ b/arch/arm/mach-tegra/board-harmony-pinmux.c
@@ -2,6 +2,7 @@
 * arch/arm/mach-tegra/board-harmony-pinmux.c
 *
 * Copyright (C) 2010 Google, Inc.
+ * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
@@ -15,153 +16,138 @@
 */
 #include <linux/kernel.h>
-#include <linux/gpio.h>
-#include <linux/of.h>
-#include <mach/pinmux.h>
-#include <mach/pinmux-tegra20.h>
-#include "gpio-names.h"
 #include "board-harmony.h"
 #include "board-pinmux.h"
-static struct tegra_pingroup_config harmony_pinmux[] = {
+static struct pinctrl_map harmony_map[] = {
-        {TEGRA_PINGROUP_ATA,   TEGRA_MUX_IDE,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("ata",   "ide",           none, driven),
-        {TEGRA_PINGROUP_ATB,   TEGRA_MUX_SDIO4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("atb",   "sdio4",         none, driven),
-        {TEGRA_PINGROUP_ATC,   TEGRA_MUX_NAND,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("atc",   "nand",          none, driven),
-        {TEGRA_PINGROUP_ATD,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("atd",   "gmi",           none, driven),
-        {TEGRA_PINGROUP_ATE,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("ate",   "gmi",           none, driven),
-        {TEGRA_PINGROUP_CDEV1, TEGRA_MUX_PLLA_OUT,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("cdev1", "plla_out",      none, driven),
-        {TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4,     TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("cdev2", "pllp_out4",     down, tristate),
-        {TEGRA_PINGROUP_CRTP,  TEGRA_MUX_CRT,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("crtp",  "crt",           none, tristate),
-        {TEGRA_PINGROUP_CSUS,  TEGRA_MUX_VI_SENSOR_CLK, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("csus",  "vi_sensor_clk", down, tristate),
-        {TEGRA_PINGROUP_DAP1,  TEGRA_MUX_DAP1,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("dap1",  "dap1",          none, driven),
-        {TEGRA_PINGROUP_DAP2,  TEGRA_MUX_DAP2,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("dap2",  "dap2",          none, tristate),
-        {TEGRA_PINGROUP_DAP3,  TEGRA_MUX_DAP3,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("dap3",  "dap3",          none, tristate),
-        {TEGRA_PINGROUP_DAP4,  TEGRA_MUX_DAP4,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("dap4",  "dap4",          none, tristate),
-        {TEGRA_PINGROUP_DDC,   TEGRA_MUX_I2C2,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("ddc",   "i2c2",          up,   driven),
-        {TEGRA_PINGROUP_DTA,   TEGRA_MUX_SDIO2,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("dta",   "sdio2",         up,   driven),
-        {TEGRA_PINGROUP_DTB,   TEGRA_MUX_RSVD1,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("dtb",   "rsvd1",         none, driven),
-        {TEGRA_PINGROUP_DTC,   TEGRA_MUX_RSVD1,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("dtc",   "rsvd1",         none, tristate),
-        {TEGRA_PINGROUP_DTD,   TEGRA_MUX_SDIO2,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("dtd",   "sdio2",         up,   driven),
-        {TEGRA_PINGROUP_DTE,   TEGRA_MUX_RSVD1,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("dte",   "rsvd1",         none, tristate),
-        {TEGRA_PINGROUP_DTF,   TEGRA_MUX_I2C3,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("dtf",   "i2c3",          none, tristate),
-        {TEGRA_PINGROUP_GMA,   TEGRA_MUX_SDIO4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("gma",   "sdio4",         none, driven),
-        {TEGRA_PINGROUP_GMB,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("gmb",   "gmi",           none, driven),
-        {TEGRA_PINGROUP_GMC,   TEGRA_MUX_UARTD,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("gmc",   "uartd",         none, driven),
-        {TEGRA_PINGROUP_GMD,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("gmd",   "gmi",           none, driven),
-        {TEGRA_PINGROUP_GME,   TEGRA_MUX_SDIO4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("gme",   "sdio4",         none, driven),
-        {TEGRA_PINGROUP_GPU,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("gpu",   "gmi",           none, tristate),
-        {TEGRA_PINGROUP_GPU7,  TEGRA_MUX_RTCK,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("gpu7",  "rtck",          none, driven),
-        {TEGRA_PINGROUP_GPV,   TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("gpv",   "pcie",          none, driven),
-        {TEGRA_PINGROUP_HDINT, TEGRA_MUX_HDMI,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("hdint", "hdmi",          na,   tristate),
-        {TEGRA_PINGROUP_I2CP,  TEGRA_MUX_I2C,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("i2cp",  "i2cp",          none, driven),
-        {TEGRA_PINGROUP_IRRX,  TEGRA_MUX_UARTA,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("irrx",  "uarta",         up,   tristate),
-        {TEGRA_PINGROUP_IRTX,  TEGRA_MUX_UARTA,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("irtx",  "uarta",         up,   tristate),
-        {TEGRA_PINGROUP_KBCA,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("kbca",  "kbc",           up,   driven),
-        {TEGRA_PINGROUP_KBCB,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("kbcb",  "kbc",           up,   driven),
-        {TEGRA_PINGROUP_KBCC,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("kbcc",  "kbc",           up,   driven),
-        {TEGRA_PINGROUP_KBCD,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("kbcd",  "kbc",           up,   driven),
-        {TEGRA_PINGROUP_KBCE,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("kbce",  "kbc",           up,   driven),
-        {TEGRA_PINGROUP_KBCF,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("kbcf",  "kbc",           up,   driven),
-        {TEGRA_PINGROUP_LCSN,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("lcsn",  "displaya",      na,   tristate),
-        {TEGRA_PINGROUP_LD0,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("ld0",   "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LD1,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("ld1",   "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LD10,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("ld10",  "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LD11,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("ld11",  "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LD12,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("ld12",  "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LD13,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("ld13",  "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LD14,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("ld14",  "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LD15,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("ld15",  "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LD16,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("ld16",  "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LD17,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("ld17",  "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LD2,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("ld2",   "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LD3,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("ld3",   "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LD4,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("ld4",   "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LD5,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("ld5",   "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LD6,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("ld6",   "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LD7,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("ld7",   "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LD8,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("ld8",   "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LD9,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("ld9",   "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LDC,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("ldc",   "displaya",      na,   tristate),
-        {TEGRA_PINGROUP_LDI,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("ldi",   "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LHP0,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("lhp0",  "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LHP1,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("lhp1",  "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LHP2,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("lhp2",  "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LHS,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("lhs",   "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LM0,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("lm0",   "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LM1,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("lm1",   "displaya",      na,   tristate),
-        {TEGRA_PINGROUP_LPP,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("lpp",   "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LPW0,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("lpw0",  "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LPW1,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("lpw1",  "displaya",      na,   tristate),
-        {TEGRA_PINGROUP_LPW2,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("lpw2",  "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LSC0,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("lsc0",  "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LSC1,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("lsc1",  "displaya",      na,   tristate),
-        {TEGRA_PINGROUP_LSCK,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("lsck",  "displaya",      na,   tristate),
-        {TEGRA_PINGROUP_LSDA,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("lsda",  "displaya",      na,   tristate),
-        {TEGRA_PINGROUP_LSDI,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("lsdi",  "displaya",      na,   tristate),
-        {TEGRA_PINGROUP_LSPI,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("lspi",  "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LVP0,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("lvp0",  "displaya",      na,   tristate),
-        {TEGRA_PINGROUP_LVP1,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("lvp1",  "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LVS,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("lvs",   "displaya",      na,   driven),
-        {TEGRA_PINGROUP_OWC,   TEGRA_MUX_RSVD2,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("owc",   "rsvd2",         na,   tristate),
-        {TEGRA_PINGROUP_PMC,   TEGRA_MUX_PWR_ON,        TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("pmc",   "pwr_on",        na,   driven),
-        {TEGRA_PINGROUP_PTA,   TEGRA_MUX_HDMI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("pta",   "hdmi",          none, driven),
-        {TEGRA_PINGROUP_RM,    TEGRA_MUX_I2C,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("rm",    "i2c1",          none, driven),
-        {TEGRA_PINGROUP_SDB,   TEGRA_MUX_PWM,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("sdb",   "pwm",           na,   tristate),
-        {TEGRA_PINGROUP_SDC,   TEGRA_MUX_PWM,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("sdc",   "pwm",           up,   driven),
-        {TEGRA_PINGROUP_SDD,   TEGRA_MUX_PWM,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("sdd",   "pwm",           up,   tristate),
-        {TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("sdio1", "sdio1",         none, tristate),
-        {TEGRA_PINGROUP_SLXA,  TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("slxa",  "pcie",          none, driven),
-        {TEGRA_PINGROUP_SLXC,  TEGRA_MUX_SPDIF,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("slxc",  "spdif",         none, tristate),
-        {TEGRA_PINGROUP_SLXD,  TEGRA_MUX_SPDIF,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("slxd",  "spdif",         none, tristate),
-        {TEGRA_PINGROUP_SLXK,  TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("slxk",  "pcie",          none, driven),
-        {TEGRA_PINGROUP_SPDI,  TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("spdi",  "rsvd2",         none, tristate),
-        {TEGRA_PINGROUP_SPDO,  TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("spdo",  "rsvd2",         none, tristate),
-        {TEGRA_PINGROUP_SPIA,  TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("spia",  "gmi",           none, driven),
-        {TEGRA_PINGROUP_SPIB,  TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("spib",  "gmi",           none, driven),
-        {TEGRA_PINGROUP_SPIC,  TEGRA_MUX_GMI,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("spic",  "gmi",           up,   tristate),
-        {TEGRA_PINGROUP_SPID,  TEGRA_MUX_SPI1,          TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("spid",  "spi1",          down, tristate),
-        {TEGRA_PINGROUP_SPIE,  TEGRA_MUX_SPI1,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("spie",  "spi1",          up,   tristate),
-        {TEGRA_PINGROUP_SPIF,  TEGRA_MUX_SPI1,          TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("spif",  "spi1",          down, tristate),
-        {TEGRA_PINGROUP_SPIG,  TEGRA_MUX_SPI2_ALT,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("spig",  "spi2_alt",      none, tristate),
-        {TEGRA_PINGROUP_SPIH,  TEGRA_MUX_SPI2_ALT,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("spih",  "spi2_alt",      up,   tristate),
-        {TEGRA_PINGROUP_UAA,   TEGRA_MUX_ULPI,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("uaa",   "ulpi",          up,   tristate),
-        {TEGRA_PINGROUP_UAB,   TEGRA_MUX_ULPI,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("uab",   "ulpi",          up,   tristate),
-        {TEGRA_PINGROUP_UAC,   TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("uac",   "rsvd2",         none, tristate),
-        {TEGRA_PINGROUP_UAD,   TEGRA_MUX_IRDA,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("uad",   "irda",          up,   tristate),
-        {TEGRA_PINGROUP_UCA,   TEGRA_MUX_UARTC,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("uca",   "uartc",         up,   tristate),
-        {TEGRA_PINGROUP_UCB,   TEGRA_MUX_UARTC,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("ucb",   "uartc",         up,   tristate),
-        {TEGRA_PINGROUP_UDA,   TEGRA_MUX_ULPI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("uda",   "ulpi",          none, tristate),
-        {TEGRA_PINGROUP_CK32,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        TEGRA_MAP_CONF("ck32",    none, na),
-        {TEGRA_PINGROUP_DDRC,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        TEGRA_MAP_CONF("ddrc",    none, na),
-        {TEGRA_PINGROUP_PMCA,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        TEGRA_MAP_CONF("pmca",    none, na),
-        {TEGRA_PINGROUP_PMCB,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        TEGRA_MAP_CONF("pmcb",    none, na),
-        {TEGRA_PINGROUP_PMCC,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        TEGRA_MAP_CONF("pmcc",    none, na),
-        {TEGRA_PINGROUP_PMCD,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        TEGRA_MAP_CONF("pmcd",    none, na),
-        {TEGRA_PINGROUP_PMCE,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        TEGRA_MAP_CONF("pmce",    none, na),
-        {TEGRA_PINGROUP_XM2C,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        TEGRA_MAP_CONF("xm2c",    none, na),
-        {TEGRA_PINGROUP_XM2D,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        TEGRA_MAP_CONF("xm2d",    none, na),
-};
+        TEGRA_MAP_CONF("ls",      up,   na),
+        TEGRA_MAP_CONF("lc",      up,   na),
-static struct tegra_gpio_table gpio_table[] = {
+        TEGRA_MAP_CONF("ld17_0",  down, na),
-        { .gpio = TEGRA_GPIO_SD2_CD,            .enable = true  },
+        TEGRA_MAP_CONF("ld19_18", down, na),
-        { .gpio = TEGRA_GPIO_SD2_WP,            .enable = true  },
+        TEGRA_MAP_CONF("ld21_20", down, na),
-        { .gpio = TEGRA_GPIO_SD2_POWER,         .enable = true  },
+        TEGRA_MAP_CONF("ld23_22", down, na),
-        { .gpio = TEGRA_GPIO_SD4_CD,            .enable = true  },
-        { .gpio = TEGRA_GPIO_SD4_WP,            .enable = true  },
-        { .gpio = TEGRA_GPIO_SD4_POWER,         .enable = true  },
-        { .gpio = TEGRA_GPIO_CDC_IRQ,           .enable = true  },
-        { .gpio = TEGRA_GPIO_HP_DET,            .enable = true  },
-        { .gpio = TEGRA_GPIO_INT_MIC_EN,        .enable = true  },
-        { .gpio = TEGRA_GPIO_EXT_MIC_EN,        .enable = true  },
 };
 static struct tegra_board_pinmux_conf conf = {
-        .pgs = harmony_pinmux,
+        .maps = harmony_map,
-        .pg_count = ARRAY_SIZE(harmony_pinmux),
+        .map_count = ARRAY_SIZE(harmony_map),
-        .gpios = gpio_table,
-        .gpio_count = ARRAY_SIZE(gpio_table),
 };
 void harmony_pinmux_init(void)
diff --git a/arch/arm/mach-tegra/board-harmony.c b/arch/arm/mach-tegra/board-harmony.c
index c00aadb01e09..222182e00226 100644
--- a/arch/arm/mach-tegra/board-harmony.c
+++ b/arch/arm/mach-tegra/board-harmony.c
@@ -19,6 +19,7 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/serial_8250.h>
+#include <linux/of_serial.h>
 #include <linux/clk.h>
 #include <linux/dma-mapping.h>
 #include <linux/pda_power.h>
@@ -52,6 +53,7 @@ static struct plat_serial8250_port debug_uart_platform_data[] = {
                .irq            = INT_UARTD,
                .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
                .type           = PORT_TEGRA,
+                .handle_break   = tegra_serial_handle_break,
                .iotype         = UPIO_MEM,
                .regshift       = 2,
                .uartclk        = 216000000,
diff --git a/arch/arm/mach-tegra/board-paz00-pinmux.c b/arch/arm/mach-tegra/board-paz00-pinmux.c
index c775572dcea4..6f1111b48e7c 100644
--- a/arch/arm/mach-tegra/board-paz00-pinmux.c
+++ b/arch/arm/mach-tegra/board-paz00-pinmux.c
@@ -2,6 +2,7 @@
 * arch/arm/mach-tegra/board-paz00-pinmux.c
 *
 * Copyright (C) 2010 Marc Dietrich <marvin24@gmx.de>
+ * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
@@ -15,150 +16,138 @@
 */
 #include <linux/kernel.h>
-#include <linux/gpio.h>
-#include <linux/of.h>
-#include <mach/pinmux.h>
-#include <mach/pinmux-tegra20.h>
-#include "gpio-names.h"
 #include "board-paz00.h"
 #include "board-pinmux.h"
-static struct tegra_pingroup_config paz00_pinmux[] = {
+static struct pinctrl_map paz00_map[] = {
-        {TEGRA_PINGROUP_ATA,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("ata",   "gmi",           none, driven),
-        {TEGRA_PINGROUP_ATB,   TEGRA_MUX_SDIO4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("atb",   "sdio4",         none, driven),
-        {TEGRA_PINGROUP_ATC,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("atc",   "gmi",           none, driven),
-        {TEGRA_PINGROUP_ATD,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("atd",   "gmi",           none, driven),
-        {TEGRA_PINGROUP_ATE,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("ate",   "gmi",           none, driven),
-        {TEGRA_PINGROUP_CDEV1, TEGRA_MUX_PLLA_OUT,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("cdev1", "plla_out",      none, driven),
-        {TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4,     TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("cdev2", "pllp_out4",     down, driven),
-        {TEGRA_PINGROUP_CRTP,  TEGRA_MUX_CRT,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("crtp",  "crt",           none, tristate),
-        {TEGRA_PINGROUP_CSUS,  TEGRA_MUX_PLLC_OUT1,     TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("csus",  "pllc_out1",     down, tristate),
-        {TEGRA_PINGROUP_DAP1,  TEGRA_MUX_DAP1,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("dap1",  "dap1",          none, driven),
-        {TEGRA_PINGROUP_DAP2,  TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("dap2",  "gmi",           none, driven),
-        {TEGRA_PINGROUP_DAP3,  TEGRA_MUX_DAP3,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("dap3",  "dap3",          none, tristate),
-        {TEGRA_PINGROUP_DAP4,  TEGRA_MUX_DAP4,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("dap4",  "dap4",          none, tristate),
-        {TEGRA_PINGROUP_DDC,   TEGRA_MUX_I2C2,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("ddc",   "i2c2",          up,   driven),
-        {TEGRA_PINGROUP_DTA,   TEGRA_MUX_RSVD1,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("dta",   "rsvd1",         up,   tristate),
-        {TEGRA_PINGROUP_DTB,   TEGRA_MUX_RSVD1,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("dtb",   "rsvd1",         none, tristate),
-        {TEGRA_PINGROUP_DTC,   TEGRA_MUX_RSVD1,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("dtc",   "rsvd1",         none, tristate),
-        {TEGRA_PINGROUP_DTD,   TEGRA_MUX_RSVD1,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("dtd",   "rsvd1",         up,   tristate),
-        {TEGRA_PINGROUP_DTE,   TEGRA_MUX_RSVD1,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("dte",   "rsvd1",         none, tristate),
-        {TEGRA_PINGROUP_DTF,   TEGRA_MUX_I2C3,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("dtf",   "i2c3",          none, driven),
-        {TEGRA_PINGROUP_GMA,   TEGRA_MUX_SDIO4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("gma",   "sdio4",         none, driven),
-        {TEGRA_PINGROUP_GMB,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("gmb",   "gmi",           none, driven),
-        {TEGRA_PINGROUP_GMC,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("gmc",   "gmi",           none, driven),
-        {TEGRA_PINGROUP_GMD,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("gmd",   "gmi",           none, driven),
-        {TEGRA_PINGROUP_GME,   TEGRA_MUX_SDIO4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("gme",   "sdio4",         none, driven),
-        {TEGRA_PINGROUP_GPU,   TEGRA_MUX_PWM,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("gpu",   "pwm",           none, driven),
-        {TEGRA_PINGROUP_GPU7,  TEGRA_MUX_RTCK,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("gpu7",  "rtck",          none, driven),
-        {TEGRA_PINGROUP_GPV,   TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("gpv",   "pcie",          none, driven),
-        {TEGRA_PINGROUP_HDINT, TEGRA_MUX_HDMI,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("hdint", "hdmi",          na,   driven),
-        {TEGRA_PINGROUP_I2CP,  TEGRA_MUX_I2C,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("i2cp",  "i2cp",          none, driven),
-        {TEGRA_PINGROUP_IRRX,  TEGRA_MUX_UARTA,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("irrx",  "uarta",         up,   driven),
-        {TEGRA_PINGROUP_IRTX,  TEGRA_MUX_UARTA,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("irtx",  "uarta",         up,   driven),
-        {TEGRA_PINGROUP_KBCA,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("kbca",  "kbc",           up,   driven),
-        {TEGRA_PINGROUP_KBCB,  TEGRA_MUX_SDIO2,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("kbcb",  "sdio2",         up,   driven),
-        {TEGRA_PINGROUP_KBCC,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("kbcc",  "kbc",           up,   driven),
-        {TEGRA_PINGROUP_KBCD,  TEGRA_MUX_SDIO2,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("kbcd",  "sdio2",         up,   driven),
-        {TEGRA_PINGROUP_KBCE,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("kbce",  "kbc",           up,   driven),
-        {TEGRA_PINGROUP_KBCF,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("kbcf",  "kbc",           up,   driven),
-        {TEGRA_PINGROUP_LCSN,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("lcsn",  "displaya",      na,   tristate),
-        {TEGRA_PINGROUP_LD0,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("ld0",   "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LD1,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("ld1",   "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LD10,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("ld10",  "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LD11,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("ld11",  "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LD12,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("ld12",  "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LD13,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("ld13",  "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LD14,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("ld14",  "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LD15,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("ld15",  "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LD16,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("ld16",  "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LD17,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("ld17",  "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LD2,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("ld2",   "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LD3,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("ld3",   "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LD4,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("ld4",   "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LD5,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("ld5",   "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LD6,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("ld6",   "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LD7,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("ld7",   "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LD8,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("ld8",   "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LD9,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("ld9",   "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LDC,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("ldc",   "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LDI,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("ldi",   "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LHP0,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("lhp0",  "displaya",      na,   tristate),
-        {TEGRA_PINGROUP_LHP1,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("lhp1",  "displaya",      na,   tristate),
-        {TEGRA_PINGROUP_LHP2,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("lhp2",  "displaya",      na,   tristate),
-        {TEGRA_PINGROUP_LHS,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("lhs",   "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LM0,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("lm0",   "displaya",      na,   tristate),
-        {TEGRA_PINGROUP_LM1,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("lm1",   "displaya",      na,   tristate),
-        {TEGRA_PINGROUP_LPP,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("lpp",   "displaya",      na,   tristate),
-        {TEGRA_PINGROUP_LPW0,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("lpw0",  "displaya",      na,   tristate),
-        {TEGRA_PINGROUP_LPW1,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("lpw1",  "displaya",      na,   tristate),
-        {TEGRA_PINGROUP_LPW2,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("lpw2",  "displaya",      na,   tristate),
-        {TEGRA_PINGROUP_LSC0,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("lsc0",  "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LSC1,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("lsc1",  "displaya",      na,   tristate),
-        {TEGRA_PINGROUP_LSCK,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("lsck",  "displaya",      na,   tristate),
-        {TEGRA_PINGROUP_LSDA,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("lsda",  "displaya",      na,   tristate),
-        {TEGRA_PINGROUP_LSDI,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("lsdi",  "displaya",      na,   tristate),
-        {TEGRA_PINGROUP_LSPI,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("lspi",  "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LVP0,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("lvp0",  "displaya",      na,   tristate),
-        {TEGRA_PINGROUP_LVP1,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("lvp1",  "displaya",      na,   tristate),
-        {TEGRA_PINGROUP_LVS,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("lvs",   "displaya",      na,   driven),
-        {TEGRA_PINGROUP_OWC,   TEGRA_MUX_OWR,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("owc",   "owr",           up,   tristate),
-        {TEGRA_PINGROUP_PMC,   TEGRA_MUX_PWR_ON,        TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("pmc",   "pwr_on",        na,   driven),
-        {TEGRA_PINGROUP_PTA,   TEGRA_MUX_HDMI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("pta",   "hdmi",          none, driven),
-        {TEGRA_PINGROUP_RM,    TEGRA_MUX_I2C,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("rm",    "i2c1",          none, driven),
-        {TEGRA_PINGROUP_SDB,   TEGRA_MUX_PWM,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("sdb",   "pwm",           na,   tristate),
-        {TEGRA_PINGROUP_SDC,   TEGRA_MUX_TWC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("sdc",   "twc",           up,   tristate),
-        {TEGRA_PINGROUP_SDD,   TEGRA_MUX_PWM,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("sdd",   "pwm",           up,   tristate),
-        {TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("sdio1", "sdio1",         none, driven),
-        {TEGRA_PINGROUP_SLXA,  TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("slxa",  "pcie",          none, tristate),
-        {TEGRA_PINGROUP_SLXC,  TEGRA_MUX_SPI4,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("slxc",  "spi4",          none, tristate),
-        {TEGRA_PINGROUP_SLXD,  TEGRA_MUX_SPI4,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("slxd",  "spi4",          none, tristate),
-        {TEGRA_PINGROUP_SLXK,  TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("slxk",  "pcie",          none, driven),
-        {TEGRA_PINGROUP_SPDI,  TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("spdi",  "rsvd2",         none, tristate),
-        {TEGRA_PINGROUP_SPDO,  TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("spdo",  "rsvd2",         none, driven),
-        {TEGRA_PINGROUP_SPIA,  TEGRA_MUX_GMI,           TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("spia",  "gmi",           down, tristate),
-        {TEGRA_PINGROUP_SPIB,  TEGRA_MUX_GMI,           TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("spib",  "gmi",           down, tristate),
-        {TEGRA_PINGROUP_SPIC,  TEGRA_MUX_GMI,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("spic",  "gmi",           up,   driven),
-        {TEGRA_PINGROUP_SPID,  TEGRA_MUX_GMI,           TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("spid",  "gmi",           down, tristate),
-        {TEGRA_PINGROUP_SPIE,  TEGRA_MUX_GMI,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("spie",  "gmi",           up,   tristate),
-        {TEGRA_PINGROUP_SPIF,  TEGRA_MUX_RSVD4,         TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("spif",  "rsvd4",         down, tristate),
-        {TEGRA_PINGROUP_SPIG,  TEGRA_MUX_SPI2_ALT,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("spig",  "spi2_alt",      up,   driven),
-        {TEGRA_PINGROUP_SPIH,  TEGRA_MUX_SPI2_ALT,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("spih",  "spi2_alt",      up,   tristate),
-        {TEGRA_PINGROUP_UAA,   TEGRA_MUX_ULPI,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("uaa",   "ulpi",          up,   driven),
-        {TEGRA_PINGROUP_UAB,   TEGRA_MUX_ULPI,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("uab",   "ulpi",          up,   driven),
-        {TEGRA_PINGROUP_UAC,   TEGRA_MUX_RSVD4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("uac",   "rsvd4",         none, driven),
-        {TEGRA_PINGROUP_UAD,   TEGRA_MUX_SPDIF,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("uad",   "spdif",         up,   tristate),
-        {TEGRA_PINGROUP_UCA,   TEGRA_MUX_UARTC,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("uca",   "uartc",         up,   tristate),
-        {TEGRA_PINGROUP_UCB,   TEGRA_MUX_UARTC,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("ucb",   "uartc",         up,   tristate),
-        {TEGRA_PINGROUP_UDA,   TEGRA_MUX_ULPI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("uda",   "ulpi",          none, driven),
-        {TEGRA_PINGROUP_CK32,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        TEGRA_MAP_CONF("ck32",    none, na),
-        {TEGRA_PINGROUP_DDRC,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        TEGRA_MAP_CONF("ddrc",    none, na),
-        {TEGRA_PINGROUP_PMCA,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        TEGRA_MAP_CONF("pmca",    none, na),
-        {TEGRA_PINGROUP_PMCB,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        TEGRA_MAP_CONF("pmcb",    none, na),
-        {TEGRA_PINGROUP_PMCC,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        TEGRA_MAP_CONF("pmcc",    none, na),
-        {TEGRA_PINGROUP_PMCD,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        TEGRA_MAP_CONF("pmcd",    none, na),
-        {TEGRA_PINGROUP_PMCE,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        TEGRA_MAP_CONF("pmce",    none, na),
-        {TEGRA_PINGROUP_XM2C,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        TEGRA_MAP_CONF("xm2c",    none, na),
-        {TEGRA_PINGROUP_XM2D,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+        TEGRA_MAP_CONF("xm2d",    none, na),
-};
+        TEGRA_MAP_CONF("ls",      up,   na),
+        TEGRA_MAP_CONF("lc",      up,   na),
-static struct tegra_gpio_table gpio_table[] = {
+        TEGRA_MAP_CONF("ld17_0",  down, na),
-        { .gpio = TEGRA_GPIO_SD1_CD,    .enable = true },
+        TEGRA_MAP_CONF("ld19_18", down, na),
-        { .gpio = TEGRA_GPIO_SD1_WP,    .enable = true },
+        TEGRA_MAP_CONF("ld21_20", down, na),
-        { .gpio = TEGRA_GPIO_SD1_POWER, .enable = true },
+        TEGRA_MAP_CONF("ld23_22", down, na),
-        { .gpio = TEGRA_ULPI_RST,       .enable = true },
-        { .gpio = TEGRA_WIFI_PWRN,      .enable = true },
-        { .gpio = TEGRA_WIFI_RST,       .enable = true },
-        { .gpio = TEGRA_WIFI_LED,       .enable = true },
 };
 static struct tegra_board_pinmux_conf conf = {
-        .pgs = paz00_pinmux,
+        .maps = paz00_map,
-        .pg_count = ARRAY_SIZE(paz00_pinmux),
+        .map_count = ARRAY_SIZE(paz00_map),
-        .gpios = gpio_table,
-        .gpio_count = ARRAY_SIZE(gpio_table),
 };
 void paz00_pinmux_init(void)
diff --git a/arch/arm/mach-tegra/board-paz00.c b/arch/arm/mach-tegra/board-paz00.c
index 330afdfa2475..d0735c70d688 100644
--- a/arch/arm/mach-tegra/board-paz00.c
+++ b/arch/arm/mach-tegra/board-paz00.c
@@ -21,6 +21,7 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/serial_8250.h>
+#include <linux/of_serial.h>
 #include <linux/clk.h>
 #include <linux/dma-mapping.h>
 #include <linux/gpio_keys.h>
@@ -55,6 +56,7 @@ static struct plat_serial8250_port debug_uart_platform_data[] = {
                .irq            = INT_UARTA,
                .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
                .type           = PORT_TEGRA,
+                .handle_break   = tegra_serial_handle_break,
                .iotype         = UPIO_MEM,
                .regshift       = 2,
                .uartclk        = 216000000,
@@ -65,6 +67,7 @@ static struct plat_serial8250_port debug_uart_platform_data[] = {
                .irq            = INT_UARTC,
                .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
                .type           = PORT_TEGRA,
+                .handle_break   = tegra_serial_handle_break,
                .iotype         = UPIO_MEM,
                .regshift       = 2,
                .uartclk        = 216000000,
diff --git a/arch/arm/mach-tegra/board-pinmux.c b/arch/arm/mach-tegra/board-pinmux.c
index adc3efe979b3..a5574c71b931 100644
--- a/arch/arm/mach-tegra/board-pinmux.c
+++ b/arch/arm/mach-tegra/board-pinmux.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2011,2012, NVIDIA CORPORATION.  All rights reserved.
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
@@ -15,75 +15,59 @@
 #include <linux/device.h>
 #include <linux/kernel.h>
 #include <linux/notifier.h>
-#include <linux/of.h>
 #include <linux/string.h>
-#include <mach/gpio-tegra.h>
-#include <mach/pinmux.h>
 #include "board-pinmux.h"
 #include "devices.h"
-struct tegra_board_pinmux_conf *confs[2];
+unsigned long tegra_pincfg_pullnone_driven[2] = {
+        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_NONE),
-static void tegra_board_pinmux_setup_gpios(void)
+        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_DRIVEN),
-{
+};
-        int i;
-        for (i = 0; i < ARRAY_SIZE(confs); i++) {
-                if (!confs[i])
-                        continue;
-                tegra_gpio_config(confs[i]->gpios, confs[i]->gpio_count);
-        }
-}
-static void tegra_board_pinmux_setup_pinmux(void)
-{
-        int i;
-        for (i = 0; i < ARRAY_SIZE(confs); i++) {
+unsigned long tegra_pincfg_pullnone_tristate[2] = {
-                if (!confs[i])
+        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_NONE),
-                        continue;
+        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_TRISTATE),
+};
-                tegra_pinmux_config_table(confs[i]->pgs, confs[i]->pg_count);
+unsigned long tegra_pincfg_pullnone_na[1] = {
+        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_NONE),
+};
-                if (confs[i]->drives)
+unsigned long tegra_pincfg_pullup_driven[2] = {
-                        tegra_drive_pinmux_config_table(confs[i]->drives,
+        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_UP),
-                                                        confs[i]->drive_count);
+        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_DRIVEN),
-        }
+};
-}
-static int tegra_board_pinmux_bus_notify(struct notifier_block *nb,
+unsigned long tegra_pincfg_pullup_tristate[2] = {
-                                         unsigned long event, void *vdev)
+        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_UP),
-{
+        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_TRISTATE),
-        static bool had_gpio;
+};
-        static bool had_pinmux;
-        struct device *dev = vdev;
+unsigned long tegra_pincfg_pullup_na[1] = {
-        const char *devname;
+        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_UP),
+};
-        if (event != BUS_NOTIFY_BOUND_DRIVER)
+unsigned long tegra_pincfg_pulldown_driven[2] = {
-                return NOTIFY_DONE;
+        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_DOWN),
+        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_DRIVEN),
+};
-        devname = dev_name(dev);
+unsigned long tegra_pincfg_pulldown_tristate[2] = {
+        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_DOWN),
+        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_TRISTATE),
+};
-        if (!had_gpio && !strcmp(devname, GPIO_DEV)) {
+unsigned long tegra_pincfg_pulldown_na[1] = {
-                tegra_board_pinmux_setup_gpios();
+        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_PULL, TEGRA_PINCONFIG_PULL_DOWN),
-                had_gpio = true;
+};
-        } else if (!had_pinmux && !strcmp(devname, PINMUX_DEV)) {
-                tegra_board_pinmux_setup_pinmux();
-                had_pinmux = true;
-        }
-        if (had_gpio && had_pinmux)
+unsigned long tegra_pincfg_pullna_driven[1] = {
-                return NOTIFY_STOP_MASK;
+        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_DRIVEN),
-        else
+};
-                return NOTIFY_DONE;
-}
-static struct notifier_block nb = {
+unsigned long tegra_pincfg_pullna_tristate[1] = {
-        .notifier_call = tegra_board_pinmux_bus_notify,
+        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_TRISTATE, TEGRA_PINCONFIG_TRISTATE),
 };
 static struct platform_device *devices[] = {
@@ -94,11 +78,10 @@ static struct platform_device *devices[] = {
 void tegra_board_pinmux_init(struct tegra_board_pinmux_conf *conf_a,
                             struct tegra_board_pinmux_conf *conf_b)
 {
-        confs[0] = conf_a;
+        if (conf_a)
-        confs[1] = conf_b;
+                pinctrl_register_mappings(conf_a->maps, conf_a->map_count);
+        if (conf_b)
-        bus_register_notifier(&platform_bus_type, &nb);
+                pinctrl_register_mappings(conf_b->maps, conf_b->map_count);
-        if (!of_machine_is_compatible("nvidia,tegra20"))
+        platform_add_devices(devices, ARRAY_SIZE(devices));
-                platform_add_devices(devices, ARRAY_SIZE(devices));
 }
diff --git a/arch/arm/mach-tegra/board-pinmux.h b/arch/arm/mach-tegra/board-pinmux.h
index 4aac73546f54..c5f3f3381e86 100644
--- a/arch/arm/mach-tegra/board-pinmux.h
+++ b/arch/arm/mach-tegra/board-pinmux.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2011,2012, NVIDIA CORPORATION.  All rights reserved.
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
@@ -15,21 +15,37 @@
 #ifndef __MACH_TEGRA_BOARD_PINMUX_H
 #define __MACH_TEGRA_BOARD_PINMUX_H
-#define GPIO_DEV "tegra-gpio"
+#include <linux/pinctrl/machine.h>
-#define PINMUX_DEV "tegra-pinmux"
-struct tegra_pingroup_config;
+#include <mach/pinconf-tegra.h>
-struct tegra_gpio_table;
-struct tegra_board_pinmux_conf {
+#define PINMUX_DEV "tegra20-pinctrl"
-        struct tegra_pingroup_config *pgs;
-        int pg_count;
+#define TEGRA_MAP_MUX(_group_, _function_) \
+        PIN_MAP_MUX_GROUP_HOG_DEFAULT(PINMUX_DEV, _group_, _function_)
+#define TEGRA_MAP_CONF(_group_, _pull_, _drive_) \
+        PIN_MAP_CONFIGS_GROUP_HOG_DEFAULT(PINMUX_DEV, _group_, tegra_pincfg_pull##_pull_##_##_drive_)
-        struct tegra_drive_pingroup_config *drives;
+#define TEGRA_MAP_MUXCONF(_group_, _function_, _pull_, _drive_) \
-        int drive_count;
+        TEGRA_MAP_MUX(_group_, _function_), \
+        TEGRA_MAP_CONF(_group_, _pull_, _drive_)
-        struct tegra_gpio_table *gpios;
+extern unsigned long tegra_pincfg_pullnone_driven[2];
-        int gpio_count;
+extern unsigned long tegra_pincfg_pullnone_tristate[2];
+extern unsigned long tegra_pincfg_pullnone_na[1];
+extern unsigned long tegra_pincfg_pullup_driven[2];
+extern unsigned long tegra_pincfg_pullup_tristate[2];
+extern unsigned long tegra_pincfg_pullup_na[1];
+extern unsigned long tegra_pincfg_pulldown_driven[2];
+extern unsigned long tegra_pincfg_pulldown_tristate[2];
+extern unsigned long tegra_pincfg_pulldown_na[1];
+extern unsigned long tegra_pincfg_pullna_driven[1];
+extern unsigned long tegra_pincfg_pullna_tristate[1];
+struct tegra_board_pinmux_conf {
+        struct pinctrl_map *maps;
+        int map_count;
 };
 void tegra_board_pinmux_init(struct tegra_board_pinmux_conf *conf_a,
diff --git a/arch/arm/mach-tegra/board-seaboard-pinmux.c b/arch/arm/mach-tegra/board-seaboard-pinmux.c
index 55e7e43a14ad..11fc8a568c64 100644
--- a/arch/arm/mach-tegra/board-seaboard-pinmux.c
+++ b/arch/arm/mach-tegra/board-seaboard-pinmux.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2010,2011 NVIDIA Corporation
+ * Copyright (C) 2010-2012 NVIDIA Corporation
 * Copyright (C) 2011 Google, Inc.
 *
 * This software is licensed under the terms of the GNU General Public
@@ -14,216 +14,176 @@
 */
 #include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/gpio.h>
-#include <linux/of.h>
-#include <mach/pinmux.h>
-#include <mach/pinmux-tegra20.h>
-#include "gpio-names.h"
-#include "board-pinmux.h"
 #include "board-seaboard.h"
+#include "board-pinmux.h"
-#define DEFAULT_DRIVE(_name)                                    \
+static unsigned long seaboard_pincfg_drive_sdio1[] = {
-        {                                                       \
+        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE, 0),
-                .pingroup = TEGRA_DRIVE_PINGROUP_##_name,       \
+        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_SCHMITT, 0),
-                .hsm = TEGRA_HSM_DISABLE,                       \
+        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_LOW_POWER_MODE, 3),
-                .schmitt = TEGRA_SCHMITT_ENABLE,                \
+        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH, 31),
-                .drive = TEGRA_DRIVE_DIV_1,                     \
+        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH, 31),
-                .pull_down = TEGRA_PULL_31,                     \
+        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING, 3),
-                .pull_up = TEGRA_PULL_31,                       \
+        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_SLEW_RATE_RISING, 3),
-                .slew_rising = TEGRA_SLEW_SLOWEST,              \
-                .slew_falling = TEGRA_SLEW_SLOWEST,             \
-        }
-static struct tegra_drive_pingroup_config seaboard_drive_pinmux[] = {
-        DEFAULT_DRIVE(SDIO1),
-};
-static struct tegra_pingroup_config common_pinmux[] = {
-        {TEGRA_PINGROUP_ATA,   TEGRA_MUX_IDE,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_ATB,   TEGRA_MUX_SDIO4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_ATC,   TEGRA_MUX_NAND,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_ATD,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_ATE,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_CDEV1, TEGRA_MUX_PLLA_OUT,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4,     TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_CRTP,  TEGRA_MUX_CRT,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_CSUS,  TEGRA_MUX_VI_SENSOR_CLK, TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_DAP1,  TEGRA_MUX_DAP1,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_DAP2,  TEGRA_MUX_DAP2,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_DAP3,  TEGRA_MUX_DAP3,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_DAP4,  TEGRA_MUX_DAP4,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_DTA,   TEGRA_MUX_VI,            TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_DTB,   TEGRA_MUX_VI,            TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_DTC,   TEGRA_MUX_VI,            TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_DTD,   TEGRA_MUX_VI,            TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_DTE,   TEGRA_MUX_VI,            TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_DTF,   TEGRA_MUX_I2C3,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_GMA,   TEGRA_MUX_SDIO4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_GMB,   TEGRA_MUX_GMI,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_GMC,   TEGRA_MUX_UARTD,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_GME,   TEGRA_MUX_SDIO4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_GPU,   TEGRA_MUX_PWM,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_GPU7,  TEGRA_MUX_RTCK,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_GPV,   TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_HDINT, TEGRA_MUX_HDMI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_I2CP,  TEGRA_MUX_I2C,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_IRRX,  TEGRA_MUX_UARTB,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_IRTX,  TEGRA_MUX_UARTB,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_KBCA,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_KBCB,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_KBCC,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_KBCD,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_KBCE,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_KBCF,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LCSN,  TEGRA_MUX_RSVD4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_LD0,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD1,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD10,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD11,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD12,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD13,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD14,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD15,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD16,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD17,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD2,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD3,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD4,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD5,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD6,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD7,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD8,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LD9,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LDC,   TEGRA_MUX_RSVD4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_LDI,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LHP0,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LHP1,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LHP2,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LHS,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LM0,   TEGRA_MUX_RSVD4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LM1,   TEGRA_MUX_CRT,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_LPP,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LPW1,  TEGRA_MUX_RSVD4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_LSC0,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LSDI,  TEGRA_MUX_RSVD4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_LSPI,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LVP0,  TEGRA_MUX_RSVD4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_LVP1,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LVS,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_OWC,   TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_PMC,   TEGRA_MUX_PWR_ON,        TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_RM,    TEGRA_MUX_I2C,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_SDB,   TEGRA_MUX_SDIO3,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_SDC,   TEGRA_MUX_SDIO3,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_SDD,   TEGRA_MUX_SDIO3,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_SLXA,  TEGRA_MUX_PCIE,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_SLXD,  TEGRA_MUX_SPDIF,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_SPDI,  TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_SPDO,  TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_SPIB,  TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_SPID,  TEGRA_MUX_SPI1,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_SPIE,  TEGRA_MUX_SPI1,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_SPIF,  TEGRA_MUX_SPI1,          TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_SPIH,  TEGRA_MUX_SPI2_ALT,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_UAA,   TEGRA_MUX_ULPI,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_UAB,   TEGRA_MUX_ULPI,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_UAC,   TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_UAD,   TEGRA_MUX_IRDA,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_UCA,   TEGRA_MUX_UARTC,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_UCB,   TEGRA_MUX_UARTC,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_UDA,   TEGRA_MUX_ULPI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_CK32,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_DDRC,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_PMCA,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_PMCB,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_PMCC,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_PMCD,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_PMCE,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_XM2C,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_XM2D,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-};
-static struct tegra_pingroup_config seaboard_pinmux[] = {
-        {TEGRA_PINGROUP_DDC,   TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_GMD,   TEGRA_MUX_SFLASH,        TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LPW0,  TEGRA_MUX_HDMI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LPW2,  TEGRA_MUX_HDMI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LSC1,  TEGRA_MUX_HDMI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_LSCK,  TEGRA_MUX_HDMI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_LSDA,  TEGRA_MUX_HDMI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_PTA,   TEGRA_MUX_HDMI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_SLXC,  TEGRA_MUX_SPDIF,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_SLXK,  TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_SPIA,  TEGRA_MUX_GMI,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_SPIC,  TEGRA_MUX_GMI,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_SPIG,  TEGRA_MUX_SPI2_ALT,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-};
-static struct tegra_pingroup_config ventana_pinmux[] = {
-        {TEGRA_PINGROUP_DDC,  TEGRA_MUX_RSVD2,    TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_GMD,  TEGRA_MUX_SFLASH,   TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_LPW0, TEGRA_MUX_RSVD4,    TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LPW2, TEGRA_MUX_RSVD4,    TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LSC1, TEGRA_MUX_RSVD4,    TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_LSCK, TEGRA_MUX_RSVD4,    TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_LSDA, TEGRA_MUX_RSVD4,    TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_PTA,  TEGRA_MUX_RSVD2,    TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_SLXC, TEGRA_MUX_SDIO3,    TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_SLXK, TEGRA_MUX_SDIO3,    TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-        {TEGRA_PINGROUP_SPIA, TEGRA_MUX_GMI,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_SPIC, TEGRA_MUX_GMI,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-        {TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
 };
-static struct tegra_gpio_table common_gpio_table[] = {
+static struct pinctrl_map common_map[] = {
-        { .gpio = TEGRA_GPIO_SD2_CD,            .enable = true },
+        TEGRA_MAP_MUXCONF("ata",   "ide",           none, driven),
-        { .gpio = TEGRA_GPIO_SD2_WP,            .enable = true },
+        TEGRA_MAP_MUXCONF("atb",   "sdio4",         none, driven),
-        { .gpio = TEGRA_GPIO_SD2_POWER,         .enable = true },
+        TEGRA_MAP_MUXCONF("atc",   "nand",          none, driven),
-        { .gpio = TEGRA_GPIO_CDC_IRQ,           .enable = true },
+        TEGRA_MAP_MUXCONF("atd",   "gmi",           none, driven),
+        TEGRA_MAP_MUXCONF("ate",   "gmi",           none, tristate),
+        TEGRA_MAP_MUXCONF("cdev1", "plla_out",      none, driven),
+        TEGRA_MAP_MUXCONF("cdev2", "pllp_out4",     none, driven),
+        TEGRA_MAP_MUXCONF("crtp",  "crt",           up,   tristate),
+        TEGRA_MAP_MUXCONF("csus",  "vi_sensor_clk", none, tristate),
+        TEGRA_MAP_MUXCONF("dap1",  "dap1",          none, driven),
+        TEGRA_MAP_MUXCONF("dap2",  "dap2",          none, driven),
+        TEGRA_MAP_MUXCONF("dap3",  "dap3",          none, tristate),
+        TEGRA_MAP_MUXCONF("dap4",  "dap4",          none, driven),
+        TEGRA_MAP_MUXCONF("dta",   "vi",            down, driven),
+        TEGRA_MAP_MUXCONF("dtb",   "vi",            down, driven),
+        TEGRA_MAP_MUXCONF("dtc",   "vi",            down, driven),
+        TEGRA_MAP_MUXCONF("dtd",   "vi",            down, driven),
+        TEGRA_MAP_MUXCONF("dte",   "vi",            down, tristate),
+        TEGRA_MAP_MUXCONF("dtf",   "i2c3",          none, driven),
+        TEGRA_MAP_MUXCONF("gma",   "sdio4",         none, driven),
+        TEGRA_MAP_MUXCONF("gmb",   "gmi",           up,   tristate),
+        TEGRA_MAP_MUXCONF("gmc",   "uartd",         none, driven),
+        TEGRA_MAP_MUXCONF("gme",   "sdio4",         none, driven),
+        TEGRA_MAP_MUXCONF("gpu",   "pwm",           none, driven),
+        TEGRA_MAP_MUXCONF("gpu7",  "rtck",          none, driven),
+        TEGRA_MAP_MUXCONF("gpv",   "pcie",          none, tristate),
+        TEGRA_MAP_MUXCONF("hdint", "hdmi",          na,   tristate),
+        TEGRA_MAP_MUXCONF("i2cp",  "i2cp",          none, driven),
+        TEGRA_MAP_MUXCONF("irrx",  "uartb",         none, driven),
+        TEGRA_MAP_MUXCONF("irtx",  "uartb",         none, driven),
+        TEGRA_MAP_MUXCONF("kbca",  "kbc",           up,   driven),
+        TEGRA_MAP_MUXCONF("kbcb",  "kbc",           up,   driven),
+        TEGRA_MAP_MUXCONF("kbcc",  "kbc",           up,   driven),
+        TEGRA_MAP_MUXCONF("kbcd",  "kbc",           up,   driven),
+        TEGRA_MAP_MUXCONF("kbce",  "kbc",           up,   driven),
+        TEGRA_MAP_MUXCONF("kbcf",  "kbc",           up,   driven),
+        TEGRA_MAP_MUXCONF("lcsn",  "rsvd4",         na,   tristate),
+        TEGRA_MAP_MUXCONF("ld0",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld1",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld10",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld11",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld12",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld13",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld14",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld15",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld16",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld17",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld2",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld3",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld4",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld5",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld6",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld7",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld8",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ld9",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("ldc",   "rsvd4",         na,   tristate),
+        TEGRA_MAP_MUXCONF("ldi",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("lhp0",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("lhp1",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("lhp2",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("lhs",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("lm0",   "rsvd4",         na,   driven),
+        TEGRA_MAP_MUXCONF("lm1",   "crt",           na,   tristate),
+        TEGRA_MAP_MUXCONF("lpp",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("lpw1",  "rsvd4",         na,   tristate),
+        TEGRA_MAP_MUXCONF("lsc0",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("lsdi",  "rsvd4",         na,   tristate),
+        TEGRA_MAP_MUXCONF("lspi",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("lvp0",  "rsvd4",         na,   tristate),
+        TEGRA_MAP_MUXCONF("lvp1",  "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("lvs",   "displaya",      na,   driven),
+        TEGRA_MAP_MUXCONF("owc",   "rsvd2",         none, tristate),
+        TEGRA_MAP_MUXCONF("pmc",   "pwr_on",        na,   driven),
+        TEGRA_MAP_MUXCONF("pta",   "hdmi",          none, driven),
+        TEGRA_MAP_MUXCONF("rm",    "i2c1",          none, driven),
+        TEGRA_MAP_MUXCONF("sdb",   "sdio3",         na,   driven),
+        TEGRA_MAP_MUXCONF("sdc",   "sdio3",         none, driven),
+        TEGRA_MAP_MUXCONF("sdd",   "sdio3",         none, driven),
+        TEGRA_MAP_MUXCONF("sdio1", "sdio1",         up,   driven),
+        TEGRA_MAP_MUXCONF("slxa",  "pcie",          up,   tristate),
+        TEGRA_MAP_MUXCONF("slxd",  "spdif",         none, driven),
+        TEGRA_MAP_MUXCONF("slxk",  "pcie",          none, driven),
+        TEGRA_MAP_MUXCONF("spdi",  "rsvd2",         none, driven),
+        TEGRA_MAP_MUXCONF("spdo",  "rsvd2",         none, driven),
+        TEGRA_MAP_MUXCONF("spib",  "gmi",           none, tristate),
+        TEGRA_MAP_MUXCONF("spid",  "spi1",          none, tristate),
+        TEGRA_MAP_MUXCONF("spie",  "spi1",          none, tristate),
+        TEGRA_MAP_MUXCONF("spif",  "spi1",          down, tristate),
+        TEGRA_MAP_MUXCONF("spih",  "spi2_alt",      up,   tristate),
+        TEGRA_MAP_MUXCONF("uaa",   "ulpi",          up,   driven),
+        TEGRA_MAP_MUXCONF("uab",   "ulpi",          up,   driven),
+        TEGRA_MAP_MUXCONF("uac",   "rsvd2",         none, driven),
+        TEGRA_MAP_MUXCONF("uad",   "irda",          none, driven),
+        TEGRA_MAP_MUXCONF("uca",   "uartc",         none, driven),
+        TEGRA_MAP_MUXCONF("ucb",   "uartc",         none, driven),
+        TEGRA_MAP_MUXCONF("uda",   "ulpi",          none, driven),
+        TEGRA_MAP_CONF("ck32",    none, na),
+        TEGRA_MAP_CONF("ddrc",    none, na),
+        TEGRA_MAP_CONF("pmca",    none, na),
+        TEGRA_MAP_CONF("pmcb",    none, na),
+        TEGRA_MAP_CONF("pmcc",    none, na),
+        TEGRA_MAP_CONF("pmcd",    none, na),
+        TEGRA_MAP_CONF("pmce",    none, na),
+        TEGRA_MAP_CONF("xm2c",    none, na),
+        TEGRA_MAP_CONF("xm2d",    none, na),
+        TEGRA_MAP_CONF("ls",      up,   na),
+        TEGRA_MAP_CONF("lc",      up,   na),
+        TEGRA_MAP_CONF("ld17_0",  down, na),
+        TEGRA_MAP_CONF("ld19_18", down, na),
+        TEGRA_MAP_CONF("ld21_20", down, na),
+        TEGRA_MAP_CONF("ld23_22", down, na),
 };
-static struct tegra_gpio_table seaboard_gpio_table[] = {
+static struct pinctrl_map seaboard_map[] = {
-        { .gpio = TEGRA_GPIO_LIDSWITCH,         .enable = true },
+        TEGRA_MAP_MUXCONF("ddc",   "rsvd2",         none, tristate),
-        { .gpio = TEGRA_GPIO_POWERKEY,          .enable = true },
+        TEGRA_MAP_MUXCONF("gmd",   "sflash",        none, driven),
-        { .gpio = TEGRA_GPIO_HP_DET,            .enable = true },
+        TEGRA_MAP_MUXCONF("lpw0",  "hdmi",          na,   driven),
-        { .gpio = TEGRA_GPIO_ISL29018_IRQ,      .enable = true },
+        TEGRA_MAP_MUXCONF("lpw2",  "hdmi",          na,   driven),
-        { .gpio = TEGRA_GPIO_USB1,              .enable = true },
+        TEGRA_MAP_MUXCONF("lsc1",  "hdmi",          na,   tristate),
+        TEGRA_MAP_MUXCONF("lsck",  "hdmi",          na,   tristate),
+        TEGRA_MAP_MUXCONF("lsda",  "hdmi",          na,   tristate),
+        TEGRA_MAP_MUXCONF("slxc",  "spdif",         none, tristate),
+        TEGRA_MAP_MUXCONF("spia",  "gmi",           up,   tristate),
+        TEGRA_MAP_MUXCONF("spic",  "gmi",           up,   driven),
+        TEGRA_MAP_MUXCONF("spig",  "spi2_alt",      up,   tristate),
+        PIN_MAP_CONFIGS_GROUP_HOG_DEFAULT(PINMUX_DEV, "drive_sdio1", seaboard_pincfg_drive_sdio1),
 };
-static struct tegra_gpio_table ventana_gpio_table[] = {
+static struct pinctrl_map ventana_map[] = {
-        /* hp_det */
+        TEGRA_MAP_MUXCONF("ddc",   "rsvd2",         none, driven),
-        { .gpio = TEGRA_GPIO_PW2,               .enable = true },
+        TEGRA_MAP_MUXCONF("gmd",   "sflash",        none, tristate),
-        /* int_mic_en */
+        TEGRA_MAP_MUXCONF("lpw0",  "displaya",      na,   driven),
-        { .gpio = TEGRA_GPIO_PX0,               .enable = true },
+        TEGRA_MAP_MUXCONF("lpw2",  "displaya",      na,   driven),
-        /* ext_mic_en */
+        TEGRA_MAP_MUXCONF("lsc1",  "displaya",      na,   driven),
-        { .gpio = TEGRA_GPIO_PX1,               .enable = true },
+        TEGRA_MAP_MUXCONF("lsck",  "displaya",      na,   tristate),
+        TEGRA_MAP_MUXCONF("lsda",  "displaya",      na,   tristate),
+        TEGRA_MAP_MUXCONF("slxc",  "sdio3",         none, driven),
+        TEGRA_MAP_MUXCONF("spia",  "gmi",           none, tristate),
+        TEGRA_MAP_MUXCONF("spic",  "gmi",           none, tristate),
+        TEGRA_MAP_MUXCONF("spig",  "spi2_alt",      none, tristate),
 };
 static struct tegra_board_pinmux_conf common_conf = {
-        .pgs = common_pinmux,
+        .maps = common_map,
-        .pg_count = ARRAY_SIZE(common_pinmux),
+        .map_count = ARRAY_SIZE(common_map),
-        .gpios = common_gpio_table,
-        .gpio_count = ARRAY_SIZE(common_gpio_table),
 };
 static struct tegra_board_pinmux_conf seaboard_conf = {
-        .pgs = seaboard_pinmux,
+        .maps = seaboard_map,
-        .pg_count = ARRAY_SIZE(seaboard_pinmux),
+        .map_count = ARRAY_SIZE(seaboard_map),
-        .drives = seaboard_drive_pinmux,
-        .drive_count = ARRAY_SIZE(seaboard_drive_pinmux),
-        .gpios = seaboard_gpio_table,
-        .gpio_count = ARRAY_SIZE(seaboard_gpio_table),
 };
 static struct tegra_board_pinmux_conf ventana_conf = {
-        .pgs = ventana_pinmux,
+        .maps = ventana_map,
-        .pg_count = ARRAY_SIZE(ventana_pinmux),
+        .map_count = ARRAY_SIZE(ventana_map),
-        .gpios = ventana_gpio_table,
-        .gpio_count = ARRAY_SIZE(ventana_gpio_table),
 };
 void seaboard_pinmux_init(void)
diff --git a/arch/arm/mach-tegra/board-seaboard.c b/arch/arm/mach-tegra/board-seaboard.c
index d669847f0485..20743bcec03a 100644
--- a/arch/arm/mach-tegra/board-seaboard.c
+++ b/arch/arm/mach-tegra/board-seaboard.c
@@ -18,12 +18,14 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/serial_8250.h>
+#include <linux/of_serial.h>
 #include <linux/i2c.h>
 #include <linux/delay.h>
 #include <linux/input.h>
 #include <linux/io.h>
 #include <linux/gpio.h>
 #include <linux/gpio_keys.h>
+#include <linux/platform_data/tegra_usb.h>
 #include <sound/wm8903.h>
@@ -47,6 +49,7 @@ static struct plat_serial8250_port debug_uart_platform_data[] = {
                /* Memory and IRQ filled in before registration */
                .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
                .type           = PORT_TEGRA,
+                .handle_break   = tegra_serial_handle_break,
                .iotype         = UPIO_MEM,
                .regshift       = 2,
                .uartclk        = 216000000,
@@ -186,20 +189,10 @@ static struct i2c_board_info __initdata wm8903_device = {
 static int seaboard_ehci_init(void)
 {
-        int gpio_status;
+        struct tegra_ehci_platform_data *pdata;
-        gpio_status = gpio_request(TEGRA_GPIO_USB1, "VBUS_USB1");
+        pdata = tegra_ehci1_device.dev.platform_data;
-        if (gpio_status < 0) {
+        pdata->vbus_gpio = TEGRA_GPIO_USB1;
-                pr_err("VBUS_USB1 request GPIO FAILED\n");
-                WARN_ON(1);
-        }
-        gpio_status = gpio_direction_output(TEGRA_GPIO_USB1, 1);
-        if (gpio_status < 0) {
-                pr_err("VBUS_USB1 request GPIO DIRECTION FAILED\n");
-                WARN_ON(1);
-        }
-        gpio_set_value(TEGRA_GPIO_USB1, 1);
        platform_device_register(&tegra_ehci1_device);
        platform_device_register(&tegra_ehci3_device);
@@ -209,9 +202,6 @@ static int seaboard_ehci_init(void)
 static void __init seaboard_i2c_init(void)
 {
-        gpio_request(TEGRA_GPIO_ISL29018_IRQ, "isl29018");
-        gpio_direction_input(TEGRA_GPIO_ISL29018_IRQ);
        isl29018_device.irq = gpio_to_irq(TEGRA_GPIO_ISL29018_IRQ);
        i2c_register_board_info(0, &isl29018_device, 1);
@@ -261,7 +251,6 @@ static void __init tegra_kaen_init(void)
        debug_uart_platform_data[0].irq = INT_UARTB;
        seaboard_audio_pdata.gpio_hp_mute = TEGRA_GPIO_KAEN_HP_MUTE;
-        tegra_gpio_enable(TEGRA_GPIO_KAEN_HP_MUTE);
        seaboard_common_init();
diff --git a/arch/arm/mach-tegra/board-trimslice-pinmux.c b/arch/arm/mach-tegra/board-trimslice-pinmux.c
index a21a2be57cb6..7b39511c0d4d 100644
--- a/arch/arm/mach-tegra/board-trimslice-pinmux.c
+++ b/arch/arm/mach-tegra/board-trimslice-pinmux.c
@@ -2,6 +2,7 @@
 * arch/arm/mach-tegra/board-trimslice-pinmux.c
 *
 * Copyright (C) 2011 CompuLab, Ltd.
+ * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
@@ -13,150 +14,139 @@
 * GNU General Public License for more details.
 *
 */
-#include <linux/gpio.h>
 #include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/of.h>
-#include <mach/pinmux.h>
-#include <mach/pinmux-tegra20.h>
-#include "gpio-names.h"
-#include "board-pinmux.h"
 #include "board-trimslice.h"
+#include "board-pinmux.h"
-static struct tegra_pingroup_config trimslice_pinmux[] = {
+static struct pinctrl_map trimslice_map[] = {
-        {TEGRA_PINGROUP_ATA,   TEGRA_MUX_IDE,           TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("ata",   "ide",           none, tristate),
-        {TEGRA_PINGROUP_ATB,   TEGRA_MUX_SDIO4,         TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("atb",   "sdio4",         none, driven),
-        {TEGRA_PINGROUP_ATC,   TEGRA_MUX_NAND,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("atc",   "nand",          none, tristate),
-        {TEGRA_PINGROUP_ATD,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("atd",   "gmi",           none, tristate),
-        {TEGRA_PINGROUP_ATE,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("ate",   "gmi",           none, tristate),
-        {TEGRA_PINGROUP_CDEV1, TEGRA_MUX_PLLA_OUT,      TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("cdev1", "plla_out",      none, driven),
-        {TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4,     TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("cdev2", "pllp_out4",     down, tristate),
-        {TEGRA_PINGROUP_CRTP,  TEGRA_MUX_CRT,           TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("crtp",  "crt",           none, tristate),
-        {TEGRA_PINGROUP_CSUS,  TEGRA_MUX_VI_SENSOR_CLK, TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("csus",  "vi_sensor_clk", down, tristate),
-        {TEGRA_PINGROUP_DAP1,  TEGRA_MUX_DAP1,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("dap1",  "dap1",          none, driven),
-        {TEGRA_PINGROUP_DAP2,  TEGRA_MUX_DAP2,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("dap2",  "dap2",          none, tristate),
-        {TEGRA_PINGROUP_DAP3,  TEGRA_MUX_DAP3,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("dap3",  "dap3",          none, tristate),
-        {TEGRA_PINGROUP_DAP4,  TEGRA_MUX_DAP4,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("dap4",  "dap4",          none, tristate),
-        {TEGRA_PINGROUP_DDC,   TEGRA_MUX_I2C2,          TEGRA_PUPD_PULL_UP,     TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("ddc",   "i2c2",          up,   driven),
-        {TEGRA_PINGROUP_DTA,   TEGRA_MUX_VI,            TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("dta",   "vi",            none, tristate),
-        {TEGRA_PINGROUP_DTB,   TEGRA_MUX_VI,            TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("dtb",   "vi",            none, tristate),
-        {TEGRA_PINGROUP_DTC,   TEGRA_MUX_VI,            TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("dtc",   "vi",            none, tristate),
-        {TEGRA_PINGROUP_DTD,   TEGRA_MUX_VI,            TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("dtd",   "vi",            none, tristate),
-        {TEGRA_PINGROUP_DTE,   TEGRA_MUX_VI,            TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("dte",   "vi",            none, tristate),
-        {TEGRA_PINGROUP_DTF,   TEGRA_MUX_I2C3,          TEGRA_PUPD_PULL_UP,     TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("dtf",   "i2c3",          up,   driven),
-        {TEGRA_PINGROUP_GMA,   TEGRA_MUX_SDIO4,         TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("gma",   "sdio4",         none, driven),
-        {TEGRA_PINGROUP_GMB,   TEGRA_MUX_NAND,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("gmb",   "nand",          none, tristate),
-        {TEGRA_PINGROUP_GMC,   TEGRA_MUX_SFLASH,        TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("gmc",   "sflash",        none, driven),
-        {TEGRA_PINGROUP_GMD,   TEGRA_MUX_SFLASH,        TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("gmd",   "sflash",        none, driven),
-        {TEGRA_PINGROUP_GME,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("gme",   "gmi",           none, tristate),
-        {TEGRA_PINGROUP_GPU,   TEGRA_MUX_UARTA,         TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("gpu",   "uarta",         none, driven),
-        {TEGRA_PINGROUP_GPU7,  TEGRA_MUX_RTCK,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("gpu7",  "rtck",          none, driven),
-        {TEGRA_PINGROUP_GPV,   TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("gpv",   "pcie",          none, driven),
-        {TEGRA_PINGROUP_HDINT, TEGRA_MUX_HDMI,          TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("hdint", "hdmi",          na,   tristate),
-        {TEGRA_PINGROUP_I2CP,  TEGRA_MUX_I2C,           TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("i2cp",  "i2cp",          none, tristate),
-        {TEGRA_PINGROUP_IRRX,  TEGRA_MUX_UARTB,         TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("irrx",  "uartb",         up,   tristate),
-        {TEGRA_PINGROUP_IRTX,  TEGRA_MUX_UARTB,         TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("irtx",  "uartb",         up,   tristate),
-        {TEGRA_PINGROUP_KBCA,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("kbca",  "kbc",           up,   tristate),
-        {TEGRA_PINGROUP_KBCB,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("kbcb",  "kbc",           up,   tristate),
-        {TEGRA_PINGROUP_KBCC,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("kbcc",  "kbc",           up,   tristate),
-        {TEGRA_PINGROUP_KBCD,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("kbcd",  "kbc",           up,   tristate),
-        {TEGRA_PINGROUP_KBCE,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("kbce",  "kbc",           up,   tristate),
-        {TEGRA_PINGROUP_KBCF,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("kbcf",  "kbc",           up,   tristate),
-        {TEGRA_PINGROUP_LCSN,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("lcsn",  "displaya",      na,   tristate),
-        {TEGRA_PINGROUP_LD0,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("ld0",   "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LD1,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("ld1",   "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LD2,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("ld10",  "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LD3,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("ld11",  "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LD4,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("ld12",  "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LD5,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("ld13",  "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LD6,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("ld14",  "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LD7,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("ld15",  "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LD8,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("ld16",  "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LD9,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("ld17",  "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LD10,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("ld2",   "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LD11,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("ld3",   "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LD12,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("ld4",   "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LD13,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("ld5",   "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LD14,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("ld6",   "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LD15,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("ld7",   "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LD16,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("ld8",   "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LD17,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("ld9",   "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LDC,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("ldc",   "displaya",      na,   tristate),
-        {TEGRA_PINGROUP_LDI,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("ldi",   "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LHP0,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("lhp0",  "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LHP1,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("lhp1",  "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LHP2,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("lhp2",  "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LHS,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,     TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("lhs",   "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LM0,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,     TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("lm0",   "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LM1,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("lm1",   "displaya",      na,   tristate),
-        {TEGRA_PINGROUP_LPP,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("lpp",   "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LPW0,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,     TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("lpw0",  "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LPW1,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("lpw1",  "displaya",      na,   tristate),
-        {TEGRA_PINGROUP_LPW2,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,     TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("lpw2",  "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LSC0,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,     TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("lsc0",  "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LSC1,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("lsc1",  "displaya",      na,   tristate),
-        {TEGRA_PINGROUP_LSCK,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("lsck",  "displaya",      na,   tristate),
-        {TEGRA_PINGROUP_LSDA,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("lsda",  "displaya",      na,   tristate),
-        {TEGRA_PINGROUP_LSDI,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("lsdi",  "displaya",      na,   tristate),
-        {TEGRA_PINGROUP_LSPI,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,     TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("lspi",  "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LVP0,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("lvp0",  "displaya",      na,   tristate),
-        {TEGRA_PINGROUP_LVP1,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("lvp1",  "displaya",      na,   driven),
-        {TEGRA_PINGROUP_LVS,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,     TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("lvs",   "displaya",      na,   driven),
-        {TEGRA_PINGROUP_OWC,   TEGRA_MUX_RSVD2,         TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("owc",   "rsvd2",         up,   tristate),
-        {TEGRA_PINGROUP_PMC,   TEGRA_MUX_PWR_ON,        TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("pmc",   "pwr_on",        na,   tristate),
-        {TEGRA_PINGROUP_PTA,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("pta",   "gmi",           none, tristate),
-        {TEGRA_PINGROUP_RM,    TEGRA_MUX_I2C,           TEGRA_PUPD_PULL_UP,     TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("rm",    "i2c1",          up,   driven),
-        {TEGRA_PINGROUP_SDB,   TEGRA_MUX_PWM,           TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("sdb",   "pwm",           na,   driven),
-        {TEGRA_PINGROUP_SDC,   TEGRA_MUX_PWM,           TEGRA_PUPD_PULL_UP,     TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("sdc",   "pwm",           up,   driven),
-        {TEGRA_PINGROUP_SDD,   TEGRA_MUX_PWM,           TEGRA_PUPD_PULL_UP,     TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("sdd",   "pwm",           up,   driven),
-        {TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1,         TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("sdio1", "sdio1",         none, driven),
-        {TEGRA_PINGROUP_SLXA,  TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("slxa",  "pcie",          none, driven),
-        {TEGRA_PINGROUP_SLXC,  TEGRA_MUX_SDIO3,         TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("slxc",  "sdio3",         none, tristate),
-        {TEGRA_PINGROUP_SLXD,  TEGRA_MUX_SDIO3,         TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("slxd",  "sdio3",         none, tristate),
-        {TEGRA_PINGROUP_SLXK,  TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("slxk",  "pcie",          none, driven),
-        {TEGRA_PINGROUP_SPDI,  TEGRA_MUX_SPDIF,         TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("spdi",  "spdif",         none, tristate),
-        {TEGRA_PINGROUP_SPDO,  TEGRA_MUX_SPDIF,         TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("spdo",  "spdif",         none, tristate),
-        {TEGRA_PINGROUP_SPIA,  TEGRA_MUX_SPI2,          TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("spia",  "spi2",          down, tristate),
-        {TEGRA_PINGROUP_SPIB,  TEGRA_MUX_SPI2,          TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("spib",  "spi2",          down, tristate),
-        {TEGRA_PINGROUP_SPIC,  TEGRA_MUX_SPI2,          TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("spic",  "spi2",          up,   tristate),
-        {TEGRA_PINGROUP_SPID,  TEGRA_MUX_SPI1,          TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("spid",  "spi1",          down, tristate),
-        {TEGRA_PINGROUP_SPIE,  TEGRA_MUX_SPI1,          TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("spie",  "spi1",          up,   tristate),
-        {TEGRA_PINGROUP_SPIF,  TEGRA_MUX_SPI1,          TEGRA_PUPD_PULL_DOWN,   TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("spif",  "spi1",          down, tristate),
-        {TEGRA_PINGROUP_SPIG,  TEGRA_MUX_SPI2_ALT,      TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("spig",  "spi2_alt",      up,   tristate),
-        {TEGRA_PINGROUP_SPIH,  TEGRA_MUX_SPI2_ALT,      TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("spih",  "spi2_alt",      up,   tristate),
-        {TEGRA_PINGROUP_UAA,   TEGRA_MUX_ULPI,          TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("uaa",   "ulpi",          up,   tristate),
-        {TEGRA_PINGROUP_UAB,   TEGRA_MUX_ULPI,          TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("uab",   "ulpi",          up,   tristate),
-        {TEGRA_PINGROUP_UAC,   TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
+        TEGRA_MAP_MUXCONF("uac",   "rsvd2",         none, driven),
-        {TEGRA_PINGROUP_UAD,   TEGRA_MUX_IRDA,          TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("uad",   "irda",          up,   tristate),
-        {TEGRA_PINGROUP_UCA,   TEGRA_MUX_UARTC,         TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("uca",   "uartc",         up,   tristate),
-        {TEGRA_PINGROUP_UCB,   TEGRA_MUX_UARTC,         TEGRA_PUPD_PULL_UP,     TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("ucb",   "uartc",         up,   tristate),
-        {TEGRA_PINGROUP_UDA,   TEGRA_MUX_ULPI,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_TRISTATE},
+        TEGRA_MAP_MUXCONF("uda",   "ulpi",          none, tristate),
-        {TEGRA_PINGROUP_CK32,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
+        TEGRA_MAP_CONF("ck32",    none, na),
-        {TEGRA_PINGROUP_DDRC,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
+        TEGRA_MAP_CONF("ddrc",    none, na),
-        {TEGRA_PINGROUP_PMCA,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
+        TEGRA_MAP_CONF("pmca",    none, na),
-        {TEGRA_PINGROUP_PMCB,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
+        TEGRA_MAP_CONF("pmcb",    none, na),
-        {TEGRA_PINGROUP_PMCC,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
+        TEGRA_MAP_CONF("pmcc",    none, na),
-        {TEGRA_PINGROUP_PMCD,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
+        TEGRA_MAP_CONF("pmcd",    none, na),
-        {TEGRA_PINGROUP_PMCE,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
+        TEGRA_MAP_CONF("pmce",    none, na),
-        {TEGRA_PINGROUP_XM2C,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
+        TEGRA_MAP_CONF("xm2c",    none, na),
-        {TEGRA_PINGROUP_XM2D,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,      TEGRA_TRI_NORMAL},
+        TEGRA_MAP_CONF("xm2d",    none, na),
-};
+        TEGRA_MAP_CONF("ls",      up,   na),
+        TEGRA_MAP_CONF("lc",      up,   na),
-static struct tegra_gpio_table gpio_table[] = {
+        TEGRA_MAP_CONF("ld17_0",  down, na),
-        { .gpio = TRIMSLICE_GPIO_SD4_CD, .enable = true }, /* mmc4 cd */
+        TEGRA_MAP_CONF("ld19_18", down, na),
-        { .gpio = TRIMSLICE_GPIO_SD4_WP, .enable = true }, /* mmc4 wp */
+        TEGRA_MAP_CONF("ld21_20", down, na),
+        TEGRA_MAP_CONF("ld23_22", down, na),
-        { .gpio = TRIMSLICE_GPIO_USB1_MODE, .enable = true }, /* USB1 mode */
-        { .gpio = TRIMSLICE_GPIO_USB2_RST,  .enable = true }, /* USB2 PHY rst */
 };
 static struct tegra_board_pinmux_conf conf = {
-        .pgs = trimslice_pinmux,
+        .maps = trimslice_map,
-        .pg_count = ARRAY_SIZE(trimslice_pinmux),
+        .map_count = ARRAY_SIZE(trimslice_map),
-        .gpios = gpio_table,
-        .gpio_count = ARRAY_SIZE(gpio_table),
 };
 void trimslice_pinmux_init(void)
diff --git a/arch/arm/mach-tegra/board-trimslice.c b/arch/arm/mach-tegra/board-trimslice.c
index cd52820a3e37..0a00183feeec 100644
--- a/arch/arm/mach-tegra/board-trimslice.c
+++ b/arch/arm/mach-tegra/board-trimslice.c
@@ -22,9 +22,11 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/serial_8250.h>
+#include <linux/of_serial.h>
 #include <linux/io.h>
 #include <linux/i2c.h>
 #include <linux/gpio.h>
+#include <linux/platform_data/tegra_usb.h>
 #include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
@@ -48,6 +50,7 @@ static struct plat_serial8250_port debug_uart_platform_data[] = {
                .irq            = INT_UARTA,
                .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
                .type           = PORT_TEGRA,
+                .handle_break   = tegra_serial_handle_break,
                .iotype         = UPIO_MEM,
                .regshift       = 2,
                .uartclk        = 216000000,
@@ -111,19 +114,13 @@ static void trimslice_i2c_init(void)
 static void trimslice_usb_init(void)
 {
-        int err;
+        struct tegra_ehci_platform_data *pdata;
-        platform_device_register(&tegra_ehci3_device);
+        pdata = tegra_ehci1_device.dev.platform_data;
+        pdata->vbus_gpio = TRIMSLICE_GPIO_USB1_MODE;
+        platform_device_register(&tegra_ehci3_device);
        platform_device_register(&tegra_ehci2_device);
-        err = gpio_request_one(TRIMSLICE_GPIO_USB1_MODE, GPIOF_OUT_INIT_HIGH,
-                               "usb1mode");
-        if (err) {
-                pr_err("TrimSlice: failed to obtain USB1 mode gpio: %d\n", err);
-                return;
-        }
        platform_device_register(&tegra_ehci1_device);
 }
diff --git a/arch/arm/mach-tegra/devices.c b/arch/arm/mach-tegra/devices.c
index 5f6b867e20b4..bd3035e0cea1 100644
--- a/arch/arm/mach-tegra/devices.c
+++ b/arch/arm/mach-tegra/devices.c
@@ -110,7 +110,7 @@ static struct resource pinmux_resource[] = {
 };
 struct platform_device tegra_pinmux_device = {
-        .name           = "tegra-pinmux",
+        .name           = "tegra20-pinctrl",
        .id             = -1,
        .resource       = pinmux_resource,
        .num_resources  = ARRAY_SIZE(pinmux_resource),
@@ -448,17 +448,20 @@ static struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = {
 struct tegra_ehci_platform_data tegra_ehci1_pdata = {
        .operating_mode = TEGRA_USB_OTG,
        .power_down_on_bus_suspend = 1,
+        .vbus_gpio = -1,
 };
 struct tegra_ehci_platform_data tegra_ehci2_pdata = {
        .phy_config = &tegra_ehci2_ulpi_phy_config,
        .operating_mode = TEGRA_USB_HOST,
        .power_down_on_bus_suspend = 1,
+        .vbus_gpio = -1,
 };
 struct tegra_ehci_platform_data tegra_ehci3_pdata = {
        .operating_mode = TEGRA_USB_HOST,
        .power_down_on_bus_suspend = 1,
+        .vbus_gpio = -1,
 };
 static u64 tegra_ehci_dmamask = DMA_BIT_MASK(32);
diff --git a/arch/arm/mach-tegra/flowctrl.c b/arch/arm/mach-tegra/flowctrl.c
index fef66a7486ed..f07488e0bd32 100644
--- a/arch/arm/mach-tegra/flowctrl.c
+++ b/arch/arm/mach-tegra/flowctrl.c
@@ -53,10 +53,10 @@ static void flowctrl_update(u8 offset, u32 value)
 void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value)
 {
-        return flowctrl_update(flowctrl_offset_halt_cpu[cpuid], value);
+        return flowctrl_update(flowctrl_offset_cpu_csr[cpuid], value);
 }
 void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value)
 {
-        return flowctrl_update(flowctrl_offset_cpu_csr[cpuid], value);
+        return flowctrl_update(flowctrl_offset_halt_cpu[cpuid], value);
 }
diff --git a/arch/arm/mach-tegra/include/mach/dma.h b/arch/arm/mach-tegra/include/mach/dma.h
index 3c9339058bec..9077092812c0 100644
--- a/arch/arm/mach-tegra/include/mach/dma.h
+++ b/arch/arm/mach-tegra/include/mach/dma.h
@@ -51,8 +51,6 @@
 #define TEGRA_DMA_REQ_SEL_OWR                   25
 #define TEGRA_DMA_REQ_SEL_INVALID               31
-#if defined(CONFIG_TEGRA_SYSTEM_DMA)
 struct tegra_dma_req;
 struct tegra_dma_channel;
@@ -151,5 +149,3 @@ void tegra_dma_free_channel(struct tegra_dma_channel *ch);
 int __init tegra_dma_init(void);
 #endif
-#endif
diff --git a/arch/arm/mach-tegra/include/mach/gpio-tegra.h b/arch/arm/mach-tegra/include/mach/gpio-tegra.h
index 6140820555e1..a978b3cc3a8d 100644
--- a/arch/arm/mach-tegra/include/mach/gpio-tegra.h
+++ b/arch/arm/mach-tegra/include/mach/gpio-tegra.h
@@ -25,13 +25,4 @@
 #define TEGRA_NR_GPIOS          INT_GPIO_NR
-struct tegra_gpio_table {
-        int     gpio;   /* GPIO number */
-        bool    enable; /* Enable for GPIO at init? */
-};
-void tegra_gpio_config(struct tegra_gpio_table *table, int num);
-void tegra_gpio_enable(int gpio);
-void tegra_gpio_disable(int gpio);
 #endif
diff --git a/arch/arm/mach-tegra/include/mach/pinmux-tegra20.h b/arch/arm/mach-tegra/include/mach/pinmux-tegra20.h
deleted file mode 100644
index 6a40c1dbab17..000000000000
--- a/arch/arm/mach-tegra/include/mach/pinmux-tegra20.h
+++ /dev/null
@@ -1,184 +0,0 @@
-/*
- * linux/arch/arm/mach-tegra/include/mach/pinmux-tegra20.h
- *
- * Copyright (C) 2010 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#ifndef __MACH_TEGRA_PINMUX_TEGRA20_H
-#define __MACH_TEGRA_PINMUX_TEGRA20_H
-enum tegra_pingroup {
-        TEGRA_PINGROUP_ATA = 0,
-        TEGRA_PINGROUP_ATB,
-        TEGRA_PINGROUP_ATC,
-        TEGRA_PINGROUP_ATD,
-        TEGRA_PINGROUP_ATE,
-        TEGRA_PINGROUP_CDEV1,
-        TEGRA_PINGROUP_CDEV2,
-        TEGRA_PINGROUP_CRTP,
-        TEGRA_PINGROUP_CSUS,
-        TEGRA_PINGROUP_DAP1,
-        TEGRA_PINGROUP_DAP2,
-        TEGRA_PINGROUP_DAP3,
-        TEGRA_PINGROUP_DAP4,
-        TEGRA_PINGROUP_DDC,
-        TEGRA_PINGROUP_DTA,
-        TEGRA_PINGROUP_DTB,
-        TEGRA_PINGROUP_DTC,
-        TEGRA_PINGROUP_DTD,
-        TEGRA_PINGROUP_DTE,
-        TEGRA_PINGROUP_DTF,
-        TEGRA_PINGROUP_GMA,
-        TEGRA_PINGROUP_GMB,
-        TEGRA_PINGROUP_GMC,
-        TEGRA_PINGROUP_GMD,
-        TEGRA_PINGROUP_GME,
-        TEGRA_PINGROUP_GPU,
-        TEGRA_PINGROUP_GPU7,
-        TEGRA_PINGROUP_GPV,
-        TEGRA_PINGROUP_HDINT,
-        TEGRA_PINGROUP_I2CP,
-        TEGRA_PINGROUP_IRRX,
-        TEGRA_PINGROUP_IRTX,
-        TEGRA_PINGROUP_KBCA,
-        TEGRA_PINGROUP_KBCB,
-        TEGRA_PINGROUP_KBCC,
-        TEGRA_PINGROUP_KBCD,
-        TEGRA_PINGROUP_KBCE,
-        TEGRA_PINGROUP_KBCF,
-        TEGRA_PINGROUP_LCSN,
-        TEGRA_PINGROUP_LD0,
-        TEGRA_PINGROUP_LD1,
-        TEGRA_PINGROUP_LD10,
-        TEGRA_PINGROUP_LD11,
-        TEGRA_PINGROUP_LD12,
-        TEGRA_PINGROUP_LD13,
-        TEGRA_PINGROUP_LD14,
-        TEGRA_PINGROUP_LD15,
-        TEGRA_PINGROUP_LD16,
-        TEGRA_PINGROUP_LD17,
-        TEGRA_PINGROUP_LD2,
-        TEGRA_PINGROUP_LD3,
-        TEGRA_PINGROUP_LD4,
-        TEGRA_PINGROUP_LD5,
-        TEGRA_PINGROUP_LD6,
-        TEGRA_PINGROUP_LD7,
-        TEGRA_PINGROUP_LD8,
-        TEGRA_PINGROUP_LD9,
-        TEGRA_PINGROUP_LDC,
-        TEGRA_PINGROUP_LDI,
-        TEGRA_PINGROUP_LHP0,
-        TEGRA_PINGROUP_LHP1,
-        TEGRA_PINGROUP_LHP2,
-        TEGRA_PINGROUP_LHS,
-        TEGRA_PINGROUP_LM0,
-        TEGRA_PINGROUP_LM1,
-        TEGRA_PINGROUP_LPP,
-        TEGRA_PINGROUP_LPW0,
-        TEGRA_PINGROUP_LPW1,
-        TEGRA_PINGROUP_LPW2,
-        TEGRA_PINGROUP_LSC0,
-        TEGRA_PINGROUP_LSC1,
-        TEGRA_PINGROUP_LSCK,
-        TEGRA_PINGROUP_LSDA,
-        TEGRA_PINGROUP_LSDI,
-        TEGRA_PINGROUP_LSPI,
-        TEGRA_PINGROUP_LVP0,
-        TEGRA_PINGROUP_LVP1,
-        TEGRA_PINGROUP_LVS,
-        TEGRA_PINGROUP_OWC,
-        TEGRA_PINGROUP_PMC,
-        TEGRA_PINGROUP_PTA,
-        TEGRA_PINGROUP_RM,
-        TEGRA_PINGROUP_SDB,
-        TEGRA_PINGROUP_SDC,
-        TEGRA_PINGROUP_SDD,
-        TEGRA_PINGROUP_SDIO1,
-        TEGRA_PINGROUP_SLXA,
-        TEGRA_PINGROUP_SLXC,
-        TEGRA_PINGROUP_SLXD,
-        TEGRA_PINGROUP_SLXK,
-        TEGRA_PINGROUP_SPDI,
-        TEGRA_PINGROUP_SPDO,
-        TEGRA_PINGROUP_SPIA,
-        TEGRA_PINGROUP_SPIB,
-        TEGRA_PINGROUP_SPIC,
-        TEGRA_PINGROUP_SPID,
-        TEGRA_PINGROUP_SPIE,
-        TEGRA_PINGROUP_SPIF,
-        TEGRA_PINGROUP_SPIG,
-        TEGRA_PINGROUP_SPIH,
-        TEGRA_PINGROUP_UAA,
-        TEGRA_PINGROUP_UAB,
-        TEGRA_PINGROUP_UAC,
-        TEGRA_PINGROUP_UAD,
-        TEGRA_PINGROUP_UCA,
-        TEGRA_PINGROUP_UCB,
-        TEGRA_PINGROUP_UDA,
-        /* these pin groups only have pullup and pull down control */
-        TEGRA_PINGROUP_CK32,
-        TEGRA_PINGROUP_DDRC,
-        TEGRA_PINGROUP_PMCA,
-        TEGRA_PINGROUP_PMCB,
-        TEGRA_PINGROUP_PMCC,
-        TEGRA_PINGROUP_PMCD,
-        TEGRA_PINGROUP_PMCE,
-        TEGRA_PINGROUP_XM2C,
-        TEGRA_PINGROUP_XM2D,
-        TEGRA_MAX_PINGROUP,
-};
-enum tegra_drive_pingroup {
-        TEGRA_DRIVE_PINGROUP_AO1 = 0,
-        TEGRA_DRIVE_PINGROUP_AO2,
-        TEGRA_DRIVE_PINGROUP_AT1,
-        TEGRA_DRIVE_PINGROUP_AT2,
-        TEGRA_DRIVE_PINGROUP_CDEV1,
-        TEGRA_DRIVE_PINGROUP_CDEV2,
-        TEGRA_DRIVE_PINGROUP_CSUS,
-        TEGRA_DRIVE_PINGROUP_DAP1,
-        TEGRA_DRIVE_PINGROUP_DAP2,
-        TEGRA_DRIVE_PINGROUP_DAP3,
-        TEGRA_DRIVE_PINGROUP_DAP4,
-        TEGRA_DRIVE_PINGROUP_DBG,
-        TEGRA_DRIVE_PINGROUP_LCD1,
-        TEGRA_DRIVE_PINGROUP_LCD2,
-        TEGRA_DRIVE_PINGROUP_SDMMC2,
-        TEGRA_DRIVE_PINGROUP_SDMMC3,
-        TEGRA_DRIVE_PINGROUP_SPI,
-        TEGRA_DRIVE_PINGROUP_UAA,
-        TEGRA_DRIVE_PINGROUP_UAB,
-        TEGRA_DRIVE_PINGROUP_UART2,
-        TEGRA_DRIVE_PINGROUP_UART3,
-        TEGRA_DRIVE_PINGROUP_VI1,
-        TEGRA_DRIVE_PINGROUP_VI2,
-        TEGRA_DRIVE_PINGROUP_XM2A,
-        TEGRA_DRIVE_PINGROUP_XM2C,
-        TEGRA_DRIVE_PINGROUP_XM2D,
-        TEGRA_DRIVE_PINGROUP_XM2CLK,
-        TEGRA_DRIVE_PINGROUP_MEMCOMP,
-        TEGRA_DRIVE_PINGROUP_SDIO1,
-        TEGRA_DRIVE_PINGROUP_CRT,
-        TEGRA_DRIVE_PINGROUP_DDC,
-        TEGRA_DRIVE_PINGROUP_GMA,
-        TEGRA_DRIVE_PINGROUP_GMB,
-        TEGRA_DRIVE_PINGROUP_GMC,
-        TEGRA_DRIVE_PINGROUP_GMD,
-        TEGRA_DRIVE_PINGROUP_GME,
-        TEGRA_DRIVE_PINGROUP_OWR,
-        TEGRA_DRIVE_PINGROUP_UAD,
-        TEGRA_MAX_DRIVE_PINGROUP,
-};
-#endif
diff --git a/arch/arm/mach-tegra/include/mach/pinmux-tegra30.h b/arch/arm/mach-tegra/include/mach/pinmux-tegra30.h
deleted file mode 100644
index c1aee3eb2df1..000000000000
--- a/arch/arm/mach-tegra/include/mach/pinmux-tegra30.h
+++ /dev/null
@@ -1,320 +0,0 @@
-/*
- * linux/arch/arm/mach-tegra/include/mach/pinmux-tegra30.h
- *
- * Copyright (C) 2010 Google, Inc.
- * Copyright (C) 2010,2011 Nvidia, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#ifndef __MACH_TEGRA_PINMUX_TEGRA30_H
-#define __MACH_TEGRA_PINMUX_TEGRA30_H
-enum tegra_pingroup {
-        TEGRA_PINGROUP_ULPI_DATA0 = 0,
-        TEGRA_PINGROUP_ULPI_DATA1,
-        TEGRA_PINGROUP_ULPI_DATA2,
-        TEGRA_PINGROUP_ULPI_DATA3,
-        TEGRA_PINGROUP_ULPI_DATA4,
-        TEGRA_PINGROUP_ULPI_DATA5,
-        TEGRA_PINGROUP_ULPI_DATA6,
-        TEGRA_PINGROUP_ULPI_DATA7,
-        TEGRA_PINGROUP_ULPI_CLK,
-        TEGRA_PINGROUP_ULPI_DIR,
-        TEGRA_PINGROUP_ULPI_NXT,
-        TEGRA_PINGROUP_ULPI_STP,
-        TEGRA_PINGROUP_DAP3_FS,
-        TEGRA_PINGROUP_DAP3_DIN,
-        TEGRA_PINGROUP_DAP3_DOUT,
-        TEGRA_PINGROUP_DAP3_SCLK,
-        TEGRA_PINGROUP_GPIO_PV0,
-        TEGRA_PINGROUP_GPIO_PV1,
-        TEGRA_PINGROUP_SDMMC1_CLK,
-        TEGRA_PINGROUP_SDMMC1_CMD,
-        TEGRA_PINGROUP_SDMMC1_DAT3,
-        TEGRA_PINGROUP_SDMMC1_DAT2,
-        TEGRA_PINGROUP_SDMMC1_DAT1,
-        TEGRA_PINGROUP_SDMMC1_DAT0,
-        TEGRA_PINGROUP_GPIO_PV2,
-        TEGRA_PINGROUP_GPIO_PV3,
-        TEGRA_PINGROUP_CLK2_OUT,
-        TEGRA_PINGROUP_CLK2_REQ,
-        TEGRA_PINGROUP_LCD_PWR1,
-        TEGRA_PINGROUP_LCD_PWR2,
-        TEGRA_PINGROUP_LCD_SDIN,
-        TEGRA_PINGROUP_LCD_SDOUT,
-        TEGRA_PINGROUP_LCD_WR_N,
-        TEGRA_PINGROUP_LCD_CS0_N,
-        TEGRA_PINGROUP_LCD_DC0,
-        TEGRA_PINGROUP_LCD_SCK,
-        TEGRA_PINGROUP_LCD_PWR0,
-        TEGRA_PINGROUP_LCD_PCLK,
-        TEGRA_PINGROUP_LCD_DE,
-        TEGRA_PINGROUP_LCD_HSYNC,
-        TEGRA_PINGROUP_LCD_VSYNC,
-        TEGRA_PINGROUP_LCD_D0,
-        TEGRA_PINGROUP_LCD_D1,
-        TEGRA_PINGROUP_LCD_D2,
-        TEGRA_PINGROUP_LCD_D3,
-        TEGRA_PINGROUP_LCD_D4,
-        TEGRA_PINGROUP_LCD_D5,
-        TEGRA_PINGROUP_LCD_D6,
-        TEGRA_PINGROUP_LCD_D7,
-        TEGRA_PINGROUP_LCD_D8,
-        TEGRA_PINGROUP_LCD_D9,
-        TEGRA_PINGROUP_LCD_D10,
-        TEGRA_PINGROUP_LCD_D11,
-        TEGRA_PINGROUP_LCD_D12,
-        TEGRA_PINGROUP_LCD_D13,
-        TEGRA_PINGROUP_LCD_D14,
-        TEGRA_PINGROUP_LCD_D15,
-        TEGRA_PINGROUP_LCD_D16,
-        TEGRA_PINGROUP_LCD_D17,
-        TEGRA_PINGROUP_LCD_D18,
-        TEGRA_PINGROUP_LCD_D19,
-        TEGRA_PINGROUP_LCD_D20,
-        TEGRA_PINGROUP_LCD_D21,
-        TEGRA_PINGROUP_LCD_D22,
-        TEGRA_PINGROUP_LCD_D23,
-        TEGRA_PINGROUP_LCD_CS1_N,
-        TEGRA_PINGROUP_LCD_M1,
-        TEGRA_PINGROUP_LCD_DC1,
-        TEGRA_PINGROUP_HDMI_INT,
-        TEGRA_PINGROUP_DDC_SCL,
-        TEGRA_PINGROUP_DDC_SDA,
-        TEGRA_PINGROUP_CRT_HSYNC,
-        TEGRA_PINGROUP_CRT_VSYNC,
-        TEGRA_PINGROUP_VI_D0,
-        TEGRA_PINGROUP_VI_D1,
-        TEGRA_PINGROUP_VI_D2,
-        TEGRA_PINGROUP_VI_D3,
-        TEGRA_PINGROUP_VI_D4,
-        TEGRA_PINGROUP_VI_D5,
-        TEGRA_PINGROUP_VI_D6,
-        TEGRA_PINGROUP_VI_D7,
-        TEGRA_PINGROUP_VI_D8,
-        TEGRA_PINGROUP_VI_D9,
-        TEGRA_PINGROUP_VI_D10,
-        TEGRA_PINGROUP_VI_D11,
-        TEGRA_PINGROUP_VI_PCLK,
-        TEGRA_PINGROUP_VI_MCLK,
-        TEGRA_PINGROUP_VI_VSYNC,
-        TEGRA_PINGROUP_VI_HSYNC,
-        TEGRA_PINGROUP_UART2_RXD,
-        TEGRA_PINGROUP_UART2_TXD,
-        TEGRA_PINGROUP_UART2_RTS_N,
-        TEGRA_PINGROUP_UART2_CTS_N,
-        TEGRA_PINGROUP_UART3_TXD,
-        TEGRA_PINGROUP_UART3_RXD,
-        TEGRA_PINGROUP_UART3_CTS_N,
-        TEGRA_PINGROUP_UART3_RTS_N,
-        TEGRA_PINGROUP_GPIO_PU0,
-        TEGRA_PINGROUP_GPIO_PU1,
-        TEGRA_PINGROUP_GPIO_PU2,
-        TEGRA_PINGROUP_GPIO_PU3,
-        TEGRA_PINGROUP_GPIO_PU4,
-        TEGRA_PINGROUP_GPIO_PU5,
-        TEGRA_PINGROUP_GPIO_PU6,
-        TEGRA_PINGROUP_GEN1_I2C_SDA,
-        TEGRA_PINGROUP_GEN1_I2C_SCL,
-        TEGRA_PINGROUP_DAP4_FS,
-        TEGRA_PINGROUP_DAP4_DIN,
-        TEGRA_PINGROUP_DAP4_DOUT,
-        TEGRA_PINGROUP_DAP4_SCLK,
-        TEGRA_PINGROUP_CLK3_OUT,
-        TEGRA_PINGROUP_CLK3_REQ,
-        TEGRA_PINGROUP_GMI_WP_N,
-        TEGRA_PINGROUP_GMI_IORDY,
-        TEGRA_PINGROUP_GMI_WAIT,
-        TEGRA_PINGROUP_GMI_ADV_N,
-        TEGRA_PINGROUP_GMI_CLK,
-        TEGRA_PINGROUP_GMI_CS0_N,
-        TEGRA_PINGROUP_GMI_CS1_N,
-        TEGRA_PINGROUP_GMI_CS2_N,
-        TEGRA_PINGROUP_GMI_CS3_N,
-        TEGRA_PINGROUP_GMI_CS4_N,
-        TEGRA_PINGROUP_GMI_CS6_N,
-        TEGRA_PINGROUP_GMI_CS7_N,
-        TEGRA_PINGROUP_GMI_AD0,
-        TEGRA_PINGROUP_GMI_AD1,
-        TEGRA_PINGROUP_GMI_AD2,
-        TEGRA_PINGROUP_GMI_AD3,
-        TEGRA_PINGROUP_GMI_AD4,
-        TEGRA_PINGROUP_GMI_AD5,
-        TEGRA_PINGROUP_GMI_AD6,
-        TEGRA_PINGROUP_GMI_AD7,
-        TEGRA_PINGROUP_GMI_AD8,
-        TEGRA_PINGROUP_GMI_AD9,
-        TEGRA_PINGROUP_GMI_AD10,
-        TEGRA_PINGROUP_GMI_AD11,
-        TEGRA_PINGROUP_GMI_AD12,
-        TEGRA_PINGROUP_GMI_AD13,
-        TEGRA_PINGROUP_GMI_AD14,
-        TEGRA_PINGROUP_GMI_AD15,
-        TEGRA_PINGROUP_GMI_A16,
-        TEGRA_PINGROUP_GMI_A17,
-        TEGRA_PINGROUP_GMI_A18,
-        TEGRA_PINGROUP_GMI_A19,
-        TEGRA_PINGROUP_GMI_WR_N,
-        TEGRA_PINGROUP_GMI_OE_N,
-        TEGRA_PINGROUP_GMI_DQS,
-        TEGRA_PINGROUP_GMI_RST_N,
-        TEGRA_PINGROUP_GEN2_I2C_SCL,
-        TEGRA_PINGROUP_GEN2_I2C_SDA,
-        TEGRA_PINGROUP_SDMMC4_CLK,
-        TEGRA_PINGROUP_SDMMC4_CMD,
-        TEGRA_PINGROUP_SDMMC4_DAT0,
-        TEGRA_PINGROUP_SDMMC4_DAT1,
-        TEGRA_PINGROUP_SDMMC4_DAT2,
-        TEGRA_PINGROUP_SDMMC4_DAT3,
-        TEGRA_PINGROUP_SDMMC4_DAT4,
-        TEGRA_PINGROUP_SDMMC4_DAT5,
-        TEGRA_PINGROUP_SDMMC4_DAT6,
-        TEGRA_PINGROUP_SDMMC4_DAT7,
-        TEGRA_PINGROUP_SDMMC4_RST_N,
-        TEGRA_PINGROUP_CAM_MCLK,
-        TEGRA_PINGROUP_GPIO_PCC1,
-        TEGRA_PINGROUP_GPIO_PBB0,
-        TEGRA_PINGROUP_CAM_I2C_SCL,
-        TEGRA_PINGROUP_CAM_I2C_SDA,
-        TEGRA_PINGROUP_GPIO_PBB3,
-        TEGRA_PINGROUP_GPIO_PBB4,
-        TEGRA_PINGROUP_GPIO_PBB5,
-        TEGRA_PINGROUP_GPIO_PBB6,
-        TEGRA_PINGROUP_GPIO_PBB7,
-        TEGRA_PINGROUP_GPIO_PCC2,
-        TEGRA_PINGROUP_JTAG_RTCK,
-        TEGRA_PINGROUP_PWR_I2C_SCL,
-        TEGRA_PINGROUP_PWR_I2C_SDA,
-        TEGRA_PINGROUP_KB_ROW0,
-        TEGRA_PINGROUP_KB_ROW1,
-        TEGRA_PINGROUP_KB_ROW2,
-        TEGRA_PINGROUP_KB_ROW3,
-        TEGRA_PINGROUP_KB_ROW4,
-        TEGRA_PINGROUP_KB_ROW5,
-        TEGRA_PINGROUP_KB_ROW6,
-        TEGRA_PINGROUP_KB_ROW7,
-        TEGRA_PINGROUP_KB_ROW8,
-        TEGRA_PINGROUP_KB_ROW9,
-        TEGRA_PINGROUP_KB_ROW10,
-        TEGRA_PINGROUP_KB_ROW11,
-        TEGRA_PINGROUP_KB_ROW12,
-        TEGRA_PINGROUP_KB_ROW13,
-        TEGRA_PINGROUP_KB_ROW14,
-        TEGRA_PINGROUP_KB_ROW15,
-        TEGRA_PINGROUP_KB_COL0,
-        TEGRA_PINGROUP_KB_COL1,
-        TEGRA_PINGROUP_KB_COL2,
-        TEGRA_PINGROUP_KB_COL3,
-        TEGRA_PINGROUP_KB_COL4,
-        TEGRA_PINGROUP_KB_COL5,
-        TEGRA_PINGROUP_KB_COL6,
-        TEGRA_PINGROUP_KB_COL7,
-        TEGRA_PINGROUP_CLK_32K_OUT,
-        TEGRA_PINGROUP_SYS_CLK_REQ,
-        TEGRA_PINGROUP_CORE_PWR_REQ,
-        TEGRA_PINGROUP_CPU_PWR_REQ,
-        TEGRA_PINGROUP_PWR_INT_N,
-        TEGRA_PINGROUP_CLK_32K_IN,
-        TEGRA_PINGROUP_OWR,
-        TEGRA_PINGROUP_DAP1_FS,
-        TEGRA_PINGROUP_DAP1_DIN,
-        TEGRA_PINGROUP_DAP1_DOUT,
-        TEGRA_PINGROUP_DAP1_SCLK,
-        TEGRA_PINGROUP_CLK1_REQ,
-        TEGRA_PINGROUP_CLK1_OUT,
-        TEGRA_PINGROUP_SPDIF_IN,
-        TEGRA_PINGROUP_SPDIF_OUT,
-        TEGRA_PINGROUP_DAP2_FS,
-        TEGRA_PINGROUP_DAP2_DIN,
-        TEGRA_PINGROUP_DAP2_DOUT,
-        TEGRA_PINGROUP_DAP2_SCLK,
-        TEGRA_PINGROUP_SPI2_MOSI,
-        TEGRA_PINGROUP_SPI2_MISO,
-        TEGRA_PINGROUP_SPI2_CS0_N,
-        TEGRA_PINGROUP_SPI2_SCK,
-        TEGRA_PINGROUP_SPI1_MOSI,
-        TEGRA_PINGROUP_SPI1_SCK,
-        TEGRA_PINGROUP_SPI1_CS0_N,
-        TEGRA_PINGROUP_SPI1_MISO,
-        TEGRA_PINGROUP_SPI2_CS1_N,
-        TEGRA_PINGROUP_SPI2_CS2_N,
-        TEGRA_PINGROUP_SDMMC3_CLK,
-        TEGRA_PINGROUP_SDMMC3_CMD,
-        TEGRA_PINGROUP_SDMMC3_DAT0,
-        TEGRA_PINGROUP_SDMMC3_DAT1,
-        TEGRA_PINGROUP_SDMMC3_DAT2,
-        TEGRA_PINGROUP_SDMMC3_DAT3,
-        TEGRA_PINGROUP_SDMMC3_DAT4,
-        TEGRA_PINGROUP_SDMMC3_DAT5,
-        TEGRA_PINGROUP_SDMMC3_DAT6,
-        TEGRA_PINGROUP_SDMMC3_DAT7,
-        TEGRA_PINGROUP_PEX_L0_PRSNT_N,
-        TEGRA_PINGROUP_PEX_L0_RST_N,
-        TEGRA_PINGROUP_PEX_L0_CLKREQ_N,
-        TEGRA_PINGROUP_PEX_WAKE_N,
-        TEGRA_PINGROUP_PEX_L1_PRSNT_N,
-        TEGRA_PINGROUP_PEX_L1_RST_N,
-        TEGRA_PINGROUP_PEX_L1_CLKREQ_N,
-        TEGRA_PINGROUP_PEX_L2_PRSNT_N,
-        TEGRA_PINGROUP_PEX_L2_RST_N,
-        TEGRA_PINGROUP_PEX_L2_CLKREQ_N,
-        TEGRA_PINGROUP_HDMI_CEC,
-        TEGRA_MAX_PINGROUP,
-};
-enum tegra_drive_pingroup {
-        TEGRA_DRIVE_PINGROUP_AO1 = 0,
-        TEGRA_DRIVE_PINGROUP_AO2,
-        TEGRA_DRIVE_PINGROUP_AT1,
-        TEGRA_DRIVE_PINGROUP_AT2,
-        TEGRA_DRIVE_PINGROUP_AT3,
-        TEGRA_DRIVE_PINGROUP_AT4,
-        TEGRA_DRIVE_PINGROUP_AT5,
-        TEGRA_DRIVE_PINGROUP_CDEV1,
-        TEGRA_DRIVE_PINGROUP_CDEV2,
-        TEGRA_DRIVE_PINGROUP_CSUS,
-        TEGRA_DRIVE_PINGROUP_DAP1,
-        TEGRA_DRIVE_PINGROUP_DAP2,
-        TEGRA_DRIVE_PINGROUP_DAP3,
-        TEGRA_DRIVE_PINGROUP_DAP4,
-        TEGRA_DRIVE_PINGROUP_DBG,
-        TEGRA_DRIVE_PINGROUP_LCD1,
-        TEGRA_DRIVE_PINGROUP_LCD2,
-        TEGRA_DRIVE_PINGROUP_SDIO2,
-        TEGRA_DRIVE_PINGROUP_SDIO3,
-        TEGRA_DRIVE_PINGROUP_SPI,
-        TEGRA_DRIVE_PINGROUP_UAA,
-        TEGRA_DRIVE_PINGROUP_UAB,
-        TEGRA_DRIVE_PINGROUP_UART2,
-        TEGRA_DRIVE_PINGROUP_UART3,
-        TEGRA_DRIVE_PINGROUP_VI1,
-        TEGRA_DRIVE_PINGROUP_SDIO1,
-        TEGRA_DRIVE_PINGROUP_CRT,
-        TEGRA_DRIVE_PINGROUP_DDC,
-        TEGRA_DRIVE_PINGROUP_GMA,
-        TEGRA_DRIVE_PINGROUP_GMB,
-        TEGRA_DRIVE_PINGROUP_GMC,
-        TEGRA_DRIVE_PINGROUP_GMD,
-        TEGRA_DRIVE_PINGROUP_GME,
-        TEGRA_DRIVE_PINGROUP_GMF,
-        TEGRA_DRIVE_PINGROUP_GMG,
-        TEGRA_DRIVE_PINGROUP_GMH,
-        TEGRA_DRIVE_PINGROUP_OWR,
-        TEGRA_DRIVE_PINGROUP_UAD,
-        TEGRA_DRIVE_PINGROUP_GPV,
-        TEGRA_DRIVE_PINGROUP_DEV3,
-        TEGRA_DRIVE_PINGROUP_CEC,
-        TEGRA_MAX_DRIVE_PINGROUP,
-};
-#endif
diff --git a/arch/arm/mach-tegra/include/mach/pinmux.h b/arch/arm/mach-tegra/include/mach/pinmux.h
deleted file mode 100644
index 055f1792c8ff..000000000000
--- a/arch/arm/mach-tegra/include/mach/pinmux.h
+++ /dev/null
@@ -1,302 +0,0 @@
-/*
- * linux/arch/arm/mach-tegra/include/mach/pinmux.h
- *
- * Copyright (C) 2010 Google, Inc.
- * Copyright (C) 2010,2011 Nvidia, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#ifndef __MACH_TEGRA_PINMUX_H
-#define __MACH_TEGRA_PINMUX_H
-enum tegra_mux_func {
-        TEGRA_MUX_RSVD = 0x8000,
-        TEGRA_MUX_RSVD1 = 0x8000,
-        TEGRA_MUX_RSVD2 = 0x8001,
-        TEGRA_MUX_RSVD3 = 0x8002,
-        TEGRA_MUX_RSVD4 = 0x8003,
-        TEGRA_MUX_INVALID = 0x4000,
-        TEGRA_MUX_NONE = -1,
-        TEGRA_MUX_AHB_CLK,
-        TEGRA_MUX_APB_CLK,
-        TEGRA_MUX_AUDIO_SYNC,
-        TEGRA_MUX_CRT,
-        TEGRA_MUX_DAP1,
-        TEGRA_MUX_DAP2,
-        TEGRA_MUX_DAP3,
-        TEGRA_MUX_DAP4,
-        TEGRA_MUX_DAP5,
-        TEGRA_MUX_DISPLAYA,
-        TEGRA_MUX_DISPLAYB,
-        TEGRA_MUX_EMC_TEST0_DLL,
-        TEGRA_MUX_EMC_TEST1_DLL,
-        TEGRA_MUX_GMI,
-        TEGRA_MUX_GMI_INT,
-        TEGRA_MUX_HDMI,
-        TEGRA_MUX_I2C,
-        TEGRA_MUX_I2C2,
-        TEGRA_MUX_I2C3,
-        TEGRA_MUX_IDE,
-        TEGRA_MUX_IRDA,
-        TEGRA_MUX_KBC,
-        TEGRA_MUX_MIO,
-        TEGRA_MUX_MIPI_HS,
-        TEGRA_MUX_NAND,
-        TEGRA_MUX_OSC,
-        TEGRA_MUX_OWR,
-        TEGRA_MUX_PCIE,
-        TEGRA_MUX_PLLA_OUT,
-        TEGRA_MUX_PLLC_OUT1,
-        TEGRA_MUX_PLLM_OUT1,
-        TEGRA_MUX_PLLP_OUT2,
-        TEGRA_MUX_PLLP_OUT3,
-        TEGRA_MUX_PLLP_OUT4,
-        TEGRA_MUX_PWM,
-        TEGRA_MUX_PWR_INTR,
-        TEGRA_MUX_PWR_ON,
-        TEGRA_MUX_RTCK,
-        TEGRA_MUX_SDIO1,
-        TEGRA_MUX_SDIO2,
-        TEGRA_MUX_SDIO3,
-        TEGRA_MUX_SDIO4,
-        TEGRA_MUX_SFLASH,
-        TEGRA_MUX_SPDIF,
-        TEGRA_MUX_SPI1,
-        TEGRA_MUX_SPI2,
-        TEGRA_MUX_SPI2_ALT,
-        TEGRA_MUX_SPI3,
-        TEGRA_MUX_SPI4,
-        TEGRA_MUX_TRACE,
-        TEGRA_MUX_TWC,
-        TEGRA_MUX_UARTA,
-        TEGRA_MUX_UARTB,
-        TEGRA_MUX_UARTC,
-        TEGRA_MUX_UARTD,
-        TEGRA_MUX_UARTE,
-        TEGRA_MUX_ULPI,
-        TEGRA_MUX_VI,
-        TEGRA_MUX_VI_SENSOR_CLK,
-        TEGRA_MUX_XIO,
-        TEGRA_MUX_BLINK,
-        TEGRA_MUX_CEC,
-        TEGRA_MUX_CLK12,
-        TEGRA_MUX_DAP,
-        TEGRA_MUX_DAPSDMMC2,
-        TEGRA_MUX_DDR,
-        TEGRA_MUX_DEV3,
-        TEGRA_MUX_DTV,
-        TEGRA_MUX_VI_ALT1,
-        TEGRA_MUX_VI_ALT2,
-        TEGRA_MUX_VI_ALT3,
-        TEGRA_MUX_EMC_DLL,
-        TEGRA_MUX_EXTPERIPH1,
-        TEGRA_MUX_EXTPERIPH2,
-        TEGRA_MUX_EXTPERIPH3,
-        TEGRA_MUX_GMI_ALT,
-        TEGRA_MUX_HDA,
-        TEGRA_MUX_HSI,
-        TEGRA_MUX_I2C4,
-        TEGRA_MUX_I2C5,
-        TEGRA_MUX_I2CPWR,
-        TEGRA_MUX_I2S0,
-        TEGRA_MUX_I2S1,
-        TEGRA_MUX_I2S2,
-        TEGRA_MUX_I2S3,
-        TEGRA_MUX_I2S4,
-        TEGRA_MUX_NAND_ALT,
-        TEGRA_MUX_POPSDIO4,
-        TEGRA_MUX_POPSDMMC4,
-        TEGRA_MUX_PWM0,
-        TEGRA_MUX_PWM1,
-        TEGRA_MUX_PWM2,
-        TEGRA_MUX_PWM3,
-        TEGRA_MUX_SATA,
-        TEGRA_MUX_SPI5,
-        TEGRA_MUX_SPI6,
-        TEGRA_MUX_SYSCLK,
-        TEGRA_MUX_VGP1,
-        TEGRA_MUX_VGP2,
-        TEGRA_MUX_VGP3,
-        TEGRA_MUX_VGP4,
-        TEGRA_MUX_VGP5,
-        TEGRA_MUX_VGP6,
-        TEGRA_MUX_SAFE,
-        TEGRA_MAX_MUX,
-};
-enum tegra_pullupdown {
-        TEGRA_PUPD_NORMAL = 0,
-        TEGRA_PUPD_PULL_DOWN,
-        TEGRA_PUPD_PULL_UP,
-};
-enum tegra_tristate {
-        TEGRA_TRI_NORMAL = 0,
-        TEGRA_TRI_TRISTATE = 1,
-};
-enum tegra_pin_io {
-        TEGRA_PIN_OUTPUT = 0,
-        TEGRA_PIN_INPUT = 1,
-};
-enum tegra_vddio {
-        TEGRA_VDDIO_BB = 0,
-        TEGRA_VDDIO_LCD,
-        TEGRA_VDDIO_VI,
-        TEGRA_VDDIO_UART,
-        TEGRA_VDDIO_DDR,
-        TEGRA_VDDIO_NAND,
-        TEGRA_VDDIO_SYS,
-        TEGRA_VDDIO_AUDIO,
-        TEGRA_VDDIO_SD,
-        TEGRA_VDDIO_CAM,
-        TEGRA_VDDIO_GMI,
-        TEGRA_VDDIO_PEXCTL,
-        TEGRA_VDDIO_SDMMC1,
-        TEGRA_VDDIO_SDMMC3,
-        TEGRA_VDDIO_SDMMC4,
-};
-struct tegra_pingroup_config {
-        int pingroup;
-        enum tegra_mux_func     func;
-        enum tegra_pullupdown   pupd;
-        enum tegra_tristate     tristate;
-};
-enum tegra_slew {
-        TEGRA_SLEW_FASTEST = 0,
-        TEGRA_SLEW_FAST,
-        TEGRA_SLEW_SLOW,
-        TEGRA_SLEW_SLOWEST,
-        TEGRA_MAX_SLEW,
-};
-enum tegra_pull_strength {
-        TEGRA_PULL_0 = 0,
-        TEGRA_PULL_1,
-        TEGRA_PULL_2,
-        TEGRA_PULL_3,
-        TEGRA_PULL_4,
-        TEGRA_PULL_5,
-        TEGRA_PULL_6,
-        TEGRA_PULL_7,
-        TEGRA_PULL_8,
-        TEGRA_PULL_9,
-        TEGRA_PULL_10,
-        TEGRA_PULL_11,
-        TEGRA_PULL_12,
-        TEGRA_PULL_13,
-        TEGRA_PULL_14,
-        TEGRA_PULL_15,
-        TEGRA_PULL_16,
-        TEGRA_PULL_17,
-        TEGRA_PULL_18,
-        TEGRA_PULL_19,
-        TEGRA_PULL_20,
-        TEGRA_PULL_21,
-        TEGRA_PULL_22,
-        TEGRA_PULL_23,
-        TEGRA_PULL_24,
-        TEGRA_PULL_25,
-        TEGRA_PULL_26,
-        TEGRA_PULL_27,
-        TEGRA_PULL_28,
-        TEGRA_PULL_29,
-        TEGRA_PULL_30,
-        TEGRA_PULL_31,
-        TEGRA_MAX_PULL,
-};
-enum tegra_drive {
-        TEGRA_DRIVE_DIV_8 = 0,
-        TEGRA_DRIVE_DIV_4,
-        TEGRA_DRIVE_DIV_2,
-        TEGRA_DRIVE_DIV_1,
-        TEGRA_MAX_DRIVE,
-};
-enum tegra_hsm {
-        TEGRA_HSM_DISABLE = 0,
-        TEGRA_HSM_ENABLE,
-};
-enum tegra_schmitt {
-        TEGRA_SCHMITT_DISABLE = 0,
-        TEGRA_SCHMITT_ENABLE,
-};
-struct tegra_drive_pingroup_config {
-        int pingroup;
-        enum tegra_hsm hsm;
-        enum tegra_schmitt schmitt;
-        enum tegra_drive drive;
-        enum tegra_pull_strength pull_down;
-        enum tegra_pull_strength pull_up;
-        enum tegra_slew slew_rising;
-        enum tegra_slew slew_falling;
-};
-struct tegra_drive_pingroup_desc {
-        const char *name;
-        s16 reg_bank;
-        s16 reg;
-};
-struct tegra_pingroup_desc {
-        const char *name;
-        int funcs[4];
-        int func_safe;
-        int vddio;
-        enum tegra_pin_io io_default;
-        s16 tri_bank;   /* Register bank the tri_reg exists within */
-        s16 mux_bank;   /* Register bank the mux_reg exists within */
-        s16 pupd_bank;  /* Register bank the pupd_reg exists within */
-        s16 tri_reg;    /* offset into the TRISTATE_REG_* register bank */
-        s16 mux_reg;    /* offset into the PIN_MUX_CTL_* register bank */
-        s16 pupd_reg;   /* offset into the PULL_UPDOWN_REG_* register bank */
-        s8 tri_bit;     /* offset into the TRISTATE_REG_* register bit */
-        s8 mux_bit;     /* offset into the PIN_MUX_CTL_* register bit */
-        s8 pupd_bit;    /* offset into the PULL_UPDOWN_REG_* register bit */
-        s8 lock_bit;    /* offset of the LOCK bit into mux register bit */
-        s8 od_bit;      /* offset of the OD bit into mux register bit */
-        s8 ioreset_bit; /* offset of the IO_RESET bit into mux register bit */
-};
-typedef void (*pinmux_init) (const struct tegra_pingroup_desc **pg,
-        int *pg_max, const struct tegra_drive_pingroup_desc **pgdrive,
-        int *pgdrive_max);
-void tegra20_pinmux_init(const struct tegra_pingroup_desc **pg, int *pg_max,
-        const struct tegra_drive_pingroup_desc **pgdrive, int *pgdrive_max);
-void tegra30_pinmux_init(const struct tegra_pingroup_desc **pg, int *pg_max,
-        const struct tegra_drive_pingroup_desc **pgdrive, int *pgdrive_max);
-int tegra_pinmux_set_tristate(int pg, enum tegra_tristate tristate);
-int tegra_pinmux_set_pullupdown(int pg, enum tegra_pullupdown pupd);
-void tegra_pinmux_config_table(const struct tegra_pingroup_config *config,
-        int len);
-void tegra_drive_pinmux_config_table(struct tegra_drive_pingroup_config *config,
-        int len);
-void tegra_pinmux_set_safe_pinmux_table(const struct tegra_pingroup_config *config,
-        int len);
-void tegra_pinmux_config_pinmux_table(const struct tegra_pingroup_config *config,
-        int len);
-void tegra_pinmux_config_tristate_table(const struct tegra_pingroup_config *config,
-        int len, enum tegra_tristate tristate);
-void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *config,
-        int len, enum tegra_pullupdown pupd);
-#endif
diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
index 54a816ff3847..0e09137506ec 100644
--- a/arch/arm/mach-tegra/pcie.c
+++ b/arch/arm/mach-tegra/pcie.c
@@ -475,7 +475,6 @@ static struct hw_pci tegra_pcie_hw __initdata = {
        .nr_controllers = 2,
        .setup          = tegra_pcie_setup,
        .scan           = tegra_pcie_scan_bus,
-        .swizzle        = pci_std_swizzle,
        .map_irq        = tegra_pcie_map_irq,
 };
diff --git a/arch/arm/mach-tegra/pinmux-tegra20-tables.c b/arch/arm/mach-tegra/pinmux-tegra20-tables.c
deleted file mode 100644
index 734add1280b7..000000000000
--- a/arch/arm/mach-tegra/pinmux-tegra20-tables.c
+++ /dev/null
@@ -1,244 +0,0 @@
-/*
- * linux/arch/arm/mach-tegra/pinmux-tegra20-tables.c
- *
- * Common pinmux configurations for Tegra20 SoCs
- *
- * Copyright (C) 2010 NVIDIA Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
- */
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/spinlock.h>
-#include <linux/io.h>
-#include <linux/init.h>
-#include <linux/string.h>
-#include <mach/iomap.h>
-#include <mach/pinmux.h>
-#include <mach/pinmux-tegra20.h>
-#include <mach/suspend.h>
-#define TRISTATE_REG_A          0x14
-#define PIN_MUX_CTL_REG_A       0x80
-#define PULLUPDOWN_REG_A        0xa0
-#define PINGROUP_REG_A          0x868
-#define DRIVE_PINGROUP(pg_name, r)                              \
-        [TEGRA_DRIVE_PINGROUP_ ## pg_name] = {                  \
-                .name = #pg_name,                               \
-                .reg_bank = 3,                                  \
-                .reg = ((r) - PINGROUP_REG_A)                   \
-        }
-static const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE_PINGROUP] = {
-        DRIVE_PINGROUP(AO1,             0x868),
-        DRIVE_PINGROUP(AO2,             0x86c),
-        DRIVE_PINGROUP(AT1,             0x870),
-        DRIVE_PINGROUP(AT2,             0x874),
-        DRIVE_PINGROUP(CDEV1,           0x878),
-        DRIVE_PINGROUP(CDEV2,           0x87c),
-        DRIVE_PINGROUP(CSUS,            0x880),
-        DRIVE_PINGROUP(DAP1,            0x884),
-        DRIVE_PINGROUP(DAP2,            0x888),
-        DRIVE_PINGROUP(DAP3,            0x88c),
-        DRIVE_PINGROUP(DAP4,            0x890),
-        DRIVE_PINGROUP(DBG,             0x894),
-        DRIVE_PINGROUP(LCD1,            0x898),
-        DRIVE_PINGROUP(LCD2,            0x89c),
-        DRIVE_PINGROUP(SDMMC2,          0x8a0),
-        DRIVE_PINGROUP(SDMMC3,          0x8a4),
-        DRIVE_PINGROUP(SPI,             0x8a8),
-        DRIVE_PINGROUP(UAA,             0x8ac),
-        DRIVE_PINGROUP(UAB,             0x8b0),
-        DRIVE_PINGROUP(UART2,           0x8b4),
-        DRIVE_PINGROUP(UART3,           0x8b8),
-        DRIVE_PINGROUP(VI1,             0x8bc),
-        DRIVE_PINGROUP(VI2,             0x8c0),
-        DRIVE_PINGROUP(XM2A,            0x8c4),
-        DRIVE_PINGROUP(XM2C,            0x8c8),
-        DRIVE_PINGROUP(XM2D,            0x8cc),
-        DRIVE_PINGROUP(XM2CLK,          0x8d0),
-        DRIVE_PINGROUP(MEMCOMP,         0x8d4),
-        DRIVE_PINGROUP(SDIO1,           0x8e0),
-        DRIVE_PINGROUP(CRT,             0x8ec),
-        DRIVE_PINGROUP(DDC,             0x8f0),
-        DRIVE_PINGROUP(GMA,             0x8f4),
-        DRIVE_PINGROUP(GMB,             0x8f8),
-        DRIVE_PINGROUP(GMC,             0x8fc),
-        DRIVE_PINGROUP(GMD,             0x900),
-        DRIVE_PINGROUP(GME,             0x904),
-        DRIVE_PINGROUP(OWR,             0x908),
-        DRIVE_PINGROUP(UAD,             0x90c),
-};
-#define PINGROUP(pg_name, vdd, f0, f1, f2, f3, f_safe,          \
-                 tri_r, tri_b, mux_r, mux_b, pupd_r, pupd_b)    \
-        [TEGRA_PINGROUP_ ## pg_name] = {                        \
-                .name = #pg_name,                               \
-                .vddio = TEGRA_VDDIO_ ## vdd,                   \
-                .funcs = {                                      \
-                        TEGRA_MUX_ ## f0,                       \
-                        TEGRA_MUX_ ## f1,                       \
-                        TEGRA_MUX_ ## f2,                       \
-                        TEGRA_MUX_ ## f3,                       \
-                },                                              \
-                .func_safe = TEGRA_MUX_ ## f_safe,              \
-                .tri_bank = 0,                                  \
-                .tri_reg = ((tri_r) - TRISTATE_REG_A),          \
-                .tri_bit = tri_b,                               \
-                .mux_bank = 1,                                  \
-                .mux_reg = ((mux_r) - PIN_MUX_CTL_REG_A),       \
-                .mux_bit = mux_b,                               \
-                .pupd_bank = 2,                         \
-                .pupd_reg = ((pupd_r) - PULLUPDOWN_REG_A),      \
-                .pupd_bit = pupd_b,                             \
-                .lock_bit = -1,                                 \
-                .od_bit = -1,                                   \
-                .ioreset_bit = -1,                              \
-                .io_default = -1,                               \
-        }
-static const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = {
-        PINGROUP(ATA,   NAND,  IDE,       NAND,      GMI,       RSVD,          IDE,       0x14, 0,  0x80, 24, 0xA0, 0),
-        PINGROUP(ATB,   NAND,  IDE,       NAND,      GMI,       SDIO4,         IDE,       0x14, 1,  0x80, 16, 0xA0, 2),
-        PINGROUP(ATC,   NAND,  IDE,       NAND,      GMI,       SDIO4,         IDE,       0x14, 2,  0x80, 22, 0xA0, 4),
-        PINGROUP(ATD,   NAND,  IDE,       NAND,      GMI,       SDIO4,         IDE,       0x14, 3,  0x80, 20, 0xA0, 6),
-        PINGROUP(ATE,   NAND,  IDE,       NAND,      GMI,       RSVD,          IDE,       0x18, 25, 0x80, 12, 0xA0, 8),
-        PINGROUP(CDEV1, AUDIO, OSC,       PLLA_OUT,  PLLM_OUT1, AUDIO_SYNC,    OSC,       0x14, 4,  0x88, 2,  0xA8, 0),
-        PINGROUP(CDEV2, AUDIO, OSC,       AHB_CLK,   APB_CLK,   PLLP_OUT4,     OSC,       0x14, 5,  0x88, 4,  0xA8, 2),
-        PINGROUP(CRTP,  LCD,   CRT,       RSVD,      RSVD,      RSVD,          RSVD,      0x20, 14, 0x98, 20, 0xA4, 24),
-        PINGROUP(CSUS,  VI,    PLLC_OUT1, PLLP_OUT2, PLLP_OUT3, VI_SENSOR_CLK, PLLC_OUT1, 0x14, 6,  0x88, 6,  0xAC, 24),
-        PINGROUP(DAP1,  AUDIO, DAP1,      RSVD,      GMI,       SDIO2,         DAP1,      0x14, 7,  0x88, 20, 0xA0, 10),
-        PINGROUP(DAP2,  AUDIO, DAP2,      TWC,       RSVD,      GMI,           DAP2,      0x14, 8,  0x88, 22, 0xA0, 12),
-        PINGROUP(DAP3,  BB,    DAP3,      RSVD,      RSVD,      RSVD,          DAP3,      0x14, 9,  0x88, 24, 0xA0, 14),
-        PINGROUP(DAP4,  UART,  DAP4,      RSVD,      GMI,       RSVD,          DAP4,      0x14, 10, 0x88, 26, 0xA0, 16),
-        PINGROUP(DDC,   LCD,   I2C2,      RSVD,      RSVD,      RSVD,          RSVD4,     0x18, 31, 0x88, 0,  0xB0, 28),
-        PINGROUP(DTA,   VI,    RSVD,      SDIO2,     VI,        RSVD,          RSVD4,     0x14, 11, 0x84, 20, 0xA0, 18),
-        PINGROUP(DTB,   VI,    RSVD,      RSVD,      VI,        SPI1,          RSVD1,     0x14, 12, 0x84, 22, 0xA0, 20),
-        PINGROUP(DTC,   VI,    RSVD,      RSVD,      VI,        RSVD,          RSVD1,     0x14, 13, 0x84, 26, 0xA0, 22),
-        PINGROUP(DTD,   VI,    RSVD,      SDIO2,     VI,        RSVD,          RSVD1,     0x14, 14, 0x84, 28, 0xA0, 24),
-        PINGROUP(DTE,   VI,    RSVD,      RSVD,      VI,        SPI1,          RSVD1,     0x14, 15, 0x84, 30, 0xA0, 26),
-        PINGROUP(DTF,   VI,    I2C3,      RSVD,      VI,        RSVD,          RSVD4,     0x20, 12, 0x98, 30, 0xA0, 28),
-        PINGROUP(GMA,   NAND,  UARTE,     SPI3,      GMI,       SDIO4,         SPI3,      0x14, 28, 0x84, 0,  0xB0, 20),
-        PINGROUP(GMB,   NAND,  IDE,       NAND,      GMI,       GMI_INT,       GMI,       0x18, 29, 0x88, 28, 0xB0, 22),
-        PINGROUP(GMC,   NAND,  UARTD,     SPI4,      GMI,       SFLASH,        SPI4,      0x14, 29, 0x84, 2,  0xB0, 24),
-        PINGROUP(GMD,   NAND,  RSVD,      NAND,      GMI,       SFLASH,        GMI,       0x18, 30, 0x88, 30, 0xB0, 26),
-        PINGROUP(GME,   NAND,  RSVD,      DAP5,      GMI,       SDIO4,         GMI,       0x18, 0,  0x8C, 0,  0xA8, 24),
-        PINGROUP(GPU,   UART,  PWM,       UARTA,     GMI,       RSVD,          RSVD4,     0x14, 16, 0x8C, 4,  0xA4, 20),
-        PINGROUP(GPU7,  SYS,   RTCK,      RSVD,      RSVD,      RSVD,          RTCK,      0x20, 11, 0x98, 28, 0xA4, 6),
-        PINGROUP(GPV,   SD,    PCIE,      RSVD,      RSVD,      RSVD,          PCIE,      0x14, 17, 0x8C, 2,  0xA0, 30),
-        PINGROUP(HDINT, LCD,   HDMI,      RSVD,      RSVD,      RSVD,          HDMI,      0x1C, 23, 0x84, 4,  0xAC, 22),
-        PINGROUP(I2CP,  SYS,   I2C,       RSVD,      RSVD,      RSVD,          RSVD4,     0x14, 18, 0x88, 8,  0xA4, 2),
-        PINGROUP(IRRX,  UART,  UARTA,     UARTB,     GMI,       SPI4,          UARTB,     0x14, 20, 0x88, 18, 0xA8, 22),
-        PINGROUP(IRTX,  UART,  UARTA,     UARTB,     GMI,       SPI4,          UARTB,     0x14, 19, 0x88, 16, 0xA8, 20),
-        PINGROUP(KBCA,  SYS,   KBC,       NAND,      SDIO2,     EMC_TEST0_DLL, KBC,       0x14, 22, 0x88, 10, 0xA4, 8),
-        PINGROUP(KBCB,  SYS,   KBC,       NAND,      SDIO2,     MIO,           KBC,       0x14, 21, 0x88, 12, 0xA4, 10),
-        PINGROUP(KBCC,  SYS,   KBC,       NAND,      TRACE,     EMC_TEST1_DLL, KBC,       0x18, 26, 0x88, 14, 0xA4, 12),
-        PINGROUP(KBCD,  SYS,   KBC,       NAND,      SDIO2,     MIO,           KBC,       0x20, 10, 0x98, 26, 0xA4, 14),
-        PINGROUP(KBCE,  SYS,   KBC,       NAND,      OWR,       RSVD,          KBC,       0x14, 26, 0x80, 28, 0xB0, 2),
-        PINGROUP(KBCF,  SYS,   KBC,       NAND,      TRACE,     MIO,           KBC,       0x14, 27, 0x80, 26, 0xB0, 0),
-        PINGROUP(LCSN,  LCD,   DISPLAYA,  DISPLAYB,  SPI3,      RSVD,          RSVD4,     0x1C, 31, 0x90, 12, 0xAC, 20),
-        PINGROUP(LD0,   LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 0,  0x94, 0,  0xAC, 12),
-        PINGROUP(LD1,   LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 1,  0x94, 2,  0xAC, 12),
-        PINGROUP(LD10,  LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 10, 0x94, 20, 0xAC, 12),
-        PINGROUP(LD11,  LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 11, 0x94, 22, 0xAC, 12),
-        PINGROUP(LD12,  LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 12, 0x94, 24, 0xAC, 12),
-        PINGROUP(LD13,  LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 13, 0x94, 26, 0xAC, 12),
-        PINGROUP(LD14,  LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 14, 0x94, 28, 0xAC, 12),
-        PINGROUP(LD15,  LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 15, 0x94, 30, 0xAC, 12),
-        PINGROUP(LD16,  LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 16, 0x98, 0,  0xAC, 12),
-        PINGROUP(LD17,  LCD,   DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          RSVD4,     0x1C, 17, 0x98, 2,  0xAC, 12),
-        PINGROUP(LD2,   LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 2,  0x94, 4,  0xAC, 12),
-        PINGROUP(LD3,   LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 3,  0x94, 6,  0xAC, 12),
-        PINGROUP(LD4,   LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 4,  0x94, 8,  0xAC, 12),
-        PINGROUP(LD5,   LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 5,  0x94, 10, 0xAC, 12),
-        PINGROUP(LD6,   LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 6,  0x94, 12, 0xAC, 12),
-        PINGROUP(LD7,   LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 7,  0x94, 14, 0xAC, 12),
-        PINGROUP(LD8,   LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 8,  0x94, 16, 0xAC, 12),
-        PINGROUP(LD9,   LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 9,  0x94, 18, 0xAC, 12),
-        PINGROUP(LDC,   LCD,   DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          RSVD4,     0x1C, 30, 0x90, 14, 0xAC, 20),
-        PINGROUP(LDI,   LCD,   DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          RSVD4,     0x20, 6,  0x98, 16, 0xAC, 18),
-        PINGROUP(LHP0,  LCD,   DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          RSVD4,     0x1C, 18, 0x98, 10, 0xAC, 16),
-        PINGROUP(LHP1,  LCD,   DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          RSVD4,     0x1C, 19, 0x98, 4,  0xAC, 14),
-        PINGROUP(LHP2,  LCD,   DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          RSVD4,     0x1C, 20, 0x98, 6,  0xAC, 14),
-        PINGROUP(LHS,   LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x20, 7,  0x90, 22, 0xAC, 22),
-        PINGROUP(LM0,   LCD,   DISPLAYA,  DISPLAYB,  SPI3,      RSVD,          RSVD4,     0x1C, 24, 0x90, 26, 0xAC, 22),
-        PINGROUP(LM1,   LCD,   DISPLAYA,  DISPLAYB,  RSVD,      CRT,           RSVD3,     0x1C, 25, 0x90, 28, 0xAC, 22),
-        PINGROUP(LPP,   LCD,   DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          RSVD4,     0x20, 8,  0x98, 14, 0xAC, 18),
-        PINGROUP(LPW0,  LCD,   DISPLAYA,  DISPLAYB,  SPI3,      HDMI,          DISPLAYA,  0x20, 3,  0x90, 0,  0xAC, 20),
-        PINGROUP(LPW1,  LCD,   DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          RSVD4,     0x20, 4,  0x90, 2,  0xAC, 20),
-        PINGROUP(LPW2,  LCD,   DISPLAYA,  DISPLAYB,  SPI3,      HDMI,          DISPLAYA,  0x20, 5,  0x90, 4,  0xAC, 20),
-        PINGROUP(LSC0,  LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 27, 0x90, 18, 0xAC, 22),
-        PINGROUP(LSC1,  LCD,   DISPLAYA,  DISPLAYB,  SPI3,      HDMI,          DISPLAYA,  0x1C, 28, 0x90, 20, 0xAC, 20),
-        PINGROUP(LSCK,  LCD,   DISPLAYA,  DISPLAYB,  SPI3,      HDMI,          DISPLAYA,  0x1C, 29, 0x90, 16, 0xAC, 20),
-        PINGROUP(LSDA,  LCD,   DISPLAYA,  DISPLAYB,  SPI3,      HDMI,          DISPLAYA,  0x20, 1,  0x90, 8,  0xAC, 20),
-        PINGROUP(LSDI,  LCD,   DISPLAYA,  DISPLAYB,  SPI3,      RSVD,          DISPLAYA,  0x20, 2,  0x90, 6,  0xAC, 20),
-        PINGROUP(LSPI,  LCD,   DISPLAYA,  DISPLAYB,  XIO,       HDMI,          DISPLAYA,  0x20, 0,  0x90, 10, 0xAC, 22),
-        PINGROUP(LVP0,  LCD,   DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          RSVD4,     0x1C, 21, 0x90, 30, 0xAC, 22),
-        PINGROUP(LVP1,  LCD,   DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          RSVD4,     0x1C, 22, 0x98, 8,  0xAC, 16),
-        PINGROUP(LVS,   LCD,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          RSVD4,     0x1C, 26, 0x90, 24, 0xAC, 22),
-        PINGROUP(OWC,   SYS,   OWR,       RSVD,      RSVD,      RSVD,          OWR,       0x14, 31, 0x84, 8,  0xB0, 30),
-        PINGROUP(PMC,   SYS,   PWR_ON,    PWR_INTR,  RSVD,      RSVD,          PWR_ON,    0x14, 23, 0x98, 18, -1,   -1),
-        PINGROUP(PTA,   NAND,  I2C2,      HDMI,      GMI,       RSVD,          RSVD4,     0x14, 24, 0x98, 22, 0xA4, 4),
-        PINGROUP(RM,    UART,  I2C,       RSVD,      RSVD,      RSVD,          RSVD4,     0x14, 25, 0x80, 14, 0xA4, 0),
-        PINGROUP(SDB,   SD,    UARTA,     PWM,       SDIO3,     SPI2,          PWM,       0x20, 15, 0x8C, 10, -1,   -1),
-        PINGROUP(SDC,   SD,    PWM,       TWC,       SDIO3,     SPI3,          TWC,       0x18, 1,  0x8C, 12, 0xAC, 28),
-        PINGROUP(SDD,   SD,    UARTA,     PWM,       SDIO3,     SPI3,          PWM,       0x18, 2,  0x8C, 14, 0xAC, 30),
-        PINGROUP(SDIO1, BB,    SDIO1,     RSVD,      UARTE,     UARTA,         RSVD2,     0x14, 30, 0x80, 30, 0xB0, 18),
-        PINGROUP(SLXA,  SD,    PCIE,      SPI4,      SDIO3,     SPI2,          PCIE,      0x18, 3,  0x84, 6,  0xA4, 22),
-        PINGROUP(SLXC,  SD,    SPDIF,     SPI4,      SDIO3,     SPI2,          SPI4,      0x18, 5,  0x84, 10, 0xA4, 26),
-        PINGROUP(SLXD,  SD,    SPDIF,     SPI4,      SDIO3,     SPI2,          SPI4,      0x18, 6,  0x84, 12, 0xA4, 28),
-        PINGROUP(SLXK,  SD,    PCIE,      SPI4,      SDIO3,     SPI2,          PCIE,      0x18, 7,  0x84, 14, 0xA4, 30),
-        PINGROUP(SPDI,  AUDIO, SPDIF,     RSVD,      I2C,       SDIO2,         RSVD2,     0x18, 8,  0x8C, 8,  0xA4, 16),
-        PINGROUP(SPDO,  AUDIO, SPDIF,     RSVD,      I2C,       SDIO2,         RSVD2,     0x18, 9,  0x8C, 6,  0xA4, 18),
-        PINGROUP(SPIA,  AUDIO, SPI1,      SPI2,      SPI3,      GMI,           GMI,       0x18, 10, 0x8C, 30, 0xA8, 4),
-        PINGROUP(SPIB,  AUDIO, SPI1,      SPI2,      SPI3,      GMI,           GMI,       0x18, 11, 0x8C, 28, 0xA8, 6),
-        PINGROUP(SPIC,  AUDIO, SPI1,      SPI2,      SPI3,      GMI,           GMI,       0x18, 12, 0x8C, 26, 0xA8, 8),
-        PINGROUP(SPID,  AUDIO, SPI2,      SPI1,      SPI2_ALT,  GMI,           GMI,       0x18, 13, 0x8C, 24, 0xA8, 10),
-        PINGROUP(SPIE,  AUDIO, SPI2,      SPI1,      SPI2_ALT,  GMI,           GMI,       0x18, 14, 0x8C, 22, 0xA8, 12),
-        PINGROUP(SPIF,  AUDIO, SPI3,      SPI1,      SPI2,      RSVD,          RSVD4,     0x18, 15, 0x8C, 20, 0xA8, 14),
-        PINGROUP(SPIG,  AUDIO, SPI3,      SPI2,      SPI2_ALT,  I2C,           SPI2_ALT,  0x18, 16, 0x8C, 18, 0xA8, 16),
-        PINGROUP(SPIH,  AUDIO, SPI3,      SPI2,      SPI2_ALT,  I2C,           SPI2_ALT,  0x18, 17, 0x8C, 16, 0xA8, 18),
-        PINGROUP(UAA,   BB,    SPI3,      MIPI_HS,   UARTA,     ULPI,          MIPI_HS,   0x18, 18, 0x80, 0,  0xAC, 0),
-        PINGROUP(UAB,   BB,    SPI2,      MIPI_HS,   UARTA,     ULPI,          MIPI_HS,   0x18, 19, 0x80, 2,  0xAC, 2),
-        PINGROUP(UAC,   BB,    OWR,       RSVD,      RSVD,      RSVD,          RSVD4,     0x18, 20, 0x80, 4,  0xAC, 4),
-        PINGROUP(UAD,   UART,  IRDA,      SPDIF,     UARTA,     SPI4,          SPDIF,     0x18, 21, 0x80, 6,  0xAC, 6),
-        PINGROUP(UCA,   UART,  UARTC,     RSVD,      GMI,       RSVD,          RSVD4,     0x18, 22, 0x84, 16, 0xAC, 8),
-        PINGROUP(UCB,   UART,  UARTC,     PWM,       GMI,       RSVD,          RSVD4,     0x18, 23, 0x84, 18, 0xAC, 10),
-        PINGROUP(UDA,   BB,    SPI1,      RSVD,      UARTD,     ULPI,          RSVD2,     0x20, 13, 0x80, 8,  0xB0, 16),
-        /* these pin groups only have pullup and pull down control */
-        PINGROUP(CK32,  SYS,   RSVD,      RSVD,      RSVD,      RSVD,          RSVD,      -1,   -1, -1,   -1, 0xB0, 14),
-        PINGROUP(DDRC,  DDR,   RSVD,      RSVD,      RSVD,      RSVD,          RSVD,      -1,   -1, -1,   -1, 0xAC, 26),
-        PINGROUP(PMCA,  SYS,   RSVD,      RSVD,      RSVD,      RSVD,          RSVD,      -1,   -1, -1,   -1, 0xB0, 4),
-        PINGROUP(PMCB,  SYS,   RSVD,      RSVD,      RSVD,      RSVD,          RSVD,      -1,   -1, -1,   -1, 0xB0, 6),
-        PINGROUP(PMCC,  SYS,   RSVD,      RSVD,      RSVD,      RSVD,          RSVD,      -1,   -1, -1,   -1, 0xB0, 8),
-        PINGROUP(PMCD,  SYS,   RSVD,      RSVD,      RSVD,      RSVD,          RSVD,      -1,   -1, -1,   -1, 0xB0, 10),
-        PINGROUP(PMCE,  SYS,   RSVD,      RSVD,      RSVD,      RSVD,          RSVD,      -1,   -1, -1,   -1, 0xB0, 12),
-        PINGROUP(XM2C,  DDR,   RSVD,      RSVD,      RSVD,      RSVD,          RSVD,      -1,   -1, -1,   -1, 0xA8, 30),
-        PINGROUP(XM2D,  DDR,   RSVD,      RSVD,      RSVD,      RSVD,          RSVD,      -1,   -1, -1,   -1, 0xA8, 28),
-};
-void __devinit tegra20_pinmux_init(const struct tegra_pingroup_desc **pg,
-                int *pg_max, const struct tegra_drive_pingroup_desc **pgdrive,
-                int *pgdrive_max)
-{
-        *pg = tegra_soc_pingroups;
-        *pg_max = TEGRA_MAX_PINGROUP;
-        *pgdrive = tegra_soc_drive_pingroups;
-        *pgdrive_max = TEGRA_MAX_DRIVE_PINGROUP;
-}
diff --git a/arch/arm/mach-tegra/pinmux-tegra30-tables.c b/arch/arm/mach-tegra/pinmux-tegra30-tables.c
deleted file mode 100644
index 14fc0e4c1c44..000000000000
--- a/arch/arm/mach-tegra/pinmux-tegra30-tables.c
+++ /dev/null
@@ -1,376 +0,0 @@
-/*
- * linux/arch/arm/mach-tegra/pinmux-tegra30-tables.c
- *
- * Common pinmux configurations for Tegra30 SoCs
- *
- * Copyright (C) 2010,2011 NVIDIA Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
- */
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/spinlock.h>
-#include <linux/io.h>
-#include <linux/init.h>
-#include <linux/string.h>
-#include <mach/iomap.h>
-#include <mach/pinmux.h>
-#include <mach/pinmux-tegra30.h>
-#include <mach/suspend.h>
-#define PINGROUP_REG_A  0x868
-#define MUXCTL_REG_A    0x3000
-#define DRIVE_PINGROUP(pg_name, r)              \
-        [TEGRA_DRIVE_PINGROUP_ ## pg_name] = {  \
-                .name = #pg_name,               \
-                .reg_bank = 0,                  \
-                .reg = ((r) - PINGROUP_REG_A)   \
-        }
-static const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE_PINGROUP] = {
-        DRIVE_PINGROUP(AO1,             0x868),
-        DRIVE_PINGROUP(AO2,             0x86c),
-        DRIVE_PINGROUP(AT1,             0x870),
-        DRIVE_PINGROUP(AT2,             0x874),
-        DRIVE_PINGROUP(AT3,             0x878),
-        DRIVE_PINGROUP(AT4,             0x87c),
-        DRIVE_PINGROUP(AT5,             0x880),
-        DRIVE_PINGROUP(CDEV1,           0x884),
-        DRIVE_PINGROUP(CDEV2,           0x888),
-        DRIVE_PINGROUP(CSUS,            0x88c),
-        DRIVE_PINGROUP(DAP1,            0x890),
-        DRIVE_PINGROUP(DAP2,            0x894),
-        DRIVE_PINGROUP(DAP3,            0x898),
-        DRIVE_PINGROUP(DAP4,            0x89c),
-        DRIVE_PINGROUP(DBG,             0x8a0),
-        DRIVE_PINGROUP(LCD1,            0x8a4),
-        DRIVE_PINGROUP(LCD2,            0x8a8),
-        DRIVE_PINGROUP(SDIO2,           0x8ac),
-        DRIVE_PINGROUP(SDIO3,           0x8b0),
-        DRIVE_PINGROUP(SPI,             0x8b4),
-        DRIVE_PINGROUP(UAA,             0x8b8),
-        DRIVE_PINGROUP(UAB,             0x8bc),
-        DRIVE_PINGROUP(UART2,           0x8c0),
-        DRIVE_PINGROUP(UART3,           0x8c4),
-        DRIVE_PINGROUP(VI1,             0x8c8),
-        DRIVE_PINGROUP(SDIO1,           0x8ec),
-        DRIVE_PINGROUP(CRT,             0x8f8),
-        DRIVE_PINGROUP(DDC,             0x8fc),
-        DRIVE_PINGROUP(GMA,             0x900),
-        DRIVE_PINGROUP(GMB,             0x904),
-        DRIVE_PINGROUP(GMC,             0x908),
-        DRIVE_PINGROUP(GMD,             0x90c),
-        DRIVE_PINGROUP(GME,             0x910),
-        DRIVE_PINGROUP(GMF,             0x914),
-        DRIVE_PINGROUP(GMG,             0x918),
-        DRIVE_PINGROUP(GMH,             0x91c),
-        DRIVE_PINGROUP(OWR,             0x920),
-        DRIVE_PINGROUP(UAD,             0x924),
-        DRIVE_PINGROUP(GPV,             0x928),
-        DRIVE_PINGROUP(DEV3,            0x92c),
-        DRIVE_PINGROUP(CEC,             0x938),
-};
-#define PINGROUP(pg_name, vdd, f0, f1, f2, f3, fs, iod, reg)    \
-        [TEGRA_PINGROUP_ ## pg_name] = {                        \
-                .name = #pg_name,                               \
-                .vddio = TEGRA_VDDIO_ ## vdd,                   \
-                .funcs = {                                      \
-                        TEGRA_MUX_ ## f0,                       \
-                        TEGRA_MUX_ ## f1,                       \
-                        TEGRA_MUX_ ## f2,                       \
-                        TEGRA_MUX_ ## f3,                       \
-                },                                              \
-                .func_safe = TEGRA_MUX_ ## fs,                  \
-                .tri_bank = 1,                                  \
-                .tri_reg = ((reg) - MUXCTL_REG_A),              \
-                .tri_bit = 4,                                   \
-                .mux_bank = 1,                                  \
-                .mux_reg = ((reg) - MUXCTL_REG_A),              \
-                .mux_bit = 0,                                   \
-                .pupd_bank = 1,                                 \
-                .pupd_reg = ((reg) - MUXCTL_REG_A),             \
-                .pupd_bit = 2,                                  \
-                .io_default = TEGRA_PIN_ ## iod,                \
-                .od_bit = 6,                                    \
-                .lock_bit = 7,                                  \
-                .ioreset_bit = 8,                               \
-        }
-static const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = {
-        /*       NAME             VDD       f0          f1          f2          f3          fSafe       io      reg */
-        PINGROUP(ULPI_DATA0,      BB,       SPI3,       HSI,        UARTA,      ULPI,       RSVD,       INPUT,  0x3000),
-        PINGROUP(ULPI_DATA1,      BB,       SPI3,       HSI,        UARTA,      ULPI,       RSVD,       INPUT,  0x3004),
-        PINGROUP(ULPI_DATA2,      BB,       SPI3,       HSI,        UARTA,      ULPI,       RSVD,       INPUT,  0x3008),
-        PINGROUP(ULPI_DATA3,      BB,       SPI3,       HSI,        UARTA,      ULPI,       RSVD,       INPUT,  0x300c),
-        PINGROUP(ULPI_DATA4,      BB,       SPI2,       HSI,        UARTA,      ULPI,       RSVD,       INPUT,  0x3010),
-        PINGROUP(ULPI_DATA5,      BB,       SPI2,       HSI,        UARTA,      ULPI,       RSVD,       INPUT,  0x3014),
-        PINGROUP(ULPI_DATA6,      BB,       SPI2,       HSI,        UARTA,      ULPI,       RSVD,       INPUT,  0x3018),
-        PINGROUP(ULPI_DATA7,      BB,       SPI2,       HSI,        UARTA,      ULPI,       RSVD,       INPUT,  0x301c),
-        PINGROUP(ULPI_CLK,        BB,       SPI1,       RSVD,       UARTD,      ULPI,       RSVD,       INPUT,  0x3020),
-        PINGROUP(ULPI_DIR,        BB,       SPI1,       RSVD,       UARTD,      ULPI,       RSVD,       INPUT,  0x3024),
-        PINGROUP(ULPI_NXT,        BB,       SPI1,       RSVD,       UARTD,      ULPI,       RSVD,       INPUT,  0x3028),
-        PINGROUP(ULPI_STP,        BB,       SPI1,       RSVD,       UARTD,      ULPI,       RSVD,       INPUT,  0x302c),
-        PINGROUP(DAP3_FS,         BB,       I2S2,       RSVD1,      DISPLAYA,   DISPLAYB,   RSVD,       INPUT,  0x3030),
-        PINGROUP(DAP3_DIN,        BB,       I2S2,       RSVD1,      DISPLAYA,   DISPLAYB,   RSVD,       INPUT,  0x3034),
-        PINGROUP(DAP3_DOUT,       BB,       I2S2,       RSVD1,      DISPLAYA,   DISPLAYB,   RSVD,       INPUT,  0x3038),
-        PINGROUP(DAP3_SCLK,       BB,       I2S2,       RSVD1,      DISPLAYA,   DISPLAYB,   RSVD,       INPUT,  0x303c),
-        PINGROUP(GPIO_PV0,        BB,       RSVD,       RSVD,       RSVD,       RSVD,       RSVD,       INPUT,  0x3040),
-        PINGROUP(GPIO_PV1,        BB,       RSVD,       RSVD,       RSVD,       RSVD,       RSVD,       INPUT,  0x3044),
-        PINGROUP(SDMMC1_CLK,      SDMMC1,   SDIO1,      RSVD1,      RSVD2,      INVALID,    RSVD,       INPUT,  0x3048),
-        PINGROUP(SDMMC1_CMD,      SDMMC1,   SDIO1,      RSVD1,      RSVD2,      INVALID,    RSVD,       INPUT,  0x304c),
-        PINGROUP(SDMMC1_DAT3,     SDMMC1,   SDIO1,      RSVD1,      UARTE,      INVALID,    RSVD,       INPUT,  0x3050),
-        PINGROUP(SDMMC1_DAT2,     SDMMC1,   SDIO1,      RSVD1,      UARTE,      INVALID,    RSVD,       INPUT,  0x3054),
-        PINGROUP(SDMMC1_DAT1,     SDMMC1,   SDIO1,      RSVD1,      UARTE,      INVALID,    RSVD,       INPUT,  0x3058),
-        PINGROUP(SDMMC1_DAT0,     SDMMC1,   SDIO1,      RSVD1,      UARTE,      INVALID,    RSVD,       INPUT,  0x305c),
-        PINGROUP(GPIO_PV2,        SDMMC1,   OWR,        RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x3060),
-        PINGROUP(GPIO_PV3,        SDMMC1,   INVALID,    RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x3064),
-        PINGROUP(CLK2_OUT,        SDMMC1,   EXTPERIPH2, RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x3068),
-        PINGROUP(CLK2_REQ,        SDMMC1,   DAP,        RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x306c),
-        PINGROUP(LCD_PWR1,        LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x3070),
-        PINGROUP(LCD_PWR2,        LCD,      DISPLAYA,   DISPLAYB,   SPI5,       INVALID,    RSVD,       OUTPUT, 0x3074),
-        PINGROUP(LCD_SDIN,        LCD,      DISPLAYA,   DISPLAYB,   SPI5,       RSVD,       RSVD,       OUTPUT, 0x3078),
-        PINGROUP(LCD_SDOUT,       LCD,      DISPLAYA,   DISPLAYB,   SPI5,       INVALID,    RSVD,       OUTPUT, 0x307c),
-        PINGROUP(LCD_WR_N,        LCD,      DISPLAYA,   DISPLAYB,   SPI5,       INVALID,    RSVD,       OUTPUT, 0x3080),
-        PINGROUP(LCD_CS0_N,       LCD,      DISPLAYA,   DISPLAYB,   SPI5,       RSVD,       RSVD,       OUTPUT, 0x3084),
-        PINGROUP(LCD_DC0,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x3088),
-        PINGROUP(LCD_SCK,         LCD,      DISPLAYA,   DISPLAYB,   SPI5,       INVALID,    RSVD,       OUTPUT, 0x308c),
-        PINGROUP(LCD_PWR0,        LCD,      DISPLAYA,   DISPLAYB,   SPI5,       INVALID,    RSVD,       OUTPUT, 0x3090),
-        PINGROUP(LCD_PCLK,        LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x3094),
-        PINGROUP(LCD_DE,          LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x3098),
-        PINGROUP(LCD_HSYNC,       LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x309c),
-        PINGROUP(LCD_VSYNC,       LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30a0),
-        PINGROUP(LCD_D0,          LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30a4),
-        PINGROUP(LCD_D1,          LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30a8),
-        PINGROUP(LCD_D2,          LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30ac),
-        PINGROUP(LCD_D3,          LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30b0),
-        PINGROUP(LCD_D4,          LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30b4),
-        PINGROUP(LCD_D5,          LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30b8),
-        PINGROUP(LCD_D6,          LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30bc),
-        PINGROUP(LCD_D7,          LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30c0),
-        PINGROUP(LCD_D8,          LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30c4),
-        PINGROUP(LCD_D9,          LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30c8),
-        PINGROUP(LCD_D10,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30cc),
-        PINGROUP(LCD_D11,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30d0),
-        PINGROUP(LCD_D12,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30d4),
-        PINGROUP(LCD_D13,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30d8),
-        PINGROUP(LCD_D14,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30dc),
-        PINGROUP(LCD_D15,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30e0),
-        PINGROUP(LCD_D16,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30e4),
-        PINGROUP(LCD_D17,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30e8),
-        PINGROUP(LCD_D18,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30ec),
-        PINGROUP(LCD_D19,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30f0),
-        PINGROUP(LCD_D20,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30f4),
-        PINGROUP(LCD_D21,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30f8),
-        PINGROUP(LCD_D22,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x30fc),
-        PINGROUP(LCD_D23,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x3100),
-        PINGROUP(LCD_CS1_N,       LCD,      DISPLAYA,   DISPLAYB,   SPI5,       RSVD2,      RSVD,       OUTPUT, 0x3104),
-        PINGROUP(LCD_M1,          LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x3108),
-        PINGROUP(LCD_DC1,         LCD,      DISPLAYA,   DISPLAYB,   RSVD1,      RSVD2,      RSVD,       OUTPUT, 0x310c),
-        PINGROUP(HDMI_INT,        LCD,      RSVD,       RSVD,       RSVD,       RSVD,       RSVD,       INPUT,  0x3110),
-        PINGROUP(DDC_SCL,         LCD,      I2C4,       RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x3114),
-        PINGROUP(DDC_SDA,         LCD,      I2C4,       RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x3118),
-        PINGROUP(CRT_HSYNC,       LCD,      CRT,        RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x311c),
-        PINGROUP(CRT_VSYNC,       LCD,      CRT,        RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x3120),
-        PINGROUP(VI_D0,           VI,       INVALID,    RSVD1,      VI,         RSVD2,      RSVD,       INPUT,  0x3124),
-        PINGROUP(VI_D1,           VI,       INVALID,    SDIO2,      VI,         RSVD1,      RSVD,       INPUT,  0x3128),
-        PINGROUP(VI_D2,           VI,       INVALID,    SDIO2,      VI,         RSVD1,      RSVD,       INPUT,  0x312c),
-        PINGROUP(VI_D3,           VI,       INVALID,    SDIO2,      VI,         RSVD1,      RSVD,       INPUT,  0x3130),
-        PINGROUP(VI_D4,           VI,       INVALID,    SDIO2,      VI,         RSVD1,      RSVD,       INPUT,  0x3134),
-        PINGROUP(VI_D5,           VI,       INVALID,    SDIO2,      VI,         RSVD1,      RSVD,       INPUT,  0x3138),
-        PINGROUP(VI_D6,           VI,       INVALID,    SDIO2,      VI,         RSVD1,      RSVD,       INPUT,  0x313c),
-        PINGROUP(VI_D7,           VI,       INVALID,    SDIO2,      VI,         RSVD1,      RSVD,       INPUT,  0x3140),
-        PINGROUP(VI_D8,           VI,       INVALID,    SDIO2,      VI,         RSVD1,      RSVD,       INPUT,  0x3144),
-        PINGROUP(VI_D9,           VI,       INVALID,    SDIO2,      VI,         RSVD1,      RSVD,       INPUT,  0x3148),
-        PINGROUP(VI_D10,          VI,       INVALID,    RSVD1,      VI,         RSVD2,      RSVD,       INPUT,  0x314c),
-        PINGROUP(VI_D11,          VI,       INVALID,    RSVD1,      VI,         RSVD2,      RSVD,       INPUT,  0x3150),
-        PINGROUP(VI_PCLK,         VI,       RSVD1,      SDIO2,      VI,         RSVD2,      RSVD,       INPUT,  0x3154),
-        PINGROUP(VI_MCLK,         VI,       VI,         INVALID,    INVALID,    INVALID,    RSVD,       INPUT,  0x3158),
-        PINGROUP(VI_VSYNC,        VI,       INVALID,    RSVD1,      VI,         RSVD2,      RSVD,       INPUT,  0x315c),
-        PINGROUP(VI_HSYNC,        VI,       INVALID,    RSVD1,      VI,         RSVD2,      RSVD,       INPUT,  0x3160),
-        PINGROUP(UART2_RXD,       UART,     IRDA,       SPDIF,      UARTA,      SPI4,       RSVD,       INPUT,  0x3164),
-        PINGROUP(UART2_TXD,       UART,     IRDA,       SPDIF,      UARTA,      SPI4,       RSVD,       INPUT,  0x3168),
-        PINGROUP(UART2_RTS_N,     UART,     UARTA,      UARTB,      GMI,        SPI4,       RSVD,       INPUT,  0x316c),
-        PINGROUP(UART2_CTS_N,     UART,     UARTA,      UARTB,      GMI,        SPI4,       RSVD,       INPUT,  0x3170),
-        PINGROUP(UART3_TXD,       UART,     UARTC,      RSVD1,      GMI,        RSVD2,      RSVD,       INPUT,  0x3174),
-        PINGROUP(UART3_RXD,       UART,     UARTC,      RSVD1,      GMI,        RSVD2,      RSVD,       INPUT,  0x3178),
-        PINGROUP(UART3_CTS_N,     UART,     UARTC,      RSVD1,      GMI,        RSVD2,      RSVD,       INPUT,  0x317c),
-        PINGROUP(UART3_RTS_N,     UART,     UARTC,      PWM0,       GMI,        RSVD2,      RSVD,       INPUT,  0x3180),
-        PINGROUP(GPIO_PU0,        UART,     OWR,        UARTA,      GMI,        RSVD1,      RSVD,       INPUT,  0x3184),
-        PINGROUP(GPIO_PU1,        UART,     RSVD1,      UARTA,      GMI,        RSVD2,      RSVD,       INPUT,  0x3188),
-        PINGROUP(GPIO_PU2,        UART,     RSVD1,      UARTA,      GMI,        RSVD2,      RSVD,       INPUT,  0x318c),
-        PINGROUP(GPIO_PU3,        UART,     PWM0,       UARTA,      GMI,        RSVD1,      RSVD,       INPUT,  0x3190),
-        PINGROUP(GPIO_PU4,        UART,     PWM1,       UARTA,      GMI,        RSVD1,      RSVD,       INPUT,  0x3194),
-        PINGROUP(GPIO_PU5,        UART,     PWM2,       UARTA,      GMI,        RSVD1,      RSVD,       INPUT,  0x3198),
-        PINGROUP(GPIO_PU6,        UART,     PWM3,       UARTA,      GMI,        RSVD1,      RSVD,       INPUT,  0x319c),
-        PINGROUP(GEN1_I2C_SDA,    UART,     I2C,        RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x31a0),
-        PINGROUP(GEN1_I2C_SCL,    UART,     I2C,        RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x31a4),
-        PINGROUP(DAP4_FS,         UART,     I2S3,       RSVD1,      GMI,        RSVD2,      RSVD,       INPUT,  0x31a8),
-        PINGROUP(DAP4_DIN,        UART,     I2S3,       RSVD1,      GMI,        RSVD2,      RSVD,       INPUT,  0x31ac),
-        PINGROUP(DAP4_DOUT,       UART,     I2S3,       RSVD1,      GMI,        RSVD2,      RSVD,       INPUT,  0x31b0),
-        PINGROUP(DAP4_SCLK,       UART,     I2S3,       RSVD1,      GMI,        RSVD2,      RSVD,       INPUT,  0x31b4),
-        PINGROUP(CLK3_OUT,        UART,     EXTPERIPH3, RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x31b8),
-        PINGROUP(CLK3_REQ,        UART,     DEV3,       RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x31bc),
-        PINGROUP(GMI_WP_N,        GMI,      RSVD1,      NAND,       GMI,        GMI_ALT,    RSVD,       INPUT,  0x31c0),
-        PINGROUP(GMI_IORDY,       GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x31c4),
-        PINGROUP(GMI_WAIT,        GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x31c8),
-        PINGROUP(GMI_ADV_N,       GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x31cc),
-        PINGROUP(GMI_CLK,         GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x31d0),
-        PINGROUP(GMI_CS0_N,       GMI,      RSVD1,      NAND,       GMI,        INVALID,    RSVD,       INPUT,  0x31d4),
-        PINGROUP(GMI_CS1_N,       GMI,      RSVD1,      NAND,       GMI,        DTV,        RSVD,       INPUT,  0x31d8),
-        PINGROUP(GMI_CS2_N,       GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x31dc),
-        PINGROUP(GMI_CS3_N,       GMI,      RSVD1,      NAND,       GMI,        GMI_ALT,    RSVD,       INPUT,  0x31e0),
-        PINGROUP(GMI_CS4_N,       GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x31e4),
-        PINGROUP(GMI_CS6_N,       GMI,      NAND,       NAND_ALT,   GMI,        SATA,       RSVD,       INPUT,  0x31e8),
-        PINGROUP(GMI_CS7_N,       GMI,      NAND,       NAND_ALT,   GMI,        GMI_ALT,    RSVD,       INPUT,  0x31ec),
-        PINGROUP(GMI_AD0,         GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x31f0),
-        PINGROUP(GMI_AD1,         GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x31f4),
-        PINGROUP(GMI_AD2,         GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x31f8),
-        PINGROUP(GMI_AD3,         GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x31fc),
-        PINGROUP(GMI_AD4,         GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x3200),
-        PINGROUP(GMI_AD5,         GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x3204),
-        PINGROUP(GMI_AD6,         GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x3208),
-        PINGROUP(GMI_AD7,         GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x320c),
-        PINGROUP(GMI_AD8,         GMI,      PWM0,       NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x3210),
-        PINGROUP(GMI_AD9,         GMI,      PWM1,       NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x3214),
-        PINGROUP(GMI_AD10,        GMI,      PWM2,       NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x3218),
-        PINGROUP(GMI_AD11,        GMI,      PWM3,       NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x321c),
-        PINGROUP(GMI_AD12,        GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x3220),
-        PINGROUP(GMI_AD13,        GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x3224),
-        PINGROUP(GMI_AD14,        GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x3228),
-        PINGROUP(GMI_AD15,        GMI,      RSVD1,      NAND,       GMI,        RSVD2,      RSVD,       INPUT,  0x322c),
-        PINGROUP(GMI_A16,         GMI,      UARTD,      SPI4,       GMI,        GMI_ALT,    RSVD,       INPUT,  0x3230),
-        PINGROUP(GMI_A17,         GMI,      UARTD,      SPI4,       GMI,        INVALID,    RSVD,       INPUT,  0x3234),
-        PINGROUP(GMI_A18,         GMI,      UARTD,      SPI4,       GMI,        INVALID,    RSVD,       INPUT,  0x3238),
-        PINGROUP(GMI_A19,         GMI,      UARTD,      SPI4,       GMI,        RSVD3,      RSVD,       INPUT,  0x323c),
-        PINGROUP(GMI_WR_N,        GMI,      RSVD1,      NAND,       GMI,        RSVD3,      RSVD,       INPUT,  0x3240),
-        PINGROUP(GMI_OE_N,        GMI,      RSVD1,      NAND,       GMI,        RSVD3,      RSVD,       INPUT,  0x3244),
-        PINGROUP(GMI_DQS,         GMI,      RSVD1,      NAND,       GMI,        RSVD3,      RSVD,       INPUT,  0x3248),
-        PINGROUP(GMI_RST_N,       GMI,      NAND,       NAND_ALT,   GMI,        RSVD3,      RSVD,       INPUT,  0x324c),
-        PINGROUP(GEN2_I2C_SCL,    GMI,      I2C2,       INVALID,    GMI,        RSVD3,      RSVD,       INPUT,  0x3250),
-        PINGROUP(GEN2_I2C_SDA,    GMI,      I2C2,       INVALID,    GMI,        RSVD3,      RSVD,       INPUT,  0x3254),
-        PINGROUP(SDMMC4_CLK,      SDMMC4,   INVALID,    NAND,       GMI,        SDIO4,      RSVD,       INPUT,  0x3258),
-        PINGROUP(SDMMC4_CMD,      SDMMC4,   I2C3,       NAND,       GMI,        SDIO4,      RSVD,       INPUT,  0x325c),
-        PINGROUP(SDMMC4_DAT0,     SDMMC4,   UARTE,      SPI3,       GMI,        SDIO4,      RSVD,       INPUT,  0x3260),
-        PINGROUP(SDMMC4_DAT1,     SDMMC4,   UARTE,      SPI3,       GMI,        SDIO4,      RSVD,       INPUT,  0x3264),
-        PINGROUP(SDMMC4_DAT2,     SDMMC4,   UARTE,      SPI3,       GMI,        SDIO4,      RSVD,       INPUT,  0x3268),
-        PINGROUP(SDMMC4_DAT3,     SDMMC4,   UARTE,      SPI3,       GMI,        SDIO4,      RSVD,       INPUT,  0x326c),
-        PINGROUP(SDMMC4_DAT4,     SDMMC4,   I2C3,       I2S4,       GMI,        SDIO4,      RSVD,       INPUT,  0x3270),
-        PINGROUP(SDMMC4_DAT5,     SDMMC4,   VGP3,       I2S4,       GMI,        SDIO4,      RSVD,       INPUT,  0x3274),
-        PINGROUP(SDMMC4_DAT6,     SDMMC4,   VGP4,       I2S4,       GMI,        SDIO4,      RSVD,       INPUT,  0x3278),
-        PINGROUP(SDMMC4_DAT7,     SDMMC4,   VGP5,       I2S4,       GMI,        SDIO4,      RSVD,       INPUT,  0x327c),
-        PINGROUP(SDMMC4_RST_N,    SDMMC4,   VGP6,       RSVD1,      RSVD2,      POPSDMMC4,  RSVD,       INPUT,  0x3280),
-        PINGROUP(CAM_MCLK,        CAM,      VI,         INVALID,    VI_ALT2,    POPSDMMC4,  RSVD,       INPUT,  0x3284),
-        PINGROUP(GPIO_PCC1,       CAM,      I2S4,       RSVD1,      RSVD2,      POPSDMMC4,  RSVD,       INPUT,  0x3288),
-        PINGROUP(GPIO_PBB0,       CAM,      I2S4,       RSVD1,      RSVD2,      POPSDMMC4,  RSVD,       INPUT,  0x328c),
-        PINGROUP(CAM_I2C_SCL,     CAM,      INVALID,    I2C3,       RSVD2,      POPSDMMC4,  RSVD,       INPUT,  0x3290),
-        PINGROUP(CAM_I2C_SDA,     CAM,      INVALID,    I2C3,       RSVD2,      POPSDMMC4,  RSVD,       INPUT,  0x3294),
-        PINGROUP(GPIO_PBB3,       CAM,      VGP3,       DISPLAYA,   DISPLAYB,   POPSDMMC4,  RSVD,       INPUT,  0x3298),
-        PINGROUP(GPIO_PBB4,       CAM,      VGP4,       DISPLAYA,   DISPLAYB,   POPSDMMC4,  RSVD,       INPUT,  0x329c),
-        PINGROUP(GPIO_PBB5,       CAM,      VGP5,       DISPLAYA,   DISPLAYB,   POPSDMMC4,  RSVD,       INPUT,  0x32a0),
-        PINGROUP(GPIO_PBB6,       CAM,      VGP6,       DISPLAYA,   DISPLAYB,   POPSDMMC4,  RSVD,       INPUT,  0x32a4),
-        PINGROUP(GPIO_PBB7,       CAM,      I2S4,       RSVD1,      RSVD2,      POPSDMMC4,  RSVD,       INPUT,  0x32a8),
-        PINGROUP(GPIO_PCC2,       CAM,      I2S4,       RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x32ac),
-        PINGROUP(JTAG_RTCK,       SYS,      RTCK,       RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x32b0),
-        PINGROUP(PWR_I2C_SCL,     SYS,      I2CPWR,     RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x32b4),
-        PINGROUP(PWR_I2C_SDA,     SYS,      I2CPWR,     RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x32b8),
-        PINGROUP(KB_ROW0,         SYS,      KBC,        INVALID,    RSVD2,      RSVD3,      RSVD,       INPUT,  0x32bc),
-        PINGROUP(KB_ROW1,         SYS,      KBC,        INVALID,    RSVD2,      RSVD3,      RSVD,       INPUT,  0x32c0),
-        PINGROUP(KB_ROW2,         SYS,      KBC,        INVALID,    RSVD2,      RSVD3,      RSVD,       INPUT,  0x32c4),
-        PINGROUP(KB_ROW3,         SYS,      KBC,        INVALID,    RSVD2,      INVALID,    RSVD,       INPUT,  0x32c8),
-        PINGROUP(KB_ROW4,         SYS,      KBC,        INVALID,    TRACE,      RSVD3,      RSVD,       INPUT,  0x32cc),
-        PINGROUP(KB_ROW5,         SYS,      KBC,        INVALID,    TRACE,      OWR,        RSVD,       INPUT,  0x32d0),
-        PINGROUP(KB_ROW6,         SYS,      KBC,        INVALID,    SDIO2,      INVALID,    RSVD,       INPUT,  0x32d4),
-        PINGROUP(KB_ROW7,         SYS,      KBC,        INVALID,    SDIO2,      INVALID,    RSVD,       INPUT,  0x32d8),
-        PINGROUP(KB_ROW8,         SYS,      KBC,        INVALID,    SDIO2,      INVALID,    RSVD,       INPUT,  0x32dc),
-        PINGROUP(KB_ROW9,         SYS,      KBC,        INVALID,    SDIO2,      INVALID,    RSVD,       INPUT,  0x32e0),
-        PINGROUP(KB_ROW10,        SYS,      KBC,        INVALID,    SDIO2,      INVALID,    RSVD,       INPUT,  0x32e4),
-        PINGROUP(KB_ROW11,        SYS,      KBC,        INVALID,    SDIO2,      INVALID,    RSVD,       INPUT,  0x32e8),
-        PINGROUP(KB_ROW12,        SYS,      KBC,        INVALID,    SDIO2,      INVALID,    RSVD,       INPUT,  0x32ec),
-        PINGROUP(KB_ROW13,        SYS,      KBC,        INVALID,    SDIO2,      INVALID,    RSVD,       INPUT,  0x32f0),
-        PINGROUP(KB_ROW14,        SYS,      KBC,        INVALID,    SDIO2,      INVALID,    RSVD,       INPUT,  0x32f4),
-        PINGROUP(KB_ROW15,        SYS,      KBC,        INVALID,    SDIO2,      INVALID,    RSVD,       INPUT,  0x32f8),
-        PINGROUP(KB_COL0,         SYS,      KBC,        INVALID,    TRACE,      INVALID,    RSVD,       INPUT,  0x32fc),
-        PINGROUP(KB_COL1,         SYS,      KBC,        INVALID,    TRACE,      INVALID,    RSVD,       INPUT,  0x3300),
-        PINGROUP(KB_COL2,         SYS,      KBC,        INVALID,    TRACE,      RSVD,       RSVD,       INPUT,  0x3304),
-        PINGROUP(KB_COL3,         SYS,      KBC,        INVALID,    TRACE,      RSVD,       RSVD,       INPUT,  0x3308),
-        PINGROUP(KB_COL4,         SYS,      KBC,        INVALID,    TRACE,      RSVD,       RSVD,       INPUT,  0x330c),
-        PINGROUP(KB_COL5,         SYS,      KBC,        INVALID,    TRACE,      RSVD,       RSVD,       INPUT,  0x3310),
-        PINGROUP(KB_COL6,         SYS,      KBC,        INVALID,    TRACE,      INVALID,    RSVD,       INPUT,  0x3314),
-        PINGROUP(KB_COL7,         SYS,      KBC,        INVALID,    TRACE,      INVALID,    RSVD,       INPUT,  0x3318),
-        PINGROUP(CLK_32K_OUT,     SYS,      BLINK,      RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x331c),
-        PINGROUP(SYS_CLK_REQ,     SYS,      SYSCLK,     RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x3320),
-        PINGROUP(CORE_PWR_REQ,    SYS,      RSVD,       RSVD,       RSVD,       RSVD,       RSVD,       INPUT,  0x3324),
-        PINGROUP(CPU_PWR_REQ,     SYS,      RSVD,       RSVD,       RSVD,       RSVD,       RSVD,       INPUT,  0x3328),
-        PINGROUP(PWR_INT_N,       SYS,      RSVD,       RSVD,       RSVD,       RSVD,       RSVD,       INPUT,  0x332c),
-        PINGROUP(CLK_32K_IN,      SYS,      RSVD,       RSVD,       RSVD,       RSVD,       RSVD,       INPUT,  0x3330),
-        PINGROUP(OWR,             SYS,      OWR,        RSVD,       RSVD,       RSVD,       RSVD,       INPUT,  0x3334),
-        PINGROUP(DAP1_FS,         AUDIO,    I2S0,       HDA,        GMI,        SDIO2,      RSVD,       INPUT,  0x3338),
-        PINGROUP(DAP1_DIN,        AUDIO,    I2S0,       HDA,        GMI,        SDIO2,      RSVD,       INPUT,  0x333c),
-        PINGROUP(DAP1_DOUT,       AUDIO,    I2S0,       HDA,        GMI,        SDIO2,      RSVD,       INPUT,  0x3340),
-        PINGROUP(DAP1_SCLK,       AUDIO,    I2S0,       HDA,        GMI,        SDIO2,      RSVD,       INPUT,  0x3344),
-        PINGROUP(CLK1_REQ,        AUDIO,    DAP,        HDA,        RSVD2,      RSVD3,      RSVD,       INPUT,  0x3348),
-        PINGROUP(CLK1_OUT,        AUDIO,    EXTPERIPH1, RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x334c),
-        PINGROUP(SPDIF_IN,        AUDIO,    SPDIF,      HDA,        INVALID,    DAPSDMMC2,  RSVD,       INPUT,  0x3350),
-        PINGROUP(SPDIF_OUT,       AUDIO,    SPDIF,      RSVD1,      INVALID,    DAPSDMMC2,  RSVD,       INPUT,  0x3354),
-        PINGROUP(DAP2_FS,         AUDIO,    I2S1,       HDA,        RSVD2,      GMI,        RSVD,       INPUT,  0x3358),
-        PINGROUP(DAP2_DIN,        AUDIO,    I2S1,       HDA,        RSVD2,      GMI,        RSVD,       INPUT,  0x335c),
-        PINGROUP(DAP2_DOUT,       AUDIO,    I2S1,       HDA,        RSVD2,      GMI,        RSVD,       INPUT,  0x3360),
-        PINGROUP(DAP2_SCLK,       AUDIO,    I2S1,       HDA,        RSVD2,      GMI,        RSVD,       INPUT,  0x3364),
-        PINGROUP(SPI2_MOSI,       AUDIO,    SPI6,       SPI2,       INVALID,    GMI,        RSVD,       INPUT,  0x3368),
-        PINGROUP(SPI2_MISO,       AUDIO,    SPI6,       SPI2,       INVALID,    GMI,        RSVD,       INPUT,  0x336c),
-        PINGROUP(SPI2_CS0_N,      AUDIO,    SPI6,       SPI2,       INVALID,    GMI,        RSVD,       INPUT,  0x3370),
-        PINGROUP(SPI2_SCK,        AUDIO,    SPI6,       SPI2,       INVALID,    GMI,        RSVD,       INPUT,  0x3374),
-        PINGROUP(SPI1_MOSI,       AUDIO,    SPI2,       SPI1,       INVALID,    GMI,        RSVD,       INPUT,  0x3378),
-        PINGROUP(SPI1_SCK,        AUDIO,    SPI2,       SPI1,       INVALID,    GMI,        RSVD,       INPUT,  0x337c),
-        PINGROUP(SPI1_CS0_N,      AUDIO,    SPI2,       SPI1,       INVALID,    GMI,        RSVD,       INPUT,  0x3380),
-        PINGROUP(SPI1_MISO,       AUDIO,    INVALID,    SPI1,       INVALID,    RSVD3,      RSVD,       INPUT,  0x3384),
-        PINGROUP(SPI2_CS1_N,      AUDIO,    INVALID,    SPI2,       INVALID,    INVALID,    RSVD,       INPUT,  0x3388),
-        PINGROUP(SPI2_CS2_N,      AUDIO,    INVALID,    SPI2,       INVALID,    INVALID,    RSVD,       INPUT,  0x338c),
-        PINGROUP(SDMMC3_CLK,      SDMMC3,   UARTA,      PWM2,       SDIO3,      INVALID,    RSVD,       INPUT,  0x3390),
-        PINGROUP(SDMMC3_CMD,      SDMMC3,   UARTA,      PWM3,       SDIO3,      INVALID,    RSVD,       INPUT,  0x3394),
-        PINGROUP(SDMMC3_DAT0,     SDMMC3,   RSVD,       RSVD1,      SDIO3,      INVALID,    RSVD,       INPUT,  0x3398),
-        PINGROUP(SDMMC3_DAT1,     SDMMC3,   RSVD,       RSVD1,      SDIO3,      INVALID,    RSVD,       INPUT,  0x339c),
-        PINGROUP(SDMMC3_DAT2,     SDMMC3,   RSVD,       PWM1,       SDIO3,      INVALID,    RSVD,       INPUT,  0x33a0),
-        PINGROUP(SDMMC3_DAT3,     SDMMC3,   RSVD,       PWM0,       SDIO3,      INVALID,    RSVD,       INPUT,  0x33a4),
-        PINGROUP(SDMMC3_DAT4,     SDMMC3,   PWM1,       INVALID,    SDIO3,      INVALID,    RSVD,       INPUT,  0x33a8),
-        PINGROUP(SDMMC3_DAT5,     SDMMC3,   PWM0,       INVALID,    SDIO3,      INVALID,    RSVD,       INPUT,  0x33ac),
-        PINGROUP(SDMMC3_DAT6,     SDMMC3,   SPDIF,      INVALID,    SDIO3,      INVALID,    RSVD,       INPUT,  0x33b0),
-        PINGROUP(SDMMC3_DAT7,     SDMMC3,   SPDIF,      INVALID,    SDIO3,      INVALID,    RSVD,       INPUT,  0x33b4),
-        PINGROUP(PEX_L0_PRSNT_N,  PEXCTL,   PCIE,       HDA,        RSVD2,      RSVD3,      RSVD,       INPUT,  0x33b8),
-        PINGROUP(PEX_L0_RST_N,    PEXCTL,   PCIE,       HDA,        RSVD2,      RSVD3,      RSVD,       INPUT,  0x33bc),
-        PINGROUP(PEX_L0_CLKREQ_N, PEXCTL,   PCIE,       HDA,        RSVD2,      RSVD3,      RSVD,       INPUT,  0x33c0),
-        PINGROUP(PEX_WAKE_N,      PEXCTL,   PCIE,       HDA,        RSVD2,      RSVD3,      RSVD,       INPUT,  0x33c4),
-        PINGROUP(PEX_L1_PRSNT_N,  PEXCTL,   PCIE,       HDA,        RSVD2,      RSVD3,      RSVD,       INPUT,  0x33c8),
-        PINGROUP(PEX_L1_RST_N,    PEXCTL,   PCIE,       HDA,        RSVD2,      RSVD3,      RSVD,       INPUT,  0x33cc),
-        PINGROUP(PEX_L1_CLKREQ_N, PEXCTL,   PCIE,       HDA,        RSVD2,      RSVD3,      RSVD,       INPUT,  0x33d0),
-        PINGROUP(PEX_L2_PRSNT_N,  PEXCTL,   PCIE,       HDA,        RSVD2,      RSVD3,      RSVD,       INPUT,  0x33d4),
-        PINGROUP(PEX_L2_RST_N,    PEXCTL,   PCIE,       HDA,        RSVD2,      RSVD3,      RSVD,       INPUT,  0x33d8),
-        PINGROUP(PEX_L2_CLKREQ_N, PEXCTL,   PCIE,       HDA,        RSVD2,      RSVD3,      RSVD,       INPUT,  0x33dc),
-        PINGROUP(HDMI_CEC,        SYS,      CEC,        RSVD1,      RSVD2,      RSVD3,      RSVD,       INPUT,  0x33e0),
-};
-void __devinit tegra30_pinmux_init(const struct tegra_pingroup_desc **pg,
-                int *pg_max, const struct tegra_drive_pingroup_desc **pgdrive,
-                int *pgdrive_max)
-{
-        *pg = tegra_soc_pingroups;
-        *pg_max = TEGRA_MAX_PINGROUP;
-        *pgdrive = tegra_soc_drive_pingroups;
-        *pgdrive_max = TEGRA_MAX_DRIVE_PINGROUP;
-}
diff --git a/arch/arm/mach-tegra/pinmux.c b/arch/arm/mach-tegra/pinmux.c
deleted file mode 100644
index ac35d2b76850..000000000000
--- a/arch/arm/mach-tegra/pinmux.c
+++ /dev/null
@@ -1,987 +0,0 @@
-/*
- * linux/arch/arm/mach-tegra/pinmux.c
- *
- * Copyright (C) 2010 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/spinlock.h>
-#include <linux/io.h>
-#include <linux/platform_device.h>
-#include <linux/of_device.h>
-#include <mach/iomap.h>
-#include <mach/pinmux.h>
-#define HSM_EN(reg)     (((reg) >> 2) & 0x1)
-#define SCHMT_EN(reg)   (((reg) >> 3) & 0x1)
-#define LPMD(reg)       (((reg) >> 4) & 0x3)
-#define DRVDN(reg)      (((reg) >> 12) & 0x1f)
-#define DRVUP(reg)      (((reg) >> 20) & 0x1f)
-#define SLWR(reg)       (((reg) >> 28) & 0x3)
-#define SLWF(reg)       (((reg) >> 30) & 0x3)
-static const struct tegra_pingroup_desc *pingroups;
-static const struct tegra_drive_pingroup_desc *drive_pingroups;
-static int pingroup_max;
-static int drive_max;
-static char *tegra_mux_names[TEGRA_MAX_MUX] = {
-        [TEGRA_MUX_AHB_CLK] = "AHB_CLK",
-        [TEGRA_MUX_APB_CLK] = "APB_CLK",
-        [TEGRA_MUX_AUDIO_SYNC] = "AUDIO_SYNC",
-        [TEGRA_MUX_CRT] = "CRT",
-        [TEGRA_MUX_DAP1] = "DAP1",
-        [TEGRA_MUX_DAP2] = "DAP2",
-        [TEGRA_MUX_DAP3] = "DAP3",
-        [TEGRA_MUX_DAP4] = "DAP4",
-        [TEGRA_MUX_DAP5] = "DAP5",
-        [TEGRA_MUX_DISPLAYA] = "DISPLAYA",
-        [TEGRA_MUX_DISPLAYB] = "DISPLAYB",
-        [TEGRA_MUX_EMC_TEST0_DLL] = "EMC_TEST0_DLL",
-        [TEGRA_MUX_EMC_TEST1_DLL] = "EMC_TEST1_DLL",
-        [TEGRA_MUX_GMI] = "GMI",
-        [TEGRA_MUX_GMI_INT] = "GMI_INT",
-        [TEGRA_MUX_HDMI] = "HDMI",
-        [TEGRA_MUX_I2C] = "I2C",
-        [TEGRA_MUX_I2C2] = "I2C2",
-        [TEGRA_MUX_I2C3] = "I2C3",
-        [TEGRA_MUX_IDE] = "IDE",
-        [TEGRA_MUX_IRDA] = "IRDA",
-        [TEGRA_MUX_KBC] = "KBC",
-        [TEGRA_MUX_MIO] = "MIO",
-        [TEGRA_MUX_MIPI_HS] = "MIPI_HS",
-        [TEGRA_MUX_NAND] = "NAND",
-        [TEGRA_MUX_OSC] = "OSC",
-        [TEGRA_MUX_OWR] = "OWR",
-        [TEGRA_MUX_PCIE] = "PCIE",
-        [TEGRA_MUX_PLLA_OUT] = "PLLA_OUT",
-        [TEGRA_MUX_PLLC_OUT1] = "PLLC_OUT1",
-        [TEGRA_MUX_PLLM_OUT1] = "PLLM_OUT1",
-        [TEGRA_MUX_PLLP_OUT2] = "PLLP_OUT2",
-        [TEGRA_MUX_PLLP_OUT3] = "PLLP_OUT3",
-        [TEGRA_MUX_PLLP_OUT4] = "PLLP_OUT4",
-        [TEGRA_MUX_PWM] = "PWM",
-        [TEGRA_MUX_PWR_INTR] = "PWR_INTR",
-        [TEGRA_MUX_PWR_ON] = "PWR_ON",
-        [TEGRA_MUX_RTCK] = "RTCK",
-        [TEGRA_MUX_SDIO1] = "SDIO1",
-        [TEGRA_MUX_SDIO2] = "SDIO2",
-        [TEGRA_MUX_SDIO3] = "SDIO3",
-        [TEGRA_MUX_SDIO4] = "SDIO4",
-        [TEGRA_MUX_SFLASH] = "SFLASH",
-        [TEGRA_MUX_SPDIF] = "SPDIF",
-        [TEGRA_MUX_SPI1] = "SPI1",
-        [TEGRA_MUX_SPI2] = "SPI2",
-        [TEGRA_MUX_SPI2_ALT] = "SPI2_ALT",
-        [TEGRA_MUX_SPI3] = "SPI3",
-        [TEGRA_MUX_SPI4] = "SPI4",
-        [TEGRA_MUX_TRACE] = "TRACE",
-        [TEGRA_MUX_TWC] = "TWC",
-        [TEGRA_MUX_UARTA] = "UARTA",
-        [TEGRA_MUX_UARTB] = "UARTB",
-        [TEGRA_MUX_UARTC] = "UARTC",
-        [TEGRA_MUX_UARTD] = "UARTD",
-        [TEGRA_MUX_UARTE] = "UARTE",
-        [TEGRA_MUX_ULPI] = "ULPI",
-        [TEGRA_MUX_VI] = "VI",
-        [TEGRA_MUX_VI_SENSOR_CLK] = "VI_SENSOR_CLK",
-        [TEGRA_MUX_XIO] = "XIO",
-        [TEGRA_MUX_BLINK] = "BLINK",
-        [TEGRA_MUX_CEC] = "CEC",
-        [TEGRA_MUX_CLK12] = "CLK12",
-        [TEGRA_MUX_DAP] = "DAP",
-        [TEGRA_MUX_DAPSDMMC2] = "DAPSDMMC2",
-        [TEGRA_MUX_DDR] = "DDR",
-        [TEGRA_MUX_DEV3] = "DEV3",
-        [TEGRA_MUX_DTV] = "DTV",
-        [TEGRA_MUX_VI_ALT1] = "VI_ALT1",
-        [TEGRA_MUX_VI_ALT2] = "VI_ALT2",
-        [TEGRA_MUX_VI_ALT3] = "VI_ALT3",
-        [TEGRA_MUX_EMC_DLL] = "EMC_DLL",
-        [TEGRA_MUX_EXTPERIPH1] = "EXTPERIPH1",
-        [TEGRA_MUX_EXTPERIPH2] = "EXTPERIPH2",
-        [TEGRA_MUX_EXTPERIPH3] = "EXTPERIPH3",
-        [TEGRA_MUX_GMI_ALT] = "GMI_ALT",
-        [TEGRA_MUX_HDA] = "HDA",
-        [TEGRA_MUX_HSI] = "HSI",
-        [TEGRA_MUX_I2C4] = "I2C4",
-        [TEGRA_MUX_I2C5] = "I2C5",
-        [TEGRA_MUX_I2CPWR] = "I2CPWR",
-        [TEGRA_MUX_I2S0] = "I2S0",
-        [TEGRA_MUX_I2S1] = "I2S1",
-        [TEGRA_MUX_I2S2] = "I2S2",
-        [TEGRA_MUX_I2S3] = "I2S3",
-        [TEGRA_MUX_I2S4] = "I2S4",
-        [TEGRA_MUX_NAND_ALT] = "NAND_ALT",
-        [TEGRA_MUX_POPSDIO4] = "POPSDIO4",
-        [TEGRA_MUX_POPSDMMC4] = "POPSDMMC4",
-        [TEGRA_MUX_PWM0] = "PWM0",
-        [TEGRA_MUX_PWM1] = "PWM2",
-        [TEGRA_MUX_PWM2] = "PWM2",
-        [TEGRA_MUX_PWM3] = "PWM3",
-        [TEGRA_MUX_SATA] = "SATA",
-        [TEGRA_MUX_SPI5] = "SPI5",
-        [TEGRA_MUX_SPI6] = "SPI6",
-        [TEGRA_MUX_SYSCLK] = "SYSCLK",
-        [TEGRA_MUX_VGP1] = "VGP1",
-        [TEGRA_MUX_VGP2] = "VGP2",
-        [TEGRA_MUX_VGP3] = "VGP3",
-        [TEGRA_MUX_VGP4] = "VGP4",
-        [TEGRA_MUX_VGP5] = "VGP5",
-        [TEGRA_MUX_VGP6] = "VGP6",
-        [TEGRA_MUX_SAFE] = "<safe>",
-};
-static const char *tegra_drive_names[TEGRA_MAX_DRIVE] = {
-        [TEGRA_DRIVE_DIV_8] = "DIV_8",
-        [TEGRA_DRIVE_DIV_4] = "DIV_4",
-        [TEGRA_DRIVE_DIV_2] = "DIV_2",
-        [TEGRA_DRIVE_DIV_1] = "DIV_1",
-};
-static const char *tegra_slew_names[TEGRA_MAX_SLEW] = {
-        [TEGRA_SLEW_FASTEST] = "FASTEST",
-        [TEGRA_SLEW_FAST] = "FAST",
-        [TEGRA_SLEW_SLOW] = "SLOW",
-        [TEGRA_SLEW_SLOWEST] = "SLOWEST",
-};
-static DEFINE_SPINLOCK(mux_lock);
-static const char *pingroup_name(int pg)
-{
-        if (pg < 0 || pg >=  pingroup_max)
-                return "<UNKNOWN>";
-        return pingroups[pg].name;
-}
-static const char *func_name(enum tegra_mux_func func)
-{
-        if (func == TEGRA_MUX_RSVD1)
-                return "RSVD1";
-        if (func == TEGRA_MUX_RSVD2)
-                return "RSVD2";
-        if (func == TEGRA_MUX_RSVD3)
-                return "RSVD3";
-        if (func == TEGRA_MUX_RSVD4)
-                return "RSVD4";
-        if (func == TEGRA_MUX_NONE)
-                return "NONE";
-        if (func < 0 || func >=  TEGRA_MAX_MUX)
-                return "<UNKNOWN>";
-        return tegra_mux_names[func];
-}
-static const char *tri_name(unsigned long val)
-{
-        return val ? "TRISTATE" : "NORMAL";
-}
-static const char *pupd_name(unsigned long val)
-{
-        switch (val) {
-        case 0:
-                return "NORMAL";
-        case 1:
-                return "PULL_DOWN";
-        case 2:
-                return "PULL_UP";
-        default:
-                return "RSVD";
-        }
-}
-static int nbanks;
-static void __iomem **regs;
-static inline u32 pg_readl(u32 bank, u32 reg)
-{
-        return readl(regs[bank] + reg);
-}
-static inline void pg_writel(u32 val, u32 bank, u32 reg)
-{
-        writel(val, regs[bank] + reg);
-}
-static int tegra_pinmux_set_func(const struct tegra_pingroup_config *config)
-{
-        int mux = -1;
-        int i;
-        unsigned long reg;
-        unsigned long flags;
-        int pg = config->pingroup;
-        enum tegra_mux_func func = config->func;
-        if (pg < 0 || pg >=  pingroup_max)
-                return -ERANGE;
-        if (pingroups[pg].mux_reg < 0)
-                return -EINVAL;
-        if (func < 0)
-                return -ERANGE;
-        if (func == TEGRA_MUX_SAFE)
-                func = pingroups[pg].func_safe;
-        if (func & TEGRA_MUX_RSVD) {
-                mux = func & 0x3;
-        } else {
-                for (i = 0; i < 4; i++) {
-                        if (pingroups[pg].funcs[i] == func) {
-                                mux = i;
-                                break;
-                        }
-                }
-        }
-        if (mux < 0)
-                return -EINVAL;
-        spin_lock_irqsave(&mux_lock, flags);
-        reg = pg_readl(pingroups[pg].mux_bank, pingroups[pg].mux_reg);
-        reg &= ~(0x3 << pingroups[pg].mux_bit);
-        reg |= mux << pingroups[pg].mux_bit;
-        pg_writel(reg, pingroups[pg].mux_bank, pingroups[pg].mux_reg);
-        spin_unlock_irqrestore(&mux_lock, flags);
-        return 0;
-}
-int tegra_pinmux_set_tristate(int pg, enum tegra_tristate tristate)
-{
-        unsigned long reg;
-        unsigned long flags;
-        if (pg < 0 || pg >=  pingroup_max)
-                return -ERANGE;
-        if (pingroups[pg].tri_reg < 0)
-                return -EINVAL;
-        spin_lock_irqsave(&mux_lock, flags);
-        reg = pg_readl(pingroups[pg].tri_bank, pingroups[pg].tri_reg);
-        reg &= ~(0x1 << pingroups[pg].tri_bit);
-        if (tristate)
-                reg |= 1 << pingroups[pg].tri_bit;
-        pg_writel(reg, pingroups[pg].tri_bank, pingroups[pg].tri_reg);
-        spin_unlock_irqrestore(&mux_lock, flags);
-        return 0;
-}
-int tegra_pinmux_set_pullupdown(int pg, enum tegra_pullupdown pupd)
-{
-        unsigned long reg;
-        unsigned long flags;
-        if (pg < 0 || pg >=  pingroup_max)
-                return -ERANGE;
-        if (pingroups[pg].pupd_reg < 0)
-                return -EINVAL;
-        if (pupd != TEGRA_PUPD_NORMAL &&
-            pupd != TEGRA_PUPD_PULL_DOWN &&
-            pupd != TEGRA_PUPD_PULL_UP)
-                return -EINVAL;
-        spin_lock_irqsave(&mux_lock, flags);
-        reg = pg_readl(pingroups[pg].pupd_bank, pingroups[pg].pupd_reg);
-        reg &= ~(0x3 << pingroups[pg].pupd_bit);
-        reg |= pupd << pingroups[pg].pupd_bit;
-        pg_writel(reg, pingroups[pg].pupd_bank, pingroups[pg].pupd_reg);
-        spin_unlock_irqrestore(&mux_lock, flags);
-        return 0;
-}
-static void tegra_pinmux_config_pingroup(const struct tegra_pingroup_config *config)
-{
-        int pingroup = config->pingroup;
-        enum tegra_mux_func func     = config->func;
-        enum tegra_pullupdown pupd   = config->pupd;
-        enum tegra_tristate tristate = config->tristate;
-        int err;
-        if (pingroups[pingroup].mux_reg >= 0) {
-                err = tegra_pinmux_set_func(config);
-                if (err < 0)
-                        pr_err("pinmux: can't set pingroup %s func to %s: %d\n",
-                               pingroup_name(pingroup), func_name(func), err);
-        }
-        if (pingroups[pingroup].pupd_reg >= 0) {
-                err = tegra_pinmux_set_pullupdown(pingroup, pupd);
-                if (err < 0)
-                        pr_err("pinmux: can't set pingroup %s pullupdown to %s: %d\n",
-                               pingroup_name(pingroup), pupd_name(pupd), err);
-        }
-        if (pingroups[pingroup].tri_reg >= 0) {
-                err = tegra_pinmux_set_tristate(pingroup, tristate);
-                if (err < 0)
-                        pr_err("pinmux: can't set pingroup %s tristate to %s: %d\n",
-                               pingroup_name(pingroup), tri_name(func), err);
-        }
-}
-void tegra_pinmux_config_table(const struct tegra_pingroup_config *config, int len)
-{
-        int i;
-        for (i = 0; i < len; i++)
-                tegra_pinmux_config_pingroup(&config[i]);
-}
-static const char *drive_pinmux_name(int pg)
-{
-        if (pg < 0 || pg >=  drive_max)
-                return "<UNKNOWN>";
-        return drive_pingroups[pg].name;
-}
-static const char *enable_name(unsigned long val)
-{
-        return val ? "ENABLE" : "DISABLE";
-}
-static const char *drive_name(unsigned long val)
-{
-        if (val >= TEGRA_MAX_DRIVE)
-                return "<UNKNOWN>";
-        return tegra_drive_names[val];
-}
-static const char *slew_name(unsigned long val)
-{
-        if (val >= TEGRA_MAX_SLEW)
-                return "<UNKNOWN>";
-        return tegra_slew_names[val];
-}
-static int tegra_drive_pinmux_set_hsm(int pg, enum tegra_hsm hsm)
-{
-        unsigned long flags;
-        u32 reg;
-        if (pg < 0 || pg >=  drive_max)
-                return -ERANGE;
-        if (hsm != TEGRA_HSM_ENABLE && hsm != TEGRA_HSM_DISABLE)
-                return -EINVAL;
-        spin_lock_irqsave(&mux_lock, flags);
-        reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
-        if (hsm == TEGRA_HSM_ENABLE)
-                reg |= (1 << 2);
-        else
-                reg &= ~(1 << 2);
-        pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
-        spin_unlock_irqrestore(&mux_lock, flags);
-        return 0;
-}
-static int tegra_drive_pinmux_set_schmitt(int pg, enum tegra_schmitt schmitt)
-{
-        unsigned long flags;
-        u32 reg;
-        if (pg < 0 || pg >=  drive_max)
-                return -ERANGE;
-        if (schmitt != TEGRA_SCHMITT_ENABLE && schmitt != TEGRA_SCHMITT_DISABLE)
-                return -EINVAL;
-        spin_lock_irqsave(&mux_lock, flags);
-        reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
-        if (schmitt == TEGRA_SCHMITT_ENABLE)
-                reg |= (1 << 3);
-        else
-                reg &= ~(1 << 3);
-        pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
-        spin_unlock_irqrestore(&mux_lock, flags);
-        return 0;
-}
-static int tegra_drive_pinmux_set_drive(int pg, enum tegra_drive drive)
-{
-        unsigned long flags;
-        u32 reg;
-        if (pg < 0 || pg >=  drive_max)
-                return -ERANGE;
-        if (drive < 0 || drive >= TEGRA_MAX_DRIVE)
-                return -EINVAL;
-        spin_lock_irqsave(&mux_lock, flags);
-        reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
-        reg &= ~(0x3 << 4);
-        reg |= drive << 4;
-        pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
-        spin_unlock_irqrestore(&mux_lock, flags);
-        return 0;
-}
-static int tegra_drive_pinmux_set_pull_down(int pg,
-        enum tegra_pull_strength pull_down)
-{
-        unsigned long flags;
-        u32 reg;
-        if (pg < 0 || pg >=  drive_max)
-                return -ERANGE;
-        if (pull_down < 0 || pull_down >= TEGRA_MAX_PULL)
-                return -EINVAL;
-        spin_lock_irqsave(&mux_lock, flags);
-        reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
-        reg &= ~(0x1f << 12);
-        reg |= pull_down << 12;
-        pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
-        spin_unlock_irqrestore(&mux_lock, flags);
-        return 0;
-}
-static int tegra_drive_pinmux_set_pull_up(int pg,
-        enum tegra_pull_strength pull_up)
-{
-        unsigned long flags;
-        u32 reg;
-        if (pg < 0 || pg >=  drive_max)
-                return -ERANGE;
-        if (pull_up < 0 || pull_up >= TEGRA_MAX_PULL)
-                return -EINVAL;
-        spin_lock_irqsave(&mux_lock, flags);
-        reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
-        reg &= ~(0x1f << 12);
-        reg |= pull_up << 12;
-        pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
-        spin_unlock_irqrestore(&mux_lock, flags);
-        return 0;
-}
-static int tegra_drive_pinmux_set_slew_rising(int pg,
-        enum tegra_slew slew_rising)
-{
-        unsigned long flags;
-        u32 reg;
-        if (pg < 0 || pg >=  drive_max)
-                return -ERANGE;
-        if (slew_rising < 0 || slew_rising >= TEGRA_MAX_SLEW)
-                return -EINVAL;
-        spin_lock_irqsave(&mux_lock, flags);
-        reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
-        reg &= ~(0x3 << 28);
-        reg |= slew_rising << 28;
-        pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
-        spin_unlock_irqrestore(&mux_lock, flags);
-        return 0;
-}
-static int tegra_drive_pinmux_set_slew_falling(int pg,
-        enum tegra_slew slew_falling)
-{
-        unsigned long flags;
-        u32 reg;
-        if (pg < 0 || pg >=  drive_max)
-                return -ERANGE;
-        if (slew_falling < 0 || slew_falling >= TEGRA_MAX_SLEW)
-                return -EINVAL;
-        spin_lock_irqsave(&mux_lock, flags);
-        reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
-        reg &= ~(0x3 << 30);
-        reg |= slew_falling << 30;
-        pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg);
-        spin_unlock_irqrestore(&mux_lock, flags);
-        return 0;
-}
-static void tegra_drive_pinmux_config_pingroup(int pingroup,
-                                          enum tegra_hsm hsm,
-                                          enum tegra_schmitt schmitt,
-                                          enum tegra_drive drive,
-                                          enum tegra_pull_strength pull_down,
-                                          enum tegra_pull_strength pull_up,
-                                          enum tegra_slew slew_rising,
-                                          enum tegra_slew slew_falling)
-{
-        int err;
-        err = tegra_drive_pinmux_set_hsm(pingroup, hsm);
-        if (err < 0)
-                pr_err("pinmux: can't set pingroup %s hsm to %s: %d\n",
-                        drive_pinmux_name(pingroup),
-                        enable_name(hsm), err);
-        err = tegra_drive_pinmux_set_schmitt(pingroup, schmitt);
-        if (err < 0)
-                pr_err("pinmux: can't set pingroup %s schmitt to %s: %d\n",
-                        drive_pinmux_name(pingroup),
-                        enable_name(schmitt), err);
-        err = tegra_drive_pinmux_set_drive(pingroup, drive);
-        if (err < 0)
-                pr_err("pinmux: can't set pingroup %s drive to %s: %d\n",
-                        drive_pinmux_name(pingroup),
-                        drive_name(drive), err);
-        err = tegra_drive_pinmux_set_pull_down(pingroup, pull_down);
-        if (err < 0)
-                pr_err("pinmux: can't set pingroup %s pull down to %d: %d\n",
-                        drive_pinmux_name(pingroup),
-                        pull_down, err);
-        err = tegra_drive_pinmux_set_pull_up(pingroup, pull_up);
-        if (err < 0)
-                pr_err("pinmux: can't set pingroup %s pull up to %d: %d\n",
-                        drive_pinmux_name(pingroup),
-                        pull_up, err);
-        err = tegra_drive_pinmux_set_slew_rising(pingroup, slew_rising);
-        if (err < 0)
-                pr_err("pinmux: can't set pingroup %s rising slew to %s: %d\n",
-                        drive_pinmux_name(pingroup),
-                        slew_name(slew_rising), err);
-        err = tegra_drive_pinmux_set_slew_falling(pingroup, slew_falling);
-        if (err < 0)
-                pr_err("pinmux: can't set pingroup %s falling slew to %s: %d\n",
-                        drive_pinmux_name(pingroup),
-                        slew_name(slew_falling), err);
-}
-void tegra_drive_pinmux_config_table(struct tegra_drive_pingroup_config *config,
-        int len)
-{
-        int i;
-        for (i = 0; i < len; i++)
-                tegra_drive_pinmux_config_pingroup(config[i].pingroup,
-                                                     config[i].hsm,
-                                                     config[i].schmitt,
-                                                     config[i].drive,
-                                                     config[i].pull_down,
-                                                     config[i].pull_up,
-                                                     config[i].slew_rising,
-                                                     config[i].slew_falling);
-}
-void tegra_pinmux_set_safe_pinmux_table(const struct tegra_pingroup_config *config,
-        int len)
-{
-        int i;
-        struct tegra_pingroup_config c;
-        for (i = 0; i < len; i++) {
-                int err;
-                c = config[i];
-                if (c.pingroup < 0 || c.pingroup >= pingroup_max) {
-                        WARN_ON(1);
-                        continue;
-                }
-                c.func = pingroups[c.pingroup].func_safe;
-                err = tegra_pinmux_set_func(&c);
-                if (err < 0)
-                        pr_err("%s: tegra_pinmux_set_func returned %d setting "
-                               "%s to %s\n", __func__, err,
-                               pingroup_name(c.pingroup), func_name(c.func));
-        }
-}
-void tegra_pinmux_config_pinmux_table(const struct tegra_pingroup_config *config,
-        int len)
-{
-        int i;
-        for (i = 0; i < len; i++) {
-                int err;
-                if (config[i].pingroup < 0 ||
-                    config[i].pingroup >= pingroup_max) {
-                        WARN_ON(1);
-                        continue;
-                }
-                err = tegra_pinmux_set_func(&config[i]);
-                if (err < 0)
-                        pr_err("%s: tegra_pinmux_set_func returned %d setting "
-                               "%s to %s\n", __func__, err,
-                               pingroup_name(config[i].pingroup),
-                               func_name(config[i].func));
-        }
-}
-void tegra_pinmux_config_tristate_table(const struct tegra_pingroup_config *config,
-        int len, enum tegra_tristate tristate)
-{
-        int i;
-        int err;
-        int pingroup;
-        for (i = 0; i < len; i++) {
-                pingroup = config[i].pingroup;
-                if (pingroups[pingroup].tri_reg >= 0) {
-                        err = tegra_pinmux_set_tristate(pingroup, tristate);
-                        if (err < 0)
-                                pr_err("pinmux: can't set pingroup %s tristate"
-                                        " to %s: %d\n", pingroup_name(pingroup),
-                                        tri_name(tristate), err);
-                }
-        }
-}
-void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *config,
-        int len, enum tegra_pullupdown pupd)
-{
-        int i;
-        int err;
-        int pingroup;
-        for (i = 0; i < len; i++) {
-                pingroup = config[i].pingroup;
-                if (pingroups[pingroup].pupd_reg >= 0) {
-                        err = tegra_pinmux_set_pullupdown(pingroup, pupd);
-                        if (err < 0)
-                                pr_err("pinmux: can't set pingroup %s pullupdown"
-                                        " to %s: %d\n", pingroup_name(pingroup),
-                                        pupd_name(pupd), err);
-                }
-        }
-}
-static struct of_device_id tegra_pinmux_of_match[] __devinitdata = {
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
-        { .compatible = "nvidia,tegra20-pinmux", tegra20_pinmux_init },
-#endif
-#ifdef CONFIG_ARCH_TEGRA_3x_SOC
-        { .compatible = "nvidia,tegra30-pinmux", tegra30_pinmux_init },
-#endif
-        { },
-};
-static int __devinit tegra_pinmux_probe(struct platform_device *pdev)
-{
-        struct resource *res;
-        int i;
-        int config_bad = 0;
-        const struct of_device_id *match;
-        match = of_match_device(tegra_pinmux_of_match, &pdev->dev);
-        if (match)
-                ((pinmux_init)(match->data))(&pingroups, &pingroup_max,
-                        &drive_pingroups, &drive_max);
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
-        else
-                /* no device tree available, so we must be on tegra20 */
-                tegra20_pinmux_init(&pingroups, &pingroup_max,
-                                        &drive_pingroups, &drive_max);
-#else
-        pr_warn("non Tegra20 platform requires pinmux devicetree node\n");
-#endif
-        for (i = 0; ; i++) {
-                res = platform_get_resource(pdev, IORESOURCE_MEM, i);
-                if (!res)
-                        break;
-        }
-        nbanks = i;
-        for (i = 0; i < pingroup_max; i++) {
-                if (pingroups[i].tri_bank >= nbanks) {
-                        dev_err(&pdev->dev, "pingroup %d: bad tri_bank\n", i);
-                        config_bad = 1;
-                }
-                if (pingroups[i].mux_bank >= nbanks) {
-                        dev_err(&pdev->dev, "pingroup %d: bad mux_bank\n", i);
-                        config_bad = 1;
-                }
-                if (pingroups[i].pupd_bank >= nbanks) {
-                        dev_err(&pdev->dev, "pingroup %d: bad pupd_bank\n", i);
-                        config_bad = 1;
-                }
-        }
-        for (i = 0; i < drive_max; i++) {
-                if (drive_pingroups[i].reg_bank >= nbanks) {
-                        dev_err(&pdev->dev,
-                                "drive pingroup %d: bad reg_bank\n", i);
-                        config_bad = 1;
-                }
-        }
-        if (config_bad)
-                return -ENODEV;
-        regs = devm_kzalloc(&pdev->dev, nbanks * sizeof(*regs), GFP_KERNEL);
-        if (!regs) {
-                dev_err(&pdev->dev, "Can't alloc regs pointer\n");
-                return -ENODEV;
-        }
-        for (i = 0; i < nbanks; i++) {
-                res = platform_get_resource(pdev, IORESOURCE_MEM, i);
-                if (!res) {
-                        dev_err(&pdev->dev, "Missing MEM resource\n");
-                        return -ENODEV;
-                }
-                if (!devm_request_mem_region(&pdev->dev, res->start,
-                                            resource_size(res),
-                                            dev_name(&pdev->dev))) {
-                        dev_err(&pdev->dev,
-                                "Couldn't request MEM resource %d\n", i);
-                        return -ENODEV;
-                }
-                regs[i] = devm_ioremap(&pdev->dev, res->start,
-                                        resource_size(res));
-                if (!regs) {
-                        dev_err(&pdev->dev, "Couldn't ioremap regs %d\n", i);
-                        return -ENODEV;
-                }
-        }
-        return 0;
-}
-static struct platform_driver tegra_pinmux_driver = {
-        .driver         = {
-                .name   = "tegra-pinmux",
-                .owner  = THIS_MODULE,
-                .of_match_table = tegra_pinmux_of_match,
-        },
-        .probe          = tegra_pinmux_probe,
-};
-static int __init tegra_pinmux_init(void)
-{
-        return platform_driver_register(&tegra_pinmux_driver);
-}
-postcore_initcall(tegra_pinmux_init);
-#ifdef  CONFIG_DEBUG_FS
-#include <linux/debugfs.h>
-#include <linux/seq_file.h>
-static void dbg_pad_field(struct seq_file *s, int len)
-{
-        seq_putc(s, ',');
-        while (len-- > -1)
-                seq_putc(s, ' ');
-}
-static int dbg_pinmux_show(struct seq_file *s, void *unused)
-{
-        int i;
-        int len;
-        for (i = 0; i < pingroup_max; i++) {
-                unsigned long reg;
-                unsigned long tri;
-                unsigned long mux;
-                unsigned long pupd;
-                seq_printf(s, "\t{TEGRA_PINGROUP_%s", pingroups[i].name);
-                len = strlen(pingroups[i].name);
-                dbg_pad_field(s, 5 - len);
-                if (pingroups[i].mux_reg < 0) {
-                        seq_printf(s, "TEGRA_MUX_NONE");
-                        len = strlen("NONE");
-                } else {
-                        reg = pg_readl(pingroups[i].mux_bank,
-                                        pingroups[i].mux_reg);
-                        mux = (reg >> pingroups[i].mux_bit) & 0x3;
-                        if (pingroups[i].funcs[mux] == TEGRA_MUX_RSVD) {
-                                seq_printf(s, "TEGRA_MUX_RSVD%1lu", mux+1);
-                                len = 5;
-                        } else {
-                                seq_printf(s, "TEGRA_MUX_%s",
-                                           tegra_mux_names[pingroups[i].funcs[mux]]);
-                                len = strlen(tegra_mux_names[pingroups[i].funcs[mux]]);
-                        }
-                }
-                dbg_pad_field(s, 13-len);
-                if (pingroups[i].pupd_reg < 0) {
-                        seq_printf(s, "TEGRA_PUPD_NORMAL");
-                        len = strlen("NORMAL");
-                } else {
-                        reg = pg_readl(pingroups[i].pupd_bank,
-                                        pingroups[i].pupd_reg);
-                        pupd = (reg >> pingroups[i].pupd_bit) & 0x3;
-                        seq_printf(s, "TEGRA_PUPD_%s", pupd_name(pupd));
-                        len = strlen(pupd_name(pupd));
-                }
-                dbg_pad_field(s, 9 - len);
-                if (pingroups[i].tri_reg < 0) {
-                        seq_printf(s, "TEGRA_TRI_NORMAL");
-                } else {
-                        reg = pg_readl(pingroups[i].tri_bank,
-                                        pingroups[i].tri_reg);
-                        tri = (reg >> pingroups[i].tri_bit) & 0x1;
-                        seq_printf(s, "TEGRA_TRI_%s", tri_name(tri));
-                }
-                seq_printf(s, "},\n");
-        }
-        return 0;
-}
-static int dbg_pinmux_open(struct inode *inode, struct file *file)
-{
-        return single_open(file, dbg_pinmux_show, &inode->i_private);
-}
-static const struct file_operations debug_fops = {
-        .open           = dbg_pinmux_open,
-        .read           = seq_read,
-        .llseek         = seq_lseek,
-        .release        = single_release,
-};
-static int dbg_drive_pinmux_show(struct seq_file *s, void *unused)
-{
-        int i;
-        int len;
-        for (i = 0; i < drive_max; i++) {
-                u32 reg;
-                seq_printf(s, "\t{TEGRA_DRIVE_PINGROUP_%s",
-                        drive_pingroups[i].name);
-                len = strlen(drive_pingroups[i].name);
-                dbg_pad_field(s, 7 - len);
-                reg = pg_readl(drive_pingroups[i].reg_bank,
-                                drive_pingroups[i].reg);
-                if (HSM_EN(reg)) {
-                        seq_printf(s, "TEGRA_HSM_ENABLE");
-                        len = 16;
-                } else {
-                        seq_printf(s, "TEGRA_HSM_DISABLE");
-                        len = 17;
-                }
-                dbg_pad_field(s, 17 - len);
-                if (SCHMT_EN(reg)) {
-                        seq_printf(s, "TEGRA_SCHMITT_ENABLE");
-                        len = 21;
-                } else {
-                        seq_printf(s, "TEGRA_SCHMITT_DISABLE");
-                        len = 22;
-                }
-                dbg_pad_field(s, 22 - len);
-                seq_printf(s, "TEGRA_DRIVE_%s", drive_name(LPMD(reg)));
-                len = strlen(drive_name(LPMD(reg)));
-                dbg_pad_field(s, 5 - len);
-                seq_printf(s, "TEGRA_PULL_%d", DRVDN(reg));
-                len = DRVDN(reg) < 10 ? 1 : 2;
-                dbg_pad_field(s, 2 - len);
-                seq_printf(s, "TEGRA_PULL_%d", DRVUP(reg));
-                len = DRVUP(reg) < 10 ? 1 : 2;
-                dbg_pad_field(s, 2 - len);
-                seq_printf(s, "TEGRA_SLEW_%s", slew_name(SLWR(reg)));
-                len = strlen(slew_name(SLWR(reg)));
-                dbg_pad_field(s, 7 - len);
-                seq_printf(s, "TEGRA_SLEW_%s", slew_name(SLWF(reg)));
-                seq_printf(s, "},\n");
-        }
-        return 0;
-}
-static int dbg_drive_pinmux_open(struct inode *inode, struct file *file)
-{
-        return single_open(file, dbg_drive_pinmux_show, &inode->i_private);
-}
-static const struct file_operations debug_drive_fops = {
-        .open           = dbg_drive_pinmux_open,
-        .read           = seq_read,
-        .llseek         = seq_lseek,
-        .release        = single_release,
-};
-static int __init tegra_pinmux_debuginit(void)
-{
-        (void) debugfs_create_file("tegra_pinmux", S_IRUGO,
-                                        NULL, NULL, &debug_fops);
-        (void) debugfs_create_file("tegra_pinmux_drive", S_IRUGO,
-                                        NULL, NULL, &debug_drive_fops);
-        return 0;
-}
-late_initcall(tegra_pinmux_debuginit);
-#endif
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
index 592a4eeb5328..2cae5cbc20ba 100644
--- a/arch/arm/mach-tegra/tegra2_clocks.c
+++ b/arch/arm/mach-tegra/tegra2_clocks.c
@@ -1764,6 +1764,12 @@ static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
        { 19200000, 760000000,  950,  24, 1, 8},
        { 26000000, 760000000,  760,  26, 1, 12},
+        /* 750 MHz */
+        { 12000000, 750000000,  750,  12, 1, 12},
+        { 13000000, 750000000,  750,  13, 1, 12},
+        { 19200000, 750000000,  625,  16, 1, 8},
+        { 26000000, 750000000,  750,  26, 1, 12},
        /* 608 MHz */
        { 12000000, 608000000,  608,  12, 1, 12},
        { 13000000, 608000000,  608,  13, 1, 12},
diff --git a/arch/arm/mach-tegra/timer.c b/arch/arm/mach-tegra/timer.c
index 1eed8d4a80ef..315672c7bd48 100644
--- a/arch/arm/mach-tegra/timer.c
+++ b/arch/arm/mach-tegra/timer.c
@@ -124,7 +124,7 @@ static u64 tegra_rtc_read_ms(void)
 }
 /*
- * read_persistent_clock -  Return time from a persistent clock.
+ * tegra_read_persistent_clock -  Return time from a persistent clock.
 *
 * Reads the time from a source which isn't disabled during PM, the
 * 32k sync timer.  Convert the cycles elapsed since last read into
@@ -133,7 +133,7 @@ static u64 tegra_rtc_read_ms(void)
 * tegra_rtc driver could be executing to avoid race conditions
 * on the RTC shadow register
 */
-void read_persistent_clock(struct timespec *ts)
+static void tegra_read_persistent_clock(struct timespec *ts)
 {
        u64 delta;
        struct timespec *tsp = &persistent_ts;
@@ -243,6 +243,7 @@ static void __init tegra_init_timer(void)
        tegra_clockevent.irq = tegra_timer_irq.irq;
        clockevents_register_device(&tegra_clockevent);
        tegra_twd_init();
+        register_persistent_clock(NULL, tegra_read_persistent_clock);
 }
 struct sys_timer tegra_timer = {
diff --git a/arch/arm/mach-tegra/usb_phy.c b/arch/arm/mach-tegra/usb_phy.c
index c5b2ac04e2a0..d71d2fed6721 100644
--- a/arch/arm/mach-tegra/usb_phy.c
+++ b/arch/arm/mach-tegra/usb_phy.c
@@ -711,7 +711,6 @@ struct tegra_usb_phy *tegra_usb_phy_open(int instance, void __iomem *regs,
                        err = -ENXIO;
                        goto err1;
                }
-                tegra_gpio_enable(ulpi_config->reset_gpio);
                gpio_request(ulpi_config->reset_gpio, "ulpi_phy_reset_b");
                gpio_direction_output(ulpi_config->reset_gpio, 0);
                phy->ulpi = otg_ulpi_create(&ulpi_viewport_access_ops, 0);
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index 1621ad07d284..33339745d432 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -1667,8 +1667,10 @@ void __init u300_init_irq(void)
        for (i = 0; i < U300_VIC_IRQS_END; i++)
                set_bit(i, (unsigned long *) &mask[0]);
-        vic_init((void __iomem *) U300_INTCON0_VBASE, 0, mask[0], mask[0]);
+        vic_init((void __iomem *) U300_INTCON0_VBASE, IRQ_U300_INTCON0_START,
-        vic_init((void __iomem *) U300_INTCON1_VBASE, 32, mask[1], mask[1]);
+                 mask[0], mask[0]);
+        vic_init((void __iomem *) U300_INTCON1_VBASE, IRQ_U300_INTCON1_START,
+                 mask[1], mask[1]);
 }
diff --git a/arch/arm/mach-u300/i2c.c b/arch/arm/mach-u300/i2c.c
index a38f80238ea9..cb04bd6ab3e7 100644
--- a/arch/arm/mach-u300/i2c.c
+++ b/arch/arm/mach-u300/i2c.c
@@ -146,9 +146,6 @@ static struct ab3100_platform_data ab3100_plf_data = {
                                .min_uV = 1800000,
                                .max_uV = 1800000,
                                .valid_modes_mask = REGULATOR_MODE_NORMAL,
-                                .valid_ops_mask =
-                                REGULATOR_CHANGE_VOLTAGE |
-                                REGULATOR_CHANGE_STATUS,
                                .always_on = 1,
                                .boot_on = 1,
                        },
@@ -160,9 +157,6 @@ static struct ab3100_platform_data ab3100_plf_data = {
                                .min_uV = 2500000,
                                .max_uV = 2500000,
                                .valid_modes_mask = REGULATOR_MODE_NORMAL,
-                                .valid_ops_mask =
-                                REGULATOR_CHANGE_VOLTAGE |
-                                REGULATOR_CHANGE_STATUS,
                                .always_on = 1,
                                .boot_on = 1,
                        },
@@ -230,8 +224,7 @@ static struct ab3100_platform_data ab3100_plf_data = {
                                .max_uV = 1800000,
                                .valid_modes_mask = REGULATOR_MODE_NORMAL,
                                .valid_ops_mask =
-                                REGULATOR_CHANGE_VOLTAGE |
+                                REGULATOR_CHANGE_VOLTAGE,
-                                REGULATOR_CHANGE_STATUS,
                                .always_on = 1,
                                .boot_on = 1,
                        },
diff --git a/arch/arm/mach-u300/include/mach/irqs.h b/arch/arm/mach-u300/include/mach/irqs.h
index ee78a26707eb..ec09c1e07b1a 100644
--- a/arch/arm/mach-u300/include/mach/irqs.h
+++ b/arch/arm/mach-u300/include/mach/irqs.h
@@ -12,101 +12,101 @@
 #ifndef __MACH_IRQS_H
 #define __MACH_IRQS_H
-#define IRQ_U300_INTCON0_START          0
+#define IRQ_U300_INTCON0_START          1
-#define IRQ_U300_INTCON1_START          32
+#define IRQ_U300_INTCON1_START          33
 /* These are on INTCON0 - 30 lines */
-#define IRQ_U300_IRQ0_EXT               0
+#define IRQ_U300_IRQ0_EXT               1
-#define IRQ_U300_IRQ1_EXT               1
+#define IRQ_U300_IRQ1_EXT               2
-#define IRQ_U300_DMA                    2
+#define IRQ_U300_DMA                    3
-#define IRQ_U300_VIDEO_ENC_0            3
+#define IRQ_U300_VIDEO_ENC_0            4
-#define IRQ_U300_VIDEO_ENC_1            4
+#define IRQ_U300_VIDEO_ENC_1            5
-#define IRQ_U300_AAIF_RX                5
+#define IRQ_U300_AAIF_RX                6
-#define IRQ_U300_AAIF_TX                6
+#define IRQ_U300_AAIF_TX                7
-#define IRQ_U300_AAIF_VGPIO             7
+#define IRQ_U300_AAIF_VGPIO             8
-#define IRQ_U300_AAIF_WAKEUP            8
+#define IRQ_U300_AAIF_WAKEUP            9
-#define IRQ_U300_PCM_I2S0_FRAME         9
+#define IRQ_U300_PCM_I2S0_FRAME         10
-#define IRQ_U300_PCM_I2S0_FIFO          10
+#define IRQ_U300_PCM_I2S0_FIFO          11
-#define IRQ_U300_PCM_I2S1_FRAME         11
+#define IRQ_U300_PCM_I2S1_FRAME         12
-#define IRQ_U300_PCM_I2S1_FIFO          12
+#define IRQ_U300_PCM_I2S1_FIFO          13
-#define IRQ_U300_XGAM_GAMCON            13
+#define IRQ_U300_XGAM_GAMCON            14
-#define IRQ_U300_XGAM_CDI               14
+#define IRQ_U300_XGAM_CDI               15
-#define IRQ_U300_XGAM_CDICON            15
+#define IRQ_U300_XGAM_CDICON            16
 #if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
 /* MMIACC not used on the DB3210 or DB3350 chips */
-#define IRQ_U300_XGAM_MMIACC            16
+#define IRQ_U300_XGAM_MMIACC            17
 #endif
-#define IRQ_U300_XGAM_PDI               17
+#define IRQ_U300_XGAM_PDI               18
-#define IRQ_U300_XGAM_PDICON            18
+#define IRQ_U300_XGAM_PDICON            19
-#define IRQ_U300_XGAM_GAMEACC           19
+#define IRQ_U300_XGAM_GAMEACC           20
-#define IRQ_U300_XGAM_MCIDCT            20
+#define IRQ_U300_XGAM_MCIDCT            21
-#define IRQ_U300_APEX                   21
+#define IRQ_U300_APEX                   22
-#define IRQ_U300_UART0                  22
+#define IRQ_U300_UART0                  23
-#define IRQ_U300_SPI                    23
+#define IRQ_U300_SPI                    24
-#define IRQ_U300_TIMER_APP_OS           24
+#define IRQ_U300_TIMER_APP_OS           25
-#define IRQ_U300_TIMER_APP_DD           25
+#define IRQ_U300_TIMER_APP_DD           26
-#define IRQ_U300_TIMER_APP_GP1          26
+#define IRQ_U300_TIMER_APP_GP1          27
-#define IRQ_U300_TIMER_APP_GP2          27
+#define IRQ_U300_TIMER_APP_GP2          28
-#define IRQ_U300_TIMER_OS               28
+#define IRQ_U300_TIMER_OS               29
-#define IRQ_U300_TIMER_MS               29
+#define IRQ_U300_TIMER_MS               30
-#define IRQ_U300_KEYPAD_KEYBF           30
+#define IRQ_U300_KEYPAD_KEYBF           31
-#define IRQ_U300_KEYPAD_KEYBR           31
+#define IRQ_U300_KEYPAD_KEYBR           32
 /* These are on INTCON1 - 32 lines */
-#define IRQ_U300_GPIO_PORT0             32
+#define IRQ_U300_GPIO_PORT0             33
-#define IRQ_U300_GPIO_PORT1             33
+#define IRQ_U300_GPIO_PORT1             34
-#define IRQ_U300_GPIO_PORT2             34
+#define IRQ_U300_GPIO_PORT2             35
 #if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330) || \
    defined(CONFIG_MACH_U300_BS335)
 /* These are for DB3150, DB3200 and DB3350 */
-#define IRQ_U300_WDOG                   35
+#define IRQ_U300_WDOG                   36
-#define IRQ_U300_EVHIST                 36
+#define IRQ_U300_EVHIST                 37
-#define IRQ_U300_MSPRO                  37
+#define IRQ_U300_MSPRO                  38
-#define IRQ_U300_MMCSD_MCIINTR0         38
+#define IRQ_U300_MMCSD_MCIINTR0         39
-#define IRQ_U300_MMCSD_MCIINTR1         39
+#define IRQ_U300_MMCSD_MCIINTR1         40
-#define IRQ_U300_I2C0                   40
+#define IRQ_U300_I2C0                   41
-#define IRQ_U300_I2C1                   41
+#define IRQ_U300_I2C1                   42
-#define IRQ_U300_RTC                    42
+#define IRQ_U300_RTC                    43
-#define IRQ_U300_NFIF                   43
+#define IRQ_U300_NFIF                   44
-#define IRQ_U300_NFIF2                  44
+#define IRQ_U300_NFIF2                  45
 #endif
 /* DB3150 and DB3200 have only 45 IRQs */
 #if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
-#define U300_VIC_IRQS_END               45
+#define U300_VIC_IRQS_END               46
 #endif
 /* The DB3350-specific interrupt lines */
 #ifdef CONFIG_MACH_U300_BS335
-#define IRQ_U300_ISP_F0                 45
+#define IRQ_U300_ISP_F0                 46
-#define IRQ_U300_ISP_F1                 46
+#define IRQ_U300_ISP_F1                 47
-#define IRQ_U300_ISP_F2                 47
+#define IRQ_U300_ISP_F2                 48
-#define IRQ_U300_ISP_F3                 48
+#define IRQ_U300_ISP_F3                 49
-#define IRQ_U300_ISP_F4                 49
+#define IRQ_U300_ISP_F4                 50
-#define IRQ_U300_GPIO_PORT3             50
+#define IRQ_U300_GPIO_PORT3             51
-#define IRQ_U300_SYSCON_PLL_LOCK        51
+#define IRQ_U300_SYSCON_PLL_LOCK        52
-#define IRQ_U300_UART1                  52
+#define IRQ_U300_UART1                  53
-#define IRQ_U300_GPIO_PORT4             53
+#define IRQ_U300_GPIO_PORT4             54
-#define IRQ_U300_GPIO_PORT5             54
+#define IRQ_U300_GPIO_PORT5             55
-#define IRQ_U300_GPIO_PORT6             55
+#define IRQ_U300_GPIO_PORT6             56
-#define U300_VIC_IRQS_END               56
+#define U300_VIC_IRQS_END               57
 #endif
 /* The DB3210-specific interrupt lines */
 #ifdef CONFIG_MACH_U300_BS365
-#define IRQ_U300_GPIO_PORT3             35
+#define IRQ_U300_GPIO_PORT3             36
-#define IRQ_U300_GPIO_PORT4             36
+#define IRQ_U300_GPIO_PORT4             37
-#define IRQ_U300_WDOG                   37
+#define IRQ_U300_WDOG                   38
-#define IRQ_U300_EVHIST                 38
+#define IRQ_U300_EVHIST                 39
-#define IRQ_U300_MSPRO                  39
+#define IRQ_U300_MSPRO                  40
-#define IRQ_U300_MMCSD_MCIINTR0         40
+#define IRQ_U300_MMCSD_MCIINTR0         41
-#define IRQ_U300_MMCSD_MCIINTR1         41
+#define IRQ_U300_MMCSD_MCIINTR1         42
-#define IRQ_U300_I2C0                   42
+#define IRQ_U300_I2C0                   43
-#define IRQ_U300_I2C1                   43
+#define IRQ_U300_I2C1                   44
-#define IRQ_U300_RTC                    44
+#define IRQ_U300_RTC                    45
-#define IRQ_U300_NFIF                   45
+#define IRQ_U300_NFIF                   46
-#define IRQ_U300_NFIF2                  46
+#define IRQ_U300_NFIF2                  47
-#define IRQ_U300_SYSCON_PLL_LOCK        47
+#define IRQ_U300_SYSCON_PLL_LOCK        48
-#define U300_VIC_IRQS_END               48
+#define U300_VIC_IRQS_END               49
 #endif
 /* Maximum 8*7 GPIO lines */
@@ -117,6 +117,6 @@
 #define IRQ_U300_GPIO_END               (U300_VIC_IRQS_END)
 #endif
-#define NR_IRQS                         (IRQ_U300_GPIO_END)
+#define NR_IRQS                         (IRQ_U300_GPIO_END - IRQ_U300_INTCON0_START)
 #endif
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index 880d02ec89d4..53d3d46dec12 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -9,16 +9,16 @@ config UX500_SOC_COMMON
        select ARM_ERRATA_754322
        select ARM_ERRATA_764369
        select CACHE_L2X0
+        select PINCTRL
-config UX500_SOC_DB5500
+        select PINCTRL_NOMADIK
-        bool
-        select MFD_DB5500_PRCMU
 config UX500_SOC_DB8500
        bool
        select MFD_DB8500_PRCMU
+        select REGULATOR
        select REGULATOR_DB8500_PRCMU
        select CPU_FREQ_TABLE if CPU_FREQ
+        select PINCTRL_DB8500
 menu "Ux500 target platform (boards)"
@@ -44,15 +44,8 @@ config MACH_SNOWBALL
        help
          Include support for the snowball development platform.
-config MACH_U5500
-        bool "U5500 Development platform"
-        select UX500_SOC_DB5500
-        help
-          Include support for the U5500 development platform.
 config UX500_AUTO_PLATFORM
        def_bool y
-        depends on !MACH_U5500
        select MACH_MOP500
        help
          At least one platform needs to be selected in order to build
@@ -73,18 +66,4 @@ config UX500_DEBUG_UART
          Choose the UART on which kernel low-level debug messages should be
          output.
-config U5500_MODEM_IRQ
-        bool "Modem IRQ support"
-        depends on UX500_SOC_DB5500
-        default y
-        help
-          Add support for handling IRQ:s from modem side
-config U5500_MBOX
-        bool "Mailbox support"
-        depends on U5500_MODEM_IRQ
-        default y
-        help
-          Add support for U5500 mailbox communication with modem side
 endif
diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile
index 465b9ec9510a..026086ff9e6c 100644
--- a/arch/arm/mach-ux500/Makefile
+++ b/arch/arm/mach-ux500/Makefile
@@ -4,17 +4,14 @@
 obj-y                           := clock.o cpu.o devices.o devices-common.o \
                                   id.o usb.o timer.o
+obj-$(CONFIG_CPU_IDLE)          += cpuidle.o
 obj-$(CONFIG_CACHE_L2X0)        += cache-l2x0.o
-obj-$(CONFIG_UX500_SOC_DB5500)  += cpu-db5500.o dma-db5500.o
 obj-$(CONFIG_UX500_SOC_DB8500)  += cpu-db8500.o devices-db8500.o
 obj-$(CONFIG_MACH_MOP500)       += board-mop500.o board-mop500-sdi.o \
                                board-mop500-regulators.o \
                                board-mop500-uib.o board-mop500-stuib.o \
                                board-mop500-u8500uib.o \
-                                board-mop500-pins.o
+                                board-mop500-pins.o \
-obj-$(CONFIG_MACH_U5500)        += board-u5500.o board-u5500-sdi.o
+                                board-mop500-msp.o
 obj-$(CONFIG_SMP)               += platsmp.o headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)       += hotplug.o
-obj-$(CONFIG_U5500_MODEM_IRQ)   += modem-irq-db5500.o
-obj-$(CONFIG_U5500_MBOX)        += mbox-db5500.o
diff --git a/arch/arm/mach-ux500/board-mop500-msp.c b/arch/arm/mach-ux500/board-mop500-msp.c
new file mode 100644
index 000000000000..996048038743
--- /dev/null
+++ b/arch/arm/mach-ux500/board-mop500-msp.c
@@ -0,0 +1,267 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * License terms: GNU General Public License (GPL), version 2
+ */
+#include <linux/platform_device.h>
+#include <linux/init.h>
+#include <linux/gpio.h>
+#include <linux/pinctrl/consumer.h>
+#include <plat/gpio-nomadik.h>
+#include <plat/pincfg.h>
+#include <plat/ste_dma40.h>
+#include <mach/devices.h>
+#include <mach/hardware.h>
+#include <mach/irqs.h>
+#include <mach/msp.h>
+#include "ste-dma40-db8500.h"
+#include "board-mop500.h"
+#include "devices-db8500.h"
+#include "pins-db8500.h"
+/* MSP1/3 Tx/Rx usage protection */
+static DEFINE_SPINLOCK(msp_rxtx_lock);
+/* Reference Count */
+static int msp_rxtx_ref;
+/* Pin modes */
+struct pinctrl *msp1_p;
+struct pinctrl_state *msp1_def;
+struct pinctrl_state *msp1_sleep;
+int msp13_i2s_init(void)
+{
+        int retval = 0;
+        unsigned long flags;
+        spin_lock_irqsave(&msp_rxtx_lock, flags);
+        if (msp_rxtx_ref == 0 && !(IS_ERR(msp1_p) || IS_ERR(msp1_def))) {
+                retval = pinctrl_select_state(msp1_p, msp1_def);
+                if (retval)
+                        pr_err("could not set MSP1 defstate\n");
+        }
+        if (!retval)
+                msp_rxtx_ref++;
+        spin_unlock_irqrestore(&msp_rxtx_lock, flags);
+        return retval;
+}
+int msp13_i2s_exit(void)
+{
+        int retval = 0;
+        unsigned long flags;
+        spin_lock_irqsave(&msp_rxtx_lock, flags);
+        WARN_ON(!msp_rxtx_ref);
+        msp_rxtx_ref--;
+        if (msp_rxtx_ref == 0 && !(IS_ERR(msp1_p) || IS_ERR(msp1_sleep))) {
+                retval = pinctrl_select_state(msp1_p, msp1_sleep);
+                if (retval)
+                        pr_err("could not set MSP1 sleepstate\n");
+        }
+        spin_unlock_irqrestore(&msp_rxtx_lock, flags);
+        return retval;
+}
+static struct stedma40_chan_cfg msp0_dma_rx = {
+        .high_priority = true,
+        .dir = STEDMA40_PERIPH_TO_MEM,
+        .src_dev_type = DB8500_DMA_DEV31_MSP0_RX_SLIM0_CH0_RX,
+        .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
+        .src_info.psize = STEDMA40_PSIZE_LOG_4,
+        .dst_info.psize = STEDMA40_PSIZE_LOG_4,
+        /* data_width is set during configuration */
+};
+static struct stedma40_chan_cfg msp0_dma_tx = {
+        .high_priority = true,
+        .dir = STEDMA40_MEM_TO_PERIPH,
+        .src_dev_type = STEDMA40_DEV_DST_MEMORY,
+        .dst_dev_type = DB8500_DMA_DEV31_MSP0_TX_SLIM0_CH0_TX,
+        .src_info.psize = STEDMA40_PSIZE_LOG_4,
+        .dst_info.psize = STEDMA40_PSIZE_LOG_4,
+        /* data_width is set during configuration */
+};
+static struct msp_i2s_platform_data msp0_platform_data = {
+        .id = MSP_I2S_0,
+        .msp_i2s_dma_rx = &msp0_dma_rx,
+        .msp_i2s_dma_tx = &msp0_dma_tx,
+};
+static struct stedma40_chan_cfg msp1_dma_rx = {
+        .high_priority = true,
+        .dir = STEDMA40_PERIPH_TO_MEM,
+        .src_dev_type = DB8500_DMA_DEV30_MSP3_RX,
+        .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
+        .src_info.psize = STEDMA40_PSIZE_LOG_4,
+        .dst_info.psize = STEDMA40_PSIZE_LOG_4,
+        /* data_width is set during configuration */
+};
+static struct stedma40_chan_cfg msp1_dma_tx = {
+        .high_priority = true,
+        .dir = STEDMA40_MEM_TO_PERIPH,
+        .src_dev_type = STEDMA40_DEV_DST_MEMORY,
+        .dst_dev_type = DB8500_DMA_DEV30_MSP1_TX,
+        .src_info.psize = STEDMA40_PSIZE_LOG_4,
+        .dst_info.psize = STEDMA40_PSIZE_LOG_4,
+        /* data_width is set during configuration */
+};
+static struct msp_i2s_platform_data msp1_platform_data = {
+        .id = MSP_I2S_1,
+        .msp_i2s_dma_rx = NULL,
+        .msp_i2s_dma_tx = &msp1_dma_tx,
+        .msp_i2s_init = msp13_i2s_init,
+        .msp_i2s_exit = msp13_i2s_exit,
+};
+static struct stedma40_chan_cfg msp2_dma_rx = {
+        .high_priority = true,
+        .dir = STEDMA40_PERIPH_TO_MEM,
+        .src_dev_type = DB8500_DMA_DEV14_MSP2_RX,
+        .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
+        /* MSP2 DMA doesn't work with PSIZE == 4 on DB8500v2 */
+        .src_info.psize = STEDMA40_PSIZE_LOG_1,
+        .dst_info.psize = STEDMA40_PSIZE_LOG_1,
+        /* data_width is set during configuration */
+};
+static struct stedma40_chan_cfg msp2_dma_tx = {
+        .high_priority = true,
+        .dir = STEDMA40_MEM_TO_PERIPH,
+        .src_dev_type = STEDMA40_DEV_DST_MEMORY,
+        .dst_dev_type = DB8500_DMA_DEV14_MSP2_TX,
+        .src_info.psize = STEDMA40_PSIZE_LOG_4,
+        .dst_info.psize = STEDMA40_PSIZE_LOG_4,
+        .use_fixed_channel = true,
+        .phy_channel = 1,
+        /* data_width is set during configuration */
+};
+static struct platform_device *db8500_add_msp_i2s(struct device *parent,
+                        int id,
+                        resource_size_t base, int irq,
+                        struct msp_i2s_platform_data *pdata)
+{
+        struct platform_device *pdev;
+        struct resource res[] = {
+                DEFINE_RES_MEM(base, SZ_4K),
+                DEFINE_RES_IRQ(irq),
+        };
+        pr_info("Register platform-device 'ux500-msp-i2s', id %d, irq %d\n",
+                id, irq);
+        pdev = platform_device_register_resndata(parent, "ux500-msp-i2s", id,
+                                                res, ARRAY_SIZE(res),
+                                                pdata, sizeof(*pdata));
+        if (!pdev) {
+                pr_err("Failed to register platform-device 'ux500-msp-i2s.%d'!\n",
+                        id);
+                return NULL;
+        }
+        return pdev;
+}
+/* Platform device for ASoC U8500 machine */
+static struct platform_device snd_soc_u8500 = {
+                .name = "snd-soc-u8500",
+                .id = 0,
+                .dev = {
+                        .platform_data = NULL,
+                },
+};
+/* Platform device for Ux500-PCM */
+static struct platform_device ux500_pcm = {
+                .name = "ux500-pcm",
+                .id = 0,
+                .dev = {
+                        .platform_data = NULL,
+                },
+};
+static struct msp_i2s_platform_data msp2_platform_data = {
+        .id = MSP_I2S_2,
+        .msp_i2s_dma_rx = &msp2_dma_rx,
+        .msp_i2s_dma_tx = &msp2_dma_tx,
+};
+static struct msp_i2s_platform_data msp3_platform_data = {
+        .id             = MSP_I2S_3,
+        .msp_i2s_dma_rx = &msp1_dma_rx,
+        .msp_i2s_dma_tx = NULL,
+        .msp_i2s_init = msp13_i2s_init,
+        .msp_i2s_exit = msp13_i2s_exit,
+};
+int mop500_msp_init(struct device *parent)
+{
+        struct platform_device *msp1;
+        pr_info("%s: Register platform-device 'snd-soc-u8500'.\n", __func__);
+        platform_device_register(&snd_soc_u8500);
+        pr_info("Initialize MSP I2S-devices.\n");
+        db8500_add_msp_i2s(parent, 0, U8500_MSP0_BASE, IRQ_DB8500_MSP0,
+                           &msp0_platform_data);
+        msp1 = db8500_add_msp_i2s(parent, 1, U8500_MSP1_BASE, IRQ_DB8500_MSP1,
+                           &msp1_platform_data);
+        db8500_add_msp_i2s(parent, 2, U8500_MSP2_BASE, IRQ_DB8500_MSP2,
+                           &msp2_platform_data);
+        db8500_add_msp_i2s(parent, 3, U8500_MSP3_BASE, IRQ_DB8500_MSP1,
+                           &msp3_platform_data);
+        /* Get the pinctrl handle for MSP1 */
+        if (msp1) {
+                msp1_p = pinctrl_get(&msp1->dev);
+                if (IS_ERR(msp1_p))
+                        dev_err(&msp1->dev, "could not get MSP1 pinctrl\n");
+                else {
+                        msp1_def = pinctrl_lookup_state(msp1_p,
+                                                        PINCTRL_STATE_DEFAULT);
+                        if (IS_ERR(msp1_def)) {
+                                dev_err(&msp1->dev,
+                                        "could not get MSP1 defstate\n");
+                        }
+                        msp1_sleep = pinctrl_lookup_state(msp1_p,
+                                                          PINCTRL_STATE_SLEEP);
+                        if (IS_ERR(msp1_sleep))
+                                dev_err(&msp1->dev,
+                                        "could not get MSP1 idlestate\n");
+                }
+        }
+        pr_info("%s: Register platform-device 'ux500-pcm'\n", __func__);
+        platform_device_register(&ux500_pcm);
+        return 0;
+}
diff --git a/arch/arm/mach-ux500/board-mop500-msp.h b/arch/arm/mach-ux500/board-mop500-msp.h
new file mode 100644
index 000000000000..6fcfb5e2cc94
--- /dev/null
+++ b/arch/arm/mach-ux500/board-mop500-msp.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2012
+ *
+ * Author: Ola Lilja <ola.o.lilja@stericsson.com>,
+ *         for ST-Ericsson.
+ *
+ * License terms:
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+void mop500_msp_init(struct device *parent);
diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c
index f5413dca532c..32fd99204464 100644
--- a/arch/arm/mach-ux500/board-mop500-pins.c
+++ b/arch/arm/mach-ux500/board-mop500-pins.c
@@ -7,299 +7,508 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/bug.h>
+#include <linux/string.h>
+#include <linux/pinctrl/machine.h>
 #include <asm/mach-types.h>
 #include <plat/pincfg.h>
 #include <plat/gpio-nomadik.h>
 #include <mach/hardware.h>
 #include "pins-db8500.h"
+#include "board-mop500.h"
-static pin_cfg_t mop500_pins_common[] = {
+enum custom_pin_cfg_t {
-        /* I2C */
+        PINS_FOR_DEFAULT,
-        GPIO147_I2C0_SCL,
+        PINS_FOR_U9500,
-        GPIO148_I2C0_SDA,
+};
-        GPIO16_I2C1_SCL,
-        GPIO17_I2C1_SDA,
-        GPIO10_I2C2_SDA,
-        GPIO11_I2C2_SCL,
-        GPIO229_I2C3_SDA,
-        GPIO230_I2C3_SCL,
-        /* MSP0 */
-        GPIO12_MSP0_TXD,
-        GPIO13_MSP0_TFS,
-        GPIO14_MSP0_TCK,
-        GPIO15_MSP0_RXD,
-        /* MSP2: HDMI */
-        GPIO193_MSP2_TXD,
-        GPIO194_MSP2_TCK,
-        GPIO195_MSP2_TFS,
-        GPIO196_MSP2_RXD | PIN_OUTPUT_LOW,
-        /* Touch screen INTERFACE */
-        GPIO84_GPIO     | PIN_INPUT_PULLUP, /* TOUCH_INT1 */
-        /* STMPE1601/tc35893 keypad  IRQ */
-        GPIO218_GPIO    | PIN_INPUT_PULLUP,
-        /* MMC0 (MicroSD card) */
-        GPIO18_MC0_CMDDIR       | PIN_OUTPUT_HIGH,
-        GPIO19_MC0_DAT0DIR      | PIN_OUTPUT_HIGH,
-        GPIO20_MC0_DAT2DIR      | PIN_OUTPUT_HIGH,
-        GPIO22_MC0_FBCLK        | PIN_INPUT_NOPULL,
-        GPIO23_MC0_CLK          | PIN_OUTPUT_LOW,
-        GPIO24_MC0_CMD          | PIN_INPUT_PULLUP,
-        GPIO25_MC0_DAT0         | PIN_INPUT_PULLUP,
-        GPIO26_MC0_DAT1         | PIN_INPUT_PULLUP,
-        GPIO27_MC0_DAT2         | PIN_INPUT_PULLUP,
-        GPIO28_MC0_DAT3         | PIN_INPUT_PULLUP,
-        /* SDI1 (SDIO) */
-        GPIO208_MC1_CLK         | PIN_OUTPUT_LOW,
-        GPIO209_MC1_FBCLK       | PIN_INPUT_NOPULL,
-        GPIO210_MC1_CMD         | PIN_INPUT_PULLUP,
-        GPIO211_MC1_DAT0        | PIN_INPUT_PULLUP,
-        GPIO212_MC1_DAT1        | PIN_INPUT_PULLUP,
-        GPIO213_MC1_DAT2        | PIN_INPUT_PULLUP,
-        GPIO214_MC1_DAT3        | PIN_INPUT_PULLUP,
-        /* MMC2 (On-board DATA INTERFACE eMMC) */
-        GPIO128_MC2_CLK         | PIN_OUTPUT_LOW,
-        GPIO129_MC2_CMD         | PIN_INPUT_PULLUP,
-        GPIO130_MC2_FBCLK       | PIN_INPUT_NOPULL,
-        GPIO131_MC2_DAT0        | PIN_INPUT_PULLUP,
-        GPIO132_MC2_DAT1        | PIN_INPUT_PULLUP,
-        GPIO133_MC2_DAT2        | PIN_INPUT_PULLUP,
-        GPIO134_MC2_DAT3        | PIN_INPUT_PULLUP,
-        GPIO135_MC2_DAT4        | PIN_INPUT_PULLUP,
-        GPIO136_MC2_DAT5        | PIN_INPUT_PULLUP,
-        GPIO137_MC2_DAT6        | PIN_INPUT_PULLUP,
-        GPIO138_MC2_DAT7        | PIN_INPUT_PULLUP,
-        /* MMC4 (On-board STORAGE INTERFACE eMMC) */
-        GPIO197_MC4_DAT3        | PIN_INPUT_PULLUP,
-        GPIO198_MC4_DAT2        | PIN_INPUT_PULLUP,
-        GPIO199_MC4_DAT1        | PIN_INPUT_PULLUP,
-        GPIO200_MC4_DAT0        | PIN_INPUT_PULLUP,
-        GPIO201_MC4_CMD         | PIN_INPUT_PULLUP,
-        GPIO202_MC4_FBCLK       | PIN_INPUT_NOPULL,
-        GPIO203_MC4_CLK         | PIN_OUTPUT_LOW,
-        GPIO204_MC4_DAT7        | PIN_INPUT_PULLUP,
-        GPIO205_MC4_DAT6        | PIN_INPUT_PULLUP,
-        GPIO206_MC4_DAT5        | PIN_INPUT_PULLUP,
-        GPIO207_MC4_DAT4        | PIN_INPUT_PULLUP,
-        /* SKE keypad */
-        GPIO153_KP_I7,
-        GPIO154_KP_I6,
-        GPIO155_KP_I5,
-        GPIO156_KP_I4,
-        GPIO157_KP_O7,
-        GPIO158_KP_O6,
-        GPIO159_KP_O5,
-        GPIO160_KP_O4,
-        GPIO161_KP_I3,
-        GPIO162_KP_I2,
-        GPIO163_KP_I1,
-        GPIO164_KP_I0,
-        GPIO165_KP_O3,
-        GPIO166_KP_O2,
-        GPIO167_KP_O1,
-        GPIO168_KP_O0,
-        /* UART */
+static enum custom_pin_cfg_t pinsfor;
-        /* uart-0 pins gpio configuration should be
-         * kept intact to prevent glitch in tx line
+/* These simply sets bias for pins */
-         * when tty dev is opened. Later these pins
+#define BIAS(a,b) static unsigned long a[] = { b }
+BIAS(pd, PIN_PULL_DOWN);
+BIAS(slpm_gpio_nopull, PIN_SLPM_GPIO|PIN_SLPM_INPUT_NOPULL);
+BIAS(in_nopull, PIN_INPUT_NOPULL);
+BIAS(in_nopull_sleep_nowkup, PIN_INPUT_NOPULL|PIN_SLPM_WAKEUP_DISABLE);
+BIAS(in_pu, PIN_INPUT_PULLUP);
+BIAS(in_pd, PIN_INPUT_PULLDOWN);
+BIAS(in_pd_slpm_in_pu, PIN_INPUT_PULLDOWN|PIN_SLPM_INPUT_PULLUP);
+BIAS(in_pu_slpm_out_lo, PIN_INPUT_PULLUP|PIN_SLPM_OUTPUT_LOW);
+BIAS(out_hi, PIN_OUTPUT_HIGH);
+BIAS(out_lo, PIN_OUTPUT_LOW);
+BIAS(out_lo_sleep_nowkup, PIN_OUTPUT_LOW|PIN_SLPM_WAKEUP_DISABLE);
+/* These also force them into GPIO mode */
+BIAS(gpio_in_pu, PIN_INPUT_PULLUP|PIN_GPIOMODE_ENABLED);
+BIAS(gpio_in_pd, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED);
+BIAS(gpio_in_pu_slpm_gpio_nopull, PIN_INPUT_PULLUP|PIN_GPIOMODE_ENABLED|PIN_SLPM_GPIO|PIN_SLPM_INPUT_NOPULL);
+BIAS(gpio_in_pd_slpm_gpio_nopull, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED|PIN_SLPM_GPIO|PIN_SLPM_INPUT_NOPULL);
+BIAS(gpio_out_hi, PIN_OUTPUT_HIGH|PIN_GPIOMODE_ENABLED);
+BIAS(gpio_out_lo, PIN_OUTPUT_LOW|PIN_GPIOMODE_ENABLED);
+/* Sleep modes */
+BIAS(sleep_in_wkup_pdis, PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
+BIAS(sleep_in_nopull_wkup, PIN_INPUT_NOPULL|PIN_SLPM_WAKEUP_ENABLE);
+BIAS(sleep_out_hi_wkup_pdis, PIN_SLPM_OUTPUT_HIGH|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
+BIAS(sleep_out_lo_wkup, PIN_OUTPUT_LOW|PIN_SLPM_WAKEUP_ENABLE);
+BIAS(sleep_out_wkup_pdis, PIN_SLPM_DIR_OUTPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
+/* We use these to define hog settings that are always done on boot */
+#define DB8500_MUX_HOG(group,func) \
+        PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-db8500", group, func)
+#define DB8500_PIN_HOG(pin,conf) \
+        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-db8500", pin, conf)
+/* These are default states associated with device and changed runtime */
+#define DB8500_MUX(group,func,dev) \
+        PIN_MAP_MUX_GROUP_DEFAULT(dev, "pinctrl-db8500", group, func)
+#define DB8500_PIN(pin,conf,dev) \
+        PIN_MAP_CONFIGS_PIN_DEFAULT(dev, "pinctrl-db8500", pin, conf)
+#define DB8500_PIN_SLEEP(pin,conf,dev) \
+        PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_SLEEP, "pinctrl-db8500", \
+                            pin, conf)
+/* Pin control settings */
+static struct pinctrl_map __initdata mop500_family_pinmap[] = {
+        /*
+         * uMSP0, mux in 4 pins, regular placement of RX/TX
+         * explicitly set the pins to no pull
+         */
+        DB8500_MUX_HOG("msp0txrx_a_1", "msp0"),
+        DB8500_MUX_HOG("msp0tfstck_a_1", "msp0"),
+        DB8500_PIN_HOG("GPIO12_AC4", in_nopull), /* TXD */
+        DB8500_PIN_HOG("GPIO15_AC3", in_nopull), /* RXD */
+        DB8500_PIN_HOG("GPIO13_AF3", in_nopull), /* TFS */
+        DB8500_PIN_HOG("GPIO14_AE3", in_nopull), /* TCK */
+        /* MSP2 for HDMI, pull down TXD, TCK, TFS  */
+        DB8500_MUX_HOG("msp2_a_1", "msp2"),
+        DB8500_PIN_HOG("GPIO193_AH27", in_pd), /* TXD */
+        DB8500_PIN_HOG("GPIO194_AF27", in_pd), /* TCK */
+        DB8500_PIN_HOG("GPIO195_AG28", in_pd), /* TFS */
+        DB8500_PIN_HOG("GPIO196_AG26", out_lo), /* RXD */
+        /*
+         * LCD, set TE0 (using LCD VSI0) and D14 (touch screen interrupt) to
+         * pull-up
+         * TODO: is this really correct? Snowball doesn't have a LCD.
+         */
+        DB8500_MUX_HOG("lcdvsi0_a_1", "lcd"),
+        DB8500_PIN_HOG("GPIO68_E1", in_pu),
+        DB8500_PIN_HOG("GPIO84_C2", gpio_in_pu),
+        /*
+         * STMPE1601/tc35893 keypad IRQ GPIO 218
+         * TODO: set for snowball and HREF really??
+         */
+        DB8500_PIN_HOG("GPIO218_AH11", gpio_in_pu),
+        /*
+         * UART0, we do not mux in u0 here.
+         * uart-0 pins gpio configuration should be kept intact to prevent
+         * a glitch in tx line when the tty dev is opened. Later these pins
         * are configured to uart mop500_pins_uart0
-         *
-         * It will be replaced with uart configuration
-         * once the issue is solved.
         */
-        GPIO0_GPIO      | PIN_INPUT_PULLUP,
+        DB8500_PIN_HOG("GPIO0_AJ5", in_pu), /* CTS */
-        GPIO1_GPIO      | PIN_OUTPUT_HIGH,
+        DB8500_PIN_HOG("GPIO1_AJ3", out_hi), /* RTS */
-        GPIO2_GPIO      | PIN_INPUT_PULLUP,
+        DB8500_PIN_HOG("GPIO2_AH4", in_pu), /* RXD */
-        GPIO3_GPIO      | PIN_OUTPUT_HIGH,
+        DB8500_PIN_HOG("GPIO3_AH3", out_hi), /* TXD */
+        /*
-        GPIO29_U2_RXD   | PIN_INPUT_PULLUP,
+         * Mux in UART2 on altfunction C and set pull-ups.
-        GPIO30_U2_TXD   | PIN_OUTPUT_HIGH,
+         * TODO: is this used on U8500 variants and Snowball really?
-        GPIO31_U2_CTSn  | PIN_INPUT_PULLUP,
+         * The setting on GPIO31 conflicts with magnetometer use on hrefv60
-        GPIO32_U2_RTSn  | PIN_OUTPUT_HIGH,
+         */
+        DB8500_MUX_HOG("u2rxtx_c_1", "u2"),
-        /* Display & HDMI HW sync */
+        DB8500_MUX_HOG("u2ctsrts_c_1", "u2"),
-        GPIO68_LCD_VSI0 | PIN_INPUT_PULLUP,
+        DB8500_PIN_HOG("GPIO29_W2", in_pu), /* RXD */
-        GPIO69_LCD_VSI1 | PIN_INPUT_PULLUP,
+        DB8500_PIN_HOG("GPIO30_W3", out_hi), /* TXD */
+        DB8500_PIN_HOG("GPIO31_V3", in_pu), /* CTS */
+        DB8500_PIN_HOG("GPIO32_V2", out_hi), /* RTS */
+        /*
+         * The following pin sets were known as "runtime pins" before being
+         * converted to the pinctrl model. Here we model them as "default"
+         * states.
+         */
+        /* Mux in UART0 after initialization */
+        DB8500_MUX("u0_a_1", "u0", "uart0"),
+        DB8500_PIN("GPIO0_AJ5", in_pu, "uart0"), /* CTS */
+        DB8500_PIN("GPIO1_AJ3", out_hi, "uart0"), /* RTS */
+        DB8500_PIN("GPIO2_AH4", in_pu, "uart0"), /* RXD */
+        DB8500_PIN("GPIO3_AH3", out_hi, "uart0"), /* TXD */
+        /* UART0 sleep state */
+        DB8500_PIN_SLEEP("GPIO0_AJ5", sleep_in_wkup_pdis, "uart0"),
+        DB8500_PIN_SLEEP("GPIO1_AJ3", sleep_out_hi_wkup_pdis, "uart0"),
+        DB8500_PIN_SLEEP("GPIO2_AH4", sleep_in_wkup_pdis, "uart0"),
+        DB8500_PIN_SLEEP("GPIO3_AH3", sleep_out_wkup_pdis, "uart0"),
+        /* MSP1 for ALSA codec */
+        DB8500_MUX("msp1txrx_a_1", "msp1", "ux500-msp-i2s.1"),
+        DB8500_MUX("msp1_a_1", "msp1", "ux500-msp-i2s.1"),
+        DB8500_PIN("GPIO33_AF2", out_lo_sleep_nowkup, "ux500-msp-i2s.1"),
+        DB8500_PIN("GPIO34_AE1", in_nopull_sleep_nowkup, "ux500-msp-i2s.1"),
+        DB8500_PIN("GPIO35_AE2", in_nopull_sleep_nowkup, "ux500-msp-i2s.1"),
+        DB8500_PIN("GPIO36_AG2", in_nopull_sleep_nowkup, "ux500-msp-i2s.1"),
+        /* MSP1 sleep state */
+        DB8500_PIN_SLEEP("GPIO33_AF2", sleep_out_lo_wkup, "ux500-msp-i2s.1"),
+        DB8500_PIN_SLEEP("GPIO34_AE1", sleep_in_nopull_wkup, "ux500-msp-i2s.1"),
+        DB8500_PIN_SLEEP("GPIO35_AE2", sleep_in_nopull_wkup, "ux500-msp-i2s.1"),
+        DB8500_PIN_SLEEP("GPIO36_AG2", sleep_in_nopull_wkup, "ux500-msp-i2s.1"),
+        /* Mux in LCD data lines 8 thru 11 and LCDA CLK for MCDE TVOUT */
+        DB8500_MUX("lcd_d8_d11_a_1", "lcd", "mcde-tvout"),
+        DB8500_MUX("lcdaclk_b_1", "lcda", "mcde-tvout"),
+        /* Mux in LCD VSI1 and pull it up for MCDE HDMI output */
+        DB8500_MUX("lcdvsi1_a_1", "lcd", "av8100-hdmi"),
+        /* Mux in I2C blocks, put pins into GPIO in sleepmode no pull-up */
+        DB8500_MUX("i2c0_a_1", "i2c0", "nmk-i2c.0"),
+        DB8500_PIN("GPIO147_C15", slpm_gpio_nopull, "nmk-i2c.0"),
+        DB8500_PIN("GPIO148_B16", slpm_gpio_nopull, "nmk-i2c.0"),
+        DB8500_MUX("i2c1_b_2", "i2c1", "nmk-i2c.1"),
+        DB8500_PIN("GPIO16_AD3", slpm_gpio_nopull, "nmk-i2c.1"),
+        DB8500_PIN("GPIO17_AD4", slpm_gpio_nopull, "nmk-i2c.1"),
+        DB8500_MUX("i2c2_b_2", "i2c2", "nmk-i2c.2"),
+        DB8500_PIN("GPIO10_AF5", slpm_gpio_nopull, "nmk-i2c.2"),
+        DB8500_PIN("GPIO11_AG4", slpm_gpio_nopull, "nmk-i2c.2"),
+        DB8500_MUX("i2c3_c_2", "i2c3", "nmk-i2c.3"),
+        DB8500_PIN("GPIO229_AG7", slpm_gpio_nopull, "nmk-i2c.3"),
+        DB8500_PIN("GPIO230_AF7", slpm_gpio_nopull, "nmk-i2c.3"),
+        /* Mux in SDI0 (here called MC0) used for removable MMC/SD/SDIO cards */
+        DB8500_MUX("mc0_a_1", "mc0", "sdi0"),
+        DB8500_PIN("GPIO18_AC2", out_hi, "sdi0"), /* CMDDIR */
+        DB8500_PIN("GPIO19_AC1", out_hi, "sdi0"), /* DAT0DIR */
+        DB8500_PIN("GPIO20_AB4", out_hi, "sdi0"), /* DAT2DIR */
+        DB8500_PIN("GPIO22_AA3", in_nopull, "sdi0"), /* FBCLK */
+        DB8500_PIN("GPIO23_AA4", out_lo, "sdi0"), /* CLK */
+        DB8500_PIN("GPIO24_AB2", in_pu, "sdi0"), /* CMD */
+        DB8500_PIN("GPIO25_Y4", in_pu, "sdi0"), /* DAT0 */
+        DB8500_PIN("GPIO26_Y2", in_pu, "sdi0"), /* DAT1 */
+        DB8500_PIN("GPIO27_AA2", in_pu, "sdi0"), /* DAT2 */
+        DB8500_PIN("GPIO28_AA1", in_pu, "sdi0"), /* DAT3 */
+        /* Mux in SDI1 (here called MC1) used for SDIO for CW1200 WLAN */
+        DB8500_MUX("mc1_a_1", "mc1", "sdi1"),
+        DB8500_PIN("GPIO208_AH16", out_lo, "sdi1"), /* CLK */
+        DB8500_PIN("GPIO209_AG15", in_nopull, "sdi1"), /* FBCLK */
+        DB8500_PIN("GPIO210_AJ15", in_pu, "sdi1"), /* CMD */
+        DB8500_PIN("GPIO211_AG14", in_pu, "sdi1"), /* DAT0 */
+        DB8500_PIN("GPIO212_AF13", in_pu, "sdi1"), /* DAT1 */
+        DB8500_PIN("GPIO213_AG13", in_pu, "sdi1"), /* DAT2 */
+        DB8500_PIN("GPIO214_AH15", in_pu, "sdi1"), /* DAT3 */
+        /* Mux in SDI2 (here called MC2) used for for PoP eMMC */
+        DB8500_MUX("mc2_a_1", "mc2", "sdi2"),
+        DB8500_PIN("GPIO128_A5", out_lo, "sdi2"), /* CLK */
+        DB8500_PIN("GPIO129_B4", in_pu, "sdi2"), /* CMD */
+        DB8500_PIN("GPIO130_C8", in_nopull, "sdi2"), /* FBCLK */
+        DB8500_PIN("GPIO131_A12", in_pu, "sdi2"), /* DAT0 */
+        DB8500_PIN("GPIO132_C10", in_pu, "sdi2"), /* DAT1 */
+        DB8500_PIN("GPIO133_B10", in_pu, "sdi2"), /* DAT2 */
+        DB8500_PIN("GPIO134_B9", in_pu, "sdi2"), /* DAT3 */
+        DB8500_PIN("GPIO135_A9", in_pu, "sdi2"), /* DAT4 */
+        DB8500_PIN("GPIO136_C7", in_pu, "sdi2"), /* DAT5 */
+        DB8500_PIN("GPIO137_A7", in_pu, "sdi2"), /* DAT6 */
+        DB8500_PIN("GPIO138_C5", in_pu, "sdi2"), /* DAT7 */
+        /* Mux in SDI4 (here called MC4) used for for PCB-mounted eMMC */
+        DB8500_MUX("mc4_a_1", "mc4", "sdi4"),
+        DB8500_PIN("GPIO197_AH24", in_pu, "sdi4"), /* DAT3 */
+        DB8500_PIN("GPIO198_AG25", in_pu, "sdi4"), /* DAT2 */
+        DB8500_PIN("GPIO199_AH23", in_pu, "sdi4"), /* DAT1 */
+        DB8500_PIN("GPIO200_AH26", in_pu, "sdi4"), /* DAT0 */
+        DB8500_PIN("GPIO201_AF24", in_pu, "sdi4"), /* CMD */
+        DB8500_PIN("GPIO202_AF25", in_nopull, "sdi4"), /* FBCLK */
+        DB8500_PIN("GPIO203_AE23", out_lo, "sdi4"), /* CLK */
+        DB8500_PIN("GPIO204_AF23", in_pu, "sdi4"), /* DAT7 */
+        DB8500_PIN("GPIO205_AG23", in_pu, "sdi4"), /* DAT6 */
+        DB8500_PIN("GPIO206_AG24", in_pu, "sdi4"), /* DAT5 */
+        DB8500_PIN("GPIO207_AJ23", in_pu, "sdi4"), /* DAT4 */
+        /* Mux in USB pins, drive STP high */
+        DB8500_MUX("usb_a_1", "usb", "musb-ux500.0"),
+        DB8500_PIN("GPIO257_AE29", out_hi, "musb-ux500.0"), /* STP */
+        /* Mux in SPI2 pins on the "other C1" altfunction */
+        DB8500_MUX("spi2_oc1_1", "spi2", "spi2"),
+        DB8500_PIN("GPIO216_AG12", gpio_out_hi, "spi2"), /* FRM */
+        DB8500_PIN("GPIO218_AH11", in_pd, "spi2"), /* RXD */
+        DB8500_PIN("GPIO215_AH13", out_lo, "spi2"), /* TXD */
+        DB8500_PIN("GPIO217_AH12", out_lo, "spi2"), /* CLK */
 };
-static pin_cfg_t mop500_pins_default[] = {
+/*
-        /* SSP0 */
+ * These are specifically for the MOP500 and HREFP (pre-v60) version of the
-        GPIO143_SSP0_CLK,
+ * board, which utilized a TC35892 GPIO expander instead of using a lot of
-        GPIO144_SSP0_FRM,
+ * on-chip pins as the HREFv60 and later does.
-        GPIO145_SSP0_RXD | PIN_PULL_DOWN,
+ */
-        GPIO146_SSP0_TXD,
+static struct pinctrl_map __initdata mop500_pinmap[] = {
+        /* Mux in SSP0, pull down RXD pin */
+        DB8500_MUX_HOG("ssp0_a_1", "ssp0"),
-        GPIO217_GPIO    | PIN_INPUT_PULLUP, /* TC35892 IRQ */
+        DB8500_PIN_HOG("GPIO145_C13", pd),
+        /*
-        /* SDI0 (MicroSD card) */
+         * XENON Flashgun on image processor GPIO (controlled from image
-        GPIO21_MC0_DAT31DIR     | PIN_OUTPUT_HIGH,
+         * processor firmware), mux in these image processor GPIO lines 0
+         * (XENON_FLASH_ID) and 1 (XENON_READY) on altfunction C and pull up
-        /* UART */
+         * the pins.
-        GPIO4_U1_RXD    | PIN_INPUT_PULLUP,
+         */
-        GPIO5_U1_TXD    | PIN_OUTPUT_HIGH,
+        DB8500_MUX_HOG("ipgpio0_c_1", "ipgpio"),
-        GPIO6_U1_CTSn   | PIN_INPUT_PULLUP,
+        DB8500_MUX_HOG("ipgpio1_c_1", "ipgpio"),
-        GPIO7_U1_RTSn   | PIN_OUTPUT_HIGH,
+        DB8500_PIN_HOG("GPIO6_AF6", in_pu),
+        DB8500_PIN_HOG("GPIO7_AG5", in_pu),
+        /* TC35892 IRQ, pull up the line, let the driver mux in the pin */
+        DB8500_PIN_HOG("GPIO217_AH12", gpio_in_pu),
+        /* Mux in UART1 and set the pull-ups */
+        DB8500_MUX_HOG("u1rxtx_a_1", "u1"),
+        DB8500_MUX_HOG("u1ctsrts_a_1", "u1"),
+        DB8500_PIN_HOG("GPIO4_AH6", in_pu), /* RXD */
+        DB8500_PIN_HOG("GPIO5_AG6", out_hi), /* TXD */
+        DB8500_PIN_HOG("GPIO6_AF6", in_pu), /* CTS */
+        DB8500_PIN_HOG("GPIO7_AG5", out_hi), /* RTS */
+        /*
+         * Runtime stuff: make it possible to mux in the SKE keypad
+         * and bias the pins
+         */
+        DB8500_MUX("kp_a_2", "kp", "ske"),
+        DB8500_PIN("GPIO153_B17", in_pd_slpm_in_pu, "ske"), /* I7 */
+        DB8500_PIN("GPIO154_C16", in_pd_slpm_in_pu, "ske"), /* I6 */
+        DB8500_PIN("GPIO155_C19", in_pd_slpm_in_pu, "ske"), /* I5 */
+        DB8500_PIN("GPIO156_C17", in_pd_slpm_in_pu, "ske"), /* I4 */
+        DB8500_PIN("GPIO161_D21", in_pd_slpm_in_pu, "ske"), /* I3 */
+        DB8500_PIN("GPIO162_D20", in_pd_slpm_in_pu, "ske"), /* I2 */
+        DB8500_PIN("GPIO163_C20", in_pd_slpm_in_pu, "ske"), /* I1 */
+        DB8500_PIN("GPIO164_B21", in_pd_slpm_in_pu, "ske"), /* I0 */
+        DB8500_PIN("GPIO157_A18", in_pu_slpm_out_lo, "ske"), /* O7 */
+        DB8500_PIN("GPIO158_C18", in_pu_slpm_out_lo, "ske"), /* O6 */
+        DB8500_PIN("GPIO159_B19", in_pu_slpm_out_lo, "ske"), /* O5 */
+        DB8500_PIN("GPIO160_B20", in_pu_slpm_out_lo, "ske"), /* O4 */
+        DB8500_PIN("GPIO165_C21", in_pu_slpm_out_lo, "ske"), /* O3 */
+        DB8500_PIN("GPIO166_A22", in_pu_slpm_out_lo, "ske"), /* O2 */
+        DB8500_PIN("GPIO167_B24", in_pu_slpm_out_lo, "ske"), /* O1 */
+        DB8500_PIN("GPIO168_C22", in_pu_slpm_out_lo, "ske"), /* O0 */
+        /* Mux in and drive the SDI0 DAT31DIR line high at runtime */
+        DB8500_MUX("mc0dat31dir_a_1", "mc0", "sdi0"),
+        DB8500_PIN("GPIO21_AB3", out_hi, "sdi0"),
 };
-static pin_cfg_t hrefv60_pins[] = {
+/*
-        /* WLAN */
+ * The HREFv60 series of platforms is using available pins on the DB8500
-        GPIO4_GPIO              | PIN_INPUT_PULLUP,/* WLAN_IRQ */
+ * insteaf of the Toshiba I2C GPIO expander, reusing some pins like the SSP0
-        GPIO85_GPIO             | PIN_OUTPUT_LOW,/* WLAN_ENA */
+ * and SSP1 ports (previously connected to the AB8500) as generic GPIO lines.
+ */
-        /* XENON Flashgun INTERFACE */
+static struct pinctrl_map __initdata hrefv60_pinmap[] = {
-        GPIO6_IP_GPIO0  | PIN_INPUT_PULLUP,/* XENON_FLASH_ID */
+        /* Drive WLAN_ENA low */
-        GPIO7_IP_GPIO1  | PIN_INPUT_PULLUP,/* XENON_READY */
+        DB8500_PIN_HOG("GPIO85_D5", gpio_out_lo), /* WLAN_ENA */
-        GPIO170_GPIO    | PIN_OUTPUT_LOW, /* XENON_CHARGE */
+        /*
+         * XENON Flashgun on image processor GPIO (controlled from image
-        /* Assistant LED INTERFACE */
+         * processor firmware), mux in these image processor GPIO lines 0
-        GPIO21_GPIO | PIN_OUTPUT_LOW,  /* XENON_EN1 */
+         * (XENON_FLASH_ID), 1 (XENON_READY) and there is an assistant
-        GPIO64_IP_GPIO4 | PIN_OUTPUT_LOW,  /* XENON_EN2 */
+         * LED on IP GPIO 4 (XENON_EN2) on altfunction C, that need bias
+         * from GPIO21 so pull up 0, 1 and drive 4 and GPIO21 low as output.
-        /* Magnetometer */
+         */
-        GPIO31_GPIO | PIN_INPUT_PULLUP,  /* magnetometer_INT */
+        DB8500_MUX_HOG("ipgpio0_c_1", "ipgpio"),
-        GPIO32_GPIO | PIN_INPUT_PULLDOWN, /* Magnetometer DRDY */
+        DB8500_MUX_HOG("ipgpio1_c_1", "ipgpio"),
+        DB8500_MUX_HOG("ipgpio4_c_1", "ipgpio"),
-        /* Display Interface */
+        DB8500_PIN_HOG("GPIO6_AF6", in_pu), /* XENON_FLASH_ID */
-        GPIO65_GPIO             | PIN_OUTPUT_LOW, /* DISP1 RST */
+        DB8500_PIN_HOG("GPIO7_AG5", in_pu), /* XENON_READY */
-        GPIO66_GPIO             | PIN_OUTPUT_LOW, /* DISP2 RST */
+        DB8500_PIN_HOG("GPIO21_AB3", gpio_out_lo), /* XENON_EN1 */
+        DB8500_PIN_HOG("GPIO64_F3", out_lo), /* XENON_EN2 */
-        /* Touch screen INTERFACE */
+        /* Magnetometer uses GPIO 31 and 32, pull these up/down respectively */
-        GPIO143_GPIO    | PIN_OUTPUT_LOW,/*TOUCH_RST1 */
+        DB8500_PIN_HOG("GPIO31_V3", gpio_in_pu), /* EN1 */
+        DB8500_PIN_HOG("GPIO32_V2", gpio_in_pd), /* DRDY */
-        /* Touch screen INTERFACE 2 */
+        /*
-        GPIO67_GPIO     | PIN_INPUT_PULLUP, /* TOUCH_INT2 */
+         * Display Interface 1 uses GPIO 65 for RST (reset).
-        GPIO146_GPIO    | PIN_OUTPUT_LOW,/*TOUCH_RST2 */
+         * Display Interface 2 uses GPIO 66 for RST (reset).
+         * Drive DISP1 reset high (not reset), driver DISP2 reset low (reset)
-        /* ETM_PTM_TRACE INTERFACE */
+         */
-        GPIO70_GPIO     | PIN_OUTPUT_LOW,/* ETM_PTM_DATA23 */
+        DB8500_PIN_HOG("GPIO65_F1", gpio_out_hi), /* DISP1 NO RST */
-        GPIO71_GPIO     | PIN_OUTPUT_LOW,/* ETM_PTM_DATA22 */
+        DB8500_PIN_HOG("GPIO66_G3", gpio_out_lo), /* DISP2 RST */
-        GPIO72_GPIO     | PIN_OUTPUT_LOW,/* ETM_PTM_DATA21 */
+        /*
-        GPIO73_GPIO     | PIN_OUTPUT_LOW,/* ETM_PTM_DATA20 */
+         * Touch screen uses GPIO 143 for RST1, GPIO 146 for RST2 and
-        GPIO74_GPIO     | PIN_OUTPUT_LOW,/* ETM_PTM_DATA19 */
+         * GPIO 67 for interrupts. Pull-up the IRQ line and drive both
+         * reset signals low.
-        /* NAHJ INTERFACE */
+         */
-        GPIO76_GPIO     | PIN_OUTPUT_LOW,/* NAHJ_CTRL */
+        DB8500_PIN_HOG("GPIO143_D12", gpio_out_lo), /* TOUCH_RST1 */
-        GPIO216_GPIO    | PIN_OUTPUT_HIGH,/* NAHJ_CTRL_INV */
+        DB8500_PIN_HOG("GPIO67_G2", gpio_in_pu), /* TOUCH_INT2 */
+        DB8500_PIN_HOG("GPIO146_D13", gpio_out_lo), /* TOUCH_RST2 */
-        /* NFC INTERFACE */
+        /*
-        GPIO77_GPIO     | PIN_OUTPUT_LOW, /* NFC_ENA */
+         * Drive D19-D23 for the ETM PTM trace interface low,
-        GPIO144_GPIO    | PIN_INPUT_PULLDOWN, /* NFC_IRQ */
+         * (presumably pins are unconnected therefore grounded here,
-        GPIO142_GPIO    | PIN_OUTPUT_LOW, /* NFC_RESET */
+         * the "other alt C1" setting enables these pins)
+         */
-        /* Keyboard MATRIX INTERFACE */
+        DB8500_PIN_HOG("GPIO70_G5", gpio_out_lo),
-        GPIO90_MC5_CMD  | PIN_OUTPUT_LOW, /* KP_O_1 */
+        DB8500_PIN_HOG("GPIO71_G4", gpio_out_lo),
-        GPIO87_MC5_DAT1 | PIN_OUTPUT_LOW, /* KP_O_2 */
+        DB8500_PIN_HOG("GPIO72_H4", gpio_out_lo),
-        GPIO86_MC5_DAT0 | PIN_OUTPUT_LOW, /* KP_O_3 */
+        DB8500_PIN_HOG("GPIO73_H3", gpio_out_lo),
-        GPIO96_KP_O6    | PIN_OUTPUT_LOW, /* KP_O_6 */
+        DB8500_PIN_HOG("GPIO74_J3", gpio_out_lo),
-        GPIO94_KP_O7    | PIN_OUTPUT_LOW, /* KP_O_7 */
+        /* NAHJ CTRL on GPIO 76 to low, CTRL_INV on GPIO216 to high */
-        GPIO93_MC5_DAT4 | PIN_INPUT_PULLUP, /* KP_I_0 */
+        DB8500_PIN_HOG("GPIO76_J2", gpio_out_lo), /* CTRL */
-        GPIO89_MC5_DAT3 | PIN_INPUT_PULLUP, /* KP_I_2 */
+        DB8500_PIN_HOG("GPIO216_AG12", gpio_out_hi), /* CTRL_INV */
-        GPIO88_MC5_DAT2 | PIN_INPUT_PULLUP, /* KP_I_3 */
+        /* NFC ENA and RESET to low, pulldown IRQ line */
-        GPIO91_GPIO     | PIN_INPUT_PULLUP, /* FORCE_SENSING_INT */
+        DB8500_PIN_HOG("GPIO77_H1", gpio_out_lo), /* NFC_ENA */
-        GPIO92_GPIO     | PIN_OUTPUT_LOW, /* FORCE_SENSING_RST */
+        DB8500_PIN_HOG("GPIO144_B13", gpio_in_pd), /* NFC_IRQ */
-        GPIO97_GPIO     | PIN_OUTPUT_LOW, /* FORCE_SENSING_WU */
+        DB8500_PIN_HOG("GPIO142_C11", gpio_out_lo), /* NFC_RESET */
+        /*
-        /* DiPro Sensor Interface */
+         * SKE keyboard partly on alt A and partly on "Other alt C1"
-        GPIO139_GPIO    | PIN_INPUT_PULLUP, /* DIPRO_INT */
+         * Driver KP_O1,2,3,6,7 low and pull up KP_I 0,2,3 for three
+         * rows of 6 keys, then pull up force sensing interrup and
-        /* HAL SWITCH INTERFACE */
+         * drive reset and force sensing WU low.
-        GPIO145_GPIO    | PIN_INPUT_PULLDOWN,/* HAL_SW */
+         */
+        DB8500_MUX_HOG("kp_a_1", "kp"),
-        /* Audio Amplifier Interface */
+        DB8500_MUX_HOG("kp_oc1_1", "kp"),
-        GPIO149_GPIO    | PIN_OUTPUT_LOW, /* VAUDIO_HF_EN */
+        DB8500_PIN_HOG("GPIO90_A3", out_lo), /* KP_O1 */
+        DB8500_PIN_HOG("GPIO87_B3", out_lo), /* KP_O2 */
-        /* GBF INTERFACE */
+        DB8500_PIN_HOG("GPIO86_C6", out_lo), /* KP_O3 */
-        GPIO171_GPIO    | PIN_OUTPUT_LOW, /* GBF_ENA_RESET */
+        DB8500_PIN_HOG("GPIO96_D8", out_lo), /* KP_O6 */
+        DB8500_PIN_HOG("GPIO94_D7", out_lo), /* KP_O7 */
-        /* MSP : HDTV INTERFACE */
+        DB8500_PIN_HOG("GPIO93_B7", in_pu), /* KP_I0 */
-        GPIO192_GPIO    | PIN_INPUT_PULLDOWN,
+        DB8500_PIN_HOG("GPIO89_E6", in_pu), /* KP_I2 */
+        DB8500_PIN_HOG("GPIO88_C4", in_pu), /* KP_I3 */
-        /* ACCELEROMETER_INTERFACE */
+        DB8500_PIN_HOG("GPIO91_B6", gpio_in_pu), /* FORCE_SENSING_INT */
-        GPIO82_GPIO             | PIN_INPUT_PULLUP, /* ACC_INT1 */
+        DB8500_PIN_HOG("GPIO92_D6", gpio_out_lo), /* FORCE_SENSING_RST */
-        GPIO83_GPIO             | PIN_INPUT_PULLUP, /* ACC_INT2 */
+        DB8500_PIN_HOG("GPIO97_D9", gpio_out_lo), /* FORCE_SENSING_WU */
+        /* DiPro Sensor interrupt */
-        /* Proximity Sensor */
+        DB8500_PIN_HOG("GPIO139_C9", gpio_in_pu), /* DIPRO_INT */
-        GPIO217_GPIO            | PIN_INPUT_PULLUP,
+        /* Audio Amplifier HF enable */
+        DB8500_PIN_HOG("GPIO149_B14", gpio_out_hi), /* VAUDIO_HF_EN, enable MAX8968 */
+        /* GBF interface, pull low to reset state */
+        DB8500_PIN_HOG("GPIO171_D23", gpio_out_lo), /* GBF_ENA_RESET */
+        /* MSP : HDTV INTERFACE GPIO line */
+        DB8500_PIN_HOG("GPIO192_AJ27", gpio_in_pd),
+        /* Accelerometer interrupt lines */
+        DB8500_PIN_HOG("GPIO82_C1", gpio_in_pu), /* ACC_INT1 */
+        DB8500_PIN_HOG("GPIO83_D3", gpio_in_pu), /* ACC_INT2 */
+        /* SD card detect GPIO pin */
+        DB8500_PIN_HOG("GPIO95_E8", gpio_in_pu),
+        /*
+         * Runtime stuff
+         * Pull up/down of some sensor GPIO pins, for proximity, HAL sensor
+         * etc.
+         */
+        DB8500_PIN("GPIO217_AH12", gpio_in_pu_slpm_gpio_nopull, "gpio-keys.0"),
+        DB8500_PIN("GPIO145_C13", gpio_in_pd_slpm_gpio_nopull, "gpio-keys.0"),
+        DB8500_PIN("GPIO139_C9", gpio_in_pu_slpm_gpio_nopull, "gpio-keys.0"),
+        /*
+         * Make it possible to mux in the SKE keypad and bias the pins
+         * FIXME: what's the point with this on HREFv60? KP/SKE is already
+         * muxed in at another place! Enabling this will bork.
+         */
+        DB8500_MUX("kp_a_2", "kp", "ske"),
+        DB8500_PIN("GPIO153_B17", in_pd_slpm_in_pu, "ske"), /* I7 */
+        DB8500_PIN("GPIO154_C16", in_pd_slpm_in_pu, "ske"), /* I6 */
+        DB8500_PIN("GPIO155_C19", in_pd_slpm_in_pu, "ske"), /* I5 */
+        DB8500_PIN("GPIO156_C17", in_pd_slpm_in_pu, "ske"), /* I4 */
+        DB8500_PIN("GPIO161_D21", in_pd_slpm_in_pu, "ske"), /* I3 */
+        DB8500_PIN("GPIO162_D20", in_pd_slpm_in_pu, "ske"), /* I2 */
+        DB8500_PIN("GPIO163_C20", in_pd_slpm_in_pu, "ske"), /* I1 */
+        DB8500_PIN("GPIO164_B21", in_pd_slpm_in_pu, "ske"), /* I0 */
+        DB8500_PIN("GPIO157_A18", in_pu_slpm_out_lo, "ske"), /* O7 */
+        DB8500_PIN("GPIO158_C18", in_pu_slpm_out_lo, "ske"), /* O6 */
+        DB8500_PIN("GPIO159_B19", in_pu_slpm_out_lo, "ske"), /* O5 */
+        DB8500_PIN("GPIO160_B20", in_pu_slpm_out_lo, "ske"), /* O4 */
+        DB8500_PIN("GPIO165_C21", in_pu_slpm_out_lo, "ske"), /* O3 */
+        DB8500_PIN("GPIO166_A22", in_pu_slpm_out_lo, "ske"), /* O2 */
+        DB8500_PIN("GPIO167_B24", in_pu_slpm_out_lo, "ske"), /* O1 */
+        DB8500_PIN("GPIO168_C22", in_pu_slpm_out_lo, "ske"), /* O0 */
 };
-static pin_cfg_t snowball_pins[] = {
+static struct pinctrl_map __initdata u9500_pinmap[] = {
-        /* SSP0, to AB8500 */
+        /* Mux in UART1 (just RX/TX) and set the pull-ups */
-        GPIO143_SSP0_CLK,
+        DB8500_MUX_HOG("u1rxtx_a_1", "u1"),
-        GPIO144_SSP0_FRM,
+        DB8500_PIN_HOG("GPIO4_AH6", in_pu),
-        GPIO145_SSP0_RXD        | PIN_PULL_DOWN,
+        DB8500_PIN_HOG("GPIO5_AG6", out_hi),
-        GPIO146_SSP0_TXD,
+        /* WLAN_IRQ line */
+        DB8500_PIN_HOG("GPIO144_B13", gpio_in_pu),
+        /* HSI */
+        DB8500_MUX_HOG("hsir_a_1", "hsi"),
+        DB8500_MUX_HOG("hsit_a_1", "hsi"),
+        DB8500_PIN_HOG("GPIO219_AG10", in_pd), /* RX FLA0 */
+        DB8500_PIN_HOG("GPIO220_AH10", in_pd), /* RX DAT0 */
+        DB8500_PIN_HOG("GPIO221_AJ11", out_lo), /* RX RDY0 */
+        DB8500_PIN_HOG("GPIO222_AJ9", out_lo), /* TX FLA0 */
+        DB8500_PIN_HOG("GPIO223_AH9", out_lo), /* TX DAT0 */
+        DB8500_PIN_HOG("GPIO224_AG9", in_pd), /* TX RDY0 */
+        DB8500_PIN_HOG("GPIO225_AG8", in_pd), /* CAWAKE0 */
+        DB8500_PIN_HOG("GPIO226_AF8", out_hi), /* ACWAKE0 */
+};
-        /* MMC0: MicroSD card */
+static struct pinctrl_map __initdata u8500_pinmap[] = {
-        GPIO21_MC0_DAT31DIR     | PIN_OUTPUT_HIGH,
+        DB8500_PIN_HOG("GPIO226_AF8", gpio_out_lo), /* WLAN_PMU_EN */
+        DB8500_PIN_HOG("GPIO4_AH6", gpio_in_pu), /* WLAN_IRQ */
+};
-        /* MMC2: LAN */
+static struct pinctrl_map __initdata snowball_pinmap[] = {
-        GPIO86_SM_ADQ0,
+        /* Mux in SSP0 connected to AB8500, pull down RXD pin */
-        GPIO87_SM_ADQ1,
+        DB8500_MUX_HOG("ssp0_a_1", "ssp0"),
-        GPIO88_SM_ADQ2,
+        DB8500_PIN_HOG("GPIO145_C13", pd),
-        GPIO89_SM_ADQ3,
+        /* Always drive the MC0 DAT31DIR line high on these boards */
-        GPIO90_SM_ADQ4,
+        DB8500_PIN_HOG("GPIO21_AB3", out_hi),
-        GPIO91_SM_ADQ5,
+        /* Mux in "SM" which is used for the SMSC911x Ethernet adapter */
-        GPIO92_SM_ADQ6,
+        DB8500_MUX_HOG("sm_b_1", "sm"),
-        GPIO93_SM_ADQ7,
+        /* Drive RSTn_LAN high */
+        DB8500_PIN_HOG("GPIO141_C12", gpio_out_hi),
+        /*  Accelerometer/Magnetometer */
+        DB8500_PIN_HOG("GPIO163_C20", gpio_in_pu), /* ACCEL_IRQ1 */
+        DB8500_PIN_HOG("GPIO164_B21", gpio_in_pu), /* ACCEL_IRQ2 */
+        DB8500_PIN_HOG("GPIO165_C21", gpio_in_pu), /* MAG_DRDY */
+        /* WLAN/GBF */
+        DB8500_PIN_HOG("GPIO161_D21", gpio_out_lo), /* WLAN_PMU_EN */
+        DB8500_PIN_HOG("GPIO171_D23", gpio_out_hi), /* GBF_ENA */
+        DB8500_PIN_HOG("GPIO215_AH13", gpio_out_lo), /* WLAN_ENA */
+        DB8500_PIN_HOG("GPIO216_AG12", gpio_in_pu), /* WLAN_IRQ */
+};
-        GPIO94_SM_ADVn,
+/*
-        GPIO95_SM_CS0n,
+ * passing "pinsfor=" in kernel cmdline allows for custom
-        GPIO96_SM_OEn,
+ * configuration of GPIOs on u8500 derived boards.
-        GPIO97_SM_WEn,
+ */
+static int __init early_pinsfor(char *p)
+{
+        pinsfor = PINS_FOR_DEFAULT;
-        GPIO128_SM_CKO,
+        if (strcmp(p, "u9500-21") == 0)
-        GPIO130_SM_FBCLK,
+                pinsfor = PINS_FOR_U9500;
-        GPIO131_SM_ADQ8,
-        GPIO132_SM_ADQ9,
-        GPIO133_SM_ADQ10,
-        GPIO134_SM_ADQ11,
-        GPIO135_SM_ADQ12,
-        GPIO136_SM_ADQ13,
-        GPIO137_SM_ADQ14,
-        GPIO138_SM_ADQ15,
-        /* RSTn_LAN */
+        return 0;
-        GPIO141_GPIO            | PIN_OUTPUT_HIGH,
+}
-};
+early_param("pinsfor", early_pinsfor);
-void __init mop500_pins_init(void)
+int pins_for_u9500(void)
 {
-        nmk_config_pins(mop500_pins_common,
+        if (pinsfor == PINS_FOR_U9500)
-                        ARRAY_SIZE(mop500_pins_common));
+                return 1;
-        nmk_config_pins(mop500_pins_default,
+        return 0;
-                        ARRAY_SIZE(mop500_pins_default));
 }
-void __init snowball_pins_init(void)
+static void __init mop500_href_family_pinmaps_init(void)
 {
-        nmk_config_pins(mop500_pins_common,
+        switch (pinsfor) {
-                        ARRAY_SIZE(mop500_pins_common));
+        case PINS_FOR_U9500:
+                pinctrl_register_mappings(u9500_pinmap,
+                                          ARRAY_SIZE(u9500_pinmap));
+                break;
+        case PINS_FOR_DEFAULT:
+                pinctrl_register_mappings(u8500_pinmap,
+                                          ARRAY_SIZE(u8500_pinmap));
+        default:
+                break;
+        }
+}
-        nmk_config_pins(snowball_pins,
+void __init mop500_pinmaps_init(void)
-                        ARRAY_SIZE(snowball_pins));
+{
+        pinctrl_register_mappings(mop500_family_pinmap,
+                                  ARRAY_SIZE(mop500_family_pinmap));
+        pinctrl_register_mappings(mop500_pinmap,
+                                  ARRAY_SIZE(mop500_pinmap));
+        mop500_href_family_pinmaps_init();
 }
-void __init hrefv60_pins_init(void)
+void __init snowball_pinmaps_init(void)
 {
-        nmk_config_pins(mop500_pins_common,
+        pinctrl_register_mappings(mop500_family_pinmap,
-                        ARRAY_SIZE(mop500_pins_common));
+                                  ARRAY_SIZE(mop500_family_pinmap));
+        pinctrl_register_mappings(snowball_pinmap,
+                                  ARRAY_SIZE(snowball_pinmap));
+        pinctrl_register_mappings(u8500_pinmap,
+                                  ARRAY_SIZE(u8500_pinmap));
+}
-        nmk_config_pins(hrefv60_pins,
+void __init hrefv60_pinmaps_init(void)
-                        ARRAY_SIZE(hrefv60_pins));
+{
+        pinctrl_register_mappings(mop500_family_pinmap,
+                                  ARRAY_SIZE(mop500_family_pinmap));
+        pinctrl_register_mappings(hrefv60_pinmap,
+                                  ARRAY_SIZE(hrefv60_pinmap));
+        mop500_href_family_pinmaps_init();
 }
diff --git a/arch/arm/mach-ux500/board-mop500-uib.c b/arch/arm/mach-ux500/board-mop500-uib.c
index 5af36aa56c08..b29a788f498c 100644
--- a/arch/arm/mach-ux500/board-mop500-uib.c
+++ b/arch/arm/mach-ux500/board-mop500-uib.c
@@ -102,7 +102,7 @@ static int __init mop500_uib_init(void)
        struct i2c_adapter *i2c0;
        int ret;
-        if (!cpu_is_u8500())
+        if (!cpu_is_u8500_family())
                return -ENODEV;
        if (uib) {
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 77d03c1fbd04..4bc0cbc5f071 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -1,3 +1,4 @@
 /*
 * Copyright (C) 2008-2009 ST-Ericsson
 *
@@ -29,18 +30,17 @@
 #include <linux/smsc911x.h>
 #include <linux/gpio_keys.h>
 #include <linux/delay.h>
 #include <linux/of.h>
 #include <linux/of_platform.h>
 #include <linux/leds.h>
+#include <linux/pinctrl/consumer.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/hardware/gic.h>
 #include <plat/i2c.h>
 #include <plat/ste_dma40.h>
-#include <plat/pincfg.h>
 #include <plat/gpio-nomadik.h>
 #include <mach/hardware.h>
@@ -48,11 +48,11 @@
 #include <mach/devices.h>
 #include <mach/irqs.h>
-#include "pins-db8500.h"
 #include "ste-dma40-db8500.h"
 #include "devices-db8500.h"
 #include "board-mop500.h"
 #include "board-mop500-regulators.h"
+#include "board-mop500-msp.h"
 static struct gpio_led snowball_led_array[] = {
        {
@@ -520,14 +520,6 @@ static struct stedma40_chan_cfg uart2_dma_cfg_tx = {
 };
 #endif
-static pin_cfg_t mop500_pins_uart0[] = {
-        GPIO0_U0_CTSn   | PIN_INPUT_PULLUP,
-        GPIO1_U0_RTSn   | PIN_OUTPUT_HIGH,
-        GPIO2_U0_RXD    | PIN_INPUT_PULLUP,
-        GPIO3_U0_TXD    | PIN_OUTPUT_HIGH,
-};
 #define PRCC_K_SOFTRST_SET      0x18
 #define PRCC_K_SOFTRST_CLEAR    0x1C
 static void ux500_uart0_reset(void)
@@ -548,24 +540,33 @@ static void ux500_uart0_reset(void)
        udelay(1);
 }
+/* This needs to be referenced by callbacks */
+struct pinctrl *u0_p;
+struct pinctrl_state *u0_def;
+struct pinctrl_state *u0_sleep;
 static void ux500_uart0_init(void)
 {
        int ret;
-        ret = nmk_config_pins(mop500_pins_uart0,
+        if (IS_ERR(u0_p) || IS_ERR(u0_def))
-                        ARRAY_SIZE(mop500_pins_uart0));
+                return;
-        if (ret < 0)
-                pr_err("pl011: uart pins_enable failed\n");
+        ret = pinctrl_select_state(u0_p, u0_def);
+        if (ret)
+                pr_err("could not set UART0 defstate\n");
 }
 static void ux500_uart0_exit(void)
 {
        int ret;
-        ret = nmk_config_pins_sleep(mop500_pins_uart0,
+        if (IS_ERR(u0_p) || IS_ERR(u0_sleep))
-                        ARRAY_SIZE(mop500_pins_uart0));
+                return;
-        if (ret < 0)
-                pr_err("pl011: uart pins_disable failed\n");
+        ret = pinctrl_select_state(u0_p, u0_sleep);
+        if (ret)
+                pr_err("could not set UART0 idlestate\n");
 }
 static struct amba_pl011_data uart0_plat = {
@@ -597,7 +598,28 @@ static struct amba_pl011_data uart2_plat = {
 static void __init mop500_uart_init(struct device *parent)
 {
-        db8500_add_uart0(parent, &uart0_plat);
+        struct amba_device *uart0_device;
+        uart0_device = db8500_add_uart0(parent, &uart0_plat);
+        if (uart0_device) {
+                u0_p = pinctrl_get(&uart0_device->dev);
+                if (IS_ERR(u0_p))
+                        dev_err(&uart0_device->dev,
+                                "could not get UART0 pinctrl\n");
+                else {
+                        u0_def = pinctrl_lookup_state(u0_p,
+                                                      PINCTRL_STATE_DEFAULT);
+                        if (IS_ERR(u0_def)) {
+                                dev_err(&uart0_device->dev,
+                                        "could not get UART0 defstate\n");
+                        }
+                        u0_sleep = pinctrl_lookup_state(u0_p,
+                                                        PINCTRL_STATE_SLEEP);
+                        if (IS_ERR(u0_sleep))
+                                dev_err(&uart0_device->dev,
+                                        "could not get UART0 idlestate\n");
+                }
+        }
        db8500_add_uart1(parent, &uart1_plat);
        db8500_add_uart2(parent, &uart2_plat);
 }
@@ -605,7 +627,6 @@ static void __init mop500_uart_init(struct device *parent)
 static struct platform_device *snowball_platform_devs[] __initdata = {
        &snowball_led_dev,
        &snowball_key_dev,
-        &snowball_sbnet_dev,
        &ab8500_device,
 };
@@ -617,10 +638,9 @@ static void __init mop500_init_machine(void)
        mop500_gpio_keys[0].gpio = GPIO_PROX_SENSOR;
+        mop500_pinmaps_init();
        parent = u8500_init_devices();
-        mop500_pins_init();
        /* FIXME: parent of ab8500 should be prcmu */
        for (i = 0; i < ARRAY_SIZE(mop500_platform_devs); i++)
                mop500_platform_devs[i]->dev.parent = parent;
@@ -631,6 +651,7 @@ static void __init mop500_init_machine(void)
        mop500_i2c_init(parent);
        mop500_sdi_init(parent);
        mop500_spi_init(parent);
+        mop500_msp_init(parent);
        mop500_uart_init(parent);
        i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
@@ -646,13 +667,11 @@ static void __init mop500_init_machine(void)
 static void __init snowball_init_machine(void)
 {
        struct device *parent = NULL;
-        int i2c0_devs;
        int i;
+        snowball_pinmaps_init();
        parent = u8500_init_devices();
-        snowball_pins_init();
        for (i = 0; i < ARRAY_SIZE(snowball_platform_devs); i++)
                snowball_platform_devs[i]->dev.parent = parent;
@@ -662,13 +681,9 @@ static void __init snowball_init_machine(void)
        mop500_i2c_init(parent);
        snowball_sdi_init(parent);
        mop500_spi_init(parent);
+        mop500_msp_init(parent);
        mop500_uart_init(parent);
-        i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
-        i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs);
-        i2c_register_board_info(2, mop500_i2c2_devices,
-                                ARRAY_SIZE(mop500_i2c2_devices));
        /* This board has full regulator constraints */
        regulator_has_full_constraints();
 }
@@ -686,10 +701,9 @@ static void __init hrefv60_init_machine(void)
         */
        mop500_gpio_keys[0].gpio = HREFV60_PROX_SENSE_GPIO;
+        hrefv60_pinmaps_init();
        parent = u8500_init_devices();
-        hrefv60_pins_init();
        for (i = 0; i < ARRAY_SIZE(mop500_platform_devs); i++)
                mop500_platform_devs[i]->dev.parent = parent;
@@ -699,6 +713,7 @@ static void __init hrefv60_init_machine(void)
        mop500_i2c_init(parent);
        hrefv60_sdi_init(parent);
        mop500_spi_init(parent);
+        mop500_msp_init(parent);
        mop500_uart_init(parent);
        i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
@@ -746,16 +761,29 @@ MACHINE_END
 #ifdef CONFIG_MACH_UX500_DT
 struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
+        /* Requires DMA and call-back bindings. */
        OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", &uart0_plat),
        OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", &uart1_plat),
        OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", &uart2_plat),
+        /* Requires DMA bindings. */
        OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0",  &ssp0_plat),
+        /* Requires clock name bindings. */
+        OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e000, "gpio.0", NULL),
+        OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e080, "gpio.1", NULL),
+        OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e000, "gpio.2", NULL),
+        OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e080, "gpio.3", NULL),
+        OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e100, "gpio.4", NULL),
+        OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e180, "gpio.5", NULL),
+        OF_DEV_AUXDATA("st,nomadik-gpio", 0x8011e000, "gpio.6", NULL),
+        OF_DEV_AUXDATA("st,nomadik-gpio", 0x8011e080, "gpio.7", NULL),
+        OF_DEV_AUXDATA("st,nomadik-gpio", 0xa03fe000, "gpio.8", NULL),
        {},
 };
-static const struct of_device_id u8500_soc_node[] = {
+static const struct of_device_id u8500_local_bus_nodes[] = {
        /* only create devices below soc node */
        { .compatible = "stericsson,db8500", },
+        { .compatible = "simple-bus"},
        { },
 };
@@ -765,8 +793,15 @@ static void __init u8500_init_machine(void)
        int i2c0_devs;
        int i;
+        /* Pinmaps must be in place before devices register */
+        if (of_machine_is_compatible("st-ericsson,mop500"))
+                mop500_pinmaps_init();
+        else if (of_machine_is_compatible("calaosystems,snowball-a9500"))
+                snowball_pinmaps_init();
+        else if (of_machine_is_compatible("st-ericsson,hrefv60+"))
+                hrefv60_pinmaps_init();
        parent = u8500_init_devices();
-        i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
        for (i = 0; i < ARRAY_SIZE(mop500_platform_devs); i++)
                mop500_platform_devs[i]->dev.parent = parent;
@@ -774,18 +809,22 @@ static void __init u8500_init_machine(void)
                snowball_platform_devs[i]->dev.parent = parent;
        /* automatically probe child nodes of db8500 device */
-        of_platform_populate(NULL, u8500_soc_node, u8500_auxdata_lookup, parent);
+        of_platform_populate(NULL, u8500_local_bus_nodes, u8500_auxdata_lookup, parent);
        if (of_machine_is_compatible("st-ericsson,mop500")) {
                mop500_gpio_keys[0].gpio = GPIO_PROX_SENSOR;
-                mop500_pins_init();
                platform_add_devices(mop500_platform_devs,
                                ARRAY_SIZE(mop500_platform_devs));
                mop500_sdi_init(parent);
+                i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
+                i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs);
+                i2c_register_board_info(2, mop500_i2c2_devices,
+                                        ARRAY_SIZE(mop500_i2c2_devices));
        } else if (of_machine_is_compatible("calaosystems,snowball-a9500")) {
-                snowball_pins_init();
                platform_add_devices(snowball_platform_devs,
                                ARRAY_SIZE(snowball_platform_devs));
@@ -797,19 +836,20 @@ static void __init u8500_init_machine(void)
                 * instead.
                 */
                mop500_gpio_keys[0].gpio = HREFV60_PROX_SENSE_GPIO;
-                i2c0_devs -= NUM_PRE_V60_I2C0_DEVICES;
-                hrefv60_pins_init();
                platform_add_devices(mop500_platform_devs,
                                ARRAY_SIZE(mop500_platform_devs));
                hrefv60_sdi_init(parent);
+                i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
+                i2c0_devs -= NUM_PRE_V60_I2C0_DEVICES;
+                i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs);
+                i2c_register_board_info(2, mop500_i2c2_devices,
+                                        ARRAY_SIZE(mop500_i2c2_devices));
        }
        mop500_i2c_init(parent);
-        i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs);
-        i2c_register_board_info(2, mop500_i2c2_devices,
-                                ARRAY_SIZE(mop500_i2c2_devices));
        /* This board has full regulator constraints */
        regulator_has_full_constraints();
 }
diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
index fdcfa8721bb4..bc44c07c71a9 100644
--- a/arch/arm/mach-ux500/board-mop500.h
+++ b/arch/arm/mach-ux500/board-mop500.h
@@ -7,6 +7,9 @@
 #ifndef __BOARD_MOP500_H
 #define __BOARD_MOP500_H
+/* For NOMADIK_NR_GPIO */
+#include <mach/irqs.h>
 /* Snowball specific GPIO assignments, this board has no GPIO expander */
 #define SNOWBALL_ACCEL_INT1_GPIO        163
 #define SNOWBALL_ACCEL_INT2_GPIO        164
@@ -73,6 +76,7 @@
 #define SNOWBALL_PME_ETH_GPIO           MOP500_AB8500_PIN_GPIO(24)      /* SYSCLKREQ7/GPIO24 */
 #define SNOWBALL_EN_3V3_ETH_GPIO        MOP500_AB8500_PIN_GPIO(26)      /* GPIO26 */
+struct device;
 struct i2c_board_info;
 extern void mop500_sdi_init(struct device *parent);
@@ -81,9 +85,9 @@ extern void hrefv60_sdi_init(struct device *parent);
 extern void mop500_sdi_tc35892_init(struct device *parent);
 void __init mop500_u8500uib_init(void);
 void __init mop500_stuib_init(void);
-void __init mop500_pins_init(void);
+void __init mop500_pinmaps_init(void);
-void __init hrefv60_pins_init(void);
+void __init snowball_pinmaps_init(void);
-void __init snowball_pins_init(void);
+void __init hrefv60_pinmaps_init(void);
 void mop500_uib_i2c_add(int busnum, struct i2c_board_info *info,
                unsigned n);
diff --git a/arch/arm/mach-ux500/board-u5500-sdi.c b/arch/arm/mach-ux500/board-u5500-sdi.c
deleted file mode 100644
index 836112eedde7..000000000000
--- a/arch/arm/mach-ux500/board-u5500-sdi.c
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2010
- *
- * Author: Hanumath Prasad <ulf.hansson@stericsson.com>
- * License terms: GNU General Public License (GPL) version 2
- */
-#include <linux/amba/mmci.h>
-#include <linux/mmc/host.h>
-#include <plat/pincfg.h>
-#include <plat/gpio-nomadik.h>
-#include <mach/db5500-regs.h>
-#include <plat/ste_dma40.h>
-#include "pins-db5500.h"
-#include "devices-db5500.h"
-#include "ste-dma40-db5500.h"
-static pin_cfg_t u5500_sdi_pins[] = {
-        /* SDI0 (POP eMMC) */
-        GPIO5_MC0_DAT0          | PIN_DIR_INPUT | PIN_PULL_UP,
-        GPIO6_MC0_DAT1          | PIN_DIR_INPUT | PIN_PULL_UP,
-        GPIO7_MC0_DAT2          | PIN_DIR_INPUT | PIN_PULL_UP,
-        GPIO8_MC0_DAT3          | PIN_DIR_INPUT | PIN_PULL_UP,
-        GPIO9_MC0_DAT4          | PIN_DIR_INPUT | PIN_PULL_UP,
-        GPIO10_MC0_DAT5         | PIN_DIR_INPUT | PIN_PULL_UP,
-        GPIO11_MC0_DAT6         | PIN_DIR_INPUT | PIN_PULL_UP,
-        GPIO12_MC0_DAT7         | PIN_DIR_INPUT | PIN_PULL_UP,
-        GPIO13_MC0_CMD          | PIN_DIR_INPUT | PIN_PULL_UP,
-        GPIO14_MC0_CLK          | PIN_DIR_OUTPUT | PIN_VAL_LOW,
-};
-#ifdef CONFIG_STE_DMA40
-struct stedma40_chan_cfg u5500_sdi0_dma_cfg_rx = {
-        .mode = STEDMA40_MODE_LOGICAL,
-        .dir = STEDMA40_PERIPH_TO_MEM,
-        .src_dev_type = DB5500_DMA_DEV24_SDMMC0_RX,
-        .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
-        .src_info.data_width = STEDMA40_WORD_WIDTH,
-        .dst_info.data_width = STEDMA40_WORD_WIDTH,
-};
-static struct stedma40_chan_cfg u5500_sdi0_dma_cfg_tx = {
-        .mode = STEDMA40_MODE_LOGICAL,
-        .dir = STEDMA40_MEM_TO_PERIPH,
-        .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
-        .dst_dev_type = DB5500_DMA_DEV24_SDMMC0_TX,
-        .src_info.data_width = STEDMA40_WORD_WIDTH,
-        .dst_info.data_width = STEDMA40_WORD_WIDTH,
-};
-#endif
-static struct mmci_platform_data u5500_sdi0_data = {
-        .ocr_mask       = MMC_VDD_165_195,
-        .f_max          = 50000000,
-        .capabilities   = MMC_CAP_4_BIT_DATA |
-                                MMC_CAP_8_BIT_DATA |
-                                MMC_CAP_MMC_HIGHSPEED,
-        .gpio_cd        = -1,
-        .gpio_wp        = -1,
-#ifdef CONFIG_STE_DMA40
-        .dma_filter     = stedma40_filter,
-        .dma_rx_param   = &u5500_sdi0_dma_cfg_rx,
-        .dma_tx_param   = &u5500_sdi0_dma_cfg_tx,
-#endif
-};
-void __init u5500_sdi_init(struct device *parent)
-{
-        nmk_config_pins(u5500_sdi_pins, ARRAY_SIZE(u5500_sdi_pins));
-        db5500_add_sdi0(parent, &u5500_sdi0_data);
-}
diff --git a/arch/arm/mach-ux500/board-u5500.c b/arch/arm/mach-ux500/board-u5500.c
deleted file mode 100644
index 0ff4be72a809..000000000000
--- a/arch/arm/mach-ux500/board-u5500.c
+++ /dev/null
@@ -1,162 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2010
- *
- * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
- * License terms: GNU General Public License (GPL) version 2
- */
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/amba/bus.h>
-#include <linux/irq.h>
-#include <linux/i2c.h>
-#include <linux/mfd/abx500/ab5500.h>
-#include <asm/hardware/gic.h>
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-#include <plat/pincfg.h>
-#include <plat/i2c.h>
-#include <plat/gpio-nomadik.h>
-#include <mach/hardware.h>
-#include <mach/devices.h>
-#include <mach/setup.h>
-#include "pins-db5500.h"
-#include "devices-db5500.h"
-#include <linux/led-lm3530.h>
-/*
- * GPIO
- */
-static pin_cfg_t u5500_pins[] = {
-        /* I2C */
-        GPIO218_I2C2_SCL        | PIN_INPUT_PULLUP,
-        GPIO219_I2C2_SDA        | PIN_INPUT_PULLUP,
-        /* DISPLAY_ENABLE */
-        GPIO226_GPIO        | PIN_OUTPUT_LOW,
-        /* Backlight Enbale */
-        GPIO224_GPIO        | PIN_OUTPUT_HIGH,
-};
-/*
- * I2C
- */
-#define U5500_I2C_CONTROLLER(id, _slsu, _tft, _rft, clk, _sm) \
-static struct nmk_i2c_controller u5500_i2c##id##_data = { \
-        /*                              \
-         * slave data setup time, which is      \
-         * 250 ns,100ns,10ns which is 14,6,2    \
-         * respectively for a 48 Mhz    \
-         * i2c clock                    \
-         */                             \
-        .slsu           = _slsu,        \
-        /* Tx FIFO threshold */         \
-        .tft            = _tft,         \
-        /* Rx FIFO threshold */         \
-        .rft            = _rft,         \
-        /* std. mode operation */       \
-        .clk_freq       = clk,          \
-        .sm             = _sm,          \
-}
-/*
- * The board uses TODO <3> i2c controllers, initialize all of
- * them with slave data setup time of 250 ns,
- * Tx & Rx FIFO threshold values as 1 and standard
- * mode of operation
- */
-U5500_I2C_CONTROLLER(2, 0xe, 1, 1, 400000, I2C_FREQ_MODE_FAST);
-static struct lm3530_platform_data u5500_als_platform_data = {
-        .mode = LM3530_BL_MODE_MANUAL,
-        .als_input_mode = LM3530_INPUT_ALS1,
-        .max_current = LM3530_FS_CURR_26mA,
-        .pwm_pol_hi = true,
-        .als_avrg_time = LM3530_ALS_AVRG_TIME_512ms,
-        .brt_ramp_law = 1,      /* Linear */
-        .brt_ramp_fall = LM3530_RAMP_TIME_8s,
-        .brt_ramp_rise = LM3530_RAMP_TIME_8s,
-        .als1_resistor_sel = LM3530_ALS_IMPD_13_53kOhm,
-        .als2_resistor_sel = LM3530_ALS_IMPD_Z,
-        .als_vmin = 730,        /* mV */
-        .als_vmax = 1020,       /* mV */
-        .brt_val = 0x7F,        /* Max brightness */
-};
-static struct i2c_board_info __initdata u5500_i2c2_devices[] = {
-        {
-                /* Backlight */
-                I2C_BOARD_INFO("lm3530-led", 0x36),
-                .platform_data = &u5500_als_platform_data,
-        },
-};
-static void __init u5500_i2c_init(struct device *parent)
-{
-        db5500_add_i2c2(parent, &u5500_i2c2_data);
-        i2c_register_board_info(2, ARRAY_AND_SIZE(u5500_i2c2_devices));
-}
-static struct ab5500_platform_data ab5500_plf_data = {
-        .irq = {
-                .base = 0,
-                .count = 0,
-        },
-        .init_settings = NULL,
-        .init_settings_sz = 0,
-        .pm_power_off = false,
-};
-static struct platform_device ab5500_device = {
-        .name = "ab5500-core",
-        .id = 0,
-        .dev = {
-                .platform_data = &ab5500_plf_data,
-        },
-        .num_resources = 0,
-};
-static struct platform_device *u5500_platform_devices[] __initdata = {
-        &ab5500_device,
-};
-static void __init u5500_uart_init(struct device *parent)
-{
-        db5500_add_uart0(parent, NULL);
-        db5500_add_uart1(parent, NULL);
-        db5500_add_uart2(parent, NULL);
-}
-static void __init u5500_init_machine(void)
-{
-        struct device *parent = NULL;
-        int i;
-        parent = u5500_init_devices();
-        nmk_config_pins(u5500_pins, ARRAY_SIZE(u5500_pins));
-        u5500_i2c_init(parent);
-        u5500_sdi_init(parent);
-        u5500_uart_init(parent);
-        for (i = 0; i < ARRAY_SIZE(u5500_platform_devices); i++)
-                u5500_platform_devices[i]->dev.parent = parent;
-        platform_add_devices(u5500_platform_devices,
-                ARRAY_SIZE(u5500_platform_devices));
-}
-MACHINE_START(U5500, "ST-Ericsson U5500 Platform")
-        .atag_offset    = 0x100,
-        .map_io         = u5500_map_io,
-        .init_irq       = ux500_init_irq,
-        .timer          = &ux500_timer,
-        .handle_irq     = gic_handle_irq,
-        .init_machine   = u5500_init_machine,
-MACHINE_END
diff --git a/arch/arm/mach-ux500/cache-l2x0.c b/arch/arm/mach-ux500/cache-l2x0.c
index 77a75ed0df67..dc12394295d5 100644
--- a/arch/arm/mach-ux500/cache-l2x0.c
+++ b/arch/arm/mach-ux500/cache-l2x0.c
@@ -36,9 +36,9 @@ static int __init ux500_l2x0_unlock(void)
 static int __init ux500_l2x0_init(void)
 {
-        if (cpu_is_u5500())
+        u32 aux_val = 0x3e000000;
-                l2x0_base = __io_address(U5500_L2CC_BASE);
-        else if (cpu_is_u8500())
+        if (cpu_is_u8500_family())
                l2x0_base = __io_address(U8500_L2CC_BASE);
        else
                ux500_unknown_soc();
@@ -46,11 +46,19 @@ static int __init ux500_l2x0_init(void)
        /* Unlock before init */
        ux500_l2x0_unlock();
+        /* DB9540's L2 has 128KB way size */
+        if (cpu_is_u9540())
+                /* 128KB way size */
+                aux_val |= (0x4 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT);
+        else
+                /* 64KB way size */
+                aux_val |= (0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT);
        /* 64KB way size, 8 way associativity, force WA */
        if (of_have_populated_dt())
-                l2x0_of_init(0x3e060000, 0xc0000fff);
+                l2x0_of_init(aux_val, 0xc0000fff);
        else
-                l2x0_init(l2x0_base, 0x3e060000, 0xc0000fff);
+                l2x0_init(l2x0_base, aux_val, 0xc0000fff);
        /*
         * We can't disable l2 as we are in non secure mode, currently
diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c
index ec35f0aa5665..a121cb472dd6 100644
--- a/arch/arm/mach-ux500/clock.c
+++ b/arch/arm/mach-ux500/clock.c
@@ -149,9 +149,7 @@ static unsigned long clk_mtu_get_rate(struct clk *clk)
        unsigned long mturate;
        unsigned long retclk;
-        if (cpu_is_u5500())
+        if (cpu_is_u8500_family())
-                addr = __io_address(U5500_PRCMU_BASE);
-        else if (cpu_is_u8500())
                addr = __io_address(U8500_PRCMU_BASE);
        else
                ux500_unknown_soc();
@@ -336,6 +334,7 @@ static DEFINE_PRCMU_CLK(uiccclk,	0x4, 1, UICCCLK); /* v1 */
 */
 /* Peripheral Cluster #1 */
+static DEFINE_PRCC_CLK(1, msp3,         11, 10, &clk_msp1clk);
 static DEFINE_PRCC_CLK(1, i2c4,         10, 9, &clk_i2cclk);
 static DEFINE_PRCC_CLK(1, gpio0,        9, -1, NULL);
 static DEFINE_PRCC_CLK(1, slimbus0,     8,  8, &clk_slimclk);
@@ -405,7 +404,7 @@ static struct clk_lookup u8500_clks[] = {
        CLK(slimbus0,   "slimbus0",     NULL),
        CLK(i2c2,       "nmk-i2c.2",    NULL),
        CLK(sdi0,       "sdi0",         NULL),
-        CLK(msp0,       "msp0",         NULL),
+        CLK(msp0,       "ux500-msp-i2s.0",      NULL),
        CLK(i2c1,       "nmk-i2c.1",    NULL),
        CLK(uart1,      "uart1",        NULL),
        CLK(uart0,      "uart0",        NULL),
@@ -455,7 +454,8 @@ static struct clk_lookup u8500_clks[] = {
        /* Peripheral Cluster #1 */
        CLK(i2c4,       "nmk-i2c.4",    NULL),
        CLK(spi3,       "spi3",         NULL),
-        CLK(msp1,       "msp1",         NULL),
+        CLK(msp1,       "ux500-msp-i2s.1",      NULL),
+        CLK(msp3,       "ux500-msp-i2s.3",      NULL),
        /* Peripheral Cluster #2 */
        CLK(gpio1,      "gpio.6",       NULL),
@@ -465,7 +465,7 @@ static struct clk_lookup u8500_clks[] = {
        CLK(spi0,       "spi0",         NULL),
        CLK(sdi3,       "sdi3",         NULL),
        CLK(sdi1,       "sdi1",         NULL),
-        CLK(msp2,       "msp2",         NULL),
+        CLK(msp2,       "ux500-msp-i2s.2",      NULL),
        CLK(sdi4,       "sdi4",         NULL),
        CLK(pwl,        "pwl",          NULL),
        CLK(spi1,       "spi1",         NULL),
@@ -705,14 +705,6 @@ late_initcall(clk_init_smp_twd_cpufreq);
 int __init clk_init(void)
 {
-        if (cpu_is_u5500()) {
-                /* Clock tree for U5500 not implemented yet */
-                clk_prcc_ops.enable = clk_prcc_ops.disable = NULL;
-                clk_prcmu_ops.enable = clk_prcmu_ops.disable = NULL;
-                clk_uartclk.rate = 36360000;
-                clk_sdmmcclk.rate = 99900000;
-        }
        clkdev_add_table(u8500_clks, ARRAY_SIZE(u8500_clks));
        clkdev_add(&clk_smp_twd_lookup);
diff --git a/arch/arm/mach-ux500/cpu-db5500.c b/arch/arm/mach-ux500/cpu-db5500.c
deleted file mode 100644
index bca47f32082f..000000000000
--- a/arch/arm/mach-ux500/cpu-db5500.c
+++ /dev/null
@@ -1,247 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2010
- *
- * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
- * License terms: GNU General Public License (GPL) version 2
- */
-#include <linux/platform_device.h>
-#include <linux/amba/bus.h>
-#include <linux/io.h>
-#include <linux/irq.h>
-#include <asm/mach/map.h>
-#include <asm/pmu.h>
-#include <plat/gpio-nomadik.h>
-#include <mach/hardware.h>
-#include <mach/devices.h>
-#include <mach/setup.h>
-#include <mach/irqs.h>
-#include <mach/usb.h>
-#include "devices-db5500.h"
-#include "ste-dma40-db5500.h"
-static struct map_desc u5500_uart_io_desc[] __initdata = {
-        __IO_DEV_DESC(U5500_UART0_BASE, SZ_4K),
-        __IO_DEV_DESC(U5500_UART2_BASE, SZ_4K),
-};
-static struct map_desc u5500_io_desc[] __initdata = {
-        /* SCU base also covers GIC CPU BASE and TWD with its 4K page */
-        __IO_DEV_DESC(U5500_SCU_BASE, SZ_4K),
-        __IO_DEV_DESC(U5500_GIC_DIST_BASE, SZ_4K),
-        __IO_DEV_DESC(U5500_L2CC_BASE, SZ_4K),
-        __IO_DEV_DESC(U5500_MTU0_BASE, SZ_4K),
-        __IO_DEV_DESC(U5500_BACKUPRAM0_BASE, SZ_8K),
-        __IO_DEV_DESC(U5500_GPIO0_BASE, SZ_4K),
-        __IO_DEV_DESC(U5500_GPIO1_BASE, SZ_4K),
-        __IO_DEV_DESC(U5500_GPIO2_BASE, SZ_4K),
-        __IO_DEV_DESC(U5500_GPIO3_BASE, SZ_4K),
-        __IO_DEV_DESC(U5500_GPIO4_BASE, SZ_4K),
-        __IO_DEV_DESC(U5500_PRCMU_BASE, SZ_4K),
-        __IO_DEV_DESC(U5500_PRCMU_TCDM_BASE, SZ_4K),
-};
-static struct resource mbox0_resources[] = {
-        {
-                .name = "mbox_peer",
-                .start = U5500_MBOX0_PEER_START,
-                .end = U5500_MBOX0_PEER_END,
-                .flags = IORESOURCE_MEM,
-        },
-        {
-                .name = "mbox_local",
-                .start = U5500_MBOX0_LOCAL_START,
-                .end = U5500_MBOX0_LOCAL_END,
-                .flags = IORESOURCE_MEM,
-        },
-        {
-                .name = "mbox_irq",
-                .start = MBOX_PAIR0_VIRT_IRQ,
-                .end = MBOX_PAIR0_VIRT_IRQ,
-                .flags = IORESOURCE_IRQ,
-        }
-};
-static struct resource mbox1_resources[] = {
-        {
-                .name = "mbox_peer",
-                .start = U5500_MBOX1_PEER_START,
-                .end = U5500_MBOX1_PEER_END,
-                .flags = IORESOURCE_MEM,
-        },
-        {
-                .name = "mbox_local",
-                .start = U5500_MBOX1_LOCAL_START,
-                .end = U5500_MBOX1_LOCAL_END,
-                .flags = IORESOURCE_MEM,
-        },
-        {
-                .name = "mbox_irq",
-                .start = MBOX_PAIR1_VIRT_IRQ,
-                .end = MBOX_PAIR1_VIRT_IRQ,
-                .flags = IORESOURCE_IRQ,
-        }
-};
-static struct resource mbox2_resources[] = {
-        {
-                .name = "mbox_peer",
-                .start = U5500_MBOX2_PEER_START,
-                .end = U5500_MBOX2_PEER_END,
-                .flags = IORESOURCE_MEM,
-        },
-        {
-                .name = "mbox_local",
-                .start = U5500_MBOX2_LOCAL_START,
-                .end = U5500_MBOX2_LOCAL_END,
-                .flags = IORESOURCE_MEM,
-        },
-        {
-                .name = "mbox_irq",
-                .start = MBOX_PAIR2_VIRT_IRQ,
-                .end = MBOX_PAIR2_VIRT_IRQ,
-                .flags = IORESOURCE_IRQ,
-        }
-};
-static struct platform_device mbox0_device = {
-        .id = 0,
-        .name = "mbox",
-        .resource = mbox0_resources,
-        .num_resources = ARRAY_SIZE(mbox0_resources),
-};
-static struct platform_device mbox1_device = {
-        .id = 1,
-        .name = "mbox",
-        .resource = mbox1_resources,
-        .num_resources = ARRAY_SIZE(mbox1_resources),
-};
-static struct platform_device mbox2_device = {
-        .id = 2,
-        .name = "mbox",
-        .resource = mbox2_resources,
-        .num_resources = ARRAY_SIZE(mbox2_resources),
-};
-static struct platform_device *db5500_platform_devs[] __initdata = {
-        &mbox0_device,
-        &mbox1_device,
-        &mbox2_device,
-};
-static resource_size_t __initdata db5500_gpio_base[] = {
-        U5500_GPIOBANK0_BASE,
-        U5500_GPIOBANK1_BASE,
-        U5500_GPIOBANK2_BASE,
-        U5500_GPIOBANK3_BASE,
-        U5500_GPIOBANK4_BASE,
-        U5500_GPIOBANK5_BASE,
-        U5500_GPIOBANK6_BASE,
-        U5500_GPIOBANK7_BASE,
-};
-static void __init db5500_add_gpios(struct device *parent)
-{
-        struct nmk_gpio_platform_data pdata = {
-                /* No custom data yet */
-        };
-        dbx500_add_gpios(parent, ARRAY_AND_SIZE(db5500_gpio_base),
-                         IRQ_DB5500_GPIO0, &pdata);
-}
-void __init u5500_map_io(void)
-{
-        /*
-         * Map the UARTs early so that the DEBUG_LL stuff continues to work.
-         */
-        iotable_init(u5500_uart_io_desc, ARRAY_SIZE(u5500_uart_io_desc));
-        ux500_map_io();
-        iotable_init(u5500_io_desc, ARRAY_SIZE(u5500_io_desc));
-        _PRCMU_BASE = __io_address(U5500_PRCMU_BASE);
-}
-static void __init db5500_pmu_init(void)
-{
-        struct resource res[] = {
-                [0] = {
-                        .start          = IRQ_DB5500_PMU0,
-                        .end            = IRQ_DB5500_PMU0,
-                        .flags          = IORESOURCE_IRQ,
-                },
-                [1] = {
-                        .start          = IRQ_DB5500_PMU1,
-                        .end            = IRQ_DB5500_PMU1,
-                        .flags          = IORESOURCE_IRQ,
-                },
-        };
-        platform_device_register_simple("arm-pmu", ARM_PMU_DEVICE_CPU,
-                                        res, ARRAY_SIZE(res));
-}
-static int usb_db5500_rx_dma_cfg[] = {
-        DB5500_DMA_DEV4_USB_OTG_IEP_1_9,
-        DB5500_DMA_DEV5_USB_OTG_IEP_2_10,
-        DB5500_DMA_DEV6_USB_OTG_IEP_3_11,
-        DB5500_DMA_DEV20_USB_OTG_IEP_4_12,
-        DB5500_DMA_DEV21_USB_OTG_IEP_5_13,
-        DB5500_DMA_DEV22_USB_OTG_IEP_6_14,
-        DB5500_DMA_DEV23_USB_OTG_IEP_7_15,
-        DB5500_DMA_DEV38_USB_OTG_IEP_8
-};
-static int usb_db5500_tx_dma_cfg[] = {
-        DB5500_DMA_DEV4_USB_OTG_OEP_1_9,
-        DB5500_DMA_DEV5_USB_OTG_OEP_2_10,
-        DB5500_DMA_DEV6_USB_OTG_OEP_3_11,
-        DB5500_DMA_DEV20_USB_OTG_OEP_4_12,
-        DB5500_DMA_DEV21_USB_OTG_OEP_5_13,
-        DB5500_DMA_DEV22_USB_OTG_OEP_6_14,
-        DB5500_DMA_DEV23_USB_OTG_OEP_7_15,
-        DB5500_DMA_DEV38_USB_OTG_OEP_8
-};
-static const char *db5500_read_soc_id(void)
-{
-        return kasprintf(GFP_KERNEL, "u5500 currently unsupported\n");
-}
-static struct device * __init db5500_soc_device_init(void)
-{
-        const char *soc_id = db5500_read_soc_id();
-        return ux500_soc_device_init(soc_id);
-}
-struct device * __init u5500_init_devices(void)
-{
-        struct device *parent;
-        int i;
-        parent = db5500_soc_device_init();
-        db5500_add_gpios(parent);
-        db5500_pmu_init();
-        db5500_dma_init(parent);
-        db5500_add_rtc(parent);
-        db5500_add_usb(parent, usb_db5500_rx_dma_cfg, usb_db5500_tx_dma_cfg);
-        for (i = 0; i < ARRAY_SIZE(db5500_platform_devs); i++)
-                db5500_platform_devs[i]->dev.parent = parent;
-        platform_add_devices(db5500_platform_devs,
-                             ARRAY_SIZE(db5500_platform_devs));
-        return parent;
-}
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 9bd8163896cf..16169c4bf6ca 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -34,8 +34,8 @@ static struct map_desc u8500_uart_io_desc[] __initdata = {
        __IO_DEV_DESC(U8500_UART0_BASE, SZ_4K),
        __IO_DEV_DESC(U8500_UART2_BASE, SZ_4K),
 };
+/*  U8500 and U9540 common io_desc */
-static struct map_desc u8500_io_desc[] __initdata = {
+static struct map_desc u8500_common_io_desc[] __initdata = {
        /* SCU base also covers GIC CPU BASE and TWD with its 4K page */
        __IO_DEV_DESC(U8500_SCU_BASE, SZ_4K),
        __IO_DEV_DESC(U8500_GIC_DIST_BASE, SZ_4K),
@@ -49,12 +49,23 @@ static struct map_desc u8500_io_desc[] __initdata = {
        __IO_DEV_DESC(U8500_CLKRST5_BASE, SZ_4K),
        __IO_DEV_DESC(U8500_CLKRST6_BASE, SZ_4K),
-        __IO_DEV_DESC(U8500_PRCMU_BASE, SZ_4K),
        __IO_DEV_DESC(U8500_GPIO0_BASE, SZ_4K),
        __IO_DEV_DESC(U8500_GPIO1_BASE, SZ_4K),
        __IO_DEV_DESC(U8500_GPIO2_BASE, SZ_4K),
        __IO_DEV_DESC(U8500_GPIO3_BASE, SZ_4K),
+};
+/* U8500 IO map specific description */
+static struct map_desc u8500_io_desc[] __initdata = {
+        __IO_DEV_DESC(U8500_PRCMU_BASE, SZ_4K),
        __IO_DEV_DESC(U8500_PRCMU_TCDM_BASE, SZ_4K),
+};
+/* U9540 IO map specific description */
+static struct map_desc u9540_io_desc[] __initdata = {
+        __IO_DEV_DESC(U8500_PRCMU_BASE, SZ_4K + SZ_8K),
+        __IO_DEV_DESC(U8500_PRCMU_TCDM_BASE, SZ_4K + SZ_8K),
 };
 void __init u8500_map_io(void)
@@ -66,7 +77,12 @@ void __init u8500_map_io(void)
        ux500_map_io();
-        iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc));
+        iotable_init(u8500_common_io_desc, ARRAY_SIZE(u8500_common_io_desc));
+        if (cpu_is_u9540())
+                iotable_init(u9540_io_desc, ARRAY_SIZE(u9540_io_desc));
+        else
+                iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc));
        _PRCMU_BASE = __io_address(U8500_PRCMU_BASE);
 }
@@ -121,6 +137,12 @@ static struct platform_device *platform_devs[] __initdata = {
        &db8500_prcmu_device,
 };
+static struct platform_device *of_platform_devs[] __initdata = {
+        &u8500_dma40_device,
+        &db8500_pmu_device,
+        &db8500_prcmu_device,
+};
 static resource_size_t __initdata db8500_gpio_base[] = {
        U8500_GPIOBANK0_BASE,
        U8500_GPIOBANK1_BASE,
@@ -141,6 +163,7 @@ static void __init db8500_add_gpios(struct device *parent)
        dbx500_add_gpios(parent, ARRAY_AND_SIZE(db8500_gpio_base),
                         IRQ_DB8500_GPIO0, &pdata);
+        dbx500_add_pinctrl(parent, "pinctrl-db8500");
 }
 static int usb_db8500_rx_dma_cfg[] = {
@@ -199,10 +222,16 @@ struct device * __init u8500_init_devices(void)
        platform_device_register_data(parent,
                "cpufreq-u8500", -1, NULL, 0);
-        for (i = 0; i < ARRAY_SIZE(platform_devs); i++)
+        for (i = 0; i < ARRAY_SIZE(of_platform_devs); i++)
-                platform_devs[i]->dev.parent = parent;
+                of_platform_devs[i]->dev.parent = parent;
-        platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
+        /*
+         * Devices to be DT:ed:
+         *   u8500_dma40_device  = todo
+         *   db8500_pmu_device   = todo
+         *   db8500_prcmu_device = todo
+         */
+        platform_add_devices(of_platform_devs, ARRAY_SIZE(of_platform_devs));
        return parent;
 }
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index d11f3892a27d..a29a0e3adcf9 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -10,7 +10,6 @@
 #include <linux/io.h>
 #include <linux/clk.h>
 #include <linux/mfd/db8500-prcmu.h>
-#include <linux/mfd/db5500-prcmu.h>
 #include <linux/clksrc-dbx500-prcmu.h>
 #include <linux/sys_soc.h>
 #include <linux/err.h>
@@ -30,6 +29,18 @@
 void __iomem *_PRCMU_BASE;
+/*
+ * FIXME: Should we set up the GPIO domain here?
+ *
+ * The problem is that we cannot put the interrupt resources into the platform
+ * device until the irqdomain has been added. Right now, we set the GIC interrupt
+ * domain from init_irq(), then load the gpio driver from
+ * core_initcall(nmk_gpio_init) and add the platform devices from
+ * arch_initcall(customize_machine).
+ *
+ * This feels fragile because it depends on the gpio device getting probed
+ * _before_ any device uses the gpio interrupts.
+*/
 static const struct of_device_id ux500_dt_irq_match[] = {
        { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
        {},
@@ -40,10 +51,7 @@ void __init ux500_init_irq(void)
        void __iomem *dist_base;
        void __iomem *cpu_base;
-        if (cpu_is_u5500()) {
+        if (cpu_is_u8500_family()) {
-                dist_base = __io_address(U5500_GIC_DIST_BASE);
-                cpu_base = __io_address(U5500_GIC_CPU_BASE);
-        } else if (cpu_is_u8500()) {
                dist_base = __io_address(U8500_GIC_DIST_BASE);
                cpu_base = __io_address(U8500_GIC_CPU_BASE);
        } else
@@ -60,9 +68,7 @@ void __init ux500_init_irq(void)
         * Init clocks here so that they are available for system timer
         * initialization.
         */
-        if (cpu_is_u5500())
+        if (cpu_is_u8500_family())
-                db5500_prcmu_early_init();
-        if (cpu_is_u8500())
                db8500_prcmu_early_init();
        clk_init();
 }
diff --git a/arch/arm/mach-ux500/cpuidle.c b/arch/arm/mach-ux500/cpuidle.c
new file mode 100644
index 000000000000..b54884bd2549
--- /dev/null
+++ b/arch/arm/mach-ux500/cpuidle.c
@@ -0,0 +1,171 @@
+/*
+ * Copyright (c) 2012 Linaro : Daniel Lezcano <daniel.lezcano@linaro.org> (IBM)
+ *
+ * Based on the work of Rickard Andersson <rickard.andersson@stericsson.com>
+ * and Jonas Aaberg <jonas.aberg@stericsson.com>.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/module.h>
+#include <linux/cpuidle.h>
+#include <linux/clockchips.h>
+#include <linux/spinlock.h>
+#include <linux/atomic.h>
+#include <linux/smp.h>
+#include <linux/mfd/dbx500-prcmu.h>
+#include <asm/cpuidle.h>
+#include <asm/proc-fns.h>
+static atomic_t master = ATOMIC_INIT(0);
+static DEFINE_SPINLOCK(master_lock);
+static DEFINE_PER_CPU(struct cpuidle_device, ux500_cpuidle_device);
+static inline int ux500_enter_idle(struct cpuidle_device *dev,
+                                   struct cpuidle_driver *drv, int index)
+{
+        int this_cpu = smp_processor_id();
+        bool recouple = false;
+        clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &this_cpu);
+        if (atomic_inc_return(&master) == num_online_cpus()) {
+                /* With this lock, we prevent the other cpu to exit and enter
+                 * this function again and become the master */
+                if (!spin_trylock(&master_lock))
+                        goto wfi;
+                /* decouple the gic from the A9 cores */
+                if (prcmu_gic_decouple())
+                        goto out;
+                /* If an error occur, we will have to recouple the gic
+                 * manually */
+                recouple = true;
+                /* At this state, as the gic is decoupled, if the other
+                 * cpu is in WFI, we have the guarantee it won't be wake
+                 * up, so we can safely go to retention */
+                if (!prcmu_is_cpu_in_wfi(this_cpu ? 0 : 1))
+                        goto out;
+                /* The prcmu will be in charge of watching the interrupts
+                 * and wake up the cpus */
+                if (prcmu_copy_gic_settings())
+                        goto out;
+                /* Check in the meantime an interrupt did
+                 * not occur on the gic ... */
+                if (prcmu_gic_pending_irq())
+                        goto out;
+                /* ... and the prcmu */
+                if (prcmu_pending_irq())
+                        goto out;
+                /* Go to the retention state, the prcmu will wait for the
+                 * cpu to go WFI and this is what happens after exiting this
+                 * 'master' critical section */
+                if (prcmu_set_power_state(PRCMU_AP_IDLE, true, true))
+                        goto out;
+                /* When we switch to retention, the prcmu is in charge
+                 * of recoupling the gic automatically */
+                recouple = false;
+                spin_unlock(&master_lock);
+        }
+wfi:
+        cpu_do_idle();
+out:
+        atomic_dec(&master);
+        if (recouple) {
+                prcmu_gic_recouple();
+                spin_unlock(&master_lock);
+        }
+        clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &this_cpu);
+        return index;
+}
+static struct cpuidle_driver ux500_idle_driver = {
+        .name = "ux500_idle",
+        .owner = THIS_MODULE,
+        .en_core_tk_irqen = 1,
+        .states = {
+                ARM_CPUIDLE_WFI_STATE,
+                {
+                        .enter            = ux500_enter_idle,
+                        .exit_latency     = 70,
+                        .target_residency = 260,
+                        .flags            = CPUIDLE_FLAG_TIME_VALID,
+                        .name             = "ApIdle",
+                        .desc             = "ARM Retention",
+                },
+        },
+        .safe_state_index = 0,
+        .state_count = 2,
+};
+/*
+ * For each cpu, setup the broadcast timer because we will
+ * need to migrate the timers for the states >= ApIdle.
+ */
+static void ux500_setup_broadcast_timer(void *arg)
+{
+        int cpu = smp_processor_id();
+        clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ON, &cpu);
+}
+int __init ux500_idle_init(void)
+{
+        int ret, cpu;
+        struct cpuidle_device *device;
+        /* Configure wake up reasons */
+        prcmu_enable_wakeups(PRCMU_WAKEUP(ARM) | PRCMU_WAKEUP(RTC) |
+                             PRCMU_WAKEUP(ABB));
+        /*
+         * Configure the timer broadcast for each cpu, that must
+         * be done from the cpu context, so we use a smp cross
+         * call with 'on_each_cpu'.
+         */
+        on_each_cpu(ux500_setup_broadcast_timer, NULL, 1);
+        ret = cpuidle_register_driver(&ux500_idle_driver);
+        if (ret) {
+                printk(KERN_ERR "failed to register ux500 idle driver\n");
+                return ret;
+        }
+        for_each_online_cpu(cpu) {
+                device = &per_cpu(ux500_cpuidle_device, cpu);
+                device->cpu = cpu;
+                ret = cpuidle_register_device(device);
+                if (ret) {
+                        printk(KERN_ERR "Failed to register cpuidle "
+                               "device for cpu%d\n", cpu);
+                        goto out_unregister;
+                }
+        }
+out:
+        return ret;
+out_unregister:
+        for_each_online_cpu(cpu) {
+                device = &per_cpu(ux500_cpuidle_device, cpu);
+                cpuidle_unregister_device(device);
+        }
+        cpuidle_unregister_driver(&ux500_idle_driver);
+        goto out;
+}
+device_initcall(ux500_idle_init);
diff --git a/arch/arm/mach-ux500/devices-common.c b/arch/arm/mach-ux500/devices-common.c
index c5312a4b49f5..dfdd4a54668d 100644
--- a/arch/arm/mach-ux500/devices-common.c
+++ b/arch/arm/mach-ux500/devices-common.c
@@ -11,7 +11,6 @@
 #include <linux/irq.h>
 #include <linux/slab.h>
 #include <linux/platform_device.h>
-#include <linux/amba/bus.h>
 #include <plat/gpio-nomadik.h>
@@ -19,38 +18,6 @@
 #include "devices-common.h"
-struct amba_device *
-dbx500_add_amba_device(struct device *parent, const char *name,
-                       resource_size_t base, int irq, void *pdata,
-                       unsigned int periphid)
-{
-        struct amba_device *dev;
-        int ret;
-        dev = amba_device_alloc(name, base, SZ_4K);
-        if (!dev)
-                return ERR_PTR(-ENOMEM);
-        dev->dma_mask = DMA_BIT_MASK(32);
-        dev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
-        dev->irq[0] = irq;
-        dev->periphid = periphid;
-        dev->dev.platform_data = pdata;
-        dev->dev.parent = parent;
-        ret = amba_device_add(dev, &iomem_resource);
-        if (ret) {
-                amba_device_put(dev);
-                return ERR_PTR(ret);
-        }
-        return dev;
-}
 static struct platform_device *
 dbx500_add_gpio(struct device *parent, int id, resource_size_t addr, int irq,
                struct nmk_gpio_platform_data *pdata)
diff --git a/arch/arm/mach-ux500/devices-common.h b/arch/arm/mach-ux500/devices-common.h
index 39c74ec82add..7cbccfd9e158 100644
--- a/arch/arm/mach-ux500/devices-common.h
+++ b/arch/arm/mach-ux500/devices-common.h
@@ -11,13 +11,9 @@
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
 #include <linux/sys_soc.h>
+#include <linux/amba/bus.h>
 #include <plat/i2c.h>
-extern struct amba_device *
-dbx500_add_amba_device(struct device *parent, const char *name,
-                       resource_size_t base, int irq, void *pdata,
-                       unsigned int periphid);
 struct spi_master_cntlr;
 static inline struct amba_device *
@@ -25,8 +21,8 @@ dbx500_add_msp_spi(struct device *parent, const char *name,
                   resource_size_t base, int irq,
                   struct spi_master_cntlr *pdata)
 {
-        return dbx500_add_amba_device(parent, name, base, irq,
+        return amba_ahb_device_add(parent, name, base, SZ_4K, irq, 0,
-                                      pdata, 0);
+                                   pdata, 0);
 }
 static inline struct amba_device *
@@ -34,8 +30,8 @@ dbx500_add_spi(struct device *parent, const char *name, resource_size_t base,
               int irq, struct spi_master_cntlr *pdata,
               u32 periphid)
 {
-        return dbx500_add_amba_device(parent, name, base, irq,
+        return amba_ahb_device_add(parent, name, base, SZ_4K, irq, 0,
-                                      pdata, periphid);
+                                   pdata, periphid);
 }
 struct mmci_platform_data;
@@ -44,8 +40,8 @@ static inline struct amba_device *
 dbx500_add_sdi(struct device *parent, const char *name, resource_size_t base,
               int irq, struct mmci_platform_data *pdata, u32 periphid)
 {
-        return dbx500_add_amba_device(parent, name, base, irq,
+        return amba_ahb_device_add(parent, name, base, SZ_4K, irq, 0,
-                                      pdata, periphid);
+                                   pdata, periphid);
 }
 struct amba_pl011_data;
@@ -54,7 +50,7 @@ static inline struct amba_device *
 dbx500_add_uart(struct device *parent, const char *name, resource_size_t base,
                int irq, struct amba_pl011_data *pdata)
 {
-        return dbx500_add_amba_device(parent, name, base, irq, pdata, 0);
+        return amba_ahb_device_add(parent, name, base, SZ_4K, irq, 0, pdata, 0);
 }
 struct nmk_i2c_controller;
@@ -85,7 +81,8 @@ dbx500_add_i2c(struct device *parent, int id, resource_size_t base, int irq,
 static inline struct amba_device *
 dbx500_add_rtc(struct device *parent, resource_size_t base, int irq)
 {
-        return dbx500_add_amba_device(parent, "rtc-pl031", base, irq, NULL, 0);
+        return amba_apb_device_add(parent, "rtc-pl031", base, SZ_4K, irq,
+                                0, NULL, 0);
 }
 struct nmk_gpio_platform_data;
@@ -93,4 +90,16 @@ struct nmk_gpio_platform_data;
 void dbx500_add_gpios(struct device *parent, resource_size_t *base, int num,
                      int irq, struct nmk_gpio_platform_data *pdata);
+static inline void
+dbx500_add_pinctrl(struct device *parent, const char *name)
+{
+        struct platform_device_info pdevinfo = {
+                .parent = parent,
+                .name = name,
+                .id = -1,
+        };
+        platform_device_register_full(&pdevinfo);
+}
 #endif
diff --git a/arch/arm/mach-ux500/devices-db5500.h b/arch/arm/mach-ux500/devices-db5500.h
deleted file mode 100644
index e70955502c35..000000000000
--- a/arch/arm/mach-ux500/devices-db5500.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2010
- *
- * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
- * License terms: GNU General Public License (GPL), version 2.
- */
-#ifndef __DEVICES_DB5500_H
-#define __DEVICES_DB5500_H
-#include "devices-common.h"
-#define db5500_add_i2c1(parent, pdata) \
-        dbx500_add_i2c(parent, 1, U5500_I2C1_BASE, IRQ_DB5500_I2C1, pdata)
-#define db5500_add_i2c2(parent, pdata) \
-        dbx500_add_i2c(parent, 2, U5500_I2C2_BASE, IRQ_DB5500_I2C2, pdata)
-#define db5500_add_i2c3(parent, pdata) \
-        dbx500_add_i2c(parent, 3, U5500_I2C3_BASE, IRQ_DB5500_I2C3, pdata)
-#define db5500_add_msp0_spi(parent, pdata) \
-        dbx500_add_msp_spi(parent, "msp0", U5500_MSP0_BASE, \
-                           IRQ_DB5500_MSP0, pdata)
-#define db5500_add_msp1_spi(parent, pdata) \
-        dbx500_add_msp_spi(parent, "msp1", U5500_MSP1_BASE, \
-                           IRQ_DB5500_MSP1, pdata)
-#define db5500_add_msp2_spi(parent, pdata) \
-        dbx500_add_msp_spi(parent, "msp2", U5500_MSP2_BASE, \
-                           IRQ_DB5500_MSP2, pdata)
-#define db5500_add_msp0_spi(parent, pdata) \
-        dbx500_add_msp_spi(parent, "msp0", U5500_MSP0_BASE, \
-                          IRQ_DB5500_MSP0, pdata)
-#define db5500_add_msp1_spi(parent, pdata) \
-        dbx500_add_msp_spi(parent, "msp1", U5500_MSP1_BASE, \
-                          IRQ_DB5500_MSP1, pdata)
-#define db5500_add_msp2_spi(parent, pdata) \
-        dbx500_add_msp_spi(parent, "msp2", U5500_MSP2_BASE, \
-                          IRQ_DB5500_MSP2, pdata)
-#define db5500_add_rtc(parent) \
-        dbx500_add_rtc(parent, U5500_RTC_BASE, IRQ_DB5500_RTC);
-#define db5500_add_usb(parent, rx_cfg, tx_cfg) \
-        ux500_add_usb(parent, U5500_USBOTG_BASE, \
-                      IRQ_DB5500_USBOTG, rx_cfg, tx_cfg)
-#define db5500_add_sdi0(parent, pdata) \
-        dbx500_add_sdi(parent, "sdi0", U5500_SDI0_BASE, \
-                       IRQ_DB5500_SDMMC0, pdata,        \
-                       0x10480180)
-#define db5500_add_sdi1(parent, pdata) \
-        dbx500_add_sdi(parent, "sdi1", U5500_SDI1_BASE, \
-                       IRQ_DB5500_SDMMC1, pdata,        \
-                       0x10480180)
-#define db5500_add_sdi2(parent, pdata) \
-        dbx500_add_sdi(parent, "sdi2", U5500_SDI2_BASE, \
-                       IRQ_DB5500_SDMMC2, pdata         \
-                       0x10480180)
-#define db5500_add_sdi3(parent, pdata) \
-        dbx500_add_sdi(parent, "sdi3", U5500_SDI3_BASE, \
-                       IRQ_DB5500_SDMMC3, pdata         \
-                       0x10480180)
-#define db5500_add_sdi4(parent, pdata) \
-        dbx500_add_sdi(parent, "sdi4", U5500_SDI4_BASE, \
-                       IRQ_DB5500_SDMMC4, pdata         \
-                       0x10480180)
-/* This one has a bad peripheral ID in the U5500 silicon */
-#define db5500_add_spi0(parent, pdata) \
-        dbx500_add_spi(parent, "spi0", U5500_SPI0_BASE, \
-                       IRQ_DB5500_SPI0, pdata,          \
-                       0x10080023)
-#define db5500_add_spi1(parent, pdata) \
-        dbx500_add_spi(parent, "spi1", U5500_SPI1_BASE, \
-                       IRQ_DB5500_SPI1, pdata,          \
-                       0x10080023)
-#define db5500_add_spi2(parent, pdata) \
-        dbx500_add_spi(parent, "spi2", U5500_SPI2_BASE, \
-                       IRQ_DB5500_SPI2, pdata           \
-                       0x10080023)
-#define db5500_add_spi3(parent, pdata) \
-        dbx500_add_spi(parent, "spi3", U5500_SPI3_BASE, \
-                       IRQ_DB5500_SPI3, pdata           \
-                       0x10080023)
-#define db5500_add_uart0(parent, plat) \
-        dbx500_add_uart(parent, "uart0", U5500_UART0_BASE, \
-                        IRQ_DB5500_UART0, plat)
-#define db5500_add_uart1(parent, plat) \
-        dbx500_add_uart(parent, "uart1", U5500_UART1_BASE, \
-                        IRQ_DB5500_UART1, plat)
-#define db5500_add_uart2(parent, plat) \
-        dbx500_add_uart(parent, "uart2", U5500_UART2_BASE, \
-                        IRQ_DB5500_UART2, plat)
-#define db5500_add_uart3(parent, plat) \
-        dbx500_add_uart(parent, "uart3", U5500_UART3_BASE, \
-                        IRQ_DB5500_UART3, plat)
-#endif
diff --git a/arch/arm/mach-ux500/devices-db8500.h b/arch/arm/mach-ux500/devices-db8500.h
index 9fd93e9da529..0b9677a95bbc 100644
--- a/arch/arm/mach-ux500/devices-db8500.h
+++ b/arch/arm/mach-ux500/devices-db8500.h
@@ -31,10 +31,9 @@ static inline struct amba_device *
 db8500_add_ssp(struct device *parent, const char *name, resource_size_t base,
               int irq, struct pl022_ssp_controller *pdata)
 {
-        return dbx500_add_amba_device(parent, name, base, irq, pdata, 0);
+        return amba_ahb_device_add(parent, name, base, SZ_4K, irq, 0, pdata, 0);
 }
 #define db8500_add_i2c0(parent, pdata) \
        dbx500_add_i2c(parent, 0, U8500_I2C0_BASE, IRQ_DB8500_I2C0, pdata)
 #define db8500_add_i2c1(parent, pdata) \
@@ -46,15 +45,6 @@ db8500_add_ssp(struct device *parent, const char *name, resource_size_t base,
 #define db8500_add_i2c4(parent, pdata) \
        dbx500_add_i2c(parent, 4, U8500_I2C4_BASE, IRQ_DB8500_I2C4, pdata)
-#define db8500_add_msp0_i2s(parent, pdata) \
-        dbx500_add_msp_i2s(parent, 0, U8500_MSP0_BASE, IRQ_DB8500_MSP0, pdata)
-#define db8500_add_msp1_i2s(parent, pdata) \
-        dbx500_add_msp_i2s(parent, 1, U8500_MSP1_BASE, IRQ_DB8500_MSP1, pdata)
-#define db8500_add_msp2_i2s(parent, pdata) \
-        dbx500_add_msp_i2s(parent, 2, U8500_MSP2_BASE, IRQ_DB8500_MSP2, pdata)
-#define db8500_add_msp3_i2s(parent, pdata) \
-        dbx500_add_msp_i2s(parent, 3, U8500_MSP3_BASE, IRQ_DB8500_MSP1, pdata)
 #define db8500_add_msp0_spi(parent, pdata) \
        dbx500_add_msp_spi(parent, "msp0", U8500_MSP0_BASE, \
                           IRQ_DB8500_MSP0, pdata)
diff --git a/arch/arm/mach-ux500/dma-db5500.c b/arch/arm/mach-ux500/dma-db5500.c
deleted file mode 100644
index 41e9470fa0e6..000000000000
--- a/arch/arm/mach-ux500/dma-db5500.c
+++ /dev/null
@@ -1,137 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2010
- *
- * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
- * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
- * Author: Rabin Vincent <rabinv.vincent@stericsson.com> for ST-Ericsson
- *
- * License terms: GNU General Public License (GPL), version 2
- */
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <plat/ste_dma40.h>
-#include <mach/setup.h>
-#include <mach/hardware.h>
-#include "ste-dma40-db5500.h"
-static struct resource dma40_resources[] = {
-        [0] = {
-                .start = U5500_DMA_BASE,
-                .end   = U5500_DMA_BASE + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-                .name  = "base",
-        },
-        [1] = {
-                .start = U5500_DMA_LCPA_BASE,
-                .end   = U5500_DMA_LCPA_BASE + 2 * SZ_1K - 1,
-                .flags = IORESOURCE_MEM,
-                .name  = "lcpa",
-        },
-        [2] = {
-                .start = IRQ_DB5500_DMA,
-                .end   = IRQ_DB5500_DMA,
-                .flags = IORESOURCE_IRQ
-        }
-};
-/* Default configuration for physical memcpy */
-static struct stedma40_chan_cfg dma40_memcpy_conf_phy = {
-        .mode = STEDMA40_MODE_PHYSICAL,
-        .dir = STEDMA40_MEM_TO_MEM,
-        .src_info.data_width = STEDMA40_BYTE_WIDTH,
-        .src_info.psize = STEDMA40_PSIZE_PHY_1,
-        .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
-        .dst_info.data_width = STEDMA40_BYTE_WIDTH,
-        .dst_info.psize = STEDMA40_PSIZE_PHY_1,
-        .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
-};
-/* Default configuration for logical memcpy */
-static struct stedma40_chan_cfg dma40_memcpy_conf_log = {
-        .dir = STEDMA40_MEM_TO_MEM,
-        .src_info.data_width = STEDMA40_BYTE_WIDTH,
-        .src_info.psize = STEDMA40_PSIZE_LOG_1,
-        .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
-        .dst_info.data_width = STEDMA40_BYTE_WIDTH,
-        .dst_info.psize = STEDMA40_PSIZE_LOG_1,
-        .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
-};
-/*
- * Mapping between soruce event lines and physical device address This was
- * created assuming that the event line is tied to a device and therefore the
- * address is constant, however this is not true for at least USB, and the
- * values are just placeholders for USB.  This table is preserved and used for
- * now.
- */
-static const dma_addr_t dma40_rx_map[DB5500_DMA_NR_DEV] = {
-        [DB5500_DMA_DEV24_SDMMC0_RX] = -1,
-        [DB5500_DMA_DEV38_USB_OTG_IEP_8] = -1,
-        [DB5500_DMA_DEV23_USB_OTG_IEP_7_15] = -1,
-        [DB5500_DMA_DEV22_USB_OTG_IEP_6_14] = -1,
-        [DB5500_DMA_DEV21_USB_OTG_IEP_5_13] = -1,
-        [DB5500_DMA_DEV20_USB_OTG_IEP_4_12] = -1,
-        [DB5500_DMA_DEV6_USB_OTG_IEP_3_11] = -1,
-        [DB5500_DMA_DEV5_USB_OTG_IEP_2_10] = -1,
-        [DB5500_DMA_DEV4_USB_OTG_IEP_1_9] = -1,
-};
-/* Mapping between destination event lines and physical device address */
-static const dma_addr_t dma40_tx_map[DB5500_DMA_NR_DEV] = {
-        [DB5500_DMA_DEV24_SDMMC0_TX] = -1,
-        [DB5500_DMA_DEV38_USB_OTG_OEP_8] = -1,
-        [DB5500_DMA_DEV23_USB_OTG_OEP_7_15] = -1,
-        [DB5500_DMA_DEV22_USB_OTG_OEP_6_14] = -1,
-        [DB5500_DMA_DEV21_USB_OTG_OEP_5_13] = -1,
-        [DB5500_DMA_DEV20_USB_OTG_OEP_4_12] = -1,
-        [DB5500_DMA_DEV6_USB_OTG_OEP_3_11] = -1,
-        [DB5500_DMA_DEV5_USB_OTG_OEP_2_10] = -1,
-        [DB5500_DMA_DEV4_USB_OTG_OEP_1_9] = -1,
-};
-static int dma40_memcpy_event[] = {
-        DB5500_DMA_MEMCPY_TX_1,
-        DB5500_DMA_MEMCPY_TX_2,
-        DB5500_DMA_MEMCPY_TX_3,
-        DB5500_DMA_MEMCPY_TX_4,
-        DB5500_DMA_MEMCPY_TX_5,
-};
-static struct stedma40_platform_data dma40_plat_data = {
-        .dev_len                = ARRAY_SIZE(dma40_rx_map),
-        .dev_rx                 = dma40_rx_map,
-        .dev_tx                 = dma40_tx_map,
-        .memcpy                 = dma40_memcpy_event,
-        .memcpy_len             = ARRAY_SIZE(dma40_memcpy_event),
-        .memcpy_conf_phy        = &dma40_memcpy_conf_phy,
-        .memcpy_conf_log        = &dma40_memcpy_conf_log,
-        .disabled_channels      = {-1},
-};
-static struct platform_device dma40_device = {
-        .dev = {
-                .platform_data = &dma40_plat_data,
-        },
-        .name           = "dma40",
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(dma40_resources),
-        .resource       = dma40_resources
-};
-void __init db5500_dma_init(struct device *parent)
-{
-        int ret;
-        dma40_device.dev.parent = parent;
-        ret = platform_device_register(&dma40_device);
-        if (ret)
-                dev_err(&dma40_device.dev, "unable to register device: %d\n", ret);
-}
diff --git a/arch/arm/mach-ux500/id.c b/arch/arm/mach-ux500/id.c
index 15a0f63b2e2b..d1579920139f 100644
--- a/arch/arm/mach-ux500/id.c
+++ b/arch/arm/mach-ux500/id.c
@@ -23,7 +23,7 @@ static unsigned int ux500_read_asicid(phys_addr_t addr)
 {
        phys_addr_t base = addr & ~0xfff;
        struct map_desc desc = {
-                .virtual        = IO_ADDRESS(base),
+                .virtual        = UX500_VIRT_ROM,
                .pfn            = __phys_to_pfn(base),
                .length         = SZ_16K,
                .type           = MT_DEVICE,
@@ -35,7 +35,7 @@ static unsigned int ux500_read_asicid(phys_addr_t addr)
        local_flush_tlb_all();
        flush_cache_all();
-        return readl(__io_address(addr));
+        return readl(IOMEM(UX500_VIRT_ROM + (addr & 0xfff)));
 }
 static void ux500_print_soc_info(unsigned int asicid)
@@ -67,6 +67,7 @@ static unsigned int partnumber(unsigned int asicid)
 * DB8500v2     0x412fc091      0x9001DBF4              0x008500B0
 * DB8520v2.2   0x412fc091      0x9001DBF4              0x008500B2
 * DB5500v1     0x412fc091      0x9001FFF4              0x005500A0
+ * DB9540       0x413fc090      0xFFFFDBF4              0x009540xx
 */
 void __init ux500_map_io(void)
@@ -91,6 +92,10 @@ void __init ux500_map_io(void)
                /* DB5500v1 */
                addr = 0x9001FFF4;
                break;
+        case 0x413fc090: /* DB9540 */
+                addr = 0xFFFFDBF4;
+                break;
        }
        if (addr)
diff --git a/arch/arm/mach-ux500/include/mach/db5500-regs.h b/arch/arm/mach-ux500/include/mach/db5500-regs.h
deleted file mode 100644
index 8e714bcb099f..000000000000
--- a/arch/arm/mach-ux500/include/mach/db5500-regs.h
+++ /dev/null
@@ -1,143 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2010
- *
- * License terms: GNU General Public License (GPL) version 2
- */
-#ifndef __MACH_DB5500_REGS_H
-#define __MACH_DB5500_REGS_H
-#define U5500_PER1_BASE         0xA0020000
-#define U5500_PER2_BASE         0xA0010000
-#define U5500_PER3_BASE         0x80140000
-#define U5500_PER4_BASE         0x80150000
-#define U5500_PER5_BASE         0x80100000
-#define U5500_PER6_BASE         0x80120000
-#define U5500_GIC_DIST_BASE     0xA0411000
-#define U5500_GIC_CPU_BASE      0xA0410100
-#define U5500_DMA_BASE          0x90030000
-#define U5500_STM_BASE          0x90020000
-#define U5500_STM_REG_BASE      (U5500_STM_BASE + 0xF000)
-#define U5500_MCDE_BASE         0xA0400000
-#define U5500_MODEM_BASE        0xB0000000
-#define U5500_L2CC_BASE         0xA0412000
-#define U5500_SCU_BASE          0xA0410000
-#define U5500_DSI1_BASE         0xA0401000
-#define U5500_DSI2_BASE         0xA0402000
-#define U5500_SIA_BASE          0xA0100000
-#define U5500_SVA_BASE          0x80200000
-#define U5500_HSEM_BASE         0xA0000000
-#define U5500_NAND0_BASE        0x60000000
-#define U5500_NAND1_BASE        0x70000000
-#define U5500_TWD_BASE          0xa0410600
-#define U5500_ICN_BASE          0xA0040000
-#define U5500_B2R2_BASE         0xa0200000
-#define U5500_BOOT_ROM_BASE     0x90000000
-#define U5500_FSMC_BASE         (U5500_PER1_BASE + 0x0000)
-#define U5500_SDI0_BASE         (U5500_PER1_BASE + 0x1000)
-#define U5500_SDI2_BASE         (U5500_PER1_BASE + 0x2000)
-#define U5500_UART0_BASE        (U5500_PER1_BASE + 0x3000)
-#define U5500_I2C1_BASE         (U5500_PER1_BASE + 0x4000)
-#define U5500_MSP0_BASE         (U5500_PER1_BASE + 0x5000)
-#define U5500_GPIO0_BASE        (U5500_PER1_BASE + 0xE000)
-#define U5500_CLKRST1_BASE      (U5500_PER1_BASE + 0xF000)
-#define U5500_USBOTG_BASE       (U5500_PER2_BASE + 0x0000)
-#define U5500_GPIO1_BASE        (U5500_PER2_BASE + 0xE000)
-#define U5500_CLKRST2_BASE      (U5500_PER2_BASE + 0xF000)
-#define U5500_KEYPAD_BASE       (U5500_PER3_BASE + 0x0000)
-#define U5500_PWM_BASE          (U5500_PER3_BASE + 0x1000)
-#define U5500_GPIO3_BASE        (U5500_PER3_BASE + 0xE000)
-#define U5500_CLKRST3_BASE      (U5500_PER3_BASE + 0xF000)
-#define U5500_BACKUPRAM0_BASE   (U5500_PER4_BASE + 0x0000)
-#define U5500_BACKUPRAM1_BASE   (U5500_PER4_BASE + 0x1000)
-#define U5500_RTT0_BASE         (U5500_PER4_BASE + 0x2000)
-#define U5500_RTT1_BASE         (U5500_PER4_BASE + 0x3000)
-#define U5500_RTC_BASE          (U5500_PER4_BASE + 0x4000)
-#define U5500_SCR_BASE          (U5500_PER4_BASE + 0x5000)
-#define U5500_DMC_BASE          (U5500_PER4_BASE + 0x6000)
-#define U5500_PRCMU_BASE        (U5500_PER4_BASE + 0x7000)
-#define U5500_PRCMU_TIMER_3_BASE (U5500_PER4_BASE + 0x07338)
-#define U5500_PRCMU_TIMER_4_BASE (U5500_PER4_BASE + 0x07450)
-#define U5500_MSP1_BASE         (U5500_PER4_BASE + 0x9000)
-#define U5500_GPIO2_BASE        (U5500_PER4_BASE + 0xA000)
-#define U5500_MTIMER_BASE       (U5500_PER4_BASE + 0xC000)
-#define U5500_CDETECT_BASE      (U5500_PER4_BASE + 0xF000)
-#define U5500_PRCMU_TCDM_BASE   (U5500_PER4_BASE + 0x18000)
-#define U5500_PRCMU_TCPM_BASE   (U5500_PER4_BASE + 0x10000)
-#define U5500_TPIU_BASE         (U5500_PER4_BASE + 0x50000)
-#define U5500_SPI0_BASE         (U5500_PER5_BASE + 0x0000)
-#define U5500_SPI1_BASE         (U5500_PER5_BASE + 0x1000)
-#define U5500_SPI2_BASE         (U5500_PER5_BASE + 0x2000)
-#define U5500_SPI3_BASE         (U5500_PER5_BASE + 0x3000)
-#define U5500_UART1_BASE        (U5500_PER5_BASE + 0x4000)
-#define U5500_UART2_BASE        (U5500_PER5_BASE + 0x5000)
-#define U5500_UART3_BASE        (U5500_PER5_BASE + 0x6000)
-#define U5500_SDI1_BASE         (U5500_PER5_BASE + 0x7000)
-#define U5500_SDI3_BASE         (U5500_PER5_BASE + 0x8000)
-#define U5500_SDI4_BASE         (U5500_PER5_BASE + 0x9000)
-#define U5500_I2C2_BASE         (U5500_PER5_BASE + 0xA000)
-#define U5500_I2C3_BASE         (U5500_PER5_BASE + 0xB000)
-#define U5500_MSP2_BASE         (U5500_PER5_BASE + 0xC000)
-#define U5500_IRDA_BASE         (U5500_PER5_BASE + 0xD000)
-#define U5500_IRRC_BASE         (U5500_PER5_BASE + 0x10000)
-#define U5500_GPIO4_BASE        (U5500_PER5_BASE + 0x1E000)
-#define U5500_CLKRST5_BASE      (U5500_PER5_BASE + 0x1F000)
-#define U5500_RNG_BASE          (U5500_PER6_BASE + 0x0000)
-#define U5500_HASH0_BASE        (U5500_PER6_BASE + 0x1000)
-#define U5500_HASH1_BASE        (U5500_PER6_BASE + 0x2000)
-#define U5500_PKA_BASE          (U5500_PER6_BASE + 0x4000)
-#define U5500_PKAM_BASE         (U5500_PER6_BASE + 0x5100)
-#define U5500_MTU0_BASE         (U5500_PER6_BASE + 0x6000)
-#define U5500_MTU1_BASE         (U5500_PER6_BASE + 0x7000)
-#define U5500_CR_BASE           (U5500_PER6_BASE + 0x8000)
-#define U5500_CRYP0_BASE        (U5500_PER6_BASE + 0xA000)
-#define U5500_CRYP1_BASE        (U5500_PER6_BASE + 0xB000)
-#define U5500_CLKRST6_BASE      (U5500_PER6_BASE + 0xF000)
-#define U5500_GPIOBANK0_BASE    U5500_GPIO0_BASE
-#define U5500_GPIOBANK1_BASE    (U5500_GPIO0_BASE + 0x80)
-#define U5500_GPIOBANK2_BASE    U5500_GPIO1_BASE
-#define U5500_GPIOBANK3_BASE    U5500_GPIO2_BASE
-#define U5500_GPIOBANK4_BASE    U5500_GPIO3_BASE
-#define U5500_GPIOBANK5_BASE    U5500_GPIO4_BASE
-#define U5500_GPIOBANK6_BASE    (U5500_GPIO4_BASE + 0x80)
-#define U5500_GPIOBANK7_BASE    (U5500_GPIO4_BASE + 0x100)
-#define U5500_MBOX_BASE         (U5500_MODEM_BASE + 0xFFD1000)
-#define U5500_MBOX0_PEER_START  (U5500_MBOX_BASE + 0x40)
-#define U5500_MBOX0_PEER_END    (U5500_MBOX_BASE + 0x5F)
-#define U5500_MBOX0_LOCAL_START (U5500_MBOX_BASE + 0x60)
-#define U5500_MBOX0_LOCAL_END   (U5500_MBOX_BASE + 0x7F)
-#define U5500_MBOX1_PEER_START  (U5500_MBOX_BASE + 0x80)
-#define U5500_MBOX1_PEER_END    (U5500_MBOX_BASE + 0x9F)
-#define U5500_MBOX1_LOCAL_START (U5500_MBOX_BASE + 0xA0)
-#define U5500_MBOX1_LOCAL_END   (U5500_MBOX_BASE + 0xBF)
-#define U5500_MBOX2_PEER_START  (U5500_MBOX_BASE + 0x00)
-#define U5500_MBOX2_PEER_END    (U5500_MBOX_BASE + 0x1F)
-#define U5500_MBOX2_LOCAL_START (U5500_MBOX_BASE + 0x20)
-#define U5500_MBOX2_LOCAL_END   (U5500_MBOX_BASE + 0x3F)
-#define U5500_ACCCON_BASE_SEC   (0xBFFF0000)
-#define U5500_ACCCON_BASE               (0xBFFF1000)
-#define U5500_ACCCON_CPUVEC_RESET_ADDR_OFFSET (0x00000020)
-#define U5500_ACCCON_ACC_CPU_CTRL_OFFSET (0x000000BC)
-#define U5500_INTCON_MBOX1_INT_RESET_ADDR       (0xBFFD31A4)
-#define U5500_ESRAM_BASE                0x40000000
-#define U5500_ESRAM_DMA_LCPA_OFFSET     0x10000
-#define U5500_DMA_LCPA_BASE    (U5500_ESRAM_BASE + U5500_ESRAM_DMA_LCPA_OFFSET)
-#define U5500_MCDE_SIZE         0x1000
-#define U5500_DSI_LINK_SIZE     0x1000
-#define U5500_DSI_LINK_COUNT    0x2
-#define U5500_DSI_LINK1_BASE    (U5500_MCDE_BASE + U5500_MCDE_SIZE)
-#define U5500_DSI_LINK2_BASE    (U5500_DSI_LINK1_BASE + U5500_DSI_LINK_SIZE)
-#endif
diff --git a/arch/arm/mach-ux500/include/mach/db8500-regs.h b/arch/arm/mach-ux500/include/mach/db8500-regs.h
index 9ec20b96d8f2..1530d493879d 100644
--- a/arch/arm/mach-ux500/include/mach/db8500-regs.h
+++ b/arch/arm/mach-ux500/include/mach/db8500-regs.h
@@ -41,6 +41,10 @@
 /* ASIC ID is at 0xbf4 offset within this region */
 #define U8500_ASIC_ID_BASE      0x9001D000
+#define U9540_BOOT_ROM_BASE     0xFFFE0000
+/* ASIC ID is at 0xbf4 offset within this region */
+#define U9540_ASIC_ID_BASE      0xFFFFD000
 #define U8500_PER6_BASE         0xa03c0000
 #define U8500_PER7_BASE         0xa03d0000
 #define U8500_PER5_BASE         0xa03e0000
@@ -96,7 +100,9 @@
 #define U8500_SCR_BASE          (U8500_PER4_BASE + 0x05000)
 #define U8500_DMC_BASE          (U8500_PER4_BASE + 0x06000)
 #define U8500_PRCMU_BASE        (U8500_PER4_BASE + 0x07000)
+#define U9540_DMC1_BASE         (U8500_PER4_BASE + 0x0A000)
 #define U8500_PRCMU_TCDM_BASE   (U8500_PER4_BASE + 0x68000)
+#define U9540_PRCMU_TCDM_BASE   (U8500_PER4_BASE + 0x6A000)
 #define U8500_PRCMU_TCPM_BASE   (U8500_PER4_BASE + 0x60000)
 #define U8500_PRCMU_TIMER_3_BASE (U8500_PER4_BASE + 0x07338)
 #define U8500_PRCMU_TIMER_4_BASE (U8500_PER4_BASE + 0x07450)
diff --git a/arch/arm/mach-ux500/include/mach/debug-macro.S b/arch/arm/mach-ux500/include/mach/debug-macro.S
index 8d74d927d4e2..67035223334a 100644
--- a/arch/arm/mach-ux500/include/mach/debug-macro.S
+++ b/arch/arm/mach-ux500/include/mach/debug-macro.S
@@ -20,10 +20,6 @@
 * built, so that there's some hint during the build that something is wrong.
 */
-#ifdef CONFIG_UX500_SOC_DB5500
-#define __UX500_UART(n) U5500_UART##n##_BASE
-#endif
 #ifdef CONFIG_UX500_SOC_DB8500
 #define __UX500_UART(n) U8500_UART##n##_BASE
 #endif
diff --git a/arch/arm/mach-ux500/include/mach/devices.h b/arch/arm/mach-ux500/include/mach/devices.h
index 5f6cb71fc62d..9b5eb69a0154 100644
--- a/arch/arm/mach-ux500/include/mach/devices.h
+++ b/arch/arm/mach-ux500/include/mach/devices.h
@@ -10,7 +10,6 @@
 struct platform_device;
 struct amba_device;
-extern struct platform_device u5500_gpio_devs[];
 extern struct platform_device u8500_gpio_devs[];
 extern struct amba_device ux500_pl031_device;
diff --git a/arch/arm/mach-ux500/include/mach/hardware.h b/arch/arm/mach-ux500/include/mach/hardware.h
index f84698936d36..808c1d6601c5 100644
--- a/arch/arm/mach-ux500/include/mach/hardware.h
+++ b/arch/arm/mach-ux500/include/mach/hardware.h
@@ -17,6 +17,8 @@
 */
 #define U8500_IO_VIRTUAL        0xf0000000
 #define U8500_IO_PHYSICAL       0xa0000000
+/* This is where we map in the ROM to check ASIC IDs */
+#define UX500_VIRT_ROM          0xf0000000
 /* This macro is used in assembly, so no cast */
 #define IO_ADDRESS(x)           \
@@ -24,11 +26,11 @@
 /* typesafe io address */
 #define __io_address(n)         IOMEM(IO_ADDRESS(n))
 /* Used by some plat-nomadik code */
 #define io_p2v(n)               __io_address(n)
 #include <mach/db8500-regs.h>
-#include <mach/db5500-regs.h>
 #define MSP_TX_RX_REG_OFFSET    0
diff --git a/arch/arm/mach-ux500/include/mach/id.h b/arch/arm/mach-ux500/include/mach/id.h
index 833d6a6edc9b..c6e2db9e9e51 100644
--- a/arch/arm/mach-ux500/include/mach/id.h
+++ b/arch/arm/mach-ux500/include/mach/id.h
@@ -41,6 +41,16 @@ static inline bool __attribute_const__ cpu_is_u8500(void)
        return dbx500_partnumber() == 0x8500;
 }
+static inline bool __attribute_const__ cpu_is_u9540(void)
+{
+        return dbx500_partnumber() == 0x9540;
+}
+static inline bool cpu_is_u8500_family(void)
+{
+        return cpu_is_u8500() || cpu_is_u9540();
+}
 static inline bool __attribute_const__ cpu_is_u5500(void)
 {
        return dbx500_partnumber() == 0x5500;
@@ -111,7 +121,12 @@ static inline bool cpu_is_u8500v21(void)
 static inline bool cpu_is_u8500v20_or_later(void)
 {
-        return cpu_is_u8500() && !cpu_is_u8500v10() && !cpu_is_u8500v11();
+        /*
+         * U9540 has so much in common with U8500 that is is considered a
+         * U8500 variant.
+         */
+        return cpu_is_u9540() ||
+                (cpu_is_u8500() && !cpu_is_u8500v10() && !cpu_is_u8500v11());
 }
 static inline bool ux500_is_svp(void)
diff --git a/arch/arm/mach-ux500/include/mach/irqs-board-u5500.h b/arch/arm/mach-ux500/include/mach/irqs-board-u5500.h
deleted file mode 100644
index 29d972c7717b..000000000000
--- a/arch/arm/mach-ux500/include/mach/irqs-board-u5500.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2010
- *
- * License terms: GNU General Public License (GPL) version 2
- */
-#ifndef __MACH_IRQS_BOARD_U5500_H
-#define __MACH_IRQS_BOARD_U5500_H
-#define AB5500_NR_IRQS          5
-#define IRQ_AB5500_BASE         IRQ_BOARD_START
-#define IRQ_AB5500_END          (IRQ_AB5500_BASE + AB5500_NR_IRQS)
-#define U5500_IRQ_END           IRQ_AB5500_END
-#if IRQ_BOARD_END < U5500_IRQ_END
-#undef IRQ_BOARD_END
-#define IRQ_BOARD_END           U5500_IRQ_END
-#endif
-#endif
diff --git a/arch/arm/mach-ux500/include/mach/irqs-db5500.h b/arch/arm/mach-ux500/include/mach/irqs-db5500.h
deleted file mode 100644
index 77239776a6f2..000000000000
--- a/arch/arm/mach-ux500/include/mach/irqs-db5500.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2010
- *
- * Author: Rabin Vincent <rabin.vincent@stericsson.com>
- * License terms: GNU General Public License (GPL) version 2
- */
-#ifndef __MACH_IRQS_DB5500_H
-#define __MACH_IRQS_DB5500_H
-#define IRQ_DB5500_MTU0                 (IRQ_SHPI_START + 4)
-#define IRQ_DB5500_SPI2                 (IRQ_SHPI_START + 6)
-#define IRQ_DB5500_PMU0                 (IRQ_SHPI_START + 7)
-#define IRQ_DB5500_SPI0                 (IRQ_SHPI_START + 8)
-#define IRQ_DB5500_RTT                  (IRQ_SHPI_START + 9)
-#define IRQ_DB5500_PKA                  (IRQ_SHPI_START + 10)
-#define IRQ_DB5500_UART0                (IRQ_SHPI_START + 11)
-#define IRQ_DB5500_I2C3                 (IRQ_SHPI_START + 12)
-#define IRQ_DB5500_L2CC                 (IRQ_SHPI_START + 13)
-#define IRQ_DB5500_MSP0                 (IRQ_SHPI_START + 14)
-#define IRQ_DB5500_CRYP1                (IRQ_SHPI_START + 15)
-#define IRQ_DB5500_PMU1                 (IRQ_SHPI_START + 16)
-#define IRQ_DB5500_MTU1                 (IRQ_SHPI_START + 17)
-#define IRQ_DB5500_RTC                  (IRQ_SHPI_START + 18)
-#define IRQ_DB5500_UART1                (IRQ_SHPI_START + 19)
-#define IRQ_DB5500_USB_WAKEUP           (IRQ_SHPI_START + 20)
-#define IRQ_DB5500_I2C0                 (IRQ_SHPI_START + 21)
-#define IRQ_DB5500_I2C1                 (IRQ_SHPI_START + 22)
-#define IRQ_DB5500_USBOTG               (IRQ_SHPI_START + 23)
-#define IRQ_DB5500_DMA_SECURE           (IRQ_SHPI_START + 24)
-#define IRQ_DB5500_DMA                  (IRQ_SHPI_START + 25)
-#define IRQ_DB5500_UART2                (IRQ_SHPI_START + 26)
-#define IRQ_DB5500_ICN_PMU1             (IRQ_SHPI_START + 27)
-#define IRQ_DB5500_ICN_PMU2             (IRQ_SHPI_START + 28)
-#define IRQ_DB5500_UART3                (IRQ_SHPI_START + 29)
-#define IRQ_DB5500_SPI3                 (IRQ_SHPI_START + 30)
-#define IRQ_DB5500_SDMMC4               (IRQ_SHPI_START + 31)
-#define IRQ_DB5500_IRRC                 (IRQ_SHPI_START + 33)
-#define IRQ_DB5500_IRDA_FT              (IRQ_SHPI_START + 34)
-#define IRQ_DB5500_IRDA_SD              (IRQ_SHPI_START + 35)
-#define IRQ_DB5500_IRDA_FI              (IRQ_SHPI_START + 36)
-#define IRQ_DB5500_IRDA_FD              (IRQ_SHPI_START + 37)
-#define IRQ_DB5500_FSMC_CODEREADY       (IRQ_SHPI_START + 38)
-#define IRQ_DB5500_FSMC_NANDWAIT        (IRQ_SHPI_START + 39)
-#define IRQ_DB5500_AB5500               (IRQ_SHPI_START + 40)
-#define IRQ_DB5500_SDMMC2               (IRQ_SHPI_START + 41)
-#define IRQ_DB5500_SIA                  (IRQ_SHPI_START + 42)
-#define IRQ_DB5500_SIA2                 (IRQ_SHPI_START + 43)
-#define IRQ_DB5500_HVA                  (IRQ_SHPI_START + 44)
-#define IRQ_DB5500_HVA2                 (IRQ_SHPI_START + 45)
-#define IRQ_DB5500_PRCMU0               (IRQ_SHPI_START + 46)
-#define IRQ_DB5500_PRCMU1               (IRQ_SHPI_START + 47)
-#define IRQ_DB5500_DISP                 (IRQ_SHPI_START + 48)
-#define IRQ_DB5500_SDMMC1               (IRQ_SHPI_START + 50)
-#define IRQ_DB5500_MSP1                 (IRQ_SHPI_START + 52)
-#define IRQ_DB5500_KBD                  (IRQ_SHPI_START + 53)
-#define IRQ_DB5500_I2C2                 (IRQ_SHPI_START + 55)
-#define IRQ_DB5500_B2R2                 (IRQ_SHPI_START + 56)
-#define IRQ_DB5500_CRYP0                (IRQ_SHPI_START + 57)
-#define IRQ_DB5500_SDMMC3               (IRQ_SHPI_START + 59)
-#define IRQ_DB5500_SDMMC0               (IRQ_SHPI_START + 60)
-#define IRQ_DB5500_HSEM                 (IRQ_SHPI_START + 61)
-#define IRQ_DB5500_SBAG                 (IRQ_SHPI_START + 63)
-#define IRQ_DB5500_MODEM                (IRQ_SHPI_START + 65)
-#define IRQ_DB5500_SPI1                 (IRQ_SHPI_START + 96)
-#define IRQ_DB5500_MSP2                 (IRQ_SHPI_START + 98)
-#define IRQ_DB5500_SRPTIMER             (IRQ_SHPI_START + 101)
-#define IRQ_DB5500_CTI0                 (IRQ_SHPI_START + 108)
-#define IRQ_DB5500_CTI1                 (IRQ_SHPI_START + 109)
-#define IRQ_DB5500_ICN_ERR              (IRQ_SHPI_START + 110)
-#define IRQ_DB5500_MALI_PPMMU           (IRQ_SHPI_START + 112)
-#define IRQ_DB5500_MALI_PP              (IRQ_SHPI_START + 113)
-#define IRQ_DB5500_MALI_GPMMU           (IRQ_SHPI_START + 114)
-#define IRQ_DB5500_MALI_GP              (IRQ_SHPI_START + 115)
-#define IRQ_DB5500_MALI                 (IRQ_SHPI_START + 116)
-#define IRQ_DB5500_PRCMU_SEM            (IRQ_SHPI_START + 118)
-#define IRQ_DB5500_GPIO0                (IRQ_SHPI_START + 119)
-#define IRQ_DB5500_GPIO1                (IRQ_SHPI_START + 120)
-#define IRQ_DB5500_GPIO2                (IRQ_SHPI_START + 121)
-#define IRQ_DB5500_GPIO3                (IRQ_SHPI_START + 122)
-#define IRQ_DB5500_GPIO4                (IRQ_SHPI_START + 123)
-#define IRQ_DB5500_GPIO5                (IRQ_SHPI_START + 124)
-#define IRQ_DB5500_GPIO6                (IRQ_SHPI_START + 125)
-#define IRQ_DB5500_GPIO7                (IRQ_SHPI_START + 126)
-#ifdef CONFIG_UX500_SOC_DB5500
-/*
- * After the GPIO ones we reserve a range of IRQ:s in which virtual
- * IRQ:s representing modem IRQ:s can be allocated
- */
-#define IRQ_MODEM_EVENTS_BASE   IRQ_SOC_START
-#define IRQ_MODEM_EVENTS_NBR    72
-#define IRQ_MODEM_EVENTS_END    (IRQ_MODEM_EVENTS_BASE + IRQ_MODEM_EVENTS_NBR)
-/* List of virtual IRQ:s that are allocated from the range above */
-#define MBOX_PAIR0_VIRT_IRQ     (IRQ_MODEM_EVENTS_BASE + 43)
-#define MBOX_PAIR1_VIRT_IRQ     (IRQ_MODEM_EVENTS_BASE + 45)
-#define MBOX_PAIR2_VIRT_IRQ     (IRQ_MODEM_EVENTS_BASE + 41)
-/*
- * We may have several SoCs, but only one will run at a
- * time, so the one with most IRQs will bump this ahead,
- * but the IRQ_SOC_START remains the same for either SoC.
- */
-#if IRQ_SOC_END < IRQ_MODEM_EVENTS_END
-#undef IRQ_SOC_END
-#define IRQ_SOC_END             IRQ_MODEM_EVENTS_END
-#endif
-#endif /* CONFIG_UX500_SOC_DB5500 */
-#endif
diff --git a/arch/arm/mach-ux500/include/mach/irqs.h b/arch/arm/mach-ux500/include/mach/irqs.h
index c23a6b5f0c4e..e8928548b6a3 100644
--- a/arch/arm/mach-ux500/include/mach/irqs.h
+++ b/arch/arm/mach-ux500/include/mach/irqs.h
@@ -24,7 +24,7 @@
 */
 #define IRQ_MTU0                (IRQ_SHPI_START + 4)
-#define DBX500_NR_INTERNAL_IRQS         160
+#define DBX500_NR_INTERNAL_IRQS         166
 /* After chip-specific IRQ numbers we have the GPIO ones */
 #define NOMADIK_NR_GPIO                 288
@@ -36,7 +36,6 @@
 /* This will be overridden by SoC-specific irq headers */
 #define IRQ_SOC_END             IRQ_SOC_START
-#include <mach/irqs-db5500.h>
 #include <mach/irqs-db8500.h>
 #define IRQ_BOARD_START         IRQ_SOC_END
@@ -47,10 +46,6 @@
 #include <mach/irqs-board-mop500.h>
 #endif
-#ifdef CONFIG_MACH_U5500
-#include <mach/irqs-board-u5500.h>
-#endif
 #define NR_IRQS                 IRQ_BOARD_END
 #endif /* ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-ux500/include/mach/mbox-db5500.h b/arch/arm/mach-ux500/include/mach/mbox-db5500.h
deleted file mode 100644
index 7f9da4d2fbda..000000000000
--- a/arch/arm/mach-ux500/include/mach/mbox-db5500.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2010
- * Author: Stefan Nilsson <stefan.xk.nilsson@stericsson.com> for ST-Ericsson.
- * Author: Martin Persson <martin.persson@stericsson.com> for ST-Ericsson.
- * License terms: GNU General Public License (GPL), version 2.
- */
-#ifndef __INC_STE_MBOX_H
-#define __INC_STE_MBOX_H
-#define MBOX_BUF_SIZE 16
-#define MBOX_NAME_SIZE 8
-/**
-  * mbox_recv_cb_t - Definition of the mailbox callback.
-  * @mbox_msg:  The mailbox message.
-  * @priv:      The clients private data as specified in the call to mbox_setup.
-  *
-  * This function will be called upon reception of new mailbox messages.
-  */
-typedef void mbox_recv_cb_t (u32 mbox_msg, void *priv);
-/**
-  * struct mbox - Mailbox instance struct
-  * @list:              Linked list head.
-  * @pdev:              Pointer to device struct.
-  * @cb:                Callback function. Will be called
-  *                     when new data is received.
-  * @client_data:       Clients private data. Will be sent back
-  *                     in the callback function.
-  * @virtbase_peer:     Virtual address for outgoing mailbox.
-  * @virtbase_local:    Virtual address for incoming mailbox.
-  * @buffer:            Then internal queue for outgoing messages.
-  * @name:              Name of this mailbox.
-  * @buffer_available:  Completion variable to achieve "blocking send".
-  *                     This variable will be signaled when there is
-  *                     internal buffer space available.
-  * @client_blocked:    To keep track if any client is currently
-  *                     blocked.
-  * @lock:              Spinlock to protect this mailbox instance.
-  * @write_index:       Index in internal buffer to write to.
-  * @read_index:        Index in internal buffer to read from.
-  * @allocated:         Indicates whether this particular mailbox
-  *                     id has been allocated by someone.
-  */
-struct mbox {
-        struct list_head list;
-        struct platform_device *pdev;
-        mbox_recv_cb_t *cb;
-        void *client_data;
-        void __iomem *virtbase_peer;
-        void __iomem *virtbase_local;
-        u32 buffer[MBOX_BUF_SIZE];
-        char name[MBOX_NAME_SIZE];
-        struct completion buffer_available;
-        u8 client_blocked;
-        spinlock_t lock;
-        u8 write_index;
-        u8 read_index;
-        bool allocated;
-};
-/**
-  * mbox_setup - Set up a mailbox and return its instance.
-  * @mbox_id:   The ID number of the mailbox. 0 or 1 for modem CPU,
-  *             2 for modem DSP.
-  * @mbox_cb:   Pointer to the callback function to be called when a new message
-  *             is received.
-  * @priv:      Client user data which will be returned in the callback.
-  *
-  * Returns a mailbox instance to be specified in subsequent calls to mbox_send.
-  */
-struct mbox *mbox_setup(u8 mbox_id, mbox_recv_cb_t *mbox_cb, void *priv);
-/**
-  * mbox_send - Send a mailbox message.
-  * @mbox:      Mailbox instance (returned by mbox_setup)
-  * @mbox_msg:  The mailbox message to send.
-  * @block:     Specifies whether this call will block until send is possible,
-  *             or return an error if the mailbox buffer is full.
-  *
-  * Returns 0 on success or a negative error code on error. -ENOMEM indicates
-  * that the internal buffer is full and you have to try again later (or
-  * specify "block" in order to block until send is possible).
-  */
-int mbox_send(struct mbox *mbox, u32 mbox_msg, bool block);
-#endif /*INC_STE_MBOX_H*/
diff --git a/arch/arm/mach-ux500/include/mach/msp.h b/arch/arm/mach-ux500/include/mach/msp.h
new file mode 100644
index 000000000000..798be19129ef
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/msp.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
+ * License terms: GNU General Public License (GPL), version 2.
+ */
+#ifndef __MSP_H
+#define __MSP_H
+#include <plat/ste_dma40.h>
+enum msp_i2s_id {
+        MSP_I2S_0 = 0,
+        MSP_I2S_1,
+        MSP_I2S_2,
+        MSP_I2S_3,
+};
+/* Platform data structure for a MSP I2S-device */
+struct msp_i2s_platform_data {
+        enum msp_i2s_id id;
+        struct stedma40_chan_cfg *msp_i2s_dma_rx;
+        struct stedma40_chan_cfg *msp_i2s_dma_tx;
+        int (*msp_i2s_init) (void);
+        int (*msp_i2s_exit) (void);
+};
+#endif
diff --git a/arch/arm/mach-ux500/include/mach/setup.h b/arch/arm/mach-ux500/include/mach/setup.h
index 3dc00ffa7bfa..4e369f1645ec 100644
--- a/arch/arm/mach-ux500/include/mach/setup.h
+++ b/arch/arm/mach-ux500/include/mach/setup.h
@@ -15,18 +15,12 @@
 #include <linux/init.h>
 void __init ux500_map_io(void);
-extern void __init u5500_map_io(void);
 extern void __init u8500_map_io(void);
-extern struct device * __init u5500_init_devices(void);
 extern struct device * __init u8500_init_devices(void);
 extern void __init ux500_init_irq(void);
-extern void __init u5500_sdi_init(struct device *parent);
-extern void __init db5500_dma_init(struct device *parent);
 extern struct device *ux500_soc_device_init(const char *soc_id);
 struct amba_device;
diff --git a/arch/arm/mach-ux500/include/mach/uncompress.h b/arch/arm/mach-ux500/include/mach/uncompress.h
index 6fb3c4b0105d..34775baadaea 100644
--- a/arch/arm/mach-ux500/include/mach/uncompress.h
+++ b/arch/arm/mach-ux500/include/mach/uncompress.h
@@ -50,11 +50,8 @@ static void flush(void)
 static inline void arch_decomp_setup(void)
 {
-        /* Check in run time if we run on an U8500 or U5500 */
+        /* Use machine_is_foo() macro if you need to switch base someday */
-        if (machine_is_u5500())
+        ux500_uart_base = U8500_UART2_BASE;
-                ux500_uart_base = U5500_UART0_BASE;
-        else
-                ux500_uart_base = U8500_UART2_BASE;
 }
 #define arch_decomp_wdog() /* nothing to do here */
diff --git a/arch/arm/mach-ux500/mbox-db5500.c b/arch/arm/mach-ux500/mbox-db5500.c
deleted file mode 100644
index 2b2d51caf9d8..000000000000
--- a/arch/arm/mach-ux500/mbox-db5500.c
+++ /dev/null
@@ -1,565 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2010
- * Author: Stefan Nilsson <stefan.xk.nilsson@stericsson.com> for ST-Ericsson.
- * Author: Martin Persson <martin.persson@stericsson.com> for ST-Ericsson.
- * License terms: GNU General Public License (GPL), version 2.
- */
-/*
- * Mailbox nomenclature:
- *
- *       APE           MODEM
- *           mbox pairX
- *   ..........................
- *   .                       .
- *   .           peer        .
- *   .     send  ----        .
- *   .      -->  |  |        .
- *   .           |  |        .
- *   .           ----        .
- *   .                       .
- *   .           local       .
- *   .     rec   ----        .
- *   .           |  | <--    .
- *   .           |  |        .
- *   .           ----        .
- *   .........................
- */
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/device.h>
-#include <linux/interrupt.h>
-#include <linux/spinlock.h>
-#include <linux/errno.h>
-#include <linux/io.h>
-#include <linux/irq.h>
-#include <linux/platform_device.h>
-#include <linux/debugfs.h>
-#include <linux/seq_file.h>
-#include <linux/completion.h>
-#include <mach/mbox-db5500.h>
-#define MBOX_NAME "mbox"
-#define MBOX_FIFO_DATA        0x000
-#define MBOX_FIFO_ADD         0x004
-#define MBOX_FIFO_REMOVE      0x008
-#define MBOX_FIFO_THRES_FREE  0x00C
-#define MBOX_FIFO_THRES_OCCUP 0x010
-#define MBOX_FIFO_STATUS      0x014
-#define MBOX_DISABLE_IRQ 0x4
-#define MBOX_ENABLE_IRQ  0x0
-#define MBOX_LATCH 1
-/* Global list of all mailboxes */
-static struct list_head mboxs = LIST_HEAD_INIT(mboxs);
-static struct mbox *get_mbox_with_id(u8 id)
-{
-        u8 i;
-        struct list_head *pos = &mboxs;
-        for (i = 0; i <= id; i++)
-                pos = pos->next;
-        return (struct mbox *) list_entry(pos, struct mbox, list);
-}
-int mbox_send(struct mbox *mbox, u32 mbox_msg, bool block)
-{
-        int res = 0;
-        spin_lock(&mbox->lock);
-        dev_dbg(&(mbox->pdev->dev),
-                "About to buffer 0x%X to mailbox 0x%X."
-                " ri = %d, wi = %d\n",
-                mbox_msg, (u32)mbox, mbox->read_index,
-                mbox->write_index);
-        /* Check if write buffer is full */
-        while (((mbox->write_index + 1) % MBOX_BUF_SIZE) == mbox->read_index) {
-                if (!block) {
-                        dev_dbg(&(mbox->pdev->dev),
-                        "Buffer full in non-blocking call! "
-                        "Returning -ENOMEM!\n");
-                        res = -ENOMEM;
-                        goto exit;
-                }
-                spin_unlock(&mbox->lock);
-                dev_dbg(&(mbox->pdev->dev),
-                        "Buffer full in blocking call! Sleeping...\n");
-                mbox->client_blocked = 1;
-                wait_for_completion(&mbox->buffer_available);
-                dev_dbg(&(mbox->pdev->dev),
-                        "Blocking send was woken up! Trying again...\n");
-                spin_lock(&mbox->lock);
-        }
-        mbox->buffer[mbox->write_index] = mbox_msg;
-        mbox->write_index = (mbox->write_index + 1) % MBOX_BUF_SIZE;
-        /*
-         * Indicate that we want an IRQ as soon as there is a slot
-         * in the FIFO
-         */
-        writel(MBOX_ENABLE_IRQ, mbox->virtbase_peer + MBOX_FIFO_THRES_FREE);
-exit:
-        spin_unlock(&mbox->lock);
-        return res;
-}
-EXPORT_SYMBOL(mbox_send);
-#if defined(CONFIG_DEBUG_FS)
-/*
- * Expected input: <value> <nbr sends>
- * Example: "echo 0xdeadbeef 4 > mbox-node" sends 0xdeadbeef 4 times
- */
-static ssize_t mbox_write_fifo(struct device *dev,
-                               struct device_attribute *attr,
-                               const char *buf,
-                               size_t count)
-{
-        unsigned long mbox_mess;
-        unsigned long nbr_sends;
-        unsigned long i;
-        char int_buf[16];
-        char *token;
-        char *val;
-        struct mbox *mbox = (struct mbox *) dev->platform_data;
-        strncpy((char *) &int_buf, buf, sizeof(int_buf));
-        token = (char *) &int_buf;
-        /* Parse message */
-        val = strsep(&token, " ");
-        if ((val == NULL) || (strict_strtoul(val, 16, &mbox_mess) != 0))
-                mbox_mess = 0xDEADBEEF;
-        val = strsep(&token, " ");
-        if ((val == NULL) || (strict_strtoul(val, 10, &nbr_sends) != 0))
-                nbr_sends = 1;
-        dev_dbg(dev, "Will write 0x%lX %ld times using data struct at 0x%X\n",
-                mbox_mess, nbr_sends, (u32) mbox);
-        for (i = 0; i < nbr_sends; i++)
-                mbox_send(mbox, mbox_mess, true);
-        return count;
-}
-static ssize_t mbox_read_fifo(struct device *dev,
-                              struct device_attribute *attr,
-                              char *buf)
-{
-        int mbox_value;
-        struct mbox *mbox = (struct mbox *) dev->platform_data;
-        if ((readl(mbox->virtbase_local + MBOX_FIFO_STATUS) & 0x7) <= 0)
-                return sprintf(buf, "Mailbox is empty\n");
-        mbox_value = readl(mbox->virtbase_local + MBOX_FIFO_DATA);
-        writel(MBOX_LATCH, (mbox->virtbase_local + MBOX_FIFO_REMOVE));
-        return sprintf(buf, "0x%X\n", mbox_value);
-}
-static DEVICE_ATTR(fifo, S_IWUGO | S_IRUGO, mbox_read_fifo, mbox_write_fifo);
-static int mbox_show(struct seq_file *s, void *data)
-{
-        struct list_head *pos;
-        u8 mbox_index = 0;
-        list_for_each(pos, &mboxs) {
-                struct mbox *m =
-                        (struct mbox *) list_entry(pos, struct mbox, list);
-                if (m == NULL) {
-                        seq_printf(s,
-                                   "Unable to retrieve mailbox %d\n",
-                                   mbox_index);
-                        continue;
-                }
-                spin_lock(&m->lock);
-                if ((m->virtbase_peer == NULL) || (m->virtbase_local == NULL)) {
-                        seq_printf(s, "MAILBOX %d not setup or corrupt\n",
-                                   mbox_index);
-                        spin_unlock(&m->lock);
-                        continue;
-                }
-                seq_printf(s,
-                "===========================\n"
-                " MAILBOX %d\n"
-                " PEER MAILBOX DUMP\n"
-                "---------------------------\n"
-                "FIFO:                 0x%X (%d)\n"
-                "Free     Threshold:   0x%.2X (%d)\n"
-                "Occupied Threshold:   0x%.2X (%d)\n"
-                "Status:               0x%.2X (%d)\n"
-                "   Free spaces  (ot):    %d (%d)\n"
-                "   Occup spaces (ot):    %d (%d)\n"
-                "===========================\n"
-                " LOCAL MAILBOX DUMP\n"
-                "---------------------------\n"
-                "FIFO:                 0x%.X (%d)\n"
-                "Free     Threshold:   0x%.2X (%d)\n"
-                "Occupied Threshold:   0x%.2X (%d)\n"
-                "Status:               0x%.2X (%d)\n"
-                "   Free spaces  (ot):    %d (%d)\n"
-                "   Occup spaces (ot):    %d (%d)\n"
-                "===========================\n"
-                "write_index: %d\n"
-                "read_index : %d\n"
-                "===========================\n"
-                "\n",
-                mbox_index,
-                readl(m->virtbase_peer + MBOX_FIFO_DATA),
-                readl(m->virtbase_peer + MBOX_FIFO_DATA),
-                readl(m->virtbase_peer + MBOX_FIFO_THRES_FREE),
-                readl(m->virtbase_peer + MBOX_FIFO_THRES_FREE),
-                readl(m->virtbase_peer + MBOX_FIFO_THRES_OCCUP),
-                readl(m->virtbase_peer + MBOX_FIFO_THRES_OCCUP),
-                readl(m->virtbase_peer + MBOX_FIFO_STATUS),
-                readl(m->virtbase_peer + MBOX_FIFO_STATUS),
-                (readl(m->virtbase_peer + MBOX_FIFO_STATUS) >> 4) & 0x7,
-                (readl(m->virtbase_peer + MBOX_FIFO_STATUS) >> 7) & 0x1,
-                (readl(m->virtbase_peer + MBOX_FIFO_STATUS) >> 0) & 0x7,
-                (readl(m->virtbase_peer + MBOX_FIFO_STATUS) >> 3) & 0x1,
-                readl(m->virtbase_local + MBOX_FIFO_DATA),
-                readl(m->virtbase_local + MBOX_FIFO_DATA),
-                readl(m->virtbase_local + MBOX_FIFO_THRES_FREE),
-                readl(m->virtbase_local + MBOX_FIFO_THRES_FREE),
-                readl(m->virtbase_local + MBOX_FIFO_THRES_OCCUP),
-                readl(m->virtbase_local + MBOX_FIFO_THRES_OCCUP),
-                readl(m->virtbase_local + MBOX_FIFO_STATUS),
-                readl(m->virtbase_local + MBOX_FIFO_STATUS),
-                (readl(m->virtbase_local + MBOX_FIFO_STATUS) >> 4) & 0x7,
-                (readl(m->virtbase_local + MBOX_FIFO_STATUS) >> 7) & 0x1,
-                (readl(m->virtbase_local + MBOX_FIFO_STATUS) >> 0) & 0x7,
-                (readl(m->virtbase_local + MBOX_FIFO_STATUS) >> 3) & 0x1,
-                m->write_index, m->read_index);
-                mbox_index++;
-                spin_unlock(&m->lock);
-        }
-        return 0;
-}
-static int mbox_open(struct inode *inode, struct file *file)
-{
-        return single_open(file, mbox_show, NULL);
-}
-static const struct file_operations mbox_operations = {
-        .owner = THIS_MODULE,
-        .open = mbox_open,
-        .read = seq_read,
-        .llseek = seq_lseek,
-        .release = single_release,
-};
-#endif
-static irqreturn_t mbox_irq(int irq, void *arg)
-{
-        u32 mbox_value;
-        int nbr_occup;
-        int nbr_free;
-        struct mbox *mbox = (struct mbox *) arg;
-        spin_lock(&mbox->lock);
-        dev_dbg(&(mbox->pdev->dev),
-                "mbox IRQ [%d] received. ri = %d, wi = %d\n",
-                irq, mbox->read_index, mbox->write_index);
-        /*
-         * Check if we have any outgoing messages, and if there is space for
-         * them in the FIFO.
-         */
-        if (mbox->read_index != mbox->write_index) {
-                /*
-                 * Check by reading FREE for LOCAL since that indicates
-                 * OCCUP for PEER
-                 */
-                nbr_free = (readl(mbox->virtbase_local + MBOX_FIFO_STATUS)
-                            >> 4) & 0x7;
-                dev_dbg(&(mbox->pdev->dev),
-                        "Status indicates %d empty spaces in the FIFO!\n",
-                        nbr_free);
-                while ((nbr_free > 0) &&
-                       (mbox->read_index != mbox->write_index)) {
-                        /* Write the message and latch it into the FIFO */
-                        writel(mbox->buffer[mbox->read_index],
-                               (mbox->virtbase_peer + MBOX_FIFO_DATA));
-                        writel(MBOX_LATCH,
-                               (mbox->virtbase_peer + MBOX_FIFO_ADD));
-                        dev_dbg(&(mbox->pdev->dev),
-                                "Wrote message 0x%X to addr 0x%X\n",
-                                mbox->buffer[mbox->read_index],
-                                (u32) (mbox->virtbase_peer + MBOX_FIFO_DATA));
-                        nbr_free--;
-                        mbox->read_index =
-                                (mbox->read_index + 1) % MBOX_BUF_SIZE;
-                }
-                /*
-                 * Check if we still want IRQ:s when there is free
-                 * space to send
-                 */
-                if (mbox->read_index != mbox->write_index) {
-                        dev_dbg(&(mbox->pdev->dev),
-                                "Still have messages to send, but FIFO full. "
-                                "Request IRQ again!\n");
-                        writel(MBOX_ENABLE_IRQ,
-                               mbox->virtbase_peer + MBOX_FIFO_THRES_FREE);
-                } else {
-                        dev_dbg(&(mbox->pdev->dev),
-                                "No more messages to send. "
-                                "Do not request IRQ again!\n");
-                        writel(MBOX_DISABLE_IRQ,
-                               mbox->virtbase_peer + MBOX_FIFO_THRES_FREE);
-                }
-                /*
-                 * Check if we can signal any blocked clients that it is OK to
-                 * start buffering again
-                 */
-                if (mbox->client_blocked &&
-                    (((mbox->write_index + 1) % MBOX_BUF_SIZE)
-                     != mbox->read_index)) {
-                        dev_dbg(&(mbox->pdev->dev),
-                                "Waking up blocked client\n");
-                        complete(&mbox->buffer_available);
-                        mbox->client_blocked = 0;
-                }
-        }
-        /* Check if we have any incoming messages */
-        nbr_occup = readl(mbox->virtbase_local + MBOX_FIFO_STATUS) & 0x7;
-        if (nbr_occup == 0)
-                goto exit;
-        if (mbox->cb == NULL) {
-                dev_dbg(&(mbox->pdev->dev), "No receive callback registered, "
-                        "leaving %d incoming messages in fifo!\n", nbr_occup);
-                goto exit;
-        }
-        /* Read and acknowledge the message */
-        mbox_value = readl(mbox->virtbase_local + MBOX_FIFO_DATA);
-        writel(MBOX_LATCH, (mbox->virtbase_local + MBOX_FIFO_REMOVE));
-        /* Notify consumer of new mailbox message */
-        dev_dbg(&(mbox->pdev->dev), "Calling callback for message 0x%X!\n",
-                mbox_value);
-        mbox->cb(mbox_value, mbox->client_data);
-exit:
-        dev_dbg(&(mbox->pdev->dev), "Exit mbox IRQ. ri = %d, wi = %d\n",
-                mbox->read_index, mbox->write_index);
-        spin_unlock(&mbox->lock);
-        return IRQ_HANDLED;
-}
-/* Setup is executed once for each mbox pair */
-struct mbox *mbox_setup(u8 mbox_id, mbox_recv_cb_t *mbox_cb, void *priv)
-{
-        struct resource *resource;
-        int irq;
-        int res;
-        struct mbox *mbox;
-        mbox = get_mbox_with_id(mbox_id);
-        if (mbox == NULL) {
-                dev_err(&(mbox->pdev->dev), "Incorrect mailbox id: %d!\n",
-                        mbox_id);
-                goto exit;
-        }
-        /*
-         * Check if mailbox has been allocated to someone else,
-         * otherwise allocate it
-         */
-        if (mbox->allocated) {
-                dev_err(&(mbox->pdev->dev), "Mailbox number %d is busy!\n",
-                        mbox_id);
-                mbox = NULL;
-                goto exit;
-        }
-        mbox->allocated = true;
-        dev_dbg(&(mbox->pdev->dev), "Initiating mailbox number %d: 0x%X...\n",
-                mbox_id, (u32)mbox);
-        mbox->client_data = priv;
-        mbox->cb = mbox_cb;
-        /* Get addr for peer mailbox and ioremap it */
-        resource = platform_get_resource_byname(mbox->pdev,
-                                                IORESOURCE_MEM,
-                                                "mbox_peer");
-        if (resource == NULL) {
-                dev_err(&(mbox->pdev->dev),
-                        "Unable to retrieve mbox peer resource\n");
-                mbox = NULL;
-                goto exit;
-        }
-        dev_dbg(&(mbox->pdev->dev),
-                "Resource name: %s start: 0x%X, end: 0x%X\n",
-                resource->name, resource->start, resource->end);
-        mbox->virtbase_peer = ioremap(resource->start, resource_size(resource));
-        if (!mbox->virtbase_peer) {
-                dev_err(&(mbox->pdev->dev), "Unable to ioremap peer mbox\n");
-                mbox = NULL;
-                goto exit;
-        }
-        dev_dbg(&(mbox->pdev->dev),
-                "ioremapped peer physical: (0x%X-0x%X) to virtual: 0x%X\n",
-                resource->start, resource->end, (u32) mbox->virtbase_peer);
-        /* Get addr for local mailbox and ioremap it */
-        resource = platform_get_resource_byname(mbox->pdev,
-                                                IORESOURCE_MEM,
-                                                "mbox_local");
-        if (resource == NULL) {
-                dev_err(&(mbox->pdev->dev),
-                        "Unable to retrieve mbox local resource\n");
-                mbox = NULL;
-                goto exit;
-        }
-        dev_dbg(&(mbox->pdev->dev),
-                "Resource name: %s start: 0x%X, end: 0x%X\n",
-                resource->name, resource->start, resource->end);
-        mbox->virtbase_local = ioremap(resource->start, resource_size(resource));
-        if (!mbox->virtbase_local) {
-                dev_err(&(mbox->pdev->dev), "Unable to ioremap local mbox\n");
-                mbox = NULL;
-                goto exit;
-        }
-        dev_dbg(&(mbox->pdev->dev),
-                "ioremapped local physical: (0x%X-0x%X) to virtual: 0x%X\n",
-                resource->start, resource->end, (u32) mbox->virtbase_peer);
-        init_completion(&mbox->buffer_available);
-        mbox->client_blocked = 0;
-        /* Get IRQ for mailbox and allocate it */
-        irq = platform_get_irq_byname(mbox->pdev, "mbox_irq");
-        if (irq < 0) {
-                dev_err(&(mbox->pdev->dev),
-                        "Unable to retrieve mbox irq resource\n");
-                mbox = NULL;
-                goto exit;
-        }
-        dev_dbg(&(mbox->pdev->dev), "Allocating irq %d...\n", irq);
-        res = request_irq(irq, mbox_irq, 0, mbox->name, (void *) mbox);
-        if (res < 0) {
-                dev_err(&(mbox->pdev->dev),
-                        "Unable to allocate mbox irq %d\n", irq);
-                mbox = NULL;
-                goto exit;
-        }
-        /* Set up mailbox to not launch IRQ on free space in mailbox */
-        writel(MBOX_DISABLE_IRQ, mbox->virtbase_peer + MBOX_FIFO_THRES_FREE);
-        /*
-         * Set up mailbox to launch IRQ on new message if we have
-         * a callback set. If not, do not raise IRQ, but keep message
-         * in FIFO for manual retrieval
-         */
-        if (mbox_cb != NULL)
-                writel(MBOX_ENABLE_IRQ,
-                       mbox->virtbase_local + MBOX_FIFO_THRES_OCCUP);
-        else
-                writel(MBOX_DISABLE_IRQ,
-                       mbox->virtbase_local + MBOX_FIFO_THRES_OCCUP);
-#if defined(CONFIG_DEBUG_FS)
-        res = device_create_file(&(mbox->pdev->dev), &dev_attr_fifo);
-        if (res != 0)
-                dev_warn(&(mbox->pdev->dev),
-                         "Unable to create mbox sysfs entry");
-        (void) debugfs_create_file("mbox", S_IFREG | S_IRUGO, NULL,
-                                   NULL, &mbox_operations);
-#endif
-        dev_info(&(mbox->pdev->dev),
-                 "Mailbox driver with index %d initiated!\n", mbox_id);
-exit:
-        return mbox;
-}
-EXPORT_SYMBOL(mbox_setup);
-int __init mbox_probe(struct platform_device *pdev)
-{
-        struct mbox local_mbox;
-        struct mbox *mbox;
-        int res = 0;
-        dev_dbg(&(pdev->dev), "Probing mailbox (pdev = 0x%X)...\n", (u32) pdev);
-        memset(&local_mbox, 0x0, sizeof(struct mbox));
-        /* Associate our mbox data with the platform device */
-        res = platform_device_add_data(pdev,
-                                       (void *) &local_mbox,
-                                       sizeof(struct mbox));
-        if (res != 0) {
-                dev_err(&(pdev->dev),
-                        "Unable to allocate driver platform data!\n");
-                goto exit;
-        }
-        mbox = (struct mbox *) pdev->dev.platform_data;
-        mbox->pdev = pdev;
-        mbox->write_index = 0;
-        mbox->read_index = 0;
-        INIT_LIST_HEAD(&(mbox->list));
-        list_add_tail(&(mbox->list), &mboxs);
-        sprintf(mbox->name, "%s", MBOX_NAME);
-        spin_lock_init(&mbox->lock);
-        dev_info(&(pdev->dev), "Mailbox driver loaded\n");
-exit:
-        return res;
-}
-static struct platform_driver mbox_driver = {
-        .driver = {
-                .name = MBOX_NAME,
-                .owner = THIS_MODULE,
-        },
-};
-static int __init mbox_init(void)
-{
-        return platform_driver_probe(&mbox_driver, mbox_probe);
-}
-module_init(mbox_init);
-void __exit mbox_exit(void)
-{
-        platform_driver_unregister(&mbox_driver);
-}
-module_exit(mbox_exit);
-MODULE_LICENSE("GPL");
-MODULE_DESCRIPTION("MBOX driver");
diff --git a/arch/arm/mach-ux500/modem-irq-db5500.c b/arch/arm/mach-ux500/modem-irq-db5500.c
deleted file mode 100644
index 6b86416c94c9..000000000000
--- a/arch/arm/mach-ux500/modem-irq-db5500.c
+++ /dev/null
@@ -1,143 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2010
- * Author: Stefan Nilsson <stefan.xk.nilsson@stericsson.com> for ST-Ericsson.
- * Author: Martin Persson <martin.persson@stericsson.com> for ST-Ericsson.
- * License terms: GNU General Public License (GPL), version 2.
- */
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/io.h>
-#include <linux/slab.h>
-#include <mach/id.h>
-#define MODEM_INTCON_BASE_ADDR 0xBFFD3000
-#define MODEM_INTCON_SIZE 0xFFF
-#define DEST_IRQ41_OFFSET 0x2A4
-#define DEST_IRQ43_OFFSET 0x2AC
-#define DEST_IRQ45_OFFSET 0x2B4
-#define PRIO_IRQ41_OFFSET 0x6A4
-#define PRIO_IRQ43_OFFSET 0x6AC
-#define PRIO_IRQ45_OFFSET 0x6B4
-#define ALLOW_IRQ_OFFSET 0x104
-#define MODEM_INTCON_CPU_NBR 0x1
-#define MODEM_INTCON_PRIO_HIGH 0x0
-#define MODEM_INTCON_ALLOW_IRQ41 0x0200
-#define MODEM_INTCON_ALLOW_IRQ43 0x0800
-#define MODEM_INTCON_ALLOW_IRQ45 0x2000
-#define MODEM_IRQ_REG_OFFSET 0x4
-struct modem_irq {
-        void __iomem *modem_intcon_base;
-};
-static void setup_modem_intcon(void __iomem *modem_intcon_base)
-{
-        /* IC_DESTINATION_BASE_ARRAY - Which CPU to receive the IRQ */
-        writel(MODEM_INTCON_CPU_NBR, modem_intcon_base + DEST_IRQ41_OFFSET);
-        writel(MODEM_INTCON_CPU_NBR, modem_intcon_base + DEST_IRQ43_OFFSET);
-        writel(MODEM_INTCON_CPU_NBR, modem_intcon_base + DEST_IRQ45_OFFSET);
-        /* IC_PRIORITY_BASE_ARRAY - IRQ priority in modem IRQ controller */
-        writel(MODEM_INTCON_PRIO_HIGH, modem_intcon_base + PRIO_IRQ41_OFFSET);
-        writel(MODEM_INTCON_PRIO_HIGH, modem_intcon_base + PRIO_IRQ43_OFFSET);
-        writel(MODEM_INTCON_PRIO_HIGH, modem_intcon_base + PRIO_IRQ45_OFFSET);
-        /* IC_ALLOW_ARRAY - IRQ enable */
-        writel(MODEM_INTCON_ALLOW_IRQ41 |
-                   MODEM_INTCON_ALLOW_IRQ43 |
-                   MODEM_INTCON_ALLOW_IRQ45,
-                   modem_intcon_base + ALLOW_IRQ_OFFSET);
-}
-static irqreturn_t modem_cpu_irq_handler(int irq, void *data)
-{
-        int real_irq;
-        int virt_irq;
-        struct modem_irq *mi = (struct modem_irq *)data;
-        /* Read modem side IRQ number from modem IRQ controller */
-        real_irq = readl(mi->modem_intcon_base + MODEM_IRQ_REG_OFFSET) & 0xFF;
-        virt_irq = IRQ_MODEM_EVENTS_BASE + real_irq;
-        pr_debug("modem_irq: Worker read addr 0x%X and got value 0x%X "
-                 "which will be 0x%X (%d) which translates to "
-                 "virtual IRQ 0x%X (%d)!\n",
-                   (u32)mi->modem_intcon_base + MODEM_IRQ_REG_OFFSET,
-                   real_irq,
-                   real_irq & 0xFF,
-                   real_irq & 0xFF,
-                   virt_irq,
-                   virt_irq);
-        if (virt_irq != 0)
-                generic_handle_irq(virt_irq);
-        pr_debug("modem_irq: Done handling virtual IRQ %d!\n", virt_irq);
-        return IRQ_HANDLED;
-}
-static void create_virtual_irq(int irq, struct irq_chip *modem_irq_chip)
-{
-        irq_set_chip_and_handler(irq, modem_irq_chip, handle_simple_irq);
-        set_irq_flags(irq, IRQF_VALID);
-        pr_debug("modem_irq: Created virtual IRQ %d\n", irq);
-}
-static int modem_irq_init(void)
-{
-        int err;
-        static struct irq_chip  modem_irq_chip;
-        struct modem_irq *mi;
-        if (!cpu_is_u5500())
-                return -ENODEV;
-        pr_info("modem_irq: Set up IRQ handler for incoming modem IRQ %d\n",
-                   IRQ_DB5500_MODEM);
-        mi = kmalloc(sizeof(struct modem_irq), GFP_KERNEL);
-        if (!mi) {
-                pr_err("modem_irq: Could not allocate device\n");
-                return -ENOMEM;
-        }
-        mi->modem_intcon_base =
-                ioremap(MODEM_INTCON_BASE_ADDR, MODEM_INTCON_SIZE);
-        pr_debug("modem_irq: ioremapped modem_intcon_base from "
-                 "phy 0x%x to virt 0x%x\n", MODEM_INTCON_BASE_ADDR,
-                 (u32)mi->modem_intcon_base);
-        setup_modem_intcon(mi->modem_intcon_base);
-        modem_irq_chip = dummy_irq_chip;
-        modem_irq_chip.name = "modem_irq";
-        /* Create the virtual IRQ:s needed */
-        create_virtual_irq(MBOX_PAIR0_VIRT_IRQ, &modem_irq_chip);
-        create_virtual_irq(MBOX_PAIR1_VIRT_IRQ, &modem_irq_chip);
-        create_virtual_irq(MBOX_PAIR2_VIRT_IRQ, &modem_irq_chip);
-        err = request_threaded_irq(IRQ_DB5500_MODEM, NULL,
-                                   modem_cpu_irq_handler, IRQF_ONESHOT,
-                                   "modem_irq", mi);
-        if (err)
-                pr_err("modem_irq: Could not register IRQ %d\n",
-                       IRQ_DB5500_MODEM);
-        return 0;
-}
-arch_initcall(modem_irq_init);
diff --git a/arch/arm/mach-ux500/pins-db5500.h b/arch/arm/mach-ux500/pins-db5500.h
deleted file mode 100644
index bf50c21fe69d..000000000000
--- a/arch/arm/mach-ux500/pins-db5500.h
+++ /dev/null
@@ -1,620 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2010
- *
- * License terms: GNU General Public License, version 2
- * Author: Rabin Vincent <rabin.vincent@stericsson.com>
- */
-#ifndef __MACH_DB5500_PINS_H
-#define __MACH_DB5500_PINS_H
-#define GPIO0_GPIO              PIN_CFG(0, GPIO)
-#define GPIO0_SM_CS3n           PIN_CFG(0, ALT_A)
-#define GPIO1_GPIO              PIN_CFG(1, GPIO)
-#define GPIO1_SM_A3             PIN_CFG(1, ALT_A)
-#define GPIO2_GPIO              PIN_CFG(2, GPIO)
-#define GPIO2_SM_A4             PIN_CFG(2, ALT_A)
-#define GPIO2_SM_AVD            PIN_CFG(2, ALT_B)
-#define GPIO3_GPIO              PIN_CFG(3, GPIO)
-#define GPIO3_I2C1_SCL          PIN_CFG(3, ALT_A)
-#define GPIO4_GPIO              PIN_CFG(4, GPIO)
-#define GPIO4_I2C1_SDA          PIN_CFG(4, ALT_A)
-#define GPIO5_GPIO              PIN_CFG(5, GPIO)
-#define GPIO5_MC0_DAT0          PIN_CFG(5, ALT_A)
-#define GPIO5_SM_ADQ8           PIN_CFG(5, ALT_B)
-#define GPIO6_GPIO              PIN_CFG(6, GPIO)
-#define GPIO6_MC0_DAT1          PIN_CFG(6, ALT_A)
-#define GPIO6_SM_ADQ0           PIN_CFG(6, ALT_B)
-#define GPIO7_GPIO              PIN_CFG(7, GPIO)
-#define GPIO7_MC0_DAT2          PIN_CFG(7, ALT_A)
-#define GPIO7_SM_ADQ9           PIN_CFG(7, ALT_B)
-#define GPIO8_GPIO              PIN_CFG(8, GPIO)
-#define GPIO8_MC0_DAT3          PIN_CFG(8, ALT_A)
-#define GPIO8_SM_ADQ1           PIN_CFG(8, ALT_B)
-#define GPIO9_GPIO              PIN_CFG(9, GPIO)
-#define GPIO9_MC0_DAT4          PIN_CFG(9, ALT_A)
-#define GPIO9_SM_ADQ10          PIN_CFG(9, ALT_B)
-#define GPIO10_GPIO             PIN_CFG(10, GPIO)
-#define GPIO10_MC0_DAT5         PIN_CFG(10, ALT_A)
-#define GPIO10_SM_ADQ2          PIN_CFG(10, ALT_B)
-#define GPIO11_GPIO             PIN_CFG(11, GPIO)
-#define GPIO11_MC0_DAT6         PIN_CFG(11, ALT_A)
-#define GPIO11_SM_ADQ11         PIN_CFG(11, ALT_B)
-#define GPIO12_GPIO             PIN_CFG(12, GPIO)
-#define GPIO12_MC0_DAT7         PIN_CFG(12, ALT_A)
-#define GPIO12_SM_ADQ3          PIN_CFG(12, ALT_B)
-#define GPIO13_GPIO             PIN_CFG(13, GPIO)
-#define GPIO13_MC0_CMD          PIN_CFG(13, ALT_A)
-#define GPIO13_SM_BUSY0n        PIN_CFG(13, ALT_B)
-#define GPIO13_SM_WAIT0n        PIN_CFG(13, ALT_C)
-#define GPIO14_GPIO             PIN_CFG(14, GPIO)
-#define GPIO14_MC0_CLK          PIN_CFG(14, ALT_A)
-#define GPIO14_SM_CS1n          PIN_CFG(14, ALT_B)
-#define GPIO14_SM_CKO           PIN_CFG(14, ALT_C)
-#define GPIO15_GPIO             PIN_CFG(15, GPIO)
-#define GPIO15_SM_A5            PIN_CFG(15, ALT_A)
-#define GPIO15_SM_CLE           PIN_CFG(15, ALT_B)
-#define GPIO16_GPIO             PIN_CFG(16, GPIO)
-#define GPIO16_MC2_CMD          PIN_CFG(16, ALT_A)
-#define GPIO16_SM_OEn           PIN_CFG(16, ALT_B)
-#define GPIO17_GPIO             PIN_CFG(17, GPIO)
-#define GPIO17_MC2_CLK          PIN_CFG(17, ALT_A)
-#define GPIO17_SM_WEn           PIN_CFG(17, ALT_B)
-#define GPIO18_GPIO             PIN_CFG(18, GPIO)
-#define GPIO18_SM_A6            PIN_CFG(18, ALT_A)
-#define GPIO18_SM_ALE           PIN_CFG(18, ALT_B)
-#define GPIO18_SM_AVDn          PIN_CFG(18, ALT_C)
-#define GPIO19_GPIO             PIN_CFG(19, GPIO)
-#define GPIO19_MC2_DAT1         PIN_CFG(19, ALT_A)
-#define GPIO19_SM_ADQ4          PIN_CFG(19, ALT_B)
-#define GPIO20_GPIO             PIN_CFG(20, GPIO)
-#define GPIO20_MC2_DAT3         PIN_CFG(20, ALT_A)
-#define GPIO20_SM_ADQ5          PIN_CFG(20, ALT_B)
-#define GPIO21_GPIO             PIN_CFG(21, GPIO)
-#define GPIO21_MC2_DAT5         PIN_CFG(21, ALT_A)
-#define GPIO21_SM_ADQ6          PIN_CFG(21, ALT_B)
-#define GPIO22_GPIO             PIN_CFG(22, GPIO)
-#define GPIO22_MC2_DAT7         PIN_CFG(22, ALT_A)
-#define GPIO22_SM_ADQ7          PIN_CFG(22, ALT_B)
-#define GPIO23_GPIO             PIN_CFG(23, GPIO)
-#define GPIO23_MC2_DAT0         PIN_CFG(23, ALT_A)
-#define GPIO23_SM_ADQ12         PIN_CFG(23, ALT_B)
-#define GPIO23_MC0_DAT1         PIN_CFG(23, ALT_C)
-#define GPIO24_GPIO             PIN_CFG(24, GPIO)
-#define GPIO24_MC2_DAT2         PIN_CFG(24, ALT_A)
-#define GPIO24_SM_ADQ13         PIN_CFG(24, ALT_B)
-#define GPIO24_MC0_DAT3         PIN_CFG(24, ALT_C)
-#define GPIO25_GPIO             PIN_CFG(25, GPIO)
-#define GPIO25_MC2_DAT4         PIN_CFG(25, ALT_A)
-#define GPIO25_SM_ADQ14         PIN_CFG(25, ALT_B)
-#define GPIO25_MC0_CMD          PIN_CFG(25, ALT_C)
-#define GPIO26_GPIO             PIN_CFG(26, GPIO)
-#define GPIO26_MC2_DAT6         PIN_CFG(26, ALT_A)
-#define GPIO26_SM_ADQ15         PIN_CFG(26, ALT_B)
-#define GPIO27_GPIO             PIN_CFG(27, GPIO)
-#define GPIO27_SM_CS0n          PIN_CFG(27, ALT_A)
-#define GPIO27_SM_PS0n          PIN_CFG(27, ALT_B)
-#define GPIO28_GPIO             PIN_CFG(28, GPIO)
-#define GPIO28_U0_TXD           PIN_CFG(28, ALT_A)
-#define GPIO28_SM_A0            PIN_CFG(28, ALT_B)
-#define GPIO29_GPIO             PIN_CFG(29, GPIO)
-#define GPIO29_U0_RXD           PIN_CFG(29, ALT_A)
-#define GPIO29_SM_A1            PIN_CFG(29, ALT_B)
-#define GPIO29_PWM_0            PIN_CFG(29, ALT_C)
-#define GPIO30_GPIO             PIN_CFG(30, GPIO)
-#define GPIO30_MC0_DAT5         PIN_CFG(30, ALT_A)
-#define GPIO30_SM_A2            PIN_CFG(30, ALT_B)
-#define GPIO30_PWM_1            PIN_CFG(30, ALT_C)
-#define GPIO31_GPIO             PIN_CFG(31, GPIO)
-#define GPIO31_MC0_DAT7         PIN_CFG(31, ALT_A)
-#define GPIO31_SM_CS2n          PIN_CFG(31, ALT_B)
-#define GPIO31_PWM_2            PIN_CFG(31, ALT_C)
-#define GPIO32_GPIO             PIN_CFG(32, GPIO)
-#define GPIO32_MSP0_TCK         PIN_CFG(32, ALT_A)
-#define GPIO32_ACCI2S0_SCK      PIN_CFG(32, ALT_B)
-#define GPIO33_GPIO             PIN_CFG(33, GPIO)
-#define GPIO33_MSP0_TFS         PIN_CFG(33, ALT_A)
-#define GPIO33_ACCI2S0_WS       PIN_CFG(33, ALT_B)
-#define GPIO34_GPIO             PIN_CFG(34, GPIO)
-#define GPIO34_MSP0_TXD         PIN_CFG(34, ALT_A)
-#define GPIO34_ACCI2S0_DLD      PIN_CFG(34, ALT_B)
-#define GPIO35_GPIO             PIN_CFG(35, GPIO)
-#define GPIO35_MSP0_RXD         PIN_CFG(35, ALT_A)
-#define GPIO35_ACCI2S0_ULD      PIN_CFG(35, ALT_B)
-#define GPIO64_GPIO             PIN_CFG(64, GPIO)
-#define GPIO64_USB_DAT0         PIN_CFG(64, ALT_A)
-#define GPIO64_U0_TXD           PIN_CFG(64, ALT_B)
-#define GPIO65_GPIO             PIN_CFG(65, GPIO)
-#define GPIO65_USB_DAT1         PIN_CFG(65, ALT_A)
-#define GPIO65_U0_RXD           PIN_CFG(65, ALT_B)
-#define GPIO66_GPIO             PIN_CFG(66, GPIO)
-#define GPIO66_USB_DAT2         PIN_CFG(66, ALT_A)
-#define GPIO67_GPIO             PIN_CFG(67, GPIO)
-#define GPIO67_USB_DAT3         PIN_CFG(67, ALT_A)
-#define GPIO68_GPIO             PIN_CFG(68, GPIO)
-#define GPIO68_USB_DAT4         PIN_CFG(68, ALT_A)
-#define GPIO69_GPIO             PIN_CFG(69, GPIO)
-#define GPIO69_USB_DAT5         PIN_CFG(69, ALT_A)
-#define GPIO70_GPIO             PIN_CFG(70, GPIO)
-#define GPIO70_USB_DAT6         PIN_CFG(70, ALT_A)
-#define GPIO71_GPIO             PIN_CFG(71, GPIO)
-#define GPIO71_USB_DAT7         PIN_CFG(71, ALT_A)
-#define GPIO72_GPIO             PIN_CFG(72, GPIO)
-#define GPIO72_USB_STP          PIN_CFG(72, ALT_A)
-#define GPIO73_GPIO             PIN_CFG(73, GPIO)
-#define GPIO73_USB_DIR          PIN_CFG(73, ALT_A)
-#define GPIO74_GPIO             PIN_CFG(74, GPIO)
-#define GPIO74_USB_NXT          PIN_CFG(74, ALT_A)
-#define GPIO75_GPIO             PIN_CFG(75, GPIO)
-#define GPIO75_USB_XCLK         PIN_CFG(75, ALT_A)
-#define GPIO76_GPIO             PIN_CFG(76, GPIO)
-#define GPIO77_GPIO             PIN_CFG(77, GPIO)
-#define GPIO77_ACCTX_ON         PIN_CFG(77, ALT_A)
-#define GPIO78_GPIO             PIN_CFG(78, GPIO)
-#define GPIO78_IRQn             PIN_CFG(78, ALT_A)
-#define GPIO79_GPIO             PIN_CFG(79, GPIO)
-#define GPIO79_ACCSIM_Clk       PIN_CFG(79, ALT_A)
-#define GPIO80_GPIO             PIN_CFG(80, GPIO)
-#define GPIO80_ACCSIM_Da        PIN_CFG(80, ALT_A)
-#define GPIO81_GPIO             PIN_CFG(81, GPIO)
-#define GPIO81_ACCSIM_Reset     PIN_CFG(81, ALT_A)
-#define GPIO82_GPIO             PIN_CFG(82, GPIO)
-#define GPIO82_ACCSIM_DDir      PIN_CFG(82, ALT_A)
-#define GPIO96_GPIO             PIN_CFG(96, GPIO)
-#define GPIO96_MSP1_TCK         PIN_CFG(96, ALT_A)
-#define GPIO96_PRCMU_DEBUG3     PIN_CFG(96, ALT_B)
-#define GPIO96_PRCMU_DEBUG7     PIN_CFG(96, ALT_C)
-#define GPIO97_GPIO             PIN_CFG(97, GPIO)
-#define GPIO97_MSP1_TFS         PIN_CFG(97, ALT_A)
-#define GPIO97_PRCMU_DEBUG2     PIN_CFG(97, ALT_B)
-#define GPIO97_PRCMU_DEBUG6     PIN_CFG(97, ALT_C)
-#define GPIO98_GPIO             PIN_CFG(98, GPIO)
-#define GPIO98_MSP1_TXD         PIN_CFG(98, ALT_A)
-#define GPIO98_PRCMU_DEBUG1     PIN_CFG(98, ALT_B)
-#define GPIO98_PRCMU_DEBUG5     PIN_CFG(98, ALT_C)
-#define GPIO99_GPIO             PIN_CFG(99, GPIO)
-#define GPIO99_MSP1_RXD         PIN_CFG(99, ALT_A)
-#define GPIO99_PRCMU_DEBUG0     PIN_CFG(99, ALT_B)
-#define GPIO99_PRCMU_DEBUG4     PIN_CFG(99, ALT_C)
-#define GPIO100_GPIO            PIN_CFG(100, GPIO)
-#define GPIO100_I2C0_SCL        PIN_CFG(100, ALT_A)
-#define GPIO101_GPIO            PIN_CFG(101, GPIO)
-#define GPIO101_I2C0_SDA        PIN_CFG(101, ALT_A)
-#define GPIO128_GPIO            PIN_CFG(128, GPIO)
-#define GPIO128_KP_I0           PIN_CFG(128, ALT_A)
-#define GPIO128_BUSMON_D0       PIN_CFG(128, ALT_B)
-#define GPIO129_GPIO            PIN_CFG(129, GPIO)
-#define GPIO129_KP_O0           PIN_CFG(129, ALT_A)
-#define GPIO129_BUSMON_D1       PIN_CFG(129, ALT_B)
-#define GPIO130_GPIO            PIN_CFG(130, GPIO)
-#define GPIO130_KP_I1           PIN_CFG(130, ALT_A)
-#define GPIO130_BUSMON_D2       PIN_CFG(130, ALT_B)
-#define GPIO131_GPIO            PIN_CFG(131, GPIO)
-#define GPIO131_KP_O1           PIN_CFG(131, ALT_A)
-#define GPIO131_BUSMON_D3       PIN_CFG(131, ALT_B)
-#define GPIO132_GPIO            PIN_CFG(132, GPIO)
-#define GPIO132_KP_I2           PIN_CFG(132, ALT_A)
-#define GPIO132_ETM_D15         PIN_CFG(132, ALT_B)
-#define GPIO132_STMAPE_CLK      PIN_CFG(132, ALT_C)
-#define GPIO133_GPIO            PIN_CFG(133, GPIO)
-#define GPIO133_KP_O2           PIN_CFG(133, ALT_A)
-#define GPIO133_ETM_D14         PIN_CFG(133, ALT_B)
-#define GPIO133_U0_RXD          PIN_CFG(133, ALT_C)
-#define GPIO134_GPIO            PIN_CFG(134, GPIO)
-#define GPIO134_KP_I3           PIN_CFG(134, ALT_A)
-#define GPIO134_ETM_D13         PIN_CFG(134, ALT_B)
-#define GPIO134_STMAPE_DAT0     PIN_CFG(134, ALT_C)
-#define GPIO135_GPIO            PIN_CFG(135, GPIO)
-#define GPIO135_KP_O3           PIN_CFG(135, ALT_A)
-#define GPIO135_ETM_D12         PIN_CFG(135, ALT_B)
-#define GPIO135_STMAPE_DAT1     PIN_CFG(135, ALT_C)
-#define GPIO136_GPIO            PIN_CFG(136, GPIO)
-#define GPIO136_KP_I4           PIN_CFG(136, ALT_A)
-#define GPIO136_ETM_D11         PIN_CFG(136, ALT_B)
-#define GPIO136_STMAPE_DAT2     PIN_CFG(136, ALT_C)
-#define GPIO137_GPIO            PIN_CFG(137, GPIO)
-#define GPIO137_KP_O4           PIN_CFG(137, ALT_A)
-#define GPIO137_ETM_D10         PIN_CFG(137, ALT_B)
-#define GPIO137_STMAPE_DAT3     PIN_CFG(137, ALT_C)
-#define GPIO138_GPIO            PIN_CFG(138, GPIO)
-#define GPIO138_KP_I5           PIN_CFG(138, ALT_A)
-#define GPIO138_ETM_D9          PIN_CFG(138, ALT_B)
-#define GPIO138_U0_TXD          PIN_CFG(138, ALT_C)
-#define GPIO139_GPIO            PIN_CFG(139, GPIO)
-#define GPIO139_KP_O5           PIN_CFG(139, ALT_A)
-#define GPIO139_ETM_D8          PIN_CFG(139, ALT_B)
-#define GPIO139_BUSMON_D11      PIN_CFG(139, ALT_C)
-#define GPIO140_GPIO            PIN_CFG(140, GPIO)
-#define GPIO140_KP_I6           PIN_CFG(140, ALT_A)
-#define GPIO140_ETM_D7          PIN_CFG(140, ALT_B)
-#define GPIO140_STMAPE_CLK      PIN_CFG(140, ALT_C)
-#define GPIO141_GPIO            PIN_CFG(141, GPIO)
-#define GPIO141_KP_O6           PIN_CFG(141, ALT_A)
-#define GPIO141_ETM_D6          PIN_CFG(141, ALT_B)
-#define GPIO141_U0_RXD          PIN_CFG(141, ALT_C)
-#define GPIO142_GPIO            PIN_CFG(142, GPIO)
-#define GPIO142_KP_I7           PIN_CFG(142, ALT_A)
-#define GPIO142_ETM_D5          PIN_CFG(142, ALT_B)
-#define GPIO142_STMAPE_DAT0     PIN_CFG(142, ALT_C)
-#define GPIO143_GPIO            PIN_CFG(143, GPIO)
-#define GPIO143_KP_O7           PIN_CFG(143, ALT_A)
-#define GPIO143_ETM_D4          PIN_CFG(143, ALT_B)
-#define GPIO143_STMAPE_DAT1     PIN_CFG(143, ALT_C)
-#define GPIO144_GPIO            PIN_CFG(144, GPIO)
-#define GPIO144_I2C3_SCL        PIN_CFG(144, ALT_A)
-#define GPIO144_ETM_D3          PIN_CFG(144, ALT_B)
-#define GPIO144_STMAPE_DAT2     PIN_CFG(144, ALT_C)
-#define GPIO145_GPIO            PIN_CFG(145, GPIO)
-#define GPIO145_I2C3_SDA        PIN_CFG(145, ALT_A)
-#define GPIO145_ETM_D2          PIN_CFG(145, ALT_B)
-#define GPIO145_STMAPE_DAT3     PIN_CFG(145, ALT_C)
-#define GPIO146_GPIO            PIN_CFG(146, GPIO)
-#define GPIO146_PWM_0           PIN_CFG(146, ALT_A)
-#define GPIO146_ETM_D1          PIN_CFG(146, ALT_B)
-#define GPIO147_GPIO            PIN_CFG(147, GPIO)
-#define GPIO147_PWM_1           PIN_CFG(147, ALT_A)
-#define GPIO147_ETM_D0          PIN_CFG(147, ALT_B)
-#define GPIO148_GPIO            PIN_CFG(148, GPIO)
-#define GPIO148_PWM_2           PIN_CFG(148, ALT_A)
-#define GPIO148_ETM_CLK         PIN_CFG(148, ALT_B)
-#define GPIO160_GPIO            PIN_CFG(160, GPIO)
-#define GPIO160_CLKOUT_REQn     PIN_CFG(160, ALT_A)
-#define GPIO161_GPIO            PIN_CFG(161, GPIO)
-#define GPIO161_CLKOUT_0        PIN_CFG(161, ALT_A)
-#define GPIO162_GPIO            PIN_CFG(162, GPIO)
-#define GPIO162_CLKOUT_1        PIN_CFG(162, ALT_A)
-#define GPIO163_GPIO            PIN_CFG(163, GPIO)
-#define GPIO164_GPIO            PIN_CFG(164, GPIO)
-#define GPIO164_GPS_START       PIN_CFG(164, ALT_A)
-#define GPIO165_GPIO            PIN_CFG(165, GPIO)
-#define GPIO165_SPI1_CS2n       PIN_CFG(165, ALT_A)
-#define GPIO165_U3_RXD          PIN_CFG(165, ALT_B)
-#define GPIO165_BUSMON_D20      PIN_CFG(165, ALT_C)
-#define GPIO166_GPIO            PIN_CFG(166, GPIO)
-#define GPIO166_SPI1_CS1n       PIN_CFG(166, ALT_A)
-#define GPIO166_U3_TXD          PIN_CFG(166, ALT_B)
-#define GPIO166_BUSMON_D21      PIN_CFG(166, ALT_C)
-#define GPIO167_GPIO            PIN_CFG(167, GPIO)
-#define GPIO167_SPI1_CS0n       PIN_CFG(167, ALT_A)
-#define GPIO167_U3_RTSn         PIN_CFG(167, ALT_B)
-#define GPIO167_BUSMON_D22      PIN_CFG(167, ALT_C)
-#define GPIO168_GPIO            PIN_CFG(168, GPIO)
-#define GPIO168_SPI1_RXD        PIN_CFG(168, ALT_A)
-#define GPIO168_U3_CTSn         PIN_CFG(168, ALT_B)
-#define GPIO168_BUSMON_D23      PIN_CFG(168, ALT_C)
-#define GPIO169_GPIO            PIN_CFG(169, GPIO)
-#define GPIO169_SPI1_TXD        PIN_CFG(169, ALT_A)
-#define GPIO169_DDR_RC          PIN_CFG(169, ALT_B)
-#define GPIO169_BUSMON_D24      PIN_CFG(169, ALT_C)
-#define GPIO170_GPIO            PIN_CFG(170, GPIO)
-#define GPIO170_SPI1_CLK        PIN_CFG(170, ALT_A)
-#define GPIO171_GPIO            PIN_CFG(171, GPIO)
-#define GPIO171_MC3_DAT0        PIN_CFG(171, ALT_A)
-#define GPIO171_SPI3_RXD        PIN_CFG(171, ALT_B)
-#define GPIO171_BUSMON_D25      PIN_CFG(171, ALT_C)
-#define GPIO172_GPIO            PIN_CFG(172, GPIO)
-#define GPIO172_MC3_DAT1        PIN_CFG(172, ALT_A)
-#define GPIO172_SPI3_CS1n       PIN_CFG(172, ALT_B)
-#define GPIO172_BUSMON_D26      PIN_CFG(172, ALT_C)
-#define GPIO173_GPIO            PIN_CFG(173, GPIO)
-#define GPIO173_MC3_DAT2        PIN_CFG(173, ALT_A)
-#define GPIO173_SPI3_CS2n       PIN_CFG(173, ALT_B)
-#define GPIO173_BUSMON_D27      PIN_CFG(173, ALT_C)
-#define GPIO174_GPIO            PIN_CFG(174, GPIO)
-#define GPIO174_MC3_DAT3        PIN_CFG(174, ALT_A)
-#define GPIO174_SPI3_CS0n       PIN_CFG(174, ALT_B)
-#define GPIO174_BUSMON_D28      PIN_CFG(174, ALT_C)
-#define GPIO175_GPIO            PIN_CFG(175, GPIO)
-#define GPIO175_MC3_CMD         PIN_CFG(175, ALT_A)
-#define GPIO175_SPI3_TXD        PIN_CFG(175, ALT_B)
-#define GPIO175_BUSMON_D29      PIN_CFG(175, ALT_C)
-#define GPIO176_GPIO            PIN_CFG(176, GPIO)
-#define GPIO176_MC3_CLK         PIN_CFG(176, ALT_A)
-#define GPIO176_SPI3_CLK        PIN_CFG(176, ALT_B)
-#define GPIO177_GPIO            PIN_CFG(177, GPIO)
-#define GPIO177_U2_RXD          PIN_CFG(177, ALT_A)
-#define GPIO177_I2C3_SCL        PIN_CFG(177, ALT_B)
-#define GPIO177_BUSMON_D30      PIN_CFG(177, ALT_C)
-#define GPIO178_GPIO            PIN_CFG(178, GPIO)
-#define GPIO178_U2_TXD          PIN_CFG(178, ALT_A)
-#define GPIO178_I2C3_SDA        PIN_CFG(178, ALT_B)
-#define GPIO178_BUSMON_D31      PIN_CFG(178, ALT_C)
-#define GPIO179_GPIO            PIN_CFG(179, GPIO)
-#define GPIO179_U2_CTSn         PIN_CFG(179, ALT_A)
-#define GPIO179_U3_RXD          PIN_CFG(179, ALT_B)
-#define GPIO179_BUSMON_D32      PIN_CFG(179, ALT_C)
-#define GPIO180_GPIO            PIN_CFG(180, GPIO)
-#define GPIO180_U2_RTSn         PIN_CFG(180, ALT_A)
-#define GPIO180_U3_TXD          PIN_CFG(180, ALT_B)
-#define GPIO180_BUSMON_D33      PIN_CFG(180, ALT_C)
-#define GPIO185_GPIO            PIN_CFG(185, GPIO)
-#define GPIO185_SPI3_CS2n       PIN_CFG(185, ALT_A)
-#define GPIO185_MC4_DAT0        PIN_CFG(185, ALT_B)
-#define GPIO186_GPIO            PIN_CFG(186, GPIO)
-#define GPIO186_SPI3_CS1n       PIN_CFG(186, ALT_A)
-#define GPIO186_MC4_DAT1        PIN_CFG(186, ALT_B)
-#define GPIO187_GPIO            PIN_CFG(187, GPIO)
-#define GPIO187_SPI3_CS0n       PIN_CFG(187, ALT_A)
-#define GPIO187_MC4_DAT2        PIN_CFG(187, ALT_B)
-#define GPIO188_GPIO            PIN_CFG(188, GPIO)
-#define GPIO188_SPI3_RXD        PIN_CFG(188, ALT_A)
-#define GPIO188_MC4_DAT3        PIN_CFG(188, ALT_B)
-#define GPIO189_GPIO            PIN_CFG(189, GPIO)
-#define GPIO189_SPI3_TXD        PIN_CFG(189, ALT_A)
-#define GPIO189_MC4_CMD         PIN_CFG(189, ALT_B)
-#define GPIO190_GPIO            PIN_CFG(190, GPIO)
-#define GPIO190_SPI3_CLK        PIN_CFG(190, ALT_A)
-#define GPIO190_MC4_CLK         PIN_CFG(190, ALT_B)
-#define GPIO191_GPIO            PIN_CFG(191, GPIO)
-#define GPIO191_MC1_DAT0        PIN_CFG(191, ALT_A)
-#define GPIO191_MC4_DAT4        PIN_CFG(191, ALT_B)
-#define GPIO191_STMAPE_DAT0     PIN_CFG(191, ALT_C)
-#define GPIO192_GPIO            PIN_CFG(192, GPIO)
-#define GPIO192_MC1_DAT1        PIN_CFG(192, ALT_A)
-#define GPIO192_MC4_DAT5        PIN_CFG(192, ALT_B)
-#define GPIO192_STMAPE_DAT1     PIN_CFG(192, ALT_C)
-#define GPIO193_GPIO            PIN_CFG(193, GPIO)
-#define GPIO193_MC1_DAT2        PIN_CFG(193, ALT_A)
-#define GPIO193_MC4_DAT6        PIN_CFG(193, ALT_B)
-#define GPIO193_STMAPE_DAT2     PIN_CFG(193, ALT_C)
-#define GPIO194_GPIO            PIN_CFG(194, GPIO)
-#define GPIO194_MC1_DAT3        PIN_CFG(194, ALT_A)
-#define GPIO194_MC4_DAT7        PIN_CFG(194, ALT_B)
-#define GPIO194_STMAPE_DAT3     PIN_CFG(194, ALT_C)
-#define GPIO195_GPIO            PIN_CFG(195, GPIO)
-#define GPIO195_MC1_CLK         PIN_CFG(195, ALT_A)
-#define GPIO195_STMAPE_CLK      PIN_CFG(195, ALT_B)
-#define GPIO195_BUSMON_CLK      PIN_CFG(195, ALT_C)
-#define GPIO196_GPIO            PIN_CFG(196, GPIO)
-#define GPIO196_MC1_CMD         PIN_CFG(196, ALT_A)
-#define GPIO196_U0_RXD          PIN_CFG(196, ALT_B)
-#define GPIO196_BUSMON_D38      PIN_CFG(196, ALT_C)
-#define GPIO197_GPIO            PIN_CFG(197, GPIO)
-#define GPIO197_MC1_CMDDIR      PIN_CFG(197, ALT_A)
-#define GPIO197_BUSMON_D39      PIN_CFG(197, ALT_B)
-#define GPIO198_GPIO            PIN_CFG(198, GPIO)
-#define GPIO198_MC1_FBCLK       PIN_CFG(198, ALT_A)
-#define GPIO199_GPIO            PIN_CFG(199, GPIO)
-#define GPIO199_MC1_DAT0DIR     PIN_CFG(199, ALT_A)
-#define GPIO199_BUSMON_D40      PIN_CFG(199, ALT_B)
-#define GPIO200_GPIO            PIN_CFG(200, GPIO)
-#define GPIO200_U1_TXD          PIN_CFG(200, ALT_A)
-#define GPIO200_ACCU0_RTSn      PIN_CFG(200, ALT_B)
-#define GPIO201_GPIO            PIN_CFG(201, GPIO)
-#define GPIO201_U1_RXD          PIN_CFG(201, ALT_A)
-#define GPIO201_ACCU0_CTSn      PIN_CFG(201, ALT_B)
-#define GPIO202_GPIO            PIN_CFG(202, GPIO)
-#define GPIO202_U1_CTSn         PIN_CFG(202, ALT_A)
-#define GPIO202_ACCU0_RXD       PIN_CFG(202, ALT_B)
-#define GPIO203_GPIO            PIN_CFG(203, GPIO)
-#define GPIO203_U1_RTSn         PIN_CFG(203, ALT_A)
-#define GPIO203_ACCU0_TXD       PIN_CFG(203, ALT_B)
-#define GPIO204_GPIO            PIN_CFG(204, GPIO)
-#define GPIO204_SPI0_CS2n       PIN_CFG(204, ALT_A)
-#define GPIO204_ACCGPIO_000     PIN_CFG(204, ALT_B)
-#define GPIO204_LCD_VSI1        PIN_CFG(204, ALT_C)
-#define GPIO205_GPIO            PIN_CFG(205, GPIO)
-#define GPIO205_SPI0_CS1n       PIN_CFG(205, ALT_A)
-#define GPIO205_ACCGPIO_001     PIN_CFG(205, ALT_B)
-#define GPIO205_LCD_D3          PIN_CFG(205, ALT_C)
-#define GPIO206_GPIO            PIN_CFG(206, GPIO)
-#define GPIO206_SPI0_CS0n       PIN_CFG(206, ALT_A)
-#define GPIO206_ACCGPIO_002     PIN_CFG(206, ALT_B)
-#define GPIO206_LCD_D2          PIN_CFG(206, ALT_C)
-#define GPIO207_GPIO            PIN_CFG(207, GPIO)
-#define GPIO207_SPI0_RXD        PIN_CFG(207, ALT_A)
-#define GPIO207_ACCGPIO_003     PIN_CFG(207, ALT_B)
-#define GPIO207_LCD_D1          PIN_CFG(207, ALT_C)
-#define GPIO208_GPIO            PIN_CFG(208, GPIO)
-#define GPIO208_SPI0_TXD        PIN_CFG(208, ALT_A)
-#define GPIO208_ACCGPIO_004     PIN_CFG(208, ALT_B)
-#define GPIO208_LCD_D0          PIN_CFG(208, ALT_C)
-#define GPIO209_GPIO            PIN_CFG(209, GPIO)
-#define GPIO209_SPI0_CLK        PIN_CFG(209, ALT_A)
-#define GPIO209_ACCGPIO_005     PIN_CFG(209, ALT_B)
-#define GPIO209_LCD_CLK         PIN_CFG(209, ALT_C)
-#define GPIO210_GPIO            PIN_CFG(210, GPIO)
-#define GPIO210_LCD_VSO         PIN_CFG(210, ALT_A)
-#define GPIO210_PRCMU_PWRCTRL1  PIN_CFG(210, ALT_B)
-#define GPIO211_GPIO            PIN_CFG(211, GPIO)
-#define GPIO211_LCD_VSI0        PIN_CFG(211, ALT_A)
-#define GPIO211_PRCMU_PWRCTRL2  PIN_CFG(211, ALT_B)
-#define GPIO212_GPIO            PIN_CFG(212, GPIO)
-#define GPIO212_SPI2_CS2n       PIN_CFG(212, ALT_A)
-#define GPIO212_LCD_HSO         PIN_CFG(212, ALT_B)
-#define GPIO213_GPIO            PIN_CFG(213, GPIO)
-#define GPIO213_SPI2_CS1n       PIN_CFG(213, ALT_A)
-#define GPIO213_LCD_DE          PIN_CFG(213, ALT_B)
-#define GPIO213_BUSMON_D16      PIN_CFG(213, ALT_C)
-#define GPIO214_GPIO            PIN_CFG(214, GPIO)
-#define GPIO214_SPI2_CS0n       PIN_CFG(214, ALT_A)
-#define GPIO214_LCD_D7          PIN_CFG(214, ALT_B)
-#define GPIO214_BUSMON_D17      PIN_CFG(214, ALT_C)
-#define GPIO215_GPIO            PIN_CFG(215, GPIO)
-#define GPIO215_SPI2_RXD        PIN_CFG(215, ALT_A)
-#define GPIO215_LCD_D6          PIN_CFG(215, ALT_B)
-#define GPIO215_BUSMON_D18      PIN_CFG(215, ALT_C)
-#define GPIO216_GPIO            PIN_CFG(216, GPIO)
-#define GPIO216_SPI2_CLK        PIN_CFG(216, ALT_A)
-#define GPIO216_LCD_D5          PIN_CFG(216, ALT_B)
-#define GPIO217_GPIO            PIN_CFG(217, GPIO)
-#define GPIO217_SPI2_TXD        PIN_CFG(217, ALT_A)
-#define GPIO217_LCD_D4          PIN_CFG(217, ALT_B)
-#define GPIO217_BUSMON_D19      PIN_CFG(217, ALT_C)
-#define GPIO218_GPIO            PIN_CFG(218, GPIO)
-#define GPIO218_I2C2_SCL        PIN_CFG(218, ALT_A)
-#define GPIO218_LCD_VSO         PIN_CFG(218, ALT_B)
-#define GPIO219_GPIO            PIN_CFG(219, GPIO)
-#define GPIO219_I2C2_SDA        PIN_CFG(219, ALT_A)
-#define GPIO219_LCD_D3          PIN_CFG(219, ALT_B)
-#define GPIO220_GPIO            PIN_CFG(220, GPIO)
-#define GPIO220_MSP2_TCK        PIN_CFG(220, ALT_A)
-#define GPIO220_LCD_D2          PIN_CFG(220, ALT_B)
-#define GPIO221_GPIO            PIN_CFG(221, GPIO)
-#define GPIO221_MSP2_TFS        PIN_CFG(221, ALT_A)
-#define GPIO221_LCD_D1          PIN_CFG(221, ALT_B)
-#define GPIO222_GPIO            PIN_CFG(222, GPIO)
-#define GPIO222_MSP2_TXD        PIN_CFG(222, ALT_A)
-#define GPIO222_LCD_D0          PIN_CFG(222, ALT_B)
-#define GPIO223_GPIO            PIN_CFG(223, GPIO)
-#define GPIO223_MSP2_RXD        PIN_CFG(223, ALT_A)
-#define GPIO223_LCD_CLK         PIN_CFG(223, ALT_B)
-#define GPIO224_GPIO            PIN_CFG(224, GPIO)
-#define GPIO224_PRCMU_PWRCTRL0  PIN_CFG(224, ALT_A)
-#define GPIO224_LCD_VSI1        PIN_CFG(224, ALT_B)
-#define GPIO225_GPIO            PIN_CFG(225, GPIO)
-#define GPIO225_PRCMU_PWRCTRL1  PIN_CFG(225, ALT_A)
-#define GPIO225_IRDA_RXD        PIN_CFG(225, ALT_B)
-#define GPIO226_GPIO            PIN_CFG(226, GPIO)
-#define GPIO226_PRCMU_PWRCTRL2  PIN_CFG(226, ALT_A)
-#define GPIO226_IRRC_DAT        PIN_CFG(226, ALT_B)
-#define GPIO227_GPIO            PIN_CFG(227, GPIO)
-#define GPIO227_IRRC_DAT        PIN_CFG(227, ALT_A)
-#define GPIO227_IRDA_TXD        PIN_CFG(227, ALT_B)
-#endif
diff --git a/arch/arm/mach-ux500/pins-db8500.h b/arch/arm/mach-ux500/pins-db8500.h
index 8b1d1a7a679e..062c7acf4576 100644
--- a/arch/arm/mach-ux500/pins-db8500.h
+++ b/arch/arm/mach-ux500/pins-db8500.h
@@ -35,40 +35,40 @@
 #define GPIO4_GPIO              PIN_CFG(4, GPIO)
 #define GPIO4_U1_RXD            PIN_CFG(4, ALT_A)
-#define GPIO4_I2C4_SCL          PIN_CFG_INPUT(4, ALT_B, PULLUP)
+#define GPIO4_I2C4_SCL          PIN_CFG(4, ALT_B)
 #define GPIO4_IP_TRSTn          PIN_CFG(4, ALT_C)
 #define GPIO5_GPIO              PIN_CFG(5, GPIO)
 #define GPIO5_U1_TXD            PIN_CFG(5, ALT_A)
-#define GPIO5_I2C4_SDA          PIN_CFG_INPUT(5, ALT_B, PULLUP)
+#define GPIO5_I2C4_SDA          PIN_CFG(5, ALT_B)
 #define GPIO5_IP_GPIO6          PIN_CFG(5, ALT_C)
 #define GPIO6_GPIO              PIN_CFG(6, GPIO)
 #define GPIO6_U1_CTSn           PIN_CFG(6, ALT_A)
-#define GPIO6_I2C1_SCL          PIN_CFG_INPUT(6, ALT_B, PULLUP)
+#define GPIO6_I2C1_SCL          PIN_CFG(6, ALT_B)
 #define GPIO6_IP_GPIO0          PIN_CFG(6, ALT_C)
 #define GPIO7_GPIO              PIN_CFG(7, GPIO)
 #define GPIO7_U1_RTSn           PIN_CFG(7, ALT_A)
-#define GPIO7_I2C1_SDA          PIN_CFG_INPUT(7, ALT_B, PULLUP)
+#define GPIO7_I2C1_SDA          PIN_CFG(7, ALT_B)
 #define GPIO7_IP_GPIO1          PIN_CFG(7, ALT_C)
 #define GPIO8_GPIO              PIN_CFG(8, GPIO)
-#define GPIO8_IPI2C_SDA         PIN_CFG_INPUT(8, ALT_A, PULLUP)
+#define GPIO8_IPI2C_SDA         PIN_CFG(8, ALT_A)
-#define GPIO8_I2C2_SDA          PIN_CFG_INPUT(8, ALT_B, PULLUP)
+#define GPIO8_I2C2_SDA          PIN_CFG(8, ALT_B)
 #define GPIO9_GPIO              PIN_CFG(9, GPIO)
-#define GPIO9_IPI2C_SCL         PIN_CFG_INPUT(9, ALT_A, PULLUP)
+#define GPIO9_IPI2C_SCL         PIN_CFG(9, ALT_A)
-#define GPIO9_I2C2_SCL          PIN_CFG_INPUT(9, ALT_B, PULLUP)
+#define GPIO9_I2C2_SCL          PIN_CFG(9, ALT_B)
 #define GPIO10_GPIO             PIN_CFG(10, GPIO)
-#define GPIO10_IPI2C_SDA        PIN_CFG_INPUT(10, ALT_A, PULLUP)
+#define GPIO10_IPI2C_SDA        PIN_CFG(10, ALT_A)
-#define GPIO10_I2C2_SDA         PIN_CFG_INPUT(10, ALT_B, PULLUP)
+#define GPIO10_I2C2_SDA         PIN_CFG(10, ALT_B)
 #define GPIO10_IP_GPIO3         PIN_CFG(10, ALT_C)
 #define GPIO11_GPIO             PIN_CFG(11, GPIO)
-#define GPIO11_IPI2C_SCL        PIN_CFG_INPUT(11, ALT_A, PULLUP)
+#define GPIO11_IPI2C_SCL        PIN_CFG(11, ALT_A)
-#define GPIO11_I2C2_SCL         PIN_CFG_INPUT(11, ALT_B, PULLUP)
+#define GPIO11_I2C2_SCL         PIN_CFG(11, ALT_B)
 #define GPIO11_IP_GPIO2         PIN_CFG(11, ALT_C)
 #define GPIO12_GPIO             PIN_CFG(12, GPIO)
@@ -87,12 +87,12 @@
 #define GPIO16_GPIO             PIN_CFG(16, GPIO)
 #define GPIO16_MSP0_RFS         PIN_CFG(16, ALT_A)
-#define GPIO16_I2C1_SCL         PIN_CFG_INPUT(16, ALT_B, PULLUP)
+#define GPIO16_I2C1_SCL         PIN_CFG(16, ALT_B)
 #define GPIO16_SLIM0_DAT        PIN_CFG(16, ALT_C)
 #define GPIO17_GPIO             PIN_CFG(17, GPIO)
 #define GPIO17_MSP0_RCK         PIN_CFG(17, ALT_A)
-#define GPIO17_I2C1_SDA         PIN_CFG_INPUT(17, ALT_B, PULLUP)
+#define GPIO17_I2C1_SDA         PIN_CFG(17, ALT_B)
 #define GPIO17_SLIM0_CLK        PIN_CFG(17, ALT_C)
 #define GPIO18_GPIO             PIN_CFG(18, GPIO)
@@ -434,10 +434,10 @@
 #define GPIO146_SSP0_TXD        PIN_CFG(146, ALT_A)
 #define GPIO147_GPIO            PIN_CFG(147, GPIO)
-#define GPIO147_I2C0_SCL        PIN_CFG_INPUT(147, ALT_A, PULLUP)
+#define GPIO147_I2C0_SCL        PIN_CFG(147, ALT_A)
 #define GPIO148_GPIO            PIN_CFG(148, GPIO)
-#define GPIO148_I2C0_SDA        PIN_CFG_INPUT(148, ALT_A, PULLUP)
+#define GPIO148_I2C0_SDA        PIN_CFG(148, ALT_A)
 #define GPIO149_GPIO            PIN_CFG(149, GPIO)
 #define GPIO149_IP_GPIO0        PIN_CFG(149, ALT_A)
@@ -459,82 +459,82 @@
 #define GPIO152_KP_O9           PIN_CFG(152, ALT_C)
 #define GPIO153_GPIO            PIN_CFG(153, GPIO)
-#define GPIO153_KP_I7           PIN_CFG_INPUT(153, ALT_A, PULLDOWN)
+#define GPIO153_KP_I7           PIN_CFG(153, ALT_A)
 #define GPIO153_LCD_D24         PIN_CFG(153, ALT_B)
 #define GPIO153_U2_RXD          PIN_CFG(153, ALT_C)
 #define GPIO154_GPIO            PIN_CFG(154, GPIO)
-#define GPIO154_KP_I6           PIN_CFG_INPUT(154, ALT_A, PULLDOWN)
+#define GPIO154_KP_I6           PIN_CFG(154, ALT_A)
 #define GPIO154_LCD_D25         PIN_CFG(154, ALT_B)
 #define GPIO154_U2_TXD          PIN_CFG(154, ALT_C)
 #define GPIO155_GPIO            PIN_CFG(155, GPIO)
-#define GPIO155_KP_I5           PIN_CFG_INPUT(155, ALT_A, PULLDOWN)
+#define GPIO155_KP_I5           PIN_CFG(155, ALT_A)
 #define GPIO155_LCD_D26         PIN_CFG(155, ALT_B)
 #define GPIO155_STMAPE_CLK      PIN_CFG(155, ALT_C)
 #define GPIO156_GPIO            PIN_CFG(156, GPIO)
-#define GPIO156_KP_I4           PIN_CFG_INPUT(156, ALT_A, PULLDOWN)
+#define GPIO156_KP_I4           PIN_CFG(156, ALT_A)
 #define GPIO156_LCD_D27         PIN_CFG(156, ALT_B)
 #define GPIO156_STMAPE_DAT3     PIN_CFG(156, ALT_C)
 #define GPIO157_GPIO            PIN_CFG(157, GPIO)
-#define GPIO157_KP_O7           PIN_CFG_INPUT(157, ALT_A, PULLUP)
+#define GPIO157_KP_O7           PIN_CFG(157, ALT_A)
 #define GPIO157_LCD_D28         PIN_CFG(157, ALT_B)
 #define GPIO157_STMAPE_DAT2     PIN_CFG(157, ALT_C)
 #define GPIO158_GPIO            PIN_CFG(158, GPIO)
-#define GPIO158_KP_O6           PIN_CFG_INPUT(158, ALT_A, PULLUP)
+#define GPIO158_KP_O6           PIN_CFG(158, ALT_A)
 #define GPIO158_LCD_D29         PIN_CFG(158, ALT_B)
 #define GPIO158_STMAPE_DAT1     PIN_CFG(158, ALT_C)
 #define GPIO159_GPIO            PIN_CFG(159, GPIO)
-#define GPIO159_KP_O5           PIN_CFG_INPUT(159, ALT_A, PULLUP)
+#define GPIO159_KP_O5           PIN_CFG(159, ALT_A)
 #define GPIO159_LCD_D30         PIN_CFG(159, ALT_B)
 #define GPIO159_STMAPE_DAT0     PIN_CFG(159, ALT_C)
 #define GPIO160_GPIO            PIN_CFG(160, GPIO)
-#define GPIO160_KP_O4           PIN_CFG_INPUT(160, ALT_A, PULLUP)
+#define GPIO160_KP_O4           PIN_CFG(160, ALT_A)
 #define GPIO160_LCD_D31         PIN_CFG(160, ALT_B)
 #define GPIO160_NONE            PIN_CFG(160, ALT_C)
 #define GPIO161_GPIO            PIN_CFG(161, GPIO)
-#define GPIO161_KP_I3           PIN_CFG_INPUT(161, ALT_A, PULLDOWN)
+#define GPIO161_KP_I3           PIN_CFG(161, ALT_A)
 #define GPIO161_LCD_D32         PIN_CFG(161, ALT_B)
 #define GPIO161_UARTMOD_RXD     PIN_CFG(161, ALT_C)
 #define GPIO162_GPIO            PIN_CFG(162, GPIO)
-#define GPIO162_KP_I2           PIN_CFG_INPUT(162, ALT_A, PULLDOWN)
+#define GPIO162_KP_I2           PIN_CFG(162, ALT_A)
 #define GPIO162_LCD_D33         PIN_CFG(162, ALT_B)
 #define GPIO162_UARTMOD_TXD     PIN_CFG(162, ALT_C)
 #define GPIO163_GPIO            PIN_CFG(163, GPIO)
-#define GPIO163_KP_I1           PIN_CFG_INPUT(163, ALT_A, PULLDOWN)
+#define GPIO163_KP_I1           PIN_CFG(163, ALT_A)
 #define GPIO163_LCD_D34         PIN_CFG(163, ALT_B)
 #define GPIO163_STMMOD_CLK      PIN_CFG(163, ALT_C)
 #define GPIO164_GPIO            PIN_CFG(164, GPIO)
-#define GPIO164_KP_I0           PIN_CFG_INPUT(164, ALT_A, PULLUP)
+#define GPIO164_KP_I0           PIN_CFG(164, ALT_A)
 #define GPIO164_LCD_D35         PIN_CFG(164, ALT_B)
 #define GPIO164_STMMOD_DAT3     PIN_CFG(164, ALT_C)
 #define GPIO165_GPIO            PIN_CFG(165, GPIO)
-#define GPIO165_KP_O3           PIN_CFG_INPUT(165, ALT_A, PULLUP)
+#define GPIO165_KP_O3           PIN_CFG(165, ALT_A)
 #define GPIO165_LCD_D36         PIN_CFG(165, ALT_B)
 #define GPIO165_STMMOD_DAT2     PIN_CFG(165, ALT_C)
 #define GPIO166_GPIO            PIN_CFG(166, GPIO)
-#define GPIO166_KP_O2           PIN_CFG_INPUT(166, ALT_A, PULLUP)
+#define GPIO166_KP_O2           PIN_CFG(166, ALT_A)
 #define GPIO166_LCD_D37         PIN_CFG(166, ALT_B)
 #define GPIO166_STMMOD_DAT1     PIN_CFG(166, ALT_C)
 #define GPIO167_GPIO            PIN_CFG(167, GPIO)
-#define GPIO167_KP_O1           PIN_CFG_INPUT(167, ALT_A, PULLUP)
+#define GPIO167_KP_O1           PIN_CFG(167, ALT_A)
 #define GPIO167_LCD_D38         PIN_CFG(167, ALT_B)
 #define GPIO167_STMMOD_DAT0     PIN_CFG(167, ALT_C)
 #define GPIO168_GPIO            PIN_CFG(168, GPIO)
-#define GPIO168_KP_O0           PIN_CFG_INPUT(168, ALT_A, PULLUP)
+#define GPIO168_KP_O0           PIN_CFG(168, ALT_A)
 #define GPIO168_LCD_D39         PIN_CFG(168, ALT_B)
 #define GPIO168_NONE            PIN_CFG(168, ALT_C)
@@ -637,7 +637,7 @@
 #define GPIO216_GPIO            PIN_CFG(216, GPIO)
 #define GPIO216_MC1_DAT2DIR     PIN_CFG(216, ALT_A)
 #define GPIO216_MC3_CMDDIR      PIN_CFG(216, ALT_B)
-#define GPIO216_I2C3_SDA        PIN_CFG_INPUT(216, ALT_C, PULLUP)
+#define GPIO216_I2C3_SDA        PIN_CFG(216, ALT_C)
 #define GPIO216_SPI2_FRM        PIN_CFG(216, ALT_C)
 #define GPIO217_GPIO            PIN_CFG(217, GPIO)
@@ -649,7 +649,7 @@
 #define GPIO218_GPIO            PIN_CFG(218, GPIO)
 #define GPIO218_MC1_DAT31DIR    PIN_CFG(218, ALT_A)
 #define GPIO218_MC3_DAT0DIR     PIN_CFG(218, ALT_B)
-#define GPIO218_I2C3_SCL        PIN_CFG_INPUT(218, ALT_C, PULLUP)
+#define GPIO218_I2C3_SCL        PIN_CFG(218, ALT_C)
 #define GPIO218_SPI2_RXD        PIN_CFG(218, ALT_C)
 #define GPIO219_GPIO            PIN_CFG(219, GPIO)
@@ -698,12 +698,12 @@
 #define GPIO229_GPIO            PIN_CFG(229, GPIO)
 #define GPIO229_CLKOUT1         PIN_CFG(229, ALT_A)
 #define GPIO229_PWL             PIN_CFG(229, ALT_B)
-#define GPIO229_I2C3_SDA        PIN_CFG_INPUT(229, ALT_C, PULLUP)
+#define GPIO229_I2C3_SDA        PIN_CFG(229, ALT_C)
 #define GPIO230_GPIO            PIN_CFG(230, GPIO)
 #define GPIO230_CLKOUT2         PIN_CFG(230, ALT_A)
 #define GPIO230_PWL             PIN_CFG(230, ALT_B)
-#define GPIO230_I2C3_SCL        PIN_CFG_INPUT(230, ALT_C, PULLUP)
+#define GPIO230_I2C3_SCL        PIN_CFG(230, ALT_C)
 #define GPIO256_GPIO            PIN_CFG(256, GPIO)
 #define GPIO256_USB_NXT         PIN_CFG(256, ALT_A)
diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c
index d2058ef8345f..da1d5ad5bd45 100644
--- a/arch/arm/mach-ux500/platsmp.c
+++ b/arch/arm/mach-ux500/platsmp.c
@@ -48,9 +48,7 @@ static void write_pen_release(int val)
 static void __iomem *scu_base_addr(void)
 {
-        if (cpu_is_u5500())
+        if (cpu_is_u8500_family())
-                return __io_address(U5500_SCU_BASE);
-        else if (cpu_is_u8500())
                return __io_address(U8500_SCU_BASE);
        else
                ux500_unknown_soc();
@@ -99,7 +97,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
         */
        write_pen_release(cpu_logical_map(cpu));
-        gic_raise_softirq(cpumask_of(cpu), 1);
+        smp_send_reschedule(cpu);
        timeout = jiffies + (1 * HZ);
        while (time_before(jiffies, timeout)) {
@@ -120,9 +118,7 @@ static void __init wakeup_secondary(void)
 {
        void __iomem *backupram;
-        if (cpu_is_u5500())
+        if (cpu_is_u8500_family())
-                backupram = __io_address(U5500_BACKUPRAM0_BASE);
-        else if (cpu_is_u8500())
                backupram = __io_address(U8500_BACKUPRAM0_BASE);
        else
                ux500_unknown_soc();
diff --git a/arch/arm/mach-ux500/ste-dma40-db5500.h b/arch/arm/mach-ux500/ste-dma40-db5500.h
deleted file mode 100644
index cb2110c32858..000000000000
--- a/arch/arm/mach-ux500/ste-dma40-db5500.h
+++ /dev/null
@@ -1,135 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2010
- *
- * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
- * License terms: GNU General Public License (GPL) version 2
- *
- * DB5500-SoC-specific configuration for DMA40
- */
-#ifndef STE_DMA40_DB5500_H
-#define STE_DMA40_DB5500_H
-#define DB5500_DMA_NR_DEV 64
-enum dma_src_dev_type {
-        DB5500_DMA_DEV0_SPI0_RX = 0,
-        DB5500_DMA_DEV1_SPI1_RX = 1,
-        DB5500_DMA_DEV2_SPI2_RX = 2,
-        DB5500_DMA_DEV3_SPI3_RX = 3,
-        DB5500_DMA_DEV4_USB_OTG_IEP_1_9 = 4,
-        DB5500_DMA_DEV5_USB_OTG_IEP_2_10 = 5,
-        DB5500_DMA_DEV6_USB_OTG_IEP_3_11 = 6,
-        DB5500_DMA_DEV7_IRDA_RFS = 7,
-        DB5500_DMA_DEV8_IRDA_FIFO_RX = 8,
-        DB5500_DMA_DEV9_MSP0_RX = 9,
-        DB5500_DMA_DEV10_MSP1_RX = 10,
-        DB5500_DMA_DEV11_MSP2_RX = 11,
-        DB5500_DMA_DEV12_UART0_RX = 12,
-        DB5500_DMA_DEV13_UART1_RX = 13,
-        DB5500_DMA_DEV14_UART2_RX = 14,
-        DB5500_DMA_DEV15_UART3_RX = 15,
-        DB5500_DMA_DEV16_USB_OTG_IEP_8 = 16,
-        DB5500_DMA_DEV17_USB_OTG_IEP_1_9 = 17,
-        DB5500_DMA_DEV18_USB_OTG_IEP_2_10 = 18,
-        DB5500_DMA_DEV19_USB_OTG_IEP_3_11 = 19,
-        DB5500_DMA_DEV20_USB_OTG_IEP_4_12 = 20,
-        DB5500_DMA_DEV21_USB_OTG_IEP_5_13 = 21,
-        DB5500_DMA_DEV22_USB_OTG_IEP_6_14 = 22,
-        DB5500_DMA_DEV23_USB_OTG_IEP_7_15 = 23,
-        DB5500_DMA_DEV24_SDMMC0_RX = 24,
-        DB5500_DMA_DEV25_SDMMC1_RX = 25,
-        DB5500_DMA_DEV26_SDMMC2_RX = 26,
-        DB5500_DMA_DEV27_SDMMC3_RX = 27,
-        DB5500_DMA_DEV28_SDMMC4_RX = 28,
-        /* 29 - 32 not used */
-        DB5500_DMA_DEV33_SDMMC0_RX = 33,
-        DB5500_DMA_DEV34_SDMMC1_RX = 34,
-        DB5500_DMA_DEV35_SDMMC2_RX = 35,
-        DB5500_DMA_DEV36_SDMMC3_RX = 36,
-        DB5500_DMA_DEV37_SDMMC4_RX = 37,
-        DB5500_DMA_DEV38_USB_OTG_IEP_8 = 38,
-        DB5500_DMA_DEV39_USB_OTG_IEP_1_9 = 39,
-        DB5500_DMA_DEV40_USB_OTG_IEP_2_10 = 40,
-        DB5500_DMA_DEV41_USB_OTG_IEP_3_11 = 41,
-        DB5500_DMA_DEV42_USB_OTG_IEP_4_12 = 42,
-        DB5500_DMA_DEV43_USB_OTG_IEP_5_13 = 43,
-        DB5500_DMA_DEV44_USB_OTG_IEP_6_14 = 44,
-        DB5500_DMA_DEV45_USB_OTG_IEP_7_15 = 45,
-        /* 46 not used */
-        DB5500_DMA_DEV47_MCDE_RX = 47,
-        DB5500_DMA_DEV48_CRYPTO1_RX = 48,
-        /* 49, 50 not used */
-        DB5500_DMA_DEV49_I2C1_RX = 51,
-        DB5500_DMA_DEV50_I2C3_RX = 52,
-        DB5500_DMA_DEV51_I2C2_RX = 53,
-        /* 54 - 60 not used */
-        DB5500_DMA_DEV61_CRYPTO0_RX = 61,
-        /* 62, 63 not used */
-};
-enum dma_dest_dev_type {
-        DB5500_DMA_DEV0_SPI0_TX = 0,
-        DB5500_DMA_DEV1_SPI1_TX = 1,
-        DB5500_DMA_DEV2_SPI2_TX = 2,
-        DB5500_DMA_DEV3_SPI3_TX = 3,
-        DB5500_DMA_DEV4_USB_OTG_OEP_1_9 = 4,
-        DB5500_DMA_DEV5_USB_OTG_OEP_2_10 = 5,
-        DB5500_DMA_DEV6_USB_OTG_OEP_3_11 = 6,
-        DB5500_DMA_DEV7_IRRC_TX = 7,
-        DB5500_DMA_DEV8_IRDA_FIFO_TX = 8,
-        DB5500_DMA_DEV9_MSP0_TX = 9,
-        DB5500_DMA_DEV10_MSP1_TX = 10,
-        DB5500_DMA_DEV11_MSP2_TX = 11,
-        DB5500_DMA_DEV12_UART0_TX = 12,
-        DB5500_DMA_DEV13_UART1_TX = 13,
-        DB5500_DMA_DEV14_UART2_TX = 14,
-        DB5500_DMA_DEV15_UART3_TX = 15,
-        DB5500_DMA_DEV16_USB_OTG_OEP_8 = 16,
-        DB5500_DMA_DEV17_USB_OTG_OEP_1_9 = 17,
-        DB5500_DMA_DEV18_USB_OTG_OEP_2_10 = 18,
-        DB5500_DMA_DEV19_USB_OTG_OEP_3_11 = 19,
-        DB5500_DMA_DEV20_USB_OTG_OEP_4_12 = 20,
-        DB5500_DMA_DEV21_USB_OTG_OEP_5_13 = 21,
-        DB5500_DMA_DEV22_USB_OTG_OEP_6_14 = 22,
-        DB5500_DMA_DEV23_USB_OTG_OEP_7_15 = 23,
-        DB5500_DMA_DEV24_SDMMC0_TX = 24,
-        DB5500_DMA_DEV25_SDMMC1_TX = 25,
-        DB5500_DMA_DEV26_SDMMC2_TX = 26,
-        DB5500_DMA_DEV27_SDMMC3_TX = 27,
-        DB5500_DMA_DEV28_SDMMC4_TX = 28,
-        /* 29 - 31 not used */
-        DB5500_DMA_DEV32_FSMC_TX = 32,
-        DB5500_DMA_DEV33_SDMMC0_TX = 33,
-        DB5500_DMA_DEV34_SDMMC1_TX = 34,
-        DB5500_DMA_DEV35_SDMMC2_TX = 35,
-        DB5500_DMA_DEV36_SDMMC3_TX = 36,
-        DB5500_DMA_DEV37_SDMMC4_TX = 37,
-        DB5500_DMA_DEV38_USB_OTG_OEP_8 = 38,
-        DB5500_DMA_DEV39_USB_OTG_OEP_1_9 = 39,
-        DB5500_DMA_DEV40_USB_OTG_OEP_2_10 = 40,
-        DB5500_DMA_DEV41_USB_OTG_OEP_3_11 = 41,
-        DB5500_DMA_DEV42_USB_OTG_OEP_4_12 = 42,
-        DB5500_DMA_DEV43_USB_OTG_OEP_5_13 = 43,
-        DB5500_DMA_DEV44_USB_OTG_OEP_6_14 = 44,
-        DB5500_DMA_DEV45_USB_OTG_OEP_7_15 = 45,
-        /* 46 not used */
-        DB5500_DMA_DEV47_STM_TX = 47,
-        DB5500_DMA_DEV48_CRYPTO1_TX = 48,
-        DB5500_DMA_DEV49_CRYPTO1_TX_HASH1_TX = 49,
-        DB5500_DMA_DEV50_HASH1_TX = 50,
-        DB5500_DMA_DEV51_I2C1_TX = 51,
-        DB5500_DMA_DEV52_I2C3_TX = 52,
-        DB5500_DMA_DEV53_I2C2_TX = 53,
-        /* 54, 55 not used */
-        DB5500_DMA_MEMCPY_TX_1 = 56,
-        DB5500_DMA_MEMCPY_TX_2 = 57,
-        DB5500_DMA_MEMCPY_TX_3 = 58,
-        DB5500_DMA_MEMCPY_TX_4 = 59,
-        DB5500_DMA_MEMCPY_TX_5 = 60,
-        DB5500_DMA_DEV61_CRYPTO0_TX = 61,
-        DB5500_DMA_DEV62_CRYPTO0_TX_HASH0_TX = 62,
-        DB5500_DMA_DEV63_HASH0_TX = 63,
-};
-#endif
diff --git a/arch/arm/mach-ux500/timer.c b/arch/arm/mach-ux500/timer.c
index d37df98b5c32..741e71feca78 100644
--- a/arch/arm/mach-ux500/timer.c
+++ b/arch/arm/mach-ux500/timer.c
@@ -8,6 +8,7 @@
 #include <linux/errno.h>
 #include <linux/clksrc-dbx500-prcmu.h>
 #include <linux/of.h>
+#include <linux/of_address.h>
 #include <asm/smp_twd.h>
@@ -18,8 +19,6 @@
 #include <mach/irqs.h>
 #ifdef CONFIG_HAVE_ARM_TWD
-static DEFINE_TWD_LOCAL_TIMER(u5500_twd_local_timer,
-                              U5500_TWD_BASE, IRQ_LOCALTIMER);
 static DEFINE_TWD_LOCAL_TIMER(u8500_twd_local_timer,
                              U8500_TWD_BASE, IRQ_LOCALTIMER);
@@ -28,8 +27,8 @@ static void __init ux500_twd_init(void)
        struct twd_local_timer *twd_local_timer;
        int err;
-        twd_local_timer = cpu_is_u5500() ? &u5500_twd_local_timer :
+        /* Use this to switch local timer base if changed in new ASICs */
-                                           &u8500_twd_local_timer;
+        twd_local_timer = &u8500_twd_local_timer;
        if (of_have_populated_dt())
                twd_local_timer_of_register();
@@ -43,21 +42,41 @@ static void __init ux500_twd_init(void)
 #define ux500_twd_init()        do { } while(0)
 #endif
+const static struct of_device_id prcmu_timer_of_match[] __initconst = {
+        { .compatible = "stericsson,db8500-prcmu-timer-4", },
+        { },
+};
 static void __init ux500_timer_init(void)
 {
        void __iomem *mtu_timer_base;
        void __iomem *prcmu_timer_base;
+        void __iomem *tmp_base;
+        struct device_node *np;
-        if (cpu_is_u5500()) {
+        if (cpu_is_u8500_family()) {
-                mtu_timer_base = __io_address(U5500_MTU0_BASE);
-                prcmu_timer_base = __io_address(U5500_PRCMU_TIMER_3_BASE);
-        } else if (cpu_is_u8500()) {
                mtu_timer_base = __io_address(U8500_MTU0_BASE);
                prcmu_timer_base = __io_address(U8500_PRCMU_TIMER_4_BASE);
        } else {
                ux500_unknown_soc();
        }
+        /* TODO: Once MTU has been DT:ed place code above into else. */
+        if (of_have_populated_dt()) {
+                np = of_find_matching_node(NULL, prcmu_timer_of_match);
+                if (!np)
+                        goto dt_fail;
+                tmp_base = of_iomap(np, 0);
+                if (!tmp_base)
+                        goto dt_fail;
+                prcmu_timer_base = tmp_base;
+        }
+dt_fail:
+        /* Doing it the old fashioned way. */
        /*
         * Here we register the timerblocks active in the system.
         * Localtimers (twd) is started when both cpu is up and running.
@@ -70,7 +89,7 @@ static void __init ux500_timer_init(void)
         * depending on delay which is not yet calibrated. RTC-RTT is in the
         * always-on powerdomain and is used as clockevent instead of twd when
         * sleeping.
-         * The PRCMU timer 4(3 for DB5500) register a clocksource and
+         * The PRCMU timer 4 register a clocksource and
         * sched_clock with higher rating then MTU since is always-on.
         *
         */
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index 6bbd74e950ab..cf4687ee2a7b 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -66,12 +66,6 @@
 #define VA_VIC_BASE             __io_address(VERSATILE_VIC_BASE)
 #define VA_SIC_BASE             __io_address(VERSATILE_SIC_BASE)
-static struct fpga_irq_data sic_irq = {
-        .base           = VA_SIC_BASE,
-        .irq_start      = IRQ_SIC_START,
-        .chip.name      = "SIC",
-};
 #if 1
 #define IRQ_MMCI0A      IRQ_VICSOURCE22
 #define IRQ_AACI        IRQ_VICSOURCE24
@@ -105,8 +99,11 @@ void __init versatile_init_irq(void)
        writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
-        fpga_irq_init(IRQ_VICSOURCE31, ~PIC_MASK, &sic_irq);
+        np = of_find_matching_node_by_address(NULL, sic_of_match,
-        irq_domain_generate_simple(sic_of_match, VERSATILE_SIC_BASE, IRQ_SIC_START);
+                                              VERSATILE_SIC_BASE);
+        fpga_irq_init(VA_SIC_BASE, "SIC", IRQ_SIC_START,
+                IRQ_VICSOURCE31, ~PIC_MASK, np);
        /*
         * Interrupts on secondary controller from 0 to 8 are routed to
@@ -666,17 +663,18 @@ static struct amba_device *amba_devs[] __initdata = {
 * having a specific name.
 */
 struct of_dev_auxdata versatile_auxdata_lookup[] __initdata = {
-        OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI0_BASE, "fpga:05", NULL),
+        OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI0_BASE, "fpga:05", &mmc0_plat_data),
        OF_DEV_AUXDATA("arm,primecell", VERSATILE_KMI0_BASE, "fpga:06", NULL),
        OF_DEV_AUXDATA("arm,primecell", VERSATILE_KMI1_BASE, "fpga:07", NULL),
        OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART3_BASE, "fpga:09", NULL),
+        /* FIXME: this is buggy, the platform data is needed for this MMC instance too */
        OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI1_BASE, "fpga:0b", NULL),
        OF_DEV_AUXDATA("arm,primecell", VERSATILE_CLCD_BASE, "dev:20", &clcd_plat_data),
        OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART0_BASE, "dev:f1", NULL),
        OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART1_BASE, "dev:f2", NULL),
        OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART2_BASE, "dev:f3", NULL),
-        OF_DEV_AUXDATA("arm,primecell", VERSATILE_SSP_BASE, "dev:f4", NULL),
+        OF_DEV_AUXDATA("arm,primecell", VERSATILE_SSP_BASE, "dev:f4", &ssp0_plat_data),
 #if 0
        /*
diff --git a/arch/arm/mach-versatile/pci.c b/arch/arm/mach-versatile/pci.c
index d2268be8c34c..15c6a00000ec 100644
--- a/arch/arm/mach-versatile/pci.c
+++ b/arch/arm/mach-versatile/pci.c
@@ -303,12 +303,6 @@ int __init pci_versatile_setup(int nr, struct pci_sys_data *sys)
 }
-struct pci_bus * __init pci_versatile_scan_bus(int nr, struct pci_sys_data *sys)
-{
-        return pci_scan_root_bus(NULL, sys->busnr, &pci_versatile_ops, sys,
-                                 &sys->resources);
-}
 void __init pci_versatile_preinit(void)
 {
        pcibios_min_io = 0x44000000;
@@ -339,19 +333,16 @@ static int __init versatile_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
         *  26     1     29
         *  27     1     30
         */
-        irq = 27 + ((slot + pin - 1) & 3);
+        irq = 27 + ((slot - 24 + pin - 1) & 3);
-        printk("PCI map irq: slot %d, pin %d, devslot %d, irq: %d\n",slot,pin,devslot,irq);
        return irq;
 }
 static struct hw_pci versatile_pci __initdata = {
-        .swizzle                = NULL,
        .map_irq                = versatile_map_irq,
        .nr_controllers         = 1,
+        .ops                    = &pci_versatile_ops,
        .setup                  = pci_versatile_setup,
-        .scan                   = pci_versatile_scan_bus,
        .preinit                = pci_versatile_preinit,
 };
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index 47cdcca5a7e7..04dd092211b8 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -19,8 +19,10 @@
 #include <linux/clkdev.h>
 #include <linux/mtd/physmap.h>
+#include <asm/arch_timer.h>
 #include <asm/mach-types.h>
 #include <asm/sizes.h>
+#include <asm/smp_twd.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
@@ -616,7 +618,6 @@ void __init v2m_dt_init_early(void)
        }
        clkdev_add_table(v2m_dt_lookups, ARRAY_SIZE(v2m_dt_lookups));
-        versatile_sched_clock_init(v2m_sysreg_base + V2M_SYS_24MHZ, 24000000);
 }
 static  struct of_device_id vexpress_irq_match[] __initdata = {
@@ -643,6 +644,11 @@ static void __init v2m_dt_timer_init(void)
                return;
        node = of_find_node_by_path(path);
        v2m_sp804_init(of_iomap(node, 0), irq_of_parse_and_map(node, 0));
+        if (arch_timer_of_register() != 0)
+                twd_local_timer_of_register();
+        if (arch_timer_sched_clock_init() != 0)
+                versatile_sched_clock_init(v2m_sysreg_base + V2M_SYS_24MHZ, 24000000);
 }
 static struct sys_timer v2m_dt_timer = {
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 7edef9121632..101b9681c08c 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -4,23 +4,6 @@ comment "Processor Type"
 # which CPUs we support in the kernel image, and the compiler instruction
 # optimiser behaviour.
-# ARM610
-config CPU_ARM610
-        bool "Support ARM610 processor" if ARCH_RPC
-        select CPU_32v3
-        select CPU_CACHE_V3
-        select CPU_CACHE_VIVT
-        select CPU_CP15_MMU
-        select CPU_COPY_V3 if MMU
-        select CPU_TLB_V3 if MMU
-        select CPU_PABRT_LEGACY
-        help
-          The ARM610 is the successor to the ARM3 processor
-          and was produced by VLSI Technology Inc.
-          Say Y if you want support for the ARM610 processor.
-          Otherwise, say N.
 # ARM7TDMI
 config CPU_ARM7TDMI
        bool "Support ARM7TDMI processor"
@@ -36,25 +19,6 @@ config CPU_ARM7TDMI
          Say Y if you want support for the ARM7TDMI processor.
          Otherwise, say N.
-# ARM710
-config CPU_ARM710
-        bool "Support ARM710 processor" if ARCH_RPC
-        select CPU_32v3
-        select CPU_CACHE_V3
-        select CPU_CACHE_VIVT
-        select CPU_CP15_MMU
-        select CPU_COPY_V3 if MMU
-        select CPU_TLB_V3 if MMU
-        select CPU_PABRT_LEGACY
-        help
-          A 32-bit RISC microprocessor based on the ARM7 processor core
-          designed by Advanced RISC Machines Ltd. The ARM710 is the
-          successor to the ARM610 processor. It was released in
-          July 1994 by VLSI Technology Inc.
-          Say Y if you want support for the ARM710 processor.
-          Otherwise, say N.
 # ARM720T
 config CPU_ARM720T
        bool "Support ARM720T processor" if ARCH_INTEGRATOR
@@ -530,9 +494,6 @@ config CPU_CACHE_FA
 if MMU
 # The copy-page model
-config CPU_COPY_V3
-        bool
 config CPU_COPY_V4WT
        bool
@@ -549,11 +510,6 @@ config CPU_COPY_V6
        bool
 # This selects the TLB model
-config CPU_TLB_V3
-        bool
-        help
-          ARM Architecture Version 3 TLB.
 config CPU_TLB_V4WT
        bool
        help
@@ -723,7 +679,7 @@ config CPU_HIGH_VECTOR
        bool "Select the High exception vector"
        help
          Say Y here to select high exception vector(0xFFFF0000~).
-          The exception vector can be vary depending on the platform
+          The exception vector can vary depending on the platform
          design in nommu mode. If your platform needs to select
          high exception vector, say Y.
          Otherwise or if you are unsure, say N, and the low exception
@@ -731,7 +687,7 @@ config CPU_HIGH_VECTOR
 config CPU_ICACHE_DISABLE
        bool "Disable I-Cache (I-bit)"
-        depends on CPU_CP15 && !(CPU_ARM610 || CPU_ARM710 || CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)
+        depends on CPU_CP15 && !(CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)
        help
          Say Y here to disable the processor instruction cache. Unless
          you have a reason not to or are unsure, say N.
diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile
index bca7e61928c7..8a9c4cb50a93 100644
--- a/arch/arm/mm/Makefile
+++ b/arch/arm/mm/Makefile
@@ -44,7 +44,6 @@ obj-$(CONFIG_CPU_CACHE_FA)	+= cache-fa.o
 AFLAGS_cache-v6.o       :=-Wa,-march=armv6
 AFLAGS_cache-v7.o       :=-Wa,-march=armv7-a
-obj-$(CONFIG_CPU_COPY_V3)       += copypage-v3.o
 obj-$(CONFIG_CPU_COPY_V4WT)     += copypage-v4wt.o
 obj-$(CONFIG_CPU_COPY_V4WB)     += copypage-v4wb.o
 obj-$(CONFIG_CPU_COPY_FEROCEON) += copypage-feroceon.o
@@ -54,7 +53,6 @@ obj-$(CONFIG_CPU_XSCALE)	+= copypage-xscale.o
 obj-$(CONFIG_CPU_XSC3)          += copypage-xsc3.o
 obj-$(CONFIG_CPU_COPY_FA)       += copypage-fa.o
-obj-$(CONFIG_CPU_TLB_V3)        += tlb-v3.o
 obj-$(CONFIG_CPU_TLB_V4WT)      += tlb-v4.o
 obj-$(CONFIG_CPU_TLB_V4WB)      += tlb-v4wb.o
 obj-$(CONFIG_CPU_TLB_V4WBI)     += tlb-v4wbi.o
@@ -66,8 +64,6 @@ obj-$(CONFIG_CPU_TLB_FA)	+= tlb-fa.o
 AFLAGS_tlb-v6.o         :=-Wa,-march=armv6
 AFLAGS_tlb-v7.o         :=-Wa,-march=armv7-a
-obj-$(CONFIG_CPU_ARM610)        += proc-arm6_7.o
-obj-$(CONFIG_CPU_ARM710)        += proc-arm6_7.o
 obj-$(CONFIG_CPU_ARM7TDMI)      += proc-arm7tdmi.o
 obj-$(CONFIG_CPU_ARM720T)       += proc-arm720.o
 obj-$(CONFIG_CPU_ARM740T)       += proc-arm740.o
diff --git a/arch/arm/mm/abort-ev6.S b/arch/arm/mm/abort-ev6.S
index ff1f7cc11f87..80741992a9fc 100644
--- a/arch/arm/mm/abort-ev6.S
+++ b/arch/arm/mm/abort-ev6.S
@@ -26,18 +26,23 @@ ENTRY(v6_early_abort)
        mrc     p15, 0, r1, c5, c0, 0           @ get FSR
        mrc     p15, 0, r0, c6, c0, 0           @ get FAR
 /*
- * Faulty SWP instruction on 1136 doesn't set bit 11 in DFSR (erratum 326103).
+ * Faulty SWP instruction on 1136 doesn't set bit 11 in DFSR.
- * The test below covers all the write situations, including Java bytecodes
 */
-        bic     r1, r1, #1 << 11                @ clear bit 11 of FSR
+#ifdef CONFIG_ARM_ERRATA_326103
+        ldr     ip, =0x4107b36
+        mrc     p15, 0, r3, c0, c0, 0           @ get processor id
+        teq     ip, r3, lsr #4                  @ r0 ARM1136?
+        bne     do_DataAbort
        tst     r5, #PSR_J_BIT                  @ Java?
+        tsteq   r5, #PSR_T_BIT                  @ Thumb?
        bne     do_DataAbort
-        do_thumb_abort fsr=r1, pc=r4, psr=r5, tmp=r3
+        bic     r1, r1, #1 << 11                @ clear bit 11 of FSR
-        ldreq   r3, [r4]                        @ read aborted ARM instruction
+        ldr     r3, [r4]                        @ read aborted ARM instruction
 #ifdef CONFIG_CPU_ENDIAN_BE8
-        reveq   r3, r3
+        rev     r3, r3
 #endif
        do_ldrd_abort tmp=ip, insn=r3
        tst     r3, #1 << 20                    @ L = 0 -> write
        orreq   r1, r1, #1 << 11                @ yes.
+#endif
        b       do_DataAbort
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index a53fd2aaa2f4..2a8e380501e8 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -32,6 +32,7 @@ static void __iomem *l2x0_base;
 static DEFINE_RAW_SPINLOCK(l2x0_lock);
 static u32 l2x0_way_mask;       /* Bitmask of active ways */
 static u32 l2x0_size;
+static unsigned long sync_reg_offset = L2X0_CACHE_SYNC;
 struct l2x0_regs l2x0_saved_regs;
@@ -61,12 +62,7 @@ static inline void cache_sync(void)
 {
        void __iomem *base = l2x0_base;
-#ifdef CONFIG_PL310_ERRATA_753970
+        writel_relaxed(0, base + sync_reg_offset);
-        /* write to an unmmapped register */
-        writel_relaxed(0, base + L2X0_DUMMY_REG);
-#else
-        writel_relaxed(0, base + L2X0_CACHE_SYNC);
-#endif
        cache_wait(base + L2X0_CACHE_SYNC, 1);
 }
@@ -85,10 +81,13 @@ static inline void l2x0_inv_line(unsigned long addr)
 }
 #if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915)
+static inline void debug_writel(unsigned long val)
+{
+        if (outer_cache.set_debug)
+                outer_cache.set_debug(val);
+}
-#define debug_writel(val)       outer_cache.set_debug(val)
+static void pl310_set_debug(unsigned long val)
-static void l2x0_set_debug(unsigned long val)
 {
        writel_relaxed(val, l2x0_base + L2X0_DEBUG_CTRL);
 }
@@ -98,7 +97,7 @@ static inline void debug_writel(unsigned long val)
 {
 }
-#define l2x0_set_debug  NULL
+#define pl310_set_debug NULL
 #endif
 #ifdef CONFIG_PL310_ERRATA_588369
@@ -331,6 +330,11 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
                else
                        ways = 8;
                type = "L310";
+#ifdef CONFIG_PL310_ERRATA_753970
+                /* Unmapped register. */
+                sync_reg_offset = L2X0_DUMMY_REG;
+#endif
+                outer_cache.set_debug = pl310_set_debug;
                break;
        case L2X0_CACHE_ID_PART_L210:
                ways = (aux >> 13) & 0xf;
@@ -379,7 +383,6 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
        outer_cache.flush_all = l2x0_flush_all;
        outer_cache.inv_all = l2x0_inv_all;
        outer_cache.disable = l2x0_disable;
-        outer_cache.set_debug = l2x0_set_debug;
        printk(KERN_INFO "%s cache controller enabled\n", type);
        printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n",
diff --git a/arch/arm/mm/cache-tauros2.c b/arch/arm/mm/cache-tauros2.c
index 1fbca05fe906..23a7643e9a87 100644
--- a/arch/arm/mm/cache-tauros2.c
+++ b/arch/arm/mm/cache-tauros2.c
@@ -108,6 +108,26 @@ static void tauros2_flush_range(unsigned long start, unsigned long end)
        dsb();
 }
+static void tauros2_disable(void)
+{
+        __asm__ __volatile__ (
+        "mcr    p15, 1, %0, c7, c11, 0 @L2 Cache Clean All\n\t"
+        "mrc    p15, 0, %0, c1, c0, 0\n\t"
+        "bic    %0, %0, #(1 << 26)\n\t"
+        "mcr    p15, 0, %0, c1, c0, 0  @Disable L2 Cache\n\t"
+        : : "r" (0x0));
+}
+static void tauros2_resume(void)
+{
+        __asm__ __volatile__ (
+        "mcr    p15, 1, %0, c7, c7, 0 @L2 Cache Invalidate All\n\t"
+        "mrc    p15, 0, %0, c1, c0, 0\n\t"
+        "orr    %0, %0, #(1 << 26)\n\t"
+        "mcr    p15, 0, %0, c1, c0, 0 @Enable L2 Cache\n\t"
+        : : "r" (0x0));
+}
 #endif
 static inline u32 __init read_extra_features(void)
@@ -194,6 +214,8 @@ void __init tauros2_init(void)
                outer_cache.inv_range = tauros2_inv_range;
                outer_cache.clean_range = tauros2_clean_range;
                outer_cache.flush_range = tauros2_flush_range;
+                outer_cache.disable = tauros2_disable;
+                outer_cache.resume = tauros2_resume;
        }
 #endif
@@ -219,6 +241,8 @@ void __init tauros2_init(void)
                outer_cache.inv_range = tauros2_inv_range;
                outer_cache.clean_range = tauros2_clean_range;
                outer_cache.flush_range = tauros2_flush_range;
+                outer_cache.disable = tauros2_disable;
+                outer_cache.resume = tauros2_resume;
        }
 #endif
diff --git a/arch/arm/mm/cache-v3.S b/arch/arm/mm/cache-v3.S
index c2301f226100..52e35f32eefb 100644
--- a/arch/arm/mm/cache-v3.S
+++ b/arch/arm/mm/cache-v3.S
@@ -78,6 +78,7 @@ ENTRY(v3_coherent_kern_range)
 *      - end    - virtual end address
 */
 ENTRY(v3_coherent_user_range)
+        mov     r0, #0
        mov     pc, lr
 /*
diff --git a/arch/arm/mm/cache-v4.S b/arch/arm/mm/cache-v4.S
index fd9bb7addc8d..022135d2b7e4 100644
--- a/arch/arm/mm/cache-v4.S
+++ b/arch/arm/mm/cache-v4.S
@@ -88,6 +88,7 @@ ENTRY(v4_coherent_kern_range)
 *      - end    - virtual end address
 */
 ENTRY(v4_coherent_user_range)
+        mov     r0, #0
        mov     pc, lr
 /*
diff --git a/arch/arm/mm/cache-v4wb.S b/arch/arm/mm/cache-v4wb.S
index 4f2c14151ccb..8f1eeae340c8 100644
--- a/arch/arm/mm/cache-v4wb.S
+++ b/arch/arm/mm/cache-v4wb.S
@@ -167,9 +167,9 @@ ENTRY(v4wb_coherent_user_range)
        add     r0, r0, #CACHE_DLINESIZE
        cmp     r0, r1
        blo     1b
-        mov     ip, #0
+        mov     r0, #0
-        mcr     p15, 0, ip, c7, c5, 0           @ invalidate I cache
+        mcr     p15, 0, r0, c7, c5, 0           @ invalidate I cache
-        mcr     p15, 0, ip, c7, c10, 4          @ drain WB
+        mcr     p15, 0, r0, c7, c10, 4          @ drain WB
        mov     pc, lr
diff --git a/arch/arm/mm/cache-v4wt.S b/arch/arm/mm/cache-v4wt.S
index 4d7b467631ce..b34a5f908a82 100644
--- a/arch/arm/mm/cache-v4wt.S
+++ b/arch/arm/mm/cache-v4wt.S
@@ -125,6 +125,7 @@ ENTRY(v4wt_coherent_user_range)
        add     r0, r0, #CACHE_DLINESIZE
        cmp     r0, r1
        blo     1b
+        mov     r0, #0
        mov     pc, lr
 /*
diff --git a/arch/arm/mm/cache-v6.S b/arch/arm/mm/cache-v6.S
index 74c2e5a33a4d..4b10760c56d6 100644
--- a/arch/arm/mm/cache-v6.S
+++ b/arch/arm/mm/cache-v6.S
@@ -12,6 +12,7 @@
 #include <linux/linkage.h>
 #include <linux/init.h>
 #include <asm/assembler.h>
+#include <asm/errno.h>
 #include <asm/unwind.h>
 #include "proc-macros.S"
@@ -135,7 +136,6 @@ ENTRY(v6_coherent_user_range)
 1:
 USER(  mcr     p15, 0, r0, c7, c10, 1  )       @ clean D line
        add     r0, r0, #CACHE_LINE_SIZE
-2:
        cmp     r0, r1
        blo     1b
 #endif
@@ -154,13 +154,11 @@ ENTRY(v6_coherent_user_range)
 /*
 * Fault handling for the cache operation above. If the virtual address in r0
- * isn't mapped, just try the next page.
+ * isn't mapped, fail with -EFAULT.
 */
 9001:
-        mov     r0, r0, lsr #12
+        mov     r0, #-EFAULT
-        mov     r0, r0, lsl #12
+        mov     pc, lr
-        add     r0, r0, #4096
-        b       2b
 UNWIND(.fnend          )
 ENDPROC(v6_coherent_user_range)
 ENDPROC(v6_coherent_kern_range)
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index a655d3da386d..39e3fb3db801 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -13,6 +13,7 @@
 #include <linux/linkage.h>
 #include <linux/init.h>
 #include <asm/assembler.h>
+#include <asm/errno.h>
 #include <asm/unwind.h>
 #include "proc-macros.S"
@@ -198,7 +199,6 @@ ENTRY(v7_coherent_user_range)
        add     r12, r12, r2
        cmp     r12, r1
        blo     2b
-3:
        mov     r0, #0
        ALT_SMP(mcr     p15, 0, r0, c7, c1, 6)  @ invalidate BTB Inner Shareable
        ALT_UP(mcr      p15, 0, r0, c7, c5, 6)  @ invalidate BTB
@@ -208,13 +208,11 @@ ENTRY(v7_coherent_user_range)
 /*
 * Fault handling for the cache operation above. If the virtual address in r0
- * isn't mapped, just try the next page.
+ * isn't mapped, fail with -EFAULT.
 */
 9001:
-        mov     r12, r12, lsr #12
+        mov     r0, #-EFAULT
-        mov     r12, r12, lsl #12
+        mov     pc, lr
-        add     r12, r12, #4096
-        b       3b
 UNWIND(.fnend          )
 ENDPROC(v7_coherent_kern_range)
 ENDPROC(v7_coherent_user_range)
diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c
index ee9bb363d606..806cc4f63516 100644
--- a/arch/arm/mm/context.c
+++ b/arch/arm/mm/context.c
@@ -18,30 +18,39 @@
 static DEFINE_RAW_SPINLOCK(cpu_asid_lock);
 unsigned int cpu_last_asid = ASID_FIRST_VERSION;
-#ifdef CONFIG_SMP
-DEFINE_PER_CPU(struct mm_struct *, current_mm);
-#endif
 #ifdef CONFIG_ARM_LPAE
-#define cpu_set_asid(asid) {                                            \
+void cpu_set_reserved_ttbr0(void)
-        unsigned long ttbl, ttbh;                                       \
+{
-        asm volatile(                                                   \
+        unsigned long ttbl = __pa(swapper_pg_dir);
-        "       mrrc    p15, 0, %0, %1, c2              @ read TTBR0\n" \
+        unsigned long ttbh = 0;
-        "       mov     %1, %2, lsl #(48 - 32)          @ set ASID\n"   \
-        "       mcrr    p15, 0, %0, %1, c2              @ set TTBR0\n"  \
+        /*
-        : "=&r" (ttbl), "=&r" (ttbh)                                    \
+         * Set TTBR0 to swapper_pg_dir which contains only global entries. The
-        : "r" (asid & ~ASID_MASK));                                     \
+         * ASID is set to 0.
+         */
+        asm volatile(
+        "       mcrr    p15, 0, %0, %1, c2              @ set TTBR0\n"
+        :
+        : "r" (ttbl), "r" (ttbh));
+        isb();
 }
 #else
-#define cpu_set_asid(asid) \
+void cpu_set_reserved_ttbr0(void)
-        asm("   mcr     p15, 0, %0, c13, c0, 1\n" : : "r" (asid))
+{
+        u32 ttb;
+        /* Copy TTBR1 into TTBR0 */
+        asm volatile(
+        "       mrc     p15, 0, %0, c2, c0, 1           @ read TTBR1\n"
+        "       mcr     p15, 0, %0, c2, c0, 0           @ set TTBR0\n"
+        : "=r" (ttb));
+        isb();
+}
 #endif
 /*
 * We fork()ed a process, and we need a new context for the child
- * to run in.  We reserve version 0 for initial tasks so we will
+ * to run in.
- * always allocate an ASID. The ASID 0 is reserved for the TTBR
- * register changing sequence.
 */
 void __init_new_context(struct task_struct *tsk, struct mm_struct *mm)
 {
@@ -51,9 +60,7 @@ void __init_new_context(struct task_struct *tsk, struct mm_struct *mm)
 static void flush_context(void)
 {
-        /* set the reserved ASID before flushing the TLB */
+        cpu_set_reserved_ttbr0();
-        cpu_set_asid(0);
-        isb();
        local_flush_tlb_all();
        if (icache_is_vivt_asid_tagged()) {
                __flush_icache_all();
@@ -98,14 +105,7 @@ static void reset_context(void *info)
 {
        unsigned int asid;
        unsigned int cpu = smp_processor_id();
-        struct mm_struct *mm = per_cpu(current_mm, cpu);
+        struct mm_struct *mm = current->active_mm;
-        /*
-         * Check if a current_mm was set on this CPU as it might still
-         * be in the early booting stages and using the reserved ASID.
-         */
-        if (!mm)
-                return;
        smp_rmb();
        asid = cpu_last_asid + cpu + 1;
@@ -114,8 +114,7 @@ static void reset_context(void *info)
        set_mm_context(mm, asid);
        /* set the new ASID */
-        cpu_set_asid(mm->context.id);
+        cpu_switch_mm(mm->pgd, mm);
-        isb();
 }
 #else
diff --git a/arch/arm/mm/copypage-v3.c b/arch/arm/mm/copypage-v3.c
deleted file mode 100644
index 3935bddd4769..000000000000
--- a/arch/arm/mm/copypage-v3.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- *  linux/arch/arm/mm/copypage-v3.c
- *
- *  Copyright (C) 1995-1999 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/init.h>
-#include <linux/highmem.h>
-/*
- * ARMv3 optimised copy_user_highpage
- *
- * FIXME: do we need to handle cache stuff...
- */
-static void __naked
-v3_copy_user_page(void *kto, const void *kfrom)
-{
-        asm("\n\
-        stmfd   sp!, {r4, lr}                   @       2\n\
-        mov     r2, %2                          @       1\n\
-        ldmia   %0!, {r3, r4, ip, lr}           @       4+1\n\
-1:      stmia   %1!, {r3, r4, ip, lr}           @       4\n\
-        ldmia   %0!, {r3, r4, ip, lr}           @       4+1\n\
-        stmia   %1!, {r3, r4, ip, lr}           @       4\n\
-        ldmia   %0!, {r3, r4, ip, lr}           @       4+1\n\
-        stmia   %1!, {r3, r4, ip, lr}           @       4\n\
-        ldmia   %0!, {r3, r4, ip, lr}           @       4\n\
-        subs    r2, r2, #1                      @       1\n\
-        stmia   %1!, {r3, r4, ip, lr}           @       4\n\
-        ldmneia %0!, {r3, r4, ip, lr}           @       4\n\
-        bne     1b                              @       1\n\
-        ldmfd   sp!, {r4, pc}                   @       3"
-        :
-        : "r" (kfrom), "r" (kto), "I" (PAGE_SIZE / 64));
-}
-void v3_copy_user_highpage(struct page *to, struct page *from,
-        unsigned long vaddr, struct vm_area_struct *vma)
-{
-        void *kto, *kfrom;
-        kto = kmap_atomic(to);
-        kfrom = kmap_atomic(from);
-        v3_copy_user_page(kto, kfrom);
-        kunmap_atomic(kfrom);
-        kunmap_atomic(kto);
-}
-/*
- * ARMv3 optimised clear_user_page
- *
- * FIXME: do we need to handle cache stuff...
- */
-void v3_clear_user_highpage(struct page *page, unsigned long vaddr)
-{
-        void *ptr, *kaddr = kmap_atomic(page);
-        asm volatile("\n\
-        mov     r1, %2                          @ 1\n\
-        mov     r2, #0                          @ 1\n\
-        mov     r3, #0                          @ 1\n\
-        mov     ip, #0                          @ 1\n\
-        mov     lr, #0                          @ 1\n\
-1:      stmia   %0!, {r2, r3, ip, lr}           @ 4\n\
-        stmia   %0!, {r2, r3, ip, lr}           @ 4\n\
-        stmia   %0!, {r2, r3, ip, lr}           @ 4\n\
-        stmia   %0!, {r2, r3, ip, lr}           @ 4\n\
-        subs    r1, r1, #1                      @ 1\n\
-        bne     1b                              @ 1"
-        : "=r" (ptr)
-        : "0" (kaddr), "I" (PAGE_SIZE / 64)
-        : "r1", "r2", "r3", "ip", "lr");
-        kunmap_atomic(kaddr);
-}
-struct cpu_user_fns v3_user_fns __initdata = {
-        .cpu_clear_user_highpage = v3_clear_user_highpage,
-        .cpu_copy_user_highpage = v3_copy_user_highpage,
-};
diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c
index 9055b5a84ec5..c3bd83450227 100644
--- a/arch/arm/mm/fault.c
+++ b/arch/arm/mm/fault.c
@@ -247,7 +247,9 @@ good_area:
        return handle_mm_fault(mm, vma, addr & PAGE_MASK, flags);
 check_stack:
-        if (vma->vm_flags & VM_GROWSDOWN && !expand_stack(vma, addr))
+        /* Don't allow expansion below FIRST_USER_ADDRESS */
+        if (vma->vm_flags & VM_GROWSDOWN &&
+            addr >= FIRST_USER_ADDRESS && !expand_stack(vma, addr))
                goto good_area;
 out:
        return fault;
@@ -320,7 +322,7 @@ retry:
         */
        perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, regs, addr);
-        if (flags & FAULT_FLAG_ALLOW_RETRY) {
+        if (!(fault & VM_FAULT_ERROR) && flags & FAULT_FLAG_ALLOW_RETRY) {
                if (fault & VM_FAULT_MAJOR) {
                        tsk->maj_flt++;
                        perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1,
@@ -430,9 +432,6 @@ do_translation_fault(unsigned long addr, unsigned int fsr,
        index = pgd_index(addr);
-        /*
-         * FIXME: CP15 C1 is write only on ARMv3 architectures.
-         */
        pgd = cpu_get_pgd() + index;
        pgd_k = init_mm.pgd + index;
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 595079fa9d1d..8f5813bbffb5 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -293,11 +293,11 @@ EXPORT_SYMBOL(pfn_valid);
 #endif
 #ifndef CONFIG_SPARSEMEM
-static void arm_memory_present(void)
+static void __init arm_memory_present(void)
 {
 }
 #else
-static void arm_memory_present(void)
+static void __init arm_memory_present(void)
 {
        struct memblock_region *reg;
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index b86f8933ff91..aa78de8bfdd3 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -489,7 +489,8 @@ static void __init build_mem_type_table(void)
         */
        for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
                mem_types[i].prot_pte |= PTE_EXT_AF;
-                mem_types[i].prot_sect |= PMD_SECT_AF;
+                if (mem_types[i].prot_sect)
+                        mem_types[i].prot_sect |= PMD_SECT_AF;
        }
        kern_pgprot |= PTE_EXT_AF;
        vecs_pgprot |= PTE_EXT_AF;
@@ -618,8 +619,8 @@ static void __init alloc_init_section(pud_t *pud, unsigned long addr,
        }
 }
-static void alloc_init_pud(pgd_t *pgd, unsigned long addr, unsigned long end,
+static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr,
-        unsigned long phys, const struct mem_type *type)
+        unsigned long end, unsigned long phys, const struct mem_type *type)
 {
        pud_t *pud = pud_offset(pgd, addr);
        unsigned long next;
diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c
index 6486d2f253cd..d51225f90ae2 100644
--- a/arch/arm/mm/nommu.c
+++ b/arch/arm/mm/nommu.c
@@ -13,6 +13,7 @@
 #include <asm/sections.h>
 #include <asm/page.h>
 #include <asm/setup.h>
+#include <asm/traps.h>
 #include <asm/mach/arch.h>
 #include "mm.h"
@@ -39,6 +40,7 @@ void __init sanity_check_meminfo(void)
 */
 void __init paging_init(struct machine_desc *mdesc)
 {
+        early_trap_init((void *)CONFIG_VECTORS_BASE);
        bootmem_init();
 }
diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S
index 234951345eb3..0650bb87c1e3 100644
--- a/arch/arm/mm/proc-arm1020.S
+++ b/arch/arm/mm/proc-arm1020.S
@@ -241,6 +241,7 @@ ENTRY(arm1020_coherent_user_range)
        cmp     r0, r1
        blo     1b
        mcr     p15, 0, ip, c7, c10, 4          @ drain WB
+        mov     r0, #0
        mov     pc, lr
 /*
diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S
index c244b06caac9..4188478325a6 100644
--- a/arch/arm/mm/proc-arm1020e.S
+++ b/arch/arm/mm/proc-arm1020e.S
@@ -235,6 +235,7 @@ ENTRY(arm1020e_coherent_user_range)
        cmp     r0, r1
        blo     1b
        mcr     p15, 0, ip, c7, c10, 4          @ drain WB
+        mov     r0, #0
        mov     pc, lr
 /*
diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S
index 38fe22efd18f..33c68824bff0 100644
--- a/arch/arm/mm/proc-arm1022.S
+++ b/arch/arm/mm/proc-arm1022.S
@@ -224,6 +224,7 @@ ENTRY(arm1022_coherent_user_range)
        cmp     r0, r1
        blo     1b
        mcr     p15, 0, ip, c7, c10, 4          @ drain WB
+        mov     r0, #0
        mov     pc, lr
 /*
diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S
index 3eb9c3c26c75..fbc1d5fc24dc 100644
--- a/arch/arm/mm/proc-arm1026.S
+++ b/arch/arm/mm/proc-arm1026.S
@@ -218,6 +218,7 @@ ENTRY(arm1026_coherent_user_range)
        cmp     r0, r1
        blo     1b
        mcr     p15, 0, ip, c7, c10, 4          @ drain WB
+        mov     r0, #0
        mov     pc, lr
 /*
diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S
deleted file mode 100644
index 4fbeb5b8e6c2..000000000000
--- a/arch/arm/mm/proc-arm6_7.S
+++ /dev/null
@@ -1,327 +0,0 @@
-/*
- *  linux/arch/arm/mm/proc-arm6,7.S
- *
- *  Copyright (C) 1997-2000 Russell King
- *  hacked for non-paged-MM by Hyok S. Choi, 2003.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- *  These are the low level assembler for performing cache and TLB
- *  functions on the ARM610 & ARM710.
- */
-#include <linux/linkage.h>
-#include <linux/init.h>
-#include <asm/assembler.h>
-#include <asm/asm-offsets.h>
-#include <asm/hwcap.h>
-#include <asm/pgtable-hwdef.h>
-#include <asm/pgtable.h>
-#include <asm/ptrace.h>
-#include "proc-macros.S"
-ENTRY(cpu_arm6_dcache_clean_area)
-ENTRY(cpu_arm7_dcache_clean_area)
-                mov     pc, lr
-/*
- * Function: arm6_7_data_abort ()
- *
- * Params  : r2 = pt_regs
- *         : r4 = aborted context pc
- *         : r5 = aborted context psr
- *
- * Purpose : obtain information about current aborted instruction
- *
- * Returns : r4-r5, r10-r11, r13 preserved
- */
-ENTRY(cpu_arm7_data_abort)
-        mrc     p15, 0, r1, c5, c0, 0           @ get FSR
-        mrc     p15, 0, r0, c6, c0, 0           @ get FAR
-        ldr     r8, [r4]                        @ read arm instruction
-        tst     r8, #1 << 20                    @ L = 0 -> write?
-        orreq   r1, r1, #1 << 11                @ yes.
-        and     r7, r8, #15 << 24
-        add     pc, pc, r7, lsr #22             @ Now branch to the relevant processing routine
-        nop
-/* 0 */ b       .data_unknown
-/* 1 */ b       do_DataAbort                    @ swp
-/* 2 */ b       .data_unknown
-/* 3 */ b       .data_unknown
-/* 4 */ b       .data_arm_lateldrpostconst      @ ldr   rd, [rn], #m
-/* 5 */ b       .data_arm_lateldrpreconst       @ ldr   rd, [rn, #m]
-/* 6 */ b       .data_arm_lateldrpostreg        @ ldr   rd, [rn], rm
-/* 7 */ b       .data_arm_lateldrprereg         @ ldr   rd, [rn, rm]
-/* 8 */ b       .data_arm_ldmstm                @ ldm*a rn, <rlist>
-/* 9 */ b       .data_arm_ldmstm                @ ldm*b rn, <rlist>
-/* a */ b       .data_unknown
-/* b */ b       .data_unknown
-/* c */ b       do_DataAbort                    @ ldc   rd, [rn], #m    @ Same as ldr   rd, [rn], #m
-/* d */ b       do_DataAbort                    @ ldc   rd, [rn, #m]
-/* e */ b       .data_unknown
-/* f */
-.data_unknown:  @ Part of jumptable
-        mov     r0, r4
-        mov     r1, r8
-        b       baddataabort
-ENTRY(cpu_arm6_data_abort)
-        mrc     p15, 0, r1, c5, c0, 0           @ get FSR
-        mrc     p15, 0, r0, c6, c0, 0           @ get FAR
-        ldr     r8, [r4]                        @ read arm instruction
-        tst     r8, #1 << 20                    @ L = 0 -> write?
-        orreq   r1, r1, #1 << 11                @ yes.
-        and     r7, r8, #14 << 24
-        teq     r7, #8 << 24                    @ was it ldm/stm
-        bne     do_DataAbort
-.data_arm_ldmstm:
-        tst     r8, #1 << 21                    @ check writeback bit
-        beq     do_DataAbort                    @ no writeback -> no fixup
-        mov     r7, #0x11
-        orr     r7, r7, #0x1100
-        and     r6, r8, r7
-        and     r9, r8, r7, lsl #1
-        add     r6, r6, r9, lsr #1
-        and     r9, r8, r7, lsl #2
-        add     r6, r6, r9, lsr #2
-        and     r9, r8, r7, lsl #3
-        add     r6, r6, r9, lsr #3
-        add     r6, r6, r6, lsr #8
-        add     r6, r6, r6, lsr #4
-        and     r6, r6, #15                     @ r6 = no. of registers to transfer.
-        and     r9, r8, #15 << 16               @ Extract 'n' from instruction
-        ldr     r7, [r2, r9, lsr #14]           @ Get register 'Rn'
-        tst     r8, #1 << 23                    @ Check U bit
-        subne   r7, r7, r6, lsl #2              @ Undo increment
-        addeq   r7, r7, r6, lsl #2              @ Undo decrement
-        str     r7, [r2, r9, lsr #14]           @ Put register 'Rn'
-        b       do_DataAbort
-.data_arm_apply_r6_and_rn:
-        and     r9, r8, #15 << 16               @ Extract 'n' from instruction
-        ldr     r7, [r2, r9, lsr #14]           @ Get register 'Rn'
-        tst     r8, #1 << 23                    @ Check U bit
-        subne   r7, r7, r6                      @ Undo incrmenet
-        addeq   r7, r7, r6                      @ Undo decrement
-        str     r7, [r2, r9, lsr #14]           @ Put register 'Rn'
-        b       do_DataAbort
-.data_arm_lateldrpreconst:
-        tst     r8, #1 << 21                    @ check writeback bit
-        beq     do_DataAbort                    @ no writeback -> no fixup
-.data_arm_lateldrpostconst:
-        movs    r6, r8, lsl #20                 @ Get offset
-        beq     do_DataAbort                    @ zero -> no fixup
-        and     r9, r8, #15 << 16               @ Extract 'n' from instruction
-        ldr     r7, [r2, r9, lsr #14]           @ Get register 'Rn'
-        tst     r8, #1 << 23                    @ Check U bit
-        subne   r7, r7, r6, lsr #20             @ Undo increment
-        addeq   r7, r7, r6, lsr #20             @ Undo decrement
-        str     r7, [r2, r9, lsr #14]           @ Put register 'Rn'
-        b       do_DataAbort
-.data_arm_lateldrprereg:
-        tst     r8, #1 << 21                    @ check writeback bit
-        beq     do_DataAbort                    @ no writeback -> no fixup
-.data_arm_lateldrpostreg:
-        and     r7, r8, #15                     @ Extract 'm' from instruction
-        ldr     r6, [r2, r7, lsl #2]            @ Get register 'Rm'
-        mov     r9, r8, lsr #7                  @ get shift count
-        ands    r9, r9, #31
-        and     r7, r8, #0x70                   @ get shift type
-        orreq   r7, r7, #8                      @ shift count = 0
-        add     pc, pc, r7
-        nop
-        mov     r6, r6, lsl r9                  @ 0: LSL #!0
-        b       .data_arm_apply_r6_and_rn
-        b       .data_arm_apply_r6_and_rn       @ 1: LSL #0
-        nop
-        b       .data_unknown                   @ 2: MUL?
-        nop
-        b       .data_unknown                   @ 3: MUL?
-        nop
-        mov     r6, r6, lsr r9                  @ 4: LSR #!0
-        b       .data_arm_apply_r6_and_rn
-        mov     r6, r6, lsr #32                 @ 5: LSR #32
-        b       .data_arm_apply_r6_and_rn
-        b       .data_unknown                   @ 6: MUL?
-        nop
-        b       .data_unknown                   @ 7: MUL?
-        nop
-        mov     r6, r6, asr r9                  @ 8: ASR #!0
-        b       .data_arm_apply_r6_and_rn
-        mov     r6, r6, asr #32                 @ 9: ASR #32
-        b       .data_arm_apply_r6_and_rn
-        b       .data_unknown                   @ A: MUL?
-        nop
-        b       .data_unknown                   @ B: MUL?
-        nop
-        mov     r6, r6, ror r9                  @ C: ROR #!0
-        b       .data_arm_apply_r6_and_rn
-        mov     r6, r6, rrx                     @ D: RRX
-        b       .data_arm_apply_r6_and_rn
-        b       .data_unknown                   @ E: MUL?
-        nop
-        b       .data_unknown                   @ F: MUL?
-/*
- * Function: arm6_7_proc_init (void)
- *         : arm6_7_proc_fin (void)
- *
- * Notes   : This processor does not require these
- */
-ENTRY(cpu_arm6_proc_init)
-ENTRY(cpu_arm7_proc_init)
-                mov     pc, lr
-ENTRY(cpu_arm6_proc_fin)
-ENTRY(cpu_arm7_proc_fin)
-                mov     r0, #0x31                       @ ....S..DP...M
-                mcr     p15, 0, r0, c1, c0, 0           @ disable caches
-                mov     pc, lr
-ENTRY(cpu_arm6_do_idle)
-ENTRY(cpu_arm7_do_idle)
-                mov     pc, lr
-/*
- * Function: arm6_7_switch_mm(unsigned long pgd_phys)
- * Params  : pgd_phys   Physical address of page table
- * Purpose : Perform a task switch, saving the old processes state, and restoring
- *           the new.
- */
-ENTRY(cpu_arm6_switch_mm)
-ENTRY(cpu_arm7_switch_mm)
-#ifdef CONFIG_MMU
-                mov     r1, #0
-                mcr     p15, 0, r1, c7, c0, 0           @ flush cache
-                mcr     p15, 0, r0, c2, c0, 0           @ update page table ptr
-                mcr     p15, 0, r1, c5, c0, 0           @ flush TLBs
-#endif
-                mov     pc, lr
-/*
- * Function: arm6_7_set_pte_ext(pte_t *ptep, pte_t pte, unsigned int ext)
- * Params  : r0 = Address to set
- *         : r1 = value to set
- * Purpose : Set a PTE and flush it out of any WB cache
- */
-        .align  5
-ENTRY(cpu_arm6_set_pte_ext)
-ENTRY(cpu_arm7_set_pte_ext)
-#ifdef CONFIG_MMU
-        armv3_set_pte_ext wc_disable=0
-#endif /* CONFIG_MMU */
-        mov     pc, lr
-/*
- * Function: _arm6_7_reset
- * Params  : r0 = address to jump to
- * Notes   : This sets up everything for a reset
- */
-                .pushsection    .idmap.text, "ax"
-ENTRY(cpu_arm6_reset)
-ENTRY(cpu_arm7_reset)
-                mov     r1, #0
-                mcr     p15, 0, r1, c7, c0, 0           @ flush cache
-#ifdef CONFIG_MMU
-                mcr     p15, 0, r1, c5, c0, 0           @ flush TLB
-#endif
-                mov     r1, #0x30
-                mcr     p15, 0, r1, c1, c0, 0           @ turn off MMU etc
-                mov     pc, r0
-ENDPROC(cpu_arm6_reset)
-ENDPROC(cpu_arm7_reset)
-                .popsection
-                __CPUINIT
-                .type   __arm6_setup, #function
-__arm6_setup:   mov     r0, #0
-                mcr     p15, 0, r0, c7, c0              @ flush caches on v3
-#ifdef CONFIG_MMU
-                mcr     p15, 0, r0, c5, c0              @ flush TLBs on v3
-                mov     r0, #0x3d                       @ . ..RS BLDP WCAM
-                orr     r0, r0, #0x100                  @ . ..01 0011 1101
-#else
-                mov     r0, #0x3c                       @ . ..RS BLDP WCA.
-#endif
-                mov     pc, lr
-                .size   __arm6_setup, . - __arm6_setup
-                .type   __arm7_setup, #function
-__arm7_setup:   mov     r0, #0
-                mcr     p15, 0, r0, c7, c0              @ flush caches on v3
-#ifdef CONFIG_MMU
-                mcr     p15, 0, r0, c5, c0              @ flush TLBs on v3
-                mcr     p15, 0, r0, c3, c0              @ load domain access register
-                mov     r0, #0x7d                       @ . ..RS BLDP WCAM
-                orr     r0, r0, #0x100                  @ . ..01 0111 1101
-#else
-                mov     r0, #0x7c                       @ . ..RS BLDP WCA.
-#endif
-                mov     pc, lr
-                .size   __arm7_setup, . - __arm7_setup
-                __INITDATA
-                @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
-                define_processor_functions arm6, dabort=cpu_arm6_data_abort, pabort=legacy_pabort
-                define_processor_functions arm7, dabort=cpu_arm7_data_abort, pabort=legacy_pabort
-                .section ".rodata"
-                string  cpu_arch_name, "armv3"
-                string  cpu_elf_name, "v3"
-                string  cpu_arm6_name, "ARM6"
-                string  cpu_arm610_name, "ARM610"
-                string  cpu_arm7_name, "ARM7"
-                string  cpu_arm710_name, "ARM710"
-                .align
-                .section ".proc.info.init", #alloc, #execinstr
-.macro arm67_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, \
-        cpu_mm_mmu_flags:req, cpu_flush:req, cpu_proc_funcs:req
-                .type   __\name\()_proc_info, #object
-__\name\()_proc_info:
-                .long   \cpu_val
-                .long   \cpu_mask
-                .long   \cpu_mm_mmu_flags
-                .long   PMD_TYPE_SECT | \
-                        PMD_BIT4 | \
-                        PMD_SECT_AP_WRITE | \
-                        PMD_SECT_AP_READ
-                b       \cpu_flush
-                .long   cpu_arch_name
-                .long   cpu_elf_name
-                .long   HWCAP_SWP | HWCAP_26BIT
-                .long   \cpu_name
-                .long   \cpu_proc_funcs
-                .long   v3_tlb_fns
-                .long   v3_user_fns
-                .long   v3_cache_fns
-                .size   __\name\()_proc_info, . - __\name\()_proc_info
-.endm
-        arm67_proc_info arm6,   0x41560600, 0xfffffff0, cpu_arm6_name, \
-                0x00000c1e, __arm6_setup, arm6_processor_functions
-        arm67_proc_info arm610, 0x41560610, 0xfffffff0, cpu_arm610_name, \
-                0x00000c1e, __arm6_setup, arm6_processor_functions
-        arm67_proc_info arm7,   0x41007000, 0xffffff00, cpu_arm7_name, \
-                0x00000c1e, __arm7_setup, arm7_processor_functions
-        arm67_proc_info arm710, 0x41007100, 0xfff8ff00, cpu_arm710_name, \
-                        PMD_TYPE_SECT | \
-                        PMD_SECT_BUFFERABLE | \
-                        PMD_SECT_CACHEABLE | \
-                        PMD_BIT4 | \
-                        PMD_SECT_AP_WRITE | \
-                        PMD_SECT_AP_READ, \
-                __arm7_setup, arm7_processor_functions
diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S
index cb941ae95f66..1a8c138eb897 100644
--- a/arch/arm/mm/proc-arm920.S
+++ b/arch/arm/mm/proc-arm920.S
@@ -210,6 +210,7 @@ ENTRY(arm920_coherent_user_range)
        cmp     r0, r1
        blo     1b
        mcr     p15, 0, r0, c7, c10, 4          @ drain WB
+        mov     r0, #0
        mov     pc, lr
 /*
diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S
index 4ec0e074dd55..4c44d7e1c3ca 100644
--- a/arch/arm/mm/proc-arm922.S
+++ b/arch/arm/mm/proc-arm922.S
@@ -212,6 +212,7 @@ ENTRY(arm922_coherent_user_range)
        cmp     r0, r1
        blo     1b
        mcr     p15, 0, r0, c7, c10, 4          @ drain WB
+        mov     r0, #0
        mov     pc, lr
 /*
diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S
index 9dccd9a365b3..ec5b1180994f 100644
--- a/arch/arm/mm/proc-arm925.S
+++ b/arch/arm/mm/proc-arm925.S
@@ -258,6 +258,7 @@ ENTRY(arm925_coherent_user_range)
        cmp     r0, r1
        blo     1b
        mcr     p15, 0, r0, c7, c10, 4          @ drain WB
+        mov     r0, #0
        mov     pc, lr
 /*
diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S
index 820259b81a1f..c31e62c606c0 100644
--- a/arch/arm/mm/proc-arm926.S
+++ b/arch/arm/mm/proc-arm926.S
@@ -221,6 +221,7 @@ ENTRY(arm926_coherent_user_range)
        cmp     r0, r1
        blo     1b
        mcr     p15, 0, r0, c7, c10, 4          @ drain WB
+        mov     r0, #0
        mov     pc, lr
 /*
diff --git a/arch/arm/mm/proc-arm940.S b/arch/arm/mm/proc-arm940.S
index 9fdc0a170974..a613a7dd7146 100644
--- a/arch/arm/mm/proc-arm940.S
+++ b/arch/arm/mm/proc-arm940.S
@@ -160,7 +160,7 @@ ENTRY(arm940_coherent_user_range)
 *      - size  - region size
 */
 ENTRY(arm940_flush_kern_dcache_area)
-        mov     ip, #0
+        mov     r0, #0
        mov     r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments
 1:      orr     r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
 2:      mcr     p15, 0, r3, c7, c14, 2          @ clean/flush D index
@@ -168,8 +168,8 @@ ENTRY(arm940_flush_kern_dcache_area)
        bcs     2b                              @ entries 63 to 0
        subs    r1, r1, #1 << 4
        bcs     1b                              @ segments 7 to 0
-        mcr     p15, 0, ip, c7, c5, 0           @ invalidate I cache
+        mcr     p15, 0, r0, c7, c5, 0           @ invalidate I cache
-        mcr     p15, 0, ip, c7, c10, 4          @ drain WB
+        mcr     p15, 0, r0, c7, c10, 4          @ drain WB
        mov     pc, lr
 /*
diff --git a/arch/arm/mm/proc-arm946.S b/arch/arm/mm/proc-arm946.S
index f684cfedcca9..9f4f2999fdd0 100644
--- a/arch/arm/mm/proc-arm946.S
+++ b/arch/arm/mm/proc-arm946.S
@@ -190,6 +190,7 @@ ENTRY(arm946_coherent_user_range)
        cmp     r0, r1
        blo     1b
        mcr     p15, 0, r0, c7, c10, 4          @ drain WB
+        mov     r0, #0
        mov     pc, lr
 /*
diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S
index ba3c500584ac..23a8e4c7f2bd 100644
--- a/arch/arm/mm/proc-feroceon.S
+++ b/arch/arm/mm/proc-feroceon.S
@@ -232,6 +232,7 @@ ENTRY(feroceon_coherent_user_range)
        cmp     r0, r1
        blo     1b
        mcr     p15, 0, r0, c7, c10, 4          @ drain WB
+        mov     r0, #0
        mov     pc, lr
 /*
diff --git a/arch/arm/mm/proc-mohawk.S b/arch/arm/mm/proc-mohawk.S
index cdfedc5b8ad8..fbb2124a547d 100644
--- a/arch/arm/mm/proc-mohawk.S
+++ b/arch/arm/mm/proc-mohawk.S
@@ -193,6 +193,7 @@ ENTRY(mohawk_coherent_user_range)
        cmp     r0, r1
        blo     1b
        mcr     p15, 0, r0, c7, c10, 4          @ drain WB
+        mov     r0, #0
        mov     pc, lr
 /*
@@ -344,6 +345,41 @@ ENTRY(cpu_mohawk_set_pte_ext)
        mcr     p15, 0, r0, c7, c10, 4          @ drain WB
        mov     pc, lr
+.globl  cpu_mohawk_suspend_size
+.equ    cpu_mohawk_suspend_size, 4 * 6
+#ifdef CONFIG_PM_SLEEP
+ENTRY(cpu_mohawk_do_suspend)
+        stmfd   sp!, {r4 - r9, lr}
+        mrc     p14, 0, r4, c6, c0, 0   @ clock configuration, for turbo mode
+        mrc     p15, 0, r5, c15, c1, 0  @ CP access reg
+        mrc     p15, 0, r6, c13, c0, 0  @ PID
+        mrc     p15, 0, r7, c3, c0, 0   @ domain ID
+        mrc     p15, 0, r8, c1, c0, 1   @ auxiliary control reg
+        mrc     p15, 0, r9, c1, c0, 0   @ control reg
+        bic     r4, r4, #2              @ clear frequency change bit
+        stmia   r0, {r4 - r9}           @ store cp regs
+        ldmia   sp!, {r4 - r9, pc}
+ENDPROC(cpu_mohawk_do_suspend)
+ENTRY(cpu_mohawk_do_resume)
+        ldmia   r0, {r4 - r9}           @ load cp regs
+        mov     ip, #0
+        mcr     p15, 0, ip, c7, c7, 0   @ invalidate I & D caches, BTB
+        mcr     p15, 0, ip, c7, c10, 4  @ drain write (&fill) buffer
+        mcr     p15, 0, ip, c7, c5, 4   @ flush prefetch buffer
+        mcr     p15, 0, ip, c8, c7, 0   @ invalidate I & D TLBs
+        mcr     p14, 0, r4, c6, c0, 0   @ clock configuration, turbo mode.
+        mcr     p15, 0, r5, c15, c1, 0  @ CP access reg
+        mcr     p15, 0, r6, c13, c0, 0  @ PID
+        mcr     p15, 0, r7, c3, c0, 0   @ domain ID
+        orr     r1, r1, #0x18           @ cache the page table in L2
+        mcr     p15, 0, r1, c2, c0, 0   @ translation table base addr
+        mcr     p15, 0, r8, c1, c0, 1   @ auxiliary control reg
+        mov     r0, r9                  @ control register
+        b       cpu_resume_mmu
+ENDPROC(cpu_mohawk_do_resume)
+#endif
        __CPUINIT
        .type   __mohawk_setup, #function
diff --git a/arch/arm/mm/proc-v7-2level.S b/arch/arm/mm/proc-v7-2level.S
index 3a4b3e7b888c..42ac069c8012 100644
--- a/arch/arm/mm/proc-v7-2level.S
+++ b/arch/arm/mm/proc-v7-2level.S
@@ -49,15 +49,10 @@ ENTRY(cpu_v7_switch_mm)
 #ifdef CONFIG_ARM_ERRATA_754322
        dsb
 #endif
-        mcr     p15, 0, r2, c13, c0, 1          @ set reserved context ID
-        isb
-1:      mcr     p15, 0, r0, c2, c0, 0           @ set TTB 0
-        isb
-#ifdef CONFIG_ARM_ERRATA_754322
-        dsb
-#endif
        mcr     p15, 0, r1, c13, c0, 1          @ set context ID
        isb
+        mcr     p15, 0, r0, c2, c0, 0           @ set TTB 0
+        isb
 #endif
        mov     pc, lr
 ENDPROC(cpu_v7_switch_mm)
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index f1c8486f7501..c2e2b66f72b5 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -255,6 +255,18 @@ __v7_setup:
        mcr     p15, 0, r5, c10, c2, 0          @ write PRRR
        mcr     p15, 0, r6, c10, c2, 1          @ write NMRR
 #endif
+#ifndef CONFIG_ARM_THUMBEE
+        mrc     p15, 0, r0, c0, c1, 0           @ read ID_PFR0 for ThumbEE
+        and     r0, r0, #(0xf << 12)            @ ThumbEE enabled field
+        teq     r0, #(1 << 12)                  @ check if ThumbEE is present
+        bne     1f
+        mov     r5, #0
+        mcr     p14, 6, r5, c1, c0, 0           @ Initialize TEEHBR to 0
+        mrc     p14, 6, r0, c0, c0, 0           @ load TEECR
+        orr     r0, r0, #1                      @ set the 1st bit in order to
+        mcr     p14, 6, r0, c0, c0, 0           @ stop userspace TEEHBR access
+1:
+#endif
        adr     r5, v7_crval
        ldmia   r5, {r5, r6}
 #ifdef CONFIG_CPU_ENDIAN_BE8
diff --git a/arch/arm/mm/tlb-v3.S b/arch/arm/mm/tlb-v3.S
deleted file mode 100644
index d253995ec4ca..000000000000
--- a/arch/arm/mm/tlb-v3.S
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- *  linux/arch/arm/mm/tlbv3.S
- *
- *  Copyright (C) 1997-2002 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- *  ARM architecture version 3 TLB handling functions.
- *
- * Processors: ARM610, ARM710.
- */
-#include <linux/linkage.h>
-#include <linux/init.h>
-#include <asm/asm-offsets.h>
-#include <asm/tlbflush.h>
-#include "proc-macros.S"
-        .align  5
-/*
- *      v3_flush_user_tlb_range(start, end, mm)
- *
- *      Invalidate a range of TLB entries in the specified address space.
- *
- *      - start - range start address
- *      - end   - range end address
- *      - mm    - mm_struct describing address space
- */
-        .align  5
-ENTRY(v3_flush_user_tlb_range)
-        vma_vm_mm r2, r2
-        act_mm  r3                              @ get current->active_mm
-        teq     r2, r3                          @ == mm ?
-        movne   pc, lr                          @ no, we dont do anything
-ENTRY(v3_flush_kern_tlb_range)
-        bic     r0, r0, #0x0ff
-        bic     r0, r0, #0xf00
-1:      mcr     p15, 0, r0, c6, c0, 0           @ invalidate TLB entry
-        add     r0, r0, #PAGE_SZ
-        cmp     r0, r1
-        blo     1b
-        mov     pc, lr
-        __INITDATA
-        /* define struct cpu_tlb_fns (see <asm/tlbflush.h> and proc-macros.S) */
-        define_tlb_functions v3, v3_tlb_flags
diff --git a/arch/arm/plat-iop/pci.c b/arch/arm/plat-iop/pci.c
index 0da42058a20f..8daae9b230ea 100644
--- a/arch/arm/plat-iop/pci.c
+++ b/arch/arm/plat-iop/pci.c
@@ -160,7 +160,7 @@ iop3xx_write_config(struct pci_bus *bus, unsigned int devfn, int where,
        return PCIBIOS_SUCCESSFUL;
 }
-static struct pci_ops iop3xx_ops = {
+struct pci_ops iop3xx_ops = {
        .read   = iop3xx_read_config,
        .write  = iop3xx_write_config,
 };
@@ -220,12 +220,6 @@ int iop3xx_pci_setup(int nr, struct pci_sys_data *sys)
        return 1;
 }
-struct pci_bus *iop3xx_pci_scan_bus(int nr, struct pci_sys_data *sys)
-{
-        return pci_scan_root_bus(NULL, sys->busnr, &iop3xx_ops, sys,
-                                 &sys->resources);
-}
 void __init iop3xx_atu_setup(void)
 {
        /* BAR 0 ( Disabled ) */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
index c7f5169a6a54..36c8989d9de6 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
@@ -256,13 +256,13 @@
 #define MX51_PAD_NANDF_RB1__GPIO3_9             IOMUX_PAD(0x4fc, 0x120, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 #define MX51_PAD_NANDF_RB1__NANDF_RB1           IOMUX_PAD(0x4fc, 0x120, 0, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_NANDF_RB1__PATA_IORDY          IOMUX_PAD(0x4fc, 0x120, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB1__SD4_CMD             IOMUX_PAD(0x4fc, 0x120, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_NANDF_RB1__SD4_CMD             IOMUX_PAD(0x4fc, 0x120, 0x15, __NA_, 0, MX51_SDHCI_PAD_CTRL)
 #define MX51_PAD_NANDF_RB2__DISP2_WAIT          IOMUX_PAD(0x500, 0x124, 5, 0x9a8, 0, NO_PAD_CTRL)
 #define MX51_PAD_NANDF_RB2__ECSPI2_SCLK         IOMUX_PAD(0x500, 0x124, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)
 #define MX51_PAD_NANDF_RB2__FEC_COL             IOMUX_PAD(0x500, 0x124, 1, 0x94c, 0, MX51_PAD_CTRL_2)
 #define MX51_PAD_NANDF_RB2__GPIO3_10            IOMUX_PAD(0x500, 0x124, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 #define MX51_PAD_NANDF_RB2__NANDF_RB2           IOMUX_PAD(0x500, 0x124, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB2__USBH3_H3_DP         IOMUX_PAD(0x500, 0x124, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB2__USBH3_H3_DP         IOMUX_PAD(0x500, 0x124, 0x17, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_NANDF_RB2__USBH3_NXT           IOMUX_PAD(0x500, 0x124, 6, 0xa20, 0, NO_PAD_CTRL)
 #define MX51_PAD_NANDF_RB3__DISP1_WAIT          IOMUX_PAD(0x504, 0x128, 5, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_NANDF_RB3__ECSPI2_MISO         IOMUX_PAD(0x504, 0x128, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)
@@ -270,7 +270,7 @@
 #define MX51_PAD_NANDF_RB3__GPIO3_11            IOMUX_PAD(0x504, 0x128, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 #define MX51_PAD_NANDF_RB3__NANDF_RB3           IOMUX_PAD(0x504, 0x128, 0, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_NANDF_RB3__USBH3_CLK           IOMUX_PAD(0x504, 0x128, 6, 0x9f8, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RB3__USBH3_H3_DM         IOMUX_PAD(0x504, 0x128, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB3__USBH3_H3_DM         IOMUX_PAD(0x504, 0x128, 0x17, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_GPIO_NAND__GPIO_NAND           IOMUX_PAD(0x514, 0x12c, 0, 0x998, 0, MX51_GPIO_PAD_CTRL)
 #define MX51_PAD_GPIO_NAND__PATA_INTRQ          IOMUX_PAD(0x514, 0x12c, 1, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_NANDF_CS0__GPIO3_16            IOMUX_PAD(0x518, 0x130, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
@@ -283,13 +283,13 @@
 #define MX51_PAD_NANDF_CS2__NANDF_CS2           IOMUX_PAD(0x520, 0x138, 0, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_NANDF_CS2__PATA_CS_0           IOMUX_PAD(0x520, 0x138, 1, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_NANDF_CS2__SD4_CLK             IOMUX_PAD(0x520, 0x138, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)
-#define MX51_PAD_NANDF_CS2__USBH3_H1_DP         IOMUX_PAD(0x520, 0x138, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS2__USBH3_H1_DP         IOMUX_PAD(0x520, 0x138, 0x17, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_NANDF_CS3__FEC_MDC             IOMUX_PAD(0x524, 0x13c, 2, __NA_, 0, MX51_PAD_CTRL_5)
 #define MX51_PAD_NANDF_CS3__GPIO3_19            IOMUX_PAD(0x524, 0x13c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 #define MX51_PAD_NANDF_CS3__NANDF_CS3           IOMUX_PAD(0x524, 0x13c, 0, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_NANDF_CS3__PATA_CS_1           IOMUX_PAD(0x524, 0x13c, 1, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_NANDF_CS3__SD4_DAT0            IOMUX_PAD(0x524, 0x13c, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_NANDF_CS3__USBH3_H1_DM         IOMUX_PAD(0x524, 0x13c, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS3__USBH3_H1_DM         IOMUX_PAD(0x524, 0x13c, 0x17, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_NANDF_CS4__FEC_TDATA1          IOMUX_PAD(0x528, 0x140, 2, __NA_, 0, MX51_PAD_CTRL_5)
 #define MX51_PAD_NANDF_CS4__GPIO3_20            IOMUX_PAD(0x528, 0x140, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 #define MX51_PAD_NANDF_CS4__NANDF_CS4           IOMUX_PAD(0x528, 0x140, 0, __NA_, 0, NO_PAD_CTRL)
@@ -316,7 +316,7 @@
 #define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK      IOMUX_PAD(0x538, 0x150, 1, 0x974, 0, MX51_PAD_CTRL_4)
 #define MX51_PAD_NANDF_RDY_INT__GPIO3_24        IOMUX_PAD(0x538, 0x150, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 #define MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT   IOMUX_PAD(0x538, 0x150, 0, 0x938, 0, NO_PAD_CTRL)
-#define MX51_PAD_NANDF_RDY_INT__SD3_CMD         IOMUX_PAD(0x538, 0x150, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL)
+#define MX51_PAD_NANDF_RDY_INT__SD3_CMD         IOMUX_PAD(0x538, 0x150, 0x15, __NA_, 0, MX51_SDHCI_PAD_CTRL)
 #define MX51_PAD_NANDF_D15__ECSPI2_MOSI         IOMUX_PAD(0x53c, 0x154, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)
 #define MX51_PAD_NANDF_D15__GPIO3_25            IOMUX_PAD(0x53c, 0x154, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 #define MX51_PAD_NANDF_D15__NANDF_D15           IOMUX_PAD(0x53c, 0x154, 0, __NA_, 0, NO_PAD_CTRL)
@@ -672,23 +672,23 @@
 #define MX51_PAD_DISP2_DAT5__DISP2_DAT5         IOMUX_PAD(0x770, 0x368, 0, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_DISP2_DAT6__DISP2_DAT6         IOMUX_PAD(0x774, 0x36c, 0, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_DISP2_DAT6__FEC_TDATA1         IOMUX_PAD(0x774, 0x36c, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_DISP2_DAT6__GPIO1_19           IOMUX_PAD(0x774, 0x36c, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT6__GPIO1_19           IOMUX_PAD(0x774, 0x36c, 5, __NA_, 0, MX51_GPIO_PAD_CTRL)
 #define MX51_PAD_DISP2_DAT6__KEY_ROW4           IOMUX_PAD(0x774, 0x36c, 4, 0x9d0, 1, NO_PAD_CTRL)
 #define MX51_PAD_DISP2_DAT6__USBH3_STP          IOMUX_PAD(0x774, 0x36c, 3, 0xa24, 1, NO_PAD_CTRL)
 #define MX51_PAD_DISP2_DAT7__DISP2_DAT7         IOMUX_PAD(0x778, 0x370, 0, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_DISP2_DAT7__FEC_TDATA2         IOMUX_PAD(0x778, 0x370, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_DISP2_DAT7__GPIO1_29           IOMUX_PAD(0x778, 0x370, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT7__GPIO1_29           IOMUX_PAD(0x778, 0x370, 5, __NA_, 0, MX51_GPIO_PAD_CTRL)
 #define MX51_PAD_DISP2_DAT7__KEY_ROW5           IOMUX_PAD(0x778, 0x370, 4, 0x9d4, 1, NO_PAD_CTRL)
 #define MX51_PAD_DISP2_DAT7__USBH3_NXT          IOMUX_PAD(0x778, 0x370, 3, 0xa20, 1, NO_PAD_CTRL)
 #define MX51_PAD_DISP2_DAT8__DISP2_DAT8         IOMUX_PAD(0x77c, 0x374, 0, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_DISP2_DAT8__FEC_TDATA3         IOMUX_PAD(0x77c, 0x374, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_DISP2_DAT8__GPIO1_30           IOMUX_PAD(0x77c, 0x374, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT8__GPIO1_30           IOMUX_PAD(0x77c, 0x374, 5, __NA_, 0, MX51_GPIO_PAD_CTRL)
 #define MX51_PAD_DISP2_DAT8__KEY_ROW6           IOMUX_PAD(0x77c, 0x374, 4, 0x9d8, 1, NO_PAD_CTRL)
 #define MX51_PAD_DISP2_DAT8__USBH3_DATA0        IOMUX_PAD(0x77c, 0x374, 3, 0x9fc, 1, NO_PAD_CTRL)
 #define MX51_PAD_DISP2_DAT9__AUD6_RXC           IOMUX_PAD(0x780, 0x378, 4, 0x8f4, 1, NO_PAD_CTRL)
 #define MX51_PAD_DISP2_DAT9__DISP2_DAT9         IOMUX_PAD(0x780, 0x378, 0, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_DISP2_DAT9__FEC_TX_EN          IOMUX_PAD(0x780, 0x378, 2, __NA_, 0, MX51_PAD_CTRL_5)
-#define MX51_PAD_DISP2_DAT9__GPIO1_31           IOMUX_PAD(0x780, 0x378, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT9__GPIO1_31           IOMUX_PAD(0x780, 0x378, 5, __NA_, 0, MX51_GPIO_PAD_CTRL)
 #define MX51_PAD_DISP2_DAT9__USBH3_DATA1        IOMUX_PAD(0x780, 0x378, 3, 0xa00, 1, NO_PAD_CTRL)
 #define MX51_PAD_DISP2_DAT10__DISP2_DAT10       IOMUX_PAD(0x784, 0x37c, 0, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_DISP2_DAT10__DISP2_SER_CS      IOMUX_PAD(0x784, 0x37c, 5, __NA_, 0, NO_PAD_CTRL)
@@ -698,7 +698,7 @@
 #define MX51_PAD_DISP2_DAT11__AUD6_TXD          IOMUX_PAD(0x788, 0x380, 4, 0x8f0, 1, NO_PAD_CTRL)
 #define MX51_PAD_DISP2_DAT11__DISP2_DAT11       IOMUX_PAD(0x788, 0x380, 0, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_DISP2_DAT11__FEC_RX_CLK        IOMUX_PAD(0x788, 0x380, 2, 0x968, 1, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT11__GPIO1_10          IOMUX_PAD(0x788, 0x380, 7, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT11__GPIO1_10          IOMUX_PAD(0x788, 0x380, 7, __NA_, 0, MX51_GPIO_PAD_CTRL)
 #define MX51_PAD_DISP2_DAT11__USBH3_DATA3       IOMUX_PAD(0x788, 0x380, 3, 0xa08, 1, NO_PAD_CTRL)
 #define MX51_PAD_DISP2_DAT12__AUD6_RXD          IOMUX_PAD(0x78c, 0x384, 4, 0x8ec, 1, NO_PAD_CTRL)
 #define MX51_PAD_DISP2_DAT12__DISP2_DAT12       IOMUX_PAD(0x78c, 0x384, 0, __NA_, 0, NO_PAD_CTRL)
@@ -746,16 +746,16 @@
 #define MX51_PAD_SD1_DATA3__CSPI_SS1            IOMUX_PAD(0x7b0, 0x3a8, 2, 0x920, 1, MX51_ECSPI_PAD_CTRL)
 #define MX51_PAD_SD1_DATA3__SD1_DATA3           IOMUX_PAD(0x7b0, 0x3a8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
 #define MX51_PAD_GPIO1_0__CSPI_SS2              IOMUX_PAD(0x7b4, 0x3ac, 2, 0x924, 0, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_GPIO1_0__GPIO1_0               IOMUX_PAD(0x7b4, 0x3ac, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_0__GPIO1_0               IOMUX_PAD(0x7b4, 0x3ac, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
 #define MX51_PAD_GPIO1_0__SD1_CD                IOMUX_PAD(0x7b4, 0x3ac, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL)
 #define MX51_PAD_GPIO1_1__CSPI_MISO             IOMUX_PAD(0x7b8, 0x3b0, 2, 0x918, 2, MX51_ECSPI_PAD_CTRL)
-#define MX51_PAD_GPIO1_1__GPIO1_1               IOMUX_PAD(0x7b8, 0x3b0, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_1__GPIO1_1               IOMUX_PAD(0x7b8, 0x3b0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
 #define MX51_PAD_GPIO1_1__SD1_WP                IOMUX_PAD(0x7b8, 0x3b0, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL)
 #define MX51_PAD_EIM_DA12__EIM_DA12             IOMUX_PAD(__NA_, 0x04c, 0, 0x000, 0, NO_PAD_CTRL)
 #define MX51_PAD_EIM_DA13__EIM_DA13             IOMUX_PAD(__NA_, 0x050, 0, 0x000, 0, NO_PAD_CTRL)
 #define MX51_PAD_EIM_DA14__EIM_DA14             IOMUX_PAD(__NA_, 0x054, 0, 0x000, 0, NO_PAD_CTRL)
 #define MX51_PAD_EIM_DA15__EIM_DA15             IOMUX_PAD(__NA_, 0x058, 0, 0x000, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_CMD__CSPI_MOSI             IOMUX_PAD(__NA_, 0x3b4, 2, 0x91c, 3, MX51_ECSPI_PAD_CTRL)
+#define MX51_PAD_SD2_CMD__CSPI_MOSI             IOMUX_PAD(0x7bc, 0x3b4, 2, 0x91c, 3, MX51_ECSPI_PAD_CTRL)
 #define MX51_PAD_SD2_CMD__I2C1_SCL              IOMUX_PAD(0x7bc, 0x3b4, 0x11, 0x9b0, 2, MX51_I2C_PAD_CTRL)
 #define MX51_PAD_SD2_CMD__SD2_CMD               IOMUX_PAD(0x7bc, 0x3b4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
 #define MX51_PAD_SD2_CLK__CSPI_SCLK             IOMUX_PAD(0x7c0, 0x3b8, 2, 0x914, 3, MX51_ECSPI_PAD_CTRL)
@@ -766,19 +766,19 @@
 #define MX51_PAD_SD2_DATA0__SD2_DATA0           IOMUX_PAD(0x7c4, 0x3bc, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
 #define MX51_PAD_SD2_DATA1__SD1_DAT5            IOMUX_PAD(0x7c8, 0x3c0, 1, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_SD2_DATA1__SD2_DATA1           IOMUX_PAD(0x7c8, 0x3c0, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_SD2_DATA1__USBH3_H2_DP         IOMUX_PAD(0x7c8, 0x3c0, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_DATA1__USBH3_H2_DP         IOMUX_PAD(0x7c8, 0x3c0, 0x12, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_SD2_DATA2__SD1_DAT6            IOMUX_PAD(0x7cc, 0x3c4, 1, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_SD2_DATA2__SD2_DATA2           IOMUX_PAD(0x7cc, 0x3c4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
-#define MX51_PAD_SD2_DATA2__USBH3_H2_DM         IOMUX_PAD(0x7cc, 0x3c4, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_DATA2__USBH3_H2_DM         IOMUX_PAD(0x7cc, 0x3c4, 0x12, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_SD2_DATA3__CSPI_SS2            IOMUX_PAD(0x7d0, 0x3c8, 2, 0x924, 1, MX51_ECSPI_PAD_CTRL)
 #define MX51_PAD_SD2_DATA3__SD1_DAT7            IOMUX_PAD(0x7d0, 0x3c8, 1, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_SD2_DATA3__SD2_DATA3           IOMUX_PAD(0x7d0, 0x3c8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
 #define MX51_PAD_GPIO1_2__CCM_OUT_2             IOMUX_PAD(0x7d4, 0x3cc, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_2__GPIO1_2               IOMUX_PAD(0x7d4, 0x3cc, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_2__GPIO1_2               IOMUX_PAD(0x7d4, 0x3cc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
 #define MX51_PAD_GPIO1_2__I2C2_SCL              IOMUX_PAD(0x7d4, 0x3cc, 0x12, 0x9b8, 3, MX51_I2C_PAD_CTRL)
 #define MX51_PAD_GPIO1_2__PLL1_BYP              IOMUX_PAD(0x7d4, 0x3cc, 7, 0x90c, 1, NO_PAD_CTRL)
 #define MX51_PAD_GPIO1_2__PWM1_PWMO             IOMUX_PAD(0x7d4, 0x3cc, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_3__GPIO1_3               IOMUX_PAD(0x7d8, 0x3d0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_3__GPIO1_3               IOMUX_PAD(0x7d8, 0x3d0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
 #define MX51_PAD_GPIO1_3__I2C2_SDA              IOMUX_PAD(0x7d8, 0x3d0, 0x12, 0x9bc, 3, MX51_I2C_PAD_CTRL)
 #define MX51_PAD_GPIO1_3__PLL2_BYP              IOMUX_PAD(0x7d8, 0x3d0, 7, 0x910, 1, NO_PAD_CTRL)
 #define MX51_PAD_GPIO1_3__PWM2_PWMO             IOMUX_PAD(0x7d8, 0x3d0, 1, __NA_, 0, NO_PAD_CTRL)
@@ -786,27 +786,27 @@
 #define MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B   IOMUX_PAD(0x7fc, 0x3d4, 1, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_GPIO1_4__DISP2_EXT_CLK         IOMUX_PAD(0x804, 0x3d8, 4, 0x908, 1, NO_PAD_CTRL)
 #define MX51_PAD_GPIO1_4__EIM_RDY               IOMUX_PAD(0x804, 0x3d8, 3, 0x938, 1, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_4__GPIO1_4               IOMUX_PAD(0x804, 0x3d8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_4__GPIO1_4               IOMUX_PAD(0x804, 0x3d8, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
 #define MX51_PAD_GPIO1_4__WDOG1_WDOG_B          IOMUX_PAD(0x804, 0x3d8, 2, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_GPIO1_5__CSI2_MCLK             IOMUX_PAD(0x808, 0x3dc, 6, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_GPIO1_5__DISP2_PIN16           IOMUX_PAD(0x808, 0x3dc, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_5__GPIO1_5               IOMUX_PAD(0x808, 0x3dc, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_5__GPIO1_5               IOMUX_PAD(0x808, 0x3dc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
 #define MX51_PAD_GPIO1_5__WDOG2_WDOG_B          IOMUX_PAD(0x808, 0x3dc, 2, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_GPIO1_6__DISP2_PIN17           IOMUX_PAD(0x80c, 0x3e0, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_6__GPIO1_6               IOMUX_PAD(0x80c, 0x3e0, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_6__GPIO1_6               IOMUX_PAD(0x80c, 0x3e0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
 #define MX51_PAD_GPIO1_6__REF_EN_B              IOMUX_PAD(0x80c, 0x3e0, 3, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_GPIO1_7__CCM_OUT_0             IOMUX_PAD(0x810, 0x3e4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_7__GPIO1_7               IOMUX_PAD(0x810, 0x3e4, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_7__GPIO1_7               IOMUX_PAD(0x810, 0x3e4, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
 #define MX51_PAD_GPIO1_7__SD2_WP                IOMUX_PAD(0x810, 0x3e4, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL)
 #define MX51_PAD_GPIO1_7__SPDIF_OUT1            IOMUX_PAD(0x810, 0x3e4, 2, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_GPIO1_8__CSI2_DATA_EN          IOMUX_PAD(0x814, 0x3e8, 2, 0x99c, 2, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_8__GPIO1_8               IOMUX_PAD(0x814, 0x3e8, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_8__GPIO1_8               IOMUX_PAD(0x814, 0x3e8, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
 #define MX51_PAD_GPIO1_8__SD2_CD                IOMUX_PAD(0x814, 0x3e8, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL)
 #define MX51_PAD_GPIO1_8__USBH3_PWR             IOMUX_PAD(0x814, 0x3e8, 1, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_GPIO1_9__CCM_OUT_1             IOMUX_PAD(0x818, 0x3ec, 3, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_GPIO1_9__DISP2_D1_CS           IOMUX_PAD(0x818, 0x3ec, 2, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_GPIO1_9__DISP2_SER_CS          IOMUX_PAD(0x818, 0x3ec, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_9__GPIO1_9               IOMUX_PAD(0x818, 0x3ec, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_9__GPIO1_9               IOMUX_PAD(0x818, 0x3ec, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
 #define MX51_PAD_GPIO1_9__SD2_LCTL              IOMUX_PAD(0x818, 0x3ec, 6, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_GPIO1_9__USBH3_OC              IOMUX_PAD(0x818, 0x3ec, 1, __NA_, 0, NO_PAD_CTRL)
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx53.h b/arch/arm/plat-mxc/include/mach/iomux-mx53.h
index 527f8fe3e31b..9761e003bde2 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx53.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx53.h
@@ -573,7 +573,7 @@
 #define MX53_PAD_EIM_D28__UART2_CTS                     IOMUX_PAD(0x494, 0x14C, 2, __NA_, 0, MX53_UART_PAD_CTRL)
 #define MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO            IOMUX_PAD(0x494, 0x14C, 3, 0x82C, 1, NO_PAD_CTRL)
 #define MX53_PAD_EIM_D28__CSPI_MOSI                     IOMUX_PAD(0x494, 0x14C, 4, 0x788, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D28__I2C1_SDA                      IOMUX_PAD(0x494, 0x14C, 5 | IOMUX_CONFIG_SION, 0x818, 1, PAD_CTRL_I2C)
+#define MX53_PAD_EIM_D28__I2C1_SDA                      IOMUX_PAD(0x494, 0x14C, 5 | IOMUX_CONFIG_SION, 0x818, 1, NO_PAD_CTRL)
 #define MX53_PAD_EIM_D28__IPU_EXT_TRIG                  IOMUX_PAD(0x494, 0x14C, 6, __NA_, 0, NO_PAD_CTRL)
 #define MX53_PAD_EIM_D28__IPU_DI0_PIN13                 IOMUX_PAD(0x494, 0x14C, 7, __NA_, 0, NO_PAD_CTRL)
 #define MX53_PAD_EIM_D29__EMI_WEIM_D_29                 IOMUX_PAD(0x498, 0x150, 0, __NA_, 0, NO_PAD_CTRL)
@@ -1187,7 +1187,7 @@
 #define MX53_PAD_GPIO_8__ESAI1_TX5_RX0                  IOMUX_PAD(0x6C8, 0x338, 0, 0x7F8, 1, NO_PAD_CTRL)
 #define MX53_PAD_GPIO_8__GPIO1_8                        IOMUX_PAD(0x6C8, 0x338, 1, __NA_, 0, NO_PAD_CTRL)
 #define MX53_PAD_GPIO_8__EPIT2_EPITO                    IOMUX_PAD(0x6C8, 0x338, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_8__CAN1_RXCAN                     IOMUX_PAD(0x6C8, 0x338, 3, 0x760, 3, NO_PAD_CTRL)
+#define MX53_PAD_GPIO_8__CAN1_RXCAN                     IOMUX_PAD(0x6C8, 0x338, 3, 0x760, 2, NO_PAD_CTRL)
 #define MX53_PAD_GPIO_8__UART2_RXD_MUX                  IOMUX_PAD(0x6C8, 0x338, 4, 0x880, 5, MX53_UART_PAD_CTRL)
 #define MX53_PAD_GPIO_8__FIRI_TXD                       IOMUX_PAD(0x6C8, 0x338, 5, __NA_, 0, NO_PAD_CTRL)
 #define MX53_PAD_GPIO_8__SPDIF_SRCLK                    IOMUX_PAD(0x6C8, 0x338, 6, __NA_, 0, NO_PAD_CTRL)
diff --git a/arch/arm/plat-nomadik/include/plat/gpio-nomadik.h b/arch/arm/plat-nomadik/include/plat/gpio-nomadik.h
index 9605bf227df9..826de74bfdd1 100644
--- a/arch/arm/plat-nomadik/include/plat/gpio-nomadik.h
+++ b/arch/arm/plat-nomadik/include/plat/gpio-nomadik.h
@@ -29,6 +29,7 @@
 #define NMK_GPIO_SLPC   0x1c
 #define NMK_GPIO_AFSLA  0x20
 #define NMK_GPIO_AFSLB  0x24
+#define NMK_GPIO_LOWEMI 0x28
 #define NMK_GPIO_RIMSC  0x40
 #define NMK_GPIO_FIMSC  0x44
@@ -61,7 +62,14 @@ enum nmk_gpio_slpm {
 extern int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode);
 extern int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull);
+#ifdef CONFIG_PINCTRL_NOMADIK
 extern int nmk_gpio_set_mode(int gpio, int gpio_mode);
+#else
+static inline int nmk_gpio_set_mode(int gpio, int gpio_mode)
+{
+        return -ENODEV;
+}
+#endif
 extern int nmk_gpio_get_mode(int gpio);
 extern void nmk_gpio_wakeups_suspend(void);
diff --git a/arch/arm/plat-nomadik/include/plat/pincfg.h b/arch/arm/plat-nomadik/include/plat/pincfg.h
index 22cb97d2d8ad..9c949c7c98a7 100644
--- a/arch/arm/plat-nomadik/include/plat/pincfg.h
+++ b/arch/arm/plat-nomadik/include/plat/pincfg.h
@@ -24,6 +24,7 @@
 *      bit 16..18 - SLPM pull up/down state
 *      bit 19..20 - SLPM direction
 *      bit 21..22 - SLPM Value (if output)
+ *      bit 23..25 - PDIS value (if input)
 *
 * to facilitate the definition, the following macros are provided
 *
@@ -67,6 +68,10 @@ typedef unsigned long pin_cfg_t;
 /* These two replace the above in DB8500v2+ */
 #define PIN_SLPM_WAKEUP_ENABLE  (NMK_GPIO_SLPM_WAKEUP_ENABLE << PIN_SLPM_SHIFT)
 #define PIN_SLPM_WAKEUP_DISABLE (NMK_GPIO_SLPM_WAKEUP_DISABLE << PIN_SLPM_SHIFT)
+#define PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP PIN_SLPM_WAKEUP_DISABLE
+#define PIN_SLPM_GPIO  PIN_SLPM_WAKEUP_ENABLE /* In SLPM, pin is a gpio */
+#define PIN_SLPM_ALTFUNC PIN_SLPM_WAKEUP_DISABLE /* In SLPM, pin is altfunc */
 #define PIN_DIR_SHIFT           14
 #define PIN_DIR_MASK            (0x1 << PIN_DIR_SHIFT)
@@ -105,6 +110,33 @@ typedef unsigned long pin_cfg_t;
 #define PIN_SLPM_VAL_LOW        ((1 + 0) << PIN_SLPM_VAL_SHIFT)
 #define PIN_SLPM_VAL_HIGH       ((1 + 1) << PIN_SLPM_VAL_SHIFT)
+#define PIN_SLPM_PDIS_SHIFT             23
+#define PIN_SLPM_PDIS_MASK              (0x3 << PIN_SLPM_PDIS_SHIFT)
+#define PIN_SLPM_PDIS(x)        \
+        (((x) & PIN_SLPM_PDIS_MASK) >> PIN_SLPM_PDIS_SHIFT)
+#define PIN_SLPM_PDIS_NO_CHANGE         (0 << PIN_SLPM_PDIS_SHIFT)
+#define PIN_SLPM_PDIS_DISABLED          (1 << PIN_SLPM_PDIS_SHIFT)
+#define PIN_SLPM_PDIS_ENABLED           (2 << PIN_SLPM_PDIS_SHIFT)
+#define PIN_LOWEMI_SHIFT        25
+#define PIN_LOWEMI_MASK         (0x1 << PIN_LOWEMI_SHIFT)
+#define PIN_LOWEMI(x)           (((x) & PIN_LOWEMI_MASK) >> PIN_LOWEMI_SHIFT)
+#define PIN_LOWEMI_DISABLED     (0 << PIN_LOWEMI_SHIFT)
+#define PIN_LOWEMI_ENABLED      (1 << PIN_LOWEMI_SHIFT)
+#define PIN_GPIOMODE_SHIFT      26
+#define PIN_GPIOMODE_MASK       (0x1 << PIN_GPIOMODE_SHIFT)
+#define PIN_GPIOMODE(x)         (((x) & PIN_GPIOMODE_MASK) >> PIN_GPIOMODE_SHIFT)
+#define PIN_GPIOMODE_DISABLED   (0 << PIN_GPIOMODE_SHIFT)
+#define PIN_GPIOMODE_ENABLED    (1 << PIN_GPIOMODE_SHIFT)
+#define PIN_SLEEPMODE_SHIFT     27
+#define PIN_SLEEPMODE_MASK      (0x1 << PIN_SLEEPMODE_SHIFT)
+#define PIN_SLEEPMODE(x)        (((x) & PIN_SLEEPMODE_MASK) >> PIN_SLEEPMODE_SHIFT)
+#define PIN_SLEEPMODE_DISABLED  (0 << PIN_SLEEPMODE_SHIFT)
+#define PIN_SLEEPMODE_ENABLED   (1 << PIN_SLEEPMODE_SHIFT)
 /* Shortcuts.  Use these instead of separate DIR, PULL, and VAL.  */
 #define PIN_INPUT_PULLDOWN      (PIN_DIR_INPUT | PIN_PULL_DOWN)
 #define PIN_INPUT_PULLUP        (PIN_DIR_INPUT | PIN_PULL_UP)
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index c0fe2757b695..ed8605f01155 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -9,9 +9,6 @@ obj-m :=
 obj-n :=
 obj-  :=
-# OCPI interconnect support for 1710, 1610 and 5912
-obj-$(CONFIG_ARCH_OMAP16XX) += ocpi.o
 # omap_device support (OMAP2+ only at the moment)
 obj-$(CONFIG_ARCH_OMAP2) += omap_device.o
 obj-$(CONFIG_ARCH_OMAP3) += omap_device.o
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index 8506cbb7fea4..62ec5c452792 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -398,32 +398,6 @@ struct clk dummy_ck = {
        .ops    = &clkops_null,
 };
-#ifdef CONFIG_CPU_FREQ
-void clk_init_cpufreq_table(struct cpufreq_frequency_table **table)
-{
-        unsigned long flags;
-        if (!arch_clock || !arch_clock->clk_init_cpufreq_table)
-                return;
-        spin_lock_irqsave(&clockfw_lock, flags);
-        arch_clock->clk_init_cpufreq_table(table);
-        spin_unlock_irqrestore(&clockfw_lock, flags);
-}
-void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table)
-{
-        unsigned long flags;
-        if (!arch_clock || !arch_clock->clk_exit_cpufreq_table)
-                return;
-        spin_lock_irqsave(&clockfw_lock, flags);
-        arch_clock->clk_exit_cpufreq_table(table);
-        spin_unlock_irqrestore(&clockfw_lock, flags);
-}
-#endif
 /*
 *
 */
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index f1e46ea6b81d..0a9b9a970113 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -20,6 +20,7 @@
 #include <plat/board.h>
 #include <plat/vram.h>
 #include <plat/dsp.h>
+#include <plat/dma.h>
 #include <plat/omap-secure.h>
diff --git a/arch/arm/plat-omap/counter_32k.c b/arch/arm/plat-omap/counter_32k.c
index 5068fe5a6910..44ae077dbc28 100644
--- a/arch/arm/plat-omap/counter_32k.c
+++ b/arch/arm/plat-omap/counter_32k.c
@@ -19,6 +19,7 @@
 #include <linux/io.h>
 #include <linux/clocksource.h>
+#include <asm/mach/time.h>
 #include <asm/sched_clock.h>
 #include <plat/hardware.h>
@@ -43,7 +44,7 @@ static u32 notrace omap_32k_read_sched_clock(void)
 }
 /**
- * read_persistent_clock -  Return time from a persistent clock.
+ * omap_read_persistent_clock -  Return time from a persistent clock.
 *
 * Reads the time from a source which isn't disabled during PM, the
 * 32k sync timer.  Convert the cycles elapsed since last read into
@@ -52,7 +53,7 @@ static u32 notrace omap_32k_read_sched_clock(void)
 static struct timespec persistent_ts;
 static cycles_t cycles, last_cycles;
 static unsigned int persistent_mult, persistent_shift;
-void read_persistent_clock(struct timespec *ts)
+static void omap_read_persistent_clock(struct timespec *ts)
 {
        unsigned long long nsecs;
        cycles_t delta;
@@ -116,6 +117,7 @@ int __init omap_init_clocksource_32k(void)
                        printk(err, "32k_counter");
                setup_sched_clock(omap_32k_read_sched_clock, 32, 32768);
+                register_persistent_clock(NULL, omap_read_persistent_clock);
        }
        return 0;
 }
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c
index 60278f47c0bd..09b07d252892 100644
--- a/arch/arm/plat-omap/devices.c
+++ b/arch/arm/plat-omap/devices.c
@@ -167,8 +167,8 @@ void __init omap_dsp_reserve_sdram_memblock(void)
        paddr = arm_memblock_steal(size, SZ_1M);
        if (!paddr) {
-                pr_err("%s: failed to reserve %x bytes\n",
+                pr_err("%s: failed to reserve %llx bytes\n",
-                                __func__, size);
+                                __func__, (unsigned long long)size);
                return;
        }
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index ecdb3da0dea9..987e6101267d 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -41,6 +41,15 @@
 #include <plat/tc.h>
+/*
+ * MAX_LOGICAL_DMA_CH_COUNT: the maximum number of logical DMA
+ * channels that an instance of the SDMA IP block can support.  Used
+ * to size arrays.  (The actual maximum on a particular SoC may be less
+ * than this -- for example, OMAP1 SDMA instances only support 17 logical
+ * DMA channels.)
+ */
+#define MAX_LOGICAL_DMA_CH_COUNT                32
 #undef DEBUG
 #ifndef CONFIG_ARCH_OMAP1
@@ -883,7 +892,7 @@ void omap_start_dma(int lch)
        if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
                int next_lch, cur_lch;
-                char dma_chan_link_map[dma_lch_count];
+                char dma_chan_link_map[MAX_LOGICAL_DMA_CH_COUNT];
                dma_chan_link_map[lch] = 1;
                /* Set the link register of the first channel */
@@ -916,6 +925,13 @@ void omap_start_dma(int lch)
                        l |= OMAP_DMA_CCR_BUFFERING_DISABLE;
        l |= OMAP_DMA_CCR_EN;
+        /*
+         * As dma_write() uses IO accessors which are weakly ordered, there
+         * is no guarantee that data in coherent DMA memory will be visible
+         * to the DMA device.  Add a memory barrier here to ensure that any
+         * such data is visible prior to enabling DMA.
+         */
+        mb();
        p->dma_write(l, CCR, lch);
        dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
@@ -965,9 +981,16 @@ void omap_stop_dma(int lch)
                p->dma_write(l, CCR, lch);
        }
+        /*
+         * Ensure that data transferred by DMA is visible to any access
+         * after DMA has been disabled.  This is important for coherent
+         * DMA regions.
+         */
+        mb();
        if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
                int next_lch, cur_lch = lch;
-                char dma_chan_link_map[dma_lch_count];
+                char dma_chan_link_map[MAX_LOGICAL_DMA_CH_COUNT];
                memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
                do {
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 652139c0339e..c4ed35e89fbd 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -349,11 +349,12 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_start);
 int omap_dm_timer_stop(struct omap_dm_timer *timer)
 {
        unsigned long rate = 0;
-        struct dmtimer_platform_data *pdata = timer->pdev->dev.platform_data;
+        struct dmtimer_platform_data *pdata;
        if (unlikely(!timer))
                return -EINVAL;
+        pdata = timer->pdev->dev.platform_data;
        if (!pdata->needs_manual_reset)
                rate = clk_get_rate(timer->fclk);
diff --git a/arch/arm/plat-omap/include/plat/board.h b/arch/arm/plat-omap/include/plat/board.h
index d5eb4c87db9d..4814c5b65306 100644
--- a/arch/arm/plat-omap/include/plat/board.h
+++ b/arch/arm/plat-omap/include/plat/board.h
@@ -91,6 +91,8 @@ struct omap_usb_config {
        u32 (*usb0_init)(unsigned nwires, unsigned is_device);
        u32 (*usb1_init)(unsigned nwires);
        u32 (*usb2_init)(unsigned nwires, unsigned alt_pingroup);
+        int (*ocpi_enable)(void);
 };
 struct omap_lcd_config {
diff --git a/arch/arm/plat-omap/include/plat/clkdev_omap.h b/arch/arm/plat-omap/include/plat/clkdev_omap.h
index b299b8d201c8..d0ed8c443a63 100644
--- a/arch/arm/plat-omap/include/plat/clkdev_omap.h
+++ b/arch/arm/plat-omap/include/plat/clkdev_omap.h
@@ -34,8 +34,7 @@ struct omap_clk {
 #define CK_243X         (1 << 5)        /* 243x, 253x */
 #define CK_3430ES1      (1 << 6)        /* 34xxES1 only */
 #define CK_3430ES2PLUS  (1 << 7)        /* 34xxES2, ES3, non-Sitara 35xx only */
-#define CK_3505         (1 << 8)
+#define CK_AM35XX       (1 << 9)        /* Sitara AM35xx */
-#define CK_3517         (1 << 9)
 #define CK_36XX         (1 << 10)       /* 36xx/37xx-specific clocks */
 #define CK_443X         (1 << 11)
 #define CK_TI816X       (1 << 12)
@@ -44,7 +43,6 @@ struct omap_clk {
 #define CK_34XX         (CK_3430ES1 | CK_3430ES2PLUS)
-#define CK_AM35XX       (CK_3505 | CK_3517)     /* all Sitara AM35xx */
 #define CK_3XXX         (CK_34XX | CK_AM35XX | CK_36XX)
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index 240a7b9fd946..d0ef57c1d71b 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -272,8 +272,6 @@ struct clk {
 #endif
 };
-struct cpufreq_frequency_table;
 struct clk_functions {
        int             (*clk_enable)(struct clk *clk);
        void            (*clk_disable)(struct clk *clk);
@@ -283,10 +281,6 @@ struct clk_functions {
        void            (*clk_allow_idle)(struct clk *clk);
        void            (*clk_deny_idle)(struct clk *clk);
        void            (*clk_disable_unused)(struct clk *clk);
-#ifdef CONFIG_CPU_FREQ
-        void            (*clk_init_cpufreq_table)(struct cpufreq_frequency_table **);
-        void            (*clk_exit_cpufreq_table)(struct cpufreq_frequency_table **);
-#endif
 };
 extern int mpurate;
@@ -301,10 +295,6 @@ extern void recalculate_root_clocks(void);
 extern unsigned long followparent_recalc(struct clk *clk);
 extern void clk_enable_init_clocks(void);
 unsigned long omap_fixed_divisor_recalc(struct clk *clk);
-#ifdef CONFIG_CPU_FREQ
-extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
-extern void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table);
-#endif
 extern struct clk *omap_clk_get_by_name(const char *name);
 extern int omap_clk_enable_autoidle_all(void);
 extern int omap_clk_disable_autoidle_all(void);
diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h
index b4d7ec3fbfbe..a557b8484e6c 100644
--- a/arch/arm/plat-omap/include/plat/common.h
+++ b/arch/arm/plat-omap/include/plat/common.h
@@ -32,6 +32,8 @@
 extern int __init omap_init_clocksource_32k(void);
+extern void __init omap_check_revision(void);
 extern void omap_reserve(void);
 extern int omap_dss_reset(struct omap_hwmod *);
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index dc6a86bf2172..4bdf14ec6747 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -445,6 +445,7 @@ IS_OMAP_TYPE(3517, 0x3517)
 #define OMAP446X_CLASS          0x44600044
 #define OMAP4460_REV_ES1_0      (OMAP446X_CLASS | (0x10 << 8))
+#define OMAP4460_REV_ES1_1      (OMAP446X_CLASS | (0x11 << 8))
 #define OMAP447X_CLASS          0x44700044
 #define OMAP4470_REV_ES1_0      (OMAP447X_CLASS | (0x10 << 8))
diff --git a/arch/arm/plat-omap/include/plat/dma.h b/arch/arm/plat-omap/include/plat/dma.h
index dc562a5c0a8a..42afb4c45517 100644
--- a/arch/arm/plat-omap/include/plat/dma.h
+++ b/arch/arm/plat-omap/include/plat/dma.h
@@ -442,6 +442,7 @@ struct omap_system_dma_plat_info {
        u32 (*dma_read)(int reg, int lch);
 };
+extern void __init omap_init_consistent_dma_size(void);
 extern void omap_set_dma_priority(int lch, int dst_port, int priority);
 extern int omap_request_dma(int dev_id, const char *dev_name,
                        void (*callback)(int lch, u16 ch_status, void *data),
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
index 9418f00b6c38..bdf871a84d62 100644
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -259,7 +259,7 @@ struct omap_dm_timer {
        unsigned long phys_base;
        int id;
        int irq;
-        struct clk *iclk, *fclk;
+        struct clk *fclk;
        void __iomem    *io_base;
        void __iomem    *sys_stat;      /* TISTAT timer status */
@@ -316,12 +316,12 @@ static inline void __omap_dm_timer_init_regs(struct omap_dm_timer *timer)
                                OMAP_TIMER_V1_SYS_STAT_OFFSET;
                timer->irq_stat = timer->io_base + OMAP_TIMER_V1_STAT_OFFSET;
                timer->irq_ena = timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET;
-                timer->irq_dis = 0;
+                timer->irq_dis = NULL;
                timer->pend = timer->io_base + _OMAP_TIMER_WRITE_PEND_OFFSET;
                timer->func_base = timer->io_base;
        } else {
                timer->revision = 2;
-                timer->sys_stat = 0;
+                timer->sys_stat = NULL;
                timer->irq_stat = timer->io_base + OMAP_TIMER_V2_IRQSTATUS;
                timer->irq_ena = timer->io_base + OMAP_TIMER_V2_IRQENABLE_SET;
                timer->irq_dis = timer->io_base + OMAP_TIMER_V2_IRQENABLE_CLR;
diff --git a/arch/arm/plat-omap/include/plat/hdq1w.h b/arch/arm/plat-omap/include/plat/hdq1w.h
new file mode 100644
index 000000000000..0c1efc846d8d
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/hdq1w.h
@@ -0,0 +1,36 @@
+/*
+ * Shared macros and function prototypes for the HDQ1W/1-wire IP block
+ *
+ * Copyright (C) 2012 Texas Instruments, Inc.
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ */
+#ifndef ARCH_ARM_MACH_OMAP2_HDQ1W_H
+#define ARCH_ARM_MACH_OMAP2_HDQ1W_H
+#include <plat/omap_hwmod.h>
+/*
+ * XXX A future cleanup patch should modify
+ * drivers/w1/masters/omap_hdq.c to use these macros
+ */
+#define HDQ_CTRL_STATUS_OFFSET                  0x0c
+#define HDQ_CTRL_STATUS_CLOCKENABLE_SHIFT       5
+extern int omap_hdq1w_reset(struct omap_hwmod *oh);
+#endif
diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h
index 7a38750c0079..3e7ae0f0215f 100644
--- a/arch/arm/plat-omap/include/plat/mmc.h
+++ b/arch/arm/plat-omap/include/plat/mmc.h
@@ -16,6 +16,7 @@
 #include <linux/mmc/host.h>
 #include <plat/board.h>
+#include <plat/omap_hwmod.h>
 #define OMAP15XX_NR_MMC         1
 #define OMAP16XX_NR_MMC         2
@@ -195,4 +196,7 @@ static inline int omap_mmc_add(const char *name, int id, unsigned long base,
 }
 #endif
+extern int omap_msdi_reset(struct omap_hwmod *oh);
 #endif
diff --git a/arch/arm/plat-omap/include/plat/omap-serial.h b/arch/arm/plat-omap/include/plat/omap-serial.h
index 9ff444469f3d..1a52725ffcf2 100644
--- a/arch/arm/plat-omap/include/plat/omap-serial.h
+++ b/arch/arm/plat-omap/include/plat/omap-serial.h
@@ -65,7 +65,6 @@ struct omap_uart_port_info {
        bool                    dma_enabled;    /* To specify DMA Mode */
        unsigned int            uartclk;        /* UART clock rate */
        upf_t                   flags;          /* UPF_* flags */
-        u32                     errata;
        unsigned int            dma_rx_buf_size;
        unsigned int            dma_rx_timeout;
        unsigned int            autosuspend_timeout;
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index 8070145ccb98..c835b7194ff5 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -213,11 +213,17 @@ struct omap_hwmod_addr_space {
 */
 #define OCP_USER_MPU                    (1 << 0)
 #define OCP_USER_SDMA                   (1 << 1)
+#define OCP_USER_DSP                    (1 << 2)
+#define OCP_USER_IVA                    (1 << 3)
 /* omap_hwmod_ocp_if.flags bits */
 #define OCPIF_SWSUP_IDLE                (1 << 0)
 #define OCPIF_CAN_BURST                 (1 << 1)
+/* omap_hwmod_ocp_if._int_flags possibilities */
+#define _OCPIF_INT_FLAGS_REGISTERED     (1 << 0)
 /**
 * struct omap_hwmod_ocp_if - OCP interface data
 * @master: struct omap_hwmod that initiates OCP transactions on this link
@@ -229,6 +235,7 @@ struct omap_hwmod_addr_space {
 * @width: OCP data width
 * @user: initiators using this interface (see OCP_USER_* macros above)
 * @flags: OCP interface flags (see OCPIF_* macros above)
+ * @_int_flags: internal flags (see _OCPIF_INT_FLAGS* macros above)
 *
 * It may also be useful to add a tag_cnt field for OCP2.x devices.
 *
@@ -247,6 +254,7 @@ struct omap_hwmod_ocp_if {
        u8                              width;
        u8                              user;
        u8                              flags;
+        u8                              _int_flags;
 };
@@ -305,6 +313,7 @@ struct omap_hwmod_sysc_fields {
 * @rev_offs: IP block revision register offset (from module base addr)
 * @sysc_offs: OCP_SYSCONFIG register offset (from module base addr)
 * @syss_offs: OCP_SYSSTATUS register offset (from module base addr)
+ * @srst_udelay: Delay needed after doing a softreset in usecs
 * @idlemodes: One or more of {SIDLE,MSTANDBY}_{OFF,FORCE,SMART}
 * @sysc_flags: SYS{C,S}_HAS* flags indicating SYSCONFIG bits supported
 * @clockact: the default value of the module CLOCKACTIVITY bits
@@ -326,13 +335,14 @@ struct omap_hwmod_sysc_fields {
 * then this field has to be populated with the correct offset structure.
 */
 struct omap_hwmod_class_sysconfig {
-        u16 rev_offs;
+        u32 rev_offs;
-        u16 sysc_offs;
+        u32 sysc_offs;
-        u16 syss_offs;
+        u32 syss_offs;
        u16 sysc_flags;
+        struct omap_hwmod_sysc_fields *sysc_fields;
+        u8 srst_udelay;
        u8 idlemodes;
        u8 clockact;
-        struct omap_hwmod_sysc_fields *sysc_fields;
 };
 /**
@@ -474,6 +484,16 @@ struct omap_hwmod_class {
 };
 /**
+ * struct omap_hwmod_link - internal structure linking hwmods with ocp_ifs
+ * @ocp_if: OCP interface structure record pointer
+ * @node: list_head pointing to next struct omap_hwmod_link in a list
+ */
+struct omap_hwmod_link {
+        struct omap_hwmod_ocp_if        *ocp_if;
+        struct list_head                node;
+};
+/**
 * struct omap_hwmod - integration data for OMAP hardware "modules" (IP blocks)
 * @name: name of the hwmod
 * @class: struct omap_hwmod_class * to the class of this hwmod
@@ -485,12 +505,10 @@ struct omap_hwmod_class {
 * @_clk: pointer to the main struct clk (filled in at runtime)
 * @opt_clks: other device clocks that drivers can request (0..*)
 * @voltdm: pointer to voltage domain (filled in at runtime)
- * @masters: ptr to array of OCP ifs that this hwmod can initiate on
- * @slaves: ptr to array of OCP ifs that this hwmod can respond on
 * @dev_attr: arbitrary device attributes that can be passed to the driver
 * @_sysc_cache: internal-use hwmod flags
 * @_mpu_rt_va: cached register target start address (internal use)
- * @_mpu_port_index: cached MPU register target slave ID (internal use)
+ * @_mpu_port: cached MPU register target slave (internal use)
 * @opt_clks_cnt: number of @opt_clks
 * @master_cnt: number of @master entries
 * @slaves_cnt: number of @slave entries
@@ -509,6 +527,8 @@ struct omap_hwmod_class {
 *
 * Parameter names beginning with an underscore are managed internally by
 * the omap_hwmod code and should not be set during initialization.
+ *
+ * @masters and @slaves are now deprecated.
 */
 struct omap_hwmod {
        const char                      *name;
@@ -527,15 +547,15 @@ struct omap_hwmod {
        struct omap_hwmod_opt_clk       *opt_clks;
        char                            *clkdm_name;
        struct clockdomain              *clkdm;
-        struct omap_hwmod_ocp_if        **masters; /* connect to *_IA */
+        struct list_head                master_ports; /* connect to *_IA */
-        struct omap_hwmod_ocp_if        **slaves;  /* connect to *_TA */
+        struct list_head                slave_ports; /* connect to *_TA */
        void                            *dev_attr;
        u32                             _sysc_cache;
        void __iomem                    *_mpu_rt_va;
        spinlock_t                      _lock;
        struct list_head                node;
+        struct omap_hwmod_ocp_if        *_mpu_port;
        u16                             flags;
-        u8                              _mpu_port_index;
        u8                              response_lat;
        u8                              rst_lines_cnt;
        u8                              opt_clks_cnt;
@@ -547,7 +567,6 @@ struct omap_hwmod {
        u8                              _postsetup_state;
 };
-int omap_hwmod_register(struct omap_hwmod **ohs);
 struct omap_hwmod *omap_hwmod_lookup(const char *name);
 int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data),
                        void *data);
@@ -579,6 +598,8 @@ int omap_hwmod_softreset(struct omap_hwmod *oh);
 int omap_hwmod_count_resources(struct omap_hwmod *oh);
 int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res);
+int omap_hwmod_get_resource_byname(struct omap_hwmod *oh, unsigned int type,
+                                   const char *name, struct resource *res);
 struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh);
 void __iomem *omap_hwmod_get_mpu_rt_va(struct omap_hwmod *oh);
@@ -617,4 +638,6 @@ extern int omap2430_hwmod_init(void);
 extern int omap3xxx_hwmod_init(void);
 extern int omap44xx_hwmod_init(void);
+extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois);
 #endif
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index d50cbc6385bd..c490240bb82c 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -475,13 +475,11 @@ static int omap_device_count_resources(struct omap_device *od)
 static int omap_device_fill_resources(struct omap_device *od,
                                      struct resource *res)
 {
-        int c = 0;
        int i, r;
        for (i = 0; i < od->hwmods_cnt; i++) {
                r = omap_hwmod_fill_resources(od->hwmods[i], res);
                res += r;
-                c += r;
        }
        return 0;
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index eec98afa0f83..477363c163ec 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -196,8 +196,8 @@ static void __init omap_map_sram(void)
         * Looks like we need to preserve some bootloader code at the
         * beginning of SRAM for jumping to flash for reboot to work...
         */
-        memset((void *)omap_sram_base + SRAM_BOOTLOADER_SZ, 0,
+        memset_io(omap_sram_base + SRAM_BOOTLOADER_SZ, 0,
-               omap_sram_size - SRAM_BOOTLOADER_SZ);
+                  omap_sram_size - SRAM_BOOTLOADER_SZ);
 }
 /*
@@ -348,7 +348,6 @@ u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc,
                        sdrc_actim_ctrl_b_1, sdrc_mr_1);
 }
-#ifdef CONFIG_PM
 void omap3_sram_restore_context(void)
 {
        omap_sram_ceil = omap_sram_base + omap_sram_size;
@@ -358,17 +357,18 @@ void omap3_sram_restore_context(void)
                               omap3_sram_configure_core_dpll_sz);
        omap_push_sram_idle();
 }
-#endif /* CONFIG_PM */
-#endif /* CONFIG_ARCH_OMAP3 */
 static inline int omap34xx_sram_init(void)
 {
-#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
        omap3_sram_restore_context();
-#endif
        return 0;
 }
+#else
+static inline int omap34xx_sram_init(void)
+{
+        return 0;
+}
+#endif /* CONFIG_ARCH_OMAP3 */
 static inline int am33xx_sram_init(void)
 {
diff --git a/arch/arm/plat-omap/usb.c b/arch/arm/plat-omap/usb.c
index d2bbfd1cb0b5..daa0327381b5 100644
--- a/arch/arm/plat-omap/usb.c
+++ b/arch/arm/plat-omap/usb.c
@@ -31,15 +31,12 @@
 #include <mach/hardware.h>
-#include "../mach-omap2/common.h"
 #ifdef  CONFIG_ARCH_OMAP_OTG
 void __init
 omap_otg_init(struct omap_usb_config *config)
 {
        u32             syscon;
-        int             status;
        int             alt_pingroup = 0;
        /* NOTE:  no bus or clock setup (yet?) */
@@ -104,6 +101,7 @@ omap_otg_init(struct omap_usb_config *config)
 #ifdef  CONFIG_USB_GADGET_OMAP
        if (config->otg || config->register_dev) {
                struct platform_device *udc_device = config->udc_device;
+                int status;
                syscon &= ~DEV_IDLE_EN;
                udc_device->dev.platform_data = config;
@@ -116,6 +114,7 @@ omap_otg_init(struct omap_usb_config *config)
 #if     defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
        if (config->otg || config->register_host) {
                struct platform_device *ohci_device = config->ohci_device;
+                int status;
                syscon &= ~HST_IDLE_EN;
                ohci_device->dev.platform_data = config;
@@ -128,6 +127,7 @@ omap_otg_init(struct omap_usb_config *config)
 #ifdef  CONFIG_USB_OTG
        if (config->otg) {
                struct platform_device *otg_device = config->otg_device;
+                int status;
                syscon &= ~OTG_IDLE_EN;
                otg_device->dev.platform_data = config;
@@ -138,8 +138,6 @@ omap_otg_init(struct omap_usb_config *config)
 #endif
        pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1));
        omap_writel(syscon, OTG_SYSCON_1);
-        status = 0;
 }
 #else
diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c
index 10d160888133..af95af257301 100644
--- a/arch/arm/plat-orion/gpio.c
+++ b/arch/arm/plat-orion/gpio.c
@@ -16,6 +16,7 @@
 #include <linux/bitops.h>
 #include <linux/io.h>
 #include <linux/gpio.h>
+#include <linux/leds.h>
 /*
 * GPIO unit register offsets.
@@ -289,12 +290,34 @@ void orion_gpio_set_blink(unsigned pin, int blink)
                return;
        spin_lock_irqsave(&ochip->lock, flags);
-        __set_level(ochip, pin, 0);
+        __set_level(ochip, pin & 31, 0);
-        __set_blinking(ochip, pin, blink);
+        __set_blinking(ochip, pin & 31, blink);
        spin_unlock_irqrestore(&ochip->lock, flags);
 }
 EXPORT_SYMBOL(orion_gpio_set_blink);
+#define ORION_BLINK_HALF_PERIOD 100 /* ms */
+int orion_gpio_led_blink_set(unsigned gpio, int state,
+        unsigned long *delay_on, unsigned long *delay_off)
+{
+        if (delay_on && delay_off && !*delay_on && !*delay_off)
+                *delay_on = *delay_off = ORION_BLINK_HALF_PERIOD;
+        switch (state) {
+        case GPIO_LED_NO_BLINK_LOW:
+        case GPIO_LED_NO_BLINK_HIGH:
+                orion_gpio_set_blink(gpio, 0);
+                gpio_set_value(gpio, state);
+                break;
+        case GPIO_LED_BLINK:
+                orion_gpio_set_blink(gpio, 1);
+        }
+        return 0;
+}
+EXPORT_SYMBOL_GPL(orion_gpio_led_blink_set);
 /*****************************************************************************
 * Orion GPIO IRQ
diff --git a/arch/arm/plat-orion/include/plat/gpio.h b/arch/arm/plat-orion/include/plat/gpio.h
index 3abf30428bee..bec0c98ce41f 100644
--- a/arch/arm/plat-orion/include/plat/gpio.h
+++ b/arch/arm/plat-orion/include/plat/gpio.h
@@ -19,6 +19,8 @@
 */
 void orion_gpio_set_unused(unsigned pin);
 void orion_gpio_set_blink(unsigned pin, int blink);
+int orion_gpio_led_blink_set(unsigned gpio, int state,
+        unsigned long *delay_on, unsigned long *delay_off);
 #define GPIO_INPUT_OK           (1 << 0)
 #define GPIO_OUTPUT_OK          (1 << 1)
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index 71553f410016..a0ffc77da809 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -302,6 +302,7 @@ comment "Power management"
 config SAMSUNG_PM_DEBUG
        bool "S3C2410 PM Suspend debug"
        depends on PM
+        select DEBUG_LL
        help
          Say Y here if you want verbose debugging from the PM Suspend and
          Resume code. See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt>
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
index 8b928f9bc1c3..1d214cb9d770 100644
--- a/arch/arm/plat-samsung/devs.c
+++ b/arch/arm/plat-samsung/devs.c
@@ -30,6 +30,7 @@
 #include <linux/mmc/host.h>
 #include <linux/ioport.h>
 #include <linux/platform_data/s3c-hsudc.h>
+#include <linux/platform_data/s3c-hsotg.h>
 #include <asm/irq.h>
 #include <asm/pmu.h>
@@ -57,7 +58,6 @@
 #include <plat/sdhci.h>
 #include <plat/ts.h>
 #include <plat/udc.h>
-#include <plat/udc-hs.h>
 #include <plat/usb-control.h>
 #include <plat/usb-phy.h>
 #include <plat/regs-iic.h>
@@ -272,16 +272,8 @@ struct platform_device s5p_device_fimc3 = {
 #ifdef CONFIG_S5P_DEV_G2D
 static struct resource s5p_g2d_resource[] = {
-        [0] = {
+        [0] = DEFINE_RES_MEM(S5P_PA_G2D, SZ_4K),
-                .start  = S5P_PA_G2D,
+        [1] = DEFINE_RES_IRQ(IRQ_2D),
-                .end    = S5P_PA_G2D + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = IRQ_2D,
-                .end    = IRQ_2D,
-                .flags  = IORESOURCE_IRQ,
-        },
 };
 struct platform_device s5p_device_g2d = {
@@ -370,7 +362,6 @@ struct s3c_sdhci_platdata s3c_hsmmc0_def_platdata = {
        .max_width      = 4,
        .host_caps      = (MMC_CAP_4_BIT_DATA |
                           MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-        .clk_type       = S3C_SDHCI_CLK_DIV_INTERNAL,
 };
 struct platform_device s3c_device_hsmmc0 = {
@@ -401,7 +392,6 @@ struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata = {
        .max_width      = 4,
        .host_caps      = (MMC_CAP_4_BIT_DATA |
                           MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-        .clk_type       = S3C_SDHCI_CLK_DIV_INTERNAL,
 };
 struct platform_device s3c_device_hsmmc1 = {
@@ -434,7 +424,6 @@ struct s3c_sdhci_platdata s3c_hsmmc2_def_platdata = {
        .max_width      = 4,
        .host_caps      = (MMC_CAP_4_BIT_DATA |
                           MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-        .clk_type       = S3C_SDHCI_CLK_DIV_INTERNAL,
 };
 struct platform_device s3c_device_hsmmc2 = {
@@ -465,7 +454,6 @@ struct s3c_sdhci_platdata s3c_hsmmc3_def_platdata = {
        .max_width      = 4,
        .host_caps      = (MMC_CAP_4_BIT_DATA |
                           MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-        .clk_type       = S3C_SDHCI_CLK_DIV_INTERNAL,
 };
 struct platform_device s3c_device_hsmmc3 = {
diff --git a/arch/arm/plat-samsung/include/plat/regs-usb-hsotg.h b/arch/arm/plat-samsung/include/plat/regs-usb-hsotg.h
deleted file mode 100644
index dc90f5ede88f..000000000000
--- a/arch/arm/plat-samsung/include/plat/regs-usb-hsotg.h
+++ /dev/null
@@ -1,379 +0,0 @@
-/* arch/arm/plat-s3c/include/plat/regs-usb-hsotg.h
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *      http://armlinux.simtec.co.uk/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C - USB2.0 Highspeed/OtG device block registers
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __PLAT_S3C64XX_REGS_USB_HSOTG_H
-#define __PLAT_S3C64XX_REGS_USB_HSOTG_H __FILE__
-#define S3C_HSOTG_REG(x) (x)
-#define S3C_GOTGCTL                             S3C_HSOTG_REG(0x000)
-#define S3C_GOTGCTL_BSESVLD                     (1 << 19)
-#define S3C_GOTGCTL_ASESVLD                     (1 << 18)
-#define S3C_GOTGCTL_DBNC_SHORT                  (1 << 17)
-#define S3C_GOTGCTL_CONID_B                     (1 << 16)
-#define S3C_GOTGCTL_DEVHNPEN                    (1 << 11)
-#define S3C_GOTGCTL_HSSETHNPEN                  (1 << 10)
-#define S3C_GOTGCTL_HNPREQ                      (1 << 9)
-#define S3C_GOTGCTL_HSTNEGSCS                   (1 << 8)
-#define S3C_GOTGCTL_SESREQ                      (1 << 1)
-#define S3C_GOTGCTL_SESREQSCS                   (1 << 0)
-#define S3C_GOTGINT                             S3C_HSOTG_REG(0x004)
-#define S3C_GOTGINT_DbnceDone                   (1 << 19)
-#define S3C_GOTGINT_ADevTOUTChg                 (1 << 18)
-#define S3C_GOTGINT_HstNegDet                   (1 << 17)
-#define S3C_GOTGINT_HstnegSucStsChng            (1 << 9)
-#define S3C_GOTGINT_SesReqSucStsChng            (1 << 8)
-#define S3C_GOTGINT_SesEndDet                   (1 << 2)
-#define S3C_GAHBCFG                             S3C_HSOTG_REG(0x008)
-#define S3C_GAHBCFG_PTxFEmpLvl                  (1 << 8)
-#define S3C_GAHBCFG_NPTxFEmpLvl                 (1 << 7)
-#define S3C_GAHBCFG_DMAEn                       (1 << 5)
-#define S3C_GAHBCFG_HBstLen_MASK                (0xf << 1)
-#define S3C_GAHBCFG_HBstLen_SHIFT               (1)
-#define S3C_GAHBCFG_HBstLen_Single              (0x0 << 1)
-#define S3C_GAHBCFG_HBstLen_Incr                (0x1 << 1)
-#define S3C_GAHBCFG_HBstLen_Incr4               (0x3 << 1)
-#define S3C_GAHBCFG_HBstLen_Incr8               (0x5 << 1)
-#define S3C_GAHBCFG_HBstLen_Incr16              (0x7 << 1)
-#define S3C_GAHBCFG_GlblIntrEn                  (1 << 0)
-#define S3C_GUSBCFG                             S3C_HSOTG_REG(0x00C)
-#define S3C_GUSBCFG_PHYLPClkSel                 (1 << 15)
-#define S3C_GUSBCFG_HNPCap                      (1 << 9)
-#define S3C_GUSBCFG_SRPCap                      (1 << 8)
-#define S3C_GUSBCFG_PHYIf16                     (1 << 3)
-#define S3C_GUSBCFG_TOutCal_MASK                (0x7 << 0)
-#define S3C_GUSBCFG_TOutCal_SHIFT               (0)
-#define S3C_GUSBCFG_TOutCal_LIMIT               (0x7)
-#define S3C_GUSBCFG_TOutCal(_x)                 ((_x) << 0)
-#define S3C_GRSTCTL                             S3C_HSOTG_REG(0x010)
-#define S3C_GRSTCTL_AHBIdle                     (1 << 31)
-#define S3C_GRSTCTL_DMAReq                      (1 << 30)
-#define S3C_GRSTCTL_TxFNum_MASK                 (0x1f << 6)
-#define S3C_GRSTCTL_TxFNum_SHIFT                (6)
-#define S3C_GRSTCTL_TxFNum_LIMIT                (0x1f)
-#define S3C_GRSTCTL_TxFNum(_x)                  ((_x) << 6)
-#define S3C_GRSTCTL_TxFFlsh                     (1 << 5)
-#define S3C_GRSTCTL_RxFFlsh                     (1 << 4)
-#define S3C_GRSTCTL_INTknQFlsh                  (1 << 3)
-#define S3C_GRSTCTL_FrmCntrRst                  (1 << 2)
-#define S3C_GRSTCTL_HSftRst                     (1 << 1)
-#define S3C_GRSTCTL_CSftRst                     (1 << 0)
-#define S3C_GINTSTS                             S3C_HSOTG_REG(0x014)
-#define S3C_GINTMSK                             S3C_HSOTG_REG(0x018)
-#define S3C_GINTSTS_WkUpInt                     (1 << 31)
-#define S3C_GINTSTS_SessReqInt                  (1 << 30)
-#define S3C_GINTSTS_DisconnInt                  (1 << 29)
-#define S3C_GINTSTS_ConIDStsChng                (1 << 28)
-#define S3C_GINTSTS_PTxFEmp                     (1 << 26)
-#define S3C_GINTSTS_HChInt                      (1 << 25)
-#define S3C_GINTSTS_PrtInt                      (1 << 24)
-#define S3C_GINTSTS_FetSusp                     (1 << 22)
-#define S3C_GINTSTS_incompIP                    (1 << 21)
-#define S3C_GINTSTS_IncomplSOIN                 (1 << 20)
-#define S3C_GINTSTS_OEPInt                      (1 << 19)
-#define S3C_GINTSTS_IEPInt                      (1 << 18)
-#define S3C_GINTSTS_EPMis                       (1 << 17)
-#define S3C_GINTSTS_EOPF                        (1 << 15)
-#define S3C_GINTSTS_ISOutDrop                   (1 << 14)
-#define S3C_GINTSTS_EnumDone                    (1 << 13)
-#define S3C_GINTSTS_USBRst                      (1 << 12)
-#define S3C_GINTSTS_USBSusp                     (1 << 11)
-#define S3C_GINTSTS_ErlySusp                    (1 << 10)
-#define S3C_GINTSTS_GOUTNakEff                  (1 << 7)
-#define S3C_GINTSTS_GINNakEff                   (1 << 6)
-#define S3C_GINTSTS_NPTxFEmp                    (1 << 5)
-#define S3C_GINTSTS_RxFLvl                      (1 << 4)
-#define S3C_GINTSTS_SOF                         (1 << 3)
-#define S3C_GINTSTS_OTGInt                      (1 << 2)
-#define S3C_GINTSTS_ModeMis                     (1 << 1)
-#define S3C_GINTSTS_CurMod_Host                 (1 << 0)
-#define S3C_GRXSTSR                             S3C_HSOTG_REG(0x01C)
-#define S3C_GRXSTSP                             S3C_HSOTG_REG(0x020)
-#define S3C_GRXSTS_FN_MASK                      (0x7f << 25)
-#define S3C_GRXSTS_FN_SHIFT                     (25)
-#define S3C_GRXSTS_PktSts_MASK                  (0xf << 17)
-#define S3C_GRXSTS_PktSts_SHIFT                 (17)
-#define S3C_GRXSTS_PktSts_GlobalOutNAK          (0x1 << 17)
-#define S3C_GRXSTS_PktSts_OutRX                 (0x2 << 17)
-#define S3C_GRXSTS_PktSts_OutDone               (0x3 << 17)
-#define S3C_GRXSTS_PktSts_SetupDone             (0x4 << 17)
-#define S3C_GRXSTS_PktSts_SetupRX               (0x6 << 17)
-#define S3C_GRXSTS_DPID_MASK                    (0x3 << 15)
-#define S3C_GRXSTS_DPID_SHIFT                   (15)
-#define S3C_GRXSTS_ByteCnt_MASK                 (0x7ff << 4)
-#define S3C_GRXSTS_ByteCnt_SHIFT                (4)
-#define S3C_GRXSTS_EPNum_MASK                   (0xf << 0)
-#define S3C_GRXSTS_EPNum_SHIFT                  (0)
-#define S3C_GRXFSIZ                             S3C_HSOTG_REG(0x024)
-#define S3C_GNPTXFSIZ                           S3C_HSOTG_REG(0x028)
-#define S3C_GNPTXFSIZ_NPTxFDep_MASK             (0xffff << 16)
-#define S3C_GNPTXFSIZ_NPTxFDep_SHIFT            (16)
-#define S3C_GNPTXFSIZ_NPTxFDep_LIMIT            (0xffff)
-#define S3C_GNPTXFSIZ_NPTxFDep(_x)              ((_x) << 16)
-#define S3C_GNPTXFSIZ_NPTxFStAddr_MASK          (0xffff << 0)
-#define S3C_GNPTXFSIZ_NPTxFStAddr_SHIFT         (0)
-#define S3C_GNPTXFSIZ_NPTxFStAddr_LIMIT         (0xffff)
-#define S3C_GNPTXFSIZ_NPTxFStAddr(_x)           ((_x) << 0)
-#define S3C_GNPTXSTS                            S3C_HSOTG_REG(0x02C)
-#define S3C_GNPTXSTS_NPtxQTop_MASK              (0x7f << 24)
-#define S3C_GNPTXSTS_NPtxQTop_SHIFT             (24)
-#define S3C_GNPTXSTS_NPTxQSpcAvail_MASK         (0xff << 16)
-#define S3C_GNPTXSTS_NPTxQSpcAvail_SHIFT        (16)
-#define S3C_GNPTXSTS_NPTxQSpcAvail_GET(_v)      (((_v) >> 16) & 0xff)
-#define S3C_GNPTXSTS_NPTxFSpcAvail_MASK         (0xffff << 0)
-#define S3C_GNPTXSTS_NPTxFSpcAvail_SHIFT        (0)
-#define S3C_GNPTXSTS_NPTxFSpcAvail_GET(_v)      (((_v) >> 0) & 0xffff)
-#define S3C_HPTXFSIZ                            S3C_HSOTG_REG(0x100)
-#define S3C_DPTXFSIZn(_a)                       S3C_HSOTG_REG(0x104 + (((_a) - 1) * 4))
-#define S3C_DPTXFSIZn_DPTxFSize_MASK            (0xffff << 16)
-#define S3C_DPTXFSIZn_DPTxFSize_SHIFT           (16)
-#define S3C_DPTXFSIZn_DPTxFSize_GET(_v)         (((_v) >> 16) & 0xffff)
-#define S3C_DPTXFSIZn_DPTxFSize_LIMIT           (0xffff)
-#define S3C_DPTXFSIZn_DPTxFSize(_x)             ((_x) << 16)
-#define S3C_DPTXFSIZn_DPTxFStAddr_MASK          (0xffff << 0)
-#define S3C_DPTXFSIZn_DPTxFStAddr_SHIFT         (0)
-/* Device mode registers */
-#define S3C_DCFG                                S3C_HSOTG_REG(0x800)
-#define S3C_DCFG_EPMisCnt_MASK                  (0x1f << 18)
-#define S3C_DCFG_EPMisCnt_SHIFT                 (18)
-#define S3C_DCFG_EPMisCnt_LIMIT                 (0x1f)
-#define S3C_DCFG_EPMisCnt(_x)                   ((_x) << 18)
-#define S3C_DCFG_PerFrInt_MASK                  (0x3 << 11)
-#define S3C_DCFG_PerFrInt_SHIFT                 (11)
-#define S3C_DCFG_PerFrInt_LIMIT                 (0x3)
-#define S3C_DCFG_PerFrInt(_x)                   ((_x) << 11)
-#define S3C_DCFG_DevAddr_MASK                   (0x7f << 4)
-#define S3C_DCFG_DevAddr_SHIFT                  (4)
-#define S3C_DCFG_DevAddr_LIMIT                  (0x7f)
-#define S3C_DCFG_DevAddr(_x)                    ((_x) << 4)
-#define S3C_DCFG_NZStsOUTHShk                   (1 << 2)
-#define S3C_DCFG_DevSpd_MASK                    (0x3 << 0)
-#define S3C_DCFG_DevSpd_SHIFT                   (0)
-#define S3C_DCFG_DevSpd_HS                      (0x0 << 0)
-#define S3C_DCFG_DevSpd_FS                      (0x1 << 0)
-#define S3C_DCFG_DevSpd_LS                      (0x2 << 0)
-#define S3C_DCFG_DevSpd_FS48                    (0x3 << 0)
-#define S3C_DCTL                                S3C_HSOTG_REG(0x804)
-#define S3C_DCTL_PWROnPrgDone                   (1 << 11)
-#define S3C_DCTL_CGOUTNak                       (1 << 10)
-#define S3C_DCTL_SGOUTNak                       (1 << 9)
-#define S3C_DCTL_CGNPInNAK                      (1 << 8)
-#define S3C_DCTL_SGNPInNAK                      (1 << 7)
-#define S3C_DCTL_TstCtl_MASK                    (0x7 << 4)
-#define S3C_DCTL_TstCtl_SHIFT                   (4)
-#define S3C_DCTL_GOUTNakSts                     (1 << 3)
-#define S3C_DCTL_GNPINNakSts                    (1 << 2)
-#define S3C_DCTL_SftDiscon                      (1 << 1)
-#define S3C_DCTL_RmtWkUpSig                     (1 << 0)
-#define S3C_DSTS                                S3C_HSOTG_REG(0x808)
-#define S3C_DSTS_SOFFN_MASK                     (0x3fff << 8)
-#define S3C_DSTS_SOFFN_SHIFT                    (8)
-#define S3C_DSTS_SOFFN_LIMIT                    (0x3fff)
-#define S3C_DSTS_SOFFN(_x)                      ((_x) << 8)
-#define S3C_DSTS_ErraticErr                     (1 << 3)
-#define S3C_DSTS_EnumSpd_MASK                   (0x3 << 1)
-#define S3C_DSTS_EnumSpd_SHIFT                  (1)
-#define S3C_DSTS_EnumSpd_HS                     (0x0 << 1)
-#define S3C_DSTS_EnumSpd_FS                     (0x1 << 1)
-#define S3C_DSTS_EnumSpd_LS                     (0x2 << 1)
-#define S3C_DSTS_EnumSpd_FS48                   (0x3 << 1)
-#define S3C_DSTS_SuspSts                        (1 << 0)
-#define S3C_DIEPMSK                             S3C_HSOTG_REG(0x810)
-#define S3C_DIEPMSK_TxFIFOEmpty                 (1 << 7)
-#define S3C_DIEPMSK_INEPNakEffMsk               (1 << 6)
-#define S3C_DIEPMSK_INTknEPMisMsk               (1 << 5)
-#define S3C_DIEPMSK_INTknTXFEmpMsk              (1 << 4)
-#define S3C_DIEPMSK_TimeOUTMsk                  (1 << 3)
-#define S3C_DIEPMSK_AHBErrMsk                   (1 << 2)
-#define S3C_DIEPMSK_EPDisbldMsk                 (1 << 1)
-#define S3C_DIEPMSK_XferComplMsk                (1 << 0)
-#define S3C_DOEPMSK                             S3C_HSOTG_REG(0x814)
-#define S3C_DOEPMSK_Back2BackSetup              (1 << 6)
-#define S3C_DOEPMSK_OUTTknEPdisMsk              (1 << 4)
-#define S3C_DOEPMSK_SetupMsk                    (1 << 3)
-#define S3C_DOEPMSK_AHBErrMsk                   (1 << 2)
-#define S3C_DOEPMSK_EPDisbldMsk                 (1 << 1)
-#define S3C_DOEPMSK_XferComplMsk                (1 << 0)
-#define S3C_DAINT                               S3C_HSOTG_REG(0x818)
-#define S3C_DAINTMSK                            S3C_HSOTG_REG(0x81C)
-#define S3C_DAINT_OutEP_SHIFT                   (16)
-#define S3C_DAINT_OutEP(x)                      (1 << ((x) + 16))
-#define S3C_DAINT_InEP(x)                       (1 << (x))
-#define S3C_DTKNQR1                             S3C_HSOTG_REG(0x820)
-#define S3C_DTKNQR2                             S3C_HSOTG_REG(0x824)
-#define S3C_DTKNQR3                             S3C_HSOTG_REG(0x830)
-#define S3C_DTKNQR4                             S3C_HSOTG_REG(0x834)
-#define S3C_DVBUSDIS                            S3C_HSOTG_REG(0x828)
-#define S3C_DVBUSPULSE                          S3C_HSOTG_REG(0x82C)
-#define S3C_DIEPCTL0                            S3C_HSOTG_REG(0x900)
-#define S3C_DOEPCTL0                            S3C_HSOTG_REG(0xB00)
-#define S3C_DIEPCTL(_a)                         S3C_HSOTG_REG(0x900 + ((_a) * 0x20))
-#define S3C_DOEPCTL(_a)                         S3C_HSOTG_REG(0xB00 + ((_a) * 0x20))
-/* EP0 specialness:
- * bits[29..28] - reserved (no SetD0PID, SetD1PID)
- * bits[25..22] - should always be zero, this isn't a periodic endpoint
- * bits[10..0] - MPS setting differenct for EP0
-*/
-#define S3C_D0EPCTL_MPS_MASK                    (0x3 << 0)
-#define S3C_D0EPCTL_MPS_SHIFT                   (0)
-#define S3C_D0EPCTL_MPS_64                      (0x0 << 0)
-#define S3C_D0EPCTL_MPS_32                      (0x1 << 0)
-#define S3C_D0EPCTL_MPS_16                      (0x2 << 0)
-#define S3C_D0EPCTL_MPS_8                       (0x3 << 0)
-#define S3C_DxEPCTL_EPEna                       (1 << 31)
-#define S3C_DxEPCTL_EPDis                       (1 << 30)
-#define S3C_DxEPCTL_SetD1PID                    (1 << 29)
-#define S3C_DxEPCTL_SetOddFr                    (1 << 29)
-#define S3C_DxEPCTL_SetD0PID                    (1 << 28)
-#define S3C_DxEPCTL_SetEvenFr                   (1 << 28)
-#define S3C_DxEPCTL_SNAK                        (1 << 27)
-#define S3C_DxEPCTL_CNAK                        (1 << 26)
-#define S3C_DxEPCTL_TxFNum_MASK                 (0xf << 22)
-#define S3C_DxEPCTL_TxFNum_SHIFT                (22)
-#define S3C_DxEPCTL_TxFNum_LIMIT                (0xf)
-#define S3C_DxEPCTL_TxFNum(_x)                  ((_x) << 22)
-#define S3C_DxEPCTL_Stall                       (1 << 21)
-#define S3C_DxEPCTL_Snp                         (1 << 20)
-#define S3C_DxEPCTL_EPType_MASK                 (0x3 << 18)
-#define S3C_DxEPCTL_EPType_SHIFT                (18)
-#define S3C_DxEPCTL_EPType_Control              (0x0 << 18)
-#define S3C_DxEPCTL_EPType_Iso                  (0x1 << 18)
-#define S3C_DxEPCTL_EPType_Bulk                 (0x2 << 18)
-#define S3C_DxEPCTL_EPType_Intterupt            (0x3 << 18)
-#define S3C_DxEPCTL_NAKsts                      (1 << 17)
-#define S3C_DxEPCTL_DPID                        (1 << 16)
-#define S3C_DxEPCTL_EOFrNum                     (1 << 16)
-#define S3C_DxEPCTL_USBActEp                    (1 << 15)
-#define S3C_DxEPCTL_NextEp_MASK                 (0xf << 11)
-#define S3C_DxEPCTL_NextEp_SHIFT                (11)
-#define S3C_DxEPCTL_NextEp_LIMIT                (0xf)
-#define S3C_DxEPCTL_NextEp(_x)                  ((_x) << 11)
-#define S3C_DxEPCTL_MPS_MASK                    (0x7ff << 0)
-#define S3C_DxEPCTL_MPS_SHIFT                   (0)
-#define S3C_DxEPCTL_MPS_LIMIT                   (0x7ff)
-#define S3C_DxEPCTL_MPS(_x)                     ((_x) << 0)
-#define S3C_DIEPINT(_a)                         S3C_HSOTG_REG(0x908 + ((_a) * 0x20))
-#define S3C_DOEPINT(_a)                         S3C_HSOTG_REG(0xB08 + ((_a) * 0x20))
-#define S3C_DxEPINT_INEPNakEff                  (1 << 6)
-#define S3C_DxEPINT_Back2BackSetup              (1 << 6)
-#define S3C_DxEPINT_INTknEPMis                  (1 << 5)
-#define S3C_DxEPINT_INTknTXFEmp                 (1 << 4)
-#define S3C_DxEPINT_OUTTknEPdis                 (1 << 4)
-#define S3C_DxEPINT_Timeout                     (1 << 3)
-#define S3C_DxEPINT_Setup                       (1 << 3)
-#define S3C_DxEPINT_AHBErr                      (1 << 2)
-#define S3C_DxEPINT_EPDisbld                    (1 << 1)
-#define S3C_DxEPINT_XferCompl                   (1 << 0)
-#define S3C_DIEPTSIZ0                           S3C_HSOTG_REG(0x910)
-#define S3C_DIEPTSIZ0_PktCnt_MASK               (0x3 << 19)
-#define S3C_DIEPTSIZ0_PktCnt_SHIFT              (19)
-#define S3C_DIEPTSIZ0_PktCnt_LIMIT              (0x3)
-#define S3C_DIEPTSIZ0_PktCnt(_x)                ((_x) << 19)
-#define S3C_DIEPTSIZ0_XferSize_MASK             (0x7f << 0)
-#define S3C_DIEPTSIZ0_XferSize_SHIFT            (0)
-#define S3C_DIEPTSIZ0_XferSize_LIMIT            (0x7f)
-#define S3C_DIEPTSIZ0_XferSize(_x)              ((_x) << 0)
-#define DOEPTSIZ0                               S3C_HSOTG_REG(0xB10)
-#define S3C_DOEPTSIZ0_SUPCnt_MASK               (0x3 << 29)
-#define S3C_DOEPTSIZ0_SUPCnt_SHIFT              (29)
-#define S3C_DOEPTSIZ0_SUPCnt_LIMIT              (0x3)
-#define S3C_DOEPTSIZ0_SUPCnt(_x)                ((_x) << 29)
-#define S3C_DOEPTSIZ0_PktCnt                    (1 << 19)
-#define S3C_DOEPTSIZ0_XferSize_MASK             (0x7f << 0)
-#define S3C_DOEPTSIZ0_XferSize_SHIFT            (0)
-#define S3C_DIEPTSIZ(_a)                        S3C_HSOTG_REG(0x910 + ((_a) * 0x20))
-#define S3C_DOEPTSIZ(_a)                        S3C_HSOTG_REG(0xB10 + ((_a) * 0x20))
-#define S3C_DxEPTSIZ_MC_MASK                    (0x3 << 29)
-#define S3C_DxEPTSIZ_MC_SHIFT                   (29)
-#define S3C_DxEPTSIZ_MC_LIMIT                   (0x3)
-#define S3C_DxEPTSIZ_MC(_x)                     ((_x) << 29)
-#define S3C_DxEPTSIZ_PktCnt_MASK                (0x3ff << 19)
-#define S3C_DxEPTSIZ_PktCnt_SHIFT               (19)
-#define S3C_DxEPTSIZ_PktCnt_GET(_v)             (((_v) >> 19) & 0x3ff)
-#define S3C_DxEPTSIZ_PktCnt_LIMIT               (0x3ff)
-#define S3C_DxEPTSIZ_PktCnt(_x)                 ((_x) << 19)
-#define S3C_DxEPTSIZ_XferSize_MASK              (0x7ffff << 0)
-#define S3C_DxEPTSIZ_XferSize_SHIFT             (0)
-#define S3C_DxEPTSIZ_XferSize_GET(_v)           (((_v) >> 0) & 0x7ffff)
-#define S3C_DxEPTSIZ_XferSize_LIMIT             (0x7ffff)
-#define S3C_DxEPTSIZ_XferSize(_x)               ((_x) << 0)
-#define S3C_DIEPDMA(_a)                         S3C_HSOTG_REG(0x914 + ((_a) * 0x20))
-#define S3C_DOEPDMA(_a)                         S3C_HSOTG_REG(0xB14 + ((_a) * 0x20))
-#define S3C_DTXFSTS(_a)                         S3C_HSOTG_REG(0x918 + ((_a) * 0x20))
-#define S3C_EPFIFO(_a)                          S3C_HSOTG_REG(0x1000 + ((_a) * 0x1000))
-#endif /* __PLAT_S3C64XX_REGS_USB_HSOTG_H */
diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h
index 317e246ffc56..151cc9195cf6 100644
--- a/arch/arm/plat-samsung/include/plat/sdhci.h
+++ b/arch/arm/plat-samsung/include/plat/sdhci.h
@@ -18,6 +18,8 @@
 #ifndef __PLAT_S3C_SDHCI_H
 #define __PLAT_S3C_SDHCI_H __FILE__
+#include <plat/devs.h>
 struct platform_device;
 struct mmc_host;
 struct mmc_card;
@@ -31,18 +33,12 @@ enum cd_types {
        S3C_SDHCI_CD_PERMANENT, /* no CD line, card permanently wired to host */
 };
-enum clk_types {
-        S3C_SDHCI_CLK_DIV_INTERNAL,     /* use mmc internal clock divider */
-        S3C_SDHCI_CLK_DIV_EXTERNAL,     /* use external clock divider */
-};
 /**
 * struct s3c_sdhci_platdata() - Platform device data for Samsung SDHCI
 * @max_width: The maximum number of data bits supported.
 * @host_caps: Standard MMC host capabilities bit field.
 * @host_caps2: The second standard MMC host capabilities bit field.
 * @cd_type: Type of Card Detection method (see cd_types enum above)
- * @clk_type: Type of clock divider method (see clk_types enum above)
 * @ext_cd_init: Initialize external card detect subsystem. Called on
 *               sdhci-s3c driver probe when cd_type == S3C_SDHCI_CD_EXTERNAL.
 *               notify_func argument is a callback to the sdhci-s3c driver
@@ -67,7 +63,6 @@ struct s3c_sdhci_platdata {
        unsigned int    host_caps2;
        unsigned int    pm_caps;
        enum cd_types   cd_type;
-        enum clk_types  clk_type;
        int             ext_cd_gpio;
        bool            ext_cd_gpio_invert;
@@ -356,4 +351,30 @@ static inline void exynos4_default_sdhci3(void) { }
 #endif /* CONFIG_EXYNOS4_SETUP_SDHCI */
+static inline void s3c_sdhci_setname(int id, char *name)
+{
+        switch (id) {
+#ifdef CONFIG_S3C_DEV_HSMMC
+        case 0:
+                s3c_device_hsmmc0.name = name;
+                break;
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC1
+        case 1:
+                s3c_device_hsmmc1.name = name;
+                break;
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC2
+        case 2:
+                s3c_device_hsmmc2.name = name;
+                break;
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC3
+        case 3:
+                s3c_device_hsmmc3.name = name;
+                break;
+#endif
+        }
+}
 #endif /* __PLAT_S3C_SDHCI_H */
diff --git a/arch/arm/plat-samsung/include/plat/udc-hs.h b/arch/arm/plat-samsung/include/plat/udc-hs.h
deleted file mode 100644
index c9e3667cb2b1..000000000000
--- a/arch/arm/plat-samsung/include/plat/udc-hs.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/* arch/arm/plat-s3c/include/plat/udc-hs.h
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * S3C USB2.0 High-speed / OtG platform information
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-enum s3c_hsotg_dmamode {
-        S3C_HSOTG_DMA_NONE,     /* do not use DMA at-all */
-        S3C_HSOTG_DMA_ONLY,     /* always use DMA */
-        S3C_HSOTG_DMA_DRV,      /* DMA is chosen by driver */
-};
-/**
- * struct s3c_hsotg_plat - platform data for high-speed otg/udc
- * @dma: Whether to use DMA or not.
- * @is_osc: The clock source is an oscillator, not a crystal
- */
-struct s3c_hsotg_plat {
-        enum s3c_hsotg_dmamode  dma;
-        unsigned int            is_osc : 1;
-        int (*phy_init)(struct platform_device *pdev, int type);
-        int (*phy_exit)(struct platform_device *pdev, int type);
-};
-extern void s3c_hsotg_set_platdata(struct s3c_hsotg_plat *pd);
diff --git a/arch/arm/plat-samsung/platformdata.c b/arch/arm/plat-samsung/platformdata.c
index fa78aa710ed1..b430e9946287 100644
--- a/arch/arm/plat-samsung/platformdata.c
+++ b/arch/arm/plat-samsung/platformdata.c
@@ -57,6 +57,4 @@ void s3c_sdhci_set_platdata(struct s3c_sdhci_platdata *pd,
                set->host_caps2 |= pd->host_caps2;
        if (pd->pm_caps)
                set->pm_caps |= pd->pm_caps;
-        if (pd->clk_type)
-                set->clk_type = pd->clk_type;
 }
diff --git a/arch/arm/plat-spear/Kconfig b/arch/arm/plat-spear/Kconfig
index 1bb3dbce8810..387655b5ce05 100644
--- a/arch/arm/plat-spear/Kconfig
+++ b/arch/arm/plat-spear/Kconfig
@@ -9,9 +9,11 @@ choice
        default ARCH_SPEAR3XX
 config ARCH_SPEAR3XX
-        bool "SPEAr3XX"
+        bool "ST SPEAr3xx with Device Tree"
        select ARM_VIC
        select CPU_ARM926T
+        select USE_OF
+        select PINCTRL
        help
          Supports for ARM's SPEAR3XX family
diff --git a/arch/arm/plat-spear/Makefile b/arch/arm/plat-spear/Makefile
index e0f2e5b9530c..7744802c83e7 100644
--- a/arch/arm/plat-spear/Makefile
+++ b/arch/arm/plat-spear/Makefile
@@ -3,6 +3,6 @@
 #
 # Common support
-obj-y   := clock.o restart.o time.o
+obj-y   := clock.o restart.o time.o pl080.o
-obj-$(CONFIG_ARCH_SPEAR3XX)     += shirq.o padmux.o
+obj-$(CONFIG_ARCH_SPEAR3XX)     += shirq.o
diff --git a/arch/arm/plat-spear/include/plat/debug-macro.S b/arch/arm/plat-spear/include/plat/debug-macro.S
index 02b160a1ec9b..ab3de721c5db 100644
--- a/arch/arm/plat-spear/include/plat/debug-macro.S
+++ b/arch/arm/plat-spear/include/plat/debug-macro.S
@@ -12,7 +12,7 @@
 */
 #include <linux/amba/serial.h>
-#include <mach/hardware.h>
+#include <mach/spear.h>
                .macro  addruart, rp, rv, tmp
                mov     \rp, #SPEAR_DBG_UART_BASE               @ Physical base
diff --git a/arch/arm/plat-spear/include/plat/hardware.h b/arch/arm/plat-spear/include/plat/hardware.h
deleted file mode 100644
index 70187d763e26..000000000000
--- a/arch/arm/plat-spear/include/plat/hardware.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * arch/arm/plat-spear/include/plat/hardware.h
- *
- * Hardware definitions for SPEAr
- *
- * Copyright (C) 2010 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#ifndef __PLAT_HARDWARE_H
-#define __PLAT_HARDWARE_H
-#endif /* __PLAT_HARDWARE_H */
diff --git a/arch/arm/plat-spear/include/plat/padmux.h b/arch/arm/plat-spear/include/plat/padmux.h
deleted file mode 100644
index 877f3adcf610..000000000000
--- a/arch/arm/plat-spear/include/plat/padmux.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * arch/arm/plat-spear/include/plat/padmux.h
- *
- * SPEAr platform specific gpio pads muxing file
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#ifndef __PLAT_PADMUX_H
-#define __PLAT_PADMUX_H
-#include <linux/types.h>
-/*
- * struct pmx_reg: configuration structure for mode reg and mux reg
- *
- * offset: offset of mode reg
- * mask: mask of mode reg
- */
-struct pmx_reg {
-        u32 offset;
-        u32 mask;
-};
-/*
- * struct pmx_dev_mode: configuration structure every group of modes of a device
- *
- * ids: all modes for this configuration
- * mask: mask for supported mode
- */
-struct pmx_dev_mode {
-        u32 ids;
-        u32 mask;
-};
-/*
- * struct pmx_mode: mode definition structure
- *
- * name: mode name
- * mask: mode mask
- */
-struct pmx_mode {
-        char *name;
-        u32 id;
-        u32 mask;
-};
-/*
- * struct pmx_dev: device definition structure
- *
- * name: device name
- * modes: device configuration array for different modes supported
- * mode_count: size of modes array
- * is_active: is peripheral active/enabled
- * enb_on_reset: if 1, mask bits to be cleared in reg otherwise to be set in reg
- */
-struct pmx_dev {
-        char *name;
-        struct pmx_dev_mode *modes;
-        u8 mode_count;
-        bool is_active;
-        bool enb_on_reset;
-};
-/*
- * struct pmx_driver: driver definition structure
- *
- * mode: mode to be set
- * devs: array of pointer to pmx devices
- * devs_count: ARRAY_SIZE of devs
- * base: base address of soc config registers
- * mode_reg: structure of mode config register
- * mux_reg: structure of device mux config register
- */
-struct pmx_driver {
-        struct pmx_mode *mode;
-        struct pmx_dev **devs;
-        u8 devs_count;
-        u32 *base;
-        struct pmx_reg mode_reg;
-        struct pmx_reg mux_reg;
-};
-/* pmx functions */
-int pmx_register(struct pmx_driver *driver);
-#endif /* __PLAT_PADMUX_H */
diff --git a/arch/arm/plat-spear/include/plat/pl080.h b/arch/arm/plat-spear/include/plat/pl080.h
new file mode 100644
index 000000000000..e14a3e4932f9
--- /dev/null
+++ b/arch/arm/plat-spear/include/plat/pl080.h
@@ -0,0 +1,21 @@
+/*
+ * arch/arm/plat-spear/include/plat/pl080.h
+ *
+ * DMAC pl080 definitions for SPEAr platform
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#ifndef __PLAT_PL080_H
+#define __PLAT_PL080_H
+struct pl08x_dma_chan;
+int pl080_get_signal(struct pl08x_dma_chan *ch);
+void pl080_put_signal(struct pl08x_dma_chan *ch);
+#endif /* __PLAT_PL080_H */
diff --git a/arch/arm/plat-spear/include/plat/uncompress.h b/arch/arm/plat-spear/include/plat/uncompress.h
index 1bf84527aee4..6dd455bafdfd 100644
--- a/arch/arm/plat-spear/include/plat/uncompress.h
+++ b/arch/arm/plat-spear/include/plat/uncompress.h
@@ -13,7 +13,7 @@
 #include <linux/io.h>
 #include <linux/amba/serial.h>
-#include <mach/hardware.h>
+#include <mach/spear.h>
 #ifndef __PLAT_UNCOMPRESS_H
 #define __PLAT_UNCOMPRESS_H
diff --git a/arch/arm/plat-spear/padmux.c b/arch/arm/plat-spear/padmux.c
deleted file mode 100644
index 555eec6dc1cb..000000000000
--- a/arch/arm/plat-spear/padmux.c
+++ /dev/null
@@ -1,164 +0,0 @@
-/*
- * arch/arm/plat-spear/include/plat/padmux.c
- *
- * SPEAr platform specific gpio pads muxing source file
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/slab.h>
-#include <plat/padmux.h>
-/*
- * struct pmx: pmx definition structure
- *
- * base: base address of configuration registers
- * mode_reg: mode configurations
- * mux_reg: muxing configurations
- * active_mode: pointer to current active mode
- */
-struct pmx {
-        u32 base;
-        struct pmx_reg mode_reg;
-        struct pmx_reg mux_reg;
-        struct pmx_mode *active_mode;
-};
-static struct pmx *pmx;
-/**
- * pmx_mode_set - Enables an multiplexing mode
- * @mode - pointer to pmx mode
- *
- * It will set mode of operation in hardware.
- * Returns -ve on Err otherwise 0
- */
-static int pmx_mode_set(struct pmx_mode *mode)
-{
-        u32 val;
-        if (!mode->name)
-                return -EFAULT;
-        pmx->active_mode = mode;
-        val = readl(pmx->base + pmx->mode_reg.offset);
-        val &= ~pmx->mode_reg.mask;
-        val |= mode->mask & pmx->mode_reg.mask;
-        writel(val, pmx->base + pmx->mode_reg.offset);
-        return 0;
-}
-/**
- * pmx_devs_enable - Enables list of devices
- * @devs - pointer to pmx device array
- * @count - number of devices to enable
- *
- * It will enable pads for all required peripherals once and only once.
- * If peripheral is not supported by current mode then request is rejected.
- * Conflicts between peripherals are not handled and peripherals will be
- * enabled in the order they are present in pmx_dev array.
- * In case of conflicts last peripheral enabled will be present.
- * Returns -ve on Err otherwise 0
- */
-static int pmx_devs_enable(struct pmx_dev **devs, u8 count)
-{
-        u32 val, i, mask;
-        if (!count)
-                return -EINVAL;
-        val = readl(pmx->base + pmx->mux_reg.offset);
-        for (i = 0; i < count; i++) {
-                u8 j = 0;
-                if (!devs[i]->name || !devs[i]->modes) {
-                        printk(KERN_ERR "padmux: dev name or modes is null\n");
-                        continue;
-                }
-                /* check if peripheral exists in active mode */
-                if (pmx->active_mode) {
-                        bool found = false;
-                        for (j = 0; j < devs[i]->mode_count; j++) {
-                                if (devs[i]->modes[j].ids &
-                                                pmx->active_mode->id) {
-                                        found = true;
-                                        break;
-                                }
-                        }
-                        if (found == false) {
-                                printk(KERN_ERR "%s device not available in %s"\
-                                                "mode\n", devs[i]->name,
-                                                pmx->active_mode->name);
-                                continue;
-                        }
-                }
-                /* enable peripheral */
-                mask = devs[i]->modes[j].mask & pmx->mux_reg.mask;
-                if (devs[i]->enb_on_reset)
-                        val &= ~mask;
-                else
-                        val |= mask;
-                devs[i]->is_active = true;
-        }
-        writel(val, pmx->base + pmx->mux_reg.offset);
-        kfree(pmx);
-        /* this will ensure that multiplexing can't be changed now */
-        pmx = (struct pmx *)-1;
-        return 0;
-}
-/**
- * pmx_register - registers a platform requesting pad mux feature
- * @driver - pointer to driver structure containing driver specific parameters
- *
- * Also this must be called only once. This will allocate memory for pmx
- * structure, will call pmx_mode_set, will call pmx_devs_enable.
- * Returns -ve on Err otherwise 0
- */
-int pmx_register(struct pmx_driver *driver)
-{
-        int ret = 0;
-        if (pmx)
-                return -EPERM;
-        if (!driver->base || !driver->devs)
-                return -EFAULT;
-        pmx = kzalloc(sizeof(*pmx), GFP_KERNEL);
-        if (!pmx)
-                return -ENOMEM;
-        pmx->base = (u32)driver->base;
-        pmx->mode_reg.offset = driver->mode_reg.offset;
-        pmx->mode_reg.mask = driver->mode_reg.mask;
-        pmx->mux_reg.offset = driver->mux_reg.offset;
-        pmx->mux_reg.mask = driver->mux_reg.mask;
-        /* choose mode to enable */
-        if (driver->mode) {
-                ret = pmx_mode_set(driver->mode);
-                if (ret)
-                        goto pmx_fail;
-        }
-        ret = pmx_devs_enable(driver->devs, driver->devs_count);
-        if (ret)
-                goto pmx_fail;
-        return 0;
-pmx_fail:
-        return ret;
-}
diff --git a/arch/arm/plat-spear/pl080.c b/arch/arm/plat-spear/pl080.c
new file mode 100644
index 000000000000..a56a067717c1
--- /dev/null
+++ b/arch/arm/plat-spear/pl080.c
@@ -0,0 +1,80 @@
+/*
+ * arch/arm/plat-spear/pl080.c
+ *
+ * DMAC pl080 definitions for SPEAr platform
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/amba/pl08x.h>
+#include <linux/amba/bus.h>
+#include <linux/bug.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/spinlock_types.h>
+#include <mach/spear.h>
+#include <mach/misc_regs.h>
+static spinlock_t lock = __SPIN_LOCK_UNLOCKED(x);
+struct {
+        unsigned char busy;
+        unsigned char val;
+} signals[16] = {{0, 0}, };
+int pl080_get_signal(struct pl08x_dma_chan *ch)
+{
+        const struct pl08x_channel_data *cd = ch->cd;
+        unsigned int signal = cd->min_signal, val;
+        unsigned long flags;
+        spin_lock_irqsave(&lock, flags);
+        /* Return if signal is already acquired by somebody else */
+        if (signals[signal].busy &&
+                        (signals[signal].val != cd->muxval)) {
+                spin_unlock_irqrestore(&lock, flags);
+                return -EBUSY;
+        }
+        /* If acquiring for the first time, configure it */
+        if (!signals[signal].busy) {
+                val = readl(DMA_CHN_CFG);
+                /*
+                 * Each request line has two bits in DMA_CHN_CFG register. To
+                 * goto the bits of current request line, do left shift of
+                 * value by 2 * signal number.
+                 */
+                val &= ~(0x3 << (signal * 2));
+                val |= cd->muxval << (signal * 2);
+                writel(val, DMA_CHN_CFG);
+        }
+        signals[signal].busy++;
+        signals[signal].val = cd->muxval;
+        spin_unlock_irqrestore(&lock, flags);
+        return signal;
+}
+void pl080_put_signal(struct pl08x_dma_chan *ch)
+{
+        const struct pl08x_channel_data *cd = ch->cd;
+        unsigned long flags;
+        spin_lock_irqsave(&lock, flags);
+        /* if signal is not used */
+        if (!signals[cd->min_signal].busy)
+                BUG();
+        signals[cd->min_signal].busy--;
+        spin_unlock_irqrestore(&lock, flags);
+}
diff --git a/arch/arm/plat-spear/restart.c b/arch/arm/plat-spear/restart.c
index 16f203e78d89..4471a232713a 100644
--- a/arch/arm/plat-spear/restart.c
+++ b/arch/arm/plat-spear/restart.c
@@ -13,7 +13,7 @@
 #include <linux/io.h>
 #include <asm/system_misc.h>
 #include <asm/hardware/sp810.h>
-#include <mach/hardware.h>
+#include <mach/spear.h>
 #include <mach/generic.h>
 void spear_restart(char mode, const char *cmd)
diff --git a/arch/arm/plat-spear/time.c b/arch/arm/plat-spear/time.c
index abb5bdecd509..a3164d1647fd 100644
--- a/arch/arm/plat-spear/time.c
+++ b/arch/arm/plat-spear/time.c
@@ -15,14 +15,13 @@
 #include <linux/err.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
+#include <linux/ioport.h>
 #include <linux/io.h>
 #include <linux/kernel.h>
 #include <linux/time.h>
 #include <linux/irq.h>
 #include <asm/mach/time.h>
 #include <mach/generic.h>
-#include <mach/hardware.h>
-#include <mach/irqs.h>
 /*
 * We would use TIMER0 and TIMER1 as clockevent and clocksource.
@@ -175,7 +174,7 @@ static struct irqaction spear_timer_irq = {
        .handler = spear_timer_interrupt
 };
-static void __init spear_clockevent_init(void)
+static void __init spear_clockevent_init(int irq)
 {
        u32 tick_rate;
@@ -195,19 +194,19 @@ static void __init spear_clockevent_init(void)
        clockevents_register_device(&clkevt);
-        setup_irq(SPEAR_GPT0_CHAN0_IRQ, &spear_timer_irq);
+        setup_irq(irq, &spear_timer_irq);
 }
-void __init spear_setup_timer(void)
+void __init spear_setup_timer(resource_size_t base, int irq)
 {
        int ret;
-        if (!request_mem_region(SPEAR_GPT0_BASE, SZ_1K, "gpt0")) {
+        if (!request_mem_region(base, SZ_1K, "gpt0")) {
                pr_err("%s:cannot get IO addr\n", __func__);
                return;
        }
-        gpt_base = (void __iomem *)ioremap(SPEAR_GPT0_BASE, SZ_1K);
+        gpt_base = ioremap(base, SZ_1K);
        if (!gpt_base) {
                pr_err("%s:ioremap failed for gpt\n", __func__);
                goto err_mem;
@@ -225,7 +224,7 @@ void __init spear_setup_timer(void)
                goto err_clk;
        }
-        spear_clockevent_init();
+        spear_clockevent_init(irq);
        spear_clocksource_init();
        return;
@@ -235,5 +234,5 @@ err_clk:
 err_iomap:
        iounmap(gpt_base);
 err_mem:
-        release_mem_region(SPEAR_GPT0_BASE, SZ_1K);
+        release_mem_region(base, SZ_1K);
 }
diff --git a/arch/arm/plat-versatile/Kconfig b/arch/arm/plat-versatile/Kconfig
index 043f7b02a9e7..81ee7cc34457 100644
--- a/arch/arm/plat-versatile/Kconfig
+++ b/arch/arm/plat-versatile/Kconfig
@@ -5,6 +5,12 @@ config PLAT_VERSATILE_CLCD
 config PLAT_VERSATILE_FPGA_IRQ
        bool
+        select IRQ_DOMAIN
+config PLAT_VERSATILE_FPGA_IRQ_NR
+       int
+       default 4
+       depends on PLAT_VERSATILE_FPGA_IRQ
 config PLAT_VERSATILE_LEDS
        def_bool y if LEDS_CLASS
diff --git a/arch/arm/plat-versatile/fpga-irq.c b/arch/arm/plat-versatile/fpga-irq.c
index f0cc8e19b094..6e70d03824a1 100644
--- a/arch/arm/plat-versatile/fpga-irq.c
+++ b/arch/arm/plat-versatile/fpga-irq.c
@@ -3,7 +3,10 @@
 */
 #include <linux/irq.h>
 #include <linux/io.h>
+#include <linux/irqdomain.h>
+#include <linux/module.h>
+#include <asm/exception.h>
 #include <asm/mach/irq.h>
 #include <plat/fpga-irq.h>
@@ -12,10 +15,32 @@
 #define IRQ_ENABLE_SET          0x08
 #define IRQ_ENABLE_CLEAR        0x0c
+/**
+ * struct fpga_irq_data - irq data container for the FPGA IRQ controller
+ * @base: memory offset in virtual memory
+ * @irq_start: first IRQ number handled by this instance
+ * @chip: chip container for this instance
+ * @domain: IRQ domain for this instance
+ * @valid: mask for valid IRQs on this controller
+ * @used_irqs: number of active IRQs on this controller
+ */
+struct fpga_irq_data {
+        void __iomem *base;
+        unsigned int irq_start;
+        struct irq_chip chip;
+        u32 valid;
+        struct irq_domain *domain;
+        u8 used_irqs;
+};
+/* we cannot allocate memory when the controllers are initially registered */
+static struct fpga_irq_data fpga_irq_devices[CONFIG_PLAT_VERSATILE_FPGA_IRQ_NR];
+static int fpga_irq_id;
 static void fpga_irq_mask(struct irq_data *d)
 {
        struct fpga_irq_data *f = irq_data_get_irq_chip_data(d);
-        u32 mask = 1 << (d->irq - f->irq_start);
+        u32 mask = 1 << d->hwirq;
        writel(mask, f->base + IRQ_ENABLE_CLEAR);
 }
@@ -23,7 +48,7 @@ static void fpga_irq_mask(struct irq_data *d)
 static void fpga_irq_unmask(struct irq_data *d)
 {
        struct fpga_irq_data *f = irq_data_get_irq_chip_data(d);
-        u32 mask = 1 << (d->irq - f->irq_start);
+        u32 mask = 1 << d->hwirq;
        writel(mask, f->base + IRQ_ENABLE_SET);
 }
@@ -41,32 +66,93 @@ static void fpga_irq_handle(unsigned int irq, struct irq_desc *desc)
        do {
                irq = ffs(status) - 1;
                status &= ~(1 << irq);
+                generic_handle_irq(irq_find_mapping(f->domain, irq));
-                generic_handle_irq(irq + f->irq_start);
        } while (status);
 }
-void __init fpga_irq_init(int parent_irq, u32 valid, struct fpga_irq_data *f)
+/*
+ * Handle each interrupt in a single FPGA IRQ controller.  Returns non-zero
+ * if we've handled at least one interrupt.  This does a single read of the
+ * status register and handles all interrupts in order from LSB first.
+ */
+static int handle_one_fpga(struct fpga_irq_data *f, struct pt_regs *regs)
+{
+        int handled = 0;
+        int irq;
+        u32 status;
+        while ((status  = readl(f->base + IRQ_STATUS))) {
+                irq = ffs(status) - 1;
+                handle_IRQ(irq_find_mapping(f->domain, irq), regs);
+                handled = 1;
+        }
+        return handled;
+}
+/*
+ * Keep iterating over all registered FPGA IRQ controllers until there are
+ * no pending interrupts.
+ */
+asmlinkage void __exception_irq_entry fpga_handle_irq(struct pt_regs *regs)
 {
-        unsigned int i;
+        int i, handled;
+        do {
+                for (i = 0, handled = 0; i < fpga_irq_id; ++i)
+                        handled |= handle_one_fpga(&fpga_irq_devices[i], regs);
+        } while (handled);
+}
+static int fpga_irqdomain_map(struct irq_domain *d, unsigned int irq,
+                irq_hw_number_t hwirq)
+{
+        struct fpga_irq_data *f = d->host_data;
+        /* Skip invalid IRQs, only register handlers for the real ones */
+        if (!(f->valid & (1 << hwirq)))
+                return -ENOTSUPP;
+        irq_set_chip_data(irq, f);
+        irq_set_chip_and_handler(irq, &f->chip,
+                                handle_level_irq);
+        set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+        f->used_irqs++;
+        return 0;
+}
+static struct irq_domain_ops fpga_irqdomain_ops = {
+        .map = fpga_irqdomain_map,
+        .xlate = irq_domain_xlate_onetwocell,
+};
+void __init fpga_irq_init(void __iomem *base, const char *name, int irq_start,
+                          int parent_irq, u32 valid, struct device_node *node)
+{
+        struct fpga_irq_data *f;
+        if (fpga_irq_id >= ARRAY_SIZE(fpga_irq_devices)) {
+                printk(KERN_ERR "%s: too few FPGA IRQ controllers, increase CONFIG_PLAT_VERSATILE_FPGA_IRQ_NR\n", __func__);
+                return;
+        }
+        f = &fpga_irq_devices[fpga_irq_id];
+        f->base = base;
+        f->irq_start = irq_start;
+        f->chip.name = name;
        f->chip.irq_ack = fpga_irq_mask;
        f->chip.irq_mask = fpga_irq_mask;
        f->chip.irq_unmask = fpga_irq_unmask;
+        f->valid = valid;
        if (parent_irq != -1) {
                irq_set_handler_data(parent_irq, f);
                irq_set_chained_handler(parent_irq, fpga_irq_handle);
        }
-        for (i = 0; i < 32; i++) {
+        f->domain = irq_domain_add_legacy(node, fls(valid), f->irq_start, 0,
-                if (valid & (1 << i)) {
+                                          &fpga_irqdomain_ops, f);
-                        unsigned int irq = f->irq_start + i;
+        pr_info("FPGA IRQ chip %d \"%s\" @ %p, %u irqs\n",
+                fpga_irq_id, name, base, f->used_irqs);
-                        irq_set_chip_data(irq, f);
+        fpga_irq_id++;
-                        irq_set_chip_and_handler(irq, &f->chip,
-                                                 handle_level_irq);
-                        set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
-                }
-        }
 }
diff --git a/arch/arm/plat-versatile/include/plat/fpga-irq.h b/arch/arm/plat-versatile/include/plat/fpga-irq.h
index 627fafd1e595..91bcfb67551d 100644
--- a/arch/arm/plat-versatile/include/plat/fpga-irq.h
+++ b/arch/arm/plat-versatile/include/plat/fpga-irq.h
@@ -1,12 +1,11 @@
 #ifndef PLAT_FPGA_IRQ_H
 #define PLAT_FPGA_IRQ_H
-struct fpga_irq_data {
+struct device_node;
-        void __iomem *base;
+struct pt_regs;
-        unsigned int irq_start;
-        struct irq_chip chip;
-};
-void fpga_irq_init(int, u32, struct fpga_irq_data *);
+void fpga_handle_irq(struct pt_regs *regs);
+void fpga_irq_init(void __iomem *, const char *, int, int, u32,
+                struct device_node *node);
 #endif
diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
index f9c9f33f8cbe..2997e56ce0dd 100644
--- a/arch/arm/tools/mach-types
+++ b/arch/arm/tools/mach-types
@@ -16,7 +16,7 @@
 # are merged into mainline or have been edited in the machine database
 # within the last 12 months.  References to machine_is_NAME() do not count!
 #
-# Last update: Tue Dec 6 11:07:38 2011
+# Last update: Thu Apr 26 08:44:23 2012
 #
 # machine_is_xxx        CONFIG_xxxx             MACH_TYPE_xxx           number
 #
@@ -205,6 +205,7 @@ omap_fsample		MACH_OMAP_FSAMPLE	OMAP_FSAMPLE		970
 snapper_cl15            MACH_SNAPPER_CL15       SNAPPER_CL15            986
 omap_palmz71            MACH_OMAP_PALMZ71       OMAP_PALMZ71            993
 smdk2412                MACH_SMDK2412           SMDK2412                1009
+bkde303                 MACH_BKDE303            BKDE303                 1021
 smdk2413                MACH_SMDK2413           SMDK2413                1022
 aml_m5900               MACH_AML_M5900          AML_M5900               1024
 balloon3                MACH_BALLOON3           BALLOON3                1029
@@ -381,8 +382,6 @@ davinci_da850_evm	MACH_DAVINCI_DA850_EVM	DAVINCI_DA850_EVM	2157
 at91sam9g10ek           MACH_AT91SAM9G10EK      AT91SAM9G10EK           2159
 omap_4430sdp            MACH_OMAP_4430SDP       OMAP_4430SDP            2160
 magx_zn5                MACH_MAGX_ZN5           MAGX_ZN5                2162
-btmavb101               MACH_BTMAVB101          BTMAVB101               2172
-btmawb101               MACH_BTMAWB101          BTMAWB101               2173
 tx25                    MACH_TX25               TX25                    2177
 omap3_torpedo           MACH_OMAP3_TORPEDO      OMAP3_TORPEDO           2178
 anw6410                 MACH_ANW6410            ANW6410                 2183
@@ -397,7 +396,6 @@ net2big_v2		MACH_NET2BIG_V2		NET2BIG_V2		2204
 net5big_v2              MACH_NET5BIG_V2         NET5BIG_V2              2206
 inetspace_v2            MACH_INETSPACE_V2       INETSPACE_V2            2208
 at91sam9g45ekes         MACH_AT91SAM9G45EKES    AT91SAM9G45EKES         2212
-pc7302                  MACH_PC7302             PC7302                  2220
 spear600                MACH_SPEAR600           SPEAR600                2236
 spear300                MACH_SPEAR300           SPEAR300                2237
 lilly1131               MACH_LILLY1131          LILLY1131               2239
@@ -407,7 +405,6 @@ d2net			MACH_D2NET		D2NET			2282
 bigdisk                 MACH_BIGDISK            BIGDISK                 2283
 at91sam9g20ek_2mmc      MACH_AT91SAM9G20EK_2MMC AT91SAM9G20EK_2MMC      2288
 bcmring                 MACH_BCMRING            BCMRING                 2289
-dp6xx                   MACH_DP6XX              DP6XX                   2302
 mahimahi                MACH_MAHIMAHI           MAHIMAHI                2304
 smdk6442                MACH_SMDK6442           SMDK6442                2324
 openrd_base             MACH_OPENRD_BASE        OPENRD_BASE             2325
@@ -444,8 +441,6 @@ mx28evk			MACH_MX28EVK		MX28EVK			2531
 smartq5                 MACH_SMARTQ5            SMARTQ5                 2534
 davinci_dm6467tevm      MACH_DAVINCI_DM6467TEVM DAVINCI_DM6467TEVM      2548
 mxt_td60                MACH_MXT_TD60           MXT_TD60                2550
-riot_bei2               MACH_RIOT_BEI2          RIOT_BEI2               2576
-riot_x37                MACH_RIOT_X37           RIOT_X37                2578
 pca101                  MACH_PCA101             PCA101                  2595
 capc7117                MACH_CAPC7117           CAPC7117                2612
 icontrol                MACH_ICONTROL           ICONTROL                2624
@@ -460,7 +455,6 @@ spear320		MACH_SPEAR320		SPEAR320		2661
 aquila                  MACH_AQUILA             AQUILA                  2676
 esata_sheevaplug        MACH_ESATA_SHEEVAPLUG   ESATA_SHEEVAPLUG        2678
 msm7x30_surf            MACH_MSM7X30_SURF       MSM7X30_SURF            2679
-ea2478devkit            MACH_EA2478DEVKIT       EA2478DEVKIT            2683
 terastation_wxl         MACH_TERASTATION_WXL    TERASTATION_WXL         2697
 msm7x25_surf            MACH_MSM7X25_SURF       MSM7X25_SURF            2703
 msm7x25_ffa             MACH_MSM7X25_FFA        MSM7X25_FFA             2704
@@ -479,8 +473,6 @@ wbd222			MACH_WBD222		WBD222			2753
 msm8x60_surf            MACH_MSM8X60_SURF       MSM8X60_SURF            2755
 msm8x60_sim             MACH_MSM8X60_SIM        MSM8X60_SIM             2756
 tcc8000_sdk             MACH_TCC8000_SDK        TCC8000_SDK             2758
-nanos                   MACH_NANOS              NANOS                   2759
-stamp9g45               MACH_STAMP9G45          STAMP9G45               2761
 cns3420vb               MACH_CNS3420VB          CNS3420VB               2776
 omap4_panda             MACH_OMAP4_PANDA        OMAP4_PANDA             2791
 ti8168evm               MACH_TI8168EVM          TI8168EVM               2800
@@ -490,12 +482,9 @@ eukrea_cpuimx35sd	MACH_EUKREA_CPUIMX35SD	EUKREA_CPUIMX35SD	2821
 eukrea_cpuimx51sd       MACH_EUKREA_CPUIMX51SD  EUKREA_CPUIMX51SD       2822
 eukrea_cpuimx51         MACH_EUKREA_CPUIMX51    EUKREA_CPUIMX51         2823
 smdkc210                MACH_SMDKC210           SMDKC210                2838
-pca102                  MACH_PCA102             PCA102                  2843
+pcaal1                  MACH_PCAAL1             PCAAL1                  2843
 t5325                   MACH_T5325              T5325                   2846
 income                  MACH_INCOME             INCOME                  2849
-vvbox_sdorig2           MACH_VVBOX_SDORIG2      VVBOX_SDORIG2           2857
-vvbox_sdlite2           MACH_VVBOX_SDLITE2      VVBOX_SDLITE2           2858
-vvbox_sdpro4            MACH_VVBOX_SDPRO4       VVBOX_SDPRO4            2859
 mx257sx                 MACH_MX257SX            MX257SX                 2861
 goni                    MACH_GONI               GONI                    2862
 bv07                    MACH_BV07               BV07                    2882
@@ -504,6 +493,7 @@ devixp			MACH_DEVIXP		DEVIXP			2885
 miccpt                  MACH_MICCPT             MICCPT                  2886
 mic256                  MACH_MIC256             MIC256                  2887
 u5500                   MACH_U5500              U5500                   2890
+pov15hd                 MACH_POV15HD            POV15HD                 2910
 linkstation_lschl       MACH_LINKSTATION_LSCHL  LINKSTATION_LSCHL       2913
 smdkv310                MACH_SMDKV310           SMDKV310                2925
 wm8505_7in_netbook      MACH_WM8505_7IN_NETBOOK WM8505_7IN_NETBOOK      2928
@@ -537,243 +527,24 @@ trimslice		MACH_TRIMSLICE		TRIMSLICE		3209
 mackerel                MACH_MACKEREL           MACKEREL                3211
 kaen                    MACH_KAEN               KAEN                    3217
 nokia_rm680             MACH_NOKIA_RM680        NOKIA_RM680             3220
-dm6446_adbox            MACH_DM6446_ADBOX       DM6446_ADBOX            3226
-quad_salsa              MACH_QUAD_SALSA         QUAD_SALSA              3227
-abb_gma_1_1             MACH_ABB_GMA_1_1        ABB_GMA_1_1             3228
-svcid                   MACH_SVCID              SVCID                   3229
 msm8960_sim             MACH_MSM8960_SIM        MSM8960_SIM             3230
 msm8960_rumi3           MACH_MSM8960_RUMI3      MSM8960_RUMI3           3231
-icon_g                  MACH_ICON_G             ICON_G                  3232
-mb3                     MACH_MB3                MB3                     3233
 gsia18s                 MACH_GSIA18S            GSIA18S                 3234
-pivicc                  MACH_PIVICC             PIVICC                  3235
-pcm048                  MACH_PCM048             PCM048                  3236
-dds                     MACH_DDS                DDS                     3237
-chalten_xa1             MACH_CHALTEN_XA1        CHALTEN_XA1             3238
-ts48xx                  MACH_TS48XX             TS48XX                  3239
-tonga2_tfttimer         MACH_TONGA2_TFTTIMER    TONGA2_TFTTIMER         3240
-whistler                MACH_WHISTLER           WHISTLER                3241
-asl_phoenix             MACH_ASL_PHOENIX        ASL_PHOENIX             3242
-at91sam9263otlite       MACH_AT91SAM9263OTLITE  AT91SAM9263OTLITE       3243
-ddplug                  MACH_DDPLUG             DDPLUG                  3244
-d2plug                  MACH_D2PLUG             D2PLUG                  3245
-kzm9d                   MACH_KZM9D              KZM9D                   3246
-verdi_lte               MACH_VERDI_LTE          VERDI_LTE               3247
-nanozoom                MACH_NANOZOOM           NANOZOOM                3248
-dm3730_som_lv           MACH_DM3730_SOM_LV      DM3730_SOM_LV           3249
-dm3730_torpedo          MACH_DM3730_TORPEDO     DM3730_TORPEDO          3250
-anchovy                 MACH_ANCHOVY            ANCHOVY                 3251
-re2rev20                MACH_RE2REV20           RE2REV20                3253
-re2rev21                MACH_RE2REV21           RE2REV21                3254
-cns21xx                 MACH_CNS21XX            CNS21XX                 3255
-rider                   MACH_RIDER              RIDER                   3257
-nsk330                  MACH_NSK330             NSK330                  3258
-cns2133evb              MACH_CNS2133EVB         CNS2133EVB              3259
-z3_816x_mod             MACH_Z3_816X_MOD        Z3_816X_MOD             3260
-z3_814x_mod             MACH_Z3_814X_MOD        Z3_814X_MOD             3261
-beect                   MACH_BEECT              BEECT                   3262
-dma_thunderbug          MACH_DMA_THUNDERBUG     DMA_THUNDERBUG          3263
-omn_at91sam9g20         MACH_OMN_AT91SAM9G20    OMN_AT91SAM9G20         3264
-mx25_e2s_uc             MACH_MX25_E2S_UC        MX25_E2S_UC             3265
-mione                   MACH_MIONE              MIONE                   3266
-top9000_tcu             MACH_TOP9000_TCU        TOP9000_TCU             3267
-top9000_bsl             MACH_TOP9000_BSL        TOP9000_BSL             3268
-kingdom                 MACH_KINGDOM            KINGDOM                 3269
-armadillo460            MACH_ARMADILLO460       ARMADILLO460            3270
-lq2                     MACH_LQ2                LQ2                     3271
-sweda_tms2              MACH_SWEDA_TMS2         SWEDA_TMS2              3272
 mx53_loco               MACH_MX53_LOCO          MX53_LOCO               3273
-acer_a8                 MACH_ACER_A8            ACER_A8                 3275
-acer_gauguin            MACH_ACER_GAUGUIN       ACER_GAUGUIN            3276
-guppy                   MACH_GUPPY              GUPPY                   3277
-mx61_ard                MACH_MX61_ARD           MX61_ARD                3278
 tx53                    MACH_TX53               TX53                    3279
-omapl138_case_a3        MACH_OMAPL138_CASE_A3   OMAPL138_CASE_A3        3280
-uemd                    MACH_UEMD               UEMD                    3281
-ccwmx51mut              MACH_CCWMX51MUT         CCWMX51MUT              3282
-rockhopper              MACH_ROCKHOPPER         ROCKHOPPER              3283
 encore                  MACH_ENCORE             ENCORE                  3284
-hkdkc100                MACH_HKDKC100           HKDKC100                3285
-ts42xx                  MACH_TS42XX             TS42XX                  3286
-aebl                    MACH_AEBL               AEBL                    3287
 wario                   MACH_WARIO              WARIO                   3288
-gfs_spm                 MACH_GFS_SPM            GFS_SPM                 3289
 cm_t3730                MACH_CM_T3730           CM_T3730                3290
-isc3                    MACH_ISC3               ISC3                    3291
-rascal                  MACH_RASCAL             RASCAL                  3292
 hrefv60                 MACH_HREFV60            HREFV60                 3293
-tpt_2_0                 MACH_TPT_2_0            TPT_2_0                 3294
-splendor                MACH_SPLENDOR           SPLENDOR                3296
-msm8x60_qt              MACH_MSM8X60_QT         MSM8X60_QT              3298
-htc_hd_mini             MACH_HTC_HD_MINI        HTC_HD_MINI             3299
-athene                  MACH_ATHENE             ATHENE                  3300
-deep_r_ek_1             MACH_DEEP_R_EK_1        DEEP_R_EK_1             3301
-vivow_ct                MACH_VIVOW_CT           VIVOW_CT                3302
-nery_1000               MACH_NERY_1000          NERY_1000               3303
-rfl109145_ssrv          MACH_RFL109145_SSRV     RFL109145_SSRV          3304
-nmh                     MACH_NMH                NMH                     3305
-wn802t                  MACH_WN802T             WN802T                  3306
-dragonet                MACH_DRAGONET           DRAGONET                3307
-at91sam9263desk16l      MACH_AT91SAM9263DESK16L AT91SAM9263DESK16L      3309
-bcmhana_sv              MACH_BCMHANA_SV         BCMHANA_SV              3310
-bcmhana_tablet          MACH_BCMHANA_TABLET     BCMHANA_TABLET          3311
-koi                     MACH_KOI                KOI                     3312
-ts4800                  MACH_TS4800             TS4800                  3313
-tqma9263                MACH_TQMA9263           TQMA9263                3314
-holiday                 MACH_HOLIDAY            HOLIDAY                 3315
-pcats_overlay           MACH_PCATS_OVERLAY      PCATS_OVERLAY           3317
-hwgw6410                MACH_HWGW6410           HWGW6410                3318
-shenzhou                MACH_SHENZHOU           SHENZHOU                3319
-cwme9210                MACH_CWME9210           CWME9210                3320
-cwme9210js              MACH_CWME9210JS         CWME9210JS              3321
-colibri_tegra2          MACH_COLIBRI_TEGRA2     COLIBRI_TEGRA2          3323
-w21                     MACH_W21                W21                     3324
-polysat1                MACH_POLYSAT1           POLYSAT1                3325
-dataway                 MACH_DATAWAY            DATAWAY                 3326
-cobral138               MACH_COBRAL138          COBRAL138               3327
-roverpcs8               MACH_ROVERPCS8          ROVERPCS8               3328
-marvelc                 MACH_MARVELC            MARVELC                 3329
-navefihid               MACH_NAVEFIHID          NAVEFIHID               3330
-dm365_cv100             MACH_DM365_CV100        DM365_CV100             3331
-able                    MACH_ABLE               ABLE                    3332
-legacy                  MACH_LEGACY             LEGACY                  3333
-icong                   MACH_ICONG              ICONG                   3334
-rover_g8                MACH_ROVER_G8           ROVER_G8                3335
-t5388p                  MACH_T5388P             T5388P                  3336
-dingo                   MACH_DINGO              DINGO                   3337
-goflexhome              MACH_GOFLEXHOME         GOFLEXHOME              3338
-lanreadyfn511           MACH_LANREADYFN511      LANREADYFN511           3340
-omap3_baia              MACH_OMAP3_BAIA         OMAP3_BAIA              3341
-omap3smartdisplay       MACH_OMAP3SMARTDISPLAY  OMAP3SMARTDISPLAY       3342
-xilinx                  MACH_XILINX             XILINX                  3343
-a2f                     MACH_A2F                A2F                     3344
-sky25                   MACH_SKY25              SKY25                   3345
-ccmx53                  MACH_CCMX53             CCMX53                  3346
-ccmx53js                MACH_CCMX53JS           CCMX53JS                3347
-ccwmx53                 MACH_CCWMX53            CCWMX53                 3348
-ccwmx53js               MACH_CCWMX53JS          CCWMX53JS               3349
-frisms                  MACH_FRISMS             FRISMS                  3350
-msm7x27a_ffa            MACH_MSM7X27A_FFA       MSM7X27A_FFA            3351
-msm7x27a_surf           MACH_MSM7X27A_SURF      MSM7X27A_SURF           3352
-msm7x27a_rumi3          MACH_MSM7X27A_RUMI3     MSM7X27A_RUMI3          3353
-dimmsam9g20             MACH_DIMMSAM9G20        DIMMSAM9G20             3354
-dimm_imx28              MACH_DIMM_IMX28         DIMM_IMX28              3355
-amk_a4                  MACH_AMK_A4             AMK_A4                  3356
-gnet_sgme               MACH_GNET_SGME          GNET_SGME               3357
-shooter_u               MACH_SHOOTER_U          SHOOTER_U               3358
-vmx53                   MACH_VMX53              VMX53                   3359
-rhino                   MACH_RHINO              RHINO                   3360
 armlex4210              MACH_ARMLEX4210         ARMLEX4210              3361
-swarcoextmodem          MACH_SWARCOEXTMODEM     SWARCOEXTMODEM          3362
 snowball                MACH_SNOWBALL           SNOWBALL                3363
-pcm049                  MACH_PCM049             PCM049                  3364
-vigor                   MACH_VIGOR              VIGOR                   3365
-oslo_amundsen           MACH_OSLO_AMUNDSEN      OSLO_AMUNDSEN           3366
-gsl_diamond             MACH_GSL_DIAMOND        GSL_DIAMOND             3367
-cv2201                  MACH_CV2201             CV2201                  3368
-cv2202                  MACH_CV2202             CV2202                  3369
-cv2203                  MACH_CV2203             CV2203                  3370
-vit_ibox                MACH_VIT_IBOX           VIT_IBOX                3371
-dm6441_esp              MACH_DM6441_ESP         DM6441_ESP              3372
-at91sam9x5ek            MACH_AT91SAM9X5EK       AT91SAM9X5EK            3373
-libra                   MACH_LIBRA              LIBRA                   3374
-easycrrh                MACH_EASYCRRH           EASYCRRH                3375
-tripel                  MACH_TRIPEL             TRIPEL                  3376
-endian_mini             MACH_ENDIAN_MINI        ENDIAN_MINI             3377
 xilinx_ep107            MACH_XILINX_EP107       XILINX_EP107            3378
 nuri                    MACH_NURI               NURI                    3379
-janus                   MACH_JANUS              JANUS                   3380
-ddnas                   MACH_DDNAS              DDNAS                   3381
-tag                     MACH_TAG                TAG                     3382
-tagw                    MACH_TAGW               TAGW                    3383
-nitrogen_vm_imx51       MACH_NITROGEN_VM_IMX51  NITROGEN_VM_IMX51       3384
-viprinet                MACH_VIPRINET           VIPRINET                3385
-bockw                   MACH_BOCKW              BOCKW                   3386
-eva2000                 MACH_EVA2000            EVA2000                 3387
-steelyard               MACH_STEELYARD          STEELYARD               3388
-nsslsboard              MACH_NSSLSBOARD         NSSLSBOARD              3392
-geneva_b5               MACH_GENEVA_B5          GENEVA_B5               3393
-spear1340               MACH_SPEAR1340          SPEAR1340               3394
-rexmas                  MACH_REXMAS             REXMAS                  3395
-msm8960_cdp             MACH_MSM8960_CDP        MSM8960_CDP             3396
-msm8960_fluid           MACH_MSM8960_FLUID      MSM8960_FLUID           3398
-msm8960_apq             MACH_MSM8960_APQ        MSM8960_APQ             3399
-helios_v2               MACH_HELIOS_V2          HELIOS_V2               3400
-mif10p                  MACH_MIF10P             MIF10P                  3401
-iam28                   MACH_IAM28              IAM28                   3402
-picasso                 MACH_PICASSO            PICASSO                 3403
-mr301a                  MACH_MR301A             MR301A                  3404
-notle                   MACH_NOTLE              NOTLE                   3405
-eelx2                   MACH_EELX2              EELX2                   3406
-moon                    MACH_MOON               MOON                    3407
-ruby                    MACH_RUBY               RUBY                    3408
-goldengate              MACH_GOLDENGATE         GOLDENGATE              3409
-ctbu_gen2               MACH_CTBU_GEN2          CTBU_GEN2               3410
-kmp_am17_01             MACH_KMP_AM17_01        KMP_AM17_01             3411
 wtplug                  MACH_WTPLUG             WTPLUG                  3412
-mx27su2                 MACH_MX27SU2            MX27SU2                 3413
-nb31                    MACH_NB31               NB31                    3414
-hjsdu                   MACH_HJSDU              HJSDU                   3415
-td3_rev1                MACH_TD3_REV1           TD3_REV1                3416
-eag_ci4000              MACH_EAG_CI4000         EAG_CI4000              3417
-net5big_nand_v2         MACH_NET5BIG_NAND_V2    NET5BIG_NAND_V2         3418
-cpx2                    MACH_CPX2               CPX2                    3419
-net2big_nand_v2         MACH_NET2BIG_NAND_V2    NET2BIG_NAND_V2         3420
-ecuv5                   MACH_ECUV5              ECUV5                   3421
-hsgx6d                  MACH_HSGX6D             HSGX6D                  3422
-dawad7                  MACH_DAWAD7             DAWAD7                  3423
-sam9repeater            MACH_SAM9REPEATER       SAM9REPEATER            3424
-gt_i5700                MACH_GT_I5700           GT_I5700                3425
-ctera_plug_c2           MACH_CTERA_PLUG_C2      CTERA_PLUG_C2           3426
-marvelct                MACH_MARVELCT           MARVELCT                3427
-ag11005                 MACH_AG11005            AG11005                 3428
-vangogh                 MACH_VANGOGH            VANGOGH                 3430
-matrix505               MACH_MATRIX505          MATRIX505               3431
-oce_nigma               MACH_OCE_NIGMA          OCE_NIGMA               3432
-t55                     MACH_T55                T55                     3433
-bio3k                   MACH_BIO3K              BIO3K                   3434
-expressct               MACH_EXPRESSCT          EXPRESSCT               3435
-cardhu                  MACH_CARDHU             CARDHU                  3436
-aruba                   MACH_ARUBA              ARUBA                   3437
-bonaire                 MACH_BONAIRE            BONAIRE                 3438
-nuc700evb               MACH_NUC700EVB          NUC700EVB               3439
-nuc710evb               MACH_NUC710EVB          NUC710EVB               3440
-nuc740evb               MACH_NUC740EVB          NUC740EVB               3441
-nuc745evb               MACH_NUC745EVB          NUC745EVB               3442
-transcede               MACH_TRANSCEDE          TRANSCEDE               3443
-mora                    MACH_MORA               MORA                    3444
-nda_evm                 MACH_NDA_EVM            NDA_EVM                 3445
-timu                    MACH_TIMU               TIMU                    3446
-expressh                MACH_EXPRESSH           EXPRESSH                3447
 veridis_a300            MACH_VERIDIS_A300       VERIDIS_A300            3448
-dm368_leopard           MACH_DM368_LEOPARD      DM368_LEOPARD           3449
-omap_mcop               MACH_OMAP_MCOP          OMAP_MCOP               3450
-tritip                  MACH_TRITIP             TRITIP                  3451
-sm1k                    MACH_SM1K               SM1K                    3452
-monch                   MACH_MONCH              MONCH                   3453
-curacao                 MACH_CURACAO            CURACAO                 3454
 origen                  MACH_ORIGEN             ORIGEN                  3455
-epc10                   MACH_EPC10              EPC10                   3456
-sgh_i740                MACH_SGH_I740           SGH_I740                3457
-tuna                    MACH_TUNA               TUNA                    3458
-mx51_tulip              MACH_MX51_TULIP         MX51_TULIP              3459
-mx51_aster7             MACH_MX51_ASTER7        MX51_ASTER7             3460
-acro37xbrd              MACH_ACRO37XBRD         ACRO37XBRD              3461
-elke                    MACH_ELKE               ELKE                    3462
-sbc6000x                MACH_SBC6000X           SBC6000X                3463
-r1801e                  MACH_R1801E             R1801E                  3464
-h1600                   MACH_H1600              H1600                   3465
-mini210                 MACH_MINI210            MINI210                 3466
-mini8168                MACH_MINI8168           MINI8168                3467
-pc7308                  MACH_PC7308             PC7308                  3468
-kmm2m01                 MACH_KMM2M01            KMM2M01                 3470
-mx51erebus              MACH_MX51EREBUS         MX51EREBUS              3471
 wm8650refboard          MACH_WM8650REFBOARD     WM8650REFBOARD          3472
-tuxrail                 MACH_TUXRAIL            TUXRAIL                 3473
-arthur                  MACH_ARTHUR             ARTHUR                  3474
-doorboy                 MACH_DOORBOY            DOORBOY                 3475
 xarina                  MACH_XARINA             XARINA                  3476
-roverx7                 MACH_ROVERX7            ROVERX7                 3477
 sdvr                    MACH_SDVR               SDVR                    3478
 acer_maya               MACH_ACER_MAYA          ACER_MAYA               3479
 pico                    MACH_PICO               PICO                    3480
@@ -999,6 +770,7 @@ promwad_jade		MACH_PROMWAD_JADE	PROMWAD_JADE		3708
 amp                     MACH_AMP                AMP                     3709
 gnet_amp                MACH_GNET_AMP           GNET_AMP                3710
 toques                  MACH_TOQUES             TOQUES                  3711
+apx4devkit              MACH_APX4DEVKIT         APX4DEVKIT              3712
 dct_storm               MACH_DCT_STORM          DCT_STORM               3713
 owl                     MACH_OWL                OWL                     3715
 cogent_csb1741          MACH_COGENT_CSB1741     COGENT_CSB1741          3716
@@ -1063,7 +835,6 @@ shelter			MACH_SHELTER		SHELTER			3778
 omap3_devkit8500        MACH_OMAP3_DEVKIT8500   OMAP3_DEVKIT8500        3779
 edgetd                  MACH_EDGETD             EDGETD                  3780
 copperyard              MACH_COPPERYARD         COPPERYARD              3781
-edge                    MACH_EDGE               EDGE                    3782
 edge_u                  MACH_EDGE_U             EDGE_U                  3783
 edge_td                 MACH_EDGE_TD            EDGE_TD                 3784
 wdss                    MACH_WDSS               WDSS                    3785
@@ -1169,3 +940,269 @@ elite_ulk		MACH_ELITE_ULK		ELITE_ULK		3888
 pov2                    MACH_POV2               POV2                    3889
 ipod_touch_2g           MACH_IPOD_TOUCH_2G      IPOD_TOUCH_2G           3890
 da850_pqab              MACH_DA850_PQAB         DA850_PQAB              3891
+fermi                   MACH_FERMI              FERMI                   3892
+ccardwmx28              MACH_CCARDWMX28         CCARDWMX28              3893
+ccardmx28               MACH_CCARDMX28          CCARDMX28               3894
+fs20_fcm2050            MACH_FS20_FCM2050       FS20_FCM2050            3895
+kinetis                 MACH_KINETIS            KINETIS                 3896
+kai                     MACH_KAI                KAI                     3897
+bcthb2                  MACH_BCTHB2             BCTHB2                  3898
+inels3_cu               MACH_INELS3_CU          INELS3_CU               3899
+da850_apollo            MACH_DA850_APOLLO       DA850_APOLLO            3901
+tracnas                 MACH_TRACNAS            TRACNAS                 3902
+mityarm335x             MACH_MITYARM335X        MITYARM335X             3903
+xcgz7x                  MACH_XCGZ7X             XCGZ7X                  3904
+cubox                   MACH_CUBOX              CUBOX                   3905
+terminator              MACH_TERMINATOR         TERMINATOR              3906
+eye03                   MACH_EYE03              EYE03                   3907
+kota3                   MACH_KOTA3              KOTA3                   3908
+pscpe                   MACH_PSCPE              PSCPE                   3910
+akt1100                 MACH_AKT1100            AKT1100                 3911
+pcaaxl2                 MACH_PCAAXL2            PCAAXL2                 3912
+primodd_ct              MACH_PRIMODD_CT         PRIMODD_CT              3913
+nsbc                    MACH_NSBC               NSBC                    3914
+meson2_skt              MACH_MESON2_SKT         MESON2_SKT              3915
+meson2_ref              MACH_MESON2_REF         MESON2_REF              3916
+ccardwmx28js            MACH_CCARDWMX28JS       CCARDWMX28JS            3917
+ccardmx28js             MACH_CCARDMX28JS        CCARDMX28JS             3918
+indico                  MACH_INDICO             INDICO                  3919
+msm8960dt               MACH_MSM8960DT          MSM8960DT               3920
+primods                 MACH_PRIMODS            PRIMODS                 3921
+beluga_m1388            MACH_BELUGA_M1388       BELUGA_M1388            3922
+primotd                 MACH_PRIMOTD            PRIMOTD                 3923
+varan_master            MACH_VARAN_MASTER       VARAN_MASTER            3924
+primodd                 MACH_PRIMODD            PRIMODD                 3925
+jetduo                  MACH_JETDUO             JETDUO                  3926
+mx53_umobo              MACH_MX53_UMOBO         MX53_UMOBO              3927
+trats                   MACH_TRATS              TRATS                   3928
+starcraft               MACH_STARCRAFT          STARCRAFT               3929
+qseven_tegra2           MACH_QSEVEN_TEGRA2      QSEVEN_TEGRA2           3930
+lichee_sun4i_devbd      MACH_LICHEE_SUN4I_DEVBD LICHEE_SUN4I_DEVBD      3931
+movenow                 MACH_MOVENOW            MOVENOW                 3932
+golf_u                  MACH_GOLF_U             GOLF_U                  3933
+msm7627a_evb            MACH_MSM7627A_EVB       MSM7627A_EVB            3934
+rambo                   MACH_RAMBO              RAMBO                   3935
+golfu                   MACH_GOLFU              GOLFU                   3936
+mango310                MACH_MANGO310           MANGO310                3937
+dns343                  MACH_DNS343             DNS343                  3938
+var_som_om44            MACH_VAR_SOM_OM44       VAR_SOM_OM44            3939
+naon                    MACH_NAON               NAON                    3940
+vp4000                  MACH_VP4000             VP4000                  3941
+impcard                 MACH_IMPCARD            IMPCARD                 3942
+smoovcam                MACH_SMOOVCAM           SMOOVCAM                3943
+cobham3725              MACH_COBHAM3725         COBHAM3725              3944
+cobham3730              MACH_COBHAM3730         COBHAM3730              3945
+cobham3703              MACH_COBHAM3703         COBHAM3703              3946
+quetzal                 MACH_QUETZAL            QUETZAL                 3947
+apq8064_cdp             MACH_APQ8064_CDP        APQ8064_CDP             3948
+apq8064_mtp             MACH_APQ8064_MTP        APQ8064_MTP             3949
+apq8064_fluid           MACH_APQ8064_FLUID      APQ8064_FLUID           3950
+apq8064_liquid          MACH_APQ8064_LIQUID     APQ8064_LIQUID          3951
+mango210                MACH_MANGO210           MANGO210                3952
+mango100                MACH_MANGO100           MANGO100                3953
+mango24                 MACH_MANGO24            MANGO24                 3954
+mango64                 MACH_MANGO64            MANGO64                 3955
+nsa320                  MACH_NSA320             NSA320                  3956
+elv_ccu2                MACH_ELV_CCU2           ELV_CCU2                3957
+triton_x00              MACH_TRITON_X00         TRITON_X00              3958
+triton_1500_2000        MACH_TRITON_1500_2000   TRITON_1500_2000        3959
+pogoplugv4              MACH_POGOPLUGV4         POGOPLUGV4              3960
+venus_cl                MACH_VENUS_CL           VENUS_CL                3961
+vulcano_g20             MACH_VULCANO_G20        VULCANO_G20             3962
+sgs_i9100               MACH_SGS_I9100          SGS_I9100               3963
+stsv2                   MACH_STSV2              STSV2                   3964
+csb1724                 MACH_CSB1724            CSB1724                 3965
+omapl138_lcdk           MACH_OMAPL138_LCDK      OMAPL138_LCDK           3966
+pvd_mx25                MACH_PVD_MX25           PVD_MX25                3968
+meson6_skt              MACH_MESON6_SKT         MESON6_SKT              3969
+meson6_ref              MACH_MESON6_REF         MESON6_REF              3970
+pxm                     MACH_PXM                PXM                     3971
+pogoplugv3              MACH_POGOPLUGV3         POGOPLUGV3              3973
+mlp89626                MACH_MLP89626           MLP89626                3974
+iomegahmndce            MACH_IOMEGAHMNDCE       IOMEGAHMNDCE            3975
+pogoplugv3pci           MACH_POGOPLUGV3PCI      POGOPLUGV3PCI           3976
+bntv250                 MACH_BNTV250            BNTV250                 3977
+mx53_qseven             MACH_MX53_QSEVEN        MX53_QSEVEN             3978
+gtl_it1100              MACH_GTL_IT1100         GTL_IT1100              3979
+mx6q_sabresd            MACH_MX6Q_SABRESD       MX6Q_SABRESD            3980
+mt4                     MACH_MT4                MT4                     3981
+jumbo_d                 MACH_JUMBO_D            JUMBO_D                 3982
+jumbo_i                 MACH_JUMBO_I            JUMBO_I                 3983
+fs20_dmp                MACH_FS20_DMP           FS20_DMP                3984
+dns320                  MACH_DNS320             DNS320                  3985
+mx28bacos               MACH_MX28BACOS          MX28BACOS               3986
+tl80                    MACH_TL80               TL80                    3987
+polatis_nic_1001        MACH_POLATIS_NIC_1001   POLATIS_NIC_1001        3988
+tely                    MACH_TELY               TELY                    3989
+u8520                   MACH_U8520              U8520                   3990
+manta                   MACH_MANTA              MANTA                   3991
+mpq8064_cdp             MACH_MPQ8064_CDP        MPQ8064_CDP             3993
+mpq8064_dtv             MACH_MPQ8064_DTV        MPQ8064_DTV             3995
+dm368som                MACH_DM368SOM           DM368SOM                3996
+gprisb2                 MACH_GPRISB2            GPRISB2                 3997
+chammid                 MACH_CHAMMID            CHAMMID                 3998
+seoul2                  MACH_SEOUL2             SEOUL2                  3999
+omap4_nooktablet        MACH_OMAP4_NOOKTABLET   OMAP4_NOOKTABLET        4000
+aalto                   MACH_AALTO              AALTO                   4001
+metro                   MACH_METRO              METRO                   4002
+cydm3730                MACH_CYDM3730           CYDM3730                4003
+tqma53                  MACH_TQMA53             TQMA53                  4004
+msm7627a_qrd3           MACH_MSM7627A_QRD3      MSM7627A_QRD3           4005
+mx28_canby              MACH_MX28_CANBY         MX28_CANBY              4006
+tiger                   MACH_TIGER              TIGER                   4007
+pcats_9307_type_a       MACH_PCATS_9307_TYPE_A  PCATS_9307_TYPE_A       4008
+pcats_9307_type_o       MACH_PCATS_9307_TYPE_O  PCATS_9307_TYPE_O       4009
+pcats_9307_type_r       MACH_PCATS_9307_TYPE_R  PCATS_9307_TYPE_R       4010
+streamplug              MACH_STREAMPLUG         STREAMPLUG              4011
+icechicken_dev          MACH_ICECHICKEN_DEV     ICECHICKEN_DEV          4012
+hedgehog                MACH_HEDGEHOG           HEDGEHOG                4013
+yusend_obc              MACH_YUSEND_OBC         YUSEND_OBC              4014
+imxninja                MACH_IMXNINJA           IMXNINJA                4015
+omap4_jarod             MACH_OMAP4_JAROD        OMAP4_JAROD             4016
+eco5_pk                 MACH_ECO5_PK            ECO5_PK                 4017
+qj2440                  MACH_QJ2440             QJ2440                  4018
+mx6q_mercury            MACH_MX6Q_MERCURY       MX6Q_MERCURY            4019
+cm6810                  MACH_CM6810             CM6810                  4020
+omap4_torpedo           MACH_OMAP4_TORPEDO      OMAP4_TORPEDO           4021
+nsa310                  MACH_NSA310             NSA310                  4022
+tmx536                  MACH_TMX536             TMX536                  4023
+ktt20                   MACH_KTT20              KTT20                   4024
+dragonix                MACH_DRAGONIX           DRAGONIX                4025
+lungching               MACH_LUNGCHING          LUNGCHING               4026
+bulogics                MACH_BULOGICS           BULOGICS                4027
+mx535_sx                MACH_MX535_SX           MX535_SX                4028
+ngui3250                MACH_NGUI3250           NGUI3250                4029
+salutec_dac             MACH_SALUTEC_DAC        SALUTEC_DAC             4030
+loco                    MACH_LOCO               LOCO                    4031
+ctera_plug_usi          MACH_CTERA_PLUG_USI     CTERA_PLUG_USI          4032
+scepter                 MACH_SCEPTER            SCEPTER                 4033
+sga                     MACH_SGA                SGA                     4034
+p_81_j5                 MACH_P_81_J5            P_81_J5                 4035
+p_81_o4                 MACH_P_81_O4            P_81_O4                 4036
+msm8625_surf            MACH_MSM8625_SURF       MSM8625_SURF            4037
+carallon_shark          MACH_CARALLON_SHARK     CARALLON_SHARK          4038
+ordog                   MACH_ORDOG              ORDOG                   4040
+puente_io               MACH_PUENTE_IO          PUENTE_IO               4041
+msm8625_evb             MACH_MSM8625_EVB        MSM8625_EVB             4042
+ev_am1707               MACH_EV_AM1707          EV_AM1707               4043
+ev_am1707e2             MACH_EV_AM1707E2        EV_AM1707E2             4044
+ev_am3517e2             MACH_EV_AM3517E2        EV_AM3517E2             4045
+calabria                MACH_CALABRIA           CALABRIA                4046
+ev_imx287               MACH_EV_IMX287          EV_IMX287               4047
+erau                    MACH_ERAU               ERAU                    4048
+sichuan                 MACH_SICHUAN            SICHUAN                 4049
+davinci_da850           MACH_DAVINCI_DA850      DAVINCI_DA850           4051
+omap138_trunarc         MACH_OMAP138_TRUNARC    OMAP138_TRUNARC         4052
+bcm4761                 MACH_BCM4761            BCM4761                 4053
+picasso_e2              MACH_PICASSO_E2         PICASSO_E2              4054
+picasso_mf              MACH_PICASSO_MF         PICASSO_MF              4055
+miro                    MACH_MIRO               MIRO                    4056
+at91sam9g20ewon3        MACH_AT91SAM9G20EWON3   AT91SAM9G20EWON3        4057
+yoyo                    MACH_YOYO               YOYO                    4058
+windjkl                 MACH_WINDJKL            WINDJKL                 4059
+monarudo                MACH_MONARUDO           MONARUDO                4060
+batan                   MACH_BATAN              BATAN                   4061
+tadao                   MACH_TADAO              TADAO                   4062
+baso                    MACH_BASO               BASO                    4063
+mahon                   MACH_MAHON              MAHON                   4064
+villec2                 MACH_VILLEC2            VILLEC2                 4065
+asi1230                 MACH_ASI1230            ASI1230                 4066
+alaska                  MACH_ALASKA             ALASKA                  4067
+swarco_shdsl2           MACH_SWARCO_SHDSL2      SWARCO_SHDSL2           4068
+oxrtu                   MACH_OXRTU              OXRTU                   4069
+omap5_panda             MACH_OMAP5_PANDA        OMAP5_PANDA             4070
+c8000                   MACH_C8000              C8000                   4072
+bje_display3_5          MACH_BJE_DISPLAY3_5     BJE_DISPLAY3_5          4073
+picomod7                MACH_PICOMOD7           PICOMOD7                4074
+picocom5                MACH_PICOCOM5           PICOCOM5                4075
+qblissa8                MACH_QBLISSA8           QBLISSA8                4076
+armstonea8              MACH_ARMSTONEA8         ARMSTONEA8              4077
+netdcu14                MACH_NETDCU14           NETDCU14                4078
+at91sam9x5_epiphan      MACH_AT91SAM9X5_EPIPHAN AT91SAM9X5_EPIPHAN      4079
+p2u                     MACH_P2U                P2U                     4080
+doris                   MACH_DORIS              DORIS                   4081
+j49                     MACH_J49                J49                     4082
+vdss2e                  MACH_VDSS2E             VDSS2E                  4083
+vc300                   MACH_VC300              VC300                   4084
+ns115_pad_test          MACH_NS115_PAD_TEST     NS115_PAD_TEST          4085
+ns115_pad_ref           MACH_NS115_PAD_REF      NS115_PAD_REF           4086
+ns115_phone_test        MACH_NS115_PHONE_TEST   NS115_PHONE_TEST        4087
+ns115_phone_ref         MACH_NS115_PHONE_REF    NS115_PHONE_REF         4088
+golfc                   MACH_GOLFC              GOLFC                   4089
+xerox_olympus           MACH_XEROX_OLYMPUS      XEROX_OLYMPUS           4090
+mx6sl_arm2              MACH_MX6SL_ARM2         MX6SL_ARM2              4091
+csb1701_csb1726         MACH_CSB1701_CSB1726    CSB1701_CSB1726         4092
+at91sam9xeek            MACH_AT91SAM9XEEK       AT91SAM9XEEK            4093
+ebv210                  MACH_EBV210             EBV210                  4094
+msm7627a_qrd7           MACH_MSM7627A_QRD7      MSM7627A_QRD7           4095
+svthin                  MACH_SVTHIN             SVTHIN                  4096
+duovero                 MACH_DUOVERO            DUOVERO                 4097
+chupacabra              MACH_CHUPACABRA         CHUPACABRA              4098
+scorpion                MACH_SCORPION           SCORPION                4099
+davinci_he_hmi10        MACH_DAVINCI_HE_HMI10   DAVINCI_HE_HMI10        4100
+topkick                 MACH_TOPKICK            TOPKICK                 4101
+m3_auguestrush          MACH_M3_AUGUESTRUSH     M3_AUGUESTRUSH          4102
+ipc335x                 MACH_IPC335X            IPC335X                 4103
+sun4i                   MACH_SUN4I              SUN4I                   4104
+imx233_olinuxino        MACH_IMX233_OLINUXINO   IMX233_OLINUXINO        4105
+k2_wl                   MACH_K2_WL              K2_WL                   4106
+k2_ul                   MACH_K2_UL              K2_UL                   4107
+k2_cl                   MACH_K2_CL              K2_CL                   4108
+minbari_w               MACH_MINBARI_W          MINBARI_W               4109
+minbari_m               MACH_MINBARI_M          MINBARI_M               4110
+k035                    MACH_K035               K035                    4111
+ariel                   MACH_ARIEL              ARIEL                   4112
+arielsaarc              MACH_ARIELSAARC         ARIELSAARC              4113
+arieldkb                MACH_ARIELDKB           ARIELDKB                4114
+armadillo810            MACH_ARMADILLO810       ARMADILLO810            4115
+tam335x                 MACH_TAM335X            TAM335X                 4116
+grouper                 MACH_GROUPER            GROUPER                 4117
+mpcsa21_9g20            MACH_MPCSA21_9G20       MPCSA21_9G20            4118
+m6u_cpu                 MACH_M6U_CPU            M6U_CPU                 4119
+davinci_dp10            MACH_DAVINCI_DP10       DAVINCI_DP10            4120
+ginkgo                  MACH_GINKGO             GINKGO                  4121
+cgt_qmx6                MACH_CGT_QMX6           CGT_QMX6                4122
+profpga                 MACH_PROFPGA            PROFPGA                 4123
+acfx100oc               MACH_ACFX100OC          ACFX100OC               4124
+acfx100nb               MACH_ACFX100NB          ACFX100NB               4125
+capricorn               MACH_CAPRICORN          CAPRICORN               4126
+pisces                  MACH_PISCES             PISCES                  4127
+aries                   MACH_ARIES              ARIES                   4128
+cancer                  MACH_CANCER             CANCER                  4129
+leo                     MACH_LEO                LEO                     4130
+virgo                   MACH_VIRGO              VIRGO                   4131
+sagittarius             MACH_SAGITTARIUS        SAGITTARIUS             4132
+devil                   MACH_DEVIL              DEVIL                   4133
+ballantines             MACH_BALLANTINES        BALLANTINES             4134
+omap3_procerusvpu       MACH_OMAP3_PROCERUSVPU  OMAP3_PROCERUSVPU       4135
+my27                    MACH_MY27               MY27                    4136
+sun6i                   MACH_SUN6I              SUN6I                   4137
+sun5i                   MACH_SUN5I              SUN5I                   4138
+mx512_mx                MACH_MX512_MX           MX512_MX                4139
+kzm9g                   MACH_KZM9G              KZM9G                   4140
+vdstbn                  MACH_VDSTBN             VDSTBN                  4141
+cfa10036                MACH_CFA10036           CFA10036                4142
+cfa10049                MACH_CFA10049           CFA10049                4143
+pcm051                  MACH_PCM051             PCM051                  4144
+vybrid_vf7xx            MACH_VYBRID_VF7XX       VYBRID_VF7XX            4145
+vybrid_vf6xx            MACH_VYBRID_VF6XX       VYBRID_VF6XX            4146
+vybrid_vf5xx            MACH_VYBRID_VF5XX       VYBRID_VF5XX            4147
+vybrid_vf4xx            MACH_VYBRID_VF4XX       VYBRID_VF4XX            4148
+aria_g25                MACH_ARIA_G25           ARIA_G25                4149
+bcm21553                MACH_BCM21553           BCM21553                4150
+smdk5410                MACH_SMDK5410           SMDK5410                4151
+lpc18xx                 MACH_LPC18XX            LPC18XX                 4152
+oratisparty             MACH_ORATISPARTY        ORATISPARTY             4153
+qseven                  MACH_QSEVEN             QSEVEN                  4154
+gmv_generic             MACH_GMV_GENERIC        GMV_GENERIC             4155
+th_link_eth             MACH_TH_LINK_ETH        TH_LINK_ETH             4156
+tn_muninn               MACH_TN_MUNINN          TN_MUNINN               4157
+rampage                 MACH_RAMPAGE            RAMPAGE                 4158
+visstrim_mv10           MACH_VISSTRIM_MV10      VISSTRIM_MV10           4159
+mx28_wilma              MACH_MX28_WILMA         MX28_WILMA              4164
+msm8625_ffa             MACH_MSM8625_FFA        MSM8625_FFA             4166
+vpu101                  MACH_VPU101             VPU101                  4167
+baileys                 MACH_BAILEYS            BAILEYS                 4169
+familybox               MACH_FAMILYBOX          FAMILYBOX               4170
+ensemble_mx35           MACH_ENSEMBLE_MX35      ENSEMBLE_MX35           4171
+sc_sps_1                MACH_SC_SPS_1           SC_SPS_1                4172
diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c
index 858748eaa144..586961929e96 100644
--- a/arch/arm/vfp/vfpmodule.c
+++ b/arch/arm/vfp/vfpmodule.c
@@ -11,12 +11,15 @@
 #include <linux/types.h>
 #include <linux/cpu.h>
 #include <linux/cpu_pm.h>
+#include <linux/hardirq.h>
 #include <linux/kernel.h>
 #include <linux/notifier.h>
 #include <linux/signal.h>
 #include <linux/sched.h>
 #include <linux/smp.h>
 #include <linux/init.h>
+#include <linux/uaccess.h>
+#include <linux/user.h>
 #include <asm/cp15.h>
 #include <asm/cputype.h>
@@ -238,11 +241,11 @@ static void vfp_panic(char *reason, u32 inst)
 {
        int i;
-        printk(KERN_ERR "VFP: Error: %s\n", reason);
+        pr_err("VFP: Error: %s\n", reason);
-        printk(KERN_ERR "VFP: EXC 0x%08x SCR 0x%08x INST 0x%08x\n",
+        pr_err("VFP: EXC 0x%08x SCR 0x%08x INST 0x%08x\n",
                fmrx(FPEXC), fmrx(FPSCR), inst);
        for (i = 0; i < 32; i += 2)
-                printk(KERN_ERR "VFP: s%2u: 0x%08x s%2u: 0x%08x\n",
+                pr_err("VFP: s%2u: 0x%08x s%2u: 0x%08x\n",
                       i, vfp_get_float(i), i+1, vfp_get_float(i+1));
 }
@@ -430,7 +433,10 @@ void VFP_bounce(u32 trigger, u32 fpexc, struct pt_regs *regs)
 static void vfp_enable(void *unused)
 {
-        u32 access = get_copro_access();
+        u32 access;
+        BUG_ON(preemptible());
+        access = get_copro_access();
        /*
         * Enable full access to VFP (cp10 and cp11)
@@ -446,7 +452,7 @@ static int vfp_pm_suspend(void)
        /* if vfp is on, then save state for resumption */
        if (fpexc & FPEXC_EN) {
-                printk(KERN_DEBUG "%s: saving vfp state\n", __func__);
+                pr_debug("%s: saving vfp state\n", __func__);
                vfp_save_state(&ti->vfpstate, fpexc);
                /* disable, just in case */
@@ -529,6 +535,93 @@ void vfp_flush_hwstate(struct thread_info *thread)
 }
 /*
+ * Save the current VFP state into the provided structures and prepare
+ * for entry into a new function (signal handler).
+ */
+int vfp_preserve_user_clear_hwstate(struct user_vfp __user *ufp,
+                                    struct user_vfp_exc __user *ufp_exc)
+{
+        struct thread_info *thread = current_thread_info();
+        struct vfp_hard_struct *hwstate = &thread->vfpstate.hard;
+        int err = 0;
+        /* Ensure that the saved hwstate is up-to-date. */
+        vfp_sync_hwstate(thread);
+        /*
+         * Copy the floating point registers. There can be unused
+         * registers see asm/hwcap.h for details.
+         */
+        err |= __copy_to_user(&ufp->fpregs, &hwstate->fpregs,
+                              sizeof(hwstate->fpregs));
+        /*
+         * Copy the status and control register.
+         */
+        __put_user_error(hwstate->fpscr, &ufp->fpscr, err);
+        /*
+         * Copy the exception registers.
+         */
+        __put_user_error(hwstate->fpexc, &ufp_exc->fpexc, err);
+        __put_user_error(hwstate->fpinst, &ufp_exc->fpinst, err);
+        __put_user_error(hwstate->fpinst2, &ufp_exc->fpinst2, err);
+        if (err)
+                return -EFAULT;
+        /* Ensure that VFP is disabled. */
+        vfp_flush_hwstate(thread);
+        /*
+         * As per the PCS, clear the length and stride bits for function
+         * entry.
+         */
+        hwstate->fpscr &= ~(FPSCR_LENGTH_MASK | FPSCR_STRIDE_MASK);
+        return 0;
+}
+/* Sanitise and restore the current VFP state from the provided structures. */
+int vfp_restore_user_hwstate(struct user_vfp __user *ufp,
+                             struct user_vfp_exc __user *ufp_exc)
+{
+        struct thread_info *thread = current_thread_info();
+        struct vfp_hard_struct *hwstate = &thread->vfpstate.hard;
+        unsigned long fpexc;
+        int err = 0;
+        /* Disable VFP to avoid corrupting the new thread state. */
+        vfp_flush_hwstate(thread);
+        /*
+         * Copy the floating point registers. There can be unused
+         * registers see asm/hwcap.h for details.
+         */
+        err |= __copy_from_user(&hwstate->fpregs, &ufp->fpregs,
+                                sizeof(hwstate->fpregs));
+        /*
+         * Copy the status and control register.
+         */
+        __get_user_error(hwstate->fpscr, &ufp->fpscr, err);
+        /*
+         * Sanitise and restore the exception registers.
+         */
+        __get_user_error(fpexc, &ufp_exc->fpexc, err);
+        /* Ensure the VFP is enabled. */
+        fpexc |= FPEXC_EN;
+        /* Ensure FPINST2 is invalid and the exception flag is cleared. */
+        fpexc &= ~(FPEXC_EX | FPEXC_FP2V);
+        hwstate->fpexc = fpexc;
+        __get_user_error(hwstate->fpinst, &ufp_exc->fpinst, err);
+        __get_user_error(hwstate->fpinst2, &ufp_exc->fpinst2, err);
+        return err ? -EFAULT : 0;
+}
+/*
 * VFP hardware can lose all context when a CPU goes offline.
 * As we will be running in SMP mode with CPU hotplug, we will save the
 * hardware state at every thread switch.  We clear our held state when
@@ -558,7 +651,7 @@ static int __init vfp_init(void)
        unsigned int cpu_arch = cpu_architecture();
        if (cpu_arch >= CPU_ARCH_ARMv6)
-                vfp_enable(NULL);
+                on_each_cpu(vfp_enable, NULL, 1);
        /*
         * First check that there is a VFP that we can use.
@@ -571,18 +664,16 @@ static int __init vfp_init(void)
        barrier();
        vfp_vector = vfp_null_entry;
-        printk(KERN_INFO "VFP support v0.3: ");
+        pr_info("VFP support v0.3: ");
        if (VFP_arch)
-                printk("not present\n");
+                pr_cont("not present\n");
        else if (vfpsid & FPSID_NODOUBLE) {
-                printk("no double precision support\n");
+                pr_cont("no double precision support\n");
        } else {
                hotcpu_notifier(vfp_hotplug, 0);
-                smp_call_function(vfp_enable, NULL, 1);
                VFP_arch = (vfpsid & FPSID_ARCH_MASK) >> FPSID_ARCH_BIT;  /* Extract the architecture version */
-                printk("implementor %02x architecture %d part %02x variant %x rev %x\n",
+                pr_cont("implementor %02x architecture %d part %02x variant %x rev %x\n",
                        (vfpsid & FPSID_IMPLEMENTER_MASK) >> FPSID_IMPLEMENTER_BIT,
                        (vfpsid & FPSID_ARCH_MASK) >> FPSID_ARCH_BIT,
                        (vfpsid & FPSID_PART_MASK) >> FPSID_PART_BIT,
diff --git a/arch/avr32/kernel/Makefile b/arch/avr32/kernel/Makefile
index 18229d0d1861..9e2c465ef3a6 100644
--- a/arch/avr32/kernel/Makefile
+++ b/arch/avr32/kernel/Makefile
@@ -8,7 +8,7 @@ obj-$(CONFIG_SUBARCH_AVR32B)	+= entry-avr32b.o
 obj-y                           += syscall_table.o syscall-stubs.o irq.o
 obj-y                           += setup.o traps.o ocd.o ptrace.o
 obj-y                           += signal.o sys_avr32.o process.o time.o
-obj-y                           += init_task.o switch_to.o cpu.o
+obj-y                           += switch_to.o cpu.o
 obj-$(CONFIG_MODULES)           += module.o avr32_ksyms.o
 obj-$(CONFIG_KPROBES)           += kprobes.o
 obj-$(CONFIG_STACKTRACE)        += stacktrace.o
diff --git a/arch/avr32/kernel/init_task.c b/arch/avr32/kernel/init_task.c
deleted file mode 100644
index 6b2343e6fe33..000000000000
--- a/arch/avr32/kernel/init_task.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * Copyright (C) 2004-2006 Atmel Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/module.h>
-#include <linux/fs.h>
-#include <linux/sched.h>
-#include <linux/init_task.h>
-#include <linux/mqueue.h>
-#include <asm/pgtable.h>
-static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
-static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
-/*
- * Initial thread structure. Must be aligned on an 8192-byte boundary.
- */
-union thread_union init_thread_union __init_task_data =
-        { INIT_THREAD_INFO(init_task) };
-/*
- * Initial task structure.
- *
- * All other task structs will be allocated on slabs in fork.c
- */
-struct task_struct init_task = INIT_TASK(init_task);
-EXPORT_SYMBOL(init_task);
diff --git a/arch/blackfin/ADI_BSD.txt b/arch/blackfin/ADI_BSD.txt
deleted file mode 100644
index 501d0b645943..000000000000
--- a/arch/blackfin/ADI_BSD.txt
+++ /dev/null
@@ -1,41 +0,0 @@
-This BSD-Style License applies to a few files in ./arch/blackfin directory,
-and is included here, so people understand which code they can use outside
-the Linux kernel, in non-GPL based projects.
-Using the files released under the "ADI BSD" license, must comply with
-these license terms.
--------------------------------------------------------------------------
-Copyright Analog Devices, Inc.
-All rights reserved.
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions
-are met:
-  - Redistributions of source code must retain the above copyright
-    notice, this list of conditions and the following disclaimer.
-  - Redistributions in binary form must reproduce the above copyright
-    notice, this list of conditions and the following disclaimer in
-    the documentation and/or other materials provided with the
-    distribution.
-  - Neither the name of Analog Devices, Inc. nor the names of its
-    contributors may be used to endorse or promote products derived
-    from this software without specific prior written permission.
-  - The use of this software may or may not infringe the patent rights
-    of one or more patent holders.  This license does not release you
-    from the requirement that you obtain separate licenses from these
-    patent holders to use this software.
-THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
-IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
-MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
-IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
-INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-BUT NOT LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF
-SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
diff --git a/arch/blackfin/Clear_BSD.txt b/arch/blackfin/Clear_BSD.txt
new file mode 100644
index 000000000000..bfa4b378a368
--- /dev/null
+++ b/arch/blackfin/Clear_BSD.txt
@@ -0,0 +1,33 @@
+The Clear BSD license:
+Copyright (c) 2012, Analog Devices, Inc.  All rights reserved.
+Redistribution and use in source and binary forms, with or without
+modification, are permitted (subject to the limitations in the
+disclaimer below) provided that the following conditions are met:
+* Redistributions of source code must retain the above copyright
+   notice, this list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright
+   notice, this list of conditions and the following disclaimer in the
+   documentation and/or other materials provided with the
+   distribution.
+* Neither the name of Analog Devices, Inc.  nor the names of its
+   contributors may be used to endorse or promote products derived
+   from this software without specific prior written permission.
+NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
+GRANTED BY THIS LICENSE.  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
+HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
+WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index b83e89ced988..79cfe2614bcc 100644
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -37,6 +37,7 @@ config BLACKFIN
        select GENERIC_IRQ_PROBE
        select IRQ_PER_CPU if SMP
        select HAVE_NMI_WATCHDOG if NMI_WATCHDOG
+        select GENERIC_SMP_IDLE_THREAD
 config GENERIC_CSUM
        def_bool y
@@ -226,6 +227,12 @@ config BF561
        help
          BF561 Processor Support.
+config BF609
+        bool "BF609"
+        select CLKDEV_LOOKUP
+        help
+          BF609 Processor Support.
 endchoice
 config SMP
@@ -251,27 +258,27 @@ config HOTPLUG_CPU
 config BF_REV_MIN
        int
-        default 0 if (BF51x || BF52x || (BF54x && !BF54xM))
+        default 0 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x
        default 2 if (BF537 || BF536 || BF534)
        default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
        default 4 if (BF538 || BF539)
 config BF_REV_MAX
        int
-        default 2 if (BF51x || BF52x || (BF54x && !BF54xM))
+        default 2 if (BF51x || BF52x || (BF54x && !BF54xM)) || BF60x
        default 3 if (BF537 || BF536 || BF534 || BF54xM)
        default 5 if (BF561 || BF538 || BF539)
        default 6 if (BF533 || BF532 || BF531)
 choice
        prompt "Silicon Rev"
-        default BF_REV_0_0 if (BF51x || BF52x)
+        default BF_REV_0_0 if (BF51x || BF52x || BF60x)
        default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
        default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
 config BF_REV_0_0
        bool "0.0"
-        depends on (BF51x || BF52x || (BF54x && !BF54xM))
+        depends on (BF51x || BF52x || (BF54x && !BF54xM) || BF60x)
 config BF_REV_0_1
        bool "0.1"
@@ -350,6 +357,7 @@ source "arch/blackfin/mach-bf561/Kconfig"
 source "arch/blackfin/mach-bf537/Kconfig"
 source "arch/blackfin/mach-bf538/Kconfig"
 source "arch/blackfin/mach-bf548/Kconfig"
+source "arch/blackfin/mach-bf609/Kconfig"
 menu "Board customizations"
@@ -379,6 +387,12 @@ config BOOT_LOAD
          memory region is used to capture NULL pointer references as well
          as some core kernel functions.
+config PHY_RAM_BASE_ADDRESS
+        hex "Physical RAM Base"
+        default 0x0
+        help
+          set BF609 FPGA physical SRAM base address
 config ROM_BASE
        hex "Kernel ROM Base"
        depends on ROMKERNEL
@@ -422,7 +436,7 @@ config BFIN_KERNEL_CLOCK
 config PLL_BYPASS
        bool "Bypass PLL"
-        depends on BFIN_KERNEL_CLOCK
+        depends on BFIN_KERNEL_CLOCK && (!BF60x)
        default n
 config CLKIN_HALF
@@ -441,7 +455,7 @@ config VCO_MULT
        default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
        default "22" if BFIN533_BLUETECHNIX_CM
        default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
-        default "20" if BFIN561_EZKIT
+        default "20" if (BFIN561_EZKIT || BF609)
        default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
        default "25" if BFIN527_AD7160EVAL
        help
@@ -473,12 +487,45 @@ config SCLK_DIV
        int "System Clock Divider"
        depends on BFIN_KERNEL_CLOCK
        range 1 15
-        default 5
+        default 4
        help
-          This sets the frequency of the system clock (including SDRAM or DDR).
+          This sets the frequency of the system clock (including SDRAM or DDR) on
+          !BF60x else it set the clock for system buses and provides the
+          source from which SCLK0 and SCLK1 are derived.
          This can be between 1 and 15
          System Clock = (PLL frequency) / (this setting)
+config SCLK0_DIV
+        int "System Clock0 Divider"
+        depends on BFIN_KERNEL_CLOCK && BF60x
+        range 1 15
+        default 1
+        help
+          This sets the frequency of the system clock0 for PVP and all other
+          peripherals not clocked by SCLK1.
+          This can be between 1 and 15
+          System Clock0 = (System Clock) / (this setting)
+config SCLK1_DIV
+        int "System Clock1 Divider"
+        depends on BFIN_KERNEL_CLOCK && BF60x
+        range 1 15
+        default 1
+        help
+          This sets the frequency of the system clock1 (including SPORT, SPI and ACM).
+          This can be between 1 and 15
+          System Clock1 = (System Clock) / (this setting)
+config DCLK_DIV
+        int "DDR Clock Divider"
+        depends on BFIN_KERNEL_CLOCK && BF60x
+        range 1 15
+        default 2
+        help
+          This sets the frequency of the DDR memory.
+          This can be between 1 and 15
+          DDR Clock = (PLL frequency) / (this setting)
 choice
        prompt "DDR SDRAM Chip Type"
        depends on BFIN_KERNEL_CLOCK
@@ -494,7 +541,7 @@ endchoice
 choice
        prompt "DDR/SDRAM Timing"
-        depends on BFIN_KERNEL_CLOCK
+        depends on BFIN_KERNEL_CLOCK && !BF60x
        default BFIN_KERNEL_CLOCK_MEMINIT_CALC
        help
          This option allows you to specify Blackfin SDRAM/DDR Timing parameters
@@ -576,6 +623,7 @@ config MAX_VCO_HZ
        default 600000000 if BF548
        default 533333333 if BF549
        default 600000000 if BF561
+        default 800000000 if BF609
 config MIN_VCO_HZ
        int
@@ -583,6 +631,7 @@ config MIN_VCO_HZ
 config MAX_SCLK_HZ
        int
+        default 200000000 if BF609
        default 133333333
 config MIN_SCLK_HZ
@@ -1051,7 +1100,7 @@ endchoice
 config BFIN_L2_DCACHEABLE
        bool "Enable DCACHE for L2 SRAM"
        depends on BFIN_DCACHE
-        depends on (BF54x || BF561) && !SMP
+        depends on (BF54x || BF561 || BF60x) && !SMP
        default n
 choice
        prompt "L2 SRAM DCACHE policy"
@@ -1077,6 +1126,7 @@ config MPU
 comment "Asynchronous Memory Configuration"
 menu "EBIU_AMGCTL Global Control"
+        depends on !BF60x
 config C_AMCKEN
        bool "Enable CLKOUT"
        default y
@@ -1127,6 +1177,7 @@ endchoice
 endmenu
 menu "EBIU_AMBCTL Control"
+        depends on !BF60x
 config BANK_0
        hex "Bank 0 (AMBCTL0.L)"
        default 0x7BB0
@@ -1206,7 +1257,7 @@ config ARCH_SUSPEND_POSSIBLE
 choice
        prompt "Standby Power Saving Mode"
-        depends on PM
+        depends on PM && !BF60x
        default PM_BFIN_SLEEP_DEEPER
 config  PM_BFIN_SLEEP_DEEPER
        bool "Sleep Deeper"
@@ -1261,6 +1312,118 @@ config PM_BFIN_WAKE_GP
          On ADSP-BF549 this option enables the same functionality on the
          /MRXON pin also PH7.
+config PM_BFIN_WAKE_PA15
+        bool "Allow Wake-Up from PA15"
+        depends on PM && BF60x
+        default n
+        help
+          Enable PA15 Wake-Up
+config PM_BFIN_WAKE_PA15_POL
+        int "Wake-up priority"
+        depends on PM_BFIN_WAKE_PA15
+        default 0
+        help
+          Wake-Up priority 0(low) 1(high)
+config PM_BFIN_WAKE_PB15
+        bool "Allow Wake-Up from PB15"
+        depends on PM && BF60x
+        default n
+        help
+          Enable PB15 Wake-Up
+config PM_BFIN_WAKE_PB15_POL
+        int "Wake-up priority"
+        depends on PM_BFIN_WAKE_PB15
+        default 0
+        help
+          Wake-Up priority 0(low) 1(high)
+config PM_BFIN_WAKE_PC15
+        bool "Allow Wake-Up from PC15"
+        depends on PM && BF60x
+        default n
+        help
+          Enable PC15 Wake-Up
+config PM_BFIN_WAKE_PC15_POL
+        int "Wake-up priority"
+        depends on PM_BFIN_WAKE_PC15
+        default 0
+        help
+          Wake-Up priority 0(low) 1(high)
+config PM_BFIN_WAKE_PD06
+        bool "Allow Wake-Up from PD06(ETH0_PHYINT)"
+        depends on PM && BF60x
+        default n
+        help
+          Enable PD06(ETH0_PHYINT) Wake-up
+config PM_BFIN_WAKE_PD06_POL
+        int "Wake-up priority"
+        depends on PM_BFIN_WAKE_PD06
+        default 0
+        help
+          Wake-Up priority 0(low) 1(high)
+config PM_BFIN_WAKE_PE12
+        bool "Allow Wake-Up from PE12(ETH1_PHYINT, PUSH BUTTON)"
+        depends on PM && BF60x
+        default n
+        help
+          Enable PE12(ETH1_PHYINT, PUSH BUTTON) Wake-up
+config PM_BFIN_WAKE_PE12_POL
+        int "Wake-up priority"
+        depends on PM_BFIN_WAKE_PE12
+        default 0
+        help
+          Wake-Up priority 0(low) 1(high)
+config PM_BFIN_WAKE_PG04
+        bool "Allow Wake-Up from PG04(CAN0_RX)"
+        depends on PM && BF60x
+        default n
+        help
+          Enable PG04(CAN0_RX) Wake-up
+config PM_BFIN_WAKE_PG04_POL
+        int "Wake-up priority"
+        depends on PM_BFIN_WAKE_PG04
+        default 0
+        help
+          Wake-Up priority 0(low) 1(high)
+config PM_BFIN_WAKE_PG13
+        bool "Allow Wake-Up from PG13"
+        depends on PM && BF60x
+        default n
+        help
+          Enable PG13 Wake-Up
+config PM_BFIN_WAKE_PG13_POL
+        int "Wake-up priority"
+        depends on PM_BFIN_WAKE_PG13
+        default 0
+        help
+          Wake-Up priority 0(low) 1(high)
+config PM_BFIN_WAKE_USB
+        bool "Allow Wake-Up from (USB)"
+        depends on PM && BF60x
+        default n
+        help
+          Enable (USB) Wake-up
+config PM_BFIN_WAKE_USB_POL
+        int "Wake-up priority"
+        depends on PM_BFIN_WAKE_USB
+        default 0
+        help
+          Wake-Up priority 0(low) 1(high)
 endmenu
 menu "CPU Frequency scaling"
diff --git a/arch/blackfin/Kconfig.debug b/arch/blackfin/Kconfig.debug
index e2a3d4c8ab9a..79594694ee90 100644
--- a/arch/blackfin/Kconfig.debug
+++ b/arch/blackfin/Kconfig.debug
@@ -253,4 +253,11 @@ config BFIN_PSEUDODBG_INSNS
          Most people should say N here.
+config BFIN_PM_WAKEUP_TIME_BENCH
+        bool "Display the total time for kernel to resume from power saving mode"
+        default n
+        help
+          Display the total time when kernel resumes normal from standby or
+          suspend to mem mode.
 endmenu
diff --git a/arch/blackfin/Makefile b/arch/blackfin/Makefile
index 46f42b2066e5..d3d7e64ca96d 100644
--- a/arch/blackfin/Makefile
+++ b/arch/blackfin/Makefile
@@ -54,6 +54,7 @@ machine-$(CONFIG_BF548M) := bf548
 machine-$(CONFIG_BF549)  := bf548
 machine-$(CONFIG_BF549M) := bf548
 machine-$(CONFIG_BF561)  := bf561
+machine-$(CONFIG_BF609)  := bf609
 MACHINE := $(machine-y)
 export MACHINE
@@ -86,6 +87,7 @@ cpu-$(CONFIG_BF548M) := bf548m
 cpu-$(CONFIG_BF549)  := bf549
 cpu-$(CONFIG_BF549M) := bf549m
 cpu-$(CONFIG_BF561)  := bf561
+cpu-$(CONFIG_BF609)  := bf609
 rev-$(CONFIG_BF_REV_0_0)  := 0.0
 rev-$(CONFIG_BF_REV_0_1)  := 0.1
@@ -107,8 +109,6 @@ KBUILD_AFLAGS += -mcpu=$(CPU_REV)
 CHECKFLAGS_SILICON = $(shell echo "" | $(CPP) $(KBUILD_CFLAGS) -dD - 2>/dev/null | awk '$$2 == "__SILICON_REVISION__" { print $$3 }')
 CHECKFLAGS += -D__SILICON_REVISION__=$(CHECKFLAGS_SILICON) -D__bfin__
-head-y   := arch/$(ARCH)/kernel/init_task.o
 core-y   += arch/$(ARCH)/kernel/ arch/$(ARCH)/mm/ arch/$(ARCH)/mach-common/
 # If we have a machine-specific directory, then include it in the build.
diff --git a/arch/blackfin/configs/BF561-EZKIT-SMP_defconfig b/arch/blackfin/configs/BF561-EZKIT-SMP_defconfig
index 680730eeaf23..e2a2fa5935ce 100644
--- a/arch/blackfin/configs/BF561-EZKIT-SMP_defconfig
+++ b/arch/blackfin/configs/BF561-EZKIT-SMP_defconfig
@@ -21,14 +21,12 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_IOSCHED_CFQ is not set
 CONFIG_PREEMPT_VOLUNTARY=y
 CONFIG_BF561=y
+CONFIG_SMP=y
 CONFIG_IRQ_TIMER0=10
 CONFIG_CLKIN_HZ=30000000
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
 CONFIG_BFIN_GPTIMERS=m
-CONFIG_BFIN_EXTMEM_WRITETHROUGH=y
-CONFIG_BFIN_L2_DCACHEABLE=y
-CONFIG_BFIN_L2_WRITETHROUGH=y
 CONFIG_C_CDPRIO=y
 CONFIG_BANK_3=0xAAC2
 CONFIG_BINFMT_FLAT=y
diff --git a/arch/blackfin/configs/BF609-EZKIT_defconfig b/arch/blackfin/configs/BF609-EZKIT_defconfig
new file mode 100644
index 000000000000..be9526bee4fb
--- /dev/null
+++ b/arch/blackfin/configs/BF609-EZKIT_defconfig
@@ -0,0 +1,155 @@
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EXPERT=y
+# CONFIG_ELF_CORE is not set
+# CONFIG_FUTEX is not set
+# CONFIG_SIGNALFD is not set
+# CONFIG_TIMERFD is not set
+# CONFIG_EVENTFD is not set
+# CONFIG_AIO is not set
+CONFIG_SLAB=y
+CONFIG_MMAP_ALLOW_UNINITIALIZED=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_LBDAF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_PREEMPT_VOLUNTARY=y
+CONFIG_BF609=y
+CONFIG_PINT1_ASSIGN=0x01010000
+CONFIG_PINT2_ASSIGN=0x07000101
+CONFIG_PINT3_ASSIGN=0x02020303
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_IP_CHECKSUM_L1=y
+CONFIG_SYSCALL_TAB_L1=y
+CONFIG_CPLB_SWITCH_TAB_L1=y
+# CONFIG_APP_STACK_L1 is not set
+# CONFIG_BFIN_INS_LOWOVERHEAD is not set
+CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
+CONFIG_BINFMT_FLAT=y
+CONFIG_BINFMT_ZFLAT=y
+CONFIG_PM_BFIN_WAKE_PE12=y
+CONFIG_PM_BFIN_WAKE_PE12_POL=1
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_IPV6 is not set
+CONFIG_NETFILTER=y
+CONFIG_CAN=y
+CONFIG_CAN_BFIN=y
+CONFIG_IRDA=y
+CONFIG_IRTTY_SIR=y
+# CONFIG_WIRELESS is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_FW_LOADER=m
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_UBI=m
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_NETDEVICES=y
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CHELSIO is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MICROCHIP is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+CONFIG_STMMAC_ETH=y
+CONFIG_STMMAC_IEEE1588=y
+# CONFIG_WLAN is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_BFIN_ROTARY=y
+# CONFIG_SERIO is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_BFIN_SIMPLE_TIMER=m
+CONFIG_BFIN_LINKPORT=y
+# CONFIG_DEVKMEM is not set
+CONFIG_SERIAL_BFIN=y
+CONFIG_SERIAL_BFIN_CONSOLE=y
+CONFIG_SERIAL_BFIN_UART0=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_BLACKFIN_TWI=y
+CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
+CONFIG_SPI=y
+CONFIG_SPI_BFIN6XX=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_SYSFS=y
+# CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_BFIN_WDT=y
+CONFIG_SOUND=m
+CONFIG_SND=m
+CONFIG_SND_MIXER_OSS=m
+CONFIG_SND_PCM_OSS=m
+# CONFIG_SND_DRIVERS is not set
+# CONFIG_SND_SPI is not set
+# CONFIG_SND_USB is not set
+CONFIG_SND_SOC=m
+CONFIG_SND_BF6XX_I2S=m
+CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61=m
+CONFIG_SND_SOC_ALL_CODECS=m
+CONFIG_USB=y
+CONFIG_USB_MUSB_HDRC=y
+CONFIG_USB_MUSB_BLACKFIN=m
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MUSB_HDRC=y
+CONFIG_USB_ZERO=y
+CONFIG_MMC=y
+CONFIG_SDH_BFIN=y
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_EXT2_FS=y
+# CONFIG_DNOTIFY is not set
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_JFFS2_FS=m
+CONFIG_UBIFS_FS=m
+CONFIG_NFS_FS=m
+CONFIG_NFS_V3=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_DEBUG_FS=y
+CONFIG_DEBUG_SHIRQ=y
+CONFIG_DETECT_HUNG_TASK=y
+CONFIG_DEBUG_INFO=y
+CONFIG_FRAME_POINTER=y
+# CONFIG_FTRACE is not set
+CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_CPLB_INFO=y
+CONFIG_BFIN_PSEUDODBG_INSNS=y
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_MD4=y
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_ARC4=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/blackfin/include/asm/bfin-global.h b/arch/blackfin/include/asm/bfin-global.h
index 17bcbf60bcae..608be5e6d25c 100644
--- a/arch/blackfin/include/asm/bfin-global.h
+++ b/arch/blackfin/include/asm/bfin-global.h
@@ -35,6 +35,11 @@ extern void bfin_setup_cpudata(unsigned int cpu);
 extern unsigned long get_cclk(void);
 extern unsigned long get_sclk(void);
+#ifdef CONFIG_BF60x
+extern unsigned long get_sclk0(void);
+extern unsigned long get_sclk1(void);
+extern unsigned long get_dclk(void);
+#endif
 extern unsigned long sclk_to_usecs(unsigned long sclk);
 extern unsigned long usecs_to_sclk(unsigned long usecs);
diff --git a/arch/blackfin/include/asm/bfin6xx_spi.h b/arch/blackfin/include/asm/bfin6xx_spi.h
new file mode 100644
index 000000000000..89370b653dcd
--- /dev/null
+++ b/arch/blackfin/include/asm/bfin6xx_spi.h
@@ -0,0 +1,258 @@
+/*
+ * Analog Devices SPI3 controller driver
+ *
+ * Copyright (c) 2011 Analog Devices Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#ifndef _SPI_CHANNEL_H_
+#define _SPI_CHANNEL_H_
+#include <linux/types.h>
+/* SPI_CONTROL */
+#define SPI_CTL_EN                  0x00000001    /* Enable */
+#define SPI_CTL_MSTR                0x00000002    /* Master/Slave */
+#define SPI_CTL_PSSE                0x00000004    /* controls modf error in master mode */
+#define SPI_CTL_ODM                 0x00000008    /* Open Drain Mode */
+#define SPI_CTL_CPHA                0x00000010    /* Clock Phase */
+#define SPI_CTL_CPOL                0x00000020    /* Clock Polarity */
+#define SPI_CTL_ASSEL               0x00000040    /* Slave Select Pin Control */
+#define SPI_CTL_SELST               0x00000080    /* Slave Select Polarity in-between transfers */
+#define SPI_CTL_EMISO               0x00000100    /* Enable MISO */
+#define SPI_CTL_SIZE                0x00000600    /* Word Transfer Size */
+#define SPI_CTL_SIZE08              0x00000000    /* SIZE: 8 bits */
+#define SPI_CTL_SIZE16              0x00000200    /* SIZE: 16 bits */
+#define SPI_CTL_SIZE32              0x00000400    /* SIZE: 32 bits */
+#define SPI_CTL_LSBF                0x00001000    /* LSB First */
+#define SPI_CTL_FCEN                0x00002000    /* Flow-Control Enable */
+#define SPI_CTL_FCCH                0x00004000    /* Flow-Control Channel Selection */
+#define SPI_CTL_FCPL                0x00008000    /* Flow-Control Polarity */
+#define SPI_CTL_FCWM                0x00030000    /* Flow-Control Water-Mark */
+#define SPI_CTL_FIFO0               0x00000000    /* FCWM: TFIFO empty or RFIFO Full */
+#define SPI_CTL_FIFO1               0x00010000    /* FCWM: TFIFO 75% or more empty or RFIFO 75% or more full */
+#define SPI_CTL_FIFO2               0x00020000    /* FCWM: TFIFO 50% or more empty or RFIFO 50% or more full */
+#define SPI_CTL_FMODE               0x00040000    /* Fast-mode Enable */
+#define SPI_CTL_MIOM                0x00300000    /* Multiple I/O Mode */
+#define SPI_CTL_MIO_DIS             0x00000000    /* MIOM: Disable */
+#define SPI_CTL_MIO_DUAL            0x00100000    /* MIOM: Enable DIOM (Dual I/O Mode) */
+#define SPI_CTL_MIO_QUAD            0x00200000    /* MIOM: Enable QUAD (Quad SPI Mode) */
+#define SPI_CTL_SOSI                0x00400000    /* Start on MOSI */
+/* SPI_RX_CONTROL */
+#define SPI_RXCTL_REN               0x00000001    /* Receive Channel Enable */
+#define SPI_RXCTL_RTI               0x00000004    /* Receive Transfer Initiate */
+#define SPI_RXCTL_RWCEN             0x00000008    /* Receive Word Counter Enable */
+#define SPI_RXCTL_RDR               0x00000070    /* Receive Data Request */
+#define SPI_RXCTL_RDR_DIS           0x00000000    /* RDR: Disabled */
+#define SPI_RXCTL_RDR_NE            0x00000010    /* RDR: RFIFO not empty */
+#define SPI_RXCTL_RDR_25            0x00000020    /* RDR: RFIFO 25% full */
+#define SPI_RXCTL_RDR_50            0x00000030    /* RDR: RFIFO 50% full */
+#define SPI_RXCTL_RDR_75            0x00000040    /* RDR: RFIFO 75% full */
+#define SPI_RXCTL_RDR_FULL          0x00000050    /* RDR: RFIFO full */
+#define SPI_RXCTL_RDO               0x00000100    /* Receive Data Over-Run */
+#define SPI_RXCTL_RRWM              0x00003000    /* FIFO Regular Water-Mark */
+#define SPI_RXCTL_RWM_0             0x00000000    /* RRWM: RFIFO Empty */
+#define SPI_RXCTL_RWM_25            0x00001000    /* RRWM: RFIFO 25% full */
+#define SPI_RXCTL_RWM_50            0x00002000    /* RRWM: RFIFO 50% full */
+#define SPI_RXCTL_RWM_75            0x00003000    /* RRWM: RFIFO 75% full */
+#define SPI_RXCTL_RUWM              0x00070000    /* FIFO Urgent Water-Mark */
+#define SPI_RXCTL_UWM_DIS           0x00000000    /* RUWM: Disabled */
+#define SPI_RXCTL_UWM_25            0x00010000    /* RUWM: RFIFO 25% full */
+#define SPI_RXCTL_UWM_50            0x00020000    /* RUWM: RFIFO 50% full */
+#define SPI_RXCTL_UWM_75            0x00030000    /* RUWM: RFIFO 75% full */
+#define SPI_RXCTL_UWM_FULL          0x00040000    /* RUWM: RFIFO full */
+/* SPI_TX_CONTROL */
+#define SPI_TXCTL_TEN               0x00000001    /* Transmit Channel Enable */
+#define SPI_TXCTL_TTI               0x00000004    /* Transmit Transfer Initiate */
+#define SPI_TXCTL_TWCEN             0x00000008    /* Transmit Word Counter Enable */
+#define SPI_TXCTL_TDR               0x00000070    /* Transmit Data Request */
+#define SPI_TXCTL_TDR_DIS           0x00000000    /* TDR: Disabled */
+#define SPI_TXCTL_TDR_NF            0x00000010    /* TDR: TFIFO not full */
+#define SPI_TXCTL_TDR_25            0x00000020    /* TDR: TFIFO 25% empty */
+#define SPI_TXCTL_TDR_50            0x00000030    /* TDR: TFIFO 50% empty */
+#define SPI_TXCTL_TDR_75            0x00000040    /* TDR: TFIFO 75% empty */
+#define SPI_TXCTL_TDR_EMPTY         0x00000050    /* TDR: TFIFO empty */
+#define SPI_TXCTL_TDU               0x00000100    /* Transmit Data Under-Run */
+#define SPI_TXCTL_TRWM              0x00003000    /* FIFO Regular Water-Mark */
+#define SPI_TXCTL_RWM_FULL          0x00000000    /* TRWM: TFIFO full */
+#define SPI_TXCTL_RWM_25            0x00001000    /* TRWM: TFIFO 25% empty */
+#define SPI_TXCTL_RWM_50            0x00002000    /* TRWM: TFIFO 50% empty */
+#define SPI_TXCTL_RWM_75            0x00003000    /* TRWM: TFIFO 75% empty */
+#define SPI_TXCTL_TUWM              0x00070000    /* FIFO Urgent Water-Mark */
+#define SPI_TXCTL_UWM_DIS           0x00000000    /* TUWM: Disabled */
+#define SPI_TXCTL_UWM_25            0x00010000    /* TUWM: TFIFO 25% empty */
+#define SPI_TXCTL_UWM_50            0x00020000    /* TUWM: TFIFO 50% empty */
+#define SPI_TXCTL_UWM_75            0x00030000    /* TUWM: TFIFO 75% empty */
+#define SPI_TXCTL_UWM_EMPTY         0x00040000    /* TUWM: TFIFO empty */
+/* SPI_CLOCK */
+#define SPI_CLK_BAUD                0x0000FFFF    /* Baud Rate */
+/* SPI_DELAY */
+#define SPI_DLY_STOP                0x000000FF    /* Transfer delay time in multiples of SCK period */
+#define SPI_DLY_LEADX               0x00000100    /* Extended (1 SCK) LEAD Control */
+#define SPI_DLY_LAGX                0x00000200    /* Extended (1 SCK) LAG control */
+/* SPI_SSEL */
+#define SPI_SLVSEL_SSE1             0x00000002    /* SPISSEL1 Enable */
+#define SPI_SLVSEL_SSE2             0x00000004    /* SPISSEL2 Enable */
+#define SPI_SLVSEL_SSE3             0x00000008    /* SPISSEL3 Enable */
+#define SPI_SLVSEL_SSE4             0x00000010    /* SPISSEL4 Enable */
+#define SPI_SLVSEL_SSE5             0x00000020    /* SPISSEL5 Enable */
+#define SPI_SLVSEL_SSE6             0x00000040    /* SPISSEL6 Enable */
+#define SPI_SLVSEL_SSE7             0x00000080    /* SPISSEL7 Enable */
+#define SPI_SLVSEL_SSEL1            0x00000200    /* SPISSEL1 Value */
+#define SPI_SLVSEL_SSEL2            0x00000400    /* SPISSEL2 Value */
+#define SPI_SLVSEL_SSEL3            0x00000800    /* SPISSEL3 Value */
+#define SPI_SLVSEL_SSEL4            0x00001000    /* SPISSEL4 Value */
+#define SPI_SLVSEL_SSEL5            0x00002000    /* SPISSEL5 Value */
+#define SPI_SLVSEL_SSEL6            0x00004000    /* SPISSEL6 Value */
+#define SPI_SLVSEL_SSEL7            0x00008000    /* SPISSEL7 Value */
+/* SPI_RWC */
+#define SPI_RWC_VALUE               0x0000FFFF    /* Received Word-Count */
+/* SPI_RWCR */
+#define SPI_RWCR_VALUE              0x0000FFFF    /* Received Word-Count Reload */
+/* SPI_TWC */
+#define SPI_TWC_VALUE               0x0000FFFF    /* Transmitted Word-Count */
+/* SPI_TWCR */
+#define SPI_TWCR_VALUE              0x0000FFFF    /* Transmitted Word-Count Reload */
+/* SPI_IMASK */
+#define SPI_IMSK_RUWM               0x00000002    /* Receive Urgent Water-Mark Interrupt Mask */
+#define SPI_IMSK_TUWM               0x00000004    /* Transmit Urgent Water-Mark Interrupt Mask */
+#define SPI_IMSK_ROM                0x00000010    /* Receive Over-Run Error Interrupt Mask */
+#define SPI_IMSK_TUM                0x00000020    /* Transmit Under-Run Error Interrupt Mask */
+#define SPI_IMSK_TCM                0x00000040    /* Transmit Collision Error Interrupt Mask */
+#define SPI_IMSK_MFM                0x00000080    /* Mode Fault Error Interrupt Mask */
+#define SPI_IMSK_RSM                0x00000100    /* Receive Start Interrupt Mask */
+#define SPI_IMSK_TSM                0x00000200    /* Transmit Start Interrupt Mask */
+#define SPI_IMSK_RFM                0x00000400    /* Receive Finish Interrupt Mask */
+#define SPI_IMSK_TFM                0x00000800    /* Transmit Finish Interrupt Mask */
+/* SPI_IMASKCL */
+#define SPI_IMSK_CLR_RUW            0x00000002    /* Receive Urgent Water-Mark Interrupt Mask */
+#define SPI_IMSK_CLR_TUWM           0x00000004    /* Transmit Urgent Water-Mark Interrupt Mask */
+#define SPI_IMSK_CLR_ROM            0x00000010    /* Receive Over-Run Error Interrupt Mask */
+#define SPI_IMSK_CLR_TUM            0x00000020    /* Transmit Under-Run Error Interrupt Mask */
+#define SPI_IMSK_CLR_TCM            0x00000040    /* Transmit Collision Error Interrupt Mask */
+#define SPI_IMSK_CLR_MFM            0x00000080    /* Mode Fault Error Interrupt Mask */
+#define SPI_IMSK_CLR_RSM            0x00000100    /* Receive Start Interrupt Mask */
+#define SPI_IMSK_CLR_TSM            0x00000200    /* Transmit Start Interrupt Mask */
+#define SPI_IMSK_CLR_RFM            0x00000400    /* Receive Finish Interrupt Mask */
+#define SPI_IMSK_CLR_TFM            0x00000800    /* Transmit Finish Interrupt Mask */
+/* SPI_IMASKST */
+#define SPI_IMSK_SET_RUWM           0x00000002    /* Receive Urgent Water-Mark Interrupt Mask */
+#define SPI_IMSK_SET_TUWM           0x00000004    /* Transmit Urgent Water-Mark Interrupt Mask */
+#define SPI_IMSK_SET_ROM            0x00000010    /* Receive Over-Run Error Interrupt Mask */
+#define SPI_IMSK_SET_TUM            0x00000020    /* Transmit Under-Run Error Interrupt Mask */
+#define SPI_IMSK_SET_TCM            0x00000040    /* Transmit Collision Error Interrupt Mask */
+#define SPI_IMSK_SET_MFM            0x00000080    /* Mode Fault Error Interrupt Mask */
+#define SPI_IMSK_SET_RSM            0x00000100    /* Receive Start Interrupt Mask */
+#define SPI_IMSK_SET_TSM            0x00000200    /* Transmit Start Interrupt Mask */
+#define SPI_IMSK_SET_RFM            0x00000400    /* Receive Finish Interrupt Mask */
+#define SPI_IMSK_SET_TFM            0x00000800    /* Transmit Finish Interrupt Mask */
+/* SPI_STATUS */
+#define SPI_STAT_SPIF               0x00000001    /* SPI Finished */
+#define SPI_STAT_RUWM               0x00000002    /* Receive Urgent Water-Mark Breached */
+#define SPI_STAT_TUWM               0x00000004    /* Transmit Urgent Water-Mark Breached */
+#define SPI_STAT_ROE                0x00000010    /* Receive Over-Run Error Indication */
+#define SPI_STAT_TUE                0x00000020    /* Transmit Under-Run Error Indication */
+#define SPI_STAT_TCE                0x00000040    /* Transmit Collision Error Indication */
+#define SPI_STAT_MODF               0x00000080    /* Mode Fault Error Indication */
+#define SPI_STAT_RS                 0x00000100    /* Receive Start Indication */
+#define SPI_STAT_TS                 0x00000200    /* Transmit Start Indication */
+#define SPI_STAT_RF                 0x00000400    /* Receive Finish Indication */
+#define SPI_STAT_TF                 0x00000800    /* Transmit Finish Indication */
+#define SPI_STAT_RFS                0x00007000    /* SPI_RFIFO status */
+#define SPI_STAT_RFIFO_EMPTY        0x00000000    /* RFS: RFIFO Empty */
+#define SPI_STAT_RFIFO_25           0x00001000    /* RFS: RFIFO 25% Full */
+#define SPI_STAT_RFIFO_50           0x00002000    /* RFS: RFIFO 50% Full */
+#define SPI_STAT_RFIFO_75           0x00003000    /* RFS: RFIFO 75% Full */
+#define SPI_STAT_RFIFO_FULL         0x00004000    /* RFS: RFIFO Full */
+#define SPI_STAT_TFS                0x00070000    /* SPI_TFIFO status */
+#define SPI_STAT_TFIFO_FULL         0x00000000    /* TFS: TFIFO full */
+#define SPI_STAT_TFIFO_25           0x00010000    /* TFS: TFIFO 25% empty */
+#define SPI_STAT_TFIFO_50           0x00020000    /* TFS: TFIFO 50% empty */
+#define SPI_STAT_TFIFO_75           0x00030000    /* TFS: TFIFO 75% empty */
+#define SPI_STAT_TFIFO_EMPTY        0x00040000    /* TFS: TFIFO empty */
+#define SPI_STAT_FCS                0x00100000    /* Flow-Control Stall Indication */
+#define SPI_STAT_RFE                0x00400000    /* SPI_RFIFO Empty */
+#define SPI_STAT_TFF                0x00800000    /* SPI_TFIFO Full */
+/* SPI_ILAT */
+#define SPI_ILAT_RUWMI              0x00000002    /* Receive Urgent Water Mark Interrupt */
+#define SPI_ILAT_TUWMI              0x00000004    /* Transmit Urgent Water Mark Interrupt */
+#define SPI_ILAT_ROI                0x00000010    /* Receive Over-Run Error Indication */
+#define SPI_ILAT_TUI                0x00000020    /* Transmit Under-Run Error Indication */
+#define SPI_ILAT_TCI                0x00000040    /* Transmit Collision Error Indication */
+#define SPI_ILAT_MFI                0x00000080    /* Mode Fault Error Indication */
+#define SPI_ILAT_RSI                0x00000100    /* Receive Start Indication */
+#define SPI_ILAT_TSI                0x00000200    /* Transmit Start Indication */
+#define SPI_ILAT_RFI                0x00000400    /* Receive Finish Indication */
+#define SPI_ILAT_TFI                0x00000800    /* Transmit Finish Indication */
+/* SPI_ILATCL */
+#define SPI_ILAT_CLR_RUWMI          0x00000002    /* Receive Urgent Water Mark Interrupt */
+#define SPI_ILAT_CLR_TUWMI          0x00000004    /* Transmit Urgent Water Mark Interrupt */
+#define SPI_ILAT_CLR_ROI            0x00000010    /* Receive Over-Run Error Indication */
+#define SPI_ILAT_CLR_TUI            0x00000020    /* Transmit Under-Run Error Indication */
+#define SPI_ILAT_CLR_TCI            0x00000040    /* Transmit Collision Error Indication */
+#define SPI_ILAT_CLR_MFI            0x00000080    /* Mode Fault Error Indication */
+#define SPI_ILAT_CLR_RSI            0x00000100    /* Receive Start Indication */
+#define SPI_ILAT_CLR_TSI            0x00000200    /* Transmit Start Indication */
+#define SPI_ILAT_CLR_RFI            0x00000400    /* Receive Finish Indication */
+#define SPI_ILAT_CLR_TFI            0x00000800    /* Transmit Finish Indication */
+/*
+ * bfin spi3 registers layout
+ */
+struct bfin_spi_regs {
+        u32 revid;
+        u32 control;
+        u32 rx_control;
+        u32 tx_control;
+        u32 clock;
+        u32 delay;
+        u32 ssel;
+        u32 rwc;
+        u32 rwcr;
+        u32 twc;
+        u32 twcr;
+        u32 reserved0;
+        u32 emask;
+        u32 emaskcl;
+        u32 emaskst;
+        u32 reserved1;
+        u32 status;
+        u32 elat;
+        u32 elatcl;
+        u32 reserved2;
+        u32 rfifo;
+        u32 reserved3;
+        u32 tfifo;
+};
+#define MAX_CTRL_CS          8  /* cs in spi controller */
+/* device.platform_data for SSP controller devices */
+struct bfin6xx_spi_master {
+        u16 num_chipselect;
+        u16 pin_req[7];
+};
+/* spi_board_info.controller_data for SPI slave devices,
+ * copied to spi_device.platform_data ... mostly for dma tuning
+ */
+struct bfin6xx_spi_chip {
+        u32 control;
+        u16 cs_chg_udelay; /* Some devices require 16-bit delays */
+        u32 tx_dummy_val; /* tx value for rx only transfer */
+        bool enable_dma;
+};
+#endif /* _SPI_CHANNEL_H_ */
diff --git a/arch/blackfin/include/asm/bfin_crc.h b/arch/blackfin/include/asm/bfin_crc.h
new file mode 100644
index 000000000000..3deb4452ceed
--- /dev/null
+++ b/arch/blackfin/include/asm/bfin_crc.h
@@ -0,0 +1,139 @@
+/*
+ * bfin_crc.h - interface to Blackfin CRC controllers
+ *
+ * Copyright 2012 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+#ifndef __BFIN_CRC_H__
+#define __BFIN_CRC_H__
+/* Function driver which use hardware crc must initialize the structure */
+struct crc_info {
+        /* Input data address */
+        unsigned char *in_addr;
+        /* Output data address */
+        unsigned char *out_addr;
+        /* Input or output bytes */
+        unsigned long datasize;
+        union {
+        /* CRC to compare with that of input buffer */
+        unsigned long crc_compare;
+        /* Value to compare with input data */
+        unsigned long val_verify;
+        /* Value to fill */
+        unsigned long val_fill;
+        };
+        /* Value to program the 32b CRC Polynomial */
+        unsigned long crc_poly;
+        union {
+        /* CRC calculated from the input data */
+        unsigned long crc_result;
+        /* First failed position to verify input data */
+        unsigned long pos_verify;
+        };
+        /* CRC mirror flags */
+        unsigned int bitmirr:1;
+        unsigned int bytmirr:1;
+        unsigned int w16swp:1;
+        unsigned int fdsel:1;
+        unsigned int rsltmirr:1;
+        unsigned int polymirr:1;
+        unsigned int cmpmirr:1;
+};
+/* Userspace interface */
+#define CRC_IOC_MAGIC           'C'
+#define CRC_IOC_CALC_CRC        _IOWR('C', 0x01, unsigned int)
+#define CRC_IOC_MEMCPY_CRC      _IOWR('C', 0x02, unsigned int)
+#define CRC_IOC_VERIFY_VAL      _IOWR('C', 0x03, unsigned int)
+#define CRC_IOC_FILL_VAL        _IOWR('C', 0x04, unsigned int)
+#ifdef __KERNEL__
+#include <linux/types.h>
+#include <linux/spinlock.h>
+#include <linux/miscdevice.h>
+struct crc_register {
+        u32 control;
+        u32 datacnt;
+        u32 datacntrld;
+        u32 __pad_1[2];
+        u32 compare;
+        u32 fillval;
+        u32 datafifo;
+        u32 intren;
+        u32 intrenset;
+        u32 intrenclr;
+        u32 poly;
+        u32 __pad_2[4];
+        u32 status;
+        u32 datacntcap;
+        u32 __pad_3;
+        u32 result;
+        u32 curresult;
+        u32 __pad_4[3];
+        u32 revid;
+};
+struct bfin_crc {
+        struct miscdevice mdev;
+        struct list_head list;
+        int irq;
+        int dma_ch_src;
+        int dma_ch_dest;
+        volatile struct crc_register *regs;
+        struct crc_info *info;
+        struct mutex mutex;
+        struct completion c;
+        unsigned short opmode;
+        char name[20];
+};
+/* CRC_STATUS Masks */
+#define CMPERR                  0x00000002      /* Compare error */
+#define DCNTEXP                 0x00000010      /* datacnt register expired */
+#define IBR                     0x00010000      /* Input buffer ready */
+#define OBR                     0x00020000      /* Output buffer ready */
+#define IRR                     0x00040000      /* Immediate result readt */
+#define LUTDONE                 0x00080000      /* Look-up table generation done */
+#define FSTAT                   0x00700000      /* FIFO status */
+#define MAX_FIFO                4               /* Max fifo size */
+/* CRC_CONTROL Masks */
+#define BLKEN                   0x00000001      /* Block enable */
+#define OPMODE                  0x000000F0      /* Operation mode */
+#define OPMODE_OFFSET           4               /* Operation mode mask offset*/
+#define MODE_DMACPY_CRC         1               /* MTM CRC compute and compare */
+#define MODE_DATA_FILL          2               /* MTM data fill */
+#define MODE_CALC_CRC           3               /* MSM CRC compute and compare */
+#define MODE_DATA_VERIFY        4               /* MSM data verify */
+#define AUTOCLRZ                0x00000100      /* Auto clear to zero */
+#define AUTOCLRF                0x00000200      /* Auto clear to one */
+#define OBRSTALL                0x00001000      /* Stall on output buffer ready */
+#define IRRSTALL                0x00002000      /* Stall on immediate result ready */
+#define BITMIRR                 0x00010000      /* Mirror bits within each byte of 32-bit input data */
+#define BITMIRR_OFFSET          16              /* Mirror bits offset */
+#define BYTMIRR                 0x00020000      /* Mirror bytes of 32-bit input data */
+#define BYTMIRR_OFFSET          17              /* Mirror bytes offset */
+#define W16SWP                  0x00040000      /* Mirror uppper and lower 16-bit word of 32-bit input data */
+#define W16SWP_OFFSET           18              /* Mirror 16-bit word offset */
+#define FDSEL                   0x00080000      /* FIFO is written after input data is mirrored */
+#define FDSEL_OFFSET            19              /* Mirror FIFO offset */
+#define RSLTMIRR                0x00100000      /* CRC result registers are mirrored. */
+#define RSLTMIRR_OFFSET         20              /* Mirror CRC result offset. */
+#define POLYMIRR                0x00200000      /* CRC poly register is mirrored. */
+#define POLYMIRR_OFFSET         21              /* Mirror CRC poly offset. */
+#define CMPMIRR                 0x00400000      /* CRC compare register is mirrored. */
+#define CMPMIRR_OFFSET          22              /* Mirror CRC compare offset. */
+/* CRC_INTREN Masks */
+#define CMPERRI                 0x02            /* CRC_ERROR_INTR */
+#define DCNTEXPI                0x10            /* CRC_STATUS_INTR */
+#endif
+#endif
diff --git a/arch/blackfin/include/asm/bfin_dma.h b/arch/blackfin/include/asm/bfin_dma.h
index d51120744148..6319f4e49083 100644
--- a/arch/blackfin/include/asm/bfin_dma.h
+++ b/arch/blackfin/include/asm/bfin_dma.h
@@ -15,12 +15,55 @@
 #define DMAEN                   0x0001  /* DMA Channel Enable */
 #define WNR                             0x0002  /* Channel Direction (W/R*) */
 #define WDSIZE_8                0x0000  /* Transfer Word Size = 8 */
+#define PSIZE_8                 0x00000000      /* Transfer Word Size = 16 */
+#ifdef CONFIG_BF60x
+#define PSIZE_16                0x00000010      /* Transfer Word Size = 16 */
+#define PSIZE_32                0x00000020      /* Transfer Word Size = 32 */
+#define PSIZE_64                0x00000030      /* Transfer Word Size = 32 */
+#define WDSIZE_16               0x00000100      /* Transfer Word Size = 16 */
+#define WDSIZE_32               0x00000200      /* Transfer Word Size = 32 */
+#define WDSIZE_64               0x00000300      /* Transfer Word Size = 32 */
+#define WDSIZE_128              0x00000400      /* Transfer Word Size = 32 */
+#define WDSIZE_256              0x00000500      /* Transfer Word Size = 32 */
+#define DMA2D                   0x04000000      /* DMA Mode (2D/1D*) */
+#define RESTART                 0x00000004      /* DMA Buffer Clear SYNC */
+#define DI_EN_X                 0x00100000      /* Data Interrupt Enable in X count */
+#define DI_EN_Y                 0x00200000      /* Data Interrupt Enable in Y count */
+#define DI_EN_P                 0x00300000      /* Data Interrupt Enable in Peripheral */
+#define DI_EN                   DI_EN_X         /* Data Interrupt Enable */
+#define NDSIZE_0                0x00000000      /* Next Descriptor Size = 1 */
+#define NDSIZE_1                0x00010000      /* Next Descriptor Size = 2 */
+#define NDSIZE_2                0x00020000      /* Next Descriptor Size = 3 */
+#define NDSIZE_3                0x00030000      /* Next Descriptor Size = 4 */
+#define NDSIZE_4                0x00040000      /* Next Descriptor Size = 5 */
+#define NDSIZE_5                0x00050000      /* Next Descriptor Size = 6 */
+#define NDSIZE_6                0x00060000      /* Next Descriptor Size = 7 */
+#define NDSIZE                  0x00070000      /* Next Descriptor Size */
+#define NDSIZE_OFFSET           16              /* Next Descriptor Size Offset */
+#define DMAFLOW_LIST            0x00004000      /* Descriptor List Mode */
+#define DMAFLOW_LARGE           DMAFLOW_LIST
+#define DMAFLOW_ARRAY           0x00005000      /* Descriptor Array Mode */
+#define DMAFLOW_LIST_DEMAND     0x00006000      /* Descriptor Demand List Mode */
+#define DMAFLOW_ARRAY_DEMAND    0x00007000      /* Descriptor Demand Array Mode */
+#define DMA_RUN_DFETCH          0x00000100      /* DMA Channel Running Indicator (DFETCH) */
+#define DMA_RUN                 0x00000200      /* DMA Channel Running Indicator */
+#define DMA_RUN_WAIT_TRIG       0x00000300      /* DMA Channel Running Indicator (WAIT TRIG) */
+#define DMA_RUN_WAIT_ACK        0x00000400      /* DMA Channel Running Indicator (WAIT ACK) */
+#else
+#define PSIZE_16                0x0000  /* Transfer Word Size = 16 */
+#define PSIZE_32                0x0000  /* Transfer Word Size = 32 */
 #define WDSIZE_16               0x0004  /* Transfer Word Size = 16 */
 #define WDSIZE_32               0x0008  /* Transfer Word Size = 32 */
 #define DMA2D                   0x0010  /* DMA Mode (2D/1D*) */
 #define RESTART                 0x0020  /* DMA Buffer Clear */
 #define DI_SEL                  0x0040  /* Data Interrupt Timing Select */
 #define DI_EN                   0x0080  /* Data Interrupt Enable */
+#define DI_EN_X                 0x00C0  /* Data Interrupt Enable in X count*/
+#define DI_EN_Y                 0x0080  /* Data Interrupt Enable in Y count*/
 #define NDSIZE_0                0x0000  /* Next Descriptor Size = 0 (Stop/Autobuffer) */
 #define NDSIZE_1                0x0100  /* Next Descriptor Size = 1 */
 #define NDSIZE_2                0x0200  /* Next Descriptor Size = 2 */
@@ -32,18 +75,26 @@
 #define NDSIZE_8                0x0800  /* Next Descriptor Size = 8 */
 #define NDSIZE_9                0x0900  /* Next Descriptor Size = 9 */
 #define NDSIZE                  0x0f00  /* Next Descriptor Size */
-#define DMAFLOW                 0x7000  /* Flow Control */
+#define NDSIZE_OFFSET           8       /* Next Descriptor Size Offset */
-#define DMAFLOW_STOP    0x0000  /* Stop Mode */
-#define DMAFLOW_AUTO    0x1000  /* Autobuffer Mode */
 #define DMAFLOW_ARRAY   0x4000  /* Descriptor Array Mode */
 #define DMAFLOW_SMALL   0x6000  /* Small Model Descriptor List Mode */
 #define DMAFLOW_LARGE   0x7000  /* Large Model Descriptor List Mode */
+#define DFETCH                  0x0004  /* DMA Descriptor Fetch Indicator */
+#define DMA_RUN                 0x0008  /* DMA Channel Running Indicator */
+#endif
+#define DMAFLOW                 0x7000  /* Flow Control */
+#define DMAFLOW_STOP    0x0000  /* Stop Mode */
+#define DMAFLOW_AUTO    0x1000  /* Autobuffer Mode */
 /* DMA_IRQ_STATUS Masks */
 #define DMA_DONE                0x0001  /* DMA Completion Interrupt Status */
 #define DMA_ERR                 0x0002  /* DMA Error Interrupt Status */
-#define DFETCH                  0x0004  /* DMA Descriptor Fetch Indicator */
+#ifdef CONFIG_BF60x
-#define DMA_RUN                 0x0008  /* DMA Channel Running Indicator */
+#define DMA_PIRQ                0x0004  /* DMA Peripheral Error Interrupt Status */
+#else
+#define DMA_PIRQ                0
+#endif
 /*
 * All Blackfin system MMRs are padded to 32bits even if the register
@@ -57,6 +108,26 @@
 struct bfin_dma_regs {
        u32 next_desc_ptr;
        u32 start_addr;
+#ifdef CONFIG_BF60x
+        u32 cfg;
+        u32 x_count;
+        u32 x_modify;
+        u32 y_count;
+        u32 y_modify;
+        u32 pad1;
+        u32 pad2;
+        u32 curr_desc_ptr;
+        u32 prev_desc_ptr;
+        u32 curr_addr;
+        u32 irq_status;
+        u32 curr_x_count;
+        u32 curr_y_count;
+        u32 pad3;
+        u32 bw_limit_count;
+        u32 curr_bw_limit_count;
+        u32 bw_monitor_count;
+        u32 curr_bw_monitor_count;
+#else
        __BFP(config);
        u32 __pad0;
        __BFP(x_count);
@@ -71,8 +142,10 @@ struct bfin_dma_regs {
        u32 __pad1;
        __BFP(curr_y_count);
        u32 __pad2;
+#endif
 };
+#ifndef CONFIG_BF60x
 /*
 * bfin handshake mdma registers layout
 */
@@ -85,6 +158,7 @@ struct bfin_hmdma_regs {
        __BFP(ecount);
        __BFP(bcount);
 };
+#endif
 #undef __BFP
diff --git a/arch/blackfin/include/asm/bfin_pfmon.h b/arch/blackfin/include/asm/bfin_pfmon.h
index accd47e2db40..bf52e1f32257 100644
--- a/arch/blackfin/include/asm/bfin_pfmon.h
+++ b/arch/blackfin/include/asm/bfin_pfmon.h
@@ -3,7 +3,7 @@
 *
 * Copyright 2005-2011 Analog Devices Inc.
 *
- * Licensed under the ADI BSD license or GPL-2 (or later).
+ * Licensed under the Clear BSD license or GPL-2 (or later).
 */
 #ifndef __ASM_BFIN_PFMON_H__
diff --git a/arch/blackfin/include/asm/bfin_ppi.h b/arch/blackfin/include/asm/bfin_ppi.h
index 3be05faa2c65..a4e872e16e75 100644
--- a/arch/blackfin/include/asm/bfin_ppi.h
+++ b/arch/blackfin/include/asm/bfin_ppi.h
@@ -10,6 +10,7 @@
 #define __ASM_BFIN_PPI_H__
 #include <linux/types.h>
+#include <asm/blackfin.h>
 /*
 * All Blackfin system MMRs are padded to 32bits even if the register
@@ -48,6 +49,133 @@ struct bfin_eppi_regs {
        u32 clip;
 };
+/*
+ * bfin eppi3 registers layout
+ */
+struct bfin_eppi3_regs {
+        u32 stat;
+        u32 hcnt;
+        u32 hdly;
+        u32 vcnt;
+        u32 vdly;
+        u32 frame;
+        u32 line;
+        u32 clkdiv;
+        u32 ctl;
+        u32 fs1_wlhb;
+        u32 fs1_paspl;
+        u32 fs2_wlvb;
+        u32 fs2_palpf;
+        u32 imsk;
+        u32 oddclip;
+        u32 evenclip;
+        u32 fs1_dly;
+        u32 fs2_dly;
+        u32 ctl2;
+};
 #undef __BFP
+#ifdef EPPI0_CTL2
+#define EPPI_STAT_CFIFOERR              0x00000001    /* Chroma FIFO Error */
+#define EPPI_STAT_YFIFOERR              0x00000002    /* Luma FIFO Error */
+#define EPPI_STAT_LTERROVR              0x00000004    /* Line Track Overflow */
+#define EPPI_STAT_LTERRUNDR             0x00000008    /* Line Track Underflow */
+#define EPPI_STAT_FTERROVR              0x00000010    /* Frame Track Overflow */
+#define EPPI_STAT_FTERRUNDR             0x00000020    /* Frame Track Underflow */
+#define EPPI_STAT_ERRNCOR               0x00000040    /* Preamble Error Not Corrected */
+#define EPPI_STAT_PXPERR                0x00000080    /* PxP Ready Error */
+#define EPPI_STAT_ERRDET                0x00004000    /* Preamble Error Detected */
+#define EPPI_STAT_FLD                   0x00008000    /* Current Field Received by EPPI */
+#define EPPI_HCNT_VALUE                 0x0000FFFF    /* Holds the number of samples to read in or write out per line, after PPIx_HDLY number of cycles have expired since the last assertion of PPIx_FS1 */
+#define EPPI_HDLY_VALUE                 0x0000FFFF    /* Number of PPIx_CLK cycles to delay after assertion of PPIx_FS1 before starting to read or write data */
+#define EPPI_VCNT_VALUE                 0x0000FFFF    /* Holds the number of lines to read in or write out, after PPIx_VDLY number of lines from the start of frame */
+#define EPPI_VDLY_VALUE                 0x0000FFFF    /* Number of lines to wait after the start of a new frame before starting to read/transmit data */
+#define EPPI_FRAME_VALUE                0x0000FFFF    /* Holds the number of lines expected per frame of data */
+#define EPPI_LINE_VALUE                 0x0000FFFF    /* Holds the number of samples expected per line */
+#define EPPI_CLKDIV_VALUE               0x0000FFFF    /* Internal clock divider */
+#define EPPI_CTL_EN                     0x00000001    /* PPI Enable */
+#define EPPI_CTL_DIR                    0x00000002    /* PPI Direction */
+#define EPPI_CTL_XFRTYPE                0x0000000C    /* PPI Operating Mode */
+#define EPPI_CTL_ACTIVE656              0x00000000    /* XFRTYPE: ITU656 Active Video Only Mode */
+#define EPPI_CTL_ENTIRE656              0x00000004    /* XFRTYPE: ITU656 Entire Field Mode */
+#define EPPI_CTL_VERT656                0x00000008    /* XFRTYPE: ITU656 Vertical Blanking Only Mode */
+#define EPPI_CTL_NON656                 0x0000000C    /* XFRTYPE: Non-ITU656 Mode (GP Mode) */
+#define EPPI_CTL_FSCFG                  0x00000030    /* Frame Sync Configuration */
+#define EPPI_CTL_SYNC0                  0x00000000    /* FSCFG: Sync Mode 0 */
+#define EPPI_CTL_SYNC1                  0x00000010    /* FSCFG: Sync Mode 1 */
+#define EPPI_CTL_SYNC2                  0x00000020    /* FSCFG: Sync Mode 2 */
+#define EPPI_CTL_SYNC3                  0x00000030    /* FSCFG: Sync Mode 3 */
+#define EPPI_CTL_FLDSEL                 0x00000040    /* Field Select/Trigger */
+#define EPPI_CTL_ITUTYPE                0x00000080    /* ITU Interlace or Progressive */
+#define EPPI_CTL_BLANKGEN               0x00000100    /* ITU Output Mode with Internal Blanking Generation */
+#define EPPI_CTL_ICLKGEN                0x00000200    /* Internal Clock Generation */
+#define EPPI_CTL_IFSGEN                 0x00000400    /* Internal Frame Sync Generation */
+#define EPPI_CTL_SIGNEXT                0x00000800    /* Sign Extension */
+#define EPPI_CTL_POLC                   0x00003000    /* Frame Sync and Data Driving and Sampling Edges */
+#define EPPI_CTL_POLC0                  0x00000000    /* POLC: Clock/Sync polarity mode 0 */
+#define EPPI_CTL_POLC1                  0x00001000    /* POLC: Clock/Sync polarity mode 1 */
+#define EPPI_CTL_POLC2                  0x00002000    /* POLC: Clock/Sync polarity mode 2 */
+#define EPPI_CTL_POLC3                  0x00003000    /* POLC: Clock/Sync polarity mode 3 */
+#define EPPI_CTL_POLS                   0x0000C000    /* Frame Sync Polarity */
+#define EPPI_CTL_FS1HI_FS2HI            0x00000000    /* POLS: FS1 and FS2 are active high */
+#define EPPI_CTL_FS1LO_FS2HI            0x00004000    /* POLS: FS1 is active low. FS2 is active high */
+#define EPPI_CTL_FS1HI_FS2LO            0x00008000    /* POLS: FS1 is active high. FS2 is active low */
+#define EPPI_CTL_FS1LO_FS2LO            0x0000C000    /* POLS: FS1 and FS2 are active low */
+#define EPPI_CTL_DLEN                   0x00070000    /* Data Length */
+#define EPPI_CTL_DLEN08                 0x00000000    /* DLEN: 8 bits */
+#define EPPI_CTL_DLEN10                 0x00010000    /* DLEN: 10 bits */
+#define EPPI_CTL_DLEN12                 0x00020000    /* DLEN: 12 bits */
+#define EPPI_CTL_DLEN14                 0x00030000    /* DLEN: 14 bits */
+#define EPPI_CTL_DLEN16                 0x00040000    /* DLEN: 16 bits */
+#define EPPI_CTL_DLEN18                 0x00050000    /* DLEN: 18 bits */
+#define EPPI_CTL_DLEN20                 0x00060000    /* DLEN: 20 bits */
+#define EPPI_CTL_DLEN24                 0x00070000    /* DLEN: 24 bits */
+#define EPPI_CTL_DMIRR                  0x00080000    /* Data Mirroring */
+#define EPPI_CTL_SKIPEN                 0x00100000    /* Skip Enable */
+#define EPPI_CTL_SKIPEO                 0x00200000    /* Skip Even or Odd */
+#define EPPI_CTL_PACKEN                 0x00400000    /* Pack/Unpack Enable */
+#define EPPI_CTL_SWAPEN                 0x00800000    /* Swap Enable */
+#define EPPI_CTL_SPLTEO                 0x01000000    /* Split Even and Odd Data Samples */
+#define EPPI_CTL_SUBSPLTODD             0x02000000    /* Sub-Split Odd Samples */
+#define EPPI_CTL_SPLTWRD                0x04000000    /* Split Word */
+#define EPPI_CTL_RGBFMTEN               0x08000000    /* RGB Formatting Enable */
+#define EPPI_CTL_DMACFG                 0x10000000    /* One or Two DMA Channels Mode */
+#define EPPI_CTL_DMAFINEN               0x20000000    /* DMA Finish Enable */
+#define EPPI_CTL_MUXSEL                 0x40000000    /* MUX Select */
+#define EPPI_CTL_CLKGATEN               0x80000000    /* Clock Gating Enable */
+#define EPPI_FS2_WLVB_F2VBAD            0xFF000000    /* In GP transmit mode with BLANKGEN = 1, contains number of lines of vertical blanking after field 2 */
+#define EPPI_FS2_WLVB_F2VBBD            0x00FF0000    /* In GP transmit mode with BLANKGEN = 1, contains number of lines of vertical blanking before field 2 */
+#define EPPI_FS2_WLVB_F1VBAD            0x0000FF00    /* In GP transmit mode with, BLANKGEN = 1, contains number of lines of vertical blanking after field 1 */
+#define EPPI_FS2_WLVB_F1VBBD            0x000000FF    /* In GP 2, or 3 FS modes used to generate PPIx_FS2 width (32-bit). In GP Transmit mode, with BLANKGEN=1, contains the number of lines of Vertical blanking before field 1. */
+#define EPPI_FS2_PALPF_F2ACT            0xFFFF0000    /* Number of lines of Active Data in Field 2 */
+#define EPPI_FS2_PALPF_F1ACT            0x0000FFFF    /* Number of lines of Active Data in Field 1 */
+#define EPPI_IMSK_CFIFOERR              0x00000001    /* Mask CFIFO Underflow or Overflow Error Interrupt */
+#define EPPI_IMSK_YFIFOERR              0x00000002    /* Mask YFIFO Underflow or Overflow Error Interrupt */
+#define EPPI_IMSK_LTERROVR              0x00000004    /* Mask Line Track Overflow Error Interrupt */
+#define EPPI_IMSK_LTERRUNDR             0x00000008    /* Mask Line Track Underflow Error Interrupt */
+#define EPPI_IMSK_FTERROVR              0x00000010    /* Mask Frame Track Overflow Error Interrupt */
+#define EPPI_IMSK_FTERRUNDR             0x00000020    /* Mask Frame Track Underflow Error Interrupt */
+#define EPPI_IMSK_ERRNCOR               0x00000040    /* Mask ITU Preamble Error Not Corrected Interrupt */
+#define EPPI_IMSK_PXPERR                0x00000080    /* Mask PxP Ready Error Interrupt */
+#define EPPI_ODDCLIP_HIGHODD            0xFFFF0000
+#define EPPI_ODDCLIP_LOWODD             0x0000FFFF
+#define EPPI_EVENCLIP_HIGHEVEN          0xFFFF0000
+#define EPPI_EVENCLIP_LOWEVEN           0x0000FFFF
+#define EPPI_CTL2_FS1FINEN              0x00000002    /* HSYNC Finish Enable */
+#endif
 #endif
diff --git a/arch/blackfin/include/asm/bfin_rotary.h b/arch/blackfin/include/asm/bfin_rotary.h
index 0b6910bdc57f..8895a750c70c 100644
--- a/arch/blackfin/include/asm/bfin_rotary.h
+++ b/arch/blackfin/include/asm/bfin_rotary.h
@@ -39,6 +39,7 @@ struct bfin_rotary_platform_data {
        unsigned int rotary_rel_code;
        unsigned short debounce;        /* 0..17 */
        unsigned short mode;
+        unsigned short pm_wakeup;
 };
 /* CNT_CONFIG bitmasks */
diff --git a/arch/blackfin/include/asm/bfin_serial.h b/arch/blackfin/include/asm/bfin_serial.h
index 68bcc3d119b6..8597158010b5 100644
--- a/arch/blackfin/include/asm/bfin_serial.h
+++ b/arch/blackfin/include/asm/bfin_serial.h
@@ -18,7 +18,7 @@
    defined(CONFIG_BFIN_UART1_CTSRTS) || \
    defined(CONFIG_BFIN_UART2_CTSRTS) || \
    defined(CONFIG_BFIN_UART3_CTSRTS)
-# ifdef BFIN_UART_BF54X_STYLE
+# if defined(BFIN_UART_BF54X_STYLE) || defined(BFIN_UART_BF60X_STYLE)
 #  define CONFIG_SERIAL_BFIN_HARD_CTSRTS
 # else
 #  define CONFIG_SERIAL_BFIN_CTSRTS
@@ -58,14 +58,69 @@ struct bfin_serial_port {
 #endif
 };
+#ifdef BFIN_UART_BF60X_STYLE
+/* UART_CTL Masks */
+#define UCEN                     0x1  /* Enable UARTx Clocks */
+#define LOOP_ENA                 0x2  /* Loopback Mode Enable */
+#define UMOD_MDB                 0x10  /* Enable MDB Mode */
+#define UMOD_IRDA                0x20  /* Enable IrDA Mode */
+#define UMOD_MASK                0x30  /* Uart Mode Mask */
+#define WLS(x)                   (((x-5) & 0x03) << 8)  /* Word Length Select */
+#define WLS_MASK                 0x300  /* Word length Select Mask */
+#define WLS_OFFSET               8      /* Word length Select Offset */
+#define STB                      0x1000  /* Stop Bits */
+#define STBH                     0x2000  /* Half Stop Bits */
+#define PEN                      0x4000  /* Parity Enable */
+#define EPS                      0x8000  /* Even Parity Select */
+#define STP                      0x10000  /* Stick Parity */
+#define FPE                      0x20000  /* Force Parity Error On Transmit */
+#define FFE                      0x40000  /* Force Framing Error On Transmit */
+#define SB                       0x80000  /* Set Break */
+#define LCR_MASK                 (SB | STP | EPS | PEN | STB | WLS_MASK)
+#define FCPOL                    0x400000  /* Flow Control Pin Polarity */
+#define RPOLC                    0x800000  /* IrDA RX Polarity Change */
+#define TPOLC                    0x1000000  /* IrDA TX Polarity Change */
+#define MRTS                     0x2000000  /* Manual Request To Send */
+#define XOFF                     0x4000000  /* Transmitter Off */
+#define ARTS                     0x8000000  /* Automatic Request To Send */
+#define ACTS                     0x10000000  /* Automatic Clear To Send */
+#define RFIT                     0x20000000  /* Receive FIFO IRQ Threshold */
+#define RFRT                     0x40000000  /* Receive FIFO RTS Threshold */
+/* UART_STAT Masks */
+#define DR                       0x01  /* Data Ready */
+#define OE                       0x02  /* Overrun Error */
+#define PE                       0x04  /* Parity Error */
+#define FE                       0x08  /* Framing Error */
+#define BI                       0x10  /* Break Interrupt */
+#define THRE                     0x20  /* THR Empty */
+#define TEMT                     0x80  /* TSR and UART_THR Empty */
+#define TFI                      0x100  /* Transmission Finished Indicator */
+#define ASTKY                    0x200  /* Address Sticky */
+#define ADDR                     0x400  /* Address bit status */
+#define RO                       0x800  /* Reception Ongoing */
+#define SCTS                     0x1000  /* Sticky CTS */
+#define CTS                      0x10000  /* Clear To Send */
+#define RFCS                     0x20000  /* Receive FIFO Count Status */
+/* UART_CLOCK Masks */
+#define EDBO                     0x80000000 /* Enable Devide by One */
+#else /* BFIN_UART_BF60X_STYLE */
 /* UART_LCR Masks */
 #define WLS(x)                   (((x)-5) & 0x03)  /* Word Length Select */
+#define WLS_MASK                 0x03  /* Word length Select Mask */
+#define WLS_OFFSET               0     /* Word length Select Offset */
 #define STB                      0x04  /* Stop Bits */
 #define PEN                      0x08  /* Parity Enable */
 #define EPS                      0x10  /* Even Parity Select */
 #define STP                      0x20  /* Stick Parity */
 #define SB                       0x40  /* Set Break */
 #define DLAB                     0x80  /* Divisor Latch Access */
+#define LCR_MASK                 (SB | STP | EPS | PEN | STB | WLS_MASK)
 /* UART_LSR Masks */
 #define DR                       0x01  /* Data Ready */
@@ -77,15 +132,6 @@ struct bfin_serial_port {
 #define TEMT                     0x40  /* TSR and UART_THR Empty */
 #define TFI                      0x80  /* Transmission Finished Indicator */
-/* UART_IER Masks */
-#define ERBFI                    0x01  /* Enable Receive Buffer Full Interrupt */
-#define ETBEI                    0x02  /* Enable Transmit Buffer Empty Interrupt */
-#define ELSI                     0x04  /* Enable RX Status Interrupt */
-#define EDSSI                    0x08  /* Enable Modem Status Interrupt */
-#define EDTPTI                   0x10  /* Enable DMA Transmit PIRQ Interrupt */
-#define ETFI                     0x20  /* Enable Transmission Finished Interrupt */
-#define ERFCI                    0x40  /* Enable Receive FIFO Count Interrupt */
 /* UART_MCR Masks */
 #define XOFF                     0x01  /* Transmitter Off */
 #define MRTS                     0x02  /* Manual Request To Send */
@@ -103,13 +149,36 @@ struct bfin_serial_port {
 /* UART_GCTL Masks */
 #define UCEN                     0x01  /* Enable UARTx Clocks */
-#define IREN                     0x02  /* Enable IrDA Mode */
+#define UMOD_IRDA                0x02  /* Enable IrDA Mode */
+#define UMOD_MASK                0x02  /* Uart Mode Mask */
 #define TPOLC                    0x04  /* IrDA TX Polarity Change */
 #define RPOLC                    0x08  /* IrDA RX Polarity Change */
 #define FPE                      0x10  /* Force Parity Error On Transmit */
 #define FFE                      0x20  /* Force Framing Error On Transmit */
-#ifdef BFIN_UART_BF54X_STYLE
+#endif /* BFIN_UART_BF60X_STYLE */
+/* UART_IER Masks */
+#define ERBFI                    0x01  /* Enable Receive Buffer Full Interrupt */
+#define ETBEI                    0x02  /* Enable Transmit Buffer Empty Interrupt */
+#define ELSI                     0x04  /* Enable RX Status Interrupt */
+#define EDSSI                    0x08  /* Enable Modem Status Interrupt */
+#define EDTPTI                   0x10  /* Enable DMA Transmit PIRQ Interrupt */
+#define ETFI                     0x20  /* Enable Transmission Finished Interrupt */
+#define ERFCI                    0x40  /* Enable Receive FIFO Count Interrupt */
+#if defined(BFIN_UART_BF60X_STYLE)
+# define OFFSET_REDIV            0x00  /* Version ID Register             */
+# define OFFSET_CTL              0x04  /* Control Register                */
+# define OFFSET_STAT             0x08  /* Status Register                 */
+# define OFFSET_SCR              0x0C  /* SCR Scratch Register            */
+# define OFFSET_CLK              0x10  /* Clock Rate Register             */
+# define OFFSET_IER              0x14  /* Interrupt Enable Register       */
+# define OFFSET_IER_SET          0x18  /* Set Interrupt Enable Register   */
+# define OFFSET_IER_CLEAR        0x1C  /* Clear Interrupt Enable Register */
+# define OFFSET_RBR              0x20  /* Receive Buffer register         */
+# define OFFSET_THR              0x24  /* Transmit Holding register       */
+#elif defined(BFIN_UART_BF54X_STYLE)
 # define OFFSET_DLL              0x00  /* Divisor Latch (Low-Byte)        */
 # define OFFSET_DLH              0x04  /* Divisor Latch (High-Byte)       */
 # define OFFSET_GCTL             0x08  /* Global Control Register         */
@@ -145,7 +214,23 @@ struct bfin_serial_port {
 */
 #define __BFP(m) u16 m; u16 __pad_##m
 struct bfin_uart_regs {
-#ifdef BFIN_UART_BF54X_STYLE
+#if defined(BFIN_UART_BF60X_STYLE)
+        u32 revid;
+        u32 ctl;
+        u32 stat;
+        u32 scr;
+        u32 clk;
+        u32 ier;
+        u32 ier_set;
+        u32 ier_clear;
+        u32 rbr;
+        u32 thr;
+        u32 taip;
+        u32 tsr;
+        u32 rsr;
+        u32 txdiv;
+        u32 rxdiv;
+#elif defined(BFIN_UART_BF54X_STYLE)
        __BFP(dll);
        __BFP(dlh);
        __BFP(gctl);
@@ -182,13 +267,70 @@ struct bfin_uart_regs {
 };
 #undef __BFP
+#define port_membase(uart)     (((struct bfin_serial_port *)(uart))->port.membase)
+/*
 #ifndef port_membase
 # define port_membase(p) 0
 #endif
+*/
+#ifdef BFIN_UART_BF60X_STYLE
+#define UART_GET_CHAR(p)      bfin_read32(port_membase(p) + OFFSET_RBR)
+#define UART_GET_CLK(p)       bfin_read32(port_membase(p) + OFFSET_CLK)
+#define UART_GET_CTL(p)       bfin_read32(port_membase(p) + OFFSET_CTL)
+#define UART_GET_GCTL(p)      UART_GET_CTL(p)
+#define UART_GET_LCR(p)       UART_GET_CTL(p)
+#define UART_GET_MCR(p)       UART_GET_CTL(p)
+#if ANOMALY_05001001
+#define UART_GET_STAT(p) \
+({ \
+        u32 __ret; \
+        unsigned long flags; \
+        flags = hard_local_irq_save(); \
+        __ret = bfin_read32(port_membase(p) + OFFSET_STAT); \
+        hard_local_irq_restore(flags); \
+        __ret; \
+})
+#else
+#define UART_GET_STAT(p)      bfin_read32(port_membase(p) + OFFSET_STAT)
+#endif
+#define UART_GET_MSR(p)       UART_GET_STAT(p)
+#define UART_PUT_CHAR(p, v)   bfin_write32(port_membase(p) + OFFSET_THR, v)
+#define UART_PUT_CLK(p, v)    bfin_write32(port_membase(p) + OFFSET_CLK, v)
+#define UART_PUT_CTL(p, v)    bfin_write32(port_membase(p) + OFFSET_CTL, v)
+#define UART_PUT_GCTL(p, v)   UART_PUT_CTL(p, v)
+#define UART_PUT_LCR(p, v)    UART_PUT_CTL(p, v)
+#define UART_PUT_MCR(p, v)    UART_PUT_CTL(p, v)
+#define UART_PUT_STAT(p, v)   bfin_write32(port_membase(p) + OFFSET_STAT, v)
+#define UART_CLEAR_IER(p, v)  bfin_write32(port_membase(p) + OFFSET_IER_CLEAR, v)
+#define UART_GET_IER(p)       bfin_read32(port_membase(p) + OFFSET_IER)
+#define UART_SET_IER(p, v)    bfin_write32(port_membase(p) + OFFSET_IER_SET, v)
+#define UART_CLEAR_DLAB(p)    /* MMRs not muxed on BF60x */
+#define UART_SET_DLAB(p)      /* MMRs not muxed on BF60x */
+#define UART_CLEAR_LSR(p)     UART_PUT_STAT(p, -1)
+#define UART_GET_LSR(p)       UART_GET_STAT(p)
+#define UART_PUT_LSR(p, v)    UART_PUT_STAT(p, v)
+/* This handles hard CTS/RTS */
+#define BFIN_UART_CTSRTS_HARD
+#define UART_CLEAR_SCTS(p)      UART_PUT_STAT(p, SCTS)
+#define UART_GET_CTS(x)         (UART_GET_MSR(x) & CTS)
+#define UART_DISABLE_RTS(x)     UART_PUT_MCR(x, UART_GET_MCR(x) & ~(ARTS | MRTS))
+#define UART_ENABLE_RTS(x)      UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS | ARTS)
+#define UART_ENABLE_INTS(x, v)  UART_SET_IER(x, v)
+#define UART_DISABLE_INTS(x)    UART_CLEAR_IER(x, 0xF)
+#else /* BFIN_UART_BF60X_STYLE */
 #define UART_GET_CHAR(p)      bfin_read16(port_membase(p) + OFFSET_RBR)
 #define UART_GET_DLL(p)       bfin_read16(port_membase(p) + OFFSET_DLL)
 #define UART_GET_DLH(p)       bfin_read16(port_membase(p) + OFFSET_DLH)
+#define UART_GET_CLK(p)       ((UART_GET_DLH(p) << 8) | UART_GET_DLL(p))
 #define UART_GET_GCTL(p)      bfin_read16(port_membase(p) + OFFSET_GCTL)
 #define UART_GET_LCR(p)       bfin_read16(port_membase(p) + OFFSET_LCR)
 #define UART_GET_MCR(p)       bfin_read16(port_membase(p) + OFFSET_MCR)
@@ -197,6 +339,11 @@ struct bfin_uart_regs {
 #define UART_PUT_CHAR(p, v)   bfin_write16(port_membase(p) + OFFSET_THR, v)
 #define UART_PUT_DLL(p, v)    bfin_write16(port_membase(p) + OFFSET_DLL, v)
 #define UART_PUT_DLH(p, v)    bfin_write16(port_membase(p) + OFFSET_DLH, v)
+#define UART_PUT_CLK(p, v) do \
+{\
+UART_PUT_DLL(p, v & 0xFF); \
+UART_PUT_DLH(p, (v >> 8) & 0xFF); } while (0);
 #define UART_PUT_GCTL(p, v)   bfin_write16(port_membase(p) + OFFSET_GCTL, v)
 #define UART_PUT_LCR(p, v)    bfin_write16(port_membase(p) + OFFSET_LCR, v)
 #define UART_PUT_MCR(p, v)    bfin_write16(port_membase(p) + OFFSET_MCR, v)
@@ -233,12 +380,17 @@ struct bfin_uart_regs {
 #define UART_CLEAR_DLAB(p)    do { UART_PUT_LCR(p, UART_GET_LCR(p) & ~DLAB); SSYNC(); } while (0)
 #define UART_SET_DLAB(p)      do { UART_PUT_LCR(p, UART_GET_LCR(p) | DLAB); SSYNC(); } while (0)
+#define get_lsr_cache(uart)    (((struct bfin_serial_port *)(uart))->lsr)
+#define put_lsr_cache(uart, v) (((struct bfin_serial_port *)(uart))->lsr = (v))
+/*
 #ifndef put_lsr_cache
 # define put_lsr_cache(p, v)
 #endif
 #ifndef get_lsr_cache
 # define get_lsr_cache(p) 0
 #endif
+*/
 /* The hardware clears the LSR bits upon read, so we need to cache
 * some of the more fun bits in software so they don't get lost
@@ -267,7 +419,9 @@ static inline void UART_PUT_LSR(void *p, uint16_t val)
 #define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
 #define UART_DISABLE_INTS(x)   UART_PUT_IER(x, 0)
-#endif
+#endif /* BFIN_UART_BF54X_STYLE */
+#endif /* BFIN_UART_BF60X_STYLE */
 #ifndef BFIN_UART_TX_FIFO_SIZE
 # define BFIN_UART_TX_FIFO_SIZE 2
diff --git a/arch/blackfin/include/asm/bfin_sport.h b/arch/blackfin/include/asm/bfin_sport.h
index 0afcfbd54a82..f8907ea6b5b6 100644
--- a/arch/blackfin/include/asm/bfin_sport.h
+++ b/arch/blackfin/include/asm/bfin_sport.h
@@ -24,6 +24,7 @@
 struct sport_config {
        /* TDM (multichannels), I2S or other mode */
        unsigned int mode:3;
+        unsigned int polled;    /* use poll instead of irq when set */
        /* if TDM mode is selected, channels must be set */
        int channels;   /* Must be in 8 units */
diff --git a/arch/blackfin/include/asm/bfin_sport3.h b/arch/blackfin/include/asm/bfin_sport3.h
new file mode 100644
index 000000000000..03c00220d69b
--- /dev/null
+++ b/arch/blackfin/include/asm/bfin_sport3.h
@@ -0,0 +1,107 @@
+/*
+ * bfin_sport - Analog Devices BF6XX SPORT registers
+ *
+ * Copyright (c) 2012 Analog Devices Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#ifndef _BFIN_SPORT3_H_
+#define _BFIN_SPORT3_H_
+#include <linux/types.h>
+#define SPORT_CTL_SPENPRI             0x00000001    /* Enable Primary Channel */
+#define SPORT_CTL_DTYPE               0x00000006    /* Data type select */
+#define SPORT_CTL_RJUSTIFY_ZFILL      0x00000000    /* DTYPE: MCM mode: Right-justify, zero-fill unused MSBs */
+#define SPORT_CTL_RJUSTIFY_SFILL      0x00000002    /* DTYPE: MCM mode: Right-justify, sign-extend unused MSBs */
+#define SPORT_CTL_USE_U_LAW           0x00000004    /* DTYPE: MCM mode: Compand using u-law */
+#define SPORT_CTL_USE_A_LAW           0x00000006    /* DTYPE: MCM mode: Compand using A-law */
+#define SPORT_CTL_LSBF                0x00000008    /* Serial bit endian select */
+#define SPORT_CTL_SLEN                0x000001F0    /* Serial Word length select */
+#define SPORT_CTL_PACK                0x00000200    /* 16-bit to 32-bit packing enable */
+#define SPORT_CTL_ICLK                0x00000400    /* Internal Clock Select */
+#define SPORT_CTL_OPMODE              0x00000800    /* Operation mode */
+#define SPORT_CTL_CKRE                0x00001000    /* Clock rising edge select */
+#define SPORT_CTL_FSR                 0x00002000    /* Frame Sync required */
+#define SPORT_CTL_IFS                 0x00004000    /* Internal Frame Sync select */
+#define SPORT_CTL_DIFS                0x00008000    /* Data-independent frame sync select */
+#define SPORT_CTL_LFS                 0x00010000    /* Active low frame sync select */
+#define SPORT_CTL_LAFS                0x00020000    /* Late Transmit frame select */
+#define SPORT_CTL_RJUST               0x00040000    /* Right Justified mode select */
+#define SPORT_CTL_FSED                0x00080000    /* External frame sync edge select */
+#define SPORT_CTL_TFIEN               0x00100000    /* Transmit finish interrrupt enable select */
+#define SPORT_CTL_GCLKEN              0x00200000    /* Gated clock mode select */
+#define SPORT_CTL_SPENSEC             0x01000000    /* Enable secondary channel */
+#define SPORT_CTL_SPTRAN              0x02000000    /* Data direction control */
+#define SPORT_CTL_DERRSEC             0x04000000    /* Secondary channel error status */
+#define SPORT_CTL_DXSSEC              0x18000000    /* Secondary channel data buffer status */
+#define SPORT_CTL_SEC_EMPTY           0x00000000    /* DXSSEC: Empty */
+#define SPORT_CTL_SEC_PART_FULL       0x10000000    /* DXSSEC: Partially full */
+#define SPORT_CTL_SEC_FULL            0x18000000    /* DXSSEC: Full */
+#define SPORT_CTL_DERRPRI             0x20000000    /* Primary channel error status */
+#define SPORT_CTL_DXSPRI              0xC0000000    /* Primary channel data buffer status */
+#define SPORT_CTL_PRM_EMPTY           0x00000000    /* DXSPRI: Empty */
+#define SPORT_CTL_PRM_PART_FULL       0x80000000    /* DXSPRI: Partially full */
+#define SPORT_CTL_PRM_FULL            0xC0000000    /* DXSPRI: Full */
+#define SPORT_DIV_CLKDIV              0x0000FFFF    /* Clock divisor */
+#define SPORT_DIV_FSDIV               0xFFFF0000    /* Frame sync divisor */
+#define SPORT_MCTL_MCE                0x00000001    /* Multichannel enable */
+#define SPORT_MCTL_MCPDE              0x00000004    /* Multichannel data packing select */
+#define SPORT_MCTL_MFD                0x000000F0    /* Multichannel frame delay */
+#define SPORT_MCTL_WSIZE              0x00007F00    /* Number of multichannel slots */
+#define SPORT_MCTL_WOFFSET            0x03FF0000    /* Window offset size */
+#define SPORT_CNT_CLKCNT              0x0000FFFF    /* Current state of clk div counter */
+#define SPORT_CNT_FSDIVCNT            0xFFFF0000    /* Current state of frame div counter */
+#define SPORT_ERR_DERRPMSK            0x00000001    /* Primary channel data error interrupt enable */
+#define SPORT_ERR_DERRSMSK            0x00000002    /* Secondary channel data error interrupt enable */
+#define SPORT_ERR_FSERRMSK            0x00000004    /* Frame sync error interrupt enable */
+#define SPORT_ERR_DERRPSTAT           0x00000010    /* Primary channel data error status */
+#define SPORT_ERR_DERRSSTAT           0x00000020    /* Secondary channel data error status */
+#define SPORT_ERR_FSERRSTAT           0x00000040    /* Frame sync error status */
+#define SPORT_MSTAT_CURCHAN           0x000003FF    /* Channel which is being serviced in the multichannel operation */
+#define SPORT_CTL2_FSMUXSEL           0x00000001    /* Frame Sync MUX Select */
+#define SPORT_CTL2_CKMUXSEL           0x00000002    /* Clock MUX Select */
+#define SPORT_CTL2_LBSEL              0x00000004    /* Loopback Select */
+struct sport_register {
+        u32 spctl;
+        u32 div;
+        u32 spmctl;
+        u32 spcs0;
+        u32 spcs1;
+        u32 spcs2;
+        u32 spcs3;
+        u32 spcnt;
+        u32 sperrctl;
+        u32 spmstat;
+        u32 spctl2;
+        u32 txa;
+        u32 rxa;
+        u32 txb;
+        u32 rxb;
+        u32 revid;
+};
+struct bfin_snd_platform_data {
+        const unsigned short *pin_req;
+};
+#endif
diff --git a/arch/blackfin/include/asm/bfin_twi.h b/arch/blackfin/include/asm/bfin_twi.h
index e767d649dfc4..2f3339a47626 100644
--- a/arch/blackfin/include/asm/bfin_twi.h
+++ b/arch/blackfin/include/asm/bfin_twi.h
@@ -10,6 +10,7 @@
 #define __ASM_BFIN_TWI_H__
 #include <linux/types.h>
+#include <linux/i2c.h>
 /*
 * All Blackfin system MMRs are padded to 32bits even if the register
@@ -42,4 +43,145 @@ struct bfin_twi_regs {
 #undef __BFP
+struct bfin_twi_iface {
+        int                     irq;
+        spinlock_t              lock;
+        char                    read_write;
+        u8                      command;
+        u8                      *transPtr;
+        int                     readNum;
+        int                     writeNum;
+        int                     cur_mode;
+        int                     manual_stop;
+        int                     result;
+        struct i2c_adapter      adap;
+        struct completion       complete;
+        struct i2c_msg          *pmsg;
+        int                     msg_num;
+        int                     cur_msg;
+        u16                     saved_clkdiv;
+        u16                     saved_control;
+        struct bfin_twi_regs    *regs_base;
+};
+#define DEFINE_TWI_REG(reg_name, reg) \
+static inline u16 read_##reg_name(struct bfin_twi_iface *iface) \
+        { return iface->regs_base->reg; } \
+static inline void write_##reg_name(struct bfin_twi_iface *iface, u16 v) \
+        { iface->regs_base->reg = v; }
+DEFINE_TWI_REG(CLKDIV, clkdiv)
+DEFINE_TWI_REG(CONTROL, control)
+DEFINE_TWI_REG(SLAVE_CTL, slave_ctl)
+DEFINE_TWI_REG(SLAVE_STAT, slave_stat)
+DEFINE_TWI_REG(SLAVE_ADDR, slave_addr)
+DEFINE_TWI_REG(MASTER_CTL, master_ctl)
+DEFINE_TWI_REG(MASTER_STAT, master_stat)
+DEFINE_TWI_REG(MASTER_ADDR, master_addr)
+DEFINE_TWI_REG(INT_STAT, int_stat)
+DEFINE_TWI_REG(INT_MASK, int_mask)
+DEFINE_TWI_REG(FIFO_CTL, fifo_ctl)
+DEFINE_TWI_REG(FIFO_STAT, fifo_stat)
+DEFINE_TWI_REG(XMT_DATA8, xmt_data8)
+DEFINE_TWI_REG(XMT_DATA16, xmt_data16)
+#if !ANOMALY_05001001
+DEFINE_TWI_REG(RCV_DATA8, rcv_data8)
+DEFINE_TWI_REG(RCV_DATA16, rcv_data16)
+#else
+static inline u16 read_RCV_DATA8(struct bfin_twi_iface *iface)
+{
+        u16 ret;
+        unsigned long flags;
+        flags = hard_local_irq_save();
+        ret = iface->regs_base->rcv_data8;
+        hard_local_irq_restore(flags);
+        return ret;
+}
+static inline u16 read_RCV_DATA16(struct bfin_twi_iface *iface)
+{
+        u16 ret;
+        unsigned long flags;
+        flags = hard_local_irq_save();
+        ret = iface->regs_base->rcv_data16;
+        hard_local_irq_restore(flags);
+        return ret;
+}
+#endif
+/*  ********************  TWO-WIRE INTERFACE (TWI) MASKS  ***********************/
+/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y);  )                                */
+#define CLKLOW(x)       ((x) & 0xFF)    /* Periods Clock Is Held Low                    */
+#define CLKHI(y)        (((y)&0xFF)<<0x8)       /* Periods Before New Clock Low                 */
+/* TWI_PRESCALE Masks                                                                                                                   */
+#define PRESCALE        0x007F  /* SCLKs Per Internal Time Reference (10MHz)    */
+#define TWI_ENA         0x0080  /* TWI Enable                                                                   */
+#define SCCB            0x0200  /* SCCB Compatibility Enable                                    */
+/* TWI_SLAVE_CTL Masks                                                                                                                  */
+#define SEN                     0x0001  /* Slave Enable                                                                 */
+#define SADD_LEN        0x0002  /* Slave Address Length                                                 */
+#define STDVAL          0x0004  /* Slave Transmit Data Valid                                    */
+#define NAK                     0x0008  /* NAK/ACK* Generated At Conclusion Of Transfer */
+#define GEN                     0x0010  /* General Call Address Matching Enabled                */
+/* TWI_SLAVE_STAT Masks                                                                                                                 */
+#define SDIR            0x0001  /* Slave Transfer Direction (Transmit/Receive*) */
+#define GCALL           0x0002  /* General Call Indicator                                               */
+/* TWI_MASTER_CTL Masks                                                                                                 */
+#define MEN                     0x0001  /* Master Mode Enable                                           */
+#define MADD_LEN        0x0002  /* Master Address Length                                        */
+#define MDIR            0x0004  /* Master Transmit Direction (RX/TX*)           */
+#define FAST            0x0008  /* Use Fast Mode Timing Specs                           */
+#define STOP            0x0010  /* Issue Stop Condition                                         */
+#define RSTART          0x0020  /* Repeat Start or Stop* At End Of Transfer     */
+#define DCNT            0x3FC0  /* Data Bytes To Transfer                                       */
+#define SDAOVR          0x4000  /* Serial Data Override                                         */
+#define SCLOVR          0x8000  /* Serial Clock Override                                        */
+/* TWI_MASTER_STAT Masks                                                                                                                */
+#define MPROG           0x0001  /* Master Transfer In Progress                                  */
+#define LOSTARB         0x0002  /* Lost Arbitration Indicator (Xfer Aborted)    */
+#define ANAK            0x0004  /* Address Not Acknowledged                                             */
+#define DNAK            0x0008  /* Data Not Acknowledged                                                */
+#define BUFRDERR        0x0010  /* Buffer Read Error                                                    */
+#define BUFWRERR        0x0020  /* Buffer Write Error                                                   */
+#define SDASEN          0x0040  /* Serial Data Sense                                                    */
+#define SCLSEN          0x0080  /* Serial Clock Sense                                                   */
+#define BUSBUSY         0x0100  /* Bus Busy Indicator                                                   */
+/* TWI_INT_SRC and TWI_INT_ENABLE Masks                                         */
+#define SINIT           0x0001  /* Slave Transfer Initiated     */
+#define SCOMP           0x0002  /* Slave Transfer Complete      */
+#define SERR            0x0004  /* Slave Transfer Error         */
+#define SOVF            0x0008  /* Slave Overflow                       */
+#define MCOMP           0x0010  /* Master Transfer Complete     */
+#define MERR            0x0020  /* Master Transfer Error        */
+#define XMTSERV         0x0040  /* Transmit FIFO Service        */
+#define RCVSERV         0x0080  /* Receive FIFO Service         */
+/* TWI_FIFO_CTRL Masks                                                                                          */
+#define XMTFLUSH        0x0001  /* Transmit Buffer Flush                        */
+#define RCVFLUSH        0x0002  /* Receive Buffer Flush                         */
+#define XMTINTLEN       0x0004  /* Transmit Buffer Interrupt Length     */
+#define RCVINTLEN       0x0008  /* Receive Buffer Interrupt Length      */
+/* TWI_FIFO_STAT Masks                                                                                                                  */
+#define XMTSTAT         0x0003  /* Transmit FIFO Status                                                 */
+#define XMT_EMPTY       0x0000  /*              Transmit FIFO Empty                                             */
+#define XMT_HALF        0x0001  /*              Transmit FIFO Has 1 Byte To Write               */
+#define XMT_FULL        0x0003  /*              Transmit FIFO Full (2 Bytes To Write)   */
+#define RCVSTAT         0x000C  /* Receive FIFO Status                                                  */
+#define RCV_EMPTY       0x0000  /*              Receive FIFO Empty                                              */
+#define RCV_HALF        0x0004  /*              Receive FIFO Has 1 Byte To Read                 */
+#define RCV_FULL        0x000C  /*              Receive FIFO Full (2 Bytes To Read)             */
 #endif
diff --git a/arch/blackfin/include/asm/blackfin.h b/arch/blackfin/include/asm/blackfin.h
index 7be5368c0512..f111f366d758 100644
--- a/arch/blackfin/include/asm/blackfin.h
+++ b/arch/blackfin/include/asm/blackfin.h
@@ -63,20 +63,16 @@ static inline void CSYNC(void)
 #if ANOMALY_05000312 || ANOMALY_05000244
 #define SSYNC(scratch)  \
-do {                    \
        cli scratch;    \
        nop; nop; nop;  \
        SSYNC;          \
-        sti scratch;    \
+        sti scratch;
-} while (0)
 #define CSYNC(scratch)  \
-do {                    \
        cli scratch;    \
        nop; nop; nop;  \
        CSYNC;          \
-        sti scratch;    \
+        sti scratch;
-} while (0)
 #else
 #define SSYNC(scratch) SSYNC;
diff --git a/arch/blackfin/include/asm/clkdev.h b/arch/blackfin/include/asm/clkdev.h
new file mode 100644
index 000000000000..9053beda8c50
--- /dev/null
+++ b/arch/blackfin/include/asm/clkdev.h
@@ -0,0 +1,14 @@
+#ifndef __ASM_CLKDEV__H_
+#define __ASM_CLKDEV__H_
+#include <linux/slab.h>
+static inline struct clk_lookup_alloc *__clkdev_alloc(size_t size)
+{
+        return kzalloc(size, GFP_KERNEL);
+}
+#define __clk_put(clk)
+#define __clk_get(clk) ({ 1; })
+#endif
diff --git a/arch/blackfin/include/asm/clocks.h b/arch/blackfin/include/asm/clocks.h
index 6f0b61852f58..9b3c85b3c288 100644
--- a/arch/blackfin/include/asm/clocks.h
+++ b/arch/blackfin/include/asm/clocks.h
@@ -48,4 +48,27 @@
 # define CONFIG_VCO_MULT 0
 #endif
+#include <linux/clk.h>
+struct clk_ops {
+        unsigned long (*get_rate)(struct clk *clk);
+        unsigned long (*round_rate)(struct clk *clk, unsigned long rate);
+        int (*set_rate)(struct clk *clk, unsigned long rate);
+        int (*enable)(struct clk *clk);
+        int (*disable)(struct clk *clk);
+};
+struct clk {
+        struct clk              *parent;
+        const char              *name;
+        unsigned long           rate;
+        spinlock_t              lock;
+        u32                     flags;
+        const struct clk_ops    *ops;
+        void __iomem            *reg;
+        u32                     mask;
+        u32                     shift;
+};
+int clk_init(void);
 #endif
diff --git a/arch/blackfin/include/asm/cplb.h b/arch/blackfin/include/asm/cplb.h
index fda96261ed62..5c37f620c4b3 100644
--- a/arch/blackfin/include/asm/cplb.h
+++ b/arch/blackfin/include/asm/cplb.h
@@ -62,6 +62,10 @@
 #define SIZE_4K 0x00001000      /* 4K */
 #define SIZE_1M 0x00100000      /* 1M */
 #define SIZE_4M 0x00400000      /* 4M */
+#define SIZE_16K 0x00004000      /* 16K */
+#define SIZE_64K 0x00010000      /* 64K */
+#define SIZE_16M 0x01000000      /* 16M */
+#define SIZE_64M 0x04000000      /* 64M */
 #define MAX_CPLBS 16
diff --git a/arch/blackfin/include/asm/def_LPBlackfin.h b/arch/blackfin/include/asm/def_LPBlackfin.h
index 823679011457..fe0ca03a1cb2 100644
--- a/arch/blackfin/include/asm/def_LPBlackfin.h
+++ b/arch/blackfin/include/asm/def_LPBlackfin.h
@@ -3,7 +3,7 @@
 *
 * Copyright 2005-2008 Analog Devices Inc.
 *
- * Licensed under the ADI BSD license or GPL-2 (or later).
+ * Licensed under the Clear BSD license or GPL-2 (or later).
 */
 #ifndef _DEF_LPBLACKFIN_H
@@ -622,6 +622,10 @@ do { \
 #define PAGE_SIZE_4KB      0x00010000   /* 4 KB page size */
 #define PAGE_SIZE_1MB      0x00020000   /* 1 MB page size */
 #define PAGE_SIZE_4MB      0x00030000   /* 4 MB page size */
+#define PAGE_SIZE_16KB     0x00040000   /* 16 KB page size */
+#define PAGE_SIZE_64KB     0x00050000   /* 64 KB page size */
+#define PAGE_SIZE_16MB     0x00060000   /* 16 MB page size */
+#define PAGE_SIZE_64MB     0x00070000   /* 64 MB page size */
 #define CPLB_L1SRAM        0x00000020   /* 0=SRAM mapped in L1, 0=SRAM not
                                         * mapped to L1
                                         */
diff --git a/arch/blackfin/include/asm/dma.h b/arch/blackfin/include/asm/dma.h
index dac0c97242bb..40e9c2bbc6e3 100644
--- a/arch/blackfin/include/asm/dma.h
+++ b/arch/blackfin/include/asm/dma.h
@@ -22,12 +22,22 @@
 #define DATA_SIZE_8                     0
 #define DATA_SIZE_16            1
 #define DATA_SIZE_32            2
+#ifdef CONFIG_BF60x
+#define DATA_SIZE_64            3
+#endif
 #define DMA_FLOW_STOP           0
 #define DMA_FLOW_AUTO           1
+#ifdef CONFIG_BF60x
+#define DMA_FLOW_LIST           4
+#define DMA_FLOW_ARRAY          5
+#define DMA_FLOW_LIST_DEMAND    6
+#define DMA_FLOW_ARRAY_DEMAND   7
+#else
 #define DMA_FLOW_ARRAY          4
 #define DMA_FLOW_SMALL          6
 #define DMA_FLOW_LARGE          7
+#endif
 #define DIMENSION_LINEAR        0
 #define DIMENSION_2D            1
@@ -36,26 +46,80 @@
 #define DIR_WRITE                       1
 #define INTR_DISABLE            0
+#ifdef CONFIG_BF60x
+#define INTR_ON_PERI                    1
+#endif
 #define INTR_ON_BUF                     2
 #define INTR_ON_ROW                     3
 #define DMA_NOSYNC_KEEP_DMA_BUF 0
 #define DMA_SYNC_RESTART                1
+#ifdef DMA_MMR_SIZE_32
+#define DMA_MMR_SIZE_TYPE long
+#define DMA_MMR_READ bfin_read32
+#define DMA_MMR_WRITE bfin_write32
+#else
+#define DMA_MMR_SIZE_TYPE short
+#define DMA_MMR_READ bfin_read16
+#define DMA_MMR_WRITE bfin_write16
+#endif
+struct dma_desc_array {
+        unsigned long start_addr;
+        unsigned DMA_MMR_SIZE_TYPE cfg;
+        unsigned DMA_MMR_SIZE_TYPE x_count;
+        DMA_MMR_SIZE_TYPE x_modify;
+} __attribute__((packed));
 struct dmasg {
        void *next_desc_addr;
        unsigned long start_addr;
-        unsigned short cfg;
+        unsigned DMA_MMR_SIZE_TYPE cfg;
-        unsigned short x_count;
+        unsigned DMA_MMR_SIZE_TYPE x_count;
-        short x_modify;
+        DMA_MMR_SIZE_TYPE x_modify;
-        unsigned short y_count;
+        unsigned DMA_MMR_SIZE_TYPE y_count;
-        short y_modify;
+        DMA_MMR_SIZE_TYPE y_modify;
 } __attribute__((packed));
 struct dma_register {
        void *next_desc_ptr;    /* DMA Next Descriptor Pointer register */
        unsigned long start_addr;       /* DMA Start address  register */
+#ifdef CONFIG_BF60x
+        unsigned long cfg;      /* DMA Configuration register */
+        unsigned long x_count;  /* DMA x_count register */
+        long x_modify;  /* DMA x_modify register */
+        unsigned long y_count;  /* DMA y_count register */
+        long y_modify;  /* DMA y_modify register */
+        unsigned long reserved;
+        unsigned long reserved2;
+        void *curr_desc_ptr;    /* DMA Current Descriptor Pointer
+                                           register */
+        void *prev_desc_ptr;    /* DMA previous initial Descriptor Pointer
+                                           register */
+        unsigned long curr_addr_ptr;    /* DMA Current Address Pointer
+                                                   register */
+        unsigned long irq_status;       /* DMA irq status register */
+        unsigned long curr_x_count;     /* DMA Current x-count register */
+        unsigned long curr_y_count;     /* DMA Current y-count register */
+        unsigned long reserved3;
+        unsigned long bw_limit_count;   /* DMA band width limit count register */
+        unsigned long curr_bw_limit_count;      /* DMA Current band width limit
+                                                        count register */
+        unsigned long bw_monitor_count; /* DMA band width limit count register */
+        unsigned long curr_bw_monitor_count;    /* DMA Current band width limit
+                                                        count register */
+#else
        unsigned short cfg;     /* DMA Configuration register */
        unsigned short dummy1;  /* DMA Configuration register */
@@ -92,6 +156,7 @@ struct dma_register {
        unsigned short dummy9;
        unsigned long reserved3;
+#endif
 };
@@ -131,23 +196,23 @@ static inline void set_dma_curr_desc_addr(unsigned int channel, void *addr)
 {
        dma_ch[channel].regs->curr_desc_ptr = addr;
 }
-static inline void set_dma_x_count(unsigned int channel, unsigned short x_count)
+static inline void set_dma_x_count(unsigned int channel, unsigned DMA_MMR_SIZE_TYPE x_count)
 {
        dma_ch[channel].regs->x_count = x_count;
 }
-static inline void set_dma_y_count(unsigned int channel, unsigned short y_count)
+static inline void set_dma_y_count(unsigned int channel, unsigned DMA_MMR_SIZE_TYPE y_count)
 {
        dma_ch[channel].regs->y_count = y_count;
 }
-static inline void set_dma_x_modify(unsigned int channel, short x_modify)
+static inline void set_dma_x_modify(unsigned int channel, DMA_MMR_SIZE_TYPE x_modify)
 {
        dma_ch[channel].regs->x_modify = x_modify;
 }
-static inline void set_dma_y_modify(unsigned int channel, short y_modify)
+static inline void set_dma_y_modify(unsigned int channel, DMA_MMR_SIZE_TYPE y_modify)
 {
        dma_ch[channel].regs->y_modify = y_modify;
 }
-static inline void set_dma_config(unsigned int channel, unsigned short config)
+static inline void set_dma_config(unsigned int channel, unsigned DMA_MMR_SIZE_TYPE config)
 {
        dma_ch[channel].regs->cfg = config;
 }
@@ -156,23 +221,55 @@ static inline void set_dma_curr_addr(unsigned int channel, unsigned long addr)
        dma_ch[channel].regs->curr_addr_ptr = addr;
 }
-static inline unsigned short
+#ifdef CONFIG_BF60x
+static inline unsigned long
+set_bfin_dma_config2(char direction, char flow_mode, char intr_mode,
+                     char dma_mode, char mem_width, char syncmode, char peri_width)
+{
+        unsigned long config = 0;
+        switch (intr_mode) {
+        case INTR_ON_BUF:
+                if (dma_mode == DIMENSION_2D)
+                        config = DI_EN_Y;
+                else
+                        config = DI_EN_X;
+                break;
+        case INTR_ON_ROW:
+                config = DI_EN_X;
+                break;
+        case INTR_ON_PERI:
+                config = DI_EN_P;
+                break;
+        };
+        return config | (direction << 1) | (mem_width << 8) | (dma_mode << 26) |
+                (flow_mode << 12) | (syncmode << 2) | (peri_width << 4);
+}
+#endif
+static inline unsigned DMA_MMR_SIZE_TYPE
 set_bfin_dma_config(char direction, char flow_mode,
-                    char intr_mode, char dma_mode, char width, char syncmode)
+                    char intr_mode, char dma_mode, char mem_width, char syncmode)
 {
-        return (direction << 1) | (width << 2) | (dma_mode << 4) |
+#ifdef CONFIG_BF60x
+        return set_bfin_dma_config2(direction, flow_mode, intr_mode, dma_mode,
+                mem_width, syncmode, mem_width);
+#else
+        return (direction << 1) | (mem_width << 2) | (dma_mode << 4) |
                (intr_mode << 6) | (flow_mode << 12) | (syncmode << 5);
+#endif
 }
-static inline unsigned short get_dma_curr_irqstat(unsigned int channel)
+static inline unsigned DMA_MMR_SIZE_TYPE get_dma_curr_irqstat(unsigned int channel)
 {
        return dma_ch[channel].regs->irq_status;
 }
-static inline unsigned short get_dma_curr_xcount(unsigned int channel)
+static inline unsigned DMA_MMR_SIZE_TYPE get_dma_curr_xcount(unsigned int channel)
 {
        return dma_ch[channel].regs->curr_x_count;
 }
-static inline unsigned short get_dma_curr_ycount(unsigned int channel)
+static inline unsigned DMA_MMR_SIZE_TYPE get_dma_curr_ycount(unsigned int channel)
 {
        return dma_ch[channel].regs->curr_y_count;
 }
@@ -184,7 +281,7 @@ static inline void *get_dma_curr_desc_ptr(unsigned int channel)
 {
        return dma_ch[channel].regs->curr_desc_ptr;
 }
-static inline unsigned short get_dma_config(unsigned int channel)
+static inline unsigned DMA_MMR_SIZE_TYPE get_dma_config(unsigned int channel)
 {
        return dma_ch[channel].regs->cfg;
 }
@@ -203,8 +300,8 @@ static inline void set_dma_sg(unsigned int channel, struct dmasg *sg, int ndsize
        dma_ch[channel].regs->next_desc_ptr = sg;
        dma_ch[channel].regs->cfg =
-                (dma_ch[channel].regs->cfg & ~(0xf << 8)) |
+                (dma_ch[channel].regs->cfg & ~NDSIZE) |
-                ((ndsize & 0xf) << 8);
+                ((ndsize << NDSIZE_OFFSET) & NDSIZE);
 }
 static inline int dma_channel_active(unsigned int channel)
@@ -239,7 +336,7 @@ static inline void dma_enable_irq(unsigned int channel)
 }
 static inline void clear_dma_irqstat(unsigned int channel)
 {
-        dma_ch[channel].regs->irq_status = DMA_DONE | DMA_ERR;
+        dma_ch[channel].regs->irq_status = DMA_DONE | DMA_ERR | DMA_PIRQ;
 }
 void *dma_memcpy(void *dest, const void *src, size_t count);
diff --git a/arch/blackfin/include/asm/dpmc.h b/arch/blackfin/include/asm/dpmc.h
index c4ec959dad78..e91eae8330a6 100644
--- a/arch/blackfin/include/asm/dpmc.h
+++ b/arch/blackfin/include/asm/dpmc.h
@@ -9,6 +9,651 @@
 #ifndef _BLACKFIN_DPMC_H_
 #define _BLACKFIN_DPMC_H_
+#ifdef __ASSEMBLY__
+#define PM_REG0  R7
+#define PM_REG1  R6
+#define PM_REG2  R5
+#define PM_REG3  R4
+#define PM_REG4  R3
+#define PM_REG5  R2
+#define PM_REG6  R1
+#define PM_REG7  R0
+#define PM_REG8  P5
+#define PM_REG9  P4
+#define PM_REG10 P3
+#define PM_REG11 P2
+#define PM_REG12 P1
+#define PM_REG13 P0
+#define PM_REGSET0  R7:7
+#define PM_REGSET1  R7:6
+#define PM_REGSET2  R7:5
+#define PM_REGSET3  R7:4
+#define PM_REGSET4  R7:3
+#define PM_REGSET5  R7:2
+#define PM_REGSET6  R7:1
+#define PM_REGSET7  R7:0
+#define PM_REGSET8  R7:0, P5:5
+#define PM_REGSET9  R7:0, P5:4
+#define PM_REGSET10 R7:0, P5:3
+#define PM_REGSET11 R7:0, P5:2
+#define PM_REGSET12 R7:0, P5:1
+#define PM_REGSET13 R7:0, P5:0
+#define _PM_PUSH(n, x, w, base) PM_REG##n = w[FP + ((x) - (base))];
+#define _PM_POP(n, x, w, base)  w[FP + ((x) - (base))] = PM_REG##n;
+#define PM_PUSH_SYNC(n)         [--sp] = (PM_REGSET##n);
+#define PM_POP_SYNC(n)          (PM_REGSET##n) = [sp++];
+#define PM_PUSH(n, x)           PM_REG##n = [FP++];
+#define PM_POP(n, x)            [FP--] = PM_REG##n;
+#define PM_CORE_PUSH(n, x)      _PM_PUSH(n, x, , COREMMR_BASE)
+#define PM_CORE_POP(n, x)       _PM_POP(n, x, , COREMMR_BASE)
+#define PM_SYS_PUSH(n, x)       _PM_PUSH(n, x, , SYSMMR_BASE)
+#define PM_SYS_POP(n, x)        _PM_POP(n, x, , SYSMMR_BASE)
+#define PM_SYS_PUSH16(n, x)     _PM_PUSH(n, x, w, SYSMMR_BASE)
+#define PM_SYS_POP16(n, x)      _PM_POP(n, x, w, SYSMMR_BASE)
+        .macro bfin_init_pm_bench_cycles
+#ifdef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH
+        R4 = 0;
+        CYCLES = R4;
+        CYCLES2 = R4;
+        R4 = SYSCFG;
+        BITSET(R4, 1);
+        SYSCFG = R4;
+#endif
+        .endm
+        .macro bfin_cpu_reg_save
+        /*
+         * Save the core regs early so we can blow them away when
+         * saving/restoring MMR states
+         */
+        [--sp] = (R7:0, P5:0);
+        [--sp] = fp;
+        [--sp] = usp;
+        [--sp] = i0;
+        [--sp] = i1;
+        [--sp] = i2;
+        [--sp] = i3;
+        [--sp] = m0;
+        [--sp] = m1;
+        [--sp] = m2;
+        [--sp] = m3;
+        [--sp] = l0;
+        [--sp] = l1;
+        [--sp] = l2;
+        [--sp] = l3;
+        [--sp] = b0;
+        [--sp] = b1;
+        [--sp] = b2;
+        [--sp] = b3;
+        [--sp] = a0.x;
+        [--sp] = a0.w;
+        [--sp] = a1.x;
+        [--sp] = a1.w;
+        [--sp] = LC0;
+        [--sp] = LC1;
+        [--sp] = LT0;
+        [--sp] = LT1;
+        [--sp] = LB0;
+        [--sp] = LB1;
+        /* We can't push RETI directly as that'll change IPEND[4] */
+        r7 = RETI;
+        [--sp] = RETS;
+        [--sp] = ASTAT;
+#ifndef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH
+        [--sp] = CYCLES;
+        [--sp] = CYCLES2;
+#endif
+        [--sp] = SYSCFG;
+        [--sp] = RETX;
+        [--sp] = SEQSTAT;
+        [--sp] = r7;
+        /* Save first func arg in M3 */
+        M3 = R0;
+        .endm
+        .macro bfin_cpu_reg_restore
+        /* Restore Core Registers */
+        RETI = [sp++];
+        SEQSTAT = [sp++];
+        RETX = [sp++];
+        SYSCFG = [sp++];
+#ifndef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH
+        CYCLES2 = [sp++];
+        CYCLES = [sp++];
+#endif
+        ASTAT = [sp++];
+        RETS = [sp++];
+        LB1 = [sp++];
+        LB0 = [sp++];
+        LT1 = [sp++];
+        LT0 = [sp++];
+        LC1 = [sp++];
+        LC0 = [sp++];
+        a1.w = [sp++];
+        a1.x = [sp++];
+        a0.w = [sp++];
+        a0.x = [sp++];
+        b3 = [sp++];
+        b2 = [sp++];
+        b1 = [sp++];
+        b0 = [sp++];
+        l3 = [sp++];
+        l2 = [sp++];
+        l1 = [sp++];
+        l0 = [sp++];
+        m3 = [sp++];
+        m2 = [sp++];
+        m1 = [sp++];
+        m0 = [sp++];
+        i3 = [sp++];
+        i2 = [sp++];
+        i1 = [sp++];
+        i0 = [sp++];
+        usp = [sp++];
+        fp = [sp++];
+        (R7:0, P5:0) = [sp++];
+        .endm
+        .macro bfin_sys_mmr_save
+        /* Save system MMRs */
+        FP.H = hi(SYSMMR_BASE);
+        FP.L = lo(SYSMMR_BASE);
+#ifdef SIC_IMASK0
+        PM_SYS_PUSH(0, SIC_IMASK0)
+        PM_SYS_PUSH(1, SIC_IMASK1)
+# ifdef SIC_IMASK2
+        PM_SYS_PUSH(2, SIC_IMASK2)
+# endif
+#else
+# ifdef SIC_IMASK
+        PM_SYS_PUSH(0, SIC_IMASK)
+# endif
+#endif
+#ifdef SIC_IAR0
+        PM_SYS_PUSH(3, SIC_IAR0)
+        PM_SYS_PUSH(4, SIC_IAR1)
+        PM_SYS_PUSH(5, SIC_IAR2)
+#endif
+#ifdef SIC_IAR3
+        PM_SYS_PUSH(6, SIC_IAR3)
+#endif
+#ifdef SIC_IAR4
+        PM_SYS_PUSH(7, SIC_IAR4)
+        PM_SYS_PUSH(8, SIC_IAR5)
+        PM_SYS_PUSH(9, SIC_IAR6)
+#endif
+#ifdef SIC_IAR7
+        PM_SYS_PUSH(10, SIC_IAR7)
+#endif
+#ifdef SIC_IAR8
+        PM_SYS_PUSH(11, SIC_IAR8)
+        PM_SYS_PUSH(12, SIC_IAR9)
+        PM_SYS_PUSH(13, SIC_IAR10)
+#endif
+        PM_PUSH_SYNC(13)
+#ifdef SIC_IAR11
+        PM_SYS_PUSH(0, SIC_IAR11)
+#endif
+#ifdef SIC_IWR
+        PM_SYS_PUSH(1, SIC_IWR)
+#endif
+#ifdef SIC_IWR0
+        PM_SYS_PUSH(1, SIC_IWR0)
+#endif
+#ifdef SIC_IWR1
+        PM_SYS_PUSH(2, SIC_IWR1)
+#endif
+#ifdef SIC_IWR2
+        PM_SYS_PUSH(3, SIC_IWR2)
+#endif
+#ifdef PINT0_ASSIGN
+        PM_SYS_PUSH(4, PINT0_MASK_SET)
+        PM_SYS_PUSH(5, PINT1_MASK_SET)
+        PM_SYS_PUSH(6, PINT2_MASK_SET)
+        PM_SYS_PUSH(7, PINT3_MASK_SET)
+        PM_SYS_PUSH(8, PINT0_ASSIGN)
+        PM_SYS_PUSH(9, PINT1_ASSIGN)
+        PM_SYS_PUSH(10, PINT2_ASSIGN)
+        PM_SYS_PUSH(11, PINT3_ASSIGN)
+        PM_SYS_PUSH(12, PINT0_INVERT_SET)
+        PM_SYS_PUSH(13, PINT1_INVERT_SET)
+        PM_PUSH_SYNC(13)
+        PM_SYS_PUSH(0, PINT2_INVERT_SET)
+        PM_SYS_PUSH(1, PINT3_INVERT_SET)
+        PM_SYS_PUSH(2, PINT0_EDGE_SET)
+        PM_SYS_PUSH(3, PINT1_EDGE_SET)
+        PM_SYS_PUSH(4, PINT2_EDGE_SET)
+        PM_SYS_PUSH(5, PINT3_EDGE_SET)
+#endif
+#ifdef SYSCR
+        PM_SYS_PUSH16(6, SYSCR)
+#endif
+#ifdef EBIU_AMGCTL
+        PM_SYS_PUSH16(7, EBIU_AMGCTL)
+        PM_SYS_PUSH(8, EBIU_AMBCTL0)
+        PM_SYS_PUSH(9, EBIU_AMBCTL1)
+#endif
+#ifdef EBIU_FCTL
+        PM_SYS_PUSH(10, EBIU_MBSCTL)
+        PM_SYS_PUSH(11, EBIU_MODE)
+        PM_SYS_PUSH(12, EBIU_FCTL)
+        PM_PUSH_SYNC(12)
+#else
+        PM_PUSH_SYNC(9)
+#endif
+        .endm
+        .macro bfin_sys_mmr_restore
+/* Restore System MMRs */
+        FP.H = hi(SYSMMR_BASE);
+        FP.L = lo(SYSMMR_BASE);
+#ifdef EBIU_FCTL
+        PM_POP_SYNC(12)
+        PM_SYS_POP(12, EBIU_FCTL)
+        PM_SYS_POP(11, EBIU_MODE)
+        PM_SYS_POP(10, EBIU_MBSCTL)
+#else
+        PM_POP_SYNC(9)
+#endif
+#ifdef EBIU_AMBCTL
+        PM_SYS_POP(9, EBIU_AMBCTL1)
+        PM_SYS_POP(8, EBIU_AMBCTL0)
+        PM_SYS_POP16(7, EBIU_AMGCTL)
+#endif
+#ifdef SYSCR
+        PM_SYS_POP16(6, SYSCR)
+#endif
+#ifdef PINT0_ASSIGN
+        PM_SYS_POP(5, PINT3_EDGE_SET)
+        PM_SYS_POP(4, PINT2_EDGE_SET)
+        PM_SYS_POP(3, PINT1_EDGE_SET)
+        PM_SYS_POP(2, PINT0_EDGE_SET)
+        PM_SYS_POP(1, PINT3_INVERT_SET)
+        PM_SYS_POP(0, PINT2_INVERT_SET)
+        PM_POP_SYNC(13)
+        PM_SYS_POP(13, PINT1_INVERT_SET)
+        PM_SYS_POP(12, PINT0_INVERT_SET)
+        PM_SYS_POP(11, PINT3_ASSIGN)
+        PM_SYS_POP(10, PINT2_ASSIGN)
+        PM_SYS_POP(9, PINT1_ASSIGN)
+        PM_SYS_POP(8, PINT0_ASSIGN)
+        PM_SYS_POP(7, PINT3_MASK_SET)
+        PM_SYS_POP(6, PINT2_MASK_SET)
+        PM_SYS_POP(5, PINT1_MASK_SET)
+        PM_SYS_POP(4, PINT0_MASK_SET)
+#endif
+#ifdef SIC_IWR2
+        PM_SYS_POP(3, SIC_IWR2)
+#endif
+#ifdef SIC_IWR1
+        PM_SYS_POP(2, SIC_IWR1)
+#endif
+#ifdef SIC_IWR0
+        PM_SYS_POP(1, SIC_IWR0)
+#endif
+#ifdef SIC_IWR
+        PM_SYS_POP(1, SIC_IWR)
+#endif
+#ifdef SIC_IAR11
+        PM_SYS_POP(0, SIC_IAR11)
+#endif
+        PM_POP_SYNC(13)
+#ifdef SIC_IAR8
+        PM_SYS_POP(13, SIC_IAR10)
+        PM_SYS_POP(12, SIC_IAR9)
+        PM_SYS_POP(11, SIC_IAR8)
+#endif
+#ifdef SIC_IAR7
+        PM_SYS_POP(10, SIC_IAR7)
+#endif
+#ifdef SIC_IAR6
+        PM_SYS_POP(9, SIC_IAR6)
+        PM_SYS_POP(8, SIC_IAR5)
+        PM_SYS_POP(7, SIC_IAR4)
+#endif
+#ifdef SIC_IAR3
+        PM_SYS_POP(6, SIC_IAR3)
+#endif
+#ifdef SIC_IAR0
+        PM_SYS_POP(5, SIC_IAR2)
+        PM_SYS_POP(4, SIC_IAR1)
+        PM_SYS_POP(3, SIC_IAR0)
+#endif
+#ifdef SIC_IMASK0
+# ifdef SIC_IMASK2
+        PM_SYS_POP(2, SIC_IMASK2)
+# endif
+        PM_SYS_POP(1, SIC_IMASK1)
+        PM_SYS_POP(0, SIC_IMASK0)
+#else
+# ifdef SIC_IMASK
+        PM_SYS_POP(0, SIC_IMASK)
+# endif
+#endif
+        .endm
+        .macro bfin_core_mmr_save
+        /* Save Core MMRs */
+        I0.H = hi(COREMMR_BASE);
+        I0.L = lo(COREMMR_BASE);
+        I1 = I0;
+        I2 = I0;
+        I3 = I0;
+        B0 = I0;
+        B1 = I0;
+        B2 = I0;
+        B3 = I0;
+        I1.L = lo(DCPLB_ADDR0);
+        I2.L = lo(DCPLB_DATA0);
+        I3.L = lo(ICPLB_ADDR0);
+        B0.L = lo(ICPLB_DATA0);
+        B1.L = lo(EVT2);
+        B2.L = lo(IMASK);
+        B3.L = lo(TCNTL);
+        /* Event Vectors */
+        FP = B1;
+        PM_PUSH(0, EVT2)
+        PM_PUSH(1, EVT3)
+        FP += 4;        /* EVT4 */
+        PM_PUSH(2, EVT5)
+        PM_PUSH(3, EVT6)
+        PM_PUSH(4, EVT7)
+        PM_PUSH(5, EVT8)
+        PM_PUSH_SYNC(5)
+        PM_PUSH(0, EVT9)
+        PM_PUSH(1, EVT10)
+        PM_PUSH(2, EVT11)
+        PM_PUSH(3, EVT12)
+        PM_PUSH(4, EVT13)
+        PM_PUSH(5, EVT14)
+        PM_PUSH(6, EVT15)
+        /* CEC */
+        FP = B2;
+        PM_PUSH(7, IMASK)
+        FP += 4;        /* IPEND */
+        PM_PUSH(8, ILAT)
+        PM_PUSH(9, IPRIO)
+        /* Core Timer */
+        FP = B3;
+        PM_PUSH(10, TCNTL)
+        PM_PUSH(11, TPERIOD)
+        PM_PUSH(12, TSCALE)
+        PM_PUSH(13, TCOUNT)
+        PM_PUSH_SYNC(13)
+        /* Misc non-contiguous registers */
+        FP = I0;
+        PM_CORE_PUSH(0, DMEM_CONTROL);
+        PM_CORE_PUSH(1, IMEM_CONTROL);
+        PM_CORE_PUSH(2, TBUFCTL);
+        PM_PUSH_SYNC(2)
+        /* DCPLB Addr */
+        FP = I1;
+        PM_PUSH(0, DCPLB_ADDR0)
+        PM_PUSH(1, DCPLB_ADDR1)
+        PM_PUSH(2, DCPLB_ADDR2)
+        PM_PUSH(3, DCPLB_ADDR3)
+        PM_PUSH(4, DCPLB_ADDR4)
+        PM_PUSH(5, DCPLB_ADDR5)
+        PM_PUSH(6, DCPLB_ADDR6)
+        PM_PUSH(7, DCPLB_ADDR7)
+        PM_PUSH(8, DCPLB_ADDR8)
+        PM_PUSH(9, DCPLB_ADDR9)
+        PM_PUSH(10, DCPLB_ADDR10)
+        PM_PUSH(11, DCPLB_ADDR11)
+        PM_PUSH(12, DCPLB_ADDR12)
+        PM_PUSH(13, DCPLB_ADDR13)
+        PM_PUSH_SYNC(13)
+        PM_PUSH(0, DCPLB_ADDR14)
+        PM_PUSH(1, DCPLB_ADDR15)
+        /* DCPLB Data */
+        FP = I2;
+        PM_PUSH(2, DCPLB_DATA0)
+        PM_PUSH(3, DCPLB_DATA1)
+        PM_PUSH(4, DCPLB_DATA2)
+        PM_PUSH(5, DCPLB_DATA3)
+        PM_PUSH(6, DCPLB_DATA4)
+        PM_PUSH(7, DCPLB_DATA5)
+        PM_PUSH(8, DCPLB_DATA6)
+        PM_PUSH(9, DCPLB_DATA7)
+        PM_PUSH(10, DCPLB_DATA8)
+        PM_PUSH(11, DCPLB_DATA9)
+        PM_PUSH(12, DCPLB_DATA10)
+        PM_PUSH(13, DCPLB_DATA11)
+        PM_PUSH_SYNC(13)
+        PM_PUSH(0, DCPLB_DATA12)
+        PM_PUSH(1, DCPLB_DATA13)
+        PM_PUSH(2, DCPLB_DATA14)
+        PM_PUSH(3, DCPLB_DATA15)
+        /* ICPLB Addr */
+        FP = I3;
+        PM_PUSH(4, ICPLB_ADDR0)
+        PM_PUSH(5, ICPLB_ADDR1)
+        PM_PUSH(6, ICPLB_ADDR2)
+        PM_PUSH(7, ICPLB_ADDR3)
+        PM_PUSH(8, ICPLB_ADDR4)
+        PM_PUSH(9, ICPLB_ADDR5)
+        PM_PUSH(10, ICPLB_ADDR6)
+        PM_PUSH(11, ICPLB_ADDR7)
+        PM_PUSH(12, ICPLB_ADDR8)
+        PM_PUSH(13, ICPLB_ADDR9)
+        PM_PUSH_SYNC(13)
+        PM_PUSH(0, ICPLB_ADDR10)
+        PM_PUSH(1, ICPLB_ADDR11)
+        PM_PUSH(2, ICPLB_ADDR12)
+        PM_PUSH(3, ICPLB_ADDR13)
+        PM_PUSH(4, ICPLB_ADDR14)
+        PM_PUSH(5, ICPLB_ADDR15)
+        /* ICPLB Data */
+        FP = B0;
+        PM_PUSH(6, ICPLB_DATA0)
+        PM_PUSH(7, ICPLB_DATA1)
+        PM_PUSH(8, ICPLB_DATA2)
+        PM_PUSH(9, ICPLB_DATA3)
+        PM_PUSH(10, ICPLB_DATA4)
+        PM_PUSH(11, ICPLB_DATA5)
+        PM_PUSH(12, ICPLB_DATA6)
+        PM_PUSH(13, ICPLB_DATA7)
+        PM_PUSH_SYNC(13)
+        PM_PUSH(0, ICPLB_DATA8)
+        PM_PUSH(1, ICPLB_DATA9)
+        PM_PUSH(2, ICPLB_DATA10)
+        PM_PUSH(3, ICPLB_DATA11)
+        PM_PUSH(4, ICPLB_DATA12)
+        PM_PUSH(5, ICPLB_DATA13)
+        PM_PUSH(6, ICPLB_DATA14)
+        PM_PUSH(7, ICPLB_DATA15)
+        PM_PUSH_SYNC(7)
+        .endm
+        .macro bfin_core_mmr_restore
+        /* Restore Core MMRs */
+        I0.H = hi(COREMMR_BASE);
+        I0.L = lo(COREMMR_BASE);
+        I1 = I0;
+        I2 = I0;
+        I3 = I0;
+        B0 = I0;
+        B1 = I0;
+        B2 = I0;
+        B3 = I0;
+        I1.L = lo(DCPLB_ADDR15);
+        I2.L = lo(DCPLB_DATA15);
+        I3.L = lo(ICPLB_ADDR15);
+        B0.L = lo(ICPLB_DATA15);
+        B1.L = lo(EVT15);
+        B2.L = lo(IPRIO);
+        B3.L = lo(TCOUNT);
+        /* ICPLB Data */
+        FP = B0;
+        PM_POP_SYNC(7)
+        PM_POP(7, ICPLB_DATA15)
+        PM_POP(6, ICPLB_DATA14)
+        PM_POP(5, ICPLB_DATA13)
+        PM_POP(4, ICPLB_DATA12)
+        PM_POP(3, ICPLB_DATA11)
+        PM_POP(2, ICPLB_DATA10)
+        PM_POP(1, ICPLB_DATA9)
+        PM_POP(0, ICPLB_DATA8)
+        PM_POP_SYNC(13)
+        PM_POP(13, ICPLB_DATA7)
+        PM_POP(12, ICPLB_DATA6)
+        PM_POP(11, ICPLB_DATA5)
+        PM_POP(10, ICPLB_DATA4)
+        PM_POP(9, ICPLB_DATA3)
+        PM_POP(8, ICPLB_DATA2)
+        PM_POP(7, ICPLB_DATA1)
+        PM_POP(6, ICPLB_DATA0)
+        /* ICPLB Addr */
+        FP = I3;
+        PM_POP(5, ICPLB_ADDR15)
+        PM_POP(4, ICPLB_ADDR14)
+        PM_POP(3, ICPLB_ADDR13)
+        PM_POP(2, ICPLB_ADDR12)
+        PM_POP(1, ICPLB_ADDR11)
+        PM_POP(0, ICPLB_ADDR10)
+        PM_POP_SYNC(13)
+        PM_POP(13, ICPLB_ADDR9)
+        PM_POP(12, ICPLB_ADDR8)
+        PM_POP(11, ICPLB_ADDR7)
+        PM_POP(10, ICPLB_ADDR6)
+        PM_POP(9, ICPLB_ADDR5)
+        PM_POP(8, ICPLB_ADDR4)
+        PM_POP(7, ICPLB_ADDR3)
+        PM_POP(6, ICPLB_ADDR2)
+        PM_POP(5, ICPLB_ADDR1)
+        PM_POP(4, ICPLB_ADDR0)
+        /* DCPLB Data */
+        FP = I2;
+        PM_POP(3, DCPLB_DATA15)
+        PM_POP(2, DCPLB_DATA14)
+        PM_POP(1, DCPLB_DATA13)
+        PM_POP(0, DCPLB_DATA12)
+        PM_POP_SYNC(13)
+        PM_POP(13, DCPLB_DATA11)
+        PM_POP(12, DCPLB_DATA10)
+        PM_POP(11, DCPLB_DATA9)
+        PM_POP(10, DCPLB_DATA8)
+        PM_POP(9, DCPLB_DATA7)
+        PM_POP(8, DCPLB_DATA6)
+        PM_POP(7, DCPLB_DATA5)
+        PM_POP(6, DCPLB_DATA4)
+        PM_POP(5, DCPLB_DATA3)
+        PM_POP(4, DCPLB_DATA2)
+        PM_POP(3, DCPLB_DATA1)
+        PM_POP(2, DCPLB_DATA0)
+        /* DCPLB Addr */
+        FP = I1;
+        PM_POP(1, DCPLB_ADDR15)
+        PM_POP(0, DCPLB_ADDR14)
+        PM_POP_SYNC(13)
+        PM_POP(13, DCPLB_ADDR13)
+        PM_POP(12, DCPLB_ADDR12)
+        PM_POP(11, DCPLB_ADDR11)
+        PM_POP(10, DCPLB_ADDR10)
+        PM_POP(9, DCPLB_ADDR9)
+        PM_POP(8, DCPLB_ADDR8)
+        PM_POP(7, DCPLB_ADDR7)
+        PM_POP(6, DCPLB_ADDR6)
+        PM_POP(5, DCPLB_ADDR5)
+        PM_POP(4, DCPLB_ADDR4)
+        PM_POP(3, DCPLB_ADDR3)
+        PM_POP(2, DCPLB_ADDR2)
+        PM_POP(1, DCPLB_ADDR1)
+        PM_POP(0, DCPLB_ADDR0)
+        /* Misc non-contiguous registers */
+        /* icache & dcache will enable later 
+           drop IMEM_CONTROL, DMEM_CONTROL pop
+        */
+        FP = I0;
+        PM_POP_SYNC(2)
+        PM_CORE_POP(2, TBUFCTL)
+        PM_CORE_POP(1, IMEM_CONTROL)
+        PM_CORE_POP(0, DMEM_CONTROL)
+        /* Core Timer */
+        FP = B3;
+        R0 = 0x1;
+        [FP - 0xC] = R0;
+        PM_POP_SYNC(13)
+        FP = B3;
+        PM_POP(13, TCOUNT)
+        PM_POP(12, TSCALE)
+        PM_POP(11, TPERIOD)
+        PM_POP(10, TCNTL)
+        /* CEC */
+        FP = B2;
+        PM_POP(9, IPRIO)
+        PM_POP(8, ILAT)
+        FP += -4;       /* IPEND */
+        PM_POP(7, IMASK)
+        /* Event Vectors */
+        FP = B1;
+        PM_POP(6, EVT15)
+        PM_POP(5, EVT14)
+        PM_POP(4, EVT13)
+        PM_POP(3, EVT12)
+        PM_POP(2, EVT11)
+        PM_POP(1, EVT10)
+        PM_POP(0, EVT9)
+        PM_POP_SYNC(5)
+        PM_POP(5, EVT8)
+        PM_POP(4, EVT7)
+        PM_POP(3, EVT6)
+        PM_POP(2, EVT5)
+        FP += -4;       /* EVT4 */
+        PM_POP(1, EVT3)
+        PM_POP(0, EVT2)
+        .endm
+#endif
 #include <mach/pll.h>
 /* PLL_CTL Masks */
@@ -98,6 +743,16 @@
 #define VLEV_130                0x00F0  /* VLEV = 1.30 V (-5% - +10% Accuracy) */
 #endif
+#ifdef CONFIG_BF60x
+#define PA15WE                  0x00000001 /* Allow Wake-Up from PA15 */
+#define PB15WE                  0x00000002 /* Allow Wake-Up from PB15 */
+#define PC15WE                  0x00000004 /* Allow Wake-Up from PC15 */
+#define PD06WE                  0x00000008 /* Allow Wake-Up from PD06(ETH0_PHYINT) */
+#define PE12WE                  0x00000010 /* Allow Wake-Up from PE12(ETH1_PHYINT, PUSH BUTTON) */
+#define PG04WE                  0x00000020 /* Allow Wake-Up from PG04(CAN0_RX) */
+#define PG13WE                  0x00000040 /* Allow Wake-Up from PG13 */
+#define USBWE                   0x00000080 /* Allow Wake-Up from (USB) */
+#else
 #define WAKE                    0x0100  /* Enable RTC/Reset Wakeup From Hibernate */
 #define CANWE                   0x0200  /* Enable CAN Wakeup From Hibernate */
 #define PHYWE                   0x0400  /* Enable PHY Wakeup From Hibernate */
@@ -113,6 +768,7 @@
 #else
 #define USBWE                   0x0800  /* Enable USB Wakeup From Hibernate */
 #endif
+#endif
 #ifndef __ASSEMBLY__
diff --git a/arch/blackfin/include/asm/fixed_code.h b/arch/blackfin/include/asm/fixed_code.h
index 73fe53e7fd24..5395088b2d0e 100644
--- a/arch/blackfin/include/asm/fixed_code.h
+++ b/arch/blackfin/include/asm/fixed_code.h
@@ -29,24 +29,28 @@ extern void sigreturn_stub(void);
 #endif
 #endif
-#define FIXED_CODE_START        0x400
+#ifndef CONFIG_PHY_RAM_BASE_ADDRESS
+#define CONFIG_PHY_RAM_BASE_ADDRESS     0x0
+#endif
+#define FIXED_CODE_START        (CONFIG_PHY_RAM_BASE_ADDRESS + 0x400)
-#define SIGRETURN_STUB          0x400
+#define SIGRETURN_STUB          (CONFIG_PHY_RAM_BASE_ADDRESS + 0x400)
-#define ATOMIC_SEQS_START       0x410
+#define ATOMIC_SEQS_START       (CONFIG_PHY_RAM_BASE_ADDRESS + 0x410)
-#define ATOMIC_XCHG32           0x410
+#define ATOMIC_XCHG32           (CONFIG_PHY_RAM_BASE_ADDRESS + 0x410)
-#define ATOMIC_CAS32            0x420
+#define ATOMIC_CAS32            (CONFIG_PHY_RAM_BASE_ADDRESS + 0x420)
-#define ATOMIC_ADD32            0x430
+#define ATOMIC_ADD32            (CONFIG_PHY_RAM_BASE_ADDRESS + 0x430)
-#define ATOMIC_SUB32            0x440
+#define ATOMIC_SUB32            (CONFIG_PHY_RAM_BASE_ADDRESS + 0x440)
-#define ATOMIC_IOR32            0x450
+#define ATOMIC_IOR32            (CONFIG_PHY_RAM_BASE_ADDRESS + 0x450)
-#define ATOMIC_AND32            0x460
+#define ATOMIC_AND32            (CONFIG_PHY_RAM_BASE_ADDRESS + 0x460)
-#define ATOMIC_XOR32            0x470
+#define ATOMIC_XOR32            (CONFIG_PHY_RAM_BASE_ADDRESS + 0x470)
-#define ATOMIC_SEQS_END         0x480
+#define ATOMIC_SEQS_END         (CONFIG_PHY_RAM_BASE_ADDRESS + 0x480)
-#define SAFE_USER_INSTRUCTION   0x480
+#define SAFE_USER_INSTRUCTION   (CONFIG_PHY_RAM_BASE_ADDRESS + 0x480)
-#define FIXED_CODE_END          0x490
+#define FIXED_CODE_END          (CONFIG_PHY_RAM_BASE_ADDRESS + 0x490)
 #endif
diff --git a/arch/blackfin/include/asm/gpio.h b/arch/blackfin/include/asm/gpio.h
index 12d3571b5232..3d84d96f7c2c 100644
--- a/arch/blackfin/include/asm/gpio.h
+++ b/arch/blackfin/include/asm/gpio.h
@@ -26,6 +26,7 @@
 #ifndef __ASSEMBLY__
 #include <linux/compiler.h>
+#include <linux/gpio.h>
 /***********************************************************
 *
@@ -244,6 +245,49 @@ static inline int gpio_set_debounce(unsigned gpio, unsigned debounce)
        return -EINVAL;
 }
+static inline int gpio_request_one(unsigned gpio, unsigned long flags, const char *label)
+{
+        int err;
+        err = bfin_gpio_request(gpio, label);
+        if (err)
+                return err;
+        if (flags & GPIOF_DIR_IN)
+                err = bfin_gpio_direction_input(gpio);
+        else
+                err = bfin_gpio_direction_output(gpio,
+                        (flags & GPIOF_INIT_HIGH) ? 1 : 0);
+        if (err)
+                bfin_gpio_free(gpio);
+        return err;
+}
+static inline int gpio_request_array(const struct gpio *array, size_t num)
+{
+        int i, err;
+        for (i = 0; i < num; i++, array++) {
+                err = gpio_request_one(array->gpio, array->flags, array->label);
+                if (err)
+                        goto err_free;
+        }
+        return 0;
+err_free:
+        while (i--)
+                bfin_gpio_free((--array)->gpio);
+        return err;
+}
+static inline void gpio_free_array(const struct gpio *array, size_t num)
+{
+        while (num--)
+                bfin_gpio_free((array++)->gpio);
+}
 static inline int __gpio_get_value(unsigned gpio)
 {
        return bfin_gpio_get_value(gpio);
diff --git a/arch/blackfin/include/asm/gptimers.h b/arch/blackfin/include/asm/gptimers.h
index 38bddcb190c8..381e3d621a4c 100644
--- a/arch/blackfin/include/asm/gptimers.h
+++ b/arch/blackfin/include/asm/gptimers.h
@@ -44,6 +44,13 @@
 # define TIMER_GROUP2          1
 #endif
 /*
+ * BF609: 8 timers:
+ */
+#if defined(CONFIG_BF60x)
+# define MAX_BLACKFIN_GPTIMERS 8
+# define TIMER0_GROUP_REG     TIMER_RUN
+#endif
+/*
 * All others: 3 timers:
 */
 #define TIMER_GROUP1           0
@@ -104,6 +111,72 @@
 # define FS2_TIMER_BIT TIMER1bit
 #endif
+#ifdef CONFIG_BF60x
+/*
+ * Timer Configuration Register Bits
+ */
+#define TIMER_EMU_RUN       0x8000
+#define TIMER_BPER_EN       0x4000
+#define TIMER_BWID_EN       0x2000
+#define TIMER_BDLY_EN       0x1000
+#define TIMER_OUT_DIS       0x0800
+#define TIMER_TIN_SEL       0x0400
+#define TIMER_CLK_SEL       0x0300
+#define TIMER_CLK_SCLK      0x0000
+#define TIMER_CLK_ALT_CLK0  0x0100
+#define TIMER_CLK_ALT_CLK1  0x0300
+#define TIMER_PULSE_HI      0x0080
+#define TIMER_SLAVE_TRIG    0x0040
+#define TIMER_IRQ_MODE      0x0030
+#define TIMER_IRQ_ACT_EDGE  0x0000
+#define TIMER_IRQ_DLY       0x0010
+#define TIMER_IRQ_WID_DLY   0x0020
+#define TIMER_IRQ_PER       0x0030
+#define TIMER_MODE          0x000f
+#define TIMER_MODE_WDOG_P   0x0008
+#define TIMER_MODE_WDOG_W   0x0009
+#define TIMER_MODE_PWM_CONT 0x000c
+#define TIMER_MODE_PWM      0x000d
+#define TIMER_MODE_WDTH     0x000a
+#define TIMER_MODE_WDTH_D   0x000b
+#define TIMER_MODE_EXT_CLK  0x000e
+#define TIMER_MODE_PININT   0x000f
+/*
+ * Timer Status Register Bits
+ */
+#define TIMER_STATUS_TIMIL0  0x0001
+#define TIMER_STATUS_TIMIL1  0x0002
+#define TIMER_STATUS_TIMIL2  0x0004
+#define TIMER_STATUS_TIMIL3  0x0008
+#define TIMER_STATUS_TIMIL4  0x0010
+#define TIMER_STATUS_TIMIL5  0x0020
+#define TIMER_STATUS_TIMIL6  0x0040
+#define TIMER_STATUS_TIMIL7  0x0080
+#define TIMER_STATUS_TOVF0   0x0001     /* timer 0 overflow error */
+#define TIMER_STATUS_TOVF1   0x0002
+#define TIMER_STATUS_TOVF2   0x0004
+#define TIMER_STATUS_TOVF3   0x0008
+#define TIMER_STATUS_TOVF4   0x0010
+#define TIMER_STATUS_TOVF5   0x0020
+#define TIMER_STATUS_TOVF6   0x0040
+#define TIMER_STATUS_TOVF7   0x0080
+/*
+ * Timer Slave Enable Status : write 1 to clear
+ */
+#define TIMER_STATUS_TRUN0  0x0001
+#define TIMER_STATUS_TRUN1  0x0002
+#define TIMER_STATUS_TRUN2  0x0004
+#define TIMER_STATUS_TRUN3  0x0008
+#define TIMER_STATUS_TRUN4  0x0010
+#define TIMER_STATUS_TRUN5  0x0020
+#define TIMER_STATUS_TRUN6  0x0040
+#define TIMER_STATUS_TRUN7  0x0080
+#else
 /*
 * Timer Configuration Register Bits
 */
@@ -170,12 +243,18 @@
 #define TIMER_STATUS_TRUN10 0x4000
 #define TIMER_STATUS_TRUN11 0x8000
+#endif
 /* The actual gptimer API */
 void     set_gptimer_pwidth(unsigned int timer_id, uint32_t width);
 uint32_t get_gptimer_pwidth(unsigned int timer_id);
 void     set_gptimer_period(unsigned int timer_id, uint32_t period);
 uint32_t get_gptimer_period(unsigned int timer_id);
+#ifdef CONFIG_BF60x
+void     set_gptimer_delay(unsigned int timer_id, uint32_t delay);
+uint32_t get_gptimer_delay(unsigned int timer_id);
+#endif
 uint32_t get_gptimer_count(unsigned int timer_id);
 int      get_gptimer_intr(unsigned int timer_id);
 void     clear_gptimer_intr(unsigned int timer_id);
@@ -217,16 +296,41 @@ struct bfin_gptimer_regs {
        u32 counter;
        u32 period;
        u32 width;
+#ifdef CONFIG_BF60x
+        u32 delay;
+#endif
 };
 /*
 * bfin group timer registers layout
 */
+#ifndef CONFIG_BF60x
 struct bfin_gptimer_group_regs {
        __BFP(enable);
        __BFP(disable);
        u32 status;
 };
+#else
+struct bfin_gptimer_group_regs {
+        __BFP(run);
+        __BFP(enable);
+        __BFP(disable);
+        __BFP(stop_cfg);
+        __BFP(stop_cfg_set);
+        __BFP(stop_cfg_clr);
+        __BFP(data_imsk);
+        __BFP(stat_imsk);
+        __BFP(tr_msk);
+        __BFP(tr_ie);
+        __BFP(data_ilat);
+        __BFP(stat_ilat);
+        __BFP(err_status);
+        __BFP(bcast_per);
+        __BFP(bcast_wid);
+        __BFP(bcast_dly);
+};
+#endif
 #undef __BFP
diff --git a/arch/blackfin/include/asm/irqflags.h b/arch/blackfin/include/asm/irqflags.h
index 43eb4749de3d..07aff230a812 100644
--- a/arch/blackfin/include/asm/irqflags.h
+++ b/arch/blackfin/include/asm/irqflags.h
@@ -67,7 +67,11 @@ static inline notrace unsigned long __hard_local_irq_save(void)
 static inline notrace int hard_irqs_disabled_flags(unsigned long flags)
 {
+#ifdef CONFIG_BF60x
+        return (flags & IMASK_IVG11) == 0;
+#else
        return (flags & ~0x3f) == 0;
+#endif
 }
 static inline notrace int hard_irqs_disabled(void)
@@ -224,7 +228,7 @@ static inline notrace void hard_local_irq_restore(unsigned long flags)
 * Direct interface to linux/irqflags.h.
 */
 #define arch_local_save_flags()         hard_local_save_flags()
-#define arch_local_irq_save(flags)      __hard_local_irq_save()
+#define arch_local_irq_save()           __hard_local_irq_save()
 #define arch_local_irq_restore(flags)   __hard_local_irq_restore(flags)
 #define arch_local_irq_enable()         __hard_local_irq_enable()
 #define arch_local_irq_disable()        __hard_local_irq_disable()
diff --git a/arch/blackfin/include/asm/page.h b/arch/blackfin/include/asm/page.h
index 7202404966f6..b93474d5be75 100644
--- a/arch/blackfin/include/asm/page.h
+++ b/arch/blackfin/include/asm/page.h
@@ -7,14 +7,15 @@
 #ifndef _BLACKFIN_PAGE_H
 #define _BLACKFIN_PAGE_H
-#include <asm-generic/page.h>
+#define ARCH_PFN_OFFSET (CONFIG_PHY_RAM_BASE_ADDRESS >> PAGE_SHIFT)
-#define MAP_NR(addr) (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT)
+#define MAP_NR(addr) ((unsigned long)(addr) >> PAGE_SHIFT)
 #define VM_DATA_DEFAULT_FLAGS \
        (VM_READ | VM_WRITE | \
        ((current->personality & READ_IMPLIES_EXEC) ? VM_EXEC : 0 ) | \
                 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
+#include <asm-generic/page.h>
 #include <asm-generic/memory_model.h>
 #include <asm-generic/getorder.h>
diff --git a/arch/blackfin/include/asm/pda.h b/arch/blackfin/include/asm/pda.h
index 28c2498c9c98..68d6f6618f2a 100644
--- a/arch/blackfin/include/asm/pda.h
+++ b/arch/blackfin/include/asm/pda.h
@@ -13,7 +13,9 @@
 #ifndef __ASSEMBLY__
 struct blackfin_pda {                   /* Per-processor Data Area */
+#ifdef CONFIG_SMP
        struct blackfin_pda *next;
+#endif
        unsigned long syscfg;
 #ifdef CONFIG_SMP
diff --git a/arch/blackfin/include/asm/pm.h b/arch/blackfin/include/asm/pm.h
new file mode 100644
index 000000000000..f72239bf3638
--- /dev/null
+++ b/arch/blackfin/include/asm/pm.h
@@ -0,0 +1,31 @@
+/*
+ * Blackfin bf609 power management
+ *
+ * Copyright 2011 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2
+ */
+#ifndef __PM_H__
+#define __PM_H__
+#include <linux/suspend.h>
+struct bfin_cpu_pm_fns {
+        void    (*save)(unsigned long *);
+        void    (*restore)(unsigned long *);
+        int     (*valid)(suspend_state_t state);
+        void    (*enter)(suspend_state_t state);
+        int     (*prepare)(void);
+        void    (*finish)(void);
+};
+extern struct bfin_cpu_pm_fns *bfin_cpu_pm;
+# ifdef CONFIG_BFIN_COREB
+void bfin_coreb_start(void);
+void bfin_coreb_stop(void);
+void bfin_coreb_reset(void);
+# endif
+#endif
diff --git a/arch/blackfin/include/asm/unistd.h b/arch/blackfin/include/asm/unistd.h
index 75ec9df5318b..3287222cba34 100644
--- a/arch/blackfin/include/asm/unistd.h
+++ b/arch/blackfin/include/asm/unistd.h
@@ -11,7 +11,7 @@
 */
 #define __NR_restart_syscall      0
 #define __NR_exit                 1
-#define __NR_fork                 2
+                                /* 2 __NR_fork not supported on nommu */
 #define __NR_read                 3
 #define __NR_write                4
 #define __NR_open                 5
diff --git a/arch/blackfin/kernel/Makefile b/arch/blackfin/kernel/Makefile
index 9a0d6d706443..08e6625106be 100644
--- a/arch/blackfin/kernel/Makefile
+++ b/arch/blackfin/kernel/Makefile
@@ -2,7 +2,7 @@
 # arch/blackfin/kernel/Makefile
 #
-extra-y := init_task.o vmlinux.lds
+extra-y := vmlinux.lds
 obj-y := \
        entry.o process.o bfin_ksyms.o ptrace.o setup.o signal.o \
diff --git a/arch/blackfin/kernel/bfin_dma.c b/arch/blackfin/kernel/bfin_dma.c
index 40c2ed61258e..c166939ffb2b 100644
--- a/arch/blackfin/kernel/bfin_dma.c
+++ b/arch/blackfin/kernel/bfin_dma.c
@@ -45,9 +45,15 @@ static int __init blackfin_dma_init(void)
                atomic_set(&dma_ch[i].chan_status, 0);
                dma_ch[i].regs = dma_io_base_addr[i];
        }
+#ifdef CH_MEM_STREAM3_SRC
+        /* Mark MEMDMA Channel 3 as requested since we're using it internally */
+        request_dma(CH_MEM_STREAM3_DEST, "Blackfin dma_memcpy");
+        request_dma(CH_MEM_STREAM3_SRC, "Blackfin dma_memcpy");
+#else
        /* Mark MEMDMA Channel 0 as requested since we're using it internally */
        request_dma(CH_MEM_STREAM0_DEST, "Blackfin dma_memcpy");
        request_dma(CH_MEM_STREAM0_SRC, "Blackfin dma_memcpy");
+#endif
 #if defined(CONFIG_DEB_DMA_URGENT)
        bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE()
@@ -84,7 +90,8 @@ static const struct file_operations proc_dma_operations = {
 static int __init proc_dma_init(void)
 {
-        return proc_create("dma", 0, NULL, &proc_dma_operations) != NULL;
+        proc_create("dma", 0, NULL, &proc_dma_operations);
+        return 0;
 }
 late_initcall(proc_dma_init);
 #endif
@@ -204,6 +211,7 @@ EXPORT_SYMBOL(free_dma);
 # ifndef MAX_DMA_SUSPEND_CHANNELS
 #  define MAX_DMA_SUSPEND_CHANNELS MAX_DMA_CHANNELS
 # endif
+# ifndef CONFIG_BF60x
 int blackfin_dma_suspend(void)
 {
        int i;
@@ -213,7 +221,6 @@ int blackfin_dma_suspend(void)
                        printk(KERN_ERR "DMA Channel %d failed to suspend\n", i);
                        return -EBUSY;
                }
                if (i < MAX_DMA_SUSPEND_CHANNELS)
                        dma_ch[i].saved_peripheral_map = dma_ch[i].regs->peripheral_map;
        }
@@ -230,7 +237,6 @@ void blackfin_dma_resume(void)
        for (i = 0; i < MAX_DMA_CHANNELS; ++i) {
                dma_ch[i].regs->cfg = 0;
                if (i < MAX_DMA_SUSPEND_CHANNELS)
                        dma_ch[i].regs->peripheral_map = dma_ch[i].saved_peripheral_map;
        }
@@ -238,6 +244,16 @@ void blackfin_dma_resume(void)
        bfin_write_DMAC_TC_PER(0x0111);
 #endif
 }
+# else
+int blackfin_dma_suspend(void)
+{
+        return 0;
+}
+void blackfin_dma_resume(void)
+{
+}
+#endif
 #endif
 /**
@@ -279,10 +295,10 @@ void __init early_dma_memcpy(void *pdst, const void *psrc, size_t size)
                        src_ch = (struct dma_register *)MDMA_S0_NEXT_DESC_PTR;
                }
-                if (!bfin_read16(&src_ch->cfg))
+                if (!DMA_MMR_READ(&src_ch->cfg))
                        break;
-                else if (bfin_read16(&dst_ch->irq_status) & DMA_DONE) {
+                else if (DMA_MMR_READ(&dst_ch->irq_status) & DMA_DONE) {
-                        bfin_write16(&src_ch->cfg, 0);
+                        DMA_MMR_WRITE(&src_ch->cfg, 0);
                        break;
                }
        }
@@ -295,22 +311,31 @@ void __init early_dma_memcpy(void *pdst, const void *psrc, size_t size)
        /* Destination */
        bfin_write32(&dst_ch->start_addr, dst);
-        bfin_write16(&dst_ch->x_count, size >> 2);
+        DMA_MMR_WRITE(&dst_ch->x_count, size >> 2);
-        bfin_write16(&dst_ch->x_modify, 1 << 2);
+        DMA_MMR_WRITE(&dst_ch->x_modify, 1 << 2);
-        bfin_write16(&dst_ch->irq_status, DMA_DONE | DMA_ERR);
+        DMA_MMR_WRITE(&dst_ch->irq_status, DMA_DONE | DMA_ERR);
        /* Source */
        bfin_write32(&src_ch->start_addr, src);
-        bfin_write16(&src_ch->x_count, size >> 2);
+        DMA_MMR_WRITE(&src_ch->x_count, size >> 2);
-        bfin_write16(&src_ch->x_modify, 1 << 2);
+        DMA_MMR_WRITE(&src_ch->x_modify, 1 << 2);
-        bfin_write16(&src_ch->irq_status, DMA_DONE | DMA_ERR);
+        DMA_MMR_WRITE(&src_ch->irq_status, DMA_DONE | DMA_ERR);
        /* Enable */
-        bfin_write16(&src_ch->cfg, DMAEN | WDSIZE_32);
+        DMA_MMR_WRITE(&src_ch->cfg, DMAEN | WDSIZE_32);
-        bfin_write16(&dst_ch->cfg, WNR | DI_EN | DMAEN | WDSIZE_32);
+        DMA_MMR_WRITE(&dst_ch->cfg, WNR | DI_EN_X | DMAEN | WDSIZE_32);
        /* Since we are atomic now, don't use the workaround ssync */
        __builtin_bfin_ssync();
+#ifdef CONFIG_BF60x
+        /* Work around a possible MDMA anomaly. Running 2 MDMA channels to
+         * transfer DDR data to L1 SRAM may corrupt data.
+         * Should be reverted after this issue is root caused.
+         */
+        while (!(DMA_MMR_READ(&dst_ch->irq_status) & DMA_DONE))
+                continue;
+#endif
 }
 void __init early_dma_memcpy_done(void)
@@ -336,6 +361,42 @@ void __init early_dma_memcpy_done(void)
        __builtin_bfin_ssync();
 }
+#ifdef CH_MEM_STREAM3_SRC
+#define bfin_read_MDMA_S_CONFIG bfin_read_MDMA_S3_CONFIG
+#define bfin_write_MDMA_S_CONFIG bfin_write_MDMA_S3_CONFIG
+#define bfin_write_MDMA_S_START_ADDR bfin_write_MDMA_S3_START_ADDR
+#define bfin_write_MDMA_S_IRQ_STATUS bfin_write_MDMA_S3_IRQ_STATUS
+#define bfin_write_MDMA_S_X_COUNT bfin_write_MDMA_S3_X_COUNT
+#define bfin_write_MDMA_S_X_MODIFY bfin_write_MDMA_S3_X_MODIFY
+#define bfin_write_MDMA_S_Y_COUNT bfin_write_MDMA_S3_Y_COUNT
+#define bfin_write_MDMA_S_Y_MODIFY bfin_write_MDMA_S3_Y_MODIFY
+#define bfin_write_MDMA_D_CONFIG bfin_write_MDMA_D3_CONFIG
+#define bfin_write_MDMA_D_START_ADDR bfin_write_MDMA_D3_START_ADDR
+#define bfin_read_MDMA_D_IRQ_STATUS bfin_read_MDMA_D3_IRQ_STATUS
+#define bfin_write_MDMA_D_IRQ_STATUS bfin_write_MDMA_D3_IRQ_STATUS
+#define bfin_write_MDMA_D_X_COUNT bfin_write_MDMA_D3_X_COUNT
+#define bfin_write_MDMA_D_X_MODIFY bfin_write_MDMA_D3_X_MODIFY
+#define bfin_write_MDMA_D_Y_COUNT bfin_write_MDMA_D3_Y_COUNT
+#define bfin_write_MDMA_D_Y_MODIFY bfin_write_MDMA_D3_Y_MODIFY
+#else
+#define bfin_read_MDMA_S_CONFIG bfin_read_MDMA_S0_CONFIG
+#define bfin_write_MDMA_S_CONFIG bfin_write_MDMA_S0_CONFIG
+#define bfin_write_MDMA_S_START_ADDR bfin_write_MDMA_S0_START_ADDR
+#define bfin_write_MDMA_S_IRQ_STATUS bfin_write_MDMA_S0_IRQ_STATUS
+#define bfin_write_MDMA_S_X_COUNT bfin_write_MDMA_S0_X_COUNT
+#define bfin_write_MDMA_S_X_MODIFY bfin_write_MDMA_S0_X_MODIFY
+#define bfin_write_MDMA_S_Y_COUNT bfin_write_MDMA_S0_Y_COUNT
+#define bfin_write_MDMA_S_Y_MODIFY bfin_write_MDMA_S0_Y_MODIFY
+#define bfin_write_MDMA_D_CONFIG bfin_write_MDMA_D0_CONFIG
+#define bfin_write_MDMA_D_START_ADDR bfin_write_MDMA_D0_START_ADDR
+#define bfin_read_MDMA_D_IRQ_STATUS bfin_read_MDMA_D0_IRQ_STATUS
+#define bfin_write_MDMA_D_IRQ_STATUS bfin_write_MDMA_D0_IRQ_STATUS
+#define bfin_write_MDMA_D_X_COUNT bfin_write_MDMA_D0_X_COUNT
+#define bfin_write_MDMA_D_X_MODIFY bfin_write_MDMA_D0_X_MODIFY
+#define bfin_write_MDMA_D_Y_COUNT bfin_write_MDMA_D0_Y_COUNT
+#define bfin_write_MDMA_D_Y_MODIFY bfin_write_MDMA_D0_Y_MODIFY
+#endif
 /**
 *      __dma_memcpy - program the MDMA registers
 *
@@ -358,8 +419,8 @@ static void __dma_memcpy(u32 daddr, s16 dmod, u32 saddr, s16 smod, size_t cnt, u
         */
        __builtin_bfin_ssync();
-        if (bfin_read_MDMA_S0_CONFIG())
+        if (bfin_read_MDMA_S_CONFIG())
-                while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE))
+                while (!(bfin_read_MDMA_D_IRQ_STATUS() & DMA_DONE))
                        continue;
        if (conf & DMA2D) {
@@ -374,39 +435,42 @@ static void __dma_memcpy(u32 daddr, s16 dmod, u32 saddr, s16 smod, size_t cnt, u
                u32 shift = abs(dmod) >> 1;
                size_t ycnt = cnt >> (16 - shift);
                cnt = 1 << (16 - shift);
-                bfin_write_MDMA_D0_Y_COUNT(ycnt);
+                bfin_write_MDMA_D_Y_COUNT(ycnt);
-                bfin_write_MDMA_S0_Y_COUNT(ycnt);
+                bfin_write_MDMA_S_Y_COUNT(ycnt);
-                bfin_write_MDMA_D0_Y_MODIFY(dmod);
+                bfin_write_MDMA_D_Y_MODIFY(dmod);
-                bfin_write_MDMA_S0_Y_MODIFY(smod);
+                bfin_write_MDMA_S_Y_MODIFY(smod);
        }
-        bfin_write_MDMA_D0_START_ADDR(daddr);
+        bfin_write_MDMA_D_START_ADDR(daddr);
-        bfin_write_MDMA_D0_X_COUNT(cnt);
+        bfin_write_MDMA_D_X_COUNT(cnt);
-        bfin_write_MDMA_D0_X_MODIFY(dmod);
+        bfin_write_MDMA_D_X_MODIFY(dmod);
-        bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
+        bfin_write_MDMA_D_IRQ_STATUS(DMA_DONE | DMA_ERR);
-        bfin_write_MDMA_S0_START_ADDR(saddr);
+        bfin_write_MDMA_S_START_ADDR(saddr);
-        bfin_write_MDMA_S0_X_COUNT(cnt);
+        bfin_write_MDMA_S_X_COUNT(cnt);
-        bfin_write_MDMA_S0_X_MODIFY(smod);
+        bfin_write_MDMA_S_X_MODIFY(smod);
-        bfin_write_MDMA_S0_IRQ_STATUS(DMA_DONE | DMA_ERR);
+        bfin_write_MDMA_S_IRQ_STATUS(DMA_DONE | DMA_ERR);
-        bfin_write_MDMA_S0_CONFIG(DMAEN | conf);
+        bfin_write_MDMA_S_CONFIG(DMAEN | conf);
-        bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | conf);
+        if (conf & DMA2D)
+                bfin_write_MDMA_D_CONFIG(WNR | DI_EN_Y | DMAEN | conf);
+        else
+                bfin_write_MDMA_D_CONFIG(WNR | DI_EN_X | DMAEN | conf);
        spin_unlock_irqrestore(&mdma_lock, flags);
        SSYNC();
-        while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE))
+        while (!(bfin_read_MDMA_D_IRQ_STATUS() & DMA_DONE))
-                if (bfin_read_MDMA_S0_CONFIG())
+                if (bfin_read_MDMA_S_CONFIG())
                        continue;
                else
                        return;
-        bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
+        bfin_write_MDMA_D_IRQ_STATUS(DMA_DONE | DMA_ERR);
-        bfin_write_MDMA_S0_CONFIG(0);
+        bfin_write_MDMA_S_CONFIG(0);
-        bfin_write_MDMA_D0_CONFIG(0);
+        bfin_write_MDMA_D_CONFIG(0);
 }
 /**
@@ -448,8 +512,10 @@ static void *_dma_memcpy(void *pdst, const void *psrc, size_t size)
        }
        size >>= shift;
+#ifndef DMA_MMR_SIZE_32
        if (size > 0x10000)
                conf |= DMA2D;
+#endif
        __dma_memcpy(dst, mod, src, mod, size, conf);
@@ -488,6 +554,9 @@ EXPORT_SYMBOL(dma_memcpy);
 */
 void *dma_memcpy_nocache(void *pdst, const void *psrc, size_t size)
 {
+#ifdef DMA_MMR_SIZE_32
+        _dma_memcpy(pdst, psrc, size);
+#else
        size_t bulk, rest;
        bulk = size & ~0xffff;
@@ -495,6 +564,7 @@ void *dma_memcpy_nocache(void *pdst, const void *psrc, size_t size)
        if (bulk)
                _dma_memcpy(pdst, psrc, bulk);
        _dma_memcpy(pdst + bulk, psrc + bulk, rest);
+#endif
        return pdst;
 }
 EXPORT_SYMBOL(dma_memcpy_nocache);
@@ -514,14 +584,14 @@ void *safe_dma_memcpy(void *dst, const void *src, size_t size)
 }
 EXPORT_SYMBOL(safe_dma_memcpy);
-static void _dma_out(unsigned long addr, unsigned long buf, unsigned short len,
+static void _dma_out(unsigned long addr, unsigned long buf, unsigned DMA_MMR_SIZE_TYPE len,
                     u16 size, u16 dma_size)
 {
        blackfin_dcache_flush_range(buf, buf + len * size);
        __dma_memcpy(addr, 0, buf, size, len, dma_size);
 }
-static void _dma_in(unsigned long addr, unsigned long buf, unsigned short len,
+static void _dma_in(unsigned long addr, unsigned long buf, unsigned DMA_MMR_SIZE_TYPE len,
                    u16 size, u16 dma_size)
 {
        blackfin_dcache_invalidate_range(buf, buf + len * size);
@@ -529,7 +599,7 @@ static void _dma_in(unsigned long addr, unsigned long buf, unsigned short len,
 }
 #define MAKE_DMA_IO(io, bwl, isize, dmasize, cnst) \
-void dma_##io##s##bwl(unsigned long addr, cnst void *buf, unsigned short len) \
+void dma_##io##s##bwl(unsigned long addr, cnst void *buf, unsigned DMA_MMR_SIZE_TYPE len) \
 { \
        _dma_##io(addr, (unsigned long)buf, len, isize, WDSIZE_##dmasize); \
 } \
diff --git a/arch/blackfin/kernel/bfin_gpio.c b/arch/blackfin/kernel/bfin_gpio.c
index 02796b88443d..83139aaf3072 100644
--- a/arch/blackfin/kernel/bfin_gpio.c
+++ b/arch/blackfin/kernel/bfin_gpio.c
@@ -58,7 +58,7 @@ static struct gpio_port_t * const gpio_array[] = {
        (struct gpio_port_t *) FIO0_FLAG_D,
        (struct gpio_port_t *) FIO1_FLAG_D,
        (struct gpio_port_t *) FIO2_FLAG_D,
-#elif defined(CONFIG_BF54x)
+#elif defined(CONFIG_BF54x) || defined(CONFIG_BF60x) 
        (struct gpio_port_t *)PORTA_FER,
        (struct gpio_port_t *)PORTB_FER,
        (struct gpio_port_t *)PORTC_FER,
@@ -66,9 +66,11 @@ static struct gpio_port_t * const gpio_array[] = {
        (struct gpio_port_t *)PORTE_FER,
        (struct gpio_port_t *)PORTF_FER,
        (struct gpio_port_t *)PORTG_FER,
+# if defined(CONFIG_BF54x)
        (struct gpio_port_t *)PORTH_FER,
        (struct gpio_port_t *)PORTI_FER,
        (struct gpio_port_t *)PORTJ_FER,
+# endif
 #else
 # error no gpio arrays defined
 #endif
@@ -210,7 +212,7 @@ static void port_setup(unsigned gpio, unsigned short usage)
        else
                *port_fer[gpio_bank(gpio)] |= gpio_bit(gpio);
        SSYNC();
-#elif defined(CONFIG_BF54x)
+#elif defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
        if (usage == GPIO_USAGE)
                gpio_array[gpio_bank(gpio)]->port_fer &= ~gpio_bit(gpio);
        else
@@ -299,7 +301,7 @@ static void portmux_setup(unsigned short per)
        pmux |= (function << offset);
        bfin_write_PORT_MUX(pmux);
 }
-#elif defined(CONFIG_BF54x)
+#elif defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
 inline void portmux_setup(unsigned short per)
 {
        u16 ident = P_IDENT(per);
@@ -377,7 +379,7 @@ static int portmux_group_check(unsigned short per)
 }
 #endif
-#ifndef CONFIG_BF54x
+#if !(defined(CONFIG_BF54x) || defined(CONFIG_BF60x))
 /***********************************************************
 *
 * FUNCTIONS: Blackfin General Purpose Ports Access Functions
@@ -680,7 +682,7 @@ void bfin_gpio_pm_hibernate_restore(void)
 #endif
-#else /* CONFIG_BF54x */
+#else /* CONFIG_BF54x || CONFIG_BF60x */
 #ifdef CONFIG_PM
 int bfin_pm_standby_ctrl(unsigned ctrl)
@@ -726,7 +728,7 @@ unsigned short get_gpio_dir(unsigned gpio)
 }
 EXPORT_SYMBOL(get_gpio_dir);
-#endif /* CONFIG_BF54x */
+#endif /* CONFIG_BF54x || CONFIG_BF60x */
 /***********************************************************
 *
@@ -783,7 +785,7 @@ int peripheral_request(unsigned short per, const char *label)
                 * be requested and used by several drivers
                 */
-#ifdef CONFIG_BF54x
+#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
                if (!((per & P_MAYSHARE) && get_portmux(per) == P_FUNCT2MUX(per))) {
 #else
                if (!(per & P_MAYSHARE)) {
@@ -937,7 +939,7 @@ int bfin_gpio_request(unsigned gpio, const char *label)
                printk(KERN_NOTICE "bfin-gpio: GPIO %d is already reserved as gpio-irq!"
                       " (Documentation/blackfin/bfin-gpio-notes.txt)\n", gpio);
        }
-#ifndef CONFIG_BF54x
+#if !(defined(CONFIG_BF54x) || defined(CONFIG_BF60x))
        else {  /* Reset POLAR setting when acquiring a gpio for the first time */
                set_gpio_polar(gpio, 0);
        }
@@ -1110,7 +1112,7 @@ void bfin_gpio_irq_free(unsigned gpio)
 static inline void __bfin_gpio_direction_input(unsigned gpio)
 {
-#ifdef CONFIG_BF54x
+#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
        gpio_array[gpio_bank(gpio)]->dir_clear = gpio_bit(gpio);
 #else
        gpio_array[gpio_bank(gpio)]->dir &= ~gpio_bit(gpio);
@@ -1138,13 +1140,13 @@ EXPORT_SYMBOL(bfin_gpio_direction_input);
 void bfin_gpio_irq_prepare(unsigned gpio)
 {
-#ifdef CONFIG_BF54x
+#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
        unsigned long flags;
 #endif
        port_setup(gpio, GPIO_USAGE);
-#ifdef CONFIG_BF54x
+#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
        flags = hard_local_irq_save();
        __bfin_gpio_direction_input(gpio);
        hard_local_irq_restore(flags);
@@ -1173,7 +1175,7 @@ int bfin_gpio_direction_output(unsigned gpio, int value)
        gpio_array[gpio_bank(gpio)]->inen &= ~gpio_bit(gpio);
        gpio_set_value(gpio, value);
-#ifdef CONFIG_BF54x
+#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
        gpio_array[gpio_bank(gpio)]->dir_set = gpio_bit(gpio);
 #else
        gpio_array[gpio_bank(gpio)]->dir |= gpio_bit(gpio);
@@ -1188,7 +1190,7 @@ EXPORT_SYMBOL(bfin_gpio_direction_output);
 int bfin_gpio_get_value(unsigned gpio)
 {
-#ifdef CONFIG_BF54x
+#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
        return (1 & (gpio_array[gpio_bank(gpio)]->data >> gpio_sub_n(gpio)));
 #else
        unsigned long flags;
diff --git a/arch/blackfin/kernel/cplb-nompu/cplbinit.c b/arch/blackfin/kernel/cplb-nompu/cplbinit.c
index 886e00014d75..3e366dc2d6e1 100644
--- a/arch/blackfin/kernel/cplb-nompu/cplbinit.c
+++ b/arch/blackfin/kernel/cplb-nompu/cplbinit.c
@@ -139,7 +139,7 @@ void __init generate_cplb_tables_all(void)
        dcplb_bounds[i_d].eaddr = BOOT_ROM_START;
        dcplb_bounds[i_d++].data = 0;
        /* BootROM -- largest one should be less than 1 meg.  */
-        dcplb_bounds[i_d].eaddr = BOOT_ROM_START + (1 * 1024 * 1024);
+        dcplb_bounds[i_d].eaddr = BOOT_ROM_START + BOOT_ROM_LENGTH;
        dcplb_bounds[i_d++].data = SDRAM_DGENERIC;
        if (L2_LENGTH) {
                /* Addressing hole up to L2 SRAM.  */
@@ -178,7 +178,7 @@ void __init generate_cplb_tables_all(void)
        icplb_bounds[i_i].eaddr = BOOT_ROM_START;
        icplb_bounds[i_i++].data = 0;
        /* BootROM -- largest one should be less than 1 meg.  */
-        icplb_bounds[i_i].eaddr = BOOT_ROM_START + (1 * 1024 * 1024);
+        icplb_bounds[i_i].eaddr = BOOT_ROM_START + BOOT_ROM_LENGTH;
        icplb_bounds[i_i++].data = SDRAM_IGENERIC;
        if (L2_LENGTH) {
diff --git a/arch/blackfin/kernel/cplb-nompu/cplbmgr.c b/arch/blackfin/kernel/cplb-nompu/cplbmgr.c
index 5b88861d6183..e854f9066cbd 100644
--- a/arch/blackfin/kernel/cplb-nompu/cplbmgr.c
+++ b/arch/blackfin/kernel/cplb-nompu/cplbmgr.c
@@ -179,6 +179,12 @@ MGR_ATTR static int dcplb_miss(int cpu)
                addr = addr1;
        }
+#ifdef CONFIG_BF60x
+        if ((addr >= ASYNC_BANK0_BASE)
+                && (addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE))
+                d_data |= PAGE_SIZE_64MB;
+#endif
        /* Pick entry to evict */
        idx = evict_one_dcplb(cpu);
diff --git a/arch/blackfin/kernel/debug-mmrs.c b/arch/blackfin/kernel/debug-mmrs.c
index 92f664826281..01232a13470d 100644
--- a/arch/blackfin/kernel/debug-mmrs.c
+++ b/arch/blackfin/kernel/debug-mmrs.c
@@ -105,6 +105,7 @@ DEFINE_SYSREG(seqstat, , );
 DEFINE_SYSREG(syscfg, , CSYNC());
 #define D_SYSREG(sr) debugfs_create_file(#sr, S_IRUSR|S_IWUSR, parent, NULL, &fops_sysreg_##sr)
+#ifndef CONFIG_BF60x
 /*
 * CAN
 */
@@ -223,8 +224,10 @@ bfin_debug_mmrs_dma(struct dentry *parent, unsigned long base, int num, char mdm
        __DMA(CURR_DESC_PTR, curr_desc_ptr);
        __DMA(CURR_ADDR, curr_addr);
        __DMA(IRQ_STATUS, irq_status);
+#ifndef CONFIG_BF60x
        if (strcmp(pfx, "IMDMA") != 0)
                __DMA(PERIPHERAL_MAP, peripheral_map);
+#endif
        __DMA(CURR_X_COUNT, curr_x_count);
        __DMA(CURR_Y_COUNT, curr_y_count);
 }
@@ -568,7 +571,7 @@ bfin_debug_mmrs_uart(struct dentry *parent, unsigned long base, int num)
 #endif
 }
 #define UART(num) bfin_debug_mmrs_uart(parent, UART##num##_DLL, num)
+#endif /* CONFIG_BF60x */
 /*
 * The actual debugfs generation
 */
@@ -740,7 +743,7 @@ static int __init bfin_debug_mmrs_init(void)
        D32(WPDACNT0);
        D32(WPDACNT1);
        D32(WPSTAT);
+#ifndef CONFIG_BF60x
        /* System MMRs */
 #ifdef ATAPI_CONTROL
        parent = debugfs_create_dir("atapi", top);
@@ -1873,7 +1876,7 @@ static int __init bfin_debug_mmrs_init(void)
        }
 #endif  /* BF54x */
+#endif /* CONFIG_BF60x */
        debug_mmrs_dentry = top;
        return 0;
diff --git a/arch/blackfin/kernel/entry.S b/arch/blackfin/kernel/entry.S
index 686478f5f66b..f33792cc1a0d 100644
--- a/arch/blackfin/kernel/entry.S
+++ b/arch/blackfin/kernel/entry.S
@@ -64,16 +64,6 @@ ENTRY(_ret_from_fork)
        jump (p0);
 ENDPROC(_ret_from_fork)
-ENTRY(_sys_fork)
-        r0 = -EINVAL;
-#if (ANOMALY_05000371)
-        nop;
-        nop;
-        nop;
-#endif
-        rts;
-ENDPROC(_sys_fork)
 ENTRY(_sys_vfork)
        r0 = sp;
        r0 += 24;
diff --git a/arch/blackfin/kernel/gptimers.c b/arch/blackfin/kernel/gptimers.c
index 06459f4bf43a..d776773d3869 100644
--- a/arch/blackfin/kernel/gptimers.c
+++ b/arch/blackfin/kernel/gptimers.c
@@ -23,7 +23,11 @@
                printk(KERN_DEBUG "%s:%s:%i: Assertion failed: " #expr "\n", __FILE__, __func__, __LINE__);
 #endif
-#define BFIN_TIMER_NUM_GROUP  (BFIN_TIMER_OCTET(MAX_BLACKFIN_GPTIMERS - 1) + 1)
+#ifndef CONFIG_BF60x
+# define BFIN_TIMER_NUM_GROUP  (BFIN_TIMER_OCTET(MAX_BLACKFIN_GPTIMERS - 1) + 1)
+#else
+# define BFIN_TIMER_NUM_GROUP  1
+#endif
 static struct bfin_gptimer_regs * const timer_regs[MAX_BLACKFIN_GPTIMERS] =
 {
@@ -158,6 +162,74 @@ uint32_t get_gptimer_count(unsigned int timer_id)
 }
 EXPORT_SYMBOL(get_gptimer_count);
+#ifdef CONFIG_BF60x
+void set_gptimer_delay(unsigned int timer_id, uint32_t delay)
+{
+        tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
+        bfin_write(&timer_regs[timer_id]->delay, delay);
+        SSYNC();
+}
+EXPORT_SYMBOL(set_gptimer_delay);
+uint32_t get_gptimer_delay(unsigned int timer_id)
+{
+        tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
+        return bfin_read(&timer_regs[timer_id]->delay);
+}
+EXPORT_SYMBOL(get_gptimer_delay);
+#endif
+#ifdef CONFIG_BF60x
+int get_gptimer_intr(unsigned int timer_id)
+{
+        tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
+        return !!(bfin_read(&group_regs[BFIN_TIMER_OCTET(timer_id)]->data_ilat) & timil_mask[timer_id]);
+}
+EXPORT_SYMBOL(get_gptimer_intr);
+void clear_gptimer_intr(unsigned int timer_id)
+{
+        tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
+        bfin_write(&group_regs[BFIN_TIMER_OCTET(timer_id)]->data_ilat, timil_mask[timer_id]);
+}
+EXPORT_SYMBOL(clear_gptimer_intr);
+int get_gptimer_over(unsigned int timer_id)
+{
+        tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
+        return !!(bfin_read(&group_regs[BFIN_TIMER_OCTET(timer_id)]->stat_ilat) & tovf_mask[timer_id]);
+}
+EXPORT_SYMBOL(get_gptimer_over);
+void clear_gptimer_over(unsigned int timer_id)
+{
+        tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
+        bfin_write(&group_regs[BFIN_TIMER_OCTET(timer_id)]->stat_ilat, tovf_mask[timer_id]);
+}
+EXPORT_SYMBOL(clear_gptimer_over);
+int get_gptimer_run(unsigned int timer_id)
+{
+        tassert(timer_id < MAX_BLACKFIN_GPTIMERS);
+        return !!(bfin_read(&group_regs[BFIN_TIMER_OCTET(timer_id)]->run) & trun_mask[timer_id]);
+}
+EXPORT_SYMBOL(get_gptimer_run);
+uint32_t get_gptimer_status(unsigned int group)
+{
+        tassert(group < BFIN_TIMER_NUM_GROUP);
+        return bfin_read(&group_regs[group]->data_ilat);
+}
+EXPORT_SYMBOL(get_gptimer_status);
+void set_gptimer_status(unsigned int group, uint32_t value)
+{
+        tassert(group < BFIN_TIMER_NUM_GROUP);
+        bfin_write(&group_regs[group]->data_ilat, value);
+        SSYNC();
+}
+EXPORT_SYMBOL(set_gptimer_status);
+#else
 uint32_t get_gptimer_status(unsigned int group)
 {
        tassert(group < BFIN_TIMER_NUM_GROUP);
@@ -212,6 +284,7 @@ int get_gptimer_run(unsigned int timer_id)
        return !!(read_gptimer_status(timer_id) & trun_mask[timer_id]);
 }
 EXPORT_SYMBOL(get_gptimer_run);
+#endif
 void set_gptimer_config(unsigned int timer_id, uint16_t config)
 {
@@ -231,6 +304,12 @@ EXPORT_SYMBOL(get_gptimer_config);
 void enable_gptimers(uint16_t mask)
 {
        int i;
+#ifdef CONFIG_BF60x
+        uint16_t imask;
+        imask = bfin_read16(TIMER_DATA_IMSK);
+        imask &= ~mask;
+        bfin_write16(TIMER_DATA_IMSK, imask);
+#endif
        tassert((mask & ~BLACKFIN_GPTIMER_IDMASK) == 0);
        for (i = 0; i < BFIN_TIMER_NUM_GROUP; ++i) {
                bfin_write(&group_regs[i]->enable, mask & 0xFF);
@@ -253,12 +332,16 @@ static void _disable_gptimers(uint16_t mask)
 void disable_gptimers(uint16_t mask)
 {
+#ifndef CONFIG_BF60x
        int i;
        _disable_gptimers(mask);
        for (i = 0; i < MAX_BLACKFIN_GPTIMERS; ++i)
                if (mask & (1 << i))
                        bfin_write(&group_regs[BFIN_TIMER_OCTET(i)]->status, trun_mask[i]);
        SSYNC();
+#else
+        _disable_gptimers(mask);
+#endif
 }
 EXPORT_SYMBOL(disable_gptimers);
diff --git a/arch/blackfin/kernel/init_task.c b/arch/blackfin/kernel/init_task.c
deleted file mode 100644
index d3970e8acd1a..000000000000
--- a/arch/blackfin/kernel/init_task.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/init_task.h>
-#include <linux/mqueue.h>
-#include <linux/fs.h>
-static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
-static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
-/*
- * Initial task structure.
- *
- * All other task structs will be allocated on slabs in fork.c
- */
-struct task_struct init_task = INIT_TASK(init_task);
-EXPORT_SYMBOL(init_task);
-/*
- * Initial thread structure.
- *
- * We need to make sure that this is 8192-byte aligned due to the
- * way process stacks are handled. This is done by having a special
- * "init_task" linker map entry.
- */
-union thread_union init_thread_union
-    __init_task_data = {
-INIT_THREAD_INFO(init_task)};
diff --git a/arch/blackfin/kernel/process.c b/arch/blackfin/kernel/process.c
index c0f4fe287eb6..2e3994b20169 100644
--- a/arch/blackfin/kernel/process.c
+++ b/arch/blackfin/kernel/process.c
@@ -95,7 +95,9 @@ void cpu_idle(void)
                        idle();
                rcu_idle_exit();
                tick_nohz_idle_exit();
-                schedule_preempt_disabled();
+                preempt_enable_no_resched();
+                schedule();
+                preempt_disable();
        }
 }
@@ -329,12 +331,16 @@ int in_mem_const(unsigned long addr, unsigned long size,
 {
        return in_mem_const_off(addr, size, 0, const_addr, const_size);
 }
+#ifdef CONFIG_BF60x
+#define ASYNC_ENABLED(bnum, bctlnum)    1
+#else
 #define ASYNC_ENABLED(bnum, bctlnum) \
 ({ \
        (bfin_read_EBIU_AMGCTL() & 0xe) < ((bnum + 1) << 1) ? 0 : \
        bfin_read_EBIU_AMBCTL##bctlnum() & B##bnum##RDYEN ? 0 : \
        1; \
 })
+#endif
 /*
 * We can't read EBIU banks that aren't enabled or we end up hanging
 * on the access to the async space.  Make sure we validate accesses
diff --git a/arch/blackfin/kernel/reboot.c b/arch/blackfin/kernel/reboot.c
index b0434f89e8de..5272e6eefd92 100644
--- a/arch/blackfin/kernel/reboot.c
+++ b/arch/blackfin/kernel/reboot.c
@@ -22,6 +22,7 @@
 __attribute__ ((__l1_text__, __noreturn__))
 static void bfin_reset(void)
 {
+#ifndef CONFIG_BF60x
        if (!ANOMALY_05000353 && !ANOMALY_05000386)
                bfrom_SoftReset((void *)(L1_SCRATCH_START + L1_SCRATCH_LENGTH - 20));
@@ -57,7 +58,6 @@ static void bfin_reset(void)
        if (__SILICON_REVISION__ < 1 && bfin_revid() < 1)
                bfin_read_SWRST();
 #endif
        /* Wait for the SWRST write to complete.  Cannot rely on SSYNC
         * though as the System state is all reset now.
         */
@@ -72,6 +72,10 @@ static void bfin_reset(void)
        while (1)
                /* Issue core reset */
                asm("raise 1");
+#else
+        while (1)
+                bfin_write_RCU0_CTL(0x1);
+#endif
 }
 __attribute__((weak))
diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c
index 2ad747e909fb..ada8f0fc71e4 100644
--- a/arch/blackfin/kernel/setup.c
+++ b/arch/blackfin/kernel/setup.c
@@ -25,12 +25,16 @@
 #include <asm/cacheflush.h>
 #include <asm/blackfin.h>
 #include <asm/cplbinit.h>
+#include <asm/clocks.h>
 #include <asm/div64.h>
 #include <asm/cpu.h>
 #include <asm/fixed_code.h>
 #include <asm/early_printk.h>
 #include <asm/irq_handler.h>
 #include <asm/pda.h>
+#ifdef CONFIG_BF60x
+#include <mach/pm.h>
+#endif
 u16 _bfin_swrst;
 EXPORT_SYMBOL(_bfin_swrst);
@@ -550,7 +554,6 @@ static __init void memory_setup(void)
 {
 #ifdef CONFIG_MTD_UCLINUX
        unsigned long mtd_phys = 0;
-        unsigned long n;
 #endif
        unsigned long max_mem;
@@ -594,9 +597,9 @@ static __init void memory_setup(void)
        mtd_size = PAGE_ALIGN(*((unsigned long *)(mtd_phys + 8)));
 # if defined(CONFIG_EXT2_FS) || defined(CONFIG_EXT3_FS)
-        n = ext2_image_size((void *)(mtd_phys + 0x400));
+        if (*((unsigned short *)(mtd_phys + 0x438)) == EXT2_SUPER_MAGIC)
-        if (n)
+                mtd_size =
-                mtd_size = PAGE_ALIGN(n * 1024);
+                    PAGE_ALIGN(*((unsigned long *)(mtd_phys + 0x404)) << 10);
 # endif
 # if defined(CONFIG_CRAMFS)
@@ -612,7 +615,8 @@ static __init void memory_setup(void)
                /* ROM_FS is XIP, so if we found it, we need to limit memory */
                if (memory_end > max_mem) {
-                        pr_info("Limiting kernel memory to %liMB due to anomaly 05000263\n", max_mem >> 20);
+                        pr_info("Limiting kernel memory to %liMB due to anomaly 05000263\n",
+                                (max_mem - CONFIG_PHY_RAM_BASE_ADDRESS) >> 20);
                        memory_end = max_mem;
                }
        }
@@ -642,7 +646,8 @@ static __init void memory_setup(void)
         * doesn't exist, or we don't need to - then dont.
         */
        if (memory_end > max_mem) {
-                pr_info("Limiting kernel memory to %liMB due to anomaly 05000263\n", max_mem >> 20);
+                pr_info("Limiting kernel memory to %liMB due to anomaly 05000263\n",
+                                (max_mem - CONFIG_PHY_RAM_BASE_ADDRESS) >> 20);
                memory_end = max_mem;
        }
@@ -661,8 +666,8 @@ static __init void memory_setup(void)
        init_mm.end_data = (unsigned long)_edata;
        init_mm.brk = (unsigned long)0;
-        printk(KERN_INFO "Board Memory: %ldMB\n", physical_mem_end >> 20);
+        printk(KERN_INFO "Board Memory: %ldMB\n", (physical_mem_end - CONFIG_PHY_RAM_BASE_ADDRESS) >> 20);
-        printk(KERN_INFO "Kernel Managed Memory: %ldMB\n", _ramend >> 20);
+        printk(KERN_INFO "Kernel Managed Memory: %ldMB\n", (_ramend - CONFIG_PHY_RAM_BASE_ADDRESS) >> 20);
        printk(KERN_INFO "Memory map:\n"
               "  fixedcode = 0x%p-0x%p\n"
@@ -705,7 +710,7 @@ void __init find_min_max_pfn(void)
        int i;
        max_pfn = 0;
-        min_low_pfn = memory_end;
+        min_low_pfn = PFN_DOWN(memory_end);
        for (i = 0; i < bfin_memmap.nr_map; i++) {
                unsigned long start, end;
@@ -748,8 +753,7 @@ static __init void setup_bootmem_allocator(void)
        /* pfn of the first usable page frame after kernel image*/
        if (min_low_pfn < memory_start >> PAGE_SHIFT)
                min_low_pfn = memory_start >> PAGE_SHIFT;
+        start_pfn = CONFIG_PHY_RAM_BASE_ADDRESS >> PAGE_SHIFT;
-        start_pfn = PAGE_OFFSET >> PAGE_SHIFT;
        end_pfn = memory_end >> PAGE_SHIFT;
        /*
@@ -794,8 +798,8 @@ static __init void setup_bootmem_allocator(void)
        }
        /* reserve memory before memory_start, including bootmap */
-        reserve_bootmem(PAGE_OFFSET,
+        reserve_bootmem(CONFIG_PHY_RAM_BASE_ADDRESS,
-                memory_start + bootmap_size + PAGE_SIZE - 1 - PAGE_OFFSET,
+                memory_start + bootmap_size + PAGE_SIZE - 1 - CONFIG_PHY_RAM_BASE_ADDRESS,
                BOOTMEM_DEFAULT);
 }
@@ -844,13 +848,40 @@ static inline int __init get_mem_size(void)
                break;
        }
        switch (ddrctl & 0x30000) {
-                case DEVWD_4:  ret *= 2;
+        case DEVWD_4:
-                case DEVWD_8:  ret *= 2;
+                ret *= 2;
-                case DEVWD_16: break;
+        case DEVWD_8:
+                ret *= 2;
+        case DEVWD_16:
+                break;
        }
        if ((ddrctl & 0xc000) == 0x4000)
                ret *= 2;
        return ret;
+#elif defined(CONFIG_BF60x)
+        u32 ddrctl = bfin_read_DMC0_CFG();
+        int ret;
+        switch (ddrctl & 0xf00) {
+        case DEVSZ_64:
+                ret = 64 / 8;
+                break;
+        case DEVSZ_128:
+                ret = 128 / 8;
+                break;
+        case DEVSZ_256:
+                ret = 256 / 8;
+                break;
+        case DEVSZ_512:
+                ret = 512 / 8;
+                break;
+        case DEVSZ_1G:
+                ret = 1024 / 8;
+                break;
+        case DEVSZ_2G:
+                ret = 2048 / 8;
+                break;
+        }
+        return ret;
 #endif
        BUG();
 }
@@ -860,6 +891,22 @@ void __init native_machine_early_platform_add_devices(void)
 {
 }
+#ifdef CONFIG_BF60x
+static inline u_long bfin_get_clk(char *name)
+{
+        struct clk *clk;
+        u_long clk_rate;
+        clk = clk_get(NULL, name);
+        if (IS_ERR(clk))
+                return 0;
+        clk_rate = clk_get_rate(clk);
+        clk_put(clk);
+        return clk_rate;
+}
+#endif
 void __init setup_arch(char **cmdline_p)
 {
        u32 mmr;
@@ -870,6 +917,7 @@ void __init setup_arch(char **cmdline_p)
        enable_shadow_console();
        /* Check to make sure we are running on the right processor */
+        mmr =  bfin_cpuid();
        if (unlikely(CPUID != bfin_cpuid()))
                printk(KERN_ERR "ERROR: Not running on ADSP-%s: unknown CPUID 0x%04x Rev 0.%d\n",
                        CPU, bfin_cpuid(), bfin_revid());
@@ -890,6 +938,10 @@ void __init setup_arch(char **cmdline_p)
        memset(&bfin_memmap, 0, sizeof(bfin_memmap));
+#ifdef CONFIG_BF60x
+        /* Should init clock device before parse command early */
+        clk_init();
+#endif
        /* If the user does not specify things on the command line, use
         * what the bootloader set things up as
         */
@@ -904,6 +956,7 @@ void __init setup_arch(char **cmdline_p)
        memory_setup();
+#ifndef CONFIG_BF60x
        /* Initialize Async memory banks */
        bfin_write_EBIU_AMBCTL0(AMBCTL0VAL);
        bfin_write_EBIU_AMBCTL1(AMBCTL1VAL);
@@ -913,6 +966,7 @@ void __init setup_arch(char **cmdline_p)
        bfin_write_EBIU_MODE(CONFIG_EBIU_MODEVAL);
        bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTLVAL);
 #endif
+#endif
 #ifdef CONFIG_BFIN_HYSTERESIS_CONTROL
        bfin_write_PORTF_HYSTERESIS(HYST_PORTF_0_15);
        bfin_write_PORTG_HYSTERESIS(HYST_PORTG_0_15);
@@ -938,7 +992,7 @@ void __init setup_arch(char **cmdline_p)
        printk(KERN_INFO "Hardware Trace %s and %sabled\n",
                (mmr & 0x1) ? "active" : "off",
                (mmr & 0x2) ? "en" : "dis");
+#ifndef CONFIG_BF60x
        mmr = bfin_read_SYSCR();
        printk(KERN_INFO "Boot Mode: %i\n", mmr & 0xF);
@@ -980,7 +1034,7 @@ void __init setup_arch(char **cmdline_p)
                printk(KERN_INFO "Recovering from Watchdog event\n");
        else if (_bfin_swrst & RESET_SOFTWARE)
                printk(KERN_NOTICE "Reset caused by Software reset\n");
+#endif
        printk(KERN_INFO "Blackfin support (C) 2004-2010 Analog Devices, Inc.\n");
        if (bfin_compiled_revid() == 0xffff)
                printk(KERN_INFO "Compiled for ADSP-%s Rev any, running on 0.%d\n", CPU, bfin_revid());
@@ -1008,8 +1062,13 @@ void __init setup_arch(char **cmdline_p)
        printk(KERN_INFO "Blackfin Linux support by http://blackfin.uclinux.org/\n");
+#ifdef CONFIG_BF60x
+        printk(KERN_INFO "Processor Speed: %lu MHz core clock, %lu MHz SCLk, %lu MHz SCLK0, %lu MHz SCLK1 and %lu MHz DCLK\n",
+                cclk / 1000000, bfin_get_clk("SYSCLK") / 1000000, get_sclk0() / 1000000, get_sclk1() / 1000000, get_dclk() / 1000000);
+#else
        printk(KERN_INFO "Processor Speed: %lu MHz core clock and %lu MHz System Clock\n",
               cclk / 1000000, sclk / 1000000);
+#endif
        setup_bootmem_allocator();
@@ -1060,10 +1119,12 @@ subsys_initcall(topology_init);
 /* Get the input clock frequency */
 static u_long cached_clkin_hz = CONFIG_CLKIN_HZ;
+#ifndef CONFIG_BF60x
 static u_long get_clkin_hz(void)
 {
        return cached_clkin_hz;
 }
+#endif
 static int __init early_init_clkin_hz(char *buf)
 {
        cached_clkin_hz = simple_strtoul(buf, NULL, 0);
@@ -1075,6 +1136,7 @@ static int __init early_init_clkin_hz(char *buf)
 }
 early_param("clkin_hz=", early_init_clkin_hz);
+#ifndef CONFIG_BF60x
 /* Get the voltage input multiplier */
 static u_long get_vco(void)
 {
@@ -1097,10 +1159,14 @@ static u_long get_vco(void)
        cached_vco *= msel;
        return cached_vco;
 }
+#endif
 /* Get the Core clock */
 u_long get_cclk(void)
 {
+#ifdef CONFIG_BF60x
+        return bfin_get_clk("CCLK");
+#else
        static u_long cached_cclk_pll_div, cached_cclk;
        u_long csel, ssel;
@@ -1120,12 +1186,39 @@ u_long get_cclk(void)
        else
                cached_cclk = get_vco() >> csel;
        return cached_cclk;
+#endif
 }
 EXPORT_SYMBOL(get_cclk);
-/* Get the System clock */
+#ifdef CONFIG_BF60x
+/* Get the bf60x clock of SCLK0 domain */
+u_long get_sclk0(void)
+{
+        return bfin_get_clk("SCLK0");
+}
+EXPORT_SYMBOL(get_sclk0);
+/* Get the bf60x clock of SCLK1 domain */
+u_long get_sclk1(void)
+{
+        return bfin_get_clk("SCLK1");
+}
+EXPORT_SYMBOL(get_sclk1);
+/* Get the bf60x DRAM clock */
+u_long get_dclk(void)
+{
+        return bfin_get_clk("DCLK");
+}
+EXPORT_SYMBOL(get_dclk);
+#endif
+/* Get the default system clock */
 u_long get_sclk(void)
 {
+#ifdef CONFIG_BF60x
+        return get_sclk0();
+#else
        static u_long cached_sclk;
        u_long ssel;
@@ -1146,6 +1239,7 @@ u_long get_sclk(void)
        cached_sclk = get_vco() / ssel;
        return cached_sclk;
+#endif
 }
 EXPORT_SYMBOL(get_sclk);
diff --git a/arch/blackfin/kernel/shadow_console.c b/arch/blackfin/kernel/shadow_console.c
index 557e9fef406a..aeb8343eeb03 100644
--- a/arch/blackfin/kernel/shadow_console.c
+++ b/arch/blackfin/kernel/shadow_console.c
@@ -15,9 +15,9 @@
 #include <asm/irq_handler.h>
 #include <asm/early_printk.h>
-#define SHADOW_CONSOLE_START            (0x500)
+#define SHADOW_CONSOLE_START            (CONFIG_PHY_RAM_BASE_ADDRESS + 0x500)
-#define SHADOW_CONSOLE_END              (0x1000)
+#define SHADOW_CONSOLE_END              (CONFIG_PHY_RAM_BASE_ADDRESS + 0x1000)
-#define SHADOW_CONSOLE_MAGIC_LOC        (0x4F0)
+#define SHADOW_CONSOLE_MAGIC_LOC        (CONFIG_PHY_RAM_BASE_ADDRESS + 0x4F0)
 #define SHADOW_CONSOLE_MAGIC            (0xDEADBEEF)
 static __initdata char *shadow_console_buffer = (char *)SHADOW_CONSOLE_START;
diff --git a/arch/blackfin/kernel/time-ts.c b/arch/blackfin/kernel/time-ts.c
index d98f2d69b0c4..f608f02f29a3 100644
--- a/arch/blackfin/kernel/time-ts.c
+++ b/arch/blackfin/kernel/time-ts.c
@@ -66,8 +66,14 @@ void __init setup_gptimer0(void)
 {
        disable_gptimers(TIMER0bit);
+#ifdef CONFIG_BF60x
+        bfin_write16(TIMER_DATA_IMSK, 0);
+        set_gptimer_config(TIMER0_id,  TIMER_OUT_DIS
+                | TIMER_MODE_PWM_CONT | TIMER_PULSE_HI | TIMER_IRQ_PER);
+#else
        set_gptimer_config(TIMER0_id, \
                TIMER_OUT_DIS | TIMER_PERIOD_CNT | TIMER_MODE_PWM);
+#endif
        set_gptimer_period(TIMER0_id, -1);
        set_gptimer_pwidth(TIMER0_id, -2);
        SSYNC();
@@ -135,9 +141,15 @@ static void bfin_gptmr0_set_mode(enum clock_event_mode mode,
 {
        switch (mode) {
        case CLOCK_EVT_MODE_PERIODIC: {
+#ifndef CONFIG_BF60x
                set_gptimer_config(TIMER0_id, \
                        TIMER_OUT_DIS | TIMER_IRQ_ENA | \
                        TIMER_PERIOD_CNT | TIMER_MODE_PWM);
+#else
+                set_gptimer_config(TIMER0_id,  TIMER_OUT_DIS
+                        | TIMER_MODE_PWM_CONT | TIMER_PULSE_HI | TIMER_IRQ_PER);
+#endif
                set_gptimer_period(TIMER0_id, get_sclk() / HZ);
                set_gptimer_pwidth(TIMER0_id, get_sclk() / HZ - 1);
                enable_gptimers(TIMER0bit);
@@ -145,8 +157,14 @@ static void bfin_gptmr0_set_mode(enum clock_event_mode mode,
        }
        case CLOCK_EVT_MODE_ONESHOT:
                disable_gptimers(TIMER0bit);
+#ifndef CONFIG_BF60x
                set_gptimer_config(TIMER0_id, \
                        TIMER_OUT_DIS | TIMER_IRQ_ENA | TIMER_MODE_PWM);
+#else
+                set_gptimer_config(TIMER0_id, TIMER_OUT_DIS | TIMER_MODE_PWM
+                        | TIMER_PULSE_HI | TIMER_IRQ_WID_DLY);
+#endif
                set_gptimer_period(TIMER0_id, 0);
                break;
        case CLOCK_EVT_MODE_UNUSED:
@@ -160,7 +178,7 @@ static void bfin_gptmr0_set_mode(enum clock_event_mode mode,
 static void bfin_gptmr0_ack(void)
 {
-        set_gptimer_status(TIMER_GROUP1, TIMER_STATUS_TIMIL0);
+        clear_gptimer_intr(TIMER0_id);
 }
 static void __init bfin_gptmr0_init(void)
@@ -197,7 +215,7 @@ static struct clock_event_device clockevent_gptmr0 = {
        .rating         = 300,
        .irq            = IRQ_TIMER0,
        .shift          = 32,
-        .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
+        .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
        .set_next_event = bfin_gptmr0_set_next_event,
        .set_mode       = bfin_gptmr0_set_mode,
 };
@@ -312,6 +330,11 @@ void bfin_coretmr_clockevent_init(void)
 #endif
+#ifdef CONFIG_SMP
+        evt->broadcast = smp_timer_broadcast;
+#endif
        evt->name = "bfin_core_timer";
        evt->rating = 350;
        evt->irq = -1;
diff --git a/arch/blackfin/lib/divsi3.S b/arch/blackfin/lib/divsi3.S
index f89c5a49c47b..ef2cd99efb89 100644
--- a/arch/blackfin/lib/divsi3.S
+++ b/arch/blackfin/lib/divsi3.S
@@ -1,7 +1,7 @@
 /*
 * Copyright 2004-2009 Analog Devices Inc.
 *
- * Licensed under the ADI BSD license or the GPL-2 (or later)
+ * Licensed under the Clear BSD license or the GPL-2 (or later)
 *
 * 16 / 32 bit signed division.
 *                 Special cases :
diff --git a/arch/blackfin/lib/memchr.S b/arch/blackfin/lib/memchr.S
index 542e40f8775f..bcfc8a14c3f2 100644
--- a/arch/blackfin/lib/memchr.S
+++ b/arch/blackfin/lib/memchr.S
@@ -1,7 +1,7 @@
 /*
 * Copyright 2005-2009 Analog Devices Inc.
 *
- * Licensed under the ADI BSD license or the GPL-2 (or later)
+ * Licensed under the Clear BSD license or the GPL-2 (or later)
 */
 #include <linux/linkage.h>
diff --git a/arch/blackfin/lib/memcmp.S b/arch/blackfin/lib/memcmp.S
index ce5b9f1a8267..2e1c9477f2f7 100644
--- a/arch/blackfin/lib/memcmp.S
+++ b/arch/blackfin/lib/memcmp.S
@@ -1,7 +1,7 @@
 /*
 * Copyright 2004-2009 Analog Devices Inc.
 *
- * Licensed under the ADI BSD license or the GPL-2 (or later)
+ * Licensed under the Clear BSD license or the GPL-2 (or later)
 */
 #include <linux/linkage.h>
diff --git a/arch/blackfin/lib/memcpy.S b/arch/blackfin/lib/memcpy.S
index c31bf22aab19..53cb3698ab33 100644
--- a/arch/blackfin/lib/memcpy.S
+++ b/arch/blackfin/lib/memcpy.S
@@ -7,7 +7,7 @@
 *
 * Copyright 2004-2009 Analog Devices Inc.
 *
- * Licensed under the ADI BSD license or the GPL-2 (or later)
+ * Licensed under the Clear BSD license or the GPL-2 (or later)
 */
 #include <linux/linkage.h>
diff --git a/arch/blackfin/lib/memmove.S b/arch/blackfin/lib/memmove.S
index 4eca566237a4..e0b78208f1d6 100644
--- a/arch/blackfin/lib/memmove.S
+++ b/arch/blackfin/lib/memmove.S
@@ -1,7 +1,7 @@
 /*
 * Copyright 2005-2009 Analog Devices Inc.
 *
- * Licensed under the ADI BSD license or the GPL-2 (or later)
+ * Licensed under the Clear BSD license or the GPL-2 (or later)
 */
 #include <linux/linkage.h>
diff --git a/arch/blackfin/lib/memset.S b/arch/blackfin/lib/memset.S
index eab1bef3f5bf..cdcf9148ea20 100644
--- a/arch/blackfin/lib/memset.S
+++ b/arch/blackfin/lib/memset.S
@@ -1,7 +1,7 @@
 /*
 * Copyright 2004-2009 Analog Devices Inc.
 *
- * Licensed under the ADI BSD license or the GPL-2 (or later)
+ * Licensed under the Clear BSD license or the GPL-2 (or later)
 */
 #include <linux/linkage.h>
diff --git a/arch/blackfin/lib/modsi3.S b/arch/blackfin/lib/modsi3.S
index 8b0c7d4052af..f7026ce1fa0e 100644
--- a/arch/blackfin/lib/modsi3.S
+++ b/arch/blackfin/lib/modsi3.S
@@ -6,7 +6,7 @@
 *
 * Copyright 2004-2009 Analog Devices Inc.
 *
- * Licensed under the ADI BSD license or the GPL-2 (or later)
+ * Licensed under the Clear BSD license or the GPL-2 (or later)
 */
 .global ___modsi3;
diff --git a/arch/blackfin/lib/muldi3.S b/arch/blackfin/lib/muldi3.S
index 953a38a1d1d1..abf9b2a515b2 100644
--- a/arch/blackfin/lib/muldi3.S
+++ b/arch/blackfin/lib/muldi3.S
@@ -1,7 +1,7 @@
 /*
 * Copyright 2008 Analog Devices Inc.
 *
- * Licensed under the ADI BSD license or the GPL-2 (or later)
+ * Licensed under the Clear BSD license or the GPL-2 (or later)
 */
 .align 2
diff --git a/arch/blackfin/lib/smulsi3_highpart.S b/arch/blackfin/lib/smulsi3_highpart.S
index 99ee8c5de38b..e50d6c4ac2a5 100644
--- a/arch/blackfin/lib/smulsi3_highpart.S
+++ b/arch/blackfin/lib/smulsi3_highpart.S
@@ -1,7 +1,7 @@
 /*
 * Copyright 2007 Analog Devices Inc.
 *
- * Licensed under the ADI BSD license or the GPL-2 (or later)
+ * Licensed under the Clear BSD license or the GPL-2 (or later)
 */
 .align 2
diff --git a/arch/blackfin/lib/strcmp.S b/arch/blackfin/lib/strcmp.S
index d7c1d158973b..9c8b9863713e 100644
--- a/arch/blackfin/lib/strcmp.S
+++ b/arch/blackfin/lib/strcmp.S
@@ -1,7 +1,7 @@
 /*
 * Copyright 2005-2010 Analog Devices Inc.
 *
- * Licensed under the ADI BSD license or the GPL-2 (or later)
+ * Licensed under the Clear BSD license or the GPL-2 (or later)
 */
 #include <linux/linkage.h>
diff --git a/arch/blackfin/lib/strcpy.S b/arch/blackfin/lib/strcpy.S
index a6a0c6363806..9495aa77cc40 100644
--- a/arch/blackfin/lib/strcpy.S
+++ b/arch/blackfin/lib/strcpy.S
@@ -1,7 +1,7 @@
 /*
 * Copyright 2005-2010 Analog Devices Inc.
 *
- * Licensed under the ADI BSD license or the GPL-2 (or later)
+ * Licensed under the Clear BSD license or the GPL-2 (or later)
 */
 #include <linux/linkage.h>
diff --git a/arch/blackfin/lib/strncmp.S b/arch/blackfin/lib/strncmp.S
index 6da37c34a847..3bfaedce893e 100644
--- a/arch/blackfin/lib/strncmp.S
+++ b/arch/blackfin/lib/strncmp.S
@@ -1,7 +1,7 @@
 /*
 * Copyright 2005-2010 Analog Devices Inc.
 *
- * Licensed under the ADI BSD license or the GPL-2 (or later)
+ * Licensed under the Clear BSD license or the GPL-2 (or later)
 */
 #include <linux/linkage.h>
diff --git a/arch/blackfin/lib/strncpy.S b/arch/blackfin/lib/strncpy.S
index 2c07dddac995..92fd1823bbee 100644
--- a/arch/blackfin/lib/strncpy.S
+++ b/arch/blackfin/lib/strncpy.S
@@ -1,7 +1,7 @@
 /*
 * Copyright 2005-2010 Analog Devices Inc.
 *
- * Licensed under the ADI BSD license or the GPL-2 (or later)
+ * Licensed under the Clear BSD license or the GPL-2 (or later)
 */
 #include <linux/linkage.h>
diff --git a/arch/blackfin/lib/udivsi3.S b/arch/blackfin/lib/udivsi3.S
index 97e904315ec6..748a6a2e8c17 100644
--- a/arch/blackfin/lib/udivsi3.S
+++ b/arch/blackfin/lib/udivsi3.S
@@ -1,7 +1,7 @@
 /*
 * Copyright 2004-2009 Analog Devices Inc.
 *
- * Licensed under the ADI BSD license or the GPL-2 (or later)
+ * Licensed under the Clear BSD license or the GPL-2 (or later)
 */
 #include <linux/linkage.h>
diff --git a/arch/blackfin/lib/umodsi3.S b/arch/blackfin/lib/umodsi3.S
index 168eba7c64c8..3794c00d859d 100644
--- a/arch/blackfin/lib/umodsi3.S
+++ b/arch/blackfin/lib/umodsi3.S
@@ -3,7 +3,7 @@
 *
 * Copyright 2004-2009 Analog Devices Inc.
 *
- * Licensed under the ADI BSD license or the GPL-2 (or later)
+ * Licensed under the Clear BSD license or the GPL-2 (or later)
 */
 #ifdef CONFIG_ARITHMETIC_OPS_L1
diff --git a/arch/blackfin/lib/umulsi3_highpart.S b/arch/blackfin/lib/umulsi3_highpart.S
index 051824a6ed00..0dcace96e4e7 100644
--- a/arch/blackfin/lib/umulsi3_highpart.S
+++ b/arch/blackfin/lib/umulsi3_highpart.S
@@ -1,7 +1,7 @@
 /*
 * Copyright 2007 Analog Devices Inc.
 *
- * Licensed under the ADI BSD license or the GPL-2 (or later)
+ * Licensed under the Clear BSD license or the GPL-2 (or later)
 */
 .align 2
diff --git a/arch/blackfin/mach-bf518/boards/ezbrd.c b/arch/blackfin/mach-bf518/boards/ezbrd.c
index a17395727efa..f8047ca3b339 100644
--- a/arch/blackfin/mach-bf518/boards/ezbrd.c
+++ b/arch/blackfin/mach-bf518/boards/ezbrd.c
@@ -529,6 +529,8 @@ static struct platform_device bfin_i2s = {
 #endif
 #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
+static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
 static struct resource bfin_twi0_resource[] = {
        [0] = {
                .start = TWI0_REGBASE,
@@ -547,6 +549,9 @@ static struct platform_device i2c_bfin_twi_device = {
        .id = 0,
        .num_resources = ARRAY_SIZE(bfin_twi0_resource),
        .resource = bfin_twi0_resource,
+        .dev = {
+                .platform_data = &bfin_twi0_pins,
+        },
 };
 #endif
diff --git a/arch/blackfin/mach-bf518/boards/tcm-bf518.c b/arch/blackfin/mach-bf518/boards/tcm-bf518.c
index 6eebee4e4217..0bedc737566b 100644
--- a/arch/blackfin/mach-bf518/boards/tcm-bf518.c
+++ b/arch/blackfin/mach-bf518/boards/tcm-bf518.c
@@ -455,6 +455,8 @@ static struct platform_device bfin_sir1_device = {
 #endif
 #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
+static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
 static struct resource bfin_twi0_resource[] = {
        [0] = {
                .start = TWI0_REGBASE,
@@ -473,6 +475,9 @@ static struct platform_device i2c_bfin_twi_device = {
        .id = 0,
        .num_resources = ARRAY_SIZE(bfin_twi0_resource),
        .resource = bfin_twi0_resource,
+        .dev = {
+                .platform_data = &bfin_twi0_pins,
+        },
 };
 #endif
diff --git a/arch/blackfin/mach-bf518/include/mach/anomaly.h b/arch/blackfin/mach-bf518/include/mach/anomaly.h
index 56383f7cbc07..845e6bc8d633 100644
--- a/arch/blackfin/mach-bf518/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf518/include/mach/anomaly.h
@@ -6,8 +6,7 @@
 * DO NOT EDIT THIS FILE
 *
 * Copyright 2004-2011 Analog Devices Inc.
- * Licensed under the ADI BSD license.
+ * Licensed under the Clear BSD license.
- *   https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
 */
 /* This file should be up to date with:
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF512.h b/arch/blackfin/mach-bf518/include/mach/cdefBF512.h
index bb79627f0929..1c03ad4bcb72 100644
--- a/arch/blackfin/mach-bf518/include/mach/cdefBF512.h
+++ b/arch/blackfin/mach-bf518/include/mach/cdefBF512.h
@@ -1,7 +1,7 @@
 /*
 * Copyright 2008-2010 Analog Devices Inc.
 *
- * Licensed under the ADI BSD license or the GPL-2 (or later)
+ * Licensed under the Clear BSD license or the GPL-2 (or later)
 */
 #ifndef _CDEF_BF512_H
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF514.h b/arch/blackfin/mach-bf518/include/mach/cdefBF514.h
index dc988668203e..861221d1dcc9 100644
--- a/arch/blackfin/mach-bf518/include/mach/cdefBF514.h
+++ b/arch/blackfin/mach-bf518/include/mach/cdefBF514.h
@@ -1,7 +1,7 @@
 /*
 * Copyright 2008-2010 Analog Devices Inc.
 *
- * Licensed under the ADI BSD license or the GPL-2 (or later)
+ * Licensed under the Clear BSD license or the GPL-2 (or later)
 */
 #ifndef _CDEF_BF514_H
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF516.h b/arch/blackfin/mach-bf518/include/mach/cdefBF516.h
index 142e45cbc253..cc9bf0d378c3 100644
--- a/arch/blackfin/mach-bf518/include/mach/cdefBF516.h
+++ b/arch/blackfin/mach-bf518/include/mach/cdefBF516.h
@@ -1,7 +1,7 @@
 /*
 * Copyright 2008-2010 Analog Devices Inc.
 *
- * Licensed under the ADI BSD license or the GPL-2 (or later)
+ * Licensed under the Clear BSD license or the GPL-2 (or later)
 */
 #ifndef _CDEF_BF516_H
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF518.h b/arch/blackfin/mach-bf518/include/mach/cdefBF518.h
index e638197bf8b1..96a82fd62ef1 100644
--- a/arch/blackfin/mach-bf518/include/mach/cdefBF518.h
+++ b/arch/blackfin/mach-bf518/include/mach/cdefBF518.h
@@ -1,7 +1,7 @@
 /*
 * Copyright 2008-2010 Analog Devices Inc.
 *
- * Licensed under the ADI BSD license or the GPL-2 (or later)
+ * Licensed under the Clear BSD license or the GPL-2 (or later)
 */
 #ifndef _CDEF_BF518_H
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF512.h b/arch/blackfin/mach-bf518/include/mach/defBF512.h
index 729704078cd7..e6a017faad01 100644
--- a/arch/blackfin/mach-bf518/include/mach/defBF512.h
+++ b/arch/blackfin/mach-bf518/include/mach/defBF512.h
@@ -1,7 +1,7 @@
 /*
 * Copyright 2008-2010 Analog Devices Inc.
 *
- * Licensed under the ADI BSD license or the GPL-2 (or later)
+ * Licensed under the Clear BSD license or the GPL-2 (or later)
 */
 #ifndef _DEF_BF512_H
@@ -1083,77 +1083,6 @@
 #define ERR_NCOR                0x8000          /* Error Not Corrected Indicator        */
-/*  ********************  TWO-WIRE INTERFACE (TWI) MASKS  ***********************/
-/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y);  )                                */
-#define CLKLOW(x)       ((x) & 0xFF)            /* Periods Clock Is Held Low                    */
-#define CLKHI(y)        (((y)&0xFF)<<0x8)       /* Periods Before New Clock Low                 */
-/* TWI_PRESCALE Masks                                                                                                                   */
-#define PRESCALE        0x007F          /* SCLKs Per Internal Time Reference (10MHz)    */
-#define TWI_ENA         0x0080          /* TWI Enable                                                                   */
-#define SCCB            0x0200          /* SCCB Compatibility Enable                                    */
-/* TWI_SLAVE_CTL Masks                                                                                                                  */
-#define SEN                     0x0001          /* Slave Enable                                                                 */
-#define SADD_LEN        0x0002          /* Slave Address Length                                                 */
-#define STDVAL          0x0004          /* Slave Transmit Data Valid                                    */
-#define NAK                     0x0008          /* NAK/ACK* Generated At Conclusion Of Transfer */
-#define GEN                     0x0010          /* General Call Adrress Matching Enabled                */
-/* TWI_SLAVE_STAT Masks                                                                                                                 */
-#define SDIR            0x0001          /* Slave Transfer Direction (Transmit/Receive*) */
-#define GCALL           0x0002          /* General Call Indicator                                               */
-/* TWI_MASTER_CTL Masks                                                                                                 */
-#define MEN                     0x0001          /* Master Mode Enable                                           */
-#define MADD_LEN        0x0002          /* Master Address Length                                        */
-#define MDIR            0x0004          /* Master Transmit Direction (RX/TX*)           */
-#define FAST            0x0008          /* Use Fast Mode Timing Specs                           */
-#define STOP            0x0010          /* Issue Stop Condition                                         */
-#define RSTART          0x0020          /* Repeat Start or Stop* At End Of Transfer     */
-#define DCNT            0x3FC0          /* Data Bytes To Transfer                                       */
-#define SDAOVR          0x4000          /* Serial Data Override                                         */
-#define SCLOVR          0x8000          /* Serial Clock Override                                        */
-/* TWI_MASTER_STAT Masks                                                                                                                */
-#define MPROG           0x0001          /* Master Transfer In Progress                                  */
-#define LOSTARB         0x0002          /* Lost Arbitration Indicator (Xfer Aborted)    */
-#define ANAK            0x0004          /* Address Not Acknowledged                                             */
-#define DNAK            0x0008          /* Data Not Acknowledged                                                */
-#define BUFRDERR        0x0010          /* Buffer Read Error                                                    */
-#define BUFWRERR        0x0020          /* Buffer Write Error                                                   */
-#define SDASEN          0x0040          /* Serial Data Sense                                                    */
-#define SCLSEN          0x0080          /* Serial Clock Sense                                                   */
-#define BUSBUSY         0x0100          /* Bus Busy Indicator                                                   */
-/* TWI_INT_SRC and TWI_INT_ENABLE Masks                                         */
-#define SINIT           0x0001          /* Slave Transfer Initiated     */
-#define SCOMP           0x0002          /* Slave Transfer Complete      */
-#define SERR            0x0004          /* Slave Transfer Error         */
-#define SOVF            0x0008          /* Slave Overflow                       */
-#define MCOMP           0x0010          /* Master Transfer Complete     */
-#define MERR            0x0020          /* Master Transfer Error        */
-#define XMTSERV         0x0040          /* Transmit FIFO Service        */
-#define RCVSERV         0x0080          /* Receive FIFO Service         */
-/* TWI_FIFO_CTRL Masks                                                                                          */
-#define XMTFLUSH        0x0001          /* Transmit Buffer Flush                        */
-#define RCVFLUSH        0x0002          /* Receive Buffer Flush                         */
-#define XMTINTLEN       0x0004          /* Transmit Buffer Interrupt Length     */
-#define RCVINTLEN       0x0008          /* Receive Buffer Interrupt Length      */
-/* TWI_FIFO_STAT Masks                                                                                                                  */
-#define XMTSTAT         0x0003          /* Transmit FIFO Status                                                 */
-#define XMT_EMPTY       0x0000          /*              Transmit FIFO Empty                                             */
-#define XMT_HALF        0x0001          /*              Transmit FIFO Has 1 Byte To Write               */
-#define XMT_FULL        0x0003          /*              Transmit FIFO Full (2 Bytes To Write)   */
-#define RCVSTAT         0x000C          /* Receive FIFO Status                                                  */
-#define RCV_EMPTY       0x0000          /*              Receive FIFO Empty                                              */
-#define RCV_HALF        0x0004          /*              Receive FIFO Has 1 Byte To Read                 */
-#define RCV_FULL        0x000C          /*              Receive FIFO Full (2 Bytes To Read)             */
 /*  *******************  PIN CONTROL REGISTER MASKS  ************************/
 /* PORT_MUX Masks                                                                                                                       */
 #define PJSE                    0x0001                  /* Port J SPI/SPORT Enable                      */
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF514.h b/arch/blackfin/mach-bf518/include/mach/defBF514.h
index cfab428e577c..97feaa629ed7 100644
--- a/arch/blackfin/mach-bf518/include/mach/defBF514.h
+++ b/arch/blackfin/mach-bf518/include/mach/defBF514.h
@@ -1,7 +1,7 @@
 /*
 * Copyright 2008-2009 Analog Devices Inc.
 *
- * Licensed under the ADI BSD license or the GPL-2 (or later)
+ * Licensed under the Clear BSD license or the GPL-2 (or later)
 */
 #ifndef _DEF_BF514_H
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF516.h b/arch/blackfin/mach-bf518/include/mach/defBF516.h
index 22a3aa0d2629..7c79cb6a03b1 100644
--- a/arch/blackfin/mach-bf518/include/mach/defBF516.h
+++ b/arch/blackfin/mach-bf518/include/mach/defBF516.h
@@ -1,7 +1,7 @@
 /*
 * Copyright 2008-2009 Analog Devices Inc.
 *
- * Licensed under the ADI BSD license or the GPL-2 (or later)
+ * Licensed under the Clear BSD license or the GPL-2 (or later)
 */
 #ifndef _DEF_BF516_H
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF518.h b/arch/blackfin/mach-bf518/include/mach/defBF518.h
index cb18270e55c2..12042ff13601 100644
--- a/arch/blackfin/mach-bf518/include/mach/defBF518.h
+++ b/arch/blackfin/mach-bf518/include/mach/defBF518.h
@@ -1,7 +1,7 @@
 /*
 * Copyright 2008-2009 Analog Devices Inc.
 *
- * Licensed under the ADI BSD license or the GPL-2 (or later)
+ * Licensed under the Clear BSD license or the GPL-2 (or later)
 */
 #ifndef _DEF_BF518_H
diff --git a/arch/blackfin/mach-bf527/boards/ad7160eval.c b/arch/blackfin/mach-bf527/boards/ad7160eval.c
index fad7fea1b0bf..d58f50e5aa4b 100644
--- a/arch/blackfin/mach-bf527/boards/ad7160eval.c
+++ b/arch/blackfin/mach-bf527/boards/ad7160eval.c
@@ -569,6 +569,8 @@ static const struct ad7160_platform_data bfin_ad7160_ts_info = {
 #endif
 #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
+static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
 static struct resource bfin_twi0_resource[] = {
        [0] = {
                .start = TWI0_REGBASE,
@@ -587,6 +589,9 @@ static struct platform_device i2c_bfin_twi_device = {
        .id = 0,
        .num_resources = ARRAY_SIZE(bfin_twi0_resource),
        .resource = bfin_twi0_resource,
+        .dev = {
+                .platform_data = &bfin_twi0_pins,
+        },
 };
 #endif
@@ -681,6 +686,7 @@ static struct bfin_rotary_platform_data bfin_rotary_data = {
        .rotary_button_key = KEY_ENTER,
        .debounce          = 10,        /* 0..17 */
        .mode              = ROT_QUAD_ENC | ROT_DEBE,
+        .pm_wakeup         = 1,
 };
 static struct resource bfin_rotary_resources[] = {
diff --git a/arch/blackfin/mach-bf527/boards/cm_bf527.c b/arch/blackfin/mach-bf527/boards/cm_bf527.c
index 65b7fbd30e16..413d0132b66f 100644
--- a/arch/blackfin/mach-bf527/boards/cm_bf527.c
+++ b/arch/blackfin/mach-bf527/boards/cm_bf527.c
@@ -698,6 +698,8 @@ static struct platform_device bfin_sir1_device = {
 #endif
 #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
+static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
 static struct resource bfin_twi0_resource[] = {
        [0] = {
                .start = TWI0_REGBASE,
@@ -716,6 +718,9 @@ static struct platform_device i2c_bfin_twi_device = {
        .id = 0,
        .num_resources = ARRAY_SIZE(bfin_twi0_resource),
        .resource = bfin_twi0_resource,
+        .dev = {
+                .platform_data = &bfin_twi0_pins,
+        },
 };
 #endif
diff --git a/arch/blackfin/mach-bf527/boards/ezbrd.c b/arch/blackfin/mach-bf527/boards/ezbrd.c
index 17c6a24cc076..50bda79194e5 100644
--- a/arch/blackfin/mach-bf527/boards/ezbrd.c
+++ b/arch/blackfin/mach-bf527/boards/ezbrd.c
@@ -576,6 +576,8 @@ static struct platform_device bfin_sir1_device = {
 #endif
 #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
+static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
 static struct resource bfin_twi0_resource[] = {
        [0] = {
                .start = TWI0_REGBASE,
@@ -594,6 +596,9 @@ static struct platform_device i2c_bfin_twi_device = {
        .id = 0,
        .num_resources = ARRAY_SIZE(bfin_twi0_resource),
        .resource = bfin_twi0_resource,
+        .dev = {
+                .platform_data = &bfin_twi0_pins,
+        },
 };
 #endif
diff --git a/arch/blackfin/mach-bf527/boards/ezkit.c b/arch/blackfin/mach-bf527/boards/ezkit.c
index 2f9a2bd83ce4..af732eb3a687 100644
--- a/arch/blackfin/mach-bf527/boards/ezkit.c
+++ b/arch/blackfin/mach-bf527/boards/ezkit.c
@@ -869,6 +869,8 @@ static struct platform_device bfin_sir1_device = {
 #endif
 #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
+static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
 static struct resource bfin_twi0_resource[] = {
        [0] = {
                .start = TWI0_REGBASE,
@@ -887,6 +889,9 @@ static struct platform_device i2c_bfin_twi_device = {
        .id = 0,
        .num_resources = ARRAY_SIZE(bfin_twi0_resource),
        .resource = bfin_twi0_resource,
+        .dev = {
+                .platform_data = &bfin_twi0_pins,
+        },
 };
 #endif
@@ -1105,6 +1110,7 @@ static struct bfin_rotary_platform_data bfin_rotary_data = {
        .rotary_button_key = KEY_ENTER,
        .debounce          = 10,        /* 0..17 */
        .mode              = ROT_QUAD_ENC | ROT_DEBE,
+        .pm_wakeup         = 1,
 };
 static struct resource bfin_rotary_resources[] = {
diff --git a/arch/blackfin/mach-bf527/boards/tll6527m.c b/arch/blackfin/mach-bf527/boards/tll6527m.c
index d192c0ac941c..1509c5a8a3ff 100644
--- a/arch/blackfin/mach-bf527/boards/tll6527m.c
+++ b/arch/blackfin/mach-bf527/boards/tll6527m.c
@@ -656,6 +656,8 @@ static struct platform_device bfin_sir1_device = {
 #endif
 #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
+static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
 static struct resource bfin_twi0_resource[] = {
        [0] = {
                .start = TWI0_REGBASE,
@@ -674,6 +676,9 @@ static struct platform_device i2c_bfin_twi_device = {
        .id = 0,
        .num_resources = ARRAY_SIZE(bfin_twi0_resource),
        .resource = bfin_twi0_resource,
+        .dev = {
+                .platform_data = &bfin_twi0_pins,
+        },
 };
 #endif
diff --git a/arch/blackfin/mach-bf527/include/mach/anomaly.h b/arch/blackfin/mach-bf527/include/mach/anomaly.h
index 688470611e15..aa14110be4c4 100644
--- a/arch/blackfin/mach-bf527/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf527/include/mach/anomaly.h
@@ -6,8 +6,7 @@
 * DO NOT EDIT THIS FILE
 *
 * Copyright 2004-2011 Analog Devices Inc.
- * Licensed under the ADI BSD license.
+ * Licensed under the Clear BSD license.
- *   https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
 */
 /* This file should be up to date with:
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF522.h b/arch/blackfin/mach-bf527/include/mach/defBF522.h
index 37d353a19722..e007017cf958 100644
--- a/arch/blackfin/mach-bf527/include/mach/defBF522.h
+++ b/arch/blackfin/mach-bf527/include/mach/defBF522.h
@@ -1,7 +1,7 @@
 /*
 * Copyright 2007-2010 Analog Devices Inc.
 *
- * Licensed under the ADI BSD license or the GPL-2 (or later)
+ * Licensed under the Clear BSD license or the GPL-2 (or later)
 */
 #ifndef _DEF_BF522_H
@@ -1084,77 +1084,6 @@
 #define ERR_NCOR                0x8000          /* Error Not Corrected Indicator        */
-/*  ********************  TWO-WIRE INTERFACE (TWI) MASKS  ***********************/
-/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y);  )                                */
-#define CLKLOW(x)       ((x) & 0xFF)            /* Periods Clock Is Held Low                    */
-#define CLKHI(y)        (((y)&0xFF)<<0x8)       /* Periods Before New Clock Low                 */
-/* TWI_PRESCALE Masks                                                                                                                   */
-#define PRESCALE        0x007F          /* SCLKs Per Internal Time Reference (10MHz)    */
-#define TWI_ENA         0x0080          /* TWI Enable                                                                   */
-#define SCCB            0x0200          /* SCCB Compatibility Enable                                    */
-/* TWI_SLAVE_CTL Masks                                                                                                                  */
-#define SEN                     0x0001          /* Slave Enable                                                                 */
-#define SADD_LEN        0x0002          /* Slave Address Length                                                 */
-#define STDVAL          0x0004          /* Slave Transmit Data Valid                                    */
-#define NAK                     0x0008          /* NAK/ACK* Generated At Conclusion Of Transfer */
-#define GEN                     0x0010          /* General Call Adrress Matching Enabled                */
-/* TWI_SLAVE_STAT Masks                                                                                                                 */
-#define SDIR            0x0001          /* Slave Transfer Direction (Transmit/Receive*) */
-#define GCALL           0x0002          /* General Call Indicator                                               */
-/* TWI_MASTER_CTL Masks                                                                                                 */
-#define MEN                     0x0001          /* Master Mode Enable                                           */
-#define MADD_LEN        0x0002          /* Master Address Length                                        */
-#define MDIR            0x0004          /* Master Transmit Direction (RX/TX*)           */
-#define FAST            0x0008          /* Use Fast Mode Timing Specs                           */
-#define STOP            0x0010          /* Issue Stop Condition                                         */
-#define RSTART          0x0020          /* Repeat Start or Stop* At End Of Transfer     */
-#define DCNT            0x3FC0          /* Data Bytes To Transfer                                       */
-#define SDAOVR          0x4000          /* Serial Data Override                                         */
-#define SCLOVR          0x8000          /* Serial Clock Override                                        */
-/* TWI_MASTER_STAT Masks                                                                                                                */
-#define MPROG           0x0001          /* Master Transfer In Progress                                  */
-#define LOSTARB         0x0002          /* Lost Arbitration Indicator (Xfer Aborted)    */
-#define ANAK            0x0004          /* Address Not Acknowledged                                             */
-#define DNAK            0x0008          /* Data Not Acknowledged                                                */
-#define BUFRDERR        0x0010          /* Buffer Read Error                                                    */
-#define BUFWRERR        0x0020          /* Buffer Write Error                                                   */
-#define SDASEN          0x0040          /* Serial Data Sense                                                    */
-#define SCLSEN          0x0080          /* Serial Clock Sense                                                   */
-#define BUSBUSY         0x0100          /* Bus Busy Indicator                                                   */
-/* TWI_INT_SRC and TWI_INT_ENABLE Masks                                         */
-#define SINIT           0x0001          /* Slave Transfer Initiated     */
-#define SCOMP           0x0002          /* Slave Transfer Complete      */
-#define SERR            0x0004          /* Slave Transfer Error         */
-#define SOVF            0x0008          /* Slave Overflow                       */
-#define MCOMP           0x0010          /* Master Transfer Complete     */
-#define MERR            0x0020          /* Master Transfer Error        */
-#define XMTSERV         0x0040          /* Transmit FIFO Service        */
-#define RCVSERV         0x0080          /* Receive FIFO Service         */
-/* TWI_FIFO_CTRL Masks                                                                                          */
-#define XMTFLUSH        0x0001          /* Transmit Buffer Flush                        */
-#define RCVFLUSH        0x0002          /* Receive Buffer Flush                         */
-#define XMTINTLEN       0x0004          /* Transmit Buffer Interrupt Length     */
-#define RCVINTLEN       0x0008          /* Receive Buffer Interrupt Length      */
-/* TWI_FIFO_STAT Masks                                                                                                                  */
-#define XMTSTAT         0x0003          /* Transmit FIFO Status                                                 */
-#define XMT_EMPTY       0x0000          /*              Transmit FIFO Empty                                             */
-#define XMT_HALF        0x0001          /*              Transmit FIFO Has 1 Byte To Write               */
-#define XMT_FULL        0x0003          /*              Transmit FIFO Full (2 Bytes To Write)   */
-#define RCVSTAT         0x000C          /* Receive FIFO Status                                                  */
-#define RCV_EMPTY       0x0000          /*              Receive FIFO Empty                                              */
-#define RCV_HALF        0x0004          /*              Receive FIFO Has 1 Byte To Read                 */
-#define RCV_FULL        0x000C          /*              Receive FIFO Full (2 Bytes To Read)             */
 /* Omit CAN masks from defBF534.h */
 /*  *******************  PIN CONTROL REGISTER MASKS  ************************/
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF525.h b/arch/blackfin/mach-bf527/include/mach/defBF525.h
index aab80bb1a683..71578d964d00 100644
--- a/arch/blackfin/mach-bf527/include/mach/defBF525.h
+++ b/arch/blackfin/mach-bf527/include/mach/defBF525.h
@@ -1,7 +1,7 @@
 /*
 * Copyright 2007-2010 Analog Devices Inc.
 *
- * Licensed under the ADI BSD license or the GPL-2 (or later)
+ * Licensed under the Clear BSD license or the GPL-2 (or later)
 */
 #ifndef _DEF_BF525_H
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF527.h b/arch/blackfin/mach-bf527/include/mach/defBF527.h
index 05369a92fbc8..aeb84795b35e 100644
--- a/arch/blackfin/mach-bf527/include/mach/defBF527.h
+++ b/arch/blackfin/mach-bf527/include/mach/defBF527.h
@@ -1,7 +1,7 @@
 /*
 * Copyright 2007-2010 Analog Devices Inc.
 *
- * Licensed under the ADI BSD license or the GPL-2 (or later)
+ * Licensed under the Clear BSD license or the GPL-2 (or later)
 */
 #ifndef _DEF_BF527_H
diff --git a/arch/blackfin/mach-bf533/include/mach/anomaly.h b/arch/blackfin/mach-bf533/include/mach/anomaly.h
index 03f2b40912a3..3a8f73a669f0 100644
--- a/arch/blackfin/mach-bf533/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf533/include/mach/anomaly.h
@@ -6,8 +6,7 @@
 * DO NOT EDIT THIS FILE
 *
 * Copyright 2004-2011 Analog Devices Inc.
- * Licensed under the ADI BSD license.
+ * Licensed under the Clear BSD license.
- *   https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
 */
 /* This file should be up to date with:
diff --git a/arch/blackfin/mach-bf533/include/mach/defBF532.h b/arch/blackfin/mach-bf533/include/mach/defBF532.h
index 2376d5393511..d438150b1025 100644
--- a/arch/blackfin/mach-bf533/include/mach/defBF532.h
+++ b/arch/blackfin/mach-bf533/include/mach/defBF532.h
@@ -3,7 +3,7 @@
 *
 * Copyright 2005-2010 Analog Devices Inc.
 *
- * Licensed under the ADI BSD license or the GPL-2 (or later)
+ * Licensed under the Clear BSD license or the GPL-2 (or later)
 */
 #ifndef _DEF_BF532_H
diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537e.c b/arch/blackfin/mach-bf537/boards/cm_bf537e.c
index 27fd2c32ae9a..9408ab56d87f 100644
--- a/arch/blackfin/mach-bf537/boards/cm_bf537e.c
+++ b/arch/blackfin/mach-bf537/boards/cm_bf537e.c
@@ -486,6 +486,8 @@ static struct platform_device bfin_sir1_device = {
 #endif
 #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
+static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
 static struct resource bfin_twi0_resource[] = {
        [0] = {
                .start = TWI0_REGBASE,
@@ -504,6 +506,9 @@ static struct platform_device i2c_bfin_twi_device = {
        .id = 0,
        .num_resources = ARRAY_SIZE(bfin_twi0_resource),
        .resource = bfin_twi0_resource,
+        .dev = {
+                .platform_data = &bfin_twi0_pins,
+        },
 };
 #endif
diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537u.c b/arch/blackfin/mach-bf537/boards/cm_bf537u.c
index 3f3abad86ec3..0143d8bef909 100644
--- a/arch/blackfin/mach-bf537/boards/cm_bf537u.c
+++ b/arch/blackfin/mach-bf537/boards/cm_bf537u.c
@@ -451,6 +451,8 @@ static struct platform_device bfin_sir1_device = {
 #endif
 #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
+static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
 static struct resource bfin_twi0_resource[] = {
        [0] = {
                .start = TWI0_REGBASE,
@@ -469,6 +471,9 @@ static struct platform_device i2c_bfin_twi_device = {
        .id = 0,
        .num_resources = ARRAY_SIZE(bfin_twi0_resource),
        .resource = bfin_twi0_resource,
+        .dev = {
+                .platform_data = &bfin_twi0_pins,
+        },
 };
 #endif
diff --git a/arch/blackfin/mach-bf537/boards/dnp5370.c b/arch/blackfin/mach-bf537/boards/dnp5370.c
index 6f77bf708ec0..8bbf0a23fd49 100644
--- a/arch/blackfin/mach-bf537/boards/dnp5370.c
+++ b/arch/blackfin/mach-bf537/boards/dnp5370.c
@@ -329,6 +329,8 @@ static struct platform_device bfin_uart1_device = {
 #endif
 #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
+static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
 static struct resource bfin_twi0_resource[] = {
        [0] = {
                .start = TWI0_REGBASE,
@@ -347,6 +349,9 @@ static struct platform_device i2c_bfin_twi_device = {
        .id            = 0,
        .num_resources = ARRAY_SIZE(bfin_twi0_resource),
        .resource      = bfin_twi0_resource,
+        .dev = {
+                .platform_data = &bfin_twi0_pins,
+        },
 };
 #endif
diff --git a/arch/blackfin/mach-bf537/boards/minotaur.c b/arch/blackfin/mach-bf537/boards/minotaur.c
index d2d71282618f..a10f90e444bc 100644
--- a/arch/blackfin/mach-bf537/boards/minotaur.c
+++ b/arch/blackfin/mach-bf537/boards/minotaur.c
@@ -386,6 +386,8 @@ static struct platform_device bfin_sir1_device = {
 #endif
 #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
+static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
 static struct resource bfin_twi0_resource[] = {
        [0] = {
                .start = TWI0_REGBASE,
@@ -404,6 +406,9 @@ static struct platform_device i2c_bfin_twi_device = {
        .id = 0,
        .num_resources = ARRAY_SIZE(bfin_twi0_resource),
        .resource = bfin_twi0_resource,
+        .dev = {
+                .platform_data = &bfin_twi0_pins,
+        },
 };
 #endif
diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c
index f3562b0922af..c9d9473a5ab2 100644
--- a/arch/blackfin/mach-bf537/boards/stamp.c
+++ b/arch/blackfin/mach-bf537/boards/stamp.c
@@ -1790,6 +1790,8 @@ static struct platform_device bfin_sir1_device = {
 #endif
 #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
+static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
 static struct resource bfin_twi0_resource[] = {
        [0] = {
                .start = TWI0_REGBASE,
@@ -1808,6 +1810,9 @@ static struct platform_device i2c_bfin_twi_device = {
        .id = 0,
        .num_resources = ARRAY_SIZE(bfin_twi0_resource),
        .resource = bfin_twi0_resource,
+        .dev = {
+                .platform_data = &bfin_twi0_pins,
+        },
 };
 #endif
@@ -2361,7 +2366,13 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
        },
 #endif
 };
+#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) \
+|| defined(CONFIG_BFIN_SPORT) || defined(CONFIG_BFIN_SPORT_MODULE)
+unsigned short bfin_sport0_peripherals[] = {
+        P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
+        P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
+};
+#endif
 #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
 static struct resource bfin_sport0_uart_resources[] = {
@@ -2382,11 +2393,6 @@ static struct resource bfin_sport0_uart_resources[] = {
        },
 };
-static unsigned short bfin_sport0_peripherals[] = {
-        P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
-        P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
-};
 static struct platform_device bfin_sport0_uart_device = {
        .name = "bfin-sport-uart",
        .id = 0,
@@ -2432,7 +2438,49 @@ static struct platform_device bfin_sport1_uart_device = {
 };
 #endif
 #endif
+#if defined(CONFIG_BFIN_SPORT) || defined(CONFIG_BFIN_SPORT_MODULE)
+static struct resource bfin_sport0_resources[] = {
+        {
+                .start = SPORT0_TCR1,
+                .end = SPORT0_MRCS3+4,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = IRQ_SPORT0_RX,
+                .end = IRQ_SPORT0_RX+1,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = IRQ_SPORT0_TX,
+                .end = IRQ_SPORT0_TX+1,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = IRQ_SPORT0_ERROR,
+                .end = IRQ_SPORT0_ERROR,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = CH_SPORT0_TX,
+                .end = CH_SPORT0_TX,
+                .flags = IORESOURCE_DMA,
+        },
+        {
+                .start = CH_SPORT0_RX,
+                .end = CH_SPORT0_RX,
+                .flags = IORESOURCE_DMA,
+        },
+};
+static struct platform_device bfin_sport0_device = {
+        .name = "bfin_sport_raw",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(bfin_sport0_resources),
+        .resource = bfin_sport0_resources,
+        .dev = {
+                .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
+        },
+};
+#endif
 #if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
 #define CF_IDE_NAND_CARD_USE_HDD_INTERFACE
 /* #define CF_IDE_NAND_CARD_USE_CF_IN_COMMON_MEMORY_MODE */
@@ -2754,7 +2802,9 @@ static struct platform_device bf5xx_adau1701_device = {
 static struct platform_device *stamp_devices[] __initdata = {
        &bfin_dpmc,
+#if defined(CONFIG_BFIN_SPORT) || defined(CONFIG_BFIN_SPORT_MODULE)
+        &bfin_sport0_device,
+#endif
 #if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
        &bfin_pcmcia_cf_device,
 #endif
diff --git a/arch/blackfin/mach-bf537/boards/tcm_bf537.c b/arch/blackfin/mach-bf537/boards/tcm_bf537.c
index 3fb421823857..e285c3675286 100644
--- a/arch/blackfin/mach-bf537/boards/tcm_bf537.c
+++ b/arch/blackfin/mach-bf537/boards/tcm_bf537.c
@@ -453,6 +453,8 @@ static struct platform_device bfin_sir1_device = {
 #endif
 #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
+static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
 static struct resource bfin_twi0_resource[] = {
        [0] = {
                .start = TWI0_REGBASE,
@@ -471,6 +473,9 @@ static struct platform_device i2c_bfin_twi_device = {
        .id = 0,
        .num_resources = ARRAY_SIZE(bfin_twi0_resource),
        .resource = bfin_twi0_resource,
+        .dev = {
+                .platform_data = &bfin_twi0_pins,
+        },
 };
 #endif
diff --git a/arch/blackfin/mach-bf537/include/mach/anomaly.h b/arch/blackfin/mach-bf537/include/mach/anomaly.h
index 543cd3fb305e..df9212696397 100644
--- a/arch/blackfin/mach-bf537/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf537/include/mach/anomaly.h
@@ -6,8 +6,7 @@
 * DO NOT EDIT THIS FILE
 *
 * Copyright 2004-2011 Analog Devices Inc.
- * Licensed under the ADI BSD license.
+ * Licensed under the Clear BSD license.
- *   https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
 */
 /* This file should be up to date with:
diff --git a/arch/blackfin/mach-bf537/include/mach/defBF534.h b/arch/blackfin/mach-bf537/include/mach/defBF534.h
index 4a031dde173f..ef6a98cdfd44 100644
--- a/arch/blackfin/mach-bf537/include/mach/defBF534.h
+++ b/arch/blackfin/mach-bf537/include/mach/defBF534.h
@@ -1,7 +1,7 @@
 /*
 * Copyright 2005-2010 Analog Devices Inc.
 *
- * Licensed under the ADI BSD license or the GPL-2 (or later)
+ * Licensed under the Clear BSD license or the GPL-2 (or later)
 */
 #ifndef _DEF_BF534_H
@@ -1403,75 +1403,6 @@
 #define ERR_DET                 0x4000  /* Error Detected Indicator                     */
 #define ERR_NCOR                0x8000  /* Error Not Corrected Indicator        */
-/*  ********************  TWO-WIRE INTERFACE (TWI) MASKS  ***********************/
-/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y);  )                                */
-#define CLKLOW(x)       ((x) & 0xFF)    /* Periods Clock Is Held Low                    */
-#define CLKHI(y)        (((y)&0xFF)<<0x8)       /* Periods Before New Clock Low                 */
-/* TWI_PRESCALE Masks                                                                                                                   */
-#define PRESCALE        0x007F  /* SCLKs Per Internal Time Reference (10MHz)    */
-#define TWI_ENA         0x0080  /* TWI Enable                                                                   */
-#define SCCB            0x0200  /* SCCB Compatibility Enable                                    */
-/* TWI_SLAVE_CTL Masks                                                                                                                  */
-#define SEN                     0x0001  /* Slave Enable                                                                 */
-#define SADD_LEN        0x0002  /* Slave Address Length                                                 */
-#define STDVAL          0x0004  /* Slave Transmit Data Valid                                    */
-#define NAK                     0x0008  /* NAK/ACK* Generated At Conclusion Of Transfer */
-#define GEN                     0x0010  /* General Call Address Matching Enabled                */
-/* TWI_SLAVE_STAT Masks                                                                                                                 */
-#define SDIR            0x0001  /* Slave Transfer Direction (Transmit/Receive*) */
-#define GCALL           0x0002  /* General Call Indicator                                               */
-/* TWI_MASTER_CTL Masks                                                                                                 */
-#define MEN                     0x0001  /* Master Mode Enable                                           */
-#define MADD_LEN        0x0002  /* Master Address Length                                        */
-#define MDIR            0x0004  /* Master Transmit Direction (RX/TX*)           */
-#define FAST            0x0008  /* Use Fast Mode Timing Specs                           */
-#define STOP            0x0010  /* Issue Stop Condition                                         */
-#define RSTART          0x0020  /* Repeat Start or Stop* At End Of Transfer     */
-#define DCNT            0x3FC0  /* Data Bytes To Transfer                                       */
-#define SDAOVR          0x4000  /* Serial Data Override                                         */
-#define SCLOVR          0x8000  /* Serial Clock Override                                        */
-/* TWI_MASTER_STAT Masks                                                                                                                */
-#define MPROG           0x0001  /* Master Transfer In Progress                                  */
-#define LOSTARB         0x0002  /* Lost Arbitration Indicator (Xfer Aborted)    */
-#define ANAK            0x0004  /* Address Not Acknowledged                                             */
-#define DNAK            0x0008  /* Data Not Acknowledged                                                */
-#define BUFRDERR        0x0010  /* Buffer Read Error                                                    */
-#define BUFWRERR        0x0020  /* Buffer Write Error                                                   */
-#define SDASEN          0x0040  /* Serial Data Sense                                                    */
-#define SCLSEN          0x0080  /* Serial Clock Sense                                                   */
-#define BUSBUSY         0x0100  /* Bus Busy Indicator                                                   */
-/* TWI_INT_SRC and TWI_INT_ENABLE Masks                                         */
-#define SINIT           0x0001  /* Slave Transfer Initiated     */
-#define SCOMP           0x0002  /* Slave Transfer Complete      */
-#define SERR            0x0004  /* Slave Transfer Error         */
-#define SOVF            0x0008  /* Slave Overflow                       */
-#define MCOMP           0x0010  /* Master Transfer Complete     */
-#define MERR            0x0020  /* Master Transfer Error        */
-#define XMTSERV         0x0040  /* Transmit FIFO Service        */
-#define RCVSERV         0x0080  /* Receive FIFO Service         */
-/* TWI_FIFO_CTRL Masks                                                                                          */
-#define XMTFLUSH        0x0001  /* Transmit Buffer Flush                        */
-#define RCVFLUSH        0x0002  /* Receive Buffer Flush                         */
-#define XMTINTLEN       0x0004  /* Transmit Buffer Interrupt Length     */
-#define RCVINTLEN       0x0008  /* Receive Buffer Interrupt Length      */
-/* TWI_FIFO_STAT Masks                                                                                                                  */
-#define XMTSTAT         0x0003  /* Transmit FIFO Status                                                 */
-#define XMT_EMPTY       0x0000  /*              Transmit FIFO Empty                                             */
-#define XMT_HALF        0x0001  /*              Transmit FIFO Has 1 Byte To Write               */
-#define XMT_FULL        0x0003  /*              Transmit FIFO Full (2 Bytes To Write)   */
-#define RCVSTAT         0x000C  /* Receive FIFO Status                                                  */
-#define RCV_EMPTY       0x0000  /*              Receive FIFO Empty                                              */
-#define RCV_HALF        0x0004  /*              Receive FIFO Has 1 Byte To Read                 */
-#define RCV_FULL        0x000C  /*              Receive FIFO Full (2 Bytes To Read)             */
 /*  *******************  PIN CONTROL REGISTER MASKS  ************************/
 /* PORT_MUX Masks                                                                                                                       */
diff --git a/arch/blackfin/mach-bf537/include/mach/defBF537.h b/arch/blackfin/mach-bf537/include/mach/defBF537.h
index 3d471d752684..e10332c9f660 100644
--- a/arch/blackfin/mach-bf537/include/mach/defBF537.h
+++ b/arch/blackfin/mach-bf537/include/mach/defBF537.h
@@ -1,7 +1,7 @@
 /*
 * Copyright 2005-2010 Analog Devices Inc.
 *
- * Licensed under the ADI BSD license or the GPL-2 (or later)
+ * Licensed under the Clear BSD license or the GPL-2 (or later)
 */
 #ifndef _DEF_BF537_H
diff --git a/arch/blackfin/mach-bf538/boards/ezkit.c b/arch/blackfin/mach-bf538/boards/ezkit.c
index 1633a6f306c0..a4fce0370c1d 100644
--- a/arch/blackfin/mach-bf538/boards/ezkit.c
+++ b/arch/blackfin/mach-bf538/boards/ezkit.c
@@ -38,7 +38,7 @@ static struct platform_device rtc_device = {
        .name = "rtc-bfin",
        .id   = -1,
 };
-#endif
+#endif  /* CONFIG_RTC_DRV_BFIN */
 #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
 #ifdef CONFIG_SERIAL_BFIN_UART0
@@ -100,7 +100,7 @@ static struct platform_device bfin_uart0_device = {
                .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
        },
 };
-#endif
+#endif  /* CONFIG_SERIAL_BFIN_UART0 */
 #ifdef CONFIG_SERIAL_BFIN_UART1
 static struct resource bfin_uart1_resources[] = {
        {
@@ -148,7 +148,7 @@ static struct platform_device bfin_uart1_device = {
                .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
        },
 };
-#endif
+#endif  /* CONFIG_SERIAL_BFIN_UART1 */
 #ifdef CONFIG_SERIAL_BFIN_UART2
 static struct resource bfin_uart2_resources[] = {
        {
@@ -196,8 +196,8 @@ static struct platform_device bfin_uart2_device = {
                .platform_data = &bfin_uart2_peripherals, /* Passed to driver */
        },
 };
-#endif
+#endif  /* CONFIG_SERIAL_BFIN_UART2 */
-#endif
+#endif  /* CONFIG_SERIAL_BFIN */
 #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
 #ifdef CONFIG_BFIN_SIR0
@@ -224,7 +224,7 @@ static struct platform_device bfin_sir0_device = {
        .num_resources = ARRAY_SIZE(bfin_sir0_resources),
        .resource = bfin_sir0_resources,
 };
-#endif
+#endif  /* CONFIG_BFIN_SIR0 */
 #ifdef CONFIG_BFIN_SIR1
 static struct resource bfin_sir1_resources[] = {
        {
@@ -249,7 +249,7 @@ static struct platform_device bfin_sir1_device = {
        .num_resources = ARRAY_SIZE(bfin_sir1_resources),
        .resource = bfin_sir1_resources,
 };
-#endif
+#endif  /* CONFIG_BFIN_SIR1 */
 #ifdef CONFIG_BFIN_SIR2
 static struct resource bfin_sir2_resources[] = {
        {
@@ -274,8 +274,8 @@ static struct platform_device bfin_sir2_device = {
        .num_resources = ARRAY_SIZE(bfin_sir2_resources),
        .resource = bfin_sir2_resources,
 };
-#endif
+#endif  /* CONFIG_BFIN_SIR2 */
-#endif
+#endif  /* CONFIG_BFIN_SIR */
 #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
@@ -311,7 +311,7 @@ static struct platform_device bfin_sport0_uart_device = {
                .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
        },
 };
-#endif
+#endif  /* CONFIG_SERIAL_BFIN_SPORT0_UART */
 #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
 static struct resource bfin_sport1_uart_resources[] = {
        {
@@ -345,7 +345,7 @@ static struct platform_device bfin_sport1_uart_device = {
                .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
        },
 };
-#endif
+#endif  /* CONFIG_SERIAL_BFIN_SPORT1_UART */
 #ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
 static struct resource bfin_sport2_uart_resources[] = {
        {
@@ -379,7 +379,7 @@ static struct platform_device bfin_sport2_uart_device = {
                .platform_data = &bfin_sport2_peripherals, /* Passed to driver */
        },
 };
-#endif
+#endif  /* CONFIG_SERIAL_BFIN_SPORT2_UART */
 #ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
 static struct resource bfin_sport3_uart_resources[] = {
        {
@@ -413,8 +413,8 @@ static struct platform_device bfin_sport3_uart_device = {
                .platform_data = &bfin_sport3_peripherals, /* Passed to driver */
        },
 };
-#endif
+#endif  /* CONFIG_SERIAL_BFIN_SPORT3_UART */
-#endif
+#endif  /* CONFIG_SERIAL_BFIN_SPORT */
 #if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
 static unsigned short bfin_can_peripherals[] = {
@@ -452,7 +452,7 @@ static struct platform_device bfin_can_device = {
                .platform_data = &bfin_can_peripherals, /* Passed to driver */
        },
 };
-#endif
+#endif  /* CONFIG_CAN_BFIN */
 /*
 *  USB-LAN EzExtender board
@@ -488,7 +488,7 @@ static struct platform_device smc91x_device = {
                .platform_data  = &smc91x_info,
        },
 };
-#endif
+#endif  /* CONFIG_SMC91X */
 #if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
 /* all SPI peripherals info goes here */
@@ -518,7 +518,8 @@ static struct flash_platform_data bfin_spi_flash_data = {
 static struct bfin5xx_spi_chip spi_flash_chip_info = {
        .enable_dma = 0,         /* use dma transfer with this chip*/
 };
-#endif
+#endif  /* CONFIG_MTD_M25P80 */
+#endif  /* CONFIG_SPI_BFIN5XX */
 #if defined(CONFIG_TOUCHSCREEN_AD7879) || defined(CONFIG_TOUCHSCREEN_AD7879_MODULE)
 #include <linux/spi/ad7879.h>
@@ -535,7 +536,7 @@ static const struct ad7879_platform_data bfin_ad7879_ts_info = {
        .gpio_export            = 1,    /* Export GPIO to gpiolib */
        .gpio_base              = -1,   /* Dynamic allocation */
 };
-#endif
+#endif  /* CONFIG_TOUCHSCREEN_AD7879 */
 #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
 #include <asm/bfin-lq035q1.h>
@@ -564,7 +565,7 @@ static struct platform_device bfin_lq035q1_device = {
                .platform_data = &bfin_lq035q1_data,
        },
 };
-#endif
+#endif  /* CONFIG_FB_BFIN_LQ035Q1 */
 static struct spi_board_info bf538_spi_board_info[] __initdata = {
 #if defined(CONFIG_MTD_M25P80) \
@@ -579,7 +580,7 @@ static struct spi_board_info bf538_spi_board_info[] __initdata = {
                .controller_data = &spi_flash_chip_info,
                .mode = SPI_MODE_3,
        },
-#endif
+#endif  /* CONFIG_MTD_M25P80 */
 #if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
        {
                .modalias = "ad7879",
@@ -590,7 +591,7 @@ static struct spi_board_info bf538_spi_board_info[] __initdata = {
                .chip_select = 1,
                .mode = SPI_CPHA | SPI_CPOL,
        },
-#endif
+#endif  /* CONFIG_TOUCHSCREEN_AD7879_SPI */
 #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
        {
                .modalias = "bfin-lq035q1-spi",
@@ -599,7 +600,7 @@ static struct spi_board_info bf538_spi_board_info[] __initdata = {
                .chip_select = 2,
                .mode = SPI_CPHA | SPI_CPOL,
        },
-#endif
+#endif  /* CONFIG_FB_BFIN_LQ035Q1 */
 #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
        {
                .modalias = "spidev",
@@ -607,7 +608,7 @@ static struct spi_board_info bf538_spi_board_info[] __initdata = {
                .bus_num = 0,
                .chip_select = 1,
        },
-#endif
+#endif  /* CONFIG_SPI_SPIDEV */
 };
 /* SPI (0) */
@@ -716,9 +717,9 @@ static struct platform_device bf538_spi_master2 = {
                },
 };
-#endif  /* spi master and devices */
 #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
+static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
 static struct resource bfin_twi0_resource[] = {
        [0] = {
                .start = TWI0_REGBASE,
@@ -737,9 +738,13 @@ static struct platform_device i2c_bfin_twi0_device = {
        .id = 0,
        .num_resources = ARRAY_SIZE(bfin_twi0_resource),
        .resource = bfin_twi0_resource,
+        .dev = {
+                .platform_data = &bfin_twi0_pins,
+        },
 };
-#if !defined(CONFIG_BF542)      /* The BF542 only has 1 TWI */
+static const u16 bfin_twi1_pins[] = {P_TWI1_SCL, P_TWI1_SDA, 0};
 static struct resource bfin_twi1_resource[] = {
        [0] = {
                .start = TWI1_REGBASE,
@@ -759,8 +764,8 @@ static struct platform_device i2c_bfin_twi1_device = {
        .num_resources = ARRAY_SIZE(bfin_twi1_resource),
        .resource = bfin_twi1_resource,
 };
-#endif
+#endif  /* CONFIG_BF542 */
-#endif
+#endif  /* CONFIG_I2C_BLACKFIN_TWI */
 #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
 #include <linux/gpio_keys.h>
diff --git a/arch/blackfin/mach-bf538/include/mach/anomaly.h b/arch/blackfin/mach-bf538/include/mach/anomaly.h
index b6ca99788710..318d922d11d4 100644
--- a/arch/blackfin/mach-bf538/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf538/include/mach/anomaly.h
@@ -6,8 +6,7 @@
 * DO NOT EDIT THIS FILE
 *
 * Copyright 2004-2011 Analog Devices Inc.
- * Licensed under the ADI BSD license.
+ * Licensed under the Clear BSD license.
- *   https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
 */
 /* This file should be up to date with:
diff --git a/arch/blackfin/mach-bf538/include/mach/defBF538.h b/arch/blackfin/mach-bf538/include/mach/defBF538.h
index d27f81d6c4b1..876a77028001 100644
--- a/arch/blackfin/mach-bf538/include/mach/defBF538.h
+++ b/arch/blackfin/mach-bf538/include/mach/defBF538.h
@@ -1,7 +1,7 @@
 /*
 * Copyright 2008-2010 Analog Devices Inc.
 *
- * Licensed under the ADI BSD license or the GPL-2 (or later)
+ * Licensed under the Clear BSD license or the GPL-2 (or later)
 */
 #ifndef _DEF_BF538_H
@@ -1746,80 +1746,4 @@
 #define SDEASE                  0x00000010 /* SDRAM EAB sticky error status - W1C */
 #define BGSTAT                  0x00000020 /* Bus granted */
-/*  ********************  TWO-WIRE INTERFACE (TWIx) MASKS  ***********************/
-/* TWIx_CLKDIV Macros (Use: *pTWIx_CLKDIV = CLKLOW(x)|CLKHI(y);  ) */
-#ifdef _MISRA_RULES
-#define CLKLOW(x)       ((x) & 0xFFu)           /* Periods Clock Is Held Low */
-#define CLKHI(y)        (((y)&0xFFu)<<0x8)      /* Periods Before New Clock Low */
-#else
-#define CLKLOW(x)       ((x) & 0xFF)            /* Periods Clock Is Held Low */
-#define CLKHI(y)        (((y)&0xFF)<<0x8)       /* Periods Before New Clock Low */
-#endif /* _MISRA_RULES */
-/* TWIx_PRESCALE Masks                                                           */
-#define PRESCALE        0x007F          /* SCLKs Per Internal Time Reference (10MHz) */
-#define TWI_ENA         0x0080          /* TWI Enable            */
-#define SCCB            0x0200          /* SCCB Compatibility Enable */
-/* TWIx_SLAVE_CTRL Masks                                                                 */
-#define SEN                     0x0001          /* Slave Enable          */
-#define SADD_LEN        0x0002          /* Slave Address Length */
-#define STDVAL          0x0004          /* Slave Transmit Data Valid */
-#define NAK                     0x0008          /* NAK/ACK* Generated At Conclusion Of Transfer */
-#define GEN                     0x0010          /* General Call Adrress Matching Enabled */
-/* TWIx_SLAVE_STAT Masks                                                                 */
-#define SDIR            0x0001          /* Slave Transfer Direction (Transmit/Receive*) */
-#define GCALL           0x0002          /* General Call Indicator */
-/* TWIx_MASTER_CTRL Masks                                                */
-#define MEN                     0x0001          /* Master Mode Enable */
-#define MADD_LEN        0x0002          /* Master Address Length */
-#define MDIR            0x0004          /* Master Transmit Direction (RX/TX*) */
-#define FAST            0x0008          /* Use Fast Mode Timing Specs */
-#define STOP            0x0010          /* Issue Stop Condition */
-#define RSTART          0x0020          /* Repeat Start or Stop* At End Of Transfer */
-#define DCNT            0x3FC0          /* Data Bytes To Transfer */
-#define SDAOVR          0x4000          /* Serial Data Override */
-#define SCLOVR          0x8000          /* Serial Clock Override */
-/* TWIx_MASTER_STAT Masks                                                        */
-#define MPROG           0x0001          /* Master Transfer In Progress */
-#define LOSTARB         0x0002          /* Lost Arbitration Indicator (Xfer Aborted) */
-#define ANAK            0x0004          /* Address Not Acknowledged */
-#define DNAK            0x0008          /* Data Not Acknowledged */
-#define BUFRDERR        0x0010          /* Buffer Read Error */
-#define BUFWRERR        0x0020          /* Buffer Write Error */
-#define SDASEN          0x0040          /* Serial Data Sense */
-#define SCLSEN          0x0080          /* Serial Clock Sense */
-#define BUSBUSY         0x0100          /* Bus Busy Indicator */
-/* TWIx_INT_SRC and TWIx_INT_ENABLE Masks */
-#define SINIT           0x0001          /* Slave Transfer Initiated */
-#define SCOMP           0x0002          /* Slave Transfer Complete */
-#define SERR            0x0004          /* Slave Transfer Error */
-#define SOVF            0x0008          /* Slave Overflow */
-#define MCOMP           0x0010          /* Master Transfer Complete */
-#define MERR            0x0020          /* Master Transfer Error */
-#define XMTSERV         0x0040          /* Transmit FIFO Service */
-#define RCVSERV         0x0080          /* Receive FIFO Service */
-/* TWIx_FIFO_CTL Masks                                   */
-#define XMTFLUSH        0x0001          /* Transmit Buffer Flush */
-#define RCVFLUSH        0x0002          /* Receive Buffer Flush */
-#define XMTINTLEN       0x0004          /* Transmit Buffer Interrupt Length */
-#define RCVINTLEN       0x0008          /* Receive Buffer Interrupt Length */
-/* TWIx_FIFO_STAT Masks                                                          */
-#define XMTSTAT         0x0003          /* Transmit FIFO Status */
-#define XMT_EMPTY       0x0000          /*              Transmit FIFO Empty */
-#define XMT_HALF        0x0001          /*              Transmit FIFO Has 1 Byte To Write */
-#define XMT_FULL        0x0003          /*              Transmit FIFO Full (2 Bytes To Write) */
-#define RCVSTAT         0x000C          /* Receive FIFO Status */
-#define RCV_EMPTY       0x0000          /*              Receive FIFO Empty */
-#define RCV_HALF        0x0004          /*              Receive FIFO Has 1 Byte To Read */
-#define RCV_FULL        0x000C          /*              Receive FIFO Full (2 Bytes To Read) */
 #endif
diff --git a/arch/blackfin/mach-bf538/include/mach/defBF539.h b/arch/blackfin/mach-bf538/include/mach/defBF539.h
index 8100bcd01a0d..199e871634b4 100644
--- a/arch/blackfin/mach-bf538/include/mach/defBF539.h
+++ b/arch/blackfin/mach-bf538/include/mach/defBF539.h
@@ -1,7 +1,7 @@
 /*
 * Copyright 2008-2010 Analog Devices Inc.
 *
- * Licensed under the ADI BSD license or the GPL-2 (or later)
+ * Licensed under the Clear BSD license or the GPL-2 (or later)
 */
 #ifndef _DEF_BF539_H
diff --git a/arch/blackfin/mach-bf548/boards/cm_bf548.c b/arch/blackfin/mach-bf548/boards/cm_bf548.c
index 68af594db48e..e92543362f35 100644
--- a/arch/blackfin/mach-bf548/boards/cm_bf548.c
+++ b/arch/blackfin/mach-bf548/boards/cm_bf548.c
@@ -1007,6 +1007,8 @@ static struct platform_device bf54x_spi_master1 = {
 #endif  /* spi master and devices */
 #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
+static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
 static struct resource bfin_twi0_resource[] = {
        [0] = {
                .start = TWI0_REGBASE,
@@ -1025,9 +1027,14 @@ static struct platform_device i2c_bfin_twi0_device = {
        .id = 0,
        .num_resources = ARRAY_SIZE(bfin_twi0_resource),
        .resource = bfin_twi0_resource,
+        .dev = {
+                .platform_data = &bfin_twi0_pins,
+        },
 };
 #if !defined(CONFIG_BF542)      /* The BF542 only has 1 TWI */
+static const u16 bfin_twi1_pins[] = {P_TWI1_SCL, P_TWI1_SDA, 0};
 static struct resource bfin_twi1_resource[] = {
        [0] = {
                .start = TWI1_REGBASE,
@@ -1046,6 +1053,9 @@ static struct platform_device i2c_bfin_twi1_device = {
        .id = 1,
        .num_resources = ARRAY_SIZE(bfin_twi1_resource),
        .resource = bfin_twi1_resource,
+        .dev = {
+                .platform_data = &bfin_twi1_pins,
+        },
 };
 #endif
 #endif
diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c
index 4cadaf8d0b56..3bd75bae750d 100644
--- a/arch/blackfin/mach-bf548/boards/ezkit.c
+++ b/arch/blackfin/mach-bf548/boards/ezkit.c
@@ -165,6 +165,7 @@ static struct bfin_rotary_platform_data bfin_rotary_data = {
        .rotary_button_key = KEY_ENTER,
        .debounce          = 10,        /* 0..17 */
        .mode              = ROT_QUAD_ENC | ROT_DEBE,
+        .pm_wakeup         = 1,
 };
 static struct resource bfin_rotary_resources[] = {
@@ -1251,6 +1252,8 @@ static struct platform_device bfin_capture_device = {
 #endif
 #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
+static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
 static struct resource bfin_twi0_resource[] = {
        [0] = {
                .start = TWI0_REGBASE,
@@ -1269,9 +1272,14 @@ static struct platform_device i2c_bfin_twi0_device = {
        .id = 0,
        .num_resources = ARRAY_SIZE(bfin_twi0_resource),
        .resource = bfin_twi0_resource,
+        .dev = {
+                .platform_data = &bfin_twi0_pins,
+        },
 };
 #if !defined(CONFIG_BF542)      /* The BF542 only has 1 TWI */
+static const u16 bfin_twi1_pins[] = {P_TWI1_SCL, P_TWI1_SDA, 0};
 static struct resource bfin_twi1_resource[] = {
        [0] = {
                .start = TWI1_REGBASE,
@@ -1290,6 +1298,9 @@ static struct platform_device i2c_bfin_twi1_device = {
        .id = 1,
        .num_resources = ARRAY_SIZE(bfin_twi1_resource),
        .resource = bfin_twi1_resource,
+        .dev = {
+                .platform_data = &bfin_twi1_pins,
+        },
 };
 #endif
 #endif
diff --git a/arch/blackfin/mach-bf548/include/mach/anomaly.h b/arch/blackfin/mach-bf548/include/mach/anomaly.h
index ac96ee83b00e..5b711d85b90b 100644
--- a/arch/blackfin/mach-bf548/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf548/include/mach/anomaly.h
@@ -6,8 +6,7 @@
 * DO NOT EDIT THIS FILE
 *
 * Copyright 2004-2011 Analog Devices Inc.
- * Licensed under the ADI BSD license.
+ * Licensed under the Clear BSD license.
- *   https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
 */
 /* This file should be up to date with:
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF542.h b/arch/blackfin/mach-bf548/include/mach/defBF542.h
index 629bf216e2b5..51161575a163 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF542.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF542.h
@@ -1,7 +1,7 @@
 /*
 * Copyright 2007-2010 Analog Devices Inc.
 *
- * Licensed under the ADI BSD license or the GPL-2 (or later)
+ * Licensed under the Clear BSD license or the GPL-2 (or later)
 */
 #ifndef _DEF_BF542_H
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF544.h b/arch/blackfin/mach-bf548/include/mach/defBF544.h
index bcccab36629c..329b2c58228b 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF544.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF544.h
@@ -1,7 +1,7 @@
 /*
 * Copyright 2007-2010 Analog Devices Inc.
 *
- * Licensed under the ADI BSD license or the GPL-2 (or later)
+ * Licensed under the Clear BSD license or the GPL-2 (or later)
 */
 #ifndef _DEF_BF544_H
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF547.h b/arch/blackfin/mach-bf548/include/mach/defBF547.h
index 1fa41ec03f31..e18de212ba1a 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF547.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF547.h
@@ -1,7 +1,7 @@
 /*
 * Copyright 2008-2010 Analog Devices Inc.
 *
- * Licensed under the ADI BSD license or the GPL-2 (or later)
+ * Licensed under the Clear BSD license or the GPL-2 (or later)
 */
 #ifndef _DEF_BF547_H
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF548.h b/arch/blackfin/mach-bf548/include/mach/defBF548.h
index 3c7f1b69349e..27f29481e283 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF548.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF548.h
@@ -1,7 +1,7 @@
 /*
 * Copyright 2007-2010 Analog Devices Inc.
 *
- * Licensed under the ADI BSD license or the GPL-2 (or later)
+ * Licensed under the Clear BSD license or the GPL-2 (or later)
 */
 #ifndef _DEF_BF548_H
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF549.h b/arch/blackfin/mach-bf548/include/mach/defBF549.h
index 9a45cb6b30da..ac569fc12972 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF549.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF549.h
@@ -1,7 +1,7 @@
 /*
 * Copyright 2007-2010 Analog Devices Inc.
 *
- * Licensed under the ADI BSD license or the GPL-2 (or later)
+ * Licensed under the Clear BSD license or the GPL-2 (or later)
 */
 #ifndef _DEF_BF549_H
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
index 0867c2bedb43..8f6e1925779d 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
@@ -1,7 +1,7 @@
 /*
 * Copyright 2007-2010 Analog Devices Inc.
 *
- * Licensed under the ADI BSD license or the GPL-2 (or later)
+ * Licensed under the Clear BSD license or the GPL-2 (or later)
 */
 #ifndef _DEF_BF54X_H
@@ -2062,115 +2062,6 @@
 #define                  LOW_EVEN  0xff0000   /* Lower Limit for Even Bytes (Luma) */
 #define                 HIGH_EVEN  0xff000000 /* Upper Limit for Even Bytes (Luma) */
-/* ************************************************ */
-/* The TWI bit masks fields are from the ADSP-BF538 */
-/* and they have not been verified as the final     */
-/* ones for the Moab processors ... bz 1/19/2007    */
-/* ************************************************ */
-/* Bit masks for TWIx_CONTROL */
-#define                  PRESCALE  0x7f       /* Prescale Value */
-#define                   TWI_ENA  0x80       /* TWI Enable */
-#define                      SCCB  0x200      /* Serial Camera Control Bus */
-/* Bit maskes for TWIx_CLKDIV */
-#define                    CLKLOW  0xff       /* Clock Low */
-#define                     CLKHI  0xff00     /* Clock High */
-/* Bit maskes for TWIx_SLAVE_CTL */
-#define                       SEN  0x1        /* Slave Enable */
-#define                    STDVAL  0x4        /* Slave Transmit Data Valid */
-#define                       NAK  0x8        /* Not Acknowledge */
-#define                       GEN  0x10       /* General Call Enable */
-/* Bit maskes for TWIx_SLAVE_ADDR */
-#define                     SADDR  0x7f       /* Slave Mode Address */
-/* Bit maskes for TWIx_SLAVE_STAT */
-#define                      SDIR  0x1        /* Slave Transfer Direction */
-#define                     GCALL  0x2        /* General Call */
-/* Bit maskes for TWIx_MASTER_CTL */
-#define                       MEN  0x1        /* Master Mode Enable */
-#define                      MDIR  0x4        /* Master Transfer Direction */
-#define                      FAST  0x8        /* Fast Mode */
-#define                      STOP  0x10       /* Issue Stop Condition */
-#define                    RSTART  0x20       /* Repeat Start */
-#define                      DCNT  0x3fc0     /* Data Transfer Count */
-#define                    SDAOVR  0x4000     /* Serial Data Override */
-#define                    SCLOVR  0x8000     /* Serial Clock Override */
-/* Bit maskes for TWIx_MASTER_ADDR */
-#define                     MADDR  0x7f       /* Master Mode Address */
-/* Bit maskes for TWIx_MASTER_STAT */
-#define                     MPROG  0x1        /* Master Transfer in Progress */
-#define                   LOSTARB  0x2        /* Lost Arbitration */
-#define                      ANAK  0x4        /* Address Not Acknowledged */
-#define                      DNAK  0x8        /* Data Not Acknowledged */
-#define                  BUFRDERR  0x10       /* Buffer Read Error */
-#define                  BUFWRERR  0x20       /* Buffer Write Error */
-#define                    SDASEN  0x40       /* Serial Data Sense */
-#define                    SCLSEN  0x80       /* Serial Clock Sense */
-#define                   BUSBUSY  0x100      /* Bus Busy */
-/* Bit maskes for TWIx_FIFO_CTL */
-#define                  XMTFLUSH  0x1        /* Transmit Buffer Flush */
-#define                  RCVFLUSH  0x2        /* Receive Buffer Flush */
-#define                 XMTINTLEN  0x4        /* Transmit Buffer Interrupt Length */
-#define                 RCVINTLEN  0x8        /* Receive Buffer Interrupt Length */
-/* Bit maskes for TWIx_FIFO_STAT */
-#define                   XMTSTAT  0x3        /* Transmit FIFO Status */
-#define                   RCVSTAT  0xc        /* Receive FIFO Status */
-/* Bit maskes for TWIx_INT_MASK */
-#define                    SINITM  0x1        /* Slave Transfer Initiated Interrupt Mask */
-#define                    SCOMPM  0x2        /* Slave Transfer Complete Interrupt Mask */
-#define                     SERRM  0x4        /* Slave Transfer Error Interrupt Mask */
-#define                     SOVFM  0x8        /* Slave Overflow Interrupt Mask */
-#define                    MCOMPM  0x10       /* Master Transfer Complete Interrupt Mask */
-#define                     MERRM  0x20       /* Master Transfer Error Interrupt Mask */
-#define                  XMTSERVM  0x40       /* Transmit FIFO Service Interrupt Mask */
-#define                  RCVSERVM  0x80       /* Receive FIFO Service Interrupt Mask */
-/* Bit maskes for TWIx_INT_STAT */
-#define                     SINIT  0x1        /* Slave Transfer Initiated */
-#define                     SCOMP  0x2        /* Slave Transfer Complete */
-#define                      SERR  0x4        /* Slave Transfer Error */
-#define                      SOVF  0x8        /* Slave Overflow */
-#define                     MCOMP  0x10       /* Master Transfer Complete */
-#define                      MERR  0x20       /* Master Transfer Error */
-#define                   XMTSERV  0x40       /* Transmit FIFO Service */
-#define                   RCVSERV  0x80       /* Receive FIFO Service */
-/* Bit maskes for TWIx_XMT_DATA8 */
-#define                  XMTDATA8  0xff       /* Transmit FIFO 8-Bit Data */
-/* Bit maskes for TWIx_XMT_DATA16 */
-#define                 XMTDATA16  0xffff     /* Transmit FIFO 16-Bit Data */
-/* Bit maskes for TWIx_RCV_DATA8 */
-#define                  RCVDATA8  0xff       /* Receive FIFO 8-Bit Data */
-/* Bit maskes for TWIx_RCV_DATA16 */
-#define                 RCVDATA16  0xffff     /* Receive FIFO 16-Bit Data */
 /* ******************************************* */
 /*     MULTI BIT MACRO ENUMERATIONS            */
diff --git a/arch/blackfin/mach-bf561/include/mach/anomaly.h b/arch/blackfin/mach-bf561/include/mach/anomaly.h
index 836baeed303a..72476ff50335 100644
--- a/arch/blackfin/mach-bf561/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf561/include/mach/anomaly.h
@@ -6,8 +6,7 @@
 * DO NOT EDIT THIS FILE
 *
 * Copyright 2004-2011 Analog Devices Inc.
- * Licensed under the ADI BSD license.
+ * Licensed under the Clear BSD license.
- *   https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
 */
 /* This file should be up to date with:
diff --git a/arch/blackfin/mach-bf561/include/mach/defBF561.h b/arch/blackfin/mach-bf561/include/mach/defBF561.h
index 5f0ac5a77a37..9f21f768c63a 100644
--- a/arch/blackfin/mach-bf561/include/mach/defBF561.h
+++ b/arch/blackfin/mach-bf561/include/mach/defBF561.h
@@ -1,7 +1,7 @@
 /*
 * Copyright 2005-2010 Analog Devices Inc.
 *
- * Licensed under the ADI BSD license or the GPL-2 (or later)
+ * Licensed under the Clear BSD license or the GPL-2 (or later)
 */
 #ifndef _DEF_BF561_H
diff --git a/arch/blackfin/mach-bf609/Kconfig b/arch/blackfin/mach-bf609/Kconfig
new file mode 100644
index 000000000000..2cb727243778
--- /dev/null
+++ b/arch/blackfin/mach-bf609/Kconfig
@@ -0,0 +1,56 @@
+config BF60x
+        def_bool y
+        depends on (BF609)
+        select IRQ_PREFLOW_FASTEOI
+if (BF60x)
+source "arch/blackfin/mach-bf609/boards/Kconfig"
+menu "BF609 Specific Configuration"
+comment "Pin Interrupt to Port Assignment"
+menu "Assignment"
+config PINTx_REASSIGN
+        bool "Reprogram PINT Assignment"
+        default y
+        help
+          The interrupt assignment registers controls the pin-to-interrupt
+          assignment in a byte-wide manner. Each option allows you to select
+          a set of pins (High/Low Byte) of an specific Port being mapped
+          to one of the four PIN Interrupts IRQ_PINTx.
+          You shouldn't change any of these unless you know exactly what you're doing.
+          Please consult the Blackfin BF60x Processor Hardware Reference Manual.
+config PINT0_ASSIGN
+        hex "PINT0_ASSIGN"
+        depends on PINTx_REASSIGN
+        default 0x00000101
+config PINT1_ASSIGN
+        hex "PINT1_ASSIGN"
+        depends on PINTx_REASSIGN
+        default 0x00000101
+config PINT2_ASSIGN
+        hex "PINT2_ASSIGN"
+        depends on PINTx_REASSIGN
+        default 0x00000101
+config PINT3_ASSIGN
+        hex "PINT3_ASSIGN"
+        depends on PINTx_REASSIGN
+        default 0x00000101
+config PINT4_ASSIGN
+        hex "PINT3_ASSIGN"
+        depends on PINTx_REASSIGN
+        default 0x00000101
+config PINT5_ASSIGN
+        hex "PINT3_ASSIGN"
+        depends on PINTx_REASSIGN
+        default 0x00000101
+endmenu
+endmenu
+endif
diff --git a/arch/blackfin/mach-bf609/Makefile b/arch/blackfin/mach-bf609/Makefile
new file mode 100644
index 000000000000..2a27f8174543
--- /dev/null
+++ b/arch/blackfin/mach-bf609/Makefile
@@ -0,0 +1,6 @@
+#
+# arch/blackfin/mach-bf609/Makefile
+#
+obj-y := dma.o clock.o
+obj-$(CONFIG_PM) += pm.o hibernate.o
diff --git a/arch/blackfin/mach-bf609/boards/Kconfig b/arch/blackfin/mach-bf609/boards/Kconfig
new file mode 100644
index 000000000000..30e8b6b0d2ed
--- /dev/null
+++ b/arch/blackfin/mach-bf609/boards/Kconfig
@@ -0,0 +1,12 @@
+choice
+        prompt "System type"
+        default BFIN609_EZKIT
+        help
+          Select your board!
+config BFIN609_EZKIT
+        bool "BF609-EZKIT"
+        help
+          BFIN609-EZKIT board support.
+          
+endchoice
diff --git a/arch/blackfin/mach-bf609/boards/Makefile b/arch/blackfin/mach-bf609/boards/Makefile
new file mode 100644
index 000000000000..11f98b0882ea
--- /dev/null
+++ b/arch/blackfin/mach-bf609/boards/Makefile
@@ -0,0 +1,5 @@
+#
+# arch/blackfin/mach-bf609/boards/Makefile
+#
+obj-$(CONFIG_BFIN609_EZKIT)            += ezkit.o
diff --git a/arch/blackfin/mach-bf609/boards/ezkit.c b/arch/blackfin/mach-bf609/boards/ezkit.c
new file mode 100644
index 000000000000..ac64f47217c1
--- /dev/null
+++ b/arch/blackfin/mach-bf609/boards/ezkit.c
@@ -0,0 +1,1340 @@
+/*
+ * Copyright 2004-2009 Analog Devices Inc.
+ *                2005 National ICT Australia (NICTA)
+ *                      Aidan Williams <aidan@nicta.com.au>
+ *
+ * Licensed under the GPL-2 or later.
+ */
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/physmap.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/flash.h>
+#include <linux/irq.h>
+#include <linux/i2c.h>
+#include <linux/interrupt.h>
+#include <linux/usb/musb.h>
+#include <asm/bfin6xx_spi.h>
+#include <asm/dma.h>
+#include <asm/gpio.h>
+#include <asm/nand.h>
+#include <asm/dpmc.h>
+#include <asm/portmux.h>
+#include <asm/bfin_sdh.h>
+#include <linux/input.h>
+#include <linux/spi/ad7877.h>
+/*
+ * Name the Board for the /proc/cpuinfo
+ */
+const char bfin_board_name[] = "ADI BF609-EZKIT";
+/*
+ *  Driver needs to know address, irq and flag pin.
+ */
+#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
+#include <linux/usb/isp1760.h>
+static struct resource bfin_isp1760_resources[] = {
+        [0] = {
+                .start  = 0x2C0C0000,
+                .end    = 0x2C0C0000 + 0xfffff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_PG7,
+                .end    = IRQ_PG7,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct isp1760_platform_data isp1760_priv = {
+        .is_isp1761 = 0,
+        .bus_width_16 = 1,
+        .port1_otg = 0,
+        .analog_oc = 0,
+        .dack_polarity_high = 0,
+        .dreq_polarity_high = 0,
+};
+static struct platform_device bfin_isp1760_device = {
+        .name           = "isp1760",
+        .id             = 0,
+        .dev = {
+                .platform_data = &isp1760_priv,
+        },
+        .num_resources  = ARRAY_SIZE(bfin_isp1760_resources),
+        .resource       = bfin_isp1760_resources,
+};
+#endif
+#if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE)
+#include <asm/bfin_rotary.h>
+static struct bfin_rotary_platform_data bfin_rotary_data = {
+        /*.rotary_up_key     = KEY_UP,*/
+        /*.rotary_down_key   = KEY_DOWN,*/
+        .rotary_rel_code   = REL_WHEEL,
+        .rotary_button_key = KEY_ENTER,
+        .debounce          = 10,        /* 0..17 */
+        .mode              = ROT_QUAD_ENC | ROT_DEBE,
+};
+static struct resource bfin_rotary_resources[] = {
+        {
+                .start = IRQ_CNT,
+                .end = IRQ_CNT,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device bfin_rotary_device = {
+        .name           = "bfin-rotary",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(bfin_rotary_resources),
+        .resource       = bfin_rotary_resources,
+        .dev            = {
+                .platform_data = &bfin_rotary_data,
+        },
+};
+#endif
+#if defined(CONFIG_STMMAC_ETH) || defined(CONFIG_STMMAC_ETH_MODULE)
+#include <linux/stmmac.h>
+static unsigned short pins[] = P_RMII0;
+static struct stmmac_mdio_bus_data phy_private_data = {
+        .bus_id = 0,
+        .phy_mask = 1,
+};
+static struct plat_stmmacenet_data eth_private_data = {
+        .bus_id   = 0,
+        .enh_desc = 1,
+        .phy_addr = 1,
+        .mdio_bus_data = &phy_private_data,
+};
+static struct platform_device bfin_eth_device = {
+        .name           = "stmmaceth",
+        .id             = 0,
+        .num_resources  = 2,
+        .resource       = (struct resource[]) {
+                {
+                        .start  = EMAC0_MACCFG,
+                        .end    = EMAC0_MACCFG + 0x1274,
+                        .flags  = IORESOURCE_MEM,
+                },
+                {
+                        .name   = "macirq",
+                        .start  = IRQ_EMAC0_STAT,
+                        .end    = IRQ_EMAC0_STAT,
+                        .flags  = IORESOURCE_IRQ,
+                },
+        },
+        .dev = {
+                .power.can_wakeup = 1,
+                .platform_data = &eth_private_data,
+        }
+};
+#endif
+#if defined(CONFIG_INPUT_ADXL34X) || defined(CONFIG_INPUT_ADXL34X_MODULE)
+#include <linux/input/adxl34x.h>
+static const struct adxl34x_platform_data adxl34x_info = {
+        .x_axis_offset = 0,
+        .y_axis_offset = 0,
+        .z_axis_offset = 0,
+        .tap_threshold = 0x31,
+        .tap_duration = 0x10,
+        .tap_latency = 0x60,
+        .tap_window = 0xF0,
+        .tap_axis_control = ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN,
+        .act_axis_control = 0xFF,
+        .activity_threshold = 5,
+        .inactivity_threshold = 3,
+        .inactivity_time = 4,
+        .free_fall_threshold = 0x7,
+        .free_fall_time = 0x20,
+        .data_rate = 0x8,
+        .data_range = ADXL_FULL_RES,
+        .ev_type = EV_ABS,
+        .ev_code_x = ABS_X,             /* EV_REL */
+        .ev_code_y = ABS_Y,             /* EV_REL */
+        .ev_code_z = ABS_Z,             /* EV_REL */
+        .ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH}, /* EV_KEY x,y,z */
+/*      .ev_code_ff = KEY_F,*/          /* EV_KEY */
+/*      .ev_code_act_inactivity = KEY_A,*/      /* EV_KEY */
+        .power_mode = ADXL_AUTO_SLEEP | ADXL_LINK,
+        .fifo_mode = ADXL_FIFO_STREAM,
+        .orientation_enable = ADXL_EN_ORIENTATION_3D,
+        .deadzone_angle = ADXL_DEADZONE_ANGLE_10p8,
+        .divisor_length = ADXL_LP_FILTER_DIVISOR_16,
+        /* EV_KEY {+Z, +Y, +X, -X, -Y, -Z} */
+        .ev_codes_orient_3d = {BTN_Z, BTN_Y, BTN_X, BTN_A, BTN_B, BTN_C},
+};
+#endif
+#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
+static struct platform_device rtc_device = {
+        .name = "rtc-bfin",
+        .id   = -1,
+};
+#endif
+#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+#ifdef CONFIG_SERIAL_BFIN_UART0
+static struct resource bfin_uart0_resources[] = {
+        {
+                .start = UART0_REVID,
+                .end = UART0_RXDIV+4,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = IRQ_UART0_TX,
+                .end = IRQ_UART0_TX,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = IRQ_UART0_RX,
+                .end = IRQ_UART0_RX,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = IRQ_UART0_STAT,
+                .end = IRQ_UART0_STAT,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = CH_UART0_TX,
+                .end = CH_UART0_TX,
+                .flags = IORESOURCE_DMA,
+        },
+        {
+                .start = CH_UART0_RX,
+                .end = CH_UART0_RX,
+                .flags = IORESOURCE_DMA,
+        },
+#ifdef CONFIG_BFIN_UART0_CTSRTS
+        {       /* CTS pin -- 0 means not supported */
+                .start = GPIO_PD10,
+                .end = GPIO_PD10,
+                .flags = IORESOURCE_IO,
+        },
+        {       /* RTS pin -- 0 means not supported */
+                .start = GPIO_PD9,
+                .end = GPIO_PD9,
+                .flags = IORESOURCE_IO,
+        },
+#endif
+};
+static unsigned short bfin_uart0_peripherals[] = {
+        P_UART0_TX, P_UART0_RX,
+#ifdef CONFIG_BFIN_UART0_CTSRTS
+        P_UART0_RTS, P_UART0_CTS,
+#endif
+        0
+};
+static struct platform_device bfin_uart0_device = {
+        .name = "bfin-uart",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(bfin_uart0_resources),
+        .resource = bfin_uart0_resources,
+        .dev = {
+                .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
+        },
+};
+#endif
+#ifdef CONFIG_SERIAL_BFIN_UART1
+static struct resource bfin_uart1_resources[] = {
+        {
+                .start = UART1_REVID,
+                .end = UART1_RXDIV+4,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = IRQ_UART1_TX,
+                .end = IRQ_UART1_TX,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = IRQ_UART1_RX,
+                .end = IRQ_UART1_RX,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = IRQ_UART1_STAT,
+                .end = IRQ_UART1_STAT,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = CH_UART1_TX,
+                .end = CH_UART1_TX,
+                .flags = IORESOURCE_DMA,
+        },
+        {
+                .start = CH_UART1_RX,
+                .end = CH_UART1_RX,
+                .flags = IORESOURCE_DMA,
+        },
+#ifdef CONFIG_BFIN_UART1_CTSRTS
+        {       /* CTS pin -- 0 means not supported */
+                .start = GPIO_PG13,
+                .end = GPIO_PG13,
+                .flags = IORESOURCE_IO,
+        },
+        {       /* RTS pin -- 0 means not supported */
+                .start = GPIO_PG10,
+                .end = GPIO_PG10,
+                .flags = IORESOURCE_IO,
+        },
+#endif
+};
+static unsigned short bfin_uart1_peripherals[] = {
+        P_UART1_TX, P_UART1_RX,
+#ifdef CONFIG_BFIN_UART1_CTSRTS
+        P_UART1_RTS, P_UART1_CTS,
+#endif
+        0
+};
+static struct platform_device bfin_uart1_device = {
+        .name = "bfin-uart",
+        .id = 1,
+        .num_resources = ARRAY_SIZE(bfin_uart1_resources),
+        .resource = bfin_uart1_resources,
+        .dev = {
+                .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
+        },
+};
+#endif
+#endif
+#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+#ifdef CONFIG_BFIN_SIR0
+static struct resource bfin_sir0_resources[] = {
+        {
+                .start = 0xFFC00400,
+                .end = 0xFFC004FF,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = IRQ_UART0_TX,
+                .end = IRQ_UART0_TX+1,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = CH_UART0_TX,
+                .end = CH_UART0_TX+1,
+                .flags = IORESOURCE_DMA,
+        },
+};
+static struct platform_device bfin_sir0_device = {
+        .name = "bfin_sir",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(bfin_sir0_resources),
+        .resource = bfin_sir0_resources,
+};
+#endif
+#ifdef CONFIG_BFIN_SIR1
+static struct resource bfin_sir1_resources[] = {
+        {
+                .start = 0xFFC02000,
+                .end = 0xFFC020FF,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = IRQ_UART1_TX,
+                .end = IRQ_UART1_TX+1,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = CH_UART1_TX,
+                .end = CH_UART1_TX+1,
+                .flags = IORESOURCE_DMA,
+        },
+};
+static struct platform_device bfin_sir1_device = {
+        .name = "bfin_sir",
+        .id = 1,
+        .num_resources = ARRAY_SIZE(bfin_sir1_resources),
+        .resource = bfin_sir1_resources,
+};
+#endif
+#endif
+#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
+static struct resource musb_resources[] = {
+        [0] = {
+                .start  = 0xFFCC1000,
+                .end    = 0xFFCC1398,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = { /* general IRQ */
+                .start  = IRQ_USB_STAT,
+                .end    = IRQ_USB_STAT,
+                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
+                .name   = "mc"
+        },
+        [2] = { /* DMA IRQ */
+                .start  = IRQ_USB_DMA,
+                .end    = IRQ_USB_DMA,
+                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
+                .name   = "dma"
+        },
+};
+static struct musb_hdrc_config musb_config = {
+        .multipoint     = 1,
+        .dyn_fifo       = 0,
+        .dma            = 1,
+        .num_eps        = 16,
+        .dma_channels   = 8,
+        .clkin          = 48,           /* musb CLKIN in MHZ */
+};
+static struct musb_hdrc_platform_data musb_plat = {
+#if defined(CONFIG_USB_MUSB_HDRC) && defined(CONFIG_USB_GADGET_MUSB_HDRC)
+        .mode           = MUSB_OTG,
+#elif defined(CONFIG_USB_MUSB_HDRC)
+        .mode           = MUSB_HOST,
+#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
+        .mode           = MUSB_PERIPHERAL,
+#endif
+        .config         = &musb_config,
+};
+static u64 musb_dmamask = ~(u32)0;
+static struct platform_device musb_device = {
+        .name           = "musb-blackfin",
+        .id             = 0,
+        .dev = {
+                .dma_mask               = &musb_dmamask,
+                .coherent_dma_mask      = 0xffffffff,
+                .platform_data          = &musb_plat,
+        },
+        .num_resources  = ARRAY_SIZE(musb_resources),
+        .resource       = musb_resources,
+};
+#endif
+#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
+#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
+static struct resource bfin_sport0_uart_resources[] = {
+        {
+                .start = SPORT0_TCR1,
+                .end = SPORT0_MRCS3+4,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = IRQ_SPORT0_RX,
+                .end = IRQ_SPORT0_RX+1,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = IRQ_SPORT0_ERROR,
+                .end = IRQ_SPORT0_ERROR,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+static unsigned short bfin_sport0_peripherals[] = {
+        P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
+        P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
+};
+static struct platform_device bfin_sport0_uart_device = {
+        .name = "bfin-sport-uart",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
+        .resource = bfin_sport0_uart_resources,
+        .dev = {
+                .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
+        },
+};
+#endif
+#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
+static struct resource bfin_sport1_uart_resources[] = {
+        {
+                .start = SPORT1_TCR1,
+                .end = SPORT1_MRCS3+4,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = IRQ_SPORT1_RX,
+                .end = IRQ_SPORT1_RX+1,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = IRQ_SPORT1_ERROR,
+                .end = IRQ_SPORT1_ERROR,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+static unsigned short bfin_sport1_peripherals[] = {
+        P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
+        P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
+};
+static struct platform_device bfin_sport1_uart_device = {
+        .name = "bfin-sport-uart",
+        .id = 1,
+        .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
+        .resource = bfin_sport1_uart_resources,
+        .dev = {
+                .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
+        },
+};
+#endif
+#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
+static struct resource bfin_sport2_uart_resources[] = {
+        {
+                .start = SPORT2_TCR1,
+                .end = SPORT2_MRCS3+4,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = IRQ_SPORT2_RX,
+                .end = IRQ_SPORT2_RX+1,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = IRQ_SPORT2_ERROR,
+                .end = IRQ_SPORT2_ERROR,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+static unsigned short bfin_sport2_peripherals[] = {
+        P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS,
+        P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0
+};
+static struct platform_device bfin_sport2_uart_device = {
+        .name = "bfin-sport-uart",
+        .id = 2,
+        .num_resources = ARRAY_SIZE(bfin_sport2_uart_resources),
+        .resource = bfin_sport2_uart_resources,
+        .dev = {
+                .platform_data = &bfin_sport2_peripherals, /* Passed to driver */
+        },
+};
+#endif
+#endif
+#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
+static unsigned short bfin_can0_peripherals[] = {
+        P_CAN0_RX, P_CAN0_TX, 0
+};
+static struct resource bfin_can0_resources[] = {
+        {
+                .start = 0xFFC00A00,
+                .end = 0xFFC00FFF,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = IRQ_CAN0_RX,
+                .end = IRQ_CAN0_RX,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = IRQ_CAN0_TX,
+                .end = IRQ_CAN0_TX,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = IRQ_CAN0_STAT,
+                .end = IRQ_CAN0_STAT,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device bfin_can0_device = {
+        .name = "bfin_can",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(bfin_can0_resources),
+        .resource = bfin_can0_resources,
+        .dev = {
+                .platform_data = &bfin_can0_peripherals, /* Passed to driver */
+        },
+};
+#endif
+#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
+static struct mtd_partition partition_info[] = {
+        {
+                .name = "bootloader(nand)",
+                .offset = 0,
+                .size = 0x80000,
+        }, {
+                .name = "linux kernel(nand)",
+                .offset = MTDPART_OFS_APPEND,
+                .size = 4 * 1024 * 1024,
+        },
+        {
+                .name = "file system(nand)",
+                .offset = MTDPART_OFS_APPEND,
+                .size = MTDPART_SIZ_FULL,
+        },
+};
+static struct bf5xx_nand_platform bfin_nand_platform = {
+        .data_width = NFC_NWIDTH_8,
+        .partitions = partition_info,
+        .nr_partitions = ARRAY_SIZE(partition_info),
+        .rd_dly = 3,
+        .wr_dly = 3,
+};
+static struct resource bfin_nand_resources[] = {
+        {
+                .start = 0xFFC03B00,
+                .end = 0xFFC03B4F,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = CH_NFC,
+                .end = CH_NFC,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device bfin_nand_device = {
+        .name = "bfin-nand",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(bfin_nand_resources),
+        .resource = bfin_nand_resources,
+        .dev = {
+                .platform_data = &bfin_nand_platform,
+        },
+};
+#endif
+#if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
+static struct bfin_sd_host bfin_sdh_data = {
+        .dma_chan = CH_RSI,
+        .irq_int0 = IRQ_RSI_INT0,
+        .pin_req = {P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0},
+};
+static struct platform_device bfin_sdh_device = {
+        .name = "bfin-sdh",
+        .id = 0,
+        .dev = {
+                .platform_data = &bfin_sdh_data,
+        },
+};
+#endif
+#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
+static struct mtd_partition ezkit_partitions[] = {
+        {
+                .name       = "bootloader(nor)",
+                .size       = 0x80000,
+                .offset     = 0,
+        }, {
+                .name       = "linux kernel(nor)",
+                .size       = 0x400000,
+                .offset     = MTDPART_OFS_APPEND,
+        }, {
+                .name       = "file system(nor)",
+                .size       = 0x1000000 - 0x80000 - 0x400000,
+                .offset     = MTDPART_OFS_APPEND,
+        },
+};
+int bf609_nor_flash_init(struct platform_device *dev)
+{
+#define CONFIG_SMC_GCTL_VAL     0x00000010
+        const unsigned short pins[] = {
+                P_A3, P_A4, P_A5, P_A6, P_A7, P_A8, P_A9, P_A10, P_A11, P_A12,
+                P_A13, P_A14, P_A15, P_A16, P_A17, P_A18, P_A19, P_A20, P_A21,
+                P_A22, P_A23, P_A24, P_A25, P_NORCK, 0,
+        };
+        peripheral_request_list(pins, "smc0");
+        bfin_write32(SMC_GCTL, CONFIG_SMC_GCTL_VAL);
+        bfin_write32(SMC_B0CTL, 0x01002011);
+        bfin_write32(SMC_B0TIM, 0x08170977);
+        bfin_write32(SMC_B0ETIM, 0x00092231);
+        return 0;
+}
+static struct physmap_flash_data ezkit_flash_data = {
+        .width      = 2,
+        .parts      = ezkit_partitions,
+        .init       = bf609_nor_flash_init,
+        .nr_parts   = ARRAY_SIZE(ezkit_partitions),
+};
+static struct resource ezkit_flash_resource = {
+        .start = 0xb0000000,
+        .end   = 0xb0ffffff,
+        .flags = IORESOURCE_MEM,
+};
+static struct platform_device ezkit_flash_device = {
+        .name          = "physmap-flash",
+        .id            = 0,
+        .dev = {
+                .platform_data = &ezkit_flash_data,
+        },
+        .num_resources = 1,
+        .resource      = &ezkit_flash_resource,
+};
+#endif
+#if defined(CONFIG_MTD_M25P80) \
+        || defined(CONFIG_MTD_M25P80_MODULE)
+/* SPI flash chip (w25q32) */
+static struct mtd_partition bfin_spi_flash_partitions[] = {
+        {
+                .name = "bootloader(spi)",
+                .size = 0x00080000,
+                .offset = 0,
+                .mask_flags = MTD_CAP_ROM
+        }, {
+                .name = "linux kernel(spi)",
+                .size = 0x00180000,
+                .offset = MTDPART_OFS_APPEND,
+        }, {
+                .name = "file system(spi)",
+                .size = MTDPART_SIZ_FULL,
+                .offset = MTDPART_OFS_APPEND,
+        }
+};
+static struct flash_platform_data bfin_spi_flash_data = {
+        .name = "m25p80",
+        .parts = bfin_spi_flash_partitions,
+        .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
+        .type = "w25q32",
+};
+static struct bfin6xx_spi_chip spi_flash_chip_info = {
+        .enable_dma = true,         /* use dma transfer with this chip*/
+};
+#endif
+#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
+static struct bfin6xx_spi_chip spidev_chip_info = {
+        .enable_dma = true,
+};
+#endif
+#if defined(CONFIG_SND_BF6XX_I2S) || defined(CONFIG_SND_BF6XX_I2S_MODULE)
+static struct platform_device bfin_i2s_pcm = {
+        .name = "bfin-i2s-pcm-audio",
+        .id = -1,
+};
+#endif
+#if defined(CONFIG_SND_BF6XX_SOC_I2S) || \
+        defined(CONFIG_SND_BF6XX_SOC_I2S_MODULE)
+#include <asm/bfin_sport3.h>
+static struct resource bfin_snd_resources[] = {
+        {
+                .start = SPORT0_CTL_A,
+                .end = SPORT0_CTL_A,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = SPORT0_CTL_B,
+                .end = SPORT0_CTL_B,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = CH_SPORT0_TX,
+                .end = CH_SPORT0_TX,
+                .flags = IORESOURCE_DMA,
+        },
+        {
+                .start = CH_SPORT0_RX,
+                .end = CH_SPORT0_RX,
+                .flags = IORESOURCE_DMA,
+        },
+        {
+                .start = IRQ_SPORT0_TX_STAT,
+                .end = IRQ_SPORT0_TX_STAT,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = IRQ_SPORT0_RX_STAT,
+                .end = IRQ_SPORT0_RX_STAT,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+static const unsigned short bfin_snd_pin[] = {
+        P_SPORT0_ACLK, P_SPORT0_AFS, P_SPORT0_AD0, P_SPORT0_BCLK,
+        P_SPORT0_BFS, P_SPORT0_BD0, 0,
+};
+static struct bfin_snd_platform_data bfin_snd_data = {
+        .pin_req = bfin_snd_pin,
+};
+static struct platform_device bfin_i2s = {
+        .name = "bfin-i2s",
+        .num_resources = ARRAY_SIZE(bfin_snd_resources),
+        .resource = bfin_snd_resources,
+        .dev = {
+                .platform_data = &bfin_snd_data,
+        },
+};
+#endif
+#if defined(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61) || \
+        defined(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61_MODULE)
+static struct platform_device adau1761_device = {
+        .name = "bfin-eval-adau1x61",
+};
+#endif
+#if defined(CONFIG_SND_SOC_ADAU1761) || defined(CONFIG_SND_SOC_ADAU1761_MODULE)
+#include <sound/adau17x1.h>
+static struct adau1761_platform_data adau1761_info = {
+        .lineout_mode = ADAU1761_OUTPUT_MODE_LINE,
+        .headphone_mode = ADAU1761_OUTPUT_MODE_HEADPHONE_CAPLESS,
+};
+#endif
+#if defined(CONFIG_VIDEO_BLACKFIN_CAPTURE) \
+        || defined(CONFIG_VIDEO_BLACKFIN_CAPTURE_MODULE)
+#include <linux/videodev2.h>
+#include <media/blackfin/bfin_capture.h>
+#include <media/blackfin/ppi.h>
+static const unsigned short ppi_req[] = {
+        P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
+        P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
+        P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
+        0,
+};
+static const struct ppi_info ppi_info = {
+        .type = PPI_TYPE_EPPI3,
+        .dma_ch = CH_EPPI0_CH0,
+        .irq_err = IRQ_EPPI0_STAT,
+        .base = (void __iomem *)EPPI0_STAT,
+        .pin_req = ppi_req,
+};
+#if defined(CONFIG_VIDEO_VS6624) \
+        || defined(CONFIG_VIDEO_VS6624_MODULE)
+static struct v4l2_input vs6624_inputs[] = {
+        {
+                .index = 0,
+                .name = "Camera",
+                .type = V4L2_INPUT_TYPE_CAMERA,
+                .std = V4L2_STD_UNKNOWN,
+        },
+};
+static struct bcap_route vs6624_routes[] = {
+        {
+                .input = 0,
+                .output = 0,
+        },
+};
+static const unsigned vs6624_ce_pin = GPIO_PD1;
+static struct bfin_capture_config bfin_capture_data = {
+        .card_name = "BF609",
+        .inputs = vs6624_inputs,
+        .num_inputs = ARRAY_SIZE(vs6624_inputs),
+        .routes = vs6624_routes,
+        .i2c_adapter_id = 0,
+        .board_info = {
+                .type = "vs6624",
+                .addr = 0x10,
+                .platform_data = (void *)&vs6624_ce_pin,
+        },
+        .ppi_info = &ppi_info,
+        .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FS1HI_FS2HI
+                        | EPPI_CTL_POLC3 | EPPI_CTL_SYNC2 | EPPI_CTL_NON656),
+        .blank_clocks = 8,
+};
+#endif
+static struct platform_device bfin_capture_device = {
+        .name = "bfin_capture",
+        .dev = {
+                .platform_data = &bfin_capture_data,
+        },
+};
+#endif
+#if defined(CONFIG_BFIN_CRC)
+#define BFIN_CRC_NAME "bfin-crc"
+static struct resource bfin_crc0_resources[] = {
+        {
+                .start = REG_CRC0_CTL,
+                .end = REG_CRC0_REVID+4,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = IRQ_CRC0_DCNTEXP,
+                .end = IRQ_CRC0_DCNTEXP,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = CH_MEM_STREAM0_SRC_CRC0,
+                .end = CH_MEM_STREAM0_SRC_CRC0,
+                .flags = IORESOURCE_DMA,
+        },
+        {
+                .start = CH_MEM_STREAM0_DEST_CRC0,
+                .end = CH_MEM_STREAM0_DEST_CRC0,
+                .flags = IORESOURCE_DMA,
+        },
+};
+static struct platform_device bfin_crc0_device = {
+        .name = BFIN_CRC_NAME,
+        .id = 0,
+        .num_resources = ARRAY_SIZE(bfin_crc0_resources),
+        .resource = bfin_crc0_resources,
+};
+static struct resource bfin_crc1_resources[] = {
+        {
+                .start = REG_CRC1_CTL,
+                .end = REG_CRC1_REVID+4,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = IRQ_CRC1_DCNTEXP,
+                .end = IRQ_CRC1_DCNTEXP,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = CH_MEM_STREAM1_SRC_CRC1,
+                .end = CH_MEM_STREAM1_SRC_CRC1,
+                .flags = IORESOURCE_DMA,
+        },
+        {
+                .start = CH_MEM_STREAM1_DEST_CRC1,
+                .end = CH_MEM_STREAM1_DEST_CRC1,
+                .flags = IORESOURCE_DMA,
+        },
+};
+static struct platform_device bfin_crc1_device = {
+        .name = BFIN_CRC_NAME,
+        .id = 1,
+        .num_resources = ARRAY_SIZE(bfin_crc1_resources),
+        .resource = bfin_crc1_resources,
+};
+#endif
+#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
+static const struct ad7877_platform_data bfin_ad7877_ts_info = {
+        .model                  = 7877,
+        .vref_delay_usecs       = 50,   /* internal, no capacitor */
+        .x_plate_ohms           = 419,
+        .y_plate_ohms           = 486,
+        .pressure_max           = 1000,
+        .pressure_min           = 0,
+        .stopacq_polarity       = 1,
+        .first_conversion_delay = 3,
+        .acquisition_time       = 1,
+        .averaging              = 1,
+        .pen_down_acc_interval  = 1,
+};
+#endif
+static struct spi_board_info bfin_spi_board_info[] __initdata = {
+#if defined(CONFIG_MTD_M25P80) \
+        || defined(CONFIG_MTD_M25P80_MODULE)
+        {
+                /* the modalias must be the same as spi device driver name */
+                .modalias = "m25p80", /* Name of spi_driver for this device */
+                .max_speed_hz = 25000000,     /* max spi clock (SCK) speed in HZ */
+                .bus_num = 0, /* Framework bus number */
+                .chip_select = 1, /* SPI_SSEL1*/
+                .platform_data = &bfin_spi_flash_data,
+                .controller_data = &spi_flash_chip_info,
+                .mode = SPI_MODE_3,
+        },
+#endif
+#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
+        {
+                .modalias               = "ad7877",
+                .platform_data          = &bfin_ad7877_ts_info,
+                .irq                    = IRQ_PB4,      /* old boards (<=Rev 1.3) use IRQ_PJ11 */
+                .max_speed_hz           = 12500000,     /* max spi clock (SCK) speed in HZ */
+                .bus_num                = 0,
+                .chip_select            = 2,
+        },
+#endif
+#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
+        {
+                .modalias = "spidev",
+                .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
+                .bus_num = 0,
+                .chip_select = 1,
+                .controller_data = &spidev_chip_info,
+        },
+#endif
+#if defined(CONFIG_INPUT_ADXL34X_SPI) || defined(CONFIG_INPUT_ADXL34X_SPI_MODULE)
+        {
+                .modalias               = "adxl34x",
+                .platform_data          = &adxl34x_info,
+                .irq                    = IRQ_PC5,
+                .max_speed_hz           = 5000000,     /* max spi clock (SCK) speed in HZ */
+                .bus_num                = 1,
+                .chip_select            = 2,
+                .mode = SPI_MODE_3,
+        },
+#endif
+};
+#if defined(CONFIG_SPI_BFIN6XX) || defined(CONFIG_SPI_BFIN6XX_MODULE)
+/* SPI (0) */
+static struct resource bfin_spi0_resource[] = {
+        {
+                .start = SPI0_REGBASE,
+                .end   = SPI0_REGBASE + 0xFF,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = CH_SPI0_TX,
+                .end   = CH_SPI0_TX,
+                .flags = IORESOURCE_DMA,
+        },
+        {
+                .start = CH_SPI0_RX,
+                .end   = CH_SPI0_RX,
+                .flags = IORESOURCE_DMA,
+        },
+};
+/* SPI (1) */
+static struct resource bfin_spi1_resource[] = {
+        {
+                .start = SPI1_REGBASE,
+                .end   = SPI1_REGBASE + 0xFF,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = CH_SPI1_TX,
+                .end   = CH_SPI1_TX,
+                .flags = IORESOURCE_DMA,
+        },
+        {
+                .start = CH_SPI1_RX,
+                .end   = CH_SPI1_RX,
+                .flags = IORESOURCE_DMA,
+        },
+};
+/* SPI controller data */
+static struct bfin6xx_spi_master bf60x_spi_master_info0 = {
+        .num_chipselect = 4,
+        .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
+};
+static struct platform_device bf60x_spi_master0 = {
+        .name = "bfin-spi",
+        .id = 0, /* Bus number */
+        .num_resources = ARRAY_SIZE(bfin_spi0_resource),
+        .resource = bfin_spi0_resource,
+        .dev = {
+                .platform_data = &bf60x_spi_master_info0, /* Passed to driver */
+        },
+};
+static struct bfin6xx_spi_master bf60x_spi_master_info1 = {
+        .num_chipselect = 4,
+        .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
+};
+static struct platform_device bf60x_spi_master1 = {
+        .name = "bfin-spi",
+        .id = 1, /* Bus number */
+        .num_resources = ARRAY_SIZE(bfin_spi1_resource),
+        .resource = bfin_spi1_resource,
+        .dev = {
+                .platform_data = &bf60x_spi_master_info1, /* Passed to driver */
+        },
+};
+#endif  /* spi master and devices */
+#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
+static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
+static struct resource bfin_twi0_resource[] = {
+        [0] = {
+                .start = TWI0_CLKDIV,
+                .end   = TWI0_CLKDIV + 0xFF,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_TWI0,
+                .end   = IRQ_TWI0,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device i2c_bfin_twi0_device = {
+        .name = "i2c-bfin-twi",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(bfin_twi0_resource),
+        .resource = bfin_twi0_resource,
+        .dev = {
+                .platform_data = &bfin_twi0_pins,
+        },
+};
+static const u16 bfin_twi1_pins[] = {P_TWI1_SCL, P_TWI1_SDA, 0};
+static struct resource bfin_twi1_resource[] = {
+        [0] = {
+                .start = TWI1_CLKDIV,
+                .end   = TWI1_CLKDIV + 0xFF,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_TWI1,
+                .end   = IRQ_TWI1,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device i2c_bfin_twi1_device = {
+        .name = "i2c-bfin-twi",
+        .id = 1,
+        .num_resources = ARRAY_SIZE(bfin_twi1_resource),
+        .resource = bfin_twi1_resource,
+        .dev = {
+                .platform_data = &bfin_twi1_pins,
+        },
+};
+#endif
+static struct i2c_board_info __initdata bfin_i2c_board_info0[] = {
+#if defined(CONFIG_INPUT_ADXL34X_I2C) || defined(CONFIG_INPUT_ADXL34X_I2C_MODULE)
+        {
+                I2C_BOARD_INFO("adxl34x", 0x53),
+                .irq = IRQ_PC5,
+                .platform_data = (void *)&adxl34x_info,
+        },
+#endif
+#if defined(CONFIG_SND_SOC_ADAU1761) || defined(CONFIG_SND_SOC_ADAU1761_MODULE)
+        {
+                I2C_BOARD_INFO("adau1761", 0x38),
+                .platform_data = (void *)&adau1761_info
+        },
+#endif
+};
+static struct i2c_board_info __initdata bfin_i2c_board_info1[] = {
+};
+static const unsigned int cclk_vlev_datasheet[] =
+{
+/*
+ * Internal VLEV BF54XSBBC1533
+ ****temporarily using these values until data sheet is updated
+ */
+        VRPAIR(VLEV_085, 150000000),
+        VRPAIR(VLEV_090, 250000000),
+        VRPAIR(VLEV_110, 276000000),
+        VRPAIR(VLEV_115, 301000000),
+        VRPAIR(VLEV_120, 525000000),
+        VRPAIR(VLEV_125, 550000000),
+        VRPAIR(VLEV_130, 600000000),
+};
+static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
+        .tuple_tab = cclk_vlev_datasheet,
+        .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
+        .vr_settling_time = 25 /* us */,
+};
+static struct platform_device bfin_dpmc = {
+        .name = "bfin dpmc",
+        .dev = {
+                .platform_data = &bfin_dmpc_vreg_data,
+        },
+};
+static struct platform_device *ezkit_devices[] __initdata = {
+        &bfin_dpmc,
+#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
+        &rtc_device,
+#endif
+#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+#ifdef CONFIG_SERIAL_BFIN_UART0
+        &bfin_uart0_device,
+#endif
+#ifdef CONFIG_SERIAL_BFIN_UART1
+        &bfin_uart1_device,
+#endif
+#endif
+#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
+#ifdef CONFIG_BFIN_SIR0
+        &bfin_sir0_device,
+#endif
+#ifdef CONFIG_BFIN_SIR1
+        &bfin_sir1_device,
+#endif
+#endif
+#if defined(CONFIG_STMMAC_ETH) || defined(CONFIG_STMMAC_ETH_MODULE)
+        &bfin_eth_device,
+#endif
+#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
+        &musb_device,
+#endif
+#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
+        &bfin_isp1760_device,
+#endif
+#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
+#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
+        &bfin_sport0_uart_device,
+#endif
+#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
+        &bfin_sport1_uart_device,
+#endif
+#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
+        &bfin_sport2_uart_device,
+#endif
+#endif
+#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
+        &bfin_can0_device,
+#endif
+#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
+        &bfin_nand_device,
+#endif
+#if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
+        &bfin_sdh_device,
+#endif
+#if defined(CONFIG_SPI_BFIN6XX) || defined(CONFIG_SPI_BFIN6XX_MODULE)
+        &bf60x_spi_master0,
+        &bf60x_spi_master1,
+#endif
+#if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE)
+        &bfin_rotary_device,
+#endif
+#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
+        &i2c_bfin_twi0_device,
+#if !defined(CONFIG_BF542)
+        &i2c_bfin_twi1_device,
+#endif
+#endif
+#if defined(CONFIG_BFIN_CRC)
+        &bfin_crc0_device,
+        &bfin_crc1_device,
+#endif
+#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+        &bfin_device_gpiokeys,
+#endif
+#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
+        &ezkit_flash_device,
+#endif
+#if defined(CONFIG_SND_BF6XX_I2S) || defined(CONFIG_SND_BF6XX_I2S_MODULE)
+        &bfin_i2s_pcm,
+#endif
+#if defined(CONFIG_SND_BF6XX_SOC_I2S) || \
+        defined(CONFIG_SND_BF6XX_SOC_I2S_MODULE)
+        &bfin_i2s,
+#endif
+#if defined(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61) || \
+        defined(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61_MODULE)
+        &adau1761_device,
+#endif
+#if defined(CONFIG_VIDEO_BLACKFIN_CAPTURE) \
+        || defined(CONFIG_VIDEO_BLACKFIN_CAPTURE_MODULE)
+        &bfin_capture_device,
+#endif
+};
+static int __init ezkit_init(void)
+{
+        printk(KERN_INFO "%s(): registering device resources\n", __func__);
+        i2c_register_board_info(0, bfin_i2c_board_info0,
+                                ARRAY_SIZE(bfin_i2c_board_info0));
+        i2c_register_board_info(1, bfin_i2c_board_info1,
+                                ARRAY_SIZE(bfin_i2c_board_info1));
+#if defined(CONFIG_STMMAC_ETH) || defined(CONFIG_STMMAC_ETH_MODULE)
+        if (!peripheral_request_list(pins, "emac0"))
+                printk(KERN_ERR "%s(): request emac pins failed\n", __func__);
+#endif
+        platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices));
+        spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
+        return 0;
+}
+arch_initcall(ezkit_init);
+static struct platform_device *ezkit_early_devices[] __initdata = {
+#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
+#ifdef CONFIG_SERIAL_BFIN_UART0
+        &bfin_uart0_device,
+#endif
+#ifdef CONFIG_SERIAL_BFIN_UART1
+        &bfin_uart1_device,
+#endif
+#endif
+#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
+#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
+        &bfin_sport0_uart_device,
+#endif
+#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
+        &bfin_sport1_uart_device,
+#endif
+#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
+        &bfin_sport2_uart_device,
+#endif
+#endif
+};
+void __init native_machine_early_platform_add_devices(void)
+{
+        printk(KERN_INFO "register early platform devices\n");
+        early_platform_add_devices(ezkit_early_devices,
+                ARRAY_SIZE(ezkit_early_devices));
+}
diff --git a/arch/blackfin/mach-bf609/clock.c b/arch/blackfin/mach-bf609/clock.c
new file mode 100644
index 000000000000..7f8f529693ae
--- /dev/null
+++ b/arch/blackfin/mach-bf609/clock.c
@@ -0,0 +1,390 @@
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/string.h>
+#include <linux/clk.h>
+#include <linux/mutex.h>
+#include <linux/spinlock.h>
+#include <linux/debugfs.h>
+#include <linux/device.h>
+#include <linux/init.h>
+#include <linux/timer.h>
+#include <linux/io.h>
+#include <linux/seq_file.h>
+#include <linux/clkdev.h>
+#include <asm/clocks.h>
+#define CGU0_CTL_DF (1 << 0)
+#define CGU0_CTL_MSEL_SHIFT 8
+#define CGU0_CTL_MSEL_MASK (0x7f << 8)
+#define CGU0_STAT_PLLEN (1 << 0)
+#define CGU0_STAT_PLLBP (1 << 1)
+#define CGU0_STAT_PLLLK (1 << 2)
+#define CGU0_STAT_CLKSALGN (1 << 3)
+#define CGU0_STAT_CCBF0 (1 << 4)
+#define CGU0_STAT_CCBF1 (1 << 5)
+#define CGU0_STAT_SCBF0 (1 << 6)
+#define CGU0_STAT_SCBF1 (1 << 7)
+#define CGU0_STAT_DCBF (1 << 8)
+#define CGU0_STAT_OCBF (1 << 9)
+#define CGU0_STAT_ADDRERR (1 << 16)
+#define CGU0_STAT_LWERR (1 << 17)
+#define CGU0_STAT_DIVERR (1 << 18)
+#define CGU0_STAT_WDFMSERR (1 << 19)
+#define CGU0_STAT_WDIVERR (1 << 20)
+#define CGU0_STAT_PLOCKERR (1 << 21)
+#define CGU0_DIV_CSEL_SHIFT 0
+#define CGU0_DIV_CSEL_MASK 0x0000001F
+#define CGU0_DIV_S0SEL_SHIFT 5
+#define CGU0_DIV_S0SEL_MASK (0x3 << CGU0_DIV_S0SEL_SHIFT)
+#define CGU0_DIV_SYSSEL_SHIFT 8
+#define CGU0_DIV_SYSSEL_MASK (0x1f << CGU0_DIV_SYSSEL_SHIFT)
+#define CGU0_DIV_S1SEL_SHIFT 13
+#define CGU0_DIV_S1SEL_MASK (0x3 << CGU0_DIV_S1SEL_SHIFT)
+#define CGU0_DIV_DSEL_SHIFT 16
+#define CGU0_DIV_DSEL_MASK (0x1f << CGU0_DIV_DSEL_SHIFT)
+#define CGU0_DIV_OSEL_SHIFT 22
+#define CGU0_DIV_OSEL_MASK (0x7f << CGU0_DIV_OSEL_SHIFT)
+#define CLK(_clk, _devname, _conname)                   \
+        {                                               \
+                .clk    = &_clk,                  \
+                .dev_id = _devname,                     \
+                .con_id = _conname,                     \
+        }
+#define NEEDS_INITIALIZATION 0x11
+static LIST_HEAD(clk_list);
+static void clk_reg_write_mask(u32 reg, uint32_t val, uint32_t mask)
+{
+        u32 val2;
+        val2 = bfin_read32(reg);
+        val2 &= ~mask;
+        val2 |= val;
+        bfin_write32(reg, val2);
+}
+static void clk_reg_set_bits(u32 reg, uint32_t mask)
+{
+        u32 val;
+        val = bfin_read32(reg);
+        val |= mask;
+        bfin_write32(reg, val);
+}
+static void clk_reg_clear_bits(u32 reg, uint32_t mask)
+{
+        u32 val;
+        val = bfin_read32(reg);
+        val &= ~mask;
+        bfin_write32(reg, val);
+}
+int wait_for_pll_align(void)
+{
+        int i = 10000;
+        while (i-- && (bfin_read32(CGU0_STAT) & CGU0_STAT_CLKSALGN));
+        if (bfin_read32(CGU0_STAT) & CGU0_STAT_CLKSALGN) {
+                printk(KERN_DEBUG "fail to align clk\n");
+                return -1;
+        }
+        return 0;
+}
+int clk_enable(struct clk *clk)
+{
+        int ret = -EIO;
+        if (clk->ops && clk->ops->enable)
+                ret = clk->ops->enable(clk);
+        return ret;
+}
+EXPORT_SYMBOL(clk_enable);
+void clk_disable(struct clk *clk)
+{
+        if (clk->ops && clk->ops->disable)
+                clk->ops->disable(clk);
+}
+EXPORT_SYMBOL(clk_disable);
+unsigned long clk_get_rate(struct clk *clk)
+{
+        unsigned long ret = 0;
+        if (clk->ops && clk->ops->get_rate)
+                ret = clk->ops->get_rate(clk);
+        return ret;
+}
+EXPORT_SYMBOL(clk_get_rate);
+long clk_round_rate(struct clk *clk, unsigned long rate)
+{
+        long ret = -EIO;
+        if (clk->ops && clk->ops->round_rate)
+                ret = clk->ops->round_rate(clk, rate);
+        return ret;
+}
+EXPORT_SYMBOL(clk_round_rate);
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+        int ret = -EIO;
+        if (clk->ops && clk->ops->set_rate)
+                ret = clk->ops->set_rate(clk, rate);
+        return ret;
+}
+EXPORT_SYMBOL(clk_set_rate);
+unsigned long vco_get_rate(struct clk *clk)
+{
+        return clk->rate;
+}
+unsigned long pll_get_rate(struct clk *clk)
+{
+        u32 df;
+        u32 msel;
+        u32 ctl = bfin_read32(CGU0_CTL);
+        u32 stat = bfin_read32(CGU0_STAT);
+        if (stat & CGU0_STAT_PLLBP)
+                return 0;
+        msel = (ctl & CGU0_CTL_MSEL_MASK) >> CGU0_CTL_MSEL_SHIFT;
+        df = (ctl &  CGU0_CTL_DF);
+        clk->parent->rate = clk_get_rate(clk->parent);
+        return clk->parent->rate / (df + 1) * msel * 2;
+}
+unsigned long pll_round_rate(struct clk *clk, unsigned long rate)
+{
+        u32 div;
+        div = rate / clk->parent->rate;
+        return clk->parent->rate * div;
+}
+int pll_set_rate(struct clk *clk, unsigned long rate)
+{
+        u32 msel;
+        u32 stat = bfin_read32(CGU0_STAT);
+        if (!(stat & CGU0_STAT_PLLEN))
+                return -EBUSY;
+        if (!(stat & CGU0_STAT_PLLLK))
+                return -EBUSY;
+        if (wait_for_pll_align())
+                return -EBUSY;
+        msel = rate / clk->parent->rate / 2;
+        clk_reg_write_mask(CGU0_CTL, msel << CGU0_CTL_MSEL_SHIFT,
+                CGU0_CTL_MSEL_MASK);
+        clk->rate = rate;
+        return 0;
+}
+unsigned long cclk_get_rate(struct clk *clk)
+{
+        if (clk->parent)
+                return clk->parent->rate;
+        else
+                return 0;
+}
+unsigned long sys_clk_get_rate(struct clk *clk)
+{
+        unsigned long drate;
+        u32 msel;
+        u32 df;
+        u32 ctl = bfin_read32(CGU0_CTL);
+        u32 div = bfin_read32(CGU0_DIV);
+        div = (div & clk->mask) >> clk->shift;
+        msel = (ctl & CGU0_CTL_MSEL_MASK) >> CGU0_CTL_MSEL_SHIFT;
+        df = (ctl &  CGU0_CTL_DF);
+        if (!strcmp(clk->parent->name, "SYS_CLKIN")) {
+                drate = clk->parent->rate / (df + 1);
+                drate *=  msel;
+                drate /= div;
+                return drate;
+        } else {
+                clk->parent->rate = clk_get_rate(clk->parent);
+                return clk->parent->rate / div;
+        }
+}
+unsigned long sys_clk_round_rate(struct clk *clk, unsigned long rate)
+{
+        unsigned long max_rate;
+        unsigned long drate;
+        int i;
+        u32 msel;
+        u32 df;
+        u32 ctl = bfin_read32(CGU0_CTL);
+        msel = (ctl & CGU0_CTL_MSEL_MASK) >> CGU0_CTL_MSEL_SHIFT;
+        df = (ctl &  CGU0_CTL_DF);
+        max_rate = clk->parent->rate / (df + 1) * msel;
+        if (rate > max_rate)
+                return 0;
+        for (i = 1; i < clk->mask; i++) {
+                drate = max_rate / i;
+                if (rate >= drate)
+                        return drate;
+        }
+        return 0;
+}
+int sys_clk_set_rate(struct clk *clk, unsigned long rate)
+{
+        u32 div = bfin_read32(CGU0_DIV);
+        div = (div & clk->mask) >> clk->shift;
+        rate = clk_round_rate(clk, rate);
+        if (!rate)
+                return -EINVAL;
+        div = (clk_get_rate(clk) * div) / rate;
+        if (wait_for_pll_align())
+                return -EBUSY;
+        clk_reg_write_mask(CGU0_DIV, div << clk->shift,
+                        clk->mask);
+        clk->rate = rate;
+        return 0;
+}
+static struct clk_ops vco_ops = {
+        .get_rate = vco_get_rate,
+};
+static struct clk_ops pll_ops = {
+        .get_rate = pll_get_rate,
+        .set_rate = pll_set_rate,
+};
+static struct clk_ops cclk_ops = {
+        .get_rate = cclk_get_rate,
+};
+static struct clk_ops sys_clk_ops = {
+        .get_rate = sys_clk_get_rate,
+        .set_rate = sys_clk_set_rate,
+        .round_rate = sys_clk_round_rate,
+};
+static struct clk sys_clkin = {
+        .name       = "SYS_CLKIN",
+        .rate       = CONFIG_CLKIN_HZ,
+        .ops        = &vco_ops,
+};
+static struct clk pll_clk = {
+        .name       = "PLLCLK",
+        .rate       = 500000000,
+        .parent     = &sys_clkin,
+        .ops = &pll_ops,
+        .flags = NEEDS_INITIALIZATION,
+};
+static struct clk cclk = {
+        .name       = "CCLK",
+        .rate       = 500000000,
+        .mask       = CGU0_DIV_CSEL_MASK,
+        .shift      = CGU0_DIV_CSEL_SHIFT,
+        .parent     = &sys_clkin,
+        .ops        = &sys_clk_ops,
+        .flags = NEEDS_INITIALIZATION,
+};
+static struct clk cclk0 = {
+        .name       = "CCLK0",
+        .parent     = &cclk,
+        .ops        = &cclk_ops,
+};
+static struct clk cclk1 = {
+        .name       = "CCLK1",
+        .parent     = &cclk,
+        .ops        = &cclk_ops,
+};
+static struct clk sysclk = {
+        .name       = "SYSCLK",
+        .rate       = 500000000,
+        .mask       = CGU0_DIV_SYSSEL_MASK,
+        .shift      = CGU0_DIV_SYSSEL_SHIFT,
+        .parent     = &sys_clkin,
+        .ops        = &sys_clk_ops,
+        .flags = NEEDS_INITIALIZATION,
+};
+static struct clk sclk0 = {
+        .name       = "SCLK0",
+        .rate       = 500000000,
+        .mask       = CGU0_DIV_S0SEL_MASK,
+        .shift      = CGU0_DIV_S0SEL_SHIFT,
+        .parent     = &sysclk,
+        .ops        = &sys_clk_ops,
+};
+static struct clk sclk1 = {
+        .name       = "SCLK1",
+        .rate       = 500000000,
+        .mask       = CGU0_DIV_S1SEL_MASK,
+        .shift      = CGU0_DIV_S1SEL_SHIFT,
+        .parent     = &sysclk,
+        .ops        = &sys_clk_ops,
+};
+static struct clk dclk = {
+        .name       = "DCLK",
+        .rate       = 500000000,
+        .mask       = CGU0_DIV_DSEL_MASK,
+        .shift       = CGU0_DIV_DSEL_SHIFT,
+        .parent     = &sys_clkin,
+        .ops        = &sys_clk_ops,
+};
+static struct clk oclk = {
+        .name       = "OCLK",
+        .rate       = 500000000,
+        .mask       = CGU0_DIV_OSEL_MASK,
+        .shift      = CGU0_DIV_OSEL_SHIFT,
+        .parent     = &pll_clk,
+};
+static struct clk_lookup bf609_clks[] = {
+        CLK(sys_clkin, NULL, "SYS_CLKIN"),
+        CLK(pll_clk, NULL, "PLLCLK"),
+        CLK(cclk, NULL, "CCLK"),
+        CLK(cclk0, NULL, "CCLK0"),
+        CLK(cclk1, NULL, "CCLK1"),
+        CLK(sysclk, NULL, "SYSCLK"),
+        CLK(sclk0, NULL, "SCLK0"),
+        CLK(sclk1, NULL, "SCLK1"),
+        CLK(dclk, NULL, "DCLK"),
+        CLK(oclk, NULL, "OCLK"),
+};
+int __init clk_init(void)
+{
+        int i;
+        struct clk *clkp;
+        for (i = 0; i < ARRAY_SIZE(bf609_clks); i++) {
+                clkp = bf609_clks[i].clk;
+                if (clkp->flags & NEEDS_INITIALIZATION)
+                        clk_get_rate(clkp);
+        }
+        clkdev_add_table(bf609_clks, ARRAY_SIZE(bf609_clks));
+        return 0;
+}
diff --git a/arch/blackfin/mach-bf609/dma.c b/arch/blackfin/mach-bf609/dma.c
new file mode 100644
index 000000000000..1da4b38ac22c
--- /dev/null
+++ b/arch/blackfin/mach-bf609/dma.c
@@ -0,0 +1,202 @@
+/*
+ * the simple DMA Implementation for Blackfin
+ *
+ * Copyright 2007-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+#include <linux/module.h>
+#include <asm/blackfin.h>
+#include <asm/dma.h>
+struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
+        (struct dma_register *) DMA0_NEXT_DESC_PTR,
+        (struct dma_register *) DMA1_NEXT_DESC_PTR,
+        (struct dma_register *) DMA2_NEXT_DESC_PTR,
+        (struct dma_register *) DMA3_NEXT_DESC_PTR,
+        (struct dma_register *) DMA4_NEXT_DESC_PTR,
+        (struct dma_register *) DMA5_NEXT_DESC_PTR,
+        (struct dma_register *) DMA6_NEXT_DESC_PTR,
+        (struct dma_register *) DMA7_NEXT_DESC_PTR,
+        (struct dma_register *) DMA8_NEXT_DESC_PTR,
+        (struct dma_register *) DMA9_NEXT_DESC_PTR,
+        (struct dma_register *) DMA10_NEXT_DESC_PTR,
+        (struct dma_register *) DMA11_NEXT_DESC_PTR,
+        (struct dma_register *) DMA12_NEXT_DESC_PTR,
+        (struct dma_register *) DMA13_NEXT_DESC_PTR,
+        (struct dma_register *) DMA14_NEXT_DESC_PTR,
+        (struct dma_register *) DMA15_NEXT_DESC_PTR,
+        (struct dma_register *) DMA16_NEXT_DESC_PTR,
+        (struct dma_register *) DMA17_NEXT_DESC_PTR,
+        (struct dma_register *) DMA18_NEXT_DESC_PTR,
+        (struct dma_register *) DMA19_NEXT_DESC_PTR,
+        (struct dma_register *) DMA20_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA0_SRC_CRC0_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA0_DEST_CRC0_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA1_SRC_CRC1_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA1_DEST_CRC1_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA2_SRC_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA2_DEST_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA3_SRC_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA3_DEST_NEXT_DESC_PTR,
+        (struct dma_register *) DMA29_NEXT_DESC_PTR,
+        (struct dma_register *) DMA30_NEXT_DESC_PTR,
+        (struct dma_register *) DMA31_NEXT_DESC_PTR,
+        (struct dma_register *) DMA32_NEXT_DESC_PTR,
+        (struct dma_register *) DMA33_NEXT_DESC_PTR,
+        (struct dma_register *) DMA34_NEXT_DESC_PTR,
+        (struct dma_register *) DMA35_NEXT_DESC_PTR,
+        (struct dma_register *) DMA36_NEXT_DESC_PTR,
+        (struct dma_register *) DMA37_NEXT_DESC_PTR,
+        (struct dma_register *) DMA38_NEXT_DESC_PTR,
+        (struct dma_register *) DMA39_NEXT_DESC_PTR,
+        (struct dma_register *) DMA40_NEXT_DESC_PTR,
+        (struct dma_register *) DMA41_NEXT_DESC_PTR,
+        (struct dma_register *) DMA42_NEXT_DESC_PTR,
+        (struct dma_register *) DMA43_NEXT_DESC_PTR,
+        (struct dma_register *) DMA44_NEXT_DESC_PTR,
+        (struct dma_register *) DMA45_NEXT_DESC_PTR,
+        (struct dma_register *) DMA46_NEXT_DESC_PTR,
+};
+EXPORT_SYMBOL(dma_io_base_addr);
+int channel2irq(unsigned int channel)
+{
+        int ret_irq = -1;
+        switch (channel) {
+        case CH_SPORT0_RX:
+                ret_irq = IRQ_SPORT0_RX;
+                break;
+        case CH_SPORT0_TX:
+                ret_irq = IRQ_SPORT0_TX;
+                break;
+        case CH_SPORT1_RX:
+                ret_irq = IRQ_SPORT1_RX;
+                break;
+        case CH_SPORT1_TX:
+                ret_irq = IRQ_SPORT1_TX;
+                break;
+        case CH_SPORT2_RX:
+                ret_irq = IRQ_SPORT2_RX;
+                break;
+        case CH_SPORT2_TX:
+                ret_irq = IRQ_SPORT2_TX;
+                break;
+        case CH_SPI0_TX:
+                ret_irq = IRQ_SPI0_TX;
+                break;
+        case CH_SPI0_RX:
+                ret_irq = IRQ_SPI0_RX;
+                break;
+        case CH_SPI1_TX:
+                ret_irq = IRQ_SPI1_TX;
+                break;
+        case CH_SPI1_RX:
+                ret_irq = IRQ_SPI1_RX;
+                break;
+        case CH_RSI:
+                ret_irq = IRQ_RSI;
+                break;
+        case CH_SDU:
+                ret_irq = IRQ_SDU;
+                break;
+        case CH_LP0:
+                ret_irq = IRQ_LP0;
+                break;
+        case CH_LP1:
+                ret_irq = IRQ_LP1;
+                break;
+        case CH_LP2:
+                ret_irq = IRQ_LP2;
+                break;
+        case CH_LP3:
+                ret_irq = IRQ_LP3;
+                break;
+        case CH_UART0_RX:
+                ret_irq = IRQ_UART0_RX;
+                break;
+        case CH_UART0_TX:
+                ret_irq = IRQ_UART0_TX;
+                break;
+        case CH_UART1_RX:
+                ret_irq = IRQ_UART1_RX;
+                break;
+        case CH_UART1_TX:
+                ret_irq = IRQ_UART1_TX;
+                break;
+        case CH_EPPI0_CH0:
+                ret_irq = IRQ_EPPI0_CH0;
+                break;
+        case CH_EPPI0_CH1:
+                ret_irq = IRQ_EPPI0_CH1;
+                break;
+        case CH_EPPI1_CH0:
+                ret_irq = IRQ_EPPI1_CH0;
+                break;
+        case CH_EPPI1_CH1:
+                ret_irq = IRQ_EPPI1_CH1;
+                break;
+        case CH_EPPI2_CH0:
+                ret_irq = IRQ_EPPI2_CH0;
+                break;
+        case CH_EPPI2_CH1:
+                ret_irq = IRQ_EPPI2_CH1;
+                break;
+        case CH_PIXC_CH0:
+                ret_irq = IRQ_PIXC_CH0;
+                break;
+        case CH_PIXC_CH1:
+                ret_irq = IRQ_PIXC_CH1;
+                break;
+        case CH_PIXC_CH2:
+                ret_irq = IRQ_PIXC_CH2;
+                break;
+        case CH_PVP_CPDOB:
+                ret_irq = IRQ_PVP_CPDOB;
+                break;
+        case CH_PVP_CPDOC:
+                ret_irq = IRQ_PVP_CPDOC;
+                break;
+        case CH_PVP_CPSTAT:
+                ret_irq = IRQ_PVP_CPSTAT;
+                break;
+        case CH_PVP_CPCI:
+                ret_irq = IRQ_PVP_CPCI;
+                break;
+        case CH_PVP_MPDO:
+                ret_irq = IRQ_PVP_MPDO;
+                break;
+        case CH_PVP_MPDI:
+                ret_irq = IRQ_PVP_MPDI;
+                break;
+        case CH_PVP_MPSTAT:
+                ret_irq = IRQ_PVP_MPSTAT;
+                break;
+        case CH_PVP_MPCI:
+                ret_irq = IRQ_PVP_MPCI;
+                break;
+        case CH_PVP_CPDOA:
+                ret_irq = IRQ_PVP_CPDOA;
+                break;
+        case CH_MEM_STREAM0_SRC:
+        case CH_MEM_STREAM0_DEST:
+                ret_irq = IRQ_MDMAS0;
+                break;
+        case CH_MEM_STREAM1_SRC:
+        case CH_MEM_STREAM1_DEST:
+                ret_irq = IRQ_MDMAS1;
+                break;
+        case CH_MEM_STREAM2_SRC:
+        case CH_MEM_STREAM2_DEST:
+                ret_irq = IRQ_MDMAS2;
+                break;
+        case CH_MEM_STREAM3_SRC:
+        case CH_MEM_STREAM3_DEST:
+                ret_irq = IRQ_MDMAS3;
+                break;
+        }
+        return ret_irq;
+}
diff --git a/arch/blackfin/mach-bf609/hibernate.S b/arch/blackfin/mach-bf609/hibernate.S
new file mode 100644
index 000000000000..d37a532519c8
--- /dev/null
+++ b/arch/blackfin/mach-bf609/hibernate.S
@@ -0,0 +1,65 @@
+#include <linux/linkage.h>
+#include <asm/blackfin.h>
+#include <asm/dpmc.h>
+#define PM_STACK   (COREA_L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12)
+.section .l1.text
+ENTRY(_enter_hibernate)
+        /* switch stack to L1 scratch, prepare for ddr srfr */
+        P0.H = HI(PM_STACK);
+        P0.L = LO(PM_STACK);
+        SP = P0;
+        call _bf609_ddr_sr;
+        call _bfin_hibernate_syscontrol;
+        P0.H = HI(DPM0_RESTORE4);
+        P0.L = LO(DPM0_RESTORE4);
+        P1.H = _bf609_pm_data;
+        P1.L = _bf609_pm_data;
+        [P0] = P1;
+        P0.H = HI(DPM0_CTL);
+        P0.L = LO(DPM0_CTL);
+        R3.H = HI(0x00000010);
+        R3.L = LO(0x00000010);
+        bfin_init_pm_bench_cycles;
+        [P0] = R3;
+        SSYNC;
+ENDPROC(_enter_hibernate_mode)
+.section .text
+ENTRY(_bf609_hibernate)
+        bfin_cpu_reg_save;
+        bfin_core_mmr_save;
+        P0.H = _bf609_pm_data;
+        P0.L = _bf609_pm_data;
+        R1.H = 0xDEAD;
+        R1.L = 0xBEEF;
+        R2.H = .Lpm_resume_here;
+        R2.L = .Lpm_resume_here;
+        [P0++] = R1;
+        [P0++] = R2;
+        [P0++] = SP;
+        P1.H = _enter_hibernate;
+        P1.L = _enter_hibernate;
+        call (P1);
+.Lpm_resume_here:
+        bfin_core_mmr_restore;
+        bfin_cpu_reg_restore;
+        [--sp] = RETI;  /* Clear Global Interrupt Disable */
+        SP += 4;
+        RTS;
+ENDPROC(_bf609_hibernate)
diff --git a/arch/blackfin/mach-bf609/include/mach/anomaly.h b/arch/blackfin/mach-bf609/include/mach/anomaly.h
new file mode 100644
index 000000000000..bdd39aefb565
--- /dev/null
+++ b/arch/blackfin/mach-bf609/include/mach/anomaly.h
@@ -0,0 +1,130 @@
+/*
+ * DO NOT EDIT THIS FILE
+ * This file is under version control at
+ *   svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
+ * and can be replaced with that version at any time
+ * DO NOT EDIT THIS FILE
+ *
+ * Copyright 2004-2011 Analog Devices Inc.
+ * Licensed under the Clear BSD license.
+ */
+/* This file should be up to date with:
+ */
+#if __SILICON_REVISION__ < 0
+# error will not work on BF506 silicon version
+#endif
+#ifndef _MACH_ANOMALY_H_
+#define _MACH_ANOMALY_H_
+/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
+#define ANOMALY_05000074 (1)
+/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
+#define ANOMALY_05000119 (1)
+/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
+#define ANOMALY_05000122 (1)
+/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
+#define ANOMALY_05000245 (1)
+/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
+#define ANOMALY_05000254 (1)
+/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
+#define ANOMALY_05000265 (1)
+/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
+#define ANOMALY_05000310 (1)
+/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
+#define ANOMALY_05000366 (1)
+/* Speculative Fetches Can Cause Undesired External FIFO Operations */
+#define ANOMALY_05000416 (1)
+/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
+#define ANOMALY_05000426 (1)
+/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
+#define ANOMALY_05000443 (1)
+/* UART IrDA Receiver Fails on Extended Bit Pulses */
+#define ANOMALY_05000447 (1)
+/* False Hardware Error when RETI Points to Invalid Memory */
+#define ANOMALY_05000461 (1)
+/* PLL Latches Incorrect Settings During Reset */
+#define ANOMALY_05000469 (1)
+/* Incorrect Default MSEL Value in PLL_CTL */
+#define ANOMALY_05000472 (1)
+/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
+#define ANOMALY_05000473 (1)
+/* TESTSET Instruction Cannot Be Interrupted */
+#define ANOMALY_05000477 (1)
+/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
+#define ANOMALY_05000481 (1)
+/* IFLUSH sucks at life */
+#define ANOMALY_05000491 (1)
+/* Tempopary anomaly ID for data loss in MMR read operation if interrupted */
+#define ANOMALY_05001001 (__SILICON_REVISION__ < 1)
+/* Anomalies that don't exist on this proc */
+#define ANOMALY_05000099 (0)
+#define ANOMALY_05000120 (0)
+#define ANOMALY_05000125 (0)
+#define ANOMALY_05000149 (0)
+#define ANOMALY_05000158 (0)
+#define ANOMALY_05000171 (0)
+#define ANOMALY_05000179 (0)
+#define ANOMALY_05000182 (0)
+#define ANOMALY_05000183 (0)
+#define ANOMALY_05000189 (0)
+#define ANOMALY_05000198 (0)
+#define ANOMALY_05000202 (0)
+#define ANOMALY_05000215 (0)
+#define ANOMALY_05000219 (0)
+#define ANOMALY_05000220 (0)
+#define ANOMALY_05000227 (0)
+#define ANOMALY_05000230 (0)
+#define ANOMALY_05000231 (0)
+#define ANOMALY_05000233 (0)
+#define ANOMALY_05000234 (0)
+#define ANOMALY_05000242 (0)
+#define ANOMALY_05000244 (0)
+#define ANOMALY_05000248 (0)
+#define ANOMALY_05000250 (0)
+#define ANOMALY_05000257 (0)
+#define ANOMALY_05000261 (0)
+#define ANOMALY_05000263 (0)
+#define ANOMALY_05000266 (0)
+#define ANOMALY_05000273 (0)
+#define ANOMALY_05000274 (0)
+#define ANOMALY_05000278 (0)
+#define ANOMALY_05000281 (0)
+#define ANOMALY_05000283 (0)
+#define ANOMALY_05000285 (0)
+#define ANOMALY_05000287 (0)
+#define ANOMALY_05000301 (0)
+#define ANOMALY_05000305 (0)
+#define ANOMALY_05000307 (0)
+#define ANOMALY_05000311 (0)
+#define ANOMALY_05000312 (0)
+#define ANOMALY_05000315 (0)
+#define ANOMALY_05000323 (0)
+#define ANOMALY_05000353 (1)
+#define ANOMALY_05000357 (0)
+#define ANOMALY_05000362 (1)
+#define ANOMALY_05000363 (0)
+#define ANOMALY_05000364 (0)
+#define ANOMALY_05000371 (0)
+#define ANOMALY_05000380 (0)
+#define ANOMALY_05000386 (0)
+#define ANOMALY_05000389 (0)
+#define ANOMALY_05000400 (0)
+#define ANOMALY_05000402 (0)
+#define ANOMALY_05000412 (0)
+#define ANOMALY_05000432 (0)
+#define ANOMALY_05000440 (0)
+#define ANOMALY_05000448 (0)
+#define ANOMALY_05000456 (0)
+#define ANOMALY_05000450 (0)
+#define ANOMALY_05000465 (0)
+#define ANOMALY_05000467 (0)
+#define ANOMALY_05000474 (0)
+#define ANOMALY_05000475 (0)
+#define ANOMALY_05000480 (0)
+#define ANOMALY_05000485 (0)
+#endif
diff --git a/arch/blackfin/mach-bf609/include/mach/bf609.h b/arch/blackfin/mach-bf609/include/mach/bf609.h
new file mode 100644
index 000000000000..c897c2a2fbfa
--- /dev/null
+++ b/arch/blackfin/mach-bf609/include/mach/bf609.h
@@ -0,0 +1,93 @@
+/*
+ * Copyright 2011 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+#ifndef __MACH_BF609_H__
+#define __MACH_BF609_H__
+#define OFFSET_(x) ((x) & 0x0000FFFF)
+/*some misc defines*/
+#define IMASK_IVG15             0x8000
+#define IMASK_IVG14             0x4000
+#define IMASK_IVG13             0x2000
+#define IMASK_IVG12             0x1000
+#define IMASK_IVG11             0x0800
+#define IMASK_IVG10             0x0400
+#define IMASK_IVG9              0x0200
+#define IMASK_IVG8              0x0100
+#define IMASK_IVG7              0x0080
+#define IMASK_IVGTMR            0x0040
+#define IMASK_IVGHW             0x0020
+/***************************/
+#define BFIN_DSUBBANKS          4
+#define BFIN_DWAYS              2
+#define BFIN_DLINES             64
+#define BFIN_ISUBBANKS          4
+#define BFIN_IWAYS              4
+#define BFIN_ILINES             32
+#define WAY0_L                  0x1
+#define WAY1_L                  0x2
+#define WAY01_L                 0x3
+#define WAY2_L                  0x4
+#define WAY02_L                 0x5
+#define WAY12_L                 0x6
+#define WAY012_L                0x7
+#define WAY3_L                  0x8
+#define WAY03_L                 0x9
+#define WAY13_L                 0xA
+#define WAY013_L                0xB
+#define WAY32_L                 0xC
+#define WAY320_L                0xD
+#define WAY321_L                0xE
+#define WAYALL_L                0xF
+#define DMC_ENABLE (2<<2)       /*yes, 2, not 1 */
+/********************************* EBIU Settings ************************************/
+#define AMBCTL0VAL      ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
+#define AMBCTL1VAL      ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
+#ifdef CONFIG_C_AMBEN_ALL
+#define V_AMBEN AMBEN_ALL
+#endif
+#ifdef CONFIG_C_AMBEN
+#define V_AMBEN 0x0
+#endif
+#ifdef CONFIG_C_AMBEN_B0
+#define V_AMBEN AMBEN_B0
+#endif
+#ifdef CONFIG_C_AMBEN_B0_B1
+#define V_AMBEN AMBEN_B0_B1
+#endif
+#ifdef CONFIG_C_AMBEN_B0_B1_B2
+#define V_AMBEN AMBEN_B0_B1_B2
+#endif
+#ifdef CONFIG_C_AMCKEN
+#define V_AMCKEN AMCKEN
+#else
+#define V_AMCKEN 0x0
+#endif
+#define AMGCTLVAL       (V_AMBEN | V_AMCKEN)
+#if defined(CONFIG_BF609)
+# define CPU   "BF609"
+# define CPUID 0x27fe   /* temperary fake value */
+#endif
+#ifndef CPU
+#error "Unknown CPU type - This kernel doesn't seem to be configured properly"
+#endif
+#endif  /* __MACH_BF609_H__  */
diff --git a/arch/blackfin/mach-bf609/include/mach/bfin_serial.h b/arch/blackfin/mach-bf609/include/mach/bfin_serial.h
new file mode 100644
index 000000000000..1fd398147fd9
--- /dev/null
+++ b/arch/blackfin/mach-bf609/include/mach/bfin_serial.h
@@ -0,0 +1,17 @@
+/*
+ * mach/bfin_serial.h - Blackfin UART/Serial definitions
+ *
+ * Copyright 2011 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+#ifndef __BFIN_MACH_SERIAL_H__
+#define __BFIN_MACH_SERIAL_H__
+#define BFIN_UART_NR_PORTS      2
+#define BFIN_UART_TX_FIFO_SIZE  8
+#define BFIN_UART_BF60X_STYLE
+#endif
diff --git a/arch/blackfin/mach-bf609/include/mach/blackfin.h b/arch/blackfin/mach-bf609/include/mach/blackfin.h
new file mode 100644
index 000000000000..b1a48c410711
--- /dev/null
+++ b/arch/blackfin/mach-bf609/include/mach/blackfin.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright 2011 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+#ifndef _MACH_BLACKFIN_H_
+#define _MACH_BLACKFIN_H_
+#include "bf609.h"
+#include "anomaly.h"
+#include <asm/def_LPBlackfin.h>
+#ifdef CONFIG_BF609
+# include "defBF609.h"
+#endif
+#ifndef __ASSEMBLY__
+# include <asm/cdef_LPBlackfin.h>
+# ifdef CONFIG_BF609
+#  include "cdefBF609.h"
+# endif
+#endif
+#endif
diff --git a/arch/blackfin/mach-bf609/include/mach/cdefBF609.h b/arch/blackfin/mach-bf609/include/mach/cdefBF609.h
new file mode 100644
index 000000000000..c4f3fe19acda
--- /dev/null
+++ b/arch/blackfin/mach-bf609/include/mach/cdefBF609.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright 2011 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+#ifndef _CDEF_BF609_H
+#define _CDEF_BF609_H
+/* include cdefBF60x_base.h for the set of #defines that are common to all ADSP-BF60x bfin_read_()rocessors */
+#include "cdefBF60x_base.h"
+/* The following are the #defines needed by ADSP-BF609 that are not in the common header */
+#endif /* _CDEF_BF609_H */
diff --git a/arch/blackfin/mach-bf609/include/mach/cdefBF60x_base.h b/arch/blackfin/mach-bf609/include/mach/cdefBF60x_base.h
new file mode 100644
index 000000000000..4954cf3f7e16
--- /dev/null
+++ b/arch/blackfin/mach-bf609/include/mach/cdefBF60x_base.h
@@ -0,0 +1,3252 @@
+/*
+ * Copyright 2011 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+#ifndef _CDEF_BF60X_H
+#define _CDEF_BF60X_H
+/* ************************************************************** */
+/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF60x    */
+/* ************************************************************** */
+/* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */
+#define bfin_read_CHIPID()              bfin_read32(CHIPID)
+#define bfin_write_CHIPID(val)          bfin_write32(CHIPID, val)
+/* System Reset and Interrubfin_read_()t Controller (0xFFC00100 - 0xFFC00104) */
+/* SEC0 Registers */
+#define bfin_read_SEC0_CCTL()           bfin_read32(SEC0_CCTL)
+#define bfin_write_SEC0_CCTL(val)       bfin_write32(SEC0_CCTL, val)
+#define bfin_read_SEC0_CSID()           bfin_read32(SEC0_CSID)
+#define bfin_write_SEC0_CSID(val)       bfin_write32(SEC0_CSID, val)
+#define bfin_read_SEC_GCTL()            bfin_read32(SEC_GCTL)
+#define bfin_write_SEC_GCTL(val)        bfin_write32(SEC_GCTL, val)
+#define bfin_read_SEC_FCTL()            bfin_read32(SEC_FCTL)
+#define bfin_write_SEC_FCTL(val)        bfin_write32(SEC_FCTL, val)
+#define bfin_read_SEC_SCTL(sid)         bfin_read32((SEC_SCTL0 + (sid) * 8))
+#define bfin_write_SEC_SCTL(sid, val)   bfin_write32((SEC_SCTL0 + (sid) * 8), val)
+#define bfin_read_SEC_SSTAT(sid)        bfin_read32((SEC_SSTAT0 + (sid) * 8))
+#define bfin_write_SEC_SSTAT(sid, val)  bfin_write32((SEC_SSTAT0 + (sid) * 8), val)
+/* RCU0 Registers */
+#define bfin_read_RCU0_CTL()            bfin_read32(RCU0_CTL)
+#define bfin_write_RCU0_CTL(val)        bfin_write32(RCU0_CTL, val)
+/* Watchdog Timer Registers */
+#define bfin_read_WDOG_CTL()            bfin_read16(WDOG_CTL)
+#define bfin_write_WDOG_CTL(val)        bfin_write16(WDOG_CTL, val)
+#define bfin_read_WDOG_CNT()            bfin_read32(WDOG_CNT)
+#define bfin_write_WDOG_CNT(val)        bfin_write32(WDOG_CNT, val)
+#define bfin_read_WDOG_STAT()           bfin_read32(WDOG_STAT)
+#define bfin_write_WDOG_STAT(val)       bfin_write32(WDOG_STAT, val)
+/* RTC Registers */
+/* UART0 Registers */
+#define bfin_read_UART0_REVID()         bfin_read32(UART0_REVID)
+#define bfin_write_UART0_REVID(val)     bfin_write32(UART0_REVID, val)
+#define bfin_read_UART0_GCTL()          bfin_read32(UART0_GCTL)
+#define bfin_write_UART0_GCTL(val)      bfin_write32(UART0_GCTL, val)
+#define bfin_read_UART0_STAT()          bfin_read32(UART0_STAT)
+#define bfin_write_UART0_STAT(val)      bfin_write32(UART0_STAT, val)
+#define bfin_read_UART0_SCR()           bfin_read32(UART0_SCR)
+#define bfin_write_UART0_SCR(val)       bfin_write32(UART0_SCR, val)
+#define bfin_read_UART0_CLK()           bfin_read32(UART0_CLK)
+#define bfin_write_UART0_CLK(val)       bfin_write32(UART0_CLK, val)
+#define bfin_read_UART0_IER()           bfin_read32(UART0_IER)
+#define bfin_write_UART0_IER(val)       bfin_write32(UART0_IER, val)
+#define bfin_read_UART0_IER_SET()       bfin_read32(UART0_IER_SET)
+#define bfin_write_UART0_IER_SET(val)   bfin_write32(UART0_IER_SET, val)
+#define bfin_read_UART0_IER_CLEAR()     bfin_read32(UART0_IER_CLEAR)
+#define bfin_write_UART0_IER_CLEAR(val) bfin_write32(UART0_IER_CLEAR, val)
+#define bfin_read_UART0_RBR()           bfin_read32(UART0_RBR)
+#define bfin_write_UART0_RBR(val)       bfin_write32(UART0_RBR, val)
+#define bfin_read_UART0_THR()           bfin_read32(UART0_THR)
+#define bfin_write_UART0_THR(val)       bfin_write32(UART0_THR, val)
+#define bfin_read_UART0_TAIP()          bfin_read32(UART0_TAIP)
+#define bfin_write_UART0_TAIP(val)      bfin_write32(UART0_TAIP, val)
+#define bfin_read_UART0_TSR()           bfin_read32(UART0_TSR)
+#define bfin_write_UART0_TSR(val)       bfin_write32(UART0_TSR, val)
+#define bfin_read_UART0_RSR()           bfin_read32(UART0_RSR)
+#define bfin_write_UART0_RSR(val)       bfin_write32(UART0_RSR, val)
+#define bfin_read_UART0_TXCNT()         bfin_read32(UART0_TXCNT)
+#define bfin_write_UART0_TXCNT(val)     bfin_write32(UART0_TXCNT, val)
+#define bfin_read_UART0_RXCNT()         bfin_read32(UART0_RXCNT)
+#define bfin_write_UART0_RXCNT(val)     bfin_write32(UART0_RXCNT, val)
+/* UART1 Registers */
+#define bfin_read_UART1_REVID()         bfin_read32(UART1_REVID)
+#define bfin_write_UART1_REVID(val)     bfin_write32(UART1_REVID, val)
+#define bfin_read_UART1_GCTL()          bfin_read32(UART1_GCTL)
+#define bfin_write_UART1_GCTL(val)      bfin_write32(UART1_GCTL, val)
+#define bfin_read_UART1_STAT()          bfin_read32(UART1_STAT)
+#define bfin_write_UART1_STAT(val)      bfin_write32(UART1_STAT, val)
+#define bfin_read_UART1_SCR()           bfin_read32(UART1_SCR)
+#define bfin_write_UART1_SCR(val)       bfin_write32(UART1_SCR, val)
+#define bfin_read_UART1_CLK()           bfin_read32(UART1_CLK)
+#define bfin_write_UART1_CLK(val)       bfin_write32(UART1_CLK, val)
+#define bfin_read_UART1_IER()           bfin_read32(UART1_IER)
+#define bfin_write_UART1_IER(val)       bfin_write32(UART1_IER, val)
+#define bfin_read_UART1_IER_SET()       bfin_read32(UART1_IER_SET)
+#define bfin_write_UART1_IER_SET(val)   bfin_write32(UART1_IER_SET, val)
+#define bfin_read_UART1_IER_CLEAR()     bfin_read32(UART1_IER_CLEAR)
+#define bfin_write_UART1_IER_CLEAR(val) bfin_write32(UART1_IER_CLEAR, val)
+#define bfin_read_UART1_RBR()           bfin_read32(UART1_RBR)
+#define bfin_write_UART1_RBR(val)       bfin_write32(UART1_RBR, val)
+#define bfin_read_UART1_THR()           bfin_read32(UART1_THR)
+#define bfin_write_UART1_THR(val)       bfin_write32(UART1_THR, val)
+#define bfin_read_UART1_TAIP()          bfin_read32(UART1_TAIP)
+#define bfin_write_UART1_TAIP(val)      bfin_write32(UART1_TAIP, val)
+#define bfin_read_UART1_TSR()           bfin_read32(UART1_TSR)
+#define bfin_write_UART1_TSR(val)       bfin_write32(UART1_TSR, val)
+#define bfin_read_UART1_RSR()           bfin_read32(UART1_RSR)
+#define bfin_write_UART1_RSR(val)       bfin_write32(UART1_RSR, val)
+#define bfin_read_UART1_TXCNT()         bfin_read32(UART1_TXCNT)
+#define bfin_write_UART1_TXCNT(val)     bfin_write32(UART1_TXCNT, val)
+#define bfin_read_UART1_RXCNT()         bfin_read32(UART1_RXCNT)
+#define bfin_write_UART1_RXCNT(val)     bfin_write32(UART1_RXCNT, val)
+/* SPI0 Registers */
+#define bfin_read_SPI0_CTL()            bfin_read32(SPI0_CTL)
+#define bfin_write_SPI0_CTL(val)        bfin_write32(SPI0_CTL, val)
+#define bfin_read_SPI0_RXCTL()          bfin_read32(SPI0_RXCTL)
+#define bfin_write_SPI0_RXCTL(val)      bfin_write32(SPI0_RXCTL, val)
+#define bfin_read_SPI0_TXCTL()          bfin_read32(SPI0_TXCTL)
+#define bfin_write_SPI0_TXCTL(val)      bfin_write32(SPI0_TXCTL, val)
+#define bfin_read_SPI0_CLK()            bfin_read32(SPI0_CLK)
+#define bfin_write_SPI0_CLK(val)        bfin_write32(SPI0_CLK, val)
+#define bfin_read_SPI0_DLY()            bfin_read32(SPI0_DLY)
+#define bfin_write_SPI0_DLY(val)        bfin_write32(SPI0_DLY, val)
+#define bfin_read_SPI0_SLVSEL()         bfin_read32(SPI0_SLVSEL)
+#define bfin_write_SPI0_SLVSEL(val)     bfin_write32(SPI0_SLVSEL, val)
+#define bfin_read_SPI0_RWC()            bfin_read32(SPI0_RWC)
+#define bfin_write_SPI0_RWC(val)        bfin_write32(SPI0_RWC, val)
+#define bfin_read_SPI0_RWCR()           bfin_read32(SPI0_RWCR)
+#define bfin_write_SPI0_RWCR(val)       bfin_write32(SPI0_RWCR, val)
+#define bfin_read_SPI0_TWC()            bfin_read32(SPI0_TWC)
+#define bfin_write_SPI0_TWC(val)        bfin_write32(SPI0_TWC, val)
+#define bfin_read_SPI0_TWCR()           bfin_read32(SPI0_TWCR)
+#define bfin_write_SPI0_TWCR(val)       bfin_write32(SPI0_TWCR, val)
+#define bfin_read_SPI0_IMSK()           bfin_read32(SPI0_IMSK)
+#define bfin_write_SPI0_IMSK(val)       bfin_write32(SPI0_IMSK, val)
+#define bfin_read_SPI0_IMSK_CLR()       bfin_read32(SPI0_IMSK_CLR)
+#define bfin_write_SPI0_IMSK_CLR(val)   bfin_write32(SPI0_IMSK_CLR, val)
+#define bfin_read_SPI0_IMSK_SET()       bfin_read32(SPI0_IMSK_SET)
+#define bfin_write_SPI0_IMSK_SET(val)   bfin_write32(SPI0_IMSK_SET, val)
+#define bfin_read_SPI0_STAT()           bfin_read32(SPI0_STAT)
+#define bfin_write_SPI0_STAT(val)       bfin_write32(SPI0_STAT, val)
+#define bfin_read_SPI0_ILAT()           bfin_read32(SPI0_ILAT)
+#define bfin_write_SPI0_ILAT(val)       bfin_write32(SPI0_ILAT, val)
+#define bfin_read_SPI0_ILAT_CLR()       bfin_read32(SPI0_ILAT_CLR)
+#define bfin_write_SPI0_ILAT_CLR(val)   bfin_write32(SPI0_ILAT_CLR, val)
+#define bfin_read_SPI0_RFIFO()          bfin_read32(SPI0_RFIFO)
+#define bfin_write_SPI0_RFIFO(val)      bfin_write32(SPI0_RFIFO, val)
+#define bfin_read_SPI0_TFIFO()          bfin_read32(SPI0_TFIFO)
+#define bfin_write_SPI0_TFIFO(val)      bfin_write32(SPI0_TFIFO, val)
+/* SPI1 Registers */
+#define bfin_read_SPI1_CTL()            bfin_read32(SPI1_CTL)
+#define bfin_write_SPI1_CTL(val)        bfin_write32(SPI1_CTL, val)
+#define bfin_read_SPI1_RXCTL()          bfin_read32(SPI1_RXCTL)
+#define bfin_write_SPI1_RXCTL(val)      bfin_write32(SPI1_RXCTL, val)
+#define bfin_read_SPI1_TXCTL()          bfin_read32(SPI1_TXCTL)
+#define bfin_write_SPI1_TXCTL(val)      bfin_write32(SPI1_TXCTL, val)
+#define bfin_read_SPI1_CLK()            bfin_read32(SPI1_CLK)
+#define bfin_write_SPI1_CLK(val)        bfin_write32(SPI1_CLK, val)
+#define bfin_read_SPI1_DLY()            bfin_read32(SPI1_DLY)
+#define bfin_write_SPI1_DLY(val)        bfin_write32(SPI1_DLY, val)
+#define bfin_read_SPI1_SLVSEL()         bfin_read32(SPI1_SLVSEL)
+#define bfin_write_SPI1_SLVSEL(val)     bfin_write32(SPI1_SLVSEL, val)
+#define bfin_read_SPI1_RWC()            bfin_read32(SPI1_RWC)
+#define bfin_write_SPI1_RWC(val)        bfin_write32(SPI1_RWC, val)
+#define bfin_read_SPI1_RWCR()           bfin_read32(SPI1_RWCR)
+#define bfin_write_SPI1_RWCR(val)       bfin_write32(SPI1_RWCR, val)
+#define bfin_read_SPI1_TWC()            bfin_read32(SPI1_TWC)
+#define bfin_write_SPI1_TWC(val)        bfin_write32(SPI1_TWC, val)
+#define bfin_read_SPI1_TWCR()           bfin_read32(SPI1_TWCR)
+#define bfin_write_SPI1_TWCR(val)       bfin_write32(SPI1_TWCR, val)
+#define bfin_read_SPI1_IMSK()           bfin_read32(SPI1_IMSK)
+#define bfin_write_SPI1_IMSK(val)       bfin_write32(SPI1_IMSK, val)
+#define bfin_read_SPI1_IMSK_CLR()       bfin_read32(SPI1_IMSK_CLR)
+#define bfin_write_SPI1_IMSK_CLR(val)   bfin_write32(SPI1_IMSK_CLR, val)
+#define bfin_read_SPI1_IMSK_SET()       bfin_read32(SPI1_IMSK_SET)
+#define bfin_write_SPI1_IMSK_SET(val)   bfin_write32(SPI1_IMSK_SET, val)
+#define bfin_read_SPI1_STAT()           bfin_read32(SPI1_STAT)
+#define bfin_write_SPI1_STAT(val)       bfin_write32(SPI1_STAT, val)
+#define bfin_read_SPI1_ILAT()           bfin_read32(SPI1_ILAT)
+#define bfin_write_SPI1_ILAT(val)       bfin_write32(SPI1_ILAT, val)
+#define bfin_read_SPI1_ILAT_CLR()       bfin_read32(SPI1_ILAT_CLR)
+#define bfin_write_SPI1_ILAT_CLR(val)   bfin_write32(SPI1_ILAT_CLR, val)
+#define bfin_read_SPI1_RFIFO()          bfin_read32(SPI1_RFIFO)
+#define bfin_write_SPI1_RFIFO(val)      bfin_write32(SPI1_RFIFO, val)
+#define bfin_read_SPI1_TFIFO()          bfin_read32(SPI1_TFIFO)
+#define bfin_write_SPI1_TFIFO(val)      bfin_write32(SPI1_TFIFO, val)
+/* Timer 0-7 registers */
+#define bfin_read_TIMER0_CONFIG()            bfin_read16(TIMER0_CONFIG)
+#define bfin_write_TIMER0_CONFIG(val)        bfin_write16(TIMER0_CONFIG, val)
+#define bfin_read_TIMER0_COUNTER()           bfin_read32(TIMER0_COUNTER)
+#define bfin_write_TIMER0_COUNTER(val)       bfin_write32(TIMER0_COUNTER, val)
+#define bfin_read_TIMER0_PERIOD()            bfin_read32(TIMER0_PERIOD)
+#define bfin_write_TIMER0_PERIOD(val)        bfin_write32(TIMER0_PERIOD, val)
+#define bfin_read_TIMER0_WIDTH()             bfin_read32(TIMER0_WIDTH)
+#define bfin_write_TIMER0_WIDTH(val)         bfin_write32(TIMER0_WIDTH, val)
+#define bfin_read_TIMER1_CONFIG()            bfin_read16(TIMER1_CONFIG)
+#define bfin_write_TIMER1_CONFIG(val)        bfin_write16(TIMER1_CONFIG, val)
+#define bfin_read_TIMER1_COUNTER()           bfin_read32(TIMER1_COUNTER)
+#define bfin_write_TIMER1_COUNTER(val)       bfin_write32(TIMER1_COUNTER, val)
+#define bfin_read_TIMER1_PERIOD()            bfin_read32(TIMER1_PERIOD)
+#define bfin_write_TIMER1_PERIOD(val)        bfin_write32(TIMER1_PERIOD, val)
+#define bfin_read_TIMER1_WIDTH()             bfin_read32(TIMER1_WIDTH)
+#define bfin_write_TIMER1_WIDTH(val)         bfin_write32(TIMER1_WIDTH, val)
+#define bfin_read_TIMER2_CONFIG()            bfin_read16(TIMER2_CONFIG)
+#define bfin_write_TIMER2_CONFIG(val)        bfin_write16(TIMER2_CONFIG, val)
+#define bfin_read_TIMER2_COUNTER()           bfin_read32(TIMER2_COUNTER)
+#define bfin_write_TIMER2_COUNTER(val)       bfin_write32(TIMER2_COUNTER, val)
+#define bfin_read_TIMER2_PERIOD()            bfin_read32(TIMER2_PERIOD)
+#define bfin_write_TIMER2_PERIOD(val)        bfin_write32(TIMER2_PERIOD, val)
+#define bfin_read_TIMER2_WIDTH()             bfin_read32(TIMER2_WIDTH)
+#define bfin_write_TIMER2_WIDTH(val)         bfin_write32(TIMER2_WIDTH, val)
+#define bfin_read_TIMER3_CONFIG()            bfin_read16(TIMER3_CONFIG)
+#define bfin_write_TIMER3_CONFIG(val)        bfin_write16(TIMER3_CONFIG, val)
+#define bfin_read_TIMER3_COUNTER()           bfin_read32(TIMER3_COUNTER)
+#define bfin_write_TIMER3_COUNTER(val)       bfin_write32(TIMER3_COUNTER, val)
+#define bfin_read_TIMER3_PERIOD()            bfin_read32(TIMER3_PERIOD)
+#define bfin_write_TIMER3_PERIOD(val)        bfin_write32(TIMER3_PERIOD, val)
+#define bfin_read_TIMER3_WIDTH()             bfin_read32(TIMER3_WIDTH)
+#define bfin_write_TIMER3_WIDTH(val)         bfin_write32(TIMER3_WIDTH, val)
+#define bfin_read_TIMER4_CONFIG()            bfin_read16(TIMER4_CONFIG)
+#define bfin_write_TIMER4_CONFIG(val)        bfin_write16(TIMER4_CONFIG, val)
+#define bfin_read_TIMER4_COUNTER()           bfin_read32(TIMER4_COUNTER)
+#define bfin_write_TIMER4_COUNTER(val)       bfin_write32(TIMER4_COUNTER, val)
+#define bfin_read_TIMER4_PERIOD()            bfin_read32(TIMER4_PERIOD)
+#define bfin_write_TIMER4_PERIOD(val)        bfin_write32(TIMER4_PERIOD, val)
+#define bfin_read_TIMER4_WIDTH()             bfin_read32(TIMER4_WIDTH)
+#define bfin_write_TIMER4_WIDTH(val)         bfin_write32(TIMER4_WIDTH, val)
+#define bfin_read_TIMER5_CONFIG()            bfin_read16(TIMER5_CONFIG)
+#define bfin_write_TIMER5_CONFIG(val)        bfin_write16(TIMER5_CONFIG, val)
+#define bfin_read_TIMER5_COUNTER()           bfin_read32(TIMER5_COUNTER)
+#define bfin_write_TIMER5_COUNTER(val)       bfin_write32(TIMER5_COUNTER, val)
+#define bfin_read_TIMER5_PERIOD()            bfin_read32(TIMER5_PERIOD)
+#define bfin_write_TIMER5_PERIOD(val)        bfin_write32(TIMER5_PERIOD, val)
+#define bfin_read_TIMER5_WIDTH()             bfin_read32(TIMER5_WIDTH)
+#define bfin_write_TIMER5_WIDTH(val)         bfin_write32(TIMER5_WIDTH, val)
+#define bfin_read_TIMER6_CONFIG()            bfin_read16(TIMER6_CONFIG)
+#define bfin_write_TIMER6_CONFIG(val)        bfin_write16(TIMER6_CONFIG, val)
+#define bfin_read_TIMER6_COUNTER()           bfin_read32(TIMER6_COUNTER)
+#define bfin_write_TIMER6_COUNTER(val)       bfin_write32(TIMER6_COUNTER, val)
+#define bfin_read_TIMER6_PERIOD()            bfin_read32(TIMER6_PERIOD)
+#define bfin_write_TIMER6_PERIOD(val)        bfin_write32(TIMER6_PERIOD, val)
+#define bfin_read_TIMER6_WIDTH()             bfin_read32(TIMER6_WIDTH)
+#define bfin_write_TIMER6_WIDTH(val)         bfin_write32(TIMER6_WIDTH, val)
+#define bfin_read_TIMER7_CONFIG()            bfin_read16(TIMER7_CONFIG)
+#define bfin_write_TIMER7_CONFIG(val)        bfin_write16(TIMER7_CONFIG, val)
+#define bfin_read_TIMER7_COUNTER()           bfin_read32(TIMER7_COUNTER)
+#define bfin_write_TIMER7_COUNTER(val)       bfin_write32(TIMER7_COUNTER, val)
+#define bfin_read_TIMER7_PERIOD()            bfin_read32(TIMER7_PERIOD)
+#define bfin_write_TIMER7_PERIOD(val)        bfin_write32(TIMER7_PERIOD, val)
+#define bfin_read_TIMER7_WIDTH()             bfin_read32(TIMER7_WIDTH)
+#define bfin_write_TIMER7_WIDTH(val)         bfin_write32(TIMER7_WIDTH, val)
+/* Two Wire Interface Registers (TWI0) */
+/* SPORT1 Registers */
+/* SMC Registers */
+#define bfin_read_SMC_GCTL() bfin_read32(SMC_GCTL)
+#define bfin_write_SMC_GCTL(val) bfin_write32(SMC_GCTL, val)
+#define bfin_read_SMC_GSTAT() bfin_read32(SMC_GSTAT)
+#define bfin_read_SMC_B0CTL() bfin_read32(SMC_B0CTL)
+#define bfin_write_SMC_B0CTL(val) bfin_write32(SMC_B0CTL, val)
+#define bfin_read_SMC_B0TIM() bfin_read32(SMC_B0TIM)
+#define bfin_write_SMC_B0TIM(val) bfin_write32(SMC_B0TIM, val)
+#define bfin_read_SMC_B0ETIM() bfin_read32(SMC_B0ETIM)
+#define bfin_write_SMC_B0ETIM(val) bfin_write32(SMC_B0ETIM, val)
+#define bfin_read_SMC_B1CTL() bfin_read32(SMC_B1CTL)
+#define bfin_write_SMC_B1CTL(val) bfin_write32(SMC_B1CTL, val)
+#define bfin_read_SMC_B1TIM() bfin_read32(SMC_B1TIM)
+#define bfin_write_SMC_B1TIM(val) bfin_write32(SMC_B1TIM, val)
+#define bfin_read_SMC_B1ETIM() bfin_read32(SMC_B1ETIM)
+#define bfin_write_SMC_B1ETIM(val) bfin_write32(SMC_B1ETIM, val)
+#define bfin_read_SMC_B2CTL() bfin_read32(SMC_B2CTL)
+#define bfin_write_SMC_B2CTL(val) bfin_write32(SMC_B2CTL, val)
+#define bfin_read_SMC_B2TIM() bfin_read32(SMC_B2TIM)
+#define bfin_write_SMC_B2TIM(val) bfin_write32(SMC_B2TIM, val)
+#define bfin_read_SMC_B2ETIM() bfin_read32(SMC_B2ETIM)
+#define bfin_write_SMC_B2ETIM(val) bfin_write32(SMC_B2ETIM, val)
+#define bfin_read_SMC_B3CTL() bfin_read32(SMC_B3CTL)
+#define bfin_write_SMC_B3CTL(val) bfin_write32(SMC_B3CTL, val)
+#define bfin_read_SMC_B3TIM() bfin_read32(SMC_B3TIM)
+#define bfin_write_SMC_B3TIM(val) bfin_write32(SMC_B3TIM, val)
+#define bfin_read_SMC_B3ETIM() bfin_read32(SMC_B3ETIM)
+#define bfin_write_SMC_B3ETIM(val) bfin_write32(SMC_B3ETIM, val)
+/* DDR2 Memory Control Registers */
+#define bfin_read_DMC0_CFG() bfin_read32(DMC0_CFG)
+#define bfin_write_DMC0_CFG(val) bfin_write32(DMC0_CFG, val)
+#define bfin_read_DMC0_TR0() bfin_read32(DMC0_TR0)
+#define bfin_write_DMC0_TR0(val) bfin_write32(DMC0_TR0, val)
+#define bfin_read_DMC0_TR1() bfin_read32(DMC0_TR1)
+#define bfin_write_DMC0_TR1(val) bfin_write32(DMC0_TR1, val)
+#define bfin_read_DMC0_TR2() bfin_read32(DMC0_TR2)
+#define bfin_write_DMC0_TR2(val) bfin_write32(DMC0_TR2, val)
+#define bfin_read_DMC0_MR() bfin_read32(DMC0_MR)
+#define bfin_write_DMC0_MR(val) bfin_write32(DMC0_MR, val)
+#define bfin_read_DMC0_EMR1() bfin_read32(DMC0_EMR1)
+#define bfin_write_DMC0_EMR1(val) bfin_write32(DMC0_EMR1, val)
+#define bfin_read_DMC0_CTL() bfin_read32(DMC0_CTL)
+#define bfin_write_DMC0_CTL(val) bfin_write32(DMC0_CTL, val)
+#define bfin_read_DMC0_STAT() bfin_read32(DMC0_STAT)
+#define bfin_write_DMC0_STAT(val) bfin_write32(DMC0_STAT, val)
+#define bfin_read_DMC0_DLLCTL() bfin_read32(DMC0_DLLCTL)
+#define bfin_write_DMC0_DLLCTL(val) bfin_write32(DMC0_DLLCTL, val)
+/* DDR BankRead and Write Count Registers */
+/* DMA Channel 0 Registers */
+#define bfin_read_DMA0_NEXT_DESC_PTR()          bfin_read32(DMA0_NEXT_DESC_PTR)
+#define bfin_write_DMA0_NEXT_DESC_PTR(val)      bfin_write32(DMA0_NEXT_DESC_PTR, val)
+#define bfin_read_DMA0_START_ADDR()             bfin_read32(DMA0_START_ADDR)
+#define bfin_write_DMA0_START_ADDR(val)         bfin_write32(DMA0_START_ADDR, val)
+#define bfin_read_DMA0_CONFIG()                 bfin_read32(DMA0_CONFIG)
+#define bfin_write_DMA0_CONFIG(val)             bfin_write32(DMA0_CONFIG, val)
+#define bfin_read_DMA0_X_COUNT()                bfin_read32(DMA0_X_COUNT)
+#define bfin_write_DMA0_X_COUNT(val)            bfin_write32(DMA0_X_COUNT, val)
+#define bfin_read_DMA0_X_MODIFY()               bfin_read32(DMA0_X_MODIFY)
+#define bfin_write_DMA0_X_MODIFY(val)           bfin_write32(DMA0_X_MODIFY, val)
+#define bfin_read_DMA0_Y_COUNT()                bfin_read32(DMA0_Y_COUNT)
+#define bfin_write_DMA0_Y_COUNT(val)            bfin_write32(DMA0_Y_COUNT, val)
+#define bfin_read_DMA0_Y_MODIFY()               bfin_read32(DMA0_Y_MODIFY)
+#define bfin_write_DMA0_Y_MODIFY(val)           bfin_write32(DMA0_Y_MODIFY, val)
+#define bfin_read_DMA0_CURR_DESC_PTR()          bfin_read32(DMA0_CURR_DESC_PTR)
+#define bfin_write_DMA0_CURR_DESC_PTR(val)      bfin_write32(DMA0_CURR_DESC_PTR, val)
+#define bfin_read_DMA0_PREV_DESC_PTR()          bfin_read32(DMA0_PREV_DESC_PTR)
+#define bfin_write_DMA0_PREV_DESC_PTR(val)      bfin_write32(DMA0_PREV_DESC_PTR, val)
+#define bfin_read_DMA0_CURR_ADDR()              bfin_read32(DMA0_CURR_ADDR)
+#define bfin_write_DMA0_CURR_ADDR(val)          bfin_write32(DMA0_CURR_ADDR, val)
+#define bfin_read_DMA0_IRQ_STATUS()             bfin_read32(DMA0_IRQ_STATUS)
+#define bfin_write_DMA0_IRQ_STATUS(val)         bfin_write32(DMA0_IRQ_STATUS, val)
+#define bfin_read_DMA0_CURR_X_COUNT()           bfin_read32(DMA0_CURR_X_COUNT)
+#define bfin_write_DMA0_CURR_X_COUNT(val)       bfin_write32(DMA0_CURR_X_COUNT, val)
+#define bfin_read_DMA0_CURR_Y_COUNT()           bfin_read32(DMA0_CURR_Y_COUNT)
+#define bfin_write_DMA0_CURR_Y_COUNT(val)       bfin_write32(DMA0_CURR_Y_COUNT, val)
+#define bfin_read_DMA0_BWL_COUNT()              bfin_read32(DMA0_BWL_COUNT)
+#define bfin_write_DMA0_BWL_COUNT(val)          bfin_write32(DMA0_BWL_COUNT, val)
+#define bfin_read_DMA0_CURR_BWL_COUNT()         bfin_read32(DMA0_CURR_BWL_COUNT)
+#define bfin_write_DMA0_CURR_BWL_COUNT(val)     bfin_write32(DMA0_CURR_BWL_COUNT, val)
+#define bfin_read_DMA0_BWM_COUNT()              bfin_read32(DMA0_BWM_COUNT)
+#define bfin_write_DMA0_BWM_COUNT(val)          bfin_write32(DMA0_BWM_COUNT, val)
+#define bfin_read_DMA0_CURR_BWM_COUNT()         bfin_read32(DMA0_CURR_BWM_COUNT)
+#define bfin_write_DMA0_CURR_BWM_COUNT(val)     bfin_write32(DMA0_CURR_BWM_COUNT, val)
+/* DMA Channel 1 Registers */
+#define bfin_read_DMA1_NEXT_DESC_PTR()          bfin_read32(DMA1_NEXT_DESC_PTR)
+#define bfin_write_DMA1_NEXT_DESC_PTR(val)      bfin_write32(DMA1_NEXT_DESC_PTR, val)
+#define bfin_read_DMA1_START_ADDR()             bfin_read32(DMA1_START_ADDR)
+#define bfin_write_DMA1_START_ADDR(val)         bfin_write32(DMA1_START_ADDR, val)
+#define bfin_read_DMA1_CONFIG()                 bfin_read32(DMA1_CONFIG)
+#define bfin_write_DMA1_CONFIG(val)             bfin_write32(DMA1_CONFIG, val)
+#define bfin_read_DMA1_X_COUNT()                bfin_read32(DMA1_X_COUNT)
+#define bfin_write_DMA1_X_COUNT(val)            bfin_write32(DMA1_X_COUNT, val)
+#define bfin_read_DMA1_X_MODIFY()               bfin_read32(DMA1_X_MODIFY)
+#define bfin_write_DMA1_X_MODIFY(val)           bfin_write32(DMA1_X_MODIFY, val)
+#define bfin_read_DMA1_Y_COUNT()                bfin_read32(DMA1_Y_COUNT)
+#define bfin_write_DMA1_Y_COUNT(val)            bfin_write32(DMA1_Y_COUNT, val)
+#define bfin_read_DMA1_Y_MODIFY()               bfin_read32(DMA1_Y_MODIFY)
+#define bfin_write_DMA1_Y_MODIFY(val)           bfin_write32(DMA1_Y_MODIFY, val)
+#define bfin_read_DMA1_CURR_DESC_PTR()          bfin_read32(DMA1_CURR_DESC_PTR)
+#define bfin_write_DMA1_CURR_DESC_PTR(val)      bfin_write32(DMA1_CURR_DESC_PTR, val)
+#define bfin_read_DMA1_PREV_DESC_PTR()          bfin_read32(DMA1_PREV_DESC_PTR)
+#define bfin_write_DMA1_PREV_DESC_PTR(val)      bfin_write32(DMA1_PREV_DESC_PTR, val)
+#define bfin_read_DMA1_CURR_ADDR()              bfin_read32(DMA1_CURR_ADDR)
+#define bfin_write_DMA1_CURR_ADDR(val)          bfin_write32(DMA1_CURR_ADDR, val)
+#define bfin_read_DMA1_IRQ_STATUS()             bfin_read32(DMA1_IRQ_STATUS)
+#define bfin_write_DMA1_IRQ_STATUS(val)         bfin_write32(DMA1_IRQ_STATUS, val)
+#define bfin_read_DMA1_CURR_X_COUNT()           bfin_read32(DMA1_CURR_X_COUNT)
+#define bfin_write_DMA1_CURR_X_COUNT(val)       bfin_write32(DMA1_CURR_X_COUNT, val)
+#define bfin_read_DMA1_CURR_Y_COUNT()           bfin_read32(DMA1_CURR_Y_COUNT)
+#define bfin_write_DMA1_CURR_Y_COUNT(val)       bfin_write32(DMA1_CURR_Y_COUNT, val)
+#define bfin_read_DMA1_BWL_COUNT()              bfin_read32(DMA1_BWL_COUNT)
+#define bfin_write_DMA1_BWL_COUNT(val)          bfin_write32(DMA1_BWL_COUNT, val)
+#define bfin_read_DMA1_CURR_BWL_COUNT()         bfin_read32(DMA1_CURR_BWL_COUNT)
+#define bfin_write_DMA1_CURR_BWL_COUNT(val)     bfin_write32(DMA1_CURR_BWL_COUNT, val)
+#define bfin_read_DMA1_BWM_COUNT()              bfin_read32(DMA1_BWM_COUNT)
+#define bfin_write_DMA1_BWM_COUNT(val)          bfin_write32(DMA1_BWM_COUNT, val)
+#define bfin_read_DMA1_CURR_BWM_COUNT()         bfin_read32(DMA1_CURR_BWM_COUNT)
+#define bfin_write_DMA1_CURR_BWM_COUNT(val)     bfin_write32(DMA1_CURR_BWM_COUNT, val)
+/* DMA Channel 2 Registers */
+#define bfin_read_DMA2_NEXT_DESC_PTR()          bfin_read32(DMA2_NEXT_DESC_PTR)
+#define bfin_write_DMA2_NEXT_DESC_PTR(val)      bfin_write32(DMA2_NEXT_DESC_PTR, val)
+#define bfin_read_DMA2_START_ADDR()             bfin_read32(DMA2_START_ADDR)
+#define bfin_write_DMA2_START_ADDR(val)         bfin_write32(DMA2_START_ADDR, val)
+#define bfin_read_DMA2_CONFIG()                 bfin_read32(DMA2_CONFIG)
+#define bfin_write_DMA2_CONFIG(val)             bfin_write32(DMA2_CONFIG, val)
+#define bfin_read_DMA2_X_COUNT()                bfin_read32(DMA2_X_COUNT)
+#define bfin_write_DMA2_X_COUNT(val)            bfin_write32(DMA2_X_COUNT, val)
+#define bfin_read_DMA2_X_MODIFY()               bfin_read32(DMA2_X_MODIFY)
+#define bfin_write_DMA2_X_MODIFY(val)           bfin_write32(DMA2_X_MODIFY, val)
+#define bfin_read_DMA2_Y_COUNT()                bfin_read32(DMA2_Y_COUNT)
+#define bfin_write_DMA2_Y_COUNT(val)            bfin_write32(DMA2_Y_COUNT, val)
+#define bfin_read_DMA2_Y_MODIFY()               bfin_read32(DMA2_Y_MODIFY)
+#define bfin_write_DMA2_Y_MODIFY(val)           bfin_write32(DMA2_Y_MODIFY, val)
+#define bfin_read_DMA2_CURR_DESC_PTR()          bfin_read32(DMA2_CURR_DESC_PTR)
+#define bfin_write_DMA2_CURR_DESC_PTR(val)      bfin_write32(DMA2_CURR_DESC_PTR, val)
+#define bfin_read_DMA2_PREV_DESC_PTR()          bfin_read32(DMA2_PREV_DESC_PTR)
+#define bfin_write_DMA2_PREV_DESC_PTR(val)      bfin_write32(DMA2_PREV_DESC_PTR, val)
+#define bfin_read_DMA2_CURR_ADDR()              bfin_read32(DMA2_CURR_ADDR)
+#define bfin_write_DMA2_CURR_ADDR(val)          bfin_write32(DMA2_CURR_ADDR, val)
+#define bfin_read_DMA2_IRQ_STATUS()             bfin_read32(DMA2_IRQ_STATUS)
+#define bfin_write_DMA2_IRQ_STATUS(val)         bfin_write32(DMA2_IRQ_STATUS, val)
+#define bfin_read_DMA2_CURR_X_COUNT()           bfin_read32(DMA2_CURR_X_COUNT)
+#define bfin_write_DMA2_CURR_X_COUNT(val)       bfin_write32(DMA2_CURR_X_COUNT, val)
+#define bfin_read_DMA2_CURR_Y_COUNT()           bfin_read32(DMA2_CURR_Y_COUNT)
+#define bfin_write_DMA2_CURR_Y_COUNT(val)       bfin_write32(DMA2_CURR_Y_COUNT, val)
+#define bfin_read_DMA2_BWL_COUNT()              bfin_read32(DMA2_BWL_COUNT)
+#define bfin_write_DMA2_BWL_COUNT(val)          bfin_write32(DMA2_BWL_COUNT, val)
+#define bfin_read_DMA2_CURR_BWL_COUNT()         bfin_read32(DMA2_CURR_BWL_COUNT)
+#define bfin_write_DMA2_CURR_BWL_COUNT(val)     bfin_write32(DMA2_CURR_BWL_COUNT, val)
+#define bfin_read_DMA2_BWM_COUNT()              bfin_read32(DMA2_BWM_COUNT)
+#define bfin_write_DMA2_BWM_COUNT(val)          bfin_write32(DMA2_BWM_COUNT, val)
+#define bfin_read_DMA2_CURR_BWM_COUNT()         bfin_read32(DMA2_CURR_BWM_COUNT)
+#define bfin_write_DMA2_CURR_BWM_COUNT(val)     bfin_write32(DMA2_CURR_BWM_COUNT, val)
+/* DMA Channel 3 Registers */
+#define bfin_read_DMA3_NEXT_DESC_PTR()          bfin_read32(DMA3_NEXT_DESC_PTR)
+#define bfin_write_DMA3_NEXT_DESC_PTR(val)      bfin_write32(DMA3_NEXT_DESC_PTR, val)
+#define bfin_read_DMA3_START_ADDR()             bfin_read32(DMA3_START_ADDR)
+#define bfin_write_DMA3_START_ADDR(val)         bfin_write32(DMA3_START_ADDR, val)
+#define bfin_read_DMA3_CONFIG()                 bfin_read32(DMA3_CONFIG)
+#define bfin_write_DMA3_CONFIG(val)             bfin_write32(DMA3_CONFIG, val)
+#define bfin_read_DMA3_X_COUNT()                bfin_read32(DMA3_X_COUNT)
+#define bfin_write_DMA3_X_COUNT(val)            bfin_write32(DMA3_X_COUNT, val)
+#define bfin_read_DMA3_X_MODIFY()               bfin_read32(DMA3_X_MODIFY)
+#define bfin_write_DMA3_X_MODIFY(val)           bfin_write32(DMA3_X_MODIFY, val)
+#define bfin_read_DMA3_Y_COUNT()                bfin_read32(DMA3_Y_COUNT)
+#define bfin_write_DMA3_Y_COUNT(val)            bfin_write32(DMA3_Y_COUNT, val)
+#define bfin_read_DMA3_Y_MODIFY()               bfin_read32(DMA3_Y_MODIFY)
+#define bfin_write_DMA3_Y_MODIFY(val)           bfin_write32(DMA3_Y_MODIFY, val)
+#define bfin_read_DMA3_CURR_DESC_PTR()          bfin_read32(DMA3_CURR_DESC_PTR)
+#define bfin_write_DMA3_CURR_DESC_PTR(val)      bfin_write32(DMA3_CURR_DESC_PTR, val)
+#define bfin_read_DMA3_PREV_DESC_PTR()          bfin_read32(DMA3_PREV_DESC_PTR)
+#define bfin_write_DMA3_PREV_DESC_PTR(val)      bfin_write32(DMA3_PREV_DESC_PTR, val)
+#define bfin_read_DMA3_CURR_ADDR()              bfin_read32(DMA3_CURR_ADDR)
+#define bfin_write_DMA3_CURR_ADDR(val)          bfin_write32(DMA3_CURR_ADDR, val)
+#define bfin_read_DMA3_IRQ_STATUS()             bfin_read32(DMA3_IRQ_STATUS)
+#define bfin_write_DMA3_IRQ_STATUS(val)         bfin_write32(DMA3_IRQ_STATUS, val)
+#define bfin_read_DMA3_CURR_X_COUNT()           bfin_read32(DMA3_CURR_X_COUNT)
+#define bfin_write_DMA3_CURR_X_COUNT(val)       bfin_write32(DMA3_CURR_X_COUNT, val)
+#define bfin_read_DMA3_CURR_Y_COUNT()           bfin_read32(DMA3_CURR_Y_COUNT)
+#define bfin_write_DMA3_CURR_Y_COUNT(val)       bfin_write32(DMA3_CURR_Y_COUNT, val)
+#define bfin_read_DMA3_BWL_COUNT()              bfin_read32(DMA3_BWL_COUNT)
+#define bfin_write_DMA3_BWL_COUNT(val)          bfin_write32(DMA3_BWL_COUNT, val)
+#define bfin_read_DMA3_CURR_BWL_COUNT()         bfin_read32(DMA3_CURR_BWL_COUNT)
+#define bfin_write_DMA3_CURR_BWL_COUNT(val)     bfin_write32(DMA3_CURR_BWL_COUNT, val)
+#define bfin_read_DMA3_BWM_COUNT()              bfin_read32(DMA3_BWM_COUNT)
+#define bfin_write_DMA3_BWM_COUNT(val)          bfin_write32(DMA3_BWM_COUNT, val)
+#define bfin_read_DMA3_CURR_BWM_COUNT()         bfin_read32(DMA3_CURR_BWM_COUNT)
+#define bfin_write_DMA3_CURR_BWM_COUNT(val)     bfin_write32(DMA3_CURR_BWM_COUNT, val)
+/* DMA Channel 4 Registers */
+#define bfin_read_DMA4_NEXT_DESC_PTR()          bfin_read32(DMA4_NEXT_DESC_PTR)
+#define bfin_write_DMA4_NEXT_DESC_PTR(val)      bfin_write32(DMA4_NEXT_DESC_PTR, val)
+#define bfin_read_DMA4_START_ADDR()             bfin_read32(DMA4_START_ADDR)
+#define bfin_write_DMA4_START_ADDR(val)         bfin_write32(DMA4_START_ADDR, val)
+#define bfin_read_DMA4_CONFIG()                 bfin_read32(DMA4_CONFIG)
+#define bfin_write_DMA4_CONFIG(val)             bfin_write32(DMA4_CONFIG, val)
+#define bfin_read_DMA4_X_COUNT()                bfin_read32(DMA4_X_COUNT)
+#define bfin_write_DMA4_X_COUNT(val)            bfin_write32(DMA4_X_COUNT, val)
+#define bfin_read_DMA4_X_MODIFY()               bfin_read32(DMA4_X_MODIFY)
+#define bfin_write_DMA4_X_MODIFY(val)           bfin_write32(DMA4_X_MODIFY, val)
+#define bfin_read_DMA4_Y_COUNT()                bfin_read32(DMA4_Y_COUNT)
+#define bfin_write_DMA4_Y_COUNT(val)            bfin_write32(DMA4_Y_COUNT, val)
+#define bfin_read_DMA4_Y_MODIFY()               bfin_read32(DMA4_Y_MODIFY)
+#define bfin_write_DMA4_Y_MODIFY(val)           bfin_write32(DMA4_Y_MODIFY, val)
+#define bfin_read_DMA4_CURR_DESC_PTR()          bfin_read32(DMA4_CURR_DESC_PTR)
+#define bfin_write_DMA4_CURR_DESC_PTR(val)      bfin_write32(DMA4_CURR_DESC_PTR, val)
+#define bfin_read_DMA4_PREV_DESC_PTR()          bfin_read32(DMA4_PREV_DESC_PTR)
+#define bfin_write_DMA4_PREV_DESC_PTR(val)      bfin_write32(DMA4_PREV_DESC_PTR, val)
+#define bfin_read_DMA4_CURR_ADDR()              bfin_read32(DMA4_CURR_ADDR)
+#define bfin_write_DMA4_CURR_ADDR(val)          bfin_write32(DMA4_CURR_ADDR, val)
+#define bfin_read_DMA4_IRQ_STATUS()             bfin_read32(DMA4_IRQ_STATUS)
+#define bfin_write_DMA4_IRQ_STATUS(val)         bfin_write32(DMA4_IRQ_STATUS, val)
+#define bfin_read_DMA4_CURR_X_COUNT()           bfin_read32(DMA4_CURR_X_COUNT)
+#define bfin_write_DMA4_CURR_X_COUNT(val)       bfin_write32(DMA4_CURR_X_COUNT, val)
+#define bfin_read_DMA4_CURR_Y_COUNT()           bfin_read32(DMA4_CURR_Y_COUNT)
+#define bfin_write_DMA4_CURR_Y_COUNT(val)       bfin_write32(DMA4_CURR_Y_COUNT, val)
+#define bfin_read_DMA4_BWL_COUNT()              bfin_read32(DMA4_BWL_COUNT)
+#define bfin_write_DMA4_BWL_COUNT(val)          bfin_write32(DMA4_BWL_COUNT, val)
+#define bfin_read_DMA4_CURR_BWL_COUNT()         bfin_read32(DMA4_CURR_BWL_COUNT)
+#define bfin_write_DMA4_CURR_BWL_COUNT(val)     bfin_write32(DMA4_CURR_BWL_COUNT, val)
+#define bfin_read_DMA4_BWM_COUNT()              bfin_read32(DMA4_BWM_COUNT)
+#define bfin_write_DMA4_BWM_COUNT(val)          bfin_write32(DMA4_BWM_COUNT, val)
+#define bfin_read_DMA4_CURR_BWM_COUNT()         bfin_read32(DMA4_CURR_BWM_COUNT)
+#define bfin_write_DMA4_CURR_BWM_COUNT(val)     bfin_write32(DMA4_CURR_BWM_COUNT, val)
+/* DMA Channel 5 Registers */
+#define bfin_read_DMA5_NEXT_DESC_PTR()          bfin_read32(DMA5_NEXT_DESC_PTR)
+#define bfin_write_DMA5_NEXT_DESC_PTR(val)      bfin_write32(DMA5_NEXT_DESC_PTR, val)
+#define bfin_read_DMA5_START_ADDR()             bfin_read32(DMA5_START_ADDR)
+#define bfin_write_DMA5_START_ADDR(val)         bfin_write32(DMA5_START_ADDR, val)
+#define bfin_read_DMA5_CONFIG()                 bfin_read32(DMA5_CONFIG)
+#define bfin_write_DMA5_CONFIG(val)             bfin_write32(DMA5_CONFIG, val)
+#define bfin_read_DMA5_X_COUNT()                bfin_read32(DMA5_X_COUNT)
+#define bfin_write_DMA5_X_COUNT(val)            bfin_write32(DMA5_X_COUNT, val)
+#define bfin_read_DMA5_X_MODIFY()               bfin_read32(DMA5_X_MODIFY)
+#define bfin_write_DMA5_X_MODIFY(val)           bfin_write32(DMA5_X_MODIFY, val)
+#define bfin_read_DMA5_Y_COUNT()                bfin_read32(DMA5_Y_COUNT)
+#define bfin_write_DMA5_Y_COUNT(val)            bfin_write32(DMA5_Y_COUNT, val)
+#define bfin_read_DMA5_Y_MODIFY()               bfin_read32(DMA5_Y_MODIFY)
+#define bfin_write_DMA5_Y_MODIFY(val)           bfin_write32(DMA5_Y_MODIFY, val)
+#define bfin_read_DMA5_CURR_DESC_PTR()          bfin_read32(DMA5_CURR_DESC_PTR)
+#define bfin_write_DMA5_CURR_DESC_PTR(val)      bfin_write32(DMA5_CURR_DESC_PTR, val)
+#define bfin_read_DMA5_PREV_DESC_PTR()          bfin_read32(DMA5_PREV_DESC_PTR)
+#define bfin_write_DMA5_PREV_DESC_PTR(val)      bfin_write32(DMA5_PREV_DESC_PTR, val)
+#define bfin_read_DMA5_CURR_ADDR()              bfin_read32(DMA5_CURR_ADDR)
+#define bfin_write_DMA5_CURR_ADDR(val)          bfin_write32(DMA5_CURR_ADDR, val)
+#define bfin_read_DMA5_IRQ_STATUS()             bfin_read32(DMA5_IRQ_STATUS)
+#define bfin_write_DMA5_IRQ_STATUS(val)         bfin_write32(DMA5_IRQ_STATUS, val)
+#define bfin_read_DMA5_CURR_X_COUNT()           bfin_read32(DMA5_CURR_X_COUNT)
+#define bfin_write_DMA5_CURR_X_COUNT(val)       bfin_write32(DMA5_CURR_X_COUNT, val)
+#define bfin_read_DMA5_CURR_Y_COUNT()           bfin_read32(DMA5_CURR_Y_COUNT)
+#define bfin_write_DMA5_CURR_Y_COUNT(val)       bfin_write32(DMA5_CURR_Y_COUNT, val)
+#define bfin_read_DMA5_BWL_COUNT()              bfin_read32(DMA5_BWL_COUNT)
+#define bfin_write_DMA5_BWL_COUNT(val)          bfin_write32(DMA5_BWL_COUNT, val)
+#define bfin_read_DMA5_CURR_BWL_COUNT()         bfin_read32(DMA5_CURR_BWL_COUNT)
+#define bfin_write_DMA5_CURR_BWL_COUNT(val)     bfin_write32(DMA5_CURR_BWL_COUNT, val)
+#define bfin_read_DMA5_BWM_COUNT()              bfin_read32(DMA5_BWM_COUNT)
+#define bfin_write_DMA5_BWM_COUNT(val)          bfin_write32(DMA5_BWM_COUNT, val)
+#define bfin_read_DMA5_CURR_BWM_COUNT()         bfin_read32(DMA5_CURR_BWM_COUNT)
+#define bfin_write_DMA5_CURR_BWM_COUNT(val)     bfin_write32(DMA5_CURR_BWM_COUNT, val)
+/* DMA Channel 6 Registers */
+#define bfin_read_DMA6_NEXT_DESC_PTR()          bfin_read32(DMA6_NEXT_DESC_PTR)
+#define bfin_write_DMA6_NEXT_DESC_PTR(val)      bfin_write32(DMA6_NEXT_DESC_PTR, val)
+#define bfin_read_DMA6_START_ADDR()             bfin_read32(DMA6_START_ADDR)
+#define bfin_write_DMA6_START_ADDR(val)         bfin_write32(DMA6_START_ADDR, val)
+#define bfin_read_DMA6_CONFIG()                 bfin_read32(DMA6_CONFIG)
+#define bfin_write_DMA6_CONFIG(val)             bfin_write32(DMA6_CONFIG, val)
+#define bfin_read_DMA6_X_COUNT()                bfin_read32(DMA6_X_COUNT)
+#define bfin_write_DMA6_X_COUNT(val)            bfin_write32(DMA6_X_COUNT, val)
+#define bfin_read_DMA6_X_MODIFY()               bfin_read32(DMA6_X_MODIFY)
+#define bfin_write_DMA6_X_MODIFY(val)           bfin_write32(DMA6_X_MODIFY, val)
+#define bfin_read_DMA6_Y_COUNT()                bfin_read32(DMA6_Y_COUNT)
+#define bfin_write_DMA6_Y_COUNT(val)            bfin_write32(DMA6_Y_COUNT, val)
+#define bfin_read_DMA6_Y_MODIFY()               bfin_read32(DMA6_Y_MODIFY)
+#define bfin_write_DMA6_Y_MODIFY(val)           bfin_write32(DMA6_Y_MODIFY, val)
+#define bfin_read_DMA6_CURR_DESC_PTR()          bfin_read32(DMA6_CURR_DESC_PTR)
+#define bfin_write_DMA6_CURR_DESC_PTR(val)      bfin_write32(DMA6_CURR_DESC_PTR, val)
+#define bfin_read_DMA6_PREV_DESC_PTR()          bfin_read32(DMA6_PREV_DESC_PTR)
+#define bfin_write_DMA6_PREV_DESC_PTR(val)      bfin_write32(DMA6_PREV_DESC_PTR, val)
+#define bfin_read_DMA6_CURR_ADDR()              bfin_read32(DMA6_CURR_ADDR)
+#define bfin_write_DMA6_CURR_ADDR(val)          bfin_write32(DMA6_CURR_ADDR, val)
+#define bfin_read_DMA6_IRQ_STATUS()             bfin_read32(DMA6_IRQ_STATUS)
+#define bfin_write_DMA6_IRQ_STATUS(val)         bfin_write32(DMA6_IRQ_STATUS, val)
+#define bfin_read_DMA6_CURR_X_COUNT()           bfin_read32(DMA6_CURR_X_COUNT)
+#define bfin_write_DMA6_CURR_X_COUNT(val)       bfin_write32(DMA6_CURR_X_COUNT, val)
+#define bfin_read_DMA6_CURR_Y_COUNT()           bfin_read32(DMA6_CURR_Y_COUNT)
+#define bfin_write_DMA6_CURR_Y_COUNT(val)       bfin_write32(DMA6_CURR_Y_COUNT, val)
+#define bfin_read_DMA6_BWL_COUNT()              bfin_read32(DMA6_BWL_COUNT)
+#define bfin_write_DMA6_BWL_COUNT(val)          bfin_write32(DMA6_BWL_COUNT, val)
+#define bfin_read_DMA6_CURR_BWL_COUNT()         bfin_read32(DMA6_CURR_BWL_COUNT)
+#define bfin_write_DMA6_CURR_BWL_COUNT(val)     bfin_write32(DMA6_CURR_BWL_COUNT, val)
+#define bfin_read_DMA6_BWM_COUNT()              bfin_read32(DMA6_BWM_COUNT)
+#define bfin_write_DMA6_BWM_COUNT(val)          bfin_write32(DMA6_BWM_COUNT, val)
+#define bfin_read_DMA6_CURR_BWM_COUNT()         bfin_read32(DMA6_CURR_BWM_COUNT)
+#define bfin_write_DMA6_CURR_BWM_COUNT(val)     bfin_write32(DMA6_CURR_BWM_COUNT, val)
+/* DMA Channel 7 Registers */
+#define bfin_read_DMA7_NEXT_DESC_PTR()          bfin_read32(DMA7_NEXT_DESC_PTR)
+#define bfin_write_DMA7_NEXT_DESC_PTR(val)      bfin_write32(DMA7_NEXT_DESC_PTR, val)
+#define bfin_read_DMA7_START_ADDR()             bfin_read32(DMA7_START_ADDR)
+#define bfin_write_DMA7_START_ADDR(val)         bfin_write32(DMA7_START_ADDR, val)
+#define bfin_read_DMA7_CONFIG()                 bfin_read32(DMA7_CONFIG)
+#define bfin_write_DMA7_CONFIG(val)             bfin_write32(DMA7_CONFIG, val)
+#define bfin_read_DMA7_X_COUNT()                bfin_read32(DMA7_X_COUNT)
+#define bfin_write_DMA7_X_COUNT(val)            bfin_write32(DMA7_X_COUNT, val)
+#define bfin_read_DMA7_X_MODIFY()               bfin_read32(DMA7_X_MODIFY)
+#define bfin_write_DMA7_X_MODIFY(val)           bfin_write32(DMA7_X_MODIFY, val)
+#define bfin_read_DMA7_Y_COUNT()                bfin_read32(DMA7_Y_COUNT)
+#define bfin_write_DMA7_Y_COUNT(val)            bfin_write32(DMA7_Y_COUNT, val)
+#define bfin_read_DMA7_Y_MODIFY()               bfin_read32(DMA7_Y_MODIFY)
+#define bfin_write_DMA7_Y_MODIFY(val)           bfin_write32(DMA7_Y_MODIFY, val)
+#define bfin_read_DMA7_CURR_DESC_PTR()          bfin_read32(DMA7_CURR_DESC_PTR)
+#define bfin_write_DMA7_CURR_DESC_PTR(val)      bfin_write32(DMA7_CURR_DESC_PTR, val)
+#define bfin_read_DMA7_PREV_DESC_PTR()          bfin_read32(DMA7_PREV_DESC_PTR)
+#define bfin_write_DMA7_PREV_DESC_PTR(val)      bfin_write32(DMA7_PREV_DESC_PTR, val)
+#define bfin_read_DMA7_CURR_ADDR()              bfin_read32(DMA7_CURR_ADDR)
+#define bfin_write_DMA7_CURR_ADDR(val)          bfin_write32(DMA7_CURR_ADDR, val)
+#define bfin_read_DMA7_IRQ_STATUS()             bfin_read32(DMA7_IRQ_STATUS)
+#define bfin_write_DMA7_IRQ_STATUS(val)         bfin_write32(DMA7_IRQ_STATUS, val)
+#define bfin_read_DMA7_CURR_X_COUNT()           bfin_read32(DMA7_CURR_X_COUNT)
+#define bfin_write_DMA7_CURR_X_COUNT(val)       bfin_write32(DMA7_CURR_X_COUNT, val)
+#define bfin_read_DMA7_CURR_Y_COUNT()           bfin_read32(DMA7_CURR_Y_COUNT)
+#define bfin_write_DMA7_CURR_Y_COUNT(val)       bfin_write32(DMA7_CURR_Y_COUNT, val)
+#define bfin_read_DMA7_BWL_COUNT()              bfin_read32(DMA7_BWL_COUNT)
+#define bfin_write_DMA7_BWL_COUNT(val)          bfin_write32(DMA7_BWL_COUNT, val)
+#define bfin_read_DMA7_CURR_BWL_COUNT()         bfin_read32(DMA7_CURR_BWL_COUNT)
+#define bfin_write_DMA7_CURR_BWL_COUNT(val)     bfin_write32(DMA7_CURR_BWL_COUNT, val)
+#define bfin_read_DMA7_BWM_COUNT()              bfin_read32(DMA7_BWM_COUNT)
+#define bfin_write_DMA7_BWM_COUNT(val)          bfin_write32(DMA7_BWM_COUNT, val)
+#define bfin_read_DMA7_CURR_BWM_COUNT()         bfin_read32(DMA7_CURR_BWM_COUNT)
+#define bfin_write_DMA7_CURR_BWM_COUNT(val)     bfin_write32(DMA7_CURR_BWM_COUNT, val)
+/* DMA Channel 8 Registers */
+#define bfin_read_DMA8_NEXT_DESC_PTR()          bfin_read32(DMA8_NEXT_DESC_PTR)
+#define bfin_write_DMA8_NEXT_DESC_PTR(val)      bfin_write32(DMA8_NEXT_DESC_PTR, val)
+#define bfin_read_DMA8_START_ADDR()             bfin_read32(DMA8_START_ADDR)
+#define bfin_write_DMA8_START_ADDR(val)         bfin_write32(DMA8_START_ADDR, val)
+#define bfin_read_DMA8_CONFIG()                 bfin_read32(DMA8_CONFIG)
+#define bfin_write_DMA8_CONFIG(val)             bfin_write32(DMA8_CONFIG, val)
+#define bfin_read_DMA8_X_COUNT()                bfin_read32(DMA8_X_COUNT)
+#define bfin_write_DMA8_X_COUNT(val)            bfin_write32(DMA8_X_COUNT, val)
+#define bfin_read_DMA8_X_MODIFY()               bfin_read32(DMA8_X_MODIFY)
+#define bfin_write_DMA8_X_MODIFY(val)           bfin_write32(DMA8_X_MODIFY, val)
+#define bfin_read_DMA8_Y_COUNT()                bfin_read32(DMA8_Y_COUNT)
+#define bfin_write_DMA8_Y_COUNT(val)            bfin_write32(DMA8_Y_COUNT, val)
+#define bfin_read_DMA8_Y_MODIFY()               bfin_read32(DMA8_Y_MODIFY)
+#define bfin_write_DMA8_Y_MODIFY(val)           bfin_write32(DMA8_Y_MODIFY, val)
+#define bfin_read_DMA8_CURR_DESC_PTR()          bfin_read32(DMA8_CURR_DESC_PTR)
+#define bfin_write_DMA8_CURR_DESC_PTR(val)      bfin_write32(DMA8_CURR_DESC_PTR, val)
+#define bfin_read_DMA8_PREV_DESC_PTR()          bfin_read32(DMA8_PREV_DESC_PTR)
+#define bfin_write_DMA8_PREV_DESC_PTR(val)      bfin_write32(DMA8_PREV_DESC_PTR, val)
+#define bfin_read_DMA8_CURR_ADDR()              bfin_read32(DMA8_CURR_ADDR)
+#define bfin_write_DMA8_CURR_ADDR(val)          bfin_write32(DMA8_CURR_ADDR, val)
+#define bfin_read_DMA8_IRQ_STATUS()             bfin_read32(DMA8_IRQ_STATUS)
+#define bfin_write_DMA8_IRQ_STATUS(val)         bfin_write32(DMA8_IRQ_STATUS, val)
+#define bfin_read_DMA8_CURR_X_COUNT()           bfin_read32(DMA8_CURR_X_COUNT)
+#define bfin_write_DMA8_CURR_X_COUNT(val)       bfin_write32(DMA8_CURR_X_COUNT, val)
+#define bfin_read_DMA8_CURR_Y_COUNT()           bfin_read32(DMA8_CURR_Y_COUNT)
+#define bfin_write_DMA8_CURR_Y_COUNT(val)       bfin_write32(DMA8_CURR_Y_COUNT, val)
+#define bfin_read_DMA8_BWL_COUNT()              bfin_read32(DMA8_BWL_COUNT)
+#define bfin_write_DMA8_BWL_COUNT(val)          bfin_write32(DMA8_BWL_COUNT, val)
+#define bfin_read_DMA8_CURR_BWL_COUNT()         bfin_read32(DMA8_CURR_BWL_COUNT)
+#define bfin_write_DMA8_CURR_BWL_COUNT(val)     bfin_write32(DMA8_CURR_BWL_COUNT, val)
+#define bfin_read_DMA8_BWM_COUNT()              bfin_read32(DMA8_BWM_COUNT)
+#define bfin_write_DMA8_BWM_COUNT(val)          bfin_write32(DMA8_BWM_COUNT, val)
+#define bfin_read_DMA8_CURR_BWM_COUNT()         bfin_read32(DMA8_CURR_BWM_COUNT)
+#define bfin_write_DMA8_CURR_BWM_COUNT(val)     bfin_write32(DMA8_CURR_BWM_COUNT, val)
+/* DMA Channel 9 Registers */
+#define bfin_read_DMA9_NEXT_DESC_PTR()          bfin_read32(DMA9_NEXT_DESC_PTR)
+#define bfin_write_DMA9_NEXT_DESC_PTR(val)      bfin_write32(DMA9_NEXT_DESC_PTR, val)
+#define bfin_read_DMA9_START_ADDR()             bfin_read32(DMA9_START_ADDR)
+#define bfin_write_DMA9_START_ADDR(val)         bfin_write32(DMA9_START_ADDR, val)
+#define bfin_read_DMA9_CONFIG()                 bfin_read32(DMA9_CONFIG)
+#define bfin_write_DMA9_CONFIG(val)             bfin_write32(DMA9_CONFIG, val)
+#define bfin_read_DMA9_X_COUNT()                bfin_read32(DMA9_X_COUNT)
+#define bfin_write_DMA9_X_COUNT(val)            bfin_write32(DMA9_X_COUNT, val)
+#define bfin_read_DMA9_X_MODIFY()               bfin_read32(DMA9_X_MODIFY)
+#define bfin_write_DMA9_X_MODIFY(val)           bfin_write32(DMA9_X_MODIFY, val)
+#define bfin_read_DMA9_Y_COUNT()                bfin_read32(DMA9_Y_COUNT)
+#define bfin_write_DMA9_Y_COUNT(val)            bfin_write32(DMA9_Y_COUNT, val)
+#define bfin_read_DMA9_Y_MODIFY()               bfin_read32(DMA9_Y_MODIFY)
+#define bfin_write_DMA9_Y_MODIFY(val)           bfin_write32(DMA9_Y_MODIFY, val)
+#define bfin_read_DMA9_CURR_DESC_PTR()          bfin_read32(DMA9_CURR_DESC_PTR)
+#define bfin_write_DMA9_CURR_DESC_PTR(val)      bfin_write32(DMA9_CURR_DESC_PTR, val)
+#define bfin_read_DMA9_PREV_DESC_PTR()          bfin_read32(DMA9_PREV_DESC_PTR)
+#define bfin_write_DMA9_PREV_DESC_PTR(val)      bfin_write32(DMA9_PREV_DESC_PTR, val)
+#define bfin_read_DMA9_CURR_ADDR()              bfin_read32(DMA9_CURR_ADDR)
+#define bfin_write_DMA9_CURR_ADDR(val)          bfin_write32(DMA9_CURR_ADDR, val)
+#define bfin_read_DMA9_IRQ_STATUS()             bfin_read32(DMA9_IRQ_STATUS)
+#define bfin_write_DMA9_IRQ_STATUS(val)         bfin_write32(DMA9_IRQ_STATUS, val)
+#define bfin_read_DMA9_CURR_X_COUNT()           bfin_read32(DMA9_CURR_X_COUNT)
+#define bfin_write_DMA9_CURR_X_COUNT(val)       bfin_write32(DMA9_CURR_X_COUNT, val)
+#define bfin_read_DMA9_CURR_Y_COUNT()           bfin_read32(DMA9_CURR_Y_COUNT)
+#define bfin_write_DMA9_CURR_Y_COUNT(val)       bfin_write32(DMA9_CURR_Y_COUNT, val)
+#define bfin_read_DMA9_BWL_COUNT()              bfin_read32(DMA9_BWL_COUNT)
+#define bfin_write_DMA9_BWL_COUNT(val)          bfin_write32(DMA9_BWL_COUNT, val)
+#define bfin_read_DMA9_CURR_BWL_COUNT()         bfin_read32(DMA9_CURR_BWL_COUNT)
+#define bfin_write_DMA9_CURR_BWL_COUNT(val)     bfin_write32(DMA9_CURR_BWL_COUNT, val)
+#define bfin_read_DMA9_BWM_COUNT()              bfin_read32(DMA9_BWM_COUNT)
+#define bfin_write_DMA9_BWM_COUNT(val)          bfin_write32(DMA9_BWM_COUNT, val)
+#define bfin_read_DMA9_CURR_BWM_COUNT()         bfin_read32(DMA9_CURR_BWM_COUNT)
+#define bfin_write_DMA9_CURR_BWM_COUNT(val)     bfin_write32(DMA9_CURR_BWM_COUNT, val)
+/* DMA Channel 10 Registers */
+#define bfin_read_DMA10_NEXT_DESC_PTR()         bfin_read32(DMA10_NEXT_DESC_PTR)
+#define bfin_write_DMA10_NEXT_DESC_PTR(val)     bfin_write32(DMA10_NEXT_DESC_PTR, val)
+#define bfin_read_DMA10_START_ADDR()            bfin_read32(DMA10_START_ADDR)
+#define bfin_write_DMA10_START_ADDR(val)        bfin_write32(DMA10_START_ADDR, val)
+#define bfin_read_DMA10_CONFIG()                bfin_read32(DMA10_CONFIG)
+#define bfin_write_DMA10_CONFIG(val)            bfin_write32(DMA10_CONFIG, val)
+#define bfin_read_DMA10_X_COUNT()               bfin_read32(DMA10_X_COUNT)
+#define bfin_write_DMA10_X_COUNT(val)           bfin_write32(DMA10_X_COUNT, val)
+#define bfin_read_DMA10_X_MODIFY()              bfin_read32(DMA10_X_MODIFY)
+#define bfin_write_DMA10_X_MODIFY(val)          bfin_write32(DMA10_X_MODIFY, val)
+#define bfin_read_DMA10_Y_COUNT()               bfin_read32(DMA10_Y_COUNT)
+#define bfin_write_DMA10_Y_COUNT(val)           bfin_write32(DMA10_Y_COUNT, val)
+#define bfin_read_DMA10_Y_MODIFY()              bfin_read32(DMA10_Y_MODIFY)
+#define bfin_write_DMA10_Y_MODIFY(val)          bfin_write32(DMA10_Y_MODIFY, val)
+#define bfin_read_DMA10_CURR_DESC_PTR()         bfin_read32(DMA10_CURR_DESC_PTR)
+#define bfin_write_DMA10_CURR_DESC_PTR(val)     bfin_write32(DMA10_CURR_DESC_PTR, val)
+#define bfin_read_DMA10_PREV_DESC_PTR()         bfin_read32(DMA10_PREV_DESC_PTR)
+#define bfin_write_DMA10_PREV_DESC_PTR(val)     bfin_write32(DMA10_PREV_DESC_PTR, val)
+#define bfin_read_DMA10_CURR_ADDR()             bfin_read32(DMA10_CURR_ADDR)
+#define bfin_write_DMA10_CURR_ADDR(val)         bfin_write32(DMA10_CURR_ADDR, val)
+#define bfin_read_DMA10_IRQ_STATUS()            bfin_read32(DMA10_IRQ_STATUS)
+#define bfin_write_DMA10_IRQ_STATUS(val)        bfin_write32(DMA10_IRQ_STATUS, val)
+#define bfin_read_DMA10_CURR_X_COUNT()          bfin_read32(DMA10_CURR_X_COUNT)
+#define bfin_write_DMA10_CURR_X_COUNT(val)      bfin_write32(DMA10_CURR_X_COUNT, val)
+#define bfin_read_DMA10_CURR_Y_COUNT()          bfin_read32(DMA10_CURR_Y_COUNT)
+#define bfin_write_DMA10_CURR_Y_COUNT(val)      bfin_write32(DMA10_CURR_Y_COUNT, val)
+#define bfin_read_DMA10_BWL_COUNT()             bfin_read32(DMA10_BWL_COUNT)
+#define bfin_write_DMA10_BWL_COUNT(val)         bfin_write32(DMA10_BWL_COUNT, val)
+#define bfin_read_DMA10_CURR_BWL_COUNT()        bfin_read32(DMA10_CURR_BWL_COUNT)
+#define bfin_write_DMA10_CURR_BWL_COUNT(val)    bfin_write32(DMA10_CURR_BWL_COUNT, val)
+#define bfin_read_DMA10_BWM_COUNT()             bfin_read32(DMA10_BWM_COUNT)
+#define bfin_write_DMA10_BWM_COUNT(val)         bfin_write32(DMA10_BWM_COUNT, val)
+#define bfin_read_DMA10_CURR_BWM_COUNT()        bfin_read32(DMA10_CURR_BWM_COUNT)
+#define bfin_write_DMA10_CURR_BWM_COUNT(val)    bfin_write32(DMA10_CURR_BWM_COUNT, val)
+/* DMA Channel 11 Registers */
+#define bfin_read_DMA11_NEXT_DESC_PTR()         bfin_read32(DMA11_NEXT_DESC_PTR)
+#define bfin_write_DMA11_NEXT_DESC_PTR(val)     bfin_write32(DMA11_NEXT_DESC_PTR, val)
+#define bfin_read_DMA11_START_ADDR()            bfin_read32(DMA11_START_ADDR)
+#define bfin_write_DMA11_START_ADDR(val)        bfin_write32(DMA11_START_ADDR, val)
+#define bfin_read_DMA11_CONFIG()                bfin_read32(DMA11_CONFIG)
+#define bfin_write_DMA11_CONFIG(val)            bfin_write32(DMA11_CONFIG, val)
+#define bfin_read_DMA11_X_COUNT()               bfin_read32(DMA11_X_COUNT)
+#define bfin_write_DMA11_X_COUNT(val)           bfin_write32(DMA11_X_COUNT, val)
+#define bfin_read_DMA11_X_MODIFY()              bfin_read32(DMA11_X_MODIFY)
+#define bfin_write_DMA11_X_MODIFY(val)          bfin_write32(DMA11_X_MODIFY, val)
+#define bfin_read_DMA11_Y_COUNT()               bfin_read32(DMA11_Y_COUNT)
+#define bfin_write_DMA11_Y_COUNT(val)           bfin_write32(DMA11_Y_COUNT, val)
+#define bfin_read_DMA11_Y_MODIFY()              bfin_read32(DMA11_Y_MODIFY)
+#define bfin_write_DMA11_Y_MODIFY(val)          bfin_write32(DMA11_Y_MODIFY, val)
+#define bfin_read_DMA11_CURR_DESC_PTR()         bfin_read32(DMA11_CURR_DESC_PTR)
+#define bfin_write_DMA11_CURR_DESC_PTR(val)     bfin_write32(DMA11_CURR_DESC_PTR, val)
+#define bfin_read_DMA11_PREV_DESC_PTR()         bfin_read32(DMA11_PREV_DESC_PTR)
+#define bfin_write_DMA11_PREV_DESC_PTR(val)     bfin_write32(DMA11_PREV_DESC_PTR, val)
+#define bfin_read_DMA11_CURR_ADDR()             bfin_read32(DMA11_CURR_ADDR)
+#define bfin_write_DMA11_CURR_ADDR(val)         bfin_write32(DMA11_CURR_ADDR, val)
+#define bfin_read_DMA11_IRQ_STATUS()            bfin_read32(DMA11_IRQ_STATUS)
+#define bfin_write_DMA11_IRQ_STATUS(val)        bfin_write32(DMA11_IRQ_STATUS, val)
+#define bfin_read_DMA11_CURR_X_COUNT()          bfin_read32(DMA11_CURR_X_COUNT)
+#define bfin_write_DMA11_CURR_X_COUNT(val)      bfin_write32(DMA11_CURR_X_COUNT, val)
+#define bfin_read_DMA11_CURR_Y_COUNT()          bfin_read32(DMA11_CURR_Y_COUNT)
+#define bfin_write_DMA11_CURR_Y_COUNT(val)      bfin_write32(DMA11_CURR_Y_COUNT, val)
+#define bfin_read_DMA11_BWL_COUNT()             bfin_read32(DMA11_BWL_COUNT)
+#define bfin_write_DMA11_BWL_COUNT(val)         bfin_write32(DMA11_BWL_COUNT, val)
+#define bfin_read_DMA11_CURR_BWL_COUNT()        bfin_read32(DMA11_CURR_BWL_COUNT)
+#define bfin_write_DMA11_CURR_BWL_COUNT(val)    bfin_write32(DMA11_CURR_BWL_COUNT, val)
+#define bfin_read_DMA11_BWM_COUNT()             bfin_read32(DMA11_BWM_COUNT)
+#define bfin_write_DMA11_BWM_COUNT(val)         bfin_write32(DMA11_BWM_COUNT, val)
+#define bfin_read_DMA11_CURR_BWM_COUNT()        bfin_read32(DMA11_CURR_BWM_COUNT)
+#define bfin_write_DMA11_CURR_BWM_COUNT(val)    bfin_write32(DMA11_CURR_BWM_COUNT, val)
+/* DMA Channel 12 Registers */
+#define bfin_read_DMA12_NEXT_DESC_PTR()         bfin_read32(DMA12_NEXT_DESC_PTR)
+#define bfin_write_DMA12_NEXT_DESC_PTR(val)     bfin_write32(DMA12_NEXT_DESC_PTR, val)
+#define bfin_read_DMA12_START_ADDR()            bfin_read32(DMA12_START_ADDR)
+#define bfin_write_DMA12_START_ADDR(val)        bfin_write32(DMA12_START_ADDR, val)
+#define bfin_read_DMA12_CONFIG()                bfin_read32(DMA12_CONFIG)
+#define bfin_write_DMA12_CONFIG(val)            bfin_write32(DMA12_CONFIG, val)
+#define bfin_read_DMA12_X_COUNT()               bfin_read32(DMA12_X_COUNT)
+#define bfin_write_DMA12_X_COUNT(val)           bfin_write32(DMA12_X_COUNT, val)
+#define bfin_read_DMA12_X_MODIFY()              bfin_read32(DMA12_X_MODIFY)
+#define bfin_write_DMA12_X_MODIFY(val)          bfin_write32(DMA12_X_MODIFY, val)
+#define bfin_read_DMA12_Y_COUNT()               bfin_read32(DMA12_Y_COUNT)
+#define bfin_write_DMA12_Y_COUNT(val)           bfin_write32(DMA12_Y_COUNT, val)
+#define bfin_read_DMA12_Y_MODIFY()              bfin_read32(DMA12_Y_MODIFY)
+#define bfin_write_DMA12_Y_MODIFY(val)          bfin_write32(DMA12_Y_MODIFY, val)
+#define bfin_read_DMA12_CURR_DESC_PTR()         bfin_read32(DMA12_CURR_DESC_PTR)
+#define bfin_write_DMA12_CURR_DESC_PTR(val)     bfin_write32(DMA12_CURR_DESC_PTR, val)
+#define bfin_read_DMA12_PREV_DESC_PTR()         bfin_read32(DMA12_PREV_DESC_PTR)
+#define bfin_write_DMA12_PREV_DESC_PTR(val)     bfin_write32(DMA12_PREV_DESC_PTR, val)
+#define bfin_read_DMA12_CURR_ADDR()             bfin_read32(DMA12_CURR_ADDR)
+#define bfin_write_DMA12_CURR_ADDR(val)         bfin_write32(DMA12_CURR_ADDR, val)
+#define bfin_read_DMA12_IRQ_STATUS()            bfin_read32(DMA12_IRQ_STATUS)
+#define bfin_write_DMA12_IRQ_STATUS(val)        bfin_write32(DMA12_IRQ_STATUS, val)
+#define bfin_read_DMA12_CURR_X_COUNT()          bfin_read32(DMA12_CURR_X_COUNT)
+#define bfin_write_DMA12_CURR_X_COUNT(val)      bfin_write32(DMA12_CURR_X_COUNT, val)
+#define bfin_read_DMA12_CURR_Y_COUNT()          bfin_read32(DMA12_CURR_Y_COUNT)
+#define bfin_write_DMA12_CURR_Y_COUNT(val)      bfin_write32(DMA12_CURR_Y_COUNT, val)
+#define bfin_read_DMA12_BWL_COUNT()             bfin_read32(DMA12_BWL_COUNT)
+#define bfin_write_DMA12_BWL_COUNT(val)         bfin_write32(DMA12_BWL_COUNT, val)
+#define bfin_read_DMA12_CURR_BWL_COUNT()        bfin_read32(DMA12_CURR_BWL_COUNT)
+#define bfin_write_DMA12_CURR_BWL_COUNT(val)    bfin_write32(DMA12_CURR_BWL_COUNT, val)
+#define bfin_read_DMA12_BWM_COUNT()             bfin_read32(DMA12_BWM_COUNT)
+#define bfin_write_DMA12_BWM_COUNT(val)         bfin_write32(DMA12_BWM_COUNT, val)
+#define bfin_read_DMA12_CURR_BWM_COUNT()        bfin_read32(DMA12_CURR_BWM_COUNT)
+#define bfin_write_DMA12_CURR_BWM_COUNT(val)    bfin_write32(DMA12_CURR_BWM_COUNT, val)
+/* DMA Channel 13 Registers */
+#define bfin_read_DMA13_NEXT_DESC_PTR()         bfin_read32(DMA13_NEXT_DESC_PTR)
+#define bfin_write_DMA13_NEXT_DESC_PTR(val)     bfin_write32(DMA13_NEXT_DESC_PTR, val)
+#define bfin_read_DMA13_START_ADDR()            bfin_read32(DMA13_START_ADDR)
+#define bfin_write_DMA13_START_ADDR(val)        bfin_write32(DMA13_START_ADDR, val)
+#define bfin_read_DMA13_CONFIG()                bfin_read32(DMA13_CONFIG)
+#define bfin_write_DMA13_CONFIG(val)            bfin_write32(DMA13_CONFIG, val)
+#define bfin_read_DMA13_X_COUNT()               bfin_read32(DMA13_X_COUNT)
+#define bfin_write_DMA13_X_COUNT(val)           bfin_write32(DMA13_X_COUNT, val)
+#define bfin_read_DMA13_X_MODIFY()              bfin_read32(DMA13_X_MODIFY)
+#define bfin_write_DMA13_X_MODIFY(val)          bfin_write32(DMA13_X_MODIFY, val)
+#define bfin_read_DMA13_Y_COUNT()               bfin_read32(DMA13_Y_COUNT)
+#define bfin_write_DMA13_Y_COUNT(val)           bfin_write32(DMA13_Y_COUNT, val)
+#define bfin_read_DMA13_Y_MODIFY()              bfin_read32(DMA13_Y_MODIFY)
+#define bfin_write_DMA13_Y_MODIFY(val)          bfin_write32(DMA13_Y_MODIFY, val)
+#define bfin_read_DMA13_CURR_DESC_PTR()         bfin_read32(DMA13_CURR_DESC_PTR)
+#define bfin_write_DMA13_CURR_DESC_PTR(val)     bfin_write32(DMA13_CURR_DESC_PTR, val)
+#define bfin_read_DMA13_PREV_DESC_PTR()         bfin_read32(DMA13_PREV_DESC_PTR)
+#define bfin_write_DMA13_PREV_DESC_PTR(val)     bfin_write32(DMA13_PREV_DESC_PTR, val)
+#define bfin_read_DMA13_CURR_ADDR()             bfin_read32(DMA13_CURR_ADDR)
+#define bfin_write_DMA13_CURR_ADDR(val)         bfin_write32(DMA13_CURR_ADDR, val)
+#define bfin_read_DMA13_IRQ_STATUS()            bfin_read32(DMA13_IRQ_STATUS)
+#define bfin_write_DMA13_IRQ_STATUS(val)        bfin_write32(DMA13_IRQ_STATUS, val)
+#define bfin_read_DMA13_CURR_X_COUNT()          bfin_read32(DMA13_CURR_X_COUNT)
+#define bfin_write_DMA13_CURR_X_COUNT(val)      bfin_write32(DMA13_CURR_X_COUNT, val)
+#define bfin_read_DMA13_CURR_Y_COUNT()          bfin_read32(DMA13_CURR_Y_COUNT)
+#define bfin_write_DMA13_CURR_Y_COUNT(val)      bfin_write32(DMA13_CURR_Y_COUNT, val)
+#define bfin_read_DMA13_BWL_COUNT()             bfin_read32(DMA13_BWL_COUNT)
+#define bfin_write_DMA13_BWL_COUNT(val)         bfin_write32(DMA13_BWL_COUNT, val)
+#define bfin_read_DMA13_CURR_BWL_COUNT()        bfin_read32(DMA13_CURR_BWL_COUNT)
+#define bfin_write_DMA13_CURR_BWL_COUNT(val)    bfin_write32(DMA13_CURR_BWL_COUNT, val)
+#define bfin_read_DMA13_BWM_COUNT()             bfin_read32(DMA13_BWM_COUNT)
+#define bfin_write_DMA13_BWM_COUNT(val)         bfin_write32(DMA13_BWM_COUNT, val)
+#define bfin_read_DMA13_CURR_BWM_COUNT()        bfin_read32(DMA13_CURR_BWM_COUNT)
+#define bfin_write_DMA13_CURR_BWM_COUNT(val)    bfin_write32(DMA13_CURR_BWM_COUNT, val)
+/* DMA Channel 14 Registers */
+#define bfin_read_DMA14_NEXT_DESC_PTR()         bfin_read32(DMA14_NEXT_DESC_PTR)
+#define bfin_write_DMA14_NEXT_DESC_PTR(val)     bfin_write32(DMA14_NEXT_DESC_PTR, val)
+#define bfin_read_DMA14_START_ADDR()            bfin_read32(DMA14_START_ADDR)
+#define bfin_write_DMA14_START_ADDR(val)        bfin_write32(DMA14_START_ADDR, val)
+#define bfin_read_DMA14_CONFIG()                bfin_read32(DMA14_CONFIG)
+#define bfin_write_DMA14_CONFIG(val)            bfin_write32(DMA14_CONFIG, val)
+#define bfin_read_DMA14_X_COUNT()               bfin_read32(DMA14_X_COUNT)
+#define bfin_write_DMA14_X_COUNT(val)           bfin_write32(DMA14_X_COUNT, val)
+#define bfin_read_DMA14_X_MODIFY()              bfin_read32(DMA14_X_MODIFY)
+#define bfin_write_DMA14_X_MODIFY(val)          bfin_write32(DMA14_X_MODIFY, val)
+#define bfin_read_DMA14_Y_COUNT()               bfin_read32(DMA14_Y_COUNT)
+#define bfin_write_DMA14_Y_COUNT(val)           bfin_write32(DMA14_Y_COUNT, val)
+#define bfin_read_DMA14_Y_MODIFY()              bfin_read32(DMA14_Y_MODIFY)
+#define bfin_write_DMA14_Y_MODIFY(val)          bfin_write32(DMA14_Y_MODIFY, val)
+#define bfin_read_DMA14_CURR_DESC_PTR()         bfin_read32(DMA14_CURR_DESC_PTR)
+#define bfin_write_DMA14_CURR_DESC_PTR(val)     bfin_write32(DMA14_CURR_DESC_PTR, val)
+#define bfin_read_DMA14_PREV_DESC_PTR()         bfin_read32(DMA14_PREV_DESC_PTR)
+#define bfin_write_DMA14_PREV_DESC_PTR(val)     bfin_write32(DMA14_PREV_DESC_PTR, val)
+#define bfin_read_DMA14_CURR_ADDR()             bfin_read32(DMA14_CURR_ADDR)
+#define bfin_write_DMA14_CURR_ADDR(val)         bfin_write32(DMA14_CURR_ADDR, val)
+#define bfin_read_DMA14_IRQ_STATUS()            bfin_read32(DMA14_IRQ_STATUS)
+#define bfin_write_DMA14_IRQ_STATUS(val)        bfin_write32(DMA14_IRQ_STATUS, val)
+#define bfin_read_DMA14_CURR_X_COUNT()          bfin_read32(DMA14_CURR_X_COUNT)
+#define bfin_write_DMA14_CURR_X_COUNT(val)      bfin_write32(DMA14_CURR_X_COUNT, val)
+#define bfin_read_DMA14_CURR_Y_COUNT()          bfin_read32(DMA14_CURR_Y_COUNT)
+#define bfin_write_DMA14_CURR_Y_COUNT(val)      bfin_write32(DMA14_CURR_Y_COUNT, val)
+#define bfin_read_DMA14_BWL_COUNT()             bfin_read32(DMA14_BWL_COUNT)
+#define bfin_write_DMA14_BWL_COUNT(val)         bfin_write32(DMA14_BWL_COUNT, val)
+#define bfin_read_DMA14_CURR_BWL_COUNT()        bfin_read32(DMA14_CURR_BWL_COUNT)
+#define bfin_write_DMA14_CURR_BWL_COUNT(val)    bfin_write32(DMA14_CURR_BWL_COUNT, val)
+#define bfin_read_DMA14_BWM_COUNT()             bfin_read32(DMA14_BWM_COUNT)
+#define bfin_write_DMA14_BWM_COUNT(val)         bfin_write32(DMA14_BWM_COUNT, val)
+#define bfin_read_DMA14_CURR_BWM_COUNT()        bfin_read32(DMA14_CURR_BWM_COUNT)
+#define bfin_write_DMA14_CURR_BWM_COUNT(val)    bfin_write32(DMA14_CURR_BWM_COUNT, val)
+/* DMA Channel 15 Registers */
+#define bfin_read_DMA15_NEXT_DESC_PTR()         bfin_read32(DMA15_NEXT_DESC_PTR)
+#define bfin_write_DMA15_NEXT_DESC_PTR(val)     bfin_write32(DMA15_NEXT_DESC_PTR, val)
+#define bfin_read_DMA15_START_ADDR()            bfin_read32(DMA15_START_ADDR)
+#define bfin_write_DMA15_START_ADDR(val)        bfin_write32(DMA15_START_ADDR, val)
+#define bfin_read_DMA15_CONFIG()                bfin_read32(DMA15_CONFIG)
+#define bfin_write_DMA15_CONFIG(val)            bfin_write32(DMA15_CONFIG, val)
+#define bfin_read_DMA15_X_COUNT()               bfin_read32(DMA15_X_COUNT)
+#define bfin_write_DMA15_X_COUNT(val)           bfin_write32(DMA15_X_COUNT, val)
+#define bfin_read_DMA15_X_MODIFY()              bfin_read32(DMA15_X_MODIFY)
+#define bfin_write_DMA15_X_MODIFY(val)          bfin_write32(DMA15_X_MODIFY, val)
+#define bfin_read_DMA15_Y_COUNT()               bfin_read32(DMA15_Y_COUNT)
+#define bfin_write_DMA15_Y_COUNT(val)           bfin_write32(DMA15_Y_COUNT, val)
+#define bfin_read_DMA15_Y_MODIFY()              bfin_read32(DMA15_Y_MODIFY)
+#define bfin_write_DMA15_Y_MODIFY(val)          bfin_write32(DMA15_Y_MODIFY, val)
+#define bfin_read_DMA15_CURR_DESC_PTR()         bfin_read32(DMA15_CURR_DESC_PTR)
+#define bfin_write_DMA15_CURR_DESC_PTR(val)     bfin_write32(DMA15_CURR_DESC_PTR, val)
+#define bfin_read_DMA15_PREV_DESC_PTR()         bfin_read32(DMA15_PREV_DESC_PTR)
+#define bfin_write_DMA15_PREV_DESC_PTR(val)     bfin_write32(DMA15_PREV_DESC_PTR, val)
+#define bfin_read_DMA15_CURR_ADDR()             bfin_read32(DMA15_CURR_ADDR)
+#define bfin_write_DMA15_CURR_ADDR(val)         bfin_write32(DMA15_CURR_ADDR, val)
+#define bfin_read_DMA15_IRQ_STATUS()            bfin_read32(DMA15_IRQ_STATUS)
+#define bfin_write_DMA15_IRQ_STATUS(val)        bfin_write32(DMA15_IRQ_STATUS, val)
+#define bfin_read_DMA15_CURR_X_COUNT()          bfin_read32(DMA15_CURR_X_COUNT)
+#define bfin_write_DMA15_CURR_X_COUNT(val)      bfin_write32(DMA15_CURR_X_COUNT, val)
+#define bfin_read_DMA15_CURR_Y_COUNT()          bfin_read32(DMA15_CURR_Y_COUNT)
+#define bfin_write_DMA15_CURR_Y_COUNT(val)      bfin_write32(DMA15_CURR_Y_COUNT, val)
+#define bfin_read_DMA15_BWL_COUNT()             bfin_read32(DMA15_BWL_COUNT)
+#define bfin_write_DMA15_BWL_COUNT(val)         bfin_write32(DMA15_BWL_COUNT, val)
+#define bfin_read_DMA15_CURR_BWL_COUNT()        bfin_read32(DMA15_CURR_BWL_COUNT)
+#define bfin_write_DMA15_CURR_BWL_COUNT(val)    bfin_write32(DMA15_CURR_BWL_COUNT, val)
+#define bfin_read_DMA15_BWM_COUNT()             bfin_read32(DMA15_BWM_COUNT)
+#define bfin_write_DMA15_BWM_COUNT(val)         bfin_write32(DMA15_BWM_COUNT, val)
+#define bfin_read_DMA15_CURR_BWM_COUNT()        bfin_read32(DMA15_CURR_BWM_COUNT)
+#define bfin_write_DMA15_CURR_BWM_COUNT(val)    bfin_write32(DMA15_CURR_BWM_COUNT, val)
+/* DMA Channel 16 Registers */
+#define bfin_read_DMA16_NEXT_DESC_PTR()         bfin_read32(DMA16_NEXT_DESC_PTR)
+#define bfin_write_DMA16_NEXT_DESC_PTR(val)     bfin_write32(DMA16_NEXT_DESC_PTR, val)
+#define bfin_read_DMA16_START_ADDR()            bfin_read32(DMA16_START_ADDR)
+#define bfin_write_DMA16_START_ADDR(val)        bfin_write32(DMA16_START_ADDR, val)
+#define bfin_read_DMA16_CONFIG()                bfin_read32(DMA16_CONFIG)
+#define bfin_write_DMA16_CONFIG(val)            bfin_write32(DMA16_CONFIG, val)
+#define bfin_read_DMA16_X_COUNT()               bfin_read32(DMA16_X_COUNT)
+#define bfin_write_DMA16_X_COUNT(val)           bfin_write32(DMA16_X_COUNT, val)
+#define bfin_read_DMA16_X_MODIFY()              bfin_read32(DMA16_X_MODIFY)
+#define bfin_write_DMA16_X_MODIFY(val)          bfin_write32(DMA16_X_MODIFY, val)
+#define bfin_read_DMA16_Y_COUNT()               bfin_read32(DMA16_Y_COUNT)
+#define bfin_write_DMA16_Y_COUNT(val)           bfin_write32(DMA16_Y_COUNT, val)
+#define bfin_read_DMA16_Y_MODIFY()              bfin_read32(DMA16_Y_MODIFY)
+#define bfin_write_DMA16_Y_MODIFY(val)          bfin_write32(DMA16_Y_MODIFY, val)
+#define bfin_read_DMA16_CURR_DESC_PTR()         bfin_read32(DMA16_CURR_DESC_PTR)
+#define bfin_write_DMA16_CURR_DESC_PTR(val)     bfin_write32(DMA16_CURR_DESC_PTR, val)
+#define bfin_read_DMA16_PREV_DESC_PTR()         bfin_read32(DMA16_PREV_DESC_PTR)
+#define bfin_write_DMA16_PREV_DESC_PTR(val)     bfin_write32(DMA16_PREV_DESC_PTR, val)
+#define bfin_read_DMA16_CURR_ADDR()             bfin_read32(DMA16_CURR_ADDR)
+#define bfin_write_DMA16_CURR_ADDR(val)         bfin_write32(DMA16_CURR_ADDR, val)
+#define bfin_read_DMA16_IRQ_STATUS()            bfin_read32(DMA16_IRQ_STATUS)
+#define bfin_write_DMA16_IRQ_STATUS(val)        bfin_write32(DMA16_IRQ_STATUS, val)
+#define bfin_read_DMA16_CURR_X_COUNT()          bfin_read32(DMA16_CURR_X_COUNT)
+#define bfin_write_DMA16_CURR_X_COUNT(val)      bfin_write32(DMA16_CURR_X_COUNT, val)
+#define bfin_read_DMA16_CURR_Y_COUNT()          bfin_read32(DMA16_CURR_Y_COUNT)
+#define bfin_write_DMA16_CURR_Y_COUNT(val)      bfin_write32(DMA16_CURR_Y_COUNT, val)
+#define bfin_read_DMA16_BWL_COUNT()             bfin_read32(DMA16_BWL_COUNT)
+#define bfin_write_DMA16_BWL_COUNT(val)         bfin_write32(DMA16_BWL_COUNT, val)
+#define bfin_read_DMA16_CURR_BWL_COUNT()        bfin_read32(DMA16_CURR_BWL_COUNT)
+#define bfin_write_DMA16_CURR_BWL_COUNT(val)    bfin_write32(DMA16_CURR_BWL_COUNT, val)
+#define bfin_read_DMA16_BWM_COUNT()             bfin_read32(DMA16_BWM_COUNT)
+#define bfin_write_DMA16_BWM_COUNT(val)         bfin_write32(DMA16_BWM_COUNT, val)
+#define bfin_read_DMA16_CURR_BWM_COUNT()        bfin_read32(DMA16_CURR_BWM_COUNT)
+#define bfin_write_DMA16_CURR_BWM_COUNT(val)    bfin_write32(DMA16_CURR_BWM_COUNT, val)
+/* DMA Channel 17 Registers */
+#define bfin_read_DMA17_NEXT_DESC_PTR()         bfin_read32(DMA17_NEXT_DESC_PTR)
+#define bfin_write_DMA17_NEXT_DESC_PTR(val)     bfin_write32(DMA17_NEXT_DESC_PTR, val)
+#define bfin_read_DMA17_START_ADDR()            bfin_read32(DMA17_START_ADDR)
+#define bfin_write_DMA17_START_ADDR(val)        bfin_write32(DMA17_START_ADDR, val)
+#define bfin_read_DMA17_CONFIG()                bfin_read32(DMA17_CONFIG)
+#define bfin_write_DMA17_CONFIG(val)            bfin_write32(DMA17_CONFIG, val)
+#define bfin_read_DMA17_X_COUNT()               bfin_read32(DMA17_X_COUNT)
+#define bfin_write_DMA17_X_COUNT(val)           bfin_write32(DMA17_X_COUNT, val)
+#define bfin_read_DMA17_X_MODIFY()              bfin_read32(DMA17_X_MODIFY)
+#define bfin_write_DMA17_X_MODIFY(val)          bfin_write32(DMA17_X_MODIFY, val)
+#define bfin_read_DMA17_Y_COUNT()               bfin_read32(DMA17_Y_COUNT)
+#define bfin_write_DMA17_Y_COUNT(val)           bfin_write32(DMA17_Y_COUNT, val)
+#define bfin_read_DMA17_Y_MODIFY()              bfin_read32(DMA17_Y_MODIFY)
+#define bfin_write_DMA17_Y_MODIFY(val)          bfin_write32(DMA17_Y_MODIFY, val)
+#define bfin_read_DMA17_CURR_DESC_PTR()         bfin_read32(DMA17_CURR_DESC_PTR)
+#define bfin_write_DMA17_CURR_DESC_PTR(val)     bfin_write32(DMA17_CURR_DESC_PTR, val)
+#define bfin_read_DMA17_PREV_DESC_PTR()         bfin_read32(DMA17_PREV_DESC_PTR)
+#define bfin_write_DMA17_PREV_DESC_PTR(val)     bfin_write32(DMA17_PREV_DESC_PTR, val)
+#define bfin_read_DMA17_CURR_ADDR()             bfin_read32(DMA17_CURR_ADDR)
+#define bfin_write_DMA17_CURR_ADDR(val)         bfin_write32(DMA17_CURR_ADDR, val)
+#define bfin_read_DMA17_IRQ_STATUS()            bfin_read32(DMA17_IRQ_STATUS)
+#define bfin_write_DMA17_IRQ_STATUS(val)        bfin_write32(DMA17_IRQ_STATUS, val)
+#define bfin_read_DMA17_CURR_X_COUNT()          bfin_read32(DMA17_CURR_X_COUNT)
+#define bfin_write_DMA17_CURR_X_COUNT(val)      bfin_write32(DMA17_CURR_X_COUNT, val)
+#define bfin_read_DMA17_CURR_Y_COUNT()          bfin_read32(DMA17_CURR_Y_COUNT)
+#define bfin_write_DMA17_CURR_Y_COUNT(val)      bfin_write32(DMA17_CURR_Y_COUNT, val)
+#define bfin_read_DMA17_BWL_COUNT()             bfin_read32(DMA17_BWL_COUNT)
+#define bfin_write_DMA17_BWL_COUNT(val)         bfin_write32(DMA17_BWL_COUNT, val)
+#define bfin_read_DMA17_CURR_BWL_COUNT()        bfin_read32(DMA17_CURR_BWL_COUNT)
+#define bfin_write_DMA17_CURR_BWL_COUNT(val)    bfin_write32(DMA17_CURR_BWL_COUNT, val)
+#define bfin_read_DMA17_BWM_COUNT()             bfin_read32(DMA17_BWM_COUNT)
+#define bfin_write_DMA17_BWM_COUNT(val)         bfin_write32(DMA17_BWM_COUNT, val)
+#define bfin_read_DMA17_CURR_BWM_COUNT()        bfin_read32(DMA17_CURR_BWM_COUNT)
+#define bfin_write_DMA17_CURR_BWM_COUNT(val)    bfin_write32(DMA17_CURR_BWM_COUNT, val)
+/* DMA Channel 18 Registers */
+#define bfin_read_DMA18_NEXT_DESC_PTR()         bfin_read32(DMA18_NEXT_DESC_PTR)
+#define bfin_write_DMA18_NEXT_DESC_PTR(val)     bfin_write32(DMA18_NEXT_DESC_PTR, val)
+#define bfin_read_DMA18_START_ADDR()            bfin_read32(DMA18_START_ADDR)
+#define bfin_write_DMA18_START_ADDR(val)        bfin_write32(DMA18_START_ADDR, val)
+#define bfin_read_DMA18_CONFIG()                bfin_read32(DMA18_CONFIG)
+#define bfin_write_DMA18_CONFIG(val)            bfin_write32(DMA18_CONFIG, val)
+#define bfin_read_DMA18_X_COUNT()               bfin_read32(DMA18_X_COUNT)
+#define bfin_write_DMA18_X_COUNT(val)           bfin_write32(DMA18_X_COUNT, val)
+#define bfin_read_DMA18_X_MODIFY()              bfin_read32(DMA18_X_MODIFY)
+#define bfin_write_DMA18_X_MODIFY(val)          bfin_write32(DMA18_X_MODIFY, val)
+#define bfin_read_DMA18_Y_COUNT()               bfin_read32(DMA18_Y_COUNT)
+#define bfin_write_DMA18_Y_COUNT(val)           bfin_write32(DMA18_Y_COUNT, val)
+#define bfin_read_DMA18_Y_MODIFY()              bfin_read32(DMA18_Y_MODIFY)
+#define bfin_write_DMA18_Y_MODIFY(val)          bfin_write32(DMA18_Y_MODIFY, val)
+#define bfin_read_DMA18_CURR_DESC_PTR()         bfin_read32(DMA18_CURR_DESC_PTR)
+#define bfin_write_DMA18_CURR_DESC_PTR(val)     bfin_write32(DMA18_CURR_DESC_PTR, val)
+#define bfin_read_DMA18_PREV_DESC_PTR()         bfin_read32(DMA18_PREV_DESC_PTR)
+#define bfin_write_DMA18_PREV_DESC_PTR(val)     bfin_write32(DMA18_PREV_DESC_PTR, val)
+#define bfin_read_DMA18_CURR_ADDR()             bfin_read32(DMA18_CURR_ADDR)
+#define bfin_write_DMA18_CURR_ADDR(val)         bfin_write32(DMA18_CURR_ADDR, val)
+#define bfin_read_DMA18_IRQ_STATUS()            bfin_read32(DMA18_IRQ_STATUS)
+#define bfin_write_DMA18_IRQ_STATUS(val)        bfin_write32(DMA18_IRQ_STATUS, val)
+#define bfin_read_DMA18_CURR_X_COUNT()          bfin_read32(DMA18_CURR_X_COUNT)
+#define bfin_write_DMA18_CURR_X_COUNT(val)      bfin_write32(DMA18_CURR_X_COUNT, val)
+#define bfin_read_DMA18_CURR_Y_COUNT()          bfin_read32(DMA18_CURR_Y_COUNT)
+#define bfin_write_DMA18_CURR_Y_COUNT(val)      bfin_write32(DMA18_CURR_Y_COUNT, val)
+#define bfin_read_DMA18_BWL_COUNT()             bfin_read32(DMA18_BWL_COUNT)
+#define bfin_write_DMA18_BWL_COUNT(val)         bfin_write32(DMA18_BWL_COUNT, val)
+#define bfin_read_DMA18_CURR_BWL_COUNT()        bfin_read32(DMA18_CURR_BWL_COUNT)
+#define bfin_write_DMA18_CURR_BWL_COUNT(val)    bfin_write32(DMA18_CURR_BWL_COUNT, val)
+#define bfin_read_DMA18_BWM_COUNT()             bfin_read32(DMA18_BWM_COUNT)
+#define bfin_write_DMA18_BWM_COUNT(val)         bfin_write32(DMA18_BWM_COUNT, val)
+#define bfin_read_DMA18_CURR_BWM_COUNT()        bfin_read32(DMA18_CURR_BWM_COUNT)
+#define bfin_write_DMA18_CURR_BWM_COUNT(val)    bfin_write32(DMA18_CURR_BWM_COUNT, val)
+/* DMA Channel 19 Registers */
+#define bfin_read_DMA19_NEXT_DESC_PTR()         bfin_read32(DMA19_NEXT_DESC_PTR)
+#define bfin_write_DMA19_NEXT_DESC_PTR(val)     bfin_write32(DMA19_NEXT_DESC_PTR, val)
+#define bfin_read_DMA19_START_ADDR()            bfin_read32(DMA19_START_ADDR)
+#define bfin_write_DMA19_START_ADDR(val)        bfin_write32(DMA19_START_ADDR, val)
+#define bfin_read_DMA19_CONFIG()                bfin_read32(DMA19_CONFIG)
+#define bfin_write_DMA19_CONFIG(val)            bfin_write32(DMA19_CONFIG, val)
+#define bfin_read_DMA19_X_COUNT()               bfin_read32(DMA19_X_COUNT)
+#define bfin_write_DMA19_X_COUNT(val)           bfin_write32(DMA19_X_COUNT, val)
+#define bfin_read_DMA19_X_MODIFY()              bfin_read32(DMA19_X_MODIFY)
+#define bfin_write_DMA19_X_MODIFY(val)          bfin_write32(DMA19_X_MODIFY, val)
+#define bfin_read_DMA19_Y_COUNT()               bfin_read32(DMA19_Y_COUNT)
+#define bfin_write_DMA19_Y_COUNT(val)           bfin_write32(DMA19_Y_COUNT, val)
+#define bfin_read_DMA19_Y_MODIFY()              bfin_read32(DMA19_Y_MODIFY)
+#define bfin_write_DMA19_Y_MODIFY(val)          bfin_write32(DMA19_Y_MODIFY, val)
+#define bfin_read_DMA19_CURR_DESC_PTR()         bfin_read32(DMA19_CURR_DESC_PTR)
+#define bfin_write_DMA19_CURR_DESC_PTR(val)     bfin_write32(DMA19_CURR_DESC_PTR, val)
+#define bfin_read_DMA19_PREV_DESC_PTR()         bfin_read32(DMA19_PREV_DESC_PTR)
+#define bfin_write_DMA19_PREV_DESC_PTR(val)     bfin_write32(DMA19_PREV_DESC_PTR, val)
+#define bfin_read_DMA19_CURR_ADDR()             bfin_read32(DMA19_CURR_ADDR)
+#define bfin_write_DMA19_CURR_ADDR(val)         bfin_write32(DMA19_CURR_ADDR, val)
+#define bfin_read_DMA19_IRQ_STATUS()            bfin_read32(DMA19_IRQ_STATUS)
+#define bfin_write_DMA19_IRQ_STATUS(val)        bfin_write32(DMA19_IRQ_STATUS, val)
+#define bfin_read_DMA19_CURR_X_COUNT()          bfin_read32(DMA19_CURR_X_COUNT)
+#define bfin_write_DMA19_CURR_X_COUNT(val)      bfin_write32(DMA19_CURR_X_COUNT, val)
+#define bfin_read_DMA19_CURR_Y_COUNT()          bfin_read32(DMA19_CURR_Y_COUNT)
+#define bfin_write_DMA19_CURR_Y_COUNT(val)      bfin_write32(DMA19_CURR_Y_COUNT, val)
+#define bfin_read_DMA19_BWL_COUNT()             bfin_read32(DMA19_BWL_COUNT)
+#define bfin_write_DMA19_BWL_COUNT(val)         bfin_write32(DMA19_BWL_COUNT, val)
+#define bfin_read_DMA19_CURR_BWL_COUNT()        bfin_read32(DMA19_CURR_BWL_COUNT)
+#define bfin_write_DMA19_CURR_BWL_COUNT(val)    bfin_write32(DMA19_CURR_BWL_COUNT, val)
+#define bfin_read_DMA19_BWM_COUNT()             bfin_read32(DMA19_BWM_COUNT)
+#define bfin_write_DMA19_BWM_COUNT(val)         bfin_write32(DMA19_BWM_COUNT, val)
+#define bfin_read_DMA19_CURR_BWM_COUNT()        bfin_read32(DMA19_CURR_BWM_COUNT)
+#define bfin_write_DMA19_CURR_BWM_COUNT(val)    bfin_write32(DMA19_CURR_BWM_COUNT, val)
+/* DMA Channel 20 Registers */
+#define bfin_read_DMA20_NEXT_DESC_PTR()         bfin_read32(DMA20_NEXT_DESC_PTR)
+#define bfin_write_DMA20_NEXT_DESC_PTR(val)     bfin_write32(DMA20_NEXT_DESC_PTR, val)
+#define bfin_read_DMA20_START_ADDR()            bfin_read32(DMA20_START_ADDR)
+#define bfin_write_DMA20_START_ADDR(val)        bfin_write32(DMA20_START_ADDR, val)
+#define bfin_read_DMA20_CONFIG()                bfin_read32(DMA20_CONFIG)
+#define bfin_write_DMA20_CONFIG(val)            bfin_write32(DMA20_CONFIG, val)
+#define bfin_read_DMA20_X_COUNT()               bfin_read32(DMA20_X_COUNT)
+#define bfin_write_DMA20_X_COUNT(val)           bfin_write32(DMA20_X_COUNT, val)
+#define bfin_read_DMA20_X_MODIFY()              bfin_read32(DMA20_X_MODIFY)
+#define bfin_write_DMA20_X_MODIFY(val)          bfin_write32(DMA20_X_MODIFY, val)
+#define bfin_read_DMA20_Y_COUNT()               bfin_read32(DMA20_Y_COUNT)
+#define bfin_write_DMA20_Y_COUNT(val)           bfin_write32(DMA20_Y_COUNT, val)
+#define bfin_read_DMA20_Y_MODIFY()              bfin_read32(DMA20_Y_MODIFY)
+#define bfin_write_DMA20_Y_MODIFY(val)          bfin_write32(DMA20_Y_MODIFY, val)
+#define bfin_read_DMA20_CURR_DESC_PTR()         bfin_read32(DMA20_CURR_DESC_PTR)
+#define bfin_write_DMA20_CURR_DESC_PTR(val)     bfin_write32(DMA20_CURR_DESC_PTR, val)
+#define bfin_read_DMA20_PREV_DESC_PTR()         bfin_read32(DMA20_PREV_DESC_PTR)
+#define bfin_write_DMA20_PREV_DESC_PTR(val)     bfin_write32(DMA20_PREV_DESC_PTR, val)
+#define bfin_read_DMA20_CURR_ADDR()             bfin_read32(DMA20_CURR_ADDR)
+#define bfin_write_DMA20_CURR_ADDR(val)         bfin_write32(DMA20_CURR_ADDR, val)
+#define bfin_read_DMA20_IRQ_STATUS()            bfin_read32(DMA20_IRQ_STATUS)
+#define bfin_write_DMA20_IRQ_STATUS(val)        bfin_write32(DMA20_IRQ_STATUS, val)
+#define bfin_read_DMA20_CURR_X_COUNT()          bfin_read32(DMA20_CURR_X_COUNT)
+#define bfin_write_DMA20_CURR_X_COUNT(val)      bfin_write32(DMA20_CURR_X_COUNT, val)
+#define bfin_read_DMA20_CURR_Y_COUNT()          bfin_read32(DMA20_CURR_Y_COUNT)
+#define bfin_write_DMA20_CURR_Y_COUNT(val)      bfin_write32(DMA20_CURR_Y_COUNT, val)
+#define bfin_read_DMA20_BWL_COUNT()             bfin_read32(DMA20_BWL_COUNT)
+#define bfin_write_DMA20_BWL_COUNT(val)         bfin_write32(DMA20_BWL_COUNT, val)
+#define bfin_read_DMA20_CURR_BWL_COUNT()        bfin_read32(DMA20_CURR_BWL_COUNT)
+#define bfin_write_DMA20_CURR_BWL_COUNT(val)    bfin_write32(DMA20_CURR_BWL_COUNT, val)
+#define bfin_read_DMA20_BWM_COUNT()             bfin_read32(DMA20_BWM_COUNT)
+#define bfin_write_DMA20_BWM_COUNT(val)         bfin_write32(DMA20_BWM_COUNT, val)
+#define bfin_read_DMA20_CURR_BWM_COUNT()        bfin_read32(DMA20_CURR_BWM_COUNT)
+#define bfin_write_DMA20_CURR_BWM_COUNT(val)    bfin_write32(DMA20_CURR_BWM_COUNT, val)
+/* MDMA Stream 0 Registers (DMA Channel 21 and 22) */
+#define bfin_read_MDMA0_DEST_CRC0_NEXT_DESC_PTR()       bfin_read32(MDMA0_DEST_CRC0_NEXT_DESC_PTR)
+#define bfin_write_MDMA0_DEST_CRC0_NEXT_DESC_PTR(val)   bfin_write32(MDMA0_DEST_CRC0_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA0_DEST_CRC0_START_ADDR()          bfin_read32(MDMA0_DEST_CRC0_START_ADDR)
+#define bfin_write_MDMA0_DEST_CRC0_START_ADDR(val)      bfin_write32(MDMA0_DEST_CRC0_START_ADDR, val)
+#define bfin_read_MDMA0_DEST_CRC0_CONFIG()              bfin_read32(MDMA0_DEST_CRC0_CONFIG)
+#define bfin_write_MDMA0_DEST_CRC0_CONFIG(val)          bfin_write32(MDMA0_DEST_CRC0_CONFIG, val)
+#define bfin_read_MDMA0_DEST_CRC0_X_COUNT()             bfin_read32(MDMA0_DEST_CRC0_X_COUNT)
+#define bfin_write_MDMA0_DEST_CRC0_X_COUNT(val)         bfin_write32(MDMA0_DEST_CRC0_X_COUNT, val)
+#define bfin_read_MDMA0_DEST_CRC0_X_MODIFY()            bfin_read32(MDMA0_DEST_CRC0_X_MODIFY)
+#define bfin_write_MDMA0_DEST_CRC0_X_MODIFY(val)        bfin_write32(MDMA0_DEST_CRC0_X_MODIFY, val)
+#define bfin_read_MDMA0_DEST_CRC0_Y_COUNT()             bfin_read32(MDMA0_DEST_CRC0_Y_COUNT)
+#define bfin_write_MDMA0_DEST_CRC0_Y_COUNT(val)         bfin_write32(MDMA0_DEST_CRC0_Y_COUNT, val)
+#define bfin_read_MDMA0_DEST_CRC0_Y_MODIFY()            bfin_read32(MDMA0_DEST_CRC0_Y_MODIFY)
+#define bfin_write_MDMA0_DEST_CRC0_Y_MODIFY(val)        bfin_write32(MDMA0_DEST_CRC0_Y_MODIFY, val)
+#define bfin_read_MDMA0_DEST_CRC0_CURR_DESC_PTR()       bfin_read32(MDMA0_DEST_CRC0_CURR_DESC_PTR)
+#define bfin_write_MDMA0_DEST_CRC0_CURR_DESC_PTR(val)   bfin_write32(MDMA0_DEST_CRC0_CURR_DESC_PTR, val)
+#define bfin_read_MDMA0_DEST_CRC0_PREV_DESC_PTR()       bfin_read32(MDMA0_DEST_CRC0_PREV_DESC_PTR)
+#define bfin_write_MDMA0_DEST_CRC0_PREV_DESC_PTR(val)   bfin_write32(MDMA0_DEST_CRC0_PREV_DESC_PTR, val)
+#define bfin_read_MDMA0_DEST_CRC0_CURR_ADDR()           bfin_read32(MDMA0_DEST_CRC0_CURR_ADDR)
+#define bfin_write_MDMA0_DEST_CRC0_CURR_ADDR(val)       bfin_write32(MDMA0_DEST_CRC0_CURR_ADDR, val)
+#define bfin_read_MDMA0_DEST_CRC0_IRQ_STATUS()          bfin_read32(MDMA0_DEST_CRC0_IRQ_STATUS)
+#define bfin_write_MDMA0_DEST_CRC0_IRQ_STATUS(val)      bfin_write32(MDMA0_DEST_CRC0_IRQ_STATUS, val)
+#define bfin_read_MDMA0_DEST_CRC0_CURR_X_COUNT()        bfin_read32(MDMA0_DEST_CRC0_CURR_X_COUNT)
+#define bfin_write_MDMA0_DEST_CRC0_CURR_X_COUNT(val)    bfin_write32(MDMA0_DEST_CRC0_CURR_X_COUNT, val)
+#define bfin_read_MDMA0_DEST_CRC0_CURR_Y_COUNT()        bfin_read32(MDMA0_DEST_CRC0_CURR_Y_COUNT)
+#define bfin_write_MDMA0_DEST_CRC0_CURR_Y_COUNT(val)    bfin_write32(MDMA0_DEST_CRC0_CURR_Y_COUNT, val)
+#define bfin_read_MDMA0_SRC_CRC0_NEXT_DESC_PTR()        bfin_read32(MDMA0_SRC_CRC0_NEXT_DESC_PTR)
+#define bfin_write_MDMA0_SRC_CRC0_NEXT_DESC_PTR(val)    bfin_write32(MDMA0_SRC_CRC0_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA0_SRC_CRC0_START_ADDR()           bfin_read32(MDMA0_SRC_CRC0_START_ADDR)
+#define bfin_write_MDMA0_SRC_CRC0_START_ADDR(val)       bfin_write32(MDMA0_SRC_CRC0_START_ADDR, val)
+#define bfin_read_MDMA0_SRC_CRC0_CONFIG()               bfin_read32(MDMA0_SRC_CRC0_CONFIG)
+#define bfin_write_MDMA0_SRC_CRC0_CONFIG(val)           bfin_write32(MDMA0_SRC_CRC0_CONFIG, val)
+#define bfin_read_MDMA0_SRC_CRC0_X_COUNT()              bfin_read32(MDMA0_SRC_CRC0_X_COUNT)
+#define bfin_write_MDMA0_SRC_CRC0_X_COUNT(val)          bfin_write32(MDMA0_SRC_CRC0_X_COUNT, val)
+#define bfin_read_MDMA0_SRC_CRC0_X_MODIFY()             bfin_read32(MDMA0_SRC_CRC0_X_MODIFY)
+#define bfin_write_MDMA0_SRC_CRC0_X_MODIFY(val)         bfin_write32(MDMA0_SRC_CRC0_X_MODIFY, val)
+#define bfin_read_MDMA0_SRC_CRC0_Y_COUNT()              bfin_read32(MDMA0_SRC_CRC0_Y_COUNT)
+#define bfin_write_MDMA0_SRC_CRC0_Y_COUNT(val)          bfin_write32(MDMA0_SRC_CRC0_Y_COUNT, val)
+#define bfin_read_MDMA0_SRC_CRC0_Y_MODIFY()             bfin_read32(MDMA0_SRC_CRC0_Y_MODIFY)
+#define bfin_write_MDMA0_SRC_CRC0_Y_MODIFY(val)         bfin_write32(MDMA0_SRC_CRC0_Y_MODIFY, val)
+#define bfin_read_MDMA0_SRC_CRC0_CURR_DESC_PTR()        bfin_read32(MDMA0_SRC_CRC0_CURR_DESC_PTR)
+#define bfin_write_MDMA0_SRC_CRC0_CURR_DESC_PTR(val)    bfin_write32(MDMA0_SRC_CRC0_CURR_DESC_PTR, val)
+#define bfin_read_MDMA0_SRC_CRC0_PREV_DESC_PTR()        bfin_read32(MDMA0_SRC_CRC0_PREV_DESC_PTR)
+#define bfin_write_MDMA0_SRC_CRC0_PREV_DESC_PTR(val)    bfin_write32(MDMA0_SRC_CRC0_PREV_DESC_PTR, val)
+#define bfin_read_MDMA0_SRC_CRC0_CURR_ADDR()            bfin_read32(MDMA0_SRC_CRC0_CURR_ADDR)
+#define bfin_write_MDMA0_SRC_CRC0_CURR_ADDR(val)        bfin_write32(MDMA0_SRC_CRC0_CURR_ADDR, val)
+#define bfin_read_MDMA0_SRC_CRC0_IRQ_STATUS()           bfin_read32(MDMA0_SRC_CRC0_IRQ_STATUS)
+#define bfin_write_MDMA0_SRC_CRC0_IRQ_STATUS(val)       bfin_write32(MDMA0_SRC_CRC0_IRQ_STATUS, val)
+#define bfin_read_MDMA0_SRC_CRC0_CURR_X_COUNT()         bfin_read32(MDMA0_SRC_CRC0_CURR_X_COUNT)
+#define bfin_write_MDMA0_SRC_CRC0_CURR_X_COUNT(val)     bfin_write32(MDMA0_SRC_CRC0_CURR_X_COUNT, val)
+#define bfin_read_MDMA0_SRC_CRC0_CURR_Y_COUNT()         bfin_read32(MDMA0_SRC_CRC0_CURR_Y_COUNT)
+#define bfin_write_MDMA0_SRC_CRC0_CURR_Y_COUNT(val)     bfin_write32(MDMA0_SRC_CRC0_CURR_Y_COUNT, val)
+/* MDMA Stream 1 Registers (DMA Channel 23 and 24) */
+#define bfin_read_MDMA1_DEST_CRC1_NEXT_DESC_PTR()       bfin_read32(MDMA1_DEST_CRC1_NEXT_DESC_PTR)
+#define bfin_write_MDMA1_DEST_CRC1_NEXT_DESC_PTR(val)   bfin_write32(MDMA1_DEST_CRC1_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA1_DEST_CRC1_START_ADDR()          bfin_read32(MDMA1_DEST_CRC1_START_ADDR)
+#define bfin_write_MDMA1_DEST_CRC1_START_ADDR(val)      bfin_write32(MDMA1_DEST_CRC1_START_ADDR, val)
+#define bfin_read_MDMA1_DEST_CRC1_CONFIG()              bfin_read32(MDMA1_DEST_CRC1_CONFIG)
+#define bfin_write_MDMA1_DEST_CRC1_CONFIG(val)          bfin_write32(MDMA1_DEST_CRC1_CONFIG, val)
+#define bfin_read_MDMA1_DEST_CRC1_X_COUNT()             bfin_read32(MDMA1_DEST_CRC1_X_COUNT)
+#define bfin_write_MDMA1_DEST_CRC1_X_COUNT(val)         bfin_write32(MDMA1_DEST_CRC1_X_COUNT, val)
+#define bfin_read_MDMA1_DEST_CRC1_X_MODIFY()            bfin_read32(MDMA1_DEST_CRC1_X_MODIFY)
+#define bfin_write_MDMA1_DEST_CRC1_X_MODIFY(val)        bfin_write32(MDMA1_DEST_CRC1_X_MODIFY, val)
+#define bfin_read_MDMA1_DEST_CRC1_Y_COUNT()             bfin_read32(MDMA1_DEST_CRC1_Y_COUNT)
+#define bfin_write_MDMA1_DEST_CRC1_Y_COUNT(val)         bfin_write32(MDMA1_DEST_CRC1_Y_COUNT, val)
+#define bfin_read_MDMA1_DEST_CRC1_Y_MODIFY()            bfin_read32(MDMA1_DEST_CRC1_Y_MODIFY)
+#define bfin_write_MDMA1_DEST_CRC1_Y_MODIFY(val)        bfin_write32(MDMA1_DEST_CRC1_Y_MODIFY, val)
+#define bfin_read_MDMA1_DEST_CRC1_CURR_DESC_PTR()       bfin_read32(MDMA1_DEST_CRC1_CURR_DESC_PTR)
+#define bfin_write_MDMA1_DEST_CRC1_CURR_DESC_PTR(val)   bfin_write32(MDMA1_DEST_CRC1_CURR_DESC_PTR, val)
+#define bfin_read_MDMA1_DEST_CRC1_PREV_DESC_PTR()       bfin_read32(MDMA1_DEST_CRC1_PREV_DESC_PTR)
+#define bfin_write_MDMA1_DEST_CRC1_PREV_DESC_PTR(val)   bfin_write32(MDMA1_DEST_CRC1_PREV_DESC_PTR, val)
+#define bfin_read_MDMA1_DEST_CRC1_CURR_ADDR()           bfin_read32(MDMA1_DEST_CRC1_CURR_ADDR)
+#define bfin_write_MDMA1_DEST_CRC1_CURR_ADDR(val)       bfin_write32(MDMA1_DEST_CRC1_CURR_ADDR, val)
+#define bfin_read_MDMA1_DEST_CRC1_IRQ_STATUS()          bfin_read32(MDMA1_DEST_CRC1_IRQ_STATUS)
+#define bfin_write_MDMA1_DEST_CRC1_IRQ_STATUS(val)      bfin_write32(MDMA1_DEST_CRC1_IRQ_STATUS, val)
+#define bfin_read_MDMA1_DEST_CRC1_CURR_X_COUNT()        bfin_read32(MDMA1_DEST_CRC1_CURR_X_COUNT)
+#define bfin_write_MDMA1_DEST_CRC1_CURR_X_COUNT(val)    bfin_write32(MDMA1_DEST_CRC1_CURR_X_COUNT, val)
+#define bfin_read_MDMA1_DEST_CRC1_CURR_Y_COUNT()        bfin_read32(MDMA1_DEST_CRC1_CURR_Y_COUNT)
+#define bfin_write_MDMA1_DEST_CRC1_CURR_Y_COUNT(val)    bfin_write32(MDMA1_DEST_CRC1_CURR_Y_COUNT, val)
+#define bfin_read_MDMA1_SRC_CRC1_NEXT_DESC_PTR()        bfin_read32(MDMA1_SRC_CRC1_NEXT_DESC_PTR)
+#define bfin_write_MDMA1_SRC_CRC1_NEXT_DESC_PTR(val)    bfin_write32(MDMA1_SRC_CRC1_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA1_SRC_CRC1_START_ADDR()           bfin_read32(MDMA1_SRC_CRC1_START_ADDR)
+#define bfin_write_MDMA1_SRC_CRC1_START_ADDR(val)       bfin_write32(MDMA1_SRC_CRC1_START_ADDR, val)
+#define bfin_read_MDMA1_SRC_CRC1_CONFIG()               bfin_read32(MDMA1_SRC_CRC1_CONFIG)
+#define bfin_write_MDMA1_SRC_CRC1_CONFIG(val)           bfin_write32(MDMA1_SRC_CRC1_CONFIG, val)
+#define bfin_read_MDMA1_SRC_CRC1_X_COUNT()              bfin_read32(MDMA1_SRC_CRC1_X_COUNT)
+#define bfin_write_MDMA1_SRC_CRC1_X_COUNT(val)          bfin_write32(MDMA1_SRC_CRC1_X_COUNT, val)
+#define bfin_read_MDMA1_SRC_CRC1_X_MODIFY()             bfin_read32(MDMA1_SRC_CRC1_X_MODIFY)
+#define bfin_write_MDMA1_SRC_CRC1_X_MODIFY(val)         bfin_write32(MDMA1_SRC_CRC1_X_MODIFY, val)
+#define bfin_read_MDMA1_SRC_CRC1_Y_COUNT()              bfin_read32(MDMA1_SRC_CRC1_Y_COUNT)
+#define bfin_write_MDMA1_SRC_CRC1_Y_COUNT(val)          bfin_write32(MDMA1_SRC_CRC1_Y_COUNT, val)
+#define bfin_read_MDMA1_SRC_CRC1_Y_MODIFY()             bfin_read32(MDMA1_SRC_CRC1_Y_MODIFY)
+#define bfin_write_MDMA1_SRC_CRC1_Y_MODIFY(val)         bfin_write32(MDMA1_SRC_CRC1_Y_MODIFY, val)
+#define bfin_read_MDMA1_SRC_CRC1_CURR_DESC_PTR()        bfin_read32(MDMA1_SRC_CRC1_CURR_DESC_PTR)
+#define bfin_write_MDMA1_SRC_CRC1_CURR_DESC_PTR(val)    bfin_write32(MDMA1_SRC_CRC1_CURR_DESC_PTR, val)
+#define bfin_read_MDMA1_SRC_CRC1_PREV_DESC_PTR()        bfin_read32(MDMA1_SRC_CRC1_PREV_DESC_PTR)
+#define bfin_write_MDMA1_SRC_CRC1_PREV_DESC_PTR(val)    bfin_write32(MDMA1_SRC_CRC1_PREV_DESC_PTR, val)
+#define bfin_read_MDMA1_SRC_CRC1_CURR_ADDR()            bfin_read32(MDMA1_SRC_CRC1_CURR_ADDR)
+#define bfin_write_MDMA1_SRC_CRC1_CURR_ADDR(val)        bfin_write32(MDMA1_SRC_CRC1_CURR_ADDR, val)
+#define bfin_read_MDMA1_SRC_CRC1_IRQ_STATUS()           bfin_read32(MDMA1_SRC_CRC1_IRQ_STATUS)
+#define bfin_write_MDMA1_SRC_CRC1_IRQ_STATUS(val)       bfin_write32(MDMA1_SRC_CRC1_IRQ_STATUS, val)
+#define bfin_read_MDMA1_SRC_CRC1_CURR_X_COUNT()         bfin_read32(MDMA1_SRC_CRC1_CURR_X_COUNT)
+#define bfin_write_MDMA1_SRC_CRC1_CURR_X_COUNT(val)     bfin_write32(MDMA1_SRC_CRC1_CURR_X_COUNT, val)
+#define bfin_read_MDMA1_SRC_CRC1_CURR_Y_COUNT()         bfin_read32(MDMA1_SRC_CRC1_CURR_Y_COUNT)
+#define bfin_write_MDMA1_SRC_CRC1_CURR_Y_COUNT(val)     bfin_write32(MDMA1_SRC_CRC1_CURR_Y_COUNT, val)
+/* MDMA Stream 2 Registers (DMA Channel 25 and 26) */
+#define bfin_read_MDMA2_DEST_NEXT_DESC_PTR()            bfin_read32(MDMA2_DEST_NEXT_DESC_PTR)
+#define bfin_write_MDMA2_DEST_NEXT_DESC_PTR(val)        bfin_write32(MDMA2_DEST_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA2_DEST_START_ADDR()               bfin_read32(MDMA2_DEST_START_ADDR)
+#define bfin_write_MDMA2_DEST_START_ADDR(val)           bfin_write32(MDMA2_DEST_START_ADDR, val)
+#define bfin_read_MDMA2_DEST_CONFIG()                   bfin_read32(MDMA2_DEST_CONFIG)
+#define bfin_write_MDMA2_DEST_CONFIG(val)               bfin_write32(MDMA2_DEST_CONFIG, val)
+#define bfin_read_MDMA2_DEST_X_COUNT()                  bfin_read32(MDMA2_DEST_X_COUNT)
+#define bfin_write_MDMA2_DEST_X_COUNT(val)              bfin_write32(MDMA2_DEST_X_COUNT, val)
+#define bfin_read_MDMA2_DEST_X_MODIFY()                 bfin_read32(MDMA2_DEST_X_MODIFY)
+#define bfin_write_MDMA2_DEST_X_MODIFY(val)             bfin_write32(MDMA2_DEST_X_MODIFY, val)
+#define bfin_read_MDMA2_DEST_Y_COUNT()                  bfin_read32(MDMA2_DEST_Y_COUNT)
+#define bfin_write_MDMA2_DEST_Y_COUNT(val)              bfin_write32(MDMA2_DEST_Y_COUNT, val)
+#define bfin_read_MDMA2_DEST_Y_MODIFY()                 bfin_read32(MDMA2_DEST_Y_MODIFY)
+#define bfin_write_MDMA2_DEST_Y_MODIFY(val)             bfin_write32(MDMA2_DEST_Y_MODIFY, val)
+#define bfin_read_MDMA2_DEST_CURR_DESC_PTR()            bfin_read32(MDMA2_DEST_CURR_DESC_PTR)
+#define bfin_write_MDMA2_DEST_CURR_DESC_PTR(val)        bfin_write32(MDMA2_DEST_CURR_DESC_PTR, val)
+#define bfin_read_MDMA2_DEST_PREV_DESC_PTR()            bfin_read32(MDMA2_DEST_PREV_DESC_PTR)
+#define bfin_write_MDMA2_DEST_PREV_DESC_PTR(val)        bfin_write32(MDMA2_DEST_PREV_DESC_PTR, val)
+#define bfin_read_MDMA2_DEST_CURR_ADDR()                bfin_read32(MDMA2_DEST_CURR_ADDR)
+#define bfin_write_MDMA2_DEST_CURR_ADDR(val)            bfin_write32(MDMA2_DEST_CURR_ADDR, val)
+#define bfin_read_MDMA2_DEST_IRQ_STATUS()               bfin_read32(MDMA2_DEST_IRQ_STATUS)
+#define bfin_write_MDMA2_DEST_IRQ_STATUS(val)           bfin_write32(MDMA2_DEST_IRQ_STATUS, val)
+#define bfin_read_MDMA2_DEST_CURR_X_COUNT()             bfin_read32(MDMA2_DEST_CURR_X_COUNT)
+#define bfin_write_MDMA2_DEST_CURR_X_COUNT(val)         bfin_write32(MDMA2_DEST_CURR_X_COUNT, val)
+#define bfin_read_MDMA2_DEST_CURR_Y_COUNT()             bfin_read32(MDMA2_DEST_CURR_Y_COUNT)
+#define bfin_write_MDMA2_DEST_CURR_Y_COUNT(val)         bfin_write32(MDMA2_DEST_CURR_Y_COUNT, val)
+#define bfin_read_MDMA2_SRC_NEXT_DESC_PTR()             bfin_read32(MDMA2_SRC_NEXT_DESC_PTR)
+#define bfin_write_MDMA2_SRC_NEXT_DESC_PTR(val)         bfin_write32(MDMA2_SRC_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA2_SRC_START_ADDR()                bfin_read32(MDMA2_SRC_START_ADDR)
+#define bfin_write_MDMA2_SRC_START_ADDR(val)            bfin_write32(MDMA2_SRC_START_ADDR, val)
+#define bfin_read_MDMA2_SRC_CONFIG()                    bfin_read32(MDMA2_SRC_CONFIG)
+#define bfin_write_MDMA2_SRC_CONFIG(val)                bfin_write32(MDMA2_SRC_CONFIG, val)
+#define bfin_read_MDMA2_SRC_X_COUNT()                   bfin_read32(MDMA2_SRC_X_COUNT)
+#define bfin_write_MDMA2_SRC_X_COUNT(val)               bfin_write32(MDMA2_SRC_X_COUNT, val)
+#define bfin_read_MDMA2_SRC_X_MODIFY()                  bfin_read32(MDMA2_SRC_X_MODIFY)
+#define bfin_write_MDMA2_SRC_X_MODIFY(val)              bfin_write32(MDMA2_SRC_X_MODIFY, val)
+#define bfin_read_MDMA2_SRC_Y_COUNT()                   bfin_read32(MDMA2_SRC_Y_COUNT)
+#define bfin_write_MDMA2_SRC_Y_COUNT(val)               bfin_write32(MDMA2_SRC_Y_COUNT, val)
+#define bfin_read_MDMA2_SRC_Y_MODIFY()                  bfin_read32(MDMA2_SRC_Y_MODIFY)
+#define bfin_write_MDMA2_SRC_Y_MODIFY(val)              bfin_write32(MDMA2_SRC_Y_MODIFY, val)
+#define bfin_read_MDMA2_SRC_CURR_DESC_PTR()             bfin_read32(MDMA2_SRC_CURR_DESC_PTR)
+#define bfin_write_MDMA2_SRC_CURR_DESC_PTR(val)         bfin_write32(MDMA2_SRC_CURR_DESC_PTR, val)
+#define bfin_read_MDMA2_SRC_PREV_DESC_PTR()             bfin_read32(MDMA2_SRC_PREV_DESC_PTR)
+#define bfin_write_MDMA2_SRC_PREV_DESC_PTR(val)         bfin_write32(MDMA2_SRC_PREV_DESC_PTR, val)
+#define bfin_read_MDMA2_SRC_CURR_ADDR()                 bfin_read32(MDMA2_SRC_CURR_ADDR)
+#define bfin_write_MDMA2_SRC_CURR_ADDR(val)             bfin_write32(MDMA2_SRC_CURR_ADDR, val)
+#define bfin_read_MDMA2_SRC_IRQ_STATUS()                bfin_read32(MDMA2_SRC_IRQ_STATUS)
+#define bfin_write_MDMA2_SRC_IRQ_STATUS(val)            bfin_write32(MDMA2_SRC_IRQ_STATUS, val)
+#define bfin_read_MDMA2_SRC_CURR_X_COUNT()              bfin_read32(MDMA2_SRC_CURR_X_COUNT)
+#define bfin_write_MDMA2_SRC_CURR_X_COUNT(val)          bfin_write32(MDMA2_SRC_CURR_X_COUNT, val)
+#define bfin_read_MDMA2_SRC_CURR_Y_COUNT()              bfin_read32(MDMA2_SRC_CURR_Y_COUNT)
+#define bfin_write_MDMA2_SRC_CURR_Y_COUNT(val)          bfin_write32(MDMA2_SRC_CURR_Y_COUNT, val)
+/* MDMA Stream 3 Registers (DMA Channel 27 and 28) */
+#define bfin_read_MDMA3_DEST_NEXT_DESC_PTR()            bfin_read32(MDMA3_DEST_NEXT_DESC_PTR)
+#define bfin_write_MDMA3_DEST_NEXT_DESC_PTR(val)        bfin_write32(MDMA3_DEST_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA3_DEST_START_ADDR()               bfin_read32(MDMA3_DEST_START_ADDR)
+#define bfin_write_MDMA3_DEST_START_ADDR(val)           bfin_write32(MDMA3_DEST_START_ADDR, val)
+#define bfin_read_MDMA3_DEST_CONFIG()                   bfin_read32(MDMA3_DEST_CONFIG)
+#define bfin_write_MDMA3_DEST_CONFIG(val)               bfin_write32(MDMA3_DEST_CONFIG, val)
+#define bfin_read_MDMA3_DEST_X_COUNT()                  bfin_read32(MDMA3_DEST_X_COUNT)
+#define bfin_write_MDMA3_DEST_X_COUNT(val)              bfin_write32(MDMA3_DEST_X_COUNT, val)
+#define bfin_read_MDMA3_DEST_X_MODIFY()                 bfin_read32(MDMA3_DEST_X_MODIFY)
+#define bfin_write_MDMA3_DEST_X_MODIFY(val)             bfin_write32(MDMA3_DEST_X_MODIFY, val)
+#define bfin_read_MDMA3_DEST_Y_COUNT()                  bfin_read32(MDMA3_DEST_Y_COUNT)
+#define bfin_write_MDMA3_DEST_Y_COUNT(val)              bfin_write32(MDMA3_DEST_Y_COUNT, val)
+#define bfin_read_MDMA3_DEST_Y_MODIFY()                 bfin_read32(MDMA3_DEST_Y_MODIFY)
+#define bfin_write_MDMA3_DEST_Y_MODIFY(val)             bfin_write32(MDMA3_DEST_Y_MODIFY, val)
+#define bfin_read_MDMA3_DEST_CURR_DESC_PTR()            bfin_read32(MDMA3_DEST_CURR_DESC_PTR)
+#define bfin_write_MDMA3_DEST_CURR_DESC_PTR(val)        bfin_write32(MDMA3_DEST_CURR_DESC_PTR, val)
+#define bfin_read_MDMA3_DEST_PREV_DESC_PTR()            bfin_read32(MDMA3_DEST_PREV_DESC_PTR)
+#define bfin_write_MDMA3_DEST_PREV_DESC_PTR(val)        bfin_write32(MDMA3_DEST_PREV_DESC_PTR, val)
+#define bfin_read_MDMA3_DEST_CURR_ADDR()                bfin_read32(MDMA3_DEST_CURR_ADDR)
+#define bfin_write_MDMA3_DEST_CURR_ADDR(val)            bfin_write32(MDMA3_DEST_CURR_ADDR, val)
+#define bfin_read_MDMA3_DEST_IRQ_STATUS()               bfin_read32(MDMA3_DEST_IRQ_STATUS)
+#define bfin_write_MDMA3_DEST_IRQ_STATUS(val)           bfin_write32(MDMA3_DEST_IRQ_STATUS, val)
+#define bfin_read_MDMA3_DEST_CURR_X_COUNT()             bfin_read32(MDMA3_DEST_CURR_X_COUNT)
+#define bfin_write_MDMA3_DEST_CURR_X_COUNT(val)         bfin_write32(MDMA3_DEST_CURR_X_COUNT, val)
+#define bfin_read_MDMA3_DEST_CURR_Y_COUNT()             bfin_read32(MDMA3_DEST_CURR_Y_COUNT)
+#define bfin_write_MDMA3_DEST_CURR_Y_COUNT(val)         bfin_write32(MDMA3_DEST_CURR_Y_COUNT, val)
+#define bfin_read_MDMA3_SRC_NEXT_DESC_PTR()             bfin_read32(MDMA3_SRC_NEXT_DESC_PTR)
+#define bfin_write_MDMA3_SRC_NEXT_DESC_PTR(val)         bfin_write32(MDMA3_SRC_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA3_SRC_START_ADDR()                bfin_read32(MDMA3_SRC_START_ADDR)
+#define bfin_write_MDMA3_SRC_START_ADDR(val)            bfin_write32(MDMA3_SRC_START_ADDR, val)
+#define bfin_read_MDMA3_SRC_CONFIG()                    bfin_read32(MDMA3_SRC_CONFIG)
+#define bfin_write_MDMA3_SRC_CONFIG(val)                bfin_write32(MDMA3_SRC_CONFIG, val)
+#define bfin_read_MDMA3_SRC_X_COUNT()                   bfin_read32(MDMA3_SRC_X_COUNT)
+#define bfin_write_MDMA3_SRC_X_COUNT(val)               bfin_write32(MDMA3_SRC_X_COUNT, val)
+#define bfin_read_MDMA3_SRC_X_MODIFY()                  bfin_read32(MDMA3_SRC_X_MODIFY)
+#define bfin_write_MDMA3_SRC_X_MODIFY(val)              bfin_write32(MDMA3_SRC_X_MODIFY, val)
+#define bfin_read_MDMA3_SRC_Y_COUNT()                   bfin_read32(MDMA3_SRC_Y_COUNT)
+#define bfin_write_MDMA3_SRC_Y_COUNT(val)               bfin_write32(MDMA3_SRC_Y_COUNT, val)
+#define bfin_read_MDMA3_SRC_Y_MODIFY()                  bfin_read32(MDMA3_SRC_Y_MODIFY)
+#define bfin_write_MDMA3_SRC_Y_MODIFY(val)              bfin_write32(MDMA3_SRC_Y_MODIFY, val)
+#define bfin_read_MDMA3_SRC_CURR_DESC_PTR()             bfin_read32(MDMA3_SRC_CURR_DESC_PTR)
+#define bfin_write_MDMA3_SRC_CURR_DESC_PTR(val)         bfin_write32(MDMA3_SRC_CURR_DESC_PTR, val)
+#define bfin_read_MDMA3_SRC_PREV_DESC_PTR()             bfin_read32(MDMA3_SRC_PREV_DESC_PTR)
+#define bfin_write_MDMA3_SRC_PREV_DESC_PTR(val)         bfin_write32(MDMA3_SRC_PREV_DESC_PTR, val)
+#define bfin_read_MDMA3_SRC_CURR_ADDR()                 bfin_read32(MDMA3_SRC_CURR_ADDR)
+#define bfin_write_MDMA3_SRC_CURR_ADDR(val)             bfin_write32(MDMA3_SRC_CURR_ADDR, val)
+#define bfin_read_MDMA3_SRC_IRQ_STATUS()                bfin_read32(MDMA3_SRC_IRQ_STATUS)
+#define bfin_write_MDMA3_SRC_IRQ_STATUS(val)            bfin_write32(MDMA3_SRC_IRQ_STATUS, val)
+#define bfin_read_MDMA3_SRC_CURR_X_COUNT()              bfin_read32(MDMA3_SRC_CURR_X_COUNT)
+#define bfin_write_MDMA3_SRC_CURR_X_COUNT(val)          bfin_write32(MDMA3_SRC_CURR_X_COUNT, val)
+#define bfin_read_MDMA3_SRC_CURR_Y_COUNT()              bfin_read32(MDMA3_SRC_CURR_Y_COUNT)
+#define bfin_write_MDMA3_SRC_CURR_Y_COUNT(val)          bfin_write32(MDMA3_SRC_CURR_Y_COUNT, val)
+/* DMA Channel 29 Registers */
+#define bfin_read_DMA29_NEXT_DESC_PTR()         bfin_read32(DMA29_NEXT_DESC_PTR)
+#define bfin_write_DMA29_NEXT_DESC_PTR(val)     bfin_write32(DMA29_NEXT_DESC_PTR, val)
+#define bfin_read_DMA29_START_ADDR()            bfin_read32(DMA29_START_ADDR)
+#define bfin_write_DMA29_START_ADDR(val)        bfin_write32(DMA29_START_ADDR, val)
+#define bfin_read_DMA29_CONFIG()                bfin_read32(DMA29_CONFIG)
+#define bfin_write_DMA29_CONFIG(val)            bfin_write32(DMA29_CONFIG, val)
+#define bfin_read_DMA29_X_COUNT()               bfin_read32(DMA29_X_COUNT)
+#define bfin_write_DMA29_X_COUNT(val)           bfin_write32(DMA29_X_COUNT, val)
+#define bfin_read_DMA29_X_MODIFY()              bfin_read32(DMA29_X_MODIFY)
+#define bfin_write_DMA29_X_MODIFY(val)          bfin_write32(DMA29_X_MODIFY, val)
+#define bfin_read_DMA29_Y_COUNT()               bfin_read32(DMA29_Y_COUNT)
+#define bfin_write_DMA29_Y_COUNT(val)           bfin_write32(DMA29_Y_COUNT, val)
+#define bfin_read_DMA29_Y_MODIFY()              bfin_read32(DMA29_Y_MODIFY)
+#define bfin_write_DMA29_Y_MODIFY(val)          bfin_write32(DMA29_Y_MODIFY, val)
+#define bfin_read_DMA29_CURR_DESC_PTR()         bfin_read32(DMA29_CURR_DESC_PTR)
+#define bfin_write_DMA29_CURR_DESC_PTR(val)     bfin_write32(DMA29_CURR_DESC_PTR, val)
+#define bfin_read_DMA29_PREV_DESC_PTR()         bfin_read32(DMA29_PREV_DESC_PTR)
+#define bfin_write_DMA29_PREV_DESC_PTR(val)     bfin_write32(DMA29_PREV_DESC_PTR, val)
+#define bfin_read_DMA29_CURR_ADDR()             bfin_read32(DMA29_CURR_ADDR)
+#define bfin_write_DMA29_CURR_ADDR(val)         bfin_write32(DMA29_CURR_ADDR, val)
+#define bfin_read_DMA29_IRQ_STATUS()            bfin_read32(DMA29_IRQ_STATUS)
+#define bfin_write_DMA29_IRQ_STATUS(val)        bfin_write32(DMA29_IRQ_STATUS, val)
+#define bfin_read_DMA29_CURR_X_COUNT()          bfin_read32(DMA29_CURR_X_COUNT)
+#define bfin_write_DMA29_CURR_X_COUNT(val)      bfin_write32(DMA29_CURR_X_COUNT, val)
+#define bfin_read_DMA29_CURR_Y_COUNT()          bfin_read32(DMA29_CURR_Y_COUNT)
+#define bfin_write_DMA29_CURR_Y_COUNT(val)      bfin_write32(DMA29_CURR_Y_COUNT, val)
+#define bfin_read_DMA29_BWL_COUNT()             bfin_read32(DMA29_BWL_COUNT)
+#define bfin_write_DMA29_BWL_COUNT(val)         bfin_write32(DMA29_BWL_COUNT, val)
+#define bfin_read_DMA29_CURR_BWL_COUNT()        bfin_read32(DMA29_CURR_BWL_COUNT)
+#define bfin_write_DMA29_CURR_BWL_COUNT(val)    bfin_write32(DMA29_CURR_BWL_COUNT, val)
+#define bfin_read_DMA29_BWM_COUNT()             bfin_read32(DMA29_BWM_COUNT)
+#define bfin_write_DMA29_BWM_COUNT(val)         bfin_write32(DMA29_BWM_COUNT, val)
+#define bfin_read_DMA29_CURR_BWM_COUNT()        bfin_read32(DMA29_CURR_BWM_COUNT)
+#define bfin_write_DMA29_CURR_BWM_COUNT(val)    bfin_write32(DMA29_CURR_BWM_COUNT, val)
+/* DMA Channel 30 Registers */
+#define bfin_read_DMA30_NEXT_DESC_PTR()         bfin_read32(DMA30_NEXT_DESC_PTR)
+#define bfin_write_DMA30_NEXT_DESC_PTR(val)     bfin_write32(DMA30_NEXT_DESC_PTR, val)
+#define bfin_read_DMA30_START_ADDR()            bfin_read32(DMA30_START_ADDR)
+#define bfin_write_DMA30_START_ADDR(val)        bfin_write32(DMA30_START_ADDR, val)
+#define bfin_read_DMA30_CONFIG()                bfin_read32(DMA30_CONFIG)
+#define bfin_write_DMA30_CONFIG(val)            bfin_write32(DMA30_CONFIG, val)
+#define bfin_read_DMA30_X_COUNT()               bfin_read32(DMA30_X_COUNT)
+#define bfin_write_DMA30_X_COUNT(val)           bfin_write32(DMA30_X_COUNT, val)
+#define bfin_read_DMA30_X_MODIFY()              bfin_read32(DMA30_X_MODIFY)
+#define bfin_write_DMA30_X_MODIFY(val)          bfin_write32(DMA30_X_MODIFY, val)
+#define bfin_read_DMA30_Y_COUNT()               bfin_read32(DMA30_Y_COUNT)
+#define bfin_write_DMA30_Y_COUNT(val)           bfin_write32(DMA30_Y_COUNT, val)
+#define bfin_read_DMA30_Y_MODIFY()              bfin_read32(DMA30_Y_MODIFY)
+#define bfin_write_DMA30_Y_MODIFY(val)          bfin_write32(DMA30_Y_MODIFY, val)
+#define bfin_read_DMA30_CURR_DESC_PTR()         bfin_read32(DMA30_CURR_DESC_PTR)
+#define bfin_write_DMA30_CURR_DESC_PTR(val)     bfin_write32(DMA30_CURR_DESC_PTR, val)
+#define bfin_read_DMA30_PREV_DESC_PTR()         bfin_read32(DMA30_PREV_DESC_PTR)
+#define bfin_write_DMA30_PREV_DESC_PTR(val)     bfin_write32(DMA30_PREV_DESC_PTR, val)
+#define bfin_read_DMA30_CURR_ADDR()             bfin_read32(DMA30_CURR_ADDR)
+#define bfin_write_DMA30_CURR_ADDR(val)         bfin_write32(DMA30_CURR_ADDR, val)
+#define bfin_read_DMA30_IRQ_STATUS()            bfin_read32(DMA30_IRQ_STATUS)
+#define bfin_write_DMA30_IRQ_STATUS(val)        bfin_write32(DMA30_IRQ_STATUS, val)
+#define bfin_read_DMA30_CURR_X_COUNT()          bfin_read32(DMA30_CURR_X_COUNT)
+#define bfin_write_DMA30_CURR_X_COUNT(val)      bfin_write32(DMA30_CURR_X_COUNT, val)
+#define bfin_read_DMA30_CURR_Y_COUNT()          bfin_read32(DMA30_CURR_Y_COUNT)
+#define bfin_write_DMA30_CURR_Y_COUNT(val)      bfin_write32(DMA30_CURR_Y_COUNT, val)
+#define bfin_read_DMA30_BWL_COUNT()             bfin_read32(DMA30_BWL_COUNT)
+#define bfin_write_DMA30_BWL_COUNT(val)         bfin_write32(DMA30_BWL_COUNT, val)
+#define bfin_read_DMA30_CURR_BWL_COUNT()        bfin_read32(DMA30_CURR_BWL_COUNT)
+#define bfin_write_DMA30_CURR_BWL_COUNT(val)    bfin_write32(DMA30_CURR_BWL_COUNT, val)
+#define bfin_read_DMA30_BWM_COUNT()             bfin_read32(DMA30_BWM_COUNT)
+#define bfin_write_DMA30_BWM_COUNT(val)         bfin_write32(DMA30_BWM_COUNT, val)
+#define bfin_read_DMA30_CURR_BWM_COUNT()        bfin_read32(DMA30_CURR_BWM_COUNT)
+#define bfin_write_DMA30_CURR_BWM_COUNT(val)    bfin_write32(DMA30_CURR_BWM_COUNT, val)
+/* DMA Channel 31 Registers */
+#define bfin_read_DMA31_NEXT_DESC_PTR()         bfin_read32(DMA31_NEXT_DESC_PTR)
+#define bfin_write_DMA31_NEXT_DESC_PTR(val)     bfin_write32(DMA31_NEXT_DESC_PTR, val)
+#define bfin_read_DMA31_START_ADDR()            bfin_read32(DMA31_START_ADDR)
+#define bfin_write_DMA31_START_ADDR(val)        bfin_write32(DMA31_START_ADDR, val)
+#define bfin_read_DMA31_CONFIG()                bfin_read32(DMA31_CONFIG)
+#define bfin_write_DMA31_CONFIG(val)            bfin_write32(DMA31_CONFIG, val)
+#define bfin_read_DMA31_X_COUNT()               bfin_read32(DMA31_X_COUNT)
+#define bfin_write_DMA31_X_COUNT(val)           bfin_write32(DMA31_X_COUNT, val)
+#define bfin_read_DMA31_X_MODIFY()              bfin_read32(DMA31_X_MODIFY)
+#define bfin_write_DMA31_X_MODIFY(val)          bfin_write32(DMA31_X_MODIFY, val)
+#define bfin_read_DMA31_Y_COUNT()               bfin_read32(DMA31_Y_COUNT)
+#define bfin_write_DMA31_Y_COUNT(val)           bfin_write32(DMA31_Y_COUNT, val)
+#define bfin_read_DMA31_Y_MODIFY()              bfin_read32(DMA31_Y_MODIFY)
+#define bfin_write_DMA31_Y_MODIFY(val)          bfin_write32(DMA31_Y_MODIFY, val)
+#define bfin_read_DMA31_CURR_DESC_PTR()         bfin_read32(DMA31_CURR_DESC_PTR)
+#define bfin_write_DMA31_CURR_DESC_PTR(val)     bfin_write32(DMA31_CURR_DESC_PTR, val)
+#define bfin_read_DMA31_PREV_DESC_PTR()         bfin_read32(DMA31_PREV_DESC_PTR)
+#define bfin_write_DMA31_PREV_DESC_PTR(val)     bfin_write32(DMA31_PREV_DESC_PTR, val)
+#define bfin_read_DMA31_CURR_ADDR()             bfin_read32(DMA31_CURR_ADDR)
+#define bfin_write_DMA31_CURR_ADDR(val)         bfin_write32(DMA31_CURR_ADDR, val)
+#define bfin_read_DMA31_IRQ_STATUS()            bfin_read32(DMA31_IRQ_STATUS)
+#define bfin_write_DMA31_IRQ_STATUS(val)        bfin_write32(DMA31_IRQ_STATUS, val)
+#define bfin_read_DMA31_CURR_X_COUNT()          bfin_read32(DMA31_CURR_X_COUNT)
+#define bfin_write_DMA31_CURR_X_COUNT(val)      bfin_write32(DMA31_CURR_X_COUNT, val)
+#define bfin_read_DMA31_CURR_Y_COUNT()          bfin_read32(DMA31_CURR_Y_COUNT)
+#define bfin_write_DMA31_CURR_Y_COUNT(val)      bfin_write32(DMA31_CURR_Y_COUNT, val)
+#define bfin_read_DMA31_BWL_COUNT()             bfin_read32(DMA31_BWL_COUNT)
+#define bfin_write_DMA31_BWL_COUNT(val)         bfin_write32(DMA31_BWL_COUNT, val)
+#define bfin_read_DMA31_CURR_BWL_COUNT()        bfin_read32(DMA31_CURR_BWL_COUNT)
+#define bfin_write_DMA31_CURR_BWL_COUNT(val)    bfin_write32(DMA31_CURR_BWL_COUNT, val)
+#define bfin_read_DMA31_BWM_COUNT()             bfin_read32(DMA31_BWM_COUNT)
+#define bfin_write_DMA31_BWM_COUNT(val)         bfin_write32(DMA31_BWM_COUNT, val)
+#define bfin_read_DMA31_CURR_BWM_COUNT()        bfin_read32(DMA31_CURR_BWM_COUNT)
+#define bfin_write_DMA31_CURR_BWM_COUNT(val)    bfin_write32(DMA31_CURR_BWM_COUNT, val)
+/* DMA Channel 32 Registers */
+#define bfin_read_DMA32_NEXT_DESC_PTR()         bfin_read32(DMA32_NEXT_DESC_PTR)
+#define bfin_write_DMA32_NEXT_DESC_PTR(val)     bfin_write32(DMA32_NEXT_DESC_PTR, val)
+#define bfin_read_DMA32_START_ADDR()            bfin_read32(DMA32_START_ADDR)
+#define bfin_write_DMA32_START_ADDR(val)        bfin_write32(DMA32_START_ADDR, val)
+#define bfin_read_DMA32_CONFIG()                bfin_read32(DMA32_CONFIG)
+#define bfin_write_DMA32_CONFIG(val)            bfin_write32(DMA32_CONFIG, val)
+#define bfin_read_DMA32_X_COUNT()               bfin_read32(DMA32_X_COUNT)
+#define bfin_write_DMA32_X_COUNT(val)           bfin_write32(DMA32_X_COUNT, val)
+#define bfin_read_DMA32_X_MODIFY()              bfin_read32(DMA32_X_MODIFY)
+#define bfin_write_DMA32_X_MODIFY(val)          bfin_write32(DMA32_X_MODIFY, val)
+#define bfin_read_DMA32_Y_COUNT()               bfin_read32(DMA32_Y_COUNT)
+#define bfin_write_DMA32_Y_COUNT(val)           bfin_write32(DMA32_Y_COUNT, val)
+#define bfin_read_DMA32_Y_MODIFY()              bfin_read32(DMA32_Y_MODIFY)
+#define bfin_write_DMA32_Y_MODIFY(val)          bfin_write32(DMA32_Y_MODIFY, val)
+#define bfin_read_DMA32_CURR_DESC_PTR()         bfin_read32(DMA32_CURR_DESC_PTR)
+#define bfin_write_DMA32_CURR_DESC_PTR(val)     bfin_write32(DMA32_CURR_DESC_PTR, val)
+#define bfin_read_DMA32_PREV_DESC_PTR()         bfin_read32(DMA32_PREV_DESC_PTR)
+#define bfin_write_DMA32_PREV_DESC_PTR(val)     bfin_write32(DMA32_PREV_DESC_PTR, val)
+#define bfin_read_DMA32_CURR_ADDR()             bfin_read32(DMA32_CURR_ADDR)
+#define bfin_write_DMA32_CURR_ADDR(val)         bfin_write32(DMA32_CURR_ADDR, val)
+#define bfin_read_DMA32_IRQ_STATUS()            bfin_read32(DMA32_IRQ_STATUS)
+#define bfin_write_DMA32_IRQ_STATUS(val)        bfin_write32(DMA32_IRQ_STATUS, val)
+#define bfin_read_DMA32_CURR_X_COUNT()          bfin_read32(DMA32_CURR_X_COUNT)
+#define bfin_write_DMA32_CURR_X_COUNT(val)      bfin_write32(DMA32_CURR_X_COUNT, val)
+#define bfin_read_DMA32_CURR_Y_COUNT()          bfin_read32(DMA32_CURR_Y_COUNT)
+#define bfin_write_DMA32_CURR_Y_COUNT(val)      bfin_write32(DMA32_CURR_Y_COUNT, val)
+#define bfin_read_DMA32_BWL_COUNT()             bfin_read32(DMA32_BWL_COUNT)
+#define bfin_write_DMA32_BWL_COUNT(val)         bfin_write32(DMA32_BWL_COUNT, val)
+#define bfin_read_DMA32_CURR_BWL_COUNT()        bfin_read32(DMA32_CURR_BWL_COUNT)
+#define bfin_write_DMA32_CURR_BWL_COUNT(val)    bfin_write32(DMA32_CURR_BWL_COUNT, val)
+#define bfin_read_DMA32_BWM_COUNT()             bfin_read32(DMA32_BWM_COUNT)
+#define bfin_write_DMA32_BWM_COUNT(val)         bfin_write32(DMA32_BWM_COUNT, val)
+#define bfin_read_DMA32_CURR_BWM_COUNT()        bfin_read32(DMA32_CURR_BWM_COUNT)
+#define bfin_write_DMA32_CURR_BWM_COUNT(val)    bfin_write32(DMA32_CURR_BWM_COUNT, val)
+/* DMA Channel 33 Registers */
+#define bfin_read_DMA33_NEXT_DESC_PTR()         bfin_read32(DMA33_NEXT_DESC_PTR)
+#define bfin_write_DMA33_NEXT_DESC_PTR(val)     bfin_write32(DMA33_NEXT_DESC_PTR, val)
+#define bfin_read_DMA33_START_ADDR()            bfin_read32(DMA33_START_ADDR)
+#define bfin_write_DMA33_START_ADDR(val)        bfin_write32(DMA33_START_ADDR, val)
+#define bfin_read_DMA33_CONFIG()                bfin_read32(DMA33_CONFIG)
+#define bfin_write_DMA33_CONFIG(val)            bfin_write32(DMA33_CONFIG, val)
+#define bfin_read_DMA33_X_COUNT()               bfin_read32(DMA33_X_COUNT)
+#define bfin_write_DMA33_X_COUNT(val)           bfin_write32(DMA33_X_COUNT, val)
+#define bfin_read_DMA33_X_MODIFY()              bfin_read32(DMA33_X_MODIFY)
+#define bfin_write_DMA33_X_MODIFY(val)          bfin_write32(DMA33_X_MODIFY, val)
+#define bfin_read_DMA33_Y_COUNT()               bfin_read32(DMA33_Y_COUNT)
+#define bfin_write_DMA33_Y_COUNT(val)           bfin_write32(DMA33_Y_COUNT, val)
+#define bfin_read_DMA33_Y_MODIFY()              bfin_read32(DMA33_Y_MODIFY)
+#define bfin_write_DMA33_Y_MODIFY(val)          bfin_write32(DMA33_Y_MODIFY, val)
+#define bfin_read_DMA33_CURR_DESC_PTR()         bfin_read32(DMA33_CURR_DESC_PTR)
+#define bfin_write_DMA33_CURR_DESC_PTR(val)     bfin_write32(DMA33_CURR_DESC_PTR, val)
+#define bfin_read_DMA33_PREV_DESC_PTR()         bfin_read32(DMA33_PREV_DESC_PTR)
+#define bfin_write_DMA33_PREV_DESC_PTR(val)     bfin_write32(DMA33_PREV_DESC_PTR, val)
+#define bfin_read_DMA33_CURR_ADDR()             bfin_read32(DMA33_CURR_ADDR)
+#define bfin_write_DMA33_CURR_ADDR(val)         bfin_write32(DMA33_CURR_ADDR, val)
+#define bfin_read_DMA33_IRQ_STATUS()            bfin_read32(DMA33_IRQ_STATUS)
+#define bfin_write_DMA33_IRQ_STATUS(val)        bfin_write32(DMA33_IRQ_STATUS, val)
+#define bfin_read_DMA33_CURR_X_COUNT()          bfin_read32(DMA33_CURR_X_COUNT)
+#define bfin_write_DMA33_CURR_X_COUNT(val)      bfin_write32(DMA33_CURR_X_COUNT, val)
+#define bfin_read_DMA33_CURR_Y_COUNT()          bfin_read32(DMA33_CURR_Y_COUNT)
+#define bfin_write_DMA33_CURR_Y_COUNT(val)      bfin_write32(DMA33_CURR_Y_COUNT, val)
+#define bfin_read_DMA33_BWL_COUNT()             bfin_read32(DMA33_BWL_COUNT)
+#define bfin_write_DMA33_BWL_COUNT(val)         bfin_write32(DMA33_BWL_COUNT, val)
+#define bfin_read_DMA33_CURR_BWL_COUNT()        bfin_read32(DMA33_CURR_BWL_COUNT)
+#define bfin_write_DMA33_CURR_BWL_COUNT(val)    bfin_write32(DMA33_CURR_BWL_COUNT, val)
+#define bfin_read_DMA33_BWM_COUNT()             bfin_read32(DMA33_BWM_COUNT)
+#define bfin_write_DMA33_BWM_COUNT(val)         bfin_write32(DMA33_BWM_COUNT, val)
+#define bfin_read_DMA33_CURR_BWM_COUNT()        bfin_read32(DMA33_CURR_BWM_COUNT)
+#define bfin_write_DMA33_CURR_BWM_COUNT(val)    bfin_write32(DMA33_CURR_BWM_COUNT, val)
+/* DMA Channel 34 Registers */
+#define bfin_read_DMA34_NEXT_DESC_PTR()         bfin_read32(DMA34_NEXT_DESC_PTR)
+#define bfin_write_DMA34_NEXT_DESC_PTR(val)     bfin_write32(DMA34_NEXT_DESC_PTR, val)
+#define bfin_read_DMA34_START_ADDR()            bfin_read32(DMA34_START_ADDR)
+#define bfin_write_DMA34_START_ADDR(val)        bfin_write32(DMA34_START_ADDR, val)
+#define bfin_read_DMA34_CONFIG()                bfin_read32(DMA34_CONFIG)
+#define bfin_write_DMA34_CONFIG(val)            bfin_write32(DMA34_CONFIG, val)
+#define bfin_read_DMA34_X_COUNT()               bfin_read32(DMA34_X_COUNT)
+#define bfin_write_DMA34_X_COUNT(val)           bfin_write32(DMA34_X_COUNT, val)
+#define bfin_read_DMA34_X_MODIFY()              bfin_read32(DMA34_X_MODIFY)
+#define bfin_write_DMA34_X_MODIFY(val)          bfin_write32(DMA34_X_MODIFY, val)
+#define bfin_read_DMA34_Y_COUNT()               bfin_read32(DMA34_Y_COUNT)
+#define bfin_write_DMA34_Y_COUNT(val)           bfin_write32(DMA34_Y_COUNT, val)
+#define bfin_read_DMA34_Y_MODIFY()              bfin_read32(DMA34_Y_MODIFY)
+#define bfin_write_DMA34_Y_MODIFY(val)          bfin_write32(DMA34_Y_MODIFY, val)
+#define bfin_read_DMA34_CURR_DESC_PTR()         bfin_read32(DMA34_CURR_DESC_PTR)
+#define bfin_write_DMA34_CURR_DESC_PTR(val)     bfin_write32(DMA34_CURR_DESC_PTR, val)
+#define bfin_read_DMA34_PREV_DESC_PTR()         bfin_read32(DMA34_PREV_DESC_PTR)
+#define bfin_write_DMA34_PREV_DESC_PTR(val)     bfin_write32(DMA34_PREV_DESC_PTR, val)
+#define bfin_read_DMA34_CURR_ADDR()             bfin_read32(DMA34_CURR_ADDR)
+#define bfin_write_DMA34_CURR_ADDR(val)         bfin_write32(DMA34_CURR_ADDR, val)
+#define bfin_read_DMA34_IRQ_STATUS()            bfin_read32(DMA34_IRQ_STATUS)
+#define bfin_write_DMA34_IRQ_STATUS(val)        bfin_write32(DMA34_IRQ_STATUS, val)
+#define bfin_read_DMA34_CURR_X_COUNT()          bfin_read32(DMA34_CURR_X_COUNT)
+#define bfin_write_DMA34_CURR_X_COUNT(val)      bfin_write32(DMA34_CURR_X_COUNT, val)
+#define bfin_read_DMA34_CURR_Y_COUNT()          bfin_read32(DMA34_CURR_Y_COUNT)
+#define bfin_write_DMA34_CURR_Y_COUNT(val)      bfin_write32(DMA34_CURR_Y_COUNT, val)
+#define bfin_read_DMA34_BWL_COUNT()             bfin_read32(DMA34_BWL_COUNT)
+#define bfin_write_DMA34_BWL_COUNT(val)         bfin_write32(DMA34_BWL_COUNT, val)
+#define bfin_read_DMA34_CURR_BWL_COUNT()        bfin_read32(DMA34_CURR_BWL_COUNT)
+#define bfin_write_DMA34_CURR_BWL_COUNT(val)    bfin_write32(DMA34_CURR_BWL_COUNT, val)
+#define bfin_read_DMA34_BWM_COUNT()             bfin_read32(DMA34_BWM_COUNT)
+#define bfin_write_DMA34_BWM_COUNT(val)         bfin_write32(DMA34_BWM_COUNT, val)
+#define bfin_read_DMA34_CURR_BWM_COUNT()        bfin_read32(DMA34_CURR_BWM_COUNT)
+#define bfin_write_DMA34_CURR_BWM_COUNT(val)    bfin_write32(DMA34_CURR_BWM_COUNT, val)
+/* DMA Channel 35 Registers */
+#define bfin_read_DMA35_NEXT_DESC_PTR()         bfin_read32(DMA35_NEXT_DESC_PTR)
+#define bfin_write_DMA35_NEXT_DESC_PTR(val)     bfin_write32(DMA35_NEXT_DESC_PTR, val)
+#define bfin_read_DMA35_START_ADDR()            bfin_read32(DMA35_START_ADDR)
+#define bfin_write_DMA35_START_ADDR(val)        bfin_write32(DMA35_START_ADDR, val)
+#define bfin_read_DMA35_CONFIG()                bfin_read32(DMA35_CONFIG)
+#define bfin_write_DMA35_CONFIG(val)            bfin_write32(DMA35_CONFIG, val)
+#define bfin_read_DMA35_X_COUNT()               bfin_read32(DMA35_X_COUNT)
+#define bfin_write_DMA35_X_COUNT(val)           bfin_write32(DMA35_X_COUNT, val)
+#define bfin_read_DMA35_X_MODIFY()              bfin_read32(DMA35_X_MODIFY)
+#define bfin_write_DMA35_X_MODIFY(val)          bfin_write32(DMA35_X_MODIFY, val)
+#define bfin_read_DMA35_Y_COUNT()               bfin_read32(DMA35_Y_COUNT)
+#define bfin_write_DMA35_Y_COUNT(val)           bfin_write32(DMA35_Y_COUNT, val)
+#define bfin_read_DMA35_Y_MODIFY()              bfin_read32(DMA35_Y_MODIFY)
+#define bfin_write_DMA35_Y_MODIFY(val)          bfin_write32(DMA35_Y_MODIFY, val)
+#define bfin_read_DMA35_CURR_DESC_PTR()         bfin_read32(DMA35_CURR_DESC_PTR)
+#define bfin_write_DMA35_CURR_DESC_PTR(val)     bfin_write32(DMA35_CURR_DESC_PTR, val)
+#define bfin_read_DMA35_PREV_DESC_PTR()         bfin_read32(DMA35_PREV_DESC_PTR)
+#define bfin_write_DMA35_PREV_DESC_PTR(val)     bfin_write32(DMA35_PREV_DESC_PTR, val)
+#define bfin_read_DMA35_CURR_ADDR()             bfin_read32(DMA35_CURR_ADDR)
+#define bfin_write_DMA35_CURR_ADDR(val)         bfin_write32(DMA35_CURR_ADDR, val)
+#define bfin_read_DMA35_IRQ_STATUS()            bfin_read32(DMA35_IRQ_STATUS)
+#define bfin_write_DMA35_IRQ_STATUS(val)        bfin_write32(DMA35_IRQ_STATUS, val)
+#define bfin_read_DMA35_CURR_X_COUNT()          bfin_read32(DMA35_CURR_X_COUNT)
+#define bfin_write_DMA35_CURR_X_COUNT(val)      bfin_write32(DMA35_CURR_X_COUNT, val)
+#define bfin_read_DMA35_CURR_Y_COUNT()          bfin_read32(DMA35_CURR_Y_COUNT)
+#define bfin_write_DMA35_CURR_Y_COUNT(val)      bfin_write32(DMA35_CURR_Y_COUNT, val)
+#define bfin_read_DMA35_BWL_COUNT()             bfin_read32(DMA35_BWL_COUNT)
+#define bfin_write_DMA35_BWL_COUNT(val)         bfin_write32(DMA35_BWL_COUNT, val)
+#define bfin_read_DMA35_CURR_BWL_COUNT()        bfin_read32(DMA35_CURR_BWL_COUNT)
+#define bfin_write_DMA35_CURR_BWL_COUNT(val)    bfin_write32(DMA35_CURR_BWL_COUNT, val)
+#define bfin_read_DMA35_BWM_COUNT()             bfin_read32(DMA35_BWM_COUNT)
+#define bfin_write_DMA35_BWM_COUNT(val)         bfin_write32(DMA35_BWM_COUNT, val)
+#define bfin_read_DMA35_CURR_BWM_COUNT()        bfin_read32(DMA35_CURR_BWM_COUNT)
+#define bfin_write_DMA35_CURR_BWM_COUNT(val)    bfin_write32(DMA35_CURR_BWM_COUNT, val)
+/* DMA Channel 36 Registers */
+#define bfin_read_DMA36_NEXT_DESC_PTR()         bfin_read32(DMA36_NEXT_DESC_PTR)
+#define bfin_write_DMA36_NEXT_DESC_PTR(val)     bfin_write32(DMA36_NEXT_DESC_PTR, val)
+#define bfin_read_DMA36_START_ADDR()            bfin_read32(DMA36_START_ADDR)
+#define bfin_write_DMA36_START_ADDR(val)        bfin_write32(DMA36_START_ADDR, val)
+#define bfin_read_DMA36_CONFIG()                bfin_read32(DMA36_CONFIG)
+#define bfin_write_DMA36_CONFIG(val)            bfin_write32(DMA36_CONFIG, val)
+#define bfin_read_DMA36_X_COUNT()               bfin_read32(DMA36_X_COUNT)
+#define bfin_write_DMA36_X_COUNT(val)           bfin_write32(DMA36_X_COUNT, val)
+#define bfin_read_DMA36_X_MODIFY()              bfin_read32(DMA36_X_MODIFY)
+#define bfin_write_DMA36_X_MODIFY(val)          bfin_write32(DMA36_X_MODIFY, val)
+#define bfin_read_DMA36_Y_COUNT()               bfin_read32(DMA36_Y_COUNT)
+#define bfin_write_DMA36_Y_COUNT(val)           bfin_write32(DMA36_Y_COUNT, val)
+#define bfin_read_DMA36_Y_MODIFY()              bfin_read32(DMA36_Y_MODIFY)
+#define bfin_write_DMA36_Y_MODIFY(val)          bfin_write32(DMA36_Y_MODIFY, val)
+#define bfin_read_DMA36_CURR_DESC_PTR()         bfin_read32(DMA36_CURR_DESC_PTR)
+#define bfin_write_DMA36_CURR_DESC_PTR(val)     bfin_write32(DMA36_CURR_DESC_PTR, val)
+#define bfin_read_DMA36_PREV_DESC_PTR()         bfin_read32(DMA36_PREV_DESC_PTR)
+#define bfin_write_DMA36_PREV_DESC_PTR(val)     bfin_write32(DMA36_PREV_DESC_PTR, val)
+#define bfin_read_DMA36_CURR_ADDR()             bfin_read32(DMA36_CURR_ADDR)
+#define bfin_write_DMA36_CURR_ADDR(val)         bfin_write32(DMA36_CURR_ADDR, val)
+#define bfin_read_DMA36_IRQ_STATUS()            bfin_read32(DMA36_IRQ_STATUS)
+#define bfin_write_DMA36_IRQ_STATUS(val)        bfin_write32(DMA36_IRQ_STATUS, val)
+#define bfin_read_DMA36_CURR_X_COUNT()          bfin_read32(DMA36_CURR_X_COUNT)
+#define bfin_write_DMA36_CURR_X_COUNT(val)      bfin_write32(DMA36_CURR_X_COUNT, val)
+#define bfin_read_DMA36_CURR_Y_COUNT()          bfin_read32(DMA36_CURR_Y_COUNT)
+#define bfin_write_DMA36_CURR_Y_COUNT(val)      bfin_write32(DMA36_CURR_Y_COUNT, val)
+#define bfin_read_DMA36_BWL_COUNT()             bfin_read32(DMA36_BWL_COUNT)
+#define bfin_write_DMA36_BWL_COUNT(val)         bfin_write32(DMA36_BWL_COUNT, val)
+#define bfin_read_DMA36_CURR_BWL_COUNT()        bfin_read32(DMA36_CURR_BWL_COUNT)
+#define bfin_write_DMA36_CURR_BWL_COUNT(val)    bfin_write32(DMA36_CURR_BWL_COUNT, val)
+#define bfin_read_DMA36_BWM_COUNT()             bfin_read32(DMA36_BWM_COUNT)
+#define bfin_write_DMA36_BWM_COUNT(val)         bfin_write32(DMA36_BWM_COUNT, val)
+#define bfin_read_DMA36_CURR_BWM_COUNT()        bfin_read32(DMA36_CURR_BWM_COUNT)
+#define bfin_write_DMA36_CURR_BWM_COUNT(val)    bfin_write32(DMA36_CURR_BWM_COUNT, val)
+/* DMA Channel 37 Registers */
+#define bfin_read_DMA37_NEXT_DESC_PTR()         bfin_read32(DMA37_NEXT_DESC_PTR)
+#define bfin_write_DMA37_NEXT_DESC_PTR(val)     bfin_write32(DMA37_NEXT_DESC_PTR, val)
+#define bfin_read_DMA37_START_ADDR()            bfin_read32(DMA37_START_ADDR)
+#define bfin_write_DMA37_START_ADDR(val)        bfin_write32(DMA37_START_ADDR, val)
+#define bfin_read_DMA37_CONFIG()                bfin_read32(DMA37_CONFIG)
+#define bfin_write_DMA37_CONFIG(val)            bfin_write32(DMA37_CONFIG, val)
+#define bfin_read_DMA37_X_COUNT()               bfin_read32(DMA37_X_COUNT)
+#define bfin_write_DMA37_X_COUNT(val)           bfin_write32(DMA37_X_COUNT, val)
+#define bfin_read_DMA37_X_MODIFY()              bfin_read32(DMA37_X_MODIFY)
+#define bfin_write_DMA37_X_MODIFY(val)          bfin_write32(DMA37_X_MODIFY, val)
+#define bfin_read_DMA37_Y_COUNT()               bfin_read32(DMA37_Y_COUNT)
+#define bfin_write_DMA37_Y_COUNT(val)           bfin_write32(DMA37_Y_COUNT, val)
+#define bfin_read_DMA37_Y_MODIFY()              bfin_read32(DMA37_Y_MODIFY)
+#define bfin_write_DMA37_Y_MODIFY(val)          bfin_write32(DMA37_Y_MODIFY, val)
+#define bfin_read_DMA37_CURR_DESC_PTR()         bfin_read32(DMA37_CURR_DESC_PTR)
+#define bfin_write_DMA37_CURR_DESC_PTR(val)     bfin_write32(DMA37_CURR_DESC_PTR, val)
+#define bfin_read_DMA37_PREV_DESC_PTR()         bfin_read32(DMA37_PREV_DESC_PTR)
+#define bfin_write_DMA37_PREV_DESC_PTR(val)     bfin_write32(DMA37_PREV_DESC_PTR, val)
+#define bfin_read_DMA37_CURR_ADDR()             bfin_read32(DMA37_CURR_ADDR)
+#define bfin_write_DMA37_CURR_ADDR(val)         bfin_write32(DMA37_CURR_ADDR, val)
+#define bfin_read_DMA37_IRQ_STATUS()            bfin_read32(DMA37_IRQ_STATUS)
+#define bfin_write_DMA37_IRQ_STATUS(val)        bfin_write32(DMA37_IRQ_STATUS, val)
+#define bfin_read_DMA37_CURR_X_COUNT()          bfin_read32(DMA37_CURR_X_COUNT)
+#define bfin_write_DMA37_CURR_X_COUNT(val)      bfin_write32(DMA37_CURR_X_COUNT, val)
+#define bfin_read_DMA37_CURR_Y_COUNT()          bfin_read32(DMA37_CURR_Y_COUNT)
+#define bfin_write_DMA37_CURR_Y_COUNT(val)      bfin_write32(DMA37_CURR_Y_COUNT, val)
+#define bfin_read_DMA37_BWL_COUNT()             bfin_read32(DMA37_BWL_COUNT)
+#define bfin_write_DMA37_BWL_COUNT(val)         bfin_write32(DMA37_BWL_COUNT, val)
+#define bfin_read_DMA37_CURR_BWL_COUNT()        bfin_read32(DMA37_CURR_BWL_COUNT)
+#define bfin_write_DMA37_CURR_BWL_COUNT(val)    bfin_write32(DMA37_CURR_BWL_COUNT, val)
+#define bfin_read_DMA37_BWM_COUNT()             bfin_read32(DMA37_BWM_COUNT)
+#define bfin_write_DMA37_BWM_COUNT(val)         bfin_write32(DMA37_BWM_COUNT, val)
+#define bfin_read_DMA37_CURR_BWM_COUNT()        bfin_read32(DMA37_CURR_BWM_COUNT)
+#define bfin_write_DMA37_CURR_BWM_COUNT(val)    bfin_write32(DMA37_CURR_BWM_COUNT, val)
+/* DMA Channel 38 Registers */
+#define bfin_read_DMA38_NEXT_DESC_PTR()         bfin_read32(DMA38_NEXT_DESC_PTR)
+#define bfin_write_DMA38_NEXT_DESC_PTR(val)     bfin_write32(DMA38_NEXT_DESC_PTR, val)
+#define bfin_read_DMA38_START_ADDR()            bfin_read32(DMA38_START_ADDR)
+#define bfin_write_DMA38_START_ADDR(val)        bfin_write32(DMA38_START_ADDR, val)
+#define bfin_read_DMA38_CONFIG()                bfin_read32(DMA38_CONFIG)
+#define bfin_write_DMA38_CONFIG(val)            bfin_write32(DMA38_CONFIG, val)
+#define bfin_read_DMA38_X_COUNT()               bfin_read32(DMA38_X_COUNT)
+#define bfin_write_DMA38_X_COUNT(val)           bfin_write32(DMA38_X_COUNT, val)
+#define bfin_read_DMA38_X_MODIFY()              bfin_read32(DMA38_X_MODIFY)
+#define bfin_write_DMA38_X_MODIFY(val)          bfin_write32(DMA38_X_MODIFY, val)
+#define bfin_read_DMA38_Y_COUNT()               bfin_read32(DMA38_Y_COUNT)
+#define bfin_write_DMA38_Y_COUNT(val)           bfin_write32(DMA38_Y_COUNT, val)
+#define bfin_read_DMA38_Y_MODIFY()              bfin_read32(DMA38_Y_MODIFY)
+#define bfin_write_DMA38_Y_MODIFY(val)          bfin_write32(DMA38_Y_MODIFY, val)
+#define bfin_read_DMA38_CURR_DESC_PTR()         bfin_read32(DMA38_CURR_DESC_PTR)
+#define bfin_write_DMA38_CURR_DESC_PTR(val)     bfin_write32(DMA38_CURR_DESC_PTR, val)
+#define bfin_read_DMA38_PREV_DESC_PTR()         bfin_read32(DMA38_PREV_DESC_PTR)
+#define bfin_write_DMA38_PREV_DESC_PTR(val)     bfin_write32(DMA38_PREV_DESC_PTR, val)
+#define bfin_read_DMA38_CURR_ADDR()             bfin_read32(DMA38_CURR_ADDR)
+#define bfin_write_DMA38_CURR_ADDR(val)         bfin_write32(DMA38_CURR_ADDR, val)
+#define bfin_read_DMA38_IRQ_STATUS()            bfin_read32(DMA38_IRQ_STATUS)
+#define bfin_write_DMA38_IRQ_STATUS(val)        bfin_write32(DMA38_IRQ_STATUS, val)
+#define bfin_read_DMA38_CURR_X_COUNT()          bfin_read32(DMA38_CURR_X_COUNT)
+#define bfin_write_DMA38_CURR_X_COUNT(val)      bfin_write32(DMA38_CURR_X_COUNT, val)
+#define bfin_read_DMA38_CURR_Y_COUNT()          bfin_read32(DMA38_CURR_Y_COUNT)
+#define bfin_write_DMA38_CURR_Y_COUNT(val)      bfin_write32(DMA38_CURR_Y_COUNT, val)
+#define bfin_read_DMA38_BWL_COUNT()             bfin_read32(DMA38_BWL_COUNT)
+#define bfin_write_DMA38_BWL_COUNT(val)         bfin_write32(DMA38_BWL_COUNT, val)
+#define bfin_read_DMA38_CURR_BWL_COUNT()        bfin_read32(DMA38_CURR_BWL_COUNT)
+#define bfin_write_DMA38_CURR_BWL_COUNT(val)    bfin_write32(DMA38_CURR_BWL_COUNT, val)
+#define bfin_read_DMA38_BWM_COUNT()             bfin_read32(DMA38_BWM_COUNT)
+#define bfin_write_DMA38_BWM_COUNT(val)         bfin_write32(DMA38_BWM_COUNT, val)
+#define bfin_read_DMA38_CURR_BWM_COUNT()        bfin_read32(DMA38_CURR_BWM_COUNT)
+#define bfin_write_DMA38_CURR_BWM_COUNT(val)    bfin_write32(DMA38_CURR_BWM_COUNT, val)
+/* DMA Channel 39 Registers */
+#define bfin_read_DMA39_NEXT_DESC_PTR()         bfin_read32(DMA39_NEXT_DESC_PTR)
+#define bfin_write_DMA39_NEXT_DESC_PTR(val)     bfin_write32(DMA39_NEXT_DESC_PTR, val)
+#define bfin_read_DMA39_START_ADDR()            bfin_read32(DMA39_START_ADDR)
+#define bfin_write_DMA39_START_ADDR(val)        bfin_write32(DMA39_START_ADDR, val)
+#define bfin_read_DMA39_CONFIG()                bfin_read32(DMA39_CONFIG)
+#define bfin_write_DMA39_CONFIG(val)            bfin_write32(DMA39_CONFIG, val)
+#define bfin_read_DMA39_X_COUNT()               bfin_read32(DMA39_X_COUNT)
+#define bfin_write_DMA39_X_COUNT(val)           bfin_write32(DMA39_X_COUNT, val)
+#define bfin_read_DMA39_X_MODIFY()              bfin_read32(DMA39_X_MODIFY)
+#define bfin_write_DMA39_X_MODIFY(val)          bfin_write32(DMA39_X_MODIFY, val)
+#define bfin_read_DMA39_Y_COUNT()               bfin_read32(DMA39_Y_COUNT)
+#define bfin_write_DMA39_Y_COUNT(val)           bfin_write32(DMA39_Y_COUNT, val)
+#define bfin_read_DMA39_Y_MODIFY()              bfin_read32(DMA39_Y_MODIFY)
+#define bfin_write_DMA39_Y_MODIFY(val)          bfin_write32(DMA39_Y_MODIFY, val)
+#define bfin_read_DMA39_CURR_DESC_PTR()         bfin_read32(DMA39_CURR_DESC_PTR)
+#define bfin_write_DMA39_CURR_DESC_PTR(val)     bfin_write32(DMA39_CURR_DESC_PTR, val)
+#define bfin_read_DMA39_PREV_DESC_PTR()         bfin_read32(DMA39_PREV_DESC_PTR)
+#define bfin_write_DMA39_PREV_DESC_PTR(val)     bfin_write32(DMA39_PREV_DESC_PTR, val)
+#define bfin_read_DMA39_CURR_ADDR()             bfin_read32(DMA39_CURR_ADDR)
+#define bfin_write_DMA39_CURR_ADDR(val)         bfin_write32(DMA39_CURR_ADDR, val)
+#define bfin_read_DMA39_IRQ_STATUS()            bfin_read32(DMA39_IRQ_STATUS)
+#define bfin_write_DMA39_IRQ_STATUS(val)        bfin_write32(DMA39_IRQ_STATUS, val)
+#define bfin_read_DMA39_CURR_X_COUNT()          bfin_read32(DMA39_CURR_X_COUNT)
+#define bfin_write_DMA39_CURR_X_COUNT(val)      bfin_write32(DMA39_CURR_X_COUNT, val)
+#define bfin_read_DMA39_CURR_Y_COUNT()          bfin_read32(DMA39_CURR_Y_COUNT)
+#define bfin_write_DMA39_CURR_Y_COUNT(val)      bfin_write32(DMA39_CURR_Y_COUNT, val)
+#define bfin_read_DMA39_BWL_COUNT()             bfin_read32(DMA39_BWL_COUNT)
+#define bfin_write_DMA39_BWL_COUNT(val)         bfin_write32(DMA39_BWL_COUNT, val)
+#define bfin_read_DMA39_CURR_BWL_COUNT()        bfin_read32(DMA39_CURR_BWL_COUNT)
+#define bfin_write_DMA39_CURR_BWL_COUNT(val)    bfin_write32(DMA39_CURR_BWL_COUNT, val)
+#define bfin_read_DMA39_BWM_COUNT()             bfin_read32(DMA39_BWM_COUNT)
+#define bfin_write_DMA39_BWM_COUNT(val)         bfin_write32(DMA39_BWM_COUNT, val)
+#define bfin_read_DMA39_CURR_BWM_COUNT()        bfin_read32(DMA39_CURR_BWM_COUNT)
+#define bfin_write_DMA39_CURR_BWM_COUNT(val)    bfin_write32(DMA39_CURR_BWM_COUNT, val)
+/* DMA Channel 40 Registers */
+#define bfin_read_DMA40_NEXT_DESC_PTR()         bfin_read32(DMA40_NEXT_DESC_PTR)
+#define bfin_write_DMA40_NEXT_DESC_PTR(val)     bfin_write32(DMA40_NEXT_DESC_PTR, val)
+#define bfin_read_DMA40_START_ADDR()            bfin_read32(DMA40_START_ADDR)
+#define bfin_write_DMA40_START_ADDR(val)        bfin_write32(DMA40_START_ADDR, val)
+#define bfin_read_DMA40_CONFIG()                bfin_read32(DMA40_CONFIG)
+#define bfin_write_DMA40_CONFIG(val)            bfin_write32(DMA40_CONFIG, val)
+#define bfin_read_DMA40_X_COUNT()               bfin_read32(DMA40_X_COUNT)
+#define bfin_write_DMA40_X_COUNT(val)           bfin_write32(DMA40_X_COUNT, val)
+#define bfin_read_DMA40_X_MODIFY()              bfin_read32(DMA40_X_MODIFY)
+#define bfin_write_DMA40_X_MODIFY(val)          bfin_write32(DMA40_X_MODIFY, val)
+#define bfin_read_DMA40_Y_COUNT()               bfin_read32(DMA40_Y_COUNT)
+#define bfin_write_DMA40_Y_COUNT(val)           bfin_write32(DMA40_Y_COUNT, val)
+#define bfin_read_DMA40_Y_MODIFY()              bfin_read32(DMA40_Y_MODIFY)
+#define bfin_write_DMA40_Y_MODIFY(val)          bfin_write32(DMA40_Y_MODIFY, val)
+#define bfin_read_DMA40_CURR_DESC_PTR()         bfin_read32(DMA40_CURR_DESC_PTR)
+#define bfin_write_DMA40_CURR_DESC_PTR(val)     bfin_write32(DMA40_CURR_DESC_PTR, val)
+#define bfin_read_DMA40_PREV_DESC_PTR()         bfin_read32(DMA40_PREV_DESC_PTR)
+#define bfin_write_DMA40_PREV_DESC_PTR(val)     bfin_write32(DMA40_PREV_DESC_PTR, val)
+#define bfin_read_DMA40_CURR_ADDR()             bfin_read32(DMA40_CURR_ADDR)
+#define bfin_write_DMA40_CURR_ADDR(val)         bfin_write32(DMA40_CURR_ADDR, val)
+#define bfin_read_DMA40_IRQ_STATUS()            bfin_read32(DMA40_IRQ_STATUS)
+#define bfin_write_DMA40_IRQ_STATUS(val)        bfin_write32(DMA40_IRQ_STATUS, val)
+#define bfin_read_DMA40_CURR_X_COUNT()          bfin_read32(DMA40_CURR_X_COUNT)
+#define bfin_write_DMA40_CURR_X_COUNT(val)      bfin_write32(DMA40_CURR_X_COUNT, val)
+#define bfin_read_DMA40_CURR_Y_COUNT()          bfin_read32(DMA40_CURR_Y_COUNT)
+#define bfin_write_DMA40_CURR_Y_COUNT(val)      bfin_write32(DMA40_CURR_Y_COUNT, val)
+#define bfin_read_DMA40_BWL_COUNT()             bfin_read32(DMA40_BWL_COUNT)
+#define bfin_write_DMA40_BWL_COUNT(val)         bfin_write32(DMA40_BWL_COUNT, val)
+#define bfin_read_DMA40_CURR_BWL_COUNT()        bfin_read32(DMA40_CURR_BWL_COUNT)
+#define bfin_write_DMA40_CURR_BWL_COUNT(val)    bfin_write32(DMA40_CURR_BWL_COUNT, val)
+#define bfin_read_DMA40_BWM_COUNT()             bfin_read32(DMA40_BWM_COUNT)
+#define bfin_write_DMA40_BWM_COUNT(val)         bfin_write32(DMA40_BWM_COUNT, val)
+#define bfin_read_DMA40_CURR_BWM_COUNT()        bfin_read32(DMA40_CURR_BWM_COUNT)
+#define bfin_write_DMA40_CURR_BWM_COUNT(val)    bfin_write32(DMA40_CURR_BWM_COUNT, val)
+/* DMA Channel 41 Registers */
+#define bfin_read_DMA41_NEXT_DESC_PTR()         bfin_read32(DMA41_NEXT_DESC_PTR)
+#define bfin_write_DMA41_NEXT_DESC_PTR(val)     bfin_write32(DMA41_NEXT_DESC_PTR, val)
+#define bfin_read_DMA41_START_ADDR()            bfin_read32(DMA41_START_ADDR)
+#define bfin_write_DMA41_START_ADDR(val)        bfin_write32(DMA41_START_ADDR, val)
+#define bfin_read_DMA41_CONFIG()                bfin_read32(DMA41_CONFIG)
+#define bfin_write_DMA41_CONFIG(val)            bfin_write32(DMA41_CONFIG, val)
+#define bfin_read_DMA41_X_COUNT()               bfin_read32(DMA41_X_COUNT)
+#define bfin_write_DMA41_X_COUNT(val)           bfin_write32(DMA41_X_COUNT, val)
+#define bfin_read_DMA41_X_MODIFY()              bfin_read32(DMA41_X_MODIFY)
+#define bfin_write_DMA41_X_MODIFY(val)          bfin_write32(DMA41_X_MODIFY, val)
+#define bfin_read_DMA41_Y_COUNT()               bfin_read32(DMA41_Y_COUNT)
+#define bfin_write_DMA41_Y_COUNT(val)           bfin_write32(DMA41_Y_COUNT, val)
+#define bfin_read_DMA41_Y_MODIFY()              bfin_read32(DMA41_Y_MODIFY)
+#define bfin_write_DMA41_Y_MODIFY(val)          bfin_write32(DMA41_Y_MODIFY, val)
+#define bfin_read_DMA41_CURR_DESC_PTR()         bfin_read32(DMA41_CURR_DESC_PTR)
+#define bfin_write_DMA41_CURR_DESC_PTR(val)     bfin_write32(DMA41_CURR_DESC_PTR, val)
+#define bfin_read_DMA41_PREV_DESC_PTR()         bfin_read32(DMA41_PREV_DESC_PTR)
+#define bfin_write_DMA41_PREV_DESC_PTR(val)     bfin_write32(DMA41_PREV_DESC_PTR, val)
+#define bfin_read_DMA41_CURR_ADDR()             bfin_read32(DMA41_CURR_ADDR)
+#define bfin_write_DMA41_CURR_ADDR(val)         bfin_write32(DMA41_CURR_ADDR, val)
+#define bfin_read_DMA41_IRQ_STATUS()            bfin_read32(DMA41_IRQ_STATUS)
+#define bfin_write_DMA41_IRQ_STATUS(val)        bfin_write32(DMA41_IRQ_STATUS, val)
+#define bfin_read_DMA41_CURR_X_COUNT()          bfin_read32(DMA41_CURR_X_COUNT)
+#define bfin_write_DMA41_CURR_X_COUNT(val)      bfin_write32(DMA41_CURR_X_COUNT, val)
+#define bfin_read_DMA41_CURR_Y_COUNT()          bfin_read32(DMA41_CURR_Y_COUNT)
+#define bfin_write_DMA41_CURR_Y_COUNT(val)      bfin_write32(DMA41_CURR_Y_COUNT, val)
+#define bfin_read_DMA41_BWL_COUNT()             bfin_read32(DMA41_BWL_COUNT)
+#define bfin_write_DMA41_BWL_COUNT(val)         bfin_write32(DMA41_BWL_COUNT, val)
+#define bfin_read_DMA41_CURR_BWL_COUNT()        bfin_read32(DMA41_CURR_BWL_COUNT)
+#define bfin_write_DMA41_CURR_BWL_COUNT(val)    bfin_write32(DMA41_CURR_BWL_COUNT, val)
+#define bfin_read_DMA41_BWM_COUNT()             bfin_read32(DMA41_BWM_COUNT)
+#define bfin_write_DMA41_BWM_COUNT(val)         bfin_write32(DMA41_BWM_COUNT, val)
+#define bfin_read_DMA41_CURR_BWM_COUNT()        bfin_read32(DMA41_CURR_BWM_COUNT)
+#define bfin_write_DMA41_CURR_BWM_COUNT(val)    bfin_write32(DMA41_CURR_BWM_COUNT, val)
+/* DMA Channel 42 Registers */
+#define bfin_read_DMA42_NEXT_DESC_PTR()         bfin_read32(DMA42_NEXT_DESC_PTR)
+#define bfin_write_DMA42_NEXT_DESC_PTR(val)     bfin_write32(DMA42_NEXT_DESC_PTR, val)
+#define bfin_read_DMA42_START_ADDR()            bfin_read32(DMA42_START_ADDR)
+#define bfin_write_DMA42_START_ADDR(val)        bfin_write32(DMA42_START_ADDR, val)
+#define bfin_read_DMA42_CONFIG()                bfin_read32(DMA42_CONFIG)
+#define bfin_write_DMA42_CONFIG(val)            bfin_write32(DMA42_CONFIG, val)
+#define bfin_read_DMA42_X_COUNT()               bfin_read32(DMA42_X_COUNT)
+#define bfin_write_DMA42_X_COUNT(val)           bfin_write32(DMA42_X_COUNT, val)
+#define bfin_read_DMA42_X_MODIFY()              bfin_read32(DMA42_X_MODIFY)
+#define bfin_write_DMA42_X_MODIFY(val)          bfin_write32(DMA42_X_MODIFY, val)
+#define bfin_read_DMA42_Y_COUNT()               bfin_read32(DMA42_Y_COUNT)
+#define bfin_write_DMA42_Y_COUNT(val)           bfin_write32(DMA42_Y_COUNT, val)
+#define bfin_read_DMA42_Y_MODIFY()              bfin_read32(DMA42_Y_MODIFY)
+#define bfin_write_DMA42_Y_MODIFY(val)          bfin_write32(DMA42_Y_MODIFY, val)
+#define bfin_read_DMA42_CURR_DESC_PTR()         bfin_read32(DMA42_CURR_DESC_PTR)
+#define bfin_write_DMA42_CURR_DESC_PTR(val)     bfin_write32(DMA42_CURR_DESC_PTR, val)
+#define bfin_read_DMA42_PREV_DESC_PTR()         bfin_read32(DMA42_PREV_DESC_PTR)
+#define bfin_write_DMA42_PREV_DESC_PTR(val)     bfin_write32(DMA42_PREV_DESC_PTR, val)
+#define bfin_read_DMA42_CURR_ADDR()             bfin_read32(DMA42_CURR_ADDR)
+#define bfin_write_DMA42_CURR_ADDR(val)         bfin_write32(DMA42_CURR_ADDR, val)
+#define bfin_read_DMA42_IRQ_STATUS()            bfin_read32(DMA42_IRQ_STATUS)
+#define bfin_write_DMA42_IRQ_STATUS(val)        bfin_write32(DMA42_IRQ_STATUS, val)
+#define bfin_read_DMA42_CURR_X_COUNT()          bfin_read32(DMA42_CURR_X_COUNT)
+#define bfin_write_DMA42_CURR_X_COUNT(val)      bfin_write32(DMA42_CURR_X_COUNT, val)
+#define bfin_read_DMA42_CURR_Y_COUNT()          bfin_read32(DMA42_CURR_Y_COUNT)
+#define bfin_write_DMA42_CURR_Y_COUNT(val)      bfin_write32(DMA42_CURR_Y_COUNT, val)
+#define bfin_read_DMA42_BWL_COUNT()             bfin_read32(DMA42_BWL_COUNT)
+#define bfin_write_DMA42_BWL_COUNT(val)         bfin_write32(DMA42_BWL_COUNT, val)
+#define bfin_read_DMA42_CURR_BWL_COUNT()        bfin_read32(DMA42_CURR_BWL_COUNT)
+#define bfin_write_DMA42_CURR_BWL_COUNT(val)    bfin_write32(DMA42_CURR_BWL_COUNT, val)
+#define bfin_read_DMA42_BWM_COUNT()             bfin_read32(DMA42_BWM_COUNT)
+#define bfin_write_DMA42_BWM_COUNT(val)         bfin_write32(DMA42_BWM_COUNT, val)
+#define bfin_read_DMA42_CURR_BWM_COUNT()        bfin_read32(DMA42_CURR_BWM_COUNT)
+#define bfin_write_DMA42_CURR_BWM_COUNT(val)    bfin_write32(DMA42_CURR_BWM_COUNT, val)
+/* DMA Channel 43 Registers */
+#define bfin_read_DMA43_NEXT_DESC_PTR()         bfin_read32(DMA43_NEXT_DESC_PTR)
+#define bfin_write_DMA43_NEXT_DESC_PTR(val)     bfin_write32(DMA43_NEXT_DESC_PTR, val)
+#define bfin_read_DMA43_START_ADDR()            bfin_read32(DMA43_START_ADDR)
+#define bfin_write_DMA43_START_ADDR(val)        bfin_write32(DMA43_START_ADDR, val)
+#define bfin_read_DMA43_CONFIG()                bfin_read32(DMA43_CONFIG)
+#define bfin_write_DMA43_CONFIG(val)            bfin_write32(DMA43_CONFIG, val)
+#define bfin_read_DMA43_X_COUNT()               bfin_read32(DMA43_X_COUNT)
+#define bfin_write_DMA43_X_COUNT(val)           bfin_write32(DMA43_X_COUNT, val)
+#define bfin_read_DMA43_X_MODIFY()              bfin_read32(DMA43_X_MODIFY)
+#define bfin_write_DMA43_X_MODIFY(val)          bfin_write32(DMA43_X_MODIFY, val)
+#define bfin_read_DMA43_Y_COUNT()               bfin_read32(DMA43_Y_COUNT)
+#define bfin_write_DMA43_Y_COUNT(val)           bfin_write32(DMA43_Y_COUNT, val)
+#define bfin_read_DMA43_Y_MODIFY()              bfin_read32(DMA43_Y_MODIFY)
+#define bfin_write_DMA43_Y_MODIFY(val)          bfin_write32(DMA43_Y_MODIFY, val)
+#define bfin_read_DMA43_CURR_DESC_PTR()         bfin_read32(DMA43_CURR_DESC_PTR)
+#define bfin_write_DMA43_CURR_DESC_PTR(val)     bfin_write32(DMA43_CURR_DESC_PTR, val)
+#define bfin_read_DMA43_PREV_DESC_PTR()         bfin_read32(DMA43_PREV_DESC_PTR)
+#define bfin_write_DMA43_PREV_DESC_PTR(val)     bfin_write32(DMA43_PREV_DESC_PTR, val)
+#define bfin_read_DMA43_CURR_ADDR()             bfin_read32(DMA43_CURR_ADDR)
+#define bfin_write_DMA43_CURR_ADDR(val)         bfin_write32(DMA43_CURR_ADDR, val)
+#define bfin_read_DMA43_IRQ_STATUS()            bfin_read32(DMA43_IRQ_STATUS)
+#define bfin_write_DMA43_IRQ_STATUS(val)        bfin_write32(DMA43_IRQ_STATUS, val)
+#define bfin_read_DMA43_CURR_X_COUNT()          bfin_read32(DMA43_CURR_X_COUNT)
+#define bfin_write_DMA43_CURR_X_COUNT(val)      bfin_write32(DMA43_CURR_X_COUNT, val)
+#define bfin_read_DMA43_CURR_Y_COUNT()          bfin_read32(DMA43_CURR_Y_COUNT)
+#define bfin_write_DMA43_CURR_Y_COUNT(val)      bfin_write32(DMA43_CURR_Y_COUNT, val)
+#define bfin_read_DMA43_BWL_COUNT()             bfin_read32(DMA43_BWL_COUNT)
+#define bfin_write_DMA43_BWL_COUNT(val)         bfin_write32(DMA43_BWL_COUNT, val)
+#define bfin_read_DMA43_CURR_BWL_COUNT()        bfin_read32(DMA43_CURR_BWL_COUNT)
+#define bfin_write_DMA43_CURR_BWL_COUNT(val)    bfin_write32(DMA43_CURR_BWL_COUNT, val)
+#define bfin_read_DMA43_BWM_COUNT()             bfin_read32(DMA43_BWM_COUNT)
+#define bfin_write_DMA43_BWM_COUNT(val)         bfin_write32(DMA43_BWM_COUNT, val)
+#define bfin_read_DMA43_CURR_BWM_COUNT()        bfin_read32(DMA43_CURR_BWM_COUNT)
+#define bfin_write_DMA43_CURR_BWM_COUNT(val)    bfin_write32(DMA43_CURR_BWM_COUNT, val)
+/* DMA Channel 44 Registers */
+#define bfin_read_DMA44_NEXT_DESC_PTR()         bfin_read32(DMA44_NEXT_DESC_PTR)
+#define bfin_write_DMA44_NEXT_DESC_PTR(val)     bfin_write32(DMA44_NEXT_DESC_PTR, val)
+#define bfin_read_DMA44_START_ADDR()            bfin_read32(DMA44_START_ADDR)
+#define bfin_write_DMA44_START_ADDR(val)        bfin_write32(DMA44_START_ADDR, val)
+#define bfin_read_DMA44_CONFIG()                bfin_read32(DMA44_CONFIG)
+#define bfin_write_DMA44_CONFIG(val)            bfin_write32(DMA44_CONFIG, val)
+#define bfin_read_DMA44_X_COUNT()               bfin_read32(DMA44_X_COUNT)
+#define bfin_write_DMA44_X_COUNT(val)           bfin_write32(DMA44_X_COUNT, val)
+#define bfin_read_DMA44_X_MODIFY()              bfin_read32(DMA44_X_MODIFY)
+#define bfin_write_DMA44_X_MODIFY(val)          bfin_write32(DMA44_X_MODIFY, val)
+#define bfin_read_DMA44_Y_COUNT()               bfin_read32(DMA44_Y_COUNT)
+#define bfin_write_DMA44_Y_COUNT(val)           bfin_write32(DMA44_Y_COUNT, val)
+#define bfin_read_DMA44_Y_MODIFY()              bfin_read32(DMA44_Y_MODIFY)
+#define bfin_write_DMA44_Y_MODIFY(val)          bfin_write32(DMA44_Y_MODIFY, val)
+#define bfin_read_DMA44_CURR_DESC_PTR()         bfin_read32(DMA44_CURR_DESC_PTR)
+#define bfin_write_DMA44_CURR_DESC_PTR(val)     bfin_write32(DMA44_CURR_DESC_PTR, val)
+#define bfin_read_DMA44_PREV_DESC_PTR()         bfin_read32(DMA44_PREV_DESC_PTR)
+#define bfin_write_DMA44_PREV_DESC_PTR(val)     bfin_write32(DMA44_PREV_DESC_PTR, val)
+#define bfin_read_DMA44_CURR_ADDR()             bfin_read32(DMA44_CURR_ADDR)
+#define bfin_write_DMA44_CURR_ADDR(val)         bfin_write32(DMA44_CURR_ADDR, val)
+#define bfin_read_DMA44_IRQ_STATUS()            bfin_read32(DMA44_IRQ_STATUS)
+#define bfin_write_DMA44_IRQ_STATUS(val)        bfin_write32(DMA44_IRQ_STATUS, val)
+#define bfin_read_DMA44_CURR_X_COUNT()          bfin_read32(DMA44_CURR_X_COUNT)
+#define bfin_write_DMA44_CURR_X_COUNT(val)      bfin_write32(DMA44_CURR_X_COUNT, val)
+#define bfin_read_DMA44_CURR_Y_COUNT()          bfin_read32(DMA44_CURR_Y_COUNT)
+#define bfin_write_DMA44_CURR_Y_COUNT(val)      bfin_write32(DMA44_CURR_Y_COUNT, val)
+#define bfin_read_DMA44_BWL_COUNT()             bfin_read32(DMA44_BWL_COUNT)
+#define bfin_write_DMA44_BWL_COUNT(val)         bfin_write32(DMA44_BWL_COUNT, val)
+#define bfin_read_DMA44_CURR_BWL_COUNT()        bfin_read32(DMA44_CURR_BWL_COUNT)
+#define bfin_write_DMA44_CURR_BWL_COUNT(val)    bfin_write32(DMA44_CURR_BWL_COUNT, val)
+#define bfin_read_DMA44_BWM_COUNT()             bfin_read32(DMA44_BWM_COUNT)
+#define bfin_write_DMA44_BWM_COUNT(val)         bfin_write32(DMA44_BWM_COUNT, val)
+#define bfin_read_DMA44_CURR_BWM_COUNT()        bfin_read32(DMA44_CURR_BWM_COUNT)
+#define bfin_write_DMA44_CURR_BWM_COUNT(val)    bfin_write32(DMA44_CURR_BWM_COUNT, val)
+/* DMA Channel 45 Registers */
+#define bfin_read_DMA45_NEXT_DESC_PTR()         bfin_read32(DMA45_NEXT_DESC_PTR)
+#define bfin_write_DMA45_NEXT_DESC_PTR(val)     bfin_write32(DMA45_NEXT_DESC_PTR, val)
+#define bfin_read_DMA45_START_ADDR()            bfin_read32(DMA45_START_ADDR)
+#define bfin_write_DMA45_START_ADDR(val)        bfin_write32(DMA45_START_ADDR, val)
+#define bfin_read_DMA45_CONFIG()                bfin_read32(DMA45_CONFIG)
+#define bfin_write_DMA45_CONFIG(val)            bfin_write32(DMA45_CONFIG, val)
+#define bfin_read_DMA45_X_COUNT()               bfin_read32(DMA45_X_COUNT)
+#define bfin_write_DMA45_X_COUNT(val)           bfin_write32(DMA45_X_COUNT, val)
+#define bfin_read_DMA45_X_MODIFY()              bfin_read32(DMA45_X_MODIFY)
+#define bfin_write_DMA45_X_MODIFY(val)          bfin_write32(DMA45_X_MODIFY, val)
+#define bfin_read_DMA45_Y_COUNT()               bfin_read32(DMA45_Y_COUNT)
+#define bfin_write_DMA45_Y_COUNT(val)           bfin_write32(DMA45_Y_COUNT, val)
+#define bfin_read_DMA45_Y_MODIFY()              bfin_read32(DMA45_Y_MODIFY)
+#define bfin_write_DMA45_Y_MODIFY(val)          bfin_write32(DMA45_Y_MODIFY, val)
+#define bfin_read_DMA45_CURR_DESC_PTR()         bfin_read32(DMA45_CURR_DESC_PTR)
+#define bfin_write_DMA45_CURR_DESC_PTR(val)     bfin_write32(DMA45_CURR_DESC_PTR, val)
+#define bfin_read_DMA45_PREV_DESC_PTR()         bfin_read32(DMA45_PREV_DESC_PTR)
+#define bfin_write_DMA45_PREV_DESC_PTR(val)     bfin_write32(DMA45_PREV_DESC_PTR, val)
+#define bfin_read_DMA45_CURR_ADDR()             bfin_read32(DMA45_CURR_ADDR)
+#define bfin_write_DMA45_CURR_ADDR(val)         bfin_write32(DMA45_CURR_ADDR, val)
+#define bfin_read_DMA45_IRQ_STATUS()            bfin_read32(DMA45_IRQ_STATUS)
+#define bfin_write_DMA45_IRQ_STATUS(val)        bfin_write32(DMA45_IRQ_STATUS, val)
+#define bfin_read_DMA45_CURR_X_COUNT()          bfin_read32(DMA45_CURR_X_COUNT)
+#define bfin_write_DMA45_CURR_X_COUNT(val)      bfin_write32(DMA45_CURR_X_COUNT, val)
+#define bfin_read_DMA45_CURR_Y_COUNT()          bfin_read32(DMA45_CURR_Y_COUNT)
+#define bfin_write_DMA45_CURR_Y_COUNT(val)      bfin_write32(DMA45_CURR_Y_COUNT, val)
+#define bfin_read_DMA45_BWL_COUNT()             bfin_read32(DMA45_BWL_COUNT)
+#define bfin_write_DMA45_BWL_COUNT(val)         bfin_write32(DMA45_BWL_COUNT, val)
+#define bfin_read_DMA45_CURR_BWL_COUNT()        bfin_read32(DMA45_CURR_BWL_COUNT)
+#define bfin_write_DMA45_CURR_BWL_COUNT(val)    bfin_write32(DMA45_CURR_BWL_COUNT, val)
+#define bfin_read_DMA45_BWM_COUNT()             bfin_read32(DMA45_BWM_COUNT)
+#define bfin_write_DMA45_BWM_COUNT(val)         bfin_write32(DMA45_BWM_COUNT, val)
+#define bfin_read_DMA45_CURR_BWM_COUNT()        bfin_read32(DMA45_CURR_BWM_COUNT)
+#define bfin_write_DMA45_CURR_BWM_COUNT(val)    bfin_write32(DMA45_CURR_BWM_COUNT, val)
+/* DMA Channel 46 Registers */
+#define bfin_read_DMA46_NEXT_DESC_PTR()         bfin_read32(DMA46_NEXT_DESC_PTR)
+#define bfin_write_DMA46_NEXT_DESC_PTR(val)     bfin_write32(DMA46_NEXT_DESC_PTR, val)
+#define bfin_read_DMA46_START_ADDR()            bfin_read32(DMA46_START_ADDR)
+#define bfin_write_DMA46_START_ADDR(val)        bfin_write32(DMA46_START_ADDR, val)
+#define bfin_read_DMA46_CONFIG()                bfin_read32(DMA46_CONFIG)
+#define bfin_write_DMA46_CONFIG(val)            bfin_write32(DMA46_CONFIG, val)
+#define bfin_read_DMA46_X_COUNT()               bfin_read32(DMA46_X_COUNT)
+#define bfin_write_DMA46_X_COUNT(val)           bfin_write32(DMA46_X_COUNT, val)
+#define bfin_read_DMA46_X_MODIFY()              bfin_read32(DMA46_X_MODIFY)
+#define bfin_write_DMA46_X_MODIFY(val)          bfin_write32(DMA46_X_MODIFY, val)
+#define bfin_read_DMA46_Y_COUNT()               bfin_read32(DMA46_Y_COUNT)
+#define bfin_write_DMA46_Y_COUNT(val)           bfin_write32(DMA46_Y_COUNT, val)
+#define bfin_read_DMA46_Y_MODIFY()              bfin_read32(DMA46_Y_MODIFY)
+#define bfin_write_DMA46_Y_MODIFY(val)          bfin_write32(DMA46_Y_MODIFY, val)
+#define bfin_read_DMA46_CURR_DESC_PTR()         bfin_read32(DMA46_CURR_DESC_PTR)
+#define bfin_write_DMA46_CURR_DESC_PTR(val)     bfin_write32(DMA46_CURR_DESC_PTR, val)
+#define bfin_read_DMA46_PREV_DESC_PTR()         bfin_read32(DMA46_PREV_DESC_PTR)
+#define bfin_write_DMA46_PREV_DESC_PTR(val)     bfin_write32(DMA46_PREV_DESC_PTR, val)
+#define bfin_read_DMA46_CURR_ADDR()             bfin_read32(DMA46_CURR_ADDR)
+#define bfin_write_DMA46_CURR_ADDR(val)         bfin_write32(DMA46_CURR_ADDR, val)
+#define bfin_read_DMA46_IRQ_STATUS()            bfin_read32(DMA46_IRQ_STATUS)
+#define bfin_write_DMA46_IRQ_STATUS(val)        bfin_write32(DMA46_IRQ_STATUS, val)
+#define bfin_read_DMA46_CURR_X_COUNT()          bfin_read32(DMA46_CURR_X_COUNT)
+#define bfin_write_DMA46_CURR_X_COUNT(val)      bfin_write32(DMA46_CURR_X_COUNT, val)
+#define bfin_read_DMA46_CURR_Y_COUNT()          bfin_read32(DMA46_CURR_Y_COUNT)
+#define bfin_write_DMA46_CURR_Y_COUNT(val)      bfin_write32(DMA46_CURR_Y_COUNT, val)
+#define bfin_read_DMA46_BWL_COUNT()             bfin_read32(DMA46_BWL_COUNT)
+#define bfin_write_DMA46_BWL_COUNT(val)         bfin_write32(DMA46_BWL_COUNT, val)
+#define bfin_read_DMA46_CURR_BWL_COUNT()        bfin_read32(DMA46_CURR_BWL_COUNT)
+#define bfin_write_DMA46_CURR_BWL_COUNT(val)    bfin_write32(DMA46_CURR_BWL_COUNT, val)
+#define bfin_read_DMA46_BWM_COUNT()             bfin_read32(DMA46_BWM_COUNT)
+#define bfin_write_DMA46_BWM_COUNT(val)         bfin_write32(DMA46_BWM_COUNT, val)
+#define bfin_read_DMA46_CURR_BWM_COUNT()        bfin_read32(DMA46_CURR_BWM_COUNT)
+#define bfin_write_DMA46_CURR_BWM_COUNT(val)    bfin_write32(DMA46_CURR_BWM_COUNT, val)
+/* EPPI1 Registers */
+/* Port Interrubfin_read_()t 0 Registers (32-bit) */
+#define bfin_read_PINT0_MASK_SET()              bfin_read32(PINT0_MASK_SET)
+#define bfin_write_PINT0_MASK_SET(val)          bfin_write32(PINT0_MASK_SET, val)
+#define bfin_read_PINT0_MASK_CLEAR()            bfin_read32(PINT0_MASK_CLEAR)
+#define bfin_write_PINT0_MASK_CLEAR(val)        bfin_write32(PINT0_MASK_CLEAR, val)
+#define bfin_read_PINT0_REQUEST()               bfin_read32(PINT0_REQUEST)
+#define bfin_write_PINT0_REQUEST(val)           bfin_write32(PINT0_REQUEST, val)
+#define bfin_read_PINT0_ASSIGN()                bfin_read32(PINT0_ASSIGN)
+#define bfin_write_PINT0_ASSIGN(val)            bfin_write32(PINT0_ASSIGN, val)
+#define bfin_read_PINT0_EDGE_SET()              bfin_read32(PINT0_EDGE_SET)
+#define bfin_write_PINT0_EDGE_SET(val)          bfin_write32(PINT0_EDGE_SET, val)
+#define bfin_read_PINT0_EDGE_CLEAR()            bfin_read32(PINT0_EDGE_CLEAR)
+#define bfin_write_PINT0_EDGE_CLEAR(val)        bfin_write32(PINT0_EDGE_CLEAR, val)
+#define bfin_read_PINT0_INVERT_SET()            bfin_read32(PINT0_INVERT_SET)
+#define bfin_write_PINT0_INVERT_SET(val)        bfin_write32(PINT0_INVERT_SET, val)
+#define bfin_read_PINT0_INVERT_CLEAR()          bfin_read32(PINT0_INVERT_CLEAR)
+#define bfin_write_PINT0_INVERT_CLEAR(val)      bfin_write32(PINT0_INVERT_CLEAR, val)
+#define bfin_read_PINT0_PINSTATE()              bfin_read32(PINT0_PINSTATE)
+#define bfin_write_PINT0_PINSTATE(val)          bfin_write32(PINT0_PINSTATE, val)
+#define bfin_read_PINT0_LATCH()                 bfin_read32(PINT0_LATCH)
+#define bfin_write_PINT0_LATCH(val)             bfin_write32(PINT0_LATCH, val)
+/* Port Interrubfin_read_()t 1 Registers (32-bit) */
+#define bfin_read_PINT1_MASK_SET()              bfin_read32(PINT1_MASK_SET)
+#define bfin_write_PINT1_MASK_SET(val)          bfin_write32(PINT1_MASK_SET, val)
+#define bfin_read_PINT1_MASK_CLEAR()            bfin_read32(PINT1_MASK_CLEAR)
+#define bfin_write_PINT1_MASK_CLEAR(val)        bfin_write32(PINT1_MASK_CLEAR, val)
+#define bfin_read_PINT1_REQUEST()               bfin_read32(PINT1_REQUEST)
+#define bfin_write_PINT1_REQUEST(val)           bfin_write32(PINT1_REQUEST, val)
+#define bfin_read_PINT1_ASSIGN()                bfin_read32(PINT1_ASSIGN)
+#define bfin_write_PINT1_ASSIGN(val)            bfin_write32(PINT1_ASSIGN, val)
+#define bfin_read_PINT1_EDGE_SET()              bfin_read32(PINT1_EDGE_SET)
+#define bfin_write_PINT1_EDGE_SET(val)          bfin_write32(PINT1_EDGE_SET, val)
+#define bfin_read_PINT1_EDGE_CLEAR()            bfin_read32(PINT1_EDGE_CLEAR)
+#define bfin_write_PINT1_EDGE_CLEAR(val)        bfin_write32(PINT1_EDGE_CLEAR, val)
+#define bfin_read_PINT1_INVERT_SET()            bfin_read32(PINT1_INVERT_SET)
+#define bfin_write_PINT1_INVERT_SET(val)        bfin_write32(PINT1_INVERT_SET, val)
+#define bfin_read_PINT1_INVERT_CLEAR()          bfin_read32(PINT1_INVERT_CLEAR)
+#define bfin_write_PINT1_INVERT_CLEAR(val)      bfin_write32(PINT1_INVERT_CLEAR, val)
+#define bfin_read_PINT1_PINSTATE()              bfin_read32(PINT1_PINSTATE)
+#define bfin_write_PINT1_PINSTATE(val)          bfin_write32(PINT1_PINSTATE, val)
+#define bfin_read_PINT1_LATCH()                 bfin_read32(PINT1_LATCH)
+#define bfin_write_PINT1_LATCH(val)             bfin_write32(PINT1_LATCH, val)
+/* Port Interrubfin_read_()t 2 Registers (32-bit) */
+#define bfin_read_PINT2_MASK_SET()              bfin_read32(PINT2_MASK_SET)
+#define bfin_write_PINT2_MASK_SET(val)          bfin_write32(PINT2_MASK_SET, val)
+#define bfin_read_PINT2_MASK_CLEAR()            bfin_read32(PINT2_MASK_CLEAR)
+#define bfin_write_PINT2_MASK_CLEAR(val)        bfin_write32(PINT2_MASK_CLEAR, val)
+#define bfin_read_PINT2_REQUEST()               bfin_read32(PINT2_REQUEST)
+#define bfin_write_PINT2_REQUEST(val)           bfin_write32(PINT2_REQUEST, val)
+#define bfin_read_PINT2_ASSIGN()                bfin_read32(PINT2_ASSIGN)
+#define bfin_write_PINT2_ASSIGN(val)            bfin_write32(PINT2_ASSIGN, val)
+#define bfin_read_PINT2_EDGE_SET()              bfin_read32(PINT2_EDGE_SET)
+#define bfin_write_PINT2_EDGE_SET(val)          bfin_write32(PINT2_EDGE_SET, val)
+#define bfin_read_PINT2_EDGE_CLEAR()            bfin_read32(PINT2_EDGE_CLEAR)
+#define bfin_write_PINT2_EDGE_CLEAR(val)        bfin_write32(PINT2_EDGE_CLEAR, val)
+#define bfin_read_PINT2_INVERT_SET()            bfin_read32(PINT2_INVERT_SET)
+#define bfin_write_PINT2_INVERT_SET(val)        bfin_write32(PINT2_INVERT_SET, val)
+#define bfin_read_PINT2_INVERT_CLEAR()          bfin_read32(PINT2_INVERT_CLEAR)
+#define bfin_write_PINT2_INVERT_CLEAR(val)      bfin_write32(PINT2_INVERT_CLEAR, val)
+#define bfin_read_PINT2_PINSTATE()              bfin_read32(PINT2_PINSTATE)
+#define bfin_write_PINT2_PINSTATE(val)          bfin_write32(PINT2_PINSTATE, val)
+#define bfin_read_PINT2_LATCH()                 bfin_read32(PINT2_LATCH)
+#define bfin_write_PINT2_LATCH(val)             bfin_write32(PINT2_LATCH, val)
+/* Port Interrubfin_read_()t 3 Registers (32-bit) */
+#define bfin_read_PINT3_MASK_SET()              bfin_read32(PINT3_MASK_SET)
+#define bfin_write_PINT3_MASK_SET(val)          bfin_write32(PINT3_MASK_SET, val)
+#define bfin_read_PINT3_MASK_CLEAR()            bfin_read32(PINT3_MASK_CLEAR)
+#define bfin_write_PINT3_MASK_CLEAR(val)        bfin_write32(PINT3_MASK_CLEAR, val)
+#define bfin_read_PINT3_REQUEST()               bfin_read32(PINT3_REQUEST)
+#define bfin_write_PINT3_REQUEST(val)           bfin_write32(PINT3_REQUEST, val)
+#define bfin_read_PINT3_ASSIGN()                bfin_read32(PINT3_ASSIGN)
+#define bfin_write_PINT3_ASSIGN(val)            bfin_write32(PINT3_ASSIGN, val)
+#define bfin_read_PINT3_EDGE_SET()              bfin_read32(PINT3_EDGE_SET)
+#define bfin_write_PINT3_EDGE_SET(val)          bfin_write32(PINT3_EDGE_SET, val)
+#define bfin_read_PINT3_EDGE_CLEAR()            bfin_read32(PINT3_EDGE_CLEAR)
+#define bfin_write_PINT3_EDGE_CLEAR(val)        bfin_write32(PINT3_EDGE_CLEAR, val)
+#define bfin_read_PINT3_INVERT_SET()            bfin_read32(PINT3_INVERT_SET)
+#define bfin_write_PINT3_INVERT_SET(val)        bfin_write32(PINT3_INVERT_SET, val)
+#define bfin_read_PINT3_INVERT_CLEAR()          bfin_read32(PINT3_INVERT_CLEAR)
+#define bfin_write_PINT3_INVERT_CLEAR(val)      bfin_write32(PINT3_INVERT_CLEAR, val)
+#define bfin_read_PINT3_PINSTATE()              bfin_read32(PINT3_PINSTATE)
+#define bfin_write_PINT3_PINSTATE(val)          bfin_write32(PINT3_PINSTATE, val)
+#define bfin_read_PINT3_LATCH()                 bfin_read32(PINT3_LATCH)
+#define bfin_write_PINT3_LATCH(val)             bfin_write32(PINT3_LATCH, val)
+/* Port Interrubfin_read_()t 4 Registers (32-bit) */
+#define bfin_read_PINT4_MASK_SET()              bfin_read32(PINT4_MASK_SET)
+#define bfin_write_PINT4_MASK_SET(val)          bfin_write32(PINT4_MASK_SET, val)
+#define bfin_read_PINT4_MASK_CLEAR()            bfin_read32(PINT4_MASK_CLEAR)
+#define bfin_write_PINT4_MASK_CLEAR(val)        bfin_write32(PINT4_MASK_CLEAR, val)
+#define bfin_read_PINT4_REQUEST()               bfin_read32(PINT4_REQUEST)
+#define bfin_write_PINT4_REQUEST(val)           bfin_write32(PINT4_REQUEST, val)
+#define bfin_read_PINT4_ASSIGN()                bfin_read32(PINT4_ASSIGN)
+#define bfin_write_PINT4_ASSIGN(val)            bfin_write32(PINT4_ASSIGN, val)
+#define bfin_read_PINT4_EDGE_SET()              bfin_read32(PINT4_EDGE_SET)
+#define bfin_write_PINT4_EDGE_SET(val)          bfin_write32(PINT4_EDGE_SET, val)
+#define bfin_read_PINT4_EDGE_CLEAR()            bfin_read32(PINT4_EDGE_CLEAR)
+#define bfin_write_PINT4_EDGE_CLEAR(val)        bfin_write32(PINT4_EDGE_CLEAR, val)
+#define bfin_read_PINT4_INVERT_SET()            bfin_read32(PINT4_INVERT_SET)
+#define bfin_write_PINT4_INVERT_SET(val)        bfin_write32(PINT4_INVERT_SET, val)
+#define bfin_read_PINT4_INVERT_CLEAR()          bfin_read32(PINT4_INVERT_CLEAR)
+#define bfin_write_PINT4_INVERT_CLEAR(val)      bfin_write32(PINT4_INVERT_CLEAR, val)
+#define bfin_read_PINT4_PINSTATE()              bfin_read32(PINT4_PINSTATE)
+#define bfin_write_PINT4_PINSTATE(val)          bfin_write32(PINT4_PINSTATE, val)
+#define bfin_read_PINT4_LATCH()                 bfin_read32(PINT4_LATCH)
+#define bfin_write_PINT4_LATCH(val)             bfin_write32(PINT4_LATCH, val)
+/* Port Interrubfin_read_()t 5 Registers (32-bit) */
+#define bfin_read_PINT5_MASK_SET()              bfin_read32(PINT5_MASK_SET)
+#define bfin_write_PINT5_MASK_SET(val)          bfin_write32(PINT5_MASK_SET, val)
+#define bfin_read_PINT5_MASK_CLEAR()            bfin_read32(PINT5_MASK_CLEAR)
+#define bfin_write_PINT5_MASK_CLEAR(val)        bfin_write32(PINT5_MASK_CLEAR, val)
+#define bfin_read_PINT5_REQUEST()               bfin_read32(PINT5_REQUEST)
+#define bfin_write_PINT5_REQUEST(val)           bfin_write32(PINT5_REQUEST, val)
+#define bfin_read_PINT5_ASSIGN()                bfin_read32(PINT5_ASSIGN)
+#define bfin_write_PINT5_ASSIGN(val)            bfin_write32(PINT5_ASSIGN, val)
+#define bfin_read_PINT5_EDGE_SET()              bfin_read32(PINT5_EDGE_SET)
+#define bfin_write_PINT5_EDGE_SET(val)          bfin_write32(PINT5_EDGE_SET, val)
+#define bfin_read_PINT5_EDGE_CLEAR()            bfin_read32(PINT5_EDGE_CLEAR)
+#define bfin_write_PINT5_EDGE_CLEAR(val)        bfin_write32(PINT5_EDGE_CLEAR, val)
+#define bfin_read_PINT5_INVERT_SET()            bfin_read32(PINT5_INVERT_SET)
+#define bfin_write_PINT5_INVERT_SET(val)        bfin_write32(PINT5_INVERT_SET, val)
+#define bfin_read_PINT5_INVERT_CLEAR()          bfin_read32(PINT5_INVERT_CLEAR)
+#define bfin_write_PINT5_INVERT_CLEAR(val)      bfin_write32(PINT5_INVERT_CLEAR, val)
+#define bfin_read_PINT5_PINSTATE()              bfin_read32(PINT5_PINSTATE)
+#define bfin_write_PINT5_PINSTATE(val)          bfin_write32(PINT5_PINSTATE, val)
+#define bfin_read_PINT5_LATCH()                 bfin_read32(PINT5_LATCH)
+#define bfin_write_PINT5_LATCH(val)             bfin_write32(PINT5_LATCH, val)
+/* Port A Registers */
+#define bfin_read_PORTA_FER()           bfin_read32(PORTA_FER)
+#define bfin_write_PORTA_FER(val)       bfin_write32(PORTA_FER, val)
+#define bfin_read_PORTA_FER_SET()       bfin_read32(PORTA_FER_SET)
+#define bfin_write_PORTA_FER_SET(val)   bfin_write32(PORTA_FER_SET, val)
+#define bfin_read_PORTA_FER_CLEAR()     bfin_read32(PORTA_FER_CLEAR)
+#define bfin_write_PORTA_FER_CLEAR(val) bfin_write32(PORTA_FER_CLEAR, val)
+#define bfin_read_PORTA()               bfin_read32(PORTA)
+#define bfin_write_PORTA(val)           bfin_write32(PORTA, val)
+#define bfin_read_PORTA_SET()           bfin_read32(PORTA_SET)
+#define bfin_write_PORTA_SET(val)       bfin_write32(PORTA_SET, val)
+#define bfin_read_PORTA_CLEAR()         bfin_read32(PORTA_CLEAR)
+#define bfin_write_PORTA_CLEAR(val)     bfin_write32(PORTA_CLEAR, val)
+#define bfin_read_PORTA_DIR()           bfin_read32(PORTA_DIR)
+#define bfin_write_PORTA_DIR(val)       bfin_write32(PORTA_DIR, val)
+#define bfin_read_PORTA_DIR_SET()       bfin_read32(PORTA_DIR_SET)
+#define bfin_write_PORTA_DIR_SET(val)   bfin_write32(PORTA_DIR_SET, val)
+#define bfin_read_PORTA_DIR_CLEAR()     bfin_read32(PORTA_DIR_CLEAR)
+#define bfin_write_PORTA_DIR_CLEAR(val) bfin_write32(PORTA_DIR_CLEAR, val)
+#define bfin_read_PORTA_INEN()          bfin_read32(PORTA_INEN)
+#define bfin_write_PORTA_INEN(val)      bfin_write32(PORTA_INEN, val)
+#define bfin_read_PORTA_INEN_SET()      bfin_read32(PORTA_INEN_SET)
+#define bfin_write_PORTA_INEN_SET(val)  bfin_write32(PORTA_INEN_SET, val)
+#define bfin_read_PORTA_INEN_CLEAR()    bfin_read32(PORTA_INEN_CLEAR)
+#define bfin_write_PORTA_INEN_CLEAR(val)        bfin_write32(PORTA_INEN_CLEAR, val)
+#define bfin_read_PORTA_MUX()           bfin_read32(PORTA_MUX)
+#define bfin_write_PORTA_MUX(val)       bfin_write32(PORTA_MUX, val)
+#define bfin_read_PORTA_DATA_TGL()      bfin_read32(PORTA_DATA_TGL)
+#define bfin_write_PORTA_DATA_TGL(val)  bfin_write32(PORTA_DATA_TGL, val)
+#define bfin_read_PORTA_POL()           bfin_read32(PORTA_POL)
+#define bfin_write_PORTA_POL(val)       bfin_write32(PORTA_POL, val)
+#define bfin_read_PORTA_POL_SET()       bfin_read32(PORTA_POL_SET)
+#define bfin_write_PORTA_POL_SET(val)   bfin_write32(PORTA_POL_SET, val)
+#define bfin_read_PORTA_POL_CLEAR()     bfin_read32(PORTA_POL_CLEAR)
+#define bfin_write_PORTA_POL_CLEAR(val) bfin_write32(PORTA_POL_CLEAR, val)
+#define bfin_read_PORTA_LOCK()          bfin_read32(PORTA_LOCK)
+#define bfin_write_PORTA_LOCK(val)      bfin_write32(PORTA_LOCK, val)
+#define bfin_read_PORTA_REVID()         bfin_read32(PORTA_REVID)
+#define bfin_write_PORTA_REVID(val)     bfin_write32(PORTA_REVID, val)
+/* Port B Registers */
+#define bfin_read_PORTB_FER()           bfin_read32(PORTB_FER)
+#define bfin_write_PORTB_FER(val)       bfin_write32(PORTB_FER, val)
+#define bfin_read_PORTB_FER_SET()       bfin_read32(PORTB_FER_SET)
+#define bfin_write_PORTB_FER_SET(val)   bfin_write32(PORTB_FER_SET, val)
+#define bfin_read_PORTB_FER_CLEAR()     bfin_read32(PORTB_FER_CLEAR)
+#define bfin_write_PORTB_FER_CLEAR(val) bfin_write32(PORTB_FER_CLEAR, val)
+#define bfin_read_PORTB()               bfin_read32(PORTB)
+#define bfin_write_PORTB(val)           bfin_write32(PORTB, val)
+#define bfin_read_PORTB_SET()           bfin_read32(PORTB_SET)
+#define bfin_write_PORTB_SET(val)       bfin_write32(PORTB_SET, val)
+#define bfin_read_PORTB_CLEAR()         bfin_read32(PORTB_CLEAR)
+#define bfin_write_PORTB_CLEAR(val)     bfin_write32(PORTB_CLEAR, val)
+#define bfin_read_PORTB_DIR()           bfin_read32(PORTB_DIR)
+#define bfin_write_PORTB_DIR(val)       bfin_write32(PORTB_DIR, val)
+#define bfin_read_PORTB_DIR_SET()       bfin_read32(PORTB_DIR_SET)
+#define bfin_write_PORTB_DIR_SET(val)   bfin_write32(PORTB_DIR_SET, val)
+#define bfin_read_PORTB_DIR_CLEAR()     bfin_read32(PORTB_DIR_CLEAR)
+#define bfin_write_PORTB_DIR_CLEAR(val) bfin_write32(PORTB_DIR_CLEAR, val)
+#define bfin_read_PORTB_INEN()          bfin_read32(PORTB_INEN)
+#define bfin_write_PORTB_INEN(val)      bfin_write32(PORTB_INEN, val)
+#define bfin_read_PORTB_INEN_SET()      bfin_read32(PORTB_INEN_SET)
+#define bfin_write_PORTB_INEN_SET(val)  bfin_write32(PORTB_INEN_SET, val)
+#define bfin_read_PORTB_INEN_CLEAR()    bfin_read32(PORTB_INEN_CLEAR)
+#define bfin_write_PORTB_INEN_CLEAR(val)        bfin_write32(PORTB_INEN_CLEAR, val)
+#define bfin_read_PORTB_MUX()           bfin_read32(PORTB_MUX)
+#define bfin_write_PORTB_MUX(val)       bfin_write32(PORTB_MUX, val)
+#define bfin_read_PORTB_DATA_TGL()      bfin_read32(PORTB_DATA_TGL)
+#define bfin_write_PORTB_DATA_TGL(val)  bfin_write32(PORTB_DATA_TGL, val)
+#define bfin_read_PORTB_POL()           bfin_read32(PORTB_POL)
+#define bfin_write_PORTB_POL(val)       bfin_write32(PORTB_POL, val)
+#define bfin_read_PORTB_POL_SET()       bfin_read32(PORTB_POL_SET)
+#define bfin_write_PORTB_POL_SET(val)   bfin_write32(PORTB_POL_SET, val)
+#define bfin_read_PORTB_POL_CLEAR()     bfin_read32(PORTB_POL_CLEAR)
+#define bfin_write_PORTB_POL_CLEAR(val) bfin_write32(PORTB_POL_CLEAR, val)
+#define bfin_read_PORTB_LOCK()          bfin_read32(PORTB_LOCK)
+#define bfin_write_PORTB_LOCK(val)      bfin_write32(PORTB_LOCK, val)
+#define bfin_read_PORTB_REVID()         bfin_read32(PORTB_REVID)
+#define bfin_write_PORTB_REVID(val)     bfin_write32(PORTB_REVID, val)
+/* Port C Registers */
+#define bfin_read_PORTC_FER()           bfin_read32(PORTC_FER)
+#define bfin_write_PORTC_FER(val)       bfin_write32(PORTC_FER, val)
+#define bfin_read_PORTC_FER_SET()       bfin_read32(PORTC_FER_SET)
+#define bfin_write_PORTC_FER_SET(val)   bfin_write32(PORTC_FER_SET, val)
+#define bfin_read_PORTC_FER_CLEAR()     bfin_read32(PORTC_FER_CLEAR)
+#define bfin_write_PORTC_FER_CLEAR(val) bfin_write32(PORTC_FER_CLEAR, val)
+#define bfin_read_PORTC()               bfin_read32(PORTC)
+#define bfin_write_PORTC(val)           bfin_write32(PORTC, val)
+#define bfin_read_PORTC_SET()           bfin_read32(PORTC_SET)
+#define bfin_write_PORTC_SET(val)       bfin_write32(PORTC_SET, val)
+#define bfin_read_PORTC_CLEAR()         bfin_read32(PORTC_CLEAR)
+#define bfin_write_PORTC_CLEAR(val)     bfin_write32(PORTC_CLEAR, val)
+#define bfin_read_PORTC_DIR()           bfin_read32(PORTC_DIR)
+#define bfin_write_PORTC_DIR(val)       bfin_write32(PORTC_DIR, val)
+#define bfin_read_PORTC_DIR_SET()       bfin_read32(PORTC_DIR_SET)
+#define bfin_write_PORTC_DIR_SET(val)   bfin_write32(PORTC_DIR_SET, val)
+#define bfin_read_PORTC_DIR_CLEAR()     bfin_read32(PORTC_DIR_CLEAR)
+#define bfin_write_PORTC_DIR_CLEAR(val) bfin_write32(PORTC_DIR_CLEAR, val)
+#define bfin_read_PORTC_INEN()          bfin_read32(PORTC_INEN)
+#define bfin_write_PORTC_INEN(val)      bfin_write32(PORTC_INEN, val)
+#define bfin_read_PORTC_INEN_SET()      bfin_read32(PORTC_INEN_SET)
+#define bfin_write_PORTC_INEN_SET(val)  bfin_write32(PORTC_INEN_SET, val)
+#define bfin_read_PORTC_INEN_CLEAR()    bfin_read32(PORTC_INEN_CLEAR)
+#define bfin_write_PORTC_INEN_CLEAR(val)        bfin_write32(PORTC_INEN_CLEAR, val)
+#define bfin_read_PORTC_MUX()           bfin_read32(PORTC_MUX)
+#define bfin_write_PORTC_MUX(val)       bfin_write32(PORTC_MUX, val)
+#define bfin_read_PORTC_DATA_TGL()      bfin_read32(PORTC_DATA_TGL)
+#define bfin_write_PORTC_DATA_TGL(val)  bfin_write32(PORTC_DATA_TGL, val)
+#define bfin_read_PORTC_POL()           bfin_read32(PORTC_POL)
+#define bfin_write_PORTC_POL(val)       bfin_write32(PORTC_POL, val)
+#define bfin_read_PORTC_POL_SET()       bfin_read32(PORTC_POL_SET)
+#define bfin_write_PORTC_POL_SET(val)   bfin_write32(PORTC_POL_SET, val)
+#define bfin_read_PORTC_POL_CLEAR()     bfin_read32(PORTC_POL_CLEAR)
+#define bfin_write_PORTC_POL_CLEAR(val) bfin_write32(PORTC_POL_CLEAR, val)
+#define bfin_read_PORTC_LOCK()          bfin_read32(PORTC_LOCK)
+#define bfin_write_PORTC_LOCK(val)      bfin_write32(PORTC_LOCK, val)
+#define bfin_read_PORTC_REVID()         bfin_read32(PORTC_REVID)
+#define bfin_write_PORTC_REVID(val)     bfin_write32(PORTC_REVID, val)
+/* Port D Registers */
+#define bfin_read_PORTD_FER()           bfin_read32(PORTD_FER)
+#define bfin_write_PORTD_FER(val)       bfin_write32(PORTD_FER, val)
+#define bfin_read_PORTD_FER_SET()       bfin_read32(PORTD_FER_SET)
+#define bfin_write_PORTD_FER_SET(val)   bfin_write32(PORTD_FER_SET, val)
+#define bfin_read_PORTD_FER_CLEAR()     bfin_read32(PORTD_FER_CLEAR)
+#define bfin_write_PORTD_FER_CLEAR(val) bfin_write32(PORTD_FER_CLEAR, val)
+#define bfin_read_PORTD()               bfin_read32(PORTD)
+#define bfin_write_PORTD(val)           bfin_write32(PORTD, val)
+#define bfin_read_PORTD_SET()           bfin_read32(PORTD_SET)
+#define bfin_write_PORTD_SET(val)       bfin_write32(PORTD_SET, val)
+#define bfin_read_PORTD_CLEAR()         bfin_read32(PORTD_CLEAR)
+#define bfin_write_PORTD_CLEAR(val)     bfin_write32(PORTD_CLEAR, val)
+#define bfin_read_PORTD_DIR()           bfin_read32(PORTD_DIR)
+#define bfin_write_PORTD_DIR(val)       bfin_write32(PORTD_DIR, val)
+#define bfin_read_PORTD_DIR_SET()       bfin_read32(PORTD_DIR_SET)
+#define bfin_write_PORTD_DIR_SET(val)   bfin_write32(PORTD_DIR_SET, val)
+#define bfin_read_PORTD_DIR_CLEAR()     bfin_read32(PORTD_DIR_CLEAR)
+#define bfin_write_PORTD_DIR_CLEAR(val) bfin_write32(PORTD_DIR_CLEAR, val)
+#define bfin_read_PORTD_INEN()          bfin_read32(PORTD_INEN)
+#define bfin_write_PORTD_INEN(val)      bfin_write32(PORTD_INEN, val)
+#define bfin_read_PORTD_INEN_SET()      bfin_read32(PORTD_INEN_SET)
+#define bfin_write_PORTD_INEN_SET(val)  bfin_write32(PORTD_INEN_SET, val)
+#define bfin_read_PORTD_INEN_CLEAR()    bfin_read32(PORTD_INEN_CLEAR)
+#define bfin_write_PORTD_INEN_CLEAR(val)        bfin_write32(PORTD_INEN_CLEAR, val)
+#define bfin_read_PORTD_MUX()           bfin_read32(PORTD_MUX)
+#define bfin_write_PORTD_MUX(val)       bfin_write32(PORTD_MUX, val)
+#define bfin_read_PORTD_DATA_TGL()      bfin_read32(PORTD_DATA_TGL)
+#define bfin_write_PORTD_DATA_TGL(val)  bfin_write32(PORTD_DATA_TGL, val)
+#define bfin_read_PORTD_POL()           bfin_read32(PORTD_POL)
+#define bfin_write_PORTD_POL(val)       bfin_write32(PORTD_POL, val)
+#define bfin_read_PORTD_POL_SET()       bfin_read32(PORTD_POL_SET)
+#define bfin_write_PORTD_POL_SET(val)   bfin_write32(PORTD_POL_SET, val)
+#define bfin_read_PORTD_POL_CLEAR()     bfin_read32(PORTD_POL_CLEAR)
+#define bfin_write_PORTD_POL_CLEAR(val) bfin_write32(PORTD_POL_CLEAR, val)
+#define bfin_read_PORTD_LOCK()          bfin_read32(PORTD_LOCK)
+#define bfin_write_PORTD_LOCK(val)      bfin_write32(PORTD_LOCK, val)
+#define bfin_read_PORTD_REVID()         bfin_read32(PORTD_REVID)
+#define bfin_write_PORTD_REVID(val)     bfin_write32(PORTD_REVID, val)
+/* Port E Registers */
+#define bfin_read_PORTE_FER()           bfin_read32(PORTE_FER)
+#define bfin_write_PORTE_FER(val)       bfin_write32(PORTE_FER, val)
+#define bfin_read_PORTE_FER_SET()       bfin_read32(PORTE_FER_SET)
+#define bfin_write_PORTE_FER_SET(val)   bfin_write32(PORTE_FER_SET, val)
+#define bfin_read_PORTE_FER_CLEAR()     bfin_read32(PORTE_FER_CLEAR)
+#define bfin_write_PORTE_FER_CLEAR(val) bfin_write32(PORTE_FER_CLEAR, val)
+#define bfin_read_PORTE()               bfin_read32(PORTE)
+#define bfin_write_PORTE(val)           bfin_write32(PORTE, val)
+#define bfin_read_PORTE_SET()           bfin_read32(PORTE_SET)
+#define bfin_write_PORTE_SET(val)       bfin_write32(PORTE_SET, val)
+#define bfin_read_PORTE_CLEAR()         bfin_read32(PORTE_CLEAR)
+#define bfin_write_PORTE_CLEAR(val)     bfin_write32(PORTE_CLEAR, val)
+#define bfin_read_PORTE_DIR()           bfin_read32(PORTE_DIR)
+#define bfin_write_PORTE_DIR(val)       bfin_write32(PORTE_DIR, val)
+#define bfin_read_PORTE_DIR_SET()       bfin_read32(PORTE_DIR_SET)
+#define bfin_write_PORTE_DIR_SET(val)   bfin_write32(PORTE_DIR_SET, val)
+#define bfin_read_PORTE_DIR_CLEAR()     bfin_read32(PORTE_DIR_CLEAR)
+#define bfin_write_PORTE_DIR_CLEAR(val) bfin_write32(PORTE_DIR_CLEAR, val)
+#define bfin_read_PORTE_INEN()          bfin_read32(PORTE_INEN)
+#define bfin_write_PORTE_INEN(val)      bfin_write32(PORTE_INEN, val)
+#define bfin_read_PORTE_INEN_SET()      bfin_read32(PORTE_INEN_SET)
+#define bfin_write_PORTE_INEN_SET(val)  bfin_write32(PORTE_INEN_SET, val)
+#define bfin_read_PORTE_INEN_CLEAR()    bfin_read32(PORTE_INEN_CLEAR)
+#define bfin_write_PORTE_INEN_CLEAR(val)        bfin_write32(PORTE_INEN_CLEAR, val)
+#define bfin_read_PORTE_MUX()           bfin_read32(PORTE_MUX)
+#define bfin_write_PORTE_MUX(val)       bfin_write32(PORTE_MUX, val)
+#define bfin_read_PORTE_DATA_TGL()      bfin_read32(PORTE_DATA_TGL)
+#define bfin_write_PORTE_DATA_TGL(val)  bfin_write32(PORTE_DATA_TGL, val)
+#define bfin_read_PORTE_POL()           bfin_read32(PORTE_POL)
+#define bfin_write_PORTE_POL(val)       bfin_write32(PORTE_POL, val)
+#define bfin_read_PORTE_POL_SET()       bfin_read32(PORTE_POL_SET)
+#define bfin_write_PORTE_POL_SET(val)   bfin_write32(PORTE_POL_SET, val)
+#define bfin_read_PORTE_POL_CLEAR()     bfin_read32(PORTE_POL_CLEAR)
+#define bfin_write_PORTE_POL_CLEAR(val) bfin_write32(PORTE_POL_CLEAR, val)
+#define bfin_read_PORTE_LOCK()          bfin_read32(PORTE_LOCK)
+#define bfin_write_PORTE_LOCK(val)      bfin_write32(PORTE_LOCK, val)
+#define bfin_read_PORTE_REVID()         bfin_read32(PORTE_REVID)
+#define bfin_write_PORTE_REVID(val)     bfin_write32(PORTE_REVID, val)
+/* Port F Registers */
+#define bfin_read_PORTF_FER()           bfin_read32(PORTF_FER)
+#define bfin_write_PORTF_FER(val)       bfin_write32(PORTF_FER, val)
+#define bfin_read_PORTF_FER_SET()       bfin_read32(PORTF_FER_SET)
+#define bfin_write_PORTF_FER_SET(val)   bfin_write32(PORTF_FER_SET, val)
+#define bfin_read_PORTF_FER_CLEAR()     bfin_read32(PORTF_FER_CLEAR)
+#define bfin_write_PORTF_FER_CLEAR(val) bfin_write32(PORTF_FER_CLEAR, val)
+#define bfin_read_PORTF()               bfin_read32(PORTF)
+#define bfin_write_PORTF(val)           bfin_write32(PORTF, val)
+#define bfin_read_PORTF_SET()           bfin_read32(PORTF_SET)
+#define bfin_write_PORTF_SET(val)       bfin_write32(PORTF_SET, val)
+#define bfin_read_PORTF_CLEAR()         bfin_read32(PORTF_CLEAR)
+#define bfin_write_PORTF_CLEAR(val)     bfin_write32(PORTF_CLEAR, val)
+#define bfin_read_PORTF_DIR()           bfin_read32(PORTF_DIR)
+#define bfin_write_PORTF_DIR(val)       bfin_write32(PORTF_DIR, val)
+#define bfin_read_PORTF_DIR_SET()       bfin_read32(PORTF_DIR_SET)
+#define bfin_write_PORTF_DIR_SET(val)   bfin_write32(PORTF_DIR_SET, val)
+#define bfin_read_PORTF_DIR_CLEAR()     bfin_read32(PORTF_DIR_CLEAR)
+#define bfin_write_PORTF_DIR_CLEAR(val) bfin_write32(PORTF_DIR_CLEAR, val)
+#define bfin_read_PORTF_INEN()          bfin_read32(PORTF_INEN)
+#define bfin_write_PORTF_INEN(val)      bfin_write32(PORTF_INEN, val)
+#define bfin_read_PORTF_INEN_SET()      bfin_read32(PORTF_INEN_SET)
+#define bfin_write_PORTF_INEN_SET(val)  bfin_write32(PORTF_INEN_SET, val)
+#define bfin_read_PORTF_INEN_CLEAR()    bfin_read32(PORTF_INEN_CLEAR)
+#define bfin_write_PORTF_INEN_CLEAR(val)        bfin_write32(PORTF_INEN_CLEAR, val)
+#define bfin_read_PORTF_MUX()           bfin_read32(PORTF_MUX)
+#define bfin_write_PORTF_MUX(val)       bfin_write32(PORTF_MUX, val)
+#define bfin_read_PORTF_DATA_TGL()      bfin_read32(PORTF_DATA_TGL)
+#define bfin_write_PORTF_DATA_TGL(val)  bfin_write32(PORTF_DATA_TGL, val)
+#define bfin_read_PORTF_POL()           bfin_read32(PORTF_POL)
+#define bfin_write_PORTF_POL(val)       bfin_write32(PORTF_POL, val)
+#define bfin_read_PORTF_POL_SET()       bfin_read32(PORTF_POL_SET)
+#define bfin_write_PORTF_POL_SET(val)   bfin_write32(PORTF_POL_SET, val)
+#define bfin_read_PORTF_POL_CLEAR()     bfin_read32(PORTF_POL_CLEAR)
+#define bfin_write_PORTF_POL_CLEAR(val) bfin_write32(PORTF_POL_CLEAR, val)
+#define bfin_read_PORTF_LOCK()          bfin_read32(PORTF_LOCK)
+#define bfin_write_PORTF_LOCK(val)      bfin_write32(PORTF_LOCK, val)
+#define bfin_read_PORTF_REVID()         bfin_read32(PORTF_REVID)
+#define bfin_write_PORTF_REVID(val)     bfin_write32(PORTF_REVID, val)
+/* Port G Registers */
+#define bfin_read_PORTG_FER()           bfin_read32(PORTG_FER)
+#define bfin_write_PORTG_FER(val)       bfin_write32(PORTG_FER, val)
+#define bfin_read_PORTG_FER_SET()       bfin_read32(PORTG_FER_SET)
+#define bfin_write_PORTG_FER_SET(val)   bfin_write32(PORTG_FER_SET, val)
+#define bfin_read_PORTG_FER_CLEAR()     bfin_read32(PORTG_FER_CLEAR)
+#define bfin_write_PORTG_FER_CLEAR(val) bfin_write32(PORTG_FER_CLEAR, val)
+#define bfin_read_PORTG()               bfin_read32(PORTG)
+#define bfin_write_PORTG(val)           bfin_write32(PORTG, val)
+#define bfin_read_PORTG_SET()           bfin_read32(PORTG_SET)
+#define bfin_write_PORTG_SET(val)       bfin_write32(PORTG_SET, val)
+#define bfin_read_PORTG_CLEAR()         bfin_read32(PORTG_CLEAR)
+#define bfin_write_PORTG_CLEAR(val)     bfin_write32(PORTG_CLEAR, val)
+#define bfin_read_PORTG_DIR()           bfin_read32(PORTG_DIR)
+#define bfin_write_PORTG_DIR(val)       bfin_write32(PORTG_DIR, val)
+#define bfin_read_PORTG_DIR_SET()       bfin_read32(PORTG_DIR_SET)
+#define bfin_write_PORTG_DIR_SET(val)   bfin_write32(PORTG_DIR_SET, val)
+#define bfin_read_PORTG_DIR_CLEAR()     bfin_read32(PORTG_DIR_CLEAR)
+#define bfin_write_PORTG_DIR_CLEAR(val) bfin_write32(PORTG_DIR_CLEAR, val)
+#define bfin_read_PORTG_INEN()          bfin_read32(PORTG_INEN)
+#define bfin_write_PORTG_INEN(val)      bfin_write32(PORTG_INEN, val)
+#define bfin_read_PORTG_INEN_SET()      bfin_read32(PORTG_INEN_SET)
+#define bfin_write_PORTG_INEN_SET(val)  bfin_write32(PORTG_INEN_SET, val)
+#define bfin_read_PORTG_INEN_CLEAR()    bfin_read32(PORTG_INEN_CLEAR)
+#define bfin_write_PORTG_INEN_CLEAR(val)        bfin_write32(PORTG_INEN_CLEAR, val)
+#define bfin_read_PORTG_MUX()           bfin_read32(PORTG_MUX)
+#define bfin_write_PORTG_MUX(val)       bfin_write32(PORTG_MUX, val)
+#define bfin_read_PORTG_DATA_TGL()      bfin_read32(PORTG_DATA_TGL)
+#define bfin_write_PORTG_DATA_TGL(val)  bfin_write32(PORTG_DATA_TGL, val)
+#define bfin_read_PORTG_POL()           bfin_read32(PORTG_POL)
+#define bfin_write_PORTG_POL(val)       bfin_write32(PORTG_POL, val)
+#define bfin_read_PORTG_POL_SET()       bfin_read32(PORTG_POL_SET)
+#define bfin_write_PORTG_POL_SET(val)   bfin_write32(PORTG_POL_SET, val)
+#define bfin_read_PORTG_POL_CLEAR()     bfin_read32(PORTG_POL_CLEAR)
+#define bfin_write_PORTG_POL_CLEAR(val) bfin_write32(PORTG_POL_CLEAR, val)
+#define bfin_read_PORTG_LOCK()          bfin_read32(PORTG_LOCK)
+#define bfin_write_PORTG_LOCK(val)      bfin_write32(PORTG_LOCK, val)
+#define bfin_read_PORTG_REVID()         bfin_read32(PORTG_REVID)
+#define bfin_write_PORTG_REVID(val)     bfin_write32(PORTG_REVID, val)
+/* CAN Controller 0 Config 1 Registers */
+#define bfin_read_CAN0_MC1()            bfin_read16(CAN0_MC1)
+#define bfin_write_CAN0_MC1(val)        bfin_write16(CAN0_MC1, val)
+#define bfin_read_CAN0_MD1()            bfin_read16(CAN0_MD1)
+#define bfin_write_CAN0_MD1(val)        bfin_write16(CAN0_MD1, val)
+#define bfin_read_CAN0_TRS1()           bfin_read16(CAN0_TRS1)
+#define bfin_write_CAN0_TRS1(val)       bfin_write16(CAN0_TRS1, val)
+#define bfin_read_CAN0_TRR1()           bfin_read16(CAN0_TRR1)
+#define bfin_write_CAN0_TRR1(val)       bfin_write16(CAN0_TRR1, val)
+#define bfin_read_CAN0_TA1()            bfin_read16(CAN0_TA1)
+#define bfin_write_CAN0_TA1(val)        bfin_write16(CAN0_TA1, val)
+#define bfin_read_CAN0_AA1()            bfin_read16(CAN0_AA1)
+#define bfin_write_CAN0_AA1(val)        bfin_write16(CAN0_AA1, val)
+#define bfin_read_CAN0_RMP1()           bfin_read16(CAN0_RMP1)
+#define bfin_write_CAN0_RMP1(val)       bfin_write16(CAN0_RMP1, val)
+#define bfin_read_CAN0_RML1()           bfin_read16(CAN0_RML1)
+#define bfin_write_CAN0_RML1(val)       bfin_write16(CAN0_RML1, val)
+#define bfin_read_CAN0_MBTIF1()         bfin_read16(CAN0_MBTIF1)
+#define bfin_write_CAN0_MBTIF1(val)     bfin_write16(CAN0_MBTIF1, val)
+#define bfin_read_CAN0_MBRIF1()         bfin_read16(CAN0_MBRIF1)
+#define bfin_write_CAN0_MBRIF1(val)     bfin_write16(CAN0_MBRIF1, val)
+#define bfin_read_CAN0_MBIM1()          bfin_read16(CAN0_MBIM1)
+#define bfin_write_CAN0_MBIM1(val)      bfin_write16(CAN0_MBIM1, val)
+#define bfin_read_CAN0_RFH1()           bfin_read16(CAN0_RFH1)
+#define bfin_write_CAN0_RFH1(val)       bfin_write16(CAN0_RFH1, val)
+#define bfin_read_CAN0_OPSS1()          bfin_read16(CAN0_OPSS1)
+#define bfin_write_CAN0_OPSS1(val)      bfin_write16(CAN0_OPSS1, val)
+/* CAN Controller 0 Config 2 Registers */
+#define bfin_read_CAN0_MC2()            bfin_read16(CAN0_MC2)
+#define bfin_write_CAN0_MC2(val)        bfin_write16(CAN0_MC2, val)
+#define bfin_read_CAN0_MD2()            bfin_read16(CAN0_MD2)
+#define bfin_write_CAN0_MD2(val)        bfin_write16(CAN0_MD2, val)
+#define bfin_read_CAN0_TRS2()           bfin_read16(CAN0_TRS2)
+#define bfin_write_CAN0_TRS2(val)       bfin_write16(CAN0_TRS2, val)
+#define bfin_read_CAN0_TRR2()           bfin_read16(CAN0_TRR2)
+#define bfin_write_CAN0_TRR2(val)       bfin_write16(CAN0_TRR2, val)
+#define bfin_read_CAN0_TA2()            bfin_read16(CAN0_TA2)
+#define bfin_write_CAN0_TA2(val)        bfin_write16(CAN0_TA2, val)
+#define bfin_read_CAN0_AA2()            bfin_read16(CAN0_AA2)
+#define bfin_write_CAN0_AA2(val)        bfin_write16(CAN0_AA2, val)
+#define bfin_read_CAN0_RMP2()           bfin_read16(CAN0_RMP2)
+#define bfin_write_CAN0_RMP2(val)       bfin_write16(CAN0_RMP2, val)
+#define bfin_read_CAN0_RML2()           bfin_read16(CAN0_RML2)
+#define bfin_write_CAN0_RML2(val)       bfin_write16(CAN0_RML2, val)
+#define bfin_read_CAN0_MBTIF2()         bfin_read16(CAN0_MBTIF2)
+#define bfin_write_CAN0_MBTIF2(val)     bfin_write16(CAN0_MBTIF2, val)
+#define bfin_read_CAN0_MBRIF2()         bfin_read16(CAN0_MBRIF2)
+#define bfin_write_CAN0_MBRIF2(val)     bfin_write16(CAN0_MBRIF2, val)
+#define bfin_read_CAN0_MBIM2()          bfin_read16(CAN0_MBIM2)
+#define bfin_write_CAN0_MBIM2(val)      bfin_write16(CAN0_MBIM2, val)
+#define bfin_read_CAN0_RFH2()           bfin_read16(CAN0_RFH2)
+#define bfin_write_CAN0_RFH2(val)       bfin_write16(CAN0_RFH2, val)
+#define bfin_read_CAN0_OPSS2()          bfin_read16(CAN0_OPSS2)
+#define bfin_write_CAN0_OPSS2(val)      bfin_write16(CAN0_OPSS2, val)
+/* CAN Controller 0 Clock/Interrubfin_read_()t/Counter Registers */
+#define bfin_read_CAN0_CLOCK()          bfin_read16(CAN0_CLOCK)
+#define bfin_write_CAN0_CLOCK(val)      bfin_write16(CAN0_CLOCK, val)
+#define bfin_read_CAN0_TIMING()         bfin_read16(CAN0_TIMING)
+#define bfin_write_CAN0_TIMING(val)     bfin_write16(CAN0_TIMING, val)
+#define bfin_read_CAN0_DEBUG()          bfin_read16(CAN0_DEBUG)
+#define bfin_write_CAN0_DEBUG(val)      bfin_write16(CAN0_DEBUG, val)
+#define bfin_read_CAN0_STATUS()         bfin_read16(CAN0_STATUS)
+#define bfin_write_CAN0_STATUS(val)     bfin_write16(CAN0_STATUS, val)
+#define bfin_read_CAN0_CEC()            bfin_read16(CAN0_CEC)
+#define bfin_write_CAN0_CEC(val)        bfin_write16(CAN0_CEC, val)
+#define bfin_read_CAN0_GIS()            bfin_read16(CAN0_GIS)
+#define bfin_write_CAN0_GIS(val)        bfin_write16(CAN0_GIS, val)
+#define bfin_read_CAN0_GIM()            bfin_read16(CAN0_GIM)
+#define bfin_write_CAN0_GIM(val)        bfin_write16(CAN0_GIM, val)
+#define bfin_read_CAN0_GIF()            bfin_read16(CAN0_GIF)
+#define bfin_write_CAN0_GIF(val)        bfin_write16(CAN0_GIF, val)
+#define bfin_read_CAN0_CONTROL()        bfin_read16(CAN0_CONTROL)
+#define bfin_write_CAN0_CONTROL(val)    bfin_write16(CAN0_CONTROL, val)
+#define bfin_read_CAN0_INTR()           bfin_read16(CAN0_INTR)
+#define bfin_write_CAN0_INTR(val)       bfin_write16(CAN0_INTR, val)
+#define bfin_read_CAN0_MBTD()           bfin_read16(CAN0_MBTD)
+#define bfin_write_CAN0_MBTD(val)       bfin_write16(CAN0_MBTD, val)
+#define bfin_read_CAN0_EWR()            bfin_read16(CAN0_EWR)
+#define bfin_write_CAN0_EWR(val)        bfin_write16(CAN0_EWR, val)
+#define bfin_read_CAN0_ESR()            bfin_read16(CAN0_ESR)
+#define bfin_write_CAN0_ESR(val)        bfin_write16(CAN0_ESR, val)
+#define bfin_read_CAN0_UCCNT()          bfin_read16(CAN0_UCCNT)
+#define bfin_write_CAN0_UCCNT(val)      bfin_write16(CAN0_UCCNT, val)
+#define bfin_read_CAN0_UCRC()           bfin_read16(CAN0_UCRC)
+#define bfin_write_CAN0_UCRC(val)       bfin_write16(CAN0_UCRC, val)
+#define bfin_read_CAN0_UCCNF()          bfin_read16(CAN0_UCCNF)
+#define bfin_write_CAN0_UCCNF(val)      bfin_write16(CAN0_UCCNF, val)
+/* CAN Controller 0 Accebfin_read_()tance Registers */
+#define bfin_read_CAN0_AM00L()          bfin_read16(CAN0_AM00L)
+#define bfin_write_CAN0_AM00L(val)      bfin_write16(CAN0_AM00L, val)
+#define bfin_read_CAN0_AM00H()          bfin_read16(CAN0_AM00H)
+#define bfin_write_CAN0_AM00H(val)      bfin_write16(CAN0_AM00H, val)
+#define bfin_read_CAN0_AM01L()          bfin_read16(CAN0_AM01L)
+#define bfin_write_CAN0_AM01L(val)      bfin_write16(CAN0_AM01L, val)
+#define bfin_read_CAN0_AM01H()          bfin_read16(CAN0_AM01H)
+#define bfin_write_CAN0_AM01H(val)      bfin_write16(CAN0_AM01H, val)
+#define bfin_read_CAN0_AM02L()          bfin_read16(CAN0_AM02L)
+#define bfin_write_CAN0_AM02L(val)      bfin_write16(CAN0_AM02L, val)
+#define bfin_read_CAN0_AM02H()          bfin_read16(CAN0_AM02H)
+#define bfin_write_CAN0_AM02H(val)      bfin_write16(CAN0_AM02H, val)
+#define bfin_read_CAN0_AM03L()          bfin_read16(CAN0_AM03L)
+#define bfin_write_CAN0_AM03L(val)      bfin_write16(CAN0_AM03L, val)
+#define bfin_read_CAN0_AM03H()          bfin_read16(CAN0_AM03H)
+#define bfin_write_CAN0_AM03H(val)      bfin_write16(CAN0_AM03H, val)
+#define bfin_read_CAN0_AM04L()          bfin_read16(CAN0_AM04L)
+#define bfin_write_CAN0_AM04L(val)      bfin_write16(CAN0_AM04L, val)
+#define bfin_read_CAN0_AM04H()          bfin_read16(CAN0_AM04H)
+#define bfin_write_CAN0_AM04H(val)      bfin_write16(CAN0_AM04H, val)
+#define bfin_read_CAN0_AM05L()          bfin_read16(CAN0_AM05L)
+#define bfin_write_CAN0_AM05L(val)      bfin_write16(CAN0_AM05L, val)
+#define bfin_read_CAN0_AM05H()          bfin_read16(CAN0_AM05H)
+#define bfin_write_CAN0_AM05H(val)      bfin_write16(CAN0_AM05H, val)
+#define bfin_read_CAN0_AM06L()          bfin_read16(CAN0_AM06L)
+#define bfin_write_CAN0_AM06L(val)      bfin_write16(CAN0_AM06L, val)
+#define bfin_read_CAN0_AM06H()          bfin_read16(CAN0_AM06H)
+#define bfin_write_CAN0_AM06H(val)      bfin_write16(CAN0_AM06H, val)
+#define bfin_read_CAN0_AM07L()          bfin_read16(CAN0_AM07L)
+#define bfin_write_CAN0_AM07L(val)      bfin_write16(CAN0_AM07L, val)
+#define bfin_read_CAN0_AM07H()          bfin_read16(CAN0_AM07H)
+#define bfin_write_CAN0_AM07H(val)      bfin_write16(CAN0_AM07H, val)
+#define bfin_read_CAN0_AM08L()          bfin_read16(CAN0_AM08L)
+#define bfin_write_CAN0_AM08L(val)      bfin_write16(CAN0_AM08L, val)
+#define bfin_read_CAN0_AM08H()          bfin_read16(CAN0_AM08H)
+#define bfin_write_CAN0_AM08H(val)      bfin_write16(CAN0_AM08H, val)
+#define bfin_read_CAN0_AM09L()          bfin_read16(CAN0_AM09L)
+#define bfin_write_CAN0_AM09L(val)      bfin_write16(CAN0_AM09L, val)
+#define bfin_read_CAN0_AM09H()          bfin_read16(CAN0_AM09H)
+#define bfin_write_CAN0_AM09H(val)      bfin_write16(CAN0_AM09H, val)
+#define bfin_read_CAN0_AM10L()          bfin_read16(CAN0_AM10L)
+#define bfin_write_CAN0_AM10L(val)      bfin_write16(CAN0_AM10L, val)
+#define bfin_read_CAN0_AM10H()          bfin_read16(CAN0_AM10H)
+#define bfin_write_CAN0_AM10H(val)      bfin_write16(CAN0_AM10H, val)
+#define bfin_read_CAN0_AM11L()          bfin_read16(CAN0_AM11L)
+#define bfin_write_CAN0_AM11L(val)      bfin_write16(CAN0_AM11L, val)
+#define bfin_read_CAN0_AM11H()          bfin_read16(CAN0_AM11H)
+#define bfin_write_CAN0_AM11H(val)      bfin_write16(CAN0_AM11H, val)
+#define bfin_read_CAN0_AM12L()          bfin_read16(CAN0_AM12L)
+#define bfin_write_CAN0_AM12L(val)      bfin_write16(CAN0_AM12L, val)
+#define bfin_read_CAN0_AM12H()          bfin_read16(CAN0_AM12H)
+#define bfin_write_CAN0_AM12H(val)      bfin_write16(CAN0_AM12H, val)
+#define bfin_read_CAN0_AM13L()          bfin_read16(CAN0_AM13L)
+#define bfin_write_CAN0_AM13L(val)      bfin_write16(CAN0_AM13L, val)
+#define bfin_read_CAN0_AM13H()          bfin_read16(CAN0_AM13H)
+#define bfin_write_CAN0_AM13H(val)      bfin_write16(CAN0_AM13H, val)
+#define bfin_read_CAN0_AM14L()          bfin_read16(CAN0_AM14L)
+#define bfin_write_CAN0_AM14L(val)      bfin_write16(CAN0_AM14L, val)
+#define bfin_read_CAN0_AM14H()          bfin_read16(CAN0_AM14H)
+#define bfin_write_CAN0_AM14H(val)      bfin_write16(CAN0_AM14H, val)
+#define bfin_read_CAN0_AM15L()          bfin_read16(CAN0_AM15L)
+#define bfin_write_CAN0_AM15L(val)      bfin_write16(CAN0_AM15L, val)
+#define bfin_read_CAN0_AM15H()          bfin_read16(CAN0_AM15H)
+#define bfin_write_CAN0_AM15H(val)      bfin_write16(CAN0_AM15H, val)
+/* CAN Controller 0 Accebfin_read_()tance Registers */
+#define bfin_read_CAN0_AM16L()          bfin_read16(CAN0_AM16L)
+#define bfin_write_CAN0_AM16L(val)      bfin_write16(CAN0_AM16L, val)
+#define bfin_read_CAN0_AM16H()          bfin_read16(CAN0_AM16H)
+#define bfin_write_CAN0_AM16H(val)      bfin_write16(CAN0_AM16H, val)
+#define bfin_read_CAN0_AM17L()          bfin_read16(CAN0_AM17L)
+#define bfin_write_CAN0_AM17L(val)      bfin_write16(CAN0_AM17L, val)
+#define bfin_read_CAN0_AM17H()          bfin_read16(CAN0_AM17H)
+#define bfin_write_CAN0_AM17H(val)      bfin_write16(CAN0_AM17H, val)
+#define bfin_read_CAN0_AM18L()          bfin_read16(CAN0_AM18L)
+#define bfin_write_CAN0_AM18L(val)      bfin_write16(CAN0_AM18L, val)
+#define bfin_read_CAN0_AM18H()          bfin_read16(CAN0_AM18H)
+#define bfin_write_CAN0_AM18H(val)      bfin_write16(CAN0_AM18H, val)
+#define bfin_read_CAN0_AM19L()          bfin_read16(CAN0_AM19L)
+#define bfin_write_CAN0_AM19L(val)      bfin_write16(CAN0_AM19L, val)
+#define bfin_read_CAN0_AM19H()          bfin_read16(CAN0_AM19H)
+#define bfin_write_CAN0_AM19H(val)      bfin_write16(CAN0_AM19H, val)
+#define bfin_read_CAN0_AM20L()          bfin_read16(CAN0_AM20L)
+#define bfin_write_CAN0_AM20L(val)      bfin_write16(CAN0_AM20L, val)
+#define bfin_read_CAN0_AM20H()          bfin_read16(CAN0_AM20H)
+#define bfin_write_CAN0_AM20H(val)      bfin_write16(CAN0_AM20H, val)
+#define bfin_read_CAN0_AM21L()          bfin_read16(CAN0_AM21L)
+#define bfin_write_CAN0_AM21L(val)      bfin_write16(CAN0_AM21L, val)
+#define bfin_read_CAN0_AM21H()          bfin_read16(CAN0_AM21H)
+#define bfin_write_CAN0_AM21H(val)      bfin_write16(CAN0_AM21H, val)
+#define bfin_read_CAN0_AM22L()          bfin_read16(CAN0_AM22L)
+#define bfin_write_CAN0_AM22L(val)      bfin_write16(CAN0_AM22L, val)
+#define bfin_read_CAN0_AM22H()          bfin_read16(CAN0_AM22H)
+#define bfin_write_CAN0_AM22H(val)      bfin_write16(CAN0_AM22H, val)
+#define bfin_read_CAN0_AM23L()          bfin_read16(CAN0_AM23L)
+#define bfin_write_CAN0_AM23L(val)      bfin_write16(CAN0_AM23L, val)
+#define bfin_read_CAN0_AM23H()          bfin_read16(CAN0_AM23H)
+#define bfin_write_CAN0_AM23H(val)      bfin_write16(CAN0_AM23H, val)
+#define bfin_read_CAN0_AM24L()          bfin_read16(CAN0_AM24L)
+#define bfin_write_CAN0_AM24L(val)      bfin_write16(CAN0_AM24L, val)
+#define bfin_read_CAN0_AM24H()          bfin_read16(CAN0_AM24H)
+#define bfin_write_CAN0_AM24H(val)      bfin_write16(CAN0_AM24H, val)
+#define bfin_read_CAN0_AM25L()          bfin_read16(CAN0_AM25L)
+#define bfin_write_CAN0_AM25L(val)      bfin_write16(CAN0_AM25L, val)
+#define bfin_read_CAN0_AM25H()          bfin_read16(CAN0_AM25H)
+#define bfin_write_CAN0_AM25H(val)      bfin_write16(CAN0_AM25H, val)
+#define bfin_read_CAN0_AM26L()          bfin_read16(CAN0_AM26L)
+#define bfin_write_CAN0_AM26L(val)      bfin_write16(CAN0_AM26L, val)
+#define bfin_read_CAN0_AM26H()          bfin_read16(CAN0_AM26H)
+#define bfin_write_CAN0_AM26H(val)      bfin_write16(CAN0_AM26H, val)
+#define bfin_read_CAN0_AM27L()          bfin_read16(CAN0_AM27L)
+#define bfin_write_CAN0_AM27L(val)      bfin_write16(CAN0_AM27L, val)
+#define bfin_read_CAN0_AM27H()          bfin_read16(CAN0_AM27H)
+#define bfin_write_CAN0_AM27H(val)      bfin_write16(CAN0_AM27H, val)
+#define bfin_read_CAN0_AM28L()          bfin_read16(CAN0_AM28L)
+#define bfin_write_CAN0_AM28L(val)      bfin_write16(CAN0_AM28L, val)
+#define bfin_read_CAN0_AM28H()          bfin_read16(CAN0_AM28H)
+#define bfin_write_CAN0_AM28H(val)      bfin_write16(CAN0_AM28H, val)
+#define bfin_read_CAN0_AM29L()          bfin_read16(CAN0_AM29L)
+#define bfin_write_CAN0_AM29L(val)      bfin_write16(CAN0_AM29L, val)
+#define bfin_read_CAN0_AM29H()          bfin_read16(CAN0_AM29H)
+#define bfin_write_CAN0_AM29H(val)      bfin_write16(CAN0_AM29H, val)
+#define bfin_read_CAN0_AM30L()          bfin_read16(CAN0_AM30L)
+#define bfin_write_CAN0_AM30L(val)      bfin_write16(CAN0_AM30L, val)
+#define bfin_read_CAN0_AM30H()          bfin_read16(CAN0_AM30H)
+#define bfin_write_CAN0_AM30H(val)      bfin_write16(CAN0_AM30H, val)
+#define bfin_read_CAN0_AM31L()          bfin_read16(CAN0_AM31L)
+#define bfin_write_CAN0_AM31L(val)      bfin_write16(CAN0_AM31L, val)
+#define bfin_read_CAN0_AM31H()          bfin_read16(CAN0_AM31H)
+#define bfin_write_CAN0_AM31H(val)      bfin_write16(CAN0_AM31H, val)
+/* CAN Controller 0 Mailbox Data Registers */
+#define bfin_read_CAN0_MB00_DATA0()             bfin_read16(CAN0_MB00_DATA0)
+#define bfin_write_CAN0_MB00_DATA0(val)         bfin_write16(CAN0_MB00_DATA0, val)
+#define bfin_read_CAN0_MB00_DATA1()             bfin_read16(CAN0_MB00_DATA1)
+#define bfin_write_CAN0_MB00_DATA1(val)         bfin_write16(CAN0_MB00_DATA1, val)
+#define bfin_read_CAN0_MB00_DATA2()             bfin_read16(CAN0_MB00_DATA2)
+#define bfin_write_CAN0_MB00_DATA2(val)         bfin_write16(CAN0_MB00_DATA2, val)
+#define bfin_read_CAN0_MB00_DATA3()             bfin_read16(CAN0_MB00_DATA3)
+#define bfin_write_CAN0_MB00_DATA3(val)         bfin_write16(CAN0_MB00_DATA3, val)
+#define bfin_read_CAN0_MB00_LENGTH()            bfin_read16(CAN0_MB00_LENGTH)
+#define bfin_write_CAN0_MB00_LENGTH(val)        bfin_write16(CAN0_MB00_LENGTH, val)
+#define bfin_read_CAN0_MB00_TIMESTAMP()         bfin_read16(CAN0_MB00_TIMESTAMP)
+#define bfin_write_CAN0_MB00_TIMESTAMP(val)     bfin_write16(CAN0_MB00_TIMESTAMP, val)
+#define bfin_read_CAN0_MB00_ID0()               bfin_read16(CAN0_MB00_ID0)
+#define bfin_write_CAN0_MB00_ID0(val)           bfin_write16(CAN0_MB00_ID0, val)
+#define bfin_read_CAN0_MB00_ID1()               bfin_read16(CAN0_MB00_ID1)
+#define bfin_write_CAN0_MB00_ID1(val)           bfin_write16(CAN0_MB00_ID1, val)
+#define bfin_read_CAN0_MB01_DATA0()             bfin_read16(CAN0_MB01_DATA0)
+#define bfin_write_CAN0_MB01_DATA0(val)         bfin_write16(CAN0_MB01_DATA0, val)
+#define bfin_read_CAN0_MB01_DATA1()             bfin_read16(CAN0_MB01_DATA1)
+#define bfin_write_CAN0_MB01_DATA1(val)         bfin_write16(CAN0_MB01_DATA1, val)
+#define bfin_read_CAN0_MB01_DATA2()             bfin_read16(CAN0_MB01_DATA2)
+#define bfin_write_CAN0_MB01_DATA2(val)         bfin_write16(CAN0_MB01_DATA2, val)
+#define bfin_read_CAN0_MB01_DATA3()             bfin_read16(CAN0_MB01_DATA3)
+#define bfin_write_CAN0_MB01_DATA3(val)         bfin_write16(CAN0_MB01_DATA3, val)
+#define bfin_read_CAN0_MB01_LENGTH()            bfin_read16(CAN0_MB01_LENGTH)
+#define bfin_write_CAN0_MB01_LENGTH(val)        bfin_write16(CAN0_MB01_LENGTH, val)
+#define bfin_read_CAN0_MB01_TIMESTAMP()         bfin_read16(CAN0_MB01_TIMESTAMP)
+#define bfin_write_CAN0_MB01_TIMESTAMP(val)     bfin_write16(CAN0_MB01_TIMESTAMP, val)
+#define bfin_read_CAN0_MB01_ID0()               bfin_read16(CAN0_MB01_ID0)
+#define bfin_write_CAN0_MB01_ID0(val)           bfin_write16(CAN0_MB01_ID0, val)
+#define bfin_read_CAN0_MB01_ID1()               bfin_read16(CAN0_MB01_ID1)
+#define bfin_write_CAN0_MB01_ID1(val)           bfin_write16(CAN0_MB01_ID1, val)
+#define bfin_read_CAN0_MB02_DATA0()             bfin_read16(CAN0_MB02_DATA0)
+#define bfin_write_CAN0_MB02_DATA0(val)         bfin_write16(CAN0_MB02_DATA0, val)
+#define bfin_read_CAN0_MB02_DATA1()             bfin_read16(CAN0_MB02_DATA1)
+#define bfin_write_CAN0_MB02_DATA1(val)         bfin_write16(CAN0_MB02_DATA1, val)
+#define bfin_read_CAN0_MB02_DATA2()             bfin_read16(CAN0_MB02_DATA2)
+#define bfin_write_CAN0_MB02_DATA2(val)         bfin_write16(CAN0_MB02_DATA2, val)
+#define bfin_read_CAN0_MB02_DATA3()             bfin_read16(CAN0_MB02_DATA3)
+#define bfin_write_CAN0_MB02_DATA3(val)         bfin_write16(CAN0_MB02_DATA3, val)
+#define bfin_read_CAN0_MB02_LENGTH()            bfin_read16(CAN0_MB02_LENGTH)
+#define bfin_write_CAN0_MB02_LENGTH(val)        bfin_write16(CAN0_MB02_LENGTH, val)
+#define bfin_read_CAN0_MB02_TIMESTAMP()         bfin_read16(CAN0_MB02_TIMESTAMP)
+#define bfin_write_CAN0_MB02_TIMESTAMP(val)     bfin_write16(CAN0_MB02_TIMESTAMP, val)
+#define bfin_read_CAN0_MB02_ID0()               bfin_read16(CAN0_MB02_ID0)
+#define bfin_write_CAN0_MB02_ID0(val)           bfin_write16(CAN0_MB02_ID0, val)
+#define bfin_read_CAN0_MB02_ID1()               bfin_read16(CAN0_MB02_ID1)
+#define bfin_write_CAN0_MB02_ID1(val)           bfin_write16(CAN0_MB02_ID1, val)
+#define bfin_read_CAN0_MB03_DATA0()             bfin_read16(CAN0_MB03_DATA0)
+#define bfin_write_CAN0_MB03_DATA0(val)         bfin_write16(CAN0_MB03_DATA0, val)
+#define bfin_read_CAN0_MB03_DATA1()             bfin_read16(CAN0_MB03_DATA1)
+#define bfin_write_CAN0_MB03_DATA1(val)         bfin_write16(CAN0_MB03_DATA1, val)
+#define bfin_read_CAN0_MB03_DATA2()             bfin_read16(CAN0_MB03_DATA2)
+#define bfin_write_CAN0_MB03_DATA2(val)         bfin_write16(CAN0_MB03_DATA2, val)
+#define bfin_read_CAN0_MB03_DATA3()             bfin_read16(CAN0_MB03_DATA3)
+#define bfin_write_CAN0_MB03_DATA3(val)         bfin_write16(CAN0_MB03_DATA3, val)
+#define bfin_read_CAN0_MB03_LENGTH()            bfin_read16(CAN0_MB03_LENGTH)
+#define bfin_write_CAN0_MB03_LENGTH(val)        bfin_write16(CAN0_MB03_LENGTH, val)
+#define bfin_read_CAN0_MB03_TIMESTAMP()         bfin_read16(CAN0_MB03_TIMESTAMP)
+#define bfin_write_CAN0_MB03_TIMESTAMP(val)     bfin_write16(CAN0_MB03_TIMESTAMP, val)
+#define bfin_read_CAN0_MB03_ID0()               bfin_read16(CAN0_MB03_ID0)
+#define bfin_write_CAN0_MB03_ID0(val)           bfin_write16(CAN0_MB03_ID0, val)
+#define bfin_read_CAN0_MB03_ID1()               bfin_read16(CAN0_MB03_ID1)
+#define bfin_write_CAN0_MB03_ID1(val)           bfin_write16(CAN0_MB03_ID1, val)
+#define bfin_read_CAN0_MB04_DATA0()             bfin_read16(CAN0_MB04_DATA0)
+#define bfin_write_CAN0_MB04_DATA0(val)         bfin_write16(CAN0_MB04_DATA0, val)
+#define bfin_read_CAN0_MB04_DATA1()             bfin_read16(CAN0_MB04_DATA1)
+#define bfin_write_CAN0_MB04_DATA1(val)         bfin_write16(CAN0_MB04_DATA1, val)
+#define bfin_read_CAN0_MB04_DATA2()             bfin_read16(CAN0_MB04_DATA2)
+#define bfin_write_CAN0_MB04_DATA2(val)         bfin_write16(CAN0_MB04_DATA2, val)
+#define bfin_read_CAN0_MB04_DATA3()             bfin_read16(CAN0_MB04_DATA3)
+#define bfin_write_CAN0_MB04_DATA3(val)         bfin_write16(CAN0_MB04_DATA3, val)
+#define bfin_read_CAN0_MB04_LENGTH()            bfin_read16(CAN0_MB04_LENGTH)
+#define bfin_write_CAN0_MB04_LENGTH(val)        bfin_write16(CAN0_MB04_LENGTH, val)
+#define bfin_read_CAN0_MB04_TIMESTAMP()         bfin_read16(CAN0_MB04_TIMESTAMP)
+#define bfin_write_CAN0_MB04_TIMESTAMP(val)     bfin_write16(CAN0_MB04_TIMESTAMP, val)
+#define bfin_read_CAN0_MB04_ID0()               bfin_read16(CAN0_MB04_ID0)
+#define bfin_write_CAN0_MB04_ID0(val)           bfin_write16(CAN0_MB04_ID0, val)
+#define bfin_read_CAN0_MB04_ID1()               bfin_read16(CAN0_MB04_ID1)
+#define bfin_write_CAN0_MB04_ID1(val)           bfin_write16(CAN0_MB04_ID1, val)
+#define bfin_read_CAN0_MB05_DATA0()             bfin_read16(CAN0_MB05_DATA0)
+#define bfin_write_CAN0_MB05_DATA0(val)         bfin_write16(CAN0_MB05_DATA0, val)
+#define bfin_read_CAN0_MB05_DATA1()             bfin_read16(CAN0_MB05_DATA1)
+#define bfin_write_CAN0_MB05_DATA1(val)         bfin_write16(CAN0_MB05_DATA1, val)
+#define bfin_read_CAN0_MB05_DATA2()             bfin_read16(CAN0_MB05_DATA2)
+#define bfin_write_CAN0_MB05_DATA2(val)         bfin_write16(CAN0_MB05_DATA2, val)
+#define bfin_read_CAN0_MB05_DATA3()             bfin_read16(CAN0_MB05_DATA3)
+#define bfin_write_CAN0_MB05_DATA3(val)         bfin_write16(CAN0_MB05_DATA3, val)
+#define bfin_read_CAN0_MB05_LENGTH()            bfin_read16(CAN0_MB05_LENGTH)
+#define bfin_write_CAN0_MB05_LENGTH(val)        bfin_write16(CAN0_MB05_LENGTH, val)
+#define bfin_read_CAN0_MB05_TIMESTAMP()         bfin_read16(CAN0_MB05_TIMESTAMP)
+#define bfin_write_CAN0_MB05_TIMESTAMP(val)     bfin_write16(CAN0_MB05_TIMESTAMP, val)
+#define bfin_read_CAN0_MB05_ID0()               bfin_read16(CAN0_MB05_ID0)
+#define bfin_write_CAN0_MB05_ID0(val)           bfin_write16(CAN0_MB05_ID0, val)
+#define bfin_read_CAN0_MB05_ID1()               bfin_read16(CAN0_MB05_ID1)
+#define bfin_write_CAN0_MB05_ID1(val)           bfin_write16(CAN0_MB05_ID1, val)
+#define bfin_read_CAN0_MB06_DATA0()             bfin_read16(CAN0_MB06_DATA0)
+#define bfin_write_CAN0_MB06_DATA0(val)         bfin_write16(CAN0_MB06_DATA0, val)
+#define bfin_read_CAN0_MB06_DATA1()             bfin_read16(CAN0_MB06_DATA1)
+#define bfin_write_CAN0_MB06_DATA1(val)         bfin_write16(CAN0_MB06_DATA1, val)
+#define bfin_read_CAN0_MB06_DATA2()             bfin_read16(CAN0_MB06_DATA2)
+#define bfin_write_CAN0_MB06_DATA2(val)         bfin_write16(CAN0_MB06_DATA2, val)
+#define bfin_read_CAN0_MB06_DATA3()             bfin_read16(CAN0_MB06_DATA3)
+#define bfin_write_CAN0_MB06_DATA3(val)         bfin_write16(CAN0_MB06_DATA3, val)
+#define bfin_read_CAN0_MB06_LENGTH()            bfin_read16(CAN0_MB06_LENGTH)
+#define bfin_write_CAN0_MB06_LENGTH(val)        bfin_write16(CAN0_MB06_LENGTH, val)
+#define bfin_read_CAN0_MB06_TIMESTAMP()         bfin_read16(CAN0_MB06_TIMESTAMP)
+#define bfin_write_CAN0_MB06_TIMESTAMP(val)     bfin_write16(CAN0_MB06_TIMESTAMP, val)
+#define bfin_read_CAN0_MB06_ID0()               bfin_read16(CAN0_MB06_ID0)
+#define bfin_write_CAN0_MB06_ID0(val)           bfin_write16(CAN0_MB06_ID0, val)
+#define bfin_read_CAN0_MB06_ID1()               bfin_read16(CAN0_MB06_ID1)
+#define bfin_write_CAN0_MB06_ID1(val)           bfin_write16(CAN0_MB06_ID1, val)
+#define bfin_read_CAN0_MB07_DATA0()             bfin_read16(CAN0_MB07_DATA0)
+#define bfin_write_CAN0_MB07_DATA0(val)         bfin_write16(CAN0_MB07_DATA0, val)
+#define bfin_read_CAN0_MB07_DATA1()             bfin_read16(CAN0_MB07_DATA1)
+#define bfin_write_CAN0_MB07_DATA1(val)         bfin_write16(CAN0_MB07_DATA1, val)
+#define bfin_read_CAN0_MB07_DATA2()             bfin_read16(CAN0_MB07_DATA2)
+#define bfin_write_CAN0_MB07_DATA2(val)         bfin_write16(CAN0_MB07_DATA2, val)
+#define bfin_read_CAN0_MB07_DATA3()             bfin_read16(CAN0_MB07_DATA3)
+#define bfin_write_CAN0_MB07_DATA3(val)         bfin_write16(CAN0_MB07_DATA3, val)
+#define bfin_read_CAN0_MB07_LENGTH()            bfin_read16(CAN0_MB07_LENGTH)
+#define bfin_write_CAN0_MB07_LENGTH(val)        bfin_write16(CAN0_MB07_LENGTH, val)
+#define bfin_read_CAN0_MB07_TIMESTAMP()         bfin_read16(CAN0_MB07_TIMESTAMP)
+#define bfin_write_CAN0_MB07_TIMESTAMP(val)     bfin_write16(CAN0_MB07_TIMESTAMP, val)
+#define bfin_read_CAN0_MB07_ID0()               bfin_read16(CAN0_MB07_ID0)
+#define bfin_write_CAN0_MB07_ID0(val)           bfin_write16(CAN0_MB07_ID0, val)
+#define bfin_read_CAN0_MB07_ID1()               bfin_read16(CAN0_MB07_ID1)
+#define bfin_write_CAN0_MB07_ID1(val)           bfin_write16(CAN0_MB07_ID1, val)
+#define bfin_read_CAN0_MB08_DATA0()             bfin_read16(CAN0_MB08_DATA0)
+#define bfin_write_CAN0_MB08_DATA0(val)         bfin_write16(CAN0_MB08_DATA0, val)
+#define bfin_read_CAN0_MB08_DATA1()             bfin_read16(CAN0_MB08_DATA1)
+#define bfin_write_CAN0_MB08_DATA1(val)         bfin_write16(CAN0_MB08_DATA1, val)
+#define bfin_read_CAN0_MB08_DATA2()             bfin_read16(CAN0_MB08_DATA2)
+#define bfin_write_CAN0_MB08_DATA2(val)         bfin_write16(CAN0_MB08_DATA2, val)
+#define bfin_read_CAN0_MB08_DATA3()             bfin_read16(CAN0_MB08_DATA3)
+#define bfin_write_CAN0_MB08_DATA3(val)         bfin_write16(CAN0_MB08_DATA3, val)
+#define bfin_read_CAN0_MB08_LENGTH()            bfin_read16(CAN0_MB08_LENGTH)
+#define bfin_write_CAN0_MB08_LENGTH(val)        bfin_write16(CAN0_MB08_LENGTH, val)
+#define bfin_read_CAN0_MB08_TIMESTAMP()         bfin_read16(CAN0_MB08_TIMESTAMP)
+#define bfin_write_CAN0_MB08_TIMESTAMP(val)     bfin_write16(CAN0_MB08_TIMESTAMP, val)
+#define bfin_read_CAN0_MB08_ID0()               bfin_read16(CAN0_MB08_ID0)
+#define bfin_write_CAN0_MB08_ID0(val)           bfin_write16(CAN0_MB08_ID0, val)
+#define bfin_read_CAN0_MB08_ID1()               bfin_read16(CAN0_MB08_ID1)
+#define bfin_write_CAN0_MB08_ID1(val)           bfin_write16(CAN0_MB08_ID1, val)
+#define bfin_read_CAN0_MB09_DATA0()             bfin_read16(CAN0_MB09_DATA0)
+#define bfin_write_CAN0_MB09_DATA0(val)         bfin_write16(CAN0_MB09_DATA0, val)
+#define bfin_read_CAN0_MB09_DATA1()             bfin_read16(CAN0_MB09_DATA1)
+#define bfin_write_CAN0_MB09_DATA1(val)         bfin_write16(CAN0_MB09_DATA1, val)
+#define bfin_read_CAN0_MB09_DATA2()             bfin_read16(CAN0_MB09_DATA2)
+#define bfin_write_CAN0_MB09_DATA2(val)         bfin_write16(CAN0_MB09_DATA2, val)
+#define bfin_read_CAN0_MB09_DATA3()             bfin_read16(CAN0_MB09_DATA3)
+#define bfin_write_CAN0_MB09_DATA3(val)         bfin_write16(CAN0_MB09_DATA3, val)
+#define bfin_read_CAN0_MB09_LENGTH()            bfin_read16(CAN0_MB09_LENGTH)
+#define bfin_write_CAN0_MB09_LENGTH(val)        bfin_write16(CAN0_MB09_LENGTH, val)
+#define bfin_read_CAN0_MB09_TIMESTAMP()         bfin_read16(CAN0_MB09_TIMESTAMP)
+#define bfin_write_CAN0_MB09_TIMESTAMP(val)     bfin_write16(CAN0_MB09_TIMESTAMP, val)
+#define bfin_read_CAN0_MB09_ID0()               bfin_read16(CAN0_MB09_ID0)
+#define bfin_write_CAN0_MB09_ID0(val)           bfin_write16(CAN0_MB09_ID0, val)
+#define bfin_read_CAN0_MB09_ID1()               bfin_read16(CAN0_MB09_ID1)
+#define bfin_write_CAN0_MB09_ID1(val)           bfin_write16(CAN0_MB09_ID1, val)
+#define bfin_read_CAN0_MB10_DATA0()             bfin_read16(CAN0_MB10_DATA0)
+#define bfin_write_CAN0_MB10_DATA0(val)         bfin_write16(CAN0_MB10_DATA0, val)
+#define bfin_read_CAN0_MB10_DATA1()             bfin_read16(CAN0_MB10_DATA1)
+#define bfin_write_CAN0_MB10_DATA1(val)         bfin_write16(CAN0_MB10_DATA1, val)
+#define bfin_read_CAN0_MB10_DATA2()             bfin_read16(CAN0_MB10_DATA2)
+#define bfin_write_CAN0_MB10_DATA2(val)         bfin_write16(CAN0_MB10_DATA2, val)
+#define bfin_read_CAN0_MB10_DATA3()             bfin_read16(CAN0_MB10_DATA3)
+#define bfin_write_CAN0_MB10_DATA3(val)         bfin_write16(CAN0_MB10_DATA3, val)
+#define bfin_read_CAN0_MB10_LENGTH()            bfin_read16(CAN0_MB10_LENGTH)
+#define bfin_write_CAN0_MB10_LENGTH(val)        bfin_write16(CAN0_MB10_LENGTH, val)
+#define bfin_read_CAN0_MB10_TIMESTAMP()         bfin_read16(CAN0_MB10_TIMESTAMP)
+#define bfin_write_CAN0_MB10_TIMESTAMP(val)     bfin_write16(CAN0_MB10_TIMESTAMP, val)
+#define bfin_read_CAN0_MB10_ID0()               bfin_read16(CAN0_MB10_ID0)
+#define bfin_write_CAN0_MB10_ID0(val)           bfin_write16(CAN0_MB10_ID0, val)
+#define bfin_read_CAN0_MB10_ID1()               bfin_read16(CAN0_MB10_ID1)
+#define bfin_write_CAN0_MB10_ID1(val)           bfin_write16(CAN0_MB10_ID1, val)
+#define bfin_read_CAN0_MB11_DATA0()             bfin_read16(CAN0_MB11_DATA0)
+#define bfin_write_CAN0_MB11_DATA0(val)         bfin_write16(CAN0_MB11_DATA0, val)
+#define bfin_read_CAN0_MB11_DATA1()             bfin_read16(CAN0_MB11_DATA1)
+#define bfin_write_CAN0_MB11_DATA1(val)         bfin_write16(CAN0_MB11_DATA1, val)
+#define bfin_read_CAN0_MB11_DATA2()             bfin_read16(CAN0_MB11_DATA2)
+#define bfin_write_CAN0_MB11_DATA2(val)         bfin_write16(CAN0_MB11_DATA2, val)
+#define bfin_read_CAN0_MB11_DATA3()             bfin_read16(CAN0_MB11_DATA3)
+#define bfin_write_CAN0_MB11_DATA3(val)         bfin_write16(CAN0_MB11_DATA3, val)
+#define bfin_read_CAN0_MB11_LENGTH()            bfin_read16(CAN0_MB11_LENGTH)
+#define bfin_write_CAN0_MB11_LENGTH(val)        bfin_write16(CAN0_MB11_LENGTH, val)
+#define bfin_read_CAN0_MB11_TIMESTAMP()         bfin_read16(CAN0_MB11_TIMESTAMP)
+#define bfin_write_CAN0_MB11_TIMESTAMP(val)     bfin_write16(CAN0_MB11_TIMESTAMP, val)
+#define bfin_read_CAN0_MB11_ID0()               bfin_read16(CAN0_MB11_ID0)
+#define bfin_write_CAN0_MB11_ID0(val)           bfin_write16(CAN0_MB11_ID0, val)
+#define bfin_read_CAN0_MB11_ID1()               bfin_read16(CAN0_MB11_ID1)
+#define bfin_write_CAN0_MB11_ID1(val)           bfin_write16(CAN0_MB11_ID1, val)
+#define bfin_read_CAN0_MB12_DATA0()             bfin_read16(CAN0_MB12_DATA0)
+#define bfin_write_CAN0_MB12_DATA0(val)         bfin_write16(CAN0_MB12_DATA0, val)
+#define bfin_read_CAN0_MB12_DATA1()             bfin_read16(CAN0_MB12_DATA1)
+#define bfin_write_CAN0_MB12_DATA1(val)         bfin_write16(CAN0_MB12_DATA1, val)
+#define bfin_read_CAN0_MB12_DATA2()             bfin_read16(CAN0_MB12_DATA2)
+#define bfin_write_CAN0_MB12_DATA2(val)         bfin_write16(CAN0_MB12_DATA2, val)
+#define bfin_read_CAN0_MB12_DATA3()             bfin_read16(CAN0_MB12_DATA3)
+#define bfin_write_CAN0_MB12_DATA3(val)         bfin_write16(CAN0_MB12_DATA3, val)
+#define bfin_read_CAN0_MB12_LENGTH()            bfin_read16(CAN0_MB12_LENGTH)
+#define bfin_write_CAN0_MB12_LENGTH(val)        bfin_write16(CAN0_MB12_LENGTH, val)
+#define bfin_read_CAN0_MB12_TIMESTAMP()         bfin_read16(CAN0_MB12_TIMESTAMP)
+#define bfin_write_CAN0_MB12_TIMESTAMP(val)     bfin_write16(CAN0_MB12_TIMESTAMP, val)
+#define bfin_read_CAN0_MB12_ID0()               bfin_read16(CAN0_MB12_ID0)
+#define bfin_write_CAN0_MB12_ID0(val)           bfin_write16(CAN0_MB12_ID0, val)
+#define bfin_read_CAN0_MB12_ID1()               bfin_read16(CAN0_MB12_ID1)
+#define bfin_write_CAN0_MB12_ID1(val)           bfin_write16(CAN0_MB12_ID1, val)
+#define bfin_read_CAN0_MB13_DATA0()             bfin_read16(CAN0_MB13_DATA0)
+#define bfin_write_CAN0_MB13_DATA0(val)         bfin_write16(CAN0_MB13_DATA0, val)
+#define bfin_read_CAN0_MB13_DATA1()             bfin_read16(CAN0_MB13_DATA1)
+#define bfin_write_CAN0_MB13_DATA1(val)         bfin_write16(CAN0_MB13_DATA1, val)
+#define bfin_read_CAN0_MB13_DATA2()             bfin_read16(CAN0_MB13_DATA2)
+#define bfin_write_CAN0_MB13_DATA2(val)         bfin_write16(CAN0_MB13_DATA2, val)
+#define bfin_read_CAN0_MB13_DATA3()             bfin_read16(CAN0_MB13_DATA3)
+#define bfin_write_CAN0_MB13_DATA3(val)         bfin_write16(CAN0_MB13_DATA3, val)
+#define bfin_read_CAN0_MB13_LENGTH()            bfin_read16(CAN0_MB13_LENGTH)
+#define bfin_write_CAN0_MB13_LENGTH(val)        bfin_write16(CAN0_MB13_LENGTH, val)
+#define bfin_read_CAN0_MB13_TIMESTAMP()         bfin_read16(CAN0_MB13_TIMESTAMP)
+#define bfin_write_CAN0_MB13_TIMESTAMP(val)     bfin_write16(CAN0_MB13_TIMESTAMP, val)
+#define bfin_read_CAN0_MB13_ID0()               bfin_read16(CAN0_MB13_ID0)
+#define bfin_write_CAN0_MB13_ID0(val)           bfin_write16(CAN0_MB13_ID0, val)
+#define bfin_read_CAN0_MB13_ID1()               bfin_read16(CAN0_MB13_ID1)
+#define bfin_write_CAN0_MB13_ID1(val)           bfin_write16(CAN0_MB13_ID1, val)
+#define bfin_read_CAN0_MB14_DATA0()             bfin_read16(CAN0_MB14_DATA0)
+#define bfin_write_CAN0_MB14_DATA0(val)         bfin_write16(CAN0_MB14_DATA0, val)
+#define bfin_read_CAN0_MB14_DATA1()             bfin_read16(CAN0_MB14_DATA1)
+#define bfin_write_CAN0_MB14_DATA1(val)         bfin_write16(CAN0_MB14_DATA1, val)
+#define bfin_read_CAN0_MB14_DATA2()             bfin_read16(CAN0_MB14_DATA2)
+#define bfin_write_CAN0_MB14_DATA2(val)         bfin_write16(CAN0_MB14_DATA2, val)
+#define bfin_read_CAN0_MB14_DATA3()             bfin_read16(CAN0_MB14_DATA3)
+#define bfin_write_CAN0_MB14_DATA3(val)         bfin_write16(CAN0_MB14_DATA3, val)
+#define bfin_read_CAN0_MB14_LENGTH()            bfin_read16(CAN0_MB14_LENGTH)
+#define bfin_write_CAN0_MB14_LENGTH(val)        bfin_write16(CAN0_MB14_LENGTH, val)
+#define bfin_read_CAN0_MB14_TIMESTAMP()         bfin_read16(CAN0_MB14_TIMESTAMP)
+#define bfin_write_CAN0_MB14_TIMESTAMP(val)     bfin_write16(CAN0_MB14_TIMESTAMP, val)
+#define bfin_read_CAN0_MB14_ID0()               bfin_read16(CAN0_MB14_ID0)
+#define bfin_write_CAN0_MB14_ID0(val)           bfin_write16(CAN0_MB14_ID0, val)
+#define bfin_read_CAN0_MB14_ID1()               bfin_read16(CAN0_MB14_ID1)
+#define bfin_write_CAN0_MB14_ID1(val)           bfin_write16(CAN0_MB14_ID1, val)
+#define bfin_read_CAN0_MB15_DATA0()             bfin_read16(CAN0_MB15_DATA0)
+#define bfin_write_CAN0_MB15_DATA0(val)         bfin_write16(CAN0_MB15_DATA0, val)
+#define bfin_read_CAN0_MB15_DATA1()             bfin_read16(CAN0_MB15_DATA1)
+#define bfin_write_CAN0_MB15_DATA1(val)         bfin_write16(CAN0_MB15_DATA1, val)
+#define bfin_read_CAN0_MB15_DATA2()             bfin_read16(CAN0_MB15_DATA2)
+#define bfin_write_CAN0_MB15_DATA2(val)         bfin_write16(CAN0_MB15_DATA2, val)
+#define bfin_read_CAN0_MB15_DATA3()             bfin_read16(CAN0_MB15_DATA3)
+#define bfin_write_CAN0_MB15_DATA3(val)         bfin_write16(CAN0_MB15_DATA3, val)
+#define bfin_read_CAN0_MB15_LENGTH()            bfin_read16(CAN0_MB15_LENGTH)
+#define bfin_write_CAN0_MB15_LENGTH(val)        bfin_write16(CAN0_MB15_LENGTH, val)
+#define bfin_read_CAN0_MB15_TIMESTAMP()         bfin_read16(CAN0_MB15_TIMESTAMP)
+#define bfin_write_CAN0_MB15_TIMESTAMP(val)     bfin_write16(CAN0_MB15_TIMESTAMP, val)
+#define bfin_read_CAN0_MB15_ID0()               bfin_read16(CAN0_MB15_ID0)
+#define bfin_write_CAN0_MB15_ID0(val)           bfin_write16(CAN0_MB15_ID0, val)
+#define bfin_read_CAN0_MB15_ID1()               bfin_read16(CAN0_MB15_ID1)
+#define bfin_write_CAN0_MB15_ID1(val)           bfin_write16(CAN0_MB15_ID1, val)
+/* CAN Controller 0 Mailbox Data Registers */
+#define bfin_read_CAN0_MB16_DATA0()             bfin_read16(CAN0_MB16_DATA0)
+#define bfin_write_CAN0_MB16_DATA0(val)         bfin_write16(CAN0_MB16_DATA0, val)
+#define bfin_read_CAN0_MB16_DATA1()             bfin_read16(CAN0_MB16_DATA1)
+#define bfin_write_CAN0_MB16_DATA1(val)         bfin_write16(CAN0_MB16_DATA1, val)
+#define bfin_read_CAN0_MB16_DATA2()             bfin_read16(CAN0_MB16_DATA2)
+#define bfin_write_CAN0_MB16_DATA2(val)         bfin_write16(CAN0_MB16_DATA2, val)
+#define bfin_read_CAN0_MB16_DATA3()             bfin_read16(CAN0_MB16_DATA3)
+#define bfin_write_CAN0_MB16_DATA3(val)         bfin_write16(CAN0_MB16_DATA3, val)
+#define bfin_read_CAN0_MB16_LENGTH()            bfin_read16(CAN0_MB16_LENGTH)
+#define bfin_write_CAN0_MB16_LENGTH(val)        bfin_write16(CAN0_MB16_LENGTH, val)
+#define bfin_read_CAN0_MB16_TIMESTAMP()         bfin_read16(CAN0_MB16_TIMESTAMP)
+#define bfin_write_CAN0_MB16_TIMESTAMP(val)     bfin_write16(CAN0_MB16_TIMESTAMP, val)
+#define bfin_read_CAN0_MB16_ID0()               bfin_read16(CAN0_MB16_ID0)
+#define bfin_write_CAN0_MB16_ID0(val)           bfin_write16(CAN0_MB16_ID0, val)
+#define bfin_read_CAN0_MB16_ID1()               bfin_read16(CAN0_MB16_ID1)
+#define bfin_write_CAN0_MB16_ID1(val)           bfin_write16(CAN0_MB16_ID1, val)
+#define bfin_read_CAN0_MB17_DATA0()             bfin_read16(CAN0_MB17_DATA0)
+#define bfin_write_CAN0_MB17_DATA0(val)         bfin_write16(CAN0_MB17_DATA0, val)
+#define bfin_read_CAN0_MB17_DATA1()             bfin_read16(CAN0_MB17_DATA1)
+#define bfin_write_CAN0_MB17_DATA1(val)         bfin_write16(CAN0_MB17_DATA1, val)
+#define bfin_read_CAN0_MB17_DATA2()             bfin_read16(CAN0_MB17_DATA2)
+#define bfin_write_CAN0_MB17_DATA2(val)         bfin_write16(CAN0_MB17_DATA2, val)
+#define bfin_read_CAN0_MB17_DATA3()             bfin_read16(CAN0_MB17_DATA3)
+#define bfin_write_CAN0_MB17_DATA3(val)         bfin_write16(CAN0_MB17_DATA3, val)
+#define bfin_read_CAN0_MB17_LENGTH()            bfin_read16(CAN0_MB17_LENGTH)
+#define bfin_write_CAN0_MB17_LENGTH(val)        bfin_write16(CAN0_MB17_LENGTH, val)
+#define bfin_read_CAN0_MB17_TIMESTAMP()         bfin_read16(CAN0_MB17_TIMESTAMP)
+#define bfin_write_CAN0_MB17_TIMESTAMP(val)     bfin_write16(CAN0_MB17_TIMESTAMP, val)
+#define bfin_read_CAN0_MB17_ID0()               bfin_read16(CAN0_MB17_ID0)
+#define bfin_write_CAN0_MB17_ID0(val)           bfin_write16(CAN0_MB17_ID0, val)
+#define bfin_read_CAN0_MB17_ID1()               bfin_read16(CAN0_MB17_ID1)
+#define bfin_write_CAN0_MB17_ID1(val)           bfin_write16(CAN0_MB17_ID1, val)
+#define bfin_read_CAN0_MB18_DATA0()             bfin_read16(CAN0_MB18_DATA0)
+#define bfin_write_CAN0_MB18_DATA0(val)         bfin_write16(CAN0_MB18_DATA0, val)
+#define bfin_read_CAN0_MB18_DATA1()             bfin_read16(CAN0_MB18_DATA1)
+#define bfin_write_CAN0_MB18_DATA1(val)         bfin_write16(CAN0_MB18_DATA1, val)
+#define bfin_read_CAN0_MB18_DATA2()             bfin_read16(CAN0_MB18_DATA2)
+#define bfin_write_CAN0_MB18_DATA2(val)         bfin_write16(CAN0_MB18_DATA2, val)
+#define bfin_read_CAN0_MB18_DATA3()             bfin_read16(CAN0_MB18_DATA3)
+#define bfin_write_CAN0_MB18_DATA3(val)         bfin_write16(CAN0_MB18_DATA3, val)
+#define bfin_read_CAN0_MB18_LENGTH()            bfin_read16(CAN0_MB18_LENGTH)
+#define bfin_write_CAN0_MB18_LENGTH(val)        bfin_write16(CAN0_MB18_LENGTH, val)
+#define bfin_read_CAN0_MB18_TIMESTAMP()         bfin_read16(CAN0_MB18_TIMESTAMP)
+#define bfin_write_CAN0_MB18_TIMESTAMP(val)     bfin_write16(CAN0_MB18_TIMESTAMP, val)
+#define bfin_read_CAN0_MB18_ID0()               bfin_read16(CAN0_MB18_ID0)
+#define bfin_write_CAN0_MB18_ID0(val)           bfin_write16(CAN0_MB18_ID0, val)
+#define bfin_read_CAN0_MB18_ID1()               bfin_read16(CAN0_MB18_ID1)
+#define bfin_write_CAN0_MB18_ID1(val)           bfin_write16(CAN0_MB18_ID1, val)
+#define bfin_read_CAN0_MB19_DATA0()             bfin_read16(CAN0_MB19_DATA0)
+#define bfin_write_CAN0_MB19_DATA0(val)         bfin_write16(CAN0_MB19_DATA0, val)
+#define bfin_read_CAN0_MB19_DATA1()             bfin_read16(CAN0_MB19_DATA1)
+#define bfin_write_CAN0_MB19_DATA1(val)         bfin_write16(CAN0_MB19_DATA1, val)
+#define bfin_read_CAN0_MB19_DATA2()             bfin_read16(CAN0_MB19_DATA2)
+#define bfin_write_CAN0_MB19_DATA2(val)         bfin_write16(CAN0_MB19_DATA2, val)
+#define bfin_read_CAN0_MB19_DATA3()             bfin_read16(CAN0_MB19_DATA3)
+#define bfin_write_CAN0_MB19_DATA3(val)         bfin_write16(CAN0_MB19_DATA3, val)
+#define bfin_read_CAN0_MB19_LENGTH()            bfin_read16(CAN0_MB19_LENGTH)
+#define bfin_write_CAN0_MB19_LENGTH(val)        bfin_write16(CAN0_MB19_LENGTH, val)
+#define bfin_read_CAN0_MB19_TIMESTAMP()         bfin_read16(CAN0_MB19_TIMESTAMP)
+#define bfin_write_CAN0_MB19_TIMESTAMP(val)     bfin_write16(CAN0_MB19_TIMESTAMP, val)
+#define bfin_read_CAN0_MB19_ID0()               bfin_read16(CAN0_MB19_ID0)
+#define bfin_write_CAN0_MB19_ID0(val)           bfin_write16(CAN0_MB19_ID0, val)
+#define bfin_read_CAN0_MB19_ID1()               bfin_read16(CAN0_MB19_ID1)
+#define bfin_write_CAN0_MB19_ID1(val)           bfin_write16(CAN0_MB19_ID1, val)
+#define bfin_read_CAN0_MB20_DATA0()             bfin_read16(CAN0_MB20_DATA0)
+#define bfin_write_CAN0_MB20_DATA0(val)         bfin_write16(CAN0_MB20_DATA0, val)
+#define bfin_read_CAN0_MB20_DATA1()             bfin_read16(CAN0_MB20_DATA1)
+#define bfin_write_CAN0_MB20_DATA1(val)         bfin_write16(CAN0_MB20_DATA1, val)
+#define bfin_read_CAN0_MB20_DATA2()             bfin_read16(CAN0_MB20_DATA2)
+#define bfin_write_CAN0_MB20_DATA2(val)         bfin_write16(CAN0_MB20_DATA2, val)
+#define bfin_read_CAN0_MB20_DATA3()             bfin_read16(CAN0_MB20_DATA3)
+#define bfin_write_CAN0_MB20_DATA3(val)         bfin_write16(CAN0_MB20_DATA3, val)
+#define bfin_read_CAN0_MB20_LENGTH()            bfin_read16(CAN0_MB20_LENGTH)
+#define bfin_write_CAN0_MB20_LENGTH(val)        bfin_write16(CAN0_MB20_LENGTH, val)
+#define bfin_read_CAN0_MB20_TIMESTAMP()         bfin_read16(CAN0_MB20_TIMESTAMP)
+#define bfin_write_CAN0_MB20_TIMESTAMP(val)     bfin_write16(CAN0_MB20_TIMESTAMP, val)
+#define bfin_read_CAN0_MB20_ID0()               bfin_read16(CAN0_MB20_ID0)
+#define bfin_write_CAN0_MB20_ID0(val)           bfin_write16(CAN0_MB20_ID0, val)
+#define bfin_read_CAN0_MB20_ID1()               bfin_read16(CAN0_MB20_ID1)
+#define bfin_write_CAN0_MB20_ID1(val)           bfin_write16(CAN0_MB20_ID1, val)
+#define bfin_read_CAN0_MB21_DATA0()             bfin_read16(CAN0_MB21_DATA0)
+#define bfin_write_CAN0_MB21_DATA0(val)         bfin_write16(CAN0_MB21_DATA0, val)
+#define bfin_read_CAN0_MB21_DATA1()             bfin_read16(CAN0_MB21_DATA1)
+#define bfin_write_CAN0_MB21_DATA1(val)         bfin_write16(CAN0_MB21_DATA1, val)
+#define bfin_read_CAN0_MB21_DATA2()             bfin_read16(CAN0_MB21_DATA2)
+#define bfin_write_CAN0_MB21_DATA2(val)         bfin_write16(CAN0_MB21_DATA2, val)
+#define bfin_read_CAN0_MB21_DATA3()             bfin_read16(CAN0_MB21_DATA3)
+#define bfin_write_CAN0_MB21_DATA3(val)         bfin_write16(CAN0_MB21_DATA3, val)
+#define bfin_read_CAN0_MB21_LENGTH()            bfin_read16(CAN0_MB21_LENGTH)
+#define bfin_write_CAN0_MB21_LENGTH(val)        bfin_write16(CAN0_MB21_LENGTH, val)
+#define bfin_read_CAN0_MB21_TIMESTAMP()         bfin_read16(CAN0_MB21_TIMESTAMP)
+#define bfin_write_CAN0_MB21_TIMESTAMP(val)     bfin_write16(CAN0_MB21_TIMESTAMP, val)
+#define bfin_read_CAN0_MB21_ID0()               bfin_read16(CAN0_MB21_ID0)
+#define bfin_write_CAN0_MB21_ID0(val)           bfin_write16(CAN0_MB21_ID0, val)
+#define bfin_read_CAN0_MB21_ID1()               bfin_read16(CAN0_MB21_ID1)
+#define bfin_write_CAN0_MB21_ID1(val)           bfin_write16(CAN0_MB21_ID1, val)
+#define bfin_read_CAN0_MB22_DATA0()             bfin_read16(CAN0_MB22_DATA0)
+#define bfin_write_CAN0_MB22_DATA0(val)         bfin_write16(CAN0_MB22_DATA0, val)
+#define bfin_read_CAN0_MB22_DATA1()             bfin_read16(CAN0_MB22_DATA1)
+#define bfin_write_CAN0_MB22_DATA1(val)         bfin_write16(CAN0_MB22_DATA1, val)
+#define bfin_read_CAN0_MB22_DATA2()             bfin_read16(CAN0_MB22_DATA2)
+#define bfin_write_CAN0_MB22_DATA2(val)         bfin_write16(CAN0_MB22_DATA2, val)
+#define bfin_read_CAN0_MB22_DATA3()             bfin_read16(CAN0_MB22_DATA3)
+#define bfin_write_CAN0_MB22_DATA3(val)         bfin_write16(CAN0_MB22_DATA3, val)
+#define bfin_read_CAN0_MB22_LENGTH()            bfin_read16(CAN0_MB22_LENGTH)
+#define bfin_write_CAN0_MB22_LENGTH(val)        bfin_write16(CAN0_MB22_LENGTH, val)
+#define bfin_read_CAN0_MB22_TIMESTAMP()         bfin_read16(CAN0_MB22_TIMESTAMP)
+#define bfin_write_CAN0_MB22_TIMESTAMP(val)     bfin_write16(CAN0_MB22_TIMESTAMP, val)
+#define bfin_read_CAN0_MB22_ID0()               bfin_read16(CAN0_MB22_ID0)
+#define bfin_write_CAN0_MB22_ID0(val)           bfin_write16(CAN0_MB22_ID0, val)
+#define bfin_read_CAN0_MB22_ID1()               bfin_read16(CAN0_MB22_ID1)
+#define bfin_write_CAN0_MB22_ID1(val)           bfin_write16(CAN0_MB22_ID1, val)
+#define bfin_read_CAN0_MB23_DATA0()             bfin_read16(CAN0_MB23_DATA0)
+#define bfin_write_CAN0_MB23_DATA0(val)         bfin_write16(CAN0_MB23_DATA0, val)
+#define bfin_read_CAN0_MB23_DATA1()             bfin_read16(CAN0_MB23_DATA1)
+#define bfin_write_CAN0_MB23_DATA1(val)         bfin_write16(CAN0_MB23_DATA1, val)
+#define bfin_read_CAN0_MB23_DATA2()             bfin_read16(CAN0_MB23_DATA2)
+#define bfin_write_CAN0_MB23_DATA2(val)         bfin_write16(CAN0_MB23_DATA2, val)
+#define bfin_read_CAN0_MB23_DATA3()             bfin_read16(CAN0_MB23_DATA3)
+#define bfin_write_CAN0_MB23_DATA3(val)         bfin_write16(CAN0_MB23_DATA3, val)
+#define bfin_read_CAN0_MB23_LENGTH()            bfin_read16(CAN0_MB23_LENGTH)
+#define bfin_write_CAN0_MB23_LENGTH(val)        bfin_write16(CAN0_MB23_LENGTH, val)
+#define bfin_read_CAN0_MB23_TIMESTAMP()         bfin_read16(CAN0_MB23_TIMESTAMP)
+#define bfin_write_CAN0_MB23_TIMESTAMP(val)     bfin_write16(CAN0_MB23_TIMESTAMP, val)
+#define bfin_read_CAN0_MB23_ID0()               bfin_read16(CAN0_MB23_ID0)
+#define bfin_write_CAN0_MB23_ID0(val)           bfin_write16(CAN0_MB23_ID0, val)
+#define bfin_read_CAN0_MB23_ID1()               bfin_read16(CAN0_MB23_ID1)
+#define bfin_write_CAN0_MB23_ID1(val)           bfin_write16(CAN0_MB23_ID1, val)
+#define bfin_read_CAN0_MB24_DATA0()             bfin_read16(CAN0_MB24_DATA0)
+#define bfin_write_CAN0_MB24_DATA0(val)         bfin_write16(CAN0_MB24_DATA0, val)
+#define bfin_read_CAN0_MB24_DATA1()             bfin_read16(CAN0_MB24_DATA1)
+#define bfin_write_CAN0_MB24_DATA1(val)         bfin_write16(CAN0_MB24_DATA1, val)
+#define bfin_read_CAN0_MB24_DATA2()             bfin_read16(CAN0_MB24_DATA2)
+#define bfin_write_CAN0_MB24_DATA2(val)         bfin_write16(CAN0_MB24_DATA2, val)
+#define bfin_read_CAN0_MB24_DATA3()             bfin_read16(CAN0_MB24_DATA3)
+#define bfin_write_CAN0_MB24_DATA3(val)         bfin_write16(CAN0_MB24_DATA3, val)
+#define bfin_read_CAN0_MB24_LENGTH()            bfin_read16(CAN0_MB24_LENGTH)
+#define bfin_write_CAN0_MB24_LENGTH(val)        bfin_write16(CAN0_MB24_LENGTH, val)
+#define bfin_read_CAN0_MB24_TIMESTAMP()         bfin_read16(CAN0_MB24_TIMESTAMP)
+#define bfin_write_CAN0_MB24_TIMESTAMP(val)     bfin_write16(CAN0_MB24_TIMESTAMP, val)
+#define bfin_read_CAN0_MB24_ID0()               bfin_read16(CAN0_MB24_ID0)
+#define bfin_write_CAN0_MB24_ID0(val)           bfin_write16(CAN0_MB24_ID0, val)
+#define bfin_read_CAN0_MB24_ID1()               bfin_read16(CAN0_MB24_ID1)
+#define bfin_write_CAN0_MB24_ID1(val)           bfin_write16(CAN0_MB24_ID1, val)
+#define bfin_read_CAN0_MB25_DATA0()             bfin_read16(CAN0_MB25_DATA0)
+#define bfin_write_CAN0_MB25_DATA0(val)         bfin_write16(CAN0_MB25_DATA0, val)
+#define bfin_read_CAN0_MB25_DATA1()             bfin_read16(CAN0_MB25_DATA1)
+#define bfin_write_CAN0_MB25_DATA1(val)         bfin_write16(CAN0_MB25_DATA1, val)
+#define bfin_read_CAN0_MB25_DATA2()             bfin_read16(CAN0_MB25_DATA2)
+#define bfin_write_CAN0_MB25_DATA2(val)         bfin_write16(CAN0_MB25_DATA2, val)
+#define bfin_read_CAN0_MB25_DATA3()             bfin_read16(CAN0_MB25_DATA3)
+#define bfin_write_CAN0_MB25_DATA3(val)         bfin_write16(CAN0_MB25_DATA3, val)
+#define bfin_read_CAN0_MB25_LENGTH()            bfin_read16(CAN0_MB25_LENGTH)
+#define bfin_write_CAN0_MB25_LENGTH(val)        bfin_write16(CAN0_MB25_LENGTH, val)
+#define bfin_read_CAN0_MB25_TIMESTAMP()         bfin_read16(CAN0_MB25_TIMESTAMP)
+#define bfin_write_CAN0_MB25_TIMESTAMP(val)     bfin_write16(CAN0_MB25_TIMESTAMP, val)
+#define bfin_read_CAN0_MB25_ID0()               bfin_read16(CAN0_MB25_ID0)
+#define bfin_write_CAN0_MB25_ID0(val)           bfin_write16(CAN0_MB25_ID0, val)
+#define bfin_read_CAN0_MB25_ID1()               bfin_read16(CAN0_MB25_ID1)
+#define bfin_write_CAN0_MB25_ID1(val)           bfin_write16(CAN0_MB25_ID1, val)
+#define bfin_read_CAN0_MB26_DATA0()             bfin_read16(CAN0_MB26_DATA0)
+#define bfin_write_CAN0_MB26_DATA0(val)         bfin_write16(CAN0_MB26_DATA0, val)
+#define bfin_read_CAN0_MB26_DATA1()             bfin_read16(CAN0_MB26_DATA1)
+#define bfin_write_CAN0_MB26_DATA1(val)         bfin_write16(CAN0_MB26_DATA1, val)
+#define bfin_read_CAN0_MB26_DATA2()             bfin_read16(CAN0_MB26_DATA2)
+#define bfin_write_CAN0_MB26_DATA2(val)         bfin_write16(CAN0_MB26_DATA2, val)
+#define bfin_read_CAN0_MB26_DATA3()             bfin_read16(CAN0_MB26_DATA3)
+#define bfin_write_CAN0_MB26_DATA3(val)         bfin_write16(CAN0_MB26_DATA3, val)
+#define bfin_read_CAN0_MB26_LENGTH()            bfin_read16(CAN0_MB26_LENGTH)
+#define bfin_write_CAN0_MB26_LENGTH(val)        bfin_write16(CAN0_MB26_LENGTH, val)
+#define bfin_read_CAN0_MB26_TIMESTAMP()         bfin_read16(CAN0_MB26_TIMESTAMP)
+#define bfin_write_CAN0_MB26_TIMESTAMP(val)     bfin_write16(CAN0_MB26_TIMESTAMP, val)
+#define bfin_read_CAN0_MB26_ID0()               bfin_read16(CAN0_MB26_ID0)
+#define bfin_write_CAN0_MB26_ID0(val)           bfin_write16(CAN0_MB26_ID0, val)
+#define bfin_read_CAN0_MB26_ID1()               bfin_read16(CAN0_MB26_ID1)
+#define bfin_write_CAN0_MB26_ID1(val)           bfin_write16(CAN0_MB26_ID1, val)
+#define bfin_read_CAN0_MB27_DATA0()             bfin_read16(CAN0_MB27_DATA0)
+#define bfin_write_CAN0_MB27_DATA0(val)         bfin_write16(CAN0_MB27_DATA0, val)
+#define bfin_read_CAN0_MB27_DATA1()             bfin_read16(CAN0_MB27_DATA1)
+#define bfin_write_CAN0_MB27_DATA1(val)         bfin_write16(CAN0_MB27_DATA1, val)
+#define bfin_read_CAN0_MB27_DATA2()             bfin_read16(CAN0_MB27_DATA2)
+#define bfin_write_CAN0_MB27_DATA2(val)         bfin_write16(CAN0_MB27_DATA2, val)
+#define bfin_read_CAN0_MB27_DATA3()             bfin_read16(CAN0_MB27_DATA3)
+#define bfin_write_CAN0_MB27_DATA3(val)         bfin_write16(CAN0_MB27_DATA3, val)
+#define bfin_read_CAN0_MB27_LENGTH()            bfin_read16(CAN0_MB27_LENGTH)
+#define bfin_write_CAN0_MB27_LENGTH(val)        bfin_write16(CAN0_MB27_LENGTH, val)
+#define bfin_read_CAN0_MB27_TIMESTAMP()         bfin_read16(CAN0_MB27_TIMESTAMP)
+#define bfin_write_CAN0_MB27_TIMESTAMP(val)     bfin_write16(CAN0_MB27_TIMESTAMP, val)
+#define bfin_read_CAN0_MB27_ID0()               bfin_read16(CAN0_MB27_ID0)
+#define bfin_write_CAN0_MB27_ID0(val)           bfin_write16(CAN0_MB27_ID0, val)
+#define bfin_read_CAN0_MB27_ID1()               bfin_read16(CAN0_MB27_ID1)
+#define bfin_write_CAN0_MB27_ID1(val)           bfin_write16(CAN0_MB27_ID1, val)
+#define bfin_read_CAN0_MB28_DATA0()             bfin_read16(CAN0_MB28_DATA0)
+#define bfin_write_CAN0_MB28_DATA0(val)         bfin_write16(CAN0_MB28_DATA0, val)
+#define bfin_read_CAN0_MB28_DATA1()             bfin_read16(CAN0_MB28_DATA1)
+#define bfin_write_CAN0_MB28_DATA1(val)         bfin_write16(CAN0_MB28_DATA1, val)
+#define bfin_read_CAN0_MB28_DATA2()             bfin_read16(CAN0_MB28_DATA2)
+#define bfin_write_CAN0_MB28_DATA2(val)         bfin_write16(CAN0_MB28_DATA2, val)
+#define bfin_read_CAN0_MB28_DATA3()             bfin_read16(CAN0_MB28_DATA3)
+#define bfin_write_CAN0_MB28_DATA3(val)         bfin_write16(CAN0_MB28_DATA3, val)
+#define bfin_read_CAN0_MB28_LENGTH()            bfin_read16(CAN0_MB28_LENGTH)
+#define bfin_write_CAN0_MB28_LENGTH(val)        bfin_write16(CAN0_MB28_LENGTH, val)
+#define bfin_read_CAN0_MB28_TIMESTAMP()         bfin_read16(CAN0_MB28_TIMESTAMP)
+#define bfin_write_CAN0_MB28_TIMESTAMP(val)     bfin_write16(CAN0_MB28_TIMESTAMP, val)
+#define bfin_read_CAN0_MB28_ID0()               bfin_read16(CAN0_MB28_ID0)
+#define bfin_write_CAN0_MB28_ID0(val)           bfin_write16(CAN0_MB28_ID0, val)
+#define bfin_read_CAN0_MB28_ID1()               bfin_read16(CAN0_MB28_ID1)
+#define bfin_write_CAN0_MB28_ID1(val)           bfin_write16(CAN0_MB28_ID1, val)
+#define bfin_read_CAN0_MB29_DATA0()             bfin_read16(CAN0_MB29_DATA0)
+#define bfin_write_CAN0_MB29_DATA0(val)         bfin_write16(CAN0_MB29_DATA0, val)
+#define bfin_read_CAN0_MB29_DATA1()             bfin_read16(CAN0_MB29_DATA1)
+#define bfin_write_CAN0_MB29_DATA1(val)         bfin_write16(CAN0_MB29_DATA1, val)
+#define bfin_read_CAN0_MB29_DATA2()             bfin_read16(CAN0_MB29_DATA2)
+#define bfin_write_CAN0_MB29_DATA2(val)         bfin_write16(CAN0_MB29_DATA2, val)
+#define bfin_read_CAN0_MB29_DATA3()             bfin_read16(CAN0_MB29_DATA3)
+#define bfin_write_CAN0_MB29_DATA3(val)         bfin_write16(CAN0_MB29_DATA3, val)
+#define bfin_read_CAN0_MB29_LENGTH()            bfin_read16(CAN0_MB29_LENGTH)
+#define bfin_write_CAN0_MB29_LENGTH(val)        bfin_write16(CAN0_MB29_LENGTH, val)
+#define bfin_read_CAN0_MB29_TIMESTAMP()         bfin_read16(CAN0_MB29_TIMESTAMP)
+#define bfin_write_CAN0_MB29_TIMESTAMP(val)     bfin_write16(CAN0_MB29_TIMESTAMP, val)
+#define bfin_read_CAN0_MB29_ID0()               bfin_read16(CAN0_MB29_ID0)
+#define bfin_write_CAN0_MB29_ID0(val)           bfin_write16(CAN0_MB29_ID0, val)
+#define bfin_read_CAN0_MB29_ID1()               bfin_read16(CAN0_MB29_ID1)
+#define bfin_write_CAN0_MB29_ID1(val)           bfin_write16(CAN0_MB29_ID1, val)
+#define bfin_read_CAN0_MB30_DATA0()             bfin_read16(CAN0_MB30_DATA0)
+#define bfin_write_CAN0_MB30_DATA0(val)         bfin_write16(CAN0_MB30_DATA0, val)
+#define bfin_read_CAN0_MB30_DATA1()             bfin_read16(CAN0_MB30_DATA1)
+#define bfin_write_CAN0_MB30_DATA1(val)         bfin_write16(CAN0_MB30_DATA1, val)
+#define bfin_read_CAN0_MB30_DATA2()             bfin_read16(CAN0_MB30_DATA2)
+#define bfin_write_CAN0_MB30_DATA2(val)         bfin_write16(CAN0_MB30_DATA2, val)
+#define bfin_read_CAN0_MB30_DATA3()             bfin_read16(CAN0_MB30_DATA3)
+#define bfin_write_CAN0_MB30_DATA3(val)         bfin_write16(CAN0_MB30_DATA3, val)
+#define bfin_read_CAN0_MB30_LENGTH()            bfin_read16(CAN0_MB30_LENGTH)
+#define bfin_write_CAN0_MB30_LENGTH(val)        bfin_write16(CAN0_MB30_LENGTH, val)
+#define bfin_read_CAN0_MB30_TIMESTAMP()         bfin_read16(CAN0_MB30_TIMESTAMP)
+#define bfin_write_CAN0_MB30_TIMESTAMP(val)     bfin_write16(CAN0_MB30_TIMESTAMP, val)
+#define bfin_read_CAN0_MB30_ID0()               bfin_read16(CAN0_MB30_ID0)
+#define bfin_write_CAN0_MB30_ID0(val)           bfin_write16(CAN0_MB30_ID0, val)
+#define bfin_read_CAN0_MB30_ID1()               bfin_read16(CAN0_MB30_ID1)
+#define bfin_write_CAN0_MB30_ID1(val)           bfin_write16(CAN0_MB30_ID1, val)
+#define bfin_read_CAN0_MB31_DATA0()             bfin_read16(CAN0_MB31_DATA0)
+#define bfin_write_CAN0_MB31_DATA0(val)         bfin_write16(CAN0_MB31_DATA0, val)
+#define bfin_read_CAN0_MB31_DATA1()             bfin_read16(CAN0_MB31_DATA1)
+#define bfin_write_CAN0_MB31_DATA1(val)         bfin_write16(CAN0_MB31_DATA1, val)
+#define bfin_read_CAN0_MB31_DATA2()             bfin_read16(CAN0_MB31_DATA2)
+#define bfin_write_CAN0_MB31_DATA2(val)         bfin_write16(CAN0_MB31_DATA2, val)
+#define bfin_read_CAN0_MB31_DATA3()             bfin_read16(CAN0_MB31_DATA3)
+#define bfin_write_CAN0_MB31_DATA3(val)         bfin_write16(CAN0_MB31_DATA3, val)
+#define bfin_read_CAN0_MB31_LENGTH()            bfin_read16(CAN0_MB31_LENGTH)
+#define bfin_write_CAN0_MB31_LENGTH(val)        bfin_write16(CAN0_MB31_LENGTH, val)
+#define bfin_read_CAN0_MB31_TIMESTAMP()         bfin_read16(CAN0_MB31_TIMESTAMP)
+#define bfin_write_CAN0_MB31_TIMESTAMP(val)     bfin_write16(CAN0_MB31_TIMESTAMP, val)
+#define bfin_read_CAN0_MB31_ID0()               bfin_read16(CAN0_MB31_ID0)
+#define bfin_write_CAN0_MB31_ID0(val)           bfin_write16(CAN0_MB31_ID0, val)
+#define bfin_read_CAN0_MB31_ID1()               bfin_read16(CAN0_MB31_ID1)
+#define bfin_write_CAN0_MB31_ID1(val)           bfin_write16(CAN0_MB31_ID1, val)
+/* Counter Registers */
+#define bfin_read_CNT_CONFIG()          bfin_read16(CNT_CONFIG)
+#define bfin_write_CNT_CONFIG(val)      bfin_write16(CNT_CONFIG, val)
+#define bfin_read_CNT_IMASK()           bfin_read16(CNT_IMASK)
+#define bfin_write_CNT_IMASK(val)       bfin_write16(CNT_IMASK, val)
+#define bfin_read_CNT_STATUS()          bfin_read16(CNT_STATUS)
+#define bfin_write_CNT_STATUS(val)      bfin_write16(CNT_STATUS, val)
+#define bfin_read_CNT_COMMAND()         bfin_read16(CNT_COMMAND)
+#define bfin_write_CNT_COMMAND(val)     bfin_write16(CNT_COMMAND, val)
+#define bfin_read_CNT_DEBOUNCE()        bfin_read16(CNT_DEBOUNCE)
+#define bfin_write_CNT_DEBOUNCE(val)    bfin_write16(CNT_DEBOUNCE, val)
+#define bfin_read_CNT_COUNTER()         bfin_read32(CNT_COUNTER)
+#define bfin_write_CNT_COUNTER(val)     bfin_write32(CNT_COUNTER, val)
+#define bfin_read_CNT_MAX()             bfin_read32(CNT_MAX)
+#define bfin_write_CNT_MAX(val)         bfin_write32(CNT_MAX, val)
+#define bfin_read_CNT_MIN()             bfin_read32(CNT_MIN)
+#define bfin_write_CNT_MIN(val)         bfin_write32(CNT_MIN, val)
+/* RSI Register */
+#define bfin_read_RSI_CLK_CTL()         bfin_read16(RSI_CLK_CONTROL)
+#define bfin_write_RSI_CLK_CTL(val)     bfin_write16(RSI_CLK_CONTROL, val)
+#define bfin_read_RSI_ARGUMENT()        bfin_read32(RSI_ARGUMENT)
+#define bfin_write_RSI_ARGUMENT(val)    bfin_write32(RSI_ARGUMENT, val)
+#define bfin_read_RSI_COMMAND()         bfin_read16(RSI_COMMAND)
+#define bfin_write_RSI_COMMAND(val)     bfin_write16(RSI_COMMAND, val)
+#define bfin_read_RSI_RESP_CMD()        bfin_read16(RSI_RESP_CMD)
+#define bfin_write_RSI_RESP_CMD(val)    bfin_write16(RSI_RESP_CMD, val)
+#define bfin_read_RSI_RESPONSE0()       bfin_read32(RSI_RESPONSE0)
+#define bfin_write_RSI_RESPONSE0(val)   bfin_write32(RSI_RESPONSE0, val)
+#define bfin_read_RSI_RESPONSE1()       bfin_read32(RSI_RESPONSE1)
+#define bfin_write_RSI_RESPONSE1(val)   bfin_write32(RSI_RESPONSE1, val)
+#define bfin_read_RSI_RESPONSE2()       bfin_read32(RSI_RESPONSE2)
+#define bfin_write_RSI_RESPONSE2(val)   bfin_write32(RSI_RESPONSE2, val)
+#define bfin_read_RSI_RESPONSE3()       bfin_read32(RSI_RESPONSE3)
+#define bfin_write_RSI_RESPONSE3(val)   bfin_write32(RSI_RESPONSE3, val)
+#define bfin_read_RSI_DATA_TIMER()      bfin_read32(RSI_DATA_TIMER)
+#define bfin_write_RSI_DATA_TIMER(val)  bfin_write32(RSI_DATA_TIMER, val)
+#define bfin_read_RSI_DATA_LGTH()       bfin_read16(RSI_DATA_LGTH)
+#define bfin_write_RSI_DATA_LGTH(val)   bfin_write16(RSI_DATA_LGTH, val)
+#define bfin_read_RSI_DATA_CTL()        bfin_read16(RSI_DATA_CONTROL)
+#define bfin_write_RSI_DATA_CTL(val)    bfin_write16(RSI_DATA_CONTROL, val)
+#define bfin_read_RSI_DATA_CNT()        bfin_read16(RSI_DATA_CNT)
+#define bfin_write_RSI_DATA_CNT(val)    bfin_write16(RSI_DATA_CNT, val)
+#define bfin_read_RSI_STATUS()          bfin_read32(RSI_STATUS)
+#define bfin_write_RSI_STATUS(val)      bfin_write32(RSI_STATUS, val)
+#define bfin_read_RSI_STATUS_CLR()      bfin_read16(RSI_STATUSCL)
+#define bfin_write_RSI_STATUS_CLR(val)  bfin_write16(RSI_STATUSCL, val)
+#define bfin_read_RSI_MASK0()           bfin_read32(RSI_MASK0)
+#define bfin_write_RSI_MASK0(val)       bfin_write32(RSI_MASK0, val)
+#define bfin_read_RSI_MASK1()           bfin_read32(RSI_MASK1)
+#define bfin_write_RSI_MASK1(val)       bfin_write32(RSI_MASK1, val)
+#define bfin_read_RSI_FIFO_CNT()        bfin_read16(RSI_FIFO_CNT)
+#define bfin_write_RSI_FIFO_CNT(val)    bfin_write16(RSI_FIFO_CNT, val)
+#define bfin_read_RSI_CEATA_CONTROL()   bfin_read16(RSI_CEATA_CONTROL)
+#define bfin_write_RSI_CEATA_CONTROL(val)       bfin_write16(RSI_CEATA_CONTROL, val)
+#define bfin_read_RSI_BLKSZ()           bfin_read16(RSI_BLKSZ)
+#define bfin_write_RSI_BLKSZ(val)       bfin_write16(RSI_BLKSZ, val)
+#define bfin_read_RSI_FIFO()            bfin_read32(RSI_FIFO)
+#define bfin_write_RSI_FIFO(val)        bfin_write32(RSI_FIFO, val)
+#define bfin_read_RSI_E_STATUS()        bfin_read32(RSI_ESTAT)
+#define bfin_write_RSI_E_STATUS(val)    bfin_write32(RSI_ESTAT, val)
+#define bfin_read_RSI_E_MASK()          bfin_read32(RSI_EMASK)
+#define bfin_write_RSI_E_MASK(val)      bfin_write32(RSI_EMASK, val)
+#define bfin_read_RSI_CFG()             bfin_read16(RSI_CONFIG)
+#define bfin_write_RSI_CFG(val)         bfin_write16(RSI_CONFIG, val)
+#define bfin_read_RSI_RD_WAIT_EN()      bfin_read16(RSI_RD_WAIT_EN)
+#define bfin_write_RSI_RD_WAIT_EN(val)  bfin_write16(RSI_RD_WAIT_EN, val)
+#define bfin_read_RSI_PID0()            bfin_read16(RSI_PID0)
+#define bfin_write_RSI_PID0(val)        bfin_write16(RSI_PID0, val)
+#define bfin_read_RSI_PID1()            bfin_read16(RSI_PID1)
+#define bfin_write_RSI_PID1(val)        bfin_write16(RSI_PID1, val)
+#define bfin_read_RSI_PID2()            bfin_read16(RSI_PID2)
+#define bfin_write_RSI_PID2(val)        bfin_write16(RSI_PID2, val)
+#define bfin_read_RSI_PID3()            bfin_read16(RSI_PID3)
+#define bfin_write_RSI_PID3(val)        bfin_write16(RSI_PID3, val)
+/* usb register */
+#define bfin_read_USB_PLLOSC_CTRL()    bfin_read16(USB_PLL_OSC)
+#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLL_OSC, val)
+#define bfin_write_USB_VBUS_CTL(val) bfin_write8(USB_VBUS_CTL, val)
+#define bfin_write_USB_APHY_CNTRL(val) bfin_write8(USB_PHY_CTL, val)
+#define bfin_read_USB_APHY_CNTRL() bfin_read8(USB_PHY_CTL)
+#endif /* _CDEF_BF60X_H */
diff --git a/arch/blackfin/mach-bf609/include/mach/defBF609.h b/arch/blackfin/mach-bf609/include/mach/defBF609.h
new file mode 100644
index 000000000000..19690cc42113
--- /dev/null
+++ b/arch/blackfin/mach-bf609/include/mach/defBF609.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright 2011 Analog Devices Inc.
+ *
+ * Licensed under the Clear BSD license or the GPL-2 (or later)
+ */
+#ifndef _DEF_BF609_H
+#define _DEF_BF609_H
+/* Include defBF60x_base.h for the set of #defines that are common to all ADSP-BF60x processors */
+#include "defBF60x_base.h"
+/* The following are the #defines needed by ADSP-BF609 that are not in the common header */
+#endif /* _DEF_BF609_H */
diff --git a/arch/blackfin/mach-bf609/include/mach/defBF60x_base.h b/arch/blackfin/mach-bf609/include/mach/defBF60x_base.h
new file mode 100644
index 000000000000..6aac38544cc9
--- /dev/null
+++ b/arch/blackfin/mach-bf609/include/mach/defBF60x_base.h
@@ -0,0 +1,3587 @@
+/*
+ * Copyright 2011 Analog Devices Inc.
+ *
+ * Licensed under the Clear BSD license or the GPL-2 (or later)
+ */
+#ifndef _DEF_BF60X_H
+#define _DEF_BF60X_H
+/* ************************************************************** */
+/*   SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF60x    */
+/* ************************************************************** */
+/* =========================
+        CNT Registers
+   ========================= */
+/* =========================
+        CNT0
+   ========================= */
+#define CNT_CONFIG                 0xFFC00400         /* CNT0 Configuration Register */
+#define CNT_IMASK                  0xFFC00404         /* CNT0 Interrupt Mask Register */
+#define CNT_STATUS                 0xFFC00408         /* CNT0 Status Register */
+#define CNT_COMMAND                0xFFC0040C         /* CNT0 Command Register */
+#define CNT_DEBOUNCE               0xFFC00410         /* CNT0 Debounce Register */
+#define CNT_COUNTER                0xFFC00414         /* CNT0 Counter Register */
+#define CNT_MAX                    0xFFC00418         /* CNT0 Maximum Count Register */
+#define CNT_MIN                    0xFFC0041C         /* CNT0 Minimum Count Register */
+/* =========================
+        RSI Registers
+   ========================= */
+#define RSI_CLK_CONTROL            0xFFC00604         /* RSI0 Clock Control Register */
+#define RSI_ARGUMENT               0xFFC00608         /* RSI0 Argument Register */
+#define RSI_COMMAND                0xFFC0060C         /* RSI0 Command Register */
+#define RSI_RESP_CMD               0xFFC00610         /* RSI0 Response Command Register */
+#define RSI_RESPONSE0              0xFFC00614         /* RSI0 Response 0 Register */
+#define RSI_RESPONSE1              0xFFC00618         /* RSI0 Response 1 Register */
+#define RSI_RESPONSE2              0xFFC0061C         /* RSI0 Response 2 Register */
+#define RSI_RESPONSE3              0xFFC00620         /* RSI0 Response 3 Register */
+#define RSI_DATA_TIMER             0xFFC00624         /* RSI0 Data Timer Register */
+#define RSI_DATA_LGTH              0xFFC00628         /* RSI0 Data Length Register */
+#define RSI_DATA_CONTROL           0xFFC0062C         /* RSI0 Data Control Register */
+#define RSI_DATA_CNT               0xFFC00630         /* RSI0 Data Count Register */
+#define RSI_STATUS                 0xFFC00634         /* RSI0 Status Register */
+#define RSI_STATUSCL               0xFFC00638         /* RSI0 Status Clear Register */
+#define RSI_MASK0                  0xFFC0063C         /* RSI0 Interrupt 0 Mask Register */
+#define RSI_MASK1                  0xFFC00640         /* RSI0 Interrupt 1 Mask Register */
+#define RSI_FIFO_CNT               0xFFC00648         /* RSI0 FIFO Counter Register */
+#define RSI_CEATA_CONTROL          0xFFC0064C         /* RSI0 This register contains bit to dis CCS gen */
+#define RSI_BOOT_TCNTR             0xFFC00650         /* RSI0 Boot Timing Counter Register */
+#define RSI_BACK_TOUT              0xFFC00654         /* RSI0 Boot Acknowledge Timeout Register */
+#define RSI_SLP_WKUP_TOUT          0xFFC00658         /* RSI0 Sleep Wakeup Timeout Register */
+#define RSI_BLKSZ                  0xFFC0065C         /* RSI0 Block Size Register */
+#define RSI_FIFO                   0xFFC00680         /* RSI0 Data FIFO Register */
+#define RSI_ESTAT                  0xFFC006C0         /* RSI0 Exception Status Register */
+#define RSI_EMASK                  0xFFC006C4         /* RSI0 Exception Mask Register */
+#define RSI_CONFIG                 0xFFC006C8         /* RSI0 Configuration Register */
+#define RSI_RD_WAIT_EN             0xFFC006CC         /* RSI0 Read Wait Enable Register */
+#define RSI_PID0                   0xFFC006D0         /* RSI0 Peripheral Identification Register */
+#define RSI_PID1                   0xFFC006D4         /* RSI0 Peripheral Identification Register */
+#define RSI_PID2                   0xFFC006D8         /* RSI0 Peripheral Identification Register */
+#define RSI_PID3                   0xFFC006DC         /* RSI0 Peripheral Identification Register */
+/* =========================
+        CAN Registers
+   ========================= */
+/* =========================
+        CAN0
+   ========================= */
+#define CAN0_MC1                    0xFFC00A00         /* CAN0 Mailbox Configuration Register 1 */
+#define CAN0_MD1                    0xFFC00A04         /* CAN0 Mailbox Direction Register 1 */
+#define CAN0_TRS1                   0xFFC00A08         /* CAN0 Transmission Request Set Register 1 */
+#define CAN0_TRR1                   0xFFC00A0C         /* CAN0 Transmission Request Reset Register 1 */
+#define CAN0_TA1                    0xFFC00A10         /* CAN0 Transmission Acknowledge Register 1 */
+#define CAN0_AA1                    0xFFC00A14         /* CAN0 Abort Acknowledge Register 1 */
+#define CAN0_RMP1                   0xFFC00A18         /* CAN0 Receive Message Pending Register 1 */
+#define CAN0_RML1                   0xFFC00A1C         /* CAN0 Receive Message Lost Register 1 */
+#define CAN0_MBTIF1                 0xFFC00A20         /* CAN0 Mailbox Transmit Interrupt Flag Register 1 */
+#define CAN0_MBRIF1                 0xFFC00A24         /* CAN0 Mailbox Receive Interrupt Flag Register 1 */
+#define CAN0_MBIM1                  0xFFC00A28         /* CAN0 Mailbox Interrupt Mask Register 1 */
+#define CAN0_RFH1                   0xFFC00A2C         /* CAN0 Remote Frame Handling Register 1 */
+#define CAN0_OPSS1                  0xFFC00A30         /* CAN0 Overwrite Protection/Single Shot Transmission Register 1 */
+#define CAN0_MC2                    0xFFC00A40         /* CAN0 Mailbox Configuration Register 2 */
+#define CAN0_MD2                    0xFFC00A44         /* CAN0 Mailbox Direction Register 2 */
+#define CAN0_TRS2                   0xFFC00A48         /* CAN0 Transmission Request Set Register 2 */
+#define CAN0_TRR2                   0xFFC00A4C         /* CAN0 Transmission Request Reset Register 2 */
+#define CAN0_TA2                    0xFFC00A50         /* CAN0 Transmission Acknowledge Register 2 */
+#define CAN0_AA2                    0xFFC00A54         /* CAN0 Abort Acknowledge Register 2 */
+#define CAN0_RMP2                   0xFFC00A58         /* CAN0 Receive Message Pending Register 2 */
+#define CAN0_RML2                   0xFFC00A5C         /* CAN0 Receive Message Lost Register 2 */
+#define CAN0_MBTIF2                 0xFFC00A60         /* CAN0 Mailbox Transmit Interrupt Flag Register 2 */
+#define CAN0_MBRIF2                 0xFFC00A64         /* CAN0 Mailbox Receive Interrupt Flag Register 2 */
+#define CAN0_MBIM2                  0xFFC00A68         /* CAN0 Mailbox Interrupt Mask Register 2 */
+#define CAN0_RFH2                   0xFFC00A6C         /* CAN0 Remote Frame Handling Register 2 */
+#define CAN0_OPSS2                  0xFFC00A70         /* CAN0 Overwrite Protection/Single Shot Transmission Register 2 */
+#define CAN0_CLOCK                    0xFFC00A80         /* CAN0 Clock Register */
+#define CAN0_TIMING                 0xFFC00A84         /* CAN0 Timing Register */
+#define CAN0_DEBUG                    0xFFC00A88         /* CAN0 Debug Register */
+#define CAN0_STATUS                   0xFFC00A8C         /* CAN0 Status Register */
+#define CAN0_CEC                    0xFFC00A90         /* CAN0 Error Counter Register */
+#define CAN0_GIS                    0xFFC00A94         /* CAN0 Global CAN Interrupt Status */
+#define CAN0_GIM                    0xFFC00A98         /* CAN0 Global CAN Interrupt Mask */
+#define CAN0_GIF                    0xFFC00A9C         /* CAN0 Global CAN Interrupt Flag */
+#define CAN0_CONTROL                    0xFFC00AA0         /* CAN0 CAN Master Control Register */
+#define CAN0_INTR                    0xFFC00AA4         /* CAN0 Interrupt Pending Register */
+#define CAN0_MBTD                   0xFFC00AAC         /* CAN0 Temporary Mailbox Disable Register */
+#define CAN0_EWR                    0xFFC00AB0         /* CAN0 Error Counter Warning Level Register */
+#define CAN0_ESR                    0xFFC00AB4         /* CAN0 Error Status Register */
+#define CAN0_UCCNT                  0xFFC00AC4         /* CAN0 Universal Counter Register */
+#define CAN0_UCRC                   0xFFC00AC8         /* CAN0 Universal Counter Reload/Capture Register */
+#define CAN0_UCCNF                  0xFFC00ACC         /* CAN0 Universal Counter Configuration Mode Register */
+#define CAN0_AM00L                  0xFFC00B00         /* CAN0 Acceptance Mask Register (L) */
+#define CAN0_AM01L                  0xFFC00B08         /* CAN0 Acceptance Mask Register (L) */
+#define CAN0_AM02L                  0xFFC00B10         /* CAN0 Acceptance Mask Register (L) */
+#define CAN0_AM03L                  0xFFC00B18         /* CAN0 Acceptance Mask Register (L) */
+#define CAN0_AM04L                  0xFFC00B20         /* CAN0 Acceptance Mask Register (L) */
+#define CAN0_AM05L                  0xFFC00B28         /* CAN0 Acceptance Mask Register (L) */
+#define CAN0_AM06L                  0xFFC00B30         /* CAN0 Acceptance Mask Register (L) */
+#define CAN0_AM07L                  0xFFC00B38         /* CAN0 Acceptance Mask Register (L) */
+#define CAN0_AM08L                  0xFFC00B40         /* CAN0 Acceptance Mask Register (L) */
+#define CAN0_AM09L                  0xFFC00B48         /* CAN0 Acceptance Mask Register (L) */
+#define CAN0_AM10L                  0xFFC00B50         /* CAN0 Acceptance Mask Register (L) */
+#define CAN0_AM11L                  0xFFC00B58         /* CAN0 Acceptance Mask Register (L) */
+#define CAN0_AM12L                  0xFFC00B60         /* CAN0 Acceptance Mask Register (L) */
+#define CAN0_AM13L                  0xFFC00B68         /* CAN0 Acceptance Mask Register (L) */
+#define CAN0_AM14L                  0xFFC00B70         /* CAN0 Acceptance Mask Register (L) */
+#define CAN0_AM15L                  0xFFC00B78         /* CAN0 Acceptance Mask Register (L) */
+#define CAN0_AM16L                  0xFFC00B80         /* CAN0 Acceptance Mask Register (L) */
+#define CAN0_AM17L                  0xFFC00B88         /* CAN0 Acceptance Mask Register (L) */
+#define CAN0_AM18L                  0xFFC00B90         /* CAN0 Acceptance Mask Register (L) */
+#define CAN0_AM19L                  0xFFC00B98         /* CAN0 Acceptance Mask Register (L) */
+#define CAN0_AM20L                  0xFFC00BA0         /* CAN0 Acceptance Mask Register (L) */
+#define CAN0_AM21L                  0xFFC00BA8         /* CAN0 Acceptance Mask Register (L) */
+#define CAN0_AM22L                  0xFFC00BB0         /* CAN0 Acceptance Mask Register (L) */
+#define CAN0_AM23L                  0xFFC00BB8         /* CAN0 Acceptance Mask Register (L) */
+#define CAN0_AM24L                  0xFFC00BC0         /* CAN0 Acceptance Mask Register (L) */
+#define CAN0_AM25L                  0xFFC00BC8         /* CAN0 Acceptance Mask Register (L) */
+#define CAN0_AM26L                  0xFFC00BD0         /* CAN0 Acceptance Mask Register (L) */
+#define CAN0_AM27L                  0xFFC00BD8         /* CAN0 Acceptance Mask Register (L) */
+#define CAN0_AM28L                  0xFFC00BE0         /* CAN0 Acceptance Mask Register (L) */
+#define CAN0_AM29L                  0xFFC00BE8         /* CAN0 Acceptance Mask Register (L) */
+#define CAN0_AM30L                  0xFFC00BF0         /* CAN0 Acceptance Mask Register (L) */
+#define CAN0_AM31L                  0xFFC00BF8         /* CAN0 Acceptance Mask Register (L) */
+#define CAN0_AM00H                  0xFFC00B04         /* CAN0 Acceptance Mask Register (H) */
+#define CAN0_AM01H                  0xFFC00B0C         /* CAN0 Acceptance Mask Register (H) */
+#define CAN0_AM02H                  0xFFC00B14         /* CAN0 Acceptance Mask Register (H) */
+#define CAN0_AM03H                  0xFFC00B1C         /* CAN0 Acceptance Mask Register (H) */
+#define CAN0_AM04H                  0xFFC00B24         /* CAN0 Acceptance Mask Register (H) */
+#define CAN0_AM05H                  0xFFC00B2C         /* CAN0 Acceptance Mask Register (H) */
+#define CAN0_AM06H                  0xFFC00B34         /* CAN0 Acceptance Mask Register (H) */
+#define CAN0_AM07H                  0xFFC00B3C         /* CAN0 Acceptance Mask Register (H) */
+#define CAN0_AM08H                  0xFFC00B44         /* CAN0 Acceptance Mask Register (H) */
+#define CAN0_AM09H                  0xFFC00B4C         /* CAN0 Acceptance Mask Register (H) */
+#define CAN0_AM10H                  0xFFC00B54         /* CAN0 Acceptance Mask Register (H) */
+#define CAN0_AM11H                  0xFFC00B5C         /* CAN0 Acceptance Mask Register (H) */
+#define CAN0_AM12H                  0xFFC00B64         /* CAN0 Acceptance Mask Register (H) */
+#define CAN0_AM13H                  0xFFC00B6C         /* CAN0 Acceptance Mask Register (H) */
+#define CAN0_AM14H                  0xFFC00B74         /* CAN0 Acceptance Mask Register (H) */
+#define CAN0_AM15H                  0xFFC00B7C         /* CAN0 Acceptance Mask Register (H) */
+#define CAN0_AM16H                  0xFFC00B84         /* CAN0 Acceptance Mask Register (H) */
+#define CAN0_AM17H                  0xFFC00B8C         /* CAN0 Acceptance Mask Register (H) */
+#define CAN0_AM18H                  0xFFC00B94         /* CAN0 Acceptance Mask Register (H) */
+#define CAN0_AM19H                  0xFFC00B9C         /* CAN0 Acceptance Mask Register (H) */
+#define CAN0_AM20H                  0xFFC00BA4         /* CAN0 Acceptance Mask Register (H) */
+#define CAN0_AM21H                  0xFFC00BAC         /* CAN0 Acceptance Mask Register (H) */
+#define CAN0_AM22H                  0xFFC00BB4         /* CAN0 Acceptance Mask Register (H) */
+#define CAN0_AM23H                  0xFFC00BBC         /* CAN0 Acceptance Mask Register (H) */
+#define CAN0_AM24H                  0xFFC00BC4         /* CAN0 Acceptance Mask Register (H) */
+#define CAN0_AM25H                  0xFFC00BCC         /* CAN0 Acceptance Mask Register (H) */
+#define CAN0_AM26H                  0xFFC00BD4         /* CAN0 Acceptance Mask Register (H) */
+#define CAN0_AM27H                  0xFFC00BDC         /* CAN0 Acceptance Mask Register (H) */
+#define CAN0_AM28H                  0xFFC00BE4         /* CAN0 Acceptance Mask Register (H) */
+#define CAN0_AM29H                  0xFFC00BEC         /* CAN0 Acceptance Mask Register (H) */
+#define CAN0_AM30H                  0xFFC00BF4         /* CAN0 Acceptance Mask Register (H) */
+#define CAN0_AM31H                  0xFFC00BFC         /* CAN0 Acceptance Mask Register (H) */
+#define CAN0_MB00_DATA0             0xFFC00C00         /* CAN0 Mailbox Word 0 Register */
+#define CAN0_MB01_DATA0             0xFFC00C20         /* CAN0 Mailbox Word 0 Register */
+#define CAN0_MB02_DATA0             0xFFC00C40         /* CAN0 Mailbox Word 0 Register */
+#define CAN0_MB03_DATA0             0xFFC00C60         /* CAN0 Mailbox Word 0 Register */
+#define CAN0_MB04_DATA0             0xFFC00C80         /* CAN0 Mailbox Word 0 Register */
+#define CAN0_MB05_DATA0             0xFFC00CA0         /* CAN0 Mailbox Word 0 Register */
+#define CAN0_MB06_DATA0             0xFFC00CC0         /* CAN0 Mailbox Word 0 Register */
+#define CAN0_MB07_DATA0             0xFFC00CE0         /* CAN0 Mailbox Word 0 Register */
+#define CAN0_MB08_DATA0             0xFFC00D00         /* CAN0 Mailbox Word 0 Register */
+#define CAN0_MB09_DATA0             0xFFC00D20         /* CAN0 Mailbox Word 0 Register */
+#define CAN0_MB10_DATA0             0xFFC00D40         /* CAN0 Mailbox Word 0 Register */
+#define CAN0_MB11_DATA0             0xFFC00D60         /* CAN0 Mailbox Word 0 Register */
+#define CAN0_MB12_DATA0             0xFFC00D80         /* CAN0 Mailbox Word 0 Register */
+#define CAN0_MB13_DATA0             0xFFC00DA0         /* CAN0 Mailbox Word 0 Register */
+#define CAN0_MB14_DATA0             0xFFC00DC0         /* CAN0 Mailbox Word 0 Register */
+#define CAN0_MB15_DATA0             0xFFC00DE0         /* CAN0 Mailbox Word 0 Register */
+#define CAN0_MB16_DATA0             0xFFC00E00         /* CAN0 Mailbox Word 0 Register */
+#define CAN0_MB17_DATA0             0xFFC00E20         /* CAN0 Mailbox Word 0 Register */
+#define CAN0_MB18_DATA0             0xFFC00E40         /* CAN0 Mailbox Word 0 Register */
+#define CAN0_MB19_DATA0             0xFFC00E60         /* CAN0 Mailbox Word 0 Register */
+#define CAN0_MB20_DATA0             0xFFC00E80         /* CAN0 Mailbox Word 0 Register */
+#define CAN0_MB21_DATA0             0xFFC00EA0         /* CAN0 Mailbox Word 0 Register */
+#define CAN0_MB22_DATA0             0xFFC00EC0         /* CAN0 Mailbox Word 0 Register */
+#define CAN0_MB23_DATA0             0xFFC00EE0         /* CAN0 Mailbox Word 0 Register */
+#define CAN0_MB24_DATA0             0xFFC00F00         /* CAN0 Mailbox Word 0 Register */
+#define CAN0_MB25_DATA0             0xFFC00F20         /* CAN0 Mailbox Word 0 Register */
+#define CAN0_MB26_DATA0             0xFFC00F40         /* CAN0 Mailbox Word 0 Register */
+#define CAN0_MB27_DATA0             0xFFC00F60         /* CAN0 Mailbox Word 0 Register */
+#define CAN0_MB28_DATA0             0xFFC00F80         /* CAN0 Mailbox Word 0 Register */
+#define CAN0_MB29_DATA0             0xFFC00FA0         /* CAN0 Mailbox Word 0 Register */
+#define CAN0_MB30_DATA0             0xFFC00FC0         /* CAN0 Mailbox Word 0 Register */
+#define CAN0_MB31_DATA0             0xFFC00FE0         /* CAN0 Mailbox Word 0 Register */
+#define CAN0_MB00_DATA1             0xFFC00C04         /* CAN0 Mailbox Word 1 Register */
+#define CAN0_MB01_DATA1             0xFFC00C24         /* CAN0 Mailbox Word 1 Register */
+#define CAN0_MB02_DATA1             0xFFC00C44         /* CAN0 Mailbox Word 1 Register */
+#define CAN0_MB03_DATA1             0xFFC00C64         /* CAN0 Mailbox Word 1 Register */
+#define CAN0_MB04_DATA1             0xFFC00C84         /* CAN0 Mailbox Word 1 Register */
+#define CAN0_MB05_DATA1             0xFFC00CA4         /* CAN0 Mailbox Word 1 Register */
+#define CAN0_MB06_DATA1             0xFFC00CC4         /* CAN0 Mailbox Word 1 Register */
+#define CAN0_MB07_DATA1             0xFFC00CE4         /* CAN0 Mailbox Word 1 Register */
+#define CAN0_MB08_DATA1             0xFFC00D04         /* CAN0 Mailbox Word 1 Register */
+#define CAN0_MB09_DATA1             0xFFC00D24         /* CAN0 Mailbox Word 1 Register */
+#define CAN0_MB10_DATA1             0xFFC00D44         /* CAN0 Mailbox Word 1 Register */
+#define CAN0_MB11_DATA1             0xFFC00D64         /* CAN0 Mailbox Word 1 Register */
+#define CAN0_MB12_DATA1             0xFFC00D84         /* CAN0 Mailbox Word 1 Register */
+#define CAN0_MB13_DATA1             0xFFC00DA4         /* CAN0 Mailbox Word 1 Register */
+#define CAN0_MB14_DATA1             0xFFC00DC4         /* CAN0 Mailbox Word 1 Register */
+#define CAN0_MB15_DATA1             0xFFC00DE4         /* CAN0 Mailbox Word 1 Register */
+#define CAN0_MB16_DATA1             0xFFC00E04         /* CAN0 Mailbox Word 1 Register */
+#define CAN0_MB17_DATA1             0xFFC00E24         /* CAN0 Mailbox Word 1 Register */
+#define CAN0_MB18_DATA1             0xFFC00E44         /* CAN0 Mailbox Word 1 Register */
+#define CAN0_MB19_DATA1             0xFFC00E64         /* CAN0 Mailbox Word 1 Register */
+#define CAN0_MB20_DATA1             0xFFC00E84         /* CAN0 Mailbox Word 1 Register */
+#define CAN0_MB21_DATA1             0xFFC00EA4         /* CAN0 Mailbox Word 1 Register */
+#define CAN0_MB22_DATA1             0xFFC00EC4         /* CAN0 Mailbox Word 1 Register */
+#define CAN0_MB23_DATA1             0xFFC00EE4         /* CAN0 Mailbox Word 1 Register */
+#define CAN0_MB24_DATA1             0xFFC00F04         /* CAN0 Mailbox Word 1 Register */
+#define CAN0_MB25_DATA1             0xFFC00F24         /* CAN0 Mailbox Word 1 Register */
+#define CAN0_MB26_DATA1             0xFFC00F44         /* CAN0 Mailbox Word 1 Register */
+#define CAN0_MB27_DATA1             0xFFC00F64         /* CAN0 Mailbox Word 1 Register */
+#define CAN0_MB28_DATA1             0xFFC00F84         /* CAN0 Mailbox Word 1 Register */
+#define CAN0_MB29_DATA1             0xFFC00FA4         /* CAN0 Mailbox Word 1 Register */
+#define CAN0_MB30_DATA1             0xFFC00FC4         /* CAN0 Mailbox Word 1 Register */
+#define CAN0_MB31_DATA1             0xFFC00FE4         /* CAN0 Mailbox Word 1 Register */
+#define CAN0_MB00_DATA2             0xFFC00C08         /* CAN0 Mailbox Word 2 Register */
+#define CAN0_MB01_DATA2             0xFFC00C28         /* CAN0 Mailbox Word 2 Register */
+#define CAN0_MB02_DATA2             0xFFC00C48         /* CAN0 Mailbox Word 2 Register */
+#define CAN0_MB03_DATA2             0xFFC00C68         /* CAN0 Mailbox Word 2 Register */
+#define CAN0_MB04_DATA2             0xFFC00C88         /* CAN0 Mailbox Word 2 Register */
+#define CAN0_MB05_DATA2             0xFFC00CA8         /* CAN0 Mailbox Word 2 Register */
+#define CAN0_MB06_DATA2             0xFFC00CC8         /* CAN0 Mailbox Word 2 Register */
+#define CAN0_MB07_DATA2             0xFFC00CE8         /* CAN0 Mailbox Word 2 Register */
+#define CAN0_MB08_DATA2             0xFFC00D08         /* CAN0 Mailbox Word 2 Register */
+#define CAN0_MB09_DATA2             0xFFC00D28         /* CAN0 Mailbox Word 2 Register */
+#define CAN0_MB10_DATA2             0xFFC00D48         /* CAN0 Mailbox Word 2 Register */
+#define CAN0_MB11_DATA2             0xFFC00D68         /* CAN0 Mailbox Word 2 Register */
+#define CAN0_MB12_DATA2             0xFFC00D88         /* CAN0 Mailbox Word 2 Register */
+#define CAN0_MB13_DATA2             0xFFC00DA8         /* CAN0 Mailbox Word 2 Register */
+#define CAN0_MB14_DATA2             0xFFC00DC8         /* CAN0 Mailbox Word 2 Register */
+#define CAN0_MB15_DATA2             0xFFC00DE8         /* CAN0 Mailbox Word 2 Register */
+#define CAN0_MB16_DATA2             0xFFC00E08         /* CAN0 Mailbox Word 2 Register */
+#define CAN0_MB17_DATA2             0xFFC00E28         /* CAN0 Mailbox Word 2 Register */
+#define CAN0_MB18_DATA2             0xFFC00E48         /* CAN0 Mailbox Word 2 Register */
+#define CAN0_MB19_DATA2             0xFFC00E68         /* CAN0 Mailbox Word 2 Register */
+#define CAN0_MB20_DATA2             0xFFC00E88         /* CAN0 Mailbox Word 2 Register */
+#define CAN0_MB21_DATA2             0xFFC00EA8         /* CAN0 Mailbox Word 2 Register */
+#define CAN0_MB22_DATA2             0xFFC00EC8         /* CAN0 Mailbox Word 2 Register */
+#define CAN0_MB23_DATA2             0xFFC00EE8         /* CAN0 Mailbox Word 2 Register */
+#define CAN0_MB24_DATA2             0xFFC00F08         /* CAN0 Mailbox Word 2 Register */
+#define CAN0_MB25_DATA2             0xFFC00F28         /* CAN0 Mailbox Word 2 Register */
+#define CAN0_MB26_DATA2             0xFFC00F48         /* CAN0 Mailbox Word 2 Register */
+#define CAN0_MB27_DATA2             0xFFC00F68         /* CAN0 Mailbox Word 2 Register */
+#define CAN0_MB28_DATA2             0xFFC00F88         /* CAN0 Mailbox Word 2 Register */
+#define CAN0_MB29_DATA2             0xFFC00FA8         /* CAN0 Mailbox Word 2 Register */
+#define CAN0_MB30_DATA2             0xFFC00FC8         /* CAN0 Mailbox Word 2 Register */
+#define CAN0_MB31_DATA2             0xFFC00FE8         /* CAN0 Mailbox Word 2 Register */
+#define CAN0_MB00_DATA3             0xFFC00C0C         /* CAN0 Mailbox Word 3 Register */
+#define CAN0_MB01_DATA3             0xFFC00C2C         /* CAN0 Mailbox Word 3 Register */
+#define CAN0_MB02_DATA3             0xFFC00C4C         /* CAN0 Mailbox Word 3 Register */
+#define CAN0_MB03_DATA3             0xFFC00C6C         /* CAN0 Mailbox Word 3 Register */
+#define CAN0_MB04_DATA3             0xFFC00C8C         /* CAN0 Mailbox Word 3 Register */
+#define CAN0_MB05_DATA3             0xFFC00CAC         /* CAN0 Mailbox Word 3 Register */
+#define CAN0_MB06_DATA3             0xFFC00CCC         /* CAN0 Mailbox Word 3 Register */
+#define CAN0_MB07_DATA3             0xFFC00CEC         /* CAN0 Mailbox Word 3 Register */
+#define CAN0_MB08_DATA3             0xFFC00D0C         /* CAN0 Mailbox Word 3 Register */
+#define CAN0_MB09_DATA3             0xFFC00D2C         /* CAN0 Mailbox Word 3 Register */
+#define CAN0_MB10_DATA3             0xFFC00D4C         /* CAN0 Mailbox Word 3 Register */
+#define CAN0_MB11_DATA3             0xFFC00D6C         /* CAN0 Mailbox Word 3 Register */
+#define CAN0_MB12_DATA3             0xFFC00D8C         /* CAN0 Mailbox Word 3 Register */
+#define CAN0_MB13_DATA3             0xFFC00DAC         /* CAN0 Mailbox Word 3 Register */
+#define CAN0_MB14_DATA3             0xFFC00DCC         /* CAN0 Mailbox Word 3 Register */
+#define CAN0_MB15_DATA3             0xFFC00DEC         /* CAN0 Mailbox Word 3 Register */
+#define CAN0_MB16_DATA3             0xFFC00E0C         /* CAN0 Mailbox Word 3 Register */
+#define CAN0_MB17_DATA3             0xFFC00E2C         /* CAN0 Mailbox Word 3 Register */
+#define CAN0_MB18_DATA3             0xFFC00E4C         /* CAN0 Mailbox Word 3 Register */
+#define CAN0_MB19_DATA3             0xFFC00E6C         /* CAN0 Mailbox Word 3 Register */
+#define CAN0_MB20_DATA3             0xFFC00E8C         /* CAN0 Mailbox Word 3 Register */
+#define CAN0_MB21_DATA3             0xFFC00EAC         /* CAN0 Mailbox Word 3 Register */
+#define CAN0_MB22_DATA3             0xFFC00ECC         /* CAN0 Mailbox Word 3 Register */
+#define CAN0_MB23_DATA3             0xFFC00EEC         /* CAN0 Mailbox Word 3 Register */
+#define CAN0_MB24_DATA3             0xFFC00F0C         /* CAN0 Mailbox Word 3 Register */
+#define CAN0_MB25_DATA3             0xFFC00F2C         /* CAN0 Mailbox Word 3 Register */
+#define CAN0_MB26_DATA3             0xFFC00F4C         /* CAN0 Mailbox Word 3 Register */
+#define CAN0_MB27_DATA3             0xFFC00F6C         /* CAN0 Mailbox Word 3 Register */
+#define CAN0_MB28_DATA3             0xFFC00F8C         /* CAN0 Mailbox Word 3 Register */
+#define CAN0_MB29_DATA3             0xFFC00FAC         /* CAN0 Mailbox Word 3 Register */
+#define CAN0_MB30_DATA3             0xFFC00FCC         /* CAN0 Mailbox Word 3 Register */
+#define CAN0_MB31_DATA3             0xFFC00FEC         /* CAN0 Mailbox Word 3 Register */
+#define CAN0_MB00_LENGTH            0xFFC00C10         /* CAN0 Mailbox Word 4 Register */
+#define CAN0_MB01_LENGTH            0xFFC00C30         /* CAN0 Mailbox Word 4 Register */
+#define CAN0_MB02_LENGTH            0xFFC00C50         /* CAN0 Mailbox Word 4 Register */
+#define CAN0_MB03_LENGTH            0xFFC00C70         /* CAN0 Mailbox Word 4 Register */
+#define CAN0_MB04_LENGTH            0xFFC00C90         /* CAN0 Mailbox Word 4 Register */
+#define CAN0_MB05_LENGTH            0xFFC00CB0         /* CAN0 Mailbox Word 4 Register */
+#define CAN0_MB06_LENGTH            0xFFC00CD0         /* CAN0 Mailbox Word 4 Register */
+#define CAN0_MB07_LENGTH            0xFFC00CF0         /* CAN0 Mailbox Word 4 Register */
+#define CAN0_MB08_LENGTH            0xFFC00D10         /* CAN0 Mailbox Word 4 Register */
+#define CAN0_MB09_LENGTH            0xFFC00D30         /* CAN0 Mailbox Word 4 Register */
+#define CAN0_MB10_LENGTH            0xFFC00D50         /* CAN0 Mailbox Word 4 Register */
+#define CAN0_MB11_LENGTH            0xFFC00D70         /* CAN0 Mailbox Word 4 Register */
+#define CAN0_MB12_LENGTH            0xFFC00D90         /* CAN0 Mailbox Word 4 Register */
+#define CAN0_MB13_LENGTH            0xFFC00DB0         /* CAN0 Mailbox Word 4 Register */
+#define CAN0_MB14_LENGTH            0xFFC00DD0         /* CAN0 Mailbox Word 4 Register */
+#define CAN0_MB15_LENGTH            0xFFC00DF0         /* CAN0 Mailbox Word 4 Register */
+#define CAN0_MB16_LENGTH            0xFFC00E10         /* CAN0 Mailbox Word 4 Register */
+#define CAN0_MB17_LENGTH            0xFFC00E30         /* CAN0 Mailbox Word 4 Register */
+#define CAN0_MB18_LENGTH            0xFFC00E50         /* CAN0 Mailbox Word 4 Register */
+#define CAN0_MB19_LENGTH            0xFFC00E70         /* CAN0 Mailbox Word 4 Register */
+#define CAN0_MB20_LENGTH            0xFFC00E90         /* CAN0 Mailbox Word 4 Register */
+#define CAN0_MB21_LENGTH            0xFFC00EB0         /* CAN0 Mailbox Word 4 Register */
+#define CAN0_MB22_LENGTH            0xFFC00ED0         /* CAN0 Mailbox Word 4 Register */
+#define CAN0_MB23_LENGTH            0xFFC00EF0         /* CAN0 Mailbox Word 4 Register */
+#define CAN0_MB24_LENGTH            0xFFC00F10         /* CAN0 Mailbox Word 4 Register */
+#define CAN0_MB25_LENGTH            0xFFC00F30         /* CAN0 Mailbox Word 4 Register */
+#define CAN0_MB26_LENGTH            0xFFC00F50         /* CAN0 Mailbox Word 4 Register */
+#define CAN0_MB27_LENGTH            0xFFC00F70         /* CAN0 Mailbox Word 4 Register */
+#define CAN0_MB28_LENGTH            0xFFC00F90         /* CAN0 Mailbox Word 4 Register */
+#define CAN0_MB29_LENGTH            0xFFC00FB0         /* CAN0 Mailbox Word 4 Register */
+#define CAN0_MB30_LENGTH            0xFFC00FD0         /* CAN0 Mailbox Word 4 Register */
+#define CAN0_MB31_LENGTH            0xFFC00FF0         /* CAN0 Mailbox Word 4 Register */
+#define CAN0_MB00_TIMESTAMP         0xFFC00C14         /* CAN0 Mailbox Word 5 Register */
+#define CAN0_MB01_TIMESTAMP         0xFFC00C34         /* CAN0 Mailbox Word 5 Register */
+#define CAN0_MB02_TIMESTAMP         0xFFC00C54         /* CAN0 Mailbox Word 5 Register */
+#define CAN0_MB03_TIMESTAMP         0xFFC00C74         /* CAN0 Mailbox Word 5 Register */
+#define CAN0_MB04_TIMESTAMP         0xFFC00C94         /* CAN0 Mailbox Word 5 Register */
+#define CAN0_MB05_TIMESTAMP         0xFFC00CB4         /* CAN0 Mailbox Word 5 Register */
+#define CAN0_MB06_TIMESTAMP         0xFFC00CD4         /* CAN0 Mailbox Word 5 Register */
+#define CAN0_MB07_TIMESTAMP         0xFFC00CF4         /* CAN0 Mailbox Word 5 Register */
+#define CAN0_MB08_TIMESTAMP         0xFFC00D14         /* CAN0 Mailbox Word 5 Register */
+#define CAN0_MB09_TIMESTAMP         0xFFC00D34         /* CAN0 Mailbox Word 5 Register */
+#define CAN0_MB10_TIMESTAMP         0xFFC00D54         /* CAN0 Mailbox Word 5 Register */
+#define CAN0_MB11_TIMESTAMP         0xFFC00D74         /* CAN0 Mailbox Word 5 Register */
+#define CAN0_MB12_TIMESTAMP         0xFFC00D94         /* CAN0 Mailbox Word 5 Register */
+#define CAN0_MB13_TIMESTAMP         0xFFC00DB4         /* CAN0 Mailbox Word 5 Register */
+#define CAN0_MB14_TIMESTAMP         0xFFC00DD4         /* CAN0 Mailbox Word 5 Register */
+#define CAN0_MB15_TIMESTAMP         0xFFC00DF4         /* CAN0 Mailbox Word 5 Register */
+#define CAN0_MB16_TIMESTAMP         0xFFC00E14         /* CAN0 Mailbox Word 5 Register */
+#define CAN0_MB17_TIMESTAMP         0xFFC00E34         /* CAN0 Mailbox Word 5 Register */
+#define CAN0_MB18_TIMESTAMP         0xFFC00E54         /* CAN0 Mailbox Word 5 Register */
+#define CAN0_MB19_TIMESTAMP         0xFFC00E74         /* CAN0 Mailbox Word 5 Register */
+#define CAN0_MB20_TIMESTAMP         0xFFC00E94         /* CAN0 Mailbox Word 5 Register */
+#define CAN0_MB21_TIMESTAMP         0xFFC00EB4         /* CAN0 Mailbox Word 5 Register */
+#define CAN0_MB22_TIMESTAMP         0xFFC00ED4         /* CAN0 Mailbox Word 5 Register */
+#define CAN0_MB23_TIMESTAMP         0xFFC00EF4         /* CAN0 Mailbox Word 5 Register */
+#define CAN0_MB24_TIMESTAMP         0xFFC00F14         /* CAN0 Mailbox Word 5 Register */
+#define CAN0_MB25_TIMESTAMP         0xFFC00F34         /* CAN0 Mailbox Word 5 Register */
+#define CAN0_MB26_TIMESTAMP         0xFFC00F54         /* CAN0 Mailbox Word 5 Register */
+#define CAN0_MB27_TIMESTAMP         0xFFC00F74         /* CAN0 Mailbox Word 5 Register */
+#define CAN0_MB28_TIMESTAMP         0xFFC00F94         /* CAN0 Mailbox Word 5 Register */
+#define CAN0_MB29_TIMESTAMP         0xFFC00FB4         /* CAN0 Mailbox Word 5 Register */
+#define CAN0_MB30_TIMESTAMP         0xFFC00FD4         /* CAN0 Mailbox Word 5 Register */
+#define CAN0_MB31_TIMESTAMP         0xFFC00FF4         /* CAN0 Mailbox Word 5 Register */
+#define CAN0_MB00_ID0               0xFFC00C18         /* CAN0 Mailbox Word 6 Register */
+#define CAN0_MB01_ID0               0xFFC00C38         /* CAN0 Mailbox Word 6 Register */
+#define CAN0_MB02_ID0               0xFFC00C58         /* CAN0 Mailbox Word 6 Register */
+#define CAN0_MB03_ID0               0xFFC00C78         /* CAN0 Mailbox Word 6 Register */
+#define CAN0_MB04_ID0               0xFFC00C98         /* CAN0 Mailbox Word 6 Register */
+#define CAN0_MB05_ID0               0xFFC00CB8         /* CAN0 Mailbox Word 6 Register */
+#define CAN0_MB06_ID0               0xFFC00CD8         /* CAN0 Mailbox Word 6 Register */
+#define CAN0_MB07_ID0               0xFFC00CF8         /* CAN0 Mailbox Word 6 Register */
+#define CAN0_MB08_ID0               0xFFC00D18         /* CAN0 Mailbox Word 6 Register */
+#define CAN0_MB09_ID0               0xFFC00D38         /* CAN0 Mailbox Word 6 Register */
+#define CAN0_MB10_ID0               0xFFC00D58         /* CAN0 Mailbox Word 6 Register */
+#define CAN0_MB11_ID0               0xFFC00D78         /* CAN0 Mailbox Word 6 Register */
+#define CAN0_MB12_ID0               0xFFC00D98         /* CAN0 Mailbox Word 6 Register */
+#define CAN0_MB13_ID0               0xFFC00DB8         /* CAN0 Mailbox Word 6 Register */
+#define CAN0_MB14_ID0               0xFFC00DD8         /* CAN0 Mailbox Word 6 Register */
+#define CAN0_MB15_ID0               0xFFC00DF8         /* CAN0 Mailbox Word 6 Register */
+#define CAN0_MB16_ID0               0xFFC00E18         /* CAN0 Mailbox Word 6 Register */
+#define CAN0_MB17_ID0               0xFFC00E38         /* CAN0 Mailbox Word 6 Register */
+#define CAN0_MB18_ID0               0xFFC00E58         /* CAN0 Mailbox Word 6 Register */
+#define CAN0_MB19_ID0               0xFFC00E78         /* CAN0 Mailbox Word 6 Register */
+#define CAN0_MB20_ID0               0xFFC00E98         /* CAN0 Mailbox Word 6 Register */
+#define CAN0_MB21_ID0               0xFFC00EB8         /* CAN0 Mailbox Word 6 Register */
+#define CAN0_MB22_ID0               0xFFC00ED8         /* CAN0 Mailbox Word 6 Register */
+#define CAN0_MB23_ID0               0xFFC00EF8         /* CAN0 Mailbox Word 6 Register */
+#define CAN0_MB24_ID0               0xFFC00F18         /* CAN0 Mailbox Word 6 Register */
+#define CAN0_MB25_ID0               0xFFC00F38         /* CAN0 Mailbox Word 6 Register */
+#define CAN0_MB26_ID0               0xFFC00F58         /* CAN0 Mailbox Word 6 Register */
+#define CAN0_MB27_ID0               0xFFC00F78         /* CAN0 Mailbox Word 6 Register */
+#define CAN0_MB28_ID0               0xFFC00F98         /* CAN0 Mailbox Word 6 Register */
+#define CAN0_MB29_ID0               0xFFC00FB8         /* CAN0 Mailbox Word 6 Register */
+#define CAN0_MB30_ID0               0xFFC00FD8         /* CAN0 Mailbox Word 6 Register */
+#define CAN0_MB31_ID0               0xFFC00FF8         /* CAN0 Mailbox Word 6 Register */
+#define CAN0_MB00_ID1               0xFFC00C1C         /* CAN0 Mailbox Word 7 Register */
+#define CAN0_MB01_ID1               0xFFC00C3C         /* CAN0 Mailbox Word 7 Register */
+#define CAN0_MB02_ID1               0xFFC00C5C         /* CAN0 Mailbox Word 7 Register */
+#define CAN0_MB03_ID1               0xFFC00C7C         /* CAN0 Mailbox Word 7 Register */
+#define CAN0_MB04_ID1               0xFFC00C9C         /* CAN0 Mailbox Word 7 Register */
+#define CAN0_MB05_ID1               0xFFC00CBC         /* CAN0 Mailbox Word 7 Register */
+#define CAN0_MB06_ID1               0xFFC00CDC         /* CAN0 Mailbox Word 7 Register */
+#define CAN0_MB07_ID1               0xFFC00CFC         /* CAN0 Mailbox Word 7 Register */
+#define CAN0_MB08_ID1               0xFFC00D1C         /* CAN0 Mailbox Word 7 Register */
+#define CAN0_MB09_ID1               0xFFC00D3C         /* CAN0 Mailbox Word 7 Register */
+#define CAN0_MB10_ID1               0xFFC00D5C         /* CAN0 Mailbox Word 7 Register */
+#define CAN0_MB11_ID1               0xFFC00D7C         /* CAN0 Mailbox Word 7 Register */
+#define CAN0_MB12_ID1               0xFFC00D9C         /* CAN0 Mailbox Word 7 Register */
+#define CAN0_MB13_ID1               0xFFC00DBC         /* CAN0 Mailbox Word 7 Register */
+#define CAN0_MB14_ID1               0xFFC00DDC         /* CAN0 Mailbox Word 7 Register */
+#define CAN0_MB15_ID1               0xFFC00DFC         /* CAN0 Mailbox Word 7 Register */
+#define CAN0_MB16_ID1               0xFFC00E1C         /* CAN0 Mailbox Word 7 Register */
+#define CAN0_MB17_ID1               0xFFC00E3C         /* CAN0 Mailbox Word 7 Register */
+#define CAN0_MB18_ID1               0xFFC00E5C         /* CAN0 Mailbox Word 7 Register */
+#define CAN0_MB19_ID1               0xFFC00E7C         /* CAN0 Mailbox Word 7 Register */
+#define CAN0_MB20_ID1               0xFFC00E9C         /* CAN0 Mailbox Word 7 Register */
+#define CAN0_MB21_ID1               0xFFC00EBC         /* CAN0 Mailbox Word 7 Register */
+#define CAN0_MB22_ID1               0xFFC00EDC         /* CAN0 Mailbox Word 7 Register */
+#define CAN0_MB23_ID1               0xFFC00EFC         /* CAN0 Mailbox Word 7 Register */
+#define CAN0_MB24_ID1               0xFFC00F1C         /* CAN0 Mailbox Word 7 Register */
+#define CAN0_MB25_ID1               0xFFC00F3C         /* CAN0 Mailbox Word 7 Register */
+#define CAN0_MB26_ID1               0xFFC00F5C         /* CAN0 Mailbox Word 7 Register */
+#define CAN0_MB27_ID1               0xFFC00F7C         /* CAN0 Mailbox Word 7 Register */
+#define CAN0_MB28_ID1               0xFFC00F9C         /* CAN0 Mailbox Word 7 Register */
+#define CAN0_MB29_ID1               0xFFC00FBC         /* CAN0 Mailbox Word 7 Register */
+#define CAN0_MB30_ID1               0xFFC00FDC         /* CAN0 Mailbox Word 7 Register */
+#define CAN0_MB31_ID1               0xFFC00FFC         /* CAN0 Mailbox Word 7 Register */
+/* =========================
+        LINK PORT Registers
+   ========================= */
+#define LP0_CTL                     0xFFC01000         /* LP0 Control Register */
+#define LP0_STAT                    0xFFC01004         /* LP0 Status Register */
+#define LP0_DIV                     0xFFC01008         /* LP0 Clock Divider Value */
+#define LP0_CNT                     0xFFC0100C         /* LP0 Current Count Value of Clock Divider */
+#define LP0_TX                      0xFFC01010         /* LP0 Transmit Buffer */
+#define LP0_RX                      0xFFC01014         /* LP0 Receive Buffer */
+#define LP0_TXIN_SHDW               0xFFC01018         /* LP0 Shadow Input Transmit Buffer */
+#define LP0_TXOUT_SHDW              0xFFC0101C         /* LP0 Shadow Output Transmit Buffer */
+#define LP1_CTL                     0xFFC01100         /* LP1 Control Register */
+#define LP1_STAT                    0xFFC01104         /* LP1 Status Register */
+#define LP1_DIV                     0xFFC01108         /* LP1 Clock Divider Value */
+#define LP1_CNT                     0xFFC0110C         /* LP1 Current Count Value of Clock Divider */
+#define LP1_TX                      0xFFC01110         /* LP1 Transmit Buffer */
+#define LP1_RX                      0xFFC01114         /* LP1 Receive Buffer */
+#define LP1_TXIN_SHDW               0xFFC01118         /* LP1 Shadow Input Transmit Buffer */
+#define LP1_TXOUT_SHDW              0xFFC0111C         /* LP1 Shadow Output Transmit Buffer */
+#define LP2_CTL                     0xFFC01200         /* LP2 Control Register */
+#define LP2_STAT                    0xFFC01204         /* LP2 Status Register */
+#define LP2_DIV                     0xFFC01208         /* LP2 Clock Divider Value */
+#define LP2_CNT                     0xFFC0120C         /* LP2 Current Count Value of Clock Divider */
+#define LP2_TX                      0xFFC01210         /* LP2 Transmit Buffer */
+#define LP2_RX                      0xFFC01214         /* LP2 Receive Buffer */
+#define LP2_TXIN_SHDW               0xFFC01218         /* LP2 Shadow Input Transmit Buffer */
+#define LP2_TXOUT_SHDW              0xFFC0121C         /* LP2 Shadow Output Transmit Buffer */
+#define LP3_CTL                     0xFFC01300         /* LP3 Control Register */
+#define LP3_STAT                    0xFFC01304         /* LP3 Status Register */
+#define LP3_DIV                     0xFFC01308         /* LP3 Clock Divider Value */
+#define LP3_CNT                     0xFFC0130C         /* LP3 Current Count Value of Clock Divider */
+#define LP3_TX                      0xFFC01310         /* LP3 Transmit Buffer */
+#define LP3_RX                      0xFFC01314         /* LP3 Receive Buffer */
+#define LP3_TXIN_SHDW               0xFFC01318         /* LP3 Shadow Input Transmit Buffer */
+#define LP3_TXOUT_SHDW              0xFFC0131C         /* LP3 Shadow Output Transmit Buffer */
+/* =========================
+        TIMER Registers
+   ========================= */
+#define TIMER_REVID                0xFFC01400         /* GPTIMER Timer IP Version ID */
+#define TIMER_RUN                  0xFFC01404         /* GPTIMER Timer Run Register */
+#define TIMER_RUN_SET              0xFFC01408         /* GPTIMER Run Register Alias to Set */
+#define TIMER_RUN_CLR              0xFFC0140C         /* GPTIMER Run Register Alias to Clear */
+#define TIMER_STOP_CFG             0xFFC01410         /* GPTIMER Stop Config Register */
+#define TIMER_STOP_CFG_SET         0xFFC01414         /* GPTIMER Stop Config Alias to Set */
+#define TIMER_STOP_CFG_CLR         0xFFC01418         /* GPTIMER Stop Config Alias to Clear */
+#define TIMER_DATA_IMSK            0xFFC0141C         /* GPTIMER Data Interrupt Mask register */
+#define TIMER_STAT_IMSK            0xFFC01420         /* GPTIMER Status Interrupt Mask register */
+#define TIMER_TRG_MSK              0xFFC01424         /* GPTIMER Output Trigger Mask register */
+#define TIMER_TRG_IE               0xFFC01428         /* GPTIMER Slave Trigger Enable register */
+#define TIMER_DATA_ILAT            0xFFC0142C         /* GPTIMER Data Interrupt Register */
+#define TIMER_STAT_ILAT            0xFFC01430         /* GPTIMER Status (Error) Interrupt Register */
+#define TIMER_ERR_TYPE             0xFFC01434         /* GPTIMER Register Indicating Type of Error */
+#define TIMER_BCAST_PER            0xFFC01438         /* GPTIMER Broadcast Period */
+#define TIMER_BCAST_WID            0xFFC0143C         /* GPTIMER Broadcast Width */
+#define TIMER_BCAST_DLY            0xFFC01440         /* GPTIMER Broadcast Delay */
+/* =========================
+        TIMER0~7
+   ========================= */
+#define TIMER0_CONFIG             0xFFC01460         /* TIMER0 Per Timer Config Register */
+#define TIMER0_COUNTER            0xFFC01464         /* TIMER0 Per Timer Counter Register */
+#define TIMER0_PERIOD             0xFFC01468         /* TIMER0 Per Timer Period Register */
+#define TIMER0_WIDTH              0xFFC0146C         /* TIMER0 Per Timer Width Register */
+#define TIMER0_DELAY              0xFFC01470         /* TIMER0 Per Timer Delay Register */
+#define TIMER1_CONFIG             0xFFC01480         /* TIMER1 Per Timer Config Register */
+#define TIMER1_COUNTER            0xFFC01484         /* TIMER1 Per Timer Counter Register */
+#define TIMER1_PERIOD             0xFFC01488         /* TIMER1 Per Timer Period Register */
+#define TIMER1_WIDTH              0xFFC0148C         /* TIMER1 Per Timer Width Register */
+#define TIMER1_DELAY              0xFFC01490         /* TIMER1 Per Timer Delay Register */
+#define TIMER2_CONFIG             0xFFC014A0         /* TIMER2 Per Timer Config Register */
+#define TIMER2_COUNTER            0xFFC014A4         /* TIMER2 Per Timer Counter Register */
+#define TIMER2_PERIOD             0xFFC014A8         /* TIMER2 Per Timer Period Register */
+#define TIMER2_WIDTH              0xFFC014AC         /* TIMER2 Per Timer Width Register */
+#define TIMER2_DELAY              0xFFC014B0         /* TIMER2 Per Timer Delay Register */
+#define TIMER3_CONFIG             0xFFC014C0         /* TIMER3 Per Timer Config Register */
+#define TIMER3_COUNTER            0xFFC014C4         /* TIMER3 Per Timer Counter Register */
+#define TIMER3_PERIOD             0xFFC014C8         /* TIMER3 Per Timer Period Register */
+#define TIMER3_WIDTH              0xFFC014CC         /* TIMER3 Per Timer Width Register */
+#define TIMER3_DELAY              0xFFC014D0         /* TIMER3 Per Timer Delay Register */
+#define TIMER4_CONFIG             0xFFC014E0         /* TIMER4 Per Timer Config Register */
+#define TIMER4_COUNTER            0xFFC014E4         /* TIMER4 Per Timer Counter Register */
+#define TIMER4_PERIOD             0xFFC014E8         /* TIMER4 Per Timer Period Register */
+#define TIMER4_WIDTH              0xFFC014EC         /* TIMER4 Per Timer Width Register */
+#define TIMER4_DELAY              0xFFC014F0         /* TIMER4 Per Timer Delay Register */
+#define TIMER5_CONFIG             0xFFC01500         /* TIMER5 Per Timer Config Register */
+#define TIMER5_COUNTER            0xFFC01504         /* TIMER5 Per Timer Counter Register */
+#define TIMER5_PERIOD             0xFFC01508         /* TIMER5 Per Timer Period Register */
+#define TIMER5_WIDTH              0xFFC0150C         /* TIMER5 Per Timer Width Register */
+#define TIMER5_DELAY              0xFFC01510         /* TIMER5 Per Timer Delay Register */
+#define TIMER6_CONFIG             0xFFC01520         /* TIMER6 Per Timer Config Register */
+#define TIMER6_COUNTER            0xFFC01524         /* TIMER6 Per Timer Counter Register */
+#define TIMER6_PERIOD             0xFFC01528         /* TIMER6 Per Timer Period Register */
+#define TIMER6_WIDTH              0xFFC0152C         /* TIMER6 Per Timer Width Register */
+#define TIMER6_DELAY              0xFFC01530         /* TIMER6 Per Timer Delay Register */
+#define TIMER7_CONFIG             0xFFC01540         /* TIMER7 Per Timer Config Register */
+#define TIMER7_COUNTER            0xFFC01544         /* TIMER7 Per Timer Counter Register */
+#define TIMER7_PERIOD             0xFFC01548         /* TIMER7 Per Timer Period Register */
+#define TIMER7_WIDTH              0xFFC0154C         /* TIMER7 Per Timer Width Register */
+#define TIMER7_DELAY              0xFFC01550         /* TIMER7 Per Timer Delay Register */
+/* =========================
+        CRC Registers
+   ========================= */
+/* =========================
+        CRC0
+   ========================= */
+#define REG_CRC0_CTL                    0xFFC01C00         /* CRC0 Control Register */
+#define REG_CRC0_DCNT                   0xFFC01C04         /* CRC0 Data Word Count Register */
+#define REG_CRC0_DCNTRLD                0xFFC01C08         /* CRC0 Data Word Count Reload Register */
+#define REG_CRC0_COMP                   0xFFC01C14         /* CRC0 DATA Compare Register */
+#define REG_CRC0_FILLVAL                0xFFC01C18         /* CRC0 Fill Value Register */
+#define REG_CRC0_DFIFO                  0xFFC01C1C         /* CRC0 DATA FIFO Register */
+#define REG_CRC0_INEN                   0xFFC01C20         /* CRC0 Interrupt Enable Register */
+#define REG_CRC0_INEN_SET               0xFFC01C24         /* CRC0 Interrupt Enable Set Register */
+#define REG_CRC0_INEN_CLR               0xFFC01C28         /* CRC0 Interrupt Enable Clear Register */
+#define REG_CRC0_POLY                   0xFFC01C2C         /* CRC0 Polynomial Register */
+#define REG_CRC0_STAT                   0xFFC01C40         /* CRC0 Status Register */
+#define REG_CRC0_DCNTCAP                0xFFC01C44         /* CRC0 DATA Count Capture Register */
+#define REG_CRC0_RESULT_FIN             0xFFC01C4C         /* CRC0 Final CRC Result Register */
+#define REG_CRC0_RESULT_CUR             0xFFC01C50         /* CRC0 Current CRC Result Register */
+#define REG_CRC0_REVID                  0xFFC01C60         /* CRC0 Revision ID Register */
+/* =========================
+        CRC1
+   ========================= */
+#define REG_CRC1_CTL                    0xFFC01D00         /* CRC1 Control Register */
+#define REG_CRC1_DCNT                   0xFFC01D04         /* CRC1 Data Word Count Register */
+#define REG_CRC1_DCNTRLD                0xFFC01D08         /* CRC1 Data Word Count Reload Register */
+#define REG_CRC1_COMP                   0xFFC01D14         /* CRC1 DATA Compare Register */
+#define REG_CRC1_FILLVAL                0xFFC01D18         /* CRC1 Fill Value Register */
+#define REG_CRC1_DFIFO                  0xFFC01D1C         /* CRC1 DATA FIFO Register */
+#define REG_CRC1_INEN                   0xFFC01D20         /* CRC1 Interrupt Enable Register */
+#define REG_CRC1_INEN_SET               0xFFC01D24         /* CRC1 Interrupt Enable Set Register */
+#define REG_CRC1_INEN_CLR               0xFFC01D28         /* CRC1 Interrupt Enable Clear Register */
+#define REG_CRC1_POLY                   0xFFC01D2C         /* CRC1 Polynomial Register */
+#define REG_CRC1_STAT                   0xFFC01D40         /* CRC1 Status Register */
+#define REG_CRC1_DCNTCAP                0xFFC01D44         /* CRC1 DATA Count Capture Register */
+#define REG_CRC1_RESULT_FIN             0xFFC01D4C         /* CRC1 Final CRC Result Register */
+#define REG_CRC1_RESULT_CUR             0xFFC01D50         /* CRC1 Current CRC Result Register */
+#define REG_CRC1_REVID                  0xFFC01D60         /* CRC1 Revision ID Register */
+/* =========================
+        TWI Registers
+   ========================= */
+/* =========================
+        TWI0
+   ========================= */
+#define TWI0_CLKDIV                    0xFFC01E00         /* TWI0 SCL Clock Divider */
+#define TWI0_CONTROL                   0xFFC01E04         /* TWI0 Control Register */
+#define TWI0_SLAVE_CTL                 0xFFC01E08         /* TWI0 Slave Mode Control Register */
+#define TWI0_SLAVE_STAT                0xFFC01E0C         /* TWI0 Slave Mode Status Register */
+#define TWI0_SLAVE_ADDR                0xFFC01E10         /* TWI0 Slave Mode Address Register */
+#define TWI0_MASTER_CTL                0xFFC01E14         /* TWI0 Master Mode Control Registers */
+#define TWI0_MASTER_STAT               0xFFC01E18         /* TWI0 Master Mode Status Register */
+#define TWI0_MASTER_ADDR               0xFFC01E1C         /* TWI0 Master Mode Address Register */
+#define TWI0_INT_STAT                  0xFFC01E20         /* TWI0 Interrupt Status Register */
+#define TWI0_INT_MASK                  0xFFC01E24         /* TWI0 Interrupt Mask Register */
+#define TWI0_FIFO_CTL                  0xFFC01E28         /* TWI0 FIFO Control Register */
+#define TWI0_FIFO_STAT                 0xFFC01E2C         /* TWI0 FIFO Status Register */
+#define TWI0_XMT_DATA8                 0xFFC01E80         /* TWI0 FIFO Transmit Data Single-Byte Register */
+#define TWI0_XMT_DATA16                0xFFC01E84         /* TWI0 FIFO Transmit Data Double-Byte Register */
+#define TWI0_RCV_DATA8                 0xFFC01E88         /* TWI0 FIFO Transmit Data Single-Byte Register */
+#define TWI0_RCV_DATA16                0xFFC01E8C         /* TWI0 FIFO Transmit Data Double-Byte Register */
+/* =========================
+        TWI1
+   ========================= */
+#define TWI1_CLKDIV                 0xFFC01F00         /* TWI1 SCL Clock Divider */
+#define TWI1_CONTROL                    0xFFC01F04         /* TWI1 Control Register */
+#define TWI1_SLAVE_CTL                 0xFFC01F08         /* TWI1 Slave Mode Control Register */
+#define TWI1_SLAVE_STAT                0xFFC01F0C         /* TWI1 Slave Mode Status Register */
+#define TWI1_SLAVE_ADDR                0xFFC01F10         /* TWI1 Slave Mode Address Register */
+#define TWI1_MASTER_CTL                0xFFC01F14         /* TWI1 Master Mode Control Registers */
+#define TWI1_MASTER_STAT               0xFFC01F18         /* TWI1 Master Mode Status Register */
+#define TWI1_MASTER_ADDR               0xFFC01F1C         /* TWI1 Master Mode Address Register */
+#define TWI1_INT_STAT                  0xFFC01F20         /* TWI1 Interrupt Status Register */
+#define TWI1_INT_MASK                   0xFFC01F24         /* TWI1 Interrupt Mask Register */
+#define TWI1_FIFO_CTL                0xFFC01F28         /* TWI1 FIFO Control Register */
+#define TWI1_FIFO_STAT               0xFFC01F2C         /* TWI1 FIFO Status Register */
+#define TWI1_XMT_DATA8                0xFFC01F80         /* TWI1 FIFO Transmit Data Single-Byte Register */
+#define TWI1_XMT_DATA16               0xFFC01F84         /* TWI1 FIFO Transmit Data Double-Byte Register */
+#define TWI1_RCV_DATA8                0xFFC01F88         /* TWI1 FIFO Transmit Data Single-Byte Register */
+#define TWI1_RCV_DATA16               0xFFC01F8C         /* TWI1 FIFO Transmit Data Double-Byte Register */
+/* =========================
+        UART Registers
+   ========================= */
+/* =========================
+        UART0
+   ========================= */
+#define UART0_REVID                 0xFFC02000         /* UART0 Revision ID Register */
+#define UART0_CTL                   0xFFC02004         /* UART0 Control Register */
+#define UART0_STAT                  0xFFC02008         /* UART0 Status Register */
+#define UART0_SCR                   0xFFC0200C         /* UART0 Scratch Register */
+#define UART0_CLK                   0xFFC02010         /* UART0 Clock Rate Register */
+#define UART0_IER                   0xFFC02014         /* UART0 Interrupt Mask Register */
+#define UART0_IER_SET               0xFFC02018         /* UART0 Interrupt Mask Set Register */
+#define UART0_IER_CLR               0xFFC0201C         /* UART0 Interrupt Mask Clear Register */
+#define UART0_RBR                   0xFFC02020         /* UART0 Receive Buffer Register */
+#define UART0_THR                   0xFFC02024         /* UART0 Transmit Hold Register */
+#define UART0_TAIP                  0xFFC02028         /* UART0 Transmit Address/Insert Pulse Register */
+#define UART0_TSR                   0xFFC0202C         /* UART0 Transmit Shift Register */
+#define UART0_RSR                   0xFFC02030         /* UART0 Receive Shift Register */
+#define UART0_TXDIV                 0xFFC02034         /* UART0 Transmit Clock Devider Register */
+#define UART0_RXDIV                 0xFFC02038         /* UART0 Receive Clock Devider Register */
+/* =========================
+        UART1
+   ========================= */
+#define UART1_REVID                 0xFFC02400         /* UART1 Revision ID Register */
+#define UART1_CTL                   0xFFC02404         /* UART1 Control Register */
+#define UART1_STAT                  0xFFC02408         /* UART1 Status Register */
+#define UART1_SCR                   0xFFC0240C         /* UART1 Scratch Register */
+#define UART1_CLK                   0xFFC02410         /* UART1 Clock Rate Register */
+#define UART1_IER                   0xFFC02414         /* UART1 Interrupt Mask Register */
+#define UART1_IER_SET               0xFFC02418         /* UART1 Interrupt Mask Set Register */
+#define UART1_IER_CLR               0xFFC0241C         /* UART1 Interrupt Mask Clear Register */
+#define UART1_RBR                   0xFFC02420         /* UART1 Receive Buffer Register */
+#define UART1_THR                   0xFFC02424         /* UART1 Transmit Hold Register */
+#define UART1_TAIP                  0xFFC02428         /* UART1 Transmit Address/Insert Pulse Register */
+#define UART1_TSR                   0xFFC0242C         /* UART1 Transmit Shift Register */
+#define UART1_RSR                   0xFFC02430         /* UART1 Receive Shift Register */
+#define UART1_TXDIV                 0xFFC02434         /* UART1 Transmit Clock Devider Register */
+#define UART1_RXDIV                 0xFFC02438         /* UART1 Receive Clock Devider Register */
+/* =========================
+        PORT Registers
+   ========================= */
+/* =========================
+        PORTA
+   ========================= */
+#define PORTA_FER                   0xFFC03000         /* PORTA Port x Function Enable Register */
+#define PORTA_FER_SET               0xFFC03004         /* PORTA Port x Function Enable Set Register */
+#define PORTA_FER_CLEAR               0xFFC03008         /* PORTA Port x Function Enable Clear Register */
+#define PORTA_DATA                  0xFFC0300C         /* PORTA Port x GPIO Data Register */
+#define PORTA_DATA_SET              0xFFC03010         /* PORTA Port x GPIO Data Set Register */
+#define PORTA_DATA_CLEAR              0xFFC03014         /* PORTA Port x GPIO Data Clear Register */
+#define PORTA_DIR                   0xFFC03018         /* PORTA Port x GPIO Direction Register */
+#define PORTA_DIR_SET               0xFFC0301C         /* PORTA Port x GPIO Direction Set Register */
+#define PORTA_DIR_CLEAR               0xFFC03020         /* PORTA Port x GPIO Direction Clear Register */
+#define PORTA_INEN                  0xFFC03024         /* PORTA Port x GPIO Input Enable Register */
+#define PORTA_INEN_SET              0xFFC03028         /* PORTA Port x GPIO Input Enable Set Register */
+#define PORTA_INEN_CLEAR              0xFFC0302C         /* PORTA Port x GPIO Input Enable Clear Register */
+#define PORTA_MUX                   0xFFC03030         /* PORTA Port x Multiplexer Control Register */
+#define PORTA_DATA_TGL              0xFFC03034         /* PORTA Port x GPIO Input Enable Toggle Register */
+#define PORTA_POL                   0xFFC03038         /* PORTA Port x GPIO Programming Inversion Register */
+#define PORTA_POL_SET               0xFFC0303C         /* PORTA Port x GPIO Programming Inversion Set Register */
+#define PORTA_POL_CLEAR               0xFFC03040         /* PORTA Port x GPIO Programming Inversion Clear Register */
+#define PORTA_LOCK                  0xFFC03044         /* PORTA Port x GPIO Lock Register */
+#define PORTA_REVID                 0xFFC0307C         /* PORTA Port x GPIO Revision ID */
+/* =========================
+        PORTB
+   ========================= */
+#define PORTB_FER                   0xFFC03080         /* PORTB Port x Function Enable Register */
+#define PORTB_FER_SET               0xFFC03084         /* PORTB Port x Function Enable Set Register */
+#define PORTB_FER_CLEAR               0xFFC03088         /* PORTB Port x Function Enable Clear Register */
+#define PORTB_DATA                  0xFFC0308C         /* PORTB Port x GPIO Data Register */
+#define PORTB_DATA_SET              0xFFC03090         /* PORTB Port x GPIO Data Set Register */
+#define PORTB_DATA_CLEAR              0xFFC03094         /* PORTB Port x GPIO Data Clear Register */
+#define PORTB_DIR                   0xFFC03098         /* PORTB Port x GPIO Direction Register */
+#define PORTB_DIR_SET               0xFFC0309C         /* PORTB Port x GPIO Direction Set Register */
+#define PORTB_DIR_CLEAR               0xFFC030A0         /* PORTB Port x GPIO Direction Clear Register */
+#define PORTB_INEN                  0xFFC030A4         /* PORTB Port x GPIO Input Enable Register */
+#define PORTB_INEN_SET              0xFFC030A8         /* PORTB Port x GPIO Input Enable Set Register */
+#define PORTB_INEN_CLEAR              0xFFC030AC         /* PORTB Port x GPIO Input Enable Clear Register */
+#define PORTB_MUX                   0xFFC030B0         /* PORTB Port x Multiplexer Control Register */
+#define PORTB_DATA_TGL              0xFFC030B4         /* PORTB Port x GPIO Input Enable Toggle Register */
+#define PORTB_POL                   0xFFC030B8         /* PORTB Port x GPIO Programming Inversion Register */
+#define PORTB_POL_SET               0xFFC030BC         /* PORTB Port x GPIO Programming Inversion Set Register */
+#define PORTB_POL_CLEAR               0xFFC030C0         /* PORTB Port x GPIO Programming Inversion Clear Register */
+#define PORTB_LOCK                  0xFFC030C4         /* PORTB Port x GPIO Lock Register */
+#define PORTB_REVID                 0xFFC030FC         /* PORTB Port x GPIO Revision ID */
+/* =========================
+        PORTC
+   ========================= */
+#define PORTC_FER                   0xFFC03100         /* PORTC Port x Function Enable Register */
+#define PORTC_FER_SET               0xFFC03104         /* PORTC Port x Function Enable Set Register */
+#define PORTC_FER_CLEAR               0xFFC03108         /* PORTC Port x Function Enable Clear Register */
+#define PORTC_DATA                  0xFFC0310C         /* PORTC Port x GPIO Data Register */
+#define PORTC_DATA_SET              0xFFC03110         /* PORTC Port x GPIO Data Set Register */
+#define PORTC_DATA_CLEAR              0xFFC03114         /* PORTC Port x GPIO Data Clear Register */
+#define PORTC_DIR                   0xFFC03118         /* PORTC Port x GPIO Direction Register */
+#define PORTC_DIR_SET               0xFFC0311C         /* PORTC Port x GPIO Direction Set Register */
+#define PORTC_DIR_CLEAR               0xFFC03120         /* PORTC Port x GPIO Direction Clear Register */
+#define PORTC_INEN                  0xFFC03124         /* PORTC Port x GPIO Input Enable Register */
+#define PORTC_INEN_SET              0xFFC03128         /* PORTC Port x GPIO Input Enable Set Register */
+#define PORTC_INEN_CLEAR              0xFFC0312C         /* PORTC Port x GPIO Input Enable Clear Register */
+#define PORTC_MUX                   0xFFC03130         /* PORTC Port x Multiplexer Control Register */
+#define PORTC_DATA_TGL              0xFFC03134         /* PORTC Port x GPIO Input Enable Toggle Register */
+#define PORTC_POL                   0xFFC03138         /* PORTC Port x GPIO Programming Inversion Register */
+#define PORTC_POL_SET               0xFFC0313C         /* PORTC Port x GPIO Programming Inversion Set Register */
+#define PORTC_POL_CLEAR               0xFFC03140         /* PORTC Port x GPIO Programming Inversion Clear Register */
+#define PORTC_LOCK                  0xFFC03144         /* PORTC Port x GPIO Lock Register */
+#define PORTC_REVID                 0xFFC0317C         /* PORTC Port x GPIO Revision ID */
+/* =========================
+        PORTD
+   ========================= */
+#define PORTD_FER                   0xFFC03180         /* PORTD Port x Function Enable Register */
+#define PORTD_FER_SET               0xFFC03184         /* PORTD Port x Function Enable Set Register */
+#define PORTD_FER_CLEAR               0xFFC03188         /* PORTD Port x Function Enable Clear Register */
+#define PORTD_DATA                  0xFFC0318C         /* PORTD Port x GPIO Data Register */
+#define PORTD_DATA_SET              0xFFC03190         /* PORTD Port x GPIO Data Set Register */
+#define PORTD_DATA_CLEAR              0xFFC03194         /* PORTD Port x GPIO Data Clear Register */
+#define PORTD_DIR                   0xFFC03198         /* PORTD Port x GPIO Direction Register */
+#define PORTD_DIR_SET               0xFFC0319C         /* PORTD Port x GPIO Direction Set Register */
+#define PORTD_DIR_CLEAR               0xFFC031A0         /* PORTD Port x GPIO Direction Clear Register */
+#define PORTD_INEN                  0xFFC031A4         /* PORTD Port x GPIO Input Enable Register */
+#define PORTD_INEN_SET              0xFFC031A8         /* PORTD Port x GPIO Input Enable Set Register */
+#define PORTD_INEN_CLEAR              0xFFC031AC         /* PORTD Port x GPIO Input Enable Clear Register */
+#define PORTD_MUX                   0xFFC031B0         /* PORTD Port x Multiplexer Control Register */
+#define PORTD_DATA_TGL              0xFFC031B4         /* PORTD Port x GPIO Input Enable Toggle Register */
+#define PORTD_POL                   0xFFC031B8         /* PORTD Port x GPIO Programming Inversion Register */
+#define PORTD_POL_SET               0xFFC031BC         /* PORTD Port x GPIO Programming Inversion Set Register */
+#define PORTD_POL_CLEAR               0xFFC031C0         /* PORTD Port x GPIO Programming Inversion Clear Register */
+#define PORTD_LOCK                  0xFFC031C4         /* PORTD Port x GPIO Lock Register */
+#define PORTD_REVID                 0xFFC031FC         /* PORTD Port x GPIO Revision ID */
+/* =========================
+        PORTE
+   ========================= */
+#define PORTE_FER                   0xFFC03200         /* PORTE Port x Function Enable Register */
+#define PORTE_FER_SET               0xFFC03204         /* PORTE Port x Function Enable Set Register */
+#define PORTE_FER_CLEAR               0xFFC03208         /* PORTE Port x Function Enable Clear Register */
+#define PORTE_DATA                  0xFFC0320C         /* PORTE Port x GPIO Data Register */
+#define PORTE_DATA_SET              0xFFC03210         /* PORTE Port x GPIO Data Set Register */
+#define PORTE_DATA_CLEAR              0xFFC03214         /* PORTE Port x GPIO Data Clear Register */
+#define PORTE_DIR                   0xFFC03218         /* PORTE Port x GPIO Direction Register */
+#define PORTE_DIR_SET               0xFFC0321C         /* PORTE Port x GPIO Direction Set Register */
+#define PORTE_DIR_CLEAR               0xFFC03220         /* PORTE Port x GPIO Direction Clear Register */
+#define PORTE_INEN                  0xFFC03224         /* PORTE Port x GPIO Input Enable Register */
+#define PORTE_INEN_SET              0xFFC03228         /* PORTE Port x GPIO Input Enable Set Register */
+#define PORTE_INEN_CLEAR              0xFFC0322C         /* PORTE Port x GPIO Input Enable Clear Register */
+#define PORTE_MUX                   0xFFC03230         /* PORTE Port x Multiplexer Control Register */
+#define PORTE_DATA_TGL              0xFFC03234         /* PORTE Port x GPIO Input Enable Toggle Register */
+#define PORTE_POL                   0xFFC03238         /* PORTE Port x GPIO Programming Inversion Register */
+#define PORTE_POL_SET               0xFFC0323C         /* PORTE Port x GPIO Programming Inversion Set Register */
+#define PORTE_POL_CLEAR               0xFFC03240         /* PORTE Port x GPIO Programming Inversion Clear Register */
+#define PORTE_LOCK                  0xFFC03244         /* PORTE Port x GPIO Lock Register */
+#define PORTE_REVID                 0xFFC0327C         /* PORTE Port x GPIO Revision ID */
+/* =========================
+        PORTF
+   ========================= */
+#define PORTF_FER                   0xFFC03280         /* PORTF Port x Function Enable Register */
+#define PORTF_FER_SET               0xFFC03284         /* PORTF Port x Function Enable Set Register */
+#define PORTF_FER_CLEAR               0xFFC03288         /* PORTF Port x Function Enable Clear Register */
+#define PORTF_DATA                  0xFFC0328C         /* PORTF Port x GPIO Data Register */
+#define PORTF_DATA_SET              0xFFC03290         /* PORTF Port x GPIO Data Set Register */
+#define PORTF_DATA_CLEAR              0xFFC03294         /* PORTF Port x GPIO Data Clear Register */
+#define PORTF_DIR                   0xFFC03298         /* PORTF Port x GPIO Direction Register */
+#define PORTF_DIR_SET               0xFFC0329C         /* PORTF Port x GPIO Direction Set Register */
+#define PORTF_DIR_CLEAR               0xFFC032A0         /* PORTF Port x GPIO Direction Clear Register */
+#define PORTF_INEN                  0xFFC032A4         /* PORTF Port x GPIO Input Enable Register */
+#define PORTF_INEN_SET              0xFFC032A8         /* PORTF Port x GPIO Input Enable Set Register */
+#define PORTF_INEN_CLEAR              0xFFC032AC         /* PORTF Port x GPIO Input Enable Clear Register */
+#define PORTF_MUX                   0xFFC032B0         /* PORTF Port x Multiplexer Control Register */
+#define PORTF_DATA_TGL              0xFFC032B4         /* PORTF Port x GPIO Input Enable Toggle Register */
+#define PORTF_POL                   0xFFC032B8         /* PORTF Port x GPIO Programming Inversion Register */
+#define PORTF_POL_SET               0xFFC032BC         /* PORTF Port x GPIO Programming Inversion Set Register */
+#define PORTF_POL_CLEAR               0xFFC032C0         /* PORTF Port x GPIO Programming Inversion Clear Register */
+#define PORTF_LOCK                  0xFFC032C4         /* PORTF Port x GPIO Lock Register */
+#define PORTF_REVID                 0xFFC032FC         /* PORTF Port x GPIO Revision ID */
+/* =========================
+        PORTG
+   ========================= */
+#define PORTG_FER                   0xFFC03300         /* PORTG Port x Function Enable Register */
+#define PORTG_FER_SET               0xFFC03304         /* PORTG Port x Function Enable Set Register */
+#define PORTG_FER_CLEAR               0xFFC03308         /* PORTG Port x Function Enable Clear Register */
+#define PORTG_DATA                  0xFFC0330C         /* PORTG Port x GPIO Data Register */
+#define PORTG_DATA_SET              0xFFC03310         /* PORTG Port x GPIO Data Set Register */
+#define PORTG_DATA_CLEAR              0xFFC03314         /* PORTG Port x GPIO Data Clear Register */
+#define PORTG_DIR                   0xFFC03318         /* PORTG Port x GPIO Direction Register */
+#define PORTG_DIR_SET               0xFFC0331C         /* PORTG Port x GPIO Direction Set Register */
+#define PORTG_DIR_CLEAR               0xFFC03320         /* PORTG Port x GPIO Direction Clear Register */
+#define PORTG_INEN                  0xFFC03324         /* PORTG Port x GPIO Input Enable Register */
+#define PORTG_INEN_SET              0xFFC03328         /* PORTG Port x GPIO Input Enable Set Register */
+#define PORTG_INEN_CLEAR              0xFFC0332C         /* PORTG Port x GPIO Input Enable Clear Register */
+#define PORTG_MUX                   0xFFC03330         /* PORTG Port x Multiplexer Control Register */
+#define PORTG_DATA_TGL              0xFFC03334         /* PORTG Port x GPIO Input Enable Toggle Register */
+#define PORTG_POL                   0xFFC03338         /* PORTG Port x GPIO Programming Inversion Register */
+#define PORTG_POL_SET               0xFFC0333C         /* PORTG Port x GPIO Programming Inversion Set Register */
+#define PORTG_POL_CLEAR               0xFFC03340         /* PORTG Port x GPIO Programming Inversion Clear Register */
+#define PORTG_LOCK                  0xFFC03344         /* PORTG Port x GPIO Lock Register */
+#define PORTG_REVID                 0xFFC0337C         /* PORTG Port x GPIO Revision ID */
+/* =========================
+        PINT Registers
+   ========================= */
+/* =========================
+        PINT0
+   ========================= */
+#define PINT0_MASK_SET              0xFFC04000         /* PINT0 Pint Mask Set Register */
+#define PINT0_MASK_CLEAR            0xFFC04004         /* PINT0 Pint Mask Clear Register */
+#define PINT0_REQUEST               0xFFC04008         /* PINT0 Pint Request Register */
+#define PINT0_ASSIGN                0xFFC0400C         /* PINT0 Pint Assign Register */
+#define PINT0_EDGE_SET              0xFFC04010         /* PINT0 Pint Edge Set Register */
+#define PINT0_EDGE_CLEAR            0xFFC04014         /* PINT0 Pint Edge Clear Register */
+#define PINT0_INVERT_SET            0xFFC04018         /* PINT0 Pint Invert Set Register */
+#define PINT0_INVERT_CLEAR          0xFFC0401C         /* PINT0 Pint Invert Clear Register */
+#define PINT0_PINSTATE              0xFFC04020         /* PINT0 Pint Pinstate Register */
+#define PINT0_LATCH                 0xFFC04024         /* PINT0 Pint Latch Register */
+/* =========================
+        PINT1
+   ========================= */
+#define PINT1_MASK_SET              0xFFC04100         /* PINT1 Pint Mask Set Register */
+#define PINT1_MASK_CLEAR            0xFFC04104         /* PINT1 Pint Mask Clear Register */
+#define PINT1_REQUEST               0xFFC04108         /* PINT1 Pint Request Register */
+#define PINT1_ASSIGN                0xFFC0410C         /* PINT1 Pint Assign Register */
+#define PINT1_EDGE_SET              0xFFC04110         /* PINT1 Pint Edge Set Register */
+#define PINT1_EDGE_CLEAR            0xFFC04114         /* PINT1 Pint Edge Clear Register */
+#define PINT1_INVERT_SET            0xFFC04118         /* PINT1 Pint Invert Set Register */
+#define PINT1_INVERT_CLEAR          0xFFC0411C         /* PINT1 Pint Invert Clear Register */
+#define PINT1_PINSTATE              0xFFC04120         /* PINT1 Pint Pinstate Register */
+#define PINT1_LATCH                 0xFFC04124         /* PINT1 Pint Latch Register */
+/* =========================
+        PINT2
+   ========================= */
+#define PINT2_MASK_SET              0xFFC04200         /* PINT2 Pint Mask Set Register */
+#define PINT2_MASK_CLEAR            0xFFC04204         /* PINT2 Pint Mask Clear Register */
+#define PINT2_REQUEST               0xFFC04208         /* PINT2 Pint Request Register */
+#define PINT2_ASSIGN                0xFFC0420C         /* PINT2 Pint Assign Register */
+#define PINT2_EDGE_SET              0xFFC04210         /* PINT2 Pint Edge Set Register */
+#define PINT2_EDGE_CLEAR            0xFFC04214         /* PINT2 Pint Edge Clear Register */
+#define PINT2_INVERT_SET            0xFFC04218         /* PINT2 Pint Invert Set Register */
+#define PINT2_INVERT_CLEAR          0xFFC0421C         /* PINT2 Pint Invert Clear Register */
+#define PINT2_PINSTATE              0xFFC04220         /* PINT2 Pint Pinstate Register */
+#define PINT2_LATCH                 0xFFC04224         /* PINT2 Pint Latch Register */
+/* =========================
+        PINT3
+   ========================= */
+#define PINT3_MASK_SET              0xFFC04300         /* PINT3 Pint Mask Set Register */
+#define PINT3_MASK_CLEAR            0xFFC04304         /* PINT3 Pint Mask Clear Register */
+#define PINT3_REQUEST               0xFFC04308         /* PINT3 Pint Request Register */
+#define PINT3_ASSIGN                0xFFC0430C         /* PINT3 Pint Assign Register */
+#define PINT3_EDGE_SET              0xFFC04310         /* PINT3 Pint Edge Set Register */
+#define PINT3_EDGE_CLEAR            0xFFC04314         /* PINT3 Pint Edge Clear Register */
+#define PINT3_INVERT_SET            0xFFC04318         /* PINT3 Pint Invert Set Register */
+#define PINT3_INVERT_CLEAR          0xFFC0431C         /* PINT3 Pint Invert Clear Register */
+#define PINT3_PINSTATE              0xFFC04320         /* PINT3 Pint Pinstate Register */
+#define PINT3_LATCH                 0xFFC04324         /* PINT3 Pint Latch Register */
+/* =========================
+        PINT4
+   ========================= */
+#define PINT4_MASK_SET              0xFFC04400         /* PINT4 Pint Mask Set Register */
+#define PINT4_MASK_CLEAR            0xFFC04404         /* PINT4 Pint Mask Clear Register */
+#define PINT4_REQUEST               0xFFC04408         /* PINT4 Pint Request Register */
+#define PINT4_ASSIGN                0xFFC0440C         /* PINT4 Pint Assign Register */
+#define PINT4_EDGE_SET              0xFFC04410         /* PINT4 Pint Edge Set Register */
+#define PINT4_EDGE_CLEAR            0xFFC04414         /* PINT4 Pint Edge Clear Register */
+#define PINT4_INVERT_SET            0xFFC04418         /* PINT4 Pint Invert Set Register */
+#define PINT4_INVERT_CLEAR          0xFFC0441C         /* PINT4 Pint Invert Clear Register */
+#define PINT4_PINSTATE              0xFFC04420         /* PINT4 Pint Pinstate Register */
+#define PINT4_LATCH                 0xFFC04424         /* PINT4 Pint Latch Register */
+/* =========================
+        PINT5
+   ========================= */
+#define PINT5_MASK_SET              0xFFC04500         /* PINT5 Pint Mask Set Register */
+#define PINT5_MASK_CLEAR            0xFFC04504         /* PINT5 Pint Mask Clear Register */
+#define PINT5_REQUEST               0xFFC04508         /* PINT5 Pint Request Register */
+#define PINT5_ASSIGN                0xFFC0450C         /* PINT5 Pint Assign Register */
+#define PINT5_EDGE_SET              0xFFC04510         /* PINT5 Pint Edge Set Register */
+#define PINT5_EDGE_CLEAR            0xFFC04514         /* PINT5 Pint Edge Clear Register */
+#define PINT5_INVERT_SET            0xFFC04518         /* PINT5 Pint Invert Set Register */
+#define PINT5_INVERT_CLEAR          0xFFC0451C         /* PINT5 Pint Invert Clear Register */
+#define PINT5_PINSTATE              0xFFC04520         /* PINT5 Pint Pinstate Register */
+#define PINT5_LATCH                 0xFFC04524         /* PINT5 Pint Latch Register */
+/* =========================
+        SMC Registers
+   ========================= */
+/* =========================
+        SMC0
+   ========================= */
+#define SMC_GCTL                   0xFFC16004         /* SMC0 SMC Control Register */
+#define SMC_GSTAT                  0xFFC16008         /* SMC0 SMC Status Register */
+#define SMC_B0CTL                  0xFFC1600C         /* SMC0 SMC Bank0 Control Register */
+#define SMC_B0TIM                  0xFFC16010         /* SMC0 SMC Bank0 Timing Register */
+#define SMC_B0ETIM                 0xFFC16014         /* SMC0 SMC Bank0 Extended Timing Register */
+#define SMC_B1CTL                  0xFFC1601C         /* SMC0 SMC BANK1 Control Register */
+#define SMC_B1TIM                  0xFFC16020         /* SMC0 SMC BANK1 Timing Register */
+#define SMC_B1ETIM                 0xFFC16024         /* SMC0 SMC BANK1 Extended Timing Register */
+#define SMC_B2CTL                  0xFFC1602C         /* SMC0 SMC BANK2 Control Register */
+#define SMC_B2TIM                  0xFFC16030         /* SMC0 SMC BANK2 Timing Register */
+#define SMC_B2ETIM                 0xFFC16034         /* SMC0 SMC BANK2 Extended Timing Register */
+#define SMC_B3CTL                  0xFFC1603C         /* SMC0 SMC BANK3 Control Register */
+#define SMC_B3TIM                  0xFFC16040         /* SMC0 SMC BANK3 Timing Register */
+#define SMC_B3ETIM                 0xFFC16044         /* SMC0 SMC BANK3 Extended Timing Register */
+/* =========================
+        WDOG Registers
+   ========================= */
+/* =========================
+        WDOG0
+   ========================= */
+#define WDOG0_CTL                   0xFFC17000         /* WDOG0 Control Register */
+#define WDOG0_CNT                   0xFFC17004         /* WDOG0 Count Register */
+#define WDOG0_STAT                  0xFFC17008         /* WDOG0 Watchdog Timer Status Register */
+#define WDOG_CTL                WDOG0_CTL
+#define WDOG_CNT                WDOG0_CNT
+#define WDOG_STAT               WDOG0_STAT
+/* =========================
+        WDOG1
+   ========================= */
+#define WDOG1_CTL                   0xFFC17800         /* WDOG1 Control Register */
+#define WDOG1_CNT                   0xFFC17804         /* WDOG1 Count Register */
+#define WDOG1_STAT                  0xFFC17808         /* WDOG1 Watchdog Timer Status Register */
+/* =========================
+        SDU Registers
+   ========================= */
+/* =========================
+        SDU0
+   ========================= */
+#define SDU0_IDCODE                 0xFFC1F020         /* SDU0 ID Code Register */
+#define SDU0_CTL                    0xFFC1F050         /* SDU0 Control Register */
+#define SDU0_STAT                   0xFFC1F054         /* SDU0 Status Register */
+#define SDU0_MACCTL                 0xFFC1F058         /* SDU0 Memory Access Control Register */
+#define SDU0_MACADDR                0xFFC1F05C         /* SDU0 Memory Access Address Register */
+#define SDU0_MACDATA                0xFFC1F060         /* SDU0 Memory Access Data Register */
+#define SDU0_DMARD                  0xFFC1F064         /* SDU0 DMA Read Data Register */
+#define SDU0_DMAWD                  0xFFC1F068         /* SDU0 DMA Write Data Register */
+#define SDU0_MSG                    0xFFC1F080         /* SDU0 Message Register */
+#define SDU0_MSG_SET                0xFFC1F084         /* SDU0 Message Set Register */
+#define SDU0_MSG_CLR                0xFFC1F088         /* SDU0 Message Clear Register */
+#define SDU0_GHLT                   0xFFC1F08C         /* SDU0 Group Halt Register */
+/* =========================
+        EMAC Registers
+   ========================= */
+/* =========================
+        EMAC0
+   ========================= */
+#define EMAC0_MACCFG                0xFFC20000         /* EMAC0 MAC Configuration Register */
+#define EMAC0_MACFRMFILT            0xFFC20004         /* EMAC0 Filter Register for filtering Received Frames */
+#define EMAC0_HASHTBL_HI            0xFFC20008         /* EMAC0 Contains the Upper 32 bits of the hash table */
+#define EMAC0_HASHTBL_LO            0xFFC2000C         /* EMAC0 Contains the lower 32 bits of the hash table */
+#define EMAC0_GMII_ADDR             0xFFC20010         /* EMAC0 Management Address Register */
+#define EMAC0_GMII_DATA             0xFFC20014         /* EMAC0 Management Data Register */
+#define EMAC0_FLOWCTL               0xFFC20018         /* EMAC0 MAC FLow Control Register */
+#define EMAC0_VLANTAG               0xFFC2001C         /* EMAC0 VLAN Tag Register */
+#define EMAC0_VER                   0xFFC20020         /* EMAC0 EMAC Version Register */
+#define EMAC0_DBG                   0xFFC20024         /* EMAC0 EMAC Debug Register */
+#define EMAC0_RMTWKUP               0xFFC20028         /* EMAC0 Remote wake up frame register */
+#define EMAC0_PMT_CTLSTAT           0xFFC2002C         /* EMAC0 PMT Control and Status Register */
+#define EMAC0_ISTAT                 0xFFC20038         /* EMAC0 EMAC Interrupt Status Register */
+#define EMAC0_IMSK                  0xFFC2003C         /* EMAC0 EMAC Interrupt Mask Register */
+#define EMAC0_ADDR0_HI              0xFFC20040         /* EMAC0 EMAC Address0 High Register */
+#define EMAC0_ADDR0_LO              0xFFC20044         /* EMAC0 EMAC Address0 Low Register */
+#define EMAC0_MMC_CTL               0xFFC20100         /* EMAC0 MMC Control Register */
+#define EMAC0_MMC_RXINT             0xFFC20104         /* EMAC0 MMC RX Interrupt Register */
+#define EMAC0_MMC_TXINT             0xFFC20108         /* EMAC0 MMC TX Interrupt Register */
+#define EMAC0_MMC_RXIMSK            0xFFC2010C         /* EMAC0 MMC RX Interrupt Mask Register */
+#define EMAC0_MMC_TXIMSK            0xFFC20110         /* EMAC0 MMC TX Interrupt Mask Register */
+#define EMAC0_TXOCTCNT_GB           0xFFC20114         /* EMAC0 Num bytes transmitted exclusive of preamble */
+#define EMAC0_TXFRMCNT_GB           0xFFC20118         /* EMAC0 Num frames transmitted exclusive of retired */
+#define EMAC0_TXBCASTFRM_G          0xFFC2011C         /* EMAC0 Number of good broadcast frames transmitted. */
+#define EMAC0_TXMCASTFRM_G          0xFFC20120         /* EMAC0 Number of good multicast frames transmitted. */
+#define EMAC0_TX64_GB               0xFFC20124         /* EMAC0 Number of 64 byte length frames */
+#define EMAC0_TX65TO127_GB          0xFFC20128         /* EMAC0 Number of frames of length b/w 65-127 (inclusive) bytes */
+#define EMAC0_TX128TO255_GB         0xFFC2012C         /* EMAC0 Number of frames of length b/w 128-255 (inclusive) bytes */
+#define EMAC0_TX256TO511_GB         0xFFC20130         /* EMAC0 Number of frames of length b/w 256-511 (inclusive) bytes */
+#define EMAC0_TX512TO1023_GB        0xFFC20134         /* EMAC0 Number of frames of length b/w 512-1023 (inclusive) bytes */
+#define EMAC0_TX1024TOMAX_GB        0xFFC20138         /* EMAC0 Number of frames of length b/w 1024-max (inclusive) bytes */
+#define EMAC0_TXUCASTFRM_GB         0xFFC2013C         /* EMAC0 Number of good and bad unicast frames transmitted */
+#define EMAC0_TXMCASTFRM_GB         0xFFC20140         /* EMAC0 Number of good and bad multicast frames transmitted */
+#define EMAC0_TXBCASTFRM_GB         0xFFC20144         /* EMAC0 Number of good and bad broadcast frames transmitted */
+#define EMAC0_TXUNDR_ERR            0xFFC20148         /* EMAC0 Number of frames aborted due to frame underflow error */
+#define EMAC0_TXSNGCOL_G            0xFFC2014C         /* EMAC0 Number of transmitted frames after single collision */
+#define EMAC0_TXMULTCOL_G           0xFFC20150         /* EMAC0 Number of transmitted frames with more than one collision */
+#define EMAC0_TXDEFERRED            0xFFC20154         /* EMAC0 Number of transmitted frames after deferral */
+#define EMAC0_TXLATECOL             0xFFC20158         /* EMAC0 Number of frames aborted due to late collision error */
+#define EMAC0_TXEXCESSCOL           0xFFC2015C         /* EMAC0 Number of aborted frames due to excessive collisions */
+#define EMAC0_TXCARR_ERR            0xFFC20160         /* EMAC0 Number of aborted frames due to carrier sense error */
+#define EMAC0_TXOCTCNT_G            0xFFC20164         /* EMAC0 Number of bytes transmitted in good frames only */
+#define EMAC0_TXFRMCNT_G            0xFFC20168         /* EMAC0 Number of good frames transmitted. */
+#define EMAC0_TXEXCESSDEF           0xFFC2016C         /* EMAC0 Number of frames aborted due to excessive deferral */
+#define EMAC0_TXPAUSEFRM            0xFFC20170         /* EMAC0 Number of good PAUSE frames transmitted. */
+#define EMAC0_TXVLANFRM_G           0xFFC20174         /* EMAC0 Number of VLAN frames transmitted */
+#define EMAC0_RXFRMCNT_GB           0xFFC20180         /* EMAC0 Number of good and bad frames received. */
+#define EMAC0_RXOCTCNT_GB           0xFFC20184         /* EMAC0 Number of bytes received in good and bad frames */
+#define EMAC0_RXOCTCNT_G            0xFFC20188         /* EMAC0 Number of bytes received only in good frames */
+#define EMAC0_RXBCASTFRM_G          0xFFC2018C         /* EMAC0 Number of good broadcast frames received. */
+#define EMAC0_RXMCASTFRM_G          0xFFC20190         /* EMAC0 Number of good multicast frames received */
+#define EMAC0_RXCRC_ERR             0xFFC20194         /* EMAC0 Number of frames received with CRC error */
+#define EMAC0_RXALIGN_ERR           0xFFC20198         /* EMAC0 Number of frames with alignment error */
+#define EMAC0_RXRUNT_ERR            0xFFC2019C         /* EMAC0 Number of frames received with runt error. */
+#define EMAC0_RXJAB_ERR             0xFFC201A0         /* EMAC0 Number of frames received with length greater than 1518 */
+#define EMAC0_RXUSIZE_G             0xFFC201A4         /* EMAC0 Number of frames received with length 64 */
+#define EMAC0_RXOSIZE_G             0xFFC201A8         /* EMAC0 Number of frames received with length greater than maxium */
+#define EMAC0_RX64_GB               0xFFC201AC         /* EMAC0 Number of good and bad frames of lengh 64 bytes */
+#define EMAC0_RX65TO127_GB          0xFFC201B0         /* EMAC0 Number of good and bad frame between 64-127(inclusive) */
+#define EMAC0_RX128TO255_GB         0xFFC201B4         /* EMAC0 Number of good and bad frames received with length between 128 and 255 (inclusive) bytes, exclusive of preamble. */
+#define EMAC0_RX256TO511_GB         0xFFC201B8         /* EMAC0 Number of good and bad frames between 256-511(inclusive) */
+#define EMAC0_RX512TO1023_GB        0xFFC201BC         /* EMAC0 Number of good and bad frames received between 512-1023 */
+#define EMAC0_RX1024TOMAX_GB        0xFFC201C0         /* EMAC0 Number of frames received between 1024 and maxsize */
+#define EMAC0_RXUCASTFRM_G          0xFFC201C4         /* EMAC0 Number of good unicast frames received. */
+#define EMAC0_RXLEN_ERR             0xFFC201C8         /* EMAC0 Number of frames received with length error */
+#define EMAC0_RXOORTYPE             0xFFC201CC         /* EMAC0 Number of frames with length not equal to valid frame size */
+#define EMAC0_RXPAUSEFRM            0xFFC201D0         /* EMAC0 Number of good and valid PAUSE frames received. */
+#define EMAC0_RXFIFO_OVF            0xFFC201D4         /* EMAC0 Number of missed received frames due to FIFO overflow. This counter is not present in the GMAC-CORE configuration. */
+#define EMAC0_RXVLANFRM_GB          0xFFC201D8         /* EMAC0 Number of good and bad VLAN frames received. */
+#define EMAC0_RXWDOG_ERR            0xFFC201DC         /* EMAC0 Frames received with error due to watchdog timeout */
+#define EMAC0_IPC_RXIMSK            0xFFC20200         /* EMAC0 MMC IPC RX Interrupt Mask Register */
+#define EMAC0_IPC_RXINT             0xFFC20208         /* EMAC0 MMC IPC RX Interrupt Register */
+#define EMAC0_RXIPV4_GD_FRM         0xFFC20210         /* EMAC0 Number of good IPv4 datagrams */
+#define EMAC0_RXIPV4_HDR_ERR_FRM    0xFFC20214         /* EMAC0 Number of IPv4 datagrams with header errors */
+#define EMAC0_RXIPV4_NOPAY_FRM      0xFFC20218         /* EMAC0 Number of IPv4 datagrams without checksum */
+#define EMAC0_RXIPV4_FRAG_FRM       0xFFC2021C         /* EMAC0 Number of good IPv4 datagrams with fragmentation */
+#define EMAC0_RXIPV4_UDSBL_FRM      0xFFC20220         /* EMAC0 Number of IPv4 UDP datagrams with disabled checksum */
+#define EMAC0_RXIPV6_GD_FRM         0xFFC20224         /* EMAC0 Number of IPv4 datagrams with TCP/UDP/ICMP payloads */
+#define EMAC0_RXIPV6_HDR_ERR_FRM    0xFFC20228         /* EMAC0 Number of IPv6 datagrams with header errors */
+#define EMAC0_RXIPV6_NOPAY_FRM      0xFFC2022C         /* EMAC0 Number of IPv6 datagrams with no TCP/UDP/ICMP payload */
+#define EMAC0_RXUDP_GD_FRM          0xFFC20230         /* EMAC0 Number of good IP datagrames with good UDP payload */
+#define EMAC0_RXUDP_ERR_FRM         0xFFC20234         /* EMAC0 Number of good IP datagrams with UDP checksum errors */
+#define EMAC0_RXTCP_GD_FRM          0xFFC20238         /* EMAC0 Number of good IP datagrams with a good TCP payload */
+#define EMAC0_RXTCP_ERR_FRM         0xFFC2023C         /* EMAC0 Number of good IP datagrams with TCP checksum errors */
+#define EMAC0_RXICMP_GD_FRM         0xFFC20240         /* EMAC0 Number of good IP datagrams with a good ICMP payload */
+#define EMAC0_RXICMP_ERR_FRM        0xFFC20244         /* EMAC0 Number of good IP datagrams with ICMP checksum errors */
+#define EMAC0_RXIPV4_GD_OCT         0xFFC20250         /* EMAC0 Bytes received in IPv4 datagrams including tcp,udp or icmp */
+#define EMAC0_RXIPV4_HDR_ERR_OCT    0xFFC20254         /* EMAC0 Bytes received in IPv4 datagrams with header errors */
+#define EMAC0_RXIPV4_NOPAY_OCT      0xFFC20258         /* EMAC0 Bytes received in IPv4 datagrams without tcp,udp,icmp load */
+#define EMAC0_RXIPV4_FRAG_OCT       0xFFC2025C         /* EMAC0 Bytes received in fragmented IPv4 datagrams */
+#define EMAC0_RXIPV4_UDSBL_OCT      0xFFC20260         /* EMAC0 Bytes received in UDP segment with checksum disabled */
+#define EMAC0_RXIPV6_GD_OCT         0xFFC20264         /* EMAC0 Bytes received in good IPv6  including tcp,udp or icmp load */
+#define EMAC0_RXIPV6_HDR_ERR_OCT    0xFFC20268         /* EMAC0 Number of bytes received in IPv6 with header errors */
+#define EMAC0_RXIPV6_NOPAY_OCT      0xFFC2026C         /* EMAC0 Bytes received in IPv6 without tcp,udp or icmp load */
+#define EMAC0_RXUDP_GD_OCT          0xFFC20270         /* EMAC0 Number of bytes received in good UDP segments */
+#define EMAC0_RXUDP_ERR_OCT         0xFFC20274         /* EMAC0 Number of bytes received in UDP segment with checksum err */
+#define EMAC0_RXTCP_GD_OCT          0xFFC20278         /* EMAC0 Number of bytes received in a good TCP segment */
+#define EMAC0_RXTCP_ERR_OCT         0xFFC2027C         /* EMAC0 Number of bytes received in TCP segment with checksum err */
+#define EMAC0_RXICMP_GD_OCT         0xFFC20280         /* EMAC0 Number of bytes received in a good ICMP segment */
+#define EMAC0_RXICMP_ERR_OCT        0xFFC20284         /* EMAC0 Bytes received in an ICMP segment with checksum errors */
+#define EMAC0_TM_CTL                0xFFC20700         /* EMAC0 EMAC Time Stamp Control Register */
+#define EMAC0_TM_SUBSEC             0xFFC20704         /* EMAC0 EMAC Time Stamp Sub Second Increment */
+#define EMAC0_TM_SEC                0xFFC20708         /* EMAC0 EMAC Time Stamp Second Register */
+#define EMAC0_TM_NSEC               0xFFC2070C         /* EMAC0 EMAC Time Stamp Nano Second Register */
+#define EMAC0_TM_SECUPDT            0xFFC20710         /* EMAC0 EMAC Time Stamp Seconds Update */
+#define EMAC0_TM_NSECUPDT           0xFFC20714         /* EMAC0 EMAC Time Stamp Nano Seconds Update */
+#define EMAC0_TM_ADDEND             0xFFC20718         /* EMAC0 EMAC Time Stamp Addend Register */
+#define EMAC0_TM_TGTM               0xFFC2071C         /* EMAC0 EMAC Time Stamp Target Time Sec. */
+#define EMAC0_TM_NTGTM              0xFFC20720         /* EMAC0 EMAC Time Stamp Target Time Nanosec. */
+#define EMAC0_TM_HISEC              0xFFC20724         /* EMAC0 EMAC Time Stamp High Second Register */
+#define EMAC0_TM_STMPSTAT           0xFFC20728         /* EMAC0 EMAC Time Stamp Status Register */
+#define EMAC0_TM_PPSCTL             0xFFC2072C         /* EMAC0 EMAC PPS Control Register */
+#define EMAC0_TM_AUXSTMP_NSEC       0xFFC20730         /* EMAC0 EMAC Auxillary Time Stamp Nano Register */
+#define EMAC0_TM_AUXSTMP_SEC        0xFFC20734         /* EMAC0 EMAC Auxillary Time Stamp Sec Register */
+#define EMAC0_DMA_BUSMODE           0xFFC21000         /* EMAC0 Bus Operating Modes for EMAC DMA */
+#define EMAC0_DMA_TXPOLL            0xFFC21004         /* EMAC0 TX DMA Poll demand register */
+#define EMAC0_DMA_RXPOLL            0xFFC21008         /* EMAC0 RX DMA Poll demand register */
+#define EMAC0_DMA_RXDSC_ADDR        0xFFC2100C         /* EMAC0 RX Descriptor List Address */
+#define EMAC0_DMA_TXDSC_ADDR        0xFFC21010         /* EMAC0 TX Descriptor List Address */
+#define EMAC0_DMA_STAT              0xFFC21014         /* EMAC0 DMA Status Register */
+#define EMAC0_DMA_OPMODE            0xFFC21018         /* EMAC0 DMA Operation Mode Register */
+#define EMAC0_DMA_IEN               0xFFC2101C         /* EMAC0 DMA Interrupt Enable Register */
+#define EMAC0_DMA_MISS_FRM          0xFFC21020         /* EMAC0 DMA missed frame and buffer overflow counter */
+#define EMAC0_DMA_RXIWDOG           0xFFC21024         /* EMAC0 DMA RX Interrupt Watch Dog timer */
+#define EMAC0_DMA_BMMODE            0xFFC21028         /* EMAC0 AXI Bus Mode Register */
+#define EMAC0_DMA_BMSTAT            0xFFC2102C         /* EMAC0 AXI Status Register */
+#define EMAC0_DMA_TXDSC_CUR         0xFFC21048         /* EMAC0 TX current descriptor register */
+#define EMAC0_DMA_RXDSC_CUR         0xFFC2104C         /* EMAC0 RX current descriptor register */
+#define EMAC0_DMA_TXBUF_CUR         0xFFC21050         /* EMAC0 TX current buffer pointer register */
+#define EMAC0_DMA_RXBUF_CUR         0xFFC21054         /* EMAC0 RX current buffer pointer register */
+#define EMAC0_HWFEAT                0xFFC21058         /* EMAC0 Hardware Feature Register */
+/* =========================
+        EMAC1
+   ========================= */
+#define EMAC1_MACCFG                0xFFC22000         /* EMAC1 MAC Configuration Register */
+#define EMAC1_MACFRMFILT            0xFFC22004         /* EMAC1 Filter Register for filtering Received Frames */
+#define EMAC1_HASHTBL_HI            0xFFC22008         /* EMAC1 Contains the Upper 32 bits of the hash table */
+#define EMAC1_HASHTBL_LO            0xFFC2200C         /* EMAC1 Contains the lower 32 bits of the hash table */
+#define EMAC1_GMII_ADDR             0xFFC22010         /* EMAC1 Management Address Register */
+#define EMAC1_GMII_DATA             0xFFC22014         /* EMAC1 Management Data Register */
+#define EMAC1_FLOWCTL               0xFFC22018         /* EMAC1 MAC FLow Control Register */
+#define EMAC1_VLANTAG               0xFFC2201C         /* EMAC1 VLAN Tag Register */
+#define EMAC1_VER                   0xFFC22020         /* EMAC1 EMAC Version Register */
+#define EMAC1_DBG                   0xFFC22024         /* EMAC1 EMAC Debug Register */
+#define EMAC1_RMTWKUP               0xFFC22028         /* EMAC1 Remote wake up frame register */
+#define EMAC1_PMT_CTLSTAT           0xFFC2202C         /* EMAC1 PMT Control and Status Register */
+#define EMAC1_ISTAT                 0xFFC22038         /* EMAC1 EMAC Interrupt Status Register */
+#define EMAC1_IMSK                  0xFFC2203C         /* EMAC1 EMAC Interrupt Mask Register */
+#define EMAC1_ADDR0_HI              0xFFC22040         /* EMAC1 EMAC Address0 High Register */
+#define EMAC1_ADDR0_LO              0xFFC22044         /* EMAC1 EMAC Address0 Low Register */
+#define EMAC1_MMC_CTL               0xFFC22100         /* EMAC1 MMC Control Register */
+#define EMAC1_MMC_RXINT             0xFFC22104         /* EMAC1 MMC RX Interrupt Register */
+#define EMAC1_MMC_TXINT             0xFFC22108         /* EMAC1 MMC TX Interrupt Register */
+#define EMAC1_MMC_RXIMSK            0xFFC2210C         /* EMAC1 MMC RX Interrupt Mask Register */
+#define EMAC1_MMC_TXIMSK            0xFFC22110         /* EMAC1 MMC TX Interrupt Mask Register */
+#define EMAC1_TXOCTCNT_GB           0xFFC22114         /* EMAC1 Num bytes transmitted exclusive of preamble */
+#define EMAC1_TXFRMCNT_GB           0xFFC22118         /* EMAC1 Num frames transmitted exclusive of retired */
+#define EMAC1_TXBCASTFRM_G          0xFFC2211C         /* EMAC1 Number of good broadcast frames transmitted. */
+#define EMAC1_TXMCASTFRM_G          0xFFC22120         /* EMAC1 Number of good multicast frames transmitted. */
+#define EMAC1_TX64_GB               0xFFC22124         /* EMAC1 Number of 64 byte length frames */
+#define EMAC1_TX65TO127_GB          0xFFC22128         /* EMAC1 Number of frames of length b/w 65-127 (inclusive) bytes */
+#define EMAC1_TX128TO255_GB         0xFFC2212C         /* EMAC1 Number of frames of length b/w 128-255 (inclusive) bytes */
+#define EMAC1_TX256TO511_GB         0xFFC22130         /* EMAC1 Number of frames of length b/w 256-511 (inclusive) bytes */
+#define EMAC1_TX512TO1023_GB        0xFFC22134         /* EMAC1 Number of frames of length b/w 512-1023 (inclusive) bytes */
+#define EMAC1_TX1024TOMAX_GB        0xFFC22138         /* EMAC1 Number of frames of length b/w 1024-max (inclusive) bytes */
+#define EMAC1_TXUCASTFRM_GB         0xFFC2213C         /* EMAC1 Number of good and bad unicast frames transmitted */
+#define EMAC1_TXMCASTFRM_GB         0xFFC22140         /* EMAC1 Number of good and bad multicast frames transmitted */
+#define EMAC1_TXBCASTFRM_GB         0xFFC22144         /* EMAC1 Number of good and bad broadcast frames transmitted */
+#define EMAC1_TXUNDR_ERR            0xFFC22148         /* EMAC1 Number of frames aborted due to frame underflow error */
+#define EMAC1_TXSNGCOL_G            0xFFC2214C         /* EMAC1 Number of transmitted frames after single collision */
+#define EMAC1_TXMULTCOL_G           0xFFC22150         /* EMAC1 Number of transmitted frames with more than one collision */
+#define EMAC1_TXDEFERRED            0xFFC22154         /* EMAC1 Number of transmitted frames after deferral */
+#define EMAC1_TXLATECOL             0xFFC22158         /* EMAC1 Number of frames aborted due to late collision error */
+#define EMAC1_TXEXCESSCOL           0xFFC2215C         /* EMAC1 Number of aborted frames due to excessive collisions */
+#define EMAC1_TXCARR_ERR            0xFFC22160         /* EMAC1 Number of aborted frames due to carrier sense error */
+#define EMAC1_TXOCTCNT_G            0xFFC22164         /* EMAC1 Number of bytes transmitted in good frames only */
+#define EMAC1_TXFRMCNT_G            0xFFC22168         /* EMAC1 Number of good frames transmitted. */
+#define EMAC1_TXEXCESSDEF           0xFFC2216C         /* EMAC1 Number of frames aborted due to excessive deferral */
+#define EMAC1_TXPAUSEFRM            0xFFC22170         /* EMAC1 Number of good PAUSE frames transmitted. */
+#define EMAC1_TXVLANFRM_G           0xFFC22174         /* EMAC1 Number of VLAN frames transmitted */
+#define EMAC1_RXFRMCNT_GB           0xFFC22180         /* EMAC1 Number of good and bad frames received. */
+#define EMAC1_RXOCTCNT_GB           0xFFC22184         /* EMAC1 Number of bytes received in good and bad frames */
+#define EMAC1_RXOCTCNT_G            0xFFC22188         /* EMAC1 Number of bytes received only in good frames */
+#define EMAC1_RXBCASTFRM_G          0xFFC2218C         /* EMAC1 Number of good broadcast frames received. */
+#define EMAC1_RXMCASTFRM_G          0xFFC22190         /* EMAC1 Number of good multicast frames received */
+#define EMAC1_RXCRC_ERR             0xFFC22194         /* EMAC1 Number of frames received with CRC error */
+#define EMAC1_RXALIGN_ERR           0xFFC22198         /* EMAC1 Number of frames with alignment error */
+#define EMAC1_RXRUNT_ERR            0xFFC2219C         /* EMAC1 Number of frames received with runt error. */
+#define EMAC1_RXJAB_ERR             0xFFC221A0         /* EMAC1 Number of frames received with length greater than 1518 */
+#define EMAC1_RXUSIZE_G             0xFFC221A4         /* EMAC1 Number of frames received with length 64 */
+#define EMAC1_RXOSIZE_G             0xFFC221A8         /* EMAC1 Number of frames received with length greater than maxium */
+#define EMAC1_RX64_GB               0xFFC221AC         /* EMAC1 Number of good and bad frames of lengh 64 bytes */
+#define EMAC1_RX65TO127_GB          0xFFC221B0         /* EMAC1 Number of good and bad frame between 64-127(inclusive) */
+#define EMAC1_RX128TO255_GB         0xFFC221B4         /* EMAC1 Number of good and bad frames received with length between 128 and 255 (inclusive) bytes, exclusive of preamble. */
+#define EMAC1_RX256TO511_GB         0xFFC221B8         /* EMAC1 Number of good and bad frames between 256-511(inclusive) */
+#define EMAC1_RX512TO1023_GB        0xFFC221BC         /* EMAC1 Number of good and bad frames received between 512-1023 */
+#define EMAC1_RX1024TOMAX_GB        0xFFC221C0         /* EMAC1 Number of frames received between 1024 and maxsize */
+#define EMAC1_RXUCASTFRM_G          0xFFC221C4         /* EMAC1 Number of good unicast frames received. */
+#define EMAC1_RXLEN_ERR             0xFFC221C8         /* EMAC1 Number of frames received with length error */
+#define EMAC1_RXOORTYPE             0xFFC221CC         /* EMAC1 Number of frames with length not equal to valid frame size */
+#define EMAC1_RXPAUSEFRM            0xFFC221D0         /* EMAC1 Number of good and valid PAUSE frames received. */
+#define EMAC1_RXFIFO_OVF            0xFFC221D4         /* EMAC1 Number of missed received frames due to FIFO overflow. This counter is not present in the GMAC-CORE configuration. */
+#define EMAC1_RXVLANFRM_GB          0xFFC221D8         /* EMAC1 Number of good and bad VLAN frames received. */
+#define EMAC1_RXWDOG_ERR            0xFFC221DC         /* EMAC1 Frames received with error due to watchdog timeout */
+#define EMAC1_IPC_RXIMSK            0xFFC22200         /* EMAC1 MMC IPC RX Interrupt Mask Register */
+#define EMAC1_IPC_RXINT             0xFFC22208         /* EMAC1 MMC IPC RX Interrupt Register */
+#define EMAC1_RXIPV4_GD_FRM         0xFFC22210         /* EMAC1 Number of good IPv4 datagrams */
+#define EMAC1_RXIPV4_HDR_ERR_FRM    0xFFC22214         /* EMAC1 Number of IPv4 datagrams with header errors */
+#define EMAC1_RXIPV4_NOPAY_FRM      0xFFC22218         /* EMAC1 Number of IPv4 datagrams without checksum */
+#define EMAC1_RXIPV4_FRAG_FRM       0xFFC2221C         /* EMAC1 Number of good IPv4 datagrams with fragmentation */
+#define EMAC1_RXIPV4_UDSBL_FRM      0xFFC22220         /* EMAC1 Number of IPv4 UDP datagrams with disabled checksum */
+#define EMAC1_RXIPV6_GD_FRM         0xFFC22224         /* EMAC1 Number of IPv4 datagrams with TCP/UDP/ICMP payloads */
+#define EMAC1_RXIPV6_HDR_ERR_FRM    0xFFC22228         /* EMAC1 Number of IPv6 datagrams with header errors */
+#define EMAC1_RXIPV6_NOPAY_FRM      0xFFC2222C         /* EMAC1 Number of IPv6 datagrams with no TCP/UDP/ICMP payload */
+#define EMAC1_RXUDP_GD_FRM          0xFFC22230         /* EMAC1 Number of good IP datagrames with good UDP payload */
+#define EMAC1_RXUDP_ERR_FRM         0xFFC22234         /* EMAC1 Number of good IP datagrams with UDP checksum errors */
+#define EMAC1_RXTCP_GD_FRM          0xFFC22238         /* EMAC1 Number of good IP datagrams with a good TCP payload */
+#define EMAC1_RXTCP_ERR_FRM         0xFFC2223C         /* EMAC1 Number of good IP datagrams with TCP checksum errors */
+#define EMAC1_RXICMP_GD_FRM         0xFFC22240         /* EMAC1 Number of good IP datagrams with a good ICMP payload */
+#define EMAC1_RXICMP_ERR_FRM        0xFFC22244         /* EMAC1 Number of good IP datagrams with ICMP checksum errors */
+#define EMAC1_RXIPV4_GD_OCT         0xFFC22250         /* EMAC1 Bytes received in IPv4 datagrams including tcp,udp or icmp */
+#define EMAC1_RXIPV4_HDR_ERR_OCT    0xFFC22254         /* EMAC1 Bytes received in IPv4 datagrams with header errors */
+#define EMAC1_RXIPV4_NOPAY_OCT      0xFFC22258         /* EMAC1 Bytes received in IPv4 datagrams without tcp,udp,icmp load */
+#define EMAC1_RXIPV4_FRAG_OCT       0xFFC2225C         /* EMAC1 Bytes received in fragmented IPv4 datagrams */
+#define EMAC1_RXIPV4_UDSBL_OCT      0xFFC22260         /* EMAC1 Bytes received in UDP segment with checksum disabled */
+#define EMAC1_RXIPV6_GD_OCT         0xFFC22264         /* EMAC1 Bytes received in good IPv6  including tcp,udp or icmp load */
+#define EMAC1_RXIPV6_HDR_ERR_OCT    0xFFC22268         /* EMAC1 Number of bytes received in IPv6 with header errors */
+#define EMAC1_RXIPV6_NOPAY_OCT      0xFFC2226C         /* EMAC1 Bytes received in IPv6 without tcp,udp or icmp load */
+#define EMAC1_RXUDP_GD_OCT          0xFFC22270         /* EMAC1 Number of bytes received in good UDP segments */
+#define EMAC1_RXUDP_ERR_OCT         0xFFC22274         /* EMAC1 Number of bytes received in UDP segment with checksum err */
+#define EMAC1_RXTCP_GD_OCT          0xFFC22278         /* EMAC1 Number of bytes received in a good TCP segment */
+#define EMAC1_RXTCP_ERR_OCT         0xFFC2227C         /* EMAC1 Number of bytes received in TCP segment with checksum err */
+#define EMAC1_RXICMP_GD_OCT         0xFFC22280         /* EMAC1 Number of bytes received in a good ICMP segment */
+#define EMAC1_RXICMP_ERR_OCT        0xFFC22284         /* EMAC1 Bytes received in an ICMP segment with checksum errors */
+#define EMAC1_TM_CTL                0xFFC22700         /* EMAC1 EMAC Time Stamp Control Register */
+#define EMAC1_TM_SUBSEC             0xFFC22704         /* EMAC1 EMAC Time Stamp Sub Second Increment */
+#define EMAC1_TM_SEC                0xFFC22708         /* EMAC1 EMAC Time Stamp Second Register */
+#define EMAC1_TM_NSEC               0xFFC2270C         /* EMAC1 EMAC Time Stamp Nano Second Register */
+#define EMAC1_TM_SECUPDT            0xFFC22710         /* EMAC1 EMAC Time Stamp Seconds Update */
+#define EMAC1_TM_NSECUPDT           0xFFC22714         /* EMAC1 EMAC Time Stamp Nano Seconds Update */
+#define EMAC1_TM_ADDEND             0xFFC22718         /* EMAC1 EMAC Time Stamp Addend Register */
+#define EMAC1_TM_TGTM               0xFFC2271C         /* EMAC1 EMAC Time Stamp Target Time Sec. */
+#define EMAC1_TM_NTGTM              0xFFC22720         /* EMAC1 EMAC Time Stamp Target Time Nanosec. */
+#define EMAC1_TM_HISEC              0xFFC22724         /* EMAC1 EMAC Time Stamp High Second Register */
+#define EMAC1_TM_STMPSTAT           0xFFC22728         /* EMAC1 EMAC Time Stamp Status Register */
+#define EMAC1_TM_PPSCTL             0xFFC2272C         /* EMAC1 EMAC PPS Control Register */
+#define EMAC1_TM_AUXSTMP_NSEC       0xFFC22730         /* EMAC1 EMAC Auxillary Time Stamp Nano Register */
+#define EMAC1_TM_AUXSTMP_SEC        0xFFC22734         /* EMAC1 EMAC Auxillary Time Stamp Sec Register */
+#define EMAC1_DMA_BUSMODE           0xFFC23000         /* EMAC1 Bus Operating Modes for EMAC DMA */
+#define EMAC1_DMA_TXPOLL            0xFFC23004         /* EMAC1 TX DMA Poll demand register */
+#define EMAC1_DMA_RXPOLL            0xFFC23008         /* EMAC1 RX DMA Poll demand register */
+#define EMAC1_DMA_RXDSC_ADDR        0xFFC2300C         /* EMAC1 RX Descriptor List Address */
+#define EMAC1_DMA_TXDSC_ADDR        0xFFC23010         /* EMAC1 TX Descriptor List Address */
+#define EMAC1_DMA_STAT              0xFFC23014         /* EMAC1 DMA Status Register */
+#define EMAC1_DMA_OPMODE            0xFFC23018         /* EMAC1 DMA Operation Mode Register */
+#define EMAC1_DMA_IEN               0xFFC2301C         /* EMAC1 DMA Interrupt Enable Register */
+#define EMAC1_DMA_MISS_FRM          0xFFC23020         /* EMAC1 DMA missed frame and buffer overflow counter */
+#define EMAC1_DMA_RXIWDOG           0xFFC23024         /* EMAC1 DMA RX Interrupt Watch Dog timer */
+#define EMAC1_DMA_BMMODE            0xFFC23028         /* EMAC1 AXI Bus Mode Register */
+#define EMAC1_DMA_BMSTAT            0xFFC2302C         /* EMAC1 AXI Status Register */
+#define EMAC1_DMA_TXDSC_CUR         0xFFC23048         /* EMAC1 TX current descriptor register */
+#define EMAC1_DMA_RXDSC_CUR         0xFFC2304C         /* EMAC1 RX current descriptor register */
+#define EMAC1_DMA_TXBUF_CUR         0xFFC23050         /* EMAC1 TX current buffer pointer register */
+#define EMAC1_DMA_RXBUF_CUR         0xFFC23054         /* EMAC1 RX current buffer pointer register */
+#define EMAC1_HWFEAT                0xFFC23058         /* EMAC1 Hardware Feature Register */
+/* =========================
+        SPI Registers
+   ========================= */
+/* =========================
+        SPI0
+   ========================= */
+#define SPI0_REGBASE                0xFFC40400
+#define SPI0_CTL                    0xFFC40404         /* SPI0 Control Register */
+#define SPI0_RXCTL                  0xFFC40408         /* SPI0 RX Control Register */
+#define SPI0_TXCTL                  0xFFC4040C         /* SPI0 TX Control Register */
+#define SPI0_CLK                    0xFFC40410         /* SPI0 Clock Rate Register */
+#define SPI0_DLY                    0xFFC40414         /* SPI0 Delay Register */
+#define SPI0_SLVSEL                 0xFFC40418         /* SPI0 Slave Select Register */
+#define SPI0_RWC                    0xFFC4041C         /* SPI0 Received Word-Count Register */
+#define SPI0_RWCR                   0xFFC40420         /* SPI0 Received Word-Count Reload Register */
+#define SPI0_TWC                    0xFFC40424         /* SPI0 Transmitted Word-Count Register */
+#define SPI0_TWCR                   0xFFC40428         /* SPI0 Transmitted Word-Count Reload Register */
+#define SPI0_IMSK                   0xFFC40430         /* SPI0 Interrupt Mask Register */
+#define SPI0_IMSK_CLR               0xFFC40434         /* SPI0 Interrupt Mask Clear Register */
+#define SPI0_IMSK_SET               0xFFC40438         /* SPI0 Interrupt Mask Set Register */
+#define SPI0_STAT                   0xFFC40440         /* SPI0 Status Register */
+#define SPI0_ILAT                   0xFFC40444         /* SPI0 Masked Interrupt Condition Register */
+#define SPI0_ILAT_CLR               0xFFC40448         /* SPI0 Masked Interrupt Clear Register */
+#define SPI0_RFIFO                  0xFFC40450         /* SPI0 Receive FIFO Data Register */
+#define SPI0_TFIFO                  0xFFC40458         /* SPI0 Transmit FIFO Data Register */
+/* =========================
+        SPI1
+   ========================= */
+#define SPI1_REGBASE                0xFFC40500
+#define SPI1_CTL                    0xFFC40504         /* SPI1 Control Register */
+#define SPI1_RXCTL                  0xFFC40508         /* SPI1 RX Control Register */
+#define SPI1_TXCTL                  0xFFC4050C         /* SPI1 TX Control Register */
+#define SPI1_CLK                    0xFFC40510         /* SPI1 Clock Rate Register */
+#define SPI1_DLY                    0xFFC40514         /* SPI1 Delay Register */
+#define SPI1_SLVSEL                 0xFFC40518         /* SPI1 Slave Select Register */
+#define SPI1_RWC                    0xFFC4051C         /* SPI1 Received Word-Count Register */
+#define SPI1_RWCR                   0xFFC40520         /* SPI1 Received Word-Count Reload Register */
+#define SPI1_TWC                    0xFFC40524         /* SPI1 Transmitted Word-Count Register */
+#define SPI1_TWCR                   0xFFC40528         /* SPI1 Transmitted Word-Count Reload Register */
+#define SPI1_IMSK                   0xFFC40530         /* SPI1 Interrupt Mask Register */
+#define SPI1_IMSK_CLR               0xFFC40534         /* SPI1 Interrupt Mask Clear Register */
+#define SPI1_IMSK_SET               0xFFC40538         /* SPI1 Interrupt Mask Set Register */
+#define SPI1_STAT                   0xFFC40540         /* SPI1 Status Register */
+#define SPI1_ILAT                   0xFFC40544         /* SPI1 Masked Interrupt Condition Register */
+#define SPI1_ILAT_CLR               0xFFC40548         /* SPI1 Masked Interrupt Clear Register */
+#define SPI1_RFIFO                  0xFFC40550         /* SPI1 Receive FIFO Data Register */
+#define SPI1_TFIFO                  0xFFC40558         /* SPI1 Transmit FIFO Data Register */
+/* =========================
+        SPORT Registers
+   ========================= */
+/* =========================
+        SPORT0
+   ========================= */
+#define SPORT0_CTL_A                0xFFC40000         /* SPORT0 'A' Control Register */
+#define SPORT0_DIV_A                0xFFC40004         /* SPORT0 'A' Clock and FS Divide Register */
+#define SPORT0_MCTL_A               0xFFC40008         /* SPORT0 'A' Multichannel Control Register */
+#define SPORT0_CS0_A                0xFFC4000C         /* SPORT0 'A' Multichannel Select Register (Channels 0-31) */
+#define SPORT0_CS1_A                0xFFC40010         /* SPORT0 'A' Multichannel Select Register (Channels 32-63) */
+#define SPORT0_CS2_A                0xFFC40014         /* SPORT0 'A' Multichannel Select Register (Channels 64-95) */
+#define SPORT0_CS3_A                0xFFC40018         /* SPORT0 'A' Multichannel Select Register (Channels 96-127) */
+#define SPORT0_CNT_A                0xFFC4001C         /* SPORT0 'A' Frame Sync And Clock Divisor Current Count */
+#define SPORT0_ERR_A                0xFFC40020         /* SPORT0 'A' Error Register */
+#define SPORT0_MSTAT_A              0xFFC40024         /* SPORT0 'A' Multichannel Mode Status Register */
+#define SPORT0_CTL2_A               0xFFC40028         /* SPORT0 'A' Control Register 2 */
+#define SPORT0_TXPRI_A              0xFFC40040         /* SPORT0 'A' Primary Channel Transmit Buffer Register */
+#define SPORT0_RXPRI_A              0xFFC40044         /* SPORT0 'A' Primary Channel Receive Buffer Register */
+#define SPORT0_TXSEC_A              0xFFC40048         /* SPORT0 'A' Secondary Channel Transmit Buffer Register */
+#define SPORT0_RXSEC_A              0xFFC4004C         /* SPORT0 'A' Secondary Channel Receive Buffer Register */
+#define SPORT0_CTL_B                0xFFC40080         /* SPORT0 'B' Control Register */
+#define SPORT0_DIV_B                0xFFC40084         /* SPORT0 'B' Clock and FS Divide Register */
+#define SPORT0_MCTL_B               0xFFC40088         /* SPORT0 'B' Multichannel Control Register */
+#define SPORT0_CS0_B                0xFFC4008C         /* SPORT0 'B' Multichannel Select Register (Channels 0-31) */
+#define SPORT0_CS1_B                0xFFC40090         /* SPORT0 'B' Multichannel Select Register (Channels 32-63) */
+#define SPORT0_CS2_B                0xFFC40094         /* SPORT0 'B' Multichannel Select Register (Channels 64-95) */
+#define SPORT0_CS3_B                0xFFC40098         /* SPORT0 'B' Multichannel Select Register (Channels 96-127) */
+#define SPORT0_CNT_B                0xFFC4009C         /* SPORT0 'B' Frame Sync And Clock Divisor Current Count */
+#define SPORT0_ERR_B                0xFFC400A0         /* SPORT0 'B' Error Register */
+#define SPORT0_MSTAT_B              0xFFC400A4         /* SPORT0 'B' Multichannel Mode Status Register */
+#define SPORT0_CTL2_B               0xFFC400A8         /* SPORT0 'B' Control Register 2 */
+#define SPORT0_TXPRI_B              0xFFC400C0         /* SPORT0 'B' Primary Channel Transmit Buffer Register */
+#define SPORT0_RXPRI_B              0xFFC400C4         /* SPORT0 'B' Primary Channel Receive Buffer Register */
+#define SPORT0_TXSEC_B              0xFFC400C8         /* SPORT0 'B' Secondary Channel Transmit Buffer Register */
+#define SPORT0_RXSEC_B              0xFFC400CC         /* SPORT0 'B' Secondary Channel Receive Buffer Register */
+/* =========================
+        SPORT1
+   ========================= */
+#define SPORT1_CTL_A                0xFFC40100         /* SPORT1 'A' Control Register */
+#define SPORT1_DIV_A                0xFFC40104         /* SPORT1 'A' Clock and FS Divide Register */
+#define SPORT1_MCTL_A               0xFFC40108         /* SPORT1 'A' Multichannel Control Register */
+#define SPORT1_CS0_A                0xFFC4010C         /* SPORT1 'A' Multichannel Select Register (Channels 0-31) */
+#define SPORT1_CS1_A                0xFFC40110         /* SPORT1 'A' Multichannel Select Register (Channels 32-63) */
+#define SPORT1_CS2_A                0xFFC40114         /* SPORT1 'A' Multichannel Select Register (Channels 64-95) */
+#define SPORT1_CS3_A                0xFFC40118         /* SPORT1 'A' Multichannel Select Register (Channels 96-127) */
+#define SPORT1_CNT_A                0xFFC4011C         /* SPORT1 'A' Frame Sync And Clock Divisor Current Count */
+#define SPORT1_ERR_A                0xFFC40120         /* SPORT1 'A' Error Register */
+#define SPORT1_MSTAT_A              0xFFC40124         /* SPORT1 'A' Multichannel Mode Status Register */
+#define SPORT1_CTL2_A               0xFFC40128         /* SPORT1 'A' Control Register 2 */
+#define SPORT1_TXPRI_A              0xFFC40140         /* SPORT1 'A' Primary Channel Transmit Buffer Register */
+#define SPORT1_RXPRI_A              0xFFC40144         /* SPORT1 'A' Primary Channel Receive Buffer Register */
+#define SPORT1_TXSEC_A              0xFFC40148         /* SPORT1 'A' Secondary Channel Transmit Buffer Register */
+#define SPORT1_RXSEC_A              0xFFC4014C         /* SPORT1 'A' Secondary Channel Receive Buffer Register */
+#define SPORT1_CTL_B                0xFFC40180         /* SPORT1 'B' Control Register */
+#define SPORT1_DIV_B                0xFFC40184         /* SPORT1 'B' Clock and FS Divide Register */
+#define SPORT1_MCTL_B               0xFFC40188         /* SPORT1 'B' Multichannel Control Register */
+#define SPORT1_CS0_B                0xFFC4018C         /* SPORT1 'B' Multichannel Select Register (Channels 0-31) */
+#define SPORT1_CS1_B                0xFFC40190         /* SPORT1 'B' Multichannel Select Register (Channels 32-63) */
+#define SPORT1_CS2_B                0xFFC40194         /* SPORT1 'B' Multichannel Select Register (Channels 64-95) */
+#define SPORT1_CS3_B                0xFFC40198         /* SPORT1 'B' Multichannel Select Register (Channels 96-127) */
+#define SPORT1_CNT_B                0xFFC4019C         /* SPORT1 'B' Frame Sync And Clock Divisor Current Count */
+#define SPORT1_ERR_B                0xFFC401A0         /* SPORT1 'B' Error Register */
+#define SPORT1_MSTAT_B              0xFFC401A4         /* SPORT1 'B' Multichannel Mode Status Register */
+#define SPORT1_CTL2_B               0xFFC401A8         /* SPORT1 'B' Control Register 2 */
+#define SPORT1_TXPRI_B              0xFFC401C0         /* SPORT1 'B' Primary Channel Transmit Buffer Register */
+#define SPORT1_RXPRI_B              0xFFC401C4         /* SPORT1 'B' Primary Channel Receive Buffer Register */
+#define SPORT1_TXSEC_B              0xFFC401C8         /* SPORT1 'B' Secondary Channel Transmit Buffer Register */
+#define SPORT1_RXSEC_B              0xFFC401CC         /* SPORT1 'B' Secondary Channel Receive Buffer Register */
+/* =========================
+        SPORT2
+   ========================= */
+#define SPORT2_CTL_A                0xFFC40200         /* SPORT2 'A' Control Register */
+#define SPORT2_DIV_A                0xFFC40204         /* SPORT2 'A' Clock and FS Divide Register */
+#define SPORT2_MCTL_A               0xFFC40208         /* SPORT2 'A' Multichannel Control Register */
+#define SPORT2_CS0_A                0xFFC4020C         /* SPORT2 'A' Multichannel Select Register (Channels 0-31) */
+#define SPORT2_CS1_A                0xFFC40210         /* SPORT2 'A' Multichannel Select Register (Channels 32-63) */
+#define SPORT2_CS2_A                0xFFC40214         /* SPORT2 'A' Multichannel Select Register (Channels 64-95) */
+#define SPORT2_CS3_A                0xFFC40218         /* SPORT2 'A' Multichannel Select Register (Channels 96-127) */
+#define SPORT2_CNT_A                0xFFC4021C         /* SPORT2 'A' Frame Sync And Clock Divisor Current Count */
+#define SPORT2_ERR_A                0xFFC40220         /* SPORT2 'A' Error Register */
+#define SPORT2_MSTAT_A              0xFFC40224         /* SPORT2 'A' Multichannel Mode Status Register */
+#define SPORT2_CTL2_A               0xFFC40228         /* SPORT2 'A' Control Register 2 */
+#define SPORT2_TXPRI_A              0xFFC40240         /* SPORT2 'A' Primary Channel Transmit Buffer Register */
+#define SPORT2_RXPRI_A              0xFFC40244         /* SPORT2 'A' Primary Channel Receive Buffer Register */
+#define SPORT2_TXSEC_A              0xFFC40248         /* SPORT2 'A' Secondary Channel Transmit Buffer Register */
+#define SPORT2_RXSEC_A              0xFFC4024C         /* SPORT2 'A' Secondary Channel Receive Buffer Register */
+#define SPORT2_CTL_B                0xFFC40280         /* SPORT2 'B' Control Register */
+#define SPORT2_DIV_B                0xFFC40284         /* SPORT2 'B' Clock and FS Divide Register */
+#define SPORT2_MCTL_B               0xFFC40288         /* SPORT2 'B' Multichannel Control Register */
+#define SPORT2_CS0_B                0xFFC4028C         /* SPORT2 'B' Multichannel Select Register (Channels 0-31) */
+#define SPORT2_CS1_B                0xFFC40290         /* SPORT2 'B' Multichannel Select Register (Channels 32-63) */
+#define SPORT2_CS2_B                0xFFC40294         /* SPORT2 'B' Multichannel Select Register (Channels 64-95) */
+#define SPORT2_CS3_B                0xFFC40298         /* SPORT2 'B' Multichannel Select Register (Channels 96-127) */
+#define SPORT2_CNT_B                0xFFC4029C         /* SPORT2 'B' Frame Sync And Clock Divisor Current Count */
+#define SPORT2_ERR_B                0xFFC402A0         /* SPORT2 'B' Error Register */
+#define SPORT2_MSTAT_B              0xFFC402A4         /* SPORT2 'B' Multichannel Mode Status Register */
+#define SPORT2_CTL2_B               0xFFC402A8         /* SPORT2 'B' Control Register 2 */
+#define SPORT2_TXPRI_B              0xFFC402C0         /* SPORT2 'B' Primary Channel Transmit Buffer Register */
+#define SPORT2_RXPRI_B              0xFFC402C4         /* SPORT2 'B' Primary Channel Receive Buffer Register */
+#define SPORT2_TXSEC_B              0xFFC402C8         /* SPORT2 'B' Secondary Channel Transmit Buffer Register */
+#define SPORT2_RXSEC_B              0xFFC402CC         /* SPORT2 'B' Secondary Channel Receive Buffer Register */
+/* =========================
+        EPPI Registers
+   ========================= */
+/* =========================
+        EPPI0
+   ========================= */
+#define EPPI0_STAT                  0xFFC18000         /* EPPI0 Status Register */
+#define EPPI0_HCNT                  0xFFC18004         /* EPPI0 Horizontal Transfer Count Register */
+#define EPPI0_HDLY                  0xFFC18008         /* EPPI0 Horizontal Delay Count Register */
+#define EPPI0_VCNT                  0xFFC1800C         /* EPPI0 Vertical Transfer Count Register */
+#define EPPI0_VDLY                  0xFFC18010         /* EPPI0 Vertical Delay Count Register */
+#define EPPI0_FRAME                 0xFFC18014         /* EPPI0 Lines Per Frame Register */
+#define EPPI0_LINE                  0xFFC18018         /* EPPI0 Samples Per Line Register */
+#define EPPI0_CLKDIV                0xFFC1801C         /* EPPI0 Clock Divide Register */
+#define EPPI0_CTL                   0xFFC18020         /* EPPI0 Control Register */
+#define EPPI0_FS1_WLHB              0xFFC18024         /* EPPI0 FS1 Width Register / EPPI Horizontal Blanking Samples Per Line Register */
+#define EPPI0_FS1_PASPL             0xFFC18028         /* EPPI0 FS1 Period Register / EPPI Active Samples Per Line Register */
+#define EPPI0_FS2_WLVB              0xFFC1802C         /* EPPI0 FS2 Width Register / EPPI Lines Of Vertical Blanking Register */
+#define EPPI0_FS2_PALPF             0xFFC18030         /* EPPI0 FS2 Period Register / EPPI Active Lines Per Field Register */
+#define EPPI0_IMSK                  0xFFC18034         /* EPPI0 Interrupt Mask Register */
+#define EPPI0_ODDCLIP               0xFFC1803C         /* EPPI0 Clipping Register for ODD (Chroma) Data */
+#define EPPI0_EVENCLIP              0xFFC18040         /* EPPI0 Clipping Register for EVEN (Luma) Data */
+#define EPPI0_FS1_DLY               0xFFC18044         /* EPPI0 Frame Sync 1 Delay Value */
+#define EPPI0_FS2_DLY               0xFFC18048         /* EPPI0 Frame Sync 2 Delay Value */
+#define EPPI0_CTL2                  0xFFC1804C         /* EPPI0 Control Register 2 */
+/* =========================
+        EPPI1
+   ========================= */
+#define EPPI1_STAT                  0xFFC18400         /* EPPI1 Status Register */
+#define EPPI1_HCNT                  0xFFC18404         /* EPPI1 Horizontal Transfer Count Register */
+#define EPPI1_HDLY                  0xFFC18408         /* EPPI1 Horizontal Delay Count Register */
+#define EPPI1_VCNT                  0xFFC1840C         /* EPPI1 Vertical Transfer Count Register */
+#define EPPI1_VDLY                  0xFFC18410         /* EPPI1 Vertical Delay Count Register */
+#define EPPI1_FRAME                 0xFFC18414         /* EPPI1 Lines Per Frame Register */
+#define EPPI1_LINE                  0xFFC18418         /* EPPI1 Samples Per Line Register */
+#define EPPI1_CLKDIV                0xFFC1841C         /* EPPI1 Clock Divide Register */
+#define EPPI1_CTL                   0xFFC18420         /* EPPI1 Control Register */
+#define EPPI1_FS1_WLHB              0xFFC18424         /* EPPI1 FS1 Width Register / EPPI Horizontal Blanking Samples Per Line Register */
+#define EPPI1_FS1_PASPL             0xFFC18428         /* EPPI1 FS1 Period Register / EPPI Active Samples Per Line Register */
+#define EPPI1_FS2_WLVB              0xFFC1842C         /* EPPI1 FS2 Width Register / EPPI Lines Of Vertical Blanking Register */
+#define EPPI1_FS2_PALPF             0xFFC18430         /* EPPI1 FS2 Period Register / EPPI Active Lines Per Field Register */
+#define EPPI1_IMSK                  0xFFC18434         /* EPPI1 Interrupt Mask Register */
+#define EPPI1_ODDCLIP               0xFFC1843C         /* EPPI1 Clipping Register for ODD (Chroma) Data */
+#define EPPI1_EVENCLIP              0xFFC18440         /* EPPI1 Clipping Register for EVEN (Luma) Data */
+#define EPPI1_FS1_DLY               0xFFC18444         /* EPPI1 Frame Sync 1 Delay Value */
+#define EPPI1_FS2_DLY               0xFFC18448         /* EPPI1 Frame Sync 2 Delay Value */
+#define EPPI1_CTL2                  0xFFC1844C         /* EPPI1 Control Register 2 */
+/* =========================
+        EPPI2
+   ========================= */
+#define EPPI2_STAT                  0xFFC18800         /* EPPI2 Status Register */
+#define EPPI2_HCNT                  0xFFC18804         /* EPPI2 Horizontal Transfer Count Register */
+#define EPPI2_HDLY                  0xFFC18808         /* EPPI2 Horizontal Delay Count Register */
+#define EPPI2_VCNT                  0xFFC1880C         /* EPPI2 Vertical Transfer Count Register */
+#define EPPI2_VDLY                  0xFFC18810         /* EPPI2 Vertical Delay Count Register */
+#define EPPI2_FRAME                 0xFFC18814         /* EPPI2 Lines Per Frame Register */
+#define EPPI2_LINE                  0xFFC18818         /* EPPI2 Samples Per Line Register */
+#define EPPI2_CLKDIV                0xFFC1881C         /* EPPI2 Clock Divide Register */
+#define EPPI2_CTL                   0xFFC18820         /* EPPI2 Control Register */
+#define EPPI2_FS1_WLHB              0xFFC18824         /* EPPI2 FS1 Width Register / EPPI Horizontal Blanking Samples Per Line Register */
+#define EPPI2_FS1_PASPL             0xFFC18828         /* EPPI2 FS1 Period Register / EPPI Active Samples Per Line Register */
+#define EPPI2_FS2_WLVB              0xFFC1882C         /* EPPI2 FS2 Width Register / EPPI Lines Of Vertical Blanking Register */
+#define EPPI2_FS2_PALPF             0xFFC18830         /* EPPI2 FS2 Period Register / EPPI Active Lines Per Field Register */
+#define EPPI2_IMSK                  0xFFC18834         /* EPPI2 Interrupt Mask Register */
+#define EPPI2_ODDCLIP               0xFFC1883C         /* EPPI2 Clipping Register for ODD (Chroma) Data */
+#define EPPI2_EVENCLIP              0xFFC18840         /* EPPI2 Clipping Register for EVEN (Luma) Data */
+#define EPPI2_FS1_DLY               0xFFC18844         /* EPPI2 Frame Sync 1 Delay Value */
+#define EPPI2_FS2_DLY               0xFFC18848         /* EPPI2 Frame Sync 2 Delay Value */
+#define EPPI2_CTL2                  0xFFC1884C         /* EPPI2 Control Register 2 */
+/* =========================
+        DDE Registers
+   ========================= */
+/* =========================
+        DMA0
+   ========================= */
+#define DMA0_NEXT_DESC_PTR          0xFFC41000         /* DMA0 Pointer to Next Initial Descriptor */
+#define DMA0_START_ADDR             0xFFC41004         /* DMA0 Start Address of Current Buffer */
+#define DMA0_CONFIG                 0xFFC41008         /* DMA0 Configuration Register */
+#define DMA0_X_COUNT                0xFFC4100C         /* DMA0 Inner Loop Count Start Value */
+#define DMA0_X_MODIFY               0xFFC41010         /* DMA0 Inner Loop Address Increment */
+#define DMA0_Y_COUNT                0xFFC41014         /* DMA0 Outer Loop Count Start Value (2D only) */
+#define DMA0_Y_MODIFY               0xFFC41018         /* DMA0 Outer Loop Address Increment (2D only) */
+#define DMA0_CURR_DESC_PTR          0xFFC41024         /* DMA0 Current Descriptor Pointer */
+#define DMA0_PREV_DESC_PTR          0xFFC41028         /* DMA0 Previous Initial Descriptor Pointer */
+#define DMA0_CURR_ADDR              0xFFC4102C         /* DMA0 Current Address */
+#define DMA0_IRQ_STATUS             0xFFC41030         /* DMA0 Status Register */
+#define DMA0_CURR_X_COUNT           0xFFC41034         /* DMA0 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA0_CURR_Y_COUNT           0xFFC41038         /* DMA0 Current Row Count (2D only) */
+#define DMA0_BWL_COUNT              0xFFC41040         /* DMA0 Bandwidth Limit Count */
+#define DMA0_CURR_BWL_COUNT         0xFFC41044         /* DMA0 Bandwidth Limit Count Current */
+#define DMA0_BWM_COUNT              0xFFC41048         /* DMA0 Bandwidth Monitor Count */
+#define DMA0_CURR_BWM_COUNT         0xFFC4104C         /* DMA0 Bandwidth Monitor Count Current */
+/* =========================
+        DMA1
+   ========================= */
+#define DMA1_NEXT_DESC_PTR             0xFFC41080         /* DMA1 Pointer to Next Initial Descriptor */
+#define DMA1_START_ADDR              0xFFC41084         /* DMA1 Start Address of Current Buffer */
+#define DMA1_CONFIG                    0xFFC41088         /* DMA1 Configuration Register */
+#define DMA1_X_COUNT                   0xFFC4108C         /* DMA1 Inner Loop Count Start Value */
+#define DMA1_X_MODIFY                   0xFFC41090         /* DMA1 Inner Loop Address Increment */
+#define DMA1_Y_COUNT                   0xFFC41094         /* DMA1 Outer Loop Count Start Value (2D only) */
+#define DMA1_Y_MODIFY                   0xFFC41098         /* DMA1 Outer Loop Address Increment (2D only) */
+#define DMA1_CURR_DESC_PTR             0xFFC410A4         /* DMA1 Current Descriptor Pointer */
+#define DMA1_PREV_DESC_PTR             0xFFC410A8         /* DMA1 Previous Initial Descriptor Pointer */
+#define DMA1_CURR_ADDR               0xFFC410AC         /* DMA1 Current Address */
+#define DMA1_IRQ_STATUS                   0xFFC410B0         /* DMA1 Status Register */
+#define DMA1_CURR_X_COUNT               0xFFC410B4         /* DMA1 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA1_CURR_Y_COUNT               0xFFC410B8         /* DMA1 Current Row Count (2D only) */
+#define DMA1_BWL_COUNT                 0xFFC410C0         /* DMA1 Bandwidth Limit Count */
+#define DMA1_CURR_BWL_COUNT             0xFFC410C4         /* DMA1 Bandwidth Limit Count Current */
+#define DMA1_BWM_COUNT                 0xFFC410C8         /* DMA1 Bandwidth Monitor Count */
+#define DMA1_CURR_BWM_COUNT             0xFFC410CC         /* DMA1 Bandwidth Monitor Count Current */
+/* =========================
+        DMA2
+   ========================= */
+#define DMA2_NEXT_DESC_PTR             0xFFC41100         /* DMA2 Pointer to Next Initial Descriptor */
+#define DMA2_START_ADDR              0xFFC41104         /* DMA2 Start Address of Current Buffer */
+#define DMA2_CONFIG                    0xFFC41108         /* DMA2 Configuration Register */
+#define DMA2_X_COUNT                   0xFFC4110C         /* DMA2 Inner Loop Count Start Value */
+#define DMA2_X_MODIFY                   0xFFC41110         /* DMA2 Inner Loop Address Increment */
+#define DMA2_Y_COUNT                   0xFFC41114         /* DMA2 Outer Loop Count Start Value (2D only) */
+#define DMA2_Y_MODIFY                   0xFFC41118         /* DMA2 Outer Loop Address Increment (2D only) */
+#define DMA2_CURR_DESC_PTR             0xFFC41124         /* DMA2 Current Descriptor Pointer */
+#define DMA2_PREV_DESC_PTR             0xFFC41128         /* DMA2 Previous Initial Descriptor Pointer */
+#define DMA2_CURR_ADDR               0xFFC4112C         /* DMA2 Current Address */
+#define DMA2_IRQ_STATUS                   0xFFC41130         /* DMA2 Status Register */
+#define DMA2_CURR_X_COUNT               0xFFC41134         /* DMA2 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA2_CURR_Y_COUNT               0xFFC41138         /* DMA2 Current Row Count (2D only) */
+#define DMA2_BWL_COUNT                 0xFFC41140         /* DMA2 Bandwidth Limit Count */
+#define DMA2_CURR_BWL_COUNT             0xFFC41144         /* DMA2 Bandwidth Limit Count Current */
+#define DMA2_BWM_COUNT                 0xFFC41148         /* DMA2 Bandwidth Monitor Count */
+#define DMA2_CURR_BWM_COUNT             0xFFC4114C         /* DMA2 Bandwidth Monitor Count Current */
+/* =========================
+        DMA3
+   ========================= */
+#define DMA3_NEXT_DESC_PTR             0xFFC41180         /* DMA3 Pointer to Next Initial Descriptor */
+#define DMA3_START_ADDR              0xFFC41184         /* DMA3 Start Address of Current Buffer */
+#define DMA3_CONFIG                    0xFFC41188         /* DMA3 Configuration Register */
+#define DMA3_X_COUNT                   0xFFC4118C         /* DMA3 Inner Loop Count Start Value */
+#define DMA3_X_MODIFY                   0xFFC41190         /* DMA3 Inner Loop Address Increment */
+#define DMA3_Y_COUNT                   0xFFC41194         /* DMA3 Outer Loop Count Start Value (2D only) */
+#define DMA3_Y_MODIFY                   0xFFC41198         /* DMA3 Outer Loop Address Increment (2D only) */
+#define DMA3_CURR_DESC_PTR             0xFFC411A4         /* DMA3 Current Descriptor Pointer */
+#define DMA3_PREV_DESC_PTR             0xFFC411A8         /* DMA3 Previous Initial Descriptor Pointer */
+#define DMA3_CURR_ADDR               0xFFC411AC         /* DMA3 Current Address */
+#define DMA3_IRQ_STATUS                   0xFFC411B0         /* DMA3 Status Register */
+#define DMA3_CURR_X_COUNT               0xFFC411B4         /* DMA3 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA3_CURR_Y_COUNT               0xFFC411B8         /* DMA3 Current Row Count (2D only) */
+#define DMA3_BWL_COUNT                 0xFFC411C0         /* DMA3 Bandwidth Limit Count */
+#define DMA3_CURR_BWL_COUNT             0xFFC411C4         /* DMA3 Bandwidth Limit Count Current */
+#define DMA3_BWM_COUNT                 0xFFC411C8         /* DMA3 Bandwidth Monitor Count */
+#define DMA3_CURR_BWM_COUNT             0xFFC411CC         /* DMA3 Bandwidth Monitor Count Current */
+/* =========================
+        DMA4
+   ========================= */
+#define DMA4_NEXT_DESC_PTR             0xFFC41200         /* DMA4 Pointer to Next Initial Descriptor */
+#define DMA4_START_ADDR              0xFFC41204         /* DMA4 Start Address of Current Buffer */
+#define DMA4_CONFIG                    0xFFC41208         /* DMA4 Configuration Register */
+#define DMA4_X_COUNT                   0xFFC4120C         /* DMA4 Inner Loop Count Start Value */
+#define DMA4_X_MODIFY                   0xFFC41210         /* DMA4 Inner Loop Address Increment */
+#define DMA4_Y_COUNT                   0xFFC41214         /* DMA4 Outer Loop Count Start Value (2D only) */
+#define DMA4_Y_MODIFY                   0xFFC41218         /* DMA4 Outer Loop Address Increment (2D only) */
+#define DMA4_CURR_DESC_PTR             0xFFC41224         /* DMA4 Current Descriptor Pointer */
+#define DMA4_PREV_DESC_PTR             0xFFC41228         /* DMA4 Previous Initial Descriptor Pointer */
+#define DMA4_CURR_ADDR               0xFFC4122C         /* DMA4 Current Address */
+#define DMA4_IRQ_STATUS                   0xFFC41230         /* DMA4 Status Register */
+#define DMA4_CURR_X_COUNT               0xFFC41234         /* DMA4 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA4_CURR_Y_COUNT               0xFFC41238         /* DMA4 Current Row Count (2D only) */
+#define DMA4_BWL_COUNT                 0xFFC41240         /* DMA4 Bandwidth Limit Count */
+#define DMA4_CURR_BWL_COUNT             0xFFC41244         /* DMA4 Bandwidth Limit Count Current */
+#define DMA4_BWM_COUNT                 0xFFC41248         /* DMA4 Bandwidth Monitor Count */
+#define DMA4_CURR_BWM_COUNT             0xFFC4124C         /* DMA4 Bandwidth Monitor Count Current */
+/* =========================
+        DMA5
+   ========================= */
+#define DMA5_NEXT_DESC_PTR             0xFFC41280         /* DMA5 Pointer to Next Initial Descriptor */
+#define DMA5_START_ADDR              0xFFC41284         /* DMA5 Start Address of Current Buffer */
+#define DMA5_CONFIG                    0xFFC41288         /* DMA5 Configuration Register */
+#define DMA5_X_COUNT                   0xFFC4128C         /* DMA5 Inner Loop Count Start Value */
+#define DMA5_X_MODIFY                   0xFFC41290         /* DMA5 Inner Loop Address Increment */
+#define DMA5_Y_COUNT                   0xFFC41294         /* DMA5 Outer Loop Count Start Value (2D only) */
+#define DMA5_Y_MODIFY                   0xFFC41298         /* DMA5 Outer Loop Address Increment (2D only) */
+#define DMA5_CURR_DESC_PTR             0xFFC412A4         /* DMA5 Current Descriptor Pointer */
+#define DMA5_PREV_DESC_PTR             0xFFC412A8         /* DMA5 Previous Initial Descriptor Pointer */
+#define DMA5_CURR_ADDR               0xFFC412AC         /* DMA5 Current Address */
+#define DMA5_IRQ_STATUS                   0xFFC412B0         /* DMA5 Status Register */
+#define DMA5_CURR_X_COUNT               0xFFC412B4         /* DMA5 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA5_CURR_Y_COUNT               0xFFC412B8         /* DMA5 Current Row Count (2D only) */
+#define DMA5_BWL_COUNT                 0xFFC412C0         /* DMA5 Bandwidth Limit Count */
+#define DMA5_CURR_BWL_COUNT             0xFFC412C4         /* DMA5 Bandwidth Limit Count Current */
+#define DMA5_BWM_COUNT                 0xFFC412C8         /* DMA5 Bandwidth Monitor Count */
+#define DMA5_CURR_BWM_COUNT             0xFFC412CC         /* DMA5 Bandwidth Monitor Count Current */
+/* =========================
+        DMA6
+   ========================= */
+#define DMA6_NEXT_DESC_PTR             0xFFC41300         /* DMA6 Pointer to Next Initial Descriptor */
+#define DMA6_START_ADDR              0xFFC41304         /* DMA6 Start Address of Current Buffer */
+#define DMA6_CONFIG                    0xFFC41308         /* DMA6 Configuration Register */
+#define DMA6_X_COUNT                   0xFFC4130C         /* DMA6 Inner Loop Count Start Value */
+#define DMA6_X_MODIFY                   0xFFC41310         /* DMA6 Inner Loop Address Increment */
+#define DMA6_Y_COUNT                   0xFFC41314         /* DMA6 Outer Loop Count Start Value (2D only) */
+#define DMA6_Y_MODIFY                   0xFFC41318         /* DMA6 Outer Loop Address Increment (2D only) */
+#define DMA6_CURR_DESC_PTR             0xFFC41324         /* DMA6 Current Descriptor Pointer */
+#define DMA6_PREV_DESC_PTR             0xFFC41328         /* DMA6 Previous Initial Descriptor Pointer */
+#define DMA6_CURR_ADDR               0xFFC4132C         /* DMA6 Current Address */
+#define DMA6_IRQ_STATUS                   0xFFC41330         /* DMA6 Status Register */
+#define DMA6_CURR_X_COUNT               0xFFC41334         /* DMA6 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA6_CURR_Y_COUNT               0xFFC41338         /* DMA6 Current Row Count (2D only) */
+#define DMA6_BWL_COUNT                 0xFFC41340         /* DMA6 Bandwidth Limit Count */
+#define DMA6_CURR_BWL_COUNT             0xFFC41344         /* DMA6 Bandwidth Limit Count Current */
+#define DMA6_BWM_COUNT                 0xFFC41348         /* DMA6 Bandwidth Monitor Count */
+#define DMA6_CURR_BWM_COUNT             0xFFC4134C         /* DMA6 Bandwidth Monitor Count Current */
+/* =========================
+        DMA7
+   ========================= */
+#define DMA7_NEXT_DESC_PTR             0xFFC41380         /* DMA7 Pointer to Next Initial Descriptor */
+#define DMA7_START_ADDR              0xFFC41384         /* DMA7 Start Address of Current Buffer */
+#define DMA7_CONFIG                    0xFFC41388         /* DMA7 Configuration Register */
+#define DMA7_X_COUNT                   0xFFC4138C         /* DMA7 Inner Loop Count Start Value */
+#define DMA7_X_MODIFY                   0xFFC41390         /* DMA7 Inner Loop Address Increment */
+#define DMA7_Y_COUNT                   0xFFC41394         /* DMA7 Outer Loop Count Start Value (2D only) */
+#define DMA7_Y_MODIFY                   0xFFC41398         /* DMA7 Outer Loop Address Increment (2D only) */
+#define DMA7_CURR_DESC_PTR             0xFFC413A4         /* DMA7 Current Descriptor Pointer */
+#define DMA7_PREV_DESC_PTR             0xFFC413A8         /* DMA7 Previous Initial Descriptor Pointer */
+#define DMA7_CURR_ADDR               0xFFC413AC         /* DMA7 Current Address */
+#define DMA7_IRQ_STATUS                   0xFFC413B0         /* DMA7 Status Register */
+#define DMA7_CURR_X_COUNT               0xFFC413B4         /* DMA7 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA7_CURR_Y_COUNT               0xFFC413B8         /* DMA7 Current Row Count (2D only) */
+#define DMA7_BWL_COUNT                 0xFFC413C0         /* DMA7 Bandwidth Limit Count */
+#define DMA7_CURR_BWL_COUNT             0xFFC413C4         /* DMA7 Bandwidth Limit Count Current */
+#define DMA7_BWM_COUNT                 0xFFC413C8         /* DMA7 Bandwidth Monitor Count */
+#define DMA7_CURR_BWM_COUNT             0xFFC413CC         /* DMA7 Bandwidth Monitor Count Current */
+/* =========================
+        DMA8
+   ========================= */
+#define DMA8_NEXT_DESC_PTR             0xFFC41400         /* DMA8 Pointer to Next Initial Descriptor */
+#define DMA8_START_ADDR              0xFFC41404         /* DMA8 Start Address of Current Buffer */
+#define DMA8_CONFIG                    0xFFC41408         /* DMA8 Configuration Register */
+#define DMA8_X_COUNT                   0xFFC4140C         /* DMA8 Inner Loop Count Start Value */
+#define DMA8_X_MODIFY                   0xFFC41410         /* DMA8 Inner Loop Address Increment */
+#define DMA8_Y_COUNT                   0xFFC41414         /* DMA8 Outer Loop Count Start Value (2D only) */
+#define DMA8_Y_MODIFY                   0xFFC41418         /* DMA8 Outer Loop Address Increment (2D only) */
+#define DMA8_CURR_DESC_PTR             0xFFC41424         /* DMA8 Current Descriptor Pointer */
+#define DMA8_PREV_DESC_PTR             0xFFC41428         /* DMA8 Previous Initial Descriptor Pointer */
+#define DMA8_CURR_ADDR               0xFFC4142C         /* DMA8 Current Address */
+#define DMA8_IRQ_STATUS                   0xFFC41430         /* DMA8 Status Register */
+#define DMA8_CURR_X_COUNT               0xFFC41434         /* DMA8 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA8_CURR_Y_COUNT               0xFFC41438         /* DMA8 Current Row Count (2D only) */
+#define DMA8_BWL_COUNT                 0xFFC41440         /* DMA8 Bandwidth Limit Count */
+#define DMA8_CURR_BWL_COUNT             0xFFC41444         /* DMA8 Bandwidth Limit Count Current */
+#define DMA8_BWM_COUNT                 0xFFC41448         /* DMA8 Bandwidth Monitor Count */
+#define DMA8_CURR_BWM_COUNT             0xFFC4144C         /* DMA8 Bandwidth Monitor Count Current */
+/* =========================
+        DMA9
+   ========================= */
+#define DMA9_NEXT_DESC_PTR             0xFFC41480         /* DMA9 Pointer to Next Initial Descriptor */
+#define DMA9_START_ADDR              0xFFC41484         /* DMA9 Start Address of Current Buffer */
+#define DMA9_CONFIG                    0xFFC41488         /* DMA9 Configuration Register */
+#define DMA9_X_COUNT                   0xFFC4148C         /* DMA9 Inner Loop Count Start Value */
+#define DMA9_X_MODIFY                   0xFFC41490         /* DMA9 Inner Loop Address Increment */
+#define DMA9_Y_COUNT                   0xFFC41494         /* DMA9 Outer Loop Count Start Value (2D only) */
+#define DMA9_Y_MODIFY                   0xFFC41498         /* DMA9 Outer Loop Address Increment (2D only) */
+#define DMA9_CURR_DESC_PTR             0xFFC414A4         /* DMA9 Current Descriptor Pointer */
+#define DMA9_PREV_DESC_PTR             0xFFC414A8         /* DMA9 Previous Initial Descriptor Pointer */
+#define DMA9_CURR_ADDR               0xFFC414AC         /* DMA9 Current Address */
+#define DMA9_IRQ_STATUS                   0xFFC414B0         /* DMA9 Status Register */
+#define DMA9_CURR_X_COUNT               0xFFC414B4         /* DMA9 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA9_CURR_Y_COUNT               0xFFC414B8         /* DMA9 Current Row Count (2D only) */
+#define DMA9_BWL_COUNT                 0xFFC414C0         /* DMA9 Bandwidth Limit Count */
+#define DMA9_CURR_BWL_COUNT             0xFFC414C4         /* DMA9 Bandwidth Limit Count Current */
+#define DMA9_BWM_COUNT                 0xFFC414C8         /* DMA9 Bandwidth Monitor Count */
+#define DMA9_CURR_BWM_COUNT             0xFFC414CC         /* DMA9 Bandwidth Monitor Count Current */
+/* =========================
+        DMA10
+   ========================= */
+#define DMA10_NEXT_DESC_PTR            0xFFC05000         /* DMA10 Pointer to Next Initial Descriptor */
+#define DMA10_START_ADDR             0xFFC05004         /* DMA10 Start Address of Current Buffer */
+#define DMA10_CONFIG                   0xFFC05008         /* DMA10 Configuration Register */
+#define DMA10_X_COUNT                  0xFFC0500C         /* DMA10 Inner Loop Count Start Value */
+#define DMA10_X_MODIFY                  0xFFC05010         /* DMA10 Inner Loop Address Increment */
+#define DMA10_Y_COUNT                  0xFFC05014         /* DMA10 Outer Loop Count Start Value (2D only) */
+#define DMA10_Y_MODIFY                  0xFFC05018         /* DMA10 Outer Loop Address Increment (2D only) */
+#define DMA10_CURR_DESC_PTR            0xFFC05024         /* DMA10 Current Descriptor Pointer */
+#define DMA10_PREV_DESC_PTR            0xFFC05028         /* DMA10 Previous Initial Descriptor Pointer */
+#define DMA10_CURR_ADDR              0xFFC0502C         /* DMA10 Current Address */
+#define DMA10_IRQ_STATUS                  0xFFC05030         /* DMA10 Status Register */
+#define DMA10_CURR_X_COUNT              0xFFC05034         /* DMA10 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA10_CURR_Y_COUNT              0xFFC05038         /* DMA10 Current Row Count (2D only) */
+#define DMA10_BWL_COUNT                0xFFC05040         /* DMA10 Bandwidth Limit Count */
+#define DMA10_CURR_BWL_COUNT            0xFFC05044         /* DMA10 Bandwidth Limit Count Current */
+#define DMA10_BWM_COUNT                0xFFC05048         /* DMA10 Bandwidth Monitor Count */
+#define DMA10_CURR_BWM_COUNT            0xFFC0504C         /* DMA10 Bandwidth Monitor Count Current */
+/* =========================
+        DMA11
+   ========================= */
+#define DMA11_NEXT_DESC_PTR            0xFFC05080         /* DMA11 Pointer to Next Initial Descriptor */
+#define DMA11_START_ADDR             0xFFC05084         /* DMA11 Start Address of Current Buffer */
+#define DMA11_CONFIG                   0xFFC05088         /* DMA11 Configuration Register */
+#define DMA11_X_COUNT                  0xFFC0508C         /* DMA11 Inner Loop Count Start Value */
+#define DMA11_X_MODIFY                  0xFFC05090         /* DMA11 Inner Loop Address Increment */
+#define DMA11_Y_COUNT                  0xFFC05094         /* DMA11 Outer Loop Count Start Value (2D only) */
+#define DMA11_Y_MODIFY                  0xFFC05098         /* DMA11 Outer Loop Address Increment (2D only) */
+#define DMA11_CURR_DESC_PTR            0xFFC050A4         /* DMA11 Current Descriptor Pointer */
+#define DMA11_PREV_DESC_PTR            0xFFC050A8         /* DMA11 Previous Initial Descriptor Pointer */
+#define DMA11_CURR_ADDR              0xFFC050AC         /* DMA11 Current Address */
+#define DMA11_IRQ_STATUS                  0xFFC050B0         /* DMA11 Status Register */
+#define DMA11_CURR_X_COUNT              0xFFC050B4         /* DMA11 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA11_CURR_Y_COUNT              0xFFC050B8         /* DMA11 Current Row Count (2D only) */
+#define DMA11_BWL_COUNT                0xFFC050C0         /* DMA11 Bandwidth Limit Count */
+#define DMA11_CURR_BWL_COUNT            0xFFC050C4         /* DMA11 Bandwidth Limit Count Current */
+#define DMA11_BWM_COUNT                0xFFC050C8         /* DMA11 Bandwidth Monitor Count */
+#define DMA11_CURR_BWM_COUNT            0xFFC050CC         /* DMA11 Bandwidth Monitor Count Current */
+/* =========================
+        DMA12
+   ========================= */
+#define DMA12_NEXT_DESC_PTR            0xFFC05100         /* DMA12 Pointer to Next Initial Descriptor */
+#define DMA12_START_ADDR             0xFFC05104         /* DMA12 Start Address of Current Buffer */
+#define DMA12_CONFIG                   0xFFC05108         /* DMA12 Configuration Register */
+#define DMA12_X_COUNT                  0xFFC0510C         /* DMA12 Inner Loop Count Start Value */
+#define DMA12_X_MODIFY                  0xFFC05110         /* DMA12 Inner Loop Address Increment */
+#define DMA12_Y_COUNT                  0xFFC05114         /* DMA12 Outer Loop Count Start Value (2D only) */
+#define DMA12_Y_MODIFY                  0xFFC05118         /* DMA12 Outer Loop Address Increment (2D only) */
+#define DMA12_CURR_DESC_PTR            0xFFC05124         /* DMA12 Current Descriptor Pointer */
+#define DMA12_PREV_DESC_PTR            0xFFC05128         /* DMA12 Previous Initial Descriptor Pointer */
+#define DMA12_CURR_ADDR              0xFFC0512C         /* DMA12 Current Address */
+#define DMA12_IRQ_STATUS                  0xFFC05130         /* DMA12 Status Register */
+#define DMA12_CURR_X_COUNT              0xFFC05134         /* DMA12 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA12_CURR_Y_COUNT              0xFFC05138         /* DMA12 Current Row Count (2D only) */
+#define DMA12_BWL_COUNT                0xFFC05140         /* DMA12 Bandwidth Limit Count */
+#define DMA12_CURR_BWL_COUNT            0xFFC05144         /* DMA12 Bandwidth Limit Count Current */
+#define DMA12_BWM_COUNT                0xFFC05148         /* DMA12 Bandwidth Monitor Count */
+#define DMA12_CURR_BWM_COUNT            0xFFC0514C         /* DMA12 Bandwidth Monitor Count Current */
+/* =========================
+        DMA13
+   ========================= */
+#define DMA13_NEXT_DESC_PTR            0xFFC07000         /* DMA13 Pointer to Next Initial Descriptor */
+#define DMA13_START_ADDR             0xFFC07004         /* DMA13 Start Address of Current Buffer */
+#define DMA13_CONFIG                   0xFFC07008         /* DMA13 Configuration Register */
+#define DMA13_X_COUNT                  0xFFC0700C         /* DMA13 Inner Loop Count Start Value */
+#define DMA13_X_MODIFY                  0xFFC07010         /* DMA13 Inner Loop Address Increment */
+#define DMA13_Y_COUNT                  0xFFC07014         /* DMA13 Outer Loop Count Start Value (2D only) */
+#define DMA13_Y_MODIFY                  0xFFC07018         /* DMA13 Outer Loop Address Increment (2D only) */
+#define DMA13_CURR_DESC_PTR            0xFFC07024         /* DMA13 Current Descriptor Pointer */
+#define DMA13_PREV_DESC_PTR            0xFFC07028         /* DMA13 Previous Initial Descriptor Pointer */
+#define DMA13_CURR_ADDR              0xFFC0702C         /* DMA13 Current Address */
+#define DMA13_IRQ_STATUS                  0xFFC07030         /* DMA13 Status Register */
+#define DMA13_CURR_X_COUNT              0xFFC07034         /* DMA13 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA13_CURR_Y_COUNT              0xFFC07038         /* DMA13 Current Row Count (2D only) */
+#define DMA13_BWL_COUNT                0xFFC07040         /* DMA13 Bandwidth Limit Count */
+#define DMA13_CURR_BWL_COUNT            0xFFC07044         /* DMA13 Bandwidth Limit Count Current */
+#define DMA13_BWM_COUNT                0xFFC07048         /* DMA13 Bandwidth Monitor Count */
+#define DMA13_CURR_BWM_COUNT            0xFFC0704C         /* DMA13 Bandwidth Monitor Count Current */
+/* =========================
+        DMA14
+   ========================= */
+#define DMA14_NEXT_DESC_PTR            0xFFC07080         /* DMA14 Pointer to Next Initial Descriptor */
+#define DMA14_START_ADDR             0xFFC07084         /* DMA14 Start Address of Current Buffer */
+#define DMA14_CONFIG                   0xFFC07088         /* DMA14 Configuration Register */
+#define DMA14_X_COUNT                  0xFFC0708C         /* DMA14 Inner Loop Count Start Value */
+#define DMA14_X_MODIFY                  0xFFC07090         /* DMA14 Inner Loop Address Increment */
+#define DMA14_Y_COUNT                  0xFFC07094         /* DMA14 Outer Loop Count Start Value (2D only) */
+#define DMA14_Y_MODIFY                  0xFFC07098         /* DMA14 Outer Loop Address Increment (2D only) */
+#define DMA14_CURR_DESC_PTR            0xFFC070A4         /* DMA14 Current Descriptor Pointer */
+#define DMA14_PREV_DESC_PTR            0xFFC070A8         /* DMA14 Previous Initial Descriptor Pointer */
+#define DMA14_CURR_ADDR              0xFFC070AC         /* DMA14 Current Address */
+#define DMA14_IRQ_STATUS                  0xFFC070B0         /* DMA14 Status Register */
+#define DMA14_CURR_X_COUNT              0xFFC070B4         /* DMA14 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA14_CURR_Y_COUNT              0xFFC070B8         /* DMA14 Current Row Count (2D only) */
+#define DMA14_BWL_COUNT                0xFFC070C0         /* DMA14 Bandwidth Limit Count */
+#define DMA14_CURR_BWL_COUNT            0xFFC070C4         /* DMA14 Bandwidth Limit Count Current */
+#define DMA14_BWM_COUNT                0xFFC070C8         /* DMA14 Bandwidth Monitor Count */
+#define DMA14_CURR_BWM_COUNT            0xFFC070CC         /* DMA14 Bandwidth Monitor Count Current */
+/* =========================
+        DMA15
+   ========================= */
+#define DMA15_NEXT_DESC_PTR            0xFFC07100         /* DMA15 Pointer to Next Initial Descriptor */
+#define DMA15_START_ADDR             0xFFC07104         /* DMA15 Start Address of Current Buffer */
+#define DMA15_CONFIG                   0xFFC07108         /* DMA15 Configuration Register */
+#define DMA15_X_COUNT                  0xFFC0710C         /* DMA15 Inner Loop Count Start Value */
+#define DMA15_X_MODIFY                  0xFFC07110         /* DMA15 Inner Loop Address Increment */
+#define DMA15_Y_COUNT                  0xFFC07114         /* DMA15 Outer Loop Count Start Value (2D only) */
+#define DMA15_Y_MODIFY                  0xFFC07118         /* DMA15 Outer Loop Address Increment (2D only) */
+#define DMA15_CURR_DESC_PTR            0xFFC07124         /* DMA15 Current Descriptor Pointer */
+#define DMA15_PREV_DESC_PTR            0xFFC07128         /* DMA15 Previous Initial Descriptor Pointer */
+#define DMA15_CURR_ADDR              0xFFC0712C         /* DMA15 Current Address */
+#define DMA15_IRQ_STATUS                  0xFFC07130         /* DMA15 Status Register */
+#define DMA15_CURR_X_COUNT              0xFFC07134         /* DMA15 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA15_CURR_Y_COUNT              0xFFC07138         /* DMA15 Current Row Count (2D only) */
+#define DMA15_BWL_COUNT                0xFFC07140         /* DMA15 Bandwidth Limit Count */
+#define DMA15_CURR_BWL_COUNT            0xFFC07144         /* DMA15 Bandwidth Limit Count Current */
+#define DMA15_BWM_COUNT                0xFFC07148         /* DMA15 Bandwidth Monitor Count */
+#define DMA15_CURR_BWM_COUNT            0xFFC0714C         /* DMA15 Bandwidth Monitor Count Current */
+/* =========================
+        DMA16
+   ========================= */
+#define DMA16_NEXT_DESC_PTR            0xFFC07180         /* DMA16 Pointer to Next Initial Descriptor */
+#define DMA16_START_ADDR             0xFFC07184         /* DMA16 Start Address of Current Buffer */
+#define DMA16_CONFIG                   0xFFC07188         /* DMA16 Configuration Register */
+#define DMA16_X_COUNT                  0xFFC0718C         /* DMA16 Inner Loop Count Start Value */
+#define DMA16_X_MODIFY                  0xFFC07190         /* DMA16 Inner Loop Address Increment */
+#define DMA16_Y_COUNT                  0xFFC07194         /* DMA16 Outer Loop Count Start Value (2D only) */
+#define DMA16_Y_MODIFY                  0xFFC07198         /* DMA16 Outer Loop Address Increment (2D only) */
+#define DMA16_CURR_DESC_PTR            0xFFC071A4         /* DMA16 Current Descriptor Pointer */
+#define DMA16_PREV_DESC_PTR            0xFFC071A8         /* DMA16 Previous Initial Descriptor Pointer */
+#define DMA16_CURR_ADDR              0xFFC071AC         /* DMA16 Current Address */
+#define DMA16_IRQ_STATUS                  0xFFC071B0         /* DMA16 Status Register */
+#define DMA16_CURR_X_COUNT              0xFFC071B4         /* DMA16 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA16_CURR_Y_COUNT              0xFFC071B8         /* DMA16 Current Row Count (2D only) */
+#define DMA16_BWL_COUNT                0xFFC071C0         /* DMA16 Bandwidth Limit Count */
+#define DMA16_CURR_BWL_COUNT            0xFFC071C4         /* DMA16 Bandwidth Limit Count Current */
+#define DMA16_BWM_COUNT                0xFFC071C8         /* DMA16 Bandwidth Monitor Count */
+#define DMA16_CURR_BWM_COUNT            0xFFC071CC         /* DMA16 Bandwidth Monitor Count Current */
+/* =========================
+        DMA17
+   ========================= */
+#define DMA17_NEXT_DESC_PTR            0xFFC07200         /* DMA17 Pointer to Next Initial Descriptor */
+#define DMA17_START_ADDR             0xFFC07204         /* DMA17 Start Address of Current Buffer */
+#define DMA17_CONFIG                   0xFFC07208         /* DMA17 Configuration Register */
+#define DMA17_X_COUNT                  0xFFC0720C         /* DMA17 Inner Loop Count Start Value */
+#define DMA17_X_MODIFY                  0xFFC07210         /* DMA17 Inner Loop Address Increment */
+#define DMA17_Y_COUNT                  0xFFC07214         /* DMA17 Outer Loop Count Start Value (2D only) */
+#define DMA17_Y_MODIFY                  0xFFC07218         /* DMA17 Outer Loop Address Increment (2D only) */
+#define DMA17_CURR_DESC_PTR            0xFFC07224         /* DMA17 Current Descriptor Pointer */
+#define DMA17_PREV_DESC_PTR            0xFFC07228         /* DMA17 Previous Initial Descriptor Pointer */
+#define DMA17_CURR_ADDR              0xFFC0722C         /* DMA17 Current Address */
+#define DMA17_IRQ_STATUS                  0xFFC07230         /* DMA17 Status Register */
+#define DMA17_CURR_X_COUNT              0xFFC07234         /* DMA17 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA17_CURR_Y_COUNT              0xFFC07238         /* DMA17 Current Row Count (2D only) */
+#define DMA17_BWL_COUNT                0xFFC07240         /* DMA17 Bandwidth Limit Count */
+#define DMA17_CURR_BWL_COUNT            0xFFC07244         /* DMA17 Bandwidth Limit Count Current */
+#define DMA17_BWM_COUNT                0xFFC07248         /* DMA17 Bandwidth Monitor Count */
+#define DMA17_CURR_BWM_COUNT            0xFFC0724C         /* DMA17 Bandwidth Monitor Count Current */
+/* =========================
+        DMA18
+   ========================= */
+#define DMA18_NEXT_DESC_PTR            0xFFC07280         /* DMA18 Pointer to Next Initial Descriptor */
+#define DMA18_START_ADDR             0xFFC07284         /* DMA18 Start Address of Current Buffer */
+#define DMA18_CONFIG                   0xFFC07288         /* DMA18 Configuration Register */
+#define DMA18_X_COUNT                  0xFFC0728C         /* DMA18 Inner Loop Count Start Value */
+#define DMA18_X_MODIFY                  0xFFC07290         /* DMA18 Inner Loop Address Increment */
+#define DMA18_Y_COUNT                  0xFFC07294         /* DMA18 Outer Loop Count Start Value (2D only) */
+#define DMA18_Y_MODIFY                  0xFFC07298         /* DMA18 Outer Loop Address Increment (2D only) */
+#define DMA18_CURR_DESC_PTR            0xFFC072A4         /* DMA18 Current Descriptor Pointer */
+#define DMA18_PREV_DESC_PTR            0xFFC072A8         /* DMA18 Previous Initial Descriptor Pointer */
+#define DMA18_CURR_ADDR              0xFFC072AC         /* DMA18 Current Address */
+#define DMA18_IRQ_STATUS                  0xFFC072B0         /* DMA18 Status Register */
+#define DMA18_CURR_X_COUNT              0xFFC072B4         /* DMA18 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA18_CURR_Y_COUNT              0xFFC072B8         /* DMA18 Current Row Count (2D only) */
+#define DMA18_BWL_COUNT                0xFFC072C0         /* DMA18 Bandwidth Limit Count */
+#define DMA18_CURR_BWL_COUNT            0xFFC072C4         /* DMA18 Bandwidth Limit Count Current */
+#define DMA18_BWM_COUNT                0xFFC072C8         /* DMA18 Bandwidth Monitor Count */
+#define DMA18_CURR_BWM_COUNT            0xFFC072CC         /* DMA18 Bandwidth Monitor Count Current */
+/* =========================
+        DMA19
+   ========================= */
+#define DMA19_NEXT_DESC_PTR            0xFFC07300         /* DMA19 Pointer to Next Initial Descriptor */
+#define DMA19_START_ADDR             0xFFC07304         /* DMA19 Start Address of Current Buffer */
+#define DMA19_CONFIG                   0xFFC07308         /* DMA19 Configuration Register */
+#define DMA19_X_COUNT                  0xFFC0730C         /* DMA19 Inner Loop Count Start Value */
+#define DMA19_X_MODIFY                  0xFFC07310         /* DMA19 Inner Loop Address Increment */
+#define DMA19_Y_COUNT                  0xFFC07314         /* DMA19 Outer Loop Count Start Value (2D only) */
+#define DMA19_Y_MODIFY                  0xFFC07318         /* DMA19 Outer Loop Address Increment (2D only) */
+#define DMA19_CURR_DESC_PTR            0xFFC07324         /* DMA19 Current Descriptor Pointer */
+#define DMA19_PREV_DESC_PTR            0xFFC07328         /* DMA19 Previous Initial Descriptor Pointer */
+#define DMA19_CURR_ADDR              0xFFC0732C         /* DMA19 Current Address */
+#define DMA19_IRQ_STATUS                  0xFFC07330         /* DMA19 Status Register */
+#define DMA19_CURR_X_COUNT              0xFFC07334         /* DMA19 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA19_CURR_Y_COUNT              0xFFC07338         /* DMA19 Current Row Count (2D only) */
+#define DMA19_BWL_COUNT                0xFFC07340         /* DMA19 Bandwidth Limit Count */
+#define DMA19_CURR_BWL_COUNT            0xFFC07344         /* DMA19 Bandwidth Limit Count Current */
+#define DMA19_BWM_COUNT                0xFFC07348         /* DMA19 Bandwidth Monitor Count */
+#define DMA19_CURR_BWM_COUNT            0xFFC0734C         /* DMA19 Bandwidth Monitor Count Current */
+/* =========================
+        DMA20
+   ========================= */
+#define DMA20_NEXT_DESC_PTR            0xFFC07380         /* DMA20 Pointer to Next Initial Descriptor */
+#define DMA20_START_ADDR             0xFFC07384         /* DMA20 Start Address of Current Buffer */
+#define DMA20_CONFIG                   0xFFC07388         /* DMA20 Configuration Register */
+#define DMA20_X_COUNT                  0xFFC0738C         /* DMA20 Inner Loop Count Start Value */
+#define DMA20_X_MODIFY                  0xFFC07390         /* DMA20 Inner Loop Address Increment */
+#define DMA20_Y_COUNT                  0xFFC07394         /* DMA20 Outer Loop Count Start Value (2D only) */
+#define DMA20_Y_MODIFY                  0xFFC07398         /* DMA20 Outer Loop Address Increment (2D only) */
+#define DMA20_CURR_DESC_PTR            0xFFC073A4         /* DMA20 Current Descriptor Pointer */
+#define DMA20_PREV_DESC_PTR            0xFFC073A8         /* DMA20 Previous Initial Descriptor Pointer */
+#define DMA20_CURR_ADDR              0xFFC073AC         /* DMA20 Current Address */
+#define DMA20_IRQ_STATUS                  0xFFC073B0         /* DMA20 Status Register */
+#define DMA20_CURR_X_COUNT              0xFFC073B4         /* DMA20 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA20_CURR_Y_COUNT              0xFFC073B8         /* DMA20 Current Row Count (2D only) */
+#define DMA20_BWL_COUNT                0xFFC073C0         /* DMA20 Bandwidth Limit Count */
+#define DMA20_CURR_BWL_COUNT            0xFFC073C4         /* DMA20 Bandwidth Limit Count Current */
+#define DMA20_BWM_COUNT                0xFFC073C8         /* DMA20 Bandwidth Monitor Count */
+#define DMA20_CURR_BWM_COUNT            0xFFC073CC         /* DMA20 Bandwidth Monitor Count Current */
+/* =========================
+        DMA21
+   ========================= */
+#define DMA21_NEXT_DESC_PTR            0xFFC09000         /* DMA21 Pointer to Next Initial Descriptor */
+#define DMA21_START_ADDR             0xFFC09004         /* DMA21 Start Address of Current Buffer */
+#define DMA21_CONFIG                   0xFFC09008         /* DMA21 Configuration Register */
+#define DMA21_X_COUNT                  0xFFC0900C         /* DMA21 Inner Loop Count Start Value */
+#define DMA21_X_MODIFY                  0xFFC09010         /* DMA21 Inner Loop Address Increment */
+#define DMA21_Y_COUNT                  0xFFC09014         /* DMA21 Outer Loop Count Start Value (2D only) */
+#define DMA21_Y_MODIFY                  0xFFC09018         /* DMA21 Outer Loop Address Increment (2D only) */
+#define DMA21_CURR_DESC_PTR            0xFFC09024         /* DMA21 Current Descriptor Pointer */
+#define DMA21_PREV_DESC_PTR            0xFFC09028         /* DMA21 Previous Initial Descriptor Pointer */
+#define DMA21_CURR_ADDR              0xFFC0902C         /* DMA21 Current Address */
+#define DMA21_IRQ_STATUS                  0xFFC09030         /* DMA21 Status Register */
+#define DMA21_CURR_X_COUNT              0xFFC09034         /* DMA21 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA21_CURR_Y_COUNT              0xFFC09038         /* DMA21 Current Row Count (2D only) */
+#define DMA21_BWL_COUNT                0xFFC09040         /* DMA21 Bandwidth Limit Count */
+#define DMA21_CURR_BWL_COUNT            0xFFC09044         /* DMA21 Bandwidth Limit Count Current */
+#define DMA21_BWM_COUNT                0xFFC09048         /* DMA21 Bandwidth Monitor Count */
+#define DMA21_CURR_BWM_COUNT            0xFFC0904C         /* DMA21 Bandwidth Monitor Count Current */
+/* =========================
+        DMA22
+   ========================= */
+#define DMA22_NEXT_DESC_PTR            0xFFC09080         /* DMA22 Pointer to Next Initial Descriptor */
+#define DMA22_START_ADDR             0xFFC09084         /* DMA22 Start Address of Current Buffer */
+#define DMA22_CONFIG                   0xFFC09088         /* DMA22 Configuration Register */
+#define DMA22_X_COUNT                  0xFFC0908C         /* DMA22 Inner Loop Count Start Value */
+#define DMA22_X_MODIFY                  0xFFC09090         /* DMA22 Inner Loop Address Increment */
+#define DMA22_Y_COUNT                  0xFFC09094         /* DMA22 Outer Loop Count Start Value (2D only) */
+#define DMA22_Y_MODIFY                  0xFFC09098         /* DMA22 Outer Loop Address Increment (2D only) */
+#define DMA22_CURR_DESC_PTR            0xFFC090A4         /* DMA22 Current Descriptor Pointer */
+#define DMA22_PREV_DESC_PTR            0xFFC090A8         /* DMA22 Previous Initial Descriptor Pointer */
+#define DMA22_CURR_ADDR              0xFFC090AC         /* DMA22 Current Address */
+#define DMA22_IRQ_STATUS                  0xFFC090B0         /* DMA22 Status Register */
+#define DMA22_CURR_X_COUNT              0xFFC090B4         /* DMA22 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA22_CURR_Y_COUNT              0xFFC090B8         /* DMA22 Current Row Count (2D only) */
+#define DMA22_BWL_COUNT                0xFFC090C0         /* DMA22 Bandwidth Limit Count */
+#define DMA22_CURR_BWL_COUNT            0xFFC090C4         /* DMA22 Bandwidth Limit Count Current */
+#define DMA22_BWM_COUNT                0xFFC090C8         /* DMA22 Bandwidth Monitor Count */
+#define DMA22_CURR_BWM_COUNT            0xFFC090CC         /* DMA22 Bandwidth Monitor Count Current */
+/* =========================
+        DMA23
+   ========================= */
+#define DMA23_NEXT_DESC_PTR            0xFFC09100         /* DMA23 Pointer to Next Initial Descriptor */
+#define DMA23_START_ADDR             0xFFC09104         /* DMA23 Start Address of Current Buffer */
+#define DMA23_CONFIG                   0xFFC09108         /* DMA23 Configuration Register */
+#define DMA23_X_COUNT                  0xFFC0910C         /* DMA23 Inner Loop Count Start Value */
+#define DMA23_X_MODIFY                  0xFFC09110         /* DMA23 Inner Loop Address Increment */
+#define DMA23_Y_COUNT                  0xFFC09114         /* DMA23 Outer Loop Count Start Value (2D only) */
+#define DMA23_Y_MODIFY                  0xFFC09118         /* DMA23 Outer Loop Address Increment (2D only) */
+#define DMA23_CURR_DESC_PTR            0xFFC09124         /* DMA23 Current Descriptor Pointer */
+#define DMA23_PREV_DESC_PTR            0xFFC09128         /* DMA23 Previous Initial Descriptor Pointer */
+#define DMA23_CURR_ADDR              0xFFC0912C         /* DMA23 Current Address */
+#define DMA23_IRQ_STATUS                  0xFFC09130         /* DMA23 Status Register */
+#define DMA23_CURR_X_COUNT              0xFFC09134         /* DMA23 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA23_CURR_Y_COUNT              0xFFC09138         /* DMA23 Current Row Count (2D only) */
+#define DMA23_BWL_COUNT                0xFFC09140         /* DMA23 Bandwidth Limit Count */
+#define DMA23_CURR_BWL_COUNT            0xFFC09144         /* DMA23 Bandwidth Limit Count Current */
+#define DMA23_BWM_COUNT                0xFFC09148         /* DMA23 Bandwidth Monitor Count */
+#define DMA23_CURR_BWM_COUNT            0xFFC0914C         /* DMA23 Bandwidth Monitor Count Current */
+/* =========================
+        DMA24
+   ========================= */
+#define DMA24_NEXT_DESC_PTR            0xFFC09180         /* DMA24 Pointer to Next Initial Descriptor */
+#define DMA24_START_ADDR             0xFFC09184         /* DMA24 Start Address of Current Buffer */
+#define DMA24_CONFIG                   0xFFC09188         /* DMA24 Configuration Register */
+#define DMA24_X_COUNT                  0xFFC0918C         /* DMA24 Inner Loop Count Start Value */
+#define DMA24_X_MODIFY                  0xFFC09190         /* DMA24 Inner Loop Address Increment */
+#define DMA24_Y_COUNT                  0xFFC09194         /* DMA24 Outer Loop Count Start Value (2D only) */
+#define DMA24_Y_MODIFY                  0xFFC09198         /* DMA24 Outer Loop Address Increment (2D only) */
+#define DMA24_CURR_DESC_PTR            0xFFC091A4         /* DMA24 Current Descriptor Pointer */
+#define DMA24_PREV_DESC_PTR            0xFFC091A8         /* DMA24 Previous Initial Descriptor Pointer */
+#define DMA24_CURR_ADDR              0xFFC091AC         /* DMA24 Current Address */
+#define DMA24_IRQ_STATUS                  0xFFC091B0         /* DMA24 Status Register */
+#define DMA24_CURR_X_COUNT              0xFFC091B4         /* DMA24 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA24_CURR_Y_COUNT              0xFFC091B8         /* DMA24 Current Row Count (2D only) */
+#define DMA24_BWL_COUNT                0xFFC091C0         /* DMA24 Bandwidth Limit Count */
+#define DMA24_CURR_BWL_COUNT            0xFFC091C4         /* DMA24 Bandwidth Limit Count Current */
+#define DMA24_BWM_COUNT                0xFFC091C8         /* DMA24 Bandwidth Monitor Count */
+#define DMA24_CURR_BWM_COUNT            0xFFC091CC         /* DMA24 Bandwidth Monitor Count Current */
+/* =========================
+        DMA25
+   ========================= */
+#define DMA25_NEXT_DESC_PTR            0xFFC09200         /* DMA25 Pointer to Next Initial Descriptor */
+#define DMA25_START_ADDR             0xFFC09204         /* DMA25 Start Address of Current Buffer */
+#define DMA25_CONFIG                   0xFFC09208         /* DMA25 Configuration Register */
+#define DMA25_X_COUNT                  0xFFC0920C         /* DMA25 Inner Loop Count Start Value */
+#define DMA25_X_MODIFY                  0xFFC09210         /* DMA25 Inner Loop Address Increment */
+#define DMA25_Y_COUNT                  0xFFC09214         /* DMA25 Outer Loop Count Start Value (2D only) */
+#define DMA25_Y_MODIFY                  0xFFC09218         /* DMA25 Outer Loop Address Increment (2D only) */
+#define DMA25_CURR_DESC_PTR            0xFFC09224         /* DMA25 Current Descriptor Pointer */
+#define DMA25_PREV_DESC_PTR            0xFFC09228         /* DMA25 Previous Initial Descriptor Pointer */
+#define DMA25_CURR_ADDR              0xFFC0922C         /* DMA25 Current Address */
+#define DMA25_IRQ_STATUS                  0xFFC09230         /* DMA25 Status Register */
+#define DMA25_CURR_X_COUNT              0xFFC09234         /* DMA25 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA25_CURR_Y_COUNT              0xFFC09238         /* DMA25 Current Row Count (2D only) */
+#define DMA25_BWL_COUNT                0xFFC09240         /* DMA25 Bandwidth Limit Count */
+#define DMA25_CURR_BWL_COUNT            0xFFC09244         /* DMA25 Bandwidth Limit Count Current */
+#define DMA25_BWM_COUNT                0xFFC09248         /* DMA25 Bandwidth Monitor Count */
+#define DMA25_CURR_BWM_COUNT            0xFFC0924C         /* DMA25 Bandwidth Monitor Count Current */
+/* =========================
+        DMA26
+   ========================= */
+#define DMA26_NEXT_DESC_PTR            0xFFC09280         /* DMA26 Pointer to Next Initial Descriptor */
+#define DMA26_START_ADDR             0xFFC09284         /* DMA26 Start Address of Current Buffer */
+#define DMA26_CONFIG                   0xFFC09288         /* DMA26 Configuration Register */
+#define DMA26_X_COUNT                  0xFFC0928C         /* DMA26 Inner Loop Count Start Value */
+#define DMA26_X_MODIFY                  0xFFC09290         /* DMA26 Inner Loop Address Increment */
+#define DMA26_Y_COUNT                  0xFFC09294         /* DMA26 Outer Loop Count Start Value (2D only) */
+#define DMA26_Y_MODIFY                  0xFFC09298         /* DMA26 Outer Loop Address Increment (2D only) */
+#define DMA26_CURR_DESC_PTR            0xFFC092A4         /* DMA26 Current Descriptor Pointer */
+#define DMA26_PREV_DESC_PTR            0xFFC092A8         /* DMA26 Previous Initial Descriptor Pointer */
+#define DMA26_CURR_ADDR              0xFFC092AC         /* DMA26 Current Address */
+#define DMA26_IRQ_STATUS                  0xFFC092B0         /* DMA26 Status Register */
+#define DMA26_CURR_X_COUNT              0xFFC092B4         /* DMA26 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA26_CURR_Y_COUNT              0xFFC092B8         /* DMA26 Current Row Count (2D only) */
+#define DMA26_BWL_COUNT                0xFFC092C0         /* DMA26 Bandwidth Limit Count */
+#define DMA26_CURR_BWL_COUNT            0xFFC092C4         /* DMA26 Bandwidth Limit Count Current */
+#define DMA26_BWM_COUNT                0xFFC092C8         /* DMA26 Bandwidth Monitor Count */
+#define DMA26_CURR_BWM_COUNT            0xFFC092CC         /* DMA26 Bandwidth Monitor Count Current */
+/* =========================
+        DMA27
+   ========================= */
+#define DMA27_NEXT_DESC_PTR            0xFFC09300         /* DMA27 Pointer to Next Initial Descriptor */
+#define DMA27_START_ADDR             0xFFC09304         /* DMA27 Start Address of Current Buffer */
+#define DMA27_CONFIG                   0xFFC09308         /* DMA27 Configuration Register */
+#define DMA27_X_COUNT                  0xFFC0930C         /* DMA27 Inner Loop Count Start Value */
+#define DMA27_X_MODIFY                  0xFFC09310         /* DMA27 Inner Loop Address Increment */
+#define DMA27_Y_COUNT                  0xFFC09314         /* DMA27 Outer Loop Count Start Value (2D only) */
+#define DMA27_Y_MODIFY                  0xFFC09318         /* DMA27 Outer Loop Address Increment (2D only) */
+#define DMA27_CURR_DESC_PTR            0xFFC09324         /* DMA27 Current Descriptor Pointer */
+#define DMA27_PREV_DESC_PTR            0xFFC09328         /* DMA27 Previous Initial Descriptor Pointer */
+#define DMA27_CURR_ADDR              0xFFC0932C         /* DMA27 Current Address */
+#define DMA27_IRQ_STATUS                  0xFFC09330         /* DMA27 Status Register */
+#define DMA27_CURR_X_COUNT              0xFFC09334         /* DMA27 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA27_CURR_Y_COUNT              0xFFC09338         /* DMA27 Current Row Count (2D only) */
+#define DMA27_BWL_COUNT                0xFFC09340         /* DMA27 Bandwidth Limit Count */
+#define DMA27_CURR_BWL_COUNT            0xFFC09344         /* DMA27 Bandwidth Limit Count Current */
+#define DMA27_BWM_COUNT                0xFFC09348         /* DMA27 Bandwidth Monitor Count */
+#define DMA27_CURR_BWM_COUNT            0xFFC0934C         /* DMA27 Bandwidth Monitor Count Current */
+/* =========================
+        DMA28
+   ========================= */
+#define DMA28_NEXT_DESC_PTR            0xFFC09380         /* DMA28 Pointer to Next Initial Descriptor */
+#define DMA28_START_ADDR             0xFFC09384         /* DMA28 Start Address of Current Buffer */
+#define DMA28_CONFIG                   0xFFC09388         /* DMA28 Configuration Register */
+#define DMA28_X_COUNT                  0xFFC0938C         /* DMA28 Inner Loop Count Start Value */
+#define DMA28_X_MODIFY                  0xFFC09390         /* DMA28 Inner Loop Address Increment */
+#define DMA28_Y_COUNT                  0xFFC09394         /* DMA28 Outer Loop Count Start Value (2D only) */
+#define DMA28_Y_MODIFY                  0xFFC09398         /* DMA28 Outer Loop Address Increment (2D only) */
+#define DMA28_CURR_DESC_PTR            0xFFC093A4         /* DMA28 Current Descriptor Pointer */
+#define DMA28_PREV_DESC_PTR            0xFFC093A8         /* DMA28 Previous Initial Descriptor Pointer */
+#define DMA28_CURR_ADDR              0xFFC093AC         /* DMA28 Current Address */
+#define DMA28_IRQ_STATUS                  0xFFC093B0         /* DMA28 Status Register */
+#define DMA28_CURR_X_COUNT              0xFFC093B4         /* DMA28 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA28_CURR_Y_COUNT              0xFFC093B8         /* DMA28 Current Row Count (2D only) */
+#define DMA28_BWL_COUNT                0xFFC093C0         /* DMA28 Bandwidth Limit Count */
+#define DMA28_CURR_BWL_COUNT            0xFFC093C4         /* DMA28 Bandwidth Limit Count Current */
+#define DMA28_BWM_COUNT                0xFFC093C8         /* DMA28 Bandwidth Monitor Count */
+#define DMA28_CURR_BWM_COUNT            0xFFC093CC         /* DMA28 Bandwidth Monitor Count Current */
+/* =========================
+        DMA29
+   ========================= */
+#define DMA29_NEXT_DESC_PTR            0xFFC0B000         /* DMA29 Pointer to Next Initial Descriptor */
+#define DMA29_START_ADDR             0xFFC0B004         /* DMA29 Start Address of Current Buffer */
+#define DMA29_CONFIG                   0xFFC0B008         /* DMA29 Configuration Register */
+#define DMA29_X_COUNT                  0xFFC0B00C         /* DMA29 Inner Loop Count Start Value */
+#define DMA29_X_MODIFY                  0xFFC0B010         /* DMA29 Inner Loop Address Increment */
+#define DMA29_Y_COUNT                  0xFFC0B014         /* DMA29 Outer Loop Count Start Value (2D only) */
+#define DMA29_Y_MODIFY                  0xFFC0B018         /* DMA29 Outer Loop Address Increment (2D only) */
+#define DMA29_CURR_DESC_PTR            0xFFC0B024         /* DMA29 Current Descriptor Pointer */
+#define DMA29_PREV_DESC_PTR            0xFFC0B028         /* DMA29 Previous Initial Descriptor Pointer */
+#define DMA29_CURR_ADDR              0xFFC0B02C         /* DMA29 Current Address */
+#define DMA29_IRQ_STATUS                  0xFFC0B030         /* DMA29 Status Register */
+#define DMA29_CURR_X_COUNT              0xFFC0B034         /* DMA29 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA29_CURR_Y_COUNT              0xFFC0B038         /* DMA29 Current Row Count (2D only) */
+#define DMA29_BWL_COUNT                0xFFC0B040         /* DMA29 Bandwidth Limit Count */
+#define DMA29_CURR_BWL_COUNT            0xFFC0B044         /* DMA29 Bandwidth Limit Count Current */
+#define DMA29_BWM_COUNT                0xFFC0B048         /* DMA29 Bandwidth Monitor Count */
+#define DMA29_CURR_BWM_COUNT            0xFFC0B04C         /* DMA29 Bandwidth Monitor Count Current */
+/* =========================
+        DMA30
+   ========================= */
+#define DMA30_NEXT_DESC_PTR            0xFFC0B080         /* DMA30 Pointer to Next Initial Descriptor */
+#define DMA30_START_ADDR             0xFFC0B084         /* DMA30 Start Address of Current Buffer */
+#define DMA30_CONFIG                   0xFFC0B088         /* DMA30 Configuration Register */
+#define DMA30_X_COUNT                  0xFFC0B08C         /* DMA30 Inner Loop Count Start Value */
+#define DMA30_X_MODIFY                  0xFFC0B090         /* DMA30 Inner Loop Address Increment */
+#define DMA30_Y_COUNT                  0xFFC0B094         /* DMA30 Outer Loop Count Start Value (2D only) */
+#define DMA30_Y_MODIFY                  0xFFC0B098         /* DMA30 Outer Loop Address Increment (2D only) */
+#define DMA30_CURR_DESC_PTR            0xFFC0B0A4         /* DMA30 Current Descriptor Pointer */
+#define DMA30_PREV_DESC_PTR            0xFFC0B0A8         /* DMA30 Previous Initial Descriptor Pointer */
+#define DMA30_CURR_ADDR              0xFFC0B0AC         /* DMA30 Current Address */
+#define DMA30_IRQ_STATUS                  0xFFC0B0B0         /* DMA30 Status Register */
+#define DMA30_CURR_X_COUNT              0xFFC0B0B4         /* DMA30 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA30_CURR_Y_COUNT              0xFFC0B0B8         /* DMA30 Current Row Count (2D only) */
+#define DMA30_BWL_COUNT                0xFFC0B0C0         /* DMA30 Bandwidth Limit Count */
+#define DMA30_CURR_BWL_COUNT            0xFFC0B0C4         /* DMA30 Bandwidth Limit Count Current */
+#define DMA30_BWM_COUNT                0xFFC0B0C8         /* DMA30 Bandwidth Monitor Count */
+#define DMA30_CURR_BWM_COUNT            0xFFC0B0CC         /* DMA30 Bandwidth Monitor Count Current */
+/* =========================
+        DMA31
+   ========================= */
+#define DMA31_NEXT_DESC_PTR            0xFFC0B100         /* DMA31 Pointer to Next Initial Descriptor */
+#define DMA31_START_ADDR             0xFFC0B104         /* DMA31 Start Address of Current Buffer */
+#define DMA31_CONFIG                   0xFFC0B108         /* DMA31 Configuration Register */
+#define DMA31_X_COUNT                  0xFFC0B10C         /* DMA31 Inner Loop Count Start Value */
+#define DMA31_X_MODIFY                  0xFFC0B110         /* DMA31 Inner Loop Address Increment */
+#define DMA31_Y_COUNT                  0xFFC0B114         /* DMA31 Outer Loop Count Start Value (2D only) */
+#define DMA31_Y_MODIFY                  0xFFC0B118         /* DMA31 Outer Loop Address Increment (2D only) */
+#define DMA31_CURR_DESC_PTR            0xFFC0B124         /* DMA31 Current Descriptor Pointer */
+#define DMA31_PREV_DESC_PTR            0xFFC0B128         /* DMA31 Previous Initial Descriptor Pointer */
+#define DMA31_CURR_ADDR              0xFFC0B12C         /* DMA31 Current Address */
+#define DMA31_IRQ_STATUS                  0xFFC0B130         /* DMA31 Status Register */
+#define DMA31_CURR_X_COUNT              0xFFC0B134         /* DMA31 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA31_CURR_Y_COUNT              0xFFC0B138         /* DMA31 Current Row Count (2D only) */
+#define DMA31_BWL_COUNT                0xFFC0B140         /* DMA31 Bandwidth Limit Count */
+#define DMA31_CURR_BWL_COUNT            0xFFC0B144         /* DMA31 Bandwidth Limit Count Current */
+#define DMA31_BWM_COUNT                0xFFC0B148         /* DMA31 Bandwidth Monitor Count */
+#define DMA31_CURR_BWM_COUNT            0xFFC0B14C         /* DMA31 Bandwidth Monitor Count Current */
+/* =========================
+        DMA32
+   ========================= */
+#define DMA32_NEXT_DESC_PTR            0xFFC0B180         /* DMA32 Pointer to Next Initial Descriptor */
+#define DMA32_START_ADDR             0xFFC0B184         /* DMA32 Start Address of Current Buffer */
+#define DMA32_CONFIG                   0xFFC0B188         /* DMA32 Configuration Register */
+#define DMA32_X_COUNT                  0xFFC0B18C         /* DMA32 Inner Loop Count Start Value */
+#define DMA32_X_MODIFY                  0xFFC0B190         /* DMA32 Inner Loop Address Increment */
+#define DMA32_Y_COUNT                  0xFFC0B194         /* DMA32 Outer Loop Count Start Value (2D only) */
+#define DMA32_Y_MODIFY                  0xFFC0B198         /* DMA32 Outer Loop Address Increment (2D only) */
+#define DMA32_CURR_DESC_PTR            0xFFC0B1A4         /* DMA32 Current Descriptor Pointer */
+#define DMA32_PREV_DESC_PTR            0xFFC0B1A8         /* DMA32 Previous Initial Descriptor Pointer */
+#define DMA32_CURR_ADDR              0xFFC0B1AC         /* DMA32 Current Address */
+#define DMA32_IRQ_STATUS                  0xFFC0B1B0         /* DMA32 Status Register */
+#define DMA32_CURR_X_COUNT              0xFFC0B1B4         /* DMA32 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA32_CURR_Y_COUNT              0xFFC0B1B8         /* DMA32 Current Row Count (2D only) */
+#define DMA32_BWL_COUNT                0xFFC0B1C0         /* DMA32 Bandwidth Limit Count */
+#define DMA32_CURR_BWL_COUNT            0xFFC0B1C4         /* DMA32 Bandwidth Limit Count Current */
+#define DMA32_BWM_COUNT                0xFFC0B1C8         /* DMA32 Bandwidth Monitor Count */
+#define DMA32_CURR_BWM_COUNT            0xFFC0B1CC         /* DMA32 Bandwidth Monitor Count Current */
+/* =========================
+        DMA33
+   ========================= */
+#define DMA33_NEXT_DESC_PTR            0xFFC0D000         /* DMA33 Pointer to Next Initial Descriptor */
+#define DMA33_START_ADDR             0xFFC0D004         /* DMA33 Start Address of Current Buffer */
+#define DMA33_CONFIG                   0xFFC0D008         /* DMA33 Configuration Register */
+#define DMA33_X_COUNT                  0xFFC0D00C         /* DMA33 Inner Loop Count Start Value */
+#define DMA33_X_MODIFY                  0xFFC0D010         /* DMA33 Inner Loop Address Increment */
+#define DMA33_Y_COUNT                  0xFFC0D014         /* DMA33 Outer Loop Count Start Value (2D only) */
+#define DMA33_Y_MODIFY                  0xFFC0D018         /* DMA33 Outer Loop Address Increment (2D only) */
+#define DMA33_CURR_DESC_PTR            0xFFC0D024         /* DMA33 Current Descriptor Pointer */
+#define DMA33_PREV_DESC_PTR            0xFFC0D028         /* DMA33 Previous Initial Descriptor Pointer */
+#define DMA33_CURR_ADDR              0xFFC0D02C         /* DMA33 Current Address */
+#define DMA33_IRQ_STATUS                  0xFFC0D030         /* DMA33 Status Register */
+#define DMA33_CURR_X_COUNT              0xFFC0D034         /* DMA33 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA33_CURR_Y_COUNT              0xFFC0D038         /* DMA33 Current Row Count (2D only) */
+#define DMA33_BWL_COUNT                0xFFC0D040         /* DMA33 Bandwidth Limit Count */
+#define DMA33_CURR_BWL_COUNT            0xFFC0D044         /* DMA33 Bandwidth Limit Count Current */
+#define DMA33_BWM_COUNT                0xFFC0D048         /* DMA33 Bandwidth Monitor Count */
+#define DMA33_CURR_BWM_COUNT            0xFFC0D04C         /* DMA33 Bandwidth Monitor Count Current */
+/* =========================
+        DMA34
+   ========================= */
+#define DMA34_NEXT_DESC_PTR            0xFFC0D080         /* DMA34 Pointer to Next Initial Descriptor */
+#define DMA34_START_ADDR             0xFFC0D084         /* DMA34 Start Address of Current Buffer */
+#define DMA34_CONFIG                   0xFFC0D088         /* DMA34 Configuration Register */
+#define DMA34_X_COUNT                  0xFFC0D08C         /* DMA34 Inner Loop Count Start Value */
+#define DMA34_X_MODIFY                  0xFFC0D090         /* DMA34 Inner Loop Address Increment */
+#define DMA34_Y_COUNT                  0xFFC0D094         /* DMA34 Outer Loop Count Start Value (2D only) */
+#define DMA34_Y_MODIFY                  0xFFC0D098         /* DMA34 Outer Loop Address Increment (2D only) */
+#define DMA34_CURR_DESC_PTR            0xFFC0D0A4         /* DMA34 Current Descriptor Pointer */
+#define DMA34_PREV_DESC_PTR            0xFFC0D0A8         /* DMA34 Previous Initial Descriptor Pointer */
+#define DMA34_CURR_ADDR              0xFFC0D0AC         /* DMA34 Current Address */
+#define DMA34_IRQ_STATUS                  0xFFC0D0B0         /* DMA34 Status Register */
+#define DMA34_CURR_X_COUNT              0xFFC0D0B4         /* DMA34 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA34_CURR_Y_COUNT              0xFFC0D0B8         /* DMA34 Current Row Count (2D only) */
+#define DMA34_BWL_COUNT                0xFFC0D0C0         /* DMA34 Bandwidth Limit Count */
+#define DMA34_CURR_BWL_COUNT            0xFFC0D0C4         /* DMA34 Bandwidth Limit Count Current */
+#define DMA34_BWM_COUNT                0xFFC0D0C8         /* DMA34 Bandwidth Monitor Count */
+#define DMA34_CURR_BWM_COUNT            0xFFC0D0CC         /* DMA34 Bandwidth Monitor Count Current */
+/* =========================
+        DMA35
+   ========================= */
+#define DMA35_NEXT_DESC_PTR            0xFFC10000         /* DMA35 Pointer to Next Initial Descriptor */
+#define DMA35_START_ADDR             0xFFC10004         /* DMA35 Start Address of Current Buffer */
+#define DMA35_CONFIG                   0xFFC10008         /* DMA35 Configuration Register */
+#define DMA35_X_COUNT                  0xFFC1000C         /* DMA35 Inner Loop Count Start Value */
+#define DMA35_X_MODIFY                  0xFFC10010         /* DMA35 Inner Loop Address Increment */
+#define DMA35_Y_COUNT                  0xFFC10014         /* DMA35 Outer Loop Count Start Value (2D only) */
+#define DMA35_Y_MODIFY                  0xFFC10018         /* DMA35 Outer Loop Address Increment (2D only) */
+#define DMA35_CURR_DESC_PTR            0xFFC10024         /* DMA35 Current Descriptor Pointer */
+#define DMA35_PREV_DESC_PTR            0xFFC10028         /* DMA35 Previous Initial Descriptor Pointer */
+#define DMA35_CURR_ADDR              0xFFC1002C         /* DMA35 Current Address */
+#define DMA35_IRQ_STATUS                  0xFFC10030         /* DMA35 Status Register */
+#define DMA35_CURR_X_COUNT              0xFFC10034         /* DMA35 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA35_CURR_Y_COUNT              0xFFC10038         /* DMA35 Current Row Count (2D only) */
+#define DMA35_BWL_COUNT                0xFFC10040         /* DMA35 Bandwidth Limit Count */
+#define DMA35_CURR_BWL_COUNT            0xFFC10044         /* DMA35 Bandwidth Limit Count Current */
+#define DMA35_BWM_COUNT                0xFFC10048         /* DMA35 Bandwidth Monitor Count */
+#define DMA35_CURR_BWM_COUNT            0xFFC1004C         /* DMA35 Bandwidth Monitor Count Current */
+/* =========================
+        DMA36
+   ========================= */
+#define DMA36_NEXT_DESC_PTR            0xFFC10080         /* DMA36 Pointer to Next Initial Descriptor */
+#define DMA36_START_ADDR             0xFFC10084         /* DMA36 Start Address of Current Buffer */
+#define DMA36_CONFIG                   0xFFC10088         /* DMA36 Configuration Register */
+#define DMA36_X_COUNT                  0xFFC1008C         /* DMA36 Inner Loop Count Start Value */
+#define DMA36_X_MODIFY                  0xFFC10090         /* DMA36 Inner Loop Address Increment */
+#define DMA36_Y_COUNT                  0xFFC10094         /* DMA36 Outer Loop Count Start Value (2D only) */
+#define DMA36_Y_MODIFY                  0xFFC10098         /* DMA36 Outer Loop Address Increment (2D only) */
+#define DMA36_CURR_DESC_PTR            0xFFC100A4         /* DMA36 Current Descriptor Pointer */
+#define DMA36_PREV_DESC_PTR            0xFFC100A8         /* DMA36 Previous Initial Descriptor Pointer */
+#define DMA36_CURR_ADDR              0xFFC100AC         /* DMA36 Current Address */
+#define DMA36_IRQ_STATUS                  0xFFC100B0         /* DMA36 Status Register */
+#define DMA36_CURR_X_COUNT              0xFFC100B4         /* DMA36 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA36_CURR_Y_COUNT              0xFFC100B8         /* DMA36 Current Row Count (2D only) */
+#define DMA36_BWL_COUNT                0xFFC100C0         /* DMA36 Bandwidth Limit Count */
+#define DMA36_CURR_BWL_COUNT            0xFFC100C4         /* DMA36 Bandwidth Limit Count Current */
+#define DMA36_BWM_COUNT                0xFFC100C8         /* DMA36 Bandwidth Monitor Count */
+#define DMA36_CURR_BWM_COUNT            0xFFC100CC         /* DMA36 Bandwidth Monitor Count Current */
+/* =========================
+        DMA37
+   ========================= */
+#define DMA37_NEXT_DESC_PTR            0xFFC10100         /* DMA37 Pointer to Next Initial Descriptor */
+#define DMA37_START_ADDR             0xFFC10104         /* DMA37 Start Address of Current Buffer */
+#define DMA37_CONFIG                   0xFFC10108         /* DMA37 Configuration Register */
+#define DMA37_X_COUNT                  0xFFC1010C         /* DMA37 Inner Loop Count Start Value */
+#define DMA37_X_MODIFY                  0xFFC10110         /* DMA37 Inner Loop Address Increment */
+#define DMA37_Y_COUNT                  0xFFC10114         /* DMA37 Outer Loop Count Start Value (2D only) */
+#define DMA37_Y_MODIFY                  0xFFC10118         /* DMA37 Outer Loop Address Increment (2D only) */
+#define DMA37_CURR_DESC_PTR            0xFFC10124         /* DMA37 Current Descriptor Pointer */
+#define DMA37_PREV_DESC_PTR            0xFFC10128         /* DMA37 Previous Initial Descriptor Pointer */
+#define DMA37_CURR_ADDR              0xFFC1012C         /* DMA37 Current Address */
+#define DMA37_IRQ_STATUS                  0xFFC10130         /* DMA37 Status Register */
+#define DMA37_CURR_X_COUNT              0xFFC10134         /* DMA37 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA37_CURR_Y_COUNT              0xFFC10138         /* DMA37 Current Row Count (2D only) */
+#define DMA37_BWL_COUNT                0xFFC10140         /* DMA37 Bandwidth Limit Count */
+#define DMA37_CURR_BWL_COUNT            0xFFC10144         /* DMA37 Bandwidth Limit Count Current */
+#define DMA37_BWM_COUNT                0xFFC10148         /* DMA37 Bandwidth Monitor Count */
+#define DMA37_CURR_BWM_COUNT            0xFFC1014C         /* DMA37 Bandwidth Monitor Count Current */
+/* =========================
+        DMA38
+   ========================= */
+#define DMA38_NEXT_DESC_PTR            0xFFC12000         /* DMA38 Pointer to Next Initial Descriptor */
+#define DMA38_START_ADDR             0xFFC12004         /* DMA38 Start Address of Current Buffer */
+#define DMA38_CONFIG                   0xFFC12008         /* DMA38 Configuration Register */
+#define DMA38_X_COUNT                  0xFFC1200C         /* DMA38 Inner Loop Count Start Value */
+#define DMA38_X_MODIFY                  0xFFC12010         /* DMA38 Inner Loop Address Increment */
+#define DMA38_Y_COUNT                  0xFFC12014         /* DMA38 Outer Loop Count Start Value (2D only) */
+#define DMA38_Y_MODIFY                  0xFFC12018         /* DMA38 Outer Loop Address Increment (2D only) */
+#define DMA38_CURR_DESC_PTR            0xFFC12024         /* DMA38 Current Descriptor Pointer */
+#define DMA38_PREV_DESC_PTR            0xFFC12028         /* DMA38 Previous Initial Descriptor Pointer */
+#define DMA38_CURR_ADDR              0xFFC1202C         /* DMA38 Current Address */
+#define DMA38_IRQ_STATUS                  0xFFC12030         /* DMA38 Status Register */
+#define DMA38_CURR_X_COUNT              0xFFC12034         /* DMA38 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA38_CURR_Y_COUNT              0xFFC12038         /* DMA38 Current Row Count (2D only) */
+#define DMA38_BWL_COUNT                0xFFC12040         /* DMA38 Bandwidth Limit Count */
+#define DMA38_CURR_BWL_COUNT            0xFFC12044         /* DMA38 Bandwidth Limit Count Current */
+#define DMA38_BWM_COUNT                0xFFC12048         /* DMA38 Bandwidth Monitor Count */
+#define DMA38_CURR_BWM_COUNT            0xFFC1204C         /* DMA38 Bandwidth Monitor Count Current */
+/* =========================
+        DMA39
+   ========================= */
+#define DMA39_NEXT_DESC_PTR            0xFFC12080         /* DMA39 Pointer to Next Initial Descriptor */
+#define DMA39_START_ADDR             0xFFC12084         /* DMA39 Start Address of Current Buffer */
+#define DMA39_CONFIG                   0xFFC12088         /* DMA39 Configuration Register */
+#define DMA39_X_COUNT                  0xFFC1208C         /* DMA39 Inner Loop Count Start Value */
+#define DMA39_X_MODIFY                  0xFFC12090         /* DMA39 Inner Loop Address Increment */
+#define DMA39_Y_COUNT                  0xFFC12094         /* DMA39 Outer Loop Count Start Value (2D only) */
+#define DMA39_Y_MODIFY                  0xFFC12098         /* DMA39 Outer Loop Address Increment (2D only) */
+#define DMA39_CURR_DESC_PTR            0xFFC120A4         /* DMA39 Current Descriptor Pointer */
+#define DMA39_PREV_DESC_PTR            0xFFC120A8         /* DMA39 Previous Initial Descriptor Pointer */
+#define DMA39_CURR_ADDR              0xFFC120AC         /* DMA39 Current Address */
+#define DMA39_IRQ_STATUS                  0xFFC120B0         /* DMA39 Status Register */
+#define DMA39_CURR_X_COUNT              0xFFC120B4         /* DMA39 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA39_CURR_Y_COUNT              0xFFC120B8         /* DMA39 Current Row Count (2D only) */
+#define DMA39_BWL_COUNT                0xFFC120C0         /* DMA39 Bandwidth Limit Count */
+#define DMA39_CURR_BWL_COUNT            0xFFC120C4         /* DMA39 Bandwidth Limit Count Current */
+#define DMA39_BWM_COUNT                0xFFC120C8         /* DMA39 Bandwidth Monitor Count */
+#define DMA39_CURR_BWM_COUNT            0xFFC120CC         /* DMA39 Bandwidth Monitor Count Current */
+/* =========================
+        DMA40
+   ========================= */
+#define DMA40_NEXT_DESC_PTR            0xFFC12100         /* DMA40 Pointer to Next Initial Descriptor */
+#define DMA40_START_ADDR             0xFFC12104         /* DMA40 Start Address of Current Buffer */
+#define DMA40_CONFIG                   0xFFC12108         /* DMA40 Configuration Register */
+#define DMA40_X_COUNT                  0xFFC1210C         /* DMA40 Inner Loop Count Start Value */
+#define DMA40_X_MODIFY                  0xFFC12110         /* DMA40 Inner Loop Address Increment */
+#define DMA40_Y_COUNT                  0xFFC12114         /* DMA40 Outer Loop Count Start Value (2D only) */
+#define DMA40_Y_MODIFY                  0xFFC12118         /* DMA40 Outer Loop Address Increment (2D only) */
+#define DMA40_CURR_DESC_PTR            0xFFC12124         /* DMA40 Current Descriptor Pointer */
+#define DMA40_PREV_DESC_PTR            0xFFC12128         /* DMA40 Previous Initial Descriptor Pointer */
+#define DMA40_CURR_ADDR              0xFFC1212C         /* DMA40 Current Address */
+#define DMA40_IRQ_STATUS                  0xFFC12130         /* DMA40 Status Register */
+#define DMA40_CURR_X_COUNT              0xFFC12134         /* DMA40 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA40_CURR_Y_COUNT              0xFFC12138         /* DMA40 Current Row Count (2D only) */
+#define DMA40_BWL_COUNT                0xFFC12140         /* DMA40 Bandwidth Limit Count */
+#define DMA40_CURR_BWL_COUNT            0xFFC12144         /* DMA40 Bandwidth Limit Count Current */
+#define DMA40_BWM_COUNT                0xFFC12148         /* DMA40 Bandwidth Monitor Count */
+#define DMA40_CURR_BWM_COUNT            0xFFC1214C         /* DMA40 Bandwidth Monitor Count Current */
+/* =========================
+        DMA41
+   ========================= */
+#define DMA41_NEXT_DESC_PTR            0xFFC12180         /* DMA41 Pointer to Next Initial Descriptor */
+#define DMA41_START_ADDR             0xFFC12184         /* DMA41 Start Address of Current Buffer */
+#define DMA41_CONFIG                   0xFFC12188         /* DMA41 Configuration Register */
+#define DMA41_X_COUNT                  0xFFC1218C         /* DMA41 Inner Loop Count Start Value */
+#define DMA41_X_MODIFY                  0xFFC12190         /* DMA41 Inner Loop Address Increment */
+#define DMA41_Y_COUNT                  0xFFC12194         /* DMA41 Outer Loop Count Start Value (2D only) */
+#define DMA41_Y_MODIFY                  0xFFC12198         /* DMA41 Outer Loop Address Increment (2D only) */
+#define DMA41_CURR_DESC_PTR            0xFFC121A4         /* DMA41 Current Descriptor Pointer */
+#define DMA41_PREV_DESC_PTR            0xFFC121A8         /* DMA41 Previous Initial Descriptor Pointer */
+#define DMA41_CURR_ADDR              0xFFC121AC         /* DMA41 Current Address */
+#define DMA41_IRQ_STATUS                  0xFFC121B0         /* DMA41 Status Register */
+#define DMA41_CURR_X_COUNT              0xFFC121B4         /* DMA41 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA41_CURR_Y_COUNT              0xFFC121B8         /* DMA41 Current Row Count (2D only) */
+#define DMA41_BWL_COUNT                0xFFC121C0         /* DMA41 Bandwidth Limit Count */
+#define DMA41_CURR_BWL_COUNT            0xFFC121C4         /* DMA41 Bandwidth Limit Count Current */
+#define DMA41_BWM_COUNT                0xFFC121C8         /* DMA41 Bandwidth Monitor Count */
+#define DMA41_CURR_BWM_COUNT            0xFFC121CC         /* DMA41 Bandwidth Monitor Count Current */
+/* =========================
+        DMA42
+   ========================= */
+#define DMA42_NEXT_DESC_PTR            0xFFC14000         /* DMA42 Pointer to Next Initial Descriptor */
+#define DMA42_START_ADDR             0xFFC14004         /* DMA42 Start Address of Current Buffer */
+#define DMA42_CONFIG                   0xFFC14008         /* DMA42 Configuration Register */
+#define DMA42_X_COUNT                  0xFFC1400C         /* DMA42 Inner Loop Count Start Value */
+#define DMA42_X_MODIFY                  0xFFC14010         /* DMA42 Inner Loop Address Increment */
+#define DMA42_Y_COUNT                  0xFFC14014         /* DMA42 Outer Loop Count Start Value (2D only) */
+#define DMA42_Y_MODIFY                  0xFFC14018         /* DMA42 Outer Loop Address Increment (2D only) */
+#define DMA42_CURR_DESC_PTR            0xFFC14024         /* DMA42 Current Descriptor Pointer */
+#define DMA42_PREV_DESC_PTR            0xFFC14028         /* DMA42 Previous Initial Descriptor Pointer */
+#define DMA42_CURR_ADDR              0xFFC1402C         /* DMA42 Current Address */
+#define DMA42_IRQ_STATUS                  0xFFC14030         /* DMA42 Status Register */
+#define DMA42_CURR_X_COUNT              0xFFC14034         /* DMA42 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA42_CURR_Y_COUNT              0xFFC14038         /* DMA42 Current Row Count (2D only) */
+#define DMA42_BWL_COUNT                0xFFC14040         /* DMA42 Bandwidth Limit Count */
+#define DMA42_CURR_BWL_COUNT            0xFFC14044         /* DMA42 Bandwidth Limit Count Current */
+#define DMA42_BWM_COUNT                0xFFC14048         /* DMA42 Bandwidth Monitor Count */
+#define DMA42_CURR_BWM_COUNT            0xFFC1404C         /* DMA42 Bandwidth Monitor Count Current */
+/* =========================
+        DMA43
+   ========================= */
+#define DMA43_NEXT_DESC_PTR            0xFFC14080         /* DMA43 Pointer to Next Initial Descriptor */
+#define DMA43_START_ADDR             0xFFC14084         /* DMA43 Start Address of Current Buffer */
+#define DMA43_CONFIG                   0xFFC14088         /* DMA43 Configuration Register */
+#define DMA43_X_COUNT                  0xFFC1408C         /* DMA43 Inner Loop Count Start Value */
+#define DMA43_X_MODIFY                  0xFFC14090         /* DMA43 Inner Loop Address Increment */
+#define DMA43_Y_COUNT                  0xFFC14094         /* DMA43 Outer Loop Count Start Value (2D only) */
+#define DMA43_Y_MODIFY                  0xFFC14098         /* DMA43 Outer Loop Address Increment (2D only) */
+#define DMA43_CURR_DESC_PTR            0xFFC140A4         /* DMA43 Current Descriptor Pointer */
+#define DMA43_PREV_DESC_PTR            0xFFC140A8         /* DMA43 Previous Initial Descriptor Pointer */
+#define DMA43_CURR_ADDR              0xFFC140AC         /* DMA43 Current Address */
+#define DMA43_IRQ_STATUS                  0xFFC140B0         /* DMA43 Status Register */
+#define DMA43_CURR_X_COUNT              0xFFC140B4         /* DMA43 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA43_CURR_Y_COUNT              0xFFC140B8         /* DMA43 Current Row Count (2D only) */
+#define DMA43_BWL_COUNT                0xFFC140C0         /* DMA43 Bandwidth Limit Count */
+#define DMA43_CURR_BWL_COUNT            0xFFC140C4         /* DMA43 Bandwidth Limit Count Current */
+#define DMA43_BWM_COUNT                0xFFC140C8         /* DMA43 Bandwidth Monitor Count */
+#define DMA43_CURR_BWM_COUNT            0xFFC140CC         /* DMA43 Bandwidth Monitor Count Current */
+/* =========================
+        DMA44
+   ========================= */
+#define DMA44_NEXT_DESC_PTR            0xFFC14100         /* DMA44 Pointer to Next Initial Descriptor */
+#define DMA44_START_ADDR             0xFFC14104         /* DMA44 Start Address of Current Buffer */
+#define DMA44_CONFIG                   0xFFC14108         /* DMA44 Configuration Register */
+#define DMA44_X_COUNT                  0xFFC1410C         /* DMA44 Inner Loop Count Start Value */
+#define DMA44_X_MODIFY                  0xFFC14110         /* DMA44 Inner Loop Address Increment */
+#define DMA44_Y_COUNT                  0xFFC14114         /* DMA44 Outer Loop Count Start Value (2D only) */
+#define DMA44_Y_MODIFY                  0xFFC14118         /* DMA44 Outer Loop Address Increment (2D only) */
+#define DMA44_CURR_DESC_PTR            0xFFC14124         /* DMA44 Current Descriptor Pointer */
+#define DMA44_PREV_DESC_PTR            0xFFC14128         /* DMA44 Previous Initial Descriptor Pointer */
+#define DMA44_CURR_ADDR              0xFFC1412C         /* DMA44 Current Address */
+#define DMA44_IRQ_STATUS                  0xFFC14130         /* DMA44 Status Register */
+#define DMA44_CURR_X_COUNT              0xFFC14134         /* DMA44 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA44_CURR_Y_COUNT              0xFFC14138         /* DMA44 Current Row Count (2D only) */
+#define DMA44_BWL_COUNT                0xFFC14140         /* DMA44 Bandwidth Limit Count */
+#define DMA44_CURR_BWL_COUNT            0xFFC14144         /* DMA44 Bandwidth Limit Count Current */
+#define DMA44_BWM_COUNT                0xFFC14148         /* DMA44 Bandwidth Monitor Count */
+#define DMA44_CURR_BWM_COUNT            0xFFC1414C         /* DMA44 Bandwidth Monitor Count Current */
+/* =========================
+        DMA45
+   ========================= */
+#define DMA45_NEXT_DESC_PTR            0xFFC14180         /* DMA45 Pointer to Next Initial Descriptor */
+#define DMA45_START_ADDR             0xFFC14184         /* DMA45 Start Address of Current Buffer */
+#define DMA45_CONFIG                   0xFFC14188         /* DMA45 Configuration Register */
+#define DMA45_X_COUNT                  0xFFC1418C         /* DMA45 Inner Loop Count Start Value */
+#define DMA45_X_MODIFY                  0xFFC14190         /* DMA45 Inner Loop Address Increment */
+#define DMA45_Y_COUNT                  0xFFC14194         /* DMA45 Outer Loop Count Start Value (2D only) */
+#define DMA45_Y_MODIFY                  0xFFC14198         /* DMA45 Outer Loop Address Increment (2D only) */
+#define DMA45_CURR_DESC_PTR            0xFFC141A4         /* DMA45 Current Descriptor Pointer */
+#define DMA45_PREV_DESC_PTR            0xFFC141A8         /* DMA45 Previous Initial Descriptor Pointer */
+#define DMA45_CURR_ADDR              0xFFC141AC         /* DMA45 Current Address */
+#define DMA45_IRQ_STATUS                  0xFFC141B0         /* DMA45 Status Register */
+#define DMA45_CURR_X_COUNT              0xFFC141B4         /* DMA45 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA45_CURR_Y_COUNT              0xFFC141B8         /* DMA45 Current Row Count (2D only) */
+#define DMA45_BWL_COUNT                0xFFC141C0         /* DMA45 Bandwidth Limit Count */
+#define DMA45_CURR_BWL_COUNT            0xFFC141C4         /* DMA45 Bandwidth Limit Count Current */
+#define DMA45_BWM_COUNT                0xFFC141C8         /* DMA45 Bandwidth Monitor Count */
+#define DMA45_CURR_BWM_COUNT            0xFFC141CC         /* DMA45 Bandwidth Monitor Count Current */
+/* =========================
+        DMA46
+   ========================= */
+#define DMA46_NEXT_DESC_PTR            0xFFC14200         /* DMA46 Pointer to Next Initial Descriptor */
+#define DMA46_START_ADDR             0xFFC14204         /* DMA46 Start Address of Current Buffer */
+#define DMA46_CONFIG                   0xFFC14208         /* DMA46 Configuration Register */
+#define DMA46_X_COUNT                  0xFFC1420C         /* DMA46 Inner Loop Count Start Value */
+#define DMA46_X_MODIFY                  0xFFC14210         /* DMA46 Inner Loop Address Increment */
+#define DMA46_Y_COUNT                  0xFFC14214         /* DMA46 Outer Loop Count Start Value (2D only) */
+#define DMA46_Y_MODIFY                  0xFFC14218         /* DMA46 Outer Loop Address Increment (2D only) */
+#define DMA46_CURR_DESC_PTR            0xFFC14224         /* DMA46 Current Descriptor Pointer */
+#define DMA46_PREV_DESC_PTR            0xFFC14228         /* DMA46 Previous Initial Descriptor Pointer */
+#define DMA46_CURR_ADDR              0xFFC1422C         /* DMA46 Current Address */
+#define DMA46_IRQ_STATUS                  0xFFC14230         /* DMA46 Status Register */
+#define DMA46_CURR_X_COUNT              0xFFC14234         /* DMA46 Current Count(1D) or intra-row XCNT (2D) */
+#define DMA46_CURR_Y_COUNT              0xFFC14238         /* DMA46 Current Row Count (2D only) */
+#define DMA46_BWL_COUNT                0xFFC14240         /* DMA46 Bandwidth Limit Count */
+#define DMA46_CURR_BWL_COUNT            0xFFC14244         /* DMA46 Bandwidth Limit Count Current */
+#define DMA46_BWM_COUNT                0xFFC14248         /* DMA46 Bandwidth Monitor Count */
+#define DMA46_CURR_BWM_COUNT            0xFFC1424C         /* DMA46 Bandwidth Monitor Count Current */
+/********************************************************************************
+    DMA Alias Definitions
+ ********************************************************************************/
+#define MDMA0_DEST_CRC0_NEXT_DESC_PTR   (DMA22_NEXT_DESC_PTR)
+#define MDMA0_DEST_CRC0_START_ADDR    (DMA22_START_ADDR)
+#define MDMA0_DEST_CRC0_CONFIG          (DMA22_CONFIG)
+#define MDMA0_DEST_CRC0_X_COUNT         (DMA22_X_COUNT)
+#define MDMA0_DEST_CRC0_X_MODIFY         (DMA22_X_MODIFY)
+#define MDMA0_DEST_CRC0_Y_COUNT         (DMA22_Y_COUNT)
+#define MDMA0_DEST_CRC0_Y_MODIFY         (DMA22_Y_MODIFY)
+#define MDMA0_DEST_CRC0_CURR_DESC_PTR   (DMA22_CURR_DESC_PTR)
+#define MDMA0_DEST_CRC0_PREV_DESC_PTR   (DMA22_PREV_DESC_PTR)
+#define MDMA0_DEST_CRC0_CURR_ADDR     (DMA22_CURR_ADDR)
+#define MDMA0_DEST_CRC0_IRQ_STATUS         (DMA22_IRQ_STATUS)
+#define MDMA0_DEST_CRC0_CURR_X_COUNT     (DMA22_CURR_X_COUNT)
+#define MDMA0_DEST_CRC0_CURR_Y_COUNT     (DMA22_CURR_Y_COUNT)
+#define MDMA0_DEST_CRC0_BWL_COUNT       (DMA22_BWL_COUNT)
+#define MDMA0_DEST_CRC0_CURR_BWL_COUNT   (DMA22_CURR_BWL_COUNT)
+#define MDMA0_DEST_CRC0_BWM_COUNT       (DMA22_BWM_COUNT)
+#define MDMA0_DEST_CRC0_CURR_BWM_COUNT   (DMA22_CURR_BWM_COUNT)
+#define MDMA0_SRC_CRC0_NEXT_DESC_PTR    (DMA21_NEXT_DESC_PTR)
+#define MDMA0_SRC_CRC0_START_ADDR     (DMA21_START_ADDR)
+#define MDMA0_SRC_CRC0_CONFIG           (DMA21_CONFIG)
+#define MDMA0_SRC_CRC0_X_COUNT          (DMA21_X_COUNT)
+#define MDMA0_SRC_CRC0_X_MODIFY          (DMA21_X_MODIFY)
+#define MDMA0_SRC_CRC0_Y_COUNT          (DMA21_Y_COUNT)
+#define MDMA0_SRC_CRC0_Y_MODIFY          (DMA21_Y_MODIFY)
+#define MDMA0_SRC_CRC0_CURR_DESC_PTR    (DMA21_CURR_DESC_PTR)
+#define MDMA0_SRC_CRC0_PREV_DESC_PTR    (DMA21_PREV_DESC_PTR)
+#define MDMA0_SRC_CRC0_CURR_ADDR      (DMA21_CURR_ADDR)
+#define MDMA0_SRC_CRC0_IRQ_STATUS          (DMA21_IRQ_STATUS)
+#define MDMA0_SRC_CRC0_CURR_X_COUNT      (DMA21_CURR_X_COUNT)
+#define MDMA0_SRC_CRC0_CURR_Y_COUNT      (DMA21_CURR_Y_COUNT)
+#define MDMA0_SRC_CRC0_BWL_COUNT        (DMA21_BWL_COUNT)
+#define MDMA0_SRC_CRC0_CURR_BWL_COUNT    (DMA21_CURR_BWL_COUNT)
+#define MDMA0_SRC_CRC0_BWM_COUNT        (DMA21_BWM_COUNT)
+#define MDMA0_SRC_CRC0_CURR_BWM_COUNT    (DMA21_CURR_BWM_COUNT)
+#define MDMA1_DEST_CRC1_NEXT_DESC_PTR   (DMA24_NEXT_DESC_PTR)
+#define MDMA1_DEST_CRC1_START_ADDR    (DMA24_START_ADDR)
+#define MDMA1_DEST_CRC1_CONFIG          (DMA24_CONFIG)
+#define MDMA1_DEST_CRC1_X_COUNT         (DMA24_X_COUNT)
+#define MDMA1_DEST_CRC1_X_MODIFY         (DMA24_X_MODIFY)
+#define MDMA1_DEST_CRC1_Y_COUNT         (DMA24_Y_COUNT)
+#define MDMA1_DEST_CRC1_Y_MODIFY         (DMA24_Y_MODIFY)
+#define MDMA1_DEST_CRC1_CURR_DESC_PTR   (DMA24_CURR_DESC_PTR)
+#define MDMA1_DEST_CRC1_PREV_DESC_PTR   (DMA24_PREV_DESC_PTR)
+#define MDMA1_DEST_CRC1_CURR_ADDR     (DMA24_CURR_ADDR)
+#define MDMA1_DEST_CRC1_IRQ_STATUS         (DMA24_IRQ_STATUS)
+#define MDMA1_DEST_CRC1_CURR_X_COUNT     (DMA24_CURR_X_COUNT)
+#define MDMA1_DEST_CRC1_CURR_Y_COUNT     (DMA24_CURR_Y_COUNT)
+#define MDMA1_DEST_CRC1_BWL_COUNT       (DMA24_BWL_COUNT)
+#define MDMA1_DEST_CRC1_CURR_BWL_COUNT   (DMA24_CURR_BWL_COUNT)
+#define MDMA1_DEST_CRC1_BWM_COUNT       (DMA24_BWM_COUNT)
+#define MDMA1_DEST_CRC1_CURR_BWM_COUNT   (DMA24_CURR_BWM_COUNT)
+#define MDMA1_SRC_CRC1_NEXT_DESC_PTR    (DMA23_NEXT_DESC_PTR)
+#define MDMA1_SRC_CRC1_START_ADDR     (DMA23_START_ADDR)
+#define MDMA1_SRC_CRC1_CONFIG           (DMA23_CONFIG)
+#define MDMA1_SRC_CRC1_X_COUNT          (DMA23_X_COUNT)
+#define MDMA1_SRC_CRC1_X_MODIFY          (DMA23_X_MODIFY)
+#define MDMA1_SRC_CRC1_Y_COUNT          (DMA23_Y_COUNT)
+#define MDMA1_SRC_CRC1_Y_MODIFY          (DMA23_Y_MODIFY)
+#define MDMA1_SRC_CRC1_CURR_DESC_PTR    (DMA23_CURR_DESC_PTR)
+#define MDMA1_SRC_CRC1_PREV_DESC_PTR    (DMA23_PREV_DESC_PTR)
+#define MDMA1_SRC_CRC1_CURR_ADDR      (DMA23_CURR_ADDR)
+#define MDMA1_SRC_CRC1_IRQ_STATUS          (DMA23_IRQ_STATUS)
+#define MDMA1_SRC_CRC1_CURR_X_COUNT      (DMA23_CURR_X_COUNT)
+#define MDMA1_SRC_CRC1_CURR_Y_COUNT      (DMA23_CURR_Y_COUNT)
+#define MDMA1_SRC_CRC1_BWL_COUNT        (DMA23_BWL_COUNT)
+#define MDMA1_SRC_CRC1_CURR_BWL_COUNT    (DMA23_CURR_BWL_COUNT)
+#define MDMA1_SRC_CRC1_BWM_COUNT        (DMA23_BWM_COUNT)
+#define MDMA1_SRC_CRC1_CURR_BWM_COUNT    (DMA23_CURR_BWM_COUNT)
+#define MDMA2_DEST_NEXT_DESC_PTR            (DMA26_NEXT_DESC_PTR)
+#define MDMA2_DEST_START_ADDR             (DMA26_START_ADDR)
+#define MDMA2_DEST_CONFIG                   (DMA26_CONFIG)
+#define MDMA2_DEST_X_COUNT                  (DMA26_X_COUNT)
+#define MDMA2_DEST_X_MODIFY                  (DMA26_X_MODIFY)
+#define MDMA2_DEST_Y_COUNT                  (DMA26_Y_COUNT)
+#define MDMA2_DEST_Y_MODIFY                  (DMA26_Y_MODIFY)
+#define MDMA2_DEST_CURR_DESC_PTR            (DMA26_CURR_DESC_PTR)
+#define MDMA2_DEST_PREV_DESC_PTR            (DMA26_PREV_DESC_PTR)
+#define MDMA2_DEST_CURR_ADDR              (DMA26_CURR_ADDR)
+#define MDMA2_DEST_IRQ_STATUS                  (DMA26_IRQ_STATUS)
+#define MDMA2_DEST_CURR_X_COUNT              (DMA26_CURR_X_COUNT)
+#define MDMA2_DEST_CURR_Y_COUNT              (DMA26_CURR_Y_COUNT)
+#define MDMA2_DEST_BWL_COUNT                (DMA26_BWL_COUNT)
+#define MDMA2_DEST_CURR_BWL_COUNT            (DMA26_CURR_BWL_COUNT)
+#define MDMA2_DEST_BWM_COUNT                (DMA26_BWM_COUNT)
+#define MDMA2_DEST_CURR_BWM_COUNT            (DMA26_CURR_BWM_COUNT)
+#define MDMA2_SRC_NEXT_DESC_PTR            (DMA25_NEXT_DESC_PTR)
+#define MDMA2_SRC_START_ADDR             (DMA25_START_ADDR)
+#define MDMA2_SRC_CONFIG                   (DMA25_CONFIG)
+#define MDMA2_SRC_X_COUNT                  (DMA25_X_COUNT)
+#define MDMA2_SRC_X_MODIFY                  (DMA25_X_MODIFY)
+#define MDMA2_SRC_Y_COUNT                  (DMA25_Y_COUNT)
+#define MDMA2_SRC_Y_MODIFY                  (DMA25_Y_MODIFY)
+#define MDMA2_SRC_CURR_DESC_PTR            (DMA25_CURR_DESC_PTR)
+#define MDMA2_SRC_PREV_DESC_PTR            (DMA25_PREV_DESC_PTR)
+#define MDMA2_SRC_CURR_ADDR              (DMA25_CURR_ADDR)
+#define MDMA2_SRC_IRQ_STATUS                  (DMA25_IRQ_STATUS)
+#define MDMA2_SRC_CURR_X_COUNT              (DMA25_CURR_X_COUNT)
+#define MDMA2_SRC_CURR_Y_COUNT              (DMA25_CURR_Y_COUNT)
+#define MDMA2_SRC_BWL_COUNT                (DMA25_BWL_COUNT)
+#define MDMA2_SRC_CURR_BWL_COUNT            (DMA25_CURR_BWL_COUNT)
+#define MDMA2_SRC_BWM_COUNT                (DMA25_BWM_COUNT)
+#define MDMA2_SRC_CURR_BWM_COUNT            (DMA25_CURR_BWM_COUNT)
+#define MDMA3_DEST_NEXT_DESC_PTR            (DMA28_NEXT_DESC_PTR)
+#define MDMA3_DEST_START_ADDR             (DMA28_START_ADDR)
+#define MDMA3_DEST_CONFIG                   (DMA28_CONFIG)
+#define MDMA3_DEST_X_COUNT                  (DMA28_X_COUNT)
+#define MDMA3_DEST_X_MODIFY                  (DMA28_X_MODIFY)
+#define MDMA3_DEST_Y_COUNT                  (DMA28_Y_COUNT)
+#define MDMA3_DEST_Y_MODIFY                  (DMA28_Y_MODIFY)
+#define MDMA3_DEST_CURR_DESC_PTR            (DMA28_CURR_DESC_PTR)
+#define MDMA3_DEST_PREV_DESC_PTR            (DMA28_PREV_DESC_PTR)
+#define MDMA3_DEST_CURR_ADDR              (DMA28_CURR_ADDR)
+#define MDMA3_DEST_IRQ_STATUS                  (DMA28_IRQ_STATUS)
+#define MDMA3_DEST_CURR_X_COUNT              (DMA28_CURR_X_COUNT)
+#define MDMA3_DEST_CURR_Y_COUNT              (DMA28_CURR_Y_COUNT)
+#define MDMA3_DEST_BWL_COUNT                (DMA28_BWL_COUNT)
+#define MDMA3_DEST_CURR_BWL_COUNT            (DMA28_CURR_BWL_COUNT)
+#define MDMA3_DEST_BWM_COUNT                (DMA28_BWM_COUNT)
+#define MDMA3_DEST_CURR_BWM_COUNT            (DMA28_CURR_BWM_COUNT)
+#define MDMA3_SRC_NEXT_DESC_PTR            (DMA27_NEXT_DESC_PTR)
+#define MDMA3_SRC_START_ADDR             (DMA27_START_ADDR)
+#define MDMA3_SRC_CONFIG                   (DMA27_CONFIG)
+#define MDMA3_SRC_X_COUNT                  (DMA27_X_COUNT)
+#define MDMA3_SRC_X_MODIFY                  (DMA27_X_MODIFY)
+#define MDMA3_SRC_Y_COUNT                  (DMA27_Y_COUNT)
+#define MDMA3_SRC_Y_MODIFY                  (DMA27_Y_MODIFY)
+#define MDMA3_SRC_CURR_DESC_PTR            (DMA27_CURR_DESC_PTR)
+#define MDMA3_SRC_PREV_DESC_PTR            (DMA27_PREV_DESC_PTR)
+#define MDMA3_SRC_CURR_ADDR              (DMA27_CURR_ADDR)
+#define MDMA3_SRC_IRQ_STATUS                  (DMA27_IRQ_STATUS)
+#define MDMA3_SRC_CURR_X_COUNT              (DMA27_CURR_X_COUNT)
+#define MDMA3_SRC_CURR_Y_COUNT              (DMA27_CURR_Y_COUNT)
+#define MDMA3_SRC_BWL_COUNT                (DMA27_BWL_COUNT)
+#define MDMA3_SRC_CURR_BWL_COUNT            (DMA27_CURR_BWL_COUNT)
+#define MDMA3_SRC_BWM_COUNT                (DMA27_BWM_COUNT)
+#define MDMA3_SRC_CURR_BWM_COUNT            (DMA27_CURR_BWM_COUNT)
+/* =========================
+        DMC Registers
+   ========================= */
+/* =========================
+        DMC0
+   ========================= */
+#define DMC0_ID                     0xFFC80000         /* DMC0 Identification Register */
+#define DMC0_CTL                    0xFFC80004         /* DMC0 Control Register */
+#define DMC0_STAT                   0xFFC80008         /* DMC0 Status Register */
+#define DMC0_EFFCTL                 0xFFC8000C         /* DMC0 Efficiency Controller */
+#define DMC0_PRIO                   0xFFC80010         /* DMC0 Priority ID Register */
+#define DMC0_PRIOMSK                0xFFC80014         /* DMC0 Priority ID Mask */
+#define DMC0_CFG                    0xFFC80040         /* DMC0 SDRAM Configuration */
+#define DMC0_TR0                    0xFFC80044         /* DMC0 Timing Register 0 */
+#define DMC0_TR1                    0xFFC80048         /* DMC0 Timing Register 1 */
+#define DMC0_TR2                    0xFFC8004C         /* DMC0 Timing Register 2 */
+#define DMC0_MSK                    0xFFC8005C         /* DMC0 Mode Register Mask */
+#define DMC0_MR                     0xFFC80060         /* DMC0 Mode Shadow register */
+#define DMC0_EMR1                   0xFFC80064         /* DMC0 EMR1 Shadow Register */
+#define DMC0_EMR2                   0xFFC80068         /* DMC0 EMR2 Shadow Register */
+#define DMC0_EMR3                   0xFFC8006C         /* DMC0 EMR3 Shadow Register */
+#define DMC0_DLLCTL                 0xFFC80080         /* DMC0 DLL Control Register */
+#define DMC0_PADCTL                 0xFFC800C0         /* DMC0 PAD Control Register 0 */
+#define DEVSZ_64                0x000         /* DMC External Bank Size = 64Mbit */
+#define DEVSZ_128               0x100         /* DMC External Bank Size = 128Mbit */
+#define DEVSZ_256               0x200         /* DMC External Bank Size = 256Mbit */
+#define DEVSZ_512               0x300         /* DMC External Bank Size = 512Mbit */
+#define DEVSZ_1G                0x400         /* DMC External Bank Size = 1Gbit */
+#define DEVSZ_2G                0x500         /* DMC External Bank Size = 2Gbit */
+/* =========================
+        L2CTL Registers
+   ========================= */
+/* =========================
+        L2CTL0
+   ========================= */
+#define L2CTL0_CTL                  0xFFCA3000         /* L2CTL0 L2 Control Register */
+#define L2CTL0_ACTL_C0              0xFFCA3004         /* L2CTL0 L2 Core 0 Access Control Register */
+#define L2CTL0_ACTL_C1              0xFFCA3008         /* L2CTL0 L2 Core 1 Access Control Register */
+#define L2CTL0_ACTL_SYS             0xFFCA300C         /* L2CTL0 L2 System Access Control Register */
+#define L2CTL0_STAT                 0xFFCA3010         /* L2CTL0 L2 Status Register */
+#define L2CTL0_RPCR                 0xFFCA3014         /* L2CTL0 L2 Read Priority Count Register */
+#define L2CTL0_WPCR                 0xFFCA3018         /* L2CTL0 L2 Write Priority Count Register */
+#define L2CTL0_RFA                  0xFFCA3024         /* L2CTL0 L2 Refresh Address Regsiter */
+#define L2CTL0_ERRADDR0             0xFFCA3040         /* L2CTL0 L2 Bank 0 ECC Error Address Register */
+#define L2CTL0_ERRADDR1             0xFFCA3044         /* L2CTL0 L2 Bank 1 ECC Error Address Register */
+#define L2CTL0_ERRADDR2             0xFFCA3048         /* L2CTL0 L2 Bank 2 ECC Error Address Register */
+#define L2CTL0_ERRADDR3             0xFFCA304C         /* L2CTL0 L2 Bank 3 ECC Error Address Register */
+#define L2CTL0_ERRADDR4             0xFFCA3050         /* L2CTL0 L2 Bank 4 ECC Error Address Register */
+#define L2CTL0_ERRADDR5             0xFFCA3054         /* L2CTL0 L2 Bank 5 ECC Error Address Register */
+#define L2CTL0_ERRADDR6             0xFFCA3058         /* L2CTL0 L2 Bank 6 ECC Error Address Register */
+#define L2CTL0_ERRADDR7             0xFFCA305C         /* L2CTL0 L2 Bank 7 ECC Error Address Register */
+#define L2CTL0_ET0                  0xFFCA3080         /* L2CTL0 L2 AXI Error 0 Type Register */
+#define L2CTL0_EADDR0               0xFFCA3084         /* L2CTL0 L2 AXI Error 0 Address Register */
+#define L2CTL0_ET1                  0xFFCA3088         /* L2CTL0 L2 AXI Error 1 Type Register */
+#define L2CTL0_EADDR1               0xFFCA308C         /* L2CTL0 L2 AXI Error 1 Address Register */
+/* =========================
+        SEC Registers
+   ========================= */
+/* ------------------------------------------------------------------------------------------------------------------------
+       SEC Core Interface (SCI) Register Definitions
+   ------------------------------------------------------------------------------------------------------------------------ */
+#define SEC_SCI_BASE 0xFFCA4400
+#define SEC_SCI_OFF 0x40
+#define SEC_CCTL 0x0         /* SEC Core Control Register n */
+#define SEC_CSTAT 0x4         /* SEC Core Status Register n */
+#define SEC_CPND 0x8         /* SEC Core Pending IRQ Register n */
+#define SEC_CACT 0xC         /* SEC Core Active IRQ Register n */
+#define SEC_CPMSK 0x10         /* SEC Core IRQ Priority Mask Register n */
+#define SEC_CGMSK 0x14         /* SEC Core IRQ Group Mask Register n */
+#define SEC_CPLVL 0x18         /* SEC Core IRQ Priority Level Register n */
+#define SEC_CSID 0x1C         /* SEC Core IRQ Source ID Register n */
+#define bfin_read_SEC_SCI(n, reg) bfin_read32(SEC_SCI_BASE + (n) * SEC_SCI_OFF + reg)
+#define bfin_write_SEC_SCI(n, reg, val) \
+        bfin_write32(SEC_SCI_BASE + (n) * SEC_SCI_OFF + reg, val)
+/* ------------------------------------------------------------------------------------------------------------------------
+       SEC Fault Management Interface (SFI) Register Definitions
+   ------------------------------------------------------------------------------------------------------------------------ */
+#define SEC_FCTL                   0xFFCA4010         /* SEC Fault Control Register */
+#define SEC_FSTAT                  0xFFCA4014         /* SEC Fault Status Register */
+#define SEC_FSID                   0xFFCA4018         /* SEC Fault Source ID Register */
+#define SEC_FEND                   0xFFCA401C         /* SEC Fault End Register */
+#define SEC_FDLY                   0xFFCA4020         /* SEC Fault Delay Register */
+#define SEC_FDLY_CUR               0xFFCA4024         /* SEC Fault Delay Current Register */
+#define SEC_FSRDLY                 0xFFCA4028         /* SEC Fault System Reset Delay Register */
+#define SEC_FSRDLY_CUR             0xFFCA402C         /* SEC Fault System Reset Delay Current Register */
+#define SEC_FCOPP                  0xFFCA4030         /* SEC Fault COP Period Register */
+#define SEC_FCOPP_CUR              0xFFCA4034         /* SEC Fault COP Period Current Register */
+/* ------------------------------------------------------------------------------------------------------------------------
+       SEC Global Register Definitions
+   ------------------------------------------------------------------------------------------------------------------------ */
+#define SEC_GCTL                   0xFFCA4000         /* SEC Global Control Register */
+#define SEC_GSTAT                  0xFFCA4004         /* SEC Global Status Register */
+#define SEC_RAISE                  0xFFCA4008         /* SEC Global Raise Register */
+#define SEC_END                    0xFFCA400C         /* SEC Global End Register */
+/* ------------------------------------------------------------------------------------------------------------------------
+       SEC Source Interface (SSI) Register Definitions
+   ------------------------------------------------------------------------------------------------------------------------ */
+#define SEC_SCTL0                  0xFFCA4800         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL1                  0xFFCA4808         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL2                  0xFFCA4810         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL3                  0xFFCA4818         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL4                  0xFFCA4820         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL5                  0xFFCA4828         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL6                  0xFFCA4830         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL7                  0xFFCA4838         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL8                  0xFFCA4840         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL9                  0xFFCA4848         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL10                 0xFFCA4850         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL11                 0xFFCA4858         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL12                 0xFFCA4860         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL13                 0xFFCA4868         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL14                 0xFFCA4870         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL15                 0xFFCA4878         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL16                 0xFFCA4880         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL17                 0xFFCA4888         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL18                 0xFFCA4890         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL19                 0xFFCA4898         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL20                 0xFFCA48A0         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL21                 0xFFCA48A8         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL22                 0xFFCA48B0         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL23                 0xFFCA48B8         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL24                 0xFFCA48C0         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL25                 0xFFCA48C8         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL26                 0xFFCA48D0         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL27                 0xFFCA48D8         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL28                 0xFFCA48E0         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL29                 0xFFCA48E8         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL30                 0xFFCA48F0         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL31                 0xFFCA48F8         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL32                 0xFFCA4900         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL33                 0xFFCA4908         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL34                 0xFFCA4910         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL35                 0xFFCA4918         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL36                 0xFFCA4920         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL37                 0xFFCA4928         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL38                 0xFFCA4930         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL39                 0xFFCA4938         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL40                 0xFFCA4940         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL41                 0xFFCA4948         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL42                 0xFFCA4950         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL43                 0xFFCA4958         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL44                 0xFFCA4960         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL45                 0xFFCA4968         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL46                 0xFFCA4970         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL47                 0xFFCA4978         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL48                 0xFFCA4980         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL49                 0xFFCA4988         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL50                 0xFFCA4990         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL51                 0xFFCA4998         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL52                 0xFFCA49A0         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL53                 0xFFCA49A8         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL54                 0xFFCA49B0         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL55                 0xFFCA49B8         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL56                 0xFFCA49C0         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL57                 0xFFCA49C8         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL58                 0xFFCA49D0         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL59                 0xFFCA49D8         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL60                 0xFFCA49E0         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL61                 0xFFCA49E8         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL62                 0xFFCA49F0         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL63                 0xFFCA49F8         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL64                 0xFFCA4A00         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL65                 0xFFCA4A08         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL66                 0xFFCA4A10         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL67                 0xFFCA4A18         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL68                 0xFFCA4A20         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL69                 0xFFCA4A28         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL70                 0xFFCA4A30         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL71                 0xFFCA4A38         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL72                 0xFFCA4A40         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL73                 0xFFCA4A48         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL74                 0xFFCA4A50         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL75                 0xFFCA4A58         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL76                 0xFFCA4A60         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL77                 0xFFCA4A68         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL78                 0xFFCA4A70         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL79                 0xFFCA4A78         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL80                 0xFFCA4A80         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL81                 0xFFCA4A88         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL82                 0xFFCA4A90         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL83                 0xFFCA4A98         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL84                 0xFFCA4AA0         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL85                 0xFFCA4AA8         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL86                 0xFFCA4AB0         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL87                 0xFFCA4AB8         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL88                 0xFFCA4AC0         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL89                 0xFFCA4AC8         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL90                 0xFFCA4AD0         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL91                 0xFFCA4AD8         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL92                 0xFFCA4AE0         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL93                 0xFFCA4AE8         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL94                 0xFFCA4AF0         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL95                 0xFFCA4AF8         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL96                 0xFFCA4B00         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL97                 0xFFCA4B08         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL98                 0xFFCA4B10         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL99                 0xFFCA4B18         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL100                0xFFCA4B20         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL101                0xFFCA4B28         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL102                0xFFCA4B30         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL103                0xFFCA4B38         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL104                0xFFCA4B40         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL105                0xFFCA4B48         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL106                0xFFCA4B50         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL107                0xFFCA4B58         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL108                0xFFCA4B60         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL109                0xFFCA4B68         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL110                0xFFCA4B70         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL111                0xFFCA4B78         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL112                0xFFCA4B80         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL113                0xFFCA4B88         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL114                0xFFCA4B90         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL115                0xFFCA4B98         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL116                0xFFCA4BA0         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL117                0xFFCA4BA8         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL118                0xFFCA4BB0         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL119                0xFFCA4BB8         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL120                0xFFCA4BC0         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL121                0xFFCA4BC8         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL122                0xFFCA4BD0         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL123                0xFFCA4BD8         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL124                0xFFCA4BE0         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL125                0xFFCA4BE8         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL126                0xFFCA4BF0         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL127                0xFFCA4BF8         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL128                0xFFCA4C00         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL129                0xFFCA4C08         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL130                0xFFCA4C10         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL131                0xFFCA4C18         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL132                0xFFCA4C20         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL133                0xFFCA4C28         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL134                0xFFCA4C30         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL135                0xFFCA4C38         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL136                0xFFCA4C40         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL137                0xFFCA4C48         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL138                0xFFCA4C50         /* SEC IRQ Source Control Register n */
+#define SEC_SCTL139                0xFFCA4C58         /* SEC IRQ Source Control Register n */
+#define SEC_SSTAT0                 0xFFCA4804         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT1                 0xFFCA480C         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT2                 0xFFCA4814         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT3                 0xFFCA481C         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT4                 0xFFCA4824         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT5                 0xFFCA482C         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT6                 0xFFCA4834         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT7                 0xFFCA483C         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT8                 0xFFCA4844         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT9                 0xFFCA484C         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT10                0xFFCA4854         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT11                0xFFCA485C         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT12                0xFFCA4864         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT13                0xFFCA486C         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT14                0xFFCA4874         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT15                0xFFCA487C         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT16                0xFFCA4884         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT17                0xFFCA488C         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT18                0xFFCA4894         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT19                0xFFCA489C         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT20                0xFFCA48A4         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT21                0xFFCA48AC         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT22                0xFFCA48B4         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT23                0xFFCA48BC         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT24                0xFFCA48C4         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT25                0xFFCA48CC         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT26                0xFFCA48D4         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT27                0xFFCA48DC         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT28                0xFFCA48E4         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT29                0xFFCA48EC         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT30                0xFFCA48F4         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT31                0xFFCA48FC         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT32                0xFFCA4904         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT33                0xFFCA490C         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT34                0xFFCA4914         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT35                0xFFCA491C         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT36                0xFFCA4924         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT37                0xFFCA492C         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT38                0xFFCA4934         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT39                0xFFCA493C         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT40                0xFFCA4944         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT41                0xFFCA494C         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT42                0xFFCA4954         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT43                0xFFCA495C         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT44                0xFFCA4964         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT45                0xFFCA496C         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT46                0xFFCA4974         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT47                0xFFCA497C         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT48                0xFFCA4984         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT49                0xFFCA498C         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT50                0xFFCA4994         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT51                0xFFCA499C         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT52                0xFFCA49A4         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT53                0xFFCA49AC         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT54                0xFFCA49B4         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT55                0xFFCA49BC         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT56                0xFFCA49C4         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT57                0xFFCA49CC         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT58                0xFFCA49D4         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT59                0xFFCA49DC         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT60                0xFFCA49E4         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT61                0xFFCA49EC         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT62                0xFFCA49F4         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT63                0xFFCA49FC         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT64                0xFFCA4A04         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT65                0xFFCA4A0C         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT66                0xFFCA4A14         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT67                0xFFCA4A1C         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT68                0xFFCA4A24         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT69                0xFFCA4A2C         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT70                0xFFCA4A34         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT71                0xFFCA4A3C         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT72                0xFFCA4A44         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT73                0xFFCA4A4C         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT74                0xFFCA4A54         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT75                0xFFCA4A5C         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT76                0xFFCA4A64         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT77                0xFFCA4A6C         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT78                0xFFCA4A74         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT79                0xFFCA4A7C         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT80                0xFFCA4A84         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT81                0xFFCA4A8C         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT82                0xFFCA4A94         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT83                0xFFCA4A9C         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT84                0xFFCA4AA4         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT85                0xFFCA4AAC         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT86                0xFFCA4AB4         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT87                0xFFCA4ABC         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT88                0xFFCA4AC4         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT89                0xFFCA4ACC         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT90                0xFFCA4AD4         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT91                0xFFCA4ADC         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT92                0xFFCA4AE4         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT93                0xFFCA4AEC         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT94                0xFFCA4AF4         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT95                0xFFCA4AFC         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT96                0xFFCA4B04         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT97                0xFFCA4B0C         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT98                0xFFCA4B14         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT99                0xFFCA4B1C         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT100               0xFFCA4B24         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT101               0xFFCA4B2C         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT102               0xFFCA4B34         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT103               0xFFCA4B3C         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT104               0xFFCA4B44         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT105               0xFFCA4B4C         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT106               0xFFCA4B54         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT107               0xFFCA4B5C         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT108               0xFFCA4B64         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT109               0xFFCA4B6C         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT110               0xFFCA4B74         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT111               0xFFCA4B7C         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT112               0xFFCA4B84         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT113               0xFFCA4B8C         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT114               0xFFCA4B94         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT115               0xFFCA4B9C         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT116               0xFFCA4BA4         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT117               0xFFCA4BAC         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT118               0xFFCA4BB4         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT119               0xFFCA4BBC         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT120               0xFFCA4BC4         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT121               0xFFCA4BCC         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT122               0xFFCA4BD4         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT123               0xFFCA4BDC         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT124               0xFFCA4BE4         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT125               0xFFCA4BEC         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT126               0xFFCA4BF4         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT127               0xFFCA4BFC         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT128               0xFFCA4C04         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT129               0xFFCA4C0C         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT130               0xFFCA4C14         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT131               0xFFCA4C1C         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT132               0xFFCA4C24         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT133               0xFFCA4C2C         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT134               0xFFCA4C34         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT135               0xFFCA4C3C         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT136               0xFFCA4C44         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT137               0xFFCA4C4C         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT138               0xFFCA4C54         /* SEC IRQ Source Status Register n */
+#define SEC_SSTAT139               0xFFCA4C5C         /* SEC IRQ Source Status Register n */
+/* ------------------------------------------------------------------------------------------------------------------------
+        SEC_CCTL                             Pos/Masks     Description
+   ------------------------------------------------------------------------------------------------------------------------ */
+#define SEC_CCTL_LOCK                   0x80000000    /* LOCK: Lock */
+#define SEC_CCTL_NMI_EN                 0x00010000    /* NMIEN: Enable */
+#define SEC_CCTL_WAITIDLE               0x00001000    /* WFI: Wait for Idle */
+#define SEC_CCTL_RESET                  0x00000002    /* RESET: Reset */
+#define SEC_CCTL_EN                     0x00000001    /* EN: Enable */
+/* ------------------------------------------------------------------------------------------------------------------------
+        SEC_CSTAT                            Pos/Masks     Description
+   ------------------------------------------------------------------------------------------------------------------------ */
+#define SEC_CSTAT_NMI                   0x00010000    /* NMI Status */
+#define SEC_CSTAT_WAITING               0x00001000    /* WFI: Waiting */
+#define SEC_CSTAT_VALID_SID             0x00000400    /* SIDV: Valid */
+#define SEC_CSTAT_VALID_ACT             0x00000200    /* ACTV: Valid */
+#define SEC_CSTAT_VALID_PND             0x00000100    /* PNDV: Valid */
+#define SEC_CSTAT_ERRC                  0x00000030    /* Error Cause */
+#define SEC_CSTAT_ACKERR                0x00000010    /* ERRC: Acknowledge Error */
+#define SEC_CSTAT_ERR                   0x00000002    /* ERR: Error Occurred */
+/* ------------------------------------------------------------------------------------------------------------------------
+        SEC_CPND                             Pos/Masks     Description
+   ------------------------------------------------------------------------------------------------------------------------ */
+#define SEC_CPND_PRIO                   0x0000FF00    /* Highest Pending IRQ Priority */
+#define SEC_CPND_SID                    0x000000FF    /* Highest Pending IRQ Source ID */
+/* ------------------------------------------------------------------------------------------------------------------------
+        SEC_CACT                             Pos/Masks     Description
+   ------------------------------------------------------------------------------------------------------------------------ */
+#define SEC_CACT_PRIO                   0x0000FF00    /* Highest Active IRQ Priority */
+#define SEC_CACT_SID                    0x000000FF    /* Highest Active IRQ Source ID */
+/* ------------------------------------------------------------------------------------------------------------------------
+        SEC_CPMSK                            Pos/Masks     Description
+   ------------------------------------------------------------------------------------------------------------------------ */
+#define SEC_CPMSK_LOCK                  0x80000000    /* LOCK: Lock */
+#define SEC_CPMSK_PRIO                  0x000000FF    /* IRQ Priority Mask */
+/* ------------------------------------------------------------------------------------------------------------------------
+        SEC_CGMSK                            Pos/Masks     Description
+   ------------------------------------------------------------------------------------------------------------------------ */
+#define SEC_CGMSK_LOCK                  0x80000000    /* LOCK: Lock */
+#define SEC_CGMSK_MASK                  0x00000100    /* UGRP: Mask Ungrouped Sources */
+#define SEC_CGMSK_GRP                   0x0000000F    /* Grouped Mask */
+/* ------------------------------------------------------------------------------------------------------------------------
+        SEC_CPLVL                            Pos/Masks     Description
+   ------------------------------------------------------------------------------------------------------------------------ */
+#define SEC_CPLVL_LOCK                  0x80000000    /* LOCK: Lock */
+#define SEC_CPLVL_PLVL                  0x00000007    /* Priority Levels */
+/* ------------------------------------------------------------------------------------------------------------------------
+        SEC_CSID                             Pos/Masks     Description
+   ------------------------------------------------------------------------------------------------------------------------ */
+#define SEC_CSID_SID                    0x000000FF    /* Source ID */
+/* ------------------------------------------------------------------------------------------------------------------------
+        SEC_FCTL                             Pos/Masks     Description
+   ------------------------------------------------------------------------------------------------------------------------ */
+#define SEC_FCTL_LOCK                   0x80000000    /* LOCK: Lock */
+#define SEC_FCTL_FLTPND_MODE            0x00002000    /* TES: Fault Pending Mode */
+#define SEC_FCTL_COP_MODE               0x00001000    /* CMS: COP Mode */
+#define SEC_FCTL_FLTIN_EN               0x00000080    /* FIEN: Enable */
+#define SEC_FCTL_SYSRST_EN              0x00000040    /* SREN: Enable */
+#define SEC_FCTL_TRGOUT_EN              0x00000020    /* TOEN: Enable */
+#define SEC_FCTL_FLTOUT_EN              0x00000010    /* FOEN: Enable */
+#define SEC_FCTL_RESET                  0x00000002    /* RESET: Reset */
+#define SEC_FCTL_EN                     0x00000001    /* EN: Enable */
+/* ------------------------------------------------------------------------------------------------------------------------
+        SEC_FSTAT                            Pos/Masks     Description
+   ------------------------------------------------------------------------------------------------------------------------ */
+#define SEC_FSTAT_NXTFLT                0x00000400    /* NPND: Pending */
+#define SEC_FSTAT_FLTACT                0x00000200    /* ACT: Active Fault */
+#define SEC_FSTAT_FLTPND                0x00000100    /* PND: Pending */
+#define SEC_FSTAT_ERRC                  0x00000030    /* Error Cause */
+#define SEC_FSTAT_ENDERR                0x00000020    /* ERRC: End Error */
+#define SEC_FSTAT_ERR                   0x00000002    /* ERR: Error Occurred */
+/* ------------------------------------------------------------------------------------------------------------------------
+        SEC_FSID                             Pos/Masks     Description
+   ------------------------------------------------------------------------------------------------------------------------ */
+#define SEC_FSID_SRC_EXTFLT             0x00010000    /* FEXT: Fault External */
+#define SEC_FSID_SID                    0x000000FF    /* Source ID */
+/* ------------------------------------------------------------------------------------------------------------------------
+        SEC_FEND                             Pos/Masks     Description
+   ------------------------------------------------------------------------------------------------------------------------ */
+#define SEC_FEND_END_EXTFLT             0x00010000    /* FEXT: Fault External */
+#define SEC_FEND_SID                    0x000000FF    /* Source ID */
+/* ------------------------------------------------------------------------------------------------------------------------
+        SEC_GCTL                             Pos/Masks     Description
+   ------------------------------------------------------------------------------------------------------------------------ */
+#define SEC_GCTL_LOCK                   0x80000000    /* Lock */
+#define SEC_GCTL_RESET                  0x00000002    /* Reset */
+#define SEC_GCTL_EN                     0x00000001    /* Enable */
+/* ------------------------------------------------------------------------------------------------------------------------
+        SEC_GSTAT                            Pos/Masks     Description
+   ------------------------------------------------------------------------------------------------------------------------ */
+#define SEC_GSTAT_LWERR                 0x80000000    /* LWERR: Error Occurred */
+#define SEC_GSTAT_ADRERR                0x40000000    /* ADRERR: Error Occurred */
+#define SEC_GSTAT_SID                   0x00FF0000    /* Source ID for SSI Error */
+#define SEC_GSTAT_SCI                   0x00000F00    /* SCI ID for SCI Error */
+#define SEC_GSTAT_ERRC                  0x00000030    /* Error Cause */
+#define SEC_GSTAT_SCIERR                0x00000010    /* ERRC: SCI Error */
+#define SEC_GSTAT_SSIERR                0x00000020    /* ERRC: SSI Error */
+#define SEC_GSTAT_ERR                   0x00000002    /* ERR: Error Occurred */
+/* ------------------------------------------------------------------------------------------------------------------------
+        SEC_RAISE                            Pos/Masks     Description
+   ------------------------------------------------------------------------------------------------------------------------ */
+#define SEC_RAISE_SID                   0x000000FF    /* Source ID IRQ Set to Pending */
+/* ------------------------------------------------------------------------------------------------------------------------
+        SEC_END                              Pos/Masks     Description
+   ------------------------------------------------------------------------------------------------------------------------ */
+#define SEC_END_SID                     0x000000FF    /* Source ID IRQ to End */
+/* ------------------------------------------------------------------------------------------------------------------------
+        SEC_SCTL                             Pos/Masks     Description
+   ------------------------------------------------------------------------------------------------------------------------ */
+#define SEC_SCTL_LOCK                   0x80000000    /* Lock */
+#define SEC_SCTL_CTG                    0x0F000000    /* Core Target Select */
+#define SEC_SCTL_GRP                    0x000F0000    /* Group Select */
+#define SEC_SCTL_PRIO                   0x0000FF00    /* Priority Level Select */
+#define SEC_SCTL_ERR_EN                 0x00000010    /* ERREN: Enable */
+#define SEC_SCTL_EDGE                   0x00000008    /* ES: Edge Sensitive */
+#define SEC_SCTL_SRC_EN                 0x00000004    /* SEN: Enable */
+#define SEC_SCTL_FAULT_EN               0x00000002    /* FEN: Enable */
+#define SEC_SCTL_INT_EN                 0x00000001    /* IEN: Enable */
+/* ------------------------------------------------------------------------------------------------------------------------
+        SEC_SSTAT                            Pos/Masks     Description
+   ------------------------------------------------------------------------------------------------------------------------ */
+#define SEC_SSTAT_CHID                  0x00FF0000    /* Channel ID */
+#define SEC_SSTAT_ACTIVE_SRC            0x00000200    /* ACT: Active Source */
+#define SEC_SSTAT_PENDING               0x00000100    /* PND: Pending */
+#define SEC_SSTAT_ERRC                  0x00000030    /* Error Cause */
+#define SEC_SSTAT_ENDERR                0x00000020    /* ERRC: End Error */
+#define SEC_SSTAT_ERR                   0x00000002    /* Error */
+/* =========================
+        RCU Registers
+   ========================= */
+/* =========================
+        RCU0
+   ========================= */
+#define RCU0_CTL                    0xFFCA6000         /* RCU0 Control Register */
+#define RCU0_STAT                   0xFFCA6004         /* RCU0 Status Register */
+#define RCU0_CRCTL                  0xFFCA6008         /* RCU0 Core Reset Control Register */
+#define RCU0_CRSTAT                 0xFFCA600C         /* RCU0 Core Reset Status Register */
+#define RCU0_SIDIS                  0xFFCA6010         /* RCU0 System Interface Disable Register */
+#define RCU0_SISTAT                 0xFFCA6014         /* RCU0 System Interface Status Register */
+#define RCU0_SVECT_LCK              0xFFCA6018         /* RCU0 SVECT Lock Register */
+#define RCU0_BCODE                  0xFFCA601C         /* RCU0 Boot Code Register */
+#define RCU0_SVECT0                 0xFFCA6020         /* RCU0 Software Vector Register n */
+#define RCU0_SVECT1                 0xFFCA6024         /* RCU0 Software Vector Register n */
+/* =========================
+        CGU0
+   ========================= */
+#define CGU0_CTL                    0xFFCA8000         /* CGU0 Control Register */
+#define CGU0_STAT                   0xFFCA8004         /* CGU0 Status Register */
+#define CGU0_DIV                    0xFFCA8008         /* CGU0 Divisor Register */
+#define CGU0_CLKOUTSEL              0xFFCA800C         /* CGU0 CLKOUT Select Register */
+/* =========================
+        DPM Registers
+   ========================= */
+/* =========================
+        DPM0
+   ========================= */
+#define DPM0_CTL                    0xFFCA9000         /* DPM0 Control Register */
+#define DPM0_STAT                   0xFFCA9004         /* DPM0 Status Register */
+#define DPM0_CCBF_DIS               0xFFCA9008         /* DPM0 Core Clock Buffer Disable Register */
+#define DPM0_CCBF_EN                0xFFCA900C         /* DPM0 Core Clock Buffer Enable Register */
+#define DPM0_CCBF_STAT              0xFFCA9010         /* DPM0 Core Clock Buffer Status Register */
+#define DPM0_CCBF_STAT_STKY         0xFFCA9014         /* DPM0 Core Clock Buffer Status Sticky Register */
+#define DPM0_SCBF_DIS               0xFFCA9018         /* DPM0 System Clock Buffer Disable Register */
+#define DPM0_WAKE_EN                0xFFCA901C         /* DPM0 Wakeup Enable Register */
+#define DPM0_WAKE_POL               0xFFCA9020         /* DPM0 Wakeup Polarity Register */
+#define DPM0_WAKE_STAT              0xFFCA9024         /* DPM0 Wakeup Status Register */
+#define DPM0_HIB_DIS                0xFFCA9028         /* DPM0 Hibernate Disable Register */
+#define DPM0_PGCNTR                 0xFFCA902C         /* DPM0 Power Good Counter Register */
+#define DPM0_RESTORE0               0xFFCA9030         /* DPM0 Restore Register */
+#define DPM0_RESTORE1               0xFFCA9034         /* DPM0 Restore Register */
+#define DPM0_RESTORE2               0xFFCA9038         /* DPM0 Restore Register */
+#define DPM0_RESTORE3               0xFFCA903C         /* DPM0 Restore Register */
+#define DPM0_RESTORE4               0xFFCA9040         /* DPM0 Restore Register */
+#define DPM0_RESTORE5               0xFFCA9044         /* DPM0 Restore Register */
+#define DPM0_RESTORE6               0xFFCA9048         /* DPM0 Restore Register */
+#define DPM0_RESTORE7               0xFFCA904C         /* DPM0 Restore Register */
+#define DPM0_RESTORE8               0xFFCA9050         /* DPM0 Restore Register */
+#define DPM0_RESTORE9               0xFFCA9054         /* DPM0 Restore Register */
+#define DPM0_RESTORE10              0xFFCA9058         /* DPM0 Restore Register */
+#define DPM0_RESTORE11              0xFFCA905C         /* DPM0 Restore Register */
+#define DPM0_RESTORE12              0xFFCA9060         /* DPM0 Restore Register */
+#define DPM0_RESTORE13              0xFFCA9064         /* DPM0 Restore Register */
+#define DPM0_RESTORE14              0xFFCA9068         /* DPM0 Restore Register */
+#define DPM0_RESTORE15              0xFFCA906C         /* DPM0 Restore Register */
+/* =========================
+        DBG Registers
+   ========================= */
+/* USB register */
+#define USB_FADDR                  0xFFCC1000         /* USB Device Address in Peripheral Mode */
+#define USB_POWER                  0xFFCC1001         /* USB Power and Device Control */
+#define USB_INTRTX                 0xFFCC1002         /* USB Transmit Interrupt */
+#define USB_INTRRX                 0xFFCC1004         /* USB Receive Interrupts */
+#define USB_INTRTXE                0xFFCC1006         /* USB Transmit Interrupt Enable */
+#define USB_INTRRXE                0xFFCC1008         /* USB Receive Interrupt Enable */
+#define USB_INTRUSB                    0xFFCC100A         /* USB USB Interrupts */
+#define USB_INTRUSBE                    0xFFCC100B         /* USB USB Interrupt Enable */
+#define USB_FRAME                  0xFFCC100C         /* USB Frame Number */
+#define USB_INDEX                  0xFFCC100E         /* USB Index */
+#define USB_TESTMODE               0xFFCC100F         /* USB Testmodes */
+#define USB_EPI_TXMAXP0            0xFFCC1010         /* USB Transmit Maximum Packet Length */
+#define USB_EP_NI0_TXMAXP          0xFFCC1010
+#define USB_EP0I_CSR0_H            0xFFCC1012         /* USB Config and Status EP0 */
+#define USB_EPI_TXCSR0_H           0xFFCC1012         /* USB Transmit Configuration and Status */
+#define USB_EP0I_CSR0_P            0xFFCC1012         /* USB Config and Status EP0 */
+#define USB_EPI_TXCSR0_P           0xFFCC1012         /* USB Transmit Configuration and Status */
+#define USB_EPI_RXMAXP0            0xFFCC1014         /* USB Receive Maximum Packet Length */
+#define USB_EPI_RXCSR0_H           0xFFCC1016         /* USB Receive Configuration and Status Register */
+#define USB_EPI_RXCSR0_P           0xFFCC1016         /* USB Receive Configuration and Status Register */
+#define USB_EP0I_CNT0              0xFFCC1018         /* USB Number of Received Bytes for Endpoint 0 */
+#define USB_EPI_RXCNT0             0xFFCC1018         /* USB Number of Byte Received */
+#define USB_EP0I_TYPE0             0xFFCC101A         /* USB Speed for Endpoint 0 */
+#define USB_EPI_TXTYPE0            0xFFCC101A         /* USB Transmit Type */
+#define USB_EP0I_NAKLIMIT0         0xFFCC101B         /* USB NAK Response Timeout for Endpoint 0 */
+#define USB_EPI_TXINTERVAL0        0xFFCC101B         /* USB Transmit Polling Interval */
+#define USB_EPI_RXTYPE0            0xFFCC101C         /* USB Receive Type */
+#define USB_EPI_RXINTERVAL0        0xFFCC101D         /* USB Receive Polling Interval */
+#define USB_EP0I_CFGDATA0          0xFFCC101F         /* USB Configuration Information */
+#define USB_FIFOB0                 0xFFCC1020         /* USB FIFO Data */
+#define USB_FIFOB1                 0xFFCC1024         /* USB FIFO Data */
+#define USB_FIFOB2                 0xFFCC1028         /* USB FIFO Data */
+#define USB_FIFOB3                 0xFFCC102C         /* USB FIFO Data */
+#define USB_FIFOB4                 0xFFCC1030         /* USB FIFO Data */
+#define USB_FIFOB5                 0xFFCC1034         /* USB FIFO Data */
+#define USB_FIFOB6                 0xFFCC1038         /* USB FIFO Data */
+#define USB_FIFOB7                 0xFFCC103C         /* USB FIFO Data */
+#define USB_FIFOB8                 0xFFCC1040         /* USB FIFO Data */
+#define USB_FIFOB9                 0xFFCC1044         /* USB FIFO Data */
+#define USB_FIFOB10                0xFFCC1048         /* USB FIFO Data */
+#define USB_FIFOB11                0xFFCC104C         /* USB FIFO Data */
+#define USB_FIFOH0                 0xFFCC1020         /* USB FIFO Data */
+#define USB_FIFOH1                 0xFFCC1024         /* USB FIFO Data */
+#define USB_FIFOH2                 0xFFCC1028         /* USB FIFO Data */
+#define USB_FIFOH3                 0xFFCC102C         /* USB FIFO Data */
+#define USB_FIFOH4                 0xFFCC1030         /* USB FIFO Data */
+#define USB_FIFOH5                 0xFFCC1034         /* USB FIFO Data */
+#define USB_FIFOH6                 0xFFCC1038         /* USB FIFO Data */
+#define USB_FIFOH7                 0xFFCC103C         /* USB FIFO Data */
+#define USB_FIFOH8                 0xFFCC1040         /* USB FIFO Data */
+#define USB_FIFOH9                 0xFFCC1044         /* USB FIFO Data */
+#define USB_FIFOH10                0xFFCC1048         /* USB FIFO Data */
+#define USB_FIFOH11                0xFFCC104C         /* USB FIFO Data */
+#define USB_FIFO0                  0xFFCC1020         /* USB FIFO Data */
+#define USB_EP0_FIFO               0xFFCC1020
+#define USB_FIFO1                  0xFFCC1024         /* USB FIFO Data */
+#define USB_FIFO2                  0xFFCC1028         /* USB FIFO Data */
+#define USB_FIFO3                  0xFFCC102C         /* USB FIFO Data */
+#define USB_FIFO4                  0xFFCC1030         /* USB FIFO Data */
+#define USB_FIFO5                  0xFFCC1034         /* USB FIFO Data */
+#define USB_FIFO6                  0xFFCC1038         /* USB FIFO Data */
+#define USB_FIFO7                  0xFFCC103C         /* USB FIFO Data */
+#define USB_FIFO8                  0xFFCC1040         /* USB FIFO Data */
+#define USB_FIFO9                  0xFFCC1044         /* USB FIFO Data */
+#define USB_FIFO10                 0xFFCC1048         /* USB FIFO Data */
+#define USB_FIFO11                 0xFFCC104C         /* USB FIFO Data */
+#define USB_OTG_DEV_CTL                0xFFCC1060         /* USB Device Control */
+#define USB_TXFIFOSZ               0xFFCC1062         /* USB Transmit FIFO Size */
+#define USB_RXFIFOSZ               0xFFCC1063         /* USB Receive FIFO Size */
+#define USB_TXFIFOADDR             0xFFCC1064         /* USB Transmit FIFO Address */
+#define USB_RXFIFOADDR             0xFFCC1066         /* USB Receive FIFO Address */
+#define USB_VENDSTAT               0xFFCC1068         /* USB Vendor Status */
+#define USB_HWVERS                 0xFFCC106C         /* USB Hardware Version */
+#define USB_EPINFO                 0xFFCC1078         /* USB Endpoint Info */
+#define USB_RAMINFO                0xFFCC1079         /* USB Ram Information */
+#define USB_LINKINFO               0xFFCC107A         /* USB Programmable Delay Values */
+#define USB_VPLEN                  0xFFCC107B         /* USB VBus Pulse Duration */
+#define USB_HS_EOF1                0xFFCC107C         /* USB High Speed End of Frame Remaining */
+#define USB_FS_EOF1                0xFFCC107D         /* USB Full Speed End of Frame Remaining */
+#define USB_LS_EOF1                0xFFCC107E         /* USB Low Speed End of Frame Remaining */
+#define USB_SOFT_RST               0xFFCC107F         /* USB Software Reset */
+#define USB_TXFUNCADDR0            0xFFCC1080         /* USB Transmit Function Address */
+#define USB_TXFUNCADDR1            0xFFCC1088         /* USB Transmit Function Address */
+#define USB_TXFUNCADDR2            0xFFCC1090         /* USB Transmit Function Address */
+#define USB_TXFUNCADDR3            0xFFCC1098         /* USB Transmit Function Address */
+#define USB_TXFUNCADDR4            0xFFCC10A0         /* USB Transmit Function Address */
+#define USB_TXFUNCADDR5            0xFFCC10A8         /* USB Transmit Function Address */
+#define USB_TXFUNCADDR6            0xFFCC10B0         /* USB Transmit Function Address */
+#define USB_TXFUNCADDR7            0xFFCC10B8         /* USB Transmit Function Address */
+#define USB_TXFUNCADDR8            0xFFCC10C0         /* USB Transmit Function Address */
+#define USB_TXFUNCADDR9            0xFFCC10C8         /* USB Transmit Function Address */
+#define USB_TXFUNCADDR10           0xFFCC10D0         /* USB Transmit Function Address */
+#define USB_TXFUNCADDR11           0xFFCC10D8         /* USB Transmit Function Address */
+#define USB_TXHUBADDR0             0xFFCC1082         /* USB Transmit Hub Address */
+#define USB_TXHUBADDR1             0xFFCC108A         /* USB Transmit Hub Address */
+#define USB_TXHUBADDR2             0xFFCC1092         /* USB Transmit Hub Address */
+#define USB_TXHUBADDR3             0xFFCC109A         /* USB Transmit Hub Address */
+#define USB_TXHUBADDR4             0xFFCC10A2         /* USB Transmit Hub Address */
+#define USB_TXHUBADDR5             0xFFCC10AA         /* USB Transmit Hub Address */
+#define USB_TXHUBADDR6             0xFFCC10B2         /* USB Transmit Hub Address */
+#define USB_TXHUBADDR7             0xFFCC10BA         /* USB Transmit Hub Address */
+#define USB_TXHUBADDR8             0xFFCC10C2         /* USB Transmit Hub Address */
+#define USB_TXHUBADDR9             0xFFCC10CA         /* USB Transmit Hub Address */
+#define USB_TXHUBADDR10            0xFFCC10D2         /* USB Transmit Hub Address */
+#define USB_TXHUBADDR11            0xFFCC10DA         /* USB Transmit Hub Address */
+#define USB_TXHUBPORT0             0xFFCC1083         /* USB Transmit Hub Port */
+#define USB_TXHUBPORT1             0xFFCC108B         /* USB Transmit Hub Port */
+#define USB_TXHUBPORT2             0xFFCC1093         /* USB Transmit Hub Port */
+#define USB_TXHUBPORT3             0xFFCC109B         /* USB Transmit Hub Port */
+#define USB_TXHUBPORT4             0xFFCC10A3         /* USB Transmit Hub Port */
+#define USB_TXHUBPORT5             0xFFCC10AB         /* USB Transmit Hub Port */
+#define USB_TXHUBPORT6             0xFFCC10B3         /* USB Transmit Hub Port */
+#define USB_TXHUBPORT7             0xFFCC10BB         /* USB Transmit Hub Port */
+#define USB_TXHUBPORT8             0xFFCC10C3         /* USB Transmit Hub Port */
+#define USB_TXHUBPORT9             0xFFCC10CB         /* USB Transmit Hub Port */
+#define USB_TXHUBPORT10            0xFFCC10D3         /* USB Transmit Hub Port */
+#define USB_TXHUBPORT11            0xFFCC10DB         /* USB Transmit Hub Port */
+#define USB_RXFUNCADDR0            0xFFCC1084         /* USB Receive Function Address */
+#define USB_RXFUNCADDR1            0xFFCC108C         /* USB Receive Function Address */
+#define USB_RXFUNCADDR2            0xFFCC1094         /* USB Receive Function Address */
+#define USB_RXFUNCADDR3            0xFFCC109C         /* USB Receive Function Address */
+#define USB_RXFUNCADDR4            0xFFCC10A4         /* USB Receive Function Address */
+#define USB_RXFUNCADDR5            0xFFCC10AC         /* USB Receive Function Address */
+#define USB_RXFUNCADDR6            0xFFCC10B4         /* USB Receive Function Address */
+#define USB_RXFUNCADDR7            0xFFCC10BC         /* USB Receive Function Address */
+#define USB_RXFUNCADDR8            0xFFCC10C4         /* USB Receive Function Address */
+#define USB_RXFUNCADDR9            0xFFCC10CC         /* USB Receive Function Address */
+#define USB_RXFUNCADDR10           0xFFCC10D4         /* USB Receive Function Address */
+#define USB_RXFUNCADDR11           0xFFCC10DC         /* USB Receive Function Address */
+#define USB_RXHUBADDR0             0xFFCC1086         /* USB Receive Hub Address */
+#define USB_RXHUBADDR1             0xFFCC108E         /* USB Receive Hub Address */
+#define USB_RXHUBADDR2             0xFFCC1096         /* USB Receive Hub Address */
+#define USB_RXHUBADDR3             0xFFCC109E         /* USB Receive Hub Address */
+#define USB_RXHUBADDR4             0xFFCC10A6         /* USB Receive Hub Address */
+#define USB_RXHUBADDR5             0xFFCC10AE         /* USB Receive Hub Address */
+#define USB_RXHUBADDR6             0xFFCC10B6         /* USB Receive Hub Address */
+#define USB_RXHUBADDR7             0xFFCC10BE         /* USB Receive Hub Address */
+#define USB_RXHUBADDR8             0xFFCC10C6         /* USB Receive Hub Address */
+#define USB_RXHUBADDR9             0xFFCC10CE         /* USB Receive Hub Address */
+#define USB_RXHUBADDR10            0xFFCC10D6         /* USB Receive Hub Address */
+#define USB_RXHUBADDR11            0xFFCC10DE         /* USB Receive Hub Address */
+#define USB_RXHUBPORT0             0xFFCC1087         /* USB Receive Hub Port */
+#define USB_RXHUBPORT1             0xFFCC108F         /* USB Receive Hub Port */
+#define USB_RXHUBPORT2             0xFFCC1097         /* USB Receive Hub Port */
+#define USB_RXHUBPORT3             0xFFCC109F         /* USB Receive Hub Port */
+#define USB_RXHUBPORT4             0xFFCC10A7         /* USB Receive Hub Port */
+#define USB_RXHUBPORT5             0xFFCC10AF         /* USB Receive Hub Port */
+#define USB_RXHUBPORT6             0xFFCC10B7         /* USB Receive Hub Port */
+#define USB_RXHUBPORT7             0xFFCC10BF         /* USB Receive Hub Port */
+#define USB_RXHUBPORT8             0xFFCC10C7         /* USB Receive Hub Port */
+#define USB_RXHUBPORT9             0xFFCC10CF         /* USB Receive Hub Port */
+#define USB_RXHUBPORT10            0xFFCC10D7         /* USB Receive Hub Port */
+#define USB_RXHUBPORT11            0xFFCC10DF         /* USB Receive Hub Port */
+#define USB_EP0_CSR0_H             0xFFCC1102         /* USB Config and Status EP0 */
+#define USB_EP0_CSR0_P             0xFFCC1102         /* USB Config and Status EP0 */
+#define USB_EP0_CNT0               0xFFCC1108         /* USB Number of Received Bytes for Endpoint 0 */
+#define USB_EP0_TYPE0              0xFFCC110A         /* USB Speed for Endpoint 0 */
+#define USB_EP0_NAKLIMIT0          0xFFCC110B         /* USB NAK Response Timeout for Endpoint 0 */
+#define USB_EP0_CFGDATA0           0xFFCC110F         /* USB Configuration Information */
+#define USB_EP_TXMAXP0             0xFFCC1110         /* USB Transmit Maximum Packet Length */
+#define USB_EP_TXMAXP1             0xFFCC1120         /* USB Transmit Maximum Packet Length */
+#define USB_EP_TXMAXP2             0xFFCC1130         /* USB Transmit Maximum Packet Length */
+#define USB_EP_TXMAXP3             0xFFCC1140         /* USB Transmit Maximum Packet Length */
+#define USB_EP_TXMAXP4             0xFFCC1150         /* USB Transmit Maximum Packet Length */
+#define USB_EP_TXMAXP5             0xFFCC1160         /* USB Transmit Maximum Packet Length */
+#define USB_EP_TXMAXP6             0xFFCC1170         /* USB Transmit Maximum Packet Length */
+#define USB_EP_TXMAXP7             0xFFCC1180         /* USB Transmit Maximum Packet Length */
+#define USB_EP_TXMAXP8             0xFFCC1190         /* USB Transmit Maximum Packet Length */
+#define USB_EP_TXMAXP9             0xFFCC11A0         /* USB Transmit Maximum Packet Length */
+#define USB_EP_TXMAXP10            0xFFCC11B0         /* USB Transmit Maximum Packet Length */
+#define USB_EP_TXCSR0_H            0xFFCC1112         /* USB Transmit Configuration and Status */
+#define USB_EP_TXCSR1_H            0xFFCC1122         /* USB Transmit Configuration and Status */
+#define USB_EP_TXCSR2_H            0xFFCC1132         /* USB Transmit Configuration and Status */
+#define USB_EP_TXCSR3_H            0xFFCC1142         /* USB Transmit Configuration and Status */
+#define USB_EP_TXCSR4_H            0xFFCC1152         /* USB Transmit Configuration and Status */
+#define USB_EP_TXCSR5_H            0xFFCC1162         /* USB Transmit Configuration and Status */
+#define USB_EP_TXCSR6_H            0xFFCC1172         /* USB Transmit Configuration and Status */
+#define USB_EP_TXCSR7_H            0xFFCC1182         /* USB Transmit Configuration and Status */
+#define USB_EP_TXCSR8_H            0xFFCC1192         /* USB Transmit Configuration and Status */
+#define USB_EP_TXCSR9_H            0xFFCC11A2         /* USB Transmit Configuration and Status */
+#define USB_EP_TXCSR10_H           0xFFCC11B2         /* USB Transmit Configuration and Status */
+#define USB_EP_TXCSR0_P            0xFFCC1112         /* USB Transmit Configuration and Status */
+#define USB_EP_TXCSR1_P            0xFFCC1122         /* USB Transmit Configuration and Status */
+#define USB_EP_TXCSR2_P            0xFFCC1132         /* USB Transmit Configuration and Status */
+#define USB_EP_TXCSR3_P            0xFFCC1142         /* USB Transmit Configuration and Status */
+#define USB_EP_TXCSR4_P            0xFFCC1152         /* USB Transmit Configuration and Status */
+#define USB_EP_TXCSR5_P            0xFFCC1162         /* USB Transmit Configuration and Status */
+#define USB_EP_TXCSR6_P            0xFFCC1172         /* USB Transmit Configuration and Status */
+#define USB_EP_TXCSR7_P            0xFFCC1182         /* USB Transmit Configuration and Status */
+#define USB_EP_TXCSR8_P            0xFFCC1192         /* USB Transmit Configuration and Status */
+#define USB_EP_TXCSR9_P            0xFFCC11A2         /* USB Transmit Configuration and Status */
+#define USB_EP_TXCSR10_P           0xFFCC11B2         /* USB Transmit Configuration and Status */
+#define USB_EP_RXMAXP0             0xFFCC1114         /* USB Receive Maximum Packet Length */
+#define USB_EP_RXMAXP1             0xFFCC1124         /* USB Receive Maximum Packet Length */
+#define USB_EP_RXMAXP2             0xFFCC1134         /* USB Receive Maximum Packet Length */
+#define USB_EP_RXMAXP3             0xFFCC1144         /* USB Receive Maximum Packet Length */
+#define USB_EP_RXMAXP4             0xFFCC1154         /* USB Receive Maximum Packet Length */
+#define USB_EP_RXMAXP5             0xFFCC1164         /* USB Receive Maximum Packet Length */
+#define USB_EP_RXMAXP6             0xFFCC1174         /* USB Receive Maximum Packet Length */
+#define USB_EP_RXMAXP7             0xFFCC1184         /* USB Receive Maximum Packet Length */
+#define USB_EP_RXMAXP8             0xFFCC1194         /* USB Receive Maximum Packet Length */
+#define USB_EP_RXMAXP9             0xFFCC11A4         /* USB Receive Maximum Packet Length */
+#define USB_EP_RXMAXP10            0xFFCC11B4         /* USB Receive Maximum Packet Length */
+#define USB_EP_RXCSR0_H            0xFFCC1116         /* USB Receive Configuration and Status Register */
+#define USB_EP_RXCSR1_H            0xFFCC1126         /* USB Receive Configuration and Status Register */
+#define USB_EP_RXCSR2_H            0xFFCC1136         /* USB Receive Configuration and Status Register */
+#define USB_EP_RXCSR3_H            0xFFCC1146         /* USB Receive Configuration and Status Register */
+#define USB_EP_RXCSR4_H            0xFFCC1156         /* USB Receive Configuration and Status Register */
+#define USB_EP_RXCSR5_H            0xFFCC1166         /* USB Receive Configuration and Status Register */
+#define USB_EP_RXCSR6_H            0xFFCC1176         /* USB Receive Configuration and Status Register */
+#define USB_EP_RXCSR7_H            0xFFCC1186         /* USB Receive Configuration and Status Register */
+#define USB_EP_RXCSR8_H            0xFFCC1196         /* USB Receive Configuration and Status Register */
+#define USB_EP_RXCSR9_H            0xFFCC11A6         /* USB Receive Configuration and Status Register */
+#define USB_EP_RXCSR10_H           0xFFCC11B6         /* USB Receive Configuration and Status Register */
+#define USB_EP_RXCSR0_P            0xFFCC1116         /* USB Receive Configuration and Status Register */
+#define USB_EP_RXCSR1_P            0xFFCC1126         /* USB Receive Configuration and Status Register */
+#define USB_EP_RXCSR2_P            0xFFCC1136         /* USB Receive Configuration and Status Register */
+#define USB_EP_RXCSR3_P            0xFFCC1146         /* USB Receive Configuration and Status Register */
+#define USB_EP_RXCSR4_P            0xFFCC1156         /* USB Receive Configuration and Status Register */
+#define USB_EP_RXCSR5_P            0xFFCC1166         /* USB Receive Configuration and Status Register */
+#define USB_EP_RXCSR6_P            0xFFCC1176         /* USB Receive Configuration and Status Register */
+#define USB_EP_RXCSR7_P            0xFFCC1186         /* USB Receive Configuration and Status Register */
+#define USB_EP_RXCSR8_P            0xFFCC1196         /* USB Receive Configuration and Status Register */
+#define USB_EP_RXCSR9_P            0xFFCC11A6         /* USB Receive Configuration and Status Register */
+#define USB_EP_RXCSR10_P           0xFFCC11B6         /* USB Receive Configuration and Status Register */
+#define USB_EP_RXCNT0              0xFFCC1118         /* USB Number of Byte Received */
+#define USB_EP_RXCNT1              0xFFCC1128         /* USB Number of Byte Received */
+#define USB_EP_RXCNT2              0xFFCC1138         /* USB Number of Byte Received */
+#define USB_EP_RXCNT3              0xFFCC1148         /* USB Number of Byte Received */
+#define USB_EP_RXCNT4              0xFFCC1158         /* USB Number of Byte Received */
+#define USB_EP_RXCNT5              0xFFCC1168         /* USB Number of Byte Received */
+#define USB_EP_RXCNT6              0xFFCC1178         /* USB Number of Byte Received */
+#define USB_EP_RXCNT7              0xFFCC1188         /* USB Number of Byte Received */
+#define USB_EP_RXCNT8              0xFFCC1198         /* USB Number of Byte Received */
+#define USB_EP_RXCNT9              0xFFCC11A8         /* USB Number of Byte Received */
+#define USB_EP_RXCNT10             0xFFCC11B8         /* USB Number of Byte Received */
+#define USB_EP_TXTYPE0             0xFFCC111A         /* USB Transmit Type */
+#define USB_EP_TXTYPE1             0xFFCC112A         /* USB Transmit Type */
+#define USB_EP_TXTYPE2             0xFFCC113A         /* USB Transmit Type */
+#define USB_EP_TXTYPE3             0xFFCC114A         /* USB Transmit Type */
+#define USB_EP_TXTYPE4             0xFFCC115A         /* USB Transmit Type */
+#define USB_EP_TXTYPE5             0xFFCC116A         /* USB Transmit Type */
+#define USB_EP_TXTYPE6             0xFFCC117A         /* USB Transmit Type */
+#define USB_EP_TXTYPE7             0xFFCC118A         /* USB Transmit Type */
+#define USB_EP_TXTYPE8             0xFFCC119A         /* USB Transmit Type */
+#define USB_EP_TXTYPE9             0xFFCC11AA         /* USB Transmit Type */
+#define USB_EP_TXTYPE10            0xFFCC11BA         /* USB Transmit Type */
+#define USB_EP_TXINTERVAL0         0xFFCC111B         /* USB Transmit Polling Interval */
+#define USB_EP_TXINTERVAL1         0xFFCC112B         /* USB Transmit Polling Interval */
+#define USB_EP_TXINTERVAL2         0xFFCC113B         /* USB Transmit Polling Interval */
+#define USB_EP_TXINTERVAL3         0xFFCC114B         /* USB Transmit Polling Interval */
+#define USB_EP_TXINTERVAL4         0xFFCC115B         /* USB Transmit Polling Interval */
+#define USB_EP_TXINTERVAL5         0xFFCC116B         /* USB Transmit Polling Interval */
+#define USB_EP_TXINTERVAL6         0xFFCC117B         /* USB Transmit Polling Interval */
+#define USB_EP_TXINTERVAL7         0xFFCC118B         /* USB Transmit Polling Interval */
+#define USB_EP_TXINTERVAL8         0xFFCC119B         /* USB Transmit Polling Interval */
+#define USB_EP_TXINTERVAL9         0xFFCC11AB         /* USB Transmit Polling Interval */
+#define USB_EP_TXINTERVAL10        0xFFCC11BB         /* USB Transmit Polling Interval */
+#define USB_EP_RXTYPE0             0xFFCC111C         /* USB Receive Type */
+#define USB_EP_RXTYPE1             0xFFCC112C         /* USB Receive Type */
+#define USB_EP_RXTYPE2             0xFFCC113C         /* USB Receive Type */
+#define USB_EP_RXTYPE3             0xFFCC114C         /* USB Receive Type */
+#define USB_EP_RXTYPE4             0xFFCC115C         /* USB Receive Type */
+#define USB_EP_RXTYPE5             0xFFCC116C         /* USB Receive Type */
+#define USB_EP_RXTYPE6             0xFFCC117C         /* USB Receive Type */
+#define USB_EP_RXTYPE7             0xFFCC118C         /* USB Receive Type */
+#define USB_EP_RXTYPE8             0xFFCC119C         /* USB Receive Type */
+#define USB_EP_RXTYPE9             0xFFCC11AC         /* USB Receive Type */
+#define USB_EP_RXTYPE10            0xFFCC11BC         /* USB Receive Type */
+#define USB_EP_RXINTERVAL0         0xFFCC111D         /* USB Receive Polling Interval */
+#define USB_EP_RXINTERVAL1         0xFFCC112D         /* USB Receive Polling Interval */
+#define USB_EP_RXINTERVAL2         0xFFCC113D         /* USB Receive Polling Interval */
+#define USB_EP_RXINTERVAL3         0xFFCC114D         /* USB Receive Polling Interval */
+#define USB_EP_RXINTERVAL4         0xFFCC115D         /* USB Receive Polling Interval */
+#define USB_EP_RXINTERVAL5         0xFFCC116D         /* USB Receive Polling Interval */
+#define USB_EP_RXINTERVAL6         0xFFCC117D         /* USB Receive Polling Interval */
+#define USB_EP_RXINTERVAL7         0xFFCC118D         /* USB Receive Polling Interval */
+#define USB_EP_RXINTERVAL8         0xFFCC119D         /* USB Receive Polling Interval */
+#define USB_EP_RXINTERVAL9         0xFFCC11AD         /* USB Receive Polling Interval */
+#define USB_EP_RXINTERVAL10        0xFFCC11BD         /* USB Receive Polling Interval */
+#define USB_DMA_IRQ                0xFFCC1200         /* USB Interrupt Register */
+#define USB_DMA_CTL0               0xFFCC1204         /* USB DMA Control */
+#define USB_DMA_CTL1               0xFFCC1214         /* USB DMA Control */
+#define USB_DMA_CTL2               0xFFCC1224         /* USB DMA Control */
+#define USB_DMA_CTL3               0xFFCC1234         /* USB DMA Control */
+#define USB_DMA_CTL4               0xFFCC1244         /* USB DMA Control */
+#define USB_DMA_CTL5               0xFFCC1254         /* USB DMA Control */
+#define USB_DMA_CTL6               0xFFCC1264         /* USB DMA Control */
+#define USB_DMA_CTL7               0xFFCC1274         /* USB DMA Control */
+#define USB_DMA_ADDR0              0xFFCC1208         /* USB DMA Address */
+#define USB_DMA_ADDR1              0xFFCC1218         /* USB DMA Address */
+#define USB_DMA_ADDR2              0xFFCC1228         /* USB DMA Address */
+#define USB_DMA_ADDR3              0xFFCC1238         /* USB DMA Address */
+#define USB_DMA_ADDR4              0xFFCC1248         /* USB DMA Address */
+#define USB_DMA_ADDR5              0xFFCC1258         /* USB DMA Address */
+#define USB_DMA_ADDR6              0xFFCC1268         /* USB DMA Address */
+#define USB_DMA_ADDR7              0xFFCC1278         /* USB DMA Address */
+#define USB_DMA_CNT0               0xFFCC120C         /* USB DMA Count */
+#define USB_DMA_CNT1               0xFFCC121C         /* USB DMA Count */
+#define USB_DMA_CNT2               0xFFCC122C         /* USB DMA Count */
+#define USB_DMA_CNT3               0xFFCC123C         /* USB DMA Count */
+#define USB_DMA_CNT4               0xFFCC124C         /* USB DMA Count */
+#define USB_DMA_CNT5               0xFFCC125C         /* USB DMA Count */
+#define USB_DMA_CNT6               0xFFCC126C         /* USB DMA Count */
+#define USB_DMA_CNT7               0xFFCC127C         /* USB DMA Count */
+#define USB_RQPKTCNT0              0xFFCC1300         /* USB Request Packet Count */
+#define USB_RQPKTCNT1              0xFFCC1304         /* USB Request Packet Count */
+#define USB_RQPKTCNT2              0xFFCC1308         /* USB Request Packet Count */
+#define USB_RQPKTCNT3              0xFFCC130C         /* USB Request Packet Count */
+#define USB_RQPKTCNT4              0xFFCC1310         /* USB Request Packet Count */
+#define USB_RQPKTCNT5              0xFFCC1314         /* USB Request Packet Count */
+#define USB_RQPKTCNT6              0xFFCC1318         /* USB Request Packet Count */
+#define USB_RQPKTCNT7              0xFFCC131C         /* USB Request Packet Count */
+#define USB_RQPKTCNT8              0xFFCC1320         /* USB Request Packet Count */
+#define USB_RQPKTCNT9              0xFFCC1324         /* USB Request Packet Count */
+#define USB_RQPKTCNT10             0xFFCC1328         /* USB Request Packet Count */
+#define USB_CT_UCH                 0xFFCC1344         /* USB Chirp Timeout */
+#define USB_CT_HHSRTN              0xFFCC1346         /* USB High Speed Resume Return to Normal */
+#define USB_CT_HSBT                0xFFCC1348         /* USB High Speed Timeout */
+#define USB_LPM_ATTR               0xFFCC1360         /* USB LPM Attribute */
+#define USB_LPM_CTL                0xFFCC1362         /* USB LPM Control */
+#define USB_LPM_IEN                0xFFCC1363         /* USB LPM Interrupt Enable */
+#define USB_LPM_IRQ                0xFFCC1364         /* USB LPM Interrupt */
+#define USB_LPM_FADDR              0xFFCC1365         /* USB LPM Function Address */
+#define USB_VBUS_CTL               0xFFCC1380         /* USB VBus Control */
+#define USB_BAT_CHG                0xFFCC1381         /* USB Battery Charging */
+#define USB_PHY_CTL                0xFFCC1394         /* USB PHY Control */
+#define USB_TESTCTL                0xFFCC1397         /* USB Test Control */
+#define USB_PLL_OSC                0xFFCC1398         /* USB PLL and Oscillator Control */
+/* =========================
+        CHIPID
+   ========================= */
+#define                           CHIPID  0xffc00014
+/* CHIPID Masks */
+#define                   CHIPID_VERSION  0xF0000000
+#define                    CHIPID_FAMILY  0x0FFFF000
+#define               CHIPID_MANUFACTURE  0x00000FFE
+#endif /* _DEF_BF60X_H */
diff --git a/arch/blackfin/mach-bf609/include/mach/dma.h b/arch/blackfin/mach-bf609/include/mach/dma.h
new file mode 100644
index 000000000000..872d141ca119
--- /dev/null
+++ b/arch/blackfin/mach-bf609/include/mach/dma.h
@@ -0,0 +1,116 @@
+/* mach/dma.h - arch-specific DMA defines
+ *
+ * Copyright 2011 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+#ifndef _MACH_DMA_H_
+#define _MACH_DMA_H_
+#define CH_SPORT0_TX                   0
+#define CH_SPORT0_RX                   1
+#define CH_SPORT1_TX                   2
+#define CH_SPORT1_RX                   3
+#define CH_SPORT2_TX                   4
+#define CH_SPORT2_RX                   5
+#define CH_SPI0_TX                     6
+#define CH_SPI0_RX                     7
+#define CH_SPI1_TX                     8
+#define CH_SPI1_RX                     9
+#define CH_RSI                        10
+#define CH_SDU                        11
+#define CH_LP0                        13
+#define CH_LP1                        14
+#define CH_LP2                        15
+#define CH_LP3                        16
+#define CH_UART0_TX                   17
+#define CH_UART0_RX                   18
+#define CH_UART1_TX                   19
+#define CH_UART1_RX                   20
+#define CH_MEM_STREAM0_SRC_CRC0      21
+#define CH_MEM_STREAM0_SRC           CH_MEM_STREAM0_SRC_CRC0
+#define CH_MEM_STREAM0_DEST_CRC0     22
+#define CH_MEM_STREAM0_DEST          CH_MEM_STREAM0_DEST_CRC0
+#define CH_MEM_STREAM1_SRC_CRC1      23
+#define CH_MEM_STREAM1_SRC           CH_MEM_STREAM1_SRC_CRC1
+#define CH_MEM_STREAM1_DEST_CRC1     24
+#define CH_MEM_STREAM1_DEST          CH_MEM_STREAM1_DEST_CRC1
+#define CH_MEM_STREAM2_SRC           25
+#define CH_MEM_STREAM2_DEST          26
+#define CH_MEM_STREAM3_SRC           27
+#define CH_MEM_STREAM3_DEST          28
+#define CH_EPPI0_CH0                  29
+#define CH_EPPI0_CH1                  30
+#define CH_EPPI1_CH0                  31
+#define CH_EPPI1_CH1                  32
+#define CH_EPPI2_CH0                  33
+#define CH_EPPI2_CH1                  34
+#define CH_PIXC_CH0                   35
+#define CH_PIXC_CH1                   36
+#define CH_PIXC_CH2                   37
+#define CH_PVP_CPDOB                  38
+#define CH_PVP_CPDOC                  39
+#define CH_PVP_CPSTAT                 40
+#define CH_PVP_CPCI                   41
+#define CH_PVP_MPDO                   42
+#define CH_PVP_MPDI                   43
+#define CH_PVP_MPSTAT                 44
+#define CH_PVP_MPCI                   45
+#define CH_PVP_CPDOA                  46
+#define MAX_DMA_CHANNELS 47
+#define MAX_DMA_SUSPEND_CHANNELS 0
+#define DMA_MMR_SIZE_32
+#define bfin_read_MDMA_S0_CONFIG bfin_read_MDMA0_SRC_CRC0_CONFIG
+#define bfin_write_MDMA_S0_CONFIG bfin_write_MDMA0_SRC_CRC0_CONFIG
+#define bfin_read_MDMA_S0_IRQ_STATUS bfin_read_MDMA0_SRC_CRC0_IRQ_STATUS
+#define bfin_write_MDMA_S0_IRQ_STATUS bfin_write_MDMA0_SRC_CRC0_IRQ_STATUS
+#define bfin_write_MDMA_S0_START_ADDR bfin_write_MDMA0_SRC_CRC0_START_ADDR
+#define bfin_write_MDMA_S0_X_COUNT bfin_write_MDMA0_SRC_CRC0_X_COUNT
+#define bfin_write_MDMA_S0_X_MODIFY bfin_write_MDMA0_SRC_CRC0_X_MODIFY
+#define bfin_write_MDMA_S0_Y_COUNT bfin_write_MDMA0_SRC_CRC0_Y_COUNT
+#define bfin_write_MDMA_S0_Y_MODIFY bfin_write_MDMA0_SRC_CRC0_Y_MODIFY
+#define bfin_read_MDMA_D0_CONFIG bfin_read_MDMA0_DEST_CRC0_CONFIG
+#define bfin_write_MDMA_D0_CONFIG bfin_write_MDMA0_DEST_CRC0_CONFIG
+#define bfin_read_MDMA_D0_IRQ_STATUS bfin_read_MDMA0_DEST_CRC0_IRQ_STATUS
+#define bfin_write_MDMA_D0_IRQ_STATUS bfin_write_MDMA0_DEST_CRC0_IRQ_STATUS
+#define bfin_write_MDMA_D0_START_ADDR bfin_write_MDMA0_DEST_CRC0_START_ADDR
+#define bfin_write_MDMA_D0_X_COUNT bfin_write_MDMA0_DEST_CRC0_X_COUNT
+#define bfin_write_MDMA_D0_X_MODIFY bfin_write_MDMA0_DEST_CRC0_X_MODIFY
+#define bfin_write_MDMA_D0_Y_COUNT bfin_write_MDMA0_DEST_CRC0_Y_COUNT
+#define bfin_write_MDMA_D0_Y_MODIFY bfin_write_MDMA0_DEST_CRC0_Y_MODIFY
+#define bfin_read_MDMA_S1_CONFIG bfin_read_MDMA1_SRC_CRC1_CONFIG
+#define bfin_write_MDMA_S1_CONFIG bfin_write_MDMA1_SRC_CRC1_CONFIG
+#define bfin_read_MDMA_D1_CONFIG bfin_read_MDMA1_DEST_CRC1_CONFIG
+#define bfin_write_MDMA_D1_CONFIG bfin_write_MDMA1_DEST_CRC1_CONFIG
+#define bfin_read_MDMA_D1_IRQ_STATUS bfin_read_MDMA1_DEST_CRC1_IRQ_STATUS
+#define bfin_write_MDMA_D1_IRQ_STATUS bfin_write_MDMA1_DEST_CRC1_IRQ_STATUS
+#define bfin_read_MDMA_S3_CONFIG bfin_read_MDMA3_SRC_CONFIG
+#define bfin_write_MDMA_S3_CONFIG bfin_write_MDMA3_SRC_CONFIG
+#define bfin_read_MDMA_S3_IRQ_STATUS bfin_read_MDMA3_SRC_IRQ_STATUS
+#define bfin_write_MDMA_S3_IRQ_STATUS bfin_write_MDMA3_SRC_IRQ_STATUS
+#define bfin_write_MDMA_S3_START_ADDR bfin_write_MDMA3_SRC_START_ADDR
+#define bfin_write_MDMA_S3_X_COUNT bfin_write_MDMA3_SRC_X_COUNT
+#define bfin_write_MDMA_S3_X_MODIFY bfin_write_MDMA3_SRC_X_MODIFY
+#define bfin_write_MDMA_S3_Y_COUNT bfin_write_MDMA3_SRC_Y_COUNT
+#define bfin_write_MDMA_S3_Y_MODIFY bfin_write_MDMA3_SRC_Y_MODIFY
+#define bfin_read_MDMA_D3_CONFIG bfin_read_MDMA3_DEST_CONFIG
+#define bfin_write_MDMA_D3_CONFIG bfin_write_MDMA3_DEST_CONFIG
+#define bfin_read_MDMA_D3_IRQ_STATUS bfin_read_MDMA3_DEST_IRQ_STATUS
+#define bfin_write_MDMA_D3_IRQ_STATUS bfin_write_MDMA3_DEST_IRQ_STATUS
+#define bfin_write_MDMA_D3_START_ADDR bfin_write_MDMA3_DEST_START_ADDR
+#define bfin_write_MDMA_D3_X_COUNT bfin_write_MDMA3_DEST_X_COUNT
+#define bfin_write_MDMA_D3_X_MODIFY bfin_write_MDMA3_DEST_X_MODIFY
+#define bfin_write_MDMA_D3_Y_COUNT bfin_write_MDMA3_DEST_Y_COUNT
+#define bfin_write_MDMA_D3_Y_MODIFY bfin_write_MDMA3_DEST_Y_MODIFY
+#define MDMA_S0_NEXT_DESC_PTR MDMA0_SRC_CRC0_NEXT_DESC_PTR
+#define MDMA_D0_NEXT_DESC_PTR MDMA0_DEST_CRC0_NEXT_DESC_PTR
+#define MDMA_S1_NEXT_DESC_PTR MDMA1_SRC_CRC1_NEXT_DESC_PTR
+#define MDMA_D1_NEXT_DESC_PTR MDMA1_DEST_CRC1_NEXT_DESC_PTR
+#endif
diff --git a/arch/blackfin/mach-bf609/include/mach/gpio.h b/arch/blackfin/mach-bf609/include/mach/gpio.h
new file mode 100644
index 000000000000..127586b1e04a
--- /dev/null
+++ b/arch/blackfin/mach-bf609/include/mach/gpio.h
@@ -0,0 +1,171 @@
+/*
+ * Copyright 2007-2009 Analog Devices Inc.
+ * Licensed under the GPL-2 or later.
+ */
+#ifndef _MACH_GPIO_H_
+#define _MACH_GPIO_H_
+#define MAX_BLACKFIN_GPIOS 112
+#define GPIO_PA0        0
+#define GPIO_PA1        1
+#define GPIO_PA2        2
+#define GPIO_PA3        3
+#define GPIO_PA4        4
+#define GPIO_PA5        5
+#define GPIO_PA6        6
+#define GPIO_PA7        7
+#define GPIO_PA8        8
+#define GPIO_PA9        9
+#define GPIO_PA10       10
+#define GPIO_PA11       11
+#define GPIO_PA12       12
+#define GPIO_PA13       13
+#define GPIO_PA14       14
+#define GPIO_PA15       15
+#define GPIO_PB0        16
+#define GPIO_PB1        17
+#define GPIO_PB2        18
+#define GPIO_PB3        19
+#define GPIO_PB4        20
+#define GPIO_PB5        21
+#define GPIO_PB6        22
+#define GPIO_PB7        23
+#define GPIO_PB8        24
+#define GPIO_PB9        25
+#define GPIO_PB10       26
+#define GPIO_PB11       27
+#define GPIO_PB12       28
+#define GPIO_PB13       29
+#define GPIO_PB14       30
+#define GPIO_PB15       31
+#define GPIO_PC0        32
+#define GPIO_PC1        33
+#define GPIO_PC2        34
+#define GPIO_PC3        35
+#define GPIO_PC4        36
+#define GPIO_PC5        37
+#define GPIO_PC6        38
+#define GPIO_PC7        39
+#define GPIO_PC8        40
+#define GPIO_PC9        41
+#define GPIO_PC10       42
+#define GPIO_PC11       43
+#define GPIO_PC12       44
+#define GPIO_PC13       45
+#define GPIO_PC14       46
+#define GPIO_PC15       47
+#define GPIO_PD0        48
+#define GPIO_PD1        49
+#define GPIO_PD2        50
+#define GPIO_PD3        51
+#define GPIO_PD4        52
+#define GPIO_PD5        53
+#define GPIO_PD6        54
+#define GPIO_PD7        55
+#define GPIO_PD8        56
+#define GPIO_PD9        57
+#define GPIO_PD10       58
+#define GPIO_PD11       59
+#define GPIO_PD12       60
+#define GPIO_PD13       61
+#define GPIO_PD14       62
+#define GPIO_PD15       63
+#define GPIO_PE0        64
+#define GPIO_PE1        65
+#define GPIO_PE2        66
+#define GPIO_PE3        67
+#define GPIO_PE4        68
+#define GPIO_PE5        69
+#define GPIO_PE6        70
+#define GPIO_PE7        71
+#define GPIO_PE8        72
+#define GPIO_PE9        73
+#define GPIO_PE10       74
+#define GPIO_PE11       75
+#define GPIO_PE12       76
+#define GPIO_PE13       77
+#define GPIO_PE14       78
+#define GPIO_PE15       79
+#define GPIO_PF0        80
+#define GPIO_PF1        81
+#define GPIO_PF2        82
+#define GPIO_PF3        83
+#define GPIO_PF4        84
+#define GPIO_PF5        85
+#define GPIO_PF6        86
+#define GPIO_PF7        87
+#define GPIO_PF8        88
+#define GPIO_PF9        89
+#define GPIO_PF10       90
+#define GPIO_PF11       91
+#define GPIO_PF12       92
+#define GPIO_PF13       93
+#define GPIO_PF14       94
+#define GPIO_PF15       95
+#define GPIO_PG0        96
+#define GPIO_PG1        97
+#define GPIO_PG2        98
+#define GPIO_PG3        99
+#define GPIO_PG4        100
+#define GPIO_PG5        101
+#define GPIO_PG6        102
+#define GPIO_PG7        103
+#define GPIO_PG8        104
+#define GPIO_PG9        105
+#define GPIO_PG10       106
+#define GPIO_PG11       107
+#define GPIO_PG12       108
+#define GPIO_PG13       109
+#define GPIO_PG14       110
+#define GPIO_PG15       111
+#define BFIN_GPIO_PINT 1
+#ifndef __ASSEMBLY__
+struct gpio_port_t {
+        unsigned long port_fer;
+        unsigned long port_fer_set;
+        unsigned long port_fer_clear;
+        unsigned long data;
+        unsigned long data_set;
+        unsigned long data_clear;
+        unsigned long dir;
+        unsigned long dir_set;
+        unsigned long dir_clear;
+        unsigned long inen;
+        unsigned long inen_set;
+        unsigned long inen_clear;
+        unsigned long port_mux;
+        unsigned long toggle;
+        unsigned long polar;
+        unsigned long polar_set;
+        unsigned long polar_clear;
+        unsigned long lock;
+        unsigned long spare;
+        unsigned long revid;
+};
+struct gpio_port_s {
+        unsigned short fer;
+        unsigned short data;
+        unsigned short dir;
+        unsigned short inen;
+        unsigned int mux;
+};
+#endif
+#include <mach-common/ports-a.h>
+#include <mach-common/ports-b.h>
+#include <mach-common/ports-c.h>
+#include <mach-common/ports-d.h>
+#include <mach-common/ports-e.h>
+#include <mach-common/ports-f.h>
+#include <mach-common/ports-g.h>
+#endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/mach-bf609/include/mach/irq.h b/arch/blackfin/mach-bf609/include/mach/irq.h
new file mode 100644
index 000000000000..0004552433b2
--- /dev/null
+++ b/arch/blackfin/mach-bf609/include/mach/irq.h
@@ -0,0 +1,318 @@
+/*
+ * Copyright 2011 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+#ifndef _BF60x_IRQ_H_
+#define _BF60x_IRQ_H_
+#include <mach-common/irq.h>
+#undef BFIN_IRQ
+#define BFIN_IRQ(x) ((x) + IVG15)
+#define NR_PERI_INTS            (5 * 32)
+#define IRQ_SEC_ERR             BFIN_IRQ(0)     /* SEC Error */
+#define IRQ_CGU_EVT             BFIN_IRQ(1)     /* CGU Event */
+#define IRQ_WATCH0              BFIN_IRQ(2)     /* Watchdog0 Interrupt */
+#define IRQ_WATCH1              BFIN_IRQ(3)     /* Watchdog1 Interrupt */
+#define IRQ_L2CTL0_ECC_ERR      BFIN_IRQ(4)     /* L2 ECC Error */
+#define IRQ_L2CTL0_ECC_WARN     BFIN_IRQ(5)     /* L2 ECC Waring */
+#define IRQ_C0_DBL_FAULT        BFIN_IRQ(6)     /* Core 0 Double Fault */
+#define IRQ_C1_DBL_FAULT        BFIN_IRQ(7)     /* Core 1 Double Fault */
+#define IRQ_C0_HW_ERR           BFIN_IRQ(8)     /* Core 0 Hardware Error */
+#define IRQ_C1_HW_ERR           BFIN_IRQ(9)     /* Core 1 Hardware Error */
+#define IRQ_C0_NMI_L1_PARITY_ERR        BFIN_IRQ(10)    /* Core 0 Unhandled NMI or L1 Memory Parity Error */
+#define IRQ_C1_NMI_L1_PARITY_ERR        BFIN_IRQ(11)    /* Core 1 Unhandled NMI or L1 Memory Parity Error */
+#define CORE_IRQS               (IRQ_C1_NMI_L1_PARITY_ERR + 1)
+#define IRQ_TIMER0              BFIN_IRQ(12)    /* Timer 0 Interrupt */
+#define IRQ_TIMER1              BFIN_IRQ(13)    /* Timer 1 Interrupt */
+#define IRQ_TIMER2              BFIN_IRQ(14)    /* Timer 2 Interrupt */
+#define IRQ_TIMER3              BFIN_IRQ(15)    /* Timer 3 Interrupt */
+#define IRQ_TIMER4              BFIN_IRQ(16)    /* Timer 4 Interrupt */
+#define IRQ_TIMER5              BFIN_IRQ(17)    /* Timer 5 Interrupt */
+#define IRQ_TIMER6              BFIN_IRQ(18)    /* Timer 6 Interrupt */
+#define IRQ_TIMER7              BFIN_IRQ(19)    /* Timer 7 Interrupt */
+#define IRQ_TIMER_STAT          BFIN_IRQ(20)    /* Timer Block Status */
+#define IRQ_PINT0               BFIN_IRQ(21)    /* PINT0 Interrupt */
+#define IRQ_PINT1               BFIN_IRQ(22)    /* PINT1 Interrupt */
+#define IRQ_PINT2               BFIN_IRQ(23)    /* PINT2 Interrupt */
+#define IRQ_PINT3               BFIN_IRQ(24)    /* PINT3 Interrupt */
+#define IRQ_PINT4               BFIN_IRQ(25)    /* PINT4 Interrupt */
+#define IRQ_PINT5               BFIN_IRQ(26)    /* PINT5 Interrupt */
+#define IRQ_CNT                 BFIN_IRQ(27)    /* CNT Interrupt */
+#define IRQ_PWM0_TRIP           BFIN_IRQ(28)    /* PWM0 Trip Interrupt */
+#define IRQ_PWM0_SYNC           BFIN_IRQ(29)    /* PWM0 Sync Interrupt */
+#define IRQ_PWM1_TRIP           BFIN_IRQ(30)    /* PWM1 Trip Interrupt */
+#define IRQ_PWM1_SYNC           BFIN_IRQ(31)    /* PWM1 Sync Interrupt */
+#define IRQ_TWI0                BFIN_IRQ(32)    /* TWI0 Interrupt */
+#define IRQ_TWI1                BFIN_IRQ(33)    /* TWI1 Interrupt */
+#define IRQ_SOFT0               BFIN_IRQ(34)    /* Software-Driven Interrupt 0 */
+#define IRQ_SOFT1               BFIN_IRQ(35)    /* Software-Driven Interrupt 1 */
+#define IRQ_SOFT2               BFIN_IRQ(36)    /* Software-Driven Interrupt 2 */
+#define IRQ_SOFT3               BFIN_IRQ(37)    /* Software-Driven Interrupt 3 */
+#define IRQ_ACM_EVT_MISS        BFIN_IRQ(38)    /* ACM Event Miss */
+#define IRQ_ACM_EVT_COMPLETE    BFIN_IRQ(39)    /* ACM Event Complete */
+#define IRQ_CAN0_RX             BFIN_IRQ(40)    /* CAN0 Receive Interrupt */
+#define IRQ_CAN0_TX             BFIN_IRQ(41)    /* CAN0 Transmit Interrupt */
+#define IRQ_CAN0_STAT           BFIN_IRQ(42)    /* CAN0 Status */
+#define IRQ_SPORT0_TX           BFIN_IRQ(43)    /* SPORT0 TX Interrupt (DMA0) */
+#define IRQ_SPORT0_TX_STAT      BFIN_IRQ(44)    /* SPORT0 TX Status Interrupt */
+#define IRQ_SPORT0_RX           BFIN_IRQ(45)    /* SPORT0 RX Interrupt (DMA1) */
+#define IRQ_SPORT0_RX_STAT      BFIN_IRQ(46)    /* SPORT0 RX Status Interrupt */
+#define IRQ_SPORT1_TX           BFIN_IRQ(47)    /* SPORT1 TX Interrupt (DMA2) */
+#define IRQ_SPORT1_TX_STAT      BFIN_IRQ(48)    /* SPORT1 TX Status Interrupt */
+#define IRQ_SPORT1_RX           BFIN_IRQ(49)    /* SPORT1 RX Interrupt (DMA3) */
+#define IRQ_SPORT1_RX_STAT      BFIN_IRQ(50)    /* SPORT1 RX Status Interrupt */
+#define IRQ_SPORT2_TX           BFIN_IRQ(51)    /* SPORT2 TX Interrupt (DMA4) */
+#define IRQ_SPORT2_TX_STAT      BFIN_IRQ(52)    /* SPORT2 TX Status Interrupt */
+#define IRQ_SPORT2_RX           BFIN_IRQ(53)    /* SPORT2 RX Interrupt (DMA5) */
+#define IRQ_SPORT2_RX_STAT      BFIN_IRQ(54)    /* SPORT2 RX Status Interrupt */
+#define IRQ_SPI0_TX             BFIN_IRQ(55)    /* SPI0 TX Interrupt (DMA6) */
+#define IRQ_SPI0_RX             BFIN_IRQ(56)    /* SPI0 RX Interrupt (DMA7) */
+#define IRQ_SPI0_STAT           BFIN_IRQ(57)    /* SPI0 Status Interrupt */
+#define IRQ_SPI1_TX             BFIN_IRQ(58)    /* SPI1 TX Interrupt (DMA8) */
+#define IRQ_SPI1_RX             BFIN_IRQ(59)    /* SPI1 RX Interrupt (DMA9) */
+#define IRQ_SPI1_STAT           BFIN_IRQ(60)    /* SPI1 Status Interrupt */
+#define IRQ_RSI                 BFIN_IRQ(61)    /* RSI (DMA10) Interrupt */
+#define IRQ_RSI_INT0            BFIN_IRQ(62)    /* RSI Interrupt0 */
+#define IRQ_RSI_INT1            BFIN_IRQ(63)    /* RSI Interrupt1 */
+#define IRQ_SDU                 BFIN_IRQ(64)    /* DMA11 Data (SDU) */
+/*       -- RESERVED --             65             DMA12 Data (Reserved) */
+/*       -- RESERVED --             66             Reserved */
+/*       -- RESERVED --             67             Reserved */
+#define IRQ_EMAC0_STAT          BFIN_IRQ(68)    /* EMAC0 Status */
+/*       -- RESERVED --             69             EMAC0 Power (Reserved) */
+#define IRQ_EMAC1_STAT          BFIN_IRQ(70)    /* EMAC1 Status */
+/*       -- RESERVED --             71             EMAC1 Power (Reserved) */
+#define IRQ_LP0                 BFIN_IRQ(72)    /* DMA13 Data (Link Port 0) */
+#define IRQ_LP0_STAT            BFIN_IRQ(73)    /* Link Port 0 Status */
+#define IRQ_LP1                 BFIN_IRQ(74)    /* DMA14 Data (Link Port 1) */
+#define IRQ_LP1_STAT            BFIN_IRQ(75)    /* Link Port 1 Status */
+#define IRQ_LP2                 BFIN_IRQ(76)    /* DMA15 Data (Link Port 2) */
+#define IRQ_LP2_STAT            BFIN_IRQ(77)    /* Link Port 2 Status */
+#define IRQ_LP3                 BFIN_IRQ(78)    /* DMA16 Data(Link Port 3) */
+#define IRQ_LP3_STAT            BFIN_IRQ(79)    /* Link Port 3 Status */
+#define IRQ_UART0_TX            BFIN_IRQ(80)    /* UART0 TX Interrupt (DMA17) */
+#define IRQ_UART0_RX            BFIN_IRQ(81)    /* UART0 RX Interrupt (DMA18) */
+#define IRQ_UART0_STAT          BFIN_IRQ(82)    /* UART0 Status(Error) Interrupt */
+#define IRQ_UART1_TX            BFIN_IRQ(83)    /* UART1 TX Interrupt (DMA19) */
+#define IRQ_UART1_RX            BFIN_IRQ(84)    /* UART1 RX Interrupt (DMA20) */
+#define IRQ_UART1_STAT          BFIN_IRQ(85)    /* UART1 Status(Error) Interrupt */
+#define IRQ_MDMA0_SRC_CRC0      BFIN_IRQ(86)    /* DMA21 Data (MDMA Stream 0 Source/CRC0 Input Channel) */
+#define IRQ_MDMA0_DEST_CRC0     BFIN_IRQ(87)    /* DMA22 Data (MDMA Stream 0 Destination/CRC0 Output Channel) */
+#define IRQ_MDMAS0              IRQ_MDMA0_DEST_CRC0
+#define IRQ_CRC0_DCNTEXP        BFIN_IRQ(88)    /* CRC0 DATACOUNT Expiration */
+#define IRQ_CRC0_ERR            BFIN_IRQ(89)    /* CRC0 Error */
+#define IRQ_MDMA1_SRC_CRC1      BFIN_IRQ(90)    /* DMA23 Data (MDMA Stream 1 Source/CRC1 Input Channel) */
+#define IRQ_MDMA1_DEST_CRC1     BFIN_IRQ(91)    /* DMA24 Data (MDMA Stream 1 Destination/CRC1 Output Channel) */
+#define IRQ_MDMAS1              IRQ_MDMA1_DEST_CRC1
+#define IRQ_CRC1_DCNTEXP        BFIN_IRQ(92)    /* CRC1 DATACOUNT Expiration */
+#define IRQ_CRC1_ERR            BFIN_IRQ(93)    /* CRC1 Error */
+#define IRQ_MDMA2_SRC           BFIN_IRQ(94)    /* DMA25 Data (MDMA Stream 2 Source Channel) */
+#define IRQ_MDMA2_DEST          BFIN_IRQ(95)    /* DMA26 Data (MDMA Stream 2 Destination Channel) */
+#define IRQ_MDMAS2              IRQ_MDMA2_DEST
+#define IRQ_MDMA3_SRC           BFIN_IRQ(96)    /* DMA27 Data (MDMA Stream 3 Source Channel) */
+#define IRQ_MDMA3_DEST          BFIN_IRQ(97)    /* DMA28 Data (MDMA Stream 3 Destination Channel) */
+#define IRQ_MDMAS3              IRQ_MDMA3_DEST
+#define IRQ_EPPI0_CH0           BFIN_IRQ(98)    /* DMA29 Data (EPPI0 Channel 0) */
+#define IRQ_EPPI0_CH1           BFIN_IRQ(99)    /* DMA30 Data (EPPI0 Channel 1) */
+#define IRQ_EPPI0_STAT          BFIN_IRQ(100)   /* EPPI0 Status */
+#define IRQ_EPPI2_CH0           BFIN_IRQ(101)   /* DMA31 Data (EPPI2 Channel 0) */
+#define IRQ_EPPI2_CH1           BFIN_IRQ(102)   /* DMA32 Data (EPPI2 Channel 1) */
+#define IRQ_EPPI2_STAT          BFIN_IRQ(103)   /* EPPI2 Status */
+#define IRQ_EPPI1_CH0           BFIN_IRQ(104)   /* DMA33 Data (EPPI1 Channel 0) */
+#define IRQ_EPPI1_CH1           BFIN_IRQ(105)   /* DMA34 Data (EPPI1 Channel 1) */
+#define IRQ_EPPI1_STAT          BFIN_IRQ(106)   /* EPPI1 Status */
+#define IRQ_PIXC_CH0            BFIN_IRQ(107)   /* DMA35 Data (PIXC Channel 0) */
+#define IRQ_PIXC_CH1            BFIN_IRQ(108)   /* DMA36 Data (PIXC Channel 1) */
+#define IRQ_PIXC_CH2            BFIN_IRQ(109)   /* DMA37 Data (PIXC Channel 2) */
+#define IRQ_PIXC_STAT           BFIN_IRQ(110)   /* PIXC Status */
+#define IRQ_PVP_CPDOB           BFIN_IRQ(111)   /* DMA38 Data (PVP0 Camera Pipe Data Out B) */
+#define IRQ_PVP_CPDOC           BFIN_IRQ(112)   /* DMA39 Data (PVP0 Camera Pipe Data Out C) */
+#define IRQ_PVP_CPSTAT          BFIN_IRQ(113)   /* DMA40 Data (PVP0 Camera Pipe Status Out) */
+#define IRQ_PVP_CPCI            BFIN_IRQ(114)   /* DMA41 Data (PVP0 Camera Pipe Control In) */
+#define IRQ_PVP_STAT0           BFIN_IRQ(115)   /* PVP0 Status 0 */
+#define IRQ_PVP_MPDO            BFIN_IRQ(116)   /* DMA42 Data (PVP0 Memory Pipe Data Out) */
+#define IRQ_PVP_MPDI            BFIN_IRQ(117)   /* DMA43 Data (PVP0 Memory Pipe Data In) */
+#define IRQ_PVP_MPSTAT          BFIN_IRQ(118)   /* DMA44 Data (PVP0 Memory Pipe Status Out) */
+#define IRQ_PVP_MPCI            BFIN_IRQ(119)   /* DMA45 Data (PVP0 Memory Pipe Control In) */
+#define IRQ_PVP_CPDOA           BFIN_IRQ(120)   /* DMA46 Data (PVP0 Camera Pipe Data Out A) */
+#define IRQ_PVP_STAT1           BFIN_IRQ(121)   /* PVP0 Status 1 */
+#define IRQ_USB_STAT            BFIN_IRQ(122)   /* USB Status Interrupt */
+#define IRQ_USB_DMA             BFIN_IRQ(123)   /* USB DMA Interrupt */
+#define IRQ_TRU_INT0            BFIN_IRQ(124)   /* TRU0 Interrupt 0 */
+#define IRQ_TRU_INT1            BFIN_IRQ(125)   /* TRU0 Interrupt 1 */
+#define IRQ_TRU_INT2            BFIN_IRQ(126)   /* TRU0 Interrupt 2 */
+#define IRQ_TRU_INT3            BFIN_IRQ(127)   /* TRU0 Interrupt 3 */
+#define IRQ_DMAC0_ERROR         BFIN_IRQ(128)   /* DMAC0 Status Interrupt */
+#define IRQ_CGU0_ERROR          BFIN_IRQ(129)   /* CGU0 Error */
+/*       -- RESERVED --             130            Reserved */
+#define IRQ_DPM                 BFIN_IRQ(131)   /* DPM0 Event */
+/*       -- RESERVED --             132            Reserved */
+#define IRQ_SWU0                BFIN_IRQ(133)   /* SWU0 */
+#define IRQ_SWU1                BFIN_IRQ(134)   /* SWU1 */
+#define IRQ_SWU2                BFIN_IRQ(135)   /* SWU2 */
+#define IRQ_SWU3                BFIN_IRQ(136)   /* SWU3 */
+#define IRQ_SWU4                BFIN_IRQ(137)   /* SWU4 */
+#define IRQ_SWU5                BFIN_IRQ(138)   /* SWU5 */
+#define IRQ_SWU6                BFIN_IRQ(139)   /* SWU6 */
+#define SYS_IRQS                IRQ_SWU6
+#define BFIN_PA_IRQ(x)          ((x) + SYS_IRQS + 1)
+#define IRQ_PA0                 BFIN_PA_IRQ(0)
+#define IRQ_PA1                 BFIN_PA_IRQ(1)
+#define IRQ_PA2                 BFIN_PA_IRQ(2)
+#define IRQ_PA3                 BFIN_PA_IRQ(3)
+#define IRQ_PA4                 BFIN_PA_IRQ(4)
+#define IRQ_PA5                 BFIN_PA_IRQ(5)
+#define IRQ_PA6                 BFIN_PA_IRQ(6)
+#define IRQ_PA7                 BFIN_PA_IRQ(7)
+#define IRQ_PA8                 BFIN_PA_IRQ(8)
+#define IRQ_PA9                 BFIN_PA_IRQ(9)
+#define IRQ_PA10                BFIN_PA_IRQ(10)
+#define IRQ_PA11                BFIN_PA_IRQ(11)
+#define IRQ_PA12                BFIN_PA_IRQ(12)
+#define IRQ_PA13                BFIN_PA_IRQ(13)
+#define IRQ_PA14                BFIN_PA_IRQ(14)
+#define IRQ_PA15                BFIN_PA_IRQ(15)
+#define BFIN_PB_IRQ(x)          ((x) + IRQ_PA15 + 1)
+#define IRQ_PB0                 BFIN_PB_IRQ(0)
+#define IRQ_PB1                 BFIN_PB_IRQ(1)
+#define IRQ_PB2                 BFIN_PB_IRQ(2)
+#define IRQ_PB3                 BFIN_PB_IRQ(3)
+#define IRQ_PB4                 BFIN_PB_IRQ(4)
+#define IRQ_PB5                 BFIN_PB_IRQ(5)
+#define IRQ_PB6                 BFIN_PB_IRQ(6)
+#define IRQ_PB7                 BFIN_PB_IRQ(7)
+#define IRQ_PB8                 BFIN_PB_IRQ(8)
+#define IRQ_PB9                 BFIN_PB_IRQ(9)
+#define IRQ_PB10                BFIN_PB_IRQ(10)
+#define IRQ_PB11                BFIN_PB_IRQ(11)
+#define IRQ_PB12                BFIN_PB_IRQ(12)
+#define IRQ_PB13                BFIN_PB_IRQ(13)
+#define IRQ_PB14                BFIN_PB_IRQ(14)
+#define IRQ_PB15                BFIN_PB_IRQ(15)         /* N/A */
+#define BFIN_PC_IRQ(x)          ((x) + IRQ_PB15 + 1)
+#define IRQ_PC0                 BFIN_PC_IRQ(0)
+#define IRQ_PC1                 BFIN_PC_IRQ(1)
+#define IRQ_PC2                 BFIN_PC_IRQ(2)
+#define IRQ_PC3                 BFIN_PC_IRQ(3)
+#define IRQ_PC4                 BFIN_PC_IRQ(4)
+#define IRQ_PC5                 BFIN_PC_IRQ(5)
+#define IRQ_PC6                 BFIN_PC_IRQ(6)
+#define IRQ_PC7                 BFIN_PC_IRQ(7)
+#define IRQ_PC8                 BFIN_PC_IRQ(8)
+#define IRQ_PC9                 BFIN_PC_IRQ(9)
+#define IRQ_PC10                BFIN_PC_IRQ(10)
+#define IRQ_PC11                BFIN_PC_IRQ(11)
+#define IRQ_PC12                BFIN_PC_IRQ(12)
+#define IRQ_PC13                BFIN_PC_IRQ(13)
+#define IRQ_PC14                BFIN_PC_IRQ(14)         /* N/A */
+#define IRQ_PC15                BFIN_PC_IRQ(15)         /* N/A */
+#define BFIN_PD_IRQ(x)          ((x) + IRQ_PC15 + 1)
+#define IRQ_PD0                 BFIN_PD_IRQ(0)
+#define IRQ_PD1                 BFIN_PD_IRQ(1)
+#define IRQ_PD2                 BFIN_PD_IRQ(2)
+#define IRQ_PD3                 BFIN_PD_IRQ(3)
+#define IRQ_PD4                 BFIN_PD_IRQ(4)
+#define IRQ_PD5                 BFIN_PD_IRQ(5)
+#define IRQ_PD6                 BFIN_PD_IRQ(6)
+#define IRQ_PD7                 BFIN_PD_IRQ(7)
+#define IRQ_PD8                 BFIN_PD_IRQ(8)
+#define IRQ_PD9                 BFIN_PD_IRQ(9)
+#define IRQ_PD10                BFIN_PD_IRQ(10)
+#define IRQ_PD11                BFIN_PD_IRQ(11)
+#define IRQ_PD12                BFIN_PD_IRQ(12)
+#define IRQ_PD13                BFIN_PD_IRQ(13)
+#define IRQ_PD14                BFIN_PD_IRQ(14)
+#define IRQ_PD15                BFIN_PD_IRQ(15)
+#define BFIN_PE_IRQ(x)          ((x) + IRQ_PD15 + 1)
+#define IRQ_PE0                 BFIN_PE_IRQ(0)
+#define IRQ_PE1                 BFIN_PE_IRQ(1)
+#define IRQ_PE2                 BFIN_PE_IRQ(2)
+#define IRQ_PE3                 BFIN_PE_IRQ(3)
+#define IRQ_PE4                 BFIN_PE_IRQ(4)
+#define IRQ_PE5                 BFIN_PE_IRQ(5)
+#define IRQ_PE6                 BFIN_PE_IRQ(6)
+#define IRQ_PE7                 BFIN_PE_IRQ(7)
+#define IRQ_PE8                 BFIN_PE_IRQ(8)
+#define IRQ_PE9                 BFIN_PE_IRQ(9)
+#define IRQ_PE10                BFIN_PE_IRQ(10)
+#define IRQ_PE11                BFIN_PE_IRQ(11)
+#define IRQ_PE12                BFIN_PE_IRQ(12)
+#define IRQ_PE13                BFIN_PE_IRQ(13)
+#define IRQ_PE14                BFIN_PE_IRQ(14)
+#define IRQ_PE15                BFIN_PE_IRQ(15)
+#define BFIN_PF_IRQ(x)          ((x) + IRQ_PE15 + 1)
+#define IRQ_PF0                 BFIN_PF_IRQ(0)
+#define IRQ_PF1                 BFIN_PF_IRQ(1)
+#define IRQ_PF2                 BFIN_PF_IRQ(2)
+#define IRQ_PF3                 BFIN_PF_IRQ(3)
+#define IRQ_PF4                 BFIN_PF_IRQ(4)
+#define IRQ_PF5                 BFIN_PF_IRQ(5)
+#define IRQ_PF6                 BFIN_PF_IRQ(6)
+#define IRQ_PF7                 BFIN_PF_IRQ(7)
+#define IRQ_PF8                 BFIN_PF_IRQ(8)
+#define IRQ_PF9                 BFIN_PF_IRQ(9)
+#define IRQ_PF10                BFIN_PF_IRQ(10)
+#define IRQ_PF11                BFIN_PF_IRQ(11)
+#define IRQ_PF12                BFIN_PF_IRQ(12)
+#define IRQ_PF13                BFIN_PF_IRQ(13)
+#define IRQ_PF14                BFIN_PF_IRQ(14)
+#define IRQ_PF15                BFIN_PF_IRQ(15)
+#define BFIN_PG_IRQ(x)          ((x) + IRQ_PF15 + 1)
+#define IRQ_PG0                 BFIN_PG_IRQ(0)
+#define IRQ_PG1                 BFIN_PG_IRQ(1)
+#define IRQ_PG2                 BFIN_PG_IRQ(2)
+#define IRQ_PG3                 BFIN_PG_IRQ(3)
+#define IRQ_PG4                 BFIN_PG_IRQ(4)
+#define IRQ_PG5                 BFIN_PG_IRQ(5)
+#define IRQ_PG6                 BFIN_PG_IRQ(6)
+#define IRQ_PG7                 BFIN_PG_IRQ(7)
+#define IRQ_PG8                 BFIN_PG_IRQ(8)
+#define IRQ_PG9                 BFIN_PG_IRQ(9)
+#define IRQ_PG10                BFIN_PG_IRQ(10)
+#define IRQ_PG11                BFIN_PG_IRQ(11)
+#define IRQ_PG12                BFIN_PG_IRQ(12)
+#define IRQ_PG13                BFIN_PG_IRQ(13)
+#define IRQ_PG14                BFIN_PG_IRQ(14)
+#define IRQ_PG15                BFIN_PG_IRQ(15)
+#define GPIO_IRQ_BASE           IRQ_PA0
+#define NR_MACH_IRQS            (IRQ_PG15 + 1)
+#ifndef __ASSEMBLY__
+#include <linux/types.h>
+/*
+ * bfin pint registers layout
+ */
+struct bfin_pint_regs {
+        u32 mask_set;
+        u32 mask_clear;
+        u32 request;
+        u32 assign;
+        u32 edge_set;
+        u32 edge_clear;
+        u32 invert_set;
+        u32 invert_clear;
+        u32 pinstate;
+        u32 latch;
+        u32 __pad0[2];
+};
+#endif
+#endif
diff --git a/arch/blackfin/mach-bf609/include/mach/mem_map.h b/arch/blackfin/mach-bf609/include/mach/mem_map.h
new file mode 100644
index 000000000000..20b65bfc5311
--- /dev/null
+++ b/arch/blackfin/mach-bf609/include/mach/mem_map.h
@@ -0,0 +1,86 @@
+/*
+ * BF60x memory map
+ *
+ * Copyright 2011 Analog Devices Inc.
+ * Licensed under the GPL-2 or later.
+ */
+#ifndef __BFIN_MACH_MEM_MAP_H__
+#define __BFIN_MACH_MEM_MAP_H__
+#ifndef __BFIN_MEM_MAP_H__
+# error "do not include mach/mem_map.h directly -- use asm/mem_map.h"
+#endif
+/* Async Memory Banks */
+#define ASYNC_BANK3_BASE        0xBC000000       /* Async Bank 3 */
+#define ASYNC_BANK3_SIZE        0x04000000      /* 64M */
+#define ASYNC_BANK2_BASE        0xB8000000       /* Async Bank 2 */
+#define ASYNC_BANK2_SIZE        0x04000000      /* 64M */
+#define ASYNC_BANK1_BASE        0xB4000000       /* Async Bank 1 */
+#define ASYNC_BANK1_SIZE        0x04000000      /* 64M */
+#define ASYNC_BANK0_BASE        0xB0000000       /* Async Bank 0 */
+#define ASYNC_BANK0_SIZE        0x04000000      /* 64M */
+/* Boot ROM Memory */
+#define BOOT_ROM_START          0xC8000000
+#define BOOT_ROM_LENGTH         0x8000
+/* Level 1 Memory */
+/* Memory Map for ADSP-BF60x processors */
+#ifdef CONFIG_BFIN_ICACHE
+#define BFIN_ICACHESIZE (16*1024)
+#define L1_CODE_LENGTH      0x10000
+#else
+#define BFIN_ICACHESIZE (0*1024)
+#define L1_CODE_LENGTH      0x14000
+#endif
+#define L1_CODE_START       0xFFA00000
+#define L1_DATA_A_START     0xFF800000
+#define L1_DATA_B_START     0xFF900000
+#define COREA_L1_SCRATCH_START  0xFFB00000
+#define COREB_L1_SCRATCH_START  0xFF700000
+#define COREB_L1_CODE_START       0xFF600000
+#define COREB_L1_DATA_A_START     0xFF400000
+#define COREB_L1_DATA_B_START     0xFF500000
+#define COREB_L1_CODE_LENGTH     0x14000
+#define COREB_L1_DATA_A_LENGTH   0x8000
+#define COREB_L1_DATA_B_LENGTH   0x8000
+#ifdef CONFIG_BFIN_DCACHE
+#ifdef CONFIG_BFIN_DCACHE_BANKA
+#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
+#define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
+#define L1_DATA_B_LENGTH      0x8000
+#define BFIN_DCACHESIZE (16*1024)
+#define BFIN_DSUPBANKS  1
+#else
+#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
+#define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
+#define L1_DATA_B_LENGTH      (0x8000 - 0x4000)
+#define BFIN_DCACHESIZE (32*1024)
+#define BFIN_DSUPBANKS  2
+#endif
+#else
+#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
+#define L1_DATA_A_LENGTH      0x8000
+#define L1_DATA_B_LENGTH      0x8000
+#define BFIN_DCACHESIZE (0*1024)
+#define BFIN_DSUPBANKS  0
+#endif /*CONFIG_BFIN_DCACHE*/
+/* Level 2 Memory */
+#define L2_START            0xC8080000
+#define L2_LENGTH           0x40000
+#endif
diff --git a/arch/blackfin/mach-bf609/include/mach/pll.h b/arch/blackfin/mach-bf609/include/mach/pll.h
new file mode 100644
index 000000000000..1857a4a0f262
--- /dev/null
+++ b/arch/blackfin/mach-bf609/include/mach/pll.h
@@ -0,0 +1 @@
+/* #include <mach-common/pll.h> */
diff --git a/arch/blackfin/mach-bf609/include/mach/pm.h b/arch/blackfin/mach-bf609/include/mach/pm.h
new file mode 100644
index 000000000000..036d9bdc889e
--- /dev/null
+++ b/arch/blackfin/mach-bf609/include/mach/pm.h
@@ -0,0 +1,21 @@
+/*
+ * Blackfin bf609 power management
+ *
+ * Copyright 2011 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2
+ */
+#ifndef __MACH_BF609_PM_H__
+#define __MACH_BF609_PM_H__
+#include <linux/suspend.h>
+int bfin609_pm_enter(suspend_state_t state);
+int bf609_pm_prepare(void);
+void bf609_pm_finish(void);
+void bf609_hibernate(void);
+void bfin_sec_raise_irq(unsigned int sid);
+void coreb_enable(void);
+#endif
diff --git a/arch/blackfin/mach-bf609/include/mach/portmux.h b/arch/blackfin/mach-bf609/include/mach/portmux.h
new file mode 100644
index 000000000000..2e1a51c25098
--- /dev/null
+++ b/arch/blackfin/mach-bf609/include/mach/portmux.h
@@ -0,0 +1,347 @@
+/*
+ * Copyright 2011 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later
+ */
+#ifndef _MACH_PORTMUX_H_
+#define _MACH_PORTMUX_H_
+#define MAX_RESOURCES   MAX_BLACKFIN_GPIOS
+/* EMAC RMII Port Mux */
+#define P_MII0_MDC      (P_DEFINED | P_IDENT(GPIO_PC6) | P_FUNCT(0))
+#define P_MII0_MDIO     (P_DEFINED | P_IDENT(GPIO_PC7) | P_FUNCT(0))
+#define P_MII0_ETxD0    (P_DEFINED | P_IDENT(GPIO_PC2) | P_FUNCT(0))
+#define P_MII0_ERxD0    (P_DEFINED | P_IDENT(GPIO_PC0) | P_FUNCT(0))
+#define P_MII0_ETxD1    (P_DEFINED | P_IDENT(GPIO_PC3) | P_FUNCT(0))
+#define P_MII0_ERxD1    (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(0))
+#define P_MII0_ETxEN    (P_DEFINED | P_IDENT(GPIO_PB13) | P_FUNCT(0))
+#define P_MII0_PHYINT   (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(0))
+#define P_MII0_CRS      (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(0))
+#define P_MII0_ERxER    (P_DEFINED | P_IDENT(GPIO_PC4) | P_FUNCT(0))
+#define P_MII0_TxCLK    (P_DEFINED | P_IDENT(GPIO_PB14) | P_FUNCT(0))
+#define P_RMII0 {\
+        P_MII0_ETxD0, \
+        P_MII0_ETxD1, \
+        P_MII0_ETxEN, \
+        P_MII0_ERxD0, \
+        P_MII0_ERxD1, \
+        P_MII0_ERxER, \
+        P_MII0_TxCLK, \
+        P_MII0_PHYINT, \
+        P_MII0_CRS, \
+        P_MII0_MDC, \
+        P_MII0_MDIO, 0}
+#define P_MII1_MDC      (P_DEFINED | P_IDENT(GPIO_PE10) | P_FUNCT(0))
+#define P_MII1_MDIO     (P_DEFINED | P_IDENT(GPIO_PE11) | P_FUNCT(0))
+#define P_MII1_ETxD0    (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
+#define P_MII1_ERxD0    (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
+#define P_MII1_ETxD1    (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0))
+#define P_MII1_ERxD1    (P_DEFINED | P_IDENT(GPIO_PE15) | P_FUNCT(0))
+#define P_MII1_ETxEN    (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
+#define P_MII1_PHYINT   (P_DEFINED | P_IDENT(GPIO_PE12) | P_FUNCT(0))
+#define P_MII1_CRS      (P_DEFINED | P_IDENT(GPIO_PE13) | P_FUNCT(0))
+#define P_MII1_ERxER    (P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(0))
+#define P_MII1_TxCLK    (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
+#define P_RMII1 {\
+        P_MII1_ETxD0, \
+        P_MII1_ETxD1, \
+        P_MII1_ETxEN, \
+        P_MII1_ERxD0, \
+        P_MII1_ERxD1, \
+        P_MII1_ERxER, \
+        P_MII1_TxCLK, \
+        P_MII1_PHYINT, \
+        P_MII1_CRS, \
+        P_MII1_MDC, \
+        P_MII1_MDIO, 0}
+/* PPI Port Mux */
+#define P_PPI0_D0       (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
+#define P_PPI0_D1       (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
+#define P_PPI0_D2       (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
+#define P_PPI0_D3       (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
+#define P_PPI0_D4       (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
+#define P_PPI0_D5       (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
+#define P_PPI0_D6       (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
+#define P_PPI0_D7       (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
+#define P_PPI0_D8       (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
+#define P_PPI0_D9       (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
+#define P_PPI0_D10      (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
+#define P_PPI0_D11      (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1))
+#define P_PPI0_D12      (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1))
+#define P_PPI0_D13      (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
+#define P_PPI0_D14      (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
+#define P_PPI0_D15      (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
+#define P_PPI0_D16      (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(1))
+#define P_PPI0_D17      (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(1))
+#define P_PPI0_D18      (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(1))
+#define P_PPI0_D19      (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(1))
+#define P_PPI0_D20      (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(1))
+#define P_PPI0_D21      (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(1))
+#define P_PPI0_D22      (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(1))
+#define P_PPI0_D23      (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(1))
+#define P_PPI0_CLK      (P_DEFINED | P_IDENT(GPIO_PE9) | P_FUNCT(1))
+#define P_PPI0_FS1      (P_DEFINED | P_IDENT(GPIO_PE8) | P_FUNCT(1))
+#define P_PPI0_FS2      (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(1))
+#define P_PPI0_FS3      (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(1))
+#define P_PPI1_D0       (P_DEFINED | P_IDENT(GPIO_PC0) | P_FUNCT(1))
+#define P_PPI1_D1       (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(1))
+#define P_PPI1_D2       (P_DEFINED | P_IDENT(GPIO_PC2) | P_FUNCT(1))
+#define P_PPI1_D3       (P_DEFINED | P_IDENT(GPIO_PC3) | P_FUNCT(1))
+#define P_PPI1_D4       (P_DEFINED | P_IDENT(GPIO_PC4) | P_FUNCT(1))
+#define P_PPI1_D5       (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(1))
+#define P_PPI1_D6       (P_DEFINED | P_IDENT(GPIO_PC6) | P_FUNCT(1))
+#define P_PPI1_D7       (P_DEFINED | P_IDENT(GPIO_PC7) | P_FUNCT(1))
+#define P_PPI1_D8       (P_DEFINED | P_IDENT(GPIO_PC8) | P_FUNCT(1))
+#define P_PPI1_D9       (P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(1))
+#define P_PPI1_D10      (P_DEFINED | P_IDENT(GPIO_PC10) | P_FUNCT(1))
+#define P_PPI1_D11      (P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(1))
+#define P_PPI1_D12      (P_DEFINED | P_IDENT(GPIO_PC12) | P_FUNCT(1))
+#define P_PPI1_D13      (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(1))
+#define P_PPI1_D14      (P_DEFINED | P_IDENT(GPIO_PC14) | P_FUNCT(1))
+#define P_PPI1_D15      (P_DEFINED | P_IDENT(GPIO_PC15) | P_FUNCT(1))
+#define P_PPI1_D16      (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(1))
+#define P_PPI1_D17      (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(1))
+#define P_PPI1_CLK      (P_DEFINED | P_IDENT(GPIO_PB14) | P_FUNCT(1))
+#define P_PPI1_FS1      (P_DEFINED | P_IDENT(GPIO_PB13) | P_FUNCT(1))
+#define P_PPI1_FS2      (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(1))
+#define P_PPI1_FS3      (P_DEFINED | P_IDENT(GPIO_PB15) | P_FUNCT(1))
+#define P_PPI2_D0       (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(1))
+#define P_PPI2_D1       (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(1))
+#define P_PPI2_D2       (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(1))
+#define P_PPI2_D3       (P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(1))
+#define P_PPI2_D4       (P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(1))
+#define P_PPI2_D5       (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(1))
+#define P_PPI2_D6       (P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(1))
+#define P_PPI2_D7       (P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(1))
+#define P_PPI2_D8       (P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(1))
+#define P_PPI2_D9       (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(1))
+#define P_PPI2_D10      (P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(1))
+#define P_PPI2_D11      (P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(1))
+#define P_PPI2_D12      (P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(1))
+#define P_PPI2_D13      (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(1))
+#define P_PPI2_D14      (P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(1))
+#define P_PPI2_D15      (P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(1))
+#define P_PPI2_D16      (P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(1))
+#define P_PPI2_D17      (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(1))
+#define P_PPI2_CLK      (P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(1))
+#define P_PPI2_FS1      (P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(1))
+#define P_PPI2_FS2      (P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(1))
+#define P_PPI2_FS3      (P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(1))
+/* SPI Port Mux */
+#define P_SPI0_SS       (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(3))
+#define P_SPI0_SCK      (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(0))
+#define P_SPI0_MISO     (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(0))
+#define P_SPI0_MOSI     (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(0))
+#define P_SPI0_RDY      (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(0))
+#define P_SPI0_D2       (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(0))
+#define P_SPI0_D3       (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(0))
+#define P_SPI0_SSEL1    (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(0))
+#define P_SPI0_SSEL2    (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(2))
+#define P_SPI0_SSEL3    (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(2))
+#define P_SPI0_SSEL4    (P_DEFINED | P_IDENT(GPIO_PC15) | P_FUNCT(0))
+#define P_SPI0_SSEL5    (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(0))
+#define P_SPI0_SSEL6    (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(0))
+#define P_SPI0_SSEL7    (P_DEFINED | P_IDENT(GPIO_PC12) | P_FUNCT(0))
+#define P_SPI1_SS       (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(3))
+#define P_SPI1_SCK      (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(0))
+#define P_SPI1_MISO     (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(0))
+#define P_SPI1_MOSI     (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(0))
+#define P_SPI1_RDY      (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(0))
+#define P_SPI1_D2       (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(0))
+#define P_SPI1_D3       (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(0))
+#define P_SPI1_SSEL1    (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(0))
+#define P_SPI1_SSEL2    (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(2))
+#define P_SPI1_SSEL3    (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(2))
+#define P_SPI1_SSEL4    (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(2))
+#define P_SPI1_SSEL5    (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
+#define P_SPI1_SSEL6    (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
+#define P_SPI1_SSEL7    (P_DEFINED | P_IDENT(GPIO_PC14) | P_FUNCT(0))
+#define GPIO_DEFAULT_BOOT_SPI_CS
+#define P_DEFAULT_BOOT_SPI_CS
+/* CORE IDLE  */
+#define P_IDLEA         (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1))
+#define P_IDLEB         (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
+#define P_SLEEP         (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(2))
+/* UART Port Mux */
+#define P_UART0_TX      (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(1))
+#define P_UART0_RX      (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(1))
+#define P_UART0_RTS     (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(1))
+#define P_UART0_CTS     (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(1))
+#define P_UART1_TX      (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
+#define P_UART1_RX      (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
+#define P_UART1_RTS     (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
+#define P_UART1_CTS     (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
+/* Timer */
+#define P_TMRCLK        (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(3))
+#define P_TMR0          (P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(2))
+#define P_TMR1          (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1))
+#define P_TMR2          (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(1))
+#define P_TMR3          (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1))
+#define P_TMR4          (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1))
+#define P_TMR5          (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
+#define P_TMR6          (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
+#define P_TMR7          (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
+/* RSI */
+#define P_RSI_DATA0     (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(2))
+#define P_RSI_DATA1     (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2))
+#define P_RSI_DATA2     (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(2))
+#define P_RSI_DATA3     (P_DEFINED | P_IDENT(GPIO_PE15) | P_FUNCT(2))
+#define P_RSI_DATA4     (P_DEFINED | P_IDENT(GPIO_PE13) | P_FUNCT(2))
+#define P_RSI_DATA5     (P_DEFINED | P_IDENT(GPIO_PE12) | P_FUNCT(2))
+#define P_RSI_DATA6     (P_DEFINED | P_IDENT(GPIO_PE10) | P_FUNCT(2))
+#define P_RSI_DATA7     (P_DEFINED | P_IDENT(GPIO_PE11) | P_FUNCT(2))
+#define P_RSI_CMD       (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1))
+#define P_RSI_CLK       (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
+/* PTP */
+#define P_PTP0_PPS      (P_DEFINED | P_IDENT(GPIO_PB15) | P_FUNCT(0))
+#define P_PTP0_CLKIN    (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(2))
+#define P_PTP0_AUXIN    (P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(2))
+#define P_PTP1_PPS      (P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(0))
+#define P_PTP1_CLKIN    (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(2))
+#define P_PTP1_AUXIN    (P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(2))
+/* SMC Port Mux */
+#define P_A3            (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(0))
+#define P_A4            (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(0))
+#define P_A5            (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(0))
+#define P_A6            (P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(0))
+#define P_A7            (P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(0))
+#define P_A8            (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(0))
+#define P_A9            (P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(0))
+#define P_A10           (P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(0))
+#define P_A11           (P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(0))
+#define P_A12           (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(0))
+#define P_A13           (P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(0))
+#define P_A14           (P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(0))
+#define P_A15           (P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(0))
+#define P_A16           (P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(0))
+#define P_A17           (P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(0))
+#define P_A18           (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(0))
+#define P_A19           (P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(0))
+#define P_A20           (P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(0))
+#define P_A21           (P_DEFINED | P_IDENT(GPIO_PB6) | P_FUNCT(0))
+#define P_A22           (P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(0))
+#define P_A23           (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(0))
+#define P_A24           (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(0))
+#define P_A25           (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(0))
+#define P_NORCK         (P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(0))
+#define P_AMS1          (P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(0))
+#define P_AMS2          (P_DEFINED | P_IDENT(GPIO_PB4) | P_FUNCT(0))
+#define P_AMS3          (P_DEFINED | P_IDENT(GPIO_PB5) | P_FUNCT(0))
+/* CAN */
+#define P_CAN0_TX       (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2))
+#define P_CAN0_RX       (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(2))
+/* SPORT */
+#define P_SPORT0_ACLK   (P_DEFINED | P_IDENT(GPIO_PB5) | P_FUNCT(2))
+#define P_SPORT0_AFS    (P_DEFINED | P_IDENT(GPIO_PB4) | P_FUNCT(2))
+#define P_SPORT0_AD0    (P_DEFINED | P_IDENT(GPIO_PB9) | P_FUNCT(2))
+#define P_SPORT0_AD1    (P_DEFINED | P_IDENT(GPIO_PB12) | P_FUNCT(2))
+#define P_SPORT0_ATDV   (P_DEFINED | P_IDENT(GPIO_PB6) | P_FUNCT(1))
+#define P_SPORT0_BCLK   (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(2))
+#define P_SPORT0_BFS    (P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(2))
+#define P_SPORT0_BD0    (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(2))
+#define P_SPORT0_BD1    (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(2))
+#define P_SPORT0_BTDV   (P_DEFINED | P_IDENT(GPIO_PB12) | P_FUNCT(1))
+#define P_SPORT1_ACLK   (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(2))
+#define P_SPORT1_AFS    (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(2))
+#define P_SPORT1_AD0    (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(2))
+#define P_SPORT1_AD1    (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(2))
+#define P_SPORT1_ATDV   (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(0))
+#define P_SPORT1_BCLK   (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(2))
+#define P_SPORT1_BFS    (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(2))
+#define P_SPORT1_BD0    (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(2))
+#define P_SPORT1_BD1    (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(2))
+#define P_SPORT1_BTDV   (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(0))
+#define P_SPORT2_ACLK   (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0))
+#define P_SPORT2_AFS    (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
+#define P_SPORT2_AD0    (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
+#define P_SPORT2_AD1    (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
+#define P_SPORT2_ATDV   (P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(1))
+#define P_SPORT2_BCLK   (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1))
+#define P_SPORT2_BFS    (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
+#define P_SPORT2_BD0    (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
+#define P_SPORT2_BD1    (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0))
+#define P_SPORT2_BTDV   (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2))
+/* LINK PORT */
+#define P_LP0_CLK       (P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(2))
+#define P_LP0_ACK       (P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(2))
+#define P_LP0_D0        (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(2))
+#define P_LP0_D1        (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(2))
+#define P_LP0_D2        (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(2))
+#define P_LP0_D3        (P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(2))
+#define P_LP0_D4        (P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(2))
+#define P_LP0_D5        (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(2))
+#define P_LP0_D6        (P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(2))
+#define P_LP0_D7        (P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(2))
+#define P_LP1_CLK       (P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(2))
+#define P_LP1_ACK       (P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(2))
+#define P_LP1_D0        (P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(2))
+#define P_LP1_D1        (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(2))
+#define P_LP1_D2        (P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(2))
+#define P_LP1_D3        (P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(2))
+#define P_LP1_D4        (P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(2))
+#define P_LP1_D5        (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(2))
+#define P_LP1_D6        (P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(2))
+#define P_LP1_D7        (P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(2))
+#define P_LP2_CLK       (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(2))
+#define P_LP2_ACK       (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(2))
+#define P_LP2_D0        (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(2))
+#define P_LP2_D1        (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(2))
+#define P_LP2_D2        (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(2))
+#define P_LP2_D3        (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(2))
+#define P_LP2_D4        (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(2))
+#define P_LP2_D5        (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(2))
+#define P_LP2_D6        (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(2))
+#define P_LP2_D7        (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(2))
+#define P_LP3_CLK       (P_DEFINED | P_IDENT(GPIO_PE9) | P_FUNCT(2))
+#define P_LP3_ACK       (P_DEFINED | P_IDENT(GPIO_PE8) | P_FUNCT(2))
+#define P_LP3_D0        (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(2))
+#define P_LP3_D1        (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(2))
+#define P_LP3_D2        (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(2))
+#define P_LP3_D3        (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(2))
+#define P_LP3_D4        (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(2))
+#define P_LP3_D5        (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(2))
+#define P_LP3_D6        (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(2))
+#define P_LP3_D7        (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(2))
+/* TWI */
+#define P_TWI0_SCL      (P_DONTCARE)
+#define P_TWI0_SDA      (P_DONTCARE)
+#define P_TWI1_SCL      (P_DONTCARE)
+#define P_TWI1_SDA      (P_DONTCARE)
+/* Rotary Encoder */
+#define P_CNT_CZM       (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(3))
+#define P_CNT_CUD       (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(3))
+#define P_CNT_CDG       (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(3))
+#endif                          /* _MACH_PORTMUX_H_ */
diff --git a/arch/blackfin/mach-bf609/pm.c b/arch/blackfin/mach-bf609/pm.c
new file mode 100644
index 000000000000..b76966eb16ad
--- /dev/null
+++ b/arch/blackfin/mach-bf609/pm.c
@@ -0,0 +1,362 @@
+/*
+ * Blackfin bf609 power management
+ *
+ * Copyright 2011 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2
+ */
+#include <linux/suspend.h>
+#include <linux/io.h>
+#include <linux/interrupt.h>
+#include <linux/gpio.h>
+#include <linux/irq.h>
+#include <linux/delay.h>
+#include <asm/dpmc.h>
+#include <asm/pm.h>
+#include <mach/pm.h>
+#include <asm/blackfin.h>
+/***********************************************************/
+/*                                                         */
+/* Wakeup Actions for DPM_RESTORE                          */
+/*                                                         */
+/***********************************************************/
+#define BITP_ROM_WUA_CHKHDR             24
+#define BITP_ROM_WUA_DDRLOCK            7
+#define BITP_ROM_WUA_DDRDLLEN           6
+#define BITP_ROM_WUA_DDR                5
+#define BITP_ROM_WUA_CGU                4
+#define BITP_ROM_WUA_MEMBOOT            2
+#define BITP_ROM_WUA_EN                 1
+#define BITM_ROM_WUA_CHKHDR             (0xFF000000)
+#define ENUM_ROM_WUA_CHKHDR_AD                  0xAD000000
+#define BITM_ROM_WUA_DDRLOCK            (0x00000080)
+#define BITM_ROM_WUA_DDRDLLEN           (0x00000040)
+#define BITM_ROM_WUA_DDR                (0x00000020)
+#define BITM_ROM_WUA_CGU                (0x00000010)
+#define BITM_ROM_WUA_MEMBOOT            (0x00000002)
+#define BITM_ROM_WUA_EN                 (0x00000001)
+/***********************************************************/
+/*                                                         */
+/* Syscontrol                                              */
+/*                                                         */
+/***********************************************************/
+#define BITP_ROM_SYSCTRL_CGU_LOCKINGEN  28    /* unlocks CGU_CTL register */
+#define BITP_ROM_SYSCTRL_WUA_OVERRIDE   24
+#define BITP_ROM_SYSCTRL_WUA_DDRDLLEN   20    /* Saves the DDR DLL and PADS registers to the DPM registers */
+#define BITP_ROM_SYSCTRL_WUA_DDR        19    /* Saves the DDR registers to the DPM registers */
+#define BITP_ROM_SYSCTRL_WUA_CGU        18    /* Saves the CGU registers into DPM registers */
+#define BITP_ROM_SYSCTRL_WUA_DPMWRITE   17    /* Saves the Syscontrol structure structure contents into DPM registers */
+#define BITP_ROM_SYSCTRL_WUA_EN         16    /* reads current PLL and DDR configuration into structure */
+#define BITP_ROM_SYSCTRL_DDR_WRITE      13    /* writes the DDR registers from Syscontrol structure for wakeup initialization of DDR */
+#define BITP_ROM_SYSCTRL_DDR_READ       12    /* Read the DDR registers into the Syscontrol structure for storing prior to hibernate */
+#define BITP_ROM_SYSCTRL_CGU_AUTODIS    11    /* Disables auto handling of UPDT and ALGN fields */
+#define BITP_ROM_SYSCTRL_CGU_CLKOUTSEL  7    /* access CGU_CLKOUTSEL register */
+#define BITP_ROM_SYSCTRL_CGU_DIV        6    /* access CGU_DIV register */
+#define BITP_ROM_SYSCTRL_CGU_STAT       5    /* access CGU_STAT register */
+#define BITP_ROM_SYSCTRL_CGU_CTL        4    /* access CGU_CTL register */
+#define BITP_ROM_SYSCTRL_CGU_RTNSTAT    2    /* Update structure STAT field upon error */
+#define BITP_ROM_SYSCTRL_WRITE          1    /* write registers */
+#define BITP_ROM_SYSCTRL_READ           0    /* read registers */
+#define BITM_ROM_SYSCTRL_CGU_READ       (0x00000001)    /* Read CGU registers */
+#define BITM_ROM_SYSCTRL_CGU_WRITE      (0x00000002)    /* Write registers */
+#define BITM_ROM_SYSCTRL_CGU_RTNSTAT    (0x00000004)    /* Update structure STAT field upon error or after a write operation */
+#define BITM_ROM_SYSCTRL_CGU_CTL        (0x00000010)    /* Access CGU_CTL register */
+#define BITM_ROM_SYSCTRL_CGU_STAT       (0x00000020)    /* Access CGU_STAT register */
+#define BITM_ROM_SYSCTRL_CGU_DIV        (0x00000040)    /* Access CGU_DIV register */
+#define BITM_ROM_SYSCTRL_CGU_CLKOUTSEL  (0x00000080)    /* Access CGU_CLKOUTSEL register */
+#define BITM_ROM_SYSCTRL_CGU_AUTODIS    (0x00000800)    /* Disables auto handling of UPDT and ALGN fields */
+#define BITM_ROM_SYSCTRL_DDR_READ       (0x00001000)    /* Reads the contents of the DDR registers and stores them into the structure */
+#define BITM_ROM_SYSCTRL_DDR_WRITE      (0x00002000)    /* Writes the DDR registers from the structure, only really intented for wakeup functionality and not for full DDR configuration */
+#define BITM_ROM_SYSCTRL_WUA_EN         (0x00010000)    /* Wakeup entry or exit opertation enable */
+#define BITM_ROM_SYSCTRL_WUA_DPMWRITE   (0x00020000)    /* When set indicates a restore of the PLL and DDR is to be performed otherwise a save is required */
+#define BITM_ROM_SYSCTRL_WUA_CGU        (0x00040000)    /* Only applicable for a PLL and DDR save operation to the DPM, saves the current settings if cleared or the contents of the structure if set */
+#define BITM_ROM_SYSCTRL_WUA_DDR        (0x00080000)    /* Only applicable for a PLL and DDR save operation to the DPM, saves the current settings if cleared or the contents of the structure if set */
+#define BITM_ROM_SYSCTRL_WUA_DDRDLLEN   (0x00100000)    /* Enables saving/restoring of the DDR DLLCTL register */
+#define BITM_ROM_SYSCTRL_WUA_OVERRIDE   (0x01000000)
+#define BITM_ROM_SYSCTRL_CGU_LOCKINGEN  (0x10000000)    /* Unlocks the CGU_CTL register */
+/* Structures for the syscontrol() function */
+struct STRUCT_ROM_SYSCTRL {
+        uint32_t ulCGU_CTL;
+        uint32_t ulCGU_STAT;
+        uint32_t ulCGU_DIV;
+        uint32_t ulCGU_CLKOUTSEL;
+        uint32_t ulWUA_Flags;
+        uint32_t ulWUA_BootAddr;
+        uint32_t ulWUA_User;
+        uint32_t ulDDR_CTL;
+        uint32_t ulDDR_CFG;
+        uint32_t ulDDR_TR0;
+        uint32_t ulDDR_TR1;
+        uint32_t ulDDR_TR2;
+        uint32_t ulDDR_MR;
+        uint32_t ulDDR_EMR1;
+        uint32_t ulDDR_EMR2;
+        uint32_t ulDDR_PADCTL;
+        uint32_t ulDDR_DLLCTL;
+        uint32_t ulReserved;
+};
+struct bfin_pm_data {
+        uint32_t magic;
+        uint32_t resume_addr;
+        uint32_t sp;
+};
+struct bfin_pm_data bf609_pm_data;
+struct STRUCT_ROM_SYSCTRL configvalues;
+uint32_t dactionflags;
+#define FUNC_ROM_SYSCONTROL 0xC8000080
+__attribute__((l1_data))
+static uint32_t (* const bfrom_SysControl)(uint32_t action_flags, struct STRUCT_ROM_SYSCTRL *settings, void *reserved) = (void *)FUNC_ROM_SYSCONTROL;
+__attribute__((l1_text))
+void bfin_cpu_suspend(void)
+{
+        __asm__ __volatile__( \
+                        ".align 8;" \
+                        "idle;" \
+                        : : \
+                        );
+}
+__attribute__((l1_text))
+void bfin_deepsleep(unsigned long mask)
+{
+        uint32_t dpm0_ctl;
+        bfin_write32(DPM0_WAKE_EN, 0x10);
+        bfin_write32(DPM0_WAKE_POL, 0x10);
+        dpm0_ctl = 0x00000008;
+        bfin_write32(DPM0_CTL, dpm0_ctl);
+        SSYNC();
+        __asm__ __volatile__( \
+                        ".align 8;" \
+                        "idle;" \
+                        : : \
+                        );
+#ifdef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH
+        __asm__ __volatile__(
+                "R0 = 0;"
+                "CYCLES = R0;"
+                "CYCLES2 = R0;"
+                "R0 = SYSCFG;"
+                "BITSET(R0, 1);"
+                "SYSCFG = R0;"
+                : : : "R0"
+        );
+#endif
+}
+__attribute__((l1_text))
+void bf609_ddr_sr(void)
+{
+        uint32_t reg;
+        reg = bfin_read_DMC0_CTL();
+        reg |= 0x8;
+        bfin_write_DMC0_CTL(reg);
+        while (!(bfin_read_DMC0_STAT() & 0x8))
+                continue;
+}
+__attribute__((l1_text))
+void bf609_ddr_sr_exit(void)
+{
+        uint32_t reg;
+        while (!(bfin_read_DMC0_STAT() & 0x1))
+                continue;
+        reg = bfin_read_DMC0_CTL();
+        reg &= ~0x8;
+        bfin_write_DMC0_CTL(reg);
+        while ((bfin_read_DMC0_STAT() & 0x8))
+                continue;
+}
+__attribute__((l1_text))
+void bfin_hibernate_syscontrol(void)
+{
+        configvalues.ulWUA_Flags = (0xAD000000 | BITM_ROM_WUA_EN
+                | BITM_ROM_WUA_CGU | BITM_ROM_WUA_DDR | BITM_ROM_WUA_DDRDLLEN);
+        dactionflags = (BITM_ROM_SYSCTRL_WUA_EN
+                | BITM_ROM_SYSCTRL_WUA_DPMWRITE | BITM_ROM_SYSCTRL_WUA_CGU
+                | BITM_ROM_SYSCTRL_WUA_DDR | BITM_ROM_SYSCTRL_WUA_DDRDLLEN);
+        bfrom_SysControl(dactionflags, &configvalues, NULL);
+        bfin_write32(DPM0_RESTORE5, bfin_read32(DPM0_RESTORE5) | 4);
+}
+#ifndef CONFIG_BF60x
+# define SIC_SYSIRQ(irq)        (irq - (IRQ_CORETMR + 1))
+#else
+# define SIC_SYSIRQ(irq)        ((irq) - IVG15)
+#endif
+void bfin_hibernate(unsigned long mask)
+{
+        bfin_write32(DPM0_WAKE_EN, 0x10);
+        bfin_write32(DPM0_WAKE_POL, 0x10);
+        bfin_write32(DPM0_PGCNTR, 0x0000FFFF);
+        bfin_write32(DPM0_HIB_DIS, 0xFFFF);
+        printk(KERN_DEBUG "hibernate: restore %x pgcnt %x\n", bfin_read32(DPM0_RESTORE0), bfin_read32(DPM0_PGCNTR));
+        bf609_hibernate();
+}
+void bf609_cpu_pm_enter(suspend_state_t state)
+{
+        int error;
+        unsigned long wakeup = 0;
+        unsigned long wakeup_pol = 0;
+#ifdef CONFIG_PM_BFIN_WAKE_PA15
+        wakeup |= PA15WE;
+# if CONFIG_PM_BFIN_WAKE_PA15_POL
+        wakeup_pol |= PA15WE;
+# endif
+#endif
+#ifdef CONFIG_PM_BFIN_WAKE_PB15
+        wakeup |= PB15WE;
+# if CONFIG_PM_BFIN_WAKE_PA15_POL
+        wakeup_pol |= PB15WE;
+# endif
+#endif
+#ifdef CONFIG_PM_BFIN_WAKE_PC15
+        wakeup |= PC15WE;
+# if CONFIG_PM_BFIN_WAKE_PC15_POL
+        wakeup_pol |= PC15WE;
+# endif
+#endif
+#ifdef CONFIG_PM_BFIN_WAKE_PD06
+        wakeup |= PD06WE;
+# if CONFIG_PM_BFIN_WAKE_PD06_POL
+        wakeup_pol |= PD06WE;
+# endif
+#endif
+#ifdef CONFIG_PM_BFIN_WAKE_PE12
+        wakeup |= PE12WE;
+# if CONFIG_PM_BFIN_WAKE_PE12_POL
+        wakeup_pol |= PE12WE;
+# endif
+#endif
+#ifdef CONFIG_PM_BFIN_WAKE_PG04
+        wakeup |= PG04WE;
+# if CONFIG_PM_BFIN_WAKE_PG04_POL
+        wakeup_pol |= PG04WE;
+# endif
+#endif
+#ifdef CONFIG_PM_BFIN_WAKE_PG13
+        wakeup |= PG13WE;
+# if CONFIG_PM_BFIN_WAKE_PG13_POL
+        wakeup_pol |= PG13WE;
+# endif
+#endif
+#ifdef CONFIG_PM_BFIN_WAKE_USB
+        wakeup |= USBWE;
+# if CONFIG_PM_BFIN_WAKE_USB_POL
+        wakeup_pol |= USBWE;
+# endif
+#endif
+        error = irq_set_irq_wake(255, 1);
+        if(error < 0)
+                printk(KERN_DEBUG "Unable to get irq wake\n");
+        error = irq_set_irq_wake(231, 1);
+        if (error < 0)
+                printk(KERN_DEBUG "Unable to get irq wake\n");
+        if (state == PM_SUSPEND_STANDBY)
+                bfin_deepsleep(wakeup);
+        else {
+                bfin_hibernate(wakeup);
+        }
+}
+int bf609_cpu_pm_prepare(void)
+{
+        return 0;
+}
+void bf609_cpu_pm_finish(void)
+{
+}
+static struct bfin_cpu_pm_fns bf609_cpu_pm = {
+        .enter          = bf609_cpu_pm_enter,
+        .prepare        = bf609_cpu_pm_prepare,
+        .finish         = bf609_cpu_pm_finish,
+};
+static irqreturn_t test_isr(int irq, void *dev_id)
+{
+        printk(KERN_DEBUG "gpio irq %d\n", irq);
+        return IRQ_HANDLED;
+}
+static irqreturn_t dpm0_isr(int irq, void *dev_id)
+{
+        uint32_t wake_stat;
+        wake_stat = bfin_read32(DPM0_WAKE_STAT);
+        printk(KERN_DEBUG "enter %s wake stat %08x\n", __func__, wake_stat);
+        bfin_write32(DPM0_WAKE_STAT, wake_stat);
+        return IRQ_HANDLED;
+}
+static int __init bf609_init_pm(void)
+{
+        int irq;
+        int error;
+#if CONFIG_PM_BFIN_WAKE_PE12
+        irq = gpio_to_irq(GPIO_PE12);
+        if (irq < 0) {
+                error = irq;
+                printk(KERN_DEBUG "Unable to get irq number for GPIO %d, error %d\n",
+                                GPIO_PE12, error);
+        }
+        error = request_irq(irq, test_isr, IRQF_TRIGGER_RISING | IRQF_NO_SUSPEND, "gpiope12", NULL);
+        if(error < 0)
+                printk(KERN_DEBUG "Unable to get irq\n");
+#endif
+        error = request_irq(IRQ_CGU_EVT, dpm0_isr, IRQF_NO_SUSPEND, "cgu0 event", NULL);
+        if(error < 0)
+                printk(KERN_DEBUG "Unable to get irq\n");
+        error = request_irq(IRQ_DPM, dpm0_isr, IRQF_NO_SUSPEND, "dpm0 event", NULL);
+        if (error < 0)
+                printk(KERN_DEBUG "Unable to get irq\n");
+        bfin_cpu_pm = &bf609_cpu_pm;
+        return 0;
+}
+late_initcall(bf609_init_pm);
diff --git a/arch/blackfin/mach-common/Makefile b/arch/blackfin/mach-common/Makefile
index ff299f24aba0..75f0ba29ebb9 100644
--- a/arch/blackfin/mach-common/Makefile
+++ b/arch/blackfin/mach-common/Makefile
@@ -6,7 +6,10 @@ obj-y := \
        cache.o cache-c.o entry.o head.o \
        interrupt.o arch_checks.o ints-priority.o
-obj-$(CONFIG_PM)          += pm.o dpmc_modes.o
+obj-$(CONFIG_PM)          += pm.o
+ifneq ($(CONFIG_BF60x),y)
+obj-$(CONFIG_PM)          += dpmc_modes.o
+endif
 obj-$(CONFIG_CPU_FREQ)    += cpufreq.o
 obj-$(CONFIG_CPU_VOLTAGE) += dpmc.o
 obj-$(CONFIG_SMP)         += smp.o
diff --git a/arch/blackfin/mach-common/clock.h b/arch/blackfin/mach-common/clock.h
new file mode 100644
index 000000000000..645ff460a1f2
--- /dev/null
+++ b/arch/blackfin/mach-common/clock.h
@@ -0,0 +1,27 @@
+#ifndef __MACH_COMMON_CLKDEV_H
+#define __MACH_COMMON_CLKDEV_H
+#include <linux/clk.h>
+struct clk_ops {
+        unsigned long (*get_rate)(struct clk *clk);
+        unsigned long (*round_rate)(struct clk *clk, unsigned long rate);
+        int (*set_rate)(struct clk *clk, unsigned long rate);
+        int (*enable)(struct clk *clk);
+        int (*disable)(struct clk *clk);
+};
+struct clk {
+        const char              *name;
+        unsigned long           rate;
+        spinlock_t              lock;
+        u32                     flags;
+        const struct clk_ops    *ops;
+        const struct params     *params;
+        void __iomem            *reg;
+        u32                     mask;
+        u32                     shift;
+};
+#endif
diff --git a/arch/blackfin/mach-common/clocks-init.c b/arch/blackfin/mach-common/clocks-init.c
index d5cfe611b778..7ad2407d1571 100644
--- a/arch/blackfin/mach-common/clocks-init.c
+++ b/arch/blackfin/mach-common/clocks-init.c
@@ -15,10 +15,121 @@
 #include <asm/mem_init.h>
 #include <asm/dpmc.h>
+#ifdef CONFIG_BF60x
+#define CSEL_P                  0
+#define S0SEL_P                 5
+#define SYSSEL_P                8
+#define S1SEL_P                 13
+#define DSEL_P                  16
+#define OSEL_P                  22
+#define ALGN_P                  29
+#define UPDT_P                  30
+#define LOCK_P                  31
+#define CGU_CTL_VAL ((CONFIG_VCO_MULT << 8) | CLKIN_HALF)
+#define CGU_DIV_VAL \
+        ((CONFIG_CCLK_DIV   << CSEL_P)   | \
+        (CONFIG_SCLK_DIV << SYSSEL_P)   | \
+        (CONFIG_SCLK0_DIV  << S0SEL_P)  | \
+        (CONFIG_SCLK1_DIV  << S1SEL_P)  | \
+        (CONFIG_DCLK_DIV   << DSEL_P))
+#define CONFIG_BFIN_DCLK (((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / CONFIG_DCLK_DIV) / 1000000)
+#if ((CONFIG_BFIN_DCLK != 125) && \
+        (CONFIG_BFIN_DCLK != 133) && (CONFIG_BFIN_DCLK != 150) && \
+        (CONFIG_BFIN_DCLK != 166) && (CONFIG_BFIN_DCLK != 200) && \
+        (CONFIG_BFIN_DCLK != 225) && (CONFIG_BFIN_DCLK != 250))
+#error "DCLK must be in (125, 133, 150, 166, 200, 225, 250)MHz"
+#endif
+struct ddr_config {
+        u32 ddr_clk;
+        u32 dmc_ddrctl;
+        u32 dmc_ddrcfg;
+        u32 dmc_ddrtr0;
+        u32 dmc_ddrtr1;
+        u32 dmc_ddrtr2;
+        u32 dmc_ddrmr;
+        u32 dmc_ddrmr1;
+};
+struct ddr_config ddr_config_table[] __attribute__((section(".data_l1"))) = {
+        [0] = {
+                .ddr_clk    = 125,
+                .dmc_ddrctl = 0x00000904,
+                .dmc_ddrcfg = 0x00000422,
+                .dmc_ddrtr0 = 0x20705212,
+                .dmc_ddrtr1 = 0x201003CF,
+                .dmc_ddrtr2 = 0x00320107,
+                .dmc_ddrmr  = 0x00000422,
+                .dmc_ddrmr1 = 0x4,
+        },
+        [1] = {
+                .ddr_clk    = 133,
+                .dmc_ddrctl = 0x00000904,
+                .dmc_ddrcfg = 0x00000422,
+                .dmc_ddrtr0 = 0x20806313,
+                .dmc_ddrtr1 = 0x2013040D,
+                .dmc_ddrtr2 = 0x00320108,
+                .dmc_ddrmr  = 0x00000632,
+                .dmc_ddrmr1 = 0x4,
+        },
+        [2] = {
+                .ddr_clk    = 150,
+                .dmc_ddrctl = 0x00000904,
+                .dmc_ddrcfg = 0x00000422,
+                .dmc_ddrtr0 = 0x20A07323,
+                .dmc_ddrtr1 = 0x20160492,
+                .dmc_ddrtr2 = 0x00320209,
+                .dmc_ddrmr  = 0x00000632,
+                .dmc_ddrmr1 = 0x4,
+        },
+        [3] = {
+                .ddr_clk    = 166,
+                .dmc_ddrctl = 0x00000904,
+                .dmc_ddrcfg = 0x00000422,
+                .dmc_ddrtr0 = 0x20A07323,
+                .dmc_ddrtr1 = 0x2016050E,
+                .dmc_ddrtr2 = 0x00320209,
+                .dmc_ddrmr  = 0x00000632,
+                .dmc_ddrmr1 = 0x4,
+        },
+        [4] = {
+                .ddr_clk    = 200,
+                .dmc_ddrctl = 0x00000904,
+                .dmc_ddrcfg = 0x00000422,
+                .dmc_ddrtr0 = 0x20a07323,
+                .dmc_ddrtr1 = 0x2016050f,
+                .dmc_ddrtr2 = 0x00320509,
+                .dmc_ddrmr  = 0x00000632,
+                .dmc_ddrmr1 = 0x4,
+        },
+        [5] = {
+                .ddr_clk    = 225,
+                .dmc_ddrctl = 0x00000904,
+                .dmc_ddrcfg = 0x00000422,
+                .dmc_ddrtr0 = 0x20E0A424,
+                .dmc_ddrtr1 = 0x302006DB,
+                .dmc_ddrtr2 = 0x0032020D,
+                .dmc_ddrmr  = 0x00000842,
+                .dmc_ddrmr1 = 0x4,
+        },
+        [6] = {
+                .ddr_clk    = 250,
+                .dmc_ddrctl = 0x00000904,
+                .dmc_ddrcfg = 0x00000422,
+                .dmc_ddrtr0 = 0x20E0A424,
+                .dmc_ddrtr1 = 0x3020079E,
+                .dmc_ddrtr2 = 0x0032020D,
+                .dmc_ddrmr  = 0x00000842,
+                .dmc_ddrmr1 = 0x4,
+        },
+};
+#else
 #define SDGCTL_WIDTH (1 << 31)  /* SDRAM external data path width */
 #define PLL_CTL_VAL \
        (((CONFIG_VCO_MULT & 63) << 9) | CLKIN_HALF | \
-         (PLL_BYPASS << 8) | (ANOMALY_05000305 ? 0 : 0x8000))
+                (PLL_BYPASS << 8) | (ANOMALY_05000305 ? 0 : 0x8000))
+#endif
 __attribute__((l1_text))
 static void do_sync(void)
@@ -33,6 +144,44 @@ void init_clocks(void)
         * in the middle of reprogramming things, and that'll screw us up.
         * For example, any automatic DMAs left by U-Boot for splash screens.
         */
+#ifdef CONFIG_BF60x
+        int i, dlldatacycle, dll_ctl;
+        bfin_write32(CGU0_DIV, CGU_DIV_VAL);
+        bfin_write32(CGU0_CTL, CGU_CTL_VAL);
+        while ((bfin_read32(CGU0_STAT) & 0x8) || !(bfin_read32(CGU0_STAT) & 0x4))
+                continue;
+        bfin_write32(CGU0_DIV, CGU_DIV_VAL | (1 << UPDT_P));
+        while (bfin_read32(CGU0_STAT) & (1 << 3))
+                continue;
+        for (i = 0; i < 7; i++) {
+                if (ddr_config_table[i].ddr_clk == CONFIG_BFIN_DCLK) {
+                        bfin_write_DDR0_CFG(ddr_config_table[i].dmc_ddrcfg);
+                        bfin_write_DDR0_TR0(ddr_config_table[i].dmc_ddrtr0);
+                        bfin_write_DDR0_TR1(ddr_config_table[i].dmc_ddrtr1);
+                        bfin_write_DDR0_TR2(ddr_config_table[i].dmc_ddrtr2);
+                        bfin_write_DDR0_MR(ddr_config_table[i].dmc_ddrmr);
+                        bfin_write_DDR0_EMR1(ddr_config_table[i].dmc_ddrmr1);
+                        bfin_write_DDR0_CTL(ddr_config_table[i].dmc_ddrctl);
+                        break;
+                }
+        }
+        do_sync();
+        while (!(bfin_read_DDR0_STAT() & 0x4))
+                continue;
+        dlldatacycle = (bfin_read_DDR0_STAT() & 0x00f00000) >> 20;
+        dll_ctl = bfin_read_DDR0_DLLCTL();
+        dll_ctl &= 0x0ff;
+        bfin_write_DDR0_DLLCTL(dll_ctl | (dlldatacycle << 8));
+        do_sync();
+        while (!(bfin_read_DDR0_STAT() & 0x2000))
+                continue;
+#else
        size_t i;
        for (i = 0; i < MAX_DMA_CHANNELS; ++i) {
                struct dma_register *dma = dma_io_base_addr[i];
@@ -91,6 +240,8 @@ void init_clocks(void)
        bfin_write_EBIU_DDRQUE(CONFIG_MEM_EBIU_DDRQUE);
 #endif
 #endif
+#endif
        do_sync();
        bfin_read16(0);
 }
diff --git a/arch/blackfin/mach-common/cpufreq.c b/arch/blackfin/mach-common/cpufreq.c
index 2e6eefd812f4..6e87dc13f6bf 100644
--- a/arch/blackfin/mach-common/cpufreq.c
+++ b/arch/blackfin/mach-common/cpufreq.c
@@ -10,6 +10,7 @@
 #include <linux/module.h>
 #include <linux/types.h>
 #include <linux/init.h>
+#include <linux/clk.h>
 #include <linux/cpufreq.h>
 #include <linux/fs.h>
 #include <linux/delay.h>
@@ -17,6 +18,7 @@
 #include <asm/time.h>
 #include <asm/dpmc.h>
 /* this is the table of CCLK frequencies, in Hz */
 /* .index is the entry in the auxiliary dpm_state_table[] */
 static struct cpufreq_frequency_table bfin_freq_table[] = {
@@ -67,12 +69,22 @@ static void __init bfin_init_tables(unsigned long cclk, unsigned long sclk)
 #else
        min_cclk = sclk;
 #endif
+#ifndef CONFIG_BF60x
        csel = ((bfin_read_PLL_DIV() & CSEL) >> 4);
+#else
+        csel = bfin_read32(CGU0_DIV) & 0x1F;
+#endif
        for (index = 0;  (cclk >> index) >= min_cclk && csel <= 3; index++, csel++) {
                bfin_freq_table[index].frequency = cclk >> index;
+#ifndef CONFIG_BF60x
                dpm_state_table[index].csel = csel << 4; /* Shift now into PLL_DIV bitpos */
                dpm_state_table[index].tscale =  (TIME_SCALE / (1 << csel)) - 1;
+#else
+                dpm_state_table[index].csel = csel;
+                dpm_state_table[index].tscale =  TIME_SCALE >> index;
+#endif
                pr_debug("cpufreq: freq:%d csel:0x%x tscale:%d\n",
                                                 bfin_freq_table[index].frequency,
@@ -99,14 +111,34 @@ static unsigned int bfin_getfreq_khz(unsigned int cpu)
        return get_cclk() / 1000;
 }
+#ifdef CONFIG_BF60x
+unsigned long cpu_set_cclk(int cpu, unsigned long new)
+{
+        struct clk *clk;
+        int ret;
+        clk = clk_get(NULL, "CCLK");
+        if (IS_ERR(clk))
+                return -ENODEV;
+        ret = clk_set_rate(clk, new);
+        clk_put(clk);
+        return ret;
+}
+#endif
 static int bfin_target(struct cpufreq_policy *poli,
                        unsigned int target_freq, unsigned int relation)
 {
-        unsigned int index, plldiv, cpu;
+#ifndef CONFIG_BF60x
+        unsigned int plldiv;
+#endif
+        unsigned int index, cpu;
        unsigned long flags, cclk_hz;
        struct cpufreq_freqs freqs;
        static unsigned long lpj_ref;
        static unsigned int  lpj_ref_freq;
+        int ret = 0;
 #if defined(CONFIG_CYCLES_CLOCKSOURCE)
        cycles_t cycles;
@@ -134,9 +166,17 @@ static int bfin_target(struct cpufreq_policy *poli,
                cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
                if (cpu == CPUFREQ_CPU) {
                        flags = hard_local_irq_save();
+#ifndef CONFIG_BF60x
                        plldiv = (bfin_read_PLL_DIV() & SSEL) |
                                                dpm_state_table[index].csel;
                        bfin_write_PLL_DIV(plldiv);
+#else
+                        ret = cpu_set_cclk(cpu, freqs.new * 1000);
+                        if (ret != 0) {
+                                pr_debug("cpufreq set freq failed %d\n", ret);
+                                break;
+                        }
+#endif
                        on_each_cpu(bfin_adjust_core_timer, &index, 1);
 #if defined(CONFIG_CYCLES_CLOCKSOURCE)
                        cycles = get_cycles();
@@ -161,7 +201,7 @@ static int bfin_target(struct cpufreq_policy *poli,
        }
        pr_debug("cpufreq: done\n");
-        return 0;
+        return ret;
 }
 static int bfin_verify_speed(struct cpufreq_policy *policy)
@@ -169,7 +209,7 @@ static int bfin_verify_speed(struct cpufreq_policy *policy)
        return cpufreq_frequency_table_verify(policy, bfin_freq_table);
 }
-static int __init __bfin_cpu_init(struct cpufreq_policy *policy)
+static int __bfin_cpu_init(struct cpufreq_policy *policy)
 {
        unsigned long cclk, sclk;
diff --git a/arch/blackfin/mach-common/dpmc_modes.S b/arch/blackfin/mach-common/dpmc_modes.S
index 1c534d298de4..de99f3aac2c5 100644
--- a/arch/blackfin/mach-common/dpmc_modes.S
+++ b/arch/blackfin/mach-common/dpmc_modes.S
@@ -10,7 +10,6 @@
 #include <asm/dpmc.h>
 .section .l1.text
 ENTRY(_sleep_mode)
        [--SP] = (R7:4, P5:3);
        [--SP] = RETS;
@@ -43,6 +42,9 @@ ENTRY(_sleep_mode)
        BITCLR (R7, 5);
        w[p0] = R7.L;
        IDLE;
+        bfin_init_pm_bench_cycles;
        call _test_pll_locked;
        RETS = [SP++];
@@ -58,12 +60,13 @@ ENDPROC(_sleep_mode)
 *
 * We accept just one argument -- the value to write to VR_CTL.
 */
 ENTRY(_hibernate_mode)
        /* Save/setup the regs we need early for minor pipeline optimization */
        R4 = R0;
        P3.H = hi(VR_CTL);
        P3.L = lo(VR_CTL);
        /* Disable all wakeup sources */
        R0 = IWR_DISABLE_ALL;
        R1 = IWR_DISABLE_ALL;
@@ -74,6 +77,9 @@ ENTRY(_hibernate_mode)
        /* Finally, we climb into our cave to hibernate */
        W[P3] = R4.L;
+        bfin_init_pm_bench_cycles;
        CLI R2;
        IDLE;
 .Lforever:
@@ -158,6 +164,8 @@ ENTRY(_sleep_deeper)
        SSYNC;
        IDLE;
+        bfin_init_pm_bench_cycles;
        call _test_pll_locked;
        P0.H = hi(PLL_DIV);
@@ -276,327 +284,10 @@ ENTRY(_test_pll_locked)
 ENDPROC(_test_pll_locked)
 .section .text
-#define PM_REG0  R7
-#define PM_REG1  R6
-#define PM_REG2  R5
-#define PM_REG3  R4
-#define PM_REG4  R3
-#define PM_REG5  R2
-#define PM_REG6  R1
-#define PM_REG7  R0
-#define PM_REG8  P5
-#define PM_REG9  P4
-#define PM_REG10 P3
-#define PM_REG11 P2
-#define PM_REG12 P1
-#define PM_REG13 P0
-#define PM_REGSET0  R7:7
-#define PM_REGSET1  R7:6
-#define PM_REGSET2  R7:5
-#define PM_REGSET3  R7:4
-#define PM_REGSET4  R7:3
-#define PM_REGSET5  R7:2
-#define PM_REGSET6  R7:1
-#define PM_REGSET7  R7:0
-#define PM_REGSET8  R7:0, P5:5
-#define PM_REGSET9  R7:0, P5:4
-#define PM_REGSET10 R7:0, P5:3
-#define PM_REGSET11 R7:0, P5:2
-#define PM_REGSET12 R7:0, P5:1
-#define PM_REGSET13 R7:0, P5:0
-#define _PM_PUSH(n, x, w, base) PM_REG##n = w[FP + ((x) - (base))];
-#define _PM_POP(n, x, w, base)  w[FP + ((x) - (base))] = PM_REG##n;
-#define PM_PUSH_SYNC(n)         [--sp] = (PM_REGSET##n);
-#define PM_POP_SYNC(n)          (PM_REGSET##n) = [sp++];
-#define PM_PUSH(n, x)           PM_REG##n = [FP++];
-#define PM_POP(n, x)            [FP--] = PM_REG##n;
-#define PM_CORE_PUSH(n, x)      _PM_PUSH(n, x, , COREMMR_BASE)
-#define PM_CORE_POP(n, x)       _PM_POP(n, x, , COREMMR_BASE)
-#define PM_SYS_PUSH(n, x)       _PM_PUSH(n, x, , SYSMMR_BASE)
-#define PM_SYS_POP(n, x)        _PM_POP(n, x, , SYSMMR_BASE)
-#define PM_SYS_PUSH16(n, x)     _PM_PUSH(n, x, w, SYSMMR_BASE)
-#define PM_SYS_POP16(n, x)      _PM_POP(n, x, w, SYSMMR_BASE)
 ENTRY(_do_hibernate)
-        /*
+        bfin_cpu_reg_save;
-         * Save the core regs early so we can blow them away when
+        bfin_sys_mmr_save;
-         * saving/restoring MMR states
+        bfin_core_mmr_save;
-         */
-        [--sp] = (R7:0, P5:0);
-        [--sp] = fp;
-        [--sp] = usp;
-        [--sp] = i0;
-        [--sp] = i1;
-        [--sp] = i2;
-        [--sp] = i3;
-        [--sp] = m0;
-        [--sp] = m1;
-        [--sp] = m2;
-        [--sp] = m3;
-        [--sp] = l0;
-        [--sp] = l1;
-        [--sp] = l2;
-        [--sp] = l3;
-        [--sp] = b0;
-        [--sp] = b1;
-        [--sp] = b2;
-        [--sp] = b3;
-        [--sp] = a0.x;
-        [--sp] = a0.w;
-        [--sp] = a1.x;
-        [--sp] = a1.w;
-        [--sp] = LC0;
-        [--sp] = LC1;
-        [--sp] = LT0;
-        [--sp] = LT1;
-        [--sp] = LB0;
-        [--sp] = LB1;
-        /* We can't push RETI directly as that'll change IPEND[4] */
-        r7 = RETI;
-        [--sp] = RETS;
-        [--sp] = ASTAT;
-        [--sp] = CYCLES;
-        [--sp] = CYCLES2;
-        [--sp] = SYSCFG;
-        [--sp] = RETX;
-        [--sp] = SEQSTAT;
-        [--sp] = r7;
-        /* Save first func arg in M3 */
-        M3 = R0;
-        /* Save system MMRs */
-        FP.H = hi(SYSMMR_BASE);
-        FP.L = lo(SYSMMR_BASE);
-#ifdef SIC_IMASK0
-        PM_SYS_PUSH(0, SIC_IMASK0)
-        PM_SYS_PUSH(1, SIC_IMASK1)
-# ifdef SIC_IMASK2
-        PM_SYS_PUSH(2, SIC_IMASK2)
-# endif
-#else
-        PM_SYS_PUSH(0, SIC_IMASK)
-#endif
-#ifdef SIC_IAR0
-        PM_SYS_PUSH(3, SIC_IAR0)
-        PM_SYS_PUSH(4, SIC_IAR1)
-        PM_SYS_PUSH(5, SIC_IAR2)
-#endif
-#ifdef SIC_IAR3
-        PM_SYS_PUSH(6, SIC_IAR3)
-#endif
-#ifdef SIC_IAR4
-        PM_SYS_PUSH(7, SIC_IAR4)
-        PM_SYS_PUSH(8, SIC_IAR5)
-        PM_SYS_PUSH(9, SIC_IAR6)
-#endif
-#ifdef SIC_IAR7
-        PM_SYS_PUSH(10, SIC_IAR7)
-#endif
-#ifdef SIC_IAR8
-        PM_SYS_PUSH(11, SIC_IAR8)
-        PM_SYS_PUSH(12, SIC_IAR9)
-        PM_SYS_PUSH(13, SIC_IAR10)
-#endif
-        PM_PUSH_SYNC(13)
-#ifdef SIC_IAR11
-        PM_SYS_PUSH(0, SIC_IAR11)
-#endif
-#ifdef SIC_IWR
-        PM_SYS_PUSH(1, SIC_IWR)
-#endif
-#ifdef SIC_IWR0
-        PM_SYS_PUSH(1, SIC_IWR0)
-#endif
-#ifdef SIC_IWR1
-        PM_SYS_PUSH(2, SIC_IWR1)
-#endif
-#ifdef SIC_IWR2
-        PM_SYS_PUSH(3, SIC_IWR2)
-#endif
-#ifdef PINT0_ASSIGN
-        PM_SYS_PUSH(4, PINT0_MASK_SET)
-        PM_SYS_PUSH(5, PINT1_MASK_SET)
-        PM_SYS_PUSH(6, PINT2_MASK_SET)
-        PM_SYS_PUSH(7, PINT3_MASK_SET)
-        PM_SYS_PUSH(8, PINT0_ASSIGN)
-        PM_SYS_PUSH(9, PINT1_ASSIGN)
-        PM_SYS_PUSH(10, PINT2_ASSIGN)
-        PM_SYS_PUSH(11, PINT3_ASSIGN)
-        PM_SYS_PUSH(12, PINT0_INVERT_SET)
-        PM_SYS_PUSH(13, PINT1_INVERT_SET)
-        PM_PUSH_SYNC(13)
-        PM_SYS_PUSH(0, PINT2_INVERT_SET)
-        PM_SYS_PUSH(1, PINT3_INVERT_SET)
-        PM_SYS_PUSH(2, PINT0_EDGE_SET)
-        PM_SYS_PUSH(3, PINT1_EDGE_SET)
-        PM_SYS_PUSH(4, PINT2_EDGE_SET)
-        PM_SYS_PUSH(5, PINT3_EDGE_SET)
-#endif
-        PM_SYS_PUSH16(6, SYSCR)
-        PM_SYS_PUSH16(7, EBIU_AMGCTL)
-        PM_SYS_PUSH(8, EBIU_AMBCTL0)
-        PM_SYS_PUSH(9, EBIU_AMBCTL1)
-#ifdef EBIU_FCTL
-        PM_SYS_PUSH(10, EBIU_MBSCTL)
-        PM_SYS_PUSH(11, EBIU_MODE)
-        PM_SYS_PUSH(12, EBIU_FCTL)
-        PM_PUSH_SYNC(12)
-#else
-        PM_PUSH_SYNC(9)
-#endif
-        /* Save Core MMRs */
-        I0.H = hi(COREMMR_BASE);
-        I0.L = lo(COREMMR_BASE);
-        I1 = I0;
-        I2 = I0;
-        I3 = I0;
-        B0 = I0;
-        B1 = I0;
-        B2 = I0;
-        B3 = I0;
-        I1.L = lo(DCPLB_ADDR0);
-        I2.L = lo(DCPLB_DATA0);
-        I3.L = lo(ICPLB_ADDR0);
-        B0.L = lo(ICPLB_DATA0);
-        B1.L = lo(EVT2);
-        B2.L = lo(IMASK);
-        B3.L = lo(TCNTL);
-        /* DCPLB Addr */
-        FP = I1;
-        PM_PUSH(0, DCPLB_ADDR0)
-        PM_PUSH(1, DCPLB_ADDR1)
-        PM_PUSH(2, DCPLB_ADDR2)
-        PM_PUSH(3, DCPLB_ADDR3)
-        PM_PUSH(4, DCPLB_ADDR4)
-        PM_PUSH(5, DCPLB_ADDR5)
-        PM_PUSH(6, DCPLB_ADDR6)
-        PM_PUSH(7, DCPLB_ADDR7)
-        PM_PUSH(8, DCPLB_ADDR8)
-        PM_PUSH(9, DCPLB_ADDR9)
-        PM_PUSH(10, DCPLB_ADDR10)
-        PM_PUSH(11, DCPLB_ADDR11)
-        PM_PUSH(12, DCPLB_ADDR12)
-        PM_PUSH(13, DCPLB_ADDR13)
-        PM_PUSH_SYNC(13)
-        PM_PUSH(0, DCPLB_ADDR14)
-        PM_PUSH(1, DCPLB_ADDR15)
-        /* DCPLB Data */
-        FP = I2;
-        PM_PUSH(2, DCPLB_DATA0)
-        PM_PUSH(3, DCPLB_DATA1)
-        PM_PUSH(4, DCPLB_DATA2)
-        PM_PUSH(5, DCPLB_DATA3)
-        PM_PUSH(6, DCPLB_DATA4)
-        PM_PUSH(7, DCPLB_DATA5)
-        PM_PUSH(8, DCPLB_DATA6)
-        PM_PUSH(9, DCPLB_DATA7)
-        PM_PUSH(10, DCPLB_DATA8)
-        PM_PUSH(11, DCPLB_DATA9)
-        PM_PUSH(12, DCPLB_DATA10)
-        PM_PUSH(13, DCPLB_DATA11)
-        PM_PUSH_SYNC(13)
-        PM_PUSH(0, DCPLB_DATA12)
-        PM_PUSH(1, DCPLB_DATA13)
-        PM_PUSH(2, DCPLB_DATA14)
-        PM_PUSH(3, DCPLB_DATA15)
-        /* ICPLB Addr */
-        FP = I3;
-        PM_PUSH(4, ICPLB_ADDR0)
-        PM_PUSH(5, ICPLB_ADDR1)
-        PM_PUSH(6, ICPLB_ADDR2)
-        PM_PUSH(7, ICPLB_ADDR3)
-        PM_PUSH(8, ICPLB_ADDR4)
-        PM_PUSH(9, ICPLB_ADDR5)
-        PM_PUSH(10, ICPLB_ADDR6)
-        PM_PUSH(11, ICPLB_ADDR7)
-        PM_PUSH(12, ICPLB_ADDR8)
-        PM_PUSH(13, ICPLB_ADDR9)
-        PM_PUSH_SYNC(13)
-        PM_PUSH(0, ICPLB_ADDR10)
-        PM_PUSH(1, ICPLB_ADDR11)
-        PM_PUSH(2, ICPLB_ADDR12)
-        PM_PUSH(3, ICPLB_ADDR13)
-        PM_PUSH(4, ICPLB_ADDR14)
-        PM_PUSH(5, ICPLB_ADDR15)
-        /* ICPLB Data */
-        FP = B0;
-        PM_PUSH(6, ICPLB_DATA0)
-        PM_PUSH(7, ICPLB_DATA1)
-        PM_PUSH(8, ICPLB_DATA2)
-        PM_PUSH(9, ICPLB_DATA3)
-        PM_PUSH(10, ICPLB_DATA4)
-        PM_PUSH(11, ICPLB_DATA5)
-        PM_PUSH(12, ICPLB_DATA6)
-        PM_PUSH(13, ICPLB_DATA7)
-        PM_PUSH_SYNC(13)
-        PM_PUSH(0, ICPLB_DATA8)
-        PM_PUSH(1, ICPLB_DATA9)
-        PM_PUSH(2, ICPLB_DATA10)
-        PM_PUSH(3, ICPLB_DATA11)
-        PM_PUSH(4, ICPLB_DATA12)
-        PM_PUSH(5, ICPLB_DATA13)
-        PM_PUSH(6, ICPLB_DATA14)
-        PM_PUSH(7, ICPLB_DATA15)
-        /* Event Vectors */
-        FP = B1;
-        PM_PUSH(8, EVT2)
-        PM_PUSH(9, EVT3)
-        FP += 4;        /* EVT4 */
-        PM_PUSH(10, EVT5)
-        PM_PUSH(11, EVT6)
-        PM_PUSH(12, EVT7)
-        PM_PUSH(13, EVT8)
-        PM_PUSH_SYNC(13)
-        PM_PUSH(0, EVT9)
-        PM_PUSH(1, EVT10)
-        PM_PUSH(2, EVT11)
-        PM_PUSH(3, EVT12)
-        PM_PUSH(4, EVT13)
-        PM_PUSH(5, EVT14)
-        PM_PUSH(6, EVT15)
-        /* CEC */
-        FP = B2;
-        PM_PUSH(7, IMASK)
-        FP += 4;        /* IPEND */
-        PM_PUSH(8, ILAT)
-        PM_PUSH(9, IPRIO)
-        /* Core Timer */
-        FP = B3;
-        PM_PUSH(10, TCNTL)
-        PM_PUSH(11, TPERIOD)
-        PM_PUSH(12, TSCALE)
-        PM_PUSH(13, TCOUNT)
-        PM_PUSH_SYNC(13)
-        /* Misc non-contiguous registers */
-        FP = I0;
-        PM_CORE_PUSH(0, DMEM_CONTROL);
-        PM_CORE_PUSH(1, IMEM_CONTROL);
-        PM_CORE_PUSH(2, TBUFCTL);
-        PM_PUSH_SYNC(2)
        /* Setup args to hibernate mode early for pipeline optimization */
        R0 = M3;
@@ -618,274 +309,9 @@ ENTRY(_do_hibernate)
 .Lpm_resume_here:
-        /* Restore Core MMRs */
+        bfin_core_mmr_restore;
-        I0.H = hi(COREMMR_BASE);
+        bfin_sys_mmr_restore;
-        I0.L = lo(COREMMR_BASE);
+        bfin_cpu_reg_restore;
-        I1 = I0;
-        I2 = I0;
-        I3 = I0;
-        B0 = I0;
-        B1 = I0;
-        B2 = I0;
-        B3 = I0;
-        I1.L = lo(DCPLB_ADDR15);
-        I2.L = lo(DCPLB_DATA15);
-        I3.L = lo(ICPLB_ADDR15);
-        B0.L = lo(ICPLB_DATA15);
-        B1.L = lo(EVT15);
-        B2.L = lo(IPRIO);
-        B3.L = lo(TCOUNT);
-        /* Misc non-contiguous registers */
-        FP = I0;
-        PM_POP_SYNC(2)
-        PM_CORE_POP(2, TBUFCTL)
-        PM_CORE_POP(1, IMEM_CONTROL)
-        PM_CORE_POP(0, DMEM_CONTROL)
-        /* Core Timer */
-        PM_POP_SYNC(13)
-        FP = B3;
-        PM_POP(13, TCOUNT)
-        PM_POP(12, TSCALE)
-        PM_POP(11, TPERIOD)
-        PM_POP(10, TCNTL)
-        /* CEC */
-        FP = B2;
-        PM_POP(9, IPRIO)
-        PM_POP(8, ILAT)
-        FP += -4;       /* IPEND */
-        PM_POP(7, IMASK)
-        /* Event Vectors */
-        FP = B1;
-        PM_POP(6, EVT15)
-        PM_POP(5, EVT14)
-        PM_POP(4, EVT13)
-        PM_POP(3, EVT12)
-        PM_POP(2, EVT11)
-        PM_POP(1, EVT10)
-        PM_POP(0, EVT9)
-        PM_POP_SYNC(13)
-        PM_POP(13, EVT8)
-        PM_POP(12, EVT7)
-        PM_POP(11, EVT6)
-        PM_POP(10, EVT5)
-        FP += -4;       /* EVT4 */
-        PM_POP(9, EVT3)
-        PM_POP(8, EVT2)
-        /* ICPLB Data */
-        FP = B0;
-        PM_POP(7, ICPLB_DATA15)
-        PM_POP(6, ICPLB_DATA14)
-        PM_POP(5, ICPLB_DATA13)
-        PM_POP(4, ICPLB_DATA12)
-        PM_POP(3, ICPLB_DATA11)
-        PM_POP(2, ICPLB_DATA10)
-        PM_POP(1, ICPLB_DATA9)
-        PM_POP(0, ICPLB_DATA8)
-        PM_POP_SYNC(13)
-        PM_POP(13, ICPLB_DATA7)
-        PM_POP(12, ICPLB_DATA6)
-        PM_POP(11, ICPLB_DATA5)
-        PM_POP(10, ICPLB_DATA4)
-        PM_POP(9, ICPLB_DATA3)
-        PM_POP(8, ICPLB_DATA2)
-        PM_POP(7, ICPLB_DATA1)
-        PM_POP(6, ICPLB_DATA0)
-        /* ICPLB Addr */
-        FP = I3;
-        PM_POP(5, ICPLB_ADDR15)
-        PM_POP(4, ICPLB_ADDR14)
-        PM_POP(3, ICPLB_ADDR13)
-        PM_POP(2, ICPLB_ADDR12)
-        PM_POP(1, ICPLB_ADDR11)
-        PM_POP(0, ICPLB_ADDR10)
-        PM_POP_SYNC(13)
-        PM_POP(13, ICPLB_ADDR9)
-        PM_POP(12, ICPLB_ADDR8)
-        PM_POP(11, ICPLB_ADDR7)
-        PM_POP(10, ICPLB_ADDR6)
-        PM_POP(9, ICPLB_ADDR5)
-        PM_POP(8, ICPLB_ADDR4)
-        PM_POP(7, ICPLB_ADDR3)
-        PM_POP(6, ICPLB_ADDR2)
-        PM_POP(5, ICPLB_ADDR1)
-        PM_POP(4, ICPLB_ADDR0)
-        /* DCPLB Data */
-        FP = I2;
-        PM_POP(3, DCPLB_DATA15)
-        PM_POP(2, DCPLB_DATA14)
-        PM_POP(1, DCPLB_DATA13)
-        PM_POP(0, DCPLB_DATA12)
-        PM_POP_SYNC(13)
-        PM_POP(13, DCPLB_DATA11)
-        PM_POP(12, DCPLB_DATA10)
-        PM_POP(11, DCPLB_DATA9)
-        PM_POP(10, DCPLB_DATA8)
-        PM_POP(9, DCPLB_DATA7)
-        PM_POP(8, DCPLB_DATA6)
-        PM_POP(7, DCPLB_DATA5)
-        PM_POP(6, DCPLB_DATA4)
-        PM_POP(5, DCPLB_DATA3)
-        PM_POP(4, DCPLB_DATA2)
-        PM_POP(3, DCPLB_DATA1)
-        PM_POP(2, DCPLB_DATA0)
-        /* DCPLB Addr */
-        FP = I1;
-        PM_POP(1, DCPLB_ADDR15)
-        PM_POP(0, DCPLB_ADDR14)
-        PM_POP_SYNC(13)
-        PM_POP(13, DCPLB_ADDR13)
-        PM_POP(12, DCPLB_ADDR12)
-        PM_POP(11, DCPLB_ADDR11)
-        PM_POP(10, DCPLB_ADDR10)
-        PM_POP(9, DCPLB_ADDR9)
-        PM_POP(8, DCPLB_ADDR8)
-        PM_POP(7, DCPLB_ADDR7)
-        PM_POP(6, DCPLB_ADDR6)
-        PM_POP(5, DCPLB_ADDR5)
-        PM_POP(4, DCPLB_ADDR4)
-        PM_POP(3, DCPLB_ADDR3)
-        PM_POP(2, DCPLB_ADDR2)
-        PM_POP(1, DCPLB_ADDR1)
-        PM_POP(0, DCPLB_ADDR0)
-        /* Restore System MMRs */
-        FP.H = hi(SYSMMR_BASE);
-        FP.L = lo(SYSMMR_BASE);
-#ifdef EBIU_FCTL
-        PM_POP_SYNC(12)
-        PM_SYS_POP(12, EBIU_FCTL)
-        PM_SYS_POP(11, EBIU_MODE)
-        PM_SYS_POP(10, EBIU_MBSCTL)
-#else
-        PM_POP_SYNC(9)
-#endif
-        PM_SYS_POP(9, EBIU_AMBCTL1)
-        PM_SYS_POP(8, EBIU_AMBCTL0)
-        PM_SYS_POP16(7, EBIU_AMGCTL)
-        PM_SYS_POP16(6, SYSCR)
-#ifdef PINT0_ASSIGN
-        PM_SYS_POP(5, PINT3_EDGE_SET)
-        PM_SYS_POP(4, PINT2_EDGE_SET)
-        PM_SYS_POP(3, PINT1_EDGE_SET)
-        PM_SYS_POP(2, PINT0_EDGE_SET)
-        PM_SYS_POP(1, PINT3_INVERT_SET)
-        PM_SYS_POP(0, PINT2_INVERT_SET)
-        PM_POP_SYNC(13)
-        PM_SYS_POP(13, PINT1_INVERT_SET)
-        PM_SYS_POP(12, PINT0_INVERT_SET)
-        PM_SYS_POP(11, PINT3_ASSIGN)
-        PM_SYS_POP(10, PINT2_ASSIGN)
-        PM_SYS_POP(9, PINT1_ASSIGN)
-        PM_SYS_POP(8, PINT0_ASSIGN)
-        PM_SYS_POP(7, PINT3_MASK_SET)
-        PM_SYS_POP(6, PINT2_MASK_SET)
-        PM_SYS_POP(5, PINT1_MASK_SET)
-        PM_SYS_POP(4, PINT0_MASK_SET)
-#endif
-#ifdef SIC_IWR2
-        PM_SYS_POP(3, SIC_IWR2)
-#endif
-#ifdef SIC_IWR1
-        PM_SYS_POP(2, SIC_IWR1)
-#endif
-#ifdef SIC_IWR0
-        PM_SYS_POP(1, SIC_IWR0)
-#endif
-#ifdef SIC_IWR
-        PM_SYS_POP(1, SIC_IWR)
-#endif
-#ifdef SIC_IAR11
-        PM_SYS_POP(0, SIC_IAR11)
-#endif
-        PM_POP_SYNC(13)
-#ifdef SIC_IAR8
-        PM_SYS_POP(13, SIC_IAR10)
-        PM_SYS_POP(12, SIC_IAR9)
-        PM_SYS_POP(11, SIC_IAR8)
-#endif
-#ifdef SIC_IAR7
-        PM_SYS_POP(10, SIC_IAR7)
-#endif
-#ifdef SIC_IAR6
-        PM_SYS_POP(9, SIC_IAR6)
-        PM_SYS_POP(8, SIC_IAR5)
-        PM_SYS_POP(7, SIC_IAR4)
-#endif
-#ifdef SIC_IAR3
-        PM_SYS_POP(6, SIC_IAR3)
-#endif
-#ifdef SIC_IAR0
-        PM_SYS_POP(5, SIC_IAR2)
-        PM_SYS_POP(4, SIC_IAR1)
-        PM_SYS_POP(3, SIC_IAR0)
-#endif
-#ifdef SIC_IMASK0
-# ifdef SIC_IMASK2
-        PM_SYS_POP(2, SIC_IMASK2)
-# endif
-        PM_SYS_POP(1, SIC_IMASK1)
-        PM_SYS_POP(0, SIC_IMASK0)
-#else
-        PM_SYS_POP(0, SIC_IMASK)
-#endif
-        /* Restore Core Registers */
-        RETI = [sp++];
-        SEQSTAT = [sp++];
-        RETX = [sp++];
-        SYSCFG = [sp++];
-        CYCLES2 = [sp++];
-        CYCLES = [sp++];
-        ASTAT = [sp++];
-        RETS = [sp++];
-        LB1 = [sp++];
-        LB0 = [sp++];
-        LT1 = [sp++];
-        LT0 = [sp++];
-        LC1 = [sp++];
-        LC0 = [sp++];
-        a1.w = [sp++];
-        a1.x = [sp++];
-        a0.w = [sp++];
-        a0.x = [sp++];
-        b3 = [sp++];
-        b2 = [sp++];
-        b1 = [sp++];
-        b0 = [sp++];
-        l3 = [sp++];
-        l2 = [sp++];
-        l1 = [sp++];
-        l0 = [sp++];
-        m3 = [sp++];
-        m2 = [sp++];
-        m1 = [sp++];
-        m0 = [sp++];
-        i3 = [sp++];
-        i2 = [sp++];
-        i1 = [sp++];
-        i0 = [sp++];
-        usp = [sp++];
-        fp = [sp++];
-        (R7:0, P5:0) = [sp++];
        [--sp] = RETI;  /* Clear Global Interrupt Disable */
        SP += 4;
diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S
index 4698a9800522..80aa2535e2c9 100644
--- a/arch/blackfin/mach-common/entry.S
+++ b/arch/blackfin/mach-common/entry.S
@@ -1141,7 +1141,8 @@ ENTRY(_schedule_and_signal_from_int)
        sti r0;
        /* finish the userspace "atomic" functions for it */
-        r1 = FIXED_CODE_END;
+        r1.l = lo(FIXED_CODE_END);
+        r1.h = hi(FIXED_CODE_END);
        r2 = [sp + PT_PC];
        cc = r1 <= r2;
        if cc jump .Lresume_userspace (bp);
@@ -1376,7 +1377,7 @@ END(_ex_table)
 ENTRY(_sys_call_table)
        .long _sys_restart_syscall      /* 0 */
        .long _sys_exit
-        .long _sys_fork
+        .long _sys_ni_syscall   /* fork */
        .long _sys_read
        .long _sys_write
        .long _sys_open         /* 5 */
diff --git a/arch/blackfin/mach-common/head.S b/arch/blackfin/mach-common/head.S
index 8b4d98854403..31515f0146f9 100644
--- a/arch/blackfin/mach-common/head.S
+++ b/arch/blackfin/mach-common/head.S
@@ -210,14 +210,12 @@ ENDPROC(__start)
 ENTRY(_real_start)
        /* Enable nested interrupts */
        [--sp] = reti;
        /* watchdog off for now */
        p0.l = lo(WDOG_CTL);
        p0.h = hi(WDOG_CTL);
        r0 = 0xAD6(z);
        w[p0] = r0;
        ssync;
        /* Pass the u-boot arguments to the global value command line */
        R0 = R7;
        call _cmdline_init;
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c
index 332dace6af34..2729cba715b0 100644
--- a/arch/blackfin/mach-common/ints-priority.c
+++ b/arch/blackfin/mach-common/ints-priority.c
@@ -16,6 +16,8 @@
 #include <linux/seq_file.h>
 #include <linux/irq.h>
 #include <linux/sched.h>
+#include <linux/syscore_ops.h>
+#include <asm/delay.h>
 #ifdef CONFIG_IPIPE
 #include <linux/ipipe.h>
 #endif
@@ -25,7 +27,11 @@
 #include <asm/irq_handler.h>
 #include <asm/dpmc.h>
-#define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1))
+#ifndef CONFIG_BF60x
+# define SIC_SYSIRQ(irq)        (irq - (IRQ_CORETMR + 1))
+#else
+# define SIC_SYSIRQ(irq)        ((irq) - IVG15)
+#endif
 /*
 * NOTES:
@@ -50,6 +56,7 @@ unsigned long bfin_sic_iwr[3];	/* Up to 3 SIC_IWRx registers */
 unsigned vr_wakeup;
 #endif
+#ifndef CONFIG_BF60x
 static struct ivgx {
        /* irq number for request_irq, available in mach-bf5xx/irq.h */
        unsigned int irqno;
@@ -78,7 +85,8 @@ static void __init search_IAR(void)
                for (irqN = 0; irqN < NR_PERI_INTS; irqN += 4) {
                        int irqn;
-                        u32 iar = bfin_read32((unsigned long *)SIC_IAR0 +
+                        u32 iar =
+                                bfin_read32((unsigned long *)SIC_IAR0 +
 #if defined(CONFIG_BF51x) || defined(CONFIG_BF52x) || \
        defined(CONFIG_BF538) || defined(CONFIG_BF539)
                                ((irqN % 32) >> 3) + ((irqN / 32) * ((SIC_IAR4 - SIC_IAR0) / 4))
@@ -86,7 +94,6 @@ static void __init search_IAR(void)
                                (irqN >> 3)
 #endif
                                );
                        for (irqn = irqN; irqn < irqN + 4; ++irqn) {
                                int iar_shift = (irqn & 7) * 4;
                                if (ivg == (0xf & (iar >> iar_shift))) {
@@ -99,11 +106,11 @@ static void __init search_IAR(void)
                }
        }
 }
+#endif
 /*
 * This is for core internal IRQs
 */
 void bfin_ack_noop(struct irq_data *d)
 {
        /* Dummy function.  */
@@ -136,21 +143,21 @@ static void bfin_core_unmask_irq(struct irq_data *d)
 void bfin_internal_mask_irq(unsigned int irq)
 {
        unsigned long flags = hard_local_irq_save();
+#ifndef CONFIG_BF60x
 #ifdef SIC_IMASK0
        unsigned mask_bank = SIC_SYSIRQ(irq) / 32;
        unsigned mask_bit = SIC_SYSIRQ(irq) % 32;
        bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
-                             ~(1 << mask_bit));
+                        ~(1 << mask_bit));
-# ifdef CONFIG_SMP
+# if defined(CONFIG_SMP) || defined(CONFIG_ICC)
        bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) &
-                             ~(1 << mask_bit));
+                        ~(1 << mask_bit));
 # endif
 #else
        bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
-                             ~(1 << SIC_SYSIRQ(irq)));
+                        ~(1 << SIC_SYSIRQ(irq)));
+#endif /* end of SIC_IMASK0 */
 #endif
        hard_local_irq_restore(flags);
 }
@@ -160,7 +167,7 @@ static void bfin_internal_mask_irq_chip(struct irq_data *d)
 }
 #ifdef CONFIG_SMP
-static void bfin_internal_unmask_irq_affinity(unsigned int irq,
+void bfin_internal_unmask_irq_affinity(unsigned int irq,
                const struct cpumask *affinity)
 #else
 void bfin_internal_unmask_irq(unsigned int irq)
@@ -168,6 +175,7 @@ void bfin_internal_unmask_irq(unsigned int irq)
 {
        unsigned long flags = hard_local_irq_save();
+#ifndef CONFIG_BF60x
 #ifdef SIC_IMASK0
        unsigned mask_bank = SIC_SYSIRQ(irq) / 32;
        unsigned mask_bit = SIC_SYSIRQ(irq) % 32;
@@ -175,22 +183,239 @@ void bfin_internal_unmask_irq(unsigned int irq)
        if (cpumask_test_cpu(0, affinity))
 # endif
                bfin_write_SIC_IMASK(mask_bank,
-                        bfin_read_SIC_IMASK(mask_bank) |
+                                bfin_read_SIC_IMASK(mask_bank) |
-                        (1 << mask_bit));
+                                (1 << mask_bit));
 # ifdef CONFIG_SMP
        if (cpumask_test_cpu(1, affinity))
                bfin_write_SICB_IMASK(mask_bank,
-                        bfin_read_SICB_IMASK(mask_bank) |
+                                bfin_read_SICB_IMASK(mask_bank) |
-                        (1 << mask_bit));
+                                (1 << mask_bit));
 # endif
 #else
        bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
-                             (1 << SIC_SYSIRQ(irq)));
+                        (1 << SIC_SYSIRQ(irq)));
+#endif
 #endif
+        hard_local_irq_restore(flags);
+}
+#ifdef CONFIG_BF60x
+static void bfin_sec_preflow_handler(struct irq_data *d)
+{
+        unsigned long flags = hard_local_irq_save();
+        unsigned int sid = SIC_SYSIRQ(d->irq);
+        bfin_write_SEC_SCI(0, SEC_CSID, sid);
+        hard_local_irq_restore(flags);
+}
+static void bfin_sec_mask_ack_irq(struct irq_data *d)
+{
+        unsigned long flags = hard_local_irq_save();
+        unsigned int sid = SIC_SYSIRQ(d->irq);
+        bfin_write_SEC_SCI(0, SEC_CSID, sid);
        hard_local_irq_restore(flags);
 }
+static void bfin_sec_unmask_irq(struct irq_data *d)
+{
+        unsigned long flags = hard_local_irq_save();
+        unsigned int sid = SIC_SYSIRQ(d->irq);
+        bfin_write32(SEC_END, sid);
+        hard_local_irq_restore(flags);
+}
+static void bfin_sec_enable_ssi(unsigned int sid)
+{
+        unsigned long flags = hard_local_irq_save();
+        uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
+        reg_sctl |= SEC_SCTL_SRC_EN;
+        bfin_write_SEC_SCTL(sid, reg_sctl);
+        hard_local_irq_restore(flags);
+}
+static void bfin_sec_disable_ssi(unsigned int sid)
+{
+        unsigned long flags = hard_local_irq_save();
+        uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
+        reg_sctl &= ((uint32_t)~SEC_SCTL_SRC_EN);
+        bfin_write_SEC_SCTL(sid, reg_sctl);
+        hard_local_irq_restore(flags);
+}
+static void bfin_sec_set_ssi_coreid(unsigned int sid, unsigned int coreid)
+{
+        unsigned long flags = hard_local_irq_save();
+        uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
+        reg_sctl &= ((uint32_t)~SEC_SCTL_CTG);
+        bfin_write_SEC_SCTL(sid, reg_sctl | ((coreid << 20) & SEC_SCTL_CTG));
+        hard_local_irq_restore(flags);
+}
+static void bfin_sec_enable_sci(unsigned int sid)
+{
+        unsigned long flags = hard_local_irq_save();
+        uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
+        if (sid == SIC_SYSIRQ(IRQ_WATCH0))
+                reg_sctl |= SEC_SCTL_FAULT_EN;
+        else
+                reg_sctl |= SEC_SCTL_INT_EN;
+        bfin_write_SEC_SCTL(sid, reg_sctl);
+        hard_local_irq_restore(flags);
+}
+static void bfin_sec_disable_sci(unsigned int sid)
+{
+        unsigned long flags = hard_local_irq_save();
+        uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
+        reg_sctl &= ((uint32_t)~SEC_SCTL_INT_EN);
+        bfin_write_SEC_SCTL(sid, reg_sctl);
+        hard_local_irq_restore(flags);
+}
+static void bfin_sec_enable(struct irq_data *d)
+{
+        unsigned long flags = hard_local_irq_save();
+        unsigned int sid = SIC_SYSIRQ(d->irq);
+        bfin_sec_enable_sci(sid);
+        bfin_sec_enable_ssi(sid);
+        hard_local_irq_restore(flags);
+}
+static void bfin_sec_disable(struct irq_data *d)
+{
+        unsigned long flags = hard_local_irq_save();
+        unsigned int sid = SIC_SYSIRQ(d->irq);
+        bfin_sec_disable_sci(sid);
+        bfin_sec_disable_ssi(sid);
+        hard_local_irq_restore(flags);
+}
+static void bfin_sec_raise_irq(unsigned int sid)
+{
+        unsigned long flags = hard_local_irq_save();
+        bfin_write32(SEC_RAISE, sid);
+        hard_local_irq_restore(flags);
+}
+static void init_software_driven_irq(void)
+{
+        bfin_sec_set_ssi_coreid(34, 0);
+        bfin_sec_set_ssi_coreid(35, 1);
+        bfin_sec_set_ssi_coreid(36, 0);
+        bfin_sec_set_ssi_coreid(37, 1);
+}
+void bfin_sec_resume(void)
+{
+        bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET);
+        udelay(100);
+        bfin_write_SEC_GCTL(SEC_GCTL_EN);
+        bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
+}
+void handle_sec_sfi_fault(uint32_t gstat)
+{
+}
+void handle_sec_sci_fault(uint32_t gstat)
+{
+        uint32_t core_id;
+        uint32_t cstat;
+        core_id = gstat & SEC_GSTAT_SCI;
+        cstat = bfin_read_SEC_SCI(core_id, SEC_CSTAT);
+        if (cstat & SEC_CSTAT_ERR) {
+                switch (cstat & SEC_CSTAT_ERRC) {
+                case SEC_CSTAT_ACKERR:
+                        printk(KERN_DEBUG "sec ack err\n");
+                        break;
+                default:
+                        printk(KERN_DEBUG "sec sci unknow err\n");
+                }
+        }
+}
+void handle_sec_ssi_fault(uint32_t gstat)
+{
+        uint32_t sid;
+        uint32_t sstat;
+        sid = gstat & SEC_GSTAT_SID;
+        sstat = bfin_read_SEC_SSTAT(sid);
+}
+void handle_sec_fault(unsigned int irq, struct irq_desc *desc)
+{
+        uint32_t sec_gstat;
+        raw_spin_lock(&desc->lock);
+        sec_gstat = bfin_read32(SEC_GSTAT);
+        if (sec_gstat & SEC_GSTAT_ERR) {
+                switch (sec_gstat & SEC_GSTAT_ERRC) {
+                case 0:
+                        handle_sec_sfi_fault(sec_gstat);
+                        break;
+                case SEC_GSTAT_SCIERR:
+                        handle_sec_sci_fault(sec_gstat);
+                        break;
+                case SEC_GSTAT_SSIERR:
+                        handle_sec_ssi_fault(sec_gstat);
+                        break;
+                }
+        }
+        raw_spin_unlock(&desc->lock);
+}
+static int sec_suspend(void)
+{
+        return 0;
+}
+static void sec_resume(void)
+{
+        bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET);
+        udelay(100);
+        bfin_write_SEC_GCTL(SEC_GCTL_EN);
+        bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
+}
+static struct syscore_ops sec_pm_syscore_ops = {
+        .suspend = sec_suspend,
+        .resume = sec_resume,
+};
+#endif
 #ifdef CONFIG_SMP
 static void bfin_internal_unmask_irq_chip(struct irq_data *d)
 {
@@ -212,7 +437,7 @@ static void bfin_internal_unmask_irq_chip(struct irq_data *d)
 }
 #endif
-#ifdef CONFIG_PM
+#if defined(CONFIG_PM) && !defined(CONFIG_BF60x)
 int bfin_internal_set_wake(unsigned int irq, unsigned int state)
 {
        u32 bank, bit, wakeup = 0;
@@ -271,22 +496,20 @@ static int bfin_internal_set_wake_chip(struct irq_data *d, unsigned int state)
        return bfin_internal_set_wake(d->irq, state);
 }
 #else
+# define bfin_internal_set_wake(irq, state)
 # define bfin_internal_set_wake_chip NULL
 #endif
 static struct irq_chip bfin_core_irqchip = {
        .name = "CORE",
-        .irq_ack = bfin_ack_noop,
        .irq_mask = bfin_core_mask_irq,
        .irq_unmask = bfin_core_unmask_irq,
 };
 static struct irq_chip bfin_internal_irqchip = {
        .name = "INTN",
-        .irq_ack = bfin_ack_noop,
        .irq_mask = bfin_internal_mask_irq_chip,
        .irq_unmask = bfin_internal_unmask_irq_chip,
-        .irq_mask_ack = bfin_internal_mask_irq_chip,
        .irq_disable = bfin_internal_mask_irq_chip,
        .irq_enable = bfin_internal_unmask_irq_chip,
 #ifdef CONFIG_SMP
@@ -295,6 +518,18 @@ static struct irq_chip bfin_internal_irqchip = {
        .irq_set_wake = bfin_internal_set_wake_chip,
 };
+#ifdef CONFIG_BF60x
+static struct irq_chip bfin_sec_irqchip = {
+        .name = "SEC",
+        .irq_mask_ack = bfin_sec_mask_ack_irq,
+        .irq_mask = bfin_sec_mask_ack_irq,
+        .irq_unmask = bfin_sec_unmask_irq,
+        .irq_eoi = bfin_sec_unmask_irq,
+        .irq_disable = bfin_sec_disable,
+        .irq_enable = bfin_sec_enable,
+};
+#endif
 void bfin_handle_irq(unsigned irq)
 {
 #ifdef CONFIG_IPIPE
@@ -396,8 +631,6 @@ int bfin_mac_status_set_wake(struct irq_data *d, unsigned int state)
 static struct irq_chip bfin_mac_status_irqchip = {
        .name = "MACST",
-        .irq_ack = bfin_ack_noop,
-        .irq_mask_ack = bfin_mac_status_mask_irq,
        .irq_mask = bfin_mac_status_mask_irq,
        .irq_unmask = bfin_mac_status_unmask_irq,
        .irq_set_wake = bfin_mac_status_set_wake,
@@ -421,15 +654,15 @@ void bfin_demux_mac_status_irq(unsigned int int_err_irq,
                } else {
                        bfin_mac_status_ack_irq(irq);
                        pr_debug("IRQ %d:"
-                                 " MASKED MAC ERROR INTERRUPT ASSERTED\n",
+                                        " MASKED MAC ERROR INTERRUPT ASSERTED\n",
-                                 irq);
+                                        irq);
                }
        } else
                printk(KERN_ERR
-                       "%s : %s : LINE %d :\nIRQ ?: MAC ERROR"
+                                "%s : %s : LINE %d :\nIRQ ?: MAC ERROR"
-                       " INTERRUPT ASSERTED BUT NO SOURCE FOUND"
+                                " INTERRUPT ASSERTED BUT NO SOURCE FOUND"
-                       "(EMAC_SYSTAT=0x%X)\n",
+                                "(EMAC_SYSTAT=0x%X)\n",
-                       __func__, __FILE__, __LINE__, status);
+                                __func__, __FILE__, __LINE__, status);
 }
 #endif
@@ -583,7 +816,7 @@ static void bfin_demux_gpio_block(unsigned int irq)
 }
 void bfin_demux_gpio_irq(unsigned int inta_irq,
-                         struct irq_desc *desc)
+                        struct irq_desc *desc)
 {
        unsigned int irq;
@@ -635,9 +868,15 @@ void bfin_demux_gpio_irq(unsigned int inta_irq,
 #else
+# ifndef CONFIG_BF60x
 #define NR_PINT_SYS_IRQS        4
-#define NR_PINT_BITS            32
 #define NR_PINTS                160
+# else
+#define NR_PINT_SYS_IRQS        6
+#define NR_PINTS                112
+#endif
+#define NR_PINT_BITS            32
 #define IRQ_NOT_AVAIL           0xFF
 #define PINT_2_BANK(x)          ((x) >> 5)
@@ -652,8 +891,13 @@ static struct bfin_pint_regs * const pint[NR_PINT_SYS_IRQS] = {
        (struct bfin_pint_regs *)PINT1_MASK_SET,
        (struct bfin_pint_regs *)PINT2_MASK_SET,
        (struct bfin_pint_regs *)PINT3_MASK_SET,
+#ifdef CONFIG_BF60x
+        (struct bfin_pint_regs *)PINT4_MASK_SET,
+        (struct bfin_pint_regs *)PINT5_MASK_SET,
+#endif
 };
+#ifndef CONFIG_BF60x
 inline unsigned int get_irq_base(u32 bank, u8 bmap)
 {
        unsigned int irq_base;
@@ -666,6 +910,16 @@ inline unsigned int get_irq_base(u32 bank, u8 bmap)
        return irq_base;
 }
+#else
+inline unsigned int get_irq_base(u32 bank, u8 bmap)
+{
+        unsigned int irq_base;
+        irq_base = IRQ_PA0 + bank * 16 + bmap * 16;
+        return irq_base;
+}
+#endif
        /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
 void init_pint_lut(void)
@@ -854,6 +1108,14 @@ static int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
        case 1:
                pint_irq = IRQ_PINT1;
                break;
+#ifdef CONFIG_BF60x
+        case 4:
+                pint_irq = IRQ_PINT4;
+                break;
+        case 5:
+                pint_irq = IRQ_PINT5;
+                break;
+#endif
        default:
                return -EINVAL;
        }
@@ -867,10 +1129,21 @@ static int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
 #endif
 void bfin_demux_gpio_irq(unsigned int inta_irq,
-                         struct irq_desc *desc)
+                        struct irq_desc *desc)
 {
        u32 bank, pint_val;
        u32 request, irq;
+        u32 level_mask;
+        int umask = 0;
+        struct irq_chip *chip = irq_desc_get_chip(desc);
+        if (chip->irq_mask_ack) {
+                chip->irq_mask_ack(&desc->irq_data);
+        } else {
+                chip->irq_mask(&desc->irq_data);
+                if (chip->irq_ack)
+                        chip->irq_ack(&desc->irq_data);
+        }
        switch (inta_irq) {
        case IRQ_PINT0:
@@ -885,6 +1158,14 @@ void bfin_demux_gpio_irq(unsigned int inta_irq,
        case IRQ_PINT1:
                bank = 1;
                break;
+#ifdef CONFIG_BF60x
+        case IRQ_PINT4:
+                bank = 4;
+                break;
+        case IRQ_PINT5:
+                bank = 5;
+                break;
+#endif
        default:
                return;
        }
@@ -893,15 +1174,23 @@ void bfin_demux_gpio_irq(unsigned int inta_irq,
        request = pint[bank]->request;
+        level_mask = pint[bank]->edge_set & request;
        while (request) {
                if (request & 1) {
                        irq = pint2irq_lut[pint_val] + SYS_IRQS;
+                        if (level_mask & PINT_BIT(pint_val)) {
+                                umask = 1;
+                                chip->irq_unmask(&desc->irq_data);
+                        }
                        bfin_handle_irq(irq);
                }
                pint_val++;
                request >>= 1;
        }
+        if (!umask)
+                chip->irq_unmask(&desc->irq_data);
 }
 #endif
@@ -951,6 +1240,7 @@ int __init init_arch_irq(void)
        int irq;
        unsigned long ilat = 0;
+#ifndef CONFIG_BF60x
        /*  Disable all the peripheral intrs  - page 4-29 HW Ref manual */
 #ifdef SIC_IMASK0
        bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
@@ -958,13 +1248,16 @@ int __init init_arch_irq(void)
 # ifdef SIC_IMASK2
        bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
 # endif
-# ifdef CONFIG_SMP
+# if defined(CONFIG_SMP) || defined(CONFIG_ICC)
        bfin_write_SICB_IMASK0(SIC_UNMASK_ALL);
        bfin_write_SICB_IMASK1(SIC_UNMASK_ALL);
 # endif
 #else
        bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
 #endif
+#else /* CONFIG_BF60x */
+        bfin_write_SEC_GCTL(SEC_GCTL_RESET);
+#endif
        local_irq_disable();
@@ -974,6 +1267,10 @@ int __init init_arch_irq(void)
        pint[1]->assign = CONFIG_PINT1_ASSIGN;
        pint[2]->assign = CONFIG_PINT2_ASSIGN;
        pint[3]->assign = CONFIG_PINT3_ASSIGN;
+# ifdef CONFIG_BF60x
+        pint[4]->assign = CONFIG_PINT4_ASSIGN;
+        pint[5]->assign = CONFIG_PINT5_ASSIGN;
+# endif
 # endif
        /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
        init_pint_lut();
@@ -986,6 +1283,7 @@ int __init init_arch_irq(void)
                        irq_set_chip(irq, &bfin_internal_irqchip);
                switch (irq) {
+#ifndef CONFIG_BF60x
 #if BFIN_GPIO_PINT
                case IRQ_PINT0:
                case IRQ_PINT1:
@@ -1015,12 +1313,13 @@ int __init init_arch_irq(void)
                                                bfin_demux_mac_status_irq);
                        break;
 #endif
-#ifdef CONFIG_SMP
+#if defined(CONFIG_SMP) || defined(CONFIG_ICC)
                case IRQ_SUPPLE_0:
                case IRQ_SUPPLE_1:
                        irq_set_handler(irq, handle_percpu_irq);
                        break;
 #endif
+#endif
 #ifdef CONFIG_TICKSOURCE_CORETMR
                case IRQ_CORETMR:
@@ -1050,7 +1349,8 @@ int __init init_arch_irq(void)
        init_mach_irq();
-#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
+#ifndef CONFIG_BF60x
+#if (defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)) && !defined(CONFIG_BF60x)
        for (irq = IRQ_MAC_PHYINT; irq <= IRQ_MAC_STMDONE; irq++)
                irq_set_chip_and_handler(irq, &bfin_mac_status_irqchip,
                                         handle_level_irq);
@@ -1060,7 +1360,28 @@ int __init init_arch_irq(void)
                irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++)
                irq_set_chip_and_handler(irq, &bfin_gpio_irqchip,
                                         handle_level_irq);
+#else
+        for (irq = BFIN_IRQ(0); irq <= SYS_IRQS; irq++) {
+                if (irq < CORE_IRQS) {
+                        irq_set_chip(irq, &bfin_sec_irqchip);
+                        __irq_set_handler(irq, handle_sec_fault, 0, NULL);
+                } else if (irq >= BFIN_IRQ(21) && irq <= BFIN_IRQ(26)) {
+                        irq_set_chip(irq, &bfin_sec_irqchip);
+                        irq_set_chained_handler(irq, bfin_demux_gpio_irq);
+                } else if (irq >= BFIN_IRQ(34) && irq <= BFIN_IRQ(37)) {
+                        irq_set_chip(irq, &bfin_sec_irqchip);
+                        irq_set_handler(irq, handle_percpu_irq);
+                } else {
+                        irq_set_chip_and_handler(irq, &bfin_sec_irqchip,
+                                        handle_fasteoi_irq);
+                        __irq_set_preflow_handler(irq, bfin_sec_preflow_handler);
+                }
+        }
+        for (irq = GPIO_IRQ_BASE;
+                irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++)
+                irq_set_chip_and_handler(irq, &bfin_gpio_irqchip,
+                                        handle_level_irq);
+#endif
        bfin_write_IMASK(0);
        CSYNC();
        ilat = bfin_read_ILAT();
@@ -1072,14 +1393,17 @@ int __init init_arch_irq(void)
        /* IMASK=xxx is equivalent to STI xx or bfin_irq_flags=xx,
         * local_irq_enable()
         */
+#ifndef CONFIG_BF60x
        program_IAR();
        /* Therefore it's better to setup IARs before interrupts enabled */
        search_IAR();
        /* Enable interrupts IVG7-15 */
        bfin_irq_flags |= IMASK_IVG15 |
-            IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
+                IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
-            IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
+                IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
+        bfin_sti(bfin_irq_flags);
        /* This implicitly covers ANOMALY_05000171
         * Boot-ROM code modifies SICA_IWRx wakeup registers
@@ -1103,7 +1427,23 @@ int __init init_arch_irq(void)
 #else
        bfin_write_SIC_IWR(IWR_DISABLE_ALL);
 #endif
+#else  /* CONFIG_BF60x */
+        /* Enable interrupts IVG7-15 */
+        bfin_irq_flags |= IMASK_IVG15 |
+            IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
+            IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
+        bfin_write_SEC_FCTL(SEC_FCTL_EN | SEC_FCTL_SYSRST_EN | SEC_FCTL_FLTIN_EN);
+        bfin_sec_enable_sci(SIC_SYSIRQ(IRQ_WATCH0));
+        bfin_sec_enable_ssi(SIC_SYSIRQ(IRQ_WATCH0));
+        bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET);
+        udelay(100);
+        bfin_write_SEC_GCTL(SEC_GCTL_EN);
+        bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
+        init_software_driven_irq();
+        register_syscore_ops(&sec_pm_syscore_ops);
+#endif
        return 0;
 }
@@ -1112,13 +1452,14 @@ __attribute__((l1_text))
 #endif
 static int vec_to_irq(int vec)
 {
+#ifndef CONFIG_BF60x
        struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
        struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
        unsigned long sic_status[3];
+#endif
        if (likely(vec == EVT_IVTMR_P))
                return IRQ_CORETMR;
+#ifndef CONFIG_BF60x
 #ifdef SIC_ISR
        sic_status[0] = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
 #else
@@ -1147,6 +1488,10 @@ static int vec_to_irq(int vec)
 #endif
                        return ivg->irqno;
        }
+#else
+        /* for bf60x read */
+        return BFIN_IRQ(bfin_read_SEC_SCI(0, SEC_CSID));
+#endif  /* end of CONFIG_BF60x */
 }
 #ifdef CONFIG_DO_IRQ_L1
diff --git a/arch/blackfin/mach-common/pm.c b/arch/blackfin/mach-common/pm.c
index 3c648a077e75..ca6655e0d653 100644
--- a/arch/blackfin/mach-common/pm.c
+++ b/arch/blackfin/mach-common/pm.c
@@ -19,20 +19,33 @@
 #include <asm/gpio.h>
 #include <asm/dma.h>
 #include <asm/dpmc.h>
+#include <asm/pm.h>
+#ifdef CONFIG_BF60x
+struct bfin_cpu_pm_fns *bfin_cpu_pm;
+#endif
 void bfin_pm_suspend_standby_enter(void)
 {
+#ifndef CONFIG_BF60x
        bfin_pm_standby_setup();
+#endif
-#ifdef CONFIG_PM_BFIN_SLEEP_DEEPER
+#ifdef CONFIG_BF60x
-        sleep_deeper(bfin_sic_iwr[0], bfin_sic_iwr[1], bfin_sic_iwr[2]);
+        bfin_cpu_pm->enter(PM_SUSPEND_STANDBY);
 #else
+# ifdef CONFIG_PM_BFIN_SLEEP_DEEPER
+        sleep_deeper(bfin_sic_iwr[0], bfin_sic_iwr[1], bfin_sic_iwr[2]);
+# else
        sleep_mode(bfin_sic_iwr[0], bfin_sic_iwr[1], bfin_sic_iwr[2]);
+# endif
 #endif
+#ifndef CONFIG_BF60x
        bfin_pm_standby_restore();
+#endif
+#ifndef CONFIG_BF60x
 #ifdef SIC_IWR0
        bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
 # ifdef SIC_IWR1
@@ -52,6 +65,8 @@ void bfin_pm_suspend_standby_enter(void)
 #else
        bfin_write_SIC_IWR(IWR_DISABLE_ALL);
 #endif
+#endif
 }
 int bf53x_suspend_l1_mem(unsigned char *memptr)
@@ -83,10 +98,13 @@ int bf53x_resume_l1_mem(unsigned char *memptr)
 }
 #if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
+# ifdef CONFIG_BF60x
+__attribute__((l1_text))
+# endif
 static void flushinv_all_dcache(void)
 {
-        u32 way, bank, subbank, set;
+        register u32 way, bank, subbank, set;
-        u32 status, addr;
+        register u32 status, addr;
        u32 dmem_ctl = bfin_read_DMEM_CONTROL();
        for (bank = 0; bank < 2; ++bank) {
@@ -133,6 +151,7 @@ int bfin_pm_suspend_mem_enter(void)
                return -ENOMEM;
        }
+#ifndef CONFIG_BF60x
        wakeup = bfin_read_VR_CTL() & ~FREQ;
        wakeup |= SCKELOW;
@@ -142,6 +161,7 @@ int bfin_pm_suspend_mem_enter(void)
 #ifdef CONFIG_PM_BFIN_WAKE_GP
        wakeup |= GPWE;
 #endif
+#endif
        ret = blackfin_dma_suspend();
@@ -159,7 +179,11 @@ int bfin_pm_suspend_mem_enter(void)
        _disable_icplb();
        bf53x_suspend_l1_mem(memptr);
+#ifndef CONFIG_BF60x
        do_hibernate(wakeup | vr_wakeup);       /* See you later! */
+#else
+        bfin_cpu_pm->enter(PM_SUSPEND_MEM);
+#endif
        bf53x_resume_l1_mem(memptr);
@@ -223,9 +247,39 @@ static int bfin_pm_enter(suspend_state_t state)
        return 0;
 }
+#ifdef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH
+void bfin_pm_end(void)
+{
+        u32 cycle, cycle2;
+        u64 usec64;
+        u32 usec;
+        __asm__ __volatile__ (
+                "1: %0 = CYCLES2\n"
+                "%1 = CYCLES\n"
+                "%2 = CYCLES2\n"
+                "CC = %2 == %0\n"
+                "if ! CC jump 1b\n"
+                : "=d,a" (cycle2), "=d,a" (cycle), "=d,a" (usec) : : "CC"
+        );
+        usec64 = ((u64)cycle2 << 32) + cycle;
+        do_div(usec64, get_cclk() / USEC_PER_SEC);
+        usec = usec64;
+        if (usec == 0)
+                usec = 1;
+        pr_info("PM: resume of kernel completes after  %ld msec %03ld usec\n",
+                usec / USEC_PER_MSEC, usec % USEC_PER_MSEC);
+}
+#endif
 static const struct platform_suspend_ops bfin_pm_ops = {
        .enter = bfin_pm_enter,
        .valid  = bfin_pm_valid,
+#ifdef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH
+        .end = bfin_pm_end,
+#endif
 };
 static int __init bfin_pm_init(void)
diff --git a/arch/blackfin/mach-common/smp.c b/arch/blackfin/mach-common/smp.c
index ac8f8a43158c..00bbe672b3b3 100644
--- a/arch/blackfin/mach-common/smp.c
+++ b/arch/blackfin/mach-common/smp.c
@@ -340,27 +340,10 @@ void smp_send_stop(void)
        return;
 }
-int __cpuinit __cpu_up(unsigned int cpu)
+int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *idle)
 {
        int ret;
-        struct blackfin_cpudata *ci = &per_cpu(cpu_data, cpu);
-        struct task_struct *idle = ci->idle;
-        if (idle) {
-                free_task(idle);
-                idle = NULL;
-        }
-        if (!idle) {
-                idle = fork_idle(cpu);
-                if (IS_ERR(idle)) {
-                        printk(KERN_ERR "CPU%u: fork() failed\n", cpu);
-                        return PTR_ERR(idle);
-                }
-                ci->idle = idle;
-        } else {
-                init_idle(idle, cpu);
-        }
        secondary_stack = task_stack_page(idle) + THREAD_SIZE;
        ret = platform_boot_secondary(cpu, idle);
diff --git a/arch/blackfin/mm/init.c b/arch/blackfin/mm/init.c
index 78daae084915..9cb85537bd2b 100644
--- a/arch/blackfin/mm/init.c
+++ b/arch/blackfin/mm/init.c
@@ -48,7 +48,7 @@ void __init paging_init(void)
        unsigned long zones_size[MAX_NR_ZONES] = {
                [0] = 0,
-                [ZONE_DMA] = (end_mem - PAGE_OFFSET) >> PAGE_SHIFT,
+                [ZONE_DMA] = (end_mem - CONFIG_PHY_RAM_BASE_ADDRESS) >> PAGE_SHIFT,
                [ZONE_NORMAL] = 0,
 #ifdef CONFIG_HIGHMEM
                [ZONE_HIGHMEM] = 0,
@@ -60,7 +60,8 @@ void __init paging_init(void)
        pr_debug("free_area_init -> start_mem is %#lx virtual_end is %#lx\n",
                PAGE_ALIGN(memory_start), end_mem);
-        free_area_init(zones_size);
+        free_area_init_node(0, zones_size,
+                CONFIG_PHY_RAM_BASE_ADDRESS >> PAGE_SHIFT, NULL);
 }
 asmlinkage void __init init_pda(void)
@@ -75,9 +76,6 @@ asmlinkage void __init init_pda(void)
           valid pointers to it. */
        memset(&cpu_pda[cpu], 0, sizeof(cpu_pda[cpu]));
-        cpu_pda[0].next = &cpu_pda[1];
-        cpu_pda[1].next = &cpu_pda[0];
 #ifdef CONFIG_EXCEPTION_L1_SCRATCH
        cpu_pda[cpu].ex_stack = (unsigned long *)(L1_SCRATCH_START + \
                                        L1_SCRATCH_LENGTH);
@@ -109,10 +107,10 @@ void __init mem_init(void)
        totalram_pages = free_all_bootmem();
        reservedpages = 0;
-        for (tmp = 0; tmp < max_mapnr; tmp++)
+        for (tmp = ARCH_PFN_OFFSET; tmp < max_mapnr; tmp++)
                if (PageReserved(pfn_to_page(tmp)))
                        reservedpages++;
-        freepages =  max_mapnr - reservedpages;
+        freepages =  max_mapnr - ARCH_PFN_OFFSET - reservedpages;
        /* do not count in kernel image between _rambase and _ramstart */
        reservedpages -= (_ramstart - _rambase) >> PAGE_SHIFT;
@@ -127,7 +125,7 @@ void __init mem_init(void)
        printk(KERN_INFO
             "Memory available: %luk/%luk RAM, "
                "(%uk init code, %uk kernel code, %uk data, %uk dma, %uk reserved)\n",
-                (unsigned long) freepages << (PAGE_SHIFT-10), _ramend >> 10,
+                (unsigned long) freepages << (PAGE_SHIFT-10), (_ramend - CONFIG_PHY_RAM_BASE_ADDRESS) >> 10,
                initk, codek, datak, DMA_UNCACHED_REGION >> 10, (reservedpages << (PAGE_SHIFT-10)));
 }
diff --git a/arch/blackfin/mm/sram-alloc.c b/arch/blackfin/mm/sram-alloc.c
index 29d98faa1efd..342e378da1ec 100644
--- a/arch/blackfin/mm/sram-alloc.c
+++ b/arch/blackfin/mm/sram-alloc.c
@@ -186,9 +186,45 @@ static void __init l1_inst_sram_init(void)
 #endif
 }
+#ifdef __ADSPBF60x__
+static irqreturn_t l2_ecc_err(int irq, void *dev_id)
+{
+        int status;
+        printk(KERN_ERR "L2 ecc error happend\n");
+        status = bfin_read32(L2CTL0_STAT);
+        if (status & 0x1)
+                printk(KERN_ERR "Core channel error type:0x%x, addr:0x%x\n",
+                        bfin_read32(L2CTL0_ET0), bfin_read32(L2CTL0_EADDR0));
+        if (status & 0x2)
+                printk(KERN_ERR "System channel error type:0x%x, addr:0x%x\n",
+                        bfin_read32(L2CTL0_ET1), bfin_read32(L2CTL0_EADDR1));
+        status = status >> 8;
+        if (status)
+                printk(KERN_ERR "L2 Bank%d error, addr:0x%x\n",
+                        status, bfin_read32(L2CTL0_ERRADDR0 + status));
+        panic("L2 Ecc error");
+        return IRQ_HANDLED;
+}
+#endif
 static void __init l2_sram_init(void)
 {
 #if L2_LENGTH != 0
+#ifdef __ADSPBF60x__
+        int ret;
+        ret = request_irq(IRQ_L2CTL0_ECC_ERR, l2_ecc_err, 0, "l2-ecc-err",
+                        NULL);
+        if (unlikely(ret < 0)) {
+                printk(KERN_INFO "Fail to request l2 ecc error interrupt");
+                return;
+        }
+#endif
        free_l2_sram_head.next =
                kmem_cache_alloc(sram_piece_cache, GFP_KERNEL);
        if (!free_l2_sram_head.next) {
diff --git a/arch/c6x/Kconfig b/arch/c6x/Kconfig
index 1c3ccd416d50..1f15b88b537f 100644
--- a/arch/c6x/Kconfig
+++ b/arch/c6x/Kconfig
@@ -3,7 +3,7 @@
 # see Documentation/kbuild/kconfig-language.txt.
 #
-config TMS320C6X
+config C6X
        def_bool y
        select CLKDEV_LOOKUP
        select GENERIC_IRQ_SHOW
@@ -19,24 +19,12 @@ config TMS320C6X
 config MMU
        def_bool n
-config ZONE_DMA
-        def_bool y
 config FPU
        def_bool n
-config HIGHMEM
-        def_bool n
-config NUMA
-        def_bool n
 config RWSEM_GENERIC_SPINLOCK
        def_bool y
-config RWSEM_XCHGADD_ALGORITHM
-        def_bool n
 config GENERIC_CALIBRATE_DELAY
        def_bool y
diff --git a/arch/c6x/include/asm/elf.h b/arch/c6x/include/asm/elf.h
index d57865ba2c44..f4552db20b4a 100644
--- a/arch/c6x/include/asm/elf.h
+++ b/arch/c6x/include/asm/elf.h
@@ -30,7 +30,19 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
 */
 #define elf_check_arch(x) ((x)->e_machine == EM_TI_C6000)
-#define elf_check_const_displacement(x) (1)
+#define elf_check_fdpic(x) (1)
+#define elf_check_const_displacement(x) (0)
+#define ELF_FDPIC_PLAT_INIT(_regs, _exec_map, _interp_map, _dynamic_addr) \
+do {                                                            \
+        _regs->b4       = (_exec_map);                          \
+        _regs->a6       = (_interp_map);                        \
+        _regs->b6       = (_dynamic_addr);                      \
+} while (0)
+#define ELF_FDPIC_CORE_EFLAGS   0
+#define ELF_CORE_COPY_FPREGS(...) 0 /* No FPU regs to copy */
 /*
 * These are used to set parameters in the core dumps.
diff --git a/arch/c6x/include/asm/irq.h b/arch/c6x/include/asm/irq.h
index f13b78d5e1ca..ab4577f93d96 100644
--- a/arch/c6x/include/asm/irq.h
+++ b/arch/c6x/include/asm/irq.h
@@ -42,10 +42,6 @@
 /* This number is used when no interrupt has been assigned */
 #define NO_IRQ          0
-struct irq_data;
-extern irq_hw_number_t irqd_to_hwirq(struct irq_data *d);
-extern irq_hw_number_t virq_to_hw(unsigned int virq);
 extern void __init init_pic_c64xplus(void);
 extern void init_IRQ(void);
diff --git a/arch/c6x/include/asm/mmu.h b/arch/c6x/include/asm/mmu.h
index 41592bf16067..4467e770a1ce 100644
--- a/arch/c6x/include/asm/mmu.h
+++ b/arch/c6x/include/asm/mmu.h
@@ -13,6 +13,10 @@
 typedef struct {
        unsigned long           end_brk;
+#ifdef CONFIG_BINFMT_ELF_FDPIC
+        unsigned long   exec_fdpic_loadmap;
+        unsigned long   interp_fdpic_loadmap;
+#endif
 } mm_context_t;
 #endif /* _ASM_C6X_MMU_H */
diff --git a/arch/c6x/include/asm/ptrace.h b/arch/c6x/include/asm/ptrace.h
index 21e8d7931fe7..b04ff5964258 100644
--- a/arch/c6x/include/asm/ptrace.h
+++ b/arch/c6x/include/asm/ptrace.h
@@ -97,6 +97,11 @@
 #define PT_DP      PT_B14  /* Data Segment Pointer (B14) */
 #define PT_SP      PT_B15  /* Stack Pointer (B15)  */
+#define PTRACE_GETFDPIC         31      /* get the ELF fdpic loadmap address */
+#define PTRACE_GETFDPIC_EXEC    0       /* [addr] request the executable loadmap */
+#define PTRACE_GETFDPIC_INTERP  1       /* [addr] request the interpreter loadmap */
 #ifndef __ASSEMBLY__
 #ifdef _BIG_ENDIAN
diff --git a/arch/c6x/include/asm/thread_info.h b/arch/c6x/include/asm/thread_info.h
index fd99148cda9d..1710bcbb8d09 100644
--- a/arch/c6x/include/asm/thread_info.h
+++ b/arch/c6x/include/asm/thread_info.h
@@ -20,11 +20,11 @@
 #ifdef CONFIG_4KSTACKS
 #define THREAD_SIZE             4096
 #define THREAD_SHIFT            12
-#define THREAD_ORDER            0
+#define THREAD_SIZE_ORDER       0
 #else
 #define THREAD_SIZE             8192
 #define THREAD_SHIFT            13
-#define THREAD_ORDER            1
+#define THREAD_SIZE_ORDER       1
 #endif
 #define THREAD_START_SP         (THREAD_SIZE - 8)
@@ -80,19 +80,6 @@ struct thread_info *current_thread_info(void)
        return ti;
 }
-#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR
-/* thread information allocation */
-#ifdef CONFIG_DEBUG_STACK_USAGE
-#define THREAD_FLAGS (GFP_KERNEL | __GFP_NOTRACK | __GFP_ZERO)
-#else
-#define THREAD_FLAGS (GFP_KERNEL | __GFP_NOTRACK)
-#endif
-#define alloc_thread_info_node(tsk, node)       \
-        ((struct thread_info *)__get_free_pages(THREAD_FLAGS, THREAD_ORDER))
-#define free_thread_info(ti)    free_pages((unsigned long) (ti), THREAD_ORDER)
 #define get_thread_info(ti)     get_task_struct((ti)->task)
 #define put_thread_info(ti)     put_task_struct((ti)->task)
 #endif /* __ASSEMBLY__ */
diff --git a/arch/c6x/kernel/irq.c b/arch/c6x/kernel/irq.c
index 65b8ddf54b44..c90fb5e82ad7 100644
--- a/arch/c6x/kernel/irq.c
+++ b/arch/c6x/kernel/irq.c
@@ -130,16 +130,3 @@ int arch_show_interrupts(struct seq_file *p, int prec)
        seq_printf(p, "%*s: %10lu\n", prec, "Err", irq_err_count);
        return 0;
 }
-irq_hw_number_t irqd_to_hwirq(struct irq_data *d)
-{
-        return d->hwirq;
-}
-EXPORT_SYMBOL_GPL(irqd_to_hwirq);
-irq_hw_number_t virq_to_hw(unsigned int virq)
-{
-        struct irq_data *irq_data = irq_get_irq_data(virq);
-        return WARN_ON(!irq_data) ? 0 : irq_data->hwirq;
-}
-EXPORT_SYMBOL_GPL(virq_to_hw);
diff --git a/arch/c6x/kernel/process.c b/arch/c6x/kernel/process.c
index 7ca8c41b03cd..45e924a636a0 100644
--- a/arch/c6x/kernel/process.c
+++ b/arch/c6x/kernel/process.c
@@ -26,22 +26,6 @@ void	(*c6x_halt)(void);
 extern asmlinkage void ret_from_fork(void);
-static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
-static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
-/*
- * Initial thread structure.
- */
-union thread_union init_thread_union __init_task_data = {
-        INIT_THREAD_INFO(init_task)
-};
-/*
- * Initial task structure.
- */
-struct task_struct init_task = INIT_TASK(init_task);
-EXPORT_SYMBOL(init_task);
 /*
 * power off function, if any
 */
diff --git a/arch/cris/Kconfig b/arch/cris/Kconfig
index b3abfb08aa5c..2995035812ec 100644
--- a/arch/cris/Kconfig
+++ b/arch/cris/Kconfig
@@ -49,6 +49,7 @@ config CRIS
        select HAVE_GENERIC_HARDIRQS
        select GENERIC_IRQ_SHOW
        select GENERIC_IOMAP
+        select GENERIC_SMP_IDLE_THREAD if ETRAX_ARCH_V32
 config HZ
        int
diff --git a/arch/cris/arch-v32/kernel/smp.c b/arch/cris/arch-v32/kernel/smp.c
index 0b99df72d2a4..ebe2cb30bd11 100644
--- a/arch/cris/arch-v32/kernel/smp.c
+++ b/arch/cris/arch-v32/kernel/smp.c
@@ -108,17 +108,12 @@ void __init smp_cpus_done(unsigned int max_cpus)
 /* Bring one cpu online.*/
 static int __init
-smp_boot_one_cpu(int cpuid)
+smp_boot_one_cpu(int cpuid, struct task_struct idle)
 {
        unsigned timeout;
-        struct task_struct *idle;
        cpumask_t cpu_mask;
        cpumask_clear(&cpu_mask);
-        idle = fork_idle(cpuid);
-        if (IS_ERR(idle))
-                panic("SMP: fork failed for CPU:%d", cpuid);
        task_thread_info(idle)->cpu = cpuid;
        /* Information to the CPU that is about to boot */
@@ -142,9 +137,6 @@ smp_boot_one_cpu(int cpuid)
                barrier();
        }
-        put_task_struct(idle);
-        idle = NULL;
        printk(KERN_CRIT "SMP: CPU:%d is stuck.\n", cpuid);
        return -1;
 }
@@ -207,9 +199,9 @@ int setup_profiling_timer(unsigned int multiplier)
 */
 unsigned long cache_decay_ticks = 1;
-int __cpuinit __cpu_up(unsigned int cpu)
+int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *tidle)
 {
-        smp_boot_one_cpu(cpu);
+        smp_boot_one_cpu(cpu, tidle);
        return cpu_online(cpu) ? 0 : -ENOSYS;
 }
diff --git a/arch/cris/include/asm/processor.h b/arch/cris/include/asm/processor.h
index 4210d72a6667..8dc56ef08712 100644
--- a/arch/cris/include/asm/processor.h
+++ b/arch/cris/include/asm/processor.h
@@ -25,13 +25,12 @@ struct task_struct;
 */
 #define TASK_UNMAPPED_BASE      (PAGE_ALIGN(TASK_SIZE / 3))
-/* THREAD_SIZE is the size of the task_struct/kernel_stack combo.
+/* THREAD_SIZE is the size of the thread_info/kernel_stack combo.
 * normally, the stack is found by doing something like p + THREAD_SIZE
 * in CRIS, a page is 8192 bytes, which seems like a sane size
 */
 #define THREAD_SIZE       PAGE_SIZE
-#define KERNEL_STACK_SIZE PAGE_SIZE
+#define THREAD_SIZE_ORDER (0)
 /*
 * At user->kernel entry, the pt_regs struct is stacked on the top of the kernel-stack.
diff --git a/arch/cris/include/asm/thread_info.h b/arch/cris/include/asm/thread_info.h
index 29b92884d793..5b1c448df5c0 100644
--- a/arch/cris/include/asm/thread_info.h
+++ b/arch/cris/include/asm/thread_info.h
@@ -65,12 +65,6 @@ struct thread_info {
 #define init_thread_info        (init_thread_union.thread_info)
-#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR
-/* thread information allocation */
-#define alloc_thread_info_node(tsk, node)       \
-        ((struct thread_info *) __get_free_pages(GFP_KERNEL, 1))
-#define free_thread_info(ti) free_pages((unsigned long) (ti), 1)
 #endif /* !__ASSEMBLY__ */
 /*
diff --git a/arch/cris/kernel/process.c b/arch/cris/kernel/process.c
index 891dad85e8bd..66fd01728790 100644
--- a/arch/cris/kernel/process.c
+++ b/arch/cris/kernel/process.c
@@ -29,34 +29,6 @@
 //#define DEBUG
 /*
- * Initial task structure. Make this a per-architecture thing,
- * because different architectures tend to have different
- * alignment requirements and potentially different initial
- * setup.
- */
-static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
-static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
-/*
- * Initial thread structure.
- *
- * We need to make sure that this is 8192-byte aligned due to the
- * way process stacks are handled. This is done by having a special
- * "init_task" linker map entry..
- */
-union thread_union init_thread_union __init_task_data =
-        { INIT_THREAD_INFO(init_task) };
-/*
- * Initial task structure.
- *
- * All other task structs will be allocated on slabs in fork.c
- */
-struct task_struct init_task = INIT_TASK(init_task);
-EXPORT_SYMBOL(init_task);
-/*
 * The hlt_counter, disable_hlt and enable_hlt is just here as a hook if
 * there would ever be a halt sequence (for power save when idle) with
 * some largish delay when halting or resuming *and* a driver that can't
diff --git a/arch/frv/Makefile b/arch/frv/Makefile
index 7ff84575b186..4d1b1e9baef1 100644
--- a/arch/frv/Makefile
+++ b/arch/frv/Makefile
@@ -81,7 +81,7 @@ ifdef CONFIG_DEBUG_INFO
 KBUILD_AFLAGS   += -Wa,--gdwarf2
 endif
-head-y          := arch/frv/kernel/head.o arch/frv/kernel/init_task.o
+head-y          := arch/frv/kernel/head.o
 core-y          += arch/frv/kernel/ arch/frv/mm/
 libs-y          += arch/frv/lib/
diff --git a/arch/frv/include/asm/processor.h b/arch/frv/include/asm/processor.h
index 81c2e271d620..9b1a92b73f60 100644
--- a/arch/frv/include/asm/processor.h
+++ b/arch/frv/include/asm/processor.h
@@ -135,10 +135,6 @@ unsigned long get_wchan(struct task_struct *p);
 #define KSTK_EIP(tsk)   ((tsk)->thread.frame0->pc)
 #define KSTK_ESP(tsk)   ((tsk)->thread.frame0->sp)
-/* Allocation and freeing of basic task resources. */
-extern struct task_struct *alloc_task_struct_node(int node);
-extern void free_task_struct(struct task_struct *p);
 #define cpu_relax()    barrier()
 /* data cache prefetch */
diff --git a/arch/frv/include/asm/thread_info.h b/arch/frv/include/asm/thread_info.h
index 92d83ea99ae5..54ab13a0de41 100644
--- a/arch/frv/include/asm/thread_info.h
+++ b/arch/frv/include/asm/thread_info.h
@@ -21,8 +21,6 @@
 #define THREAD_SIZE             8192
-#define __HAVE_ARCH_TASK_STRUCT_ALLOCATOR
 /*
 * low level task data that entry.S needs immediate access to
 * - this struct should fit entirely inside of one cache line
@@ -82,19 +80,6 @@ register struct thread_info *__current_thread_info asm("gr15");
 #define current_thread_info() ({ __current_thread_info; })
-#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR
-/* thread information allocation */
-#ifdef CONFIG_DEBUG_STACK_USAGE
-#define alloc_thread_info_node(tsk, node)                       \
-                kzalloc_node(THREAD_SIZE, GFP_KERNEL, node)
-#else
-#define alloc_thread_info_node(tsk, node)                       \
-                kmalloc_node(THREAD_SIZE, GFP_KERNEL, node)
-#endif
-#define free_thread_info(info)  kfree(info)
 #endif /* __ASSEMBLY__ */
 /*
diff --git a/arch/frv/kernel/Makefile b/arch/frv/kernel/Makefile
index c36f70b6699a..ad4087b69968 100644
--- a/arch/frv/kernel/Makefile
+++ b/arch/frv/kernel/Makefile
@@ -5,7 +5,7 @@
 heads-y                         := head-uc-fr401.o head-uc-fr451.o head-uc-fr555.o
 heads-$(CONFIG_MMU)             := head-mmu-fr451.o
-extra-y:= head.o init_task.o vmlinux.lds
+extra-y:= head.o vmlinux.lds
 obj-y := $(heads-y) entry.o entry-table.o break.o switch_to.o kernel_thread.o \
         kernel_execve.o process.o traps.o ptrace.o signal.o dma.o \
diff --git a/arch/frv/kernel/init_task.c b/arch/frv/kernel/init_task.c
deleted file mode 100644
index 3c3e0b336a9d..000000000000
--- a/arch/frv/kernel/init_task.c
+++ /dev/null
@@ -1,32 +0,0 @@
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/sched.h>
-#include <linux/init.h>
-#include <linux/init_task.h>
-#include <linux/fs.h>
-#include <linux/mqueue.h>
-#include <asm/uaccess.h>
-#include <asm/pgtable.h>
-static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
-static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
-/*
- * Initial thread structure.
- *
- * We need to make sure that this is THREAD_SIZE aligned due to the
- * way process stacks are handled. This is done by having a special
- * "init_task" linker map entry..
- */
-union thread_union init_thread_union __init_task_data =
-        { INIT_THREAD_INFO(init_task) };
-/*
- * Initial task structure.
- *
- * All other task structs will be allocated on slabs in fork.c
- */
-struct task_struct init_task = INIT_TASK(init_task);
-EXPORT_SYMBOL(init_task);
diff --git a/arch/frv/kernel/process.c b/arch/frv/kernel/process.c
index d4de48bd5efe..ed09e9e2c653 100644
--- a/arch/frv/kernel/process.c
+++ b/arch/frv/kernel/process.c
@@ -43,21 +43,6 @@ asmlinkage void ret_from_fork(void);
 void (*pm_power_off)(void);
 EXPORT_SYMBOL(pm_power_off);
-struct task_struct *alloc_task_struct_node(int node)
-{
-        struct task_struct *p = kmalloc_node(THREAD_SIZE, GFP_KERNEL, node);
-        if (p)
-                atomic_set((atomic_t *)(p+1), 1);
-        return p;
-}
-void free_task_struct(struct task_struct *p)
-{
-        if (atomic_dec_and_test((atomic_t *)(p+1)))
-                kfree(p);
-}
 static void core_sleep_idle(void)
 {
 #ifdef LED_DEBUG_SLEEP
diff --git a/arch/h8300/kernel/Makefile b/arch/h8300/kernel/Makefile
index 8d4d2a54be9e..1cc57f872d34 100644
--- a/arch/h8300/kernel/Makefile
+++ b/arch/h8300/kernel/Makefile
@@ -6,7 +6,7 @@ extra-y := vmlinux.lds
 obj-y := process.o traps.o ptrace.o irq.o \
         sys_h8300.o time.o signal.o \
-         setup.o gpio.o init_task.o syscalls.o \
+         setup.o gpio.o syscalls.o \
         entry.o timer/
 obj-$(CONFIG_MODULES) += module.o h8300_ksyms.o 
diff --git a/arch/h8300/kernel/init_task.c b/arch/h8300/kernel/init_task.c
deleted file mode 100644
index 54c1062ee80e..000000000000
--- a/arch/h8300/kernel/init_task.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- *  linux/arch/h8300/kernel/init_task.c
- */
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/sched.h>
-#include <linux/init.h>
-#include <linux/init_task.h>
-#include <linux/fs.h>
-#include <linux/mqueue.h>
-#include <asm/uaccess.h>
-#include <asm/pgtable.h>
-static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
-static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
-/*
- * Initial task structure.
- *
- * All other task structs will be allocated on slabs in fork.c
- */
-__asm__(".align 4");
-struct task_struct init_task = INIT_TASK(init_task);
-EXPORT_SYMBOL(init_task);
-/*
- * Initial thread structure.
- *
- * We need to make sure that this is 8192-byte aligned due to the
- * way process stacks are handled. This is done by having a special
- * "init_task" linker map entry..
- */
-union thread_union init_thread_union __init_task_data =
-        { INIT_THREAD_INFO(init_task) };
diff --git a/arch/hexagon/Kconfig b/arch/hexagon/Kconfig
index 9059e3905887..22615dd02219 100644
--- a/arch/hexagon/Kconfig
+++ b/arch/hexagon/Kconfig
@@ -18,8 +18,6 @@ config HEXAGON
        select GENERIC_ATOMIC64
        select HAVE_PERF_EVENTS
        select HAVE_GENERIC_HARDIRQS
-        select GENERIC_HARDIRQS_NO__DO_IRQ
-        select GENERIC_HARDIRQS_NO_DEPRECATED
        # GENERIC_ALLOCATOR is used by dma_alloc_coherent()
        select GENERIC_ALLOCATOR
        select GENERIC_IRQ_SHOW
@@ -27,6 +25,7 @@ config HEXAGON
        select HAVE_ARCH_TRACEHOOK
        select NO_IOPORT
        select GENERIC_IOMAP
+        select GENERIC_SMP_IDLE_THREAD
        # mostly generic routines, with some accelerated ones
        ---help---
          Qualcomm Hexagon is a processor architecture designed for high
diff --git a/arch/hexagon/Makefile b/arch/hexagon/Makefile
index 0c4de8790fd5..e27d030846ae 100644
--- a/arch/hexagon/Makefile
+++ b/arch/hexagon/Makefile
@@ -45,8 +45,7 @@ KBUILD_AFLAGS += -DTHREADINFO_REG=$(TIR_NAME)
 LIBGCC := $(shell $(CC) $(KBUILD_CFLAGS) -print-libgcc-file-name)
 libs-y += $(LIBGCC)
-head-y := arch/hexagon/kernel/head.o \
+head-y := arch/hexagon/kernel/head.o
-        arch/hexagon/kernel/init_task.o
 core-y += arch/hexagon/kernel/ \
        arch/hexagon/mm/ \
diff --git a/arch/hexagon/include/asm/thread_info.h b/arch/hexagon/include/asm/thread_info.h
index 9c2934ff5756..4f936a7ee847 100644
--- a/arch/hexagon/include/asm/thread_info.h
+++ b/arch/hexagon/include/asm/thread_info.h
@@ -31,15 +31,7 @@
 #define THREAD_SHIFT            12
 #define THREAD_SIZE             (1<<THREAD_SHIFT)
-#if THREAD_SHIFT >= PAGE_SHIFT
 #define THREAD_SIZE_ORDER       (THREAD_SHIFT - PAGE_SHIFT)
-#else  /*  don't use standard allocator  */
-#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR
-extern struct thread_info *alloc_thread_info_node(struct task_struct *tsk, int node);
-extern void free_thread_info(struct thread_info *ti);
-#endif
 #ifndef __ASSEMBLY__
diff --git a/arch/hexagon/kernel/Makefile b/arch/hexagon/kernel/Makefile
index 3689f3754d09..536aec093e62 100644
--- a/arch/hexagon/kernel/Makefile
+++ b/arch/hexagon/kernel/Makefile
@@ -1,4 +1,4 @@
-extra-y := head.o vmlinux.lds init_task.o
+extra-y := head.o vmlinux.lds
 obj-$(CONFIG_SMP) += smp.o topology.o
diff --git a/arch/hexagon/kernel/dma.c b/arch/hexagon/kernel/dma.c
index 37302218ca4a..0f2367cc5493 100644
--- a/arch/hexagon/kernel/dma.c
+++ b/arch/hexagon/kernel/dma.c
@@ -22,6 +22,7 @@
 #include <linux/bootmem.h>
 #include <linux/genalloc.h>
 #include <asm/dma-mapping.h>
+#include <linux/module.h>
 struct dma_map_ops *dma_ops;
 EXPORT_SYMBOL(dma_ops);
diff --git a/arch/hexagon/kernel/init_task.c b/arch/hexagon/kernel/init_task.c
deleted file mode 100644
index 73283d3edf09..000000000000
--- a/arch/hexagon/kernel/init_task.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * Init task definition
- *
- * Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
- * 02110-1301, USA.
- */
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/sched.h>
-#include <linux/init_task.h>
-#include <linux/fs.h>
-#include <linux/mqueue.h>
-#include <asm/thread_info.h>
-#include <asm/uaccess.h>
-#include <asm/pgtable.h>
-static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
-static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
-/*
- * Initial thread structure.
- *
- * We need to make sure that this is 8192-byte aligned due to the
- * way process stacks are handled. This is done by making sure
- * the linker maps this in the .text segment right after head.S,
- * and making head.S ensure the proper alignment.
- */
-union thread_union init_thread_union
-        __attribute__((__section__(".data.init_task"),
-                __aligned__(THREAD_SIZE))) = {
-                        INIT_THREAD_INFO(init_task)
-                };
-/*
- * Initial task structure.
- *
- * All other task structs will be allocated on slabs in fork.c
- */
-struct task_struct init_task = INIT_TASK(init_task);
-EXPORT_SYMBOL(init_task);
diff --git a/arch/hexagon/kernel/process.c b/arch/hexagon/kernel/process.c
index 18c4f0b0f4ba..af51de63b835 100644
--- a/arch/hexagon/kernel/process.c
+++ b/arch/hexagon/kernel/process.c
@@ -1,7 +1,7 @@
 /*
 * Process creation support for Hexagon
 *
- * Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2010-2012, Code Aurora Forum. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
@@ -88,7 +88,7 @@ void (*idle_sleep)(void) = default_idle;
 void cpu_idle(void)
 {
        while (1) {
-                tick_nohz_stop_sched_tick(1);
+                tick_nohz_idle_enter();
                local_irq_disable();
                while (!need_resched()) {
                        idle_sleep();
@@ -97,7 +97,7 @@ void cpu_idle(void)
                        local_irq_disable();
                }
                local_irq_enable();
-                tick_nohz_restart_sched_tick();
+                tick_nohz_idle_exit();
                schedule();
        }
 }
@@ -234,43 +234,6 @@ unsigned long get_wchan(struct task_struct *p)
 }
 /*
- * Borrowed from PowerPC -- basically allow smaller kernel stacks if we
- * go crazy with the page sizes.
- */
-#if THREAD_SHIFT < PAGE_SHIFT
-static struct kmem_cache *thread_info_cache;
-struct thread_info *alloc_thread_info_node(struct task_struct *tsk, int node)
-{
-        struct thread_info *ti;
-        ti = kmem_cache_alloc_node(thread_info_cache, GFP_KERNEL, node);
-        if (unlikely(ti == NULL))
-                return NULL;
-#ifdef CONFIG_DEBUG_STACK_USAGE
-        memset(ti, 0, THREAD_SIZE);
-#endif
-        return ti;
-}
-void free_thread_info(struct thread_info *ti)
-{
-        kmem_cache_free(thread_info_cache, ti);
-}
-/*  Weak symbol; called by init/main.c  */
-void thread_info_cache_init(void)
-{
-        thread_info_cache = kmem_cache_create("thread_info", THREAD_SIZE,
-                                              THREAD_SIZE, 0, NULL);
-        BUG_ON(thread_info_cache == NULL);
-}
-#endif /* THREAD_SHIFT < PAGE_SHIFT */
-/*
 * Required placeholder.
 */
 int dump_fpu(struct pt_regs *regs, elf_fpregset_t *fpu)
diff --git a/arch/hexagon/kernel/ptrace.c b/arch/hexagon/kernel/ptrace.c
index 32342de1a79c..96c3b2c4dbad 100644
--- a/arch/hexagon/kernel/ptrace.c
+++ b/arch/hexagon/kernel/ptrace.c
@@ -28,6 +28,7 @@
 #include <linux/ptrace.h>
 #include <linux/regset.h>
 #include <linux/user.h>
+#include <linux/elf.h>
 #include <asm/user.h>
diff --git a/arch/hexagon/kernel/smp.c b/arch/hexagon/kernel/smp.c
index 9b44a9e2d05a..f7264621e58d 100644
--- a/arch/hexagon/kernel/smp.c
+++ b/arch/hexagon/kernel/smp.c
@@ -1,7 +1,7 @@
 /*
 * SMP support for Hexagon
 *
- * Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2010-2012, Code Aurora Forum. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
@@ -28,6 +28,7 @@
 #include <linux/sched.h>
 #include <linux/smp.h>
 #include <linux/spinlock.h>
+#include <linux/cpu.h>
 #include <asm/time.h>    /*  timer_interrupt  */
 #include <asm/hexagon_vm.h>
@@ -177,7 +178,12 @@ void __cpuinit start_secondary(void)
        printk(KERN_INFO "%s cpu %d\n", __func__, current_thread_info()->cpu);
+        notify_cpu_starting(cpu);
+        ipi_call_lock();
        set_cpu_online(cpu, true);
+        ipi_call_unlock();
        local_irq_enable();
        cpu_idle();
@@ -190,18 +196,11 @@ void __cpuinit start_secondary(void)
 * maintains control until "cpu_online(cpu)" is set.
 */
-int __cpuinit __cpu_up(unsigned int cpu)
+int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *idle)
 {
-        struct task_struct *idle;
+        struct thread_info *thread = (struct thread_info *)idle->stack;
-        struct thread_info *thread;
        void *stack_start;
-        /*  Create new init task for the CPU  */
-        idle = fork_idle(cpu);
-        if (IS_ERR(idle))
-                panic(KERN_ERR "fork_idle failed\n");
-        thread = (struct thread_info *)idle->stack;
        thread->cpu = cpu;
        /*  Boot to the head.  */
diff --git a/arch/hexagon/kernel/time.c b/arch/hexagon/kernel/time.c
index 6bee15c9c113..5d9b33b67935 100644
--- a/arch/hexagon/kernel/time.c
+++ b/arch/hexagon/kernel/time.c
@@ -28,6 +28,7 @@
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
+#include <linux/module.h>
 #include <asm/timer-regs.h>
 #include <asm/hexagon_vm.h>
diff --git a/arch/hexagon/kernel/vdso.c b/arch/hexagon/kernel/vdso.c
index f212a453b527..5d39f42f7085 100644
--- a/arch/hexagon/kernel/vdso.c
+++ b/arch/hexagon/kernel/vdso.c
@@ -21,6 +21,7 @@
 #include <linux/err.h>
 #include <linux/mm.h>
 #include <linux/vmalloc.h>
+#include <linux/binfmts.h>
 #include <asm/vdso.h>
diff --git a/arch/ia64/Kconfig b/arch/ia64/Kconfig
index bd7266903bf8..ba667b60f32d 100644
--- a/arch/ia64/Kconfig
+++ b/arch/ia64/Kconfig
@@ -33,6 +33,10 @@ config IA64
        select ARCH_WANT_OPTIONAL_GPIOLIB
        select ARCH_HAVE_NMI_SAFE_CMPXCHG
        select GENERIC_IOMAP
+        select GENERIC_SMP_IDLE_THREAD
+        select ARCH_INIT_TASK
+        select ARCH_TASK_STRUCT_ALLOCATOR
+        select ARCH_THREAD_INFO_ALLOCATOR
        default y
        help
          The Itanium Processor Family is Intel's 64-bit successor to
diff --git a/arch/ia64/include/asm/cmpxchg.h b/arch/ia64/include/asm/cmpxchg.h
index 4c96187e2049..4f37dbbb8640 100644
--- a/arch/ia64/include/asm/cmpxchg.h
+++ b/arch/ia64/include/asm/cmpxchg.h
@@ -1 +1,147 @@
-#include <asm/intrinsics.h>
+#ifndef _ASM_IA64_CMPXCHG_H
+#define _ASM_IA64_CMPXCHG_H
+/*
+ * Compare/Exchange, forked from asm/intrinsics.h
+ * which was:
+ *
+ *      Copyright (C) 2002-2003 Hewlett-Packard Co
+ *      David Mosberger-Tang <davidm@hpl.hp.com>
+ */
+#ifndef __ASSEMBLY__
+#include <linux/types.h>
+/* include compiler specific intrinsics */
+#include <asm/ia64regs.h>
+#ifdef __INTEL_COMPILER
+# include <asm/intel_intrin.h>
+#else
+# include <asm/gcc_intrin.h>
+#endif
+/*
+ * This function doesn't exist, so you'll get a linker error if
+ * something tries to do an invalid xchg().
+ */
+extern void ia64_xchg_called_with_bad_pointer(void);
+#define __xchg(x, ptr, size)                                            \
+({                                                                      \
+        unsigned long __xchg_result;                                    \
+                                                                        \
+        switch (size) {                                                 \
+        case 1:                                                         \
+                __xchg_result = ia64_xchg1((__u8 *)ptr, x);             \
+                break;                                                  \
+                                                                        \
+        case 2:                                                         \
+                __xchg_result = ia64_xchg2((__u16 *)ptr, x);            \
+                break;                                                  \
+                                                                        \
+        case 4:                                                         \
+                __xchg_result = ia64_xchg4((__u32 *)ptr, x);            \
+                break;                                                  \
+                                                                        \
+        case 8:                                                         \
+                __xchg_result = ia64_xchg8((__u64 *)ptr, x);            \
+                break;                                                  \
+        default:                                                        \
+                ia64_xchg_called_with_bad_pointer();                    \
+        }                                                               \
+        __xchg_result;                                                  \
+})
+#define xchg(ptr, x)                                                    \
+((__typeof__(*(ptr))) __xchg((unsigned long) (x), (ptr), sizeof(*(ptr))))
+/*
+ * Atomic compare and exchange.  Compare OLD with MEM, if identical,
+ * store NEW in MEM.  Return the initial value in MEM.  Success is
+ * indicated by comparing RETURN with OLD.
+ */
+#define __HAVE_ARCH_CMPXCHG 1
+/*
+ * This function doesn't exist, so you'll get a linker error
+ * if something tries to do an invalid cmpxchg().
+ */
+extern long ia64_cmpxchg_called_with_bad_pointer(void);
+#define ia64_cmpxchg(sem, ptr, old, new, size)                          \
+({                                                                      \
+        __u64 _o_, _r_;                                                 \
+                                                                        \
+        switch (size) {                                                 \
+        case 1:                                                         \
+                _o_ = (__u8) (long) (old);                              \
+                break;                                                  \
+        case 2:                                                         \
+                _o_ = (__u16) (long) (old);                             \
+                break;                                                  \
+        case 4:                                                         \
+                _o_ = (__u32) (long) (old);                             \
+                break;                                                  \
+        case 8:                                                         \
+                _o_ = (__u64) (long) (old);                             \
+                break;                                                  \
+        default:                                                        \
+                break;                                                  \
+        }                                                               \
+        switch (size) {                                                 \
+        case 1:                                                         \
+                _r_ = ia64_cmpxchg1_##sem((__u8 *) ptr, new, _o_);      \
+                break;                                                  \
+                                                                        \
+        case 2:                                                         \
+                _r_ = ia64_cmpxchg2_##sem((__u16 *) ptr, new, _o_);     \
+                break;                                                  \
+                                                                        \
+        case 4:                                                         \
+                _r_ = ia64_cmpxchg4_##sem((__u32 *) ptr, new, _o_);     \
+                break;                                                  \
+                                                                        \
+        case 8:                                                         \
+                _r_ = ia64_cmpxchg8_##sem((__u64 *) ptr, new, _o_);     \
+                break;                                                  \
+                                                                        \
+        default:                                                        \
+                _r_ = ia64_cmpxchg_called_with_bad_pointer();           \
+                break;                                                  \
+        }                                                               \
+        (__typeof__(old)) _r_;                                          \
+})
+#define cmpxchg_acq(ptr, o, n)  \
+        ia64_cmpxchg(acq, (ptr), (o), (n), sizeof(*(ptr)))
+#define cmpxchg_rel(ptr, o, n)  \
+        ia64_cmpxchg(rel, (ptr), (o), (n), sizeof(*(ptr)))
+/* for compatibility with other platforms: */
+#define cmpxchg(ptr, o, n)      cmpxchg_acq((ptr), (o), (n))
+#define cmpxchg64(ptr, o, n)    cmpxchg_acq((ptr), (o), (n))
+#define cmpxchg_local           cmpxchg
+#define cmpxchg64_local         cmpxchg64
+#ifdef CONFIG_IA64_DEBUG_CMPXCHG
+# define CMPXCHG_BUGCHECK_DECL  int _cmpxchg_bugcheck_count = 128;
+# define CMPXCHG_BUGCHECK(v)                                            \
+do {                                                                    \
+        if (_cmpxchg_bugcheck_count-- <= 0) {                           \
+                void *ip;                                               \
+                extern int printk(const char *fmt, ...);                \
+                ip = (void *) ia64_getreg(_IA64_REG_IP);                \
+                printk("CMPXCHG_BUGCHECK: stuck at %p on word %p\n", ip, (v));\
+                break;                                                  \
+        }                                                               \
+} while (0)
+#else /* !CONFIG_IA64_DEBUG_CMPXCHG */
+# define CMPXCHG_BUGCHECK_DECL
+# define CMPXCHG_BUGCHECK(v)
+#endif /* !CONFIG_IA64_DEBUG_CMPXCHG */
+#endif /* !__ASSEMBLY__ */
+#endif /* _ASM_IA64_CMPXCHG_H */
diff --git a/arch/ia64/include/asm/futex.h b/arch/ia64/include/asm/futex.h
index 0ab82cc2dc8f..d2bf1fd5e44f 100644
--- a/arch/ia64/include/asm/futex.h
+++ b/arch/ia64/include/asm/futex.h
@@ -106,15 +106,16 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
                return -EFAULT;
        {
-                register unsigned long r8 __asm ("r8") = 0;
+                register unsigned long r8 __asm ("r8");
                unsigned long prev;
                __asm__ __volatile__(
                        "       mf;;                                    \n"
-                        "       mov ar.ccv=%3;;                         \n"
+                        "       mov %0=r0                               \n"
-                        "[1:]   cmpxchg4.acq %0=[%1],%2,ar.ccv          \n"
+                        "       mov ar.ccv=%4;;                         \n"
+                        "[1:]   cmpxchg4.acq %1=[%2],%3,ar.ccv          \n"
                        "       .xdata4 \"__ex_table\", 1b-., 2f-.      \n"
                        "[2:]"
-                        : "=r" (prev)
+                        : "=r" (r8), "=r" (prev)
                        : "r" (uaddr), "r" (newval),
                          "rO" ((long) (unsigned) oldval)
                        : "memory");
diff --git a/arch/ia64/include/asm/intrinsics.h b/arch/ia64/include/asm/intrinsics.h
index e4076b511829..d129e367e764 100644
--- a/arch/ia64/include/asm/intrinsics.h
+++ b/arch/ia64/include/asm/intrinsics.h
@@ -18,6 +18,7 @@
 #else
 # include <asm/gcc_intrin.h>
 #endif
+#include <asm/cmpxchg.h>
 #define ia64_native_get_psr_i() (ia64_native_getreg(_IA64_REG_PSR) & IA64_PSR_I)
@@ -81,119 +82,6 @@ extern unsigned long __bad_increment_for_ia64_fetch_and_add (void);
 #define ia64_fetch_and_add(i,v) (ia64_fetchadd(i, v, rel) + (i)) /* return new value */
-/*
- * This function doesn't exist, so you'll get a linker error if
- * something tries to do an invalid xchg().
- */
-extern void ia64_xchg_called_with_bad_pointer (void);
-#define __xchg(x,ptr,size)                                              \
-({                                                                      \
-        unsigned long __xchg_result;                                    \
-                                                                        \
-        switch (size) {                                                 \
-              case 1:                                                   \
-                __xchg_result = ia64_xchg1((__u8 *)ptr, x);             \
-                break;                                                  \
-                                                                        \
-              case 2:                                                   \
-                __xchg_result = ia64_xchg2((__u16 *)ptr, x);            \
-                break;                                                  \
-                                                                        \
-              case 4:                                                   \
-                __xchg_result = ia64_xchg4((__u32 *)ptr, x);            \
-                break;                                                  \
-                                                                        \
-              case 8:                                                   \
-                __xchg_result = ia64_xchg8((__u64 *)ptr, x);            \
-                break;                                                  \
-              default:                                                  \
-                ia64_xchg_called_with_bad_pointer();                    \
-        }                                                               \
-        __xchg_result;                                                  \
-})
-#define xchg(ptr,x)                                                          \
-  ((__typeof__(*(ptr))) __xchg ((unsigned long) (x), (ptr), sizeof(*(ptr))))
-/*
- * Atomic compare and exchange.  Compare OLD with MEM, if identical,
- * store NEW in MEM.  Return the initial value in MEM.  Success is
- * indicated by comparing RETURN with OLD.
- */
-#define __HAVE_ARCH_CMPXCHG 1
-/*
- * This function doesn't exist, so you'll get a linker error
- * if something tries to do an invalid cmpxchg().
- */
-extern long ia64_cmpxchg_called_with_bad_pointer (void);
-#define ia64_cmpxchg(sem,ptr,old,new,size)                                              \
-({                                                                                      \
-        __u64 _o_, _r_;                                                                 \
-                                                                                        \
-        switch (size) {                                                                 \
-              case 1: _o_ = (__u8 ) (long) (old); break;                                \
-              case 2: _o_ = (__u16) (long) (old); break;                                \
-              case 4: _o_ = (__u32) (long) (old); break;                                \
-              case 8: _o_ = (__u64) (long) (old); break;                                \
-              default: break;                                                           \
-        }                                                                               \
-        switch (size) {                                                                 \
-              case 1:                                                                   \
-                _r_ = ia64_cmpxchg1_##sem((__u8 *) ptr, new, _o_);                      \
-                break;                                                                  \
-                                                                                        \
-              case 2:                                                                   \
-               _r_ = ia64_cmpxchg2_##sem((__u16 *) ptr, new, _o_);                      \
-                break;                                                                  \
-                                                                                        \
-              case 4:                                                                   \
-                _r_ = ia64_cmpxchg4_##sem((__u32 *) ptr, new, _o_);                     \
-                break;                                                                  \
-                                                                                        \
-              case 8:                                                                   \
-                _r_ = ia64_cmpxchg8_##sem((__u64 *) ptr, new, _o_);                     \
-                break;                                                                  \
-                                                                                        \
-              default:                                                                  \
-                _r_ = ia64_cmpxchg_called_with_bad_pointer();                           \
-                break;                                                                  \
-        }                                                                               \
-        (__typeof__(old)) _r_;                                                          \
-})
-#define cmpxchg_acq(ptr, o, n)  \
-        ia64_cmpxchg(acq, (ptr), (o), (n), sizeof(*(ptr)))
-#define cmpxchg_rel(ptr, o, n)  \
-        ia64_cmpxchg(rel, (ptr), (o), (n), sizeof(*(ptr)))
-/* for compatibility with other platforms: */
-#define cmpxchg(ptr, o, n)      cmpxchg_acq((ptr), (o), (n))
-#define cmpxchg64(ptr, o, n)    cmpxchg_acq((ptr), (o), (n))
-#define cmpxchg_local           cmpxchg
-#define cmpxchg64_local         cmpxchg64
-#ifdef CONFIG_IA64_DEBUG_CMPXCHG
-# define CMPXCHG_BUGCHECK_DECL  int _cmpxchg_bugcheck_count = 128;
-# define CMPXCHG_BUGCHECK(v)                                                    \
-  do {                                                                          \
-        if (_cmpxchg_bugcheck_count-- <= 0) {                                   \
-                void *ip;                                                       \
-                extern int printk(const char *fmt, ...);                        \
-                ip = (void *) ia64_getreg(_IA64_REG_IP);                        \
-                printk("CMPXCHG_BUGCHECK: stuck at %p on word %p\n", ip, (v));  \
-                break;                                                          \
-        }                                                                       \
-  } while (0)
-#else /* !CONFIG_IA64_DEBUG_CMPXCHG */
-# define CMPXCHG_BUGCHECK_DECL
-# define CMPXCHG_BUGCHECK(v)
-#endif /* !CONFIG_IA64_DEBUG_CMPXCHG */
 #endif
 #ifdef __KERNEL__
diff --git a/arch/ia64/include/asm/irq_remapping.h b/arch/ia64/include/asm/irq_remapping.h
new file mode 100644
index 000000000000..a8687b1d8906
--- /dev/null
+++ b/arch/ia64/include/asm/irq_remapping.h
@@ -0,0 +1,4 @@
+#ifndef __IA64_INTR_REMAPPING_H
+#define __IA64_INTR_REMAPPING_H
+#define irq_remapping_enabled 0
+#endif
diff --git a/arch/ia64/include/asm/processor.h b/arch/ia64/include/asm/processor.h
index 483f6c6a4238..f92f67aba618 100644
--- a/arch/ia64/include/asm/processor.h
+++ b/arch/ia64/include/asm/processor.h
@@ -723,7 +723,6 @@ extern unsigned long boot_option_idle_override;
 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_FORCE_MWAIT,
                         IDLE_NOMWAIT, IDLE_POLL};
-void cpu_idle_wait(void);
 void default_idle(void);
 #define ia64_platform_is(x) (strcmp(x, platform_name) == 0)
diff --git a/arch/ia64/include/asm/thread_info.h b/arch/ia64/include/asm/thread_info.h
index e054bcc4273c..310d9734f02d 100644
--- a/arch/ia64/include/asm/thread_info.h
+++ b/arch/ia64/include/asm/thread_info.h
@@ -54,8 +54,6 @@ struct thread_info {
        },                                      \
 }
-#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR
 #ifndef ASM_OFFSETS_C
 /* how to get the thread information struct from C */
 #define current_thread_info()   ((struct thread_info *) ((char *) current + IA64_TASK_SIZE))
@@ -84,7 +82,6 @@ struct thread_info {
 #endif
 #define end_of_stack(p) (unsigned long *)((void *)(p) + IA64_RBS_OFFSET)
-#define __HAVE_ARCH_TASK_STRUCT_ALLOCATOR
 #define alloc_task_struct_node(node)                                            \
 ({                                                                              \
        struct page *page = alloc_pages_node(node, GFP_KERNEL | __GFP_COMP,     \
diff --git a/arch/ia64/include/asm/topology.h b/arch/ia64/include/asm/topology.h
index 09f646753d1a..a2496e449b75 100644
--- a/arch/ia64/include/asm/topology.h
+++ b/arch/ia64/include/asm/topology.h
@@ -70,31 +70,6 @@ void build_cpu_to_node_map(void);
        .nr_balance_failed      = 0,                    \
 }
-/* sched_domains SD_NODE_INIT for IA64 NUMA machines */
-#define SD_NODE_INIT (struct sched_domain) {            \
-        .parent                 = NULL,                 \
-        .child                  = NULL,                 \
-        .groups                 = NULL,                 \
-        .min_interval           = 8,                    \
-        .max_interval           = 8*(min(num_online_cpus(), 32U)), \
-        .busy_factor            = 64,                   \
-        .imbalance_pct          = 125,                  \
-        .cache_nice_tries       = 2,                    \
-        .busy_idx               = 3,                    \
-        .idle_idx               = 2,                    \
-        .newidle_idx            = 0,                    \
-        .wake_idx               = 0,                    \
-        .forkexec_idx           = 0,                    \
-        .flags                  = SD_LOAD_BALANCE       \
-                                | SD_BALANCE_NEWIDLE    \
-                                | SD_BALANCE_EXEC       \
-                                | SD_BALANCE_FORK       \
-                                | SD_SERIALIZE,         \
-        .last_balance           = jiffies,              \
-        .balance_interval       = 64,                   \
-        .nr_balance_failed      = 0,                    \
-}
 #endif /* CONFIG_NUMA */
 #ifdef CONFIG_SMP
diff --git a/arch/ia64/kernel/perfmon.c b/arch/ia64/kernel/perfmon.c
index 9d0fd7d5bb82..f00ba025375d 100644
--- a/arch/ia64/kernel/perfmon.c
+++ b/arch/ia64/kernel/perfmon.c
@@ -604,12 +604,6 @@ pfm_unprotect_ctx_ctxsw(pfm_context_t *x, unsigned long f)
        spin_unlock(&(x)->ctx_lock);
 }
-static inline unsigned int
-pfm_do_munmap(struct mm_struct *mm, unsigned long addr, size_t len, int acct)
-{
-        return do_munmap(mm, addr, len);
-}
 static inline unsigned long 
 pfm_get_unmapped_area(struct file *file, unsigned long addr, unsigned long len, unsigned long pgoff, unsigned long flags, unsigned long exec)
 {
@@ -1458,8 +1452,9 @@ pfm_unreserve_session(pfm_context_t *ctx, int is_syswide, unsigned int cpu)
 * a PROTECT_CTX() section.
 */
 static int
-pfm_remove_smpl_mapping(struct task_struct *task, void *vaddr, unsigned long size)
+pfm_remove_smpl_mapping(void *vaddr, unsigned long size)
 {
+        struct task_struct *task = current;
        int r;
        /* sanity checks */
@@ -1473,13 +1468,8 @@ pfm_remove_smpl_mapping(struct task_struct *task, void *vaddr, unsigned long siz
        /*
         * does the actual unmapping
         */
-        down_write(&task->mm->mmap_sem);
+        r = vm_munmap((unsigned long)vaddr, size);
-        DPRINT(("down_write done smpl_vaddr=%p size=%lu\n", vaddr, size));
-        r = pfm_do_munmap(task->mm, (unsigned long)vaddr, size, 0);
-        up_write(&task->mm->mmap_sem);
        if (r !=0) {
                printk(KERN_ERR "perfmon: [%d] unable to unmap sampling buffer @%p size=%lu\n", task_pid_nr(task), vaddr, size);
        }
@@ -1945,7 +1935,7 @@ pfm_flush(struct file *filp, fl_owner_t id)
         * because some VM function reenables interrupts.
         *
         */
-        if (smpl_buf_vaddr) pfm_remove_smpl_mapping(current, smpl_buf_vaddr, smpl_buf_size);
+        if (smpl_buf_vaddr) pfm_remove_smpl_mapping(smpl_buf_vaddr, smpl_buf_size);
        return 0;
 }
diff --git a/arch/ia64/kernel/process.c b/arch/ia64/kernel/process.c
index ce74e143aea3..5e0e86ddb12f 100644
--- a/arch/ia64/kernel/process.c
+++ b/arch/ia64/kernel/process.c
@@ -273,26 +273,6 @@ static inline void play_dead(void)
 }
 #endif /* CONFIG_HOTPLUG_CPU */
-static void do_nothing(void *unused)
-{
-}
-/*
- * cpu_idle_wait - Used to ensure that all the CPUs discard old value of
- * pm_idle and update to new pm_idle value. Required while changing pm_idle
- * handler on SMP systems.
- *
- * Caller must have changed pm_idle to the new value before the call. Old
- * pm_idle value will not be used by any CPU after the return of this function.
- */
-void cpu_idle_wait(void)
-{
-        smp_mb();
-        /* kick all the CPUs so that they exit out of pm_idle */
-        smp_call_function(do_nothing, NULL, 1);
-}
-EXPORT_SYMBOL_GPL(cpu_idle_wait);
 void __attribute__((noreturn))
 cpu_idle (void)
 {
diff --git a/arch/ia64/kernel/smpboot.c b/arch/ia64/kernel/smpboot.c
index 796f6a5b966a..1113b8aba07f 100644
--- a/arch/ia64/kernel/smpboot.c
+++ b/arch/ia64/kernel/smpboot.c
@@ -75,13 +75,6 @@
 #endif
 /*
- * Store all idle threads, this can be reused instead of creating
- * a new thread. Also avoids complicated thread destroy functionality
- * for idle threads.
- */
-struct task_struct *idle_thread_array[NR_CPUS];
-/*
 * Global array allocated for NR_CPUS at boot time
 */
 struct sal_to_os_boot sal_boot_rendez_state[NR_CPUS];
@@ -94,13 +87,7 @@ struct sal_to_os_boot *sal_state_for_booting_cpu = &sal_boot_rendez_state[0];
 #define set_brendez_area(x) (sal_state_for_booting_cpu = &sal_boot_rendez_state[(x)]);
-#define get_idle_for_cpu(x)             (idle_thread_array[(x)])
-#define set_idle_for_cpu(x,p)   (idle_thread_array[(x)] = (p))
 #else
-#define get_idle_for_cpu(x)             (NULL)
-#define set_idle_for_cpu(x,p)
 #define set_brendez_area(x)
 #endif
@@ -480,54 +467,12 @@ struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs)
        return NULL;
 }
-struct create_idle {
-        struct work_struct work;
-        struct task_struct *idle;
-        struct completion done;
-        int cpu;
-};
-void __cpuinit
-do_fork_idle(struct work_struct *work)
-{
-        struct create_idle *c_idle =
-                container_of(work, struct create_idle, work);
-        c_idle->idle = fork_idle(c_idle->cpu);
-        complete(&c_idle->done);
-}
 static int __cpuinit
-do_boot_cpu (int sapicid, int cpu)
+do_boot_cpu (int sapicid, int cpu, struct task_struct *idle)
 {
        int timeout;
-        struct create_idle c_idle = {
-                .work = __WORK_INITIALIZER(c_idle.work, do_fork_idle),
-                .cpu    = cpu,
-                .done   = COMPLETION_INITIALIZER(c_idle.done),
-        };
-        /*
-         * We can't use kernel_thread since we must avoid to
-         * reschedule the child.
-         */
-        c_idle.idle = get_idle_for_cpu(cpu);
-        if (c_idle.idle) {
-                init_idle(c_idle.idle, cpu);
-                goto do_rest;
-        }
-        schedule_work(&c_idle.work);
-        wait_for_completion(&c_idle.done);
-        if (IS_ERR(c_idle.idle))
-                panic("failed fork for CPU %d", cpu);
-        set_idle_for_cpu(cpu, c_idle.idle);
-do_rest:
-        task_for_booting_cpu = c_idle.idle;
+        task_for_booting_cpu = idle;
        Dprintk("Sending wakeup vector %lu to AP 0x%x/0x%x.\n", ap_wakeup_vector, cpu, sapicid);
        set_brendez_area(cpu);
@@ -793,7 +738,7 @@ set_cpu_sibling_map(int cpu)
 }
 int __cpuinit
-__cpu_up (unsigned int cpu)
+__cpu_up(unsigned int cpu, struct task_struct *tidle)
 {
        int ret;
        int sapicid;
@@ -811,7 +756,7 @@ __cpu_up (unsigned int cpu)
        per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
        /* Processor goes to start_secondary(), sets online flag */
-        ret = do_boot_cpu(sapicid, cpu);
+        ret = do_boot_cpu(sapicid, cpu, tidle);
        if (ret < 0)
                return ret;
diff --git a/arch/ia64/kvm/kvm-ia64.c b/arch/ia64/kvm/kvm-ia64.c
index f5104b7c52cd..463fb3bbe11e 100644
--- a/arch/ia64/kvm/kvm-ia64.c
+++ b/arch/ia64/kvm/kvm-ia64.c
@@ -1174,7 +1174,7 @@ out:
 bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
 {
-        return irqchip_in_kernel(vcpu->kcm) == (vcpu->arch.apic != NULL);
+        return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
 }
 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
diff --git a/arch/m32r/Makefile b/arch/m32r/Makefile
index 8ff5ba0ea26c..def8dd0b6bc5 100644
--- a/arch/m32r/Makefile
+++ b/arch/m32r/Makefile
@@ -31,7 +31,7 @@ KBUILD_AFLAGS += $(aflags-y)
 CHECKFLAGS      += -D__m32r__ -D__BIG_ENDIAN__=1
-head-y  := arch/m32r/kernel/head.o arch/m32r/kernel/init_task.o
+head-y  := arch/m32r/kernel/head.o
 LIBGCC  := $(shell $(CC) $(KBUILD_CFLAGS) -print-libgcc-file-name)
diff --git a/arch/m32r/include/asm/thread_info.h b/arch/m32r/include/asm/thread_info.h
index bf8fa3c06f4e..c083f6073ef4 100644
--- a/arch/m32r/include/asm/thread_info.h
+++ b/arch/m32r/include/asm/thread_info.h
@@ -55,8 +55,8 @@ struct thread_info {
 #define PREEMPT_ACTIVE          0x10000000
-#define THREAD_SIZE (PAGE_SIZE << 1)
+#define THREAD_SIZE             (PAGE_SIZE << 1)
+#define THREAD_SIZE_ORDER       1
 /*
 * macros/functions for gaining access to the thread information structure
 */
@@ -92,19 +92,6 @@ static inline struct thread_info *current_thread_info(void)
        return ti;
 }
-#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR
-/* thread information allocation */
-#ifdef CONFIG_DEBUG_STACK_USAGE
-#define alloc_thread_info_node(tsk, node)                       \
-                kzalloc_node(THREAD_SIZE, GFP_KERNEL, node)
-#else
-#define alloc_thread_info_node(tsk, node)                       \
-                kmalloc_node(THREAD_SIZE, GFP_KERNEL, node)
-#endif
-#define free_thread_info(info) kfree(info)
 #define TI_FLAG_FAULT_CODE_SHIFT        28
 static inline void set_thread_fault_code(unsigned int val)
diff --git a/arch/m32r/kernel/Makefile b/arch/m32r/kernel/Makefile
index b1a4b6036591..0c09dad8b1f8 100644
--- a/arch/m32r/kernel/Makefile
+++ b/arch/m32r/kernel/Makefile
@@ -2,7 +2,7 @@
 # Makefile for the Linux/M32R kernel.
 #
-extra-y := head.o init_task.o vmlinux.lds
+extra-y := head.o vmlinux.lds
 obj-y   := process.o entry.o traps.o align.o irq.o setup.o time.o \
        m32r_ksyms.o sys_m32r.o signal.o ptrace.o
diff --git a/arch/m32r/kernel/init_task.c b/arch/m32r/kernel/init_task.c
deleted file mode 100644
index 6c42d5f8df50..000000000000
--- a/arch/m32r/kernel/init_task.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/* orig : i386 init_task.c */
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/sched.h>
-#include <linux/init.h>
-#include <linux/init_task.h>
-#include <linux/fs.h>
-#include <linux/mqueue.h>
-#include <asm/uaccess.h>
-#include <asm/pgtable.h>
-static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
-static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
-/*
- * Initial thread structure.
- *
- * We need to make sure that this is 8192-byte aligned due to the
- * way process stacks are handled. This is done by having a special
- * "init_task" linker map entry..
- */
-union thread_union init_thread_union __init_task_data =
-        { INIT_THREAD_INFO(init_task) };
-/*
- * Initial task structure.
- *
- * All other task structs will be allocated on slabs in fork.c
- */
-struct task_struct init_task = INIT_TASK(init_task);
-EXPORT_SYMBOL(init_task);
diff --git a/arch/m32r/kernel/smpboot.c b/arch/m32r/kernel/smpboot.c
index cfdbe5d15002..a2cfc0abb05c 100644
--- a/arch/m32r/kernel/smpboot.c
+++ b/arch/m32r/kernel/smpboot.c
@@ -109,12 +109,8 @@ static unsigned int calibration_result;
 /* Function Prototypes                                                       */
 /*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
-void smp_prepare_boot_cpu(void);
-void smp_prepare_cpus(unsigned int);
 static void init_ipi_lock(void);
 static void do_boot_cpu(int);
-int __cpu_up(unsigned int);
-void smp_cpus_done(unsigned int);
 int start_secondary(void *);
 static void smp_callin(void);
@@ -347,7 +343,7 @@ static void __init do_boot_cpu(int phys_id)
        }
 }
-int __cpuinit __cpu_up(unsigned int cpu_id)
+int __cpuinit __cpu_up(unsigned int cpu_id, struct task_struct *tidle)
 {
        int timeout;
diff --git a/arch/m68k/Makefile b/arch/m68k/Makefile
index cf318f20c64d..b7f2e2d5cd2e 100644
--- a/arch/m68k/Makefile
+++ b/arch/m68k/Makefile
@@ -16,6 +16,13 @@
 KBUILD_DEFCONFIG := multi_defconfig
+ifneq ($(SUBARCH),$(ARCH))
+        ifeq ($(CROSS_COMPILE),)
+                CROSS_COMPILE := $(call cc-cross-prefix, \
+                        m68k-linux-gnu- m68k-linux- m68k-unknown-linux-gnu-)
+        endif
+endif
 #
 #       Enable processor type. Ordering of these is important - we want to
 #       use the minimum processor type of the range we support. The logic
@@ -62,12 +69,6 @@ endif
 LDFLAGS := -m m68kelf
 KBUILD_LDFLAGS_MODULE += -T $(srctree)/arch/m68k/kernel/module.lds
-ifneq ($(SUBARCH),$(ARCH))
-        ifeq ($(CROSS_COMPILE),)
-                CROSS_COMPILE := $(call cc-cross-prefix, \
-                        m68k-linux-gnu- m68k-linux- m68k-unknown-linux-gnu-)
-        endif
-endif
 ifdef CONFIG_SUN3
 LDFLAGS_vmlinux = -N
@@ -115,18 +116,6 @@ core-$(CONFIG_M68000)		+= arch/m68k/platform/68328/
 core-$(CONFIG_M68EZ328)         += arch/m68k/platform/68EZ328/
 core-$(CONFIG_M68VZ328)         += arch/m68k/platform/68VZ328/
 core-$(CONFIG_COLDFIRE)         += arch/m68k/platform/coldfire/
-core-$(CONFIG_M5206)            += arch/m68k/platform/5206/
-core-$(CONFIG_M5206e)           += arch/m68k/platform/5206/
-core-$(CONFIG_M520x)            += arch/m68k/platform/520x/
-core-$(CONFIG_M523x)            += arch/m68k/platform/523x/
-core-$(CONFIG_M5249)            += arch/m68k/platform/5249/
-core-$(CONFIG_M527x)            += arch/m68k/platform/527x/
-core-$(CONFIG_M5272)            += arch/m68k/platform/5272/
-core-$(CONFIG_M528x)            += arch/m68k/platform/528x/
-core-$(CONFIG_M5307)            += arch/m68k/platform/5307/
-core-$(CONFIG_M532x)            += arch/m68k/platform/532x/
-core-$(CONFIG_M5407)            += arch/m68k/platform/5407/
-core-$(CONFIG_M54xx)            += arch/m68k/platform/54xx/
 all:    zImage
diff --git a/arch/m68k/amiga/platform.c b/arch/m68k/amiga/platform.c
index 7fd8b41723ea..80076d368b7e 100644
--- a/arch/m68k/amiga/platform.c
+++ b/arch/m68k/amiga/platform.c
@@ -6,6 +6,7 @@
 * for more details.
 */
+#include <linux/err.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/zorro.h>
@@ -46,18 +47,25 @@ static const struct resource zorro_resources[] __initconst = {
 static int __init amiga_init_bus(void)
 {
+        struct platform_device *pdev;
+        unsigned int n;
        if (!MACH_IS_AMIGA || !AMIGAHW_PRESENT(ZORRO))
                return -ENODEV;
-        platform_device_register_simple("amiga-zorro", -1, zorro_resources,
+        n = AMIGAHW_PRESENT(ZORRO3) ? 4 : 2;
-                                        AMIGAHW_PRESENT(ZORRO3) ? 4 : 2);
+        pdev = platform_device_register_simple("amiga-zorro", -1,
+                                               zorro_resources, n);
+        if (IS_ERR(pdev))
+                return PTR_ERR(pdev);
        return 0;
 }
 subsys_initcall(amiga_init_bus);
-static int z_dev_present(zorro_id id)
+static int __init z_dev_present(zorro_id id)
 {
        unsigned int i;
@@ -126,72 +134,122 @@ static const struct resource amiga_rtc_resource __initconst = {
 static int __init amiga_init_devices(void)
 {
        struct platform_device *pdev;
+        int error;
        if (!MACH_IS_AMIGA)
                return -ENODEV;
        /* video hardware */
-        if (AMIGAHW_PRESENT(AMI_VIDEO))
+        if (AMIGAHW_PRESENT(AMI_VIDEO)) {
-                platform_device_register_simple("amiga-video", -1, NULL, 0);
+                pdev = platform_device_register_simple("amiga-video", -1, NULL,
+                                                       0);
+                if (IS_ERR(pdev))
+                        return PTR_ERR(pdev);
+        }
        /* sound hardware */
-        if (AMIGAHW_PRESENT(AMI_AUDIO))
+        if (AMIGAHW_PRESENT(AMI_AUDIO)) {
-                platform_device_register_simple("amiga-audio", -1, NULL, 0);
+                pdev = platform_device_register_simple("amiga-audio", -1, NULL,
+                                                       0);
+                if (IS_ERR(pdev))
+                        return PTR_ERR(pdev);
+        }
        /* storage interfaces */
-        if (AMIGAHW_PRESENT(AMI_FLOPPY))
+        if (AMIGAHW_PRESENT(AMI_FLOPPY)) {
-                platform_device_register_simple("amiga-floppy", -1, NULL, 0);
+                pdev = platform_device_register_simple("amiga-floppy", -1,
+                                                       NULL, 0);
+                if (IS_ERR(pdev))
+                        return PTR_ERR(pdev);
+        }
-        if (AMIGAHW_PRESENT(A3000_SCSI))
+        if (AMIGAHW_PRESENT(A3000_SCSI)) {
-                platform_device_register_simple("amiga-a3000-scsi", -1,
+                pdev = platform_device_register_simple("amiga-a3000-scsi", -1,
-                                                &a3000_scsi_resource, 1);
+                                                       &a3000_scsi_resource, 1);
+                if (IS_ERR(pdev))
+                        return PTR_ERR(pdev);
+        }
-        if (AMIGAHW_PRESENT(A4000_SCSI))
+        if (AMIGAHW_PRESENT(A4000_SCSI)) {
-                platform_device_register_simple("amiga-a4000t-scsi", -1,
+                pdev = platform_device_register_simple("amiga-a4000t-scsi", -1,
-                                                &a4000t_scsi_resource, 1);
+                                                       &a4000t_scsi_resource,
+                                                       1);
+                if (IS_ERR(pdev))
+                        return PTR_ERR(pdev);
+        }
        if (AMIGAHW_PRESENT(A1200_IDE) ||
            z_dev_present(ZORRO_PROD_MTEC_VIPER_MK_V_E_MATRIX_530_SCSI_IDE)) {
                pdev = platform_device_register_simple("amiga-gayle-ide", -1,
                                                       &a1200_ide_resource, 1);
-                platform_device_add_data(pdev, &a1200_ide_pdata,
+                if (IS_ERR(pdev))
-                                         sizeof(a1200_ide_pdata));
+                        return PTR_ERR(pdev);
+                error = platform_device_add_data(pdev, &a1200_ide_pdata,
+                                                 sizeof(a1200_ide_pdata));
+                if (error)
+                        return error;
        }
        if (AMIGAHW_PRESENT(A4000_IDE)) {
                pdev = platform_device_register_simple("amiga-gayle-ide", -1,
                                                       &a4000_ide_resource, 1);
-                platform_device_add_data(pdev, &a4000_ide_pdata,
+                if (IS_ERR(pdev))
-                                         sizeof(a4000_ide_pdata));
+                        return PTR_ERR(pdev);
+                error = platform_device_add_data(pdev, &a4000_ide_pdata,
+                                                 sizeof(a4000_ide_pdata));
+                if (error)
+                        return error;
        }
        /* other I/O hardware */
-        if (AMIGAHW_PRESENT(AMI_KEYBOARD))
+        if (AMIGAHW_PRESENT(AMI_KEYBOARD)) {
-                platform_device_register_simple("amiga-keyboard", -1, NULL, 0);
+                pdev = platform_device_register_simple("amiga-keyboard", -1,
+                                                       NULL, 0);
+                if (IS_ERR(pdev))
+                        return PTR_ERR(pdev);
+        }
-        if (AMIGAHW_PRESENT(AMI_MOUSE))
+        if (AMIGAHW_PRESENT(AMI_MOUSE)) {
-                platform_device_register_simple("amiga-mouse", -1, NULL, 0);
+                pdev = platform_device_register_simple("amiga-mouse", -1, NULL,
+                                                       0);
+                if (IS_ERR(pdev))
+                        return PTR_ERR(pdev);
+        }
-        if (AMIGAHW_PRESENT(AMI_SERIAL))
+        if (AMIGAHW_PRESENT(AMI_SERIAL)) {
-                platform_device_register_simple("amiga-serial", -1, NULL, 0);
+                pdev = platform_device_register_simple("amiga-serial", -1,
+                                                       NULL, 0);
+                if (IS_ERR(pdev))
+                        return PTR_ERR(pdev);
+        }
-        if (AMIGAHW_PRESENT(AMI_PARALLEL))
+        if (AMIGAHW_PRESENT(AMI_PARALLEL)) {
-                platform_device_register_simple("amiga-parallel", -1, NULL, 0);
+                pdev = platform_device_register_simple("amiga-parallel", -1,
+                                                       NULL, 0);
+                if (IS_ERR(pdev))
+                        return PTR_ERR(pdev);
+        }
        /* real time clocks */
-        if (AMIGAHW_PRESENT(A2000_CLK))
+        if (AMIGAHW_PRESENT(A2000_CLK)) {
-                platform_device_register_simple("rtc-msm6242", -1,
+                pdev = platform_device_register_simple("rtc-msm6242", -1,
-                                                &amiga_rtc_resource, 1);
+                                                       &amiga_rtc_resource, 1);
+                if (IS_ERR(pdev))
+                        return PTR_ERR(pdev);
+        }
-        if (AMIGAHW_PRESENT(A3000_CLK))
+        if (AMIGAHW_PRESENT(A3000_CLK)) {
-                platform_device_register_simple("rtc-rp5c01", -1,
+                pdev = platform_device_register_simple("rtc-rp5c01", -1,
-                                                &amiga_rtc_resource, 1);
+                                                       &amiga_rtc_resource, 1);
+                if (IS_ERR(pdev))
+                        return PTR_ERR(pdev);
+        }
        return 0;
 }
-device_initcall(amiga_init_devices);
+arch_initcall(amiga_init_devices);
diff --git a/arch/m68k/atari/ataints.c b/arch/m68k/atari/ataints.c
index 783d8f02360d..3f41092d1b70 100644
--- a/arch/m68k/atari/ataints.c
+++ b/arch/m68k/atari/ataints.c
@@ -206,7 +206,7 @@ void __init atari_init_IRQ(void)
 * hardware with a programmable int vector (probably a VME board).
 */
-unsigned long atari_register_vme_int(void)
+unsigned int atari_register_vme_int(void)
 {
        int i;
@@ -223,7 +223,7 @@ unsigned long atari_register_vme_int(void)
 EXPORT_SYMBOL(atari_register_vme_int);
-void atari_unregister_vme_int(unsigned long irq)
+void atari_unregister_vme_int(unsigned int irq)
 {
        if (irq >= VME_SOURCE_BASE && irq < VME_SOURCE_BASE + VME_MAX_SOURCES) {
                irq -= VME_SOURCE_BASE;
diff --git a/arch/m68k/configs/m5275evb_defconfig b/arch/m68k/configs/m5275evb_defconfig
index 33c32aeca12b..a1230e82bb1e 100644
--- a/arch/m68k/configs/m5275evb_defconfig
+++ b/arch/m68k/configs/m5275evb_defconfig
@@ -49,7 +49,6 @@ CONFIG_BLK_DEV_RAM=y
 CONFIG_NETDEVICES=y
 CONFIG_NET_ETHERNET=y
 CONFIG_FEC=y
-CONFIG_FEC2=y
 # CONFIG_NETDEV_1000 is not set
 # CONFIG_NETDEV_10000 is not set
 CONFIG_PPP=y
diff --git a/arch/m68k/configs/m5475evb_defconfig b/arch/m68k/configs/m5475evb_defconfig
new file mode 100644
index 000000000000..c5018a68819b
--- /dev/null
+++ b/arch/m68k/configs/m5475evb_defconfig
@@ -0,0 +1,62 @@
+CONFIG_EXPERIMENTAL=y
+# CONFIG_SWAP is not set
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_SYSCTL_SYSCALL=y
+# CONFIG_KALLSYMS is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_FUTEX is not set
+# CONFIG_EPOLL is not set
+# CONFIG_SIGNALFD is not set
+# CONFIG_TIMERFD is not set
+# CONFIG_EVENTFD is not set
+# CONFIG_SHMEM is not set
+# CONFIG_AIO is not set
+CONFIG_EMBEDDED=y
+CONFIG_MODULES=y
+# CONFIG_LBDAF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_COLDFIRE=y
+CONFIG_M547x=y
+CONFIG_CLOCK_SET=y
+CONFIG_CLOCK_FREQ=266000000
+# CONFIG_4KSTACKS is not set
+CONFIG_RAMBASE=0x0
+CONFIG_RAMSIZE=0x2000000
+CONFIG_VECTORBASE=0x0
+CONFIG_MBAR=0xff000000
+CONFIG_KERNELBASE=0x20000
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_FW_LOADER is not set
+CONFIG_MTD=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_RAM=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_UCLINUX=y
+CONFIG_BLK_DEV_RAM=y
+# CONFIG_INPUT is not set
+# CONFIG_VT is not set
+# CONFIG_UNIX98_PTYS is not set
+CONFIG_SERIAL_MCF=y
+CONFIG_SERIAL_MCF_CONSOLE=y
+# CONFIG_HW_RANDOM is not set
+# CONFIG_HWMON is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_EXT2_FS=y
+# CONFIG_FILE_LOCKING is not set
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY_USER is not set
+# CONFIG_PROC_PAGE_MONITOR is not set
+CONFIG_ROMFS_FS=y
+CONFIG_ROMFS_BACKED_BY_MTD=y
+# CONFIG_SCHED_DEBUG is not set
+CONFIG_BOOTPARAM=y
+CONFIG_BOOTPARAM_STRING="root=/dev/mtdblock0"
diff --git a/arch/m68k/include/asm/atariints.h b/arch/m68k/include/asm/atariints.h
index 656bbbf5a6ff..5fc13bdf9044 100644
--- a/arch/m68k/include/asm/atariints.h
+++ b/arch/m68k/include/asm/atariints.h
@@ -198,7 +198,7 @@ static inline int atari_irq_pending( unsigned irq )
        return( get_mfp_bit( irq, MFP_PENDING ) );
 }
-unsigned long atari_register_vme_int( void );
+unsigned int atari_register_vme_int(void);
-void atari_unregister_vme_int( unsigned long );
+void atari_unregister_vme_int(unsigned int);
 #endif /* linux/atariints.h */
diff --git a/arch/m68k/include/asm/cacheflush_no.h b/arch/m68k/include/asm/cacheflush_no.h
index cb88aa96c4f1..7cafb537d03c 100644
--- a/arch/m68k/include/asm/cacheflush_no.h
+++ b/arch/m68k/include/asm/cacheflush_no.h
@@ -30,11 +30,8 @@
 void mcf_cache_push(void);
-static inline void __flush_cache_all(void)
+static inline void __clear_cache_all(void)
 {
-#ifdef CACHE_PUSH
-        mcf_cache_push();
-#endif
 #ifdef CACHE_INVALIDATE
        __asm__ __volatile__ (
                "movel  %0, %%d0\n\t"
@@ -44,6 +41,14 @@ static inline void __flush_cache_all(void)
 #endif
 }
+static inline void __flush_cache_all(void)
+{
+#ifdef CACHE_PUSH
+        mcf_cache_push();
+#endif
+        __clear_cache_all();
+}
 /*
 * Some ColdFire parts implement separate instruction and data caches,
 * on those we should just flush the appropriate cache. If we don't need
@@ -76,4 +81,23 @@ static inline void __flush_dcache_all(void)
        __asm__ __volatile__ ( "nop" );
 #endif
 }
+/*
+ * Push cache entries at supplied address. We want to write back any dirty
+ * data and the invalidate the cache lines associated with this address.
+ */
+static inline void cache_push(unsigned long paddr, int len)
+{
+        __flush_cache_all();
+}
+/*
+ * Clear cache entries at supplied address (that is don't write back any
+ * dirty data).
+ */
+static inline void cache_clear(unsigned long paddr, int len)
+{
+        __clear_cache_all();
+}
 #endif /* _M68KNOMMU_CACHEFLUSH_H */
diff --git a/arch/m68k/include/asm/entry.h b/arch/m68k/include/asm/entry.h
index 622138dc7288..d7de0f1a8957 100644
--- a/arch/m68k/include/asm/entry.h
+++ b/arch/m68k/include/asm/entry.h
@@ -33,13 +33,11 @@
 /* the following macro is used when enabling interrupts */
 #if defined(MACH_ATARI_ONLY)
-        /* block out HSYNC on the atari */
+        /* block out HSYNC = ipl 2 on the atari */
-#define ALLOWINT        (~0x400)
+#define ALLOWINT        (~0x500)
-#define MAX_NOINT_IPL   3
 #else
        /* portable version */
 #define ALLOWINT        (~0x700)
-#define MAX_NOINT_IPL   0
 #endif /* machine compilation types */
 #ifdef __ASSEMBLY__
diff --git a/arch/m68k/include/asm/flat.h b/arch/m68k/include/asm/flat.h
index a0e290793978..f9454b89a51b 100644
--- a/arch/m68k/include/asm/flat.h
+++ b/arch/m68k/include/asm/flat.h
@@ -11,6 +11,11 @@
 #define flat_get_addr_from_rp(rp, relval, flags, p)     get_unaligned(rp)
 #define flat_put_addr_at_rp(rp, val, relval)    put_unaligned(val,rp)
 #define flat_get_relocate_addr(rel)             (rel)
-#define flat_set_persistent(relval, p)          0
+static inline int flat_set_persistent(unsigned long relval,
+                                      unsigned long *persistent)
+{
+        return 0;
+}
 #endif /* __M68KNOMMU_FLAT_H__ */
diff --git a/arch/m68k/include/asm/io_mm.h b/arch/m68k/include/asm/io_mm.h
index 0fb3468000e7..fa4324bcf566 100644
--- a/arch/m68k/include/asm/io_mm.h
+++ b/arch/m68k/include/asm/io_mm.h
@@ -278,6 +278,13 @@ static inline void isa_delay(void)
 #define readl(addr)      in_le32(addr)
 #define writel(val,addr) out_le32((addr),(val))
+#define readsb(port, buf, nr)     raw_insb((port), (u8 *)(buf), (nr))
+#define readsw(port, buf, nr)     raw_insw((port), (u16 *)(buf), (nr))
+#define readsl(port, buf, nr)     raw_insl((port), (u32 *)(buf), (nr))
+#define writesb(port, buf, nr)    raw_outsb((port), (u8 *)(buf), (nr))
+#define writesw(port, buf, nr)    raw_outsw((port), (u16 *)(buf), (nr))
+#define writesl(port, buf, nr)    raw_outsl((port), (u32 *)(buf), (nr))
 #define mmiowb()
 static inline void __iomem *ioremap(unsigned long physaddr, unsigned long size)
diff --git a/arch/m68k/include/asm/m528xsim.h b/arch/m68k/include/asm/m528xsim.h
index 569476fba18c..d63b99ff7ff7 100644
--- a/arch/m68k/include/asm/m528xsim.h
+++ b/arch/m68k/include/asm/m528xsim.h
@@ -97,100 +97,81 @@
 /*
 *      GPIO registers
 */
-#define MCFGPIO_PORTA           (MCF_IPSBAR + 0x00100000)
+#define MCFGPIO_PODR_A          (MCF_IPSBAR + 0x00100000)
-#define MCFGPIO_PORTB           (MCF_IPSBAR + 0x00100001)
+#define MCFGPIO_PODR_B          (MCF_IPSBAR + 0x00100001)
-#define MCFGPIO_PORTC           (MCF_IPSBAR + 0x00100002)
+#define MCFGPIO_PODR_C          (MCF_IPSBAR + 0x00100002)
-#define MCFGPIO_PORTD           (MCF_IPSBAR + 0x00100003)
+#define MCFGPIO_PODR_D          (MCF_IPSBAR + 0x00100003)
-#define MCFGPIO_PORTE           (MCF_IPSBAR + 0x00100004)
+#define MCFGPIO_PODR_E          (MCF_IPSBAR + 0x00100004)
-#define MCFGPIO_PORTF           (MCF_IPSBAR + 0x00100005)
+#define MCFGPIO_PODR_F          (MCF_IPSBAR + 0x00100005)
-#define MCFGPIO_PORTG           (MCF_IPSBAR + 0x00100006)
+#define MCFGPIO_PODR_G          (MCF_IPSBAR + 0x00100006)
-#define MCFGPIO_PORTH           (MCF_IPSBAR + 0x00100007)
+#define MCFGPIO_PODR_H          (MCF_IPSBAR + 0x00100007)
-#define MCFGPIO_PORTJ           (MCF_IPSBAR + 0x00100008)
+#define MCFGPIO_PODR_J          (MCF_IPSBAR + 0x00100008)
-#define MCFGPIO_PORTDD          (MCF_IPSBAR + 0x00100009)
+#define MCFGPIO_PODR_DD         (MCF_IPSBAR + 0x00100009)
-#define MCFGPIO_PORTEH          (MCF_IPSBAR + 0x0010000A)
+#define MCFGPIO_PODR_EH         (MCF_IPSBAR + 0x0010000A)
-#define MCFGPIO_PORTEL          (MCF_IPSBAR + 0x0010000B)
+#define MCFGPIO_PODR_EL         (MCF_IPSBAR + 0x0010000B)
-#define MCFGPIO_PORTAS          (MCF_IPSBAR + 0x0010000C)
+#define MCFGPIO_PODR_AS         (MCF_IPSBAR + 0x0010000C)
-#define MCFGPIO_PORTQS          (MCF_IPSBAR + 0x0010000D)
+#define MCFGPIO_PODR_QS         (MCF_IPSBAR + 0x0010000D)
-#define MCFGPIO_PORTSD          (MCF_IPSBAR + 0x0010000E)
+#define MCFGPIO_PODR_SD         (MCF_IPSBAR + 0x0010000E)
-#define MCFGPIO_PORTTC          (MCF_IPSBAR + 0x0010000F)
+#define MCFGPIO_PODR_TC         (MCF_IPSBAR + 0x0010000F)
-#define MCFGPIO_PORTTD          (MCF_IPSBAR + 0x00100010)
+#define MCFGPIO_PODR_TD         (MCF_IPSBAR + 0x00100010)
-#define MCFGPIO_PORTUA          (MCF_IPSBAR + 0x00100011)
+#define MCFGPIO_PODR_UA         (MCF_IPSBAR + 0x00100011)
-#define MCFGPIO_DDRA            (MCF_IPSBAR + 0x00100014)
+#define MCFGPIO_PDDR_A          (MCF_IPSBAR + 0x00100014)
-#define MCFGPIO_DDRB            (MCF_IPSBAR + 0x00100015)
+#define MCFGPIO_PDDR_B          (MCF_IPSBAR + 0x00100015)
-#define MCFGPIO_DDRC            (MCF_IPSBAR + 0x00100016)
+#define MCFGPIO_PDDR_C          (MCF_IPSBAR + 0x00100016)
-#define MCFGPIO_DDRD            (MCF_IPSBAR + 0x00100017)
+#define MCFGPIO_PDDR_D          (MCF_IPSBAR + 0x00100017)
-#define MCFGPIO_DDRE            (MCF_IPSBAR + 0x00100018)
+#define MCFGPIO_PDDR_E          (MCF_IPSBAR + 0x00100018)
-#define MCFGPIO_DDRF            (MCF_IPSBAR + 0x00100019)
+#define MCFGPIO_PDDR_F          (MCF_IPSBAR + 0x00100019)
-#define MCFGPIO_DDRG            (MCF_IPSBAR + 0x0010001A)
+#define MCFGPIO_PDDR_G          (MCF_IPSBAR + 0x0010001A)
-#define MCFGPIO_DDRH            (MCF_IPSBAR + 0x0010001B)
+#define MCFGPIO_PDDR_H          (MCF_IPSBAR + 0x0010001B)
-#define MCFGPIO_DDRJ            (MCF_IPSBAR + 0x0010001C)
+#define MCFGPIO_PDDR_J          (MCF_IPSBAR + 0x0010001C)
-#define MCFGPIO_DDRDD           (MCF_IPSBAR + 0x0010001D)
+#define MCFGPIO_PDDR_DD         (MCF_IPSBAR + 0x0010001D)
-#define MCFGPIO_DDREH           (MCF_IPSBAR + 0x0010001E)
+#define MCFGPIO_PDDR_EH         (MCF_IPSBAR + 0x0010001E)
-#define MCFGPIO_DDREL           (MCF_IPSBAR + 0x0010001F)
+#define MCFGPIO_PDDR_EL         (MCF_IPSBAR + 0x0010001F)
-#define MCFGPIO_DDRAS           (MCF_IPSBAR + 0x00100020)
+#define MCFGPIO_PDDR_AS         (MCF_IPSBAR + 0x00100020)
-#define MCFGPIO_DDRQS           (MCF_IPSBAR + 0x00100021)
+#define MCFGPIO_PDDR_QS         (MCF_IPSBAR + 0x00100021)
-#define MCFGPIO_DDRSD           (MCF_IPSBAR + 0x00100022)
+#define MCFGPIO_PDDR_SD         (MCF_IPSBAR + 0x00100022)
-#define MCFGPIO_DDRTC           (MCF_IPSBAR + 0x00100023)
+#define MCFGPIO_PDDR_TC         (MCF_IPSBAR + 0x00100023)
-#define MCFGPIO_DDRTD           (MCF_IPSBAR + 0x00100024)
+#define MCFGPIO_PDDR_TD         (MCF_IPSBAR + 0x00100024)
-#define MCFGPIO_DDRUA           (MCF_IPSBAR + 0x00100025)
+#define MCFGPIO_PDDR_UA         (MCF_IPSBAR + 0x00100025)
-#define MCFGPIO_PORTAP          (MCF_IPSBAR + 0x00100028)
+#define MCFGPIO_PPDSDR_A        (MCF_IPSBAR + 0x00100028)
-#define MCFGPIO_PORTBP          (MCF_IPSBAR + 0x00100029)
+#define MCFGPIO_PPDSDR_B        (MCF_IPSBAR + 0x00100029)
-#define MCFGPIO_PORTCP          (MCF_IPSBAR + 0x0010002A)
+#define MCFGPIO_PPDSDR_C        (MCF_IPSBAR + 0x0010002A)
-#define MCFGPIO_PORTDP          (MCF_IPSBAR + 0x0010002B)
+#define MCFGPIO_PPDSDR_D        (MCF_IPSBAR + 0x0010002B)
-#define MCFGPIO_PORTEP          (MCF_IPSBAR + 0x0010002C)
+#define MCFGPIO_PPDSDR_E        (MCF_IPSBAR + 0x0010002C)
-#define MCFGPIO_PORTFP          (MCF_IPSBAR + 0x0010002D)
+#define MCFGPIO_PPDSDR_F        (MCF_IPSBAR + 0x0010002D)
-#define MCFGPIO_PORTGP          (MCF_IPSBAR + 0x0010002E)
+#define MCFGPIO_PPDSDR_G        (MCF_IPSBAR + 0x0010002E)
-#define MCFGPIO_PORTHP          (MCF_IPSBAR + 0x0010002F)
+#define MCFGPIO_PPDSDR_H        (MCF_IPSBAR + 0x0010002F)
-#define MCFGPIO_PORTJP          (MCF_IPSBAR + 0x00100030)
+#define MCFGPIO_PPDSDR_J        (MCF_IPSBAR + 0x00100030)
-#define MCFGPIO_PORTDDP         (MCF_IPSBAR + 0x00100031)
+#define MCFGPIO_PPDSDR_DD       (MCF_IPSBAR + 0x00100031)
-#define MCFGPIO_PORTEHP         (MCF_IPSBAR + 0x00100032)
+#define MCFGPIO_PPDSDR_EH       (MCF_IPSBAR + 0x00100032)
-#define MCFGPIO_PORTELP         (MCF_IPSBAR + 0x00100033)
+#define MCFGPIO_PPDSDR_EL       (MCF_IPSBAR + 0x00100033)
-#define MCFGPIO_PORTASP         (MCF_IPSBAR + 0x00100034)
+#define MCFGPIO_PPDSDR_AS       (MCF_IPSBAR + 0x00100034)
-#define MCFGPIO_PORTQSP         (MCF_IPSBAR + 0x00100035)
+#define MCFGPIO_PPDSDR_QS       (MCF_IPSBAR + 0x00100035)
-#define MCFGPIO_PORTSDP         (MCF_IPSBAR + 0x00100036)
+#define MCFGPIO_PPDSDR_SD       (MCF_IPSBAR + 0x00100036)
-#define MCFGPIO_PORTTCP         (MCF_IPSBAR + 0x00100037)
+#define MCFGPIO_PPDSDR_TC       (MCF_IPSBAR + 0x00100037)
-#define MCFGPIO_PORTTDP         (MCF_IPSBAR + 0x00100038)
+#define MCFGPIO_PPDSDR_TD       (MCF_IPSBAR + 0x00100038)
-#define MCFGPIO_PORTUAP         (MCF_IPSBAR + 0x00100039)
+#define MCFGPIO_PPDSDR_UA       (MCF_IPSBAR + 0x00100039)
-#define MCFGPIO_SETA            (MCF_IPSBAR + 0x00100028)
+#define MCFGPIO_PCLRR_A         (MCF_IPSBAR + 0x0010003C)
-#define MCFGPIO_SETB            (MCF_IPSBAR + 0x00100029)
+#define MCFGPIO_PCLRR_B         (MCF_IPSBAR + 0x0010003D)
-#define MCFGPIO_SETC            (MCF_IPSBAR + 0x0010002A)
+#define MCFGPIO_PCLRR_C         (MCF_IPSBAR + 0x0010003E)
-#define MCFGPIO_SETD            (MCF_IPSBAR + 0x0010002B)
+#define MCFGPIO_PCLRR_D         (MCF_IPSBAR + 0x0010003F)
-#define MCFGPIO_SETE            (MCF_IPSBAR + 0x0010002C)
+#define MCFGPIO_PCLRR_E         (MCF_IPSBAR + 0x00100040)
-#define MCFGPIO_SETF            (MCF_IPSBAR + 0x0010002D)
+#define MCFGPIO_PCLRR_F         (MCF_IPSBAR + 0x00100041)
-#define MCFGPIO_SETG            (MCF_IPSBAR + 0x0010002E)
+#define MCFGPIO_PCLRR_G         (MCF_IPSBAR + 0x00100042)
-#define MCFGPIO_SETH            (MCF_IPSBAR + 0x0010002F)
+#define MCFGPIO_PCLRR_H         (MCF_IPSBAR + 0x00100043)
-#define MCFGPIO_SETJ            (MCF_IPSBAR + 0x00100030)
+#define MCFGPIO_PCLRR_J         (MCF_IPSBAR + 0x00100044)
-#define MCFGPIO_SETDD           (MCF_IPSBAR + 0x00100031)
+#define MCFGPIO_PCLRR_DD        (MCF_IPSBAR + 0x00100045)
-#define MCFGPIO_SETEH           (MCF_IPSBAR + 0x00100032)
+#define MCFGPIO_PCLRR_EH        (MCF_IPSBAR + 0x00100046)
-#define MCFGPIO_SETEL           (MCF_IPSBAR + 0x00100033)
+#define MCFGPIO_PCLRR_EL        (MCF_IPSBAR + 0x00100047)
-#define MCFGPIO_SETAS           (MCF_IPSBAR + 0x00100034)
+#define MCFGPIO_PCLRR_AS        (MCF_IPSBAR + 0x00100048)
-#define MCFGPIO_SETQS           (MCF_IPSBAR + 0x00100035)
+#define MCFGPIO_PCLRR_QS        (MCF_IPSBAR + 0x00100049)
-#define MCFGPIO_SETSD           (MCF_IPSBAR + 0x00100036)
+#define MCFGPIO_PCLRR_SD        (MCF_IPSBAR + 0x0010004A)
-#define MCFGPIO_SETTC           (MCF_IPSBAR + 0x00100037)
+#define MCFGPIO_PCLRR_TC        (MCF_IPSBAR + 0x0010004B)
-#define MCFGPIO_SETTD           (MCF_IPSBAR + 0x00100038)
+#define MCFGPIO_PCLRR_TD        (MCF_IPSBAR + 0x0010004C)
-#define MCFGPIO_SETUA           (MCF_IPSBAR + 0x00100039)
+#define MCFGPIO_PCLRR_UA        (MCF_IPSBAR + 0x0010004D)
-#define MCFGPIO_CLRA            (MCF_IPSBAR + 0x0010003C)
-#define MCFGPIO_CLRB            (MCF_IPSBAR + 0x0010003D)
-#define MCFGPIO_CLRC            (MCF_IPSBAR + 0x0010003E)
-#define MCFGPIO_CLRD            (MCF_IPSBAR + 0x0010003F)
-#define MCFGPIO_CLRE            (MCF_IPSBAR + 0x00100040)
-#define MCFGPIO_CLRF            (MCF_IPSBAR + 0x00100041)
-#define MCFGPIO_CLRG            (MCF_IPSBAR + 0x00100042)
-#define MCFGPIO_CLRH            (MCF_IPSBAR + 0x00100043)
-#define MCFGPIO_CLRJ            (MCF_IPSBAR + 0x00100044)
-#define MCFGPIO_CLRDD           (MCF_IPSBAR + 0x00100045)
-#define MCFGPIO_CLREH           (MCF_IPSBAR + 0x00100046)
-#define MCFGPIO_CLREL           (MCF_IPSBAR + 0x00100047)
-#define MCFGPIO_CLRAS           (MCF_IPSBAR + 0x00100048)
-#define MCFGPIO_CLRQS           (MCF_IPSBAR + 0x00100049)
-#define MCFGPIO_CLRSD           (MCF_IPSBAR + 0x0010004A)
-#define MCFGPIO_CLRTC           (MCF_IPSBAR + 0x0010004B)
-#define MCFGPIO_CLRTD           (MCF_IPSBAR + 0x0010004C)
-#define MCFGPIO_CLRUA           (MCF_IPSBAR + 0x0010004D)
 #define MCFGPIO_PBCDPAR         (MCF_IPSBAR + 0x00100050)
 #define MCFGPIO_PFPAR           (MCF_IPSBAR + 0x00100051)
@@ -242,11 +223,11 @@
 * definitions for generic gpio support
 *
 */
-#define MCFGPIO_PODR            MCFGPIO_PORTA   /* port output data */
+#define MCFGPIO_PODR            MCFGPIO_PODR_A  /* port output data */
-#define MCFGPIO_PDDR            MCFGPIO_DDRA    /* port data direction */
+#define MCFGPIO_PDDR            MCFGPIO_PDDR_A  /* port data direction */
-#define MCFGPIO_PPDR            MCFGPIO_PORTAP  /* port pin data */
+#define MCFGPIO_PPDR            MCFGPIO_PPDSDR_A/* port pin data */
-#define MCFGPIO_SETR            MCFGPIO_SETA    /* set output */
+#define MCFGPIO_SETR            MCFGPIO_PPDSDR_A/* set output */
-#define MCFGPIO_CLRR            MCFGPIO_CLRA    /* clr output */
+#define MCFGPIO_CLRR            MCFGPIO_PCLRR_A /* clr output */
 #define MCFGPIO_IRQ_MAX         8
 #define MCFGPIO_IRQ_VECBASE     MCFINT_VECBASE
diff --git a/arch/m68k/include/asm/mcfgpio.h b/arch/m68k/include/asm/mcfgpio.h
index ee5e4ccce89e..fe468eaa51e0 100644
--- a/arch/m68k/include/asm/mcfgpio.h
+++ b/arch/m68k/include/asm/mcfgpio.h
@@ -29,6 +29,9 @@ struct mcf_gpio_chip {
        const u8 *gpio_to_pinmux;
 };
+extern struct mcf_gpio_chip mcf_gpio_chips[];
+extern unsigned int mcf_gpio_chips_size;
 int mcf_gpio_direction_input(struct gpio_chip *, unsigned);
 int mcf_gpio_get_value(struct gpio_chip *, unsigned);
 int mcf_gpio_direction_output(struct gpio_chip *, unsigned, int);
@@ -37,4 +40,58 @@ void mcf_gpio_set_value_fast(struct gpio_chip *, unsigned, int);
 int mcf_gpio_request(struct gpio_chip *, unsigned);
 void mcf_gpio_free(struct gpio_chip *, unsigned);
+/*
+ *      Define macros to ease the pain of setting up the GPIO tables. There
+ *      are two cases we need to deal with here, they cover all currently
+ *      available ColdFire GPIO hardware. There are of course minor differences
+ *      in the layout and number of bits in each ColdFire part, but the macros
+ *      take all that in.
+ *
+ *      Firstly is the conventional GPIO registers where we toggle individual
+ *      bits in a register, preserving the other bits in the register. For
+ *      lack of a better term I have called this the slow method.
+ */
+#define MCFGPS(mlabel, mbase, mngpio, mpddr, mpodr, mppdr)                  \
+        {                                                                   \
+                .gpio_chip                      = {                         \
+                        .label                  = #mlabel,                  \
+                        .request                = mcf_gpio_request,         \
+                        .free                   = mcf_gpio_free,            \
+                        .direction_input        = mcf_gpio_direction_input, \
+                        .direction_output       = mcf_gpio_direction_output,\
+                        .get                    = mcf_gpio_get_value,       \
+                        .set                    = mcf_gpio_set_value,       \
+                        .base                   = mbase,                    \
+                        .ngpio                  = mngpio,                   \
+                },                                                          \
+                .pddr           = (void __iomem *) mpddr,                   \
+                .podr           = (void __iomem *) mpodr,                   \
+                .ppdr           = (void __iomem *) mppdr,                   \
+        }
+/*
+ *      Secondly is the faster case, where we have set and clear registers
+ *      that allow us to set or clear a bit with a single write, not having
+ *      to worry about preserving other bits.
+ */
+#define MCFGPF(mlabel, mbase, mngpio)                                       \
+        {                                                                   \
+                .gpio_chip                      = {                         \
+                        .label                  = #mlabel,                  \
+                        .request                = mcf_gpio_request,         \
+                        .free                   = mcf_gpio_free,            \
+                        .direction_input        = mcf_gpio_direction_input, \
+                        .direction_output       = mcf_gpio_direction_output,\
+                        .get                    = mcf_gpio_get_value,       \
+                        .set                    = mcf_gpio_set_value_fast,  \
+                        .base                   = mbase,                    \
+                        .ngpio                  = mngpio,                   \
+                },                                                          \
+                .pddr           = (void __iomem *) MCFGPIO_PDDR_##mlabel,   \
+                .podr           = (void __iomem *) MCFGPIO_PODR_##mlabel,   \
+                .ppdr           = (void __iomem *) MCFGPIO_PPDSDR_##mlabel, \
+                .setr           = (void __iomem *) MCFGPIO_PPDSDR_##mlabel, \
+                .clrr           = (void __iomem *) MCFGPIO_PCLRR_##mlabel,  \
+        }
 #endif
diff --git a/arch/m68k/include/asm/unaligned.h b/arch/m68k/include/asm/unaligned.h
index 019caa740c21..f4043ae63db1 100644
--- a/arch/m68k/include/asm/unaligned.h
+++ b/arch/m68k/include/asm/unaligned.h
@@ -2,7 +2,7 @@
 #define _ASM_M68K_UNALIGNED_H
-#ifdef CONFIG_COLDFIRE
+#if defined(CONFIG_COLDFIRE) || defined(CONFIG_M68000)
 #include <linux/unaligned/be_struct.h>
 #include <linux/unaligned/le_byteshift.h>
 #include <linux/unaligned/generic.h>
diff --git a/arch/m68k/include/asm/vga.h b/arch/m68k/include/asm/vga.h
new file mode 100644
index 000000000000..d3aa1401e7aa
--- /dev/null
+++ b/arch/m68k/include/asm/vga.h
@@ -0,0 +1,27 @@
+#ifndef _ASM_M68K_VGA_H
+#define _ASM_M68K_VGA_H
+#include <asm/raw_io.h>
+/*
+ * FIXME
+ * Ugh, we don't have PCI space, so map readb() and friends to use raw I/O
+ * accessors, which are identical to the z_*() Zorro bus accessors.
+ * This should make cirrusfb work again on Amiga
+ */
+#undef inb_p
+#undef inw_p
+#undef outb_p
+#undef outw
+#undef readb
+#undef writeb
+#undef writew
+#define inb_p(port)             0
+#define inw_p(port)             0
+#define outb_p(port, val)       do { } while (0)
+#define outw(port, val)         do { } while (0)
+#define readb                   raw_inb
+#define writeb                  raw_outb
+#define writew                  raw_outw
+#endif /* _ASM_M68K_VGA_H */
diff --git a/arch/m68k/kernel/Makefile b/arch/m68k/kernel/Makefile
index 40d29a788b05..5c7070e21eb7 100644
--- a/arch/m68k/kernel/Makefile
+++ b/arch/m68k/kernel/Makefile
@@ -13,7 +13,7 @@ extra-$(CONFIG_SUN3X)	:= head.o
 extra-$(CONFIG_SUN3)    := sun3-head.o
 extra-y                 += vmlinux.lds
-obj-y   := entry.o init_task.o irq.o m68k_ksyms.o module.o process.o ptrace.o
+obj-y   := entry.o irq.o m68k_ksyms.o module.o process.o ptrace.o
 obj-y   += setup.o signal.o sys_m68k.o syscalltable.o time.o traps.o
 obj-$(CONFIG_MMU_MOTOROLA) += ints.o vectors.o
diff --git a/arch/m68k/kernel/dma.c b/arch/m68k/kernel/dma.c
index 90e8cb726c8c..f6daf6e15d2e 100644
--- a/arch/m68k/kernel/dma.c
+++ b/arch/m68k/kernel/dma.c
@@ -1,5 +1,164 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file COPYING in the main directory of this archive
+ * for more details.
+ */
+#undef DEBUG
+#include <linux/dma-mapping.h>
+#include <linux/device.h>
+#include <linux/kernel.h>
+#include <linux/scatterlist.h>
+#include <linux/slab.h>
+#include <linux/vmalloc.h>
+#include <linux/export.h>
+#include <asm/pgalloc.h>
 #ifdef CONFIG_MMU
-#include "dma_mm.c"
+void *dma_alloc_coherent(struct device *dev, size_t size,
+                         dma_addr_t *handle, gfp_t flag)
+{
+        struct page *page, **map;
+        pgprot_t pgprot;
+        void *addr;
+        int i, order;
+        pr_debug("dma_alloc_coherent: %d,%x\n", size, flag);
+        size = PAGE_ALIGN(size);
+        order = get_order(size);
+        page = alloc_pages(flag, order);
+        if (!page)
+                return NULL;
+        *handle = page_to_phys(page);
+        map = kmalloc(sizeof(struct page *) << order, flag & ~__GFP_DMA);
+        if (!map) {
+                __free_pages(page, order);
+                return NULL;
+        }
+        split_page(page, order);
+        order = 1 << order;
+        size >>= PAGE_SHIFT;
+        map[0] = page;
+        for (i = 1; i < size; i++)
+                map[i] = page + i;
+        for (; i < order; i++)
+                __free_page(page + i);
+        pgprot = __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_DIRTY);
+        if (CPU_IS_040_OR_060)
+                pgprot_val(pgprot) |= _PAGE_GLOBAL040 | _PAGE_NOCACHE_S;
+        else
+                pgprot_val(pgprot) |= _PAGE_NOCACHE030;
+        addr = vmap(map, size, VM_MAP, pgprot);
+        kfree(map);
+        return addr;
+}
+void dma_free_coherent(struct device *dev, size_t size,
+                       void *addr, dma_addr_t handle)
+{
+        pr_debug("dma_free_coherent: %p, %x\n", addr, handle);
+        vfree(addr);
+}
 #else
-#include "dma_no.c"
-#endif
+#include <asm/cacheflush.h>
+void *dma_alloc_coherent(struct device *dev, size_t size,
+                           dma_addr_t *dma_handle, gfp_t gfp)
+{
+        void *ret;
+        /* ignore region specifiers */
+        gfp &= ~(__GFP_DMA | __GFP_HIGHMEM);
+        if (dev == NULL || (*dev->dma_mask < 0xffffffff))
+                gfp |= GFP_DMA;
+        ret = (void *)__get_free_pages(gfp, get_order(size));
+        if (ret != NULL) {
+                memset(ret, 0, size);
+                *dma_handle = virt_to_phys(ret);
+        }
+        return ret;
+}
+void dma_free_coherent(struct device *dev, size_t size,
+                         void *vaddr, dma_addr_t dma_handle)
+{
+        free_pages((unsigned long)vaddr, get_order(size));
+}
+#endif /* CONFIG_MMU */
+EXPORT_SYMBOL(dma_alloc_coherent);
+EXPORT_SYMBOL(dma_free_coherent);
+void dma_sync_single_for_device(struct device *dev, dma_addr_t handle,
+                                size_t size, enum dma_data_direction dir)
+{
+        switch (dir) {
+        case DMA_TO_DEVICE:
+                cache_push(handle, size);
+                break;
+        case DMA_FROM_DEVICE:
+                cache_clear(handle, size);
+                break;
+        default:
+                if (printk_ratelimit())
+                        printk("dma_sync_single_for_device: unsupported dir %u\n", dir);
+                break;
+        }
+}
+EXPORT_SYMBOL(dma_sync_single_for_device);
+void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nents,
+                            enum dma_data_direction dir)
+{
+        int i;
+        for (i = 0; i < nents; sg++, i++)
+                dma_sync_single_for_device(dev, sg->dma_address, sg->length, dir);
+}
+EXPORT_SYMBOL(dma_sync_sg_for_device);
+dma_addr_t dma_map_single(struct device *dev, void *addr, size_t size,
+                          enum dma_data_direction dir)
+{
+        dma_addr_t handle = virt_to_bus(addr);
+        dma_sync_single_for_device(dev, handle, size, dir);
+        return handle;
+}
+EXPORT_SYMBOL(dma_map_single);
+dma_addr_t dma_map_page(struct device *dev, struct page *page,
+                        unsigned long offset, size_t size,
+                        enum dma_data_direction dir)
+{
+        dma_addr_t handle = page_to_phys(page) + offset;
+        dma_sync_single_for_device(dev, handle, size, dir);
+        return handle;
+}
+EXPORT_SYMBOL(dma_map_page);
+int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
+               enum dma_data_direction dir)
+{
+        int i;
+        for (i = 0; i < nents; sg++, i++) {
+                sg->dma_address = sg_phys(sg);
+                dma_sync_single_for_device(dev, sg->dma_address, sg->length, dir);
+        }
+        return nents;
+}
+EXPORT_SYMBOL(dma_map_sg);
diff --git a/arch/m68k/kernel/dma_mm.c b/arch/m68k/kernel/dma_mm.c
deleted file mode 100644
index a3c471b523f2..000000000000
--- a/arch/m68k/kernel/dma_mm.c
+++ /dev/null
@@ -1,131 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file COPYING in the main directory of this archive
- * for more details.
- */
-#undef DEBUG
-#include <linux/dma-mapping.h>
-#include <linux/device.h>
-#include <linux/kernel.h>
-#include <linux/scatterlist.h>
-#include <linux/slab.h>
-#include <linux/vmalloc.h>
-#include <linux/export.h>
-#include <asm/pgalloc.h>
-void *dma_alloc_coherent(struct device *dev, size_t size,
-                         dma_addr_t *handle, gfp_t flag)
-{
-        struct page *page, **map;
-        pgprot_t pgprot;
-        void *addr;
-        int i, order;
-        pr_debug("dma_alloc_coherent: %d,%x\n", size, flag);
-        size = PAGE_ALIGN(size);
-        order = get_order(size);
-        page = alloc_pages(flag, order);
-        if (!page)
-                return NULL;
-        *handle = page_to_phys(page);
-        map = kmalloc(sizeof(struct page *) << order, flag & ~__GFP_DMA);
-        if (!map) {
-                __free_pages(page, order);
-                return NULL;
-        }
-        split_page(page, order);
-        order = 1 << order;
-        size >>= PAGE_SHIFT;
-        map[0] = page;
-        for (i = 1; i < size; i++)
-                map[i] = page + i;
-        for (; i < order; i++)
-                __free_page(page + i);
-        pgprot = __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_DIRTY);
-        if (CPU_IS_040_OR_060)
-                pgprot_val(pgprot) |= _PAGE_GLOBAL040 | _PAGE_NOCACHE_S;
-        else
-                pgprot_val(pgprot) |= _PAGE_NOCACHE030;
-        addr = vmap(map, size, VM_MAP, pgprot);
-        kfree(map);
-        return addr;
-}
-EXPORT_SYMBOL(dma_alloc_coherent);
-void dma_free_coherent(struct device *dev, size_t size,
-                       void *addr, dma_addr_t handle)
-{
-        pr_debug("dma_free_coherent: %p, %x\n", addr, handle);
-        vfree(addr);
-}
-EXPORT_SYMBOL(dma_free_coherent);
-void dma_sync_single_for_device(struct device *dev, dma_addr_t handle,
-                                size_t size, enum dma_data_direction dir)
-{
-        switch (dir) {
-        case DMA_TO_DEVICE:
-                cache_push(handle, size);
-                break;
-        case DMA_FROM_DEVICE:
-                cache_clear(handle, size);
-                break;
-        default:
-                if (printk_ratelimit())
-                        printk("dma_sync_single_for_device: unsupported dir %u\n", dir);
-                break;
-        }
-}
-EXPORT_SYMBOL(dma_sync_single_for_device);
-void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nents,
-                            enum dma_data_direction dir)
-{
-        int i;
-        for (i = 0; i < nents; sg++, i++)
-                dma_sync_single_for_device(dev, sg->dma_address, sg->length, dir);
-}
-EXPORT_SYMBOL(dma_sync_sg_for_device);
-dma_addr_t dma_map_single(struct device *dev, void *addr, size_t size,
-                          enum dma_data_direction dir)
-{
-        dma_addr_t handle = virt_to_bus(addr);
-        dma_sync_single_for_device(dev, handle, size, dir);
-        return handle;
-}
-EXPORT_SYMBOL(dma_map_single);
-dma_addr_t dma_map_page(struct device *dev, struct page *page,
-                        unsigned long offset, size_t size,
-                        enum dma_data_direction dir)
-{
-        dma_addr_t handle = page_to_phys(page) + offset;
-        dma_sync_single_for_device(dev, handle, size, dir);
-        return handle;
-}
-EXPORT_SYMBOL(dma_map_page);
-int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
-               enum dma_data_direction dir)
-{
-        int i;
-        for (i = 0; i < nents; sg++, i++) {
-                sg->dma_address = sg_phys(sg);
-                dma_sync_single_for_device(dev, sg->dma_address, sg->length, dir);
-        }
-        return nents;
-}
-EXPORT_SYMBOL(dma_map_sg);
diff --git a/arch/m68k/kernel/dma_no.c b/arch/m68k/kernel/dma_no.c
deleted file mode 100644
index f1dc3fc71bc2..000000000000
--- a/arch/m68k/kernel/dma_no.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * Dynamic DMA mapping support.
- *
- * We never have any address translations to worry about, so this
- * is just alloc/free.
- */
-#include <linux/types.h>
-#include <linux/gfp.h>
-#include <linux/mm.h>
-#include <linux/device.h>
-#include <linux/dma-mapping.h>
-#include <linux/export.h>
-#include <asm/cacheflush.h>
-void *dma_alloc_coherent(struct device *dev, size_t size,
-                           dma_addr_t *dma_handle, gfp_t gfp)
-{
-        void *ret;
-        /* ignore region specifiers */
-        gfp &= ~(__GFP_DMA | __GFP_HIGHMEM);
-        if (dev == NULL || (*dev->dma_mask < 0xffffffff))
-                gfp |= GFP_DMA;
-        ret = (void *)__get_free_pages(gfp, get_order(size));
-        if (ret != NULL) {
-                memset(ret, 0, size);
-                *dma_handle = virt_to_phys(ret);
-        }
-        return ret;
-}
-void dma_free_coherent(struct device *dev, size_t size,
-                         void *vaddr, dma_addr_t dma_handle)
-{
-        free_pages((unsigned long)vaddr, get_order(size));
-}
-void dma_sync_single_for_device(struct device *dev, dma_addr_t handle,
-                                size_t size, enum dma_data_direction dir)
-{
-        switch (dir) {
-        case DMA_TO_DEVICE:
-                flush_dcache_range(handle, size);
-                break;
-        case DMA_FROM_DEVICE:
-                /* Should be clear already */
-                break;
-        default:
-                if (printk_ratelimit())
-                        printk("dma_sync_single_for_device: unsupported dir %u\n", dir);
-                break;
-        }
-}
-EXPORT_SYMBOL(dma_sync_single_for_device);
-dma_addr_t dma_map_single(struct device *dev, void *addr, size_t size,
-                          enum dma_data_direction dir)
-{
-        dma_addr_t handle = virt_to_phys(addr);
-        flush_dcache_range(handle, size);
-        return handle;
-}
-EXPORT_SYMBOL(dma_map_single);
-dma_addr_t dma_map_page(struct device *dev, struct page *page,
-                        unsigned long offset, size_t size,
-                        enum dma_data_direction dir)
-{
-        dma_addr_t handle = page_to_phys(page) + offset;
-        dma_sync_single_for_device(dev, handle, size, dir);
-        return handle;
-}
-EXPORT_SYMBOL(dma_map_page);
diff --git a/arch/m68k/kernel/init_task.c b/arch/m68k/kernel/init_task.c
deleted file mode 100644
index c744cfc6bfa1..000000000000
--- a/arch/m68k/kernel/init_task.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- *  linux/arch/m68knommu/kernel/init_task.c
- */
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/sched.h>
-#include <linux/init.h>
-#include <linux/init_task.h>
-#include <linux/fs.h>
-#include <linux/mqueue.h>
-#include <asm/uaccess.h>
-#include <asm/pgtable.h>
-static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
-static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
-/*
- * Initial task structure.
- *
- * All other task structs will be allocated on slabs in fork.c
- */
-struct task_struct init_task = INIT_TASK(init_task);
-EXPORT_SYMBOL(init_task);
-/*
- * Initial thread structure.
- *
- * We need to make sure that this is THREAD size aligned due to the
- * way process stacks are handled. This is done by having a special
- * "init_task" linker map entry..
- */
-union thread_union init_thread_union __init_task_data =
-        { INIT_THREAD_INFO(init_task) };
diff --git a/arch/m68k/kernel/signal.c b/arch/m68k/kernel/signal.c
index 2e25713e2ead..1747c7030a33 100644
--- a/arch/m68k/kernel/signal.c
+++ b/arch/m68k/kernel/signal.c
@@ -1,5 +1,1202 @@
+/*
+ *  linux/arch/m68k/kernel/signal.c
+ *
+ *  Copyright (C) 1991, 1992  Linus Torvalds
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file COPYING in the main directory of this archive
+ * for more details.
+ */
+/*
+ * Linux/m68k support by Hamish Macdonald
+ *
+ * 68060 fixes by Jesper Skov
+ *
+ * 1997-12-01  Modified for POSIX.1b signals by Andreas Schwab
+ *
+ * mathemu support by Roman Zippel
+ *  (Note: fpstate in the signal context is completely ignored for the emulator
+ *         and the internal floating point format is put on stack)
+ */
+/*
+ * ++roman (07/09/96): implemented signal stacks (specially for tosemu on
+ * Atari :-) Current limitation: Only one sigstack can be active at one time.
+ * If a second signal with SA_ONSTACK set arrives while working on a sigstack,
+ * SA_ONSTACK is ignored. This behaviour avoids lots of trouble with nested
+ * signal handlers!
+ */
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <linux/kernel.h>
+#include <linux/signal.h>
+#include <linux/syscalls.h>
+#include <linux/errno.h>
+#include <linux/wait.h>
+#include <linux/ptrace.h>
+#include <linux/unistd.h>
+#include <linux/stddef.h>
+#include <linux/highuid.h>
+#include <linux/personality.h>
+#include <linux/tty.h>
+#include <linux/binfmts.h>
+#include <linux/module.h>
+#include <asm/setup.h>
+#include <asm/uaccess.h>
+#include <asm/pgtable.h>
+#include <asm/traps.h>
+#include <asm/ucontext.h>
+#define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP)))
 #ifdef CONFIG_MMU
-#include "signal_mm.c"
+/*
+ * Handle the slight differences in classic 68k and ColdFire trap frames.
+ */
+#ifdef CONFIG_COLDFIRE
+#define FORMAT          4
+#define FMT4SIZE        0
 #else
-#include "signal_no.c"
+#define FORMAT          0
+#define FMT4SIZE        sizeof(((struct frame *)0)->un.fmt4)
 #endif
+static const int frame_size_change[16] = {
+  [1]   = -1, /* sizeof(((struct frame *)0)->un.fmt1), */
+  [2]   = sizeof(((struct frame *)0)->un.fmt2),
+  [3]   = sizeof(((struct frame *)0)->un.fmt3),
+  [4]   = FMT4SIZE,
+  [5]   = -1, /* sizeof(((struct frame *)0)->un.fmt5), */
+  [6]   = -1, /* sizeof(((struct frame *)0)->un.fmt6), */
+  [7]   = sizeof(((struct frame *)0)->un.fmt7),
+  [8]   = -1, /* sizeof(((struct frame *)0)->un.fmt8), */
+  [9]   = sizeof(((struct frame *)0)->un.fmt9),
+  [10]  = sizeof(((struct frame *)0)->un.fmta),
+  [11]  = sizeof(((struct frame *)0)->un.fmtb),
+  [12]  = -1, /* sizeof(((struct frame *)0)->un.fmtc), */
+  [13]  = -1, /* sizeof(((struct frame *)0)->un.fmtd), */
+  [14]  = -1, /* sizeof(((struct frame *)0)->un.fmte), */
+  [15]  = -1, /* sizeof(((struct frame *)0)->un.fmtf), */
+};
+static inline int frame_extra_sizes(int f)
+{
+        return frame_size_change[f];
+}
+int handle_kernel_fault(struct pt_regs *regs)
+{
+        const struct exception_table_entry *fixup;
+        struct pt_regs *tregs;
+        /* Are we prepared to handle this kernel fault? */
+        fixup = search_exception_tables(regs->pc);
+        if (!fixup)
+                return 0;
+        /* Create a new four word stack frame, discarding the old one. */
+        regs->stkadj = frame_extra_sizes(regs->format);
+        tregs = (struct pt_regs *)((long)regs + regs->stkadj);
+        tregs->vector = regs->vector;
+        tregs->format = FORMAT;
+        tregs->pc = fixup->fixup;
+        tregs->sr = regs->sr;
+        return 1;
+}
+void ptrace_signal_deliver(struct pt_regs *regs, void *cookie)
+{
+        if (regs->orig_d0 < 0)
+                return;
+        switch (regs->d0) {
+        case -ERESTARTNOHAND:
+        case -ERESTARTSYS:
+        case -ERESTARTNOINTR:
+                regs->d0 = regs->orig_d0;
+                regs->orig_d0 = -1;
+                regs->pc -= 2;
+                break;
+        }
+}
+static inline void push_cache (unsigned long vaddr)
+{
+        /*
+         * Using the old cache_push_v() was really a big waste.
+         *
+         * What we are trying to do is to flush 8 bytes to ram.
+         * Flushing 2 cache lines of 16 bytes is much cheaper than
+         * flushing 1 or 2 pages, as previously done in
+         * cache_push_v().
+         *                                                     Jes
+         */
+        if (CPU_IS_040) {
+                unsigned long temp;
+                __asm__ __volatile__ (".chip 68040\n\t"
+                                      "nop\n\t"
+                                      "ptestr (%1)\n\t"
+                                      "movec %%mmusr,%0\n\t"
+                                      ".chip 68k"
+                                      : "=r" (temp)
+                                      : "a" (vaddr));
+                temp &= PAGE_MASK;
+                temp |= vaddr & ~PAGE_MASK;
+                __asm__ __volatile__ (".chip 68040\n\t"
+                                      "nop\n\t"
+                                      "cpushl %%bc,(%0)\n\t"
+                                      ".chip 68k"
+                                      : : "a" (temp));
+        }
+        else if (CPU_IS_060) {
+                unsigned long temp;
+                __asm__ __volatile__ (".chip 68060\n\t"
+                                      "plpar (%0)\n\t"
+                                      ".chip 68k"
+                                      : "=a" (temp)
+                                      : "0" (vaddr));
+                __asm__ __volatile__ (".chip 68060\n\t"
+                                      "cpushl %%bc,(%0)\n\t"
+                                      ".chip 68k"
+                                      : : "a" (temp));
+        } else if (!CPU_IS_COLDFIRE) {
+                /*
+                 * 68030/68020 have no writeback cache;
+                 * still need to clear icache.
+                 * Note that vaddr is guaranteed to be long word aligned.
+                 */
+                unsigned long temp;
+                asm volatile ("movec %%cacr,%0" : "=r" (temp));
+                temp += 4;
+                asm volatile ("movec %0,%%caar\n\t"
+                              "movec %1,%%cacr"
+                              : : "r" (vaddr), "r" (temp));
+                asm volatile ("movec %0,%%caar\n\t"
+                              "movec %1,%%cacr"
+                              : : "r" (vaddr + 4), "r" (temp));
+        }
+}
+static inline void adjustformat(struct pt_regs *regs)
+{
+}
+static inline void save_a5_state(struct sigcontext *sc, struct pt_regs *regs)
+{
+}
+#else /* CONFIG_MMU */
+void ret_from_user_signal(void);
+void ret_from_user_rt_signal(void);
+static inline int frame_extra_sizes(int f)
+{
+        /* No frame size adjustments required on non-MMU CPUs */
+        return 0;
+}
+static inline void adjustformat(struct pt_regs *regs)
+{
+        ((struct switch_stack *)regs - 1)->a5 = current->mm->start_data;
+        /*
+         * set format byte to make stack appear modulo 4, which it will
+         * be when doing the rte
+         */
+        regs->format = 0x4;
+}
+static inline void save_a5_state(struct sigcontext *sc, struct pt_regs *regs)
+{
+        sc->sc_a5 = ((struct switch_stack *)regs - 1)->a5;
+}
+static inline void push_cache(unsigned long vaddr)
+{
+}
+#endif /* CONFIG_MMU */
+/*
+ * Atomically swap in the new signal mask, and wait for a signal.
+ */
+asmlinkage int
+sys_sigsuspend(int unused0, int unused1, old_sigset_t mask)
+{
+        mask &= _BLOCKABLE;
+        spin_lock_irq(&current->sighand->siglock);
+        current->saved_sigmask = current->blocked;
+        siginitset(&current->blocked, mask);
+        recalc_sigpending();
+        spin_unlock_irq(&current->sighand->siglock);
+        current->state = TASK_INTERRUPTIBLE;
+        schedule();
+        set_restore_sigmask();
+        return -ERESTARTNOHAND;
+}
+asmlinkage int
+sys_sigaction(int sig, const struct old_sigaction __user *act,
+              struct old_sigaction __user *oact)
+{
+        struct k_sigaction new_ka, old_ka;
+        int ret;
+        if (act) {
+                old_sigset_t mask;
+                if (!access_ok(VERIFY_READ, act, sizeof(*act)) ||
+                    __get_user(new_ka.sa.sa_handler, &act->sa_handler) ||
+                    __get_user(new_ka.sa.sa_restorer, &act->sa_restorer) ||
+                    __get_user(new_ka.sa.sa_flags, &act->sa_flags) ||
+                    __get_user(mask, &act->sa_mask))
+                        return -EFAULT;
+                siginitset(&new_ka.sa.sa_mask, mask);
+        }
+        ret = do_sigaction(sig, act ? &new_ka : NULL, oact ? &old_ka : NULL);
+        if (!ret && oact) {
+                if (!access_ok(VERIFY_WRITE, oact, sizeof(*oact)) ||
+                    __put_user(old_ka.sa.sa_handler, &oact->sa_handler) ||
+                    __put_user(old_ka.sa.sa_restorer, &oact->sa_restorer) ||
+                    __put_user(old_ka.sa.sa_flags, &oact->sa_flags) ||
+                    __put_user(old_ka.sa.sa_mask.sig[0], &oact->sa_mask))
+                        return -EFAULT;
+        }
+        return ret;
+}
+asmlinkage int
+sys_sigaltstack(const stack_t __user *uss, stack_t __user *uoss)
+{
+        return do_sigaltstack(uss, uoss, rdusp());
+}
+/*
+ * Do a signal return; undo the signal stack.
+ *
+ * Keep the return code on the stack quadword aligned!
+ * That makes the cache flush below easier.
+ */
+struct sigframe
+{
+        char __user *pretcode;
+        int sig;
+        int code;
+        struct sigcontext __user *psc;
+        char retcode[8];
+        unsigned long extramask[_NSIG_WORDS-1];
+        struct sigcontext sc;
+};
+struct rt_sigframe
+{
+        char __user *pretcode;
+        int sig;
+        struct siginfo __user *pinfo;
+        void __user *puc;
+        char retcode[8];
+        struct siginfo info;
+        struct ucontext uc;
+};
+#define FPCONTEXT_SIZE  216
+#define uc_fpstate      uc_filler[0]
+#define uc_formatvec    uc_filler[FPCONTEXT_SIZE/4]
+#define uc_extra        uc_filler[FPCONTEXT_SIZE/4+1]
+#ifdef CONFIG_FPU
+static unsigned char fpu_version;       /* version number of fpu, set by setup_frame */
+static inline int restore_fpu_state(struct sigcontext *sc)
+{
+        int err = 1;
+        if (FPU_IS_EMU) {
+            /* restore registers */
+            memcpy(current->thread.fpcntl, sc->sc_fpcntl, 12);
+            memcpy(current->thread.fp, sc->sc_fpregs, 24);
+            return 0;
+        }
+        if (CPU_IS_060 ? sc->sc_fpstate[2] : sc->sc_fpstate[0]) {
+            /* Verify the frame format.  */
+            if (!(CPU_IS_060 || CPU_IS_COLDFIRE) &&
+                 (sc->sc_fpstate[0] != fpu_version))
+                goto out;
+            if (CPU_IS_020_OR_030) {
+                if (m68k_fputype & FPU_68881 &&
+                    !(sc->sc_fpstate[1] == 0x18 || sc->sc_fpstate[1] == 0xb4))
+                    goto out;
+                if (m68k_fputype & FPU_68882 &&
+                    !(sc->sc_fpstate[1] == 0x38 || sc->sc_fpstate[1] == 0xd4))
+                    goto out;
+            } else if (CPU_IS_040) {
+                if (!(sc->sc_fpstate[1] == 0x00 ||
+                      sc->sc_fpstate[1] == 0x28 ||
+                      sc->sc_fpstate[1] == 0x60))
+                    goto out;
+            } else if (CPU_IS_060) {
+                if (!(sc->sc_fpstate[3] == 0x00 ||
+                      sc->sc_fpstate[3] == 0x60 ||
+                      sc->sc_fpstate[3] == 0xe0))
+                    goto out;
+            } else if (CPU_IS_COLDFIRE) {
+                if (!(sc->sc_fpstate[0] == 0x00 ||
+                      sc->sc_fpstate[0] == 0x05 ||
+                      sc->sc_fpstate[0] == 0xe5))
+                    goto out;
+            } else
+                goto out;
+            if (CPU_IS_COLDFIRE) {
+                __asm__ volatile ("fmovemd %0,%%fp0-%%fp1\n\t"
+                                  "fmovel %1,%%fpcr\n\t"
+                                  "fmovel %2,%%fpsr\n\t"
+                                  "fmovel %3,%%fpiar"
+                                  : /* no outputs */
+                                  : "m" (sc->sc_fpregs[0]),
+                                    "m" (sc->sc_fpcntl[0]),
+                                    "m" (sc->sc_fpcntl[1]),
+                                    "m" (sc->sc_fpcntl[2]));
+            } else {
+                __asm__ volatile (".chip 68k/68881\n\t"
+                                  "fmovemx %0,%%fp0-%%fp1\n\t"
+                                  "fmoveml %1,%%fpcr/%%fpsr/%%fpiar\n\t"
+                                  ".chip 68k"
+                                  : /* no outputs */
+                                  : "m" (*sc->sc_fpregs),
+                                    "m" (*sc->sc_fpcntl));
+            }
+        }
+        if (CPU_IS_COLDFIRE) {
+                __asm__ volatile ("frestore %0" : : "m" (*sc->sc_fpstate));
+        } else {
+                __asm__ volatile (".chip 68k/68881\n\t"
+                                  "frestore %0\n\t"
+                                  ".chip 68k"
+                                  : : "m" (*sc->sc_fpstate));
+        }
+        err = 0;
+out:
+        return err;
+}
+static inline int rt_restore_fpu_state(struct ucontext __user *uc)
+{
+        unsigned char fpstate[FPCONTEXT_SIZE];
+        int context_size = CPU_IS_060 ? 8 : (CPU_IS_COLDFIRE ? 12 : 0);
+        fpregset_t fpregs;
+        int err = 1;
+        if (FPU_IS_EMU) {
+                /* restore fpu control register */
+                if (__copy_from_user(current->thread.fpcntl,
+                                uc->uc_mcontext.fpregs.f_fpcntl, 12))
+                        goto out;
+                /* restore all other fpu register */
+                if (__copy_from_user(current->thread.fp,
+                                uc->uc_mcontext.fpregs.f_fpregs, 96))
+                        goto out;
+                return 0;
+        }
+        if (__get_user(*(long *)fpstate, (long __user *)&uc->uc_fpstate))
+                goto out;
+        if (CPU_IS_060 ? fpstate[2] : fpstate[0]) {
+                if (!(CPU_IS_060 || CPU_IS_COLDFIRE))
+                        context_size = fpstate[1];
+                /* Verify the frame format.  */
+                if (!(CPU_IS_060 || CPU_IS_COLDFIRE) &&
+                     (fpstate[0] != fpu_version))
+                        goto out;
+                if (CPU_IS_020_OR_030) {
+                        if (m68k_fputype & FPU_68881 &&
+                            !(context_size == 0x18 || context_size == 0xb4))
+                                goto out;
+                        if (m68k_fputype & FPU_68882 &&
+                            !(context_size == 0x38 || context_size == 0xd4))
+                                goto out;
+                } else if (CPU_IS_040) {
+                        if (!(context_size == 0x00 ||
+                              context_size == 0x28 ||
+                              context_size == 0x60))
+                                goto out;
+                } else if (CPU_IS_060) {
+                        if (!(fpstate[3] == 0x00 ||
+                              fpstate[3] == 0x60 ||
+                              fpstate[3] == 0xe0))
+                                goto out;
+                } else if (CPU_IS_COLDFIRE) {
+                        if (!(fpstate[3] == 0x00 ||
+                              fpstate[3] == 0x05 ||
+                              fpstate[3] == 0xe5))
+                                goto out;
+                } else
+                        goto out;
+                if (__copy_from_user(&fpregs, &uc->uc_mcontext.fpregs,
+                                     sizeof(fpregs)))
+                        goto out;
+                if (CPU_IS_COLDFIRE) {
+                        __asm__ volatile ("fmovemd %0,%%fp0-%%fp7\n\t"
+                                          "fmovel %1,%%fpcr\n\t"
+                                          "fmovel %2,%%fpsr\n\t"
+                                          "fmovel %3,%%fpiar"
+                                          : /* no outputs */
+                                          : "m" (fpregs.f_fpregs[0]),
+                                            "m" (fpregs.f_fpcntl[0]),
+                                            "m" (fpregs.f_fpcntl[1]),
+                                            "m" (fpregs.f_fpcntl[2]));
+                } else {
+                        __asm__ volatile (".chip 68k/68881\n\t"
+                                          "fmovemx %0,%%fp0-%%fp7\n\t"
+                                          "fmoveml %1,%%fpcr/%%fpsr/%%fpiar\n\t"
+                                          ".chip 68k"
+                                          : /* no outputs */
+                                          : "m" (*fpregs.f_fpregs),
+                                            "m" (*fpregs.f_fpcntl));
+                }
+        }
+        if (context_size &&
+            __copy_from_user(fpstate + 4, (long __user *)&uc->uc_fpstate + 1,
+                             context_size))
+                goto out;
+        if (CPU_IS_COLDFIRE) {
+                __asm__ volatile ("frestore %0" : : "m" (*fpstate));
+        } else {
+                __asm__ volatile (".chip 68k/68881\n\t"
+                                  "frestore %0\n\t"
+                                  ".chip 68k"
+                                  : : "m" (*fpstate));
+        }
+        err = 0;
+out:
+        return err;
+}
+/*
+ * Set up a signal frame.
+ */
+static inline void save_fpu_state(struct sigcontext *sc, struct pt_regs *regs)
+{
+        if (FPU_IS_EMU) {
+                /* save registers */
+                memcpy(sc->sc_fpcntl, current->thread.fpcntl, 12);
+                memcpy(sc->sc_fpregs, current->thread.fp, 24);
+                return;
+        }
+        if (CPU_IS_COLDFIRE) {
+                __asm__ volatile ("fsave %0"
+                                  : : "m" (*sc->sc_fpstate) : "memory");
+        } else {
+                __asm__ volatile (".chip 68k/68881\n\t"
+                                  "fsave %0\n\t"
+                                  ".chip 68k"
+                                  : : "m" (*sc->sc_fpstate) : "memory");
+        }
+        if (CPU_IS_060 ? sc->sc_fpstate[2] : sc->sc_fpstate[0]) {
+                fpu_version = sc->sc_fpstate[0];
+                if (CPU_IS_020_OR_030 &&
+                    regs->vector >= (VEC_FPBRUC * 4) &&
+                    regs->vector <= (VEC_FPNAN * 4)) {
+                        /* Clear pending exception in 68882 idle frame */
+                        if (*(unsigned short *) sc->sc_fpstate == 0x1f38)
+                                sc->sc_fpstate[0x38] |= 1 << 3;
+                }
+                if (CPU_IS_COLDFIRE) {
+                        __asm__ volatile ("fmovemd %%fp0-%%fp1,%0\n\t"
+                                          "fmovel %%fpcr,%1\n\t"
+                                          "fmovel %%fpsr,%2\n\t"
+                                          "fmovel %%fpiar,%3"
+                                          : "=m" (sc->sc_fpregs[0]),
+                                            "=m" (sc->sc_fpcntl[0]),
+                                            "=m" (sc->sc_fpcntl[1]),
+                                            "=m" (sc->sc_fpcntl[2])
+                                          : /* no inputs */
+                                          : "memory");
+                } else {
+                        __asm__ volatile (".chip 68k/68881\n\t"
+                                          "fmovemx %%fp0-%%fp1,%0\n\t"
+                                          "fmoveml %%fpcr/%%fpsr/%%fpiar,%1\n\t"
+                                          ".chip 68k"
+                                          : "=m" (*sc->sc_fpregs),
+                                            "=m" (*sc->sc_fpcntl)
+                                          : /* no inputs */
+                                          : "memory");
+                }
+        }
+}
+static inline int rt_save_fpu_state(struct ucontext __user *uc, struct pt_regs *regs)
+{
+        unsigned char fpstate[FPCONTEXT_SIZE];
+        int context_size = CPU_IS_060 ? 8 : (CPU_IS_COLDFIRE ? 12 : 0);
+        int err = 0;
+        if (FPU_IS_EMU) {
+                /* save fpu control register */
+                err |= copy_to_user(uc->uc_mcontext.fpregs.f_fpcntl,
+                                current->thread.fpcntl, 12);
+                /* save all other fpu register */
+                err |= copy_to_user(uc->uc_mcontext.fpregs.f_fpregs,
+                                current->thread.fp, 96);
+                return err;
+        }
+        if (CPU_IS_COLDFIRE) {
+                __asm__ volatile ("fsave %0" : : "m" (*fpstate) : "memory");
+        } else {
+                __asm__ volatile (".chip 68k/68881\n\t"
+                                  "fsave %0\n\t"
+                                  ".chip 68k"
+                                  : : "m" (*fpstate) : "memory");
+        }
+        err |= __put_user(*(long *)fpstate, (long __user *)&uc->uc_fpstate);
+        if (CPU_IS_060 ? fpstate[2] : fpstate[0]) {
+                fpregset_t fpregs;
+                if (!(CPU_IS_060 || CPU_IS_COLDFIRE))
+                        context_size = fpstate[1];
+                fpu_version = fpstate[0];
+                if (CPU_IS_020_OR_030 &&
+                    regs->vector >= (VEC_FPBRUC * 4) &&
+                    regs->vector <= (VEC_FPNAN * 4)) {
+                        /* Clear pending exception in 68882 idle frame */
+                        if (*(unsigned short *) fpstate == 0x1f38)
+                                fpstate[0x38] |= 1 << 3;
+                }
+                if (CPU_IS_COLDFIRE) {
+                        __asm__ volatile ("fmovemd %%fp0-%%fp7,%0\n\t"
+                                          "fmovel %%fpcr,%1\n\t"
+                                          "fmovel %%fpsr,%2\n\t"
+                                          "fmovel %%fpiar,%3"
+                                          : "=m" (fpregs.f_fpregs[0]),
+                                            "=m" (fpregs.f_fpcntl[0]),
+                                            "=m" (fpregs.f_fpcntl[1]),
+                                            "=m" (fpregs.f_fpcntl[2])
+                                          : /* no inputs */
+                                          : "memory");
+                } else {
+                        __asm__ volatile (".chip 68k/68881\n\t"
+                                          "fmovemx %%fp0-%%fp7,%0\n\t"
+                                          "fmoveml %%fpcr/%%fpsr/%%fpiar,%1\n\t"
+                                          ".chip 68k"
+                                          : "=m" (*fpregs.f_fpregs),
+                                            "=m" (*fpregs.f_fpcntl)
+                                          : /* no inputs */
+                                          : "memory");
+                }
+                err |= copy_to_user(&uc->uc_mcontext.fpregs, &fpregs,
+                                    sizeof(fpregs));
+        }
+        if (context_size)
+                err |= copy_to_user((long __user *)&uc->uc_fpstate + 1, fpstate + 4,
+                                    context_size);
+        return err;
+}
+#else /* CONFIG_FPU */
+/*
+ * For the case with no FPU configured these all do nothing.
+ */
+static inline int restore_fpu_state(struct sigcontext *sc)
+{
+        return 0;
+}
+static inline int rt_restore_fpu_state(struct ucontext __user *uc)
+{
+        return 0;
+}
+static inline void save_fpu_state(struct sigcontext *sc, struct pt_regs *regs)
+{
+}
+static inline int rt_save_fpu_state(struct ucontext __user *uc, struct pt_regs *regs)
+{
+        return 0;
+}
+#endif /* CONFIG_FPU */
+static int mangle_kernel_stack(struct pt_regs *regs, int formatvec,
+                               void __user *fp)
+{
+        int fsize = frame_extra_sizes(formatvec >> 12);
+        if (fsize < 0) {
+                /*
+                 * user process trying to return with weird frame format
+                 */
+#ifdef DEBUG
+                printk("user process returning with weird frame format\n");
+#endif
+                return 1;
+        }
+        if (!fsize) {
+                regs->format = formatvec >> 12;
+                regs->vector = formatvec & 0xfff;
+        } else {
+                struct switch_stack *sw = (struct switch_stack *)regs - 1;
+                unsigned long buf[fsize / 2]; /* yes, twice as much */
+                /* that'll make sure that expansion won't crap over data */
+                if (copy_from_user(buf + fsize / 4, fp, fsize))
+                        return 1;
+                /* point of no return */
+                regs->format = formatvec >> 12;
+                regs->vector = formatvec & 0xfff;
+#define frame_offset (sizeof(struct pt_regs)+sizeof(struct switch_stack))
+                __asm__ __volatile__ (
+#ifdef CONFIG_COLDFIRE
+                         "   movel %0,%/sp\n\t"
+                         "   bra ret_from_signal\n"
+#else
+                         "   movel %0,%/a0\n\t"
+                         "   subl %1,%/a0\n\t"     /* make room on stack */
+                         "   movel %/a0,%/sp\n\t"  /* set stack pointer */
+                         /* move switch_stack and pt_regs */
+                         "1: movel %0@+,%/a0@+\n\t"
+                         "   dbra %2,1b\n\t"
+                         "   lea %/sp@(%c3),%/a0\n\t" /* add offset of fmt */
+                         "   lsrl  #2,%1\n\t"
+                         "   subql #1,%1\n\t"
+                         /* copy to the gap we'd made */
+                         "2: movel %4@+,%/a0@+\n\t"
+                         "   dbra %1,2b\n\t"
+                         "   bral ret_from_signal\n"
+#endif
+                         : /* no outputs, it doesn't ever return */
+                         : "a" (sw), "d" (fsize), "d" (frame_offset/4-1),
+                           "n" (frame_offset), "a" (buf + fsize/4)
+                         : "a0");
+#undef frame_offset
+        }
+        return 0;
+}
+static inline int
+restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *usc, void __user *fp)
+{
+        int formatvec;
+        struct sigcontext context;
+        int err = 0;
+        /* Always make any pending restarted system calls return -EINTR */
+        current_thread_info()->restart_block.fn = do_no_restart_syscall;
+        /* get previous context */
+        if (copy_from_user(&context, usc, sizeof(context)))
+                goto badframe;
+        /* restore passed registers */
+        regs->d0 = context.sc_d0;
+        regs->d1 = context.sc_d1;
+        regs->a0 = context.sc_a0;
+        regs->a1 = context.sc_a1;
+        regs->sr = (regs->sr & 0xff00) | (context.sc_sr & 0xff);
+        regs->pc = context.sc_pc;
+        regs->orig_d0 = -1;             /* disable syscall checks */
+        wrusp(context.sc_usp);
+        formatvec = context.sc_formatvec;
+        err = restore_fpu_state(&context);
+        if (err || mangle_kernel_stack(regs, formatvec, fp))
+                goto badframe;
+        return 0;
+badframe:
+        return 1;
+}
+static inline int
+rt_restore_ucontext(struct pt_regs *regs, struct switch_stack *sw,
+                    struct ucontext __user *uc)
+{
+        int temp;
+        greg_t __user *gregs = uc->uc_mcontext.gregs;
+        unsigned long usp;
+        int err;
+        /* Always make any pending restarted system calls return -EINTR */
+        current_thread_info()->restart_block.fn = do_no_restart_syscall;
+        err = __get_user(temp, &uc->uc_mcontext.version);
+        if (temp != MCONTEXT_VERSION)
+                goto badframe;
+        /* restore passed registers */
+        err |= __get_user(regs->d0, &gregs[0]);
+        err |= __get_user(regs->d1, &gregs[1]);
+        err |= __get_user(regs->d2, &gregs[2]);
+        err |= __get_user(regs->d3, &gregs[3]);
+        err |= __get_user(regs->d4, &gregs[4]);
+        err |= __get_user(regs->d5, &gregs[5]);
+        err |= __get_user(sw->d6, &gregs[6]);
+        err |= __get_user(sw->d7, &gregs[7]);
+        err |= __get_user(regs->a0, &gregs[8]);
+        err |= __get_user(regs->a1, &gregs[9]);
+        err |= __get_user(regs->a2, &gregs[10]);
+        err |= __get_user(sw->a3, &gregs[11]);
+        err |= __get_user(sw->a4, &gregs[12]);
+        err |= __get_user(sw->a5, &gregs[13]);
+        err |= __get_user(sw->a6, &gregs[14]);
+        err |= __get_user(usp, &gregs[15]);
+        wrusp(usp);
+        err |= __get_user(regs->pc, &gregs[16]);
+        err |= __get_user(temp, &gregs[17]);
+        regs->sr = (regs->sr & 0xff00) | (temp & 0xff);
+        regs->orig_d0 = -1;             /* disable syscall checks */
+        err |= __get_user(temp, &uc->uc_formatvec);
+        err |= rt_restore_fpu_state(uc);
+        if (err || do_sigaltstack(&uc->uc_stack, NULL, usp) == -EFAULT)
+                goto badframe;
+        if (mangle_kernel_stack(regs, temp, &uc->uc_extra))
+                goto badframe;
+        return 0;
+badframe:
+        return 1;
+}
+asmlinkage int do_sigreturn(unsigned long __unused)
+{
+        struct switch_stack *sw = (struct switch_stack *) &__unused;
+        struct pt_regs *regs = (struct pt_regs *) (sw + 1);
+        unsigned long usp = rdusp();
+        struct sigframe __user *frame = (struct sigframe __user *)(usp - 4);
+        sigset_t set;
+        if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
+                goto badframe;
+        if (__get_user(set.sig[0], &frame->sc.sc_mask) ||
+            (_NSIG_WORDS > 1 &&
+             __copy_from_user(&set.sig[1], &frame->extramask,
+                              sizeof(frame->extramask))))
+                goto badframe;
+        sigdelsetmask(&set, ~_BLOCKABLE);
+        current->blocked = set;
+        recalc_sigpending();
+        if (restore_sigcontext(regs, &frame->sc, frame + 1))
+                goto badframe;
+        return regs->d0;
+badframe:
+        force_sig(SIGSEGV, current);
+        return 0;
+}
+asmlinkage int do_rt_sigreturn(unsigned long __unused)
+{
+        struct switch_stack *sw = (struct switch_stack *) &__unused;
+        struct pt_regs *regs = (struct pt_regs *) (sw + 1);
+        unsigned long usp = rdusp();
+        struct rt_sigframe __user *frame = (struct rt_sigframe __user *)(usp - 4);
+        sigset_t set;
+        if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
+                goto badframe;
+        if (__copy_from_user(&set, &frame->uc.uc_sigmask, sizeof(set)))
+                goto badframe;
+        sigdelsetmask(&set, ~_BLOCKABLE);
+        current->blocked = set;
+        recalc_sigpending();
+        if (rt_restore_ucontext(regs, sw, &frame->uc))
+                goto badframe;
+        return regs->d0;
+badframe:
+        force_sig(SIGSEGV, current);
+        return 0;
+}
+static void setup_sigcontext(struct sigcontext *sc, struct pt_regs *regs,
+                             unsigned long mask)
+{
+        sc->sc_mask = mask;
+        sc->sc_usp = rdusp();
+        sc->sc_d0 = regs->d0;
+        sc->sc_d1 = regs->d1;
+        sc->sc_a0 = regs->a0;
+        sc->sc_a1 = regs->a1;
+        sc->sc_sr = regs->sr;
+        sc->sc_pc = regs->pc;
+        sc->sc_formatvec = regs->format << 12 | regs->vector;
+        save_a5_state(sc, regs);
+        save_fpu_state(sc, regs);
+}
+static inline int rt_setup_ucontext(struct ucontext __user *uc, struct pt_regs *regs)
+{
+        struct switch_stack *sw = (struct switch_stack *)regs - 1;
+        greg_t __user *gregs = uc->uc_mcontext.gregs;
+        int err = 0;
+        err |= __put_user(MCONTEXT_VERSION, &uc->uc_mcontext.version);
+        err |= __put_user(regs->d0, &gregs[0]);
+        err |= __put_user(regs->d1, &gregs[1]);
+        err |= __put_user(regs->d2, &gregs[2]);
+        err |= __put_user(regs->d3, &gregs[3]);
+        err |= __put_user(regs->d4, &gregs[4]);
+        err |= __put_user(regs->d5, &gregs[5]);
+        err |= __put_user(sw->d6, &gregs[6]);
+        err |= __put_user(sw->d7, &gregs[7]);
+        err |= __put_user(regs->a0, &gregs[8]);
+        err |= __put_user(regs->a1, &gregs[9]);
+        err |= __put_user(regs->a2, &gregs[10]);
+        err |= __put_user(sw->a3, &gregs[11]);
+        err |= __put_user(sw->a4, &gregs[12]);
+        err |= __put_user(sw->a5, &gregs[13]);
+        err |= __put_user(sw->a6, &gregs[14]);
+        err |= __put_user(rdusp(), &gregs[15]);
+        err |= __put_user(regs->pc, &gregs[16]);
+        err |= __put_user(regs->sr, &gregs[17]);
+        err |= __put_user((regs->format << 12) | regs->vector, &uc->uc_formatvec);
+        err |= rt_save_fpu_state(uc, regs);
+        return err;
+}
+static inline void __user *
+get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, size_t frame_size)
+{
+        unsigned long usp;
+        /* Default to using normal stack.  */
+        usp = rdusp();
+        /* This is the X/Open sanctioned signal stack switching.  */
+        if (ka->sa.sa_flags & SA_ONSTACK) {
+                if (!sas_ss_flags(usp))
+                        usp = current->sas_ss_sp + current->sas_ss_size;
+        }
+        return (void __user *)((usp - frame_size) & -8UL);
+}
+static int setup_frame (int sig, struct k_sigaction *ka,
+                         sigset_t *set, struct pt_regs *regs)
+{
+        struct sigframe __user *frame;
+        int fsize = frame_extra_sizes(regs->format);
+        struct sigcontext context;
+        int err = 0;
+        if (fsize < 0) {
+#ifdef DEBUG
+                printk ("setup_frame: Unknown frame format %#x\n",
+                        regs->format);
+#endif
+                goto give_sigsegv;
+        }
+        frame = get_sigframe(ka, regs, sizeof(*frame) + fsize);
+        if (fsize)
+                err |= copy_to_user (frame + 1, regs + 1, fsize);
+        err |= __put_user((current_thread_info()->exec_domain
+                           && current_thread_info()->exec_domain->signal_invmap
+                           && sig < 32
+                           ? current_thread_info()->exec_domain->signal_invmap[sig]
+                           : sig),
+                          &frame->sig);
+        err |= __put_user(regs->vector, &frame->code);
+        err |= __put_user(&frame->sc, &frame->psc);
+        if (_NSIG_WORDS > 1)
+                err |= copy_to_user(frame->extramask, &set->sig[1],
+                                    sizeof(frame->extramask));
+        setup_sigcontext(&context, regs, set->sig[0]);
+        err |= copy_to_user (&frame->sc, &context, sizeof(context));
+        /* Set up to return from userspace.  */
+#ifdef CONFIG_MMU
+        err |= __put_user(frame->retcode, &frame->pretcode);
+        /* moveq #,d0; trap #0 */
+        err |= __put_user(0x70004e40 + (__NR_sigreturn << 16),
+                          (long __user *)(frame->retcode));
+#else
+        err |= __put_user((void *) ret_from_user_signal, &frame->pretcode);
+#endif
+        if (err)
+                goto give_sigsegv;
+        push_cache ((unsigned long) &frame->retcode);
+        /*
+         * Set up registers for signal handler.  All the state we are about
+         * to destroy is successfully copied to sigframe.
+         */
+        wrusp ((unsigned long) frame);
+        regs->pc = (unsigned long) ka->sa.sa_handler;
+        adjustformat(regs);
+        /*
+         * This is subtle; if we build more than one sigframe, all but the
+         * first one will see frame format 0 and have fsize == 0, so we won't
+         * screw stkadj.
+         */
+        if (fsize)
+                regs->stkadj = fsize;
+        /* Prepare to skip over the extra stuff in the exception frame.  */
+        if (regs->stkadj) {
+                struct pt_regs *tregs =
+                        (struct pt_regs *)((ulong)regs + regs->stkadj);
+#ifdef DEBUG
+                printk("Performing stackadjust=%04x\n", regs->stkadj);
+#endif
+                /* This must be copied with decreasing addresses to
+                   handle overlaps.  */
+                tregs->vector = 0;
+                tregs->format = 0;
+                tregs->pc = regs->pc;
+                tregs->sr = regs->sr;
+        }
+        return 0;
+give_sigsegv:
+        force_sigsegv(sig, current);
+        return err;
+}
+static int setup_rt_frame (int sig, struct k_sigaction *ka, siginfo_t *info,
+                            sigset_t *set, struct pt_regs *regs)
+{
+        struct rt_sigframe __user *frame;
+        int fsize = frame_extra_sizes(regs->format);
+        int err = 0;
+        if (fsize < 0) {
+#ifdef DEBUG
+                printk ("setup_frame: Unknown frame format %#x\n",
+                        regs->format);
+#endif
+                goto give_sigsegv;
+        }
+        frame = get_sigframe(ka, regs, sizeof(*frame));
+        if (fsize)
+                err |= copy_to_user (&frame->uc.uc_extra, regs + 1, fsize);
+        err |= __put_user((current_thread_info()->exec_domain
+                           && current_thread_info()->exec_domain->signal_invmap
+                           && sig < 32
+                           ? current_thread_info()->exec_domain->signal_invmap[sig]
+                           : sig),
+                          &frame->sig);
+        err |= __put_user(&frame->info, &frame->pinfo);
+        err |= __put_user(&frame->uc, &frame->puc);
+        err |= copy_siginfo_to_user(&frame->info, info);
+        /* Create the ucontext.  */
+        err |= __put_user(0, &frame->uc.uc_flags);
+        err |= __put_user(NULL, &frame->uc.uc_link);
+        err |= __put_user((void __user *)current->sas_ss_sp,
+                          &frame->uc.uc_stack.ss_sp);
+        err |= __put_user(sas_ss_flags(rdusp()),
+                          &frame->uc.uc_stack.ss_flags);
+        err |= __put_user(current->sas_ss_size, &frame->uc.uc_stack.ss_size);
+        err |= rt_setup_ucontext(&frame->uc, regs);
+        err |= copy_to_user (&frame->uc.uc_sigmask, set, sizeof(*set));
+        /* Set up to return from userspace.  */
+#ifdef CONFIG_MMU
+        err |= __put_user(frame->retcode, &frame->pretcode);
+#ifdef __mcoldfire__
+        /* movel #__NR_rt_sigreturn,d0; trap #0 */
+        err |= __put_user(0x203c0000, (long __user *)(frame->retcode + 0));
+        err |= __put_user(0x00004e40 + (__NR_rt_sigreturn << 16),
+                          (long __user *)(frame->retcode + 4));
+#else
+        /* moveq #,d0; notb d0; trap #0 */
+        err |= __put_user(0x70004600 + ((__NR_rt_sigreturn ^ 0xff) << 16),
+                          (long __user *)(frame->retcode + 0));
+        err |= __put_user(0x4e40, (short __user *)(frame->retcode + 4));
+#endif
+#else
+        err |= __put_user((void *) ret_from_user_rt_signal, &frame->pretcode);
+#endif /* CONFIG_MMU */
+        if (err)
+                goto give_sigsegv;
+        push_cache ((unsigned long) &frame->retcode);
+        /*
+         * Set up registers for signal handler.  All the state we are about
+         * to destroy is successfully copied to sigframe.
+         */
+        wrusp ((unsigned long) frame);
+        regs->pc = (unsigned long) ka->sa.sa_handler;
+        adjustformat(regs);
+        /*
+         * This is subtle; if we build more than one sigframe, all but the
+         * first one will see frame format 0 and have fsize == 0, so we won't
+         * screw stkadj.
+         */
+        if (fsize)
+                regs->stkadj = fsize;
+        /* Prepare to skip over the extra stuff in the exception frame.  */
+        if (regs->stkadj) {
+                struct pt_regs *tregs =
+                        (struct pt_regs *)((ulong)regs + regs->stkadj);
+#ifdef DEBUG
+                printk("Performing stackadjust=%04x\n", regs->stkadj);
+#endif
+                /* This must be copied with decreasing addresses to
+                   handle overlaps.  */
+                tregs->vector = 0;
+                tregs->format = 0;
+                tregs->pc = regs->pc;
+                tregs->sr = regs->sr;
+        }
+        return 0;
+give_sigsegv:
+        force_sigsegv(sig, current);
+        return err;
+}
+static inline void
+handle_restart(struct pt_regs *regs, struct k_sigaction *ka, int has_handler)
+{
+        switch (regs->d0) {
+        case -ERESTARTNOHAND:
+                if (!has_handler)
+                        goto do_restart;
+                regs->d0 = -EINTR;
+                break;
+        case -ERESTART_RESTARTBLOCK:
+                if (!has_handler) {
+                        regs->d0 = __NR_restart_syscall;
+                        regs->pc -= 2;
+                        break;
+                }
+                regs->d0 = -EINTR;
+                break;
+        case -ERESTARTSYS:
+                if (has_handler && !(ka->sa.sa_flags & SA_RESTART)) {
+                        regs->d0 = -EINTR;
+                        break;
+                }
+        /* fallthrough */
+        case -ERESTARTNOINTR:
+        do_restart:
+                regs->d0 = regs->orig_d0;
+                regs->pc -= 2;
+                break;
+        }
+}
+/*
+ * OK, we're invoking a handler
+ */
+static void
+handle_signal(int sig, struct k_sigaction *ka, siginfo_t *info,
+              sigset_t *oldset, struct pt_regs *regs)
+{
+        int err;
+        /* are we from a system call? */
+        if (regs->orig_d0 >= 0)
+                /* If so, check system call restarting.. */
+                handle_restart(regs, ka, 1);
+        /* set up the stack frame */
+        if (ka->sa.sa_flags & SA_SIGINFO)
+                err = setup_rt_frame(sig, ka, info, oldset, regs);
+        else
+                err = setup_frame(sig, ka, oldset, regs);
+        if (err)
+                return;
+        sigorsets(&current->blocked,&current->blocked,&ka->sa.sa_mask);
+        if (!(ka->sa.sa_flags & SA_NODEFER))
+                sigaddset(&current->blocked,sig);
+        recalc_sigpending();
+        if (test_thread_flag(TIF_DELAYED_TRACE)) {
+                regs->sr &= ~0x8000;
+                send_sig(SIGTRAP, current, 1);
+        }
+        clear_thread_flag(TIF_RESTORE_SIGMASK);
+}
+/*
+ * Note that 'init' is a special process: it doesn't get signals it doesn't
+ * want to handle. Thus you cannot kill init even with a SIGKILL even by
+ * mistake.
+ */
+asmlinkage void do_signal(struct pt_regs *regs)
+{
+        siginfo_t info;
+        struct k_sigaction ka;
+        int signr;
+        sigset_t *oldset;
+        current->thread.esp0 = (unsigned long) regs;
+        if (test_thread_flag(TIF_RESTORE_SIGMASK))
+                oldset = &current->saved_sigmask;
+        else
+                oldset = &current->blocked;
+        signr = get_signal_to_deliver(&info, &ka, regs, NULL);
+        if (signr > 0) {
+                /* Whee!  Actually deliver the signal.  */
+                handle_signal(signr, &ka, &info, oldset, regs);
+                return;
+        }
+        /* Did we come from a system call? */
+        if (regs->orig_d0 >= 0)
+                /* Restart the system call - no handlers present */
+                handle_restart(regs, NULL, 0);
+        /* If there's no signal to deliver, we just restore the saved mask.  */
+        if (test_thread_flag(TIF_RESTORE_SIGMASK)) {
+                clear_thread_flag(TIF_RESTORE_SIGMASK);
+                sigprocmask(SIG_SETMASK, &current->saved_sigmask, NULL);
+        }
+}
diff --git a/arch/m68k/kernel/signal_mm.c b/arch/m68k/kernel/signal_mm.c
deleted file mode 100644
index cb856f9da655..000000000000
--- a/arch/m68k/kernel/signal_mm.c
+++ /dev/null
@@ -1,1115 +0,0 @@
-/*
- *  linux/arch/m68k/kernel/signal.c
- *
- *  Copyright (C) 1991, 1992  Linus Torvalds
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file COPYING in the main directory of this archive
- * for more details.
- */
-/*
- * Linux/m68k support by Hamish Macdonald
- *
- * 68060 fixes by Jesper Skov
- *
- * 1997-12-01  Modified for POSIX.1b signals by Andreas Schwab
- *
- * mathemu support by Roman Zippel
- *  (Note: fpstate in the signal context is completely ignored for the emulator
- *         and the internal floating point format is put on stack)
- */
-/*
- * ++roman (07/09/96): implemented signal stacks (specially for tosemu on
- * Atari :-) Current limitation: Only one sigstack can be active at one time.
- * If a second signal with SA_ONSTACK set arrives while working on a sigstack,
- * SA_ONSTACK is ignored. This behaviour avoids lots of trouble with nested
- * signal handlers!
- */
-#include <linux/sched.h>
-#include <linux/mm.h>
-#include <linux/kernel.h>
-#include <linux/signal.h>
-#include <linux/syscalls.h>
-#include <linux/errno.h>
-#include <linux/wait.h>
-#include <linux/ptrace.h>
-#include <linux/unistd.h>
-#include <linux/stddef.h>
-#include <linux/highuid.h>
-#include <linux/personality.h>
-#include <linux/tty.h>
-#include <linux/binfmts.h>
-#include <linux/module.h>
-#include <asm/setup.h>
-#include <asm/uaccess.h>
-#include <asm/pgtable.h>
-#include <asm/traps.h>
-#include <asm/ucontext.h>
-#define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP)))
-static const int frame_extra_sizes[16] = {
-  [1]   = -1, /* sizeof(((struct frame *)0)->un.fmt1), */
-  [2]   = sizeof(((struct frame *)0)->un.fmt2),
-  [3]   = sizeof(((struct frame *)0)->un.fmt3),
-#ifdef CONFIG_COLDFIRE
-  [4]   = 0,
-#else
-  [4]   = sizeof(((struct frame *)0)->un.fmt4),
-#endif
-  [5]   = -1, /* sizeof(((struct frame *)0)->un.fmt5), */
-  [6]   = -1, /* sizeof(((struct frame *)0)->un.fmt6), */
-  [7]   = sizeof(((struct frame *)0)->un.fmt7),
-  [8]   = -1, /* sizeof(((struct frame *)0)->un.fmt8), */
-  [9]   = sizeof(((struct frame *)0)->un.fmt9),
-  [10]  = sizeof(((struct frame *)0)->un.fmta),
-  [11]  = sizeof(((struct frame *)0)->un.fmtb),
-  [12]  = -1, /* sizeof(((struct frame *)0)->un.fmtc), */
-  [13]  = -1, /* sizeof(((struct frame *)0)->un.fmtd), */
-  [14]  = -1, /* sizeof(((struct frame *)0)->un.fmte), */
-  [15]  = -1, /* sizeof(((struct frame *)0)->un.fmtf), */
-};
-int handle_kernel_fault(struct pt_regs *regs)
-{
-        const struct exception_table_entry *fixup;
-        struct pt_regs *tregs;
-        /* Are we prepared to handle this kernel fault? */
-        fixup = search_exception_tables(regs->pc);
-        if (!fixup)
-                return 0;
-        /* Create a new four word stack frame, discarding the old one. */
-        regs->stkadj = frame_extra_sizes[regs->format];
-        tregs = (struct pt_regs *)((long)regs + regs->stkadj);
-        tregs->vector = regs->vector;
-#ifdef CONFIG_COLDFIRE
-        tregs->format = 4;
-#else
-        tregs->format = 0;
-#endif
-        tregs->pc = fixup->fixup;
-        tregs->sr = regs->sr;
-        return 1;
-}
-/*
- * Atomically swap in the new signal mask, and wait for a signal.
- */
-asmlinkage int
-sys_sigsuspend(int unused0, int unused1, old_sigset_t mask)
-{
-        mask &= _BLOCKABLE;
-        spin_lock_irq(&current->sighand->siglock);
-        current->saved_sigmask = current->blocked;
-        siginitset(&current->blocked, mask);
-        recalc_sigpending();
-        spin_unlock_irq(&current->sighand->siglock);
-        current->state = TASK_INTERRUPTIBLE;
-        schedule();
-        set_restore_sigmask();
-        return -ERESTARTNOHAND;
-}
-asmlinkage int
-sys_sigaction(int sig, const struct old_sigaction __user *act,
-              struct old_sigaction __user *oact)
-{
-        struct k_sigaction new_ka, old_ka;
-        int ret;
-        if (act) {
-                old_sigset_t mask;
-                if (!access_ok(VERIFY_READ, act, sizeof(*act)) ||
-                    __get_user(new_ka.sa.sa_handler, &act->sa_handler) ||
-                    __get_user(new_ka.sa.sa_restorer, &act->sa_restorer) ||
-                    __get_user(new_ka.sa.sa_flags, &act->sa_flags) ||
-                    __get_user(mask, &act->sa_mask))
-                        return -EFAULT;
-                siginitset(&new_ka.sa.sa_mask, mask);
-        }
-        ret = do_sigaction(sig, act ? &new_ka : NULL, oact ? &old_ka : NULL);
-        if (!ret && oact) {
-                if (!access_ok(VERIFY_WRITE, oact, sizeof(*oact)) ||
-                    __put_user(old_ka.sa.sa_handler, &oact->sa_handler) ||
-                    __put_user(old_ka.sa.sa_restorer, &oact->sa_restorer) ||
-                    __put_user(old_ka.sa.sa_flags, &oact->sa_flags) ||
-                    __put_user(old_ka.sa.sa_mask.sig[0], &oact->sa_mask))
-                        return -EFAULT;
-        }
-        return ret;
-}
-asmlinkage int
-sys_sigaltstack(const stack_t __user *uss, stack_t __user *uoss)
-{
-        return do_sigaltstack(uss, uoss, rdusp());
-}
-/*
- * Do a signal return; undo the signal stack.
- *
- * Keep the return code on the stack quadword aligned!
- * That makes the cache flush below easier.
- */
-struct sigframe
-{
-        char __user *pretcode;
-        int sig;
-        int code;
-        struct sigcontext __user *psc;
-        char retcode[8];
-        unsigned long extramask[_NSIG_WORDS-1];
-        struct sigcontext sc;
-};
-struct rt_sigframe
-{
-        char __user *pretcode;
-        int sig;
-        struct siginfo __user *pinfo;
-        void __user *puc;
-        char retcode[8];
-        struct siginfo info;
-        struct ucontext uc;
-};
-static unsigned char fpu_version;       /* version number of fpu, set by setup_frame */
-static inline int restore_fpu_state(struct sigcontext *sc)
-{
-        int err = 1;
-        if (FPU_IS_EMU) {
-            /* restore registers */
-            memcpy(current->thread.fpcntl, sc->sc_fpcntl, 12);
-            memcpy(current->thread.fp, sc->sc_fpregs, 24);
-            return 0;
-        }
-        if (CPU_IS_060 ? sc->sc_fpstate[2] : sc->sc_fpstate[0]) {
-            /* Verify the frame format.  */
-            if (!(CPU_IS_060 || CPU_IS_COLDFIRE) &&
-                 (sc->sc_fpstate[0] != fpu_version))
-                goto out;
-            if (CPU_IS_020_OR_030) {
-                if (m68k_fputype & FPU_68881 &&
-                    !(sc->sc_fpstate[1] == 0x18 || sc->sc_fpstate[1] == 0xb4))
-                    goto out;
-                if (m68k_fputype & FPU_68882 &&
-                    !(sc->sc_fpstate[1] == 0x38 || sc->sc_fpstate[1] == 0xd4))
-                    goto out;
-            } else if (CPU_IS_040) {
-                if (!(sc->sc_fpstate[1] == 0x00 ||
-                      sc->sc_fpstate[1] == 0x28 ||
-                      sc->sc_fpstate[1] == 0x60))
-                    goto out;
-            } else if (CPU_IS_060) {
-                if (!(sc->sc_fpstate[3] == 0x00 ||
-                      sc->sc_fpstate[3] == 0x60 ||
-                      sc->sc_fpstate[3] == 0xe0))
-                    goto out;
-            } else if (CPU_IS_COLDFIRE) {
-                if (!(sc->sc_fpstate[0] == 0x00 ||
-                      sc->sc_fpstate[0] == 0x05 ||
-                      sc->sc_fpstate[0] == 0xe5))
-                    goto out;
-            } else
-                goto out;
-            if (CPU_IS_COLDFIRE) {
-                __asm__ volatile ("fmovemd %0,%%fp0-%%fp1\n\t"
-                                  "fmovel %1,%%fpcr\n\t"
-                                  "fmovel %2,%%fpsr\n\t"
-                                  "fmovel %3,%%fpiar"
-                                  : /* no outputs */
-                                  : "m" (sc->sc_fpregs[0]),
-                                    "m" (sc->sc_fpcntl[0]),
-                                    "m" (sc->sc_fpcntl[1]),
-                                    "m" (sc->sc_fpcntl[2]));
-            } else {
-                __asm__ volatile (".chip 68k/68881\n\t"
-                                  "fmovemx %0,%%fp0-%%fp1\n\t"
-                                  "fmoveml %1,%%fpcr/%%fpsr/%%fpiar\n\t"
-                                  ".chip 68k"
-                                  : /* no outputs */
-                                  : "m" (*sc->sc_fpregs),
-                                    "m" (*sc->sc_fpcntl));
-            }
-        }
-        if (CPU_IS_COLDFIRE) {
-                __asm__ volatile ("frestore %0" : : "m" (*sc->sc_fpstate));
-        } else {
-                __asm__ volatile (".chip 68k/68881\n\t"
-                                  "frestore %0\n\t"
-                                  ".chip 68k"
-                                  : : "m" (*sc->sc_fpstate));
-        }
-        err = 0;
-out:
-        return err;
-}
-#define FPCONTEXT_SIZE  216
-#define uc_fpstate      uc_filler[0]
-#define uc_formatvec    uc_filler[FPCONTEXT_SIZE/4]
-#define uc_extra        uc_filler[FPCONTEXT_SIZE/4+1]
-static inline int rt_restore_fpu_state(struct ucontext __user *uc)
-{
-        unsigned char fpstate[FPCONTEXT_SIZE];
-        int context_size = CPU_IS_060 ? 8 : (CPU_IS_COLDFIRE ? 12 : 0);
-        fpregset_t fpregs;
-        int err = 1;
-        if (FPU_IS_EMU) {
-                /* restore fpu control register */
-                if (__copy_from_user(current->thread.fpcntl,
-                                uc->uc_mcontext.fpregs.f_fpcntl, 12))
-                        goto out;
-                /* restore all other fpu register */
-                if (__copy_from_user(current->thread.fp,
-                                uc->uc_mcontext.fpregs.f_fpregs, 96))
-                        goto out;
-                return 0;
-        }
-        if (__get_user(*(long *)fpstate, (long __user *)&uc->uc_fpstate))
-                goto out;
-        if (CPU_IS_060 ? fpstate[2] : fpstate[0]) {
-                if (!(CPU_IS_060 || CPU_IS_COLDFIRE))
-                        context_size = fpstate[1];
-                /* Verify the frame format.  */
-                if (!(CPU_IS_060 || CPU_IS_COLDFIRE) &&
-                     (fpstate[0] != fpu_version))
-                        goto out;
-                if (CPU_IS_020_OR_030) {
-                        if (m68k_fputype & FPU_68881 &&
-                            !(context_size == 0x18 || context_size == 0xb4))
-                                goto out;
-                        if (m68k_fputype & FPU_68882 &&
-                            !(context_size == 0x38 || context_size == 0xd4))
-                                goto out;
-                } else if (CPU_IS_040) {
-                        if (!(context_size == 0x00 ||
-                              context_size == 0x28 ||
-                              context_size == 0x60))
-                                goto out;
-                } else if (CPU_IS_060) {
-                        if (!(fpstate[3] == 0x00 ||
-                              fpstate[3] == 0x60 ||
-                              fpstate[3] == 0xe0))
-                                goto out;
-                } else if (CPU_IS_COLDFIRE) {
-                        if (!(fpstate[3] == 0x00 ||
-                              fpstate[3] == 0x05 ||
-                              fpstate[3] == 0xe5))
-                                goto out;
-                } else
-                        goto out;
-                if (__copy_from_user(&fpregs, &uc->uc_mcontext.fpregs,
-                                     sizeof(fpregs)))
-                        goto out;
-                if (CPU_IS_COLDFIRE) {
-                        __asm__ volatile ("fmovemd %0,%%fp0-%%fp7\n\t"
-                                          "fmovel %1,%%fpcr\n\t"
-                                          "fmovel %2,%%fpsr\n\t"
-                                          "fmovel %3,%%fpiar"
-                                          : /* no outputs */
-                                          : "m" (fpregs.f_fpregs[0]),
-                                            "m" (fpregs.f_fpcntl[0]),
-                                            "m" (fpregs.f_fpcntl[1]),
-                                            "m" (fpregs.f_fpcntl[2]));
-                } else {
-                        __asm__ volatile (".chip 68k/68881\n\t"
-                                          "fmovemx %0,%%fp0-%%fp7\n\t"
-                                          "fmoveml %1,%%fpcr/%%fpsr/%%fpiar\n\t"
-                                          ".chip 68k"
-                                          : /* no outputs */
-                                          : "m" (*fpregs.f_fpregs),
-                                            "m" (*fpregs.f_fpcntl));
-                }
-        }
-        if (context_size &&
-            __copy_from_user(fpstate + 4, (long __user *)&uc->uc_fpstate + 1,
-                             context_size))
-                goto out;
-        if (CPU_IS_COLDFIRE) {
-                __asm__ volatile ("frestore %0" : : "m" (*fpstate));
-        } else {
-                __asm__ volatile (".chip 68k/68881\n\t"
-                                  "frestore %0\n\t"
-                                  ".chip 68k"
-                                  : : "m" (*fpstate));
-        }
-        err = 0;
-out:
-        return err;
-}
-static int mangle_kernel_stack(struct pt_regs *regs, int formatvec,
-                               void __user *fp)
-{
-        int fsize = frame_extra_sizes[formatvec >> 12];
-        if (fsize < 0) {
-                /*
-                 * user process trying to return with weird frame format
-                 */
-#ifdef DEBUG
-                printk("user process returning with weird frame format\n");
-#endif
-                return 1;
-        }
-        if (!fsize) {
-                regs->format = formatvec >> 12;
-                regs->vector = formatvec & 0xfff;
-        } else {
-                struct switch_stack *sw = (struct switch_stack *)regs - 1;
-                unsigned long buf[fsize / 2]; /* yes, twice as much */
-                /* that'll make sure that expansion won't crap over data */
-                if (copy_from_user(buf + fsize / 4, fp, fsize))
-                        return 1;
-                /* point of no return */
-                regs->format = formatvec >> 12;
-                regs->vector = formatvec & 0xfff;
-#define frame_offset (sizeof(struct pt_regs)+sizeof(struct switch_stack))
-                __asm__ __volatile__ (
-#ifdef CONFIG_COLDFIRE
-                         "   movel %0,%/sp\n\t"
-                         "   bra ret_from_signal\n"
-#else
-                         "   movel %0,%/a0\n\t"
-                         "   subl %1,%/a0\n\t"     /* make room on stack */
-                         "   movel %/a0,%/sp\n\t"  /* set stack pointer */
-                         /* move switch_stack and pt_regs */
-                         "1: movel %0@+,%/a0@+\n\t"
-                         "   dbra %2,1b\n\t"
-                         "   lea %/sp@(%c3),%/a0\n\t" /* add offset of fmt */
-                         "   lsrl  #2,%1\n\t"
-                         "   subql #1,%1\n\t"
-                         /* copy to the gap we'd made */
-                         "2: movel %4@+,%/a0@+\n\t"
-                         "   dbra %1,2b\n\t"
-                         "   bral ret_from_signal\n"
-#endif
-                         : /* no outputs, it doesn't ever return */
-                         : "a" (sw), "d" (fsize), "d" (frame_offset/4-1),
-                           "n" (frame_offset), "a" (buf + fsize/4)
-                         : "a0");
-#undef frame_offset
-        }
-        return 0;
-}
-static inline int
-restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *usc, void __user *fp)
-{
-        int formatvec;
-        struct sigcontext context;
-        int err;
-        /* Always make any pending restarted system calls return -EINTR */
-        current_thread_info()->restart_block.fn = do_no_restart_syscall;
-        /* get previous context */
-        if (copy_from_user(&context, usc, sizeof(context)))
-                goto badframe;
-        /* restore passed registers */
-        regs->d0 = context.sc_d0;
-        regs->d1 = context.sc_d1;
-        regs->a0 = context.sc_a0;
-        regs->a1 = context.sc_a1;
-        regs->sr = (regs->sr & 0xff00) | (context.sc_sr & 0xff);
-        regs->pc = context.sc_pc;
-        regs->orig_d0 = -1;             /* disable syscall checks */
-        wrusp(context.sc_usp);
-        formatvec = context.sc_formatvec;
-        err = restore_fpu_state(&context);
-        if (err || mangle_kernel_stack(regs, formatvec, fp))
-                goto badframe;
-        return 0;
-badframe:
-        return 1;
-}
-static inline int
-rt_restore_ucontext(struct pt_regs *regs, struct switch_stack *sw,
-                    struct ucontext __user *uc)
-{
-        int temp;
-        greg_t __user *gregs = uc->uc_mcontext.gregs;
-        unsigned long usp;
-        int err;
-        /* Always make any pending restarted system calls return -EINTR */
-        current_thread_info()->restart_block.fn = do_no_restart_syscall;
-        err = __get_user(temp, &uc->uc_mcontext.version);
-        if (temp != MCONTEXT_VERSION)
-                goto badframe;
-        /* restore passed registers */
-        err |= __get_user(regs->d0, &gregs[0]);
-        err |= __get_user(regs->d1, &gregs[1]);
-        err |= __get_user(regs->d2, &gregs[2]);
-        err |= __get_user(regs->d3, &gregs[3]);
-        err |= __get_user(regs->d4, &gregs[4]);
-        err |= __get_user(regs->d5, &gregs[5]);
-        err |= __get_user(sw->d6, &gregs[6]);
-        err |= __get_user(sw->d7, &gregs[7]);
-        err |= __get_user(regs->a0, &gregs[8]);
-        err |= __get_user(regs->a1, &gregs[9]);
-        err |= __get_user(regs->a2, &gregs[10]);
-        err |= __get_user(sw->a3, &gregs[11]);
-        err |= __get_user(sw->a4, &gregs[12]);
-        err |= __get_user(sw->a5, &gregs[13]);
-        err |= __get_user(sw->a6, &gregs[14]);
-        err |= __get_user(usp, &gregs[15]);
-        wrusp(usp);
-        err |= __get_user(regs->pc, &gregs[16]);
-        err |= __get_user(temp, &gregs[17]);
-        regs->sr = (regs->sr & 0xff00) | (temp & 0xff);
-        regs->orig_d0 = -1;             /* disable syscall checks */
-        err |= __get_user(temp, &uc->uc_formatvec);
-        err |= rt_restore_fpu_state(uc);
-        if (err || do_sigaltstack(&uc->uc_stack, NULL, usp) == -EFAULT)
-                goto badframe;
-        if (mangle_kernel_stack(regs, temp, &uc->uc_extra))
-                goto badframe;
-        return 0;
-badframe:
-        return 1;
-}
-asmlinkage int do_sigreturn(unsigned long __unused)
-{
-        struct switch_stack *sw = (struct switch_stack *) &__unused;
-        struct pt_regs *regs = (struct pt_regs *) (sw + 1);
-        unsigned long usp = rdusp();
-        struct sigframe __user *frame = (struct sigframe __user *)(usp - 4);
-        sigset_t set;
-        if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
-                goto badframe;
-        if (__get_user(set.sig[0], &frame->sc.sc_mask) ||
-            (_NSIG_WORDS > 1 &&
-             __copy_from_user(&set.sig[1], &frame->extramask,
-                              sizeof(frame->extramask))))
-                goto badframe;
-        sigdelsetmask(&set, ~_BLOCKABLE);
-        current->blocked = set;
-        recalc_sigpending();
-        if (restore_sigcontext(regs, &frame->sc, frame + 1))
-                goto badframe;
-        return regs->d0;
-badframe:
-        force_sig(SIGSEGV, current);
-        return 0;
-}
-asmlinkage int do_rt_sigreturn(unsigned long __unused)
-{
-        struct switch_stack *sw = (struct switch_stack *) &__unused;
-        struct pt_regs *regs = (struct pt_regs *) (sw + 1);
-        unsigned long usp = rdusp();
-        struct rt_sigframe __user *frame = (struct rt_sigframe __user *)(usp - 4);
-        sigset_t set;
-        if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
-                goto badframe;
-        if (__copy_from_user(&set, &frame->uc.uc_sigmask, sizeof(set)))
-                goto badframe;
-        sigdelsetmask(&set, ~_BLOCKABLE);
-        current->blocked = set;
-        recalc_sigpending();
-        if (rt_restore_ucontext(regs, sw, &frame->uc))
-                goto badframe;
-        return regs->d0;
-badframe:
-        force_sig(SIGSEGV, current);
-        return 0;
-}
-/*
- * Set up a signal frame.
- */
-static inline void save_fpu_state(struct sigcontext *sc, struct pt_regs *regs)
-{
-        if (FPU_IS_EMU) {
-                /* save registers */
-                memcpy(sc->sc_fpcntl, current->thread.fpcntl, 12);
-                memcpy(sc->sc_fpregs, current->thread.fp, 24);
-                return;
-        }
-        if (CPU_IS_COLDFIRE) {
-                __asm__ volatile ("fsave %0"
-                                  : : "m" (*sc->sc_fpstate) : "memory");
-        } else {
-                __asm__ volatile (".chip 68k/68881\n\t"
-                                  "fsave %0\n\t"
-                                  ".chip 68k"
-                                  : : "m" (*sc->sc_fpstate) : "memory");
-        }
-        if (CPU_IS_060 ? sc->sc_fpstate[2] : sc->sc_fpstate[0]) {
-                fpu_version = sc->sc_fpstate[0];
-                if (CPU_IS_020_OR_030 &&
-                    regs->vector >= (VEC_FPBRUC * 4) &&
-                    regs->vector <= (VEC_FPNAN * 4)) {
-                        /* Clear pending exception in 68882 idle frame */
-                        if (*(unsigned short *) sc->sc_fpstate == 0x1f38)
-                                sc->sc_fpstate[0x38] |= 1 << 3;
-                }
-                if (CPU_IS_COLDFIRE) {
-                        __asm__ volatile ("fmovemd %%fp0-%%fp1,%0\n\t"
-                                          "fmovel %%fpcr,%1\n\t"
-                                          "fmovel %%fpsr,%2\n\t"
-                                          "fmovel %%fpiar,%3"
-                                          : "=m" (sc->sc_fpregs[0]),
-                                            "=m" (sc->sc_fpcntl[0]),
-                                            "=m" (sc->sc_fpcntl[1]),
-                                            "=m" (sc->sc_fpcntl[2])
-                                          : /* no inputs */
-                                          : "memory");
-                } else {
-                        __asm__ volatile (".chip 68k/68881\n\t"
-                                          "fmovemx %%fp0-%%fp1,%0\n\t"
-                                          "fmoveml %%fpcr/%%fpsr/%%fpiar,%1\n\t"
-                                          ".chip 68k"
-                                          : "=m" (*sc->sc_fpregs),
-                                            "=m" (*sc->sc_fpcntl)
-                                          : /* no inputs */
-                                          : "memory");
-                }
-        }
-}
-static inline int rt_save_fpu_state(struct ucontext __user *uc, struct pt_regs *regs)
-{
-        unsigned char fpstate[FPCONTEXT_SIZE];
-        int context_size = CPU_IS_060 ? 8 : (CPU_IS_COLDFIRE ? 12 : 0);
-        int err = 0;
-        if (FPU_IS_EMU) {
-                /* save fpu control register */
-                err |= copy_to_user(uc->uc_mcontext.fpregs.f_fpcntl,
-                                current->thread.fpcntl, 12);
-                /* save all other fpu register */
-                err |= copy_to_user(uc->uc_mcontext.fpregs.f_fpregs,
-                                current->thread.fp, 96);
-                return err;
-        }
-        if (CPU_IS_COLDFIRE) {
-                __asm__ volatile ("fsave %0" : : "m" (*fpstate) : "memory");
-        } else {
-                __asm__ volatile (".chip 68k/68881\n\t"
-                                  "fsave %0\n\t"
-                                  ".chip 68k"
-                                  : : "m" (*fpstate) : "memory");
-        }
-        err |= __put_user(*(long *)fpstate, (long __user *)&uc->uc_fpstate);
-        if (CPU_IS_060 ? fpstate[2] : fpstate[0]) {
-                fpregset_t fpregs;
-                if (!(CPU_IS_060 || CPU_IS_COLDFIRE))
-                        context_size = fpstate[1];
-                fpu_version = fpstate[0];
-                if (CPU_IS_020_OR_030 &&
-                    regs->vector >= (VEC_FPBRUC * 4) &&
-                    regs->vector <= (VEC_FPNAN * 4)) {
-                        /* Clear pending exception in 68882 idle frame */
-                        if (*(unsigned short *) fpstate == 0x1f38)
-                                fpstate[0x38] |= 1 << 3;
-                }
-                if (CPU_IS_COLDFIRE) {
-                        __asm__ volatile ("fmovemd %%fp0-%%fp7,%0\n\t"
-                                          "fmovel %%fpcr,%1\n\t"
-                                          "fmovel %%fpsr,%2\n\t"
-                                          "fmovel %%fpiar,%3"
-                                          : "=m" (fpregs.f_fpregs[0]),
-                                            "=m" (fpregs.f_fpcntl[0]),
-                                            "=m" (fpregs.f_fpcntl[1]),
-                                            "=m" (fpregs.f_fpcntl[2])
-                                          : /* no inputs */
-                                          : "memory");
-                } else {
-                        __asm__ volatile (".chip 68k/68881\n\t"
-                                          "fmovemx %%fp0-%%fp7,%0\n\t"
-                                          "fmoveml %%fpcr/%%fpsr/%%fpiar,%1\n\t"
-                                          ".chip 68k"
-                                          : "=m" (*fpregs.f_fpregs),
-                                            "=m" (*fpregs.f_fpcntl)
-                                          : /* no inputs */
-                                          : "memory");
-                }
-                err |= copy_to_user(&uc->uc_mcontext.fpregs, &fpregs,
-                                    sizeof(fpregs));
-        }
-        if (context_size)
-                err |= copy_to_user((long __user *)&uc->uc_fpstate + 1, fpstate + 4,
-                                    context_size);
-        return err;
-}
-static void setup_sigcontext(struct sigcontext *sc, struct pt_regs *regs,
-                             unsigned long mask)
-{
-        sc->sc_mask = mask;
-        sc->sc_usp = rdusp();
-        sc->sc_d0 = regs->d0;
-        sc->sc_d1 = regs->d1;
-        sc->sc_a0 = regs->a0;
-        sc->sc_a1 = regs->a1;
-        sc->sc_sr = regs->sr;
-        sc->sc_pc = regs->pc;
-        sc->sc_formatvec = regs->format << 12 | regs->vector;
-        save_fpu_state(sc, regs);
-}
-static inline int rt_setup_ucontext(struct ucontext __user *uc, struct pt_regs *regs)
-{
-        struct switch_stack *sw = (struct switch_stack *)regs - 1;
-        greg_t __user *gregs = uc->uc_mcontext.gregs;
-        int err = 0;
-        err |= __put_user(MCONTEXT_VERSION, &uc->uc_mcontext.version);
-        err |= __put_user(regs->d0, &gregs[0]);
-        err |= __put_user(regs->d1, &gregs[1]);
-        err |= __put_user(regs->d2, &gregs[2]);
-        err |= __put_user(regs->d3, &gregs[3]);
-        err |= __put_user(regs->d4, &gregs[4]);
-        err |= __put_user(regs->d5, &gregs[5]);
-        err |= __put_user(sw->d6, &gregs[6]);
-        err |= __put_user(sw->d7, &gregs[7]);
-        err |= __put_user(regs->a0, &gregs[8]);
-        err |= __put_user(regs->a1, &gregs[9]);
-        err |= __put_user(regs->a2, &gregs[10]);
-        err |= __put_user(sw->a3, &gregs[11]);
-        err |= __put_user(sw->a4, &gregs[12]);
-        err |= __put_user(sw->a5, &gregs[13]);
-        err |= __put_user(sw->a6, &gregs[14]);
-        err |= __put_user(rdusp(), &gregs[15]);
-        err |= __put_user(regs->pc, &gregs[16]);
-        err |= __put_user(regs->sr, &gregs[17]);
-        err |= __put_user((regs->format << 12) | regs->vector, &uc->uc_formatvec);
-        err |= rt_save_fpu_state(uc, regs);
-        return err;
-}
-static inline void push_cache (unsigned long vaddr)
-{
-        /*
-         * Using the old cache_push_v() was really a big waste.
-         *
-         * What we are trying to do is to flush 8 bytes to ram.
-         * Flushing 2 cache lines of 16 bytes is much cheaper than
-         * flushing 1 or 2 pages, as previously done in
-         * cache_push_v().
-         *                                                     Jes
-         */
-        if (CPU_IS_040) {
-                unsigned long temp;
-                __asm__ __volatile__ (".chip 68040\n\t"
-                                      "nop\n\t"
-                                      "ptestr (%1)\n\t"
-                                      "movec %%mmusr,%0\n\t"
-                                      ".chip 68k"
-                                      : "=r" (temp)
-                                      : "a" (vaddr));
-                temp &= PAGE_MASK;
-                temp |= vaddr & ~PAGE_MASK;
-                __asm__ __volatile__ (".chip 68040\n\t"
-                                      "nop\n\t"
-                                      "cpushl %%bc,(%0)\n\t"
-                                      ".chip 68k"
-                                      : : "a" (temp));
-        }
-        else if (CPU_IS_060) {
-                unsigned long temp;
-                __asm__ __volatile__ (".chip 68060\n\t"
-                                      "plpar (%0)\n\t"
-                                      ".chip 68k"
-                                      : "=a" (temp)
-                                      : "0" (vaddr));
-                __asm__ __volatile__ (".chip 68060\n\t"
-                                      "cpushl %%bc,(%0)\n\t"
-                                      ".chip 68k"
-                                      : : "a" (temp));
-        } else if (!CPU_IS_COLDFIRE) {
-                /*
-                 * 68030/68020 have no writeback cache;
-                 * still need to clear icache.
-                 * Note that vaddr is guaranteed to be long word aligned.
-                 */
-                unsigned long temp;
-                asm volatile ("movec %%cacr,%0" : "=r" (temp));
-                temp += 4;
-                asm volatile ("movec %0,%%caar\n\t"
-                              "movec %1,%%cacr"
-                              : : "r" (vaddr), "r" (temp));
-                asm volatile ("movec %0,%%caar\n\t"
-                              "movec %1,%%cacr"
-                              : : "r" (vaddr + 4), "r" (temp));
-        }
-}
-static inline void __user *
-get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, size_t frame_size)
-{
-        unsigned long usp;
-        /* Default to using normal stack.  */
-        usp = rdusp();
-        /* This is the X/Open sanctioned signal stack switching.  */
-        if (ka->sa.sa_flags & SA_ONSTACK) {
-                if (!sas_ss_flags(usp))
-                        usp = current->sas_ss_sp + current->sas_ss_size;
-        }
-        return (void __user *)((usp - frame_size) & -8UL);
-}
-static int setup_frame (int sig, struct k_sigaction *ka,
-                         sigset_t *set, struct pt_regs *regs)
-{
-        struct sigframe __user *frame;
-        int fsize = frame_extra_sizes[regs->format];
-        struct sigcontext context;
-        int err = 0;
-        if (fsize < 0) {
-#ifdef DEBUG
-                printk ("setup_frame: Unknown frame format %#x\n",
-                        regs->format);
-#endif
-                goto give_sigsegv;
-        }
-        frame = get_sigframe(ka, regs, sizeof(*frame) + fsize);
-        if (fsize)
-                err |= copy_to_user (frame + 1, regs + 1, fsize);
-        err |= __put_user((current_thread_info()->exec_domain
-                           && current_thread_info()->exec_domain->signal_invmap
-                           && sig < 32
-                           ? current_thread_info()->exec_domain->signal_invmap[sig]
-                           : sig),
-                          &frame->sig);
-        err |= __put_user(regs->vector, &frame->code);
-        err |= __put_user(&frame->sc, &frame->psc);
-        if (_NSIG_WORDS > 1)
-                err |= copy_to_user(frame->extramask, &set->sig[1],
-                                    sizeof(frame->extramask));
-        setup_sigcontext(&context, regs, set->sig[0]);
-        err |= copy_to_user (&frame->sc, &context, sizeof(context));
-        /* Set up to return from userspace.  */
-        err |= __put_user(frame->retcode, &frame->pretcode);
-        /* moveq #,d0; trap #0 */
-        err |= __put_user(0x70004e40 + (__NR_sigreturn << 16),
-                          (long __user *)(frame->retcode));
-        if (err)
-                goto give_sigsegv;
-        push_cache ((unsigned long) &frame->retcode);
-        /*
-         * Set up registers for signal handler.  All the state we are about
-         * to destroy is successfully copied to sigframe.
-         */
-        wrusp ((unsigned long) frame);
-        regs->pc = (unsigned long) ka->sa.sa_handler;
-        /*
-         * This is subtle; if we build more than one sigframe, all but the
-         * first one will see frame format 0 and have fsize == 0, so we won't
-         * screw stkadj.
-         */
-        if (fsize)
-                regs->stkadj = fsize;
-        /* Prepare to skip over the extra stuff in the exception frame.  */
-        if (regs->stkadj) {
-                struct pt_regs *tregs =
-                        (struct pt_regs *)((ulong)regs + regs->stkadj);
-#ifdef DEBUG
-                printk("Performing stackadjust=%04x\n", regs->stkadj);
-#endif
-                /* This must be copied with decreasing addresses to
-                   handle overlaps.  */
-                tregs->vector = 0;
-                tregs->format = 0;
-                tregs->pc = regs->pc;
-                tregs->sr = regs->sr;
-        }
-        return 0;
-give_sigsegv:
-        force_sigsegv(sig, current);
-        return err;
-}
-static int setup_rt_frame (int sig, struct k_sigaction *ka, siginfo_t *info,
-                            sigset_t *set, struct pt_regs *regs)
-{
-        struct rt_sigframe __user *frame;
-        int fsize = frame_extra_sizes[regs->format];
-        int err = 0;
-        if (fsize < 0) {
-#ifdef DEBUG
-                printk ("setup_frame: Unknown frame format %#x\n",
-                        regs->format);
-#endif
-                goto give_sigsegv;
-        }
-        frame = get_sigframe(ka, regs, sizeof(*frame));
-        if (fsize)
-                err |= copy_to_user (&frame->uc.uc_extra, regs + 1, fsize);
-        err |= __put_user((current_thread_info()->exec_domain
-                           && current_thread_info()->exec_domain->signal_invmap
-                           && sig < 32
-                           ? current_thread_info()->exec_domain->signal_invmap[sig]
-                           : sig),
-                          &frame->sig);
-        err |= __put_user(&frame->info, &frame->pinfo);
-        err |= __put_user(&frame->uc, &frame->puc);
-        err |= copy_siginfo_to_user(&frame->info, info);
-        /* Create the ucontext.  */
-        err |= __put_user(0, &frame->uc.uc_flags);
-        err |= __put_user(NULL, &frame->uc.uc_link);
-        err |= __put_user((void __user *)current->sas_ss_sp,
-                          &frame->uc.uc_stack.ss_sp);
-        err |= __put_user(sas_ss_flags(rdusp()),
-                          &frame->uc.uc_stack.ss_flags);
-        err |= __put_user(current->sas_ss_size, &frame->uc.uc_stack.ss_size);
-        err |= rt_setup_ucontext(&frame->uc, regs);
-        err |= copy_to_user (&frame->uc.uc_sigmask, set, sizeof(*set));
-        /* Set up to return from userspace.  */
-        err |= __put_user(frame->retcode, &frame->pretcode);
-#ifdef __mcoldfire__
-        /* movel #__NR_rt_sigreturn,d0; trap #0 */
-        err |= __put_user(0x203c0000, (long __user *)(frame->retcode + 0));
-        err |= __put_user(0x00004e40 + (__NR_rt_sigreturn << 16),
-                          (long __user *)(frame->retcode + 4));
-#else
-        /* moveq #,d0; notb d0; trap #0 */
-        err |= __put_user(0x70004600 + ((__NR_rt_sigreturn ^ 0xff) << 16),
-                          (long __user *)(frame->retcode + 0));
-        err |= __put_user(0x4e40, (short __user *)(frame->retcode + 4));
-#endif
-        if (err)
-                goto give_sigsegv;
-        push_cache ((unsigned long) &frame->retcode);
-        /*
-         * Set up registers for signal handler.  All the state we are about
-         * to destroy is successfully copied to sigframe.
-         */
-        wrusp ((unsigned long) frame);
-        regs->pc = (unsigned long) ka->sa.sa_handler;
-        /*
-         * This is subtle; if we build more than one sigframe, all but the
-         * first one will see frame format 0 and have fsize == 0, so we won't
-         * screw stkadj.
-         */
-        if (fsize)
-                regs->stkadj = fsize;
-        /* Prepare to skip over the extra stuff in the exception frame.  */
-        if (regs->stkadj) {
-                struct pt_regs *tregs =
-                        (struct pt_regs *)((ulong)regs + regs->stkadj);
-#ifdef DEBUG
-                printk("Performing stackadjust=%04x\n", regs->stkadj);
-#endif
-                /* This must be copied with decreasing addresses to
-                   handle overlaps.  */
-                tregs->vector = 0;
-                tregs->format = 0;
-                tregs->pc = regs->pc;
-                tregs->sr = regs->sr;
-        }
-        return 0;
-give_sigsegv:
-        force_sigsegv(sig, current);
-        return err;
-}
-static inline void
-handle_restart(struct pt_regs *regs, struct k_sigaction *ka, int has_handler)
-{
-        switch (regs->d0) {
-        case -ERESTARTNOHAND:
-                if (!has_handler)
-                        goto do_restart;
-                regs->d0 = -EINTR;
-                break;
-        case -ERESTART_RESTARTBLOCK:
-                if (!has_handler) {
-                        regs->d0 = __NR_restart_syscall;
-                        regs->pc -= 2;
-                        break;
-                }
-                regs->d0 = -EINTR;
-                break;
-        case -ERESTARTSYS:
-                if (has_handler && !(ka->sa.sa_flags & SA_RESTART)) {
-                        regs->d0 = -EINTR;
-                        break;
-                }
-        /* fallthrough */
-        case -ERESTARTNOINTR:
-        do_restart:
-                regs->d0 = regs->orig_d0;
-                regs->pc -= 2;
-                break;
-        }
-}
-void ptrace_signal_deliver(struct pt_regs *regs, void *cookie)
-{
-        if (regs->orig_d0 < 0)
-                return;
-        switch (regs->d0) {
-        case -ERESTARTNOHAND:
-        case -ERESTARTSYS:
-        case -ERESTARTNOINTR:
-                regs->d0 = regs->orig_d0;
-                regs->orig_d0 = -1;
-                regs->pc -= 2;
-                break;
-        }
-}
-/*
- * OK, we're invoking a handler
- */
-static void
-handle_signal(int sig, struct k_sigaction *ka, siginfo_t *info,
-              sigset_t *oldset, struct pt_regs *regs)
-{
-        int err;
-        /* are we from a system call? */
-        if (regs->orig_d0 >= 0)
-                /* If so, check system call restarting.. */
-                handle_restart(regs, ka, 1);
-        /* set up the stack frame */
-        if (ka->sa.sa_flags & SA_SIGINFO)
-                err = setup_rt_frame(sig, ka, info, oldset, regs);
-        else
-                err = setup_frame(sig, ka, oldset, regs);
-        if (err)
-                return;
-        sigorsets(&current->blocked,&current->blocked,&ka->sa.sa_mask);
-        if (!(ka->sa.sa_flags & SA_NODEFER))
-                sigaddset(&current->blocked,sig);
-        recalc_sigpending();
-        if (test_thread_flag(TIF_DELAYED_TRACE)) {
-                regs->sr &= ~0x8000;
-                send_sig(SIGTRAP, current, 1);
-        }
-        clear_thread_flag(TIF_RESTORE_SIGMASK);
-}
-/*
- * Note that 'init' is a special process: it doesn't get signals it doesn't
- * want to handle. Thus you cannot kill init even with a SIGKILL even by
- * mistake.
- */
-asmlinkage void do_signal(struct pt_regs *regs)
-{
-        siginfo_t info;
-        struct k_sigaction ka;
-        int signr;
-        sigset_t *oldset;
-        current->thread.esp0 = (unsigned long) regs;
-        if (test_thread_flag(TIF_RESTORE_SIGMASK))
-                oldset = &current->saved_sigmask;
-        else
-                oldset = &current->blocked;
-        signr = get_signal_to_deliver(&info, &ka, regs, NULL);
-        if (signr > 0) {
-                /* Whee!  Actually deliver the signal.  */
-                handle_signal(signr, &ka, &info, oldset, regs);
-                return;
-        }
-        /* Did we come from a system call? */
-        if (regs->orig_d0 >= 0)
-                /* Restart the system call - no handlers present */
-                handle_restart(regs, NULL, 0);
-        /* If there's no signal to deliver, we just restore the saved mask.  */
-        if (test_thread_flag(TIF_RESTORE_SIGMASK)) {
-                clear_thread_flag(TIF_RESTORE_SIGMASK);
-                sigprocmask(SIG_SETMASK, &current->saved_sigmask, NULL);
-        }
-}
diff --git a/arch/m68k/kernel/signal_no.c b/arch/m68k/kernel/signal_no.c
deleted file mode 100644
index 36a81bb6835a..000000000000
--- a/arch/m68k/kernel/signal_no.c
+++ /dev/null
@@ -1,765 +0,0 @@
-/*
- *  linux/arch/m68knommu/kernel/signal.c
- *
- *  Copyright (C) 1991, 1992  Linus Torvalds
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file COPYING in the main directory of this archive
- * for more details.
- */
-/*
- * Linux/m68k support by Hamish Macdonald
- *
- * 68060 fixes by Jesper Skov
- *
- * 1997-12-01  Modified for POSIX.1b signals by Andreas Schwab
- *
- * mathemu support by Roman Zippel
- *  (Note: fpstate in the signal context is completely ignored for the emulator
- *         and the internal floating point format is put on stack)
- */
-/*
- * ++roman (07/09/96): implemented signal stacks (specially for tosemu on
- * Atari :-) Current limitation: Only one sigstack can be active at one time.
- * If a second signal with SA_ONSTACK set arrives while working on a sigstack,
- * SA_ONSTACK is ignored. This behaviour avoids lots of trouble with nested
- * signal handlers!
- */
-#include <linux/sched.h>
-#include <linux/mm.h>
-#include <linux/kernel.h>
-#include <linux/signal.h>
-#include <linux/syscalls.h>
-#include <linux/errno.h>
-#include <linux/wait.h>
-#include <linux/ptrace.h>
-#include <linux/unistd.h>
-#include <linux/stddef.h>
-#include <linux/highuid.h>
-#include <linux/tty.h>
-#include <linux/personality.h>
-#include <linux/binfmts.h>
-#include <asm/setup.h>
-#include <asm/uaccess.h>
-#include <asm/pgtable.h>
-#include <asm/traps.h>
-#include <asm/ucontext.h>
-#define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP)))
-void ret_from_user_signal(void);
-void ret_from_user_rt_signal(void);
-/*
- * Atomically swap in the new signal mask, and wait for a signal.
- */
-asmlinkage int
-sys_sigsuspend(int unused0, int unused1, old_sigset_t mask)
-{
-        mask &= _BLOCKABLE;
-        spin_lock_irq(&current->sighand->siglock);
-        current->saved_sigmask = current->blocked;
-        siginitset(&current->blocked, mask);
-        recalc_sigpending();
-        spin_unlock_irq(&current->sighand->siglock);
-        current->state = TASK_INTERRUPTIBLE;
-        schedule();
-        set_restore_sigmask();
-        return -ERESTARTNOHAND;
-}
-asmlinkage int
-sys_sigaction(int sig, const struct old_sigaction __user *act,
-              struct old_sigaction __user *oact)
-{
-        struct k_sigaction new_ka, old_ka;
-        int ret;
-        if (act) {
-                old_sigset_t mask;
-                if (!access_ok(VERIFY_READ, act, sizeof(*act)) ||
-                    __get_user(new_ka.sa.sa_handler, &act->sa_handler) ||
-                    __get_user(new_ka.sa.sa_restorer, &act->sa_restorer) ||
-                    __get_user(new_ka.sa.sa_flags, &act->sa_flags) ||
-                    __get_user(mask, &act->sa_mask))
-                        return -EFAULT;
-                siginitset(&new_ka.sa.sa_mask, mask);
-        }
-        ret = do_sigaction(sig, act ? &new_ka : NULL, oact ? &old_ka : NULL);
-        if (!ret && oact) {
-                if (!access_ok(VERIFY_WRITE, oact, sizeof(*oact)) ||
-                    __put_user(old_ka.sa.sa_handler, &oact->sa_handler) ||
-                    __put_user(old_ka.sa.sa_restorer, &oact->sa_restorer) ||
-                    __put_user(old_ka.sa.sa_flags, &oact->sa_flags) ||
-                    __put_user(old_ka.sa.sa_mask.sig[0], &oact->sa_mask))
-                        return -EFAULT;
-        }
-        return ret;
-}
-asmlinkage int
-sys_sigaltstack(const stack_t __user *uss, stack_t __user *uoss)
-{
-        return do_sigaltstack(uss, uoss, rdusp());
-}
-/*
- * Do a signal return; undo the signal stack.
- *
- * Keep the return code on the stack quadword aligned!
- * That makes the cache flush below easier.
- */
-struct sigframe
-{
-        char __user *pretcode;
-        int sig;
-        int code;
-        struct sigcontext __user *psc;
-        char retcode[8];
-        unsigned long extramask[_NSIG_WORDS-1];
-        struct sigcontext sc;
-};
-struct rt_sigframe
-{
-        char __user *pretcode;
-        int sig;
-        struct siginfo __user *pinfo;
-        void __user *puc;
-        char retcode[8];
-        struct siginfo info;
-        struct ucontext uc;
-};
-#ifdef CONFIG_FPU
-static unsigned char fpu_version = 0;   /* version number of fpu, set by setup_frame */
-static inline int restore_fpu_state(struct sigcontext *sc)
-{
-        int err = 1;
-        if (FPU_IS_EMU) {
-            /* restore registers */
-            memcpy(current->thread.fpcntl, sc->sc_fpcntl, 12);
-            memcpy(current->thread.fp, sc->sc_fpregs, 24);
-            return 0;
-        }
-        if (sc->sc_fpstate[0]) {
-            /* Verify the frame format.  */
-            if (sc->sc_fpstate[0] != fpu_version)
-                goto out;
-            __asm__ volatile (".chip 68k/68881\n\t"
-                              "fmovemx %0,%%fp0-%%fp1\n\t"
-                              "fmoveml %1,%%fpcr/%%fpsr/%%fpiar\n\t"
-                              ".chip 68k"
-                              : /* no outputs */
-                              : "m" (*sc->sc_fpregs), "m" (*sc->sc_fpcntl));
-        }
-        __asm__ volatile (".chip 68k/68881\n\t"
-                          "frestore %0\n\t"
-                          ".chip 68k" : : "m" (*sc->sc_fpstate));
-        err = 0;
-out:
-        return err;
-}
-#define FPCONTEXT_SIZE  216
-#define uc_fpstate      uc_filler[0]
-#define uc_formatvec    uc_filler[FPCONTEXT_SIZE/4]
-#define uc_extra        uc_filler[FPCONTEXT_SIZE/4+1]
-static inline int rt_restore_fpu_state(struct ucontext __user *uc)
-{
-        unsigned char fpstate[FPCONTEXT_SIZE];
-        int context_size = 0;
-        fpregset_t fpregs;
-        int err = 1;
-        if (FPU_IS_EMU) {
-                /* restore fpu control register */
-                if (__copy_from_user(current->thread.fpcntl,
-                                uc->uc_mcontext.fpregs.f_fpcntl, 12))
-                        goto out;
-                /* restore all other fpu register */
-                if (__copy_from_user(current->thread.fp,
-                                uc->uc_mcontext.fpregs.f_fpregs, 96))
-                        goto out;
-                return 0;
-        }
-        if (__get_user(*(long *)fpstate, (long __user *)&uc->uc_fpstate))
-                goto out;
-        if (fpstate[0]) {
-                context_size = fpstate[1];
-                /* Verify the frame format.  */
-                if (fpstate[0] != fpu_version)
-                        goto out;
-                if (__copy_from_user(&fpregs, &uc->uc_mcontext.fpregs,
-                     sizeof(fpregs)))
-                        goto out;
-                __asm__ volatile (".chip 68k/68881\n\t"
-                                  "fmovemx %0,%%fp0-%%fp7\n\t"
-                                  "fmoveml %1,%%fpcr/%%fpsr/%%fpiar\n\t"
-                                  ".chip 68k"
-                                  : /* no outputs */
-                                  : "m" (*fpregs.f_fpregs),
-                                    "m" (*fpregs.f_fpcntl));
-        }
-        if (context_size &&
-            __copy_from_user(fpstate + 4, (long __user *)&uc->uc_fpstate + 1,
-                             context_size))
-                goto out;
-        __asm__ volatile (".chip 68k/68881\n\t"
-                          "frestore %0\n\t"
-                          ".chip 68k" : : "m" (*fpstate));
-        err = 0;
-out:
-        return err;
-}
-#endif
-static inline int
-restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *usc, void __user *fp,
-                   int *pd0)
-{
-        int formatvec;
-        struct sigcontext context;
-        int err = 0;
-        /* Always make any pending restarted system calls return -EINTR */
-        current_thread_info()->restart_block.fn = do_no_restart_syscall;
-        /* get previous context */
-        if (copy_from_user(&context, usc, sizeof(context)))
-                goto badframe;
-        
-        /* restore passed registers */
-        regs->d1 = context.sc_d1;
-        regs->a0 = context.sc_a0;
-        regs->a1 = context.sc_a1;
-        ((struct switch_stack *)regs - 1)->a5 = context.sc_a5;
-        regs->sr = (regs->sr & 0xff00) | (context.sc_sr & 0xff);
-        regs->pc = context.sc_pc;
-        regs->orig_d0 = -1;             /* disable syscall checks */
-        wrusp(context.sc_usp);
-        formatvec = context.sc_formatvec;
-        regs->format = formatvec >> 12;
-        regs->vector = formatvec & 0xfff;
-#ifdef CONFIG_FPU
-        err = restore_fpu_state(&context);
-#endif
-        *pd0 = context.sc_d0;
-        return err;
-badframe:
-        return 1;
-}
-static inline int
-rt_restore_ucontext(struct pt_regs *regs, struct switch_stack *sw,
-                    struct ucontext __user *uc, int *pd0)
-{
-        int temp;
-        greg_t __user *gregs = uc->uc_mcontext.gregs;
-        unsigned long usp;
-        int err;
-        /* Always make any pending restarted system calls return -EINTR */
-        current_thread_info()->restart_block.fn = do_no_restart_syscall;
-        err = __get_user(temp, &uc->uc_mcontext.version);
-        if (temp != MCONTEXT_VERSION)
-                goto badframe;
-        /* restore passed registers */
-        err |= __get_user(regs->d0, &gregs[0]);
-        err |= __get_user(regs->d1, &gregs[1]);
-        err |= __get_user(regs->d2, &gregs[2]);
-        err |= __get_user(regs->d3, &gregs[3]);
-        err |= __get_user(regs->d4, &gregs[4]);
-        err |= __get_user(regs->d5, &gregs[5]);
-        err |= __get_user(sw->d6, &gregs[6]);
-        err |= __get_user(sw->d7, &gregs[7]);
-        err |= __get_user(regs->a0, &gregs[8]);
-        err |= __get_user(regs->a1, &gregs[9]);
-        err |= __get_user(regs->a2, &gregs[10]);
-        err |= __get_user(sw->a3, &gregs[11]);
-        err |= __get_user(sw->a4, &gregs[12]);
-        err |= __get_user(sw->a5, &gregs[13]);
-        err |= __get_user(sw->a6, &gregs[14]);
-        err |= __get_user(usp, &gregs[15]);
-        wrusp(usp);
-        err |= __get_user(regs->pc, &gregs[16]);
-        err |= __get_user(temp, &gregs[17]);
-        regs->sr = (regs->sr & 0xff00) | (temp & 0xff);
-        regs->orig_d0 = -1;             /* disable syscall checks */
-        regs->format = temp >> 12;
-        regs->vector = temp & 0xfff;
-        if (do_sigaltstack(&uc->uc_stack, NULL, usp) == -EFAULT)
-                goto badframe;
-        *pd0 = regs->d0;
-        return err;
-badframe:
-        return 1;
-}
-asmlinkage int do_sigreturn(unsigned long __unused)
-{
-        struct switch_stack *sw = (struct switch_stack *) &__unused;
-        struct pt_regs *regs = (struct pt_regs *) (sw + 1);
-        unsigned long usp = rdusp();
-        struct sigframe __user *frame = (struct sigframe __user *)(usp - 4);
-        sigset_t set;
-        int d0;
-        if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
-                goto badframe;
-        if (__get_user(set.sig[0], &frame->sc.sc_mask) ||
-            (_NSIG_WORDS > 1 &&
-             __copy_from_user(&set.sig[1], &frame->extramask,
-                              sizeof(frame->extramask))))
-                goto badframe;
-        sigdelsetmask(&set, ~_BLOCKABLE);
-        spin_lock_irq(&current->sighand->siglock);
-        current->blocked = set;
-        recalc_sigpending();
-        spin_unlock_irq(&current->sighand->siglock);
-        
-        if (restore_sigcontext(regs, &frame->sc, frame + 1, &d0))
-                goto badframe;
-        return d0;
-badframe:
-        force_sig(SIGSEGV, current);
-        return 0;
-}
-asmlinkage int do_rt_sigreturn(unsigned long __unused)
-{
-        struct switch_stack *sw = (struct switch_stack *) &__unused;
-        struct pt_regs *regs = (struct pt_regs *) (sw + 1);
-        unsigned long usp = rdusp();
-        struct rt_sigframe __user *frame = (struct rt_sigframe __user *)(usp - 4);
-        sigset_t set;
-        int d0;
-        if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
-                goto badframe;
-        if (__copy_from_user(&set, &frame->uc.uc_sigmask, sizeof(set)))
-                goto badframe;
-        sigdelsetmask(&set, ~_BLOCKABLE);
-        spin_lock_irq(&current->sighand->siglock);
-        current->blocked = set;
-        recalc_sigpending();
-        spin_unlock_irq(&current->sighand->siglock);
-        
-        if (rt_restore_ucontext(regs, sw, &frame->uc, &d0))
-                goto badframe;
-        return d0;
-badframe:
-        force_sig(SIGSEGV, current);
-        return 0;
-}
-#ifdef CONFIG_FPU
-/*
- * Set up a signal frame.
- */
-static inline void save_fpu_state(struct sigcontext *sc, struct pt_regs *regs)
-{
-        if (FPU_IS_EMU) {
-                /* save registers */
-                memcpy(sc->sc_fpcntl, current->thread.fpcntl, 12);
-                memcpy(sc->sc_fpregs, current->thread.fp, 24);
-                return;
-        }
-        __asm__ volatile (".chip 68k/68881\n\t"
-                          "fsave %0\n\t"
-                          ".chip 68k"
-                          : : "m" (*sc->sc_fpstate) : "memory");
-        if (sc->sc_fpstate[0]) {
-                fpu_version = sc->sc_fpstate[0];
-                __asm__ volatile (".chip 68k/68881\n\t"
-                                  "fmovemx %%fp0-%%fp1,%0\n\t"
-                                  "fmoveml %%fpcr/%%fpsr/%%fpiar,%1\n\t"
-                                  ".chip 68k"
-                                  : "=m" (*sc->sc_fpregs),
-                                    "=m" (*sc->sc_fpcntl)
-                                  : /* no inputs */
-                                  : "memory");
-        }
-}
-static inline int rt_save_fpu_state(struct ucontext __user *uc, struct pt_regs *regs)
-{
-        unsigned char fpstate[FPCONTEXT_SIZE];
-        int context_size = 0;
-        int err = 0;
-        if (FPU_IS_EMU) {
-                /* save fpu control register */
-                err |= copy_to_user(uc->uc_mcontext.fpregs.f_pcntl,
-                                current->thread.fpcntl, 12);
-                /* save all other fpu register */
-                err |= copy_to_user(uc->uc_mcontext.fpregs.f_fpregs,
-                                current->thread.fp, 96);
-                return err;
-        }
-        __asm__ volatile (".chip 68k/68881\n\t"
-                          "fsave %0\n\t"
-                          ".chip 68k"
-                          : : "m" (*fpstate) : "memory");
-        err |= __put_user(*(long *)fpstate, (long __user *)&uc->uc_fpstate);
-        if (fpstate[0]) {
-                fpregset_t fpregs;
-                context_size = fpstate[1];
-                fpu_version = fpstate[0];
-                __asm__ volatile (".chip 68k/68881\n\t"
-                                  "fmovemx %%fp0-%%fp7,%0\n\t"
-                                  "fmoveml %%fpcr/%%fpsr/%%fpiar,%1\n\t"
-                                  ".chip 68k"
-                                  : "=m" (*fpregs.f_fpregs),
-                                    "=m" (*fpregs.f_fpcntl)
-                                  : /* no inputs */
-                                  : "memory");
-                err |= copy_to_user(&uc->uc_mcontext.fpregs, &fpregs,
-                                    sizeof(fpregs));
-        }
-        if (context_size)
-                err |= copy_to_user((long __user *)&uc->uc_fpstate + 1, fpstate + 4,
-                                    context_size);
-        return err;
-}
-#endif
-static void setup_sigcontext(struct sigcontext *sc, struct pt_regs *regs,
-                             unsigned long mask)
-{
-        sc->sc_mask = mask;
-        sc->sc_usp = rdusp();
-        sc->sc_d0 = regs->d0;
-        sc->sc_d1 = regs->d1;
-        sc->sc_a0 = regs->a0;
-        sc->sc_a1 = regs->a1;
-        sc->sc_a5 = ((struct switch_stack *)regs - 1)->a5;
-        sc->sc_sr = regs->sr;
-        sc->sc_pc = regs->pc;
-        sc->sc_formatvec = regs->format << 12 | regs->vector;
-#ifdef CONFIG_FPU
-        save_fpu_state(sc, regs);
-#endif
-}
-static inline int rt_setup_ucontext(struct ucontext __user *uc, struct pt_regs *regs)
-{
-        struct switch_stack *sw = (struct switch_stack *)regs - 1;
-        greg_t __user *gregs = uc->uc_mcontext.gregs;
-        int err = 0;
-        err |= __put_user(MCONTEXT_VERSION, &uc->uc_mcontext.version);
-        err |= __put_user(regs->d0, &gregs[0]);
-        err |= __put_user(regs->d1, &gregs[1]);
-        err |= __put_user(regs->d2, &gregs[2]);
-        err |= __put_user(regs->d3, &gregs[3]);
-        err |= __put_user(regs->d4, &gregs[4]);
-        err |= __put_user(regs->d5, &gregs[5]);
-        err |= __put_user(sw->d6, &gregs[6]);
-        err |= __put_user(sw->d7, &gregs[7]);
-        err |= __put_user(regs->a0, &gregs[8]);
-        err |= __put_user(regs->a1, &gregs[9]);
-        err |= __put_user(regs->a2, &gregs[10]);
-        err |= __put_user(sw->a3, &gregs[11]);
-        err |= __put_user(sw->a4, &gregs[12]);
-        err |= __put_user(sw->a5, &gregs[13]);
-        err |= __put_user(sw->a6, &gregs[14]);
-        err |= __put_user(rdusp(), &gregs[15]);
-        err |= __put_user(regs->pc, &gregs[16]);
-        err |= __put_user(regs->sr, &gregs[17]);
-#ifdef CONFIG_FPU
-        err |= rt_save_fpu_state(uc, regs);
-#endif
-        return err;
-}
-static inline void __user *
-get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, size_t frame_size)
-{
-        unsigned long usp;
-        /* Default to using normal stack.  */
-        usp = rdusp();
-        /* This is the X/Open sanctioned signal stack switching.  */
-        if (ka->sa.sa_flags & SA_ONSTACK) {
-                if (!sas_ss_flags(usp))
-                        usp = current->sas_ss_sp + current->sas_ss_size;
-        }
-        return (void __user *)((usp - frame_size) & -8UL);
-}
-static int setup_frame (int sig, struct k_sigaction *ka,
-                         sigset_t *set, struct pt_regs *regs)
-{
-        struct sigframe __user *frame;
-        struct sigcontext context;
-        int err = 0;
-        frame = get_sigframe(ka, regs, sizeof(*frame));
-        err |= __put_user((current_thread_info()->exec_domain
-                           && current_thread_info()->exec_domain->signal_invmap
-                           && sig < 32
-                           ? current_thread_info()->exec_domain->signal_invmap[sig]
-                           : sig),
-                          &frame->sig);
-        err |= __put_user(regs->vector, &frame->code);
-        err |= __put_user(&frame->sc, &frame->psc);
-        if (_NSIG_WORDS > 1)
-                err |= copy_to_user(frame->extramask, &set->sig[1],
-                                    sizeof(frame->extramask));
-        setup_sigcontext(&context, regs, set->sig[0]);
-        err |= copy_to_user (&frame->sc, &context, sizeof(context));
-        /* Set up to return from userspace.  */
-        err |= __put_user((void *) ret_from_user_signal, &frame->pretcode);
-        if (err)
-                goto give_sigsegv;
-        /* Set up registers for signal handler */
-        wrusp ((unsigned long) frame);
-        regs->pc = (unsigned long) ka->sa.sa_handler;
-        ((struct switch_stack *)regs - 1)->a5 = current->mm->start_data;
-        regs->format = 0x4; /*set format byte to make stack appear modulo 4 
-                                                which it will be when doing the rte */
-adjust_stack:
-        /* Prepare to skip over the extra stuff in the exception frame.  */
-        if (regs->stkadj) {
-                struct pt_regs *tregs =
-                        (struct pt_regs *)((ulong)regs + regs->stkadj);
-#if defined(DEBUG)
-                printk(KERN_DEBUG "Performing stackadjust=%04x\n", regs->stkadj);
-#endif
-                /* This must be copied with decreasing addresses to
-                   handle overlaps.  */
-                tregs->vector = 0;
-                tregs->format = 0;
-                tregs->pc = regs->pc;
-                tregs->sr = regs->sr;
-        }
-        return err;
-give_sigsegv:
-        force_sigsegv(sig, current);
-        goto adjust_stack;
-}
-static int setup_rt_frame (int sig, struct k_sigaction *ka, siginfo_t *info,
-                            sigset_t *set, struct pt_regs *regs)
-{
-        struct rt_sigframe __user *frame;
-        int err = 0;
-        frame = get_sigframe(ka, regs, sizeof(*frame));
-        err |= __put_user((current_thread_info()->exec_domain
-                           && current_thread_info()->exec_domain->signal_invmap
-                           && sig < 32
-                           ? current_thread_info()->exec_domain->signal_invmap[sig]
-                           : sig),
-                          &frame->sig);
-        err |= __put_user(&frame->info, &frame->pinfo);
-        err |= __put_user(&frame->uc, &frame->puc);
-        err |= copy_siginfo_to_user(&frame->info, info);
-        /* Create the ucontext.  */
-        err |= __put_user(0, &frame->uc.uc_flags);
-        err |= __put_user(NULL, &frame->uc.uc_link);
-        err |= __put_user((void __user *)current->sas_ss_sp,
-                          &frame->uc.uc_stack.ss_sp);
-        err |= __put_user(sas_ss_flags(rdusp()),
-                          &frame->uc.uc_stack.ss_flags);
-        err |= __put_user(current->sas_ss_size, &frame->uc.uc_stack.ss_size);
-        err |= rt_setup_ucontext(&frame->uc, regs);
-        err |= copy_to_user (&frame->uc.uc_sigmask, set, sizeof(*set));
-        /* Set up to return from userspace.  */
-        err |= __put_user((void *) ret_from_user_rt_signal, &frame->pretcode);
-        if (err)
-                goto give_sigsegv;
-        /* Set up registers for signal handler */
-        wrusp ((unsigned long) frame);
-        regs->pc = (unsigned long) ka->sa.sa_handler;
-        ((struct switch_stack *)regs - 1)->a5 = current->mm->start_data;
-        regs->format = 0x4; /*set format byte to make stack appear modulo 4 
-                                                which it will be when doing the rte */
-adjust_stack:
-        /* Prepare to skip over the extra stuff in the exception frame.  */
-        if (regs->stkadj) {
-                struct pt_regs *tregs =
-                        (struct pt_regs *)((ulong)regs + regs->stkadj);
-#if defined(DEBUG)
-                printk(KERN_DEBUG "Performing stackadjust=%04x\n", regs->stkadj);
-#endif
-                /* This must be copied with decreasing addresses to
-                   handle overlaps.  */
-                tregs->vector = 0;
-                tregs->format = 0;
-                tregs->pc = regs->pc;
-                tregs->sr = regs->sr;
-        }
-        return err;
-give_sigsegv:
-        force_sigsegv(sig, current);
-        goto adjust_stack;
-}
-static inline void
-handle_restart(struct pt_regs *regs, struct k_sigaction *ka, int has_handler)
-{
-        switch (regs->d0) {
-        case -ERESTARTNOHAND:
-                if (!has_handler)
-                        goto do_restart;
-                regs->d0 = -EINTR;
-                break;
-        case -ERESTART_RESTARTBLOCK:
-                if (!has_handler) {
-                        regs->d0 = __NR_restart_syscall;
-                        regs->pc -= 2;
-                        break;
-                }
-                regs->d0 = -EINTR;
-                break;
-        case -ERESTARTSYS:
-                if (has_handler && !(ka->sa.sa_flags & SA_RESTART)) {
-                        regs->d0 = -EINTR;
-                        break;
-                }
-        /* fallthrough */
-        case -ERESTARTNOINTR:
-        do_restart:
-                regs->d0 = regs->orig_d0;
-                regs->pc -= 2;
-                break;
-        }
-}
-/*
- * OK, we're invoking a handler
- */
-static void
-handle_signal(int sig, struct k_sigaction *ka, siginfo_t *info,
-              sigset_t *oldset, struct pt_regs *regs)
-{
-        int err;
-        /* are we from a system call? */
-        if (regs->orig_d0 >= 0)
-                /* If so, check system call restarting.. */
-                handle_restart(regs, ka, 1);
-        /* set up the stack frame */
-        if (ka->sa.sa_flags & SA_SIGINFO)
-                err = setup_rt_frame(sig, ka, info, oldset, regs);
-        else
-                err = setup_frame(sig, ka, oldset, regs);
-        if (err)
-                return;
-        spin_lock_irq(&current->sighand->siglock);
-        sigorsets(&current->blocked,&current->blocked,&ka->sa.sa_mask);
-        if (!(ka->sa.sa_flags & SA_NODEFER))
-                sigaddset(&current->blocked,sig);
-        recalc_sigpending();
-        spin_unlock_irq(&current->sighand->siglock);
-        clear_thread_flag(TIF_RESTORE_SIGMASK);
-}
-/*
- * Note that 'init' is a special process: it doesn't get signals it doesn't
- * want to handle. Thus you cannot kill init even with a SIGKILL even by
- * mistake.
- */
-asmlinkage void do_signal(struct pt_regs *regs)
-{
-        struct k_sigaction ka;
-        siginfo_t info;
-        int signr;
-        sigset_t *oldset;
-        /*
-         * We want the common case to go fast, which
-         * is why we may in certain cases get here from
-         * kernel mode. Just return without doing anything
-         * if so.
-         */
-        if (!user_mode(regs))
-                return;
-        if (test_thread_flag(TIF_RESTORE_SIGMASK))
-                oldset = &current->saved_sigmask;
-        else
-                oldset = &current->blocked;
-        signr = get_signal_to_deliver(&info, &ka, regs, NULL);
-        if (signr > 0) {
-                /* Whee!  Actually deliver the signal.  */
-                handle_signal(signr, &ka, &info, oldset, regs);
-                return;
-        }
-        /* Did we come from a system call? */
-        if (regs->orig_d0 >= 0) {
-                /* Restart the system call - no handlers present */
-                handle_restart(regs, NULL, 0);
-        }
-        /* If there's no signal to deliver, we just restore the saved mask.  */
-        if (test_thread_flag(TIF_RESTORE_SIGMASK)) {
-                clear_thread_flag(TIF_RESTORE_SIGMASK);
-                sigprocmask(SIG_SETMASK, &current->saved_sigmask, NULL);
-        }
-}
diff --git a/arch/m68k/mm/fault.c b/arch/m68k/mm/fault.c
index 6b020a8461e7..aeebbb7b30f0 100644
--- a/arch/m68k/mm/fault.c
+++ b/arch/m68k/mm/fault.c
@@ -72,7 +72,8 @@ int do_page_fault(struct pt_regs *regs, unsigned long address,
 {
        struct mm_struct *mm = current->mm;
        struct vm_area_struct * vma;
-        int write, fault;
+        int fault;
+        unsigned int flags = FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE;
 #ifdef DEBUG
        printk ("do page fault:\nregs->sr=%#x, regs->pc=%#lx, address=%#lx, %ld, %p\n",
@@ -87,6 +88,7 @@ int do_page_fault(struct pt_regs *regs, unsigned long address,
        if (in_atomic() || !mm)
                goto no_context;
+retry:
        down_read(&mm->mmap_sem);
        vma = find_vma(mm, address);
@@ -117,14 +119,13 @@ good_area:
 #ifdef DEBUG
        printk("do_page_fault: good_area\n");
 #endif
-        write = 0;
        switch (error_code & 3) {
                default:        /* 3: write, present */
                        /* fall through */
                case 2:         /* write, not present */
                        if (!(vma->vm_flags & VM_WRITE))
                                goto acc_err;
-                        write++;
+                        flags |= FAULT_FLAG_WRITE;
                        break;
                case 1:         /* read, present */
                        goto acc_err;
@@ -139,10 +140,14 @@ good_area:
         * the fault.
         */
-        fault = handle_mm_fault(mm, vma, address, write ? FAULT_FLAG_WRITE : 0);
+        fault = handle_mm_fault(mm, vma, address, flags);
 #ifdef DEBUG
        printk("handle_mm_fault returns %d\n",fault);
 #endif
+        if ((fault & VM_FAULT_RETRY) && fatal_signal_pending(current))
+                return 0;
        if (unlikely(fault & VM_FAULT_ERROR)) {
                if (fault & VM_FAULT_OOM)
                        goto out_of_memory;
@@ -150,10 +155,31 @@ good_area:
                        goto bus_err;
                BUG();
        }
-        if (fault & VM_FAULT_MAJOR)
-                current->maj_flt++;
+        /*
-        else
+         * Major/minor page fault accounting is only done on the
-                current->min_flt++;
+         * initial attempt. If we go through a retry, it is extremely
+         * likely that the page will be found in page cache at that point.
+         */
+        if (flags & FAULT_FLAG_ALLOW_RETRY) {
+                if (fault & VM_FAULT_MAJOR)
+                        current->maj_flt++;
+                else
+                        current->min_flt++;
+                if (fault & VM_FAULT_RETRY) {
+                        /* Clear FAULT_FLAG_ALLOW_RETRY to avoid any risk
+                         * of starvation. */
+                        flags &= ~FAULT_FLAG_ALLOW_RETRY;
+                        /*
+                         * No need to up_read(&mm->mmap_sem) as we would
+                         * have already released it in __lock_page_or_retry
+                         * in mm/filemap.c.
+                         */
+                        goto retry;
+                }
+        }
        up_read(&mm->mmap_sem);
        return 0;
diff --git a/arch/m68k/platform/5206/Makefile b/arch/m68k/platform/5206/Makefile
deleted file mode 100644
index b5db05625cfa..000000000000
--- a/arch/m68k/platform/5206/Makefile
+++ /dev/null
@@ -1,18 +0,0 @@
-#
-# Makefile for the m68knommu linux kernel.
-#
-#
-# If you want to play with the HW breakpoints then you will
-# need to add define this,  which will give you a stack backtrace
-# on the console port whenever a DBG interrupt occurs.  You have to
-# set up you HW breakpoints to trigger a DBG interrupt:
-#
-# ccflags-y := -DTRAP_DBG_INTERRUPT
-# asflags-y := -DTRAP_DBG_INTERRUPT
-#
-asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
-obj-y := config.o gpio.o
diff --git a/arch/m68k/platform/5206/gpio.c b/arch/m68k/platform/5206/gpio.c
deleted file mode 100644
index b9ab4a120f28..000000000000
--- a/arch/m68k/platform/5206/gpio.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * Coldfire generic GPIO support
- *
- * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
-*/
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <asm/coldfire.h>
-#include <asm/mcfsim.h>
-#include <asm/mcfgpio.h>
-static struct mcf_gpio_chip mcf_gpio_chips[] = {
-        {
-                .gpio_chip                      = {
-                        .label                  = "PP",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value,
-                        .ngpio                  = 8,
-                },
-                .pddr                           = (void __iomem *) MCFSIM_PADDR,
-                .podr                           = (void __iomem *) MCFSIM_PADAT,
-                .ppdr                           = (void __iomem *) MCFSIM_PADAT,
-        },
-};
-static int __init mcf_gpio_init(void)
-{
-        unsigned i = 0;
-        while (i < ARRAY_SIZE(mcf_gpio_chips))
-                (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
-        return 0;
-}
-core_initcall(mcf_gpio_init);
diff --git a/arch/m68k/platform/520x/Makefile b/arch/m68k/platform/520x/Makefile
deleted file mode 100644
index ad3f4e5a57ce..000000000000
--- a/arch/m68k/platform/520x/Makefile
+++ /dev/null
@@ -1,17 +0,0 @@
-#
-# Makefile for the M5208 specific file.
-#
-#
-# If you want to play with the HW breakpoints then you will
-# need to add define this,  which will give you a stack backtrace
-# on the console port whenever a DBG interrupt occurs.  You have to
-# set up you HW breakpoints to trigger a DBG interrupt:
-#
-# ccflags-y := -DTRAP_DBG_INTERRUPT
-# asflags-y := -DTRAP_DBG_INTERRUPT
-#
-asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
-obj-y := config.o gpio.o
diff --git a/arch/m68k/platform/520x/gpio.c b/arch/m68k/platform/520x/gpio.c
deleted file mode 100644
index 9bcc3e4b60c5..000000000000
--- a/arch/m68k/platform/520x/gpio.c
+++ /dev/null
@@ -1,175 +0,0 @@
-/*
- * Coldfire generic GPIO support
- *
- * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
-*/
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <asm/coldfire.h>
-#include <asm/mcfsim.h>
-#include <asm/mcfgpio.h>
-static struct mcf_gpio_chip mcf_gpio_chips[] = {
-        {
-                .gpio_chip                      = {
-                        .label                  = "PIRQ",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value,
-                        .ngpio                  = 8,
-                },
-                .pddr                           = (void __iomem *) MCFEPORT_EPDDR,
-                .podr                           = (void __iomem *) MCFEPORT_EPDR,
-                .ppdr                           = (void __iomem *) MCFEPORT_EPPDR,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "CS",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 9,
-                        .ngpio                  = 3,
-                },
-                .pddr                           = (void __iomem *) MCFGPIO_PDDR_CS,
-                .podr                           = (void __iomem *) MCFGPIO_PODR_CS,
-                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_CS,
-                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_CS,
-                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_CS,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "FECI2C",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 16,
-                        .ngpio                  = 4,
-                },
-                .pddr                           = (void __iomem *) MCFGPIO_PDDR_FECI2C,
-                .podr                           = (void __iomem *) MCFGPIO_PODR_FECI2C,
-                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
-                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
-                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_FECI2C,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "QSPI",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 24,
-                        .ngpio                  = 4,
-                },
-                .pddr                           = (void __iomem *) MCFGPIO_PDDR_QSPI,
-                .podr                           = (void __iomem *) MCFGPIO_PODR_QSPI,
-                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_QSPI,
-                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_QSPI,
-                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_QSPI,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "TIMER",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 32,
-                        .ngpio                  = 4,
-                },
-                .pddr                           = (void __iomem *) MCFGPIO_PDDR_TIMER,
-                .podr                           = (void __iomem *) MCFGPIO_PODR_TIMER,
-                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_TIMER,
-                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_TIMER,
-                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_TIMER,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "UART",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 40,
-                        .ngpio                  = 8,
-                },
-                .pddr                           = (void __iomem *) MCFGPIO_PDDR_UART,
-                .podr                           = (void __iomem *) MCFGPIO_PODR_UART,
-                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_UART,
-                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_UART,
-                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_UART,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "FECH",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 48,
-                        .ngpio                  = 8,
-                },
-                .pddr                           = (void __iomem *) MCFGPIO_PDDR_FECH,
-                .podr                           = (void __iomem *) MCFGPIO_PODR_FECH,
-                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_FECH,
-                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_FECH,
-                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_FECH,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "FECL",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 56,
-                        .ngpio                  = 8,
-                },
-                .pddr                           = (void __iomem *) MCFGPIO_PDDR_FECL,
-                .podr                           = (void __iomem *) MCFGPIO_PODR_FECL,
-                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_FECL,
-                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_FECL,
-                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_FECL,
-        },
-};
-static int __init mcf_gpio_init(void)
-{
-        unsigned i = 0;
-        while (i < ARRAY_SIZE(mcf_gpio_chips))
-                (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
-        return 0;
-}
-core_initcall(mcf_gpio_init);
diff --git a/arch/m68k/platform/523x/Makefile b/arch/m68k/platform/523x/Makefile
deleted file mode 100644
index c04b8f71c88c..000000000000
--- a/arch/m68k/platform/523x/Makefile
+++ /dev/null
@@ -1,17 +0,0 @@
-#
-# Makefile for the m68knommu linux kernel.
-#
-#
-# If you want to play with the HW breakpoints then you will
-# need to add define this,  which will give you a stack backtrace
-# on the console port whenever a DBG interrupt occurs.  You have to
-# set up you HW breakpoints to trigger a DBG interrupt:
-#
-# ccflags-y := -DTRAP_DBG_INTERRUPT
-# asflags-y := -DTRAP_DBG_INTERRUPT
-#
-asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
-obj-y := config.o gpio.o
diff --git a/arch/m68k/platform/523x/gpio.c b/arch/m68k/platform/523x/gpio.c
deleted file mode 100644
index 327ebf142c8e..000000000000
--- a/arch/m68k/platform/523x/gpio.c
+++ /dev/null
@@ -1,284 +0,0 @@
-/*
- * Coldfire generic GPIO support
- *
- * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
-*/
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <asm/coldfire.h>
-#include <asm/mcfsim.h>
-#include <asm/mcfgpio.h>
-static struct mcf_gpio_chip mcf_gpio_chips[] = {
-        {
-                .gpio_chip                      = {
-                        .label                  = "PIRQ",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value,
-                        .base                   = 1,
-                        .ngpio                  = 7,
-                },
-                .pddr                           = (void __iomem *) MCFEPORT_EPDDR,
-                .podr                           = (void __iomem *) MCFEPORT_EPDR,
-                .ppdr                           = (void __iomem *) MCFEPORT_EPPDR,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "ADDR",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 13,
-                        .ngpio                  = 3,
-                },
-                .pddr                           = (void __iomem *) MCFGPIO_PDDR_ADDR,
-                .podr                           = (void __iomem *) MCFGPIO_PODR_ADDR,
-                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_ADDR,
-                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_ADDR,
-                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_ADDR,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "DATAH",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 16,
-                        .ngpio                  = 8,
-                },
-                .pddr                           = (void __iomem *) MCFGPIO_PDDR_DATAH,
-                .podr                           = (void __iomem *) MCFGPIO_PODR_DATAH,
-                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_DATAH,
-                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_DATAH,
-                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_DATAH,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "DATAL",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 24,
-                        .ngpio                  = 8,
-                },
-                .pddr                           = (void __iomem *) MCFGPIO_PDDR_DATAL,
-                .podr                           = (void __iomem *) MCFGPIO_PODR_DATAL,
-                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_DATAL,
-                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_DATAL,
-                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_DATAL,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "BUSCTL",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 32,
-                        .ngpio                  = 8,
-                },
-                .pddr                           = (void __iomem *) MCFGPIO_PDDR_BUSCTL,
-                .podr                           = (void __iomem *) MCFGPIO_PODR_BUSCTL,
-                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
-                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
-                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_BUSCTL,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "BS",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 40,
-                        .ngpio                  = 4,
-                },
-                .pddr                           = (void __iomem *) MCFGPIO_PDDR_BS,
-                .podr                           = (void __iomem *) MCFGPIO_PODR_BS,
-                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_BS,
-                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_BS,
-                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_BS,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "CS",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 49,
-                        .ngpio                  = 7,
-                },
-                .pddr                           = (void __iomem *) MCFGPIO_PDDR_CS,
-                .podr                           = (void __iomem *) MCFGPIO_PODR_CS,
-                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_CS,
-                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_CS,
-                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_CS,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "SDRAM",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 56,
-                        .ngpio                  = 6,
-                },
-                .pddr                           = (void __iomem *) MCFGPIO_PDDR_SDRAM,
-                .podr                           = (void __iomem *) MCFGPIO_PODR_SDRAM,
-                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_SDRAM,
-                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_SDRAM,
-                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_SDRAM,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "FECI2C",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 64,
-                        .ngpio                  = 4,
-                },
-                .pddr                           = (void __iomem *) MCFGPIO_PDDR_FECI2C,
-                .podr                           = (void __iomem *) MCFGPIO_PODR_FECI2C,
-                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
-                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
-                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_FECI2C,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "UARTH",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 72,
-                        .ngpio                  = 2,
-                },
-                .pddr                           = (void __iomem *) MCFGPIO_PDDR_UARTH,
-                .podr                           = (void __iomem *) MCFGPIO_PODR_UARTH,
-                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_UARTH,
-                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_UARTH,
-                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_UARTH,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "UARTL",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 80,
-                        .ngpio                  = 8,
-                },
-                .pddr                           = (void __iomem *) MCFGPIO_PDDR_UARTL,
-                .podr                           = (void __iomem *) MCFGPIO_PODR_UARTL,
-                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_UARTL,
-                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_UARTL,
-                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_UARTL,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "QSPI",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 88,
-                        .ngpio                  = 5,
-                },
-                .pddr                           = (void __iomem *) MCFGPIO_PDDR_QSPI,
-                .podr                           = (void __iomem *) MCFGPIO_PODR_QSPI,
-                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_QSPI,
-                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_QSPI,
-                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_QSPI,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "TIMER",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 96,
-                        .ngpio                  = 8,
-                },
-                .pddr                           = (void __iomem *) MCFGPIO_PDDR_TIMER,
-                .podr                           = (void __iomem *) MCFGPIO_PODR_TIMER,
-                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_TIMER,
-                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_TIMER,
-                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_TIMER,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "ETPU",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 104,
-                        .ngpio                  = 3,
-                },
-                .pddr                           = (void __iomem *) MCFGPIO_PDDR_ETPU,
-                .podr                           = (void __iomem *) MCFGPIO_PODR_ETPU,
-                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_ETPU,
-                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_ETPU,
-                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_ETPU,
-        },
-};
-static int __init mcf_gpio_init(void)
-{
-        unsigned i = 0;
-        while (i < ARRAY_SIZE(mcf_gpio_chips))
-                (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
-        return 0;
-}
-core_initcall(mcf_gpio_init);
diff --git a/arch/m68k/platform/5249/Makefile b/arch/m68k/platform/5249/Makefile
deleted file mode 100644
index 4bed30fd0073..000000000000
--- a/arch/m68k/platform/5249/Makefile
+++ /dev/null
@@ -1,18 +0,0 @@
-#
-# Makefile for the m68knommu linux kernel.
-#
-#
-# If you want to play with the HW breakpoints then you will
-# need to add define this,  which will give you a stack backtrace
-# on the console port whenever a DBG interrupt occurs.  You have to
-# set up you HW breakpoints to trigger a DBG interrupt:
-#
-# ccflags-y := -DTRAP_DBG_INTERRUPT
-# asflags-y := -DTRAP_DBG_INTERRUPT
-#
-asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
-obj-y := config.o gpio.o intc2.o
diff --git a/arch/m68k/platform/5249/gpio.c b/arch/m68k/platform/5249/gpio.c
deleted file mode 100644
index 2b56c6ef65bf..000000000000
--- a/arch/m68k/platform/5249/gpio.c
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * Coldfire generic GPIO support
- *
- * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
-*/
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <asm/coldfire.h>
-#include <asm/mcfsim.h>
-#include <asm/mcfgpio.h>
-static struct mcf_gpio_chip mcf_gpio_chips[] = {
-        {
-                .gpio_chip                      = {
-                        .label                  = "GPIO0",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value,
-                        .ngpio                  = 32,
-                },
-                .pddr                           = (void __iomem *) MCFSIM2_GPIOENABLE,
-                .podr                           = (void __iomem *) MCFSIM2_GPIOWRITE,
-                .ppdr                           = (void __iomem *) MCFSIM2_GPIOREAD,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "GPIO1",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value,
-                        .base                   = 32,
-                        .ngpio                  = 32,
-                },
-                .pddr                           = (void __iomem *) MCFSIM2_GPIO1ENABLE,
-                .podr                           = (void __iomem *) MCFSIM2_GPIO1WRITE,
-                .ppdr                           = (void __iomem *) MCFSIM2_GPIO1READ,
-        },
-};
-static int __init mcf_gpio_init(void)
-{
-        unsigned i = 0;
-        while (i < ARRAY_SIZE(mcf_gpio_chips))
-                (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
-        return 0;
-}
-core_initcall(mcf_gpio_init);
diff --git a/arch/m68k/platform/5272/Makefile b/arch/m68k/platform/5272/Makefile
deleted file mode 100644
index 34110fc14301..000000000000
--- a/arch/m68k/platform/5272/Makefile
+++ /dev/null
@@ -1,18 +0,0 @@
-#
-# Makefile for the linux kernel.
-#
-#
-# If you want to play with the HW breakpoints then you will
-# need to add define this,  which will give you a stack backtrace
-# on the console port whenever a DBG interrupt occurs.  You have to
-# set up you HW breakpoints to trigger a DBG interrupt:
-#
-# ccflags-y := -DTRAP_DBG_INTERRUPT
-# asflags-y := -DTRAP_DBG_INTERRUPT
-#
-asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
-obj-y := config.o gpio.o intc.o
diff --git a/arch/m68k/platform/5272/gpio.c b/arch/m68k/platform/5272/gpio.c
deleted file mode 100644
index 57ac10a5d7f7..000000000000
--- a/arch/m68k/platform/5272/gpio.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * Coldfire generic GPIO support
- *
- * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
-*/
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <asm/coldfire.h>
-#include <asm/mcfsim.h>
-#include <asm/mcfgpio.h>
-static struct mcf_gpio_chip mcf_gpio_chips[] = {
-        {
-                .gpio_chip                      = {
-                        .label                  = "PA",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value,
-                        .ngpio                  = 16,
-                },
-                .pddr                           = (void __iomem *) MCFSIM_PADDR,
-                .podr                           = (void __iomem *) MCFSIM_PADAT,
-                .ppdr                           = (void __iomem *) MCFSIM_PADAT,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "PB",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value,
-                        .base                   = 16,
-                        .ngpio                  = 16,
-                },
-                .pddr                           = (void __iomem *) MCFSIM_PBDDR,
-                .podr                           = (void __iomem *) MCFSIM_PBDAT,
-                .ppdr                           = (void __iomem *) MCFSIM_PBDAT,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "PC",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value,
-                        .base                   = 32,
-                        .ngpio                  = 16,
-                },
-                .pddr                           = (void __iomem *) MCFSIM_PCDDR,
-                .podr                           = (void __iomem *) MCFSIM_PCDAT,
-                .ppdr                           = (void __iomem *) MCFSIM_PCDAT,
-        },
-};
-static int __init mcf_gpio_init(void)
-{
-        unsigned i = 0;
-        while (i < ARRAY_SIZE(mcf_gpio_chips))
-                (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
-        return 0;
-}
-core_initcall(mcf_gpio_init);
diff --git a/arch/m68k/platform/527x/Makefile b/arch/m68k/platform/527x/Makefile
deleted file mode 100644
index 6ac4b57370ea..000000000000
--- a/arch/m68k/platform/527x/Makefile
+++ /dev/null
@@ -1,18 +0,0 @@
-#
-# Makefile for the linux kernel.
-#
-#
-# If you want to play with the HW breakpoints then you will
-# need to add define this,  which will give you a stack backtrace
-# on the console port whenever a DBG interrupt occurs.  You have to
-# set up you HW breakpoints to trigger a DBG interrupt:
-#
-# ccflags-y := -DTRAP_DBG_INTERRUPT
-# asflags-y := -DTRAP_DBG_INTERRUPT
-#
-asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
-obj-y := config.o gpio.o
diff --git a/arch/m68k/platform/527x/gpio.c b/arch/m68k/platform/527x/gpio.c
deleted file mode 100644
index 205da0aa0f2d..000000000000
--- a/arch/m68k/platform/527x/gpio.c
+++ /dev/null
@@ -1,609 +0,0 @@
-/*
- * Coldfire generic GPIO support
- *
- * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
-*/
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <asm/coldfire.h>
-#include <asm/mcfsim.h>
-#include <asm/mcfgpio.h>
-static struct mcf_gpio_chip mcf_gpio_chips[] = {
-#if defined(CONFIG_M5271)
-        {
-                .gpio_chip                      = {
-                        .label                  = "PIRQ",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value,
-                        .base                   = 1,
-                        .ngpio                  = 7,
-                },
-                .pddr                           = (void __iomem *) MCFEPORT_EPDDR,
-                .podr                           = (void __iomem *) MCFEPORT_EPDR,
-                .ppdr                           = (void __iomem *) MCFEPORT_EPPDR,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "ADDR",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 13,
-                        .ngpio                  = 3,
-                },
-                .pddr                           = (void __iomem *) MCFGPIO_PDDR_ADDR,
-                .podr                           = (void __iomem *) MCFGPIO_PODR_ADDR,
-                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_ADDR,
-                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_ADDR,
-                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_ADDR,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "DATAH",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 16,
-                        .ngpio                  = 8,
-                },
-                .pddr                           = (void __iomem *) MCFGPIO_PDDR_DATAH,
-                .podr                           = (void __iomem *) MCFGPIO_PODR_DATAH,
-                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_DATAH,
-                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_DATAH,
-                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_DATAH,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "DATAL",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 24,
-                        .ngpio                  = 8,
-                },
-                .pddr                           = (void __iomem *) MCFGPIO_PDDR_DATAL,
-                .podr                           = (void __iomem *) MCFGPIO_PODR_DATAL,
-                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_DATAL,
-                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_DATAL,
-                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_DATAL,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "BUSCTL",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 32,
-                        .ngpio                  = 8,
-                },
-                .pddr                           = (void __iomem *) MCFGPIO_PDDR_BUSCTL,
-                .podr                           = (void __iomem *) MCFGPIO_PODR_BUSCTL,
-                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
-                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
-                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_BUSCTL,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "BS",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 40,
-                        .ngpio                  = 4,
-                },
-                .pddr                           = (void __iomem *) MCFGPIO_PDDR_BS,
-                .podr                           = (void __iomem *) MCFGPIO_PODR_BS,
-                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_BS,
-                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_BS,
-                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_BS,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "CS",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 49,
-                        .ngpio                  = 7,
-                },
-                .pddr                           = (void __iomem *) MCFGPIO_PDDR_CS,
-                .podr                           = (void __iomem *) MCFGPIO_PODR_CS,
-                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_CS,
-                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_CS,
-                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_CS,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "SDRAM",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 56,
-                        .ngpio                  = 6,
-                },
-                .pddr                           = (void __iomem *) MCFGPIO_PDDR_SDRAM,
-                .podr                           = (void __iomem *) MCFGPIO_PODR_SDRAM,
-                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_SDRAM,
-                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_SDRAM,
-                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_SDRAM,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "FECI2C",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 64,
-                        .ngpio                  = 4,
-                },
-                .pddr                           = (void __iomem *) MCFGPIO_PDDR_FECI2C,
-                .podr                           = (void __iomem *) MCFGPIO_PODR_FECI2C,
-                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
-                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
-                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_FECI2C,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "UARTH",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 72,
-                        .ngpio                  = 2,
-                },
-                .pddr                           = (void __iomem *) MCFGPIO_PDDR_UARTH,
-                .podr                           = (void __iomem *) MCFGPIO_PODR_UARTH,
-                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_UARTH,
-                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_UARTH,
-                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_UARTH,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "UARTL",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 80,
-                        .ngpio                  = 8,
-                },
-                .pddr                           = (void __iomem *) MCFGPIO_PDDR_UARTL,
-                .podr                           = (void __iomem *) MCFGPIO_PODR_UARTL,
-                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_UARTL,
-                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_UARTL,
-                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_UARTL,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "QSPI",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 88,
-                        .ngpio                  = 5,
-                },
-                .pddr                           = (void __iomem *) MCFGPIO_PDDR_QSPI,
-                .podr                           = (void __iomem *) MCFGPIO_PODR_QSPI,
-                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_QSPI,
-                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_QSPI,
-                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_QSPI,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "TIMER",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 96,
-                        .ngpio                  = 8,
-                },
-                .pddr                           = (void __iomem *) MCFGPIO_PDDR_TIMER,
-                .podr                           = (void __iomem *) MCFGPIO_PODR_TIMER,
-                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_TIMER,
-                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_TIMER,
-                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_TIMER,
-        },
-#elif defined(CONFIG_M5275)
-        {
-                .gpio_chip                      = {
-                        .label                  = "PIRQ",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value,
-                        .base                   = 1,
-                        .ngpio                  = 7,
-                },
-                .pddr                           = (void __iomem *) MCFEPORT_EPDDR,
-                .podr                           = (void __iomem *) MCFEPORT_EPDR,
-                .ppdr                           = (void __iomem *) MCFEPORT_EPPDR,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "BUSCTL",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 8,
-                        .ngpio                  = 8,
-                },
-                .pddr                           = (void __iomem *) MCFGPIO_PDDR_BUSCTL,
-                .podr                           = (void __iomem *) MCFGPIO_PODR_BUSCTL,
-                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
-                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
-                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_BUSCTL,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "ADDR",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 21,
-                        .ngpio                  = 3,
-                },
-                .pddr                           = (void __iomem *) MCFGPIO_PDDR_ADDR,
-                .podr                           = (void __iomem *) MCFGPIO_PODR_ADDR,
-                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_ADDR,
-                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_ADDR,
-                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_ADDR,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "CS",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 25,
-                        .ngpio                  = 7,
-                },
-                .pddr                           = (void __iomem *) MCFGPIO_PDDR_CS,
-                .podr                           = (void __iomem *) MCFGPIO_PODR_CS,
-                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_CS,
-                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_CS,
-                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_CS,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "FEC0H",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 32,
-                        .ngpio                  = 8,
-                },
-                .pddr                           = (void __iomem *) MCFGPIO_PDDR_FEC0H,
-                .podr                           = (void __iomem *) MCFGPIO_PODR_FEC0H,
-                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_FEC0H,
-                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_FEC0H,
-                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_FEC0H,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "FEC0L",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 40,
-                        .ngpio                  = 8,
-                },
-                .pddr                           = (void __iomem *) MCFGPIO_PDDR_FEC0L,
-                .podr                           = (void __iomem *) MCFGPIO_PODR_FEC0L,
-                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_FEC0L,
-                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_FEC0L,
-                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_FEC0L,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "FECI2C",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 48,
-                        .ngpio                  = 6,
-                },
-                .pddr                           = (void __iomem *) MCFGPIO_PDDR_FECI2C,
-                .podr                           = (void __iomem *) MCFGPIO_PODR_FECI2C,
-                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
-                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
-                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_FECI2C,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "QSPI",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 56,
-                        .ngpio                  = 7,
-                },
-                .pddr                           = (void __iomem *) MCFGPIO_PDDR_QSPI,
-                .podr                           = (void __iomem *) MCFGPIO_PODR_QSPI,
-                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_QSPI,
-                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_QSPI,
-                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_QSPI,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "SDRAM",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 64,
-                        .ngpio                  = 8,
-                },
-                .pddr                           = (void __iomem *) MCFGPIO_PDDR_SDRAM,
-                .podr                           = (void __iomem *) MCFGPIO_PODR_SDRAM,
-                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_SDRAM,
-                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_SDRAM,
-                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_SDRAM,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "TIMERH",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 72,
-                        .ngpio                  = 4,
-                },
-                .pddr                           = (void __iomem *) MCFGPIO_PDDR_TIMERH,
-                .podr                           = (void __iomem *) MCFGPIO_PODR_TIMERH,
-                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_TIMERH,
-                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_TIMERH,
-                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_TIMERH,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "TIMERL",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 80,
-                        .ngpio                  = 4,
-                },
-                .pddr                           = (void __iomem *) MCFGPIO_PDDR_TIMERL,
-                .podr                           = (void __iomem *) MCFGPIO_PODR_TIMERL,
-                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_TIMERL,
-                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_TIMERL,
-                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_TIMERL,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "UARTL",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 88,
-                        .ngpio                  = 8,
-                },
-                .pddr                           = (void __iomem *) MCFGPIO_PDDR_UARTL,
-                .podr                           = (void __iomem *) MCFGPIO_PODR_UARTL,
-                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_UARTL,
-                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_UARTL,
-                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_UARTL,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "FEC1H",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 96,
-                        .ngpio                  = 8,
-                },
-                .pddr                           = (void __iomem *) MCFGPIO_PDDR_FEC1H,
-                .podr                           = (void __iomem *) MCFGPIO_PODR_FEC1H,
-                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_FEC1H,
-                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_FEC1H,
-                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_FEC1H,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "FEC1L",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 104,
-                        .ngpio                  = 8,
-                },
-                .pddr                           = (void __iomem *) MCFGPIO_PDDR_FEC1L,
-                .podr                           = (void __iomem *) MCFGPIO_PODR_FEC1L,
-                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_FEC1L,
-                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_FEC1L,
-                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_FEC1L,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "BS",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 114,
-                        .ngpio                  = 2,
-                },
-                .pddr                           = (void __iomem *) MCFGPIO_PDDR_BS,
-                .podr                           = (void __iomem *) MCFGPIO_PODR_BS,
-                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_BS,
-                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_BS,
-                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_BS,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "IRQ",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 121,
-                        .ngpio                  = 7,
-                },
-                .pddr                           = (void __iomem *) MCFGPIO_PDDR_IRQ,
-                .podr                           = (void __iomem *) MCFGPIO_PODR_IRQ,
-                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_IRQ,
-                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_IRQ,
-                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_IRQ,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "USBH",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 128,
-                        .ngpio                  = 1,
-                },
-                .pddr                           = (void __iomem *) MCFGPIO_PDDR_USBH,
-                .podr                           = (void __iomem *) MCFGPIO_PODR_USBH,
-                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_USBH,
-                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_USBH,
-                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_USBH,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "USBL",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 136,
-                        .ngpio                  = 8,
-                },
-                .pddr                           = (void __iomem *) MCFGPIO_PDDR_USBL,
-                .podr                           = (void __iomem *) MCFGPIO_PODR_USBL,
-                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_USBL,
-                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_USBL,
-                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_USBL,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "UARTH",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 144,
-                        .ngpio                  = 4,
-                },
-                .pddr                           = (void __iomem *) MCFGPIO_PDDR_UARTH,
-                .podr                           = (void __iomem *) MCFGPIO_PODR_UARTH,
-                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_UARTH,
-                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_UARTH,
-                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_UARTH,
-        },
-#endif
-};
-static int __init mcf_gpio_init(void)
-{
-        unsigned i = 0;
-        while (i < ARRAY_SIZE(mcf_gpio_chips))
-                (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
-        return 0;
-}
-core_initcall(mcf_gpio_init);
diff --git a/arch/m68k/platform/528x/Makefile b/arch/m68k/platform/528x/Makefile
deleted file mode 100644
index 6ac4b57370ea..000000000000
--- a/arch/m68k/platform/528x/Makefile
+++ /dev/null
@@ -1,18 +0,0 @@
-#
-# Makefile for the linux kernel.
-#
-#
-# If you want to play with the HW breakpoints then you will
-# need to add define this,  which will give you a stack backtrace
-# on the console port whenever a DBG interrupt occurs.  You have to
-# set up you HW breakpoints to trigger a DBG interrupt:
-#
-# ccflags-y := -DTRAP_DBG_INTERRUPT
-# asflags-y := -DTRAP_DBG_INTERRUPT
-#
-asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
-obj-y := config.o gpio.o
diff --git a/arch/m68k/platform/528x/gpio.c b/arch/m68k/platform/528x/gpio.c
deleted file mode 100644
index 526db665d87e..000000000000
--- a/arch/m68k/platform/528x/gpio.c
+++ /dev/null
@@ -1,438 +0,0 @@
-/*
- * Coldfire generic GPIO support
- *
- * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
-*/
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <asm/coldfire.h>
-#include <asm/mcfsim.h>
-#include <asm/mcfgpio.h>
-static struct mcf_gpio_chip mcf_gpio_chips[] = {
-        {
-                .gpio_chip                      = {
-                        .label                  = "NQ",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value,
-                        .base                   = 1,
-                        .ngpio                  = 7,
-                },
-                .pddr                           = (void __iomem *)MCFEPORT_EPDDR,
-                .podr                           = (void __iomem *)MCFEPORT_EPDR,
-                .ppdr                           = (void __iomem *)MCFEPORT_EPPDR,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "TA",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 8,
-                        .ngpio                  = 4,
-                },
-                .pddr                           = (void __iomem *)MCFGPTA_GPTDDR,
-                .podr                           = (void __iomem *)MCFGPTA_GPTPORT,
-                .ppdr                           = (void __iomem *)MCFGPTB_GPTPORT,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "TB",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 16,
-                        .ngpio                  = 4,
-                },
-                .pddr                           = (void __iomem *)MCFGPTB_GPTDDR,
-                .podr                           = (void __iomem *)MCFGPTB_GPTPORT,
-                .ppdr                           = (void __iomem *)MCFGPTB_GPTPORT,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "QA",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 24,
-                        .ngpio                  = 4,
-                },
-                .pddr                           = (void __iomem *)MCFQADC_DDRQA,
-                .podr                           = (void __iomem *)MCFQADC_PORTQA,
-                .ppdr                           = (void __iomem *)MCFQADC_PORTQA,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "QB",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 32,
-                        .ngpio                  = 4,
-                },
-                .pddr                           = (void __iomem *)MCFQADC_DDRQB,
-                .podr                           = (void __iomem *)MCFQADC_PORTQB,
-                .ppdr                           = (void __iomem *)MCFQADC_PORTQB,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "A",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 40,
-                        .ngpio                  = 8,
-                },
-                .pddr                           = (void __iomem *)MCFGPIO_DDRA,
-                .podr                           = (void __iomem *)MCFGPIO_PORTA,
-                .ppdr                           = (void __iomem *)MCFGPIO_PORTAP,
-                .setr                           = (void __iomem *)MCFGPIO_SETA,
-                .clrr                           = (void __iomem *)MCFGPIO_CLRA,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "B",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 48,
-                        .ngpio                  = 8,
-                },
-                .pddr                           = (void __iomem *)MCFGPIO_DDRB,
-                .podr                           = (void __iomem *)MCFGPIO_PORTB,
-                .ppdr                           = (void __iomem *)MCFGPIO_PORTBP,
-                .setr                           = (void __iomem *)MCFGPIO_SETB,
-                .clrr                           = (void __iomem *)MCFGPIO_CLRB,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "C",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 56,
-                        .ngpio                  = 8,
-                },
-                .pddr                           = (void __iomem *)MCFGPIO_DDRC,
-                .podr                           = (void __iomem *)MCFGPIO_PORTC,
-                .ppdr                           = (void __iomem *)MCFGPIO_PORTCP,
-                .setr                           = (void __iomem *)MCFGPIO_SETC,
-                .clrr                           = (void __iomem *)MCFGPIO_CLRC,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "D",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 64,
-                        .ngpio                  = 8,
-                },
-                .pddr                           = (void __iomem *)MCFGPIO_DDRD,
-                .podr                           = (void __iomem *)MCFGPIO_PORTD,
-                .ppdr                           = (void __iomem *)MCFGPIO_PORTDP,
-                .setr                           = (void __iomem *)MCFGPIO_SETD,
-                .clrr                           = (void __iomem *)MCFGPIO_CLRD,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "E",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 72,
-                        .ngpio                  = 8,
-                },
-                .pddr                           = (void __iomem *)MCFGPIO_DDRE,
-                .podr                           = (void __iomem *)MCFGPIO_PORTE,
-                .ppdr                           = (void __iomem *)MCFGPIO_PORTEP,
-                .setr                           = (void __iomem *)MCFGPIO_SETE,
-                .clrr                           = (void __iomem *)MCFGPIO_CLRE,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "F",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 80,
-                        .ngpio                  = 8,
-                },
-                .pddr                           = (void __iomem *)MCFGPIO_DDRF,
-                .podr                           = (void __iomem *)MCFGPIO_PORTF,
-                .ppdr                           = (void __iomem *)MCFGPIO_PORTFP,
-                .setr                           = (void __iomem *)MCFGPIO_SETF,
-                .clrr                           = (void __iomem *)MCFGPIO_CLRF,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "G",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 88,
-                        .ngpio                  = 8,
-                },
-                .pddr                           = (void __iomem *)MCFGPIO_DDRG,
-                .podr                           = (void __iomem *)MCFGPIO_PORTG,
-                .ppdr                           = (void __iomem *)MCFGPIO_PORTGP,
-                .setr                           = (void __iomem *)MCFGPIO_SETG,
-                .clrr                           = (void __iomem *)MCFGPIO_CLRG,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "H",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 96,
-                        .ngpio                  = 8,
-                },
-                .pddr                           = (void __iomem *)MCFGPIO_DDRH,
-                .podr                           = (void __iomem *)MCFGPIO_PORTH,
-                .ppdr                           = (void __iomem *)MCFGPIO_PORTHP,
-                .setr                           = (void __iomem *)MCFGPIO_SETH,
-                .clrr                           = (void __iomem *)MCFGPIO_CLRH,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "J",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 104,
-                        .ngpio                  = 8,
-                },
-                .pddr                           = (void __iomem *)MCFGPIO_DDRJ,
-                .podr                           = (void __iomem *)MCFGPIO_PORTJ,
-                .ppdr                           = (void __iomem *)MCFGPIO_PORTJP,
-                .setr                           = (void __iomem *)MCFGPIO_SETJ,
-                .clrr                           = (void __iomem *)MCFGPIO_CLRJ,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "DD",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 112,
-                        .ngpio                  = 8,
-                },
-                .pddr                           = (void __iomem *)MCFGPIO_DDRDD,
-                .podr                           = (void __iomem *)MCFGPIO_PORTDD,
-                .ppdr                           = (void __iomem *)MCFGPIO_PORTDDP,
-                .setr                           = (void __iomem *)MCFGPIO_SETDD,
-                .clrr                           = (void __iomem *)MCFGPIO_CLRDD,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "EH",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 120,
-                        .ngpio                  = 8,
-                },
-                .pddr                           = (void __iomem *)MCFGPIO_DDREH,
-                .podr                           = (void __iomem *)MCFGPIO_PORTEH,
-                .ppdr                           = (void __iomem *)MCFGPIO_PORTEHP,
-                .setr                           = (void __iomem *)MCFGPIO_SETEH,
-                .clrr                           = (void __iomem *)MCFGPIO_CLREH,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "EL",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 128,
-                        .ngpio                  = 8,
-                },
-                .pddr                           = (void __iomem *)MCFGPIO_DDREL,
-                .podr                           = (void __iomem *)MCFGPIO_PORTEL,
-                .ppdr                           = (void __iomem *)MCFGPIO_PORTELP,
-                .setr                           = (void __iomem *)MCFGPIO_SETEL,
-                .clrr                           = (void __iomem *)MCFGPIO_CLREL,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "AS",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 136,
-                        .ngpio                  = 6,
-                },
-                .pddr                           = (void __iomem *)MCFGPIO_DDRAS,
-                .podr                           = (void __iomem *)MCFGPIO_PORTAS,
-                .ppdr                           = (void __iomem *)MCFGPIO_PORTASP,
-                .setr                           = (void __iomem *)MCFGPIO_SETAS,
-                .clrr                           = (void __iomem *)MCFGPIO_CLRAS,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "QS",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 144,
-                        .ngpio                  = 7,
-                },
-                .pddr                           = (void __iomem *)MCFGPIO_DDRQS,
-                .podr                           = (void __iomem *)MCFGPIO_PORTQS,
-                .ppdr                           = (void __iomem *)MCFGPIO_PORTQSP,
-                .setr                           = (void __iomem *)MCFGPIO_SETQS,
-                .clrr                           = (void __iomem *)MCFGPIO_CLRQS,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "SD",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 152,
-                        .ngpio                  = 6,
-                },
-                .pddr                           = (void __iomem *)MCFGPIO_DDRSD,
-                .podr                           = (void __iomem *)MCFGPIO_PORTSD,
-                .ppdr                           = (void __iomem *)MCFGPIO_PORTSDP,
-                .setr                           = (void __iomem *)MCFGPIO_SETSD,
-                .clrr                           = (void __iomem *)MCFGPIO_CLRSD,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "TC",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 160,
-                        .ngpio                  = 4,
-                },
-                .pddr                           = (void __iomem *)MCFGPIO_DDRTC,
-                .podr                           = (void __iomem *)MCFGPIO_PORTTC,
-                .ppdr                           = (void __iomem *)MCFGPIO_PORTTCP,
-                .setr                           = (void __iomem *)MCFGPIO_SETTC,
-                .clrr                           = (void __iomem *)MCFGPIO_CLRTC,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "TD",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 168,
-                        .ngpio                  = 4,
-                },
-                .pddr                           = (void __iomem *)MCFGPIO_DDRTD,
-                .podr                           = (void __iomem *)MCFGPIO_PORTTD,
-                .ppdr                           = (void __iomem *)MCFGPIO_PORTTDP,
-                .setr                           = (void __iomem *)MCFGPIO_SETTD,
-                .clrr                           = (void __iomem *)MCFGPIO_CLRTD,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "UA",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 176,
-                        .ngpio                  = 4,
-                },
-                .pddr                           = (void __iomem *)MCFGPIO_DDRUA,
-                .podr                           = (void __iomem *)MCFGPIO_PORTUA,
-                .ppdr                           = (void __iomem *)MCFGPIO_PORTUAP,
-                .setr                           = (void __iomem *)MCFGPIO_SETUA,
-                .clrr                           = (void __iomem *)MCFGPIO_CLRUA,
-        },
-};
-static int __init mcf_gpio_init(void)
-{
-        unsigned i = 0;
-        while (i < ARRAY_SIZE(mcf_gpio_chips))
-                (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
-        return 0;
-}
-core_initcall(mcf_gpio_init);
diff --git a/arch/m68k/platform/5307/Makefile b/arch/m68k/platform/5307/Makefile
deleted file mode 100644
index d4293b791f2e..000000000000
--- a/arch/m68k/platform/5307/Makefile
+++ /dev/null
@@ -1,20 +0,0 @@
-#
-# Makefile for the m68knommu kernel.
-#
-#
-# If you want to play with the HW breakpoints then you will
-# need to add define this,  which will give you a stack backtrace
-# on the console port whenever a DBG interrupt occurs. You have to
-# set up you HW breakpoints to trigger a DBG interrupt:
-#
-# ccflags-y := -DTRAP_DBG_INTERRUPT
-# asflags-y := -DTRAP_DBG_INTERRUPT
-#
-asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
-obj-y                   += config.o gpio.o
-obj-$(CONFIG_NETtel)    += nettel.o
-obj-$(CONFIG_CLEOPATRA) += nettel.o
diff --git a/arch/m68k/platform/5307/gpio.c b/arch/m68k/platform/5307/gpio.c
deleted file mode 100644
index 5850612b4a38..000000000000
--- a/arch/m68k/platform/5307/gpio.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * Coldfire generic GPIO support
- *
- * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
-*/
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <asm/coldfire.h>
-#include <asm/mcfsim.h>
-#include <asm/mcfgpio.h>
-static struct mcf_gpio_chip mcf_gpio_chips[] = {
-        {
-                .gpio_chip                      = {
-                        .label                  = "PP",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value,
-                        .ngpio                  = 16,
-                },
-                .pddr                           = (void __iomem *) MCFSIM_PADDR,
-                .podr                           = (void __iomem *) MCFSIM_PADAT,
-                .ppdr                           = (void __iomem *) MCFSIM_PADAT,
-        },
-};
-static int __init mcf_gpio_init(void)
-{
-        unsigned i = 0;
-        while (i < ARRAY_SIZE(mcf_gpio_chips))
-                (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
-        return 0;
-}
-core_initcall(mcf_gpio_init);
diff --git a/arch/m68k/platform/532x/Makefile b/arch/m68k/platform/532x/Makefile
deleted file mode 100644
index ce01669399c6..000000000000
--- a/arch/m68k/platform/532x/Makefile
+++ /dev/null
@@ -1,18 +0,0 @@
-#
-# Makefile for the m68knommu linux kernel.
-#
-#
-# If you want to play with the HW breakpoints then you will
-# need to add define this,  which will give you a stack backtrace
-# on the console port whenever a DBG interrupt occurs. You have to
-# set up you HW breakpoints to trigger a DBG interrupt:
-#
-# ccflags-y := -DTRAP_DBG_INTERRUPT
-# asflags-y := -DTRAP_DBG_INTERRUPT
-#
-asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
-#obj-y := config.o usb-mcf532x.o spi-mcf532x.o
-obj-y := config.o gpio.o
diff --git a/arch/m68k/platform/532x/gpio.c b/arch/m68k/platform/532x/gpio.c
deleted file mode 100644
index 212a85deac90..000000000000
--- a/arch/m68k/platform/532x/gpio.c
+++ /dev/null
@@ -1,337 +0,0 @@
-/*
- * Coldfire generic GPIO support
- *
- * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
-*/
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <asm/coldfire.h>
-#include <asm/mcfsim.h>
-#include <asm/mcfgpio.h>
-static struct mcf_gpio_chip mcf_gpio_chips[] = {
-        {
-                .gpio_chip                      = {
-                        .label                  = "PIRQ",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value,
-                        .ngpio                  = 8,
-                },
-                .pddr                           = (void __iomem *) MCFEPORT_EPDDR,
-                .podr                           = (void __iomem *) MCFEPORT_EPDR,
-                .ppdr                           = (void __iomem *) MCFEPORT_EPPDR,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "FECH",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 8,
-                        .ngpio                  = 8,
-                },
-                .pddr                           = (void __iomem *) MCFGPIO_PDDR_FECH,
-                .podr                           = (void __iomem *) MCFGPIO_PODR_FECH,
-                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_FECH,
-                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_FECH,
-                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_FECH,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "FECL",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 16,
-                        .ngpio                  = 8,
-                },
-                .pddr                           = (void __iomem *) MCFGPIO_PDDR_FECL,
-                .podr                           = (void __iomem *) MCFGPIO_PODR_FECL,
-                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_FECL,
-                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_FECL,
-                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_FECL,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "SSI",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 24,
-                        .ngpio                  = 5,
-                },
-                .pddr                           = (void __iomem *) MCFGPIO_PDDR_SSI,
-                .podr                           = (void __iomem *) MCFGPIO_PODR_SSI,
-                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_SSI,
-                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_SSI,
-                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_SSI,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "BUSCTL",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 32,
-                        .ngpio                  = 4,
-                },
-                .pddr                           = (void __iomem *) MCFGPIO_PDDR_BUSCTL,
-                .podr                           = (void __iomem *) MCFGPIO_PODR_BUSCTL,
-                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
-                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL,
-                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_BUSCTL,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "BE",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 40,
-                        .ngpio                  = 4,
-                },
-                .pddr                           = (void __iomem *) MCFGPIO_PDDR_BE,
-                .podr                           = (void __iomem *) MCFGPIO_PODR_BE,
-                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_BE,
-                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_BE,
-                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_BE,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "CS",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 49,
-                        .ngpio                  = 5,
-                },
-                .pddr                           = (void __iomem *) MCFGPIO_PDDR_CS,
-                .podr                           = (void __iomem *) MCFGPIO_PODR_CS,
-                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_CS,
-                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_CS,
-                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_CS,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "PWM",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 58,
-                        .ngpio                  = 4,
-                },
-                .pddr                           = (void __iomem *) MCFGPIO_PDDR_PWM,
-                .podr                           = (void __iomem *) MCFGPIO_PODR_PWM,
-                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_PWM,
-                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_PWM,
-                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_PWM,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "FECI2C",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 64,
-                        .ngpio                  = 4,
-                },
-                .pddr                           = (void __iomem *) MCFGPIO_PDDR_FECI2C,
-                .podr                           = (void __iomem *) MCFGPIO_PODR_FECI2C,
-                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
-                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_FECI2C,
-                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_FECI2C,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "UART",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 72,
-                        .ngpio                  = 8,
-                },
-                .pddr                           = (void __iomem *) MCFGPIO_PDDR_UART,
-                .podr                           = (void __iomem *) MCFGPIO_PODR_UART,
-                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_UART,
-                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_UART,
-                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_UART,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "QSPI",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 80,
-                        .ngpio                  = 6,
-                },
-                .pddr                           = (void __iomem *) MCFGPIO_PDDR_QSPI,
-                .podr                           = (void __iomem *) MCFGPIO_PODR_QSPI,
-                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_QSPI,
-                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_QSPI,
-                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_QSPI,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "TIMER",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 88,
-                        .ngpio                  = 4,
-                },
-                .pddr                           = (void __iomem *) MCFGPIO_PDDR_TIMER,
-                .podr                           = (void __iomem *) MCFGPIO_PODR_TIMER,
-                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_TIMER,
-                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_TIMER,
-                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_TIMER,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "LCDDATAH",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 96,
-                        .ngpio                  = 2,
-                },
-                .pddr                           = (void __iomem *) MCFGPIO_PDDR_LCDDATAH,
-                .podr                           = (void __iomem *) MCFGPIO_PODR_LCDDATAH,
-                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_LCDDATAH,
-                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_LCDDATAH,
-                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_LCDDATAH,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "LCDDATAM",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 104,
-                        .ngpio                  = 8,
-                },
-                .pddr                           = (void __iomem *) MCFGPIO_PDDR_LCDDATAM,
-                .podr                           = (void __iomem *) MCFGPIO_PODR_LCDDATAM,
-                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_LCDDATAM,
-                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_LCDDATAM,
-                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_LCDDATAM,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "LCDDATAL",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 112,
-                        .ngpio                  = 8,
-                },
-                .pddr                           = (void __iomem *) MCFGPIO_PDDR_LCDDATAL,
-                .podr                           = (void __iomem *) MCFGPIO_PODR_LCDDATAL,
-                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_LCDDATAL,
-                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_LCDDATAL,
-                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_LCDDATAL,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "LCDCTLH",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 120,
-                        .ngpio                  = 1,
-                },
-                .pddr                           = (void __iomem *) MCFGPIO_PDDR_LCDCTLH,
-                .podr                           = (void __iomem *) MCFGPIO_PODR_LCDCTLH,
-                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_LCDCTLH,
-                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_LCDCTLH,
-                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_LCDCTLH,
-        },
-        {
-                .gpio_chip                      = {
-                        .label                  = "LCDCTLL",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value_fast,
-                        .base                   = 128,
-                        .ngpio                  = 8,
-                },
-                .pddr                           = (void __iomem *) MCFGPIO_PDDR_LCDCTLL,
-                .podr                           = (void __iomem *) MCFGPIO_PODR_LCDCTLL,
-                .ppdr                           = (void __iomem *) MCFGPIO_PPDSDR_LCDCTLL,
-                .setr                           = (void __iomem *) MCFGPIO_PPDSDR_LCDCTLL,
-                .clrr                           = (void __iomem *) MCFGPIO_PCLRR_LCDCTLL,
-        },
-};
-static int __init mcf_gpio_init(void)
-{
-        unsigned i = 0;
-        while (i < ARRAY_SIZE(mcf_gpio_chips))
-                (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
-        return 0;
-}
-core_initcall(mcf_gpio_init);
diff --git a/arch/m68k/platform/5407/Makefile b/arch/m68k/platform/5407/Makefile
deleted file mode 100644
index e83fe148eddc..000000000000
--- a/arch/m68k/platform/5407/Makefile
+++ /dev/null
@@ -1,18 +0,0 @@
-#
-# Makefile for the m68knommu linux kernel.
-#
-#
-# If you want to play with the HW breakpoints then you will
-# need to add define this,  which will give you a stack backtrace
-# on the console port whenever a DBG interrupt occurs. You have to
-# set up you HW breakpoints to trigger a DBG interrupt:
-#
-# ccflags-y := -DTRAP_DBG_INTERRUPT
-# asflags-y := -DTRAP_DBG_INTERRUPT
-#
-asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
-obj-y := config.o gpio.o
diff --git a/arch/m68k/platform/5407/gpio.c b/arch/m68k/platform/5407/gpio.c
deleted file mode 100644
index 5850612b4a38..000000000000
--- a/arch/m68k/platform/5407/gpio.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * Coldfire generic GPIO support
- *
- * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
-*/
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <asm/coldfire.h>
-#include <asm/mcfsim.h>
-#include <asm/mcfgpio.h>
-static struct mcf_gpio_chip mcf_gpio_chips[] = {
-        {
-                .gpio_chip                      = {
-                        .label                  = "PP",
-                        .request                = mcf_gpio_request,
-                        .free                   = mcf_gpio_free,
-                        .direction_input        = mcf_gpio_direction_input,
-                        .direction_output       = mcf_gpio_direction_output,
-                        .get                    = mcf_gpio_get_value,
-                        .set                    = mcf_gpio_set_value,
-                        .ngpio                  = 16,
-                },
-                .pddr                           = (void __iomem *) MCFSIM_PADDR,
-                .podr                           = (void __iomem *) MCFSIM_PADAT,
-                .ppdr                           = (void __iomem *) MCFSIM_PADAT,
-        },
-};
-static int __init mcf_gpio_init(void)
-{
-        unsigned i = 0;
-        while (i < ARRAY_SIZE(mcf_gpio_chips))
-                (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
-        return 0;
-}
-core_initcall(mcf_gpio_init);
diff --git a/arch/m68k/platform/54xx/Makefile b/arch/m68k/platform/54xx/Makefile
deleted file mode 100644
index 6cfd090ec3cd..000000000000
--- a/arch/m68k/platform/54xx/Makefile
+++ /dev/null
@@ -1,19 +0,0 @@
-#
-# Makefile for the m68knommu linux kernel.
-#
-#
-# If you want to play with the HW breakpoints then you will
-# need to add define this,  which will give you a stack backtrace
-# on the console port whenever a DBG interrupt occurs. You have to
-# set up you HW breakpoints to trigger a DBG interrupt:
-#
-# EXTRA_CFLAGS += -DTRAP_DBG_INTERRUPT
-# EXTRA_AFLAGS += -DTRAP_DBG_INTERRUPT
-#
-asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
-obj-y := config.o
-obj-$(CONFIG_FIREBEE) += firebee.o
diff --git a/arch/m68k/platform/68EZ328/Makefile b/arch/m68k/platform/68EZ328/Makefile
index ee97735a242c..b44d799b1115 100644
--- a/arch/m68k/platform/68EZ328/Makefile
+++ b/arch/m68k/platform/68EZ328/Makefile
@@ -3,9 +3,3 @@
 #
 obj-y := config.o
-extra-y := bootlogo.rh
-$(obj)/bootlogo.rh: $(src)/bootlogo.h
-        perl $(src)/../68328/bootlogo.pl < $(src)/bootlogo.h \
-                > $(obj)/bootlogo.rh
diff --git a/arch/m68k/platform/68VZ328/Makefile b/arch/m68k/platform/68VZ328/Makefile
index 447ffa0fd7c7..a49d75e65489 100644
--- a/arch/m68k/platform/68VZ328/Makefile
+++ b/arch/m68k/platform/68VZ328/Makefile
@@ -3,14 +3,9 @@
 #
 obj-y           := config.o
-logo-$(UCDIMM)  := bootlogo.rh
+extra-$(DRAGEN2):= screen.h
-logo-$(DRAGEN2) := screen.h
-extra-y         := $(logo-y)
-$(obj)/bootlogo.rh: $(src)/../68EZ328/bootlogo.h
-        perl $(src)/bootlogo.pl < $(src)/../68328/bootlogo.h > $(obj)/bootlogo.rh
 $(obj)/screen.h: $(src)/screen.xbm $(src)/xbm2lcd.pl
        perl $(src)/xbm2lcd.pl < $(src)/screen.xbm > $(obj)/screen.h
-clean-files := $(obj)/screen.h $(obj)/bootlogo.rh
+clean-files := $(obj)/screen.h
diff --git a/arch/m68k/platform/68EZ328/bootlogo.h b/arch/m68k/platform/68VZ328/bootlogo.h
index e842bdae5839..b38e2b255142 100644
--- a/arch/m68k/platform/68EZ328/bootlogo.h
+++ b/arch/m68k/platform/68VZ328/bootlogo.h
@@ -1,6 +1,6 @@
 #define splash_width 640
 #define splash_height 480
-static unsigned char splash_bits[] = {
+unsigned char __attribute__ ((aligned(16))) bootlogo_bits[] = {
  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
diff --git a/arch/m68k/platform/coldfire/Makefile b/arch/m68k/platform/coldfire/Makefile
index a0815c61dec1..76d389d9a84e 100644
--- a/arch/m68k/platform/coldfire/Makefile
+++ b/arch/m68k/platform/coldfire/Makefile
@@ -15,18 +15,22 @@
 asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
 obj-$(CONFIG_COLDFIRE)  += cache.o clk.o device.o dma.o entry.o vectors.o
-obj-$(CONFIG_M5206)     += timers.o intc.o reset.o
+obj-$(CONFIG_M5206)     += m5206.o timers.o intc.o reset.o
-obj-$(CONFIG_M5206e)    += timers.o intc.o reset.o
+obj-$(CONFIG_M5206e)    += m5206.o timers.o intc.o reset.o
-obj-$(CONFIG_M520x)     += pit.o intc-simr.o reset.o
+obj-$(CONFIG_M520x)     += m520x.o pit.o intc-simr.o reset.o
-obj-$(CONFIG_M523x)     += pit.o dma_timer.o intc-2.o reset.o
+obj-$(CONFIG_M523x)     += m523x.o pit.o dma_timer.o intc-2.o reset.o
-obj-$(CONFIG_M5249)     += timers.o intc.o reset.o
+obj-$(CONFIG_M5249)     += m5249.o timers.o intc.o intc-5249.o reset.o
-obj-$(CONFIG_M527x)     += pit.o intc-2.o reset.o
+obj-$(CONFIG_M527x)     += m527x.o pit.o intc-2.o reset.o
-obj-$(CONFIG_M5272)     += timers.o
+obj-$(CONFIG_M5272)     += m5272.o intc-5272.o timers.o
-obj-$(CONFIG_M528x)     += pit.o intc-2.o reset.o
+obj-$(CONFIG_M528x)     += m528x.o pit.o intc-2.o reset.o
-obj-$(CONFIG_M5307)     += timers.o intc.o reset.o
+obj-$(CONFIG_M5307)     += m5307.o timers.o intc.o reset.o
-obj-$(CONFIG_M532x)     += timers.o intc-simr.o reset.o
+obj-$(CONFIG_M532x)     += m532x.o timers.o intc-simr.o reset.o
-obj-$(CONFIG_M5407)     += timers.o intc.o reset.o
+obj-$(CONFIG_M5407)     += m5407.o timers.o intc.o reset.o
-obj-$(CONFIG_M54xx)     += sltimers.o intc-2.o
+obj-$(CONFIG_M54xx)     += m54xx.o sltimers.o intc-2.o
+obj-$(CONFIG_NETtel)    += nettel.o
+obj-$(CONFIG_CLEOPATRA) += nettel.o
+obj-$(CONFIG_FIREBEE)   += firebee.o
 obj-y                   += pinmux.o gpio.o
 extra-y := head.o
diff --git a/arch/m68k/platform/coldfire/device.c b/arch/m68k/platform/coldfire/device.c
index fa50c48292ff..3aa77ddea89d 100644
--- a/arch/m68k/platform/coldfire/device.c
+++ b/arch/m68k/platform/coldfire/device.c
@@ -114,14 +114,14 @@ static struct resource mcf_fec1_resources[] = {
 static struct platform_device mcf_fec1 = {
        .name                   = "fec",
-        .id                     = 0,
+        .id                     = 1,
        .num_resources          = ARRAY_SIZE(mcf_fec1_resources),
        .resource               = mcf_fec1_resources,
 };
 #endif /* MCFFEC_BASE1 */
 #endif /* CONFIG_FEC */
-#ifdef CONFIG_SPI_COLDFIRE_QSPI
+#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
 /*
 *      The ColdFire QSPI module is an SPI protocol hardware block used
 *      on a number of different ColdFire CPUs.
@@ -274,7 +274,7 @@ static struct platform_device mcf_qspi = {
        .resource               = mcf_qspi_resources,
        .dev.platform_data      = &mcf_qspi_data,
 };
-#endif /* CONFIG_SPI_COLDFIRE_QSPI */
+#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
 static struct platform_device *mcf_devices[] __initdata = {
        &mcf_uart,
@@ -284,7 +284,7 @@ static struct platform_device *mcf_devices[] __initdata = {
        &mcf_fec1,
 #endif
 #endif
-#ifdef CONFIG_SPI_COLDFIRE_QSPI
+#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
        &mcf_qspi,
 #endif
 };
diff --git a/arch/m68k/platform/54xx/firebee.c b/arch/m68k/platform/coldfire/firebee.c
index 46d50534f981..46d50534f981 100644
--- a/arch/m68k/platform/54xx/firebee.c
+++ b/arch/m68k/platform/coldfire/firebee.c
diff --git a/arch/m68k/platform/coldfire/gpio.c b/arch/m68k/platform/coldfire/gpio.c
index 292a1a5a2d7c..4c8c42450a4e 100644
--- a/arch/m68k/platform/coldfire/gpio.c
+++ b/arch/m68k/platform/coldfire/gpio.c
@@ -122,6 +122,10 @@ struct bus_type mcf_gpio_subsys = {
 static int __init mcf_gpio_sysinit(void)
 {
+        unsigned int i = 0;
+        while (i < mcf_gpio_chips_size)
+                gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
        return subsys_system_register(&mcf_gpio_subsys, NULL);
 }
diff --git a/arch/m68k/platform/5249/intc2.c b/arch/m68k/platform/coldfire/intc-5249.c
index f343bf7bf5b0..f343bf7bf5b0 100644
--- a/arch/m68k/platform/5249/intc2.c
+++ b/arch/m68k/platform/coldfire/intc-5249.c
diff --git a/arch/m68k/platform/5272/intc.c b/arch/m68k/platform/coldfire/intc-5272.c
index 7160e618b0a9..7160e618b0a9 100644
--- a/arch/m68k/platform/5272/intc.c
+++ b/arch/m68k/platform/coldfire/intc-5272.c
diff --git a/arch/m68k/platform/5206/config.c b/arch/m68k/platform/coldfire/m5206.c
index 6bfbeebd231b..a8b81df653f0 100644
--- a/arch/m68k/platform/5206/config.c
+++ b/arch/m68k/platform/coldfire/m5206.c
@@ -16,6 +16,15 @@
 #include <asm/machdep.h>
 #include <asm/coldfire.h>
 #include <asm/mcfsim.h>
+#include <asm/mcfgpio.h>
+/***************************************************************************/
+struct mcf_gpio_chip mcf_gpio_chips[] = {
+        MCFGPS(PP, 0, 8, MCFSIM_PADDR, MCFSIM_PADAT, MCFSIM_PADAT),
+};
+unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips);
 /***************************************************************************/
diff --git a/arch/m68k/platform/520x/config.c b/arch/m68k/platform/coldfire/m520x.c
index 235947844f27..3264b8883d5f 100644
--- a/arch/m68k/platform/520x/config.c
+++ b/arch/m68k/platform/coldfire/m520x.c
@@ -19,10 +19,26 @@
 #include <asm/coldfire.h>
 #include <asm/mcfsim.h>
 #include <asm/mcfuart.h>
+#include <asm/mcfgpio.h>
 /***************************************************************************/
-#ifdef CONFIG_SPI_COLDFIRE_QSPI
+struct mcf_gpio_chip mcf_gpio_chips[] = {
+        MCFGPS(PIRQ, 0, 8, MCFEPORT_EPDDR, MCFEPORT_EPDR, MCFEPORT_EPPDR),
+        MCFGPF(CS, 9, 3),
+        MCFGPF(FECI2C, 16, 4),
+        MCFGPF(QSPI, 24, 4),
+        MCFGPF(TIMER, 32, 4),
+        MCFGPF(UART, 40, 8),
+        MCFGPF(FECH, 48, 8),
+        MCFGPF(FECL, 56, 8),
+};
+unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips);
+/***************************************************************************/
+#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
 static void __init m520x_qspi_init(void)
 {
@@ -35,7 +51,7 @@ static void __init m520x_qspi_init(void)
        writew(par, MCF_GPIO_PAR_UART);
 }
-#endif /* CONFIG_SPI_COLDFIRE_QSPI */
+#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
 /***************************************************************************/
@@ -79,7 +95,7 @@ void __init config_BSP(char *commandp, int size)
        mach_sched_init = hw_timer_init;
        m520x_uarts_init();
        m520x_fec_init();
-#ifdef CONFIG_SPI_COLDFIRE_QSPI
+#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
        m520x_qspi_init();
 #endif
 }
diff --git a/arch/m68k/platform/523x/config.c b/arch/m68k/platform/coldfire/m523x.c
index c8b405d5a961..5d57a4249412 100644
--- a/arch/m68k/platform/523x/config.c
+++ b/arch/m68k/platform/coldfire/m523x.c
@@ -19,10 +19,32 @@
 #include <asm/machdep.h>
 #include <asm/coldfire.h>
 #include <asm/mcfsim.h>
+#include <asm/mcfgpio.h>
 /***************************************************************************/
-#ifdef CONFIG_SPI_COLDFIRE_QSPI
+struct mcf_gpio_chip mcf_gpio_chips[] = {
+        MCFGPS(PIRQ, 1, 7, MCFEPORT_EPDDR, MCFEPORT_EPDR, MCFEPORT_EPPDR),
+        MCFGPF(ADDR, 13, 3),
+        MCFGPF(DATAH, 16, 8),
+        MCFGPF(DATAL, 24, 8),
+        MCFGPF(BUSCTL, 32, 8),
+        MCFGPF(BS, 40, 4),
+        MCFGPF(CS, 49, 7),
+        MCFGPF(SDRAM, 56, 6),
+        MCFGPF(FECI2C, 64, 4),
+        MCFGPF(UARTH, 72, 2),
+        MCFGPF(UARTL, 80, 8),
+        MCFGPF(QSPI, 88, 5),
+        MCFGPF(TIMER, 96, 8),
+        MCFGPF(ETPU, 104, 3),
+};
+unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips);
+/***************************************************************************/
+#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
 static void __init m523x_qspi_init(void)
 {
@@ -36,7 +58,7 @@ static void __init m523x_qspi_init(void)
        writew(par, MCFGPIO_PAR_TIMER);
 }
-#endif /* CONFIG_SPI_COLDFIRE_QSPI */
+#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
 /***************************************************************************/
@@ -58,7 +80,7 @@ void __init config_BSP(char *commandp, int size)
 {
        mach_sched_init = hw_timer_init;
        m523x_fec_init();
-#ifdef CONFIG_SPI_COLDFIRE_QSPI
+#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
        m523x_qspi_init();
 #endif
 }
diff --git a/arch/m68k/platform/5249/config.c b/arch/m68k/platform/coldfire/m5249.c
index bbf05135bb98..fdfa1edfd1ac 100644
--- a/arch/m68k/platform/5249/config.c
+++ b/arch/m68k/platform/coldfire/m5249.c
@@ -16,6 +16,16 @@
 #include <asm/machdep.h>
 #include <asm/coldfire.h>
 #include <asm/mcfsim.h>
+#include <asm/mcfgpio.h>
+/***************************************************************************/
+struct mcf_gpio_chip mcf_gpio_chips[] = {
+        MCFGPS(GPIO0, 0, 32, MCFSIM2_GPIOENABLE, MCFSIM2_GPIOWRITE, MCFSIM2_GPIOREAD),
+        MCFGPS(GPIO1, 32, 32, MCFSIM2_GPIO1ENABLE, MCFSIM2_GPIO1WRITE, MCFSIM2_GPIO1READ),
+};
+unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips);
 /***************************************************************************/
@@ -51,7 +61,7 @@ static struct platform_device *m5249_devices[] __initdata = {
 /***************************************************************************/
-#ifdef CONFIG_SPI_COLDFIRE_QSPI
+#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
 static void __init m5249_qspi_init(void)
 {
@@ -61,7 +71,7 @@ static void __init m5249_qspi_init(void)
        mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI);
 }
-#endif /* CONFIG_SPI_COLDFIRE_QSPI */
+#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
 /***************************************************************************/
@@ -90,7 +100,7 @@ void __init config_BSP(char *commandp, int size)
 #ifdef CONFIG_M5249C3
        m5249_smc91x_init();
 #endif
-#ifdef CONFIG_SPI_COLDFIRE_QSPI
+#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
        m5249_qspi_init();
 #endif
 }
diff --git a/arch/m68k/platform/5272/config.c b/arch/m68k/platform/coldfire/m5272.c
index e68bc7a148eb..43e36060da18 100644
--- a/arch/m68k/platform/5272/config.c
+++ b/arch/m68k/platform/coldfire/m5272.c
@@ -19,6 +19,7 @@
 #include <asm/coldfire.h>
 #include <asm/mcfsim.h>
 #include <asm/mcfuart.h>
+#include <asm/mcfgpio.h>
 /***************************************************************************/
@@ -30,6 +31,16 @@ unsigned char ledbank = 0xff;
 /***************************************************************************/
+struct mcf_gpio_chip mcf_gpio_chips[] = {
+        MCFGPS(PA,  0, 16, MCFSIM_PADDR, MCFSIM_PADAT, MCFSIM_PADAT),
+        MCFGPS(PB, 16, 16, MCFSIM_PBDDR, MCFSIM_PBDAT, MCFSIM_PBDAT),
+        MCFGPS(Pc, 32, 16, MCFSIM_PCDDR, MCFSIM_PCDAT, MCFSIM_PCDAT),
+};
+unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips);
+/***************************************************************************/
 static void __init m5272_uarts_init(void)
 {
        u32 v;
diff --git a/arch/m68k/platform/527x/config.c b/arch/m68k/platform/coldfire/m527x.c
index 7ed848c3b848..9b0b66aabd1b 100644
--- a/arch/m68k/platform/527x/config.c
+++ b/arch/m68k/platform/coldfire/m527x.c
@@ -20,10 +20,53 @@
 #include <asm/coldfire.h>
 #include <asm/mcfsim.h>
 #include <asm/mcfuart.h>
+#include <asm/mcfgpio.h>
 /***************************************************************************/
-#ifdef CONFIG_SPI_COLDFIRE_QSPI
+struct mcf_gpio_chip mcf_gpio_chips[] = {
+#if defined(CONFIG_M5271)
+        MCFGPS(PIRQ, 1, 7, MCFEPORT_EPDDR, MCFEPORT_EPDR, MCFEPORT_EPPDR),
+        MCFGPF(ADDR, 13, 3),
+        MCFGPF(DATAH, 16, 8),
+        MCFGPF(DATAL, 24, 8),
+        MCFGPF(BUSCTL, 32, 8),
+        MCFGPF(BS, 40, 4),
+        MCFGPF(CS, 49, 7),
+        MCFGPF(SDRAM, 56, 6),
+        MCFGPF(FECI2C, 64, 4),
+        MCFGPF(UARTH, 72, 2),
+        MCFGPF(UARTL, 80, 8),
+        MCFGPF(QSPI, 88, 5),
+        MCFGPF(TIMER, 96, 8),
+#elif defined(CONFIG_M5275)
+        MCFGPS(PIRQ, 1, 7, MCFEPORT_EPDDR, MCFEPORT_EPDR, MCFEPORT_EPPDR),
+        MCFGPF(BUSCTL, 8, 8),
+        MCFGPF(ADDR, 21, 3),
+        MCFGPF(CS, 25, 7),
+        MCFGPF(FEC0H, 32, 8),
+        MCFGPF(FEC0L, 40, 8),
+        MCFGPF(FECI2C, 48, 6),
+        MCFGPF(QSPI, 56, 7),
+        MCFGPF(SDRAM, 64, 8),
+        MCFGPF(TIMERH, 72, 4),
+        MCFGPF(TIMERL, 80, 4),
+        MCFGPF(UARTL, 88, 8),
+        MCFGPF(FEC1H, 96, 8),
+        MCFGPF(FEC1L, 104, 8),
+        MCFGPF(BS, 114, 2),
+        MCFGPF(IRQ, 121, 7),
+        MCFGPF(USBH, 128, 1),
+        MCFGPF(USBL, 136, 8),
+        MCFGPF(UARTH, 144, 4),
+#endif
+};
+unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips);
+/***************************************************************************/
+#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
 static void __init m527x_qspi_init(void)
 {
@@ -42,7 +85,7 @@ static void __init m527x_qspi_init(void)
 #endif
 }
-#endif /* CONFIG_SPI_COLDFIRE_QSPI */
+#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
 /***************************************************************************/
@@ -74,9 +117,7 @@ static void __init m527x_fec_init(void)
        writew(par | 0xf00, MCF_IPSBAR + 0x100082);
        v = readb(MCF_IPSBAR + 0x100078);
        writeb(v | 0xc0, MCF_IPSBAR + 0x100078);
-#endif
-#ifdef CONFIG_FEC2
        /* Set multi-function pins to ethernet mode for fec1 */
        par = readw(MCF_IPSBAR + 0x100082);
        writew(par | 0xa0, MCF_IPSBAR + 0x100082);
@@ -92,7 +133,7 @@ void __init config_BSP(char *commandp, int size)
        mach_sched_init = hw_timer_init;
        m527x_uarts_init();
        m527x_fec_init();
-#ifdef CONFIG_SPI_COLDFIRE_QSPI
+#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
        m527x_qspi_init();
 #endif
 }
diff --git a/arch/m68k/platform/528x/config.c b/arch/m68k/platform/coldfire/m528x.c
index d4492926614c..7ed1276b29dc 100644
--- a/arch/m68k/platform/528x/config.c
+++ b/arch/m68k/platform/coldfire/m528x.c
@@ -21,10 +21,41 @@
 #include <asm/coldfire.h>
 #include <asm/mcfsim.h>
 #include <asm/mcfuart.h>
+#include <asm/mcfgpio.h>
 /***************************************************************************/
-#ifdef CONFIG_SPI_COLDFIRE_QSPI
+struct mcf_gpio_chip mcf_gpio_chips[] = {
+        MCFGPS(NQ, 1, 7, MCFEPORT_EPDDR, MCFEPORT_EPDR, MCFEPORT_EPPDR),
+        MCFGPS(TA, 8, 4, MCFGPTA_GPTDDR, MCFGPTA_GPTPORT, MCFGPTB_GPTPORT),
+        MCFGPS(TB, 16, 4, MCFGPTB_GPTDDR, MCFGPTB_GPTPORT, MCFGPTB_GPTPORT),
+        MCFGPS(QA, 24, 4, MCFQADC_DDRQA, MCFQADC_PORTQA, MCFQADC_PORTQA),
+        MCFGPS(QB, 32, 4, MCFQADC_DDRQB, MCFQADC_PORTQB, MCFQADC_PORTQB),
+        MCFGPF(A, 40, 8),
+        MCFGPF(B, 48, 8),
+        MCFGPF(C, 56, 8),
+        MCFGPF(D, 64, 8),
+        MCFGPF(E, 72, 8),
+        MCFGPF(F, 80, 8),
+        MCFGPF(G, 88, 8),
+        MCFGPF(H, 96, 8),
+        MCFGPF(J, 104, 8),
+        MCFGPF(DD, 112, 8),
+        MCFGPF(EH, 120, 8),
+        MCFGPF(EL, 128, 8),
+        MCFGPF(AS, 136, 6),
+        MCFGPF(QS, 144, 7),
+        MCFGPF(SD, 152, 6),
+        MCFGPF(TC, 160, 4),
+        MCFGPF(TD, 168, 4),
+        MCFGPF(UA, 176, 4),
+};
+unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips);
+/***************************************************************************/
+#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
 static void __init m528x_qspi_init(void)
 {
@@ -32,7 +63,7 @@ static void __init m528x_qspi_init(void)
        __raw_writeb(0x07, MCFGPIO_PQSPAR);
 }
-#endif /* CONFIG_SPI_COLDFIRE_QSPI */
+#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
 /***************************************************************************/
@@ -98,7 +129,7 @@ void __init config_BSP(char *commandp, int size)
        mach_sched_init = hw_timer_init;
        m528x_uarts_init();
        m528x_fec_init();
-#ifdef CONFIG_SPI_COLDFIRE_QSPI
+#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
        m528x_qspi_init();
 #endif
 }
diff --git a/arch/m68k/platform/5307/config.c b/arch/m68k/platform/coldfire/m5307.c
index a568d2870d15..93b484976ab3 100644
--- a/arch/m68k/platform/5307/config.c
+++ b/arch/m68k/platform/coldfire/m5307.c
@@ -16,6 +16,7 @@
 #include <asm/machdep.h>
 #include <asm/coldfire.h>
 #include <asm/mcfsim.h>
+#include <asm/mcfgpio.h>
 #include <asm/mcfwdebug.h>
 /***************************************************************************/
@@ -28,6 +29,14 @@ unsigned char ledbank = 0xff;
 /***************************************************************************/
+struct mcf_gpio_chip mcf_gpio_chips[] = {
+        MCFGPS(PP, 0, 16, MCFSIM_PADDR, MCFSIM_PADAT, MCFSIM_PADAT),
+};
+unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips);
+/***************************************************************************/
 void __init config_BSP(char *commandp, int size)
 {
 #if defined(CONFIG_NETtel) || \
diff --git a/arch/m68k/platform/532x/config.c b/arch/m68k/platform/coldfire/m532x.c
index db8707f5e037..5394223639f8 100644
--- a/arch/m68k/platform/532x/config.c
+++ b/arch/m68k/platform/coldfire/m532x.c
@@ -26,11 +26,36 @@
 #include <asm/mcfsim.h>
 #include <asm/mcfuart.h>
 #include <asm/mcfdma.h>
+#include <asm/mcfgpio.h>
 #include <asm/mcfwdebug.h>
 /***************************************************************************/
-#ifdef CONFIG_SPI_COLDFIRE_QSPI
+struct mcf_gpio_chip mcf_gpio_chips[] = {
+        MCFGPS(PIRQ, 0, 8, MCFEPORT_EPDDR, MCFEPORT_EPDR, MCFEPORT_EPPDR),
+        MCFGPF(FECH, 8, 8),
+        MCFGPF(FECL, 16, 8),
+        MCFGPF(SSI, 24, 5),
+        MCFGPF(BUSCTL, 32, 4),
+        MCFGPF(BE, 40, 4),
+        MCFGPF(CS, 49, 5),
+        MCFGPF(PWM, 58, 4),
+        MCFGPF(FECI2C, 64, 4),
+        MCFGPF(UART, 72, 8),
+        MCFGPF(QSPI, 80, 6),
+        MCFGPF(TIMER, 88, 4),
+        MCFGPF(LCDDATAH, 96, 2),
+        MCFGPF(LCDDATAM, 104, 8),
+        MCFGPF(LCDDATAL, 112, 8),
+        MCFGPF(LCDCTLH, 120, 1),
+        MCFGPF(LCDCTLL, 128, 8),
+};
+unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips);
+/***************************************************************************/
+#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
 static void __init m532x_qspi_init(void)
 {
@@ -38,7 +63,7 @@ static void __init m532x_qspi_init(void)
        writew(0x01f0, MCF_GPIO_PAR_QSPI);
 }
-#endif /* CONFIG_SPI_COLDFIRE_QSPI */
+#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
 /***************************************************************************/
@@ -77,7 +102,7 @@ void __init config_BSP(char *commandp, int size)
        mach_sched_init = hw_timer_init;
        m532x_uarts_init();
        m532x_fec_init();
-#ifdef CONFIG_SPI_COLDFIRE_QSPI
+#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
        m532x_qspi_init();
 #endif
diff --git a/arch/m68k/platform/5407/config.c b/arch/m68k/platform/coldfire/m5407.c
index bb6c746ae819..faa6680b3404 100644
--- a/arch/m68k/platform/5407/config.c
+++ b/arch/m68k/platform/coldfire/m5407.c
@@ -16,6 +16,15 @@
 #include <asm/machdep.h>
 #include <asm/coldfire.h>
 #include <asm/mcfsim.h>
+#include <asm/mcfgpio.h>
+/***************************************************************************/
+struct mcf_gpio_chip mcf_gpio_chips[] = {
+        MCFGPS(PP, 0, 16, MCFSIM_PADDR, MCFSIM_PADAT, MCFSIM_PADAT),
+};
+unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips);
 /***************************************************************************/
diff --git a/arch/m68k/platform/54xx/config.c b/arch/m68k/platform/coldfire/m54xx.c
index 2081c6cbb3de..20672dadb252 100644
--- a/arch/m68k/platform/54xx/config.c
+++ b/arch/m68k/platform/coldfire/m54xx.c
@@ -21,12 +21,19 @@
 #include <asm/m54xxsim.h>
 #include <asm/mcfuart.h>
 #include <asm/m54xxgpt.h>
+#include <asm/mcfgpio.h>
 #ifdef CONFIG_MMU
 #include <asm/mmu_context.h>
 #endif
 /***************************************************************************/
+struct mcf_gpio_chip mcf_gpio_chips[] = { };
+unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips);
+/***************************************************************************/
 static void __init m54xx_uarts_init(void)
 {
        /* enable io pins */
diff --git a/arch/m68k/platform/5307/nettel.c b/arch/m68k/platform/coldfire/nettel.c
index e925ea4602f8..e925ea4602f8 100644
--- a/arch/m68k/platform/5307/nettel.c
+++ b/arch/m68k/platform/coldfire/nettel.c
diff --git a/arch/microblaze/kernel/Makefile b/arch/microblaze/kernel/Makefile
index 494b63b72dd7..928c950fc14c 100644
--- a/arch/microblaze/kernel/Makefile
+++ b/arch/microblaze/kernel/Makefile
@@ -16,7 +16,7 @@ endif
 extra-y := head.o vmlinux.lds
 obj-y += dma.o exceptions.o \
-        hw_exception_handler.o init_task.o intc.o irq.o \
+        hw_exception_handler.o intc.o irq.o \
        process.o prom.o prom_parse.o ptrace.o \
        reset.o setup.o signal.o sys_microblaze.o timer.o traps.o unwind.o
diff --git a/arch/microblaze/kernel/init_task.c b/arch/microblaze/kernel/init_task.c
deleted file mode 100644
index b5d711f94ff8..000000000000
--- a/arch/microblaze/kernel/init_task.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * Copyright (C) 2009 Michal Simek <monstr@monstr.eu>
- * Copyright (C) 2009 PetaLogix
- * Copyright (C) 2006 Atmark Techno, Inc.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#include <linux/module.h>
-#include <linux/sched.h>
-#include <linux/init_task.h>
-#include <linux/fs.h>
-#include <linux/mqueue.h>
-#include <asm/pgtable.h>
-static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
-static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
-union thread_union init_thread_union __init_task_data =
-        { INIT_THREAD_INFO(init_task) };
-struct task_struct init_task = INIT_TASK(init_task);
-EXPORT_SYMBOL(init_task);
diff --git a/arch/microblaze/kernel/ptrace.c b/arch/microblaze/kernel/ptrace.c
index 6eb2aa927d89..ab1b9db661f3 100644
--- a/arch/microblaze/kernel/ptrace.c
+++ b/arch/microblaze/kernel/ptrace.c
@@ -136,7 +136,7 @@ asmlinkage long do_syscall_trace_enter(struct pt_regs *regs)
 {
        long ret = 0;
-        secure_computing(regs->r12);
+        secure_computing_strict(regs->r12);
        if (test_thread_flag(TIF_SYSCALL_TRACE) &&
            tracehook_report_syscall_entry(regs))
diff --git a/arch/microblaze/pci/pci-common.c b/arch/microblaze/pci/pci-common.c
index d10403dadd2b..ed22bfc5db14 100644
--- a/arch/microblaze/pci/pci-common.c
+++ b/arch/microblaze/pci/pci-common.c
@@ -1422,6 +1422,7 @@ int pcibios_enable_device(struct pci_dev *dev, int mask)
 static void __devinit pcibios_setup_phb_resources(struct pci_controller *hose, struct list_head *resources)
 {
+        unsigned long io_offset;
        struct resource *res;
        int i;
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 923a6c3b9a0a..f5e121213c22 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -29,6 +29,7 @@ config MIPS
        select HAVE_MEMBLOCK
        select HAVE_MEMBLOCK_NODE_MAP
        select ARCH_DISCARD_MEMBLOCK
+        select GENERIC_SMP_IDLE_THREAD
 menu "Machine selection"
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 4fedf5a51d96..76017c25a9e6 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -235,7 +235,7 @@ endif
 OBJCOPYFLAGS            += --remove-section=.reginfo
-head-y := arch/mips/kernel/head.o arch/mips/kernel/init_task.o
+head-y := arch/mips/kernel/head.o
 libs-y                  += arch/mips/lib/
diff --git a/arch/mips/ath79/dev-wmac.c b/arch/mips/ath79/dev-wmac.c
index e21507052066..9c717bf98ffe 100644
--- a/arch/mips/ath79/dev-wmac.c
+++ b/arch/mips/ath79/dev-wmac.c
@@ -58,8 +58,8 @@ static void __init ar913x_wmac_setup(void)
 static int ar933x_wmac_reset(void)
 {
-        ath79_device_reset_clear(AR933X_RESET_WMAC);
        ath79_device_reset_set(AR933X_RESET_WMAC);
+        ath79_device_reset_clear(AR933X_RESET_WMAC);
        return 0;
 }
diff --git a/arch/mips/configs/mtx1_defconfig b/arch/mips/configs/mtx1_defconfig
index 807c97eed8a8..46c61edcdf7b 100644
--- a/arch/mips/configs/mtx1_defconfig
+++ b/arch/mips/configs/mtx1_defconfig
@@ -346,11 +346,8 @@ CONFIG_CHELSIO_T1=m
 CONFIG_IXGB=m
 CONFIG_S2IO=m
 CONFIG_MYRI10GE=m
-CONFIG_TR=y
 CONFIG_IBMOL=m
 CONFIG_IBMLS=m
-CONFIG_3C359=m
-CONFIG_TMS380TR=m
 CONFIG_TMSPCI=m
 CONFIG_ABYSS=m
 CONFIG_USB_CATC=m
@@ -376,7 +373,6 @@ CONFIG_PCMCIA_SMC91C92=m
 CONFIG_PCMCIA_XIRC2PS=m
 CONFIG_PCMCIA_AXNET=m
 CONFIG_ARCNET_COM20020_CS=m
-CONFIG_PCMCIA_IBMTR=m
 CONFIG_WAN=y
 CONFIG_LANMEDIA=m
 CONFIG_HDLC=m
diff --git a/arch/mips/include/asm/mach-ip27/topology.h b/arch/mips/include/asm/mach-ip27/topology.h
index 1b1a7d1632b9..b2cf641f206f 100644
--- a/arch/mips/include/asm/mach-ip27/topology.h
+++ b/arch/mips/include/asm/mach-ip27/topology.h
@@ -36,23 +36,6 @@ extern unsigned char __node_distances[MAX_COMPACT_NODES][MAX_COMPACT_NODES];
 #define node_distance(from, to) (__node_distances[(from)][(to)])
-/* sched_domains SD_NODE_INIT for SGI IP27 machines */
-#define SD_NODE_INIT (struct sched_domain) {            \
-        .parent                 = NULL,                 \
-        .child                  = NULL,                 \
-        .groups                 = NULL,                 \
-        .min_interval           = 8,                    \
-        .max_interval           = 32,                   \
-        .busy_factor            = 32,                   \
-        .imbalance_pct          = 125,                  \
-        .cache_nice_tries       = 1,                    \
-        .flags                  = SD_LOAD_BALANCE |     \
-                                  SD_BALANCE_EXEC,      \
-        .last_balance           = jiffies,              \
-        .balance_interval       = 1,                    \
-        .nr_balance_failed      = 0,                    \
-}
 #include <asm-generic/topology.h>
 #endif /* _ASM_MACH_TOPOLOGY_H */
diff --git a/arch/mips/include/asm/mach-jz4740/irq.h b/arch/mips/include/asm/mach-jz4740/irq.h
index a865c983c70a..5ad1a9c113c6 100644
--- a/arch/mips/include/asm/mach-jz4740/irq.h
+++ b/arch/mips/include/asm/mach-jz4740/irq.h
@@ -45,7 +45,7 @@
 #define JZ4740_IRQ_LCD          JZ4740_IRQ(30)
 /* 2nd-level interrupts */
-#define JZ4740_IRQ_DMA(x)       (JZ4740_IRQ(32) + (X))
+#define JZ4740_IRQ_DMA(x)       (JZ4740_IRQ(32) + (x))
 #define JZ4740_IRQ_INTC_GPIO(x) (JZ4740_IRQ_GPIO0 - (x))
 #define JZ4740_IRQ_GPIO(x)      (JZ4740_IRQ(48) + (x))
diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h
index 73c0d45798de..9b02cfba7449 100644
--- a/arch/mips/include/asm/mmu_context.h
+++ b/arch/mips/include/asm/mmu_context.h
@@ -37,12 +37,6 @@ extern void tlbmiss_handler_setup_pgd(unsigned long pgd);
                write_c0_xcontext((unsigned long) smp_processor_id() << 51); \
        } while (0)
-static inline unsigned long get_current_pgd(void)
-{
-        return PHYS_TO_XKSEG_CACHED((read_c0_context() >> 11) & ~0xfffUL);
-}
 #else /* CONFIG_MIPS_PGD_C0_CONTEXT: using  pgd_current*/
 /*
diff --git a/arch/mips/include/asm/thread_info.h b/arch/mips/include/asm/thread_info.h
index 0d85d8e440c5..e2eca7d10598 100644
--- a/arch/mips/include/asm/thread_info.h
+++ b/arch/mips/include/asm/thread_info.h
@@ -85,18 +85,6 @@ register struct thread_info *__current_thread_info __asm__("$28");
 #define STACK_WARN      (THREAD_SIZE / 8)
-#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR
-#ifdef CONFIG_DEBUG_STACK_USAGE
-#define alloc_thread_info_node(tsk, node) \
-                kzalloc_node(THREAD_SIZE, GFP_KERNEL, node)
-#else
-#define alloc_thread_info_node(tsk, node) \
-                kmalloc_node(THREAD_SIZE, GFP_KERNEL, node)
-#endif
-#define free_thread_info(info) kfree(info)
 #endif /* !__ASSEMBLY__ */
 #define PREEMPT_ACTIVE          0x10000000
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index 0c6877ea9004..fdaf65e1a99d 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -2,7 +2,7 @@
 # Makefile for the Linux/MIPS kernel.
 #
-extra-y         := head.o init_task.o vmlinux.lds
+extra-y         := head.o vmlinux.lds
 obj-y           += cpu-probe.o branch.o entry.o genex.o irq.o process.o \
                   ptrace.o reset.o setup.o signal.o syscall.o \
diff --git a/arch/mips/kernel/init_task.c b/arch/mips/kernel/init_task.c
deleted file mode 100644
index 5f9a76263c9a..000000000000
--- a/arch/mips/kernel/init_task.c
+++ /dev/null
@@ -1,35 +0,0 @@
-#include <linux/mm.h>
-#include <linux/export.h>
-#include <linux/sched.h>
-#include <linux/init_task.h>
-#include <linux/fs.h>
-#include <linux/mqueue.h>
-#include <asm/thread_info.h>
-#include <asm/uaccess.h>
-#include <asm/pgtable.h>
-static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
-static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
-/*
- * Initial thread structure.
- *
- * We need to make sure that this is 8192-byte aligned due to the
- * way process stacks are handled. This is done by making sure
- * the linker maps this in the .text segment right after head.S,
- * and making head.S ensure the proper alignment.
- *
- * The things we do for performance..
- */
-union thread_union init_thread_union __init_task_data
-        __attribute__((__aligned__(THREAD_SIZE))) =
-                { INIT_THREAD_INFO(init_task) };
-/*
- * Initial task structure.
- *
- * All other task structs will be allocated on slabs in fork.c
- */
-struct task_struct init_task = INIT_TASK(init_task);
-EXPORT_SYMBOL(init_task);
diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c
index 811084f4e422..ab73fa2fb9b5 100644
--- a/arch/mips/kernel/perf_event_mipsxx.c
+++ b/arch/mips/kernel/perf_event_mipsxx.c
@@ -1325,7 +1325,7 @@ static int mipsxx_pmu_handle_shared_irq(void)
        regs = get_irq_regs();
-        perf_sample_data_init(&data, 0);
+        perf_sample_data_init(&data, 0, 0);
        switch (counters) {
 #define HANDLE_COUNTER(n)                                               \
diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c
index 7c24c2973c6d..4812c6d916e4 100644
--- a/arch/mips/kernel/ptrace.c
+++ b/arch/mips/kernel/ptrace.c
@@ -535,7 +535,7 @@ static inline int audit_arch(void)
 asmlinkage void syscall_trace_enter(struct pt_regs *regs)
 {
        /* do the secure computing check first */
-        secure_computing(regs->regs[2]);
+        secure_computing_strict(regs->regs[2]);
        if (!(current->ptrace & PT_PTRACED))
                goto out;
diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c
index 185ca00c4c84..d5a338a1739c 100644
--- a/arch/mips/kernel/signal.c
+++ b/arch/mips/kernel/signal.c
@@ -257,11 +257,8 @@ asmlinkage int sys_sigsuspend(nabi_no_regargs struct pt_regs regs)
                return -EFAULT;
        sigdelsetmask(&newset, ~_BLOCKABLE);
-        spin_lock_irq(&current->sighand->siglock);
        current->saved_sigmask = current->blocked;
-        current->blocked = newset;
+        set_current_blocked(&newset);
-        recalc_sigpending();
-        spin_unlock_irq(&current->sighand->siglock);
        current->state = TASK_INTERRUPTIBLE;
        schedule();
@@ -286,11 +283,8 @@ asmlinkage int sys_rt_sigsuspend(nabi_no_regargs struct pt_regs regs)
                return -EFAULT;
        sigdelsetmask(&newset, ~_BLOCKABLE);
-        spin_lock_irq(&current->sighand->siglock);
        current->saved_sigmask = current->blocked;
-        current->blocked = newset;
+        set_current_blocked(&newset);
-        recalc_sigpending();
-        spin_unlock_irq(&current->sighand->siglock);
        current->state = TASK_INTERRUPTIBLE;
        schedule();
@@ -362,10 +356,7 @@ asmlinkage void sys_sigreturn(nabi_no_regargs struct pt_regs regs)
                goto badframe;
        sigdelsetmask(&blocked, ~_BLOCKABLE);
-        spin_lock_irq(&current->sighand->siglock);
+        set_current_blocked(&blocked);
-        current->blocked = blocked;
-        recalc_sigpending();
-        spin_unlock_irq(&current->sighand->siglock);
        sig = restore_sigcontext(&regs, &frame->sf_sc);
        if (sig < 0)
@@ -401,10 +392,7 @@ asmlinkage void sys_rt_sigreturn(nabi_no_regargs struct pt_regs regs)
                goto badframe;
        sigdelsetmask(&set, ~_BLOCKABLE);
-        spin_lock_irq(&current->sighand->siglock);
+        set_current_blocked(&set);
-        current->blocked = set;
-        recalc_sigpending();
-        spin_unlock_irq(&current->sighand->siglock);
        sig = restore_sigcontext(&regs, &frame->rs_uc.uc_mcontext);
        if (sig < 0)
@@ -580,12 +568,7 @@ static int handle_signal(unsigned long sig, siginfo_t *info,
        if (ret)
                return ret;
-        spin_lock_irq(&current->sighand->siglock);
+        block_sigmask(ka, sig);
-        sigorsets(&current->blocked, &current->blocked, &ka->sa.sa_mask);
-        if (!(ka->sa.sa_flags & SA_NODEFER))
-                sigaddset(&current->blocked, sig);
-        recalc_sigpending();
-        spin_unlock_irq(&current->sighand->siglock);
        return ret;
 }
diff --git a/arch/mips/kernel/signal32.c b/arch/mips/kernel/signal32.c
index 06b5da392e24..ac3b8d89aae5 100644
--- a/arch/mips/kernel/signal32.c
+++ b/arch/mips/kernel/signal32.c
@@ -290,11 +290,8 @@ asmlinkage int sys32_sigsuspend(nabi_no_regargs struct pt_regs regs)
                return -EFAULT;
        sigdelsetmask(&newset, ~_BLOCKABLE);
-        spin_lock_irq(&current->sighand->siglock);
        current->saved_sigmask = current->blocked;
-        current->blocked = newset;
+        set_current_blocked(&newset);
-        recalc_sigpending();
-        spin_unlock_irq(&current->sighand->siglock);
        current->state = TASK_INTERRUPTIBLE;
        schedule();
@@ -318,11 +315,8 @@ asmlinkage int sys32_rt_sigsuspend(nabi_no_regargs struct pt_regs regs)
                return -EFAULT;
        sigdelsetmask(&newset, ~_BLOCKABLE);
-        spin_lock_irq(&current->sighand->siglock);
        current->saved_sigmask = current->blocked;
-        current->blocked = newset;
+        set_current_blocked(&newset);
-        recalc_sigpending();
-        spin_unlock_irq(&current->sighand->siglock);
        current->state = TASK_INTERRUPTIBLE;
        schedule();
@@ -488,10 +482,7 @@ asmlinkage void sys32_sigreturn(nabi_no_regargs struct pt_regs regs)
                goto badframe;
        sigdelsetmask(&blocked, ~_BLOCKABLE);
-        spin_lock_irq(&current->sighand->siglock);
+        set_current_blocked(&blocked);
-        current->blocked = blocked;
-        recalc_sigpending();
-        spin_unlock_irq(&current->sighand->siglock);
        sig = restore_sigcontext32(&regs, &frame->sf_sc);
        if (sig < 0)
@@ -529,10 +520,7 @@ asmlinkage void sys32_rt_sigreturn(nabi_no_regargs struct pt_regs regs)
                goto badframe;
        sigdelsetmask(&set, ~_BLOCKABLE);
-        spin_lock_irq(&current->sighand->siglock);
+        set_current_blocked(&set);
-        current->blocked = set;
-        recalc_sigpending();
-        spin_unlock_irq(&current->sighand->siglock);
        sig = restore_sigcontext32(&regs, &frame->rs_uc.uc_mcontext);
        if (sig < 0)
diff --git a/arch/mips/kernel/signal_n32.c b/arch/mips/kernel/signal_n32.c
index ae29e894ab8d..86eb4b04631c 100644
--- a/arch/mips/kernel/signal_n32.c
+++ b/arch/mips/kernel/signal_n32.c
@@ -93,11 +93,8 @@ asmlinkage int sysn32_rt_sigsuspend(nabi_no_regargs struct pt_regs regs)
        sigset_from_compat(&newset, &uset);
        sigdelsetmask(&newset, ~_BLOCKABLE);
-        spin_lock_irq(&current->sighand->siglock);
        current->saved_sigmask = current->blocked;
-        current->blocked = newset;
+        set_current_blocked(&newset);
-        recalc_sigpending();
-        spin_unlock_irq(&current->sighand->siglock);
        current->state = TASK_INTERRUPTIBLE;
        schedule();
@@ -121,10 +118,7 @@ asmlinkage void sysn32_rt_sigreturn(nabi_no_regargs struct pt_regs regs)
                goto badframe;
        sigdelsetmask(&set, ~_BLOCKABLE);
-        spin_lock_irq(&current->sighand->siglock);
+        set_current_blocked(&set);
-        current->blocked = set;
-        recalc_sigpending();
-        spin_unlock_irq(&current->sighand->siglock);
        sig = restore_sigcontext(&regs, &frame->rs_uc.uc_mcontext);
        if (sig < 0)
diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c
index ba9376bf52a1..71a95f55a649 100644
--- a/arch/mips/kernel/smp.c
+++ b/arch/mips/kernel/smp.c
@@ -186,61 +186,9 @@ void __devinit smp_prepare_boot_cpu(void)
        cpu_set(0, cpu_callin_map);
 }
-/*
+int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *tidle)
- * Called once for each "cpu_possible(cpu)".  Needs to spin up the cpu
- * and keep control until "cpu_online(cpu)" is set.  Note: cpu is
- * physical, not logical.
- */
-static struct task_struct *cpu_idle_thread[NR_CPUS];
-struct create_idle {
-        struct work_struct work;
-        struct task_struct *idle;
-        struct completion done;
-        int cpu;
-};
-static void __cpuinit do_fork_idle(struct work_struct *work)
-{
-        struct create_idle *c_idle =
-                container_of(work, struct create_idle, work);
-        c_idle->idle = fork_idle(c_idle->cpu);
-        complete(&c_idle->done);
-}
-int __cpuinit __cpu_up(unsigned int cpu)
 {
-        struct task_struct *idle;
+        mp_ops->boot_secondary(cpu, tidle);
-        /*
-         * Processor goes to start_secondary(), sets online flag
-         * The following code is purely to make sure
-         * Linux can schedule processes on this slave.
-         */
-        if (!cpu_idle_thread[cpu]) {
-                /*
-                 * Schedule work item to avoid forking user task
-                 * Ported from arch/x86/kernel/smpboot.c
-                 */
-                struct create_idle c_idle = {
-                        .cpu    = cpu,
-                        .done   = COMPLETION_INITIALIZER_ONSTACK(c_idle.done),
-                };
-                INIT_WORK_ONSTACK(&c_idle.work, do_fork_idle);
-                schedule_work(&c_idle.work);
-                wait_for_completion(&c_idle.done);
-                idle = cpu_idle_thread[cpu] = c_idle.idle;
-                if (IS_ERR(idle))
-                        panic(KERN_ERR "Fork failed for CPU %d", cpu);
-        } else {
-                idle = cpu_idle_thread[cpu];
-                init_idle(idle, cpu);
-        }
-        mp_ops->boot_secondary(cpu, idle);
        /*
         * Trust is futile.  We should really have timeouts ...
diff --git a/arch/mn10300/Makefile b/arch/mn10300/Makefile
index 7120282bf0d8..33188b6e81e4 100644
--- a/arch/mn10300/Makefile
+++ b/arch/mn10300/Makefile
@@ -51,7 +51,7 @@ UNIT		:= asb2364
 endif
-head-y          := arch/mn10300/kernel/head.o arch/mn10300/kernel/init_task.o
+head-y          := arch/mn10300/kernel/head.o
 core-y          += arch/mn10300/kernel/ arch/mn10300/mm/
diff --git a/arch/mn10300/include/asm/thread_info.h b/arch/mn10300/include/asm/thread_info.h
index 28cf52100baa..08251d6f6b11 100644
--- a/arch/mn10300/include/asm/thread_info.h
+++ b/arch/mn10300/include/asm/thread_info.h
@@ -20,8 +20,10 @@
 #ifdef CONFIG_4KSTACKS
 #define THREAD_SIZE             (4096)
+#define THREAD_SIZE_ORDER       (0)
 #else
 #define THREAD_SIZE             (8192)
+#define THREAD_SIZE_ORDER       (1)
 #endif
 #define STACK_WARN              (THREAD_SIZE / 8)
@@ -120,21 +122,8 @@ static inline unsigned long current_stack_pointer(void)
        return sp;
 }
-#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR
-/* thread information allocation */
-#ifdef CONFIG_DEBUG_STACK_USAGE
-#define alloc_thread_info_node(tsk, node)                       \
-                kzalloc_node(THREAD_SIZE, GFP_KERNEL, node)
-#else
-#define alloc_thread_info_node(tsk, node)                       \
-                kmalloc_node(THREAD_SIZE, GFP_KERNEL, node)
-#endif
 #ifndef CONFIG_KGDB
-#define free_thread_info(ti)    kfree((ti))
+void arch_release_thread_info(struct thread_info *ti)
-#else
-extern void free_thread_info(struct thread_info *);
 #endif
 #define get_thread_info(ti)     get_task_struct((ti)->task)
 #define put_thread_info(ti)     put_task_struct((ti)->task)
diff --git a/arch/mn10300/kernel/Makefile b/arch/mn10300/kernel/Makefile
index 47ed30fe8178..d06749173d63 100644
--- a/arch/mn10300/kernel/Makefile
+++ b/arch/mn10300/kernel/Makefile
@@ -1,7 +1,7 @@
 #
 # Makefile for the MN10300-specific core kernel code
 #
-extra-y := head.o init_task.o vmlinux.lds
+extra-y := head.o vmlinux.lds
 fpu-obj-y := fpu-nofpu.o fpu-nofpu-low.o
 fpu-obj-$(CONFIG_FPU) := fpu.o fpu-low.o
diff --git a/arch/mn10300/kernel/init_task.c b/arch/mn10300/kernel/init_task.c
deleted file mode 100644
index a481b043bea7..000000000000
--- a/arch/mn10300/kernel/init_task.c
+++ /dev/null
@@ -1,39 +0,0 @@
-/* MN10300 Initial task definitions
- *
- * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/sched.h>
-#include <linux/init.h>
-#include <linux/init_task.h>
-#include <linux/fs.h>
-#include <linux/mqueue.h>
-#include <asm/uaccess.h>
-#include <asm/pgtable.h>
-static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
-static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
-/*
- * Initial thread structure.
- *
- * We need to make sure that this is THREAD_SIZE aligned due to the
- * way process stacks are handled. This is done by having a special
- * "init_task" linker map entry..
- */
-union thread_union init_thread_union __init_task_data =
-        { INIT_THREAD_INFO(init_task) };
-/*
- * Initial task structure.
- *
- * All other task structs will be allocated on slabs in fork.c
- */
-struct task_struct init_task = INIT_TASK(init_task);
-EXPORT_SYMBOL(init_task);
diff --git a/arch/mn10300/kernel/kgdb.c b/arch/mn10300/kernel/kgdb.c
index f6c981db2a36..99770823451a 100644
--- a/arch/mn10300/kernel/kgdb.c
+++ b/arch/mn10300/kernel/kgdb.c
@@ -397,7 +397,7 @@ static bool kgdb_arch_undo_singlestep(struct pt_regs *regs)
 * single-step state is cleared.  At this point the breakpoints should have
 * been removed by __switch_to().
 */
-void free_thread_info(struct thread_info *ti)
+void arch_release_thread_info(struct thread_info *ti)
 {
        if (kgdb_sstep_thread == ti) {
                kgdb_sstep_thread = NULL;
@@ -407,7 +407,6 @@ void free_thread_info(struct thread_info *ti)
                 * so force immediate reentry */
                kgdb_breakpoint();
        }
-        kfree(ti);
 }
 /*
diff --git a/arch/mn10300/kernel/smp.c b/arch/mn10300/kernel/smp.c
index 910dddf65e44..090d35d36973 100644
--- a/arch/mn10300/kernel/smp.c
+++ b/arch/mn10300/kernel/smp.c
@@ -24,6 +24,7 @@
 #include <linux/sched.h>
 #include <linux/profile.h>
 #include <linux/smp.h>
+#include <linux/cpu.h>
 #include <asm/tlbflush.h>
 #include <asm/bitops.h>
 #include <asm/processor.h>
@@ -38,7 +39,6 @@
 #include "internal.h"
 #ifdef CONFIG_HOTPLUG_CPU
-#include <linux/cpu.h>
 #include <asm/cacheflush.h>
 static unsigned long sleep_mode[NR_CPUS];
@@ -874,10 +874,13 @@ static void __init smp_online(void)
        cpu = smp_processor_id();
-        local_irq_enable();
+        notify_cpu_starting(cpu);
+        ipi_call_lock();
        set_cpu_online(cpu, true);
-        smp_wmb();
+        ipi_call_unlock();
+        local_irq_enable();
 }
 /**
@@ -921,7 +924,7 @@ void initialize_secondary(void)
 * __cpu_up - Set smp_commenced_mask for the nominated CPU
 * @cpu: The target CPU.
 */
-int __devinit __cpu_up(unsigned int cpu)
+int __devinit __cpu_up(unsigned int cpu, struct task_struct *tidle)
 {
        int timeout;
diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig
index 66dff2046987..297bd38f7c5d 100644
--- a/arch/openrisc/Kconfig
+++ b/arch/openrisc/Kconfig
@@ -7,6 +7,7 @@ config OPENRISC
        def_bool y
        select OF
        select OF_EARLY_FLATTREE
+        select IRQ_DOMAIN
        select HAVE_MEMBLOCK
        select ARCH_WANT_OPTIONAL_GPIOLIB
        select HAVE_ARCH_TRACEHOOK
diff --git a/arch/openrisc/Makefile b/arch/openrisc/Makefile
index 158ae4c0dc6c..966886c8daf5 100644
--- a/arch/openrisc/Makefile
+++ b/arch/openrisc/Makefile
@@ -38,7 +38,7 @@ else
        KBUILD_CFLAGS += $(call cc-option,-msoft-div)
 endif
-head-y          := arch/openrisc/kernel/head.o arch/openrisc/kernel/init_task.o
+head-y          := arch/openrisc/kernel/head.o
 core-y          += arch/openrisc/lib/ \
                   arch/openrisc/kernel/ \
diff --git a/arch/openrisc/include/asm/Kbuild b/arch/openrisc/include/asm/Kbuild
index dcea5a0308ae..c936483bc8e2 100644
--- a/arch/openrisc/include/asm/Kbuild
+++ b/arch/openrisc/include/asm/Kbuild
@@ -1,6 +1,7 @@
 include include/asm-generic/Kbuild.asm
-header-y += spr_defs.h
+header-y += elf.h
+header-y += ucontext.h
 generic-y += atomic.h
 generic-y += auxvec.h
diff --git a/arch/openrisc/include/asm/dma-mapping.h b/arch/openrisc/include/asm/dma-mapping.h
index b206ba4608b2..fab8628e1b6e 100644
--- a/arch/openrisc/include/asm/dma-mapping.h
+++ b/arch/openrisc/include/asm/dma-mapping.h
@@ -20,150 +20,71 @@
 /*
 * See Documentation/DMA-API-HOWTO.txt and
 * Documentation/DMA-API.txt for documentation.
- *
- * This file is written with the intention of eventually moving over
- * to largely using asm-generic/dma-mapping-common.h in its place.
 */
 #include <linux/dma-debug.h>
 #include <asm-generic/dma-coherent.h>
 #include <linux/kmemcheck.h>
+#include <linux/dma-mapping.h>
 #define DMA_ERROR_CODE          (~(dma_addr_t)0x0)
+extern struct dma_map_ops or1k_dma_map_ops;
-#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
+static inline struct dma_map_ops *get_dma_ops(struct device *dev)
-#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
-void *or1k_dma_alloc_coherent(struct device *dev, size_t size,
-                              dma_addr_t *dma_handle, gfp_t flag);
-void or1k_dma_free_coherent(struct device *dev, size_t size, void *vaddr,
-                            dma_addr_t dma_handle);
-dma_addr_t or1k_map_page(struct device *dev, struct page *page,
-                         unsigned long offset, size_t size,
-                         enum dma_data_direction dir,
-                         struct dma_attrs *attrs);
-void or1k_unmap_page(struct device *dev, dma_addr_t dma_handle,
-                     size_t size, enum dma_data_direction dir,
-                     struct dma_attrs *attrs);
-int or1k_map_sg(struct device *dev, struct scatterlist *sg,
-                int nents, enum dma_data_direction dir,
-                struct dma_attrs *attrs);
-void or1k_unmap_sg(struct device *dev, struct scatterlist *sg,
-                   int nents, enum dma_data_direction dir,
-                   struct dma_attrs *attrs);
-void or1k_sync_single_for_cpu(struct device *dev,
-                              dma_addr_t dma_handle, size_t size,
-                              enum dma_data_direction dir);
-void or1k_sync_single_for_device(struct device *dev,
-                                 dma_addr_t dma_handle, size_t size,
-                                 enum dma_data_direction dir);
-static inline void *dma_alloc_coherent(struct device *dev, size_t size,
-                                        dma_addr_t *dma_handle, gfp_t flag)
 {
-        void *memory;
+        return &or1k_dma_map_ops;
-        memory = or1k_dma_alloc_coherent(dev, size, dma_handle, flag);
-        debug_dma_alloc_coherent(dev, size, *dma_handle, memory);
-        return memory;
 }
-static inline void dma_free_coherent(struct device *dev, size_t size,
+#include <asm-generic/dma-mapping-common.h>
-                                     void *cpu_addr, dma_addr_t dma_handle)
-{
-        debug_dma_free_coherent(dev, size, cpu_addr, dma_handle);
-        or1k_dma_free_coherent(dev, size, cpu_addr, dma_handle);
-}
-static inline dma_addr_t dma_map_single(struct device *dev, void *ptr,
+#define dma_alloc_coherent(d,s,h,f) dma_alloc_attrs(d,s,h,f,NULL) 
-                                        size_t size,
-                                        enum dma_data_direction dir)
-{
-        dma_addr_t addr;
-        kmemcheck_mark_initialized(ptr, size);
-        BUG_ON(!valid_dma_direction(dir));
-        addr = or1k_map_page(dev, virt_to_page(ptr),
-                             (unsigned long)ptr & ~PAGE_MASK, size,
-                             dir, NULL);
-        debug_dma_map_page(dev, virt_to_page(ptr),
-                           (unsigned long)ptr & ~PAGE_MASK, size,
-                           dir, addr, true);
-        return addr;
-}
-static inline void dma_unmap_single(struct device *dev, dma_addr_t addr,
+static inline void *dma_alloc_attrs(struct device *dev, size_t size,
-                                          size_t size,
+                                    dma_addr_t *dma_handle, gfp_t gfp,
-                                          enum dma_data_direction dir)
+                                    struct dma_attrs *attrs)
 {
-        BUG_ON(!valid_dma_direction(dir));
+        struct dma_map_ops *ops = get_dma_ops(dev);
-        or1k_unmap_page(dev, addr, size, dir, NULL);
+        void *memory;
-        debug_dma_unmap_page(dev, addr, size, dir, true);
-}
-static inline int dma_map_sg(struct device *dev, struct scatterlist *sg,
+        memory = ops->alloc(dev, size, dma_handle, gfp, attrs);
-                                   int nents, enum dma_data_direction dir)
-{
-        int i, ents;
-        struct scatterlist *s;
-        for_each_sg(sg, s, nents, i)
+        debug_dma_alloc_coherent(dev, size, *dma_handle, memory);
-                kmemcheck_mark_initialized(sg_virt(s), s->length);
-        BUG_ON(!valid_dma_direction(dir));
-        ents = or1k_map_sg(dev, sg, nents, dir, NULL);
-        debug_dma_map_sg(dev, sg, nents, ents, dir);
-        return ents;
+        return memory;
 }
-static inline void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
+#define dma_free_coherent(d,s,c,h) dma_free_attrs(d,s,c,h,NULL)
-                                      int nents, enum dma_data_direction dir)
-{
-        BUG_ON(!valid_dma_direction(dir));
-        debug_dma_unmap_sg(dev, sg, nents, dir);
-        or1k_unmap_sg(dev, sg, nents, dir, NULL);
-}
-static inline dma_addr_t dma_map_page(struct device *dev, struct page *page,
+static inline void dma_free_attrs(struct device *dev, size_t size,
-                                      size_t offset, size_t size,
+                                  void *cpu_addr, dma_addr_t dma_handle,
-                                      enum dma_data_direction dir)
+                                  struct dma_attrs *attrs)
 {
-        dma_addr_t addr;
+        struct dma_map_ops *ops = get_dma_ops(dev);
-        kmemcheck_mark_initialized(page_address(page) + offset, size);
+        debug_dma_free_coherent(dev, size, cpu_addr, dma_handle);
-        BUG_ON(!valid_dma_direction(dir));
-        addr = or1k_map_page(dev, page, offset, size, dir, NULL);
-        debug_dma_map_page(dev, page, offset, size, dir, addr, false);
-        return addr;
+        ops->free(dev, size, cpu_addr, dma_handle, attrs);
 }
-static inline void dma_unmap_page(struct device *dev, dma_addr_t addr,
+static inline void *dma_alloc_noncoherent(struct device *dev, size_t size,
-                                  size_t size, enum dma_data_direction dir)
+                                          dma_addr_t *dma_handle, gfp_t gfp)
 {
-        BUG_ON(!valid_dma_direction(dir));
+        struct dma_attrs attrs;
-        or1k_unmap_page(dev, addr, size, dir, NULL);
-        debug_dma_unmap_page(dev, addr, size, dir, true);
-}
-static inline void dma_sync_single_for_cpu(struct device *dev, dma_addr_t addr,
+        dma_set_attr(DMA_ATTR_NON_CONSISTENT, &attrs);
-                                           size_t size,
-                                           enum dma_data_direction dir)
+        return dma_alloc_attrs(dev, size, dma_handle, gfp, &attrs);
-{
-        BUG_ON(!valid_dma_direction(dir));
-        or1k_sync_single_for_cpu(dev, addr, size, dir);
-        debug_dma_sync_single_for_cpu(dev, addr, size, dir);
 }
-static inline void dma_sync_single_for_device(struct device *dev,
+static inline void dma_free_noncoherent(struct device *dev, size_t size,
-                                              dma_addr_t addr, size_t size,
+                                         void *cpu_addr, dma_addr_t dma_handle)
-                                              enum dma_data_direction dir)
 {
-        BUG_ON(!valid_dma_direction(dir));
+        struct dma_attrs attrs;
-        or1k_sync_single_for_device(dev, addr, size, dir);
-        debug_dma_sync_single_for_device(dev, addr, size, dir);
+        dma_set_attr(DMA_ATTR_NON_CONSISTENT, &attrs);
+        dma_free_attrs(dev, size, cpu_addr, dma_handle, &attrs);
 }
 static inline int dma_supported(struct device *dev, u64 dma_mask)
diff --git a/arch/openrisc/include/asm/elf.h b/arch/openrisc/include/asm/elf.h
index 2ce603bbfdd3..a8fe2c513070 100644
--- a/arch/openrisc/include/asm/elf.h
+++ b/arch/openrisc/include/asm/elf.h
@@ -20,11 +20,17 @@
 #define __ASM_OPENRISC_ELF_H
 /*
+ * This files is partially exported to userspace.  This allows us to keep
+ * the ELF bits in one place which should assist in keeping the kernel and
+ * userspace in sync.
+ */
+/*
 * ELF register definitions..
 */
-#include <linux/types.h>
-#include <linux/ptrace.h>
+/* for struct user_regs_struct definition */
+#include <asm/ptrace.h>
 /* The OR1K relocation types... not all relevant for module loader */
 #define R_OR32_NONE     0
@@ -62,6 +68,8 @@ typedef unsigned long elf_fpregset_t;
 #ifdef __KERNEL__
+#include <linux/types.h>
 /*
 * This is used to ensure we don't load something for the wrong architecture.
 */
diff --git a/arch/openrisc/include/asm/ptrace.h b/arch/openrisc/include/asm/ptrace.h
index 4651a737591d..8555c0c3d4d7 100644
--- a/arch/openrisc/include/asm/ptrace.h
+++ b/arch/openrisc/include/asm/ptrace.h
@@ -19,8 +19,6 @@
 #ifndef __ASM_OPENRISC_PTRACE_H
 #define __ASM_OPENRISC_PTRACE_H
-#include <asm/spr_defs.h>
 #ifndef __ASSEMBLY__
 /*
 * This is the layout of the regset returned by the GETREGSET ptrace call
@@ -30,13 +28,13 @@ struct user_regs_struct {
        unsigned long gpr[32];
        unsigned long pc;
        unsigned long sr;
-        unsigned long pad1;
-        unsigned long pad2;
 };
 #endif
 #ifdef __KERNEL__
+#include <asm/spr_defs.h>
 /*
 * Make kernel PTrace/register structures opaque to userspace... userspace can
 * access thread state via the regset mechanism.  This allows us a bit of
diff --git a/arch/openrisc/kernel/Makefile b/arch/openrisc/kernel/Makefile
index 9a4c2706d795..e1ee0fa2bbda 100644
--- a/arch/openrisc/kernel/Makefile
+++ b/arch/openrisc/kernel/Makefile
@@ -2,7 +2,7 @@
 # Makefile for the linux kernel.
 #
-extra-y := head.o vmlinux.lds init_task.o
+extra-y := head.o vmlinux.lds
 obj-y   := setup.o idle.o or32_ksyms.o process.o dma.o \
           traps.o time.o irq.o entry.o ptrace.o signal.o sys_or32.o \
diff --git a/arch/openrisc/kernel/dma.c b/arch/openrisc/kernel/dma.c
index f1c8ee2895d0..0b77ddb1ee07 100644
--- a/arch/openrisc/kernel/dma.c
+++ b/arch/openrisc/kernel/dma.c
@@ -21,13 +21,16 @@
 #include <linux/dma-mapping.h>
 #include <linux/dma-debug.h>
+#include <linux/export.h>
+#include <linux/dma-attrs.h>
 #include <asm/cpuinfo.h>
 #include <asm/spr_defs.h>
 #include <asm/tlbflush.h>
-static int page_set_nocache(pte_t *pte, unsigned long addr,
+static int
-                            unsigned long next, struct mm_walk *walk)
+page_set_nocache(pte_t *pte, unsigned long addr,
+                 unsigned long next, struct mm_walk *walk)
 {
        unsigned long cl;
@@ -46,8 +49,9 @@ static int page_set_nocache(pte_t *pte, unsigned long addr,
        return 0;
 }
-static int page_clear_nocache(pte_t *pte, unsigned long addr,
+static int
-                              unsigned long next, struct mm_walk *walk)
+page_clear_nocache(pte_t *pte, unsigned long addr,
+                   unsigned long next, struct mm_walk *walk)
 {
        pte_val(*pte) &= ~_PAGE_CI;
@@ -67,9 +71,19 @@ static int page_clear_nocache(pte_t *pte, unsigned long addr,
 * cache-inhibit bit on those pages, and makes sure that the pages are
 * flushed out of the cache before they are used.
 *
+ * If the NON_CONSISTENT attribute is set, then this function just
+ * returns "normal", cachable memory.
+ *
+ * There are additional flags WEAK_ORDERING and WRITE_COMBINE to take
+ * into consideration here, too.  All current known implementations of
+ * the OR1K support only strongly ordered memory accesses, so that flag
+ * is being ignored for now; uncached but write-combined memory is a
+ * missing feature of the OR1K.
 */
-void *or1k_dma_alloc_coherent(struct device *dev, size_t size,
+static void *
-                              dma_addr_t *dma_handle, gfp_t gfp)
+or1k_dma_alloc(struct device *dev, size_t size,
+               dma_addr_t *dma_handle, gfp_t gfp,
+               struct dma_attrs *attrs)
 {
        unsigned long va;
        void *page;
@@ -87,20 +101,23 @@ void *or1k_dma_alloc_coherent(struct device *dev, size_t size,
        va = (unsigned long)page;
-        /*
+        if (!dma_get_attr(DMA_ATTR_NON_CONSISTENT, attrs)) {
-         * We need to iterate through the pages, clearing the dcache for
+                /*
-         * them and setting the cache-inhibit bit.
+                 * We need to iterate through the pages, clearing the dcache for
-         */
+                 * them and setting the cache-inhibit bit.
-        if (walk_page_range(va, va + size, &walk)) {
+                 */
-                free_pages_exact(page, size);
+                if (walk_page_range(va, va + size, &walk)) {
-                return NULL;
+                        free_pages_exact(page, size);
+                        return NULL;
+                }
        }
        return (void *)va;
 }
-void or1k_dma_free_coherent(struct device *dev, size_t size, void *vaddr,
+static void
-                            dma_addr_t dma_handle)
+or1k_dma_free(struct device *dev, size_t size, void *vaddr,
+              dma_addr_t dma_handle, struct dma_attrs *attrs)
 {
        unsigned long va = (unsigned long)vaddr;
        struct mm_walk walk = {
@@ -108,16 +125,19 @@ void or1k_dma_free_coherent(struct device *dev, size_t size, void *vaddr,
                .mm = &init_mm
        };
-        /* walk_page_range shouldn't be able to fail here */
+        if (!dma_get_attr(DMA_ATTR_NON_CONSISTENT, attrs)) {
-        WARN_ON(walk_page_range(va, va + size, &walk));
+                /* walk_page_range shouldn't be able to fail here */
+                WARN_ON(walk_page_range(va, va + size, &walk));
+        }
        free_pages_exact(vaddr, size);
 }
-dma_addr_t or1k_map_page(struct device *dev, struct page *page,
+static dma_addr_t
-                         unsigned long offset, size_t size,
+or1k_map_page(struct device *dev, struct page *page,
-                         enum dma_data_direction dir,
+              unsigned long offset, size_t size,
-                         struct dma_attrs *attrs)
+              enum dma_data_direction dir,
+              struct dma_attrs *attrs)
 {
        unsigned long cl;
        dma_addr_t addr = page_to_phys(page) + offset;
@@ -147,16 +167,18 @@ dma_addr_t or1k_map_page(struct device *dev, struct page *page,
        return addr;
 }
-void or1k_unmap_page(struct device *dev, dma_addr_t dma_handle,
+static void
-                     size_t size, enum dma_data_direction dir,
+or1k_unmap_page(struct device *dev, dma_addr_t dma_handle,
-                     struct dma_attrs *attrs)
+                size_t size, enum dma_data_direction dir,
+                struct dma_attrs *attrs)
 {
        /* Nothing special to do here... */
 }
-int or1k_map_sg(struct device *dev, struct scatterlist *sg,
+static int
-                int nents, enum dma_data_direction dir,
+or1k_map_sg(struct device *dev, struct scatterlist *sg,
-                struct dma_attrs *attrs)
+            int nents, enum dma_data_direction dir,
+            struct dma_attrs *attrs)
 {
        struct scatterlist *s;
        int i;
@@ -169,9 +191,10 @@ int or1k_map_sg(struct device *dev, struct scatterlist *sg,
        return nents;
 }
-void or1k_unmap_sg(struct device *dev, struct scatterlist *sg,
+static void
-                   int nents, enum dma_data_direction dir,
+or1k_unmap_sg(struct device *dev, struct scatterlist *sg,
-                   struct dma_attrs *attrs)
+              int nents, enum dma_data_direction dir,
+              struct dma_attrs *attrs)
 {
        struct scatterlist *s;
        int i;
@@ -181,9 +204,10 @@ void or1k_unmap_sg(struct device *dev, struct scatterlist *sg,
        }
 }
-void or1k_sync_single_for_cpu(struct device *dev,
+static void
-                              dma_addr_t dma_handle, size_t size,
+or1k_sync_single_for_cpu(struct device *dev,
-                              enum dma_data_direction dir)
+                         dma_addr_t dma_handle, size_t size,
+                         enum dma_data_direction dir)
 {
        unsigned long cl;
        dma_addr_t addr = dma_handle;
@@ -193,9 +217,10 @@ void or1k_sync_single_for_cpu(struct device *dev,
                mtspr(SPR_DCBIR, cl);
 }
-void or1k_sync_single_for_device(struct device *dev,
+static void
-                                 dma_addr_t dma_handle, size_t size,
+or1k_sync_single_for_device(struct device *dev,
-                                 enum dma_data_direction dir)
+                            dma_addr_t dma_handle, size_t size,
+                            enum dma_data_direction dir)
 {
        unsigned long cl;
        dma_addr_t addr = dma_handle;
@@ -205,6 +230,18 @@ void or1k_sync_single_for_device(struct device *dev,
                mtspr(SPR_DCBFR, cl);
 }
+struct dma_map_ops or1k_dma_map_ops = {
+        .alloc = or1k_dma_alloc,
+        .free = or1k_dma_free,
+        .map_page = or1k_map_page,
+        .unmap_page = or1k_unmap_page,
+        .map_sg = or1k_map_sg,
+        .unmap_sg = or1k_unmap_sg,
+        .sync_single_for_cpu = or1k_sync_single_for_cpu,
+        .sync_single_for_device = or1k_sync_single_for_device,
+};
+EXPORT_SYMBOL(or1k_dma_map_ops);
 /* Number of entries preallocated for DMA-API debugging */
 #define PREALLOC_DMA_DEBUG_ENTRIES (1 << 16)
diff --git a/arch/openrisc/kernel/entry.S b/arch/openrisc/kernel/entry.S
index 6e61af8682b8..ddfcaa828b0e 100644
--- a/arch/openrisc/kernel/entry.S
+++ b/arch/openrisc/kernel/entry.S
@@ -1117,10 +1117,10 @@ ENTRY(sys_rt_sigreturn)
 ENTRY(sys_or1k_atomic)
        /* FIXME: This ignores r3 and always does an XCHG */
        DISABLE_INTERRUPTS(r17,r19)
-        l.lwz   r30,0(r4)
+        l.lwz   r29,0(r4)
-        l.lwz   r28,0(r5)
+        l.lwz   r27,0(r5)
-        l.sw    0(r4),r28
+        l.sw    0(r4),r27
-        l.sw    0(r5),r30
+        l.sw    0(r5),r29
        ENABLE_INTERRUPTS(r17)
        l.jr    r9
         l.or   r11,r0,r0
diff --git a/arch/openrisc/kernel/init_task.c b/arch/openrisc/kernel/init_task.c
deleted file mode 100644
index ca534082d5f3..000000000000
--- a/arch/openrisc/kernel/init_task.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * OpenRISC init_task.c
- *
- * Linux architectural port borrowing liberally from similar works of
- * others.  All original copyrights apply as per the original source
- * declaration.
- *
- * Modifications for the OpenRISC architecture:
- * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
- * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
- *
- *      This program is free software; you can redistribute it and/or
- *      modify it under the terms of the GNU General Public License
- *      as published by the Free Software Foundation; either version
- *      2 of the License, or (at your option) any later version.
- */
-#include <linux/init_task.h>
-#include <linux/mqueue.h>
-#include <linux/export.h>
-static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
-static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
-/*
- * Initial thread structure.
- *
- * We need to make sure that this is THREAD_SIZE aligned due to the
- * way process stacks are handled. This is done by having a special
- * "init_task" linker map entry..
- */
-union thread_union init_thread_union __init_task_data = {
-        INIT_THREAD_INFO(init_task)
-};
-/*
- * Initial task structure.
- *
- * All other task structs will be allocated on slabs in fork.c
- */
-struct task_struct init_task = INIT_TASK(init_task);
-EXPORT_SYMBOL(init_task);
diff --git a/arch/openrisc/kernel/irq.c b/arch/openrisc/kernel/irq.c
index 4bfead220956..e935b9d8eee1 100644
--- a/arch/openrisc/kernel/irq.c
+++ b/arch/openrisc/kernel/irq.c
@@ -14,17 +14,13 @@
 *      2 of the License, or (at your option) any later version.
 */
-#include <linux/ptrace.h>
-#include <linux/errno.h>
 #include <linux/interrupt.h>
 #include <linux/init.h>
 #include <linux/of.h>
 #include <linux/ftrace.h>
 #include <linux/irq.h>
-#include <linux/seq_file.h>
-#include <linux/kernel_stat.h>
 #include <linux/export.h>
+#include <linux/irqdomain.h>
 #include <linux/irqflags.h>
 /* read interrupt enabled status */
@@ -98,6 +94,7 @@ static void or1k_pic_mask_ack(struct irq_data *data)
 #endif
 }
+#if 0
 static int or1k_pic_set_type(struct irq_data *data, unsigned int flow_type)
 {
        /* There's nothing to do in the PIC configuration when changing
@@ -107,43 +104,64 @@ static int or1k_pic_set_type(struct irq_data *data, unsigned int flow_type)
        return irq_setup_alt_chip(data, flow_type);
 }
+#endif
+static struct irq_chip or1k_dev = {
+        .name = "or1k-PIC",
+        .irq_unmask = or1k_pic_unmask,
+        .irq_mask = or1k_pic_mask,
+        .irq_ack = or1k_pic_ack,
+        .irq_mask_ack = or1k_pic_mask_ack,
+};
+static struct irq_domain *root_domain;
 static inline int pic_get_irq(int first)
 {
-        int irq;
+        int hwirq;
-        irq = ffs(mfspr(SPR_PICSR) >> first);
+        hwirq = ffs(mfspr(SPR_PICSR) >> first);
+        if (!hwirq)
+                return NO_IRQ;
+        else
+                hwirq = hwirq + first -1;
-        return irq ? irq + first - 1 : NO_IRQ;
+        return irq_find_mapping(root_domain, hwirq);
 }
-static void __init or1k_irq_init(void)
+static int or1k_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
 {
-        struct irq_chip_generic *gc;
+        irq_set_chip_and_handler_name(irq, &or1k_dev,
-        struct irq_chip_type *ct;
+                                      handle_level_irq, "level");
+        irq_set_status_flags(irq, IRQ_LEVEL | IRQ_NOPROBE);
-        /* Disable all interrupts until explicitly requested */
+        return 0;
-        mtspr(SPR_PICMR, (0UL));
+}
-        gc = irq_alloc_generic_chip("or1k-PIC", 1, 0, 0, handle_level_irq);
+static const struct irq_domain_ops or1k_irq_domain_ops = {
-        ct = gc->chip_types;
+        .xlate = irq_domain_xlate_onecell,
+        .map = or1k_map,
+};
-        ct->chip.irq_unmask = or1k_pic_unmask;
+/*
-        ct->chip.irq_mask = or1k_pic_mask;
+ * This sets up the IRQ domain for the PIC built in to the OpenRISC
-        ct->chip.irq_ack = or1k_pic_ack;
+ * 1000 CPU.  This is the "root" domain as these are the interrupts
-        ct->chip.irq_mask_ack = or1k_pic_mask_ack;
+ * that directly trigger an exception in the CPU.
-        ct->chip.irq_set_type = or1k_pic_set_type;
+ */
+static void __init or1k_irq_init(void)
+{
+        struct device_node *intc = NULL;
-        /* The OR1K PIC can handle both level and edge trigged
+        /* The interrupt controller device node is mandatory */
-         * interrupts in roughly the same manner
+        intc = of_find_compatible_node(NULL, NULL, "opencores,or1k-pic");
-         */
+        BUG_ON(!intc);
-#if 0
-        /* FIXME: chip.type??? */
-        ct->chip.type = IRQ_TYPE_EDGE_BOTH | IRQ_TYPE_LEVEL_MASK;
-#endif
-        irq_setup_generic_chip(gc, IRQ_MSK(NR_IRQS), 0,
+        /* Disable all interrupts until explicitly requested */
-                               IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);
+        mtspr(SPR_PICMR, (0UL));
+        root_domain = irq_domain_add_linear(intc, 32,
+                                            &or1k_irq_domain_ops, NULL);
 }
 void __init init_IRQ(void)
@@ -164,10 +182,3 @@ void __irq_entry do_IRQ(struct pt_regs *regs)
        irq_exit();
        set_irq_regs(old_regs);
 }
-unsigned int irq_create_of_mapping(struct device_node *controller,
-                                   const u32 *intspec, unsigned int intsize)
-{
-        return intspec[0];
-}
-EXPORT_SYMBOL_GPL(irq_create_of_mapping);
diff --git a/arch/openrisc/mm/fault.c b/arch/openrisc/mm/fault.c
index a5dce82f864b..40f850e9766c 100644
--- a/arch/openrisc/mm/fault.c
+++ b/arch/openrisc/mm/fault.c
@@ -54,6 +54,7 @@ asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long address,
        struct vm_area_struct *vma;
        siginfo_t info;
        int fault;
+        unsigned int flags = FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE;
        tsk = current;
@@ -105,6 +106,7 @@ asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long address,
        if (in_interrupt() || !mm)
                goto no_context;
+retry:
        down_read(&mm->mmap_sem);
        vma = find_vma(mm, address);
@@ -143,6 +145,7 @@ good_area:
        if (write_acc) {
                if (!(vma->vm_flags & VM_WRITE))
                        goto bad_area;
+                flags |= FAULT_FLAG_WRITE;
        } else {
                /* not present */
                if (!(vma->vm_flags & (VM_READ | VM_EXEC)))
@@ -159,7 +162,11 @@ good_area:
         * the fault.
         */
-        fault = handle_mm_fault(mm, vma, address, write_acc);
+        fault = handle_mm_fault(mm, vma, address, flags);
+        if ((fault & VM_FAULT_RETRY) && fatal_signal_pending(current))
+                return;
        if (unlikely(fault & VM_FAULT_ERROR)) {
                if (fault & VM_FAULT_OOM)
                        goto out_of_memory;
@@ -167,11 +174,24 @@ good_area:
                        goto do_sigbus;
                BUG();
        }
-        /*RGD modeled on Cris */
-        if (fault & VM_FAULT_MAJOR)
+        if (flags & FAULT_FLAG_ALLOW_RETRY) {
-                tsk->maj_flt++;
+                /*RGD modeled on Cris */
-        else
+                if (fault & VM_FAULT_MAJOR)
-                tsk->min_flt++;
+                        tsk->maj_flt++;
+                else
+                        tsk->min_flt++;
+                if (fault & VM_FAULT_RETRY) {
+                        flags &= ~FAULT_FLAG_ALLOW_RETRY;
+                         /* No need to up_read(&mm->mmap_sem) as we would
+                         * have already released it in __lock_page_or_retry
+                         * in mm/filemap.c.
+                         */
+                        goto retry;
+                }
+        }
        up_read(&mm->mmap_sem);
        return;
diff --git a/arch/parisc/Kconfig b/arch/parisc/Kconfig
index 242a1b7ac759..ddb8b24b823d 100644
--- a/arch/parisc/Kconfig
+++ b/arch/parisc/Kconfig
@@ -17,6 +17,7 @@ config PARISC
        select GENERIC_PCI_IOMAP
        select IRQ_PER_CPU
        select ARCH_HAVE_NMI_SAFE_CMPXCHG
+        select GENERIC_SMP_IDLE_THREAD
        help
          The PA-RISC microprocessor is designed by Hewlett-Packard and used
diff --git a/arch/parisc/Makefile b/arch/parisc/Makefile
index 19ab7b2ea1cd..dbc3850b1d0d 100644
--- a/arch/parisc/Makefile
+++ b/arch/parisc/Makefile
@@ -75,7 +75,7 @@ head-y			:= arch/parisc/kernel/head.o
 KBUILD_CFLAGS   += $(cflags-y)
-kernel-y                        := mm/ kernel/ math-emu/ kernel/init_task.o
+kernel-y                        := mm/ kernel/ math-emu/
 kernel-$(CONFIG_HPUX)           += hpux/
 core-y  += $(addprefix arch/parisc/, $(kernel-y))
diff --git a/arch/parisc/include/asm/hardware.h b/arch/parisc/include/asm/hardware.h
index 4e9626836bab..d1d864b81bae 100644
--- a/arch/parisc/include/asm/hardware.h
+++ b/arch/parisc/include/asm/hardware.h
@@ -2,7 +2,6 @@
 #define _PARISC_HARDWARE_H
 #include <linux/mod_devicetable.h>
-#include <asm/pdc.h>
 #define HWTYPE_ANY_ID           PA_HWTYPE_ANY_ID
 #define HVERSION_ANY_ID         PA_HVERSION_ANY_ID
@@ -95,12 +94,14 @@ struct bc_module {
 #define HPHW_MC        15
 #define HPHW_FAULTY    31
+struct parisc_device_id;
 /* hardware.c: */
 extern const char *parisc_hardware_description(struct parisc_device_id *id);
 extern enum cpu_type parisc_get_cpu_type(unsigned long hversion);
 struct pci_dev;
+struct hardware_path;
 /* drivers.c: */
 extern struct parisc_device *alloc_pa_dev(unsigned long hpa,
diff --git a/arch/parisc/include/asm/page.h b/arch/parisc/include/asm/page.h
index a84cc1f925f6..4e0e7dbf0f3f 100644
--- a/arch/parisc/include/asm/page.h
+++ b/arch/parisc/include/asm/page.h
@@ -160,5 +160,11 @@ extern int npmem_ranges;
 #include <asm-generic/memory_model.h>
 #include <asm-generic/getorder.h>
+#include <asm/pdc.h>
+#define PAGE0   ((struct zeropage *)__PAGE_OFFSET)
+/* DEFINITION OF THE ZERO-PAGE (PAG0) */
+/* based on work by Jason Eckhardt (jason@equator.com) */
 #endif /* _PARISC_PAGE_H */
diff --git a/arch/parisc/include/asm/pdc.h b/arch/parisc/include/asm/pdc.h
index 4ca510b3c6f8..7f0f2d23059d 100644
--- a/arch/parisc/include/asm/pdc.h
+++ b/arch/parisc/include/asm/pdc.h
@@ -343,8 +343,6 @@
 #ifdef __KERNEL__
-#include <asm/page.h> /* for __PAGE_OFFSET */
 extern int pdc_type;
 /* Values for pdc_type */
@@ -677,11 +675,6 @@ static inline char * os_id_to_string(u16 os_id) {
 #endif /* __KERNEL__ */
-#define PAGE0   ((struct zeropage *)__PAGE_OFFSET)
-/* DEFINITION OF THE ZERO-PAGE (PAG0) */
-/* based on work by Jason Eckhardt (jason@equator.com) */
 /* flags of the device_path */
 #define PF_AUTOBOOT     0x80
 #define PF_AUTOSEARCH   0x40
diff --git a/arch/parisc/include/asm/pgtable.h b/arch/parisc/include/asm/pgtable.h
index 22dadeb58695..ee99f2339356 100644
--- a/arch/parisc/include/asm/pgtable.h
+++ b/arch/parisc/include/asm/pgtable.h
@@ -44,6 +44,8 @@ struct vm_area_struct;
 #endif /* !__ASSEMBLY__ */
+#include <asm/page.h>
 #define pte_ERROR(e) \
        printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
 #define pmd_ERROR(e) \
diff --git a/arch/parisc/include/asm/prefetch.h b/arch/parisc/include/asm/prefetch.h
index c5edc60c059f..1ee7c82672c1 100644
--- a/arch/parisc/include/asm/prefetch.h
+++ b/arch/parisc/include/asm/prefetch.h
@@ -21,7 +21,12 @@
 #define ARCH_HAS_PREFETCH
 static inline void prefetch(const void *addr)
 {
-        __asm__("ldw 0(%0), %%r0" : : "r" (addr));
+        __asm__(
+#ifndef CONFIG_PA20
+                /* Need to avoid prefetch of NULL on PA7300LC */
+                "       extrw,u,= %0,31,32,%%r0\n"
+#endif
+                "       ldw 0(%0), %%r0" : : "r" (addr));
 }
 /* LDD is a PA2.0 addition. */
diff --git a/arch/parisc/include/asm/spinlock.h b/arch/parisc/include/asm/spinlock.h
index 804aa28ab1d6..3516e0b27044 100644
--- a/arch/parisc/include/asm/spinlock.h
+++ b/arch/parisc/include/asm/spinlock.h
@@ -1,6 +1,8 @@
 #ifndef __ASM_SPINLOCK_H
 #define __ASM_SPINLOCK_H
+#include <asm/barrier.h>
+#include <asm/ldcw.h>
 #include <asm/processor.h>
 #include <asm/spinlock_types.h>
diff --git a/arch/parisc/kernel/Makefile b/arch/parisc/kernel/Makefile
index 67db0722e6ca..66ee3f12df58 100644
--- a/arch/parisc/kernel/Makefile
+++ b/arch/parisc/kernel/Makefile
@@ -2,7 +2,7 @@
 # Makefile for arch/parisc/kernel
 #
-extra-y                 := init_task.o head.o vmlinux.lds
+extra-y                 := head.o vmlinux.lds
 obj-y           := cache.o pacache.o setup.o traps.o time.o irq.o \
                   pa7300lc.o syscall.o entry.o sys_parisc.o firmware.o \
diff --git a/arch/parisc/kernel/entry.S b/arch/parisc/kernel/entry.S
index 6f0594439143..535034217021 100644
--- a/arch/parisc/kernel/entry.S
+++ b/arch/parisc/kernel/entry.S
@@ -581,7 +581,11 @@
         */
        cmpiclr,=       0x01,\tmp,%r0
        ldi             (_PAGE_DIRTY|_PAGE_READ|_PAGE_WRITE),\prot
+#ifdef CONFIG_64BIT
        depd,z          \prot,8,7,\prot
+#else
+        depw,z          \prot,8,7,\prot
+#endif
        /*
         * OK, it is in the temp alias region, check whether "from" or "to".
         * Check "subtle" note in pacache.S re: r23/r26.
diff --git a/arch/parisc/kernel/init_task.c b/arch/parisc/kernel/init_task.c
deleted file mode 100644
index 4a91e433416f..000000000000
--- a/arch/parisc/kernel/init_task.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/* 
- *    Static declaration of "init" task data structure.
- *
- *    Copyright (C) 2000 Paul Bame <bame at parisc-linux.org>
- *    Copyright (C) 2000-2001 John Marvin <jsm at parisc-linux.org>
- *    Copyright (C) 2001 Helge Deller <deller @ parisc-linux.org>
- *    Copyright (C) 2002 Matthew Wilcox <willy with parisc-linux.org>
- *
- *
- *    This program is free software; you can redistribute it and/or modify
- *    it under the terms of the GNU General Public License as published by
- *    the Free Software Foundation; either version 2 of the License, or
- *    (at your option) any later version.
- *
- *    This program is distributed in the hope that it will be useful,
- *    but WITHOUT ANY WARRANTY; without even the implied warranty of
- *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *    GNU General Public License for more details.
- *
- *    You should have received a copy of the GNU General Public License
- *    along with this program; if not, write to the Free Software
- *    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/mm.h>
-#include <linux/fs.h>
-#include <linux/module.h>
-#include <linux/sched.h>
-#include <linux/init.h>
-#include <linux/init_task.h>
-#include <linux/mqueue.h>
-#include <asm/uaccess.h>
-#include <asm/pgtable.h>
-#include <asm/pgalloc.h>
-static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
-static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
-/*
- * Initial task structure.
- *
- * We need to make sure that this is 16384-byte aligned due to the
- * way process stacks are handled. This is done by having a special
- * "init_task" linker map entry..
- */
-union thread_union init_thread_union __init_task_data
-        __attribute__((aligned(128))) =
-                { INIT_THREAD_INFO(init_task) };
-#if PT_NLEVELS == 3
-/* NOTE: This layout exactly conforms to the hybrid L2/L3 page table layout
- * with the first pmd adjacent to the pgd and below it. gcc doesn't actually
- * guarantee that global objects will be laid out in memory in the same order 
- * as the order of declaration, so put these in different sections and use
- * the linker script to order them. */
-pmd_t pmd0[PTRS_PER_PMD] __attribute__ ((__section__ (".data..vm0.pmd"), aligned(PAGE_SIZE)));
-#endif
-pgd_t swapper_pg_dir[PTRS_PER_PGD] __attribute__ ((__section__ (".data..vm0.pgd"), aligned(PAGE_SIZE)));
-pte_t pg0[PT_INITIAL * PTRS_PER_PTE] __attribute__ ((__section__ (".data..vm0.pte"), aligned(PAGE_SIZE)));
-/*
- * Initial task structure.
- *
- * All other task structs will be allocated on slabs in fork.c
- */
-EXPORT_SYMBOL(init_task);
-__asm__(".data");
-struct task_struct init_task = INIT_TASK(init_task);
diff --git a/arch/parisc/kernel/pacache.S b/arch/parisc/kernel/pacache.S
index 93ff3d90edd1..5d7218ad885c 100644
--- a/arch/parisc/kernel/pacache.S
+++ b/arch/parisc/kernel/pacache.S
@@ -692,7 +692,7 @@ ENTRY(flush_icache_page_asm)
        /* Purge any old translation */
-        pitlb           (%sr0,%r28)
+        pitlb           (%sr4,%r28)
        ldil            L%icache_stride, %r1
        ldw             R%icache_stride(%r1), %r1
@@ -706,27 +706,29 @@ ENTRY(flush_icache_page_asm)
        sub             %r25, %r1, %r25
-1:      fic,m           %r1(%r28)
+        /* fic only has the type 26 form on PA1.1, requiring an
-        fic,m           %r1(%r28)
+         * explicit space specification, so use %sr4 */
-        fic,m           %r1(%r28)
+1:      fic,m           %r1(%sr4,%r28)
-        fic,m           %r1(%r28)
+        fic,m           %r1(%sr4,%r28)
-        fic,m           %r1(%r28)
+        fic,m           %r1(%sr4,%r28)
-        fic,m           %r1(%r28)
+        fic,m           %r1(%sr4,%r28)
-        fic,m           %r1(%r28)
+        fic,m           %r1(%sr4,%r28)
-        fic,m           %r1(%r28)
+        fic,m           %r1(%sr4,%r28)
-        fic,m           %r1(%r28)
+        fic,m           %r1(%sr4,%r28)
-        fic,m           %r1(%r28)
+        fic,m           %r1(%sr4,%r28)
-        fic,m           %r1(%r28)
+        fic,m           %r1(%sr4,%r28)
-        fic,m           %r1(%r28)
+        fic,m           %r1(%sr4,%r28)
-        fic,m           %r1(%r28)
+        fic,m           %r1(%sr4,%r28)
-        fic,m           %r1(%r28)
+        fic,m           %r1(%sr4,%r28)
-        fic,m           %r1(%r28)
+        fic,m           %r1(%sr4,%r28)
+        fic,m           %r1(%sr4,%r28)
+        fic,m           %r1(%sr4,%r28)
        cmpb,COND(<<)           %r28, %r25,1b
-        fic,m           %r1(%r28)
+        fic,m           %r1(%sr4,%r28)
        sync
        bv              %r0(%r2)
-        pitlb           (%sr0,%r25)
+        pitlb           (%sr4,%r25)
        .exit
        .procend
diff --git a/arch/parisc/kernel/pdc_cons.c b/arch/parisc/kernel/pdc_cons.c
index 4f004596a6e7..47341aa208f2 100644
--- a/arch/parisc/kernel/pdc_cons.c
+++ b/arch/parisc/kernel/pdc_cons.c
@@ -50,6 +50,7 @@
 #include <linux/init.h>
 #include <linux/major.h>
 #include <linux/tty.h>
+#include <asm/page.h>           /* for PAGE0 */
 #include <asm/pdc.h>            /* for iodc_call() proto and friends */
 static DEFINE_SPINLOCK(pdc_console_lock);
@@ -104,7 +105,7 @@ static int pdc_console_tty_open(struct tty_struct *tty, struct file *filp)
 static void pdc_console_tty_close(struct tty_struct *tty, struct file *filp)
 {
-        if (!tty->count) {
+        if (tty->count == 1) {
                del_timer_sync(&pdc_console_timer);
                tty_port_tty_set(&tty_port, NULL);
        }
diff --git a/arch/parisc/kernel/smp.c b/arch/parisc/kernel/smp.c
index 0bb1d63907f8..a47828d31fe6 100644
--- a/arch/parisc/kernel/smp.c
+++ b/arch/parisc/kernel/smp.c
@@ -31,6 +31,7 @@
 #include <linux/delay.h>
 #include <linux/bitops.h>
 #include <linux/ftrace.h>
+#include <linux/cpu.h>
 #include <linux/atomic.h>
 #include <asm/current.h>
@@ -295,8 +296,13 @@ smp_cpu_init(int cpunum)
                printk(KERN_CRIT "CPU#%d already initialized!\n", cpunum);
                machine_halt();
-        }  
+        }
+        notify_cpu_starting(cpunum);
+        ipi_call_lock();
        set_cpu_online(cpunum, true);
+        ipi_call_unlock();
        /* Initialise the idle task for this CPU */
        atomic_inc(&init_mm.mm_count);
@@ -334,26 +340,11 @@ void __init smp_callin(void)
 /*
 * Bring one cpu online.
 */
-int __cpuinit smp_boot_one_cpu(int cpuid)
+int __cpuinit smp_boot_one_cpu(int cpuid, struct task_struct *idle)
 {
        const struct cpuinfo_parisc *p = &per_cpu(cpu_data, cpuid);
-        struct task_struct *idle;
        long timeout;
-        /* 
-         * Create an idle task for this CPU.  Note the address wed* give 
-         * to kernel_thread is irrelevant -- it's going to start
-         * where OS_BOOT_RENDEVZ vector in SAL says to start.  But
-         * this gets all the other task-y sort of data structures set
-         * up like we wish.   We need to pull the just created idle task 
-         * off the run queue and stuff it into the init_tasks[] array.  
-         * Sheesh . . .
-         */
-        idle = fork_idle(cpuid);
-        if (IS_ERR(idle))
-                panic("SMP: fork failed for CPU:%d", cpuid);
        task_thread_info(idle)->cpu = cpuid;
        /* Let _start know what logical CPU we're booting
@@ -397,10 +388,6 @@ int __cpuinit smp_boot_one_cpu(int cpuid)
                udelay(100);
                barrier();
        }
-        put_task_struct(idle);
-        idle = NULL;
        printk(KERN_CRIT "SMP: CPU:%d is stuck.\n", cpuid);
        return -1;
@@ -449,10 +436,10 @@ void smp_cpus_done(unsigned int cpu_max)
 }
-int __cpuinit __cpu_up(unsigned int cpu)
+int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *tidle)
 {
        if (cpu != 0 && cpu < parisc_max_cpus)
-                smp_boot_one_cpu(cpu);
+                smp_boot_one_cpu(cpu, tidle);
        return cpu_online(cpu) ? 0 : -ENOSYS;
 }
diff --git a/arch/parisc/kernel/time.c b/arch/parisc/kernel/time.c
index 7c0774397b89..70e105d62423 100644
--- a/arch/parisc/kernel/time.c
+++ b/arch/parisc/kernel/time.c
@@ -29,6 +29,7 @@
 #include <asm/uaccess.h>
 #include <asm/io.h>
 #include <asm/irq.h>
+#include <asm/page.h>
 #include <asm/param.h>
 #include <asm/pdc.h>
 #include <asm/led.h>
diff --git a/arch/parisc/mm/init.c b/arch/parisc/mm/init.c
index 82f364e209fc..3ac462de53a4 100644
--- a/arch/parisc/mm/init.c
+++ b/arch/parisc/mm/init.c
@@ -33,6 +33,18 @@
 extern int  data_start;
+#if PT_NLEVELS == 3
+/* NOTE: This layout exactly conforms to the hybrid L2/L3 page table layout
+ * with the first pmd adjacent to the pgd and below it. gcc doesn't actually
+ * guarantee that global objects will be laid out in memory in the same order
+ * as the order of declaration, so put these in different sections and use
+ * the linker script to order them. */
+pmd_t pmd0[PTRS_PER_PMD] __attribute__ ((__section__ (".data..vm0.pmd"), aligned(PAGE_SIZE)));
+#endif
+pgd_t swapper_pg_dir[PTRS_PER_PGD] __attribute__ ((__section__ (".data..vm0.pgd"), aligned(PAGE_SIZE)));
+pte_t pg0[PT_INITIAL * PTRS_PER_PTE] __attribute__ ((__section__ (".data..vm0.pte"), aligned(PAGE_SIZE)));
 #ifdef CONFIG_DISCONTIGMEM
 struct node_map_data node_data[MAX_NUMNODES] __read_mostly;
 unsigned char pfnnid_map[PFNNID_MAP_MAX] __read_mostly;
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index feab3bad6d0f..8a01098eaaca 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -87,10 +87,6 @@ config ARCH_HAS_ILOG2_U64
        bool
        default y if 64BIT
-config ARCH_HAS_CPU_IDLE_WAIT
-        bool
-        default y
 config GENERIC_HWEIGHT
        bool
        default y
@@ -141,9 +137,10 @@ config PPC
        select IRQ_FORCED_THREADING
        select HAVE_RCU_TABLE_FREE if SMP
        select HAVE_SYSCALL_TRACEPOINTS
-        select HAVE_BPF_JIT if (PPC64 && NET)
+        select HAVE_BPF_JIT if PPC64
        select HAVE_ARCH_JUMP_LABEL
        select ARCH_HAVE_NMI_SAFE_CMPXCHG
+        select GENERIC_SMP_IDLE_THREAD
 config EARLY_PRINTK
        bool
diff --git a/arch/powerpc/boot/dts/fsl/pq3-mpic-message-B.dtsi b/arch/powerpc/boot/dts/fsl/pq3-mpic-message-B.dtsi
new file mode 100644
index 000000000000..1cf0b77b1efe
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-mpic-message-B.dtsi
@@ -0,0 +1,43 @@
+/*
+ * PQ3 MPIC Message (Group B) device tree stub [ controller @ offset 0x42400 ]
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+message@42400 {
+        compatible = "fsl,mpic-v3.1-msgr";
+        reg = <0x42400 0x200>;
+        interrupts = <
+                0xb4 2 0 0
+                0xb5 2 0 0
+                0xb6 2 0 0
+                0xb7 2 0 0>;
+};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi b/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi
index fdedf7b1fe0f..71c30eb10056 100644
--- a/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi
+++ b/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi
@@ -53,6 +53,16 @@ timer@41100 {
                      3 0 3 0>;
 };
+message@41400 {
+        compatible = "fsl,mpic-v3.1-msgr";
+        reg = <0x41400 0x200>;
+        interrupts = <
+                0xb0 2 0 0
+                0xb1 2 0 0
+                0xb2 2 0 0
+                0xb3 2 0 0>;
+};
 msi@41600 {
        compatible = "fsl,mpic-msi";
        reg = <0x41600 0x80>;
diff --git a/arch/powerpc/configs/chroma_defconfig b/arch/powerpc/configs/chroma_defconfig
index f104ccde6b53..b1f9597fe312 100644
--- a/arch/powerpc/configs/chroma_defconfig
+++ b/arch/powerpc/configs/chroma_defconfig
@@ -32,7 +32,7 @@ CONFIG_RD_LZMA=y
 CONFIG_INITRAMFS_COMPRESSION_GZIP=y
 CONFIG_KALLSYMS_ALL=y
 CONFIG_EMBEDDED=y
-CONFIG_PERF_COUNTERS=y
+CONFIG_PERF_EVENTS=y
 CONFIG_PROFILING=y
 CONFIG_OPROFILE=y
 CONFIG_KPROBES=y
diff --git a/arch/powerpc/configs/gamecube_defconfig b/arch/powerpc/configs/gamecube_defconfig
index e74d3a483705..9ef2cc13e1b4 100644
--- a/arch/powerpc/configs/gamecube_defconfig
+++ b/arch/powerpc/configs/gamecube_defconfig
@@ -8,7 +8,7 @@ CONFIG_BLK_DEV_INITRD=y
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_EXPERT=y
 # CONFIG_ELF_CORE is not set
-CONFIG_PERF_COUNTERS=y
+CONFIG_PERF_EVENTS=y
 # CONFIG_VM_EVENT_COUNTERS is not set
 CONFIG_SLAB=y
 CONFIG_MODULES=y
diff --git a/arch/powerpc/configs/wii_defconfig b/arch/powerpc/configs/wii_defconfig
index 175295fbf4f3..1e2b7d062aa4 100644
--- a/arch/powerpc/configs/wii_defconfig
+++ b/arch/powerpc/configs/wii_defconfig
@@ -9,7 +9,7 @@ CONFIG_BLK_DEV_INITRD=y
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_EXPERT=y
 # CONFIG_ELF_CORE is not set
-CONFIG_PERF_COUNTERS=y
+CONFIG_PERF_EVENTS=y
 # CONFIG_VM_EVENT_COUNTERS is not set
 CONFIG_SLAB=y
 CONFIG_MODULES=y
diff --git a/arch/powerpc/include/asm/exception-64s.h b/arch/powerpc/include/asm/exception-64s.h
index 548da3aa0a30..d58fc4e4149c 100644
--- a/arch/powerpc/include/asm/exception-64s.h
+++ b/arch/powerpc/include/asm/exception-64s.h
@@ -288,13 +288,6 @@ label##_hv:								\
 /* Exception addition: Hard disable interrupts */
 #define DISABLE_INTS    SOFT_DISABLE_INTS(r10,r11)
-/* Exception addition: Keep interrupt state */
-#define ENABLE_INTS                             \
-        ld      r11,PACAKMSR(r13);              \
-        ld      r12,_MSR(r1);                   \
-        rlwimi  r11,r12,0,MSR_EE;               \
-        mtmsrd  r11,1
 #define ADD_NVGPRS                              \
        bl      .save_nvgprs
diff --git a/arch/powerpc/include/asm/irq.h b/arch/powerpc/include/asm/irq.h
index cf417e510736..0e40843a1c6e 100644
--- a/arch/powerpc/include/asm/irq.h
+++ b/arch/powerpc/include/asm/irq.h
@@ -18,10 +18,6 @@
 #include <linux/atomic.h>
-/* Define a way to iterate across irqs. */
-#define for_each_irq(i) \
-        for ((i) = 0; (i) < NR_IRQS; ++(i))
 extern atomic_t ppc_n_lost_interrupts;
 /* This number is used when no interrupt has been assigned */
@@ -33,8 +29,6 @@ extern atomic_t ppc_n_lost_interrupts;
 /* Same thing, used by the generic IRQ code */
 #define NR_IRQS_LEGACY          NUM_ISA_INTERRUPTS
-struct irq_data;
-extern irq_hw_number_t irqd_to_hwirq(struct irq_data *d);
 extern irq_hw_number_t virq_to_hw(unsigned int virq);
 /**
diff --git a/arch/powerpc/include/asm/kvm_book3s.h b/arch/powerpc/include/asm/kvm_book3s.h
index aa795ccef294..fd07f43d6622 100644
--- a/arch/powerpc/include/asm/kvm_book3s.h
+++ b/arch/powerpc/include/asm/kvm_book3s.h
@@ -81,12 +81,13 @@ struct kvmppc_vcpu_book3s {
        u64 sdr1;
        u64 hior;
        u64 msr_mask;
-        u64 vsid_next;
 #ifdef CONFIG_PPC_BOOK3S_32
        u32 vsid_pool[VSID_POOL_SIZE];
+        u32 vsid_next;
 #else
-        u64 vsid_first;
+        u64 proto_vsid_first;
-        u64 vsid_max;
+        u64 proto_vsid_max;
+        u64 proto_vsid_next;
 #endif
        int context_id[SID_CONTEXTS];
diff --git a/arch/powerpc/include/asm/mpic.h b/arch/powerpc/include/asm/mpic.h
index c65b9294376e..c9f698a994be 100644
--- a/arch/powerpc/include/asm/mpic.h
+++ b/arch/powerpc/include/asm/mpic.h
@@ -275,9 +275,6 @@ struct mpic
        unsigned int            isu_mask;
        /* Number of sources */
        unsigned int            num_sources;
-        /* default senses array */
-        unsigned char           *senses;
-        unsigned int            senses_count;
        /* vector numbers used for internal sources (ipi/timers) */
        unsigned int            ipi_vecs[4];
@@ -415,21 +412,6 @@ extern struct mpic *mpic_alloc(struct device_node *node,
 extern void mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
                            phys_addr_t phys_addr);
-/* Set default sense codes
- *
- * @mpic:       controller
- * @senses:     array of sense codes
- * @count:      size of above array
- *
- * Optionally provide an array (indexed on hardware interrupt numbers
- * for this MPIC) of default sense codes for the chip. Those are linux
- * sense codes IRQ_TYPE_*
- *
- * The driver gets ownership of the pointer, don't dispose of it or
- * anything like that. __init only.
- */
-extern void mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count);
 /* Initialize the controller. After this has been called, none of the above
 * should be called again for this mpic
diff --git a/arch/powerpc/include/asm/mpic_msgr.h b/arch/powerpc/include/asm/mpic_msgr.h
index 3ec37dc9003e..326d33ca55cd 100644
--- a/arch/powerpc/include/asm/mpic_msgr.h
+++ b/arch/powerpc/include/asm/mpic_msgr.h
@@ -13,6 +13,7 @@
 #include <linux/types.h>
 #include <linux/spinlock.h>
+#include <asm/smp.h>
 struct mpic_msgr {
        u32 __iomem *base;
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 8e2d0371fe1e..48a26d379222 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -386,7 +386,6 @@ extern unsigned long cpuidle_disable;
 enum idle_boot_override {IDLE_NO_OVERRIDE = 0, IDLE_POWERSAVE_OFF};
 extern int powersave_nap;       /* set if nap mode can be used in idle loop */
-void cpu_idle_wait(void);
 #ifdef CONFIG_PSERIES_IDLE
 extern void update_smt_snooze_delay(int snooze);
diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h
index b86faa9107da..8a97aa7289d3 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -15,11 +15,6 @@
 #ifndef __ASM_POWERPC_REG_BOOKE_H__
 #define __ASM_POWERPC_REG_BOOKE_H__
-#ifdef CONFIG_BOOKE_WDT
-extern u32 booke_wdt_enabled;
-extern u32 booke_wdt_period;
-#endif /* CONFIG_BOOKE_WDT */
 /* Machine State Register (MSR) Fields */
 #define MSR_GS          (1<<28) /* Guest state */
 #define MSR_UCLE        (1<<26) /* User-mode cache lock enable */
diff --git a/arch/powerpc/include/asm/thread_info.h b/arch/powerpc/include/asm/thread_info.h
index 4a741c7efd02..1a1bb00f061a 100644
--- a/arch/powerpc/include/asm/thread_info.h
+++ b/arch/powerpc/include/asm/thread_info.h
@@ -62,21 +62,8 @@ struct thread_info {
 #define init_thread_info        (init_thread_union.thread_info)
 #define init_stack              (init_thread_union.stack)
-/* thread information allocation */
-#if THREAD_SHIFT >= PAGE_SHIFT
 #define THREAD_SIZE_ORDER       (THREAD_SHIFT - PAGE_SHIFT)
-#else /* THREAD_SHIFT < PAGE_SHIFT */
-#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR
-extern struct thread_info *alloc_thread_info_node(struct task_struct *tsk, int node);
-extern void free_thread_info(struct thread_info *ti);
-#endif /* THREAD_SHIFT < PAGE_SHIFT */
 /* how to get the thread information struct from C */
 static inline struct thread_info *current_thread_info(void)
 {
diff --git a/arch/powerpc/include/asm/topology.h b/arch/powerpc/include/asm/topology.h
index c97185885c6d..852ed1b384f6 100644
--- a/arch/powerpc/include/asm/topology.h
+++ b/arch/powerpc/include/asm/topology.h
@@ -18,12 +18,6 @@ struct device_node;
 */
 #define RECLAIM_DISTANCE 10
-/*
- * Avoid creating an extra level of balancing (SD_ALLNODES) on the largest
- * POWER7 boxes which have a maximum of 32 nodes.
- */
-#define SD_NODES_PER_DOMAIN 32
 #include <asm/mmzone.h>
 static inline int cpu_to_node(int cpu)
@@ -51,36 +45,6 @@ static inline int pcibus_to_node(struct pci_bus *bus)
                                 cpu_all_mask :                         \
                                 cpumask_of_node(pcibus_to_node(bus)))
-/* sched_domains SD_NODE_INIT for PPC64 machines */
-#define SD_NODE_INIT (struct sched_domain) {                            \
-        .min_interval           = 8,                                    \
-        .max_interval           = 32,                                   \
-        .busy_factor            = 32,                                   \
-        .imbalance_pct          = 125,                                  \
-        .cache_nice_tries       = 1,                                    \
-        .busy_idx               = 3,                                    \
-        .idle_idx               = 1,                                    \
-        .newidle_idx            = 0,                                    \
-        .wake_idx               = 0,                                    \
-        .forkexec_idx           = 0,                                    \
-                                                                        \
-        .flags                  = 1*SD_LOAD_BALANCE                     \
-                                | 0*SD_BALANCE_NEWIDLE                  \
-                                | 1*SD_BALANCE_EXEC                     \
-                                | 1*SD_BALANCE_FORK                     \
-                                | 0*SD_BALANCE_WAKE                     \
-                                | 1*SD_WAKE_AFFINE                      \
-                                | 0*SD_PREFER_LOCAL                     \
-                                | 0*SD_SHARE_CPUPOWER                   \
-                                | 0*SD_POWERSAVINGS_BALANCE             \
-                                | 0*SD_SHARE_PKG_RESOURCES              \
-                                | 1*SD_SERIALIZE                        \
-                                | 0*SD_PREFER_SIBLING                   \
-                                ,                                       \
-        .last_balance           = jiffies,                              \
-        .balance_interval       = 1,                                    \
-}
 extern int __node_distance(int, int);
 #define node_distance(a, b) __node_distance(a, b)
diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile
index f5808a35688c..83afacd3ba7b 100644
--- a/arch/powerpc/kernel/Makefile
+++ b/arch/powerpc/kernel/Makefile
@@ -28,7 +28,7 @@ endif
 obj-y                           := cputable.o ptrace.o syscalls.o \
                                   irq.o align.o signal_32.o pmc.o vdso.o \
-                                   init_task.o process.o systbl.o idle.o \
+                                   process.o systbl.o idle.o \
                                   signal.o sysfs.o cacheinfo.o time.o \
                                   prom.o traps.o setup-common.o \
                                   udbg.o misc.o io.o dma.o \
diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S
index 3e57a00b8cba..ba3aeb4bc06a 100644
--- a/arch/powerpc/kernel/entry_32.S
+++ b/arch/powerpc/kernel/entry_32.S
@@ -206,40 +206,43 @@ reenable_mmu:				/* re-enable mmu so we can */
        andi.   r10,r10,MSR_EE          /* Did EE change? */
        beq     1f
-        /* Save handler and return address into the 2 unused words
-         * of the STACK_FRAME_OVERHEAD (sneak sneak sneak). Everything
-         * else can be recovered from the pt_regs except r3 which for
-         * normal interrupts has been set to pt_regs and for syscalls
-         * is an argument, so we temporarily use ORIG_GPR3 to save it
-         */
-        stw     r9,8(r1)
-        stw     r11,12(r1)
-        stw     r3,ORIG_GPR3(r1)
        /*
         * The trace_hardirqs_off will use CALLER_ADDR0 and CALLER_ADDR1.
         * If from user mode there is only one stack frame on the stack, and
         * accessing CALLER_ADDR1 will cause oops. So we need create a dummy
         * stack frame to make trace_hardirqs_off happy.
+         *
+         * This is handy because we also need to save a bunch of GPRs,
+         * r3 can be different from GPR3(r1) at this point, r9 and r11
+         * contains the old MSR and handler address respectively,
+         * r4 & r5 can contain page fault arguments that need to be passed
+         * along as well. r12, CCR, CTR, XER etc... are left clobbered as
+         * they aren't useful past this point (aren't syscall arguments),
+         * the rest is restored from the exception frame.
         */
+        stwu    r1,-32(r1)
+        stw     r9,8(r1)
+        stw     r11,12(r1)
+        stw     r3,16(r1)
+        stw     r4,20(r1)
+        stw     r5,24(r1)
        andi.   r12,r12,MSR_PR
-        beq     11f
+        b       11f
-        stwu    r1,-16(r1)
        bl      trace_hardirqs_off
-        addi    r1,r1,16
        b       12f
 11:
        bl      trace_hardirqs_off
 12:
+        lwz     r5,24(r1)
+        lwz     r4,20(r1)
+        lwz     r3,16(r1)
+        lwz     r11,12(r1)
+        lwz     r9,8(r1)
+        addi    r1,r1,32
        lwz     r0,GPR0(r1)
-        lwz     r3,ORIG_GPR3(r1)
-        lwz     r4,GPR4(r1)
-        lwz     r5,GPR5(r1)
        lwz     r6,GPR6(r1)
        lwz     r7,GPR7(r1)
        lwz     r8,GPR8(r1)
-        lwz     r9,8(r1)
-        lwz     r11,12(r1)
 1:      mtctr   r11
        mtlr    r9
        bctr                            /* jump to handler */
diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S
index f8a7a1a1a9f4..ef2074c3e906 100644
--- a/arch/powerpc/kernel/entry_64.S
+++ b/arch/powerpc/kernel/entry_64.S
@@ -588,23 +588,19 @@ _GLOBAL(ret_from_except_lite)
 fast_exc_return_irq:
 restore:
        /*
-         * This is the main kernel exit path, we first check if we
+         * This is the main kernel exit path. First we check if we
-         * have to change our interrupt state.
+         * are about to re-enable interrupts
         */
        ld      r5,SOFTE(r1)
        lbz     r6,PACASOFTIRQEN(r13)
-        cmpwi   cr1,r5,0
+        cmpwi   cr0,r5,0
-        cmpw    cr0,r5,r6
+        beq     restore_irq_off
-        beq     cr0,4f
-        /* We do, handle disable first, which is easy */
+        /* We are enabling, were we already enabled ? Yes, just return */
-        bne     cr1,3f;
+        cmpwi   cr0,r6,1
-        li      r0,0
+        beq     cr0,do_restore
-        stb     r0,PACASOFTIRQEN(r13);
-        TRACE_DISABLE_INTS
-        b       4f
-3:      /*
+        /*
         * We are about to soft-enable interrupts (we are hard disabled
         * at this point). We check if there's anything that needs to
         * be replayed first.
@@ -626,7 +622,7 @@ restore_no_replay:
        /*
         * Final return path. BookE is handled in a different file
         */
-4:
+do_restore:
 #ifdef CONFIG_PPC_BOOK3E
        b       .exception_return_book3e
 #else
@@ -700,6 +696,25 @@ fast_exception_return:
 #endif /* CONFIG_PPC_BOOK3E */
        /*
+         * We are returning to a context with interrupts soft disabled.
+         *
+         * However, we may also about to hard enable, so we need to
+         * make sure that in this case, we also clear PACA_IRQ_HARD_DIS
+         * or that bit can get out of sync and bad things will happen
+         */
+restore_irq_off:
+        ld      r3,_MSR(r1)
+        lbz     r7,PACAIRQHAPPENED(r13)
+        andi.   r0,r3,MSR_EE
+        beq     1f
+        rlwinm  r7,r7,0,~PACA_IRQ_HARD_DIS
+        stb     r7,PACAIRQHAPPENED(r13)
+1:      li      r0,0
+        stb     r0,PACASOFTIRQEN(r13);
+        TRACE_DISABLE_INTS
+        b       do_restore
+        /*
         * Something did happen, check if a re-emit is needed
         * (this also clears paca->irq_happened)
         */
@@ -748,6 +763,9 @@ restore_check_irq_replay:
 #endif /* CONFIG_PPC_BOOK3E */
 1:      b       .ret_from_except /* What else to do here ? */
 
+3:
 do_work:
 #ifdef CONFIG_PREEMPT
        andi.   r0,r3,MSR_PR    /* Returning to user mode? */
@@ -767,16 +785,6 @@ do_work:
        SOFT_DISABLE_INTS(r3,r4)
 1:      bl      .preempt_schedule_irq
-        /* Hard-disable interrupts again (and update PACA) */
-#ifdef CONFIG_PPC_BOOK3E
-        wrteei  0
-#else
-        ld      r10,PACAKMSR(r13) /* Get kernel MSR without EE */
-        mtmsrd  r10,1
-#endif /* CONFIG_PPC_BOOK3E */
-        li      r0,PACA_IRQ_HARD_DIS
-        stb     r0,PACAIRQHAPPENED(r13)
        /* Re-test flags and eventually loop */
        clrrdi  r9,r1,THREAD_SHIFT
        ld      r4,TI_FLAGS(r9)
@@ -787,14 +795,6 @@ do_work:
 user_work:
 #endif /* CONFIG_PREEMPT */
-        /* Enable interrupts */
-#ifdef CONFIG_PPC_BOOK3E
-        wrteei  1
-#else
-        ori     r10,r10,MSR_EE
-        mtmsrd  r10,1
-#endif /* CONFIG_PPC_BOOK3E */
        andi.   r0,r4,_TIF_NEED_RESCHED
        beq     1f
        bl      .restore_interrupts
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index cb705fdbb458..8f880bc77c56 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -768,8 +768,8 @@ alignment_common:
        std     r3,_DAR(r1)
        std     r4,_DSISR(r1)
        bl      .save_nvgprs
+        DISABLE_INTS
        addi    r3,r1,STACK_FRAME_OVERHEAD
-        ENABLE_INTS
        bl      .alignment_exception
        b       .ret_from_except
diff --git a/arch/powerpc/kernel/idle.c b/arch/powerpc/kernel/idle.c
index 6d2209ac0c44..2099d9a879e8 100644
--- a/arch/powerpc/kernel/idle.c
+++ b/arch/powerpc/kernel/idle.c
@@ -113,29 +113,6 @@ void cpu_idle(void)
        }
 }
-/*
- * cpu_idle_wait - Used to ensure that all the CPUs come out of the old
- * idle loop and start using the new idle loop.
- * Required while changing idle handler on SMP systems.
- * Caller must have changed idle handler to the new value before the call.
- * This window may be larger on shared systems.
- */
-void cpu_idle_wait(void)
-{
-        int cpu;
-        smp_mb();
-        /* kick all the CPUs so that they exit out of old idle routine */
-        get_online_cpus();
-        for_each_online_cpu(cpu) {
-                if (cpu != smp_processor_id())
-                        smp_send_reschedule(cpu);
-        }
-        put_online_cpus();
-}
-EXPORT_SYMBOL_GPL(cpu_idle_wait);
 int powersave_nap;
 #ifdef CONFIG_SYSCTL
diff --git a/arch/powerpc/kernel/init_task.c b/arch/powerpc/kernel/init_task.c
deleted file mode 100644
index d076d465dbd1..000000000000
--- a/arch/powerpc/kernel/init_task.c
+++ /dev/null
@@ -1,29 +0,0 @@
-#include <linux/mm.h>
-#include <linux/export.h>
-#include <linux/sched.h>
-#include <linux/init.h>
-#include <linux/init_task.h>
-#include <linux/fs.h>
-#include <linux/mqueue.h>
-#include <asm/uaccess.h>
-static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
-static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
-/*
- * Initial thread structure.
- *
- * We need to make sure that this is 16384-byte aligned due to the
- * way process stacks are handled. This is done by having a special
- * "init_task" linker map entry..
- */
-union thread_union init_thread_union __init_task_data =
-        { INIT_THREAD_INFO(init_task) };
-/*
- * Initial task structure.
- *
- * All other task structs will be allocated on slabs in fork.c
- */
-struct task_struct init_task = INIT_TASK(init_task);
-EXPORT_SYMBOL(init_task);
diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c
index 243dbabfe74d..641da9e868ce 100644
--- a/arch/powerpc/kernel/irq.c
+++ b/arch/powerpc/kernel/irq.c
@@ -229,6 +229,19 @@ notrace void arch_local_irq_restore(unsigned long en)
         */
        if (unlikely(irq_happened != PACA_IRQ_HARD_DIS))
                __hard_irq_disable();
+#ifdef CONFIG_TRACE_IRQFLAG
+        else {
+                /*
+                 * We should already be hard disabled here. We had bugs
+                 * where that wasn't the case so let's dbl check it and
+                 * warn if we are wrong. Only do that when IRQ tracing
+                 * is enabled as mfmsr() can be costly.
+                 */
+                if (WARN_ON(mfmsr() & MSR_EE))
+                        __hard_irq_disable();
+        }
+#endif /* CONFIG_TRACE_IRQFLAG */
        set_soft_enabled(0);
        /*
@@ -260,11 +273,17 @@ EXPORT_SYMBOL(arch_local_irq_restore);
 * if they are currently disabled. This is typically called before
 * schedule() or do_signal() when returning to userspace. We do it
 * in C to avoid the burden of dealing with lockdep etc...
+ *
+ * NOTE: This is called with interrupts hard disabled but not marked
+ * as such in paca->irq_happened, so we need to resync this.
 */
 void restore_interrupts(void)
 {
-        if (irqs_disabled())
+        if (irqs_disabled()) {
+                local_paca->irq_happened |= PACA_IRQ_HARD_DIS;
                local_irq_enable();
+        } else
+                __hard_irq_enable();
 }
 #endif /* CONFIG_PPC64 */
@@ -330,14 +349,10 @@ void migrate_irqs(void)
        alloc_cpumask_var(&mask, GFP_KERNEL);
-        for_each_irq(irq) {
+        for_each_irq_desc(irq, desc) {
                struct irq_data *data;
                struct irq_chip *chip;
-                desc = irq_to_desc(irq);
-                if (!desc)
-                        continue;
                data = irq_desc_get_irq_data(desc);
                if (irqd_is_per_cpu(data))
                        continue;
@@ -560,12 +575,6 @@ void do_softirq(void)
        local_irq_restore(flags);
 }
-irq_hw_number_t irqd_to_hwirq(struct irq_data *d)
-{
-        return d->hwirq;
-}
-EXPORT_SYMBOL_GPL(irqd_to_hwirq);
 irq_hw_number_t virq_to_hw(unsigned int virq)
 {
        struct irq_data *irq_data = irq_get_irq_data(virq);
diff --git a/arch/powerpc/kernel/machine_kexec.c b/arch/powerpc/kernel/machine_kexec.c
index c957b1202bdc..5df777794403 100644
--- a/arch/powerpc/kernel/machine_kexec.c
+++ b/arch/powerpc/kernel/machine_kexec.c
@@ -23,14 +23,11 @@
 void machine_kexec_mask_interrupts(void) {
        unsigned int i;
+        struct irq_desc *desc;
-        for_each_irq(i) {
+        for_each_irq_desc(i, desc) {
-                struct irq_desc *desc = irq_to_desc(i);
                struct irq_chip *chip;
-                if (!desc)
-                        continue;
                chip = irq_desc_get_chip(desc);
                if (!chip)
                        continue;
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index f88698c0f332..aa05935b6947 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -1235,7 +1235,7 @@ void __ppc64_runlatch_on(void)
        ctrl |= CTRL_RUNLATCH;
        mtspr(SPRN_CTRLT, ctrl);
-        ti->local_flags |= TLF_RUNLATCH;
+        ti->local_flags |= _TLF_RUNLATCH;
 }
 /* Called with hard IRQs off */
@@ -1244,7 +1244,7 @@ void __ppc64_runlatch_off(void)
        struct thread_info *ti = current_thread_info();
        unsigned long ctrl;
-        ti->local_flags &= ~TLF_RUNLATCH;
+        ti->local_flags &= ~_TLF_RUNLATCH;
        ctrl = mfspr(SPRN_CTRLF);
        ctrl &= ~CTRL_RUNLATCH;
@@ -1252,37 +1252,6 @@ void __ppc64_runlatch_off(void)
 }
 #endif /* CONFIG_PPC64 */
-#if THREAD_SHIFT < PAGE_SHIFT
-static struct kmem_cache *thread_info_cache;
-struct thread_info *alloc_thread_info_node(struct task_struct *tsk, int node)
-{
-        struct thread_info *ti;
-        ti = kmem_cache_alloc_node(thread_info_cache, GFP_KERNEL, node);
-        if (unlikely(ti == NULL))
-                return NULL;
-#ifdef CONFIG_DEBUG_STACK_USAGE
-        memset(ti, 0, THREAD_SIZE);
-#endif
-        return ti;
-}
-void free_thread_info(struct thread_info *ti)
-{
-        kmem_cache_free(thread_info_cache, ti);
-}
-void thread_info_cache_init(void)
-{
-        thread_info_cache = kmem_cache_create("thread_info", THREAD_SIZE,
-                                              THREAD_SIZE, 0, NULL);
-        BUG_ON(thread_info_cache == NULL);
-}
-#endif /* THREAD_SHIFT < PAGE_SHIFT */
 unsigned long arch_align_stack(unsigned long sp)
 {
        if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
diff --git a/arch/powerpc/kernel/ptrace.c b/arch/powerpc/kernel/ptrace.c
index 8d8e028893be..dd5e214cdf21 100644
--- a/arch/powerpc/kernel/ptrace.c
+++ b/arch/powerpc/kernel/ptrace.c
@@ -1710,7 +1710,7 @@ long do_syscall_trace_enter(struct pt_regs *regs)
 {
        long ret = 0;
-        secure_computing(regs->gpr[0]);
+        secure_computing_strict(regs->gpr[0]);
        if (test_thread_flag(TIF_SYSCALL_TRACE) &&
            tracehook_report_syscall_entry(regs))
diff --git a/arch/powerpc/kernel/setup_32.c b/arch/powerpc/kernel/setup_32.c
index 9825f29d1faf..ec8a53fa9e8f 100644
--- a/arch/powerpc/kernel/setup_32.c
+++ b/arch/powerpc/kernel/setup_32.c
@@ -150,6 +150,9 @@ notrace void __init machine_init(u64 dt_ptr)
 }
 #ifdef CONFIG_BOOKE_WDT
+extern u32 booke_wdt_enabled;
+extern u32 booke_wdt_period;
 /* Checks wdt=x and wdt_period=xx command-line option */
 notrace int __init early_parse_wdt(char *p)
 {
diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c
index d9f94410fd7f..e4cb34322de4 100644
--- a/arch/powerpc/kernel/smp.c
+++ b/arch/powerpc/kernel/smp.c
@@ -57,27 +57,9 @@
 #define DBG(fmt...)
 #endif
-/* Store all idle threads, this can be reused instead of creating
-* a new thread. Also avoids complicated thread destroy functionality
-* for idle threads.
-*/
 #ifdef CONFIG_HOTPLUG_CPU
-/*
- * Needed only for CONFIG_HOTPLUG_CPU because __cpuinitdata is
- * removed after init for !CONFIG_HOTPLUG_CPU.
- */
-static DEFINE_PER_CPU(struct task_struct *, idle_thread_array);
-#define get_idle_for_cpu(x)      (per_cpu(idle_thread_array, x))
-#define set_idle_for_cpu(x, p)   (per_cpu(idle_thread_array, x) = (p))
 /* State of each CPU during hotplug phases */
 static DEFINE_PER_CPU(int, cpu_state) = { 0 };
-#else
-static struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ;
-#define get_idle_for_cpu(x)      (idle_thread_array[(x)])
-#define set_idle_for_cpu(x, p)   (idle_thread_array[(x)] = (p))
 #endif
 struct thread_info *secondary_ti;
@@ -429,60 +411,19 @@ int generic_check_cpu_restart(unsigned int cpu)
 }
 #endif
-struct create_idle {
+static void cpu_idle_thread_init(unsigned int cpu, struct task_struct *idle)
-        struct work_struct work;
-        struct task_struct *idle;
-        struct completion done;
-        int cpu;
-};
-static void __cpuinit do_fork_idle(struct work_struct *work)
 {
-        struct create_idle *c_idle =
+        struct thread_info *ti = task_thread_info(idle);
-                container_of(work, struct create_idle, work);
-        c_idle->idle = fork_idle(c_idle->cpu);
-        complete(&c_idle->done);
-}
-static int __cpuinit create_idle(unsigned int cpu)
-{
-        struct thread_info *ti;
-        struct create_idle c_idle = {
-                .cpu    = cpu,
-                .done   = COMPLETION_INITIALIZER_ONSTACK(c_idle.done),
-        };
-        INIT_WORK_ONSTACK(&c_idle.work, do_fork_idle);
-        c_idle.idle = get_idle_for_cpu(cpu);
-        /* We can't use kernel_thread since we must avoid to
-         * reschedule the child. We use a workqueue because
-         * we want to fork from a kernel thread, not whatever
-         * userspace process happens to be trying to online us.
-         */
-        if (!c_idle.idle) {
-                schedule_work(&c_idle.work);
-                wait_for_completion(&c_idle.done);
-        } else
-                init_idle(c_idle.idle, cpu);
-        if (IS_ERR(c_idle.idle)) {              
-                pr_err("Failed fork for CPU %u: %li", cpu, PTR_ERR(c_idle.idle));
-                return PTR_ERR(c_idle.idle);
-        }
-        ti = task_thread_info(c_idle.idle);
 #ifdef CONFIG_PPC64
-        paca[cpu].__current = c_idle.idle;
+        paca[cpu].__current = idle;
        paca[cpu].kstack = (unsigned long)ti + THREAD_SIZE - STACK_FRAME_OVERHEAD;
 #endif
        ti->cpu = cpu;
-        current_set[cpu] = ti;
+        secondary_ti = current_set[cpu] = ti;
-        return 0;
 }
-int __cpuinit __cpu_up(unsigned int cpu)
+int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *tidle)
 {
        int rc, c;
@@ -490,12 +431,7 @@ int __cpuinit __cpu_up(unsigned int cpu)
            (smp_ops->cpu_bootable && !smp_ops->cpu_bootable(cpu)))
                return -EINVAL;
-        /* Make sure we have an idle thread */
+        cpu_idle_thread_init(cpu, tidle);
-        rc = create_idle(cpu);
-        if (rc)
-                return rc;
-        secondary_ti = current_set[cpu];
        /* Make sure callin-map entry is 0 (can be leftover a CPU
         * hotplug
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index 6aa0c663e247..158972341a2d 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -248,7 +248,7 @@ void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr)
                                   addr, regs->nip, regs->link, code);
        }
-        if (!arch_irq_disabled_regs(regs))
+        if (arch_irqs_disabled() && !arch_irq_disabled_regs(regs))
                local_irq_enable();
        memset(&info, 0, sizeof(info));
@@ -1019,7 +1019,9 @@ void __kprobes program_check_exception(struct pt_regs *regs)
                return;
        }
-        local_irq_enable();
+        /* We restore the interrupt state now */
+        if (!arch_irq_disabled_regs(regs))
+                local_irq_enable();
 #ifdef CONFIG_MATH_EMULATION
        /* (reason & REASON_ILLEGAL) would be the obvious thing here,
@@ -1069,6 +1071,10 @@ void alignment_exception(struct pt_regs *regs)
 {
        int sig, code, fixed = 0;
+        /* We restore the interrupt state now */
+        if (!arch_irq_disabled_regs(regs))
+                local_irq_enable();
        /* we don't implement logging of alignment exceptions */
        if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS))
                fixed = fix_alignment(regs);
diff --git a/arch/powerpc/kvm/book3s_64_mmu_host.c b/arch/powerpc/kvm/book3s_64_mmu_host.c
index 6f87f39a1ac2..10fc8ec9d2a8 100644
--- a/arch/powerpc/kvm/book3s_64_mmu_host.c
+++ b/arch/powerpc/kvm/book3s_64_mmu_host.c
@@ -194,14 +194,14 @@ static struct kvmppc_sid_map *create_sid_map(struct kvm_vcpu *vcpu, u64 gvsid)
        backwards_map = !backwards_map;
        /* Uh-oh ... out of mappings. Let's flush! */
-        if (vcpu_book3s->vsid_next == vcpu_book3s->vsid_max) {
+        if (vcpu_book3s->proto_vsid_next == vcpu_book3s->proto_vsid_max) {
-                vcpu_book3s->vsid_next = vcpu_book3s->vsid_first;
+                vcpu_book3s->proto_vsid_next = vcpu_book3s->proto_vsid_first;
                memset(vcpu_book3s->sid_map, 0,
                       sizeof(struct kvmppc_sid_map) * SID_MAP_NUM);
                kvmppc_mmu_pte_flush(vcpu, 0, 0);
                kvmppc_mmu_flush_segments(vcpu);
        }
-        map->host_vsid = vcpu_book3s->vsid_next++;
+        map->host_vsid = vsid_scramble(vcpu_book3s->proto_vsid_next++, 256M);
        map->guest_vsid = gvsid;
        map->valid = true;
@@ -319,9 +319,10 @@ int kvmppc_mmu_init(struct kvm_vcpu *vcpu)
                return -1;
        vcpu3s->context_id[0] = err;
-        vcpu3s->vsid_max = ((vcpu3s->context_id[0] + 1) << USER_ESID_BITS) - 1;
+        vcpu3s->proto_vsid_max = ((vcpu3s->context_id[0] + 1)
-        vcpu3s->vsid_first = vcpu3s->context_id[0] << USER_ESID_BITS;
+                                  << USER_ESID_BITS) - 1;
-        vcpu3s->vsid_next = vcpu3s->vsid_first;
+        vcpu3s->proto_vsid_first = vcpu3s->context_id[0] << USER_ESID_BITS;
+        vcpu3s->proto_vsid_next = vcpu3s->proto_vsid_first;
        kvmppc_mmu_hpte_init(vcpu);
diff --git a/arch/powerpc/kvm/book3s_64_mmu_hv.c b/arch/powerpc/kvm/book3s_64_mmu_hv.c
index ddc485a529f2..c3beaeef3f60 100644
--- a/arch/powerpc/kvm/book3s_64_mmu_hv.c
+++ b/arch/powerpc/kvm/book3s_64_mmu_hv.c
@@ -258,6 +258,8 @@ static long kvmppc_get_guest_page(struct kvm *kvm, unsigned long gfn,
                            !(memslot->userspace_addr & (s - 1))) {
                                start &= ~(s - 1);
                                pgsize = s;
+                                get_page(hpage);
+                                put_page(page);
                                page = hpage;
                        }
                }
@@ -281,11 +283,8 @@ static long kvmppc_get_guest_page(struct kvm *kvm, unsigned long gfn,
        err = 0;
 out:
-        if (got) {
+        if (got)
-                if (PageHuge(page))
-                        page = compound_head(page);
                put_page(page);
-        }
        return err;
 up_err:
@@ -678,8 +677,15 @@ int kvmppc_book3s_hv_page_fault(struct kvm_run *run, struct kvm_vcpu *vcpu,
                SetPageDirty(page);
 out_put:
-        if (page)
+        if (page) {
-                put_page(page);
+                /*
+                 * We drop pages[0] here, not page because page might
+                 * have been set to the head page of a compound, but
+                 * we have to drop the reference on the correct tail
+                 * page to match the get inside gup()
+                 */
+                put_page(pages[0]);
+        }
        return ret;
 out_unlock:
@@ -979,6 +985,7 @@ void *kvmppc_pin_guest_page(struct kvm *kvm, unsigned long gpa,
                        pa = *physp;
                }
                page = pfn_to_page(pa >> PAGE_SHIFT);
+                get_page(page);
        } else {
                hva = gfn_to_hva_memslot(memslot, gfn);
                npages = get_user_pages_fast(hva, 1, 1, pages);
@@ -991,8 +998,6 @@ void *kvmppc_pin_guest_page(struct kvm *kvm, unsigned long gpa,
                page = compound_head(page);
                psize <<= compound_order(page);
        }
-        if (!kvm->arch.using_mmu_notifiers)
-                get_page(page);
        offset = gpa & (psize - 1);
        if (nb_ret)
                *nb_ret = psize - offset;
@@ -1003,7 +1008,6 @@ void kvmppc_unpin_guest_page(struct kvm *kvm, void *va)
 {
        struct page *page = virt_to_page(va);
-        page = compound_head(page);
        put_page(page);
 }
diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
index 01294a5099dd..108d1f580177 100644
--- a/arch/powerpc/kvm/book3s_hv.c
+++ b/arch/powerpc/kvm/book3s_hv.c
@@ -1192,8 +1192,6 @@ static void unpin_slot(struct kvm *kvm, int slot_id)
                                continue;
                        pfn = physp[j] >> PAGE_SHIFT;
                        page = pfn_to_page(pfn);
-                        if (PageHuge(page))
-                                page = compound_head(page);
                        SetPageDirty(page);
                        put_page(page);
                }
diff --git a/arch/powerpc/kvm/book3s_hv_rm_mmu.c b/arch/powerpc/kvm/book3s_hv_rm_mmu.c
index def880aea63a..cec4daddbf31 100644
--- a/arch/powerpc/kvm/book3s_hv_rm_mmu.c
+++ b/arch/powerpc/kvm/book3s_hv_rm_mmu.c
@@ -463,6 +463,7 @@ long kvmppc_h_bulk_remove(struct kvm_vcpu *vcpu)
                                /* insert R and C bits from PTE */
                                rcbits = rev->guest_rpte & (HPTE_R_R|HPTE_R_C);
                                args[j] |= rcbits << (56 - 5);
+                                hp[0] = 0;
                                continue;
                        }
diff --git a/arch/powerpc/kvm/book3s_segment.S b/arch/powerpc/kvm/book3s_segment.S
index 0676ae249b9f..6e6e9cef34a8 100644
--- a/arch/powerpc/kvm/book3s_segment.S
+++ b/arch/powerpc/kvm/book3s_segment.S
@@ -197,7 +197,8 @@ kvmppc_interrupt:
        /* Save guest PC and MSR */
 #ifdef CONFIG_PPC64
 BEGIN_FTR_SECTION
-        andi.   r0,r12,0x2
+        andi.   r0, r12, 0x2
+        cmpwi   cr1, r0, 0
        beq     1f
        mfspr   r3,SPRN_HSRR0
        mfspr   r4,SPRN_HSRR1
@@ -250,6 +251,12 @@ END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
        beq     ld_last_prev_inst
        cmpwi   r12, BOOK3S_INTERRUPT_ALIGNMENT
        beq-    ld_last_inst
+#ifdef CONFIG_PPC64
+BEGIN_FTR_SECTION
+        cmpwi   r12, BOOK3S_INTERRUPT_H_EMUL_ASSIST
+        beq-    ld_last_inst
+END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
+#endif
        b       no_ld_last_inst
@@ -316,23 +323,17 @@ no_dcbz32_off:
         * Having set up SRR0/1 with the address where we want
         * to continue with relocation on (potentially in module
         * space), we either just go straight there with rfi[d],
-         * or we jump to an interrupt handler with bctr if there
+         * or we jump to an interrupt handler if there is an
-         * is an interrupt to be handled first.  In the latter
+         * interrupt to be handled first.  In the latter case,
-         * case, the rfi[d] at the end of the interrupt handler
+         * the rfi[d] at the end of the interrupt handler will
-         * will get us back to where we want to continue.
+         * get us back to where we want to continue.
         */
-        cmpwi   r12, BOOK3S_INTERRUPT_EXTERNAL
-        beq     1f
-        cmpwi   r12, BOOK3S_INTERRUPT_DECREMENTER
-        beq     1f
-        cmpwi   r12, BOOK3S_INTERRUPT_PERFMON
-1:      mtctr   r12
        /* Register usage at this point:
         *
         * R1       = host R1
         * R2       = host R2
+         * R10      = raw exit handler id
         * R12      = exit handler id
         * R13      = shadow vcpu (32-bit) or PACA (64-bit)
         * SVCPU.*  = guest *
@@ -342,12 +343,25 @@ no_dcbz32_off:
        PPC_LL  r6, HSTATE_HOST_MSR(r13)
        PPC_LL  r8, HSTATE_VMHANDLER(r13)
-        /* Restore host msr -> SRR1 */
+#ifdef CONFIG_PPC64
+BEGIN_FTR_SECTION
+        beq     cr1, 1f
+        mtspr   SPRN_HSRR1, r6
+        mtspr   SPRN_HSRR0, r8
+END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
+#endif
+1:      /* Restore host msr -> SRR1 */
        mtsrr1  r6
        /* Load highmem handler address */
        mtsrr0  r8
        /* RFI into the highmem handler, or jump to interrupt handler */
-        beqctr
+        cmpwi   r12, BOOK3S_INTERRUPT_EXTERNAL
+        beqa    BOOK3S_INTERRUPT_EXTERNAL
+        cmpwi   r12, BOOK3S_INTERRUPT_DECREMENTER
+        beqa    BOOK3S_INTERRUPT_DECREMENTER
+        cmpwi   r12, BOOK3S_INTERRUPT_PERFMON
+        beqa    BOOK3S_INTERRUPT_PERFMON
        RFI
 kvmppc_handler_trampoline_exit_end:
diff --git a/arch/powerpc/mm/hugetlbpage.c b/arch/powerpc/mm/hugetlbpage.c
index fb05b123218f..1a6de0a7d8eb 100644
--- a/arch/powerpc/mm/hugetlbpage.c
+++ b/arch/powerpc/mm/hugetlbpage.c
@@ -271,7 +271,8 @@ int alloc_bootmem_huge_page(struct hstate *hstate)
 unsigned long gpage_npages[MMU_PAGE_COUNT];
-static int __init do_gpage_early_setup(char *param, char *val)
+static int __init do_gpage_early_setup(char *param, char *val,
+                                       const char *unused)
 {
        static phys_addr_t size;
        unsigned long npages;
diff --git a/arch/powerpc/net/bpf_jit.h b/arch/powerpc/net/bpf_jit.h
index af1ab5e9a691..5c3cf2d04e41 100644
--- a/arch/powerpc/net/bpf_jit.h
+++ b/arch/powerpc/net/bpf_jit.h
@@ -48,7 +48,13 @@
 /*
 * Assembly helpers from arch/powerpc/net/bpf_jit.S:
 */
-extern u8 sk_load_word[], sk_load_half[], sk_load_byte[], sk_load_byte_msh[];
+#define DECLARE_LOAD_FUNC(func) \
+        extern u8 func[], func##_negative_offset[], func##_positive_offset[]
+DECLARE_LOAD_FUNC(sk_load_word);
+DECLARE_LOAD_FUNC(sk_load_half);
+DECLARE_LOAD_FUNC(sk_load_byte);
+DECLARE_LOAD_FUNC(sk_load_byte_msh);
 #define FUNCTION_DESCR_SIZE     24
diff --git a/arch/powerpc/net/bpf_jit_64.S b/arch/powerpc/net/bpf_jit_64.S
index ff4506e85cce..55ba3855a97f 100644
--- a/arch/powerpc/net/bpf_jit_64.S
+++ b/arch/powerpc/net/bpf_jit_64.S
@@ -31,14 +31,13 @@
 * then branch directly to slow_path_XXX if required.  (In fact, could
 * load a spare GPR with the address of slow_path_generic and pass size
 * as an argument, making the call site a mtlr, li and bllr.)
- *
- * Technically, the "is addr < 0" check is unnecessary & slowing down
- * the ABS path, as it's statically checked on generation.
 */
        .globl  sk_load_word
 sk_load_word:
        cmpdi   r_addr, 0
-        blt     bpf_error
+        blt     bpf_slow_path_word_neg
+        .globl  sk_load_word_positive_offset
+sk_load_word_positive_offset:
        /* Are we accessing past headlen? */
        subi    r_scratch1, r_HL, 4
        cmpd    r_scratch1, r_addr
@@ -51,7 +50,9 @@ sk_load_word:
        .globl  sk_load_half
 sk_load_half:
        cmpdi   r_addr, 0
-        blt     bpf_error
+        blt     bpf_slow_path_half_neg
+        .globl  sk_load_half_positive_offset
+sk_load_half_positive_offset:
        subi    r_scratch1, r_HL, 2
        cmpd    r_scratch1, r_addr
        blt     bpf_slow_path_half
@@ -61,7 +62,9 @@ sk_load_half:
        .globl  sk_load_byte
 sk_load_byte:
        cmpdi   r_addr, 0
-        blt     bpf_error
+        blt     bpf_slow_path_byte_neg
+        .globl  sk_load_byte_positive_offset
+sk_load_byte_positive_offset:
        cmpd    r_HL, r_addr
        ble     bpf_slow_path_byte
        lbzx    r_A, r_D, r_addr
@@ -69,22 +72,20 @@ sk_load_byte:
 /*
 * BPF_S_LDX_B_MSH: ldxb  4*([offset]&0xf)
- * r_addr is the offset value, already known positive
+ * r_addr is the offset value
 */
        .globl sk_load_byte_msh
 sk_load_byte_msh:
+        cmpdi   r_addr, 0
+        blt     bpf_slow_path_byte_msh_neg
+        .globl sk_load_byte_msh_positive_offset
+sk_load_byte_msh_positive_offset:
        cmpd    r_HL, r_addr
        ble     bpf_slow_path_byte_msh
        lbzx    r_X, r_D, r_addr
        rlwinm  r_X, r_X, 2, 32-4-2, 31-2
        blr
-bpf_error:
-        /* Entered with cr0 = lt */
-        li      r3, 0
-        /* Generated code will 'blt epilogue', returning 0. */
-        blr
 /* Call out to skb_copy_bits:
 * We'll need to back up our volatile regs first; we have
 * local variable space at r1+(BPF_PPC_STACK_BASIC).
@@ -136,3 +137,84 @@ bpf_slow_path_byte_msh:
        lbz     r_X, BPF_PPC_STACK_BASIC+(2*8)(r1)
        rlwinm  r_X, r_X, 2, 32-4-2, 31-2
        blr
+/* Call out to bpf_internal_load_pointer_neg_helper:
+ * We'll need to back up our volatile regs first; we have
+ * local variable space at r1+(BPF_PPC_STACK_BASIC).
+ * Allocate a new stack frame here to remain ABI-compliant in
+ * stashing LR.
+ */
+#define sk_negative_common(SIZE)                                \
+        mflr    r0;                                             \
+        std     r0, 16(r1);                                     \
+        /* R3 goes in parameter space of caller's frame */      \
+        std     r_skb, (BPF_PPC_STACKFRAME+48)(r1);             \
+        std     r_A, (BPF_PPC_STACK_BASIC+(0*8))(r1);           \
+        std     r_X, (BPF_PPC_STACK_BASIC+(1*8))(r1);           \
+        stdu    r1, -BPF_PPC_SLOWPATH_FRAME(r1);                \
+        /* R3 = r_skb, as passed */                             \
+        mr      r4, r_addr;                                     \
+        li      r5, SIZE;                                       \
+        bl      bpf_internal_load_pointer_neg_helper;           \
+        /* R3 != 0 on success */                                \
+        addi    r1, r1, BPF_PPC_SLOWPATH_FRAME;                 \
+        ld      r0, 16(r1);                                     \
+        ld      r_A, (BPF_PPC_STACK_BASIC+(0*8))(r1);           \
+        ld      r_X, (BPF_PPC_STACK_BASIC+(1*8))(r1);           \
+        mtlr    r0;                                             \
+        cmpldi  r3, 0;                                          \
+        beq     bpf_error_slow; /* cr0 = EQ */                  \
+        mr      r_addr, r3;                                     \
+        ld      r_skb, (BPF_PPC_STACKFRAME+48)(r1);             \
+        /* Great success! */
+bpf_slow_path_word_neg:
+        lis     r_scratch1,-32  /* SKF_LL_OFF */
+        cmpd    r_addr, r_scratch1      /* addr < SKF_* */
+        blt     bpf_error       /* cr0 = LT */
+        .globl  sk_load_word_negative_offset
+sk_load_word_negative_offset:
+        sk_negative_common(4)
+        lwz     r_A, 0(r_addr)
+        blr
+bpf_slow_path_half_neg:
+        lis     r_scratch1,-32  /* SKF_LL_OFF */
+        cmpd    r_addr, r_scratch1      /* addr < SKF_* */
+        blt     bpf_error       /* cr0 = LT */
+        .globl  sk_load_half_negative_offset
+sk_load_half_negative_offset:
+        sk_negative_common(2)
+        lhz     r_A, 0(r_addr)
+        blr
+bpf_slow_path_byte_neg:
+        lis     r_scratch1,-32  /* SKF_LL_OFF */
+        cmpd    r_addr, r_scratch1      /* addr < SKF_* */
+        blt     bpf_error       /* cr0 = LT */
+        .globl  sk_load_byte_negative_offset
+sk_load_byte_negative_offset:
+        sk_negative_common(1)
+        lbz     r_A, 0(r_addr)
+        blr
+bpf_slow_path_byte_msh_neg:
+        lis     r_scratch1,-32  /* SKF_LL_OFF */
+        cmpd    r_addr, r_scratch1      /* addr < SKF_* */
+        blt     bpf_error       /* cr0 = LT */
+        .globl  sk_load_byte_msh_negative_offset
+sk_load_byte_msh_negative_offset:
+        sk_negative_common(1)
+        lbz     r_X, 0(r_addr)
+        rlwinm  r_X, r_X, 2, 32-4-2, 31-2
+        blr
+bpf_error_slow:
+        /* fabricate a cr0 = lt */
+        li      r_scratch1, -1
+        cmpdi   r_scratch1, 0
+bpf_error:
+        /* Entered with cr0 = lt */
+        li      r3, 0
+        /* Generated code will 'blt epilogue', returning 0. */
+        blr
diff --git a/arch/powerpc/net/bpf_jit_comp.c b/arch/powerpc/net/bpf_jit_comp.c
index 73619d3aeb6c..2dc8b1484845 100644
--- a/arch/powerpc/net/bpf_jit_comp.c
+++ b/arch/powerpc/net/bpf_jit_comp.c
@@ -127,6 +127,9 @@ static void bpf_jit_build_epilogue(u32 *image, struct codegen_context *ctx)
        PPC_BLR();
 }
+#define CHOOSE_LOAD_FUNC(K, func) \
+        ((int)K < 0 ? ((int)K >= SKF_LL_OFF ? func##_negative_offset : func) : func##_positive_offset)
 /* Assemble the body code between the prologue & epilogue. */
 static int bpf_jit_build_body(struct sk_filter *fp, u32 *image,
                              struct codegen_context *ctx,
@@ -391,21 +394,16 @@ static int bpf_jit_build_body(struct sk_filter *fp, u32 *image,
                        /*** Absolute loads from packet header/data ***/
                case BPF_S_LD_W_ABS:
-                        func = sk_load_word;
+                        func = CHOOSE_LOAD_FUNC(K, sk_load_word);
                        goto common_load;
                case BPF_S_LD_H_ABS:
-                        func = sk_load_half;
+                        func = CHOOSE_LOAD_FUNC(K, sk_load_half);
                        goto common_load;
                case BPF_S_LD_B_ABS:
-                        func = sk_load_byte;
+                        func = CHOOSE_LOAD_FUNC(K, sk_load_byte);
                common_load:
-                        /*
+                        /* Load from [K]. */
-                         * Load from [K].  Reference with the (negative)
-                         * SKF_NET_OFF/SKF_LL_OFF offsets is unsupported.
-                         */
                        ctx->seen |= SEEN_DATAREF;
-                        if ((int)K < 0)
-                                return -ENOTSUPP;
                        PPC_LI64(r_scratch1, func);
                        PPC_MTLR(r_scratch1);
                        PPC_LI32(r_addr, K);
@@ -429,7 +427,7 @@ static int bpf_jit_build_body(struct sk_filter *fp, u32 *image,
                common_load_ind:
                        /*
                         * Load from [X + K].  Negative offsets are tested for
-                         * in the helper functions, and result in a 'ret 0'.
+                         * in the helper functions.
                         */
                        ctx->seen |= SEEN_DATAREF | SEEN_XREG;
                        PPC_LI64(r_scratch1, func);
@@ -443,13 +441,7 @@ static int bpf_jit_build_body(struct sk_filter *fp, u32 *image,
                        break;
                case BPF_S_LDX_B_MSH:
-                        /*
+                        func = CHOOSE_LOAD_FUNC(K, sk_load_byte_msh);
-                         * x86 version drops packet (RET 0) when K<0, whereas
-                         * interpreter does allow K<0 (__load_pointer, special
-                         * ancillary data).  common_load returns ENOTSUPP if K<0,
-                         * so we fall back to interpreter & filter works.
-                         */
-                        func = sk_load_byte_msh;
                        goto common_load;
                        break;
diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c
index 02aee03e713c..8f84bcba18da 100644
--- a/arch/powerpc/perf/core-book3s.c
+++ b/arch/powerpc/perf/core-book3s.c
@@ -1299,8 +1299,7 @@ static void record_and_restart(struct perf_event *event, unsigned long val,
        if (record) {
                struct perf_sample_data data;
-                perf_sample_data_init(&data, ~0ULL);
+                perf_sample_data_init(&data, ~0ULL, event->hw.last_period);
-                data.period = event->hw.last_period;
                if (event->attr.sample_type & PERF_SAMPLE_ADDR)
                        perf_get_data_addr(regs, &data.addr);
diff --git a/arch/powerpc/perf/core-fsl-emb.c b/arch/powerpc/perf/core-fsl-emb.c
index 0a6d2a9d569c..106c53354675 100644
--- a/arch/powerpc/perf/core-fsl-emb.c
+++ b/arch/powerpc/perf/core-fsl-emb.c
@@ -613,8 +613,7 @@ static void record_and_restart(struct perf_event *event, unsigned long val,
        if (record) {
                struct perf_sample_data data;
-                perf_sample_data_init(&data, 0);
+                perf_sample_data_init(&data, 0, event->hw.last_period);
-                data.period = event->hw.last_period;
                if (perf_event_overflow(event, &data, regs))
                        fsl_emb_pmu_stop(event, 0);
diff --git a/arch/powerpc/platforms/85xx/common.c b/arch/powerpc/platforms/85xx/common.c
index 9fef5302adc1..67dac22b4363 100644
--- a/arch/powerpc/platforms/85xx/common.c
+++ b/arch/powerpc/platforms/85xx/common.c
@@ -21,6 +21,12 @@ static struct of_device_id __initdata mpc85xx_common_ids[] = {
        { .compatible = "fsl,qe", },
        { .compatible = "fsl,cpm2", },
        { .compatible = "fsl,srio", },
+        /* So that the DMA channel nodes can be probed individually: */
+        { .compatible = "fsl,eloplus-dma", },
+        /* For the PMC driver */
+        { .compatible = "fsl,mpc8548-guts", },
+        /* Probably unnecessary? */
+        { .compatible = "gpio-leds", },
        {},
 };
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index 9a6f04406e0d..d208ebccb91c 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -399,12 +399,6 @@ static int __init board_fixups(void)
 machine_arch_initcall(mpc8568_mds, board_fixups);
 machine_arch_initcall(mpc8569_mds, board_fixups);
-static struct of_device_id mpc85xx_ids[] = {
-        { .compatible = "fsl,mpc8548-guts", },
-        { .compatible = "gpio-leds", },
-        {},
-};
 static int __init mpc85xx_publish_devices(void)
 {
        if (machine_is(mpc8568_mds))
@@ -412,10 +406,7 @@ static int __init mpc85xx_publish_devices(void)
        if (machine_is(mpc8569_mds))
                simple_gpiochip_init("fsl,mpc8569mds-bcsr-gpio");
-        mpc85xx_common_publish_devices();
+        return mpc85xx_common_publish_devices();
-        of_platform_bus_probe(NULL, mpc85xx_ids, NULL);
-        return 0;
 }
 machine_device_initcall(mpc8568_mds, mpc85xx_publish_devices);
diff --git a/arch/powerpc/platforms/85xx/p1022_ds.c b/arch/powerpc/platforms/85xx/p1022_ds.c
index e74b7cde9aee..f700c81a1321 100644
--- a/arch/powerpc/platforms/85xx/p1022_ds.c
+++ b/arch/powerpc/platforms/85xx/p1022_ds.c
@@ -460,18 +460,7 @@ static void __init p1022_ds_setup_arch(void)
        pr_info("Freescale P1022 DS reference board\n");
 }
-static struct of_device_id __initdata p1022_ds_ids[] = {
+machine_device_initcall(p1022_ds, mpc85xx_common_publish_devices);
-        /* So that the DMA channel nodes can be probed individually: */
-        { .compatible = "fsl,eloplus-dma", },
-        {},
-};
-static int __init p1022_ds_publish_devices(void)
-{
-        mpc85xx_common_publish_devices();
-        return of_platform_bus_probe(NULL, p1022_ds_ids, NULL);
-}
-machine_device_initcall(p1022_ds, p1022_ds_publish_devices);
 machine_arch_initcall(p1022_ds, swiotlb_setup_bus_notifier);
diff --git a/arch/powerpc/platforms/cell/axon_msi.c b/arch/powerpc/platforms/cell/axon_msi.c
index db360fc4cf0e..85825b5401e5 100644
--- a/arch/powerpc/platforms/cell/axon_msi.c
+++ b/arch/powerpc/platforms/cell/axon_msi.c
@@ -114,7 +114,7 @@ static void axon_msi_cascade(unsigned int irq, struct irq_desc *desc)
                pr_devel("axon_msi: woff %x roff %x msi %x\n",
                          write_offset, msic->read_offset, msi);
-                if (msi < NR_IRQS && irq_get_chip_data(msi) == msic) {
+                if (msi < nr_irqs && irq_get_chip_data(msi) == msic) {
                        generic_handle_irq(msi);
                        msic->fifo_virt[idx] = cpu_to_le32(0xffffffff);
                } else {
@@ -276,9 +276,6 @@ static int axon_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
        if (rc)
                return rc;
-        /* We rely on being able to stash a virq in a u16 */
-        BUILD_BUG_ON(NR_IRQS > 65536);
        list_for_each_entry(entry, &dev->msi_list, list) {
                virq = irq_create_direct_mapping(msic->irq_domain);
                if (virq == NO_IRQ) {
@@ -392,7 +389,8 @@ static int axon_msi_probe(struct platform_device *device)
        }
        memset(msic->fifo_virt, 0xff, MSIC_FIFO_SIZE_BYTES);
-        msic->irq_domain = irq_domain_add_nomap(dn, &msic_host_ops, msic);
+        /* We rely on being able to stash a virq in a u16, so limit irqs to < 65536 */
+        msic->irq_domain = irq_domain_add_nomap(dn, 65536, &msic_host_ops, msic);
        if (!msic->irq_domain) {
                printk(KERN_ERR "axon_msi: couldn't allocate irq_domain for %s\n",
                       dn->full_name);
diff --git a/arch/powerpc/platforms/cell/beat_interrupt.c b/arch/powerpc/platforms/cell/beat_interrupt.c
index e5c3a2c6090d..8c6dc42ecf65 100644
--- a/arch/powerpc/platforms/cell/beat_interrupt.c
+++ b/arch/powerpc/platforms/cell/beat_interrupt.c
@@ -239,7 +239,7 @@ void __init beatic_init_IRQ(void)
        ppc_md.get_irq = beatic_get_irq;
        /* Allocate an irq host */
-        beatic_host = irq_domain_add_nomap(NULL, &beatic_pic_host_ops, NULL);
+        beatic_host = irq_domain_add_nomap(NULL, 0, &beatic_pic_host_ops, NULL);
        BUG_ON(beatic_host == NULL);
        irq_set_default_host(beatic_host);
 }
@@ -248,6 +248,6 @@ void beatic_deinit_IRQ(void)
 {
        int     i;
-        for (i = 1; i < NR_IRQS; i++)
+        for (i = 1; i < nr_irqs; i++)
                beat_destruct_irq_plug(i);
 }
diff --git a/arch/powerpc/platforms/powermac/low_i2c.c b/arch/powerpc/platforms/powermac/low_i2c.c
index 996c5ff7824b..03685a329d7d 100644
--- a/arch/powerpc/platforms/powermac/low_i2c.c
+++ b/arch/powerpc/platforms/powermac/low_i2c.c
@@ -366,11 +366,20 @@ static void kw_i2c_timeout(unsigned long data)
        unsigned long flags;
        spin_lock_irqsave(&host->lock, flags);
+        /*
+         * If the timer is pending, that means we raced with the
+         * irq, in which case we just return
+         */
+        if (timer_pending(&host->timeout_timer))
+                goto skip;
        kw_i2c_handle_interrupt(host, kw_read_reg(reg_isr));
        if (host->state != state_idle) {
                host->timeout_timer.expires = jiffies + KW_POLL_TIMEOUT;
                add_timer(&host->timeout_timer);
        }
+ skip:
        spin_unlock_irqrestore(&host->lock, flags);
 }
diff --git a/arch/powerpc/platforms/powermac/pic.c b/arch/powerpc/platforms/powermac/pic.c
index 66ad93de1d55..c4e630576ff2 100644
--- a/arch/powerpc/platforms/powermac/pic.c
+++ b/arch/powerpc/platforms/powermac/pic.c
@@ -57,9 +57,9 @@ static int max_real_irqs;
 static DEFINE_RAW_SPINLOCK(pmac_pic_lock);
-#define NR_MASK_WORDS   ((NR_IRQS + 31) / 32)
+/* The max irq number this driver deals with is 128; see max_irqs */
-static unsigned long ppc_lost_interrupts[NR_MASK_WORDS];
+static DECLARE_BITMAP(ppc_lost_interrupts, 128);
-static unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
+static DECLARE_BITMAP(ppc_cached_irq_mask, 128);
 static int pmac_irq_cascade = -1;
 static struct irq_domain *pmac_pic_host;
diff --git a/arch/powerpc/platforms/powermac/smp.c b/arch/powerpc/platforms/powermac/smp.c
index a81e5a88fbdf..b4ddaa3fbb29 100644
--- a/arch/powerpc/platforms/powermac/smp.c
+++ b/arch/powerpc/platforms/powermac/smp.c
@@ -192,7 +192,7 @@ static int psurge_secondary_ipi_init(void)
 {
        int rc = -ENOMEM;
-        psurge_host = irq_domain_add_nomap(NULL, &psurge_host_ops, NULL);
+        psurge_host = irq_domain_add_nomap(NULL, 0, &psurge_host_ops, NULL);
        if (psurge_host)
                psurge_secondary_virq = irq_create_direct_mapping(psurge_host);
diff --git a/arch/powerpc/platforms/ps3/interrupt.c b/arch/powerpc/platforms/ps3/interrupt.c
index 2a4ff86cc21f..5f3b23220b8e 100644
--- a/arch/powerpc/platforms/ps3/interrupt.c
+++ b/arch/powerpc/platforms/ps3/interrupt.c
@@ -753,9 +753,8 @@ void __init ps3_init_IRQ(void)
        unsigned cpu;
        struct irq_domain *host;
-        host = irq_domain_add_nomap(NULL, &ps3_host_ops, NULL);
+        host = irq_domain_add_nomap(NULL, PS3_PLUG_MAX + 1, &ps3_host_ops, NULL);
        irq_set_default_host(host);
-        irq_set_virq_count(PS3_PLUG_MAX + 1);
        for_each_possible_cpu(cpu) {
                struct ps3_private *pd = &per_cpu(ps3_private, cpu);
diff --git a/arch/powerpc/platforms/pseries/Kconfig b/arch/powerpc/platforms/pseries/Kconfig
index 10ad207dccc2..837cf49357ed 100644
--- a/arch/powerpc/platforms/pseries/Kconfig
+++ b/arch/powerpc/platforms/pseries/Kconfig
@@ -30,9 +30,9 @@ config PPC_SPLPAR
          two or more partitions.
 config EEH
-        bool "PCI Extended Error Handling (EEH)" if EXPERT
+        bool
        depends on PPC_PSERIES && PCI
-        default y if !EXPERT
+        default y
 config PSERIES_MSI
       bool
diff --git a/arch/powerpc/platforms/pseries/eeh.c b/arch/powerpc/platforms/pseries/eeh.c
index 309d38ef7322..a75e37dc41aa 100644
--- a/arch/powerpc/platforms/pseries/eeh.c
+++ b/arch/powerpc/platforms/pseries/eeh.c
@@ -1076,7 +1076,7 @@ static void eeh_add_device_late(struct pci_dev *dev)
        pr_debug("EEH: Adding device %s\n", pci_name(dev));
        dn = pci_device_to_OF_node(dev);
-        edev = pci_dev_to_eeh_dev(dev);
+        edev = of_node_to_eeh_dev(dn);
        if (edev->pdev == dev) {
                pr_debug("EEH: Already referenced !\n");
                return;
diff --git a/arch/powerpc/sysdev/cpm2_pic.c b/arch/powerpc/sysdev/cpm2_pic.c
index d3be961e2ae7..10386b676d87 100644
--- a/arch/powerpc/sysdev/cpm2_pic.c
+++ b/arch/powerpc/sysdev/cpm2_pic.c
@@ -51,8 +51,7 @@
 static intctl_cpm2_t __iomem *cpm2_intctl;
 static struct irq_domain *cpm2_pic_host;
-#define NR_MASK_WORDS   ((NR_IRQS + 31) / 32)
+static unsigned long ppc_cached_irq_mask[2]; /* 2 32-bit registers */
-static unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
 static const u_char irq_to_siureg[] = {
        1, 1, 1, 1, 1, 1, 1, 1,
diff --git a/arch/powerpc/sysdev/mpc8xx_pic.c b/arch/powerpc/sysdev/mpc8xx_pic.c
index d5f5416be310..b724622c3a0b 100644
--- a/arch/powerpc/sysdev/mpc8xx_pic.c
+++ b/arch/powerpc/sysdev/mpc8xx_pic.c
@@ -18,69 +18,45 @@
 extern int cpm_get_irq(struct pt_regs *regs);
 static struct irq_domain *mpc8xx_pic_host;
-#define NR_MASK_WORDS   ((NR_IRQS + 31) / 32)
+static unsigned long mpc8xx_cached_irq_mask;
-static unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
 static sysconf8xx_t __iomem *siu_reg;
-int cpm_get_irq(struct pt_regs *regs);
+static inline unsigned long mpc8xx_irqd_to_bit(struct irq_data *d)
+{
+        return 0x80000000 >> irqd_to_hwirq(d);
+}
 static void mpc8xx_unmask_irq(struct irq_data *d)
 {
-        int     bit, word;
+        mpc8xx_cached_irq_mask |= mpc8xx_irqd_to_bit(d);
-        unsigned int irq_nr = (unsigned int)irqd_to_hwirq(d);
+        out_be32(&siu_reg->sc_simask, mpc8xx_cached_irq_mask);
-        bit = irq_nr & 0x1f;
-        word = irq_nr >> 5;
-        ppc_cached_irq_mask[word] |= (1 << (31-bit));
-        out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]);
 }
 static void mpc8xx_mask_irq(struct irq_data *d)
 {
-        int     bit, word;
+        mpc8xx_cached_irq_mask &= ~mpc8xx_irqd_to_bit(d);
-        unsigned int irq_nr = (unsigned int)irqd_to_hwirq(d);
+        out_be32(&siu_reg->sc_simask, mpc8xx_cached_irq_mask);
-        bit = irq_nr & 0x1f;
-        word = irq_nr >> 5;
-        ppc_cached_irq_mask[word] &= ~(1 << (31-bit));
-        out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]);
 }
 static void mpc8xx_ack(struct irq_data *d)
 {
-        int     bit;
+        out_be32(&siu_reg->sc_sipend, mpc8xx_irqd_to_bit(d));
-        unsigned int irq_nr = (unsigned int)irqd_to_hwirq(d);
-        bit = irq_nr & 0x1f;
-        out_be32(&siu_reg->sc_sipend, 1 << (31-bit));
 }
 static void mpc8xx_end_irq(struct irq_data *d)
 {
-        int bit, word;
+        mpc8xx_cached_irq_mask |= mpc8xx_irqd_to_bit(d);
-        unsigned int irq_nr = (unsigned int)irqd_to_hwirq(d);
+        out_be32(&siu_reg->sc_simask, mpc8xx_cached_irq_mask);
-        bit = irq_nr & 0x1f;
-        word = irq_nr >> 5;
-        ppc_cached_irq_mask[word] |= (1 << (31-bit));
-        out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]);
 }
 static int mpc8xx_set_irq_type(struct irq_data *d, unsigned int flow_type)
 {
-        if (flow_type & IRQ_TYPE_EDGE_FALLING) {
+        /* only external IRQ senses are programmable */
-                irq_hw_number_t hw = (unsigned int)irqd_to_hwirq(d);
+        if ((flow_type & IRQ_TYPE_EDGE_FALLING) && !(irqd_to_hwirq(d) & 1)) {
                unsigned int siel = in_be32(&siu_reg->sc_siel);
+                siel |= mpc8xx_irqd_to_bit(d);
-                /* only external IRQ senses are programmable */
+                out_be32(&siu_reg->sc_siel, siel);
-                if ((hw & 1) == 0) {
+                __irq_set_handler_locked(d->irq, handle_edge_irq);
-                        siel |= (0x80000000 >> hw);
-                        out_be32(&siu_reg->sc_siel, siel);
-                        __irq_set_handler_locked(d->irq, handle_edge_irq);
-                }
        }
        return 0;
 }
@@ -132,6 +108,9 @@ static int mpc8xx_pic_host_xlate(struct irq_domain *h, struct device_node *ct,
                IRQ_TYPE_EDGE_FALLING,
        };
+        if (intspec[0] > 0x1f)
+                return 0;
        *out_hwirq = intspec[0];
        if (intsize > 1 && intspec[1] < 4)
                *out_flags = map_pic_senses[intspec[1]];
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index 9ac71ebd2c40..395af1347749 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -604,18 +604,14 @@ static struct mpic *mpic_find(unsigned int irq)
 }
 /* Determine if the linux irq is an IPI */
-static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int irq)
+static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int src)
 {
-        unsigned int src = virq_to_hw(irq);
        return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]);
 }
 /* Determine if the linux irq is a timer */
-static unsigned int mpic_is_tm(struct mpic *mpic, unsigned int irq)
+static unsigned int mpic_is_tm(struct mpic *mpic, unsigned int src)
 {
-        unsigned int src = virq_to_hw(irq);
        return (src >= mpic->timer_vecs[0] && src <= mpic->timer_vecs[7]);
 }
@@ -876,21 +872,45 @@ int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type)
        if (src >= mpic->num_sources)
                return -EINVAL;
+        vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
+        /* We don't support "none" type */
        if (flow_type == IRQ_TYPE_NONE)
-                if (mpic->senses && src < mpic->senses_count)
+                flow_type = IRQ_TYPE_DEFAULT;
-                        flow_type = mpic->senses[src];
-        if (flow_type == IRQ_TYPE_NONE)
+        /* Default: read HW settings */
-                flow_type = IRQ_TYPE_LEVEL_LOW;
+        if (flow_type == IRQ_TYPE_DEFAULT) {
+                switch(vold & (MPIC_INFO(VECPRI_POLARITY_MASK) |
+                               MPIC_INFO(VECPRI_SENSE_MASK))) {
+                        case MPIC_INFO(VECPRI_SENSE_EDGE) |
+                             MPIC_INFO(VECPRI_POLARITY_POSITIVE):
+                                flow_type = IRQ_TYPE_EDGE_RISING;
+                                break;
+                        case MPIC_INFO(VECPRI_SENSE_EDGE) |
+                             MPIC_INFO(VECPRI_POLARITY_NEGATIVE):
+                                flow_type = IRQ_TYPE_EDGE_FALLING;
+                                break;
+                        case MPIC_INFO(VECPRI_SENSE_LEVEL) |
+                             MPIC_INFO(VECPRI_POLARITY_POSITIVE):
+                                flow_type = IRQ_TYPE_LEVEL_HIGH;
+                                break;
+                        case MPIC_INFO(VECPRI_SENSE_LEVEL) |
+                             MPIC_INFO(VECPRI_POLARITY_NEGATIVE):
+                                flow_type = IRQ_TYPE_LEVEL_LOW;
+                                break;
+                }
+        }
+        /* Apply to irq desc */
        irqd_set_trigger_type(d, flow_type);
+        /* Apply to HW */
        if (mpic_is_ht_interrupt(mpic, src))
                vecpri = MPIC_VECPRI_POLARITY_POSITIVE |
                        MPIC_VECPRI_SENSE_EDGE;
        else
                vecpri = mpic_type_to_vecpri(mpic, flow_type);
-        vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
        vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) |
                        MPIC_INFO(VECPRI_SENSE_MASK));
        vnew |= vecpri;
@@ -1026,7 +1046,7 @@ static int mpic_host_map(struct irq_domain *h, unsigned int virq,
        irq_set_chip_and_handler(virq, chip, handle_fasteoi_irq);
        /* Set default irq type */
-        irq_set_irq_type(virq, IRQ_TYPE_NONE);
+        irq_set_irq_type(virq, IRQ_TYPE_DEFAULT);
        /* If the MPIC was reset, then all vectors have already been
         * initialized.  Otherwise, a per source lazy initialization
@@ -1417,12 +1437,6 @@ void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
                mpic->num_sources = isu_first + mpic->isu_size;
 }
-void __init mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count)
-{
-        mpic->senses = senses;
-        mpic->senses_count = count;
-}
 void __init mpic_init(struct mpic *mpic)
 {
        int i, cpu;
@@ -1555,12 +1569,12 @@ void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
                return;
        raw_spin_lock_irqsave(&mpic_lock, flags);
-        if (mpic_is_ipi(mpic, irq)) {
+        if (mpic_is_ipi(mpic, src)) {
                reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) &
                        ~MPIC_VECPRI_PRIORITY_MASK;
                mpic_ipi_write(src - mpic->ipi_vecs[0],
                               reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
-        } else if (mpic_is_tm(mpic, irq)) {
+        } else if (mpic_is_tm(mpic, src)) {
                reg = mpic_tm_read(src - mpic->timer_vecs[0]) &
                        ~MPIC_VECPRI_PRIORITY_MASK;
                mpic_tm_write(src - mpic->timer_vecs[0],
diff --git a/arch/powerpc/sysdev/mpic_msgr.c b/arch/powerpc/sysdev/mpic_msgr.c
index 6e7fa386e76a..483d8fa72e8b 100644
--- a/arch/powerpc/sysdev/mpic_msgr.c
+++ b/arch/powerpc/sysdev/mpic_msgr.c
@@ -27,6 +27,7 @@
 static struct mpic_msgr **mpic_msgrs;
 static unsigned int mpic_msgr_count;
+static DEFINE_RAW_SPINLOCK(msgrs_lock);
 static inline void _mpic_msgr_mer_write(struct mpic_msgr *msgr, u32 value)
 {
@@ -56,12 +57,11 @@ struct mpic_msgr *mpic_msgr_get(unsigned int reg_num)
        if (reg_num >= mpic_msgr_count)
                return ERR_PTR(-ENODEV);
-        raw_spin_lock_irqsave(&msgr->lock, flags);
+        raw_spin_lock_irqsave(&msgrs_lock, flags);
-        if (mpic_msgrs[reg_num]->in_use == MSGR_FREE) {
+        msgr = mpic_msgrs[reg_num];
-                msgr = mpic_msgrs[reg_num];
+        if (msgr->in_use == MSGR_FREE)
                msgr->in_use = MSGR_INUSE;
-        }
+        raw_spin_unlock_irqrestore(&msgrs_lock, flags);
-        raw_spin_unlock_irqrestore(&msgr->lock, flags);
        return msgr;
 }
@@ -228,7 +228,7 @@ static __devinit int mpic_msgr_probe(struct platform_device *dev)
                reg_number = block_number * MPIC_MSGR_REGISTERS_PER_BLOCK + i;
                msgr->base = msgr_block_addr + i * MPIC_MSGR_STRIDE;
-                msgr->mer = msgr->base + MPIC_MSGR_MER_OFFSET;
+                msgr->mer = (u32 *)((u8 *)msgr->base + MPIC_MSGR_MER_OFFSET);
                msgr->in_use = MSGR_FREE;
                msgr->num = i;
                raw_spin_lock_init(&msgr->lock);
diff --git a/arch/powerpc/sysdev/scom.c b/arch/powerpc/sysdev/scom.c
index 49a3ece1c6b3..702256a1ca11 100644
--- a/arch/powerpc/sysdev/scom.c
+++ b/arch/powerpc/sysdev/scom.c
@@ -22,6 +22,7 @@
 #include <linux/debugfs.h>
 #include <linux/slab.h>
 #include <linux/export.h>
+#include <asm/debug.h>
 #include <asm/prom.h>
 #include <asm/scom.h>
diff --git a/arch/powerpc/sysdev/xics/xics-common.c b/arch/powerpc/sysdev/xics/xics-common.c
index ea5e204e3450..cd1d18db92c6 100644
--- a/arch/powerpc/sysdev/xics/xics-common.c
+++ b/arch/powerpc/sysdev/xics/xics-common.c
@@ -188,6 +188,7 @@ void xics_migrate_irqs_away(void)
 {
        int cpu = smp_processor_id(), hw_cpu = hard_smp_processor_id();
        unsigned int irq, virq;
+        struct irq_desc *desc;
        /* If we used to be the default server, move to the new "boot_cpuid" */
        if (hw_cpu == xics_default_server)
@@ -202,8 +203,7 @@ void xics_migrate_irqs_away(void)
        /* Allow IPIs again... */
        icp_ops->set_priority(DEFAULT_PRIORITY);
-        for_each_irq(virq) {
+        for_each_irq_desc(virq, desc) {
-                struct irq_desc *desc;
                struct irq_chip *chip;
                long server;
                unsigned long flags;
@@ -212,9 +212,8 @@ void xics_migrate_irqs_away(void)
                /* We can't set affinity on ISA interrupts */
                if (virq < NUM_ISA_INTERRUPTS)
                        continue;
-                desc = irq_to_desc(virq);
                /* We only need to migrate enabled IRQS */
-                if (!desc || !desc->action)
+                if (!desc->action)
                        continue;
                if (desc->irq_data.domain != xics_host)
                        continue;
diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig
index 2b7c0fbe578e..e16390c0bca8 100644
--- a/arch/s390/Kconfig
+++ b/arch/s390/Kconfig
@@ -90,7 +90,6 @@ config S390
        select HAVE_KERNEL_XZ
        select HAVE_ARCH_MUTEX_CPU_RELAX
        select HAVE_ARCH_JUMP_LABEL if !MARCH_G5
-        select HAVE_RCU_TABLE_FREE if SMP
        select ARCH_SAVE_PAGE_KEYS if HIBERNATION
        select HAVE_MEMBLOCK
        select HAVE_MEMBLOCK_NODE_MAP
@@ -123,6 +122,7 @@ config S390
        select ARCH_INLINE_WRITE_UNLOCK_BH
        select ARCH_INLINE_WRITE_UNLOCK_IRQ
        select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE
+        select GENERIC_SMP_IDLE_THREAD
 config SCHED_OMIT_FRAME_POINTER
        def_bool y
@@ -218,7 +218,7 @@ config COMPAT
        def_bool y
        prompt "Kernel support for 31 bit emulation"
        depends on 64BIT
-        select COMPAT_BINFMT_ELF
+        select COMPAT_BINFMT_ELF if BINFMT_ELF
        select ARCH_WANT_OLD_COMPAT_IPC
        help
          Select this option if you want to enable your system kernel to
@@ -235,6 +235,25 @@ config KEYS_COMPAT
 config AUDIT_ARCH
        def_bool y
+config HAVE_MARCH_Z900_FEATURES
+        def_bool n
+config HAVE_MARCH_Z990_FEATURES
+        def_bool n
+        select HAVE_MARCH_Z900_FEATURES
+config HAVE_MARCH_Z9_109_FEATURES
+        def_bool n
+        select HAVE_MARCH_Z990_FEATURES
+config HAVE_MARCH_Z10_FEATURES
+        def_bool n
+        select HAVE_MARCH_Z9_109_FEATURES
+config HAVE_MARCH_Z196_FEATURES
+        def_bool n
+        select HAVE_MARCH_Z10_FEATURES
 comment "Code generation options"
 choice
@@ -250,6 +269,7 @@ config MARCH_G5
 config MARCH_Z900
        bool "IBM zSeries model z800 and z900"
+        select HAVE_MARCH_Z900_FEATURES if 64BIT
        help
          Select this to enable optimizations for model z800/z900 (2064 and
          2066 series). This will enable some optimizations that are not
@@ -257,6 +277,7 @@ config MARCH_Z900
 config MARCH_Z990
        bool "IBM zSeries model z890 and z990"
+        select HAVE_MARCH_Z990_FEATURES if 64BIT
        help
          Select this to enable optimizations for model z890/z990 (2084 and
          2086 series). The kernel will be slightly faster but will not work
@@ -264,6 +285,7 @@ config MARCH_Z990
 config MARCH_Z9_109
        bool "IBM System z9"
+        select HAVE_MARCH_Z9_109_FEATURES if 64BIT
        help
          Select this to enable optimizations for IBM System z9 (2094 and
          2096 series). The kernel will be slightly faster but will not work
@@ -271,6 +293,7 @@ config MARCH_Z9_109
 config MARCH_Z10
        bool "IBM System z10"
+        select HAVE_MARCH_Z10_FEATURES if 64BIT
        help
          Select this to enable optimizations for IBM System z10 (2097 and
          2098 series). The kernel will be slightly faster but will not work
@@ -278,6 +301,7 @@ config MARCH_Z10
 config MARCH_Z196
        bool "IBM zEnterprise 114 and 196"
+        select HAVE_MARCH_Z196_FEATURES if 64BIT
        help
          Select this to enable optimizations for IBM zEnterprise 114 and 196
          (2818 and 2817 series). The kernel will be slightly faster but will
@@ -407,33 +431,6 @@ config CHSC_SCH
 comment "Misc"
-config IPL
-        def_bool y
-        prompt "Builtin IPL record support"
-        help
-          If you want to use the produced kernel to IPL directly from a
-          device, you have to merge a bootsector specific to the device
-          into the first bytes of the kernel. You will have to select the
-          IPL device.
-choice
-        prompt "IPL method generated into head.S"
-        depends on IPL
-        default IPL_VM
-        help
-          Select "tape" if you want to IPL the image from a Tape.
-          Select "vm_reader" if you are running under VM/ESA and want
-          to IPL the image from the emulated card reader.
-config IPL_TAPE
-        bool "tape"
-config IPL_VM
-        bool "vm_reader"
-endchoice
 source "fs/Kconfig.binfmt"
 config FORCE_MAX_ZONEORDER
@@ -570,7 +567,7 @@ config KEXEC
 config CRASH_DUMP
        bool "kernel crash dumps"
-        depends on 64BIT
+        depends on 64BIT && SMP
        select KEXEC
        help
          Generate crash dump after being started by kexec.
diff --git a/arch/s390/Makefile b/arch/s390/Makefile
index 0ad2f1e1ce9e..49e76e8b477d 100644
--- a/arch/s390/Makefile
+++ b/arch/s390/Makefile
@@ -91,7 +91,6 @@ OBJCOPYFLAGS	:= -O binary
 head-y          := arch/s390/kernel/head.o
 head-y          += arch/s390/kernel/$(if $(CONFIG_64BIT),head64.o,head31.o)
-head-y          += arch/s390/kernel/init_task.o
 # See arch/s390/Kbuild for content of core part of the kernel
 core-y          += arch/s390/
diff --git a/arch/s390/boot/.gitignore b/arch/s390/boot/.gitignore
new file mode 100644
index 000000000000..017d5912ad2d
--- /dev/null
+++ b/arch/s390/boot/.gitignore
@@ -0,0 +1,2 @@
+image
+bzImage
diff --git a/arch/s390/boot/compressed/.gitignore b/arch/s390/boot/compressed/.gitignore
new file mode 100644
index 000000000000..ae06b9b4c02f
--- /dev/null
+++ b/arch/s390/boot/compressed/.gitignore
@@ -0,0 +1,3 @@
+sizes.h
+vmlinux
+vmlinux.lds
diff --git a/arch/s390/defconfig b/arch/s390/defconfig
index 6cf8e26b3137..37d2bf267964 100644
--- a/arch/s390/defconfig
+++ b/arch/s390/defconfig
@@ -1,8 +1,12 @@
 CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
+CONFIG_FHANDLE=y
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
 CONFIG_AUDIT=y
-CONFIG_RCU_TRACE=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_CGROUPS=y
@@ -14,16 +18,22 @@ CONFIG_CGROUP_MEM_RES_CTLR_SWAP=y
 CONFIG_CGROUP_SCHED=y
 CONFIG_RT_GROUP_SCHED=y
 CONFIG_BLK_CGROUP=y
+CONFIG_NAMESPACES=y
 CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
+CONFIG_RD_XZ=y
+CONFIG_RD_LZO=y
+CONFIG_EXPERT=y
 # CONFIG_COMPAT_BRK is not set
-CONFIG_SLAB=y
 CONFIG_PROFILING=y
 CONFIG_OPROFILE=y
 CONFIG_KPROBES=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 CONFIG_MODVERSIONS=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_IBM_PARTITION=y
 CONFIG_DEFAULT_DEADLINE=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
@@ -34,18 +44,15 @@ CONFIG_KSM=y
 CONFIG_BINFMT_MISC=m
 CONFIG_CMM=m
 CONFIG_HZ_100=y
-CONFIG_KEXEC=y
+CONFIG_CRASH_DUMP=y
-CONFIG_PM=y
 CONFIG_HIBERNATION=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
 CONFIG_NET_KEY=y
-CONFIG_AFIUCV=m
 CONFIG_INET=y
 CONFIG_IP_MULTICAST=y
 # CONFIG_INET_LRO is not set
 CONFIG_IPV6=y
-CONFIG_NET_SCTPPROBE=m
 CONFIG_L2TP=m
 CONFIG_L2TP_DEBUGFS=m
 CONFIG_VLAN_8021Q=y
@@ -84,15 +91,14 @@ CONFIG_SCSI_CONSTANTS=y
 CONFIG_SCSI_LOGGING=y
 CONFIG_SCSI_SCAN_ASYNC=y
 CONFIG_ZFCP=y
-CONFIG_ZFCP_DIF=y
 CONFIG_NETDEVICES=y
-CONFIG_DUMMY=m
 CONFIG_BONDING=m
+CONFIG_DUMMY=m
 CONFIG_EQUALIZER=m
 CONFIG_TUN=m
-CONFIG_NET_ETHERNET=y
 CONFIG_VIRTIO_NET=y
 CONFIG_RAW_DRIVER=m
+CONFIG_VIRTIO_BALLOON=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
 # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
@@ -103,27 +109,21 @@ CONFIG_PROC_KCORE=y
 CONFIG_TMPFS=y
 CONFIG_TMPFS_POSIX_ACL=y
 # CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_IBM_PARTITION=y
-CONFIG_DLM=m
 CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
 CONFIG_TIMER_STATS=y
 CONFIG_PROVE_LOCKING=y
 CONFIG_PROVE_RCU=y
 CONFIG_LOCK_STAT=y
 CONFIG_DEBUG_LOCKDEP=y
-CONFIG_DEBUG_SPINLOCK_SLEEP=y
 CONFIG_DEBUG_LIST=y
 CONFIG_DEBUG_NOTIFIERS=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+CONFIG_RCU_TRACE=y
 CONFIG_KPROBES_SANITY_TEST=y
 CONFIG_DEBUG_FORCE_WEAK_PER_CPU=y
 CONFIG_CPU_NOTIFIER_ERROR_INJECT=m
 CONFIG_LATENCYTOP=y
-CONFIG_SYSCTL_SYSCALL_CHECK=y
 CONFIG_DEBUG_PAGEALLOC=y
-# CONFIG_FTRACE is not set
+CONFIG_BLK_DEV_IO_TRACE=y
 # CONFIG_STRICT_DEVMEM is not set
 CONFIG_CRYPTO_NULL=m
 CONFIG_CRYPTO_CRYPTD=m
@@ -155,7 +155,6 @@ CONFIG_CRYPTO_BLOWFISH=m
 CONFIG_CRYPTO_CAMELLIA=m
 CONFIG_CRYPTO_CAST5=m
 CONFIG_CRYPTO_CAST6=m
-CONFIG_CRYPTO_DES=m
 CONFIG_CRYPTO_FCRYPT=m
 CONFIG_CRYPTO_KHAZAD=m
 CONFIG_CRYPTO_SALSA20=m
@@ -173,4 +172,3 @@ CONFIG_CRYPTO_SHA512_S390=m
 CONFIG_CRYPTO_DES_S390=m
 CONFIG_CRYPTO_AES_S390=m
 CONFIG_CRC7=m
-CONFIG_VIRTIO_BALLOON=y
diff --git a/arch/s390/include/asm/barrier.h b/arch/s390/include/asm/barrier.h
index 451273ad4d34..10a508802940 100644
--- a/arch/s390/include/asm/barrier.h
+++ b/arch/s390/include/asm/barrier.h
@@ -11,25 +11,28 @@
 * Force strict CPU ordering.
 * And yes, this is required on UP too when we're talking
 * to devices.
- *
- * This is very similar to the ppc eieio/sync instruction in that is
- * does a checkpoint syncronisation & makes sure that 
- * all memory ops have completed wrt other CPU's ( see 7-15 POP  DJB ).
 */
-#define eieio() asm volatile("bcr 15,0" : : : "memory")
+static inline void mb(void)
-#define SYNC_OTHER_CORES(x)   eieio()
+{
-#define mb()    eieio()
+#ifdef CONFIG_HAVE_MARCH_Z196_FEATURES
-#define rmb()   eieio()
+        /* Fast-BCR without checkpoint synchronization */
-#define wmb()   eieio()
+        asm volatile("bcr 14,0" : : : "memory");
-#define read_barrier_depends() do { } while(0)
+#else
-#define smp_mb()       mb()
+        asm volatile("bcr 15,0" : : : "memory");
-#define smp_rmb()      rmb()
+#endif
-#define smp_wmb()      wmb()
+}
-#define smp_read_barrier_depends()    read_barrier_depends()
-#define smp_mb__before_clear_bit()     smp_mb()
+#define rmb()                           mb()
-#define smp_mb__after_clear_bit()      smp_mb()
+#define wmb()                           mb()
+#define read_barrier_depends()          do { } while(0)
+#define smp_mb()                        mb()
+#define smp_rmb()                       rmb()
+#define smp_wmb()                       wmb()
+#define smp_read_barrier_depends()      read_barrier_depends()
+#define smp_mb__before_clear_bit()      smp_mb()
+#define smp_mb__after_clear_bit()       smp_mb()
-#define set_mb(var, value)      do { var = value; mb(); } while (0)
+#define set_mb(var, value)              do { var = value; mb(); } while (0)
 #endif /* __ASM_BARRIER_H */
diff --git a/arch/s390/include/asm/ccwgroup.h b/arch/s390/include/asm/ccwgroup.h
index f2ea2c56a7e1..f2ef34f6d6e5 100644
--- a/arch/s390/include/asm/ccwgroup.h
+++ b/arch/s390/include/asm/ccwgroup.h
@@ -29,9 +29,7 @@ struct ccwgroup_device {
 /**
 * struct ccwgroup_driver - driver for ccw group devices
- * @max_slaves: maximum number of slave devices
+ * @setup: function called during device creation to setup the device
- * @driver_id: unique id
- * @probe: function called on probe
 * @remove: function called on remove
 * @set_online: function called when device is set online
 * @set_offline: function called when device is set offline
@@ -44,10 +42,7 @@ struct ccwgroup_device {
 * @driver: embedded driver structure
 */
 struct ccwgroup_driver {
-        int max_slaves;
+        int (*setup) (struct ccwgroup_device *);
-        unsigned long driver_id;
-        int (*probe) (struct ccwgroup_device *);
        void (*remove) (struct ccwgroup_device *);
        int (*set_online) (struct ccwgroup_device *);
        int (*set_offline) (struct ccwgroup_device *);
@@ -63,9 +58,8 @@ struct ccwgroup_driver {
 extern int  ccwgroup_driver_register   (struct ccwgroup_driver *cdriver);
 extern void ccwgroup_driver_unregister (struct ccwgroup_driver *cdriver);
-int ccwgroup_create_from_string(struct device *root, unsigned int creator_id,
+int ccwgroup_create_dev(struct device *root, struct ccwgroup_driver *gdrv,
-                                struct ccw_driver *cdrv, int num_devices,
+                        int num_devices, const char *buf);
-                                const char *buf);
 extern int ccwgroup_probe_ccwdev(struct ccw_device *cdev);
 extern void ccwgroup_remove_ccwdev(struct ccw_device *cdev);
diff --git a/arch/s390/include/asm/facility.h b/arch/s390/include/asm/facility.h
index 1e5b27edc0c9..2ee66a65f2d4 100644
--- a/arch/s390/include/asm/facility.h
+++ b/arch/s390/include/asm/facility.h
@@ -38,12 +38,11 @@ static inline void stfle(u64 *stfle_fac_list, int size)
        unsigned long nr;
        preempt_disable();
-        S390_lowcore.stfl_fac_list = 0;
        asm volatile(
                "       .insn s,0xb2b10000,0(0)\n" /* stfl */
                "0:\n"
                EX_TABLE(0b, 0b)
-                : "=m" (S390_lowcore.stfl_fac_list));
+                : "+m" (S390_lowcore.stfl_fac_list));
        nr = 4; /* bytes stored by stfl */
        memcpy(stfle_fac_list, &S390_lowcore.stfl_fac_list, 4);
        if (S390_lowcore.stfl_fac_list & 0x01000000) {
diff --git a/arch/s390/include/asm/io.h b/arch/s390/include/asm/io.h
index b7ff6afc3caa..27216d317991 100644
--- a/arch/s390/include/asm/io.h
+++ b/arch/s390/include/asm/io.h
@@ -38,11 +38,8 @@ static inline void * phys_to_virt(unsigned long address)
        return (void *) address;
 }
-/*
+void *xlate_dev_mem_ptr(unsigned long phys);
- * Convert a physical pointer to a virtual kernel pointer for /dev/mem
+void unxlate_dev_mem_ptr(unsigned long phys, void *addr);
- * access
- */
-#define xlate_dev_mem_ptr(p)    __va(p)
 /*
 * Convert a virtual cached pointer to an uncached pointer
diff --git a/arch/s390/include/asm/pgalloc.h b/arch/s390/include/asm/pgalloc.h
index 8eef9b5b3cf4..78e3041919de 100644
--- a/arch/s390/include/asm/pgalloc.h
+++ b/arch/s390/include/asm/pgalloc.h
@@ -22,10 +22,7 @@ void crst_table_free(struct mm_struct *, unsigned long *);
 unsigned long *page_table_alloc(struct mm_struct *, unsigned long);
 void page_table_free(struct mm_struct *, unsigned long *);
-#ifdef CONFIG_HAVE_RCU_TABLE_FREE
 void page_table_free_rcu(struct mmu_gather *, unsigned long *);
-void __tlb_remove_table(void *_table);
-#endif
 static inline void clear_table(unsigned long *s, unsigned long val, size_t n)
 {
diff --git a/arch/s390/include/asm/qdio.h b/arch/s390/include/asm/qdio.h
index d75c8e78f7e3..f039d86adf67 100644
--- a/arch/s390/include/asm/qdio.h
+++ b/arch/s390/include/asm/qdio.h
@@ -258,11 +258,6 @@ struct slsb {
        u8 val[QDIO_MAX_BUFFERS_PER_Q];
 } __attribute__ ((packed, aligned(256)));
-#define CHSC_AC2_MULTI_BUFFER_AVAILABLE 0x0080
-#define CHSC_AC2_MULTI_BUFFER_ENABLED   0x0040
-#define CHSC_AC2_DATA_DIV_AVAILABLE     0x0010
-#define CHSC_AC2_DATA_DIV_ENABLED       0x0002
 /**
 * struct qdio_outbuf_state - SBAL related asynchronous operation information
 *   (for communication with upper layer programs)
@@ -293,6 +288,8 @@ struct qdio_outbuf_state {
 #define AC1_SC_QEBSM_AVAILABLE          0x02    /* available for subchannel */
 #define AC1_SC_QEBSM_ENABLED            0x01    /* enabled for subchannel */
+#define CHSC_AC2_MULTI_BUFFER_AVAILABLE 0x0080
+#define CHSC_AC2_MULTI_BUFFER_ENABLED   0x0040
 #define CHSC_AC2_DATA_DIV_AVAILABLE     0x0010
 #define CHSC_AC2_DATA_DIV_ENABLED       0x0002
@@ -328,11 +325,13 @@ typedef void qdio_handler_t(struct ccw_device *, unsigned int, int,
                            int, int, unsigned long);
 /* qdio errors reported to the upper-layer program */
-#define QDIO_ERROR_SIGA_TARGET                  0x02
+#define QDIO_ERROR_ACTIVATE                     0x0001
-#define QDIO_ERROR_SIGA_ACCESS_EXCEPTION        0x10
+#define QDIO_ERROR_GET_BUF_STATE                0x0002
-#define QDIO_ERROR_SIGA_BUSY                    0x20
+#define QDIO_ERROR_SET_BUF_STATE                0x0004
-#define QDIO_ERROR_ACTIVATE_CHECK_CONDITION     0x40
+#define QDIO_ERROR_SLSB_STATE                   0x0100
-#define QDIO_ERROR_SLSB_STATE                   0x80
+#define QDIO_ERROR_FATAL                        0x00ff
+#define QDIO_ERROR_TEMPORARY                    0xff00
 /* for qdio_cleanup */
 #define QDIO_FLAG_CLEANUP_USING_CLEAR           0x01
diff --git a/arch/s390/include/asm/setup.h b/arch/s390/include/asm/setup.h
index b21e46e5d4b8..7244e1f64126 100644
--- a/arch/s390/include/asm/setup.h
+++ b/arch/s390/include/asm/setup.h
@@ -82,7 +82,6 @@ extern unsigned int user_mode;
 #define MACHINE_FLAG_LPAR       (1UL << 12)
 #define MACHINE_FLAG_SPP        (1UL << 13)
 #define MACHINE_FLAG_TOPOLOGY   (1UL << 14)
-#define MACHINE_FLAG_STCKF      (1UL << 15)
 #define MACHINE_IS_VM           (S390_lowcore.machine_flags & MACHINE_FLAG_VM)
 #define MACHINE_IS_KVM          (S390_lowcore.machine_flags & MACHINE_FLAG_KVM)
@@ -101,7 +100,6 @@ extern unsigned int user_mode;
 #define MACHINE_HAS_PFMF        (0)
 #define MACHINE_HAS_SPP         (0)
 #define MACHINE_HAS_TOPOLOGY    (0)
-#define MACHINE_HAS_STCKF       (0)
 #else /* __s390x__ */
 #define MACHINE_HAS_IEEE        (1)
 #define MACHINE_HAS_CSP         (1)
@@ -113,7 +111,6 @@ extern unsigned int user_mode;
 #define MACHINE_HAS_PFMF        (S390_lowcore.machine_flags & MACHINE_FLAG_PFMF)
 #define MACHINE_HAS_SPP         (S390_lowcore.machine_flags & MACHINE_FLAG_SPP)
 #define MACHINE_HAS_TOPOLOGY    (S390_lowcore.machine_flags & MACHINE_FLAG_TOPOLOGY)
-#define MACHINE_HAS_STCKF       (S390_lowcore.machine_flags & MACHINE_FLAG_STCKF)
 #endif /* __s390x__ */
 #define ZFCPDUMP_HSA_SIZE       (32UL<<20)
diff --git a/arch/s390/include/asm/smp.h b/arch/s390/include/asm/smp.h
index c77c6de6f6c0..0b6f586c1383 100644
--- a/arch/s390/include/asm/smp.h
+++ b/arch/s390/include/asm/smp.h
@@ -16,7 +16,7 @@
 extern struct mutex smp_cpu_state_mutex;
 extern struct save_area *zfcpdump_save_areas[NR_CPUS + 1];
-extern int __cpu_up(unsigned int cpu);
+extern int __cpu_up(unsigned int cpu, struct task_struct *tidle);
 extern void arch_send_call_function_single_ipi(int cpu);
 extern void arch_send_call_function_ipi_mask(const struct cpumask *mask);
diff --git a/arch/s390/include/asm/swab.h b/arch/s390/include/asm/swab.h
index 6bdee21c077e..a3e4ebb32090 100644
--- a/arch/s390/include/asm/swab.h
+++ b/arch/s390/include/asm/swab.h
@@ -77,7 +77,7 @@ static inline __u16 __arch_swab16p(const __u16 *x)
        
        asm volatile(
 #ifndef __s390x__
-                "       icm     %0,2,%O+1(%R1)\n"
+                "       icm     %0,2,%O1+1(%R1)\n"
                "       ic      %0,%1\n"
                : "=&d" (result) : "Q" (*x) : "cc");
 #else /* __s390x__ */
diff --git a/arch/s390/include/asm/thread_info.h b/arch/s390/include/asm/thread_info.h
index a73038155e0d..003b04edcff6 100644
--- a/arch/s390/include/asm/thread_info.h
+++ b/arch/s390/include/asm/thread_info.h
@@ -95,7 +95,6 @@ static inline struct thread_info *current_thread_info(void)
 #define TIF_SYSCALL_AUDIT       9       /* syscall auditing active */
 #define TIF_SECCOMP             10      /* secure computing */
 #define TIF_SYSCALL_TRACEPOINT  11      /* syscall tracepoint instrumentation */
-#define TIF_SIE                 12      /* guest execution active */
 #define TIF_POLLING_NRFLAG      16      /* true if poll_idle() is polling
                                           TIF_NEED_RESCHED */
 #define TIF_31BIT               17      /* 32bit process */
@@ -114,7 +113,6 @@ static inline struct thread_info *current_thread_info(void)
 #define _TIF_SYSCALL_AUDIT      (1<<TIF_SYSCALL_AUDIT)
 #define _TIF_SECCOMP            (1<<TIF_SECCOMP)
 #define _TIF_SYSCALL_TRACEPOINT (1<<TIF_SYSCALL_TRACEPOINT)
-#define _TIF_SIE                (1<<TIF_SIE)
 #define _TIF_POLLING_NRFLAG     (1<<TIF_POLLING_NRFLAG)
 #define _TIF_31BIT              (1<<TIF_31BIT)
 #define _TIF_SINGLE_STEP        (1<<TIF_SINGLE_STEP)
diff --git a/arch/s390/include/asm/timex.h b/arch/s390/include/asm/timex.h
index c447a27a7fdb..239ece9e53c1 100644
--- a/arch/s390/include/asm/timex.h
+++ b/arch/s390/include/asm/timex.h
@@ -73,11 +73,15 @@ static inline void local_tick_enable(unsigned long long comp)
 typedef unsigned long long cycles_t;
-static inline unsigned long long get_clock (void)
+static inline unsigned long long get_clock(void)
 {
        unsigned long long clk;
+#ifdef CONFIG_HAVE_MARCH_Z9_109_FEATURES
+        asm volatile(".insn s,0xb27c0000,%0" : "=Q" (clk) : : "cc");
+#else
        asm volatile("stck %0" : "=Q" (clk) : : "cc");
+#endif
        return clk;
 }
@@ -86,17 +90,6 @@ static inline void get_clock_ext(char *clk)
        asm volatile("stcke %0" : "=Q" (*clk) : : "cc");
 }
-static inline unsigned long long get_clock_fast(void)
-{
-        unsigned long long clk;
-        if (MACHINE_HAS_STCKF)
-                asm volatile(".insn     s,0xb27c0000,%0" : "=Q" (clk) : : "cc");
-        else
-                clk = get_clock();
-        return clk;
-}
 static inline unsigned long long get_clock_xt(void)
 {
        unsigned char clk[16];
diff --git a/arch/s390/include/asm/tlb.h b/arch/s390/include/asm/tlb.h
index c687a2c83462..775a5eea8f9e 100644
--- a/arch/s390/include/asm/tlb.h
+++ b/arch/s390/include/asm/tlb.h
@@ -30,14 +30,10 @@
 struct mmu_gather {
        struct mm_struct *mm;
-#ifdef CONFIG_HAVE_RCU_TABLE_FREE
        struct mmu_table_batch *batch;
-#endif
        unsigned int fullmm;
-        unsigned int need_flush;
 };
-#ifdef CONFIG_HAVE_RCU_TABLE_FREE
 struct mmu_table_batch {
        struct rcu_head         rcu;
        unsigned int            nr;
@@ -49,7 +45,6 @@ struct mmu_table_batch {
 extern void tlb_table_flush(struct mmu_gather *tlb);
 extern void tlb_remove_table(struct mmu_gather *tlb, void *table);
-#endif
 static inline void tlb_gather_mmu(struct mmu_gather *tlb,
                                  struct mm_struct *mm,
@@ -57,29 +52,20 @@ static inline void tlb_gather_mmu(struct mmu_gather *tlb,
 {
        tlb->mm = mm;
        tlb->fullmm = full_mm_flush;
-        tlb->need_flush = 0;
-#ifdef CONFIG_HAVE_RCU_TABLE_FREE
        tlb->batch = NULL;
-#endif
        if (tlb->fullmm)
                __tlb_flush_mm(mm);
 }
 static inline void tlb_flush_mmu(struct mmu_gather *tlb)
 {
-        if (!tlb->need_flush)
-                return;
-        tlb->need_flush = 0;
-        __tlb_flush_mm(tlb->mm);
-#ifdef CONFIG_HAVE_RCU_TABLE_FREE
        tlb_table_flush(tlb);
-#endif
 }
 static inline void tlb_finish_mmu(struct mmu_gather *tlb,
                                  unsigned long start, unsigned long end)
 {
-        tlb_flush_mmu(tlb);
+        tlb_table_flush(tlb);
 }
 /*
@@ -105,10 +91,8 @@ static inline void tlb_remove_page(struct mmu_gather *tlb, struct page *page)
 static inline void pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte,
                                unsigned long address)
 {
-#ifdef CONFIG_HAVE_RCU_TABLE_FREE
        if (!tlb->fullmm)
                return page_table_free_rcu(tlb, (unsigned long *) pte);
-#endif
        page_table_free(tlb->mm, (unsigned long *) pte);
 }
@@ -125,10 +109,8 @@ static inline void pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmd,
 #ifdef __s390x__
        if (tlb->mm->context.asce_limit <= (1UL << 31))
                return;
-#ifdef CONFIG_HAVE_RCU_TABLE_FREE
        if (!tlb->fullmm)
                return tlb_remove_table(tlb, pmd);
-#endif
        crst_table_free(tlb->mm, (unsigned long *) pmd);
 #endif
 }
@@ -146,10 +128,8 @@ static inline void pud_free_tlb(struct mmu_gather *tlb, pud_t *pud,
 #ifdef __s390x__
        if (tlb->mm->context.asce_limit <= (1UL << 42))
                return;
-#ifdef CONFIG_HAVE_RCU_TABLE_FREE
        if (!tlb->fullmm)
                return tlb_remove_table(tlb, pud);
-#endif
        crst_table_free(tlb->mm, (unsigned long *) pud);
 #endif
 }
diff --git a/arch/s390/kernel/.gitignore b/arch/s390/kernel/.gitignore
new file mode 100644
index 000000000000..c5f676c3c224
--- /dev/null
+++ b/arch/s390/kernel/.gitignore
@@ -0,0 +1 @@
+vmlinux.lds
diff --git a/arch/s390/kernel/Makefile b/arch/s390/kernel/Makefile
index 884b18afc864..9733b3f0eb6d 100644
--- a/arch/s390/kernel/Makefile
+++ b/arch/s390/kernel/Makefile
@@ -28,7 +28,7 @@ obj-y	:=  bitmap.o traps.o time.o process.o base.o early.o setup.o vtime.o \
 obj-y   += $(if $(CONFIG_64BIT),entry64.o,entry.o)
 obj-y   += $(if $(CONFIG_64BIT),reipl64.o,reipl.o)
-extra-y                         += head.o init_task.o vmlinux.lds
+extra-y                         += head.o vmlinux.lds
 extra-y                         += $(if $(CONFIG_64BIT),head64.o,head31.o)
 obj-$(CONFIG_MODULES)           += s390_ksyms.o module.o
diff --git a/arch/s390/kernel/compat_signal.c b/arch/s390/kernel/compat_signal.c
index 28040fd5e8a2..377c096ca4a7 100644
--- a/arch/s390/kernel/compat_signal.c
+++ b/arch/s390/kernel/compat_signal.c
@@ -437,13 +437,6 @@ get_sigframe(struct k_sigaction *ka, struct pt_regs * regs, size_t frame_size)
                        sp = current->sas_ss_sp + current->sas_ss_size;
        }
-        /* This is the legacy signal stack switching. */
-        else if (!user_mode(regs) &&
-                 !(ka->sa.sa_flags & SA_RESTORER) &&
-                 ka->sa.sa_restorer) {
-                sp = (unsigned long) ka->sa.sa_restorer;
-        }
        return (void __user *)((sp - frame_size) & -8ul);
 }
diff --git a/arch/s390/kernel/early.c b/arch/s390/kernel/early.c
index 9475e682727f..d84181f1f5e8 100644
--- a/arch/s390/kernel/early.c
+++ b/arch/s390/kernel/early.c
@@ -374,8 +374,6 @@ static __init void detect_machine_facilities(void)
                S390_lowcore.machine_flags |= MACHINE_FLAG_MVCOS;
        if (test_facility(40))
                S390_lowcore.machine_flags |= MACHINE_FLAG_SPP;
-        if (test_facility(25))
-                S390_lowcore.machine_flags |= MACHINE_FLAG_STCKF;
 #endif
 }
diff --git a/arch/s390/kernel/entry.S b/arch/s390/kernel/entry.S
index 74ee563fe62b..1ae93b573d7d 100644
--- a/arch/s390/kernel/entry.S
+++ b/arch/s390/kernel/entry.S
@@ -145,22 +145,23 @@ STACK_SIZE  = 1 << STACK_SHIFT
 *  gpr2 = prev
 */
 ENTRY(__switch_to)
+        stm     %r6,%r15,__SF_GPRS(%r15)        # store gprs of prev task
+        st      %r15,__THREAD_ksp(%r2)          # store kernel stack of prev
        l       %r4,__THREAD_info(%r2)          # get thread_info of prev
        l       %r5,__THREAD_info(%r3)          # get thread_info of next
+        lr      %r15,%r5
+        ahi     %r15,STACK_SIZE                 # end of kernel stack of next
+        st      %r3,__LC_CURRENT                # store task struct of next
+        st      %r5,__LC_THREAD_INFO            # store thread info of next
+        st      %r15,__LC_KERNEL_STACK          # store end of kernel stack
+        lctl    %c4,%c4,__TASK_pid(%r3)         # load pid to control reg. 4
+        mvc     __LC_CURRENT_PID(4,%r0),__TASK_pid(%r3) # store pid of next
+        l       %r15,__THREAD_ksp(%r3)          # load kernel stack of next
        tm      __TI_flags+3(%r4),_TIF_MCCK_PENDING # machine check pending?
        jz      0f
        ni      __TI_flags+3(%r4),255-_TIF_MCCK_PENDING # clear flag in prev
        oi      __TI_flags+3(%r5),_TIF_MCCK_PENDING     # set it in next
-0:      stm     %r6,%r15,__SF_GPRS(%r15)        # store gprs of prev task
+0:      lm      %r6,%r15,__SF_GPRS(%r15)        # load gprs of next task
-        st      %r15,__THREAD_ksp(%r2)          # store kernel stack of prev
-        l       %r15,__THREAD_ksp(%r3)          # load kernel stack of next
-        lctl    %c4,%c4,__TASK_pid(%r3)         # load pid to control reg. 4
-        lm      %r6,%r15,__SF_GPRS(%r15)        # load gprs of next task
-        st      %r3,__LC_CURRENT                # store task struct of next
-        mvc     __LC_CURRENT_PID(4,%r0),__TASK_pid(%r3) # store pid of next
-        st      %r5,__LC_THREAD_INFO            # store thread info of next
-        ahi     %r5,STACK_SIZE                  # end of kernel stack of next
-        st      %r5,__LC_KERNEL_STACK           # store end of kernel stack
        br      %r14
 __critical_start:
diff --git a/arch/s390/kernel/entry64.S b/arch/s390/kernel/entry64.S
index 4e1c292fa7e3..229fe1d07749 100644
--- a/arch/s390/kernel/entry64.S
+++ b/arch/s390/kernel/entry64.S
@@ -81,16 +81,14 @@ _TIF_EXIT_SIE = (_TIF_SIGPENDING | _TIF_NEED_RESCHED | _TIF_MCCK_PENDING)
        .macro  HANDLE_SIE_INTERCEPT scratch
 #if defined(CONFIG_KVM) || defined(CONFIG_KVM_MODULE)
-        tm      __TI_flags+6(%r12),_TIF_SIE>>8
+        tmhh    %r8,0x0001              # interrupting from user ?
-        jz      .+42
+        jnz     .+42
-        tm      __LC_MACHINE_FLAGS+6,0x20       # MACHINE_FLAG_SPP
-        jz      .+8
-        .insn   s,0xb2800000,BASED(.Lhost_id)   # set host id
        lgr     \scratch,%r9
        slg     \scratch,BASED(.Lsie_loop)
        clg     \scratch,BASED(.Lsie_length)
-        jhe     .+10
+        jhe     .+22
        lg      %r9,BASED(.Lsie_loop)
+        SPP     BASED(.Lhost_id)        # set host id
 #endif
        .endm
@@ -148,6 +146,14 @@ _TIF_EXIT_SIE = (_TIF_SIGPENDING | _TIF_NEED_RESCHED | _TIF_MCCK_PENDING)
        ssm     __LC_RETURN_PSW
        .endm
+        .macro STCK savearea
+#ifdef CONFIG_HAVE_MARCH_Z9_109_FEATURES
+        .insn   s,0xb27c0000,\savearea          # store clock fast
+#else
+        .insn   s,0xb2050000,\savearea          # store clock
+#endif
+        .endm
        .section .kprobes.text, "ax"
 /*
@@ -158,22 +164,23 @@ _TIF_EXIT_SIE = (_TIF_SIGPENDING | _TIF_NEED_RESCHED | _TIF_MCCK_PENDING)
 *  gpr2 = prev
 */
 ENTRY(__switch_to)
+        stmg    %r6,%r15,__SF_GPRS(%r15)        # store gprs of prev task
+        stg     %r15,__THREAD_ksp(%r2)          # store kernel stack of prev
        lg      %r4,__THREAD_info(%r2)          # get thread_info of prev
        lg      %r5,__THREAD_info(%r3)          # get thread_info of next
+        lgr     %r15,%r5
+        aghi    %r15,STACK_SIZE                 # end of kernel stack of next
+        stg     %r3,__LC_CURRENT                # store task struct of next
+        stg     %r5,__LC_THREAD_INFO            # store thread info of next
+        stg     %r15,__LC_KERNEL_STACK          # store end of kernel stack
+        lctl    %c4,%c4,__TASK_pid(%r3)         # load pid to control reg. 4
+        mvc     __LC_CURRENT_PID+4(4,%r0),__TASK_pid(%r3) # store pid of next
+        lg      %r15,__THREAD_ksp(%r3)          # load kernel stack of next
        tm      __TI_flags+7(%r4),_TIF_MCCK_PENDING # machine check pending?
        jz      0f
        ni      __TI_flags+7(%r4),255-_TIF_MCCK_PENDING # clear flag in prev
        oi      __TI_flags+7(%r5),_TIF_MCCK_PENDING     # set it in next
-0:      stmg    %r6,%r15,__SF_GPRS(%r15)        # store gprs of prev task
+0:      lmg     %r6,%r15,__SF_GPRS(%r15)        # load gprs of next task
-        stg     %r15,__THREAD_ksp(%r2)          # store kernel stack of prev
-        lg      %r15,__THREAD_ksp(%r3)          # load kernel stack of next
-        lctl    %c4,%c4,__TASK_pid(%r3)         # load pid to control reg. 4
-        lmg     %r6,%r15,__SF_GPRS(%r15)        # load gprs of next task
-        stg     %r3,__LC_CURRENT                # store task struct of next
-        mvc     __LC_CURRENT_PID+4(4,%r0),__TASK_pid(%r3) # store pid of next
-        stg     %r5,__LC_THREAD_INFO            # store thread info of next
-        aghi    %r5,STACK_SIZE                  # end of kernel stack of next
-        stg     %r5,__LC_KERNEL_STACK           # store end of kernel stack
        br      %r14
 __critical_start:
@@ -458,7 +465,7 @@ pgm_svcper:
 * IO interrupt handler routine
 */
 ENTRY(io_int_handler)
-        stck    __LC_INT_CLOCK
+        STCK    __LC_INT_CLOCK
        stpt    __LC_ASYNC_ENTER_TIMER
        stmg    %r8,%r15,__LC_SAVE_AREA_ASYNC
        lg      %r10,__LC_LAST_BREAK
@@ -604,7 +611,7 @@ io_notify_resume:
 * External interrupt handler routine
 */
 ENTRY(ext_int_handler)
-        stck    __LC_INT_CLOCK
+        STCK    __LC_INT_CLOCK
        stpt    __LC_ASYNC_ENTER_TIMER
        stmg    %r8,%r15,__LC_SAVE_AREA_ASYNC
        lg      %r10,__LC_LAST_BREAK
@@ -622,6 +629,7 @@ ext_skip:
        mvc     __PT_R8(64,%r11),__LC_SAVE_AREA_ASYNC
        stmg    %r8,%r9,__PT_PSW(%r11)
        TRACE_IRQS_OFF
+        xc      __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
        lghi    %r1,4096
        lgr     %r2,%r11                # pass pointer to pt_regs
        llgf    %r3,__LC_EXT_CPU_ADDR   # get cpu address + interruption code
@@ -638,7 +646,7 @@ ENTRY(psw_idle)
        larl    %r1,psw_idle_lpsw+4
        stg     %r1,__SF_EMPTY+8(%r15)
        larl    %r1,.Lvtimer_max
-        stck    __IDLE_ENTER(%r2)
+        STCK    __IDLE_ENTER(%r2)
        ltr     %r5,%r5
        stpt    __VQ_IDLE_ENTER(%r3)
        jz      psw_idle_lpsw
@@ -654,7 +662,7 @@ __critical_end:
 * Machine check handler routines
 */
 ENTRY(mcck_int_handler)
-        stck    __LC_MCCK_CLOCK
+        STCK    __LC_MCCK_CLOCK
        la      %r1,4095                # revalidate r1
        spt     __LC_CPU_TIMER_SAVE_AREA-4095(%r1)      # revalidate cpu timer
        lmg     %r0,%r15,__LC_GPREGS_SAVE_AREA-4095(%r1)# revalidate gprs
@@ -967,7 +975,6 @@ ENTRY(sie64a)
        xc      __SF_EMPTY+16(8,%r15),__SF_EMPTY+16(%r15) # host id == 0
        lmg     %r0,%r13,0(%r3)                 # load guest gprs 0-13
        lg      %r14,__LC_THREAD_INFO           # pointer thread_info struct
-        oi      __TI_flags+6(%r14),_TIF_SIE>>8
 sie_loop:
        lg      %r14,__LC_THREAD_INFO           # pointer thread_info struct
        tm      __TI_flags+7(%r14),_TIF_EXIT_SIE
@@ -985,7 +992,6 @@ sie_done:
        lg      %r14,__LC_THREAD_INFO           # pointer thread_info struct
 sie_exit:
        lctlg   %c1,%c1,__LC_USER_ASCE          # load primary asce
-        ni      __TI_flags+6(%r14),255-(_TIF_SIE>>8)
        lg      %r14,__SF_EMPTY+8(%r15)         # load guest register save area
        stmg    %r0,%r13,0(%r14)                # save guest gprs 0-13
        lmg     %r6,%r14,__SF_GPRS(%r15)        # restore kernel registers
@@ -994,7 +1000,6 @@ sie_exit:
 sie_fault:
        lctlg   %c1,%c1,__LC_USER_ASCE          # load primary asce
        lg      %r14,__LC_THREAD_INFO           # pointer thread_info struct
-        ni      __TI_flags+6(%r14),255-(_TIF_SIE>>8)
        lg      %r14,__SF_EMPTY+8(%r15)         # load guest register save area
        stmg    %r0,%r13,0(%r14)                # save guest gprs 0-13
        lmg     %r6,%r14,__SF_GPRS(%r15)        # restore kernel registers
diff --git a/arch/s390/kernel/head.S b/arch/s390/kernel/head.S
index c27a0727f930..4939d15375aa 100644
--- a/arch/s390/kernel/head.S
+++ b/arch/s390/kernel/head.S
@@ -34,125 +34,7 @@
 #endif
 __HEAD
-#ifndef CONFIG_IPL
-        .org   0
-        .long  0x00080000,0x80000000+startup    # Just a restart PSW
-#else
-#ifdef CONFIG_IPL_TAPE
-#define IPL_BS 1024
-        .org   0
-        .long  0x00080000,0x80000000+iplstart   # The first 24 bytes are loaded
-        .long  0x27000000,0x60000001            # by ipl to addresses 0-23.
-        .long  0x02000000,0x20000000+IPL_BS     # (a PSW and two CCWs).
-        .long  0x00000000,0x00000000            # external old psw
-        .long  0x00000000,0x00000000            # svc old psw
-        .long  0x00000000,0x00000000            # program check old psw
-        .long  0x00000000,0x00000000            # machine check old psw
-        .long  0x00000000,0x00000000            # io old psw
-        .long  0x00000000,0x00000000
-        .long  0x00000000,0x00000000
-        .long  0x00000000,0x00000000
-        .long  0x000a0000,0x00000058            # external new psw
-        .long  0x000a0000,0x00000060            # svc new psw
-        .long  0x000a0000,0x00000068            # program check new psw
-        .long  0x000a0000,0x00000070            # machine check new psw
-        .long  0x00080000,0x80000000+.Lioint    # io new psw
-        .org   0x100
-#
-# subroutine for loading from tape
-# Parameters:
-#  R1 = device number
-#  R2 = load address
-.Lloader:
-        st      %r14,.Lldret
-        la      %r3,.Lorbread           # r3 = address of orb
-        la      %r5,.Lirb               # r5 = address of irb
-        st      %r2,.Lccwread+4         # initialize CCW data addresses
-        lctl    %c6,%c6,.Lcr6
-        slr     %r2,%r2
-.Lldlp:
-        la      %r6,3                   # 3 retries
-.Lssch:
-        ssch    0(%r3)                  # load chunk of IPL_BS bytes
-        bnz     .Llderr
-.Lw4end:
-        bas     %r14,.Lwait4io
-        tm      8(%r5),0x82             # do we have a problem ?
-        bnz     .Lrecov
-        slr     %r7,%r7
-        icm     %r7,3,10(%r5)           # get residual count
-        lcr     %r7,%r7
-        la      %r7,IPL_BS(%r7)         # IPL_BS-residual=#bytes read
-        ar      %r2,%r7                 # add to total size
-        tm      8(%r5),0x01             # found a tape mark ?
-        bnz     .Ldone
-        l       %r0,.Lccwread+4         # update CCW data addresses
-        ar      %r0,%r7
-        st      %r0,.Lccwread+4
-        b       .Lldlp
-.Ldone:
-        l       %r14,.Lldret
-        br      %r14                    # r2 contains the total size
-.Lrecov:
-        bas     %r14,.Lsense            # do the sensing
-        bct     %r6,.Lssch              # dec. retry count & branch
-        b       .Llderr
-#
-# Sense subroutine
-#
-.Lsense:
-        st      %r14,.Lsnsret
-        la      %r7,.Lorbsense
-        ssch    0(%r7)                  # start sense command
-        bnz     .Llderr
-        bas     %r14,.Lwait4io
-        l       %r14,.Lsnsret
-        tm      8(%r5),0x82             # do we have a problem ?
-        bnz     .Llderr
-        br      %r14
-#
-# Wait for interrupt subroutine
-#
-.Lwait4io:
-        lpsw    .Lwaitpsw
-.Lioint:
-        c       %r1,0xb8                # compare subchannel number
-        bne     .Lwait4io
-        tsch    0(%r5)
-        slr     %r0,%r0
-        tm      8(%r5),0x82             # do we have a problem ?
-        bnz     .Lwtexit
-        tm      8(%r5),0x04             # got device end ?
-        bz      .Lwait4io
-.Lwtexit:
-        br      %r14
-.Llderr:
-        lpsw    .Lcrash
-        .align  8
-.Lorbread:
-        .long   0x00000000,0x0080ff00,.Lccwread
-        .align  8
-.Lorbsense:
-        .long   0x00000000,0x0080ff00,.Lccwsense
-        .align  8
-.Lccwread:
-        .long   0x02200000+IPL_BS,0x00000000
-.Lccwsense:
-        .long   0x04200001,0x00000000
-.Lwaitpsw:
-        .long   0x020a0000,0x80000000+.Lioint
-.Lirb:  .long   0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
-.Lcr6:  .long   0xff000000
-        .align  8
-.Lcrash:.long   0x000a0000,0x00000000
-.Lldret:.long   0
-.Lsnsret: .long 0
-#endif  /* CONFIG_IPL_TAPE */
-#ifdef CONFIG_IPL_VM
 #define IPL_BS  0x730
        .org    0
        .long   0x00080000,0x80000000+iplstart  # The first 24 bytes are loaded
@@ -256,7 +138,6 @@ __HEAD
        .long   0x02600050,0x00000000
        .endr
        .long   0x02200050,0x00000000
-#endif  /* CONFIG_IPL_VM */
 iplstart:
        lh      %r1,0xb8                # test if subchannel number
@@ -325,7 +206,6 @@ iplstart:
        clc     0(3,%r2),.L_eof
        bz      .Lagain2
-#ifdef CONFIG_IPL_VM
 #
 # reset files in VM reader
 #
@@ -358,7 +238,6 @@ iplstart:
        .long   0x00080000,0x80000000+.Lrdrint
 .Lrdrwaitpsw:
        .long   0x020a0000,0x80000000+.Lrdrint
-#endif
 #
 # everything loaded, go for it
@@ -376,8 +255,6 @@ iplstart:
 .L_eof: .long   0xc5d6c600       /* C'EOF' */
 .L_hdr: .long   0xc8c4d900       /* C'HDR' */
-#endif  /* CONFIG_IPL */
 #
 # SALIPL loader support. Based on a patch by Rob van der Heij.
 # This entry point is called directly from the SALIPL loader and
@@ -474,9 +351,9 @@ ENTRY(startup_kdump)
        stck    __LC_LAST_UPDATE_CLOCK
        spt     5f-.LPG0(%r13)
        mvc     __LC_LAST_UPDATE_TIMER(8),5f-.LPG0(%r13)
+        xc      __LC_STFL_FAC_LIST(8),__LC_STFL_FAC_LIST
 #ifndef CONFIG_MARCH_G5
        # check capabilities against MARCH_{G5,Z900,Z990,Z9_109,Z10}
-        xc      __LC_STFL_FAC_LIST(8),__LC_STFL_FAC_LIST
        .insn   s,0xb2b10000,__LC_STFL_FAC_LIST # store facility list
        tm      __LC_STFL_FAC_LIST,0x01 # stfle available ?
        jz      0f
diff --git a/arch/s390/kernel/init_task.c b/arch/s390/kernel/init_task.c
deleted file mode 100644
index 4d1c9fb0b540..000000000000
--- a/arch/s390/kernel/init_task.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- *  arch/s390/kernel/init_task.c
- *
- *  S390 version
- *
- *  Derived from "arch/i386/kernel/init_task.c"
- */
-#include <linux/mm.h>
-#include <linux/fs.h>
-#include <linux/module.h>
-#include <linux/sched.h>
-#include <linux/init_task.h>
-#include <linux/mqueue.h>
-#include <asm/uaccess.h>
-#include <asm/pgtable.h>
-static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
-static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
-/*
- * Initial thread structure.
- *
- * We need to make sure that this is THREAD_SIZE aligned due to the
- * way process stacks are handled. This is done by having a special
- * "init_task" linker map entry..
- */
-union thread_union init_thread_union __init_task_data =
-        { INIT_THREAD_INFO(init_task) };
-/*
- * Initial task structure.
- *
- * All other task structs will be allocated on slabs in fork.c
- */
-struct task_struct init_task = INIT_TASK(init_task);
-EXPORT_SYMBOL(init_task);
diff --git a/arch/s390/kernel/irq.c b/arch/s390/kernel/irq.c
index 1c2cdd59ccd0..8a22c27219dd 100644
--- a/arch/s390/kernel/irq.c
+++ b/arch/s390/kernel/irq.c
@@ -118,9 +118,10 @@ asmlinkage void do_softirq(void)
                                         "a" (__do_softirq)
                                     : "0", "1", "2", "3", "4", "5", "14",
                                       "cc", "memory" );
-                } else
+                } else {
                        /* We are already on the async stack. */
                        __do_softirq();
+                }
        }
        local_irq_restore(flags);
@@ -192,11 +193,12 @@ int unregister_external_interrupt(u16 code, ext_int_handler_t handler)
        int index = ext_hash(code);
        spin_lock_irqsave(&ext_int_hash_lock, flags);
-        list_for_each_entry_rcu(p, &ext_int_hash[index], entry)
+        list_for_each_entry_rcu(p, &ext_int_hash[index], entry) {
                if (p->code == code && p->handler == handler) {
                        list_del_rcu(&p->entry);
                        kfree_rcu(p, rcu);
                }
+        }
        spin_unlock_irqrestore(&ext_int_hash_lock, flags);
        return 0;
 }
@@ -211,9 +213,10 @@ void __irq_entry do_extint(struct pt_regs *regs, struct ext_code ext_code,
        old_regs = set_irq_regs(regs);
        irq_enter();
-        if (S390_lowcore.int_clock >= S390_lowcore.clock_comparator)
+        if (S390_lowcore.int_clock >= S390_lowcore.clock_comparator) {
                /* Serve timer interrupts first. */
                clock_comparator_work();
+        }
        kstat_cpu(smp_processor_id()).irqs[EXTERNAL_INTERRUPT]++;
        if (ext_code.code != 0x1004)
                __get_cpu_var(s390_idle).nohz_delay = 1;
diff --git a/arch/s390/kernel/perf_cpum_cf.c b/arch/s390/kernel/perf_cpum_cf.c
index 46405086479c..cb019f429e88 100644
--- a/arch/s390/kernel/perf_cpum_cf.c
+++ b/arch/s390/kernel/perf_cpum_cf.c
@@ -178,7 +178,7 @@ static void cpumf_pmu_enable(struct pmu *pmu)
        err = lcctl(cpuhw->state);
        if (err) {
                pr_err("Enabling the performance measuring unit "
-                       "failed with rc=%lx\n", err);
+                       "failed with rc=%x\n", err);
                return;
        }
@@ -203,7 +203,7 @@ static void cpumf_pmu_disable(struct pmu *pmu)
        err = lcctl(inactive);
        if (err) {
                pr_err("Disabling the performance measuring unit "
-                       "failed with rc=%lx\n", err);
+                       "failed with rc=%x\n", err);
                return;
        }
diff --git a/arch/s390/kernel/ptrace.c b/arch/s390/kernel/ptrace.c
index 02f300fbf070..4993e689b2c2 100644
--- a/arch/s390/kernel/ptrace.c
+++ b/arch/s390/kernel/ptrace.c
@@ -719,7 +719,7 @@ asmlinkage long do_syscall_trace_enter(struct pt_regs *regs)
        long ret = 0;
        /* Do the secure computing check first. */
-        secure_computing(regs->gprs[2]);
+        secure_computing_strict(regs->gprs[2]);
        /*
         * The sysc_tracesys code in entry.S stored the system
diff --git a/arch/s390/kernel/signal.c b/arch/s390/kernel/signal.c
index f7582b27f600..8a4e2b760d56 100644
--- a/arch/s390/kernel/signal.c
+++ b/arch/s390/kernel/signal.c
@@ -235,13 +235,6 @@ get_sigframe(struct k_sigaction *ka, struct pt_regs * regs, size_t frame_size)
                        sp = current->sas_ss_sp + current->sas_ss_size;
        }
-        /* This is the legacy signal stack switching. */
-        else if (!user_mode(regs) &&
-                 !(ka->sa.sa_flags & SA_RESTORER) &&
-                 ka->sa.sa_restorer) {
-                sp = (unsigned long) ka->sa.sa_restorer;
-        }
        return (void __user *)((sp - frame_size) & -8ul);
 }
@@ -414,15 +407,6 @@ void do_signal(struct pt_regs *regs)
        struct k_sigaction ka;
        sigset_t *oldset;
-        /*
-         * We want the common case to go fast, which
-         * is why we may in certain cases get here from
-         * kernel mode. Just return without doing anything
-         * if so.
-         */
-        if (!user_mode(regs))
-                return;
        if (test_thread_flag(TIF_RESTORE_SIGMASK))
                oldset = &current->saved_sigmask;
        else
diff --git a/arch/s390/kernel/smp.c b/arch/s390/kernel/smp.c
index 1f77227669e8..647ba9425893 100644
--- a/arch/s390/kernel/smp.c
+++ b/arch/s390/kernel/smp.c
@@ -85,7 +85,6 @@ enum {
 struct pcpu {
        struct cpu cpu;
-        struct task_struct *idle;       /* idle process for the cpu */
        struct _lowcore *lowcore;       /* lowcore page(s) for the cpu */
        unsigned long async_stack;      /* async stack for the cpu */
        unsigned long panic_stack;      /* panic stack for the cpu */
@@ -226,6 +225,8 @@ out:
        return -ENOMEM;
 }
+#ifdef CONFIG_HOTPLUG_CPU
 static void pcpu_free_lowcore(struct pcpu *pcpu)
 {
        pcpu_sigp_retry(pcpu, sigp_set_prefix, 0);
@@ -247,6 +248,8 @@ static void pcpu_free_lowcore(struct pcpu *pcpu)
        }
 }
+#endif /* CONFIG_HOTPLUG_CPU */
 static void pcpu_prepare_secondary(struct pcpu *pcpu, int cpu)
 {
        struct _lowcore *lc = pcpu->lowcore;
@@ -721,26 +724,9 @@ static void __cpuinit smp_start_secondary(void *cpuvoid)
        cpu_idle();
 }
-struct create_idle {
-        struct work_struct work;
-        struct task_struct *idle;
-        struct completion done;
-        int cpu;
-};
-static void __cpuinit smp_fork_idle(struct work_struct *work)
-{
-        struct create_idle *c_idle;
-        c_idle = container_of(work, struct create_idle, work);
-        c_idle->idle = fork_idle(c_idle->cpu);
-        complete(&c_idle->done);
-}
 /* Upping and downing of CPUs */
-int __cpuinit __cpu_up(unsigned int cpu)
+int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *tidle)
 {
-        struct create_idle c_idle;
        struct pcpu *pcpu;
        int rc;
@@ -750,22 +736,12 @@ int __cpuinit __cpu_up(unsigned int cpu)
        if (pcpu_sigp_retry(pcpu, sigp_initial_cpu_reset, 0) !=
            sigp_order_code_accepted)
                return -EIO;
-        if (!pcpu->idle) {
-                c_idle.done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done);
-                INIT_WORK_ONSTACK(&c_idle.work, smp_fork_idle);
-                c_idle.cpu = cpu;
-                schedule_work(&c_idle.work);
-                wait_for_completion(&c_idle.done);
-                if (IS_ERR(c_idle.idle))
-                        return PTR_ERR(c_idle.idle);
-                pcpu->idle = c_idle.idle;
-        }
-        init_idle(pcpu->idle, cpu);
        rc = pcpu_alloc_lowcore(pcpu, cpu);
        if (rc)
                return rc;
        pcpu_prepare_secondary(pcpu, cpu);
-        pcpu_attach_task(pcpu, pcpu->idle);
+        pcpu_attach_task(pcpu, tidle);
        pcpu_start_fn(pcpu, smp_start_secondary, NULL);
        while (!cpu_online(cpu))
                cpu_relax();
@@ -852,7 +828,6 @@ void __init smp_prepare_boot_cpu(void)
        struct pcpu *pcpu = pcpu_devices;
        boot_cpu_address = stap();
-        pcpu->idle = current;
        pcpu->state = CPU_STATE_CONFIGURED;
        pcpu->address = boot_cpu_address;
        pcpu->lowcore = (struct _lowcore *)(unsigned long) store_prefix();
diff --git a/arch/s390/kernel/vdso32/.gitignore b/arch/s390/kernel/vdso32/.gitignore
new file mode 100644
index 000000000000..e45fba9d0ced
--- /dev/null
+++ b/arch/s390/kernel/vdso32/.gitignore
@@ -0,0 +1 @@
+vdso32.lds
diff --git a/arch/s390/kernel/vdso64/.gitignore b/arch/s390/kernel/vdso64/.gitignore
new file mode 100644
index 000000000000..3fd18cf9fec2
--- /dev/null
+++ b/arch/s390/kernel/vdso64/.gitignore
@@ -0,0 +1 @@
+vdso64.lds
diff --git a/arch/s390/mm/fault.c b/arch/s390/mm/fault.c
index 46ef3fd0663b..72cec9ecd96c 100644
--- a/arch/s390/mm/fault.c
+++ b/arch/s390/mm/fault.c
@@ -294,7 +294,7 @@ static inline int do_exception(struct pt_regs *regs, int access)
        down_read(&mm->mmap_sem);
 #ifdef CONFIG_PGSTE
-        if (test_tsk_thread_flag(current, TIF_SIE) && S390_lowcore.gmap) {
+        if ((current->flags & PF_VCPU) && S390_lowcore.gmap) {
                address = __gmap_fault(address,
                                     (struct gmap *) S390_lowcore.gmap);
                if (address == -EFAULT) {
@@ -549,19 +549,15 @@ static void pfault_interrupt(struct ext_code ext_code,
        if ((subcode & 0xff00) != __SUBCODE_MASK)
                return;
        kstat_cpu(smp_processor_id()).irqs[EXTINT_PFL]++;
-        if (subcode & 0x0080) {
+        /* Get the token (= pid of the affected task). */
-                /* Get the token (= pid of the affected task). */
+        pid = sizeof(void *) == 4 ? param32 : param64;
-                pid = sizeof(void *) == 4 ? param32 : param64;
+        rcu_read_lock();
-                rcu_read_lock();
+        tsk = find_task_by_pid_ns(pid, &init_pid_ns);
-                tsk = find_task_by_pid_ns(pid, &init_pid_ns);
+        if (tsk)
-                if (tsk)
+                get_task_struct(tsk);
-                        get_task_struct(tsk);
+        rcu_read_unlock();
-                rcu_read_unlock();
+        if (!tsk)
-                if (!tsk)
+                return;
-                        return;
-        } else {
-                tsk = current;
-        }
        spin_lock(&pfault_lock);
        if (subcode & 0x0080) {
                /* signal bit is set -> a page has been swapped in by VM */
@@ -574,6 +570,7 @@ static void pfault_interrupt(struct ext_code ext_code,
                        tsk->thread.pfault_wait = 0;
                        list_del(&tsk->thread.list);
                        wake_up_process(tsk);
+                        put_task_struct(tsk);
                } else {
                        /* Completion interrupt was faster than initial
                         * interrupt. Set pfault_wait to -1 so the initial
@@ -585,24 +582,35 @@ static void pfault_interrupt(struct ext_code ext_code,
                        if (tsk->state == TASK_RUNNING)
                                tsk->thread.pfault_wait = -1;
                }
-                put_task_struct(tsk);
        } else {
                /* signal bit not set -> a real page is missing. */
-                if (tsk->thread.pfault_wait == -1) {
+                if (WARN_ON_ONCE(tsk != current))
+                        goto out;
+                if (tsk->thread.pfault_wait == 1) {
+                        /* Already on the list with a reference: put to sleep */
+                        __set_task_state(tsk, TASK_UNINTERRUPTIBLE);
+                        set_tsk_need_resched(tsk);
+                } else if (tsk->thread.pfault_wait == -1) {
                        /* Completion interrupt was faster than the initial
                         * interrupt (pfault_wait == -1). Set pfault_wait
                         * back to zero and exit. */
                        tsk->thread.pfault_wait = 0;
                } else {
                        /* Initial interrupt arrived before completion
-                         * interrupt. Let the task sleep. */
+                         * interrupt. Let the task sleep.
+                         * An extra task reference is needed since a different
+                         * cpu may set the task state to TASK_RUNNING again
+                         * before the scheduler is reached. */
+                        get_task_struct(tsk);
                        tsk->thread.pfault_wait = 1;
                        list_add(&tsk->thread.list, &pfault_list);
-                        set_task_state(tsk, TASK_UNINTERRUPTIBLE);
+                        __set_task_state(tsk, TASK_UNINTERRUPTIBLE);
                        set_tsk_need_resched(tsk);
                }
        }
+out:
        spin_unlock(&pfault_lock);
+        put_task_struct(tsk);
 }
 static int __cpuinit pfault_cpu_notify(struct notifier_block *self,
@@ -620,6 +628,7 @@ static int __cpuinit pfault_cpu_notify(struct notifier_block *self,
                        list_del(&thread->list);
                        tsk = container_of(thread, struct task_struct, thread);
                        wake_up_process(tsk);
+                        put_task_struct(tsk);
                }
                spin_unlock_irq(&pfault_lock);
                break;
diff --git a/arch/s390/mm/hugetlbpage.c b/arch/s390/mm/hugetlbpage.c
index 597bb2d27c3c..900de2b3cf28 100644
--- a/arch/s390/mm/hugetlbpage.c
+++ b/arch/s390/mm/hugetlbpage.c
@@ -58,6 +58,8 @@ void arch_release_hugepage(struct page *page)
        ptep = (pte_t *) page[1].index;
        if (!ptep)
                return;
+        clear_table((unsigned long *) ptep, _PAGE_TYPE_EMPTY,
+                    PTRS_PER_PTE * sizeof(pte_t));
        page_table_free(&init_mm, (unsigned long *) ptep);
        page[1].index = 0;
 }
diff --git a/arch/s390/mm/maccess.c b/arch/s390/mm/maccess.c
index 7bb15fcca75e..795a0a9bb2eb 100644
--- a/arch/s390/mm/maccess.c
+++ b/arch/s390/mm/maccess.c
@@ -12,6 +12,7 @@
 #include <linux/types.h>
 #include <linux/errno.h>
 #include <linux/gfp.h>
+#include <linux/cpu.h>
 #include <asm/ctl_reg.h>
 /*
@@ -61,21 +62,14 @@ long probe_kernel_write(void *dst, const void *src, size_t size)
        return copied < 0 ? -EFAULT : 0;
 }
-/*
+static int __memcpy_real(void *dest, void *src, size_t count)
- * Copy memory in real mode (kernel to kernel)
- */
-int memcpy_real(void *dest, void *src, size_t count)
 {
        register unsigned long _dest asm("2") = (unsigned long) dest;
        register unsigned long _len1 asm("3") = (unsigned long) count;
        register unsigned long _src  asm("4") = (unsigned long) src;
        register unsigned long _len2 asm("5") = (unsigned long) count;
-        unsigned long flags;
        int rc = -EFAULT;
-        if (!count)
-                return 0;
-        flags = __arch_local_irq_stnsm(0xf8UL);
        asm volatile (
                "0:     mvcle   %1,%2,0x0\n"
                "1:     jo      0b\n"
@@ -86,7 +80,23 @@ int memcpy_real(void *dest, void *src, size_t count)
                  "+d" (_len2), "=m" (*((long *) dest))
                : "m" (*((long *) src))
                : "cc", "memory");
-        arch_local_irq_restore(flags);
+        return rc;
+}
+/*
+ * Copy memory in real mode (kernel to kernel)
+ */
+int memcpy_real(void *dest, void *src, size_t count)
+{
+        unsigned long flags;
+        int rc;
+        if (!count)
+                return 0;
+        local_irq_save(flags);
+        __arch_local_irq_stnsm(0xfbUL);
+        rc = __memcpy_real(dest, src, count);
+        local_irq_restore(flags);
        return rc;
 }
@@ -157,3 +167,69 @@ out:
        free_page((unsigned long) buf);
        return rc;
 }
+/*
+ * Check if physical address is within prefix or zero page
+ */
+static int is_swapped(unsigned long addr)
+{
+        unsigned long lc;
+        int cpu;
+        if (addr < sizeof(struct _lowcore))
+                return 1;
+        for_each_online_cpu(cpu) {
+                lc = (unsigned long) lowcore_ptr[cpu];
+                if (addr > lc + sizeof(struct _lowcore) - 1 || addr < lc)
+                        continue;
+                return 1;
+        }
+        return 0;
+}
+/*
+ * Return swapped prefix or zero page address
+ */
+static unsigned long get_swapped(unsigned long addr)
+{
+        unsigned long prefix = store_prefix();
+        if (addr < sizeof(struct _lowcore))
+                return addr + prefix;
+        if (addr >= prefix && addr < prefix + sizeof(struct _lowcore))
+                return addr - prefix;
+        return addr;
+}
+/*
+ * Convert a physical pointer for /dev/mem access
+ *
+ * For swapped prefix pages a new buffer is returned that contains a copy of
+ * the absolute memory. The buffer size is maximum one page large.
+ */
+void *xlate_dev_mem_ptr(unsigned long addr)
+{
+        void *bounce = (void *) addr;
+        unsigned long size;
+        get_online_cpus();
+        preempt_disable();
+        if (is_swapped(addr)) {
+                size = PAGE_SIZE - (addr & ~PAGE_MASK);
+                bounce = (void *) __get_free_page(GFP_ATOMIC);
+                if (bounce)
+                        memcpy_real(bounce, (void *) get_swapped(addr), size);
+        }
+        preempt_enable();
+        put_online_cpus();
+        return bounce;
+}
+/*
+ * Free converted buffer for /dev/mem access (if necessary)
+ */
+void unxlate_dev_mem_ptr(unsigned long addr, void *buf)
+{
+        if ((void *) addr != buf)
+                free_page((unsigned long) buf);
+}
diff --git a/arch/s390/mm/pgtable.c b/arch/s390/mm/pgtable.c
index 373adf69b01c..a3db5a3ea083 100644
--- a/arch/s390/mm/pgtable.c
+++ b/arch/s390/mm/pgtable.c
@@ -678,8 +678,6 @@ void page_table_free(struct mm_struct *mm, unsigned long *table)
        }
 }
-#ifdef CONFIG_HAVE_RCU_TABLE_FREE
 static void __page_table_free_rcu(void *table, unsigned bit)
 {
        struct page *page;
@@ -733,7 +731,66 @@ void __tlb_remove_table(void *_table)
                free_pages((unsigned long) table, ALLOC_ORDER);
 }
-#endif
+static void tlb_remove_table_smp_sync(void *arg)
+{
+        /* Simply deliver the interrupt */
+}
+static void tlb_remove_table_one(void *table)
+{
+        /*
+         * This isn't an RCU grace period and hence the page-tables cannot be
+         * assumed to be actually RCU-freed.
+         *
+         * It is however sufficient for software page-table walkers that rely
+         * on IRQ disabling. See the comment near struct mmu_table_batch.
+         */
+        smp_call_function(tlb_remove_table_smp_sync, NULL, 1);
+        __tlb_remove_table(table);
+}
+static void tlb_remove_table_rcu(struct rcu_head *head)
+{
+        struct mmu_table_batch *batch;
+        int i;
+        batch = container_of(head, struct mmu_table_batch, rcu);
+        for (i = 0; i < batch->nr; i++)
+                __tlb_remove_table(batch->tables[i]);
+        free_page((unsigned long)batch);
+}
+void tlb_table_flush(struct mmu_gather *tlb)
+{
+        struct mmu_table_batch **batch = &tlb->batch;
+        if (*batch) {
+                __tlb_flush_mm(tlb->mm);
+                call_rcu_sched(&(*batch)->rcu, tlb_remove_table_rcu);
+                *batch = NULL;
+        }
+}
+void tlb_remove_table(struct mmu_gather *tlb, void *table)
+{
+        struct mmu_table_batch **batch = &tlb->batch;
+        if (*batch == NULL) {
+                *batch = (struct mmu_table_batch *)
+                        __get_free_page(GFP_NOWAIT | __GFP_NOWARN);
+                if (*batch == NULL) {
+                        __tlb_flush_mm(tlb->mm);
+                        tlb_remove_table_one(table);
+                        return;
+                }
+                (*batch)->nr = 0;
+        }
+        (*batch)->tables[(*batch)->nr++] = table;
+        if ((*batch)->nr == MAX_TABLE_BATCH)
+                tlb_table_flush(tlb);
+}
 /*
 * switch on pgstes for its userspace process (for kvm)
@@ -765,6 +822,8 @@ int s390_enable_sie(void)
        /* we copy the mm and let dup_mm create the page tables with_pgstes */
        tsk->mm->context.alloc_pgste = 1;
+        /* make sure that both mms have a correct rss state */
+        sync_mm_rss(tsk->mm);
        mm = dup_mm(tsk);
        tsk->mm->context.alloc_pgste = 0;
        if (!mm)
diff --git a/arch/score/include/asm/thread_info.h b/arch/score/include/asm/thread_info.h
index 2205c62284db..a18006e97f1c 100644
--- a/arch/score/include/asm/thread_info.h
+++ b/arch/score/include/asm/thread_info.h
@@ -11,10 +11,9 @@
 #include <linux/const.h>
 /* thread information allocation */
-#define THREAD_SIZE_ORDER       (1)
+#define THREAD_SIZE_ORDER       (1)
-#define THREAD_SIZE             (PAGE_SIZE << THREAD_SIZE_ORDER)
+#define THREAD_SIZE             (PAGE_SIZE << THREAD_SIZE_ORDER)
-#define THREAD_MASK             (THREAD_SIZE - _AC(1,UL))
+#define THREAD_MASK             (THREAD_SIZE - _AC(1,UL))
-#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR
 #ifndef __ASSEMBLY__
@@ -71,9 +70,6 @@ struct thread_info {
 register struct thread_info *__current_thread_info __asm__("r28");
 #define current_thread_info()   __current_thread_info
-#define alloc_thread_info_node(tsk, node) kmalloc_node(THREAD_SIZE, GFP_KERNEL, node)
-#define free_thread_info(info) kfree(info)
 #endif /* !__ASSEMBLY__ */
 #define PREEMPT_ACTIVE          0x10000000
diff --git a/arch/score/kernel/Makefile b/arch/score/kernel/Makefile
index f218673b5d3d..fb1802b3f542 100644
--- a/arch/score/kernel/Makefile
+++ b/arch/score/kernel/Makefile
@@ -4,7 +4,7 @@
 extra-y := head.o vmlinux.lds
-obj-y += entry.o init_task.o irq.o process.o ptrace.o \
+obj-y += entry.o irq.o process.o ptrace.o \
        setup.o signal.o sys_score.o time.o traps.o \
        sys_call_table.o
diff --git a/arch/score/kernel/init_task.c b/arch/score/kernel/init_task.c
deleted file mode 100644
index baa03ee217d1..000000000000
--- a/arch/score/kernel/init_task.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * arch/score/kernel/init_task.c
- *
- * Score Processor version.
- *
- * Copyright (C) 2009 Sunplus Core Technology Co., Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-#include <linux/init_task.h>
-#include <linux/mqueue.h>
-static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
-static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
-/*
- * Initial thread structure.
- *
- * We need to make sure that this is THREAD_SIZE aligned due to the
- * way process stacks are handled. This is done by having a special
- * "init_task" linker map entry..
- */
-union thread_union init_thread_union __init_task_data =
-        { INIT_THREAD_INFO(init_task) };
-/*
- * Initial task structure.
- *
- * All other task structs will be allocated on slabs in fork.c
- */
-struct task_struct init_task = INIT_TASK(init_task);
-EXPORT_SYMBOL(init_task);
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index ff9e033ce626..04a8cb4700af 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -28,6 +28,7 @@ config SUPERH
        select RTC_LIB
        select GENERIC_ATOMIC64
        select GENERIC_IRQ_SHOW
+        select GENERIC_SMP_IDLE_THREAD
        help
          The SuperH is a RISC processor targeted for use in embedded systems
          and consumer electronics; it was also used in the Sega Dreamcast
@@ -152,9 +153,6 @@ config ARCH_NO_VIRT_TO_BUS
 config ARCH_HAS_DEFAULT_IDLE
        def_bool y
-config ARCH_HAS_CPU_IDLE_WAIT
-        def_bool y
 config NO_IOPORT
        def_bool !PCI
        depends on !SH_CAYMAN && !SH_SH4202_MICRODEV && !SH_SHMIN
diff --git a/arch/sh/Makefile b/arch/sh/Makefile
index 3fc0f413777c..e14a676a0c7d 100644
--- a/arch/sh/Makefile
+++ b/arch/sh/Makefile
@@ -124,7 +124,7 @@ endif
 export ld-bfd BITS
-head-y  := arch/sh/kernel/init_task.o arch/sh/kernel/head_$(BITS).o
+head-y  := arch/sh/kernel/head_$(BITS).o
 core-y                          += arch/sh/kernel/ arch/sh/mm/ arch/sh/boards/
 core-$(CONFIG_SH_FPU_EMU)       += arch/sh/math-emu/
diff --git a/arch/sh/configs/sh7785lcr_32bit_defconfig b/arch/sh/configs/sh7785lcr_32bit_defconfig
index 7b9c696ac5e0..9bdcf72ec06a 100644
--- a/arch/sh/configs/sh7785lcr_32bit_defconfig
+++ b/arch/sh/configs/sh7785lcr_32bit_defconfig
@@ -5,7 +5,7 @@ CONFIG_BSD_PROCESS_ACCT=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=16
-CONFIG_PERF_COUNTERS=y
+CONFIG_PERF_EVENTS=y
 # CONFIG_COMPAT_BRK is not set
 CONFIG_SLAB=y
 CONFIG_PROFILING=y
diff --git a/arch/sh/include/asm/atomic.h b/arch/sh/include/asm/atomic.h
index 37f2f4a55231..f4c1c20bcdf6 100644
--- a/arch/sh/include/asm/atomic.h
+++ b/arch/sh/include/asm/atomic.h
@@ -11,7 +11,7 @@
 #include <linux/types.h>
 #include <asm/cmpxchg.h>
-#define ATOMIC_INIT(i)  ( (atomic_t) { (i) } )
+#define ATOMIC_INIT(i)  { (i) }
 #define atomic_read(v)          (*(volatile int *)&(v)->counter)
 #define atomic_set(v,i)         ((v)->counter = (i))
diff --git a/arch/sh/include/asm/processor.h b/arch/sh/include/asm/processor.h
index a229c393826a..6dbc1be28a0f 100644
--- a/arch/sh/include/asm/processor.h
+++ b/arch/sh/include/asm/processor.h
@@ -85,10 +85,6 @@ struct sh_cpuinfo {
        struct tlb_info itlb;
        struct tlb_info dtlb;
-#ifdef CONFIG_SMP
-        struct task_struct *idle;
-#endif
        unsigned int phys_bits;
        unsigned long flags;
 } __attribute__ ((aligned(L1_CACHE_BYTES)));
@@ -102,7 +98,6 @@ extern struct sh_cpuinfo cpu_data[];
 #define cpu_relax()     barrier()
 void default_idle(void);
-void cpu_idle_wait(void);
 void stop_this_cpu(void *);
 /* Forward decl */
diff --git a/arch/sh/include/asm/thread_info.h b/arch/sh/include/asm/thread_info.h
index 20ee40af16e9..b6902061d4dc 100644
--- a/arch/sh/include/asm/thread_info.h
+++ b/arch/sh/include/asm/thread_info.h
@@ -88,22 +88,13 @@ static inline struct thread_info *current_thread_info(void)
        return ti;
 }
-/* thread information allocation */
-#if THREAD_SHIFT >= PAGE_SHIFT
 #define THREAD_SIZE_ORDER       (THREAD_SHIFT - PAGE_SHIFT)
-#endif
-extern struct thread_info *alloc_thread_info_node(struct task_struct *tsk, int node);
-extern void free_thread_info(struct thread_info *ti);
 extern void arch_task_cache_init(void);
-#define arch_task_cache_init arch_task_cache_init
 extern int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src);
+extern void arch_release_task_struct(struct task_struct *tsk);
 extern void init_thread_xstate(void);
-#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR
 #endif /* __ASSEMBLY__ */
 /*
diff --git a/arch/sh/include/asm/topology.h b/arch/sh/include/asm/topology.h
index 88e734069fa6..b0a282d65f6a 100644
--- a/arch/sh/include/asm/topology.h
+++ b/arch/sh/include/asm/topology.h
@@ -3,31 +3,6 @@
 #ifdef CONFIG_NUMA
-/* sched_domains SD_NODE_INIT for sh machines */
-#define SD_NODE_INIT (struct sched_domain) {            \
-        .parent                 = NULL,                 \
-        .child                  = NULL,                 \
-        .groups                 = NULL,                 \
-        .min_interval           = 8,                    \
-        .max_interval           = 32,                   \
-        .busy_factor            = 32,                   \
-        .imbalance_pct          = 125,                  \
-        .cache_nice_tries       = 2,                    \
-        .busy_idx               = 3,                    \
-        .idle_idx               = 2,                    \
-        .newidle_idx            = 0,                    \
-        .wake_idx               = 0,                    \
-        .forkexec_idx           = 0,                    \
-        .flags                  = SD_LOAD_BALANCE       \
-                                | SD_BALANCE_FORK       \
-                                | SD_BALANCE_EXEC       \
-                                | SD_BALANCE_NEWIDLE    \
-                                | SD_SERIALIZE,         \
-        .last_balance           = jiffies,              \
-        .balance_interval       = 1,                    \
-        .nr_balance_failed      = 0,                    \
-}
 #define cpu_to_node(cpu)        ((void)(cpu),0)
 #define parent_node(node)       ((void)(node),0)
diff --git a/arch/sh/kernel/Makefile b/arch/sh/kernel/Makefile
index 77f7ae1d4647..88571ff8eeec 100644
--- a/arch/sh/kernel/Makefile
+++ b/arch/sh/kernel/Makefile
@@ -2,7 +2,7 @@
 # Makefile for the Linux/SuperH kernel.
 #
-extra-y := head_$(BITS).o init_task.o vmlinux.lds
+extra-y := head_$(BITS).o vmlinux.lds
 ifdef CONFIG_FUNCTION_TRACER
 # Do not profile debug and lowlevel utilities
diff --git a/arch/sh/kernel/idle.c b/arch/sh/kernel/idle.c
index ee226e20c20c..0c910163caa3 100644
--- a/arch/sh/kernel/idle.c
+++ b/arch/sh/kernel/idle.c
@@ -132,10 +132,6 @@ void __init select_idle_routine(void)
                pm_idle = poll_idle;
 }
-static void do_nothing(void *unused)
-{
-}
 void stop_this_cpu(void *unused)
 {
        local_irq_disable();
@@ -144,19 +140,3 @@ void stop_this_cpu(void *unused)
        for (;;)
                cpu_sleep();
 }
-/*
- * cpu_idle_wait - Used to ensure that all the CPUs discard old value of
- * pm_idle and update to new pm_idle value. Required while changing pm_idle
- * handler on SMP systems.
- *
- * Caller must have changed pm_idle to the new value before the call. Old
- * pm_idle value will not be used by any CPU after the return of this function.
- */
-void cpu_idle_wait(void)
-{
-        smp_mb();
-        /* kick all the CPUs so that they exit out of pm_idle */
-        smp_call_function(do_nothing, NULL, 1);
-}
-EXPORT_SYMBOL_GPL(cpu_idle_wait);
diff --git a/arch/sh/kernel/init_task.c b/arch/sh/kernel/init_task.c
deleted file mode 100644
index 11f2ea556a6b..000000000000
--- a/arch/sh/kernel/init_task.c
+++ /dev/null
@@ -1,30 +0,0 @@
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/sched.h>
-#include <linux/init_task.h>
-#include <linux/mqueue.h>
-#include <linux/fs.h>
-#include <asm/uaccess.h>
-#include <asm/pgtable.h>
-static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
-static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
-struct pt_regs fake_swapper_regs;
-/*
- * Initial thread structure.
- *
- * We need to make sure that this is 8192-byte aligned due to the
- * way process stacks are handled. This is done by having a special
- * "init_task" linker map entry..
- */
-union thread_union init_thread_union __init_task_data =
-        { INIT_THREAD_INFO(init_task) };
-/*
- * Initial task structure.
- *
- * All other task structs will be allocated on slabs in fork.c
- */
-struct task_struct init_task = INIT_TASK(init_task);
-EXPORT_SYMBOL(init_task);
diff --git a/arch/sh/kernel/process.c b/arch/sh/kernel/process.c
index 325f98b1736d..f2621abdf01d 100644
--- a/arch/sh/kernel/process.c
+++ b/arch/sh/kernel/process.c
@@ -29,52 +29,10 @@ void free_thread_xstate(struct task_struct *tsk)
        }
 }
-#if THREAD_SHIFT < PAGE_SHIFT
+void arch_release_task_struct(struct task_struct *tsk)
-static struct kmem_cache *thread_info_cache;
-struct thread_info *alloc_thread_info_node(struct task_struct *tsk, int node)
-{
-        struct thread_info *ti;
-#ifdef CONFIG_DEBUG_STACK_USAGE
-        gfp_t mask = GFP_KERNEL | __GFP_ZERO;
-#else
-        gfp_t mask = GFP_KERNEL;
-#endif
-        ti = kmem_cache_alloc_node(thread_info_cache, mask, node);
-        return ti;
-}
-void free_thread_info(struct thread_info *ti)
-{
-        free_thread_xstate(ti->task);
-        kmem_cache_free(thread_info_cache, ti);
-}
-void thread_info_cache_init(void)
-{
-        thread_info_cache = kmem_cache_create("thread_info", THREAD_SIZE,
-                                              THREAD_SIZE, SLAB_PANIC, NULL);
-}
-#else
-struct thread_info *alloc_thread_info_node(struct task_struct *tsk, int node)
-{
-#ifdef CONFIG_DEBUG_STACK_USAGE
-        gfp_t mask = GFP_KERNEL | __GFP_ZERO;
-#else
-        gfp_t mask = GFP_KERNEL;
-#endif
-        struct page *page = alloc_pages_node(node, mask, THREAD_SIZE_ORDER);
-        return page ? page_address(page) : NULL;
-}
-void free_thread_info(struct thread_info *ti)
 {
-        free_thread_xstate(ti->task);
+        free_thread_xstate(tsk);
-        free_pages((unsigned long)ti, THREAD_SIZE_ORDER);
 }
-#endif /* THREAD_SHIFT < PAGE_SHIFT */
 void arch_task_cache_init(void)
 {
diff --git a/arch/sh/kernel/ptrace_32.c b/arch/sh/kernel/ptrace_32.c
index 9698671444e6..81f999a672f6 100644
--- a/arch/sh/kernel/ptrace_32.c
+++ b/arch/sh/kernel/ptrace_32.c
@@ -503,7 +503,7 @@ asmlinkage long do_syscall_trace_enter(struct pt_regs *regs)
 {
        long ret = 0;
-        secure_computing(regs->regs[0]);
+        secure_computing_strict(regs->regs[0]);
        if (test_thread_flag(TIF_SYSCALL_TRACE) &&
            tracehook_report_syscall_entry(regs))
diff --git a/arch/sh/kernel/ptrace_64.c b/arch/sh/kernel/ptrace_64.c
index bc81e07dc098..af90339dadcd 100644
--- a/arch/sh/kernel/ptrace_64.c
+++ b/arch/sh/kernel/ptrace_64.c
@@ -522,7 +522,7 @@ asmlinkage long long do_syscall_trace_enter(struct pt_regs *regs)
 {
        long long ret = 0;
-        secure_computing(regs->regs[9]);
+        secure_computing_strict(regs->regs[9]);
        if (test_thread_flag(TIF_SYSCALL_TRACE) &&
            tracehook_report_syscall_entry(regs))
diff --git a/arch/sh/kernel/smp.c b/arch/sh/kernel/smp.c
index eaebdf6a5c77..b86e9ca79455 100644
--- a/arch/sh/kernel/smp.c
+++ b/arch/sh/kernel/smp.c
@@ -220,22 +220,10 @@ extern struct {
        void *thread_info;
 } stack_start;
-int __cpuinit __cpu_up(unsigned int cpu)
+int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *tsk)
 {
-        struct task_struct *tsk;
        unsigned long timeout;
-        tsk = cpu_data[cpu].idle;
-        if (!tsk) {
-                tsk = fork_idle(cpu);
-                if (IS_ERR(tsk)) {
-                        pr_err("Failed forking idle task for cpu %d\n", cpu);
-                        return PTR_ERR(tsk);
-                }
-                cpu_data[cpu].idle = tsk;
-        }
        per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
        /* Fill in data in head.S for secondary cpus */
diff --git a/arch/sh/mm/fault_32.c b/arch/sh/mm/fault_32.c
index 324eef93c900..e99b104d967a 100644
--- a/arch/sh/mm/fault_32.c
+++ b/arch/sh/mm/fault_32.c
@@ -86,7 +86,7 @@ static noinline int vmalloc_fault(unsigned long address)
        pte_t *pte_k;
        /* Make sure we are in vmalloc/module/P3 area: */
-        if (!(address >= VMALLOC_START && address < P3_ADDR_MAX))
+        if (!(address >= P3SEG && address < P3_ADDR_MAX))
                return -1;
        /*
diff --git a/arch/sparc/Kbuild b/arch/sparc/Kbuild
new file mode 100644
index 000000000000..5cd01161fd00
--- /dev/null
+++ b/arch/sparc/Kbuild
@@ -0,0 +1,8 @@
+#
+# core part of the sparc kernel
+#
+obj-y += kernel/
+obj-y += mm/
+obj-y += math-emu/
+obj-y += net/
diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig
index 6c0683d3fcba..1ea3fd954756 100644
--- a/arch/sparc/Kconfig
+++ b/arch/sparc/Kconfig
@@ -30,11 +30,14 @@ config SPARC
        select USE_GENERIC_SMP_HELPERS if SMP
        select GENERIC_PCI_IOMAP
        select HAVE_NMI_WATCHDOG if SPARC64
+        select HAVE_BPF_JIT
+        select GENERIC_SMP_IDLE_THREAD
 config SPARC32
        def_bool !64BIT
        select GENERIC_ATOMIC64
        select CLZ_TAB
+        select ARCH_THREAD_INFO_ALLOCATOR
 config SPARC64
        def_bool 64BIT
@@ -61,6 +64,7 @@ config SPARC64
        select IRQ_PREFLOW_FASTEOI
        select ARCH_HAVE_NMI_SAFE_CMPXCHG
        select HAVE_C_RECORDMCOUNT
+        select NO_BOOTMEM
 config ARCH_DEFCONFIG
        string
@@ -73,17 +77,12 @@ config BITS
        default 32 if SPARC32
        default 64 if SPARC64
-config ARCH_USES_GETTIMEOFFSET
-        bool
-        default y if SPARC32
 config GENERIC_CMOS_UPDATE
        bool
        default y
 config GENERIC_CLOCKEVENTS
-        bool
+        def_bool y
-        default y if SPARC64
 config IOMMU_HELPER
        bool
@@ -154,7 +153,7 @@ source "kernel/Kconfig.freezer"
 menu "Processor type and features"
 config SMP
-        bool "Symmetric multi-processing support (does not work on sun4/sun4c)"
+        bool "Symmetric multi-processing support"
        ---help---
          This enables support for systems with more than one CPU. If you have
          a system with only one CPU, say N. If you have a system with more
@@ -584,6 +583,9 @@ config SYSVIPC_COMPAT
        depends on COMPAT && SYSVIPC
        default y
+config KEYS_COMPAT
+        def_bool y if COMPAT && KEYS
 endmenu
 source "net/Kconfig"
diff --git a/arch/sparc/Makefile b/arch/sparc/Makefile
index eddcfb36aafb..541b8b075c7d 100644
--- a/arch/sparc/Makefile
+++ b/arch/sparc/Makefile
@@ -19,39 +19,27 @@ ifeq ($(CONFIG_SPARC32),y)
 # sparc32
 #
-#
-# Uncomment the first KBUILD_CFLAGS if you are doing kgdb source level
-# debugging of the kernel to get the proper debugging information.
-AS             := $(AS) -32
-LDFLAGS        := -m elf32_sparc
 CHECKFLAGS     += -D__sparc__
+LDFLAGS        := -m elf32_sparc
 export BITS    := 32
 UTS_MACHINE    := sparc
-#KBUILD_CFLAGS += -g -pipe -fcall-used-g5 -fcall-used-g7
+KBUILD_CFLAGS  += -m32 -mcpu=v8 -pipe -mno-fpu -fcall-used-g5 -fcall-used-g7
-KBUILD_CFLAGS += -m32 -pipe -mno-fpu -fcall-used-g5 -fcall-used-g7
+KBUILD_AFLAGS  += -m32 -Wa,-Av8
-KBUILD_AFLAGS += -m32 -Wa,-Av8
-#LDFLAGS_vmlinux = -N -Ttext 0xf0004000
-#  Since 2.5.40, the first stage is left not btfix-ed.
-#  Actual linking is done with "make image".
-LDFLAGS_vmlinux = -r
 else
 #####
 # sparc64
 #
-CHECKFLAGS      += -D__sparc__ -D__sparc_v9__ -D__arch64__ -m64
+CHECKFLAGS    += -D__sparc__ -D__sparc_v9__ -D__arch64__ -m64
+LDFLAGS       := -m elf64_sparc
+export BITS   := 64
+UTS_MACHINE   := sparc64
-LDFLAGS              := -m elf64_sparc
+KBUILD_CFLAGS += -m64 -pipe -mno-fpu -mcpu=ultrasparc -mcmodel=medlow
-export BITS          := 64
+KBUILD_CFLAGS += -ffixed-g4 -ffixed-g5 -fcall-used-g7 -Wno-sign-compare
-UTS_MACHINE          := sparc64
+KBUILD_CFLAGS += -Wa,--undeclared-regs
-KBUILD_CFLAGS += -m64 -pipe -mno-fpu -mcpu=ultrasparc -mcmodel=medlow   \
-                 -ffixed-g4 -ffixed-g5 -fcall-used-g7 -Wno-sign-compare \
-                 -Wa,--undeclared-regs
 KBUILD_CFLAGS += $(call cc-option,-mtune=ultrasparc3)
 KBUILD_AFLAGS += -m64 -mcpu=ultrasparc -Wa,--undeclared-regs
@@ -62,27 +50,15 @@ endif
 endif
 head-y                 := arch/sparc/kernel/head_$(BITS).o
-head-y                 += arch/sparc/kernel/init_task.o
-core-y                 += arch/sparc/kernel/
+# See arch/sparc/Kbuild for the core part of the kernel
-core-y                 += arch/sparc/mm/ arch/sparc/math-emu/
+core-y                 += arch/sparc/
 libs-y                 += arch/sparc/prom/
 libs-y                 += arch/sparc/lib/
 drivers-$(CONFIG_OPROFILE)      += arch/sparc/oprofile/
-# Export what is needed by arch/sparc/boot/Makefile
-export VMLINUX_INIT VMLINUX_MAIN
-VMLINUX_INIT := $(head-y) $(init-y)
-VMLINUX_MAIN := $(core-y) kernel/ mm/ fs/ ipc/ security/ crypto/ block/
-VMLINUX_MAIN += $(patsubst %/, %/lib.a, $(libs-y)) $(libs-y)
-VMLINUX_MAIN += $(drivers-y) $(net-y)
-ifdef CONFIG_KALLSYMS
-export kallsyms.o := .tmp_kallsyms2.o
-endif
 boot := arch/sparc/boot
 # Default target
diff --git a/arch/sparc/boot/Makefile b/arch/sparc/boot/Makefile
index d56d199c1aa8..6e63afb128d9 100644
--- a/arch/sparc/boot/Makefile
+++ b/arch/sparc/boot/Makefile
@@ -6,8 +6,8 @@
 ROOT_IMG        := /usr/src/root.img
 ELFTOAOUT       := elftoaout
-hostprogs-y     := piggyback btfixupprep
+hostprogs-y     := piggyback
-targets         := tftpboot.img btfix.o btfix.S image zImage vmlinux.aout
+targets         := tftpboot.img image zImage vmlinux.aout
 clean-files     := System.map
 quiet_cmd_elftoaout     = ELFTOAOUT $@
@@ -17,58 +17,9 @@ quiet_cmd_piggy		= PIGGY   $@
 quiet_cmd_strip         = STRIP   $@
      cmd_strip         = $(STRIP) -R .comment -R .note -K sun4u_init -K _end -K _start $< -o $@
-ifeq ($(CONFIG_SPARC32),y)
-quiet_cmd_btfix         = BTFIX   $@
-      cmd_btfix         = $(OBJDUMP) -x vmlinux | $(obj)/btfixupprep > $@
-quiet_cmd_sysmap        = SYSMAP  $(obj)/System.map
-      cmd_sysmap        = $(CONFIG_SHELL) $(srctree)/scripts/mksysmap
-quiet_cmd_image = LD      $@
-      cmd_image = $(LD) $(LDFLAGS) $(EXTRA_LDFLAGS) $(LDFLAGS_$(@F)) -o $@
-define rule_image
-        $(if $($(quiet)cmd_image),               \
-          echo '  $($(quiet)cmd_image)' &&)      \
-          $(cmd_image);                          \
-        $(if $($(quiet)cmd_sysmap),              \
-          echo '  $($(quiet)cmd_sysmap)' &&)  \
-        $(cmd_sysmap) $@ $(obj)/System.map;      \
-        if [ $$? -ne 0 ]; then                   \
-                rm -f $@;                        \
-                /bin/false;                      \
-        fi;                                      \
-        echo 'cmd_$@ := $(cmd_image)' > $(@D)/.$(@F).cmd
-endef
-BTOBJS := $(patsubst %/, %/built-in.o, $(VMLINUX_INIT))
-BTLIBS := $(patsubst %/, %/built-in.o, $(VMLINUX_MAIN))
-LDFLAGS_image := -T arch/sparc/kernel/vmlinux.lds $(BTOBJS) \
-                  --start-group $(BTLIBS) --end-group \
-                  $(kallsyms.o) $(obj)/btfix.o
-# Link the final image including btfixup'ed symbols.
-# This is a replacement for the link done in the top-level Makefile.
-# Note: No dependency on the prerequisite files since that would require
-# make to try check if they are updated - and due to changes
-# in gcc options (path for example) this would result in
-# these files being recompiled for each build.
-$(obj)/image: $(obj)/btfix.o FORCE
-        $(call if_changed_rule,image)
-$(obj)/zImage: $(obj)/image
-        $(call if_changed,strip)
-        @echo '  kernel: $@ is ready'
-$(obj)/btfix.S: $(obj)/btfixupprep vmlinux FORCE
-        $(call if_changed,btfix)
-endif
 ifeq ($(CONFIG_SPARC64),y)
 # Actual linking
-$(obj)/image: vmlinux FORCE
-        $(call if_changed,strip)
-        @echo '  kernel: $@ is ready'
 $(obj)/zImage: $(obj)/image
        $(call if_changed,gzip)
@@ -79,6 +30,10 @@ $(obj)/vmlinux.aout: vmlinux FORCE
        @echo '  kernel: $@ is ready'
 else
+$(obj)/zImage: $(obj)/image
+        $(call if_changed,strip)
+        @echo '  kernel: $@ is ready'
 # The following lines make a readable image for U-Boot.
 #  uImage   - Binary file read by U-boot
 #  uImage.o - object file of uImage for loading with a
@@ -107,6 +62,10 @@ $(obj)/uImage: $(obj)/image.gz
 endif
+$(obj)/image: vmlinux FORCE
+        $(call if_changed,strip)
+        @echo '  kernel: $@ is ready'
 $(obj)/tftpboot.img: $(obj)/image $(obj)/piggyback System.map $(ROOT_IMG) FORCE
        $(call if_changed,elftoaout)
        $(call if_changed,piggy)
diff --git a/arch/sparc/boot/btfixupprep.c b/arch/sparc/boot/btfixupprep.c
deleted file mode 100644
index da031159e2b7..000000000000
--- a/arch/sparc/boot/btfixupprep.c
+++ /dev/null
@@ -1,386 +0,0 @@
-/*
-   Simple utility to prepare vmlinux image for sparc.
-   Resolves all BTFIXUP uses and settings and creates
-   a special .s object to link to the image.
-   
-   Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
-   
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2 of the License, or
-   (at your option) any later version.
-   
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-   You should have received a copy of the GNU General Public License
-   along with this program; if not, write to the Free Software
-   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.  */
-   
-#include <stdio.h>
-#include <string.h>
-#include <ctype.h>
-#include <errno.h>
-#include <unistd.h>
-#include <stdlib.h>
-#include <malloc.h>
-#define MAXSYMS 1024
-static char *symtab = "SYMBOL TABLE:";
-static char *relrec = "RELOCATION RECORDS FOR [";
-static int rellen;
-static int symlen;
-int mode;
-struct _btfixup;
-typedef struct _btfixuprel {
-        char *sect;
-        unsigned long offset;
-        struct _btfixup *f;
-        int frel;
-        struct _btfixuprel *next;
-} btfixuprel;
-typedef struct _btfixup {
-        int type;
-        int setinitval;
-        unsigned int initval;
-        char *initvalstr;
-        char *name;
-        btfixuprel *rel;
-} btfixup;
-btfixup array[MAXSYMS];
-int last = 0;
-char buffer[1024];
-unsigned long lastfoffset = -1;
-unsigned long lastfrelno;
-btfixup *lastf;
-static void fatal(void) __attribute__((noreturn));
-static void fatal(void)
-{
-        fprintf(stderr, "Malformed output from objdump\n%s\n", buffer);
-        exit(1);
-}
-static btfixup *find(int type, char *name)
-{
-        int i;
-        for (i = 0; i < last; i++) {
-                if (array[i].type == type && !strcmp(array[i].name, name))
-                        return array + i;
-        }
-        array[last].type = type;
-        array[last].name = strdup(name);
-        array[last].setinitval = 0;
-        if (!array[last].name) fatal();
-        array[last].rel = NULL;
-        last++;
-        if (last >= MAXSYMS) {
-                fprintf(stderr, "Ugh. Something strange. More than %d different BTFIXUP symbols\n", MAXSYMS);
-                exit(1);
-        }
-        return array + last - 1;
-}
-static void set_mode (char *buffer)
-{
-        for (mode = 0;; mode++)
-                if (buffer[mode] < '0' || buffer[mode] > '9')
-                        break;
-        if (mode != 8 && mode != 16)
-                fatal();
-}
-int main(int argc,char **argv)
-{
-        char *p, *q;
-        char *sect;
-        int i, j, k;
-        unsigned int initval;
-        int shift;
-        btfixup *f;
-        btfixuprel *r, **rr;
-        unsigned long offset;
-        char *initvalstr;
-        symlen = strlen(symtab);
-        while (fgets (buffer, 1024, stdin) != NULL)
-                if (!strncmp (buffer, symtab, symlen))
-                        goto main0;
-        fatal();
-main0:
-        rellen = strlen(relrec);
-        while (fgets (buffer, 1024, stdin) != NULL)
-                if (!strncmp (buffer, relrec, rellen))
-                        goto main1;
-        fatal();
-main1:
-        sect = malloc(strlen (buffer + rellen) + 1);
-        if (!sect) fatal();
-        strcpy (sect, buffer + rellen);
-        p = strchr (sect, ']');
-        if (!p) fatal();
-        *p = 0;
-        if (fgets (buffer, 1024, stdin) == NULL)
-                fatal();
-        while (fgets (buffer, 1024, stdin) != NULL) {
-                int nbase;
-                if (!strncmp (buffer, relrec, rellen))
-                        goto main1;
-                if (mode == 0)
-                        set_mode (buffer);
-                p = strchr (buffer, '\n');
-                if (p) *p = 0;
-                if (strlen (buffer) < 22+mode)
-                        continue;
-                if (strncmp (buffer + mode, " R_SPARC_", 9))
-                        continue;
-                nbase = 27 - 8 + mode;
-                if (buffer[nbase] != '_' || buffer[nbase+1] != '_' || buffer[nbase+2] != '_')
-                        continue;
-                switch (buffer[nbase+3]) {
-                        case 'f':       /* CALL */
-                        case 'b':       /* BLACKBOX */
-                        case 's':       /* SIMM13 */
-                        case 'a':       /* HALF */
-                        case 'h':       /* SETHI */
-                        case 'i':       /* INT */
-                                break;
-                        default:
-                                continue;
-                }
-                p = strchr (buffer + nbase+5, '+');
-                if (p) *p = 0;
-                shift = nbase + 5;
-                if (buffer[nbase+4] == 's' && buffer[nbase+5] == '_') {
-                        shift = nbase + 6;
-                        if (strcmp (sect, ".init.text")) {
-                                fprintf(stderr,
-                                    "Wrong use of '%s' BTFIXUPSET in '%s' section.\n"
-                                    "BTFIXUPSET_CALL can be used only in"
-                                    " __init sections\n",
-                                    buffer + shift, sect);
-                                exit(1);
-                        }
-                } else if (buffer[nbase+4] != '_')
-                        continue;
-                if (!strcmp (sect, ".text.exit"))
-                        continue;
-                if (strcmp (sect, ".text") &&
-                    strcmp (sect, ".init.text") &&
-                    strcmp (sect, ".fixup") &&
-                    (strcmp (sect, "__ksymtab") || buffer[nbase+3] != 'f')) {
-                        if (buffer[nbase+3] == 'f')
-                                fprintf(stderr,
-                                    "Wrong use of '%s' in '%s' section.\n"
-                                    " It can be used only in .text, .init.text,"
-                                    " .fixup and __ksymtab\n",
-                                    buffer + shift, sect);
-                        else
-                                fprintf(stderr,
-                                    "Wrong use of '%s' in '%s' section.\n"
-                                    " It can be only used in .text, .init.text,"
-                                    " and .fixup\n", buffer + shift, sect);
-                        exit(1);
-                }
-                p = strstr (buffer + shift, "__btset_");
-                if (p && buffer[nbase+4] == 's') {
-                        fprintf(stderr, "__btset_ in BTFIXUP name can only be used when defining the variable, not for setting\n%s\n", buffer);
-                        exit(1);
-                }
-                initval = 0;
-                initvalstr = NULL;
-                if (p) {
-                        if (p[8] != '0' || p[9] != 'x') {
-                                fprintf(stderr, "Pre-initialized values can be only initialized with hexadecimal constants starting 0x\n%s\n", buffer);
-                                exit(1);
-                        }
-                        initval = strtoul(p + 10, &q, 16);
-                        if (*q || !initval) {
-                                fprintf(stderr, "Pre-initialized values can be only in the form name__btset_0xXXXXXXXX where X are hex digits.\nThey cannot be name__btset_0x00000000 though. Use BTFIXUPDEF_XX instead of BTFIXUPDEF_XX_INIT then.\n%s\n", buffer);
-                                exit(1);
-                        }
-                        initvalstr = p + 10;
-                        *p = 0;
-                }
-                f = find(buffer[nbase+3], buffer + shift);
-                if (buffer[nbase+4] == 's')
-                        continue;
-                switch (buffer[nbase+3]) {
-                case 'f':
-                        if (initval) {
-                                fprintf(stderr, "Cannot use pre-initialized fixups for calls\n%s\n", buffer);
-                                exit(1);
-                        }
-                        if (!strcmp (sect, "__ksymtab")) {
-                                if (strncmp (buffer + mode+9, "32        ", 10)) {
-                                        fprintf(stderr, "BTFIXUP_CALL in EXPORT_SYMBOL results in relocation other than R_SPARC_32\n\%s\n", buffer);
-                                        exit(1);
-                                }
-                        } else if (strncmp (buffer + mode+9, "WDISP30   ", 10) &&
-                                   strncmp (buffer + mode+9, "HI22      ", 10) &&
-                                   strncmp (buffer + mode+9, "LO10      ", 10)) {
-                                fprintf(stderr, "BTFIXUP_CALL results in relocation other than R_SPARC_WDISP30, R_SPARC_HI22 or R_SPARC_LO10\n%s\n", buffer);
-                                exit(1);
-                        }
-                        break;
-                case 'b':
-                        if (initval) {
-                                fprintf(stderr, "Cannot use pre-initialized fixups for blackboxes\n%s\n", buffer);
-                                exit(1);
-                        }
-                        if (strncmp (buffer + mode+9, "HI22      ", 10)) {
-                                fprintf(stderr, "BTFIXUP_BLACKBOX results in relocation other than R_SPARC_HI22\n%s\n", buffer);
-                                exit(1);
-                        }
-                        break;
-                case 's':
-                        if (initval + 0x1000 >= 0x2000) {
-                                fprintf(stderr, "Wrong initializer for SIMM13. Has to be from $fffff000 to $00000fff\n%s\n", buffer);
-                                exit(1);
-                        }
-                        if (strncmp (buffer + mode+9, "13        ", 10)) {
-                                fprintf(stderr, "BTFIXUP_SIMM13 results in relocation other than R_SPARC_13\n%s\n", buffer);
-                                exit(1);
-                        }
-                        break;
-                case 'a':
-                        if (initval + 0x1000 >= 0x2000 && (initval & 0x3ff)) {
-                                fprintf(stderr, "Wrong initializer for HALF.\n%s\n", buffer);
-                                exit(1);
-                        }
-                        if (strncmp (buffer + mode+9, "13        ", 10)) {
-                                fprintf(stderr, "BTFIXUP_HALF results in relocation other than R_SPARC_13\n%s\n", buffer);
-                                exit(1);
-                        }
-                        break;
-                case 'h':
-                        if (initval & 0x3ff) {
-                                fprintf(stderr, "Wrong initializer for SETHI. Cannot have set low 10 bits\n%s\n", buffer);
-                                exit(1);
-                        }
-                        if (strncmp (buffer + mode+9, "HI22      ", 10)) {
-                                fprintf(stderr, "BTFIXUP_SETHI results in relocation other than R_SPARC_HI22\n%s\n", buffer);
-                                exit(1);
-                        }
-                        break;
-                case 'i':
-                        if (initval) {
-                                fprintf(stderr, "Cannot use pre-initialized fixups for INT\n%s\n", buffer);
-                                exit(1);
-                        }
-                        if (strncmp (buffer + mode+9, "HI22      ", 10) && strncmp (buffer + mode+9, "LO10      ", 10)) {
-                                fprintf(stderr, "BTFIXUP_INT results in relocation other than R_SPARC_HI22 and R_SPARC_LO10\n%s\n", buffer);
-                                exit(1);
-                        }
-                        break;
-                }
-                if (!f->setinitval) {
-                        f->initval = initval;
-                        if (initvalstr) {
-                                f->initvalstr = strdup(initvalstr);
-                                if (!f->initvalstr) fatal();
-                        }
-                        f->setinitval = 1;
-                } else if (f->initval != initval) {
-                        fprintf(stderr, "Btfixup %s previously used with initializer %s which doesn't match with current initializer\n%s\n",
-                                        f->name, f->initvalstr ? : "0x00000000", buffer);
-                        exit(1);
-                } else if (initval && strcmp(f->initvalstr, initvalstr)) {
-                        fprintf(stderr, "Btfixup %s previously used with initializer %s which doesn't match with current initializer.\n"
-                                        "Initializers have to match literally as well.\n%s\n",
-                                        f->name, f->initvalstr, buffer);
-                        exit(1);
-                }
-                offset = strtoul(buffer, &q, 16);
-                if (q != buffer + mode || (!offset && (mode == 8 ? strncmp (buffer, "00000000 ", 9) : strncmp (buffer, "0000000000000000 ", 17)))) {
-                        fprintf(stderr, "Malformed relocation address in\n%s\n", buffer);
-                        exit(1);
-                }
-                for (k = 0, r = f->rel, rr = &f->rel; r; rr = &r->next, r = r->next, k++)
-                        if (r->offset == offset && !strcmp(r->sect, sect)) {
-                                fprintf(stderr, "Ugh. One address has two relocation records\n");
-                                exit(1);
-                        }
-                *rr = malloc(sizeof(btfixuprel));
-                if (!*rr) fatal();
-                (*rr)->offset = offset;
-                (*rr)->f = NULL;
-                if (buffer[nbase+3] == 'f') {
-                        lastf = f;
-                        lastfoffset = offset;
-                        lastfrelno = k;
-                } else if (lastfoffset + 4 == offset) {
-                        (*rr)->f = lastf;
-                        (*rr)->frel = lastfrelno;
-                }
-                (*rr)->sect = sect;
-                (*rr)->next = NULL;
-        }
-        printf("! Generated by btfixupprep. Do not edit.\n\n");
-        printf("\t.section\t\".data..init\",#alloc,#write\n\t.align\t4\n\n");
-        printf("\t.global\t___btfixup_start\n___btfixup_start:\n\n");
-        for (i = 0; i < last; i++) {
-                f = array + i;
-                printf("\t.global\t___%cs_%s\n", f->type, f->name);
-                if (f->type == 'f')
-                        printf("___%cs_%s:\n\t.word 0x%08x,0,0,", f->type, f->name, f->type << 24);
-                else
-                        printf("___%cs_%s:\n\t.word 0x%08x,0,", f->type, f->name, f->type << 24);
-                for (j = 0, r = f->rel; r != NULL; j++, r = r->next);
-                if (j)
-                        printf("%d\n\t.word\t", j * 2);
-                else
-                        printf("0\n");
-                for (r = f->rel, j--; r != NULL; j--, r = r->next) {
-                        if (!strcmp (r->sect, ".text"))
-                                printf ("_stext+0x%08lx", r->offset);
-                        else if (!strcmp (r->sect, ".init.text"))
-                                printf ("__init_begin+0x%08lx", r->offset);
-                        else if (!strcmp (r->sect, "__ksymtab"))
-                                printf ("__start___ksymtab+0x%08lx", r->offset);
-                        else if (!strcmp (r->sect, ".fixup"))
-                                printf ("__start___fixup+0x%08lx", r->offset);
-                        else
-                                fatal();
-                        if (f->type == 'f' || !r->f)
-                                printf (",0");
-                        else
-                                printf (",___fs_%s+0x%08x", r->f->name, (4 + r->frel*2)*4 + 4);
-                        if (j) printf (",");
-                        else printf ("\n");
-                }
-                printf("\n");
-        }
-        printf("\n\t.global\t___btfixup_end\n___btfixup_end:\n");
-        printf("\n\n! Define undefined references\n\n");
-        for (i = 0; i < last; i++) {
-                f = array + i;
-                if (f->type == 'f') {
-                        printf("\t.global\t___f_%s\n", f->name);
-                        printf("___f_%s:\n", f->name);
-                }
-        }
-        printf("\tretl\n\t nop\n\n");
-        for (i = 0; i < last; i++) {
-                f = array + i;
-                if (f->type != 'f') {
-                        if (!f->initval) {
-                                printf("\t.global\t___%c_%s\n", f->type, f->name);
-                                printf("___%c_%s = 0\n", f->type, f->name);
-                        } else {
-                                printf("\t.global\t___%c_%s__btset_0x%s\n", f->type, f->name, f->initvalstr);
-                                printf("___%c_%s__btset_0x%s = 0x%08x\n", f->type, f->name, f->initvalstr, f->initval);
-                        }
-                }
-        }
-        printf("\n\n");
-        exit(0);
-}
diff --git a/arch/sparc/configs/sparc64_defconfig b/arch/sparc/configs/sparc64_defconfig
index 3c1e85807403..9d8521b8c854 100644
--- a/arch/sparc/configs/sparc64_defconfig
+++ b/arch/sparc/configs/sparc64_defconfig
@@ -5,7 +5,7 @@ CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
 CONFIG_LOG_BUF_SHIFT=18
 CONFIG_BLK_DEV_INITRD=y
-CONFIG_PERF_COUNTERS=y
+CONFIG_PERF_EVENTS=y
 # CONFIG_COMPAT_BRK is not set
 CONFIG_SLAB=y
 CONFIG_PROFILING=y
diff --git a/arch/sparc/include/asm/asi.h b/arch/sparc/include/asm/asi.h
index b2e3db63a64b..cbb93e5141de 100644
--- a/arch/sparc/include/asm/asi.h
+++ b/arch/sparc/include/asm/asi.h
@@ -112,6 +112,20 @@
 #define ASI_M_ACTION       0x4c   /* Breakpoint Action Register (GNU/Viking) */
+/* LEON ASI */
+#define ASI_LEON_NOCACHE        0x01
+#define ASI_LEON_DCACHE_MISS    0x01
+#define ASI_LEON_CACHEREGS      0x02
+#define ASI_LEON_IFLUSH         0x10
+#define ASI_LEON_DFLUSH         0x11
+#define ASI_LEON_MMUFLUSH       0x18
+#define ASI_LEON_MMUREGS        0x19
+#define ASI_LEON_BYPASS         0x1c
+#define ASI_LEON_FLUSH_PAGE     0x10
 /* V9 Architecture mandary ASIs. */
 #define ASI_N                   0x04 /* Nucleus                         */
 #define ASI_NL                  0x0c /* Nucleus, little endian          */
diff --git a/arch/sparc/include/asm/asmmacro.h b/arch/sparc/include/asm/asmmacro.h
index a995bf8aba3f..02a172fb193a 100644
--- a/arch/sparc/include/asm/asmmacro.h
+++ b/arch/sparc/include/asm/asmmacro.h
@@ -6,17 +6,6 @@
 #ifndef _SPARC_ASMMACRO_H
 #define _SPARC_ASMMACRO_H
-#include <asm/btfixup.h>
-#include <asm/asi.h>
-#define GET_PROCESSOR4M_ID(reg) \
-        rd      %tbr, %reg; \
-        srl     %reg, 12, %reg; \
-        and     %reg, 3, %reg;
-#define GET_PROCESSOR4D_ID(reg) \
-        lda     [%g0] ASI_M_VIKING_TMP1, %reg;
 /* All trap entry points _must_ begin with this macro or else you
 * lose.  It makes sure the kernel has a proper window so that
 * c-code can be called.
@@ -31,10 +20,4 @@
 /* All traps low-level code here must end with this macro. */
 #define RESTORE_ALL b ret_trap_entry; clr %l6;
-/* sun4 probably wants half word accesses to ASI_SEGMAP, while sun4c+
-   likes byte accesses. These are to avoid ifdef mania. */
-#define lduXa   lduba
-#define stXa    stba
 #endif /* !(_SPARC_ASMMACRO_H) */
diff --git a/arch/sparc/include/asm/btfixup.h b/arch/sparc/include/asm/btfixup.h
deleted file mode 100644
index 797722cf69f2..000000000000
--- a/arch/sparc/include/asm/btfixup.h
+++ /dev/null
@@ -1,208 +0,0 @@
-/*
- *  asm/btfixup.h:    Macros for boot time linking.
- *
- *  Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
- */
- 
-#ifndef _SPARC_BTFIXUP_H
-#define _SPARC_BTFIXUP_H
-#include <linux/init.h>
-#ifndef __ASSEMBLY__
-#ifdef MODULE
-extern unsigned int ___illegal_use_of_BTFIXUP_SIMM13_in_module(void);
-extern unsigned int ___illegal_use_of_BTFIXUP_SETHI_in_module(void);
-extern unsigned int ___illegal_use_of_BTFIXUP_HALF_in_module(void);
-extern unsigned int ___illegal_use_of_BTFIXUP_INT_in_module(void);
-#define BTFIXUP_SIMM13(__name) ___illegal_use_of_BTFIXUP_SIMM13_in_module()
-#define BTFIXUP_HALF(__name) ___illegal_use_of_BTFIXUP_HALF_in_module()
-#define BTFIXUP_SETHI(__name) ___illegal_use_of_BTFIXUP_SETHI_in_module()
-#define BTFIXUP_INT(__name) ___illegal_use_of_BTFIXUP_INT_in_module()
-#define BTFIXUP_BLACKBOX(__name) ___illegal_use_of_BTFIXUP_BLACKBOX_in_module
-#else
-#define BTFIXUP_SIMM13(__name) ___sf_##__name()
-#define BTFIXUP_HALF(__name) ___af_##__name()
-#define BTFIXUP_SETHI(__name) ___hf_##__name()
-#define BTFIXUP_INT(__name) ((unsigned int)&___i_##__name)
-/* This must be written in assembly and present in a sethi */
-#define BTFIXUP_BLACKBOX(__name) ___b_##__name
-#endif /* MODULE */
-/* Fixup call xx */
-#define BTFIXUPDEF_CALL(__type, __name, __args...)                                      \
-        extern __type ___f_##__name(__args);                                            \
-        extern unsigned ___fs_##__name[3];
-#define BTFIXUPDEF_CALL_CONST(__type, __name, __args...)                                \
-        extern __type ___f_##__name(__args) __attribute_const__;                        \
-        extern unsigned ___fs_##__name[3];
-#define BTFIXUP_CALL(__name) ___f_##__name
-#define BTFIXUPDEF_BLACKBOX(__name)                                                     \
-        extern unsigned ___bs_##__name[2];
-/* Put bottom 13bits into some register variable */
-#define BTFIXUPDEF_SIMM13(__name)                                                       \
-        static inline unsigned int ___sf_##__name(void) __attribute_const__;            \
-        extern unsigned ___ss_##__name[2];                                              \
-        static inline unsigned int ___sf_##__name(void) {                               \
-                unsigned int ret;                                                       \
-                __asm__ ("or %%g0, ___s_" #__name ", %0" : "=r"(ret));                  \
-                return ret;                                                             \
-        }
-#define BTFIXUPDEF_SIMM13_INIT(__name,__val)                                            \
-        static inline unsigned int ___sf_##__name(void) __attribute_const__;            \
-        extern unsigned ___ss_##__name[2];                                              \
-        static inline unsigned int ___sf_##__name(void) {                               \
-                unsigned int ret;                                                       \
-                __asm__ ("or %%g0, ___s_" #__name "__btset_" #__val ", %0" : "=r"(ret));\
-                return ret;                                                             \
-        }
-/* Put either bottom 13 bits, or upper 22 bits into some register variable
- * (depending on the value, this will lead into sethi FIX, reg; or
- * mov FIX, reg; )
- */
-#define BTFIXUPDEF_HALF(__name)                                                         \
-        static inline unsigned int ___af_##__name(void) __attribute_const__;            \
-        extern unsigned ___as_##__name[2];                                              \
-        static inline unsigned int ___af_##__name(void) {                               \
-                unsigned int ret;                                                       \
-                __asm__ ("or %%g0, ___a_" #__name ", %0" : "=r"(ret));                  \
-                return ret;                                                             \
-        }
-#define BTFIXUPDEF_HALF_INIT(__name,__val)                                              \
-        static inline unsigned int ___af_##__name(void) __attribute_const__;            \
-        extern unsigned ___as_##__name[2];                                              \
-        static inline unsigned int ___af_##__name(void) {                               \
-                unsigned int ret;                                                       \
-                __asm__ ("or %%g0, ___a_" #__name "__btset_" #__val ", %0" : "=r"(ret));\
-                return ret;                                                             \
-        }
-/* Put upper 22 bits into some register variable */
-#define BTFIXUPDEF_SETHI(__name)                                                        \
-        static inline unsigned int ___hf_##__name(void) __attribute_const__;            \
-        extern unsigned ___hs_##__name[2];                                              \
-        static inline unsigned int ___hf_##__name(void) {                               \
-                unsigned int ret;                                                       \
-                __asm__ ("sethi %%hi(___h_" #__name "), %0" : "=r"(ret));               \
-                return ret;                                                             \
-        }
-#define BTFIXUPDEF_SETHI_INIT(__name,__val)                                             \
-        static inline unsigned int ___hf_##__name(void) __attribute_const__;            \
-        extern unsigned ___hs_##__name[2];                                              \
-        static inline unsigned int ___hf_##__name(void) {                               \
-                unsigned int ret;                                                       \
-                __asm__ ("sethi %%hi(___h_" #__name "__btset_" #__val "), %0" :         \
-                         "=r"(ret));                                                    \
-                return ret;                                                             \
-        }
-/* Put a full 32bit integer into some register variable */
-#define BTFIXUPDEF_INT(__name)                                                          \
-        extern unsigned char ___i_##__name;                                             \
-        extern unsigned ___is_##__name[2];
-#define BTFIXUPCALL_NORM        0x00000000                      /* Always call */
-#define BTFIXUPCALL_NOP         0x01000000                      /* Possibly optimize to nop */
-#define BTFIXUPCALL_RETINT(i)   (0x90102000|((i) & 0x1fff))     /* Possibly optimize to mov i, %o0 */
-#define BTFIXUPCALL_ORINT(i)    (0x90122000|((i) & 0x1fff))     /* Possibly optimize to or %o0, i, %o0 */
-#define BTFIXUPCALL_RETO0       0x01000000                      /* Return first parameter, actually a nop */
-#define BTFIXUPCALL_ANDNINT(i)  (0x902a2000|((i) & 0x1fff))     /* Possibly optimize to andn %o0, i, %o0 */
-#define BTFIXUPCALL_SWAPO0O1    0xd27a0000                      /* Possibly optimize to swap [%o0],%o1 */
-#define BTFIXUPCALL_SWAPO0G0    0xc07a0000                      /* Possibly optimize to swap [%o0],%g0 */
-#define BTFIXUPCALL_SWAPG1G2    0xc4784000                      /* Possibly optimize to swap [%g1],%g2 */
-#define BTFIXUPCALL_STG0O0      0xc0220000                      /* Possibly optimize to st %g0,[%o0] */
-#define BTFIXUPCALL_STO1O0      0xd2220000                      /* Possibly optimize to st %o1,[%o0] */
-#define BTFIXUPSET_CALL(__name, __addr, __insn)                                         \
-        do {                                                                            \
-                ___fs_##__name[0] |= 1;                                                 \
-                ___fs_##__name[1] = (unsigned long)__addr;                              \
-                ___fs_##__name[2] = __insn;                                             \
-        } while (0)
-        
-#define BTFIXUPSET_BLACKBOX(__name, __func)                                             \
-        do {                                                                            \
-                ___bs_##__name[0] |= 1;                                                 \
-                ___bs_##__name[1] = (unsigned long)__func;                              \
-        } while (0)
-        
-#define BTFIXUPCOPY_CALL(__name, __from)                                                \
-        do {                                                                            \
-                ___fs_##__name[0] |= 1;                                                 \
-                ___fs_##__name[1] = ___fs_##__from[1];                                  \
-                ___fs_##__name[2] = ___fs_##__from[2];                                  \
-        } while (0)
-                
-#define BTFIXUPSET_SIMM13(__name, __val)                                                \
-        do {                                                                            \
-                ___ss_##__name[0] |= 1;                                                 \
-                ___ss_##__name[1] = (unsigned)__val;                                    \
-        } while (0)
-        
-#define BTFIXUPCOPY_SIMM13(__name, __from)                                              \
-        do {                                                                            \
-                ___ss_##__name[0] |= 1;                                                 \
-                ___ss_##__name[1] = ___ss_##__from[1];                                  \
-        } while (0)
-                
-#define BTFIXUPSET_HALF(__name, __val)                                                  \
-        do {                                                                            \
-                ___as_##__name[0] |= 1;                                                 \
-                ___as_##__name[1] = (unsigned)__val;                                    \
-        } while (0)
-        
-#define BTFIXUPCOPY_HALF(__name, __from)                                                \
-        do {                                                                            \
-                ___as_##__name[0] |= 1;                                                 \
-                ___as_##__name[1] = ___as_##__from[1];                                  \
-        } while (0)
-                
-#define BTFIXUPSET_SETHI(__name, __val)                                                 \
-        do {                                                                            \
-                ___hs_##__name[0] |= 1;                                                 \
-                ___hs_##__name[1] = (unsigned)__val;                                    \
-        } while (0)
-        
-#define BTFIXUPCOPY_SETHI(__name, __from)                                               \
-        do {                                                                            \
-                ___hs_##__name[0] |= 1;                                                 \
-                ___hs_##__name[1] = ___hs_##__from[1];                                  \
-        } while (0)
-                
-#define BTFIXUPSET_INT(__name, __val)                                                   \
-        do {                                                                            \
-                ___is_##__name[0] |= 1;                                                 \
-                ___is_##__name[1] = (unsigned)__val;                                    \
-        } while (0)
-        
-#define BTFIXUPCOPY_INT(__name, __from)                                                 \
-        do {                                                                            \
-                ___is_##__name[0] |= 1;                                                 \
-                ___is_##__name[1] = ___is_##__from[1];                                  \
-        } while (0)
-        
-#define BTFIXUPVAL_CALL(__name)                                                         \
-        ((unsigned long)___fs_##__name[1])
-        
-extern void btfixup(void);
-#else /* __ASSEMBLY__ */
-#define BTFIXUP_SETHI(__name)                   %hi(___h_ ## __name)
-#define BTFIXUP_SETHI_INIT(__name,__val)        %hi(___h_ ## __name ## __btset_ ## __val)
-#endif /* __ASSEMBLY__ */
-        
-#endif /* !(_SPARC_BTFIXUP_H) */
diff --git a/arch/sparc/include/asm/cache.h b/arch/sparc/include/asm/cache.h
index 69358b590c91..5bb6991b4857 100644
--- a/arch/sparc/include/asm/cache.h
+++ b/arch/sparc/include/asm/cache.h
@@ -22,118 +22,4 @@
 #define __read_mostly __attribute__((__section__(".data..read_mostly")))
-#ifdef CONFIG_SPARC32
-#include <asm/asi.h>
-/* Direct access to the instruction cache is provided through and
- * alternate address space.  The IDC bit must be off in the ICCR on
- * HyperSparcs for these accesses to work.  The code below does not do
- * any checking, the caller must do so.  These routines are for
- * diagnostics only, but could end up being useful.  Use with care.
- * Also, you are asking for trouble if you execute these in one of the
- * three instructions following a %asr/%psr access or modification.
- */
-/* First, cache-tag access. */
-static inline unsigned int get_icache_tag(int setnum, int tagnum)
-{
-        unsigned int vaddr, retval;
-        vaddr = ((setnum&1) << 12) | ((tagnum&0x7f) << 5);
-        __asm__ __volatile__("lda [%1] %2, %0\n\t" :
-                             "=r" (retval) :
-                             "r" (vaddr), "i" (ASI_M_TXTC_TAG));
-        return retval;
-}
-static inline void put_icache_tag(int setnum, int tagnum, unsigned int entry)
-{
-        unsigned int vaddr;
-        vaddr = ((setnum&1) << 12) | ((tagnum&0x7f) << 5);
-        __asm__ __volatile__("sta %0, [%1] %2\n\t" : :
-                             "r" (entry), "r" (vaddr), "i" (ASI_M_TXTC_TAG) :
-                             "memory");
-}
-/* Second cache-data access.  The data is returned two-32bit quantities
- * at a time.
- */
-static inline void get_icache_data(int setnum, int tagnum, int subblock,
-                                       unsigned int *data)
-{
-        unsigned int value1, value2, vaddr;
-        vaddr = ((setnum&0x1) << 12) | ((tagnum&0x7f) << 5) |
-                ((subblock&0x3) << 3);
-        __asm__ __volatile__("ldda [%2] %3, %%g2\n\t"
-                             "or %%g0, %%g2, %0\n\t"
-                             "or %%g0, %%g3, %1\n\t" :
-                             "=r" (value1), "=r" (value2) :
-                             "r" (vaddr), "i" (ASI_M_TXTC_DATA) :
-                             "g2", "g3");
-        data[0] = value1; data[1] = value2;
-}
-static inline void put_icache_data(int setnum, int tagnum, int subblock,
-                                       unsigned int *data)
-{
-        unsigned int value1, value2, vaddr;
-        vaddr = ((setnum&0x1) << 12) | ((tagnum&0x7f) << 5) |
-                ((subblock&0x3) << 3);
-        value1 = data[0]; value2 = data[1];
-        __asm__ __volatile__("or %%g0, %0, %%g2\n\t"
-                             "or %%g0, %1, %%g3\n\t"
-                             "stda %%g2, [%2] %3\n\t" : :
-                             "r" (value1), "r" (value2), 
-                             "r" (vaddr), "i" (ASI_M_TXTC_DATA) :
-                             "g2", "g3", "memory" /* no joke */);
-}
-/* Different types of flushes with the ICACHE.  Some of the flushes
- * affect both the ICACHE and the external cache.  Others only clear
- * the ICACHE entries on the cpu itself.  V8's (most) allow
- * granularity of flushes on the packet (element in line), whole line,
- * and entire cache (ie. all lines) level.  The ICACHE only flushes are
- * ROSS HyperSparc specific and are in ross.h
- */
-/* Flushes which clear out both the on-chip and external caches */
-static inline void flush_ei_page(unsigned int addr)
-{
-        __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
-                             "r" (addr), "i" (ASI_M_FLUSH_PAGE) :
-                             "memory");
-}
-static inline void flush_ei_seg(unsigned int addr)
-{
-        __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
-                             "r" (addr), "i" (ASI_M_FLUSH_SEG) :
-                             "memory");
-}
-static inline void flush_ei_region(unsigned int addr)
-{
-        __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
-                             "r" (addr), "i" (ASI_M_FLUSH_REGION) :
-                             "memory");
-}
-static inline void flush_ei_ctx(unsigned int addr)
-{
-        __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
-                             "r" (addr), "i" (ASI_M_FLUSH_CTX) :
-                             "memory");
-}
-static inline void flush_ei_user(unsigned int addr)
-{
-        __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
-                             "r" (addr), "i" (ASI_M_FLUSH_USER) :
-                             "memory");
-}
-#endif /* CONFIG_SPARC32 */
 #endif /* !(_SPARC_CACHE_H) */
diff --git a/arch/sparc/include/asm/cacheflush.h b/arch/sparc/include/asm/cacheflush.h
index 049168087b19..f6c4839b8388 100644
--- a/arch/sparc/include/asm/cacheflush.h
+++ b/arch/sparc/include/asm/cacheflush.h
@@ -1,5 +1,9 @@
 #ifndef ___ASM_SPARC_CACHEFLUSH_H
 #define ___ASM_SPARC_CACHEFLUSH_H
+/* flush addr - to allow use of self-modifying code */
+#define flushi(addr)    __asm__ __volatile__ ("flush %0" : : "r" (addr) : "memory")
 #if defined(__sparc__) && defined(__arch64__)
 #include <asm/cacheflush_64.h>
 #else
diff --git a/arch/sparc/include/asm/cacheflush_32.h b/arch/sparc/include/asm/cacheflush_32.h
index 68431b47a22a..bb014c24f318 100644
--- a/arch/sparc/include/asm/cacheflush_32.h
+++ b/arch/sparc/include/asm/cacheflush_32.h
@@ -1,56 +1,18 @@
 #ifndef _SPARC_CACHEFLUSH_H
 #define _SPARC_CACHEFLUSH_H
-#include <linux/mm.h>           /* Common for other includes */
+#include <asm/cachetlb_32.h>
-// #include <linux/kernel.h> from pgalloc.h
-// #include <linux/sched.h>  from pgalloc.h
+#define flush_cache_all() \
+        sparc32_cachetlb_ops->cache_all()
-// #include <asm/page.h>
+#define flush_cache_mm(mm) \
-#include <asm/btfixup.h>
+        sparc32_cachetlb_ops->cache_mm(mm)
+#define flush_cache_dup_mm(mm) \
-/*
+        sparc32_cachetlb_ops->cache_mm(mm)
- * Fine grained cache flushing.
+#define flush_cache_range(vma,start,end) \
- */
+        sparc32_cachetlb_ops->cache_range(vma, start, end)
-#ifdef CONFIG_SMP
+#define flush_cache_page(vma,addr,pfn) \
+        sparc32_cachetlb_ops->cache_page(vma, addr)
-BTFIXUPDEF_CALL(void, local_flush_cache_all, void)
-BTFIXUPDEF_CALL(void, local_flush_cache_mm, struct mm_struct *)
-BTFIXUPDEF_CALL(void, local_flush_cache_range, struct vm_area_struct *, unsigned long, unsigned long)
-BTFIXUPDEF_CALL(void, local_flush_cache_page, struct vm_area_struct *, unsigned long)
-#define local_flush_cache_all() BTFIXUP_CALL(local_flush_cache_all)()
-#define local_flush_cache_mm(mm) BTFIXUP_CALL(local_flush_cache_mm)(mm)
-#define local_flush_cache_range(vma,start,end) BTFIXUP_CALL(local_flush_cache_range)(vma,start,end)
-#define local_flush_cache_page(vma,addr) BTFIXUP_CALL(local_flush_cache_page)(vma,addr)
-BTFIXUPDEF_CALL(void, local_flush_page_to_ram, unsigned long)
-BTFIXUPDEF_CALL(void, local_flush_sig_insns, struct mm_struct *, unsigned long)
-#define local_flush_page_to_ram(addr) BTFIXUP_CALL(local_flush_page_to_ram)(addr)
-#define local_flush_sig_insns(mm,insn_addr) BTFIXUP_CALL(local_flush_sig_insns)(mm,insn_addr)
-extern void smp_flush_cache_all(void);
-extern void smp_flush_cache_mm(struct mm_struct *mm);
-extern void smp_flush_cache_range(struct vm_area_struct *vma,
-                                  unsigned long start,
-                                  unsigned long end);
-extern void smp_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
-extern void smp_flush_page_to_ram(unsigned long page);
-extern void smp_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
-#endif /* CONFIG_SMP */
-BTFIXUPDEF_CALL(void, flush_cache_all, void)
-BTFIXUPDEF_CALL(void, flush_cache_mm, struct mm_struct *)
-BTFIXUPDEF_CALL(void, flush_cache_range, struct vm_area_struct *, unsigned long, unsigned long)
-BTFIXUPDEF_CALL(void, flush_cache_page, struct vm_area_struct *, unsigned long)
-#define flush_cache_all() BTFIXUP_CALL(flush_cache_all)()
-#define flush_cache_mm(mm) BTFIXUP_CALL(flush_cache_mm)(mm)
-#define flush_cache_dup_mm(mm) BTFIXUP_CALL(flush_cache_mm)(mm)
-#define flush_cache_range(vma,start,end) BTFIXUP_CALL(flush_cache_range)(vma,start,end)
-#define flush_cache_page(vma,addr,pfn) BTFIXUP_CALL(flush_cache_page)(vma,addr)
 #define flush_icache_range(start, end)          do { } while (0)
 #define flush_icache_page(vma, pg)              do { } while (0)
@@ -67,11 +29,12 @@ BTFIXUPDEF_CALL(void, flush_cache_page, struct vm_area_struct *, unsigned long)
                memcpy(dst, src, len);                          \
        } while (0)
-BTFIXUPDEF_CALL(void, __flush_page_to_ram, unsigned long)
+#define __flush_page_to_ram(addr) \
-BTFIXUPDEF_CALL(void, flush_sig_insns, struct mm_struct *, unsigned long)
+        sparc32_cachetlb_ops->page_to_ram(addr)
+#define flush_sig_insns(mm,insn_addr) \
-#define __flush_page_to_ram(addr) BTFIXUP_CALL(__flush_page_to_ram)(addr)
+        sparc32_cachetlb_ops->sig_insns(mm, insn_addr)
-#define flush_sig_insns(mm,insn_addr) BTFIXUP_CALL(flush_sig_insns)(mm,insn_addr)
+#define flush_page_for_dma(addr) \
+        sparc32_cachetlb_ops->page_for_dma(addr)
 extern void sparc_flush_page_to_ram(struct page *page);
diff --git a/arch/sparc/include/asm/cacheflush_64.h b/arch/sparc/include/asm/cacheflush_64.h
index 2efea2ff88b7..301736d9e7a1 100644
--- a/arch/sparc/include/asm/cacheflush_64.h
+++ b/arch/sparc/include/asm/cacheflush_64.h
@@ -8,9 +8,6 @@
 #include <linux/mm.h>
 /* Cache flush operations. */
-#define flushi(addr)    __asm__ __volatile__ ("flush %0" : : "r" (addr) : "memory")
 #define flushw_all()    __asm__ __volatile__("flushw")
 extern void __flushw_user(void);
diff --git a/arch/sparc/include/asm/cachetlb_32.h b/arch/sparc/include/asm/cachetlb_32.h
new file mode 100644
index 000000000000..efb19889a083
--- /dev/null
+++ b/arch/sparc/include/asm/cachetlb_32.h
@@ -0,0 +1,29 @@
+#ifndef _SPARC_CACHETLB_H
+#define _SPARC_CACHETLB_H
+struct mm_struct;
+struct vm_area_struct;
+struct sparc32_cachetlb_ops {
+        void (*cache_all)(void);
+        void (*cache_mm)(struct mm_struct *);
+        void (*cache_range)(struct vm_area_struct *, unsigned long,
+                            unsigned long);
+        void (*cache_page)(struct vm_area_struct *, unsigned long);
+        void (*tlb_all)(void);
+        void (*tlb_mm)(struct mm_struct *);
+        void (*tlb_range)(struct vm_area_struct *, unsigned long,
+                          unsigned long);
+        void (*tlb_page)(struct vm_area_struct *, unsigned long);
+        void (*page_to_ram)(unsigned long);
+        void (*sig_insns)(struct mm_struct *, unsigned long);
+        void (*page_for_dma)(unsigned long);
+};
+extern const struct sparc32_cachetlb_ops *sparc32_cachetlb_ops;
+#ifdef CONFIG_SMP
+extern const struct sparc32_cachetlb_ops *local_ops;
+#endif
+#endif /* SPARC_CACHETLB_H */
diff --git a/arch/sparc/include/asm/cmpxchg_32.h b/arch/sparc/include/asm/cmpxchg_32.h
index c786b0a92b51..1fae1a02e3c2 100644
--- a/arch/sparc/include/asm/cmpxchg_32.h
+++ b/arch/sparc/include/asm/cmpxchg_32.h
@@ -11,40 +11,13 @@
 #ifndef __ARCH_SPARC_CMPXCHG__
 #define __ARCH_SPARC_CMPXCHG__
-#include <asm/btfixup.h>
-/* This has special calling conventions */
-#ifndef CONFIG_SMP
-BTFIXUPDEF_CALL(void, ___xchg32, void)
-#endif
 static inline unsigned long xchg_u32(__volatile__ unsigned long *m, unsigned long val)
 {
-#ifdef CONFIG_SMP
        __asm__ __volatile__("swap [%2], %0"
                             : "=&r" (val)
                             : "0" (val), "r" (m)
                             : "memory");
        return val;
-#else
-        register unsigned long *ptr asm("g1");
-        register unsigned long ret asm("g2");
-        ptr = (unsigned long *) m;
-        ret = val;
-        /* Note: this is magic and the nop there is
-           really needed. */
-        __asm__ __volatile__(
-        "mov    %%o7, %%g4\n\t"
-        "call   ___f____xchg32\n\t"
-        " nop\n\t"
-        : "=&r" (ret)
-        : "0" (ret), "r" (ptr)
-        : "g3", "g4", "g7", "memory", "cc");
-        return ret;
-#endif
 }
 extern void __xchg_called_with_bad_pointer(void);
diff --git a/arch/sparc/include/asm/contregs.h b/arch/sparc/include/asm/contregs.h
index 48fa8a4ef357..b8abdfcf5555 100644
--- a/arch/sparc/include/asm/contregs.h
+++ b/arch/sparc/include/asm/contregs.h
@@ -7,28 +7,6 @@
 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
 */
-/* 3=sun3
-   4=sun4 (as in sun4 sysmaint student book)
-   c=sun4c (according to davem) */
-#define AC_IDPROM     0x00000000    /* 34  ID PROM, R/O, byte, 32 bytes      */
-#define AC_PAGEMAP    0x10000000    /* 3   Pagemap R/W, long                 */
-#define AC_SEGMAP     0x20000000    /* 3   Segment map, byte                 */
-#define AC_CONTEXT    0x30000000    /* 34c current mmu-context               */
-#define AC_SENABLE    0x40000000    /* 34c system dvma/cache/reset enable reg*/
-#define AC_UDVMA_ENB  0x50000000    /* 34  Not used on Sun boards, byte      */
-#define AC_BUS_ERROR  0x60000000    /* 34  Not cleared on read, byte.        */
-#define AC_SYNC_ERR   0x60000000    /*  c fault type                         */
-#define AC_SYNC_VA    0x60000004    /*  c fault virtual address              */
-#define AC_ASYNC_ERR  0x60000008    /*  c asynchronous fault type            */
-#define AC_ASYNC_VA   0x6000000c    /*  c async fault virtual address        */
-#define AC_LEDS       0x70000000    /* 34  Zero turns on LEDs, byte          */
-#define AC_CACHETAGS  0x80000000    /* 34c direct access to the VAC tags     */
-#define AC_CACHEDDATA 0x90000000    /* 3 c direct access to the VAC data     */
-#define AC_UDVMA_MAP  0xD0000000    /* 4  Not used on Sun boards, byte       */
-#define AC_VME_VECTOR 0xE0000000    /* 4  For non-Autovector VME, byte       */
-#define AC_BOOT_SCC   0xF0000000    /* 34  bypass to access Zilog 8530. byte.*/
 /* s=Swift, h=Ross_HyperSPARC, v=TI_Viking, t=Tsunami, r=Ross_Cypress        */
 #define AC_M_PCR      0x0000        /* shv Processor Control Reg             */
 #define AC_M_CTPR     0x0100        /* shv Context Table Pointer Reg         */
diff --git a/arch/sparc/include/asm/cpu_type.h b/arch/sparc/include/asm/cpu_type.h
index 4ca184d95d82..84d7d83b8084 100644
--- a/arch/sparc/include/asm/cpu_type.h
+++ b/arch/sparc/include/asm/cpu_type.h
@@ -5,30 +5,24 @@
 * Sparc (general) CPU types
 */
 enum sparc_cpu {
-  sun4        = 0x00,
+  sun4m       = 0x00,
-  sun4c       = 0x01,
+  sun4d       = 0x01,
-  sun4m       = 0x02,
+  sun4e       = 0x02,
-  sun4d       = 0x03,
+  sun4u       = 0x03, /* V8 ploos ploos */
-  sun4e       = 0x04,
+  sun_unknown = 0x04,
-  sun4u       = 0x05, /* V8 ploos ploos */
+  ap1000      = 0x05, /* almost a sun4m */
-  sun_unknown = 0x06,
+  sparc_leon  = 0x06, /* Leon SoC */
-  ap1000      = 0x07, /* almost a sun4m */
-  sparc_leon  = 0x08, /* Leon SoC */
 };
 #ifdef CONFIG_SPARC32
 extern enum sparc_cpu sparc_cpu_model;
-#define ARCH_SUN4C (sparc_cpu_model==sun4c)
 #define SUN4M_NCPUS            4              /* Architectural limit of sun4m. */
 #else
 #define sparc_cpu_model sun4u
-/* This cannot ever be a sun4c :) That's just history. */
-#define ARCH_SUN4C 0
 #endif
 #endif /* __ASM_CPU_TYPE_H */
diff --git a/arch/sparc/include/asm/cpudata_32.h b/arch/sparc/include/asm/cpudata_32.h
index a4c5a938b936..0300d94c25b3 100644
--- a/arch/sparc/include/asm/cpudata_32.h
+++ b/arch/sparc/include/asm/cpudata_32.h
@@ -14,7 +14,6 @@
 typedef struct {
        unsigned long udelay_val;
        unsigned long clock_tick;
-        unsigned int multiplier;
        unsigned int counter;
 #ifdef CONFIG_SMP
        unsigned int irq_resched_count;
diff --git a/arch/sparc/include/asm/cypress.h b/arch/sparc/include/asm/cypress.h
deleted file mode 100644
index 95e9772ea394..000000000000
--- a/arch/sparc/include/asm/cypress.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * cypress.h: Cypress module specific definitions and defines.
- *
- * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
- */
-#ifndef _SPARC_CYPRESS_H
-#define _SPARC_CYPRESS_H
-/* Cypress chips have %psr 'impl' of '0001' and 'vers' of '0001'. */
-/* The MMU control register fields on the Sparc Cypress 604/605 MMU's.
- *
- * ---------------------------------------------------------------
- * |implvers| MCA | MCM |MV| MID |BM| C|RSV|MR|CM|CL|CE|RSV|NF|ME|
- * ---------------------------------------------------------------
- *  31    24 23-22 21-20 19 18-15 14 13  12 11 10  9  8 7-2  1  0
- *
- * MCA: MultiChip Access -- Used for configuration of multiple
- *      CY7C604/605 cache units.
- * MCM: MultiChip Mask -- Again, for multiple cache unit config.
- * MV: MultiChip Valid -- Indicates MCM and MCA have valid settings.
- * MID: ModuleID -- Unique processor ID for MBus transactions. (605 only)
- * BM: Boot Mode -- 0 = not in boot mode, 1 = in boot mode
- * C: Cacheable -- Indicates whether accesses are cacheable while
- *    the MMU is off.  0=no 1=yes
- * MR: MemoryReflection -- Indicates whether the bus attached to the
- *     MBus supports memory reflection. 0=no 1=yes (605 only)
- * CM: CacheMode -- Indicates whether the cache is operating in write
- *     through or copy-back mode. 0=write-through 1=copy-back
- * CL: CacheLock -- Indicates if the entire cache is locked or not.
- *     0=not-locked 1=locked  (604 only)
- * CE: CacheEnable -- Is the virtual cache on? 0=no 1=yes
- * NF: NoFault -- Do faults generate traps? 0=yes 1=no
- * ME: MmuEnable -- Is the MMU doing translations? 0=no 1=yes
- */
-#define CYPRESS_MCA       0x00c00000
-#define CYPRESS_MCM       0x00300000
-#define CYPRESS_MVALID    0x00080000
-#define CYPRESS_MIDMASK   0x00078000   /* Only on 605 */
-#define CYPRESS_BMODE     0x00004000
-#define CYPRESS_ACENABLE  0x00002000
-#define CYPRESS_MRFLCT    0x00000800   /* Only on 605 */
-#define CYPRESS_CMODE     0x00000400
-#define CYPRESS_CLOCK     0x00000200   /* Only on 604 */
-#define CYPRESS_CENABLE   0x00000100
-#define CYPRESS_NFAULT    0x00000002
-#define CYPRESS_MENABLE   0x00000001
-static inline void cypress_flush_page(unsigned long page)
-{
-        __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
-                             "r" (page), "i" (ASI_M_FLUSH_PAGE));
-}
-static inline void cypress_flush_segment(unsigned long addr)
-{
-        __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
-                             "r" (addr), "i" (ASI_M_FLUSH_SEG));
-}
-static inline void cypress_flush_region(unsigned long addr)
-{
-        __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
-                             "r" (addr), "i" (ASI_M_FLUSH_REGION));
-}
-static inline void cypress_flush_context(void)
-{
-        __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t" : :
-                             "i" (ASI_M_FLUSH_CTX));
-}
-/* XXX Displacement flushes for buggy chips and initial testing
- * XXX go here.
- */
-#endif /* !(_SPARC_CYPRESS_H) */
diff --git a/arch/sparc/include/asm/dma.h b/arch/sparc/include/asm/dma.h
index b554927bbaf6..3d434ef5eae3 100644
--- a/arch/sparc/include/asm/dma.h
+++ b/arch/sparc/include/asm/dma.h
@@ -92,27 +92,31 @@ extern int isa_dma_bridge_buggy;
 #ifdef CONFIG_SPARC32
 /* Routines for data transfer buffers. */
-BTFIXUPDEF_CALL(char *, mmu_lockarea, char *, unsigned long)
-BTFIXUPDEF_CALL(void,   mmu_unlockarea, char *, unsigned long)
-#define mmu_lockarea(vaddr,len) BTFIXUP_CALL(mmu_lockarea)(vaddr,len)
-#define mmu_unlockarea(vaddr,len) BTFIXUP_CALL(mmu_unlockarea)(vaddr,len)
-struct page;
 struct device;
 struct scatterlist;
-/* These are implementations for sbus_map_sg/sbus_unmap_sg... collapse later */
+struct sparc32_dma_ops {
-BTFIXUPDEF_CALL(__u32, mmu_get_scsi_one, struct device *, char *, unsigned long)
+        __u32 (*get_scsi_one)(struct device *, char *, unsigned long);
-BTFIXUPDEF_CALL(void,  mmu_get_scsi_sgl, struct device *, struct scatterlist *, int)
+        void (*get_scsi_sgl)(struct device *, struct scatterlist *, int);
-BTFIXUPDEF_CALL(void,  mmu_release_scsi_one, struct device *, __u32, unsigned long)
+        void (*release_scsi_one)(struct device *, __u32, unsigned long);
-BTFIXUPDEF_CALL(void,  mmu_release_scsi_sgl, struct device *, struct scatterlist *, int)
+        void (*release_scsi_sgl)(struct device *, struct scatterlist *,int);
+#ifdef CONFIG_SBUS
-#define mmu_get_scsi_one(dev,vaddr,len) BTFIXUP_CALL(mmu_get_scsi_one)(dev,vaddr,len)
+        int (*map_dma_area)(struct device *, dma_addr_t *, unsigned long, unsigned long, int);
-#define mmu_get_scsi_sgl(dev,sg,sz) BTFIXUP_CALL(mmu_get_scsi_sgl)(dev,sg,sz)
+        void (*unmap_dma_area)(struct device *, unsigned long, int);
-#define mmu_release_scsi_one(dev,vaddr,len) BTFIXUP_CALL(mmu_release_scsi_one)(dev,vaddr,len)
+#endif
-#define mmu_release_scsi_sgl(dev,sg,sz) BTFIXUP_CALL(mmu_release_scsi_sgl)(dev,sg,sz)
+};
+extern const struct sparc32_dma_ops *sparc32_dma_ops;
+#define mmu_get_scsi_one(dev,vaddr,len) \
+        sparc32_dma_ops->get_scsi_one(dev, vaddr, len)
+#define mmu_get_scsi_sgl(dev,sg,sz) \
+        sparc32_dma_ops->get_scsi_sgl(dev, sg, sz)
+#define mmu_release_scsi_one(dev,vaddr,len) \
+        sparc32_dma_ops->release_scsi_one(dev, vaddr,len)
+#define mmu_release_scsi_sgl(dev,sg,sz) \
+        sparc32_dma_ops->release_scsi_sgl(dev, sg, sz)
+#ifdef CONFIG_SBUS
 /*
 * mmu_map/unmap are provided by iommu/iounit; Invalid to call on IIep.
 *
@@ -123,17 +127,17 @@ BTFIXUPDEF_CALL(void,  mmu_release_scsi_sgl, struct device *, struct scatterlist
 * Second mapping is for device visible address, or "bus" address.
 * The bus address is returned at '*pba'.
 *
- * These functions seem distinct, but are hard to split. On sun4c,
+ * These functions seem distinct, but are hard to split.
- * at least for now, 'a' is equal to bus address, and retured in *pba.
 * On sun4m, page attributes depend on the CPU type, so we have to
 * know if we are mapping RAM or I/O, so it has to be an additional argument
 * to a separate mapping function for CPU visible mappings.
 */
-BTFIXUPDEF_CALL(int, mmu_map_dma_area, struct device *, dma_addr_t *, unsigned long, unsigned long, int len)
+#define sbus_map_dma_area(dev,pba,va,a,len) \
-BTFIXUPDEF_CALL(void, mmu_unmap_dma_area, struct device *, unsigned long busa, int len)
+        sparc32_dma_ops->map_dma_area(dev, pba, va, a, len)
+#define sbus_unmap_dma_area(dev,ba,len) \
+        sparc32_dma_ops->unmap_dma_area(dev, ba, len)
+#endif /* CONFIG_SBUS */
-#define mmu_map_dma_area(dev,pba,va,a,len) BTFIXUP_CALL(mmu_map_dma_area)(dev,pba,va,a,len)
-#define mmu_unmap_dma_area(dev,ba,len) BTFIXUP_CALL(mmu_unmap_dma_area)(dev,ba,len)
 #endif
 #endif /* !(_ASM_SPARC_DMA_H) */
diff --git a/arch/sparc/include/asm/elf_32.h b/arch/sparc/include/asm/elf_32.h
index 4269ca6ad18a..2d4d755cba9e 100644
--- a/arch/sparc/include/asm/elf_32.h
+++ b/arch/sparc/include/asm/elf_32.h
@@ -118,16 +118,9 @@ typedef struct {
   instruction set this cpu supports.  This can NOT be done in userspace
   on Sparc.  */
-/* Sun4c has none of the capabilities, most sun4m's have them all.
+/* Most sun4m's have them all.  */
- * XXX This is gross, set some global variable at boot time. -DaveM
+#define ELF_HWCAP       (HWCAP_SPARC_FLUSH | HWCAP_SPARC_STBAR | \
- */
+                         HWCAP_SPARC_SWAP | HWCAP_SPARC_MULDIV)
-#define ELF_HWCAP       ((ARCH_SUN4C) ? 0 : \
-                         (HWCAP_SPARC_FLUSH | HWCAP_SPARC_STBAR | \
-                          HWCAP_SPARC_SWAP | \
-                          ((srmmu_modtype != Cypress && \
-                            srmmu_modtype != Cypress_vE && \
-                            srmmu_modtype != Cypress_vD) ? \
-                           HWCAP_SPARC_MULDIV : 0)))
 /* This yields a string that ld.so will use to load implementation
   specific libraries for optimization.  This is more specific in
diff --git a/arch/sparc/include/asm/floppy_32.h b/arch/sparc/include/asm/floppy_32.h
index 698d9559fead..fb3f16954c69 100644
--- a/arch/sparc/include/asm/floppy_32.h
+++ b/arch/sparc/include/asm/floppy_32.h
@@ -12,7 +12,6 @@
 #include <asm/page.h>
 #include <asm/pgtable.h>
 #include <asm/idprom.h>
-#include <asm/machines.h>
 #include <asm/oplib.h>
 #include <asm/auxio.h>
 #include <asm/irq.h>
@@ -103,25 +102,13 @@ static struct sun_floppy_ops sun_fdops;
 /* Routines unique to each controller type on a Sun. */
 static void sun_set_dor(unsigned char value, int fdc_82077)
 {
-        if (sparc_cpu_model == sun4c) {
+        if (fdc_82077)
-                unsigned int bits = 0;
-                if (value & 0x10)
-                        bits |= AUXIO_FLPY_DSEL;
-                if ((value & 0x80) == 0)
-                        bits |= AUXIO_FLPY_EJCT;
-                set_auxio(bits, (~bits) & (AUXIO_FLPY_DSEL|AUXIO_FLPY_EJCT));
-        }
-        if (fdc_82077) {
                sun_fdc->dor_82077 = value;
-        }
 }
 static unsigned char sun_read_dir(void)
 {
-        if (sparc_cpu_model == sun4c)
+        return sun_fdc->dir_82077;
-                return (get_auxio() & AUXIO_FLPY_DCHG) ? 0x80 : 0;
-        else
-                return sun_fdc->dir_82077;
 }
 static unsigned char sun_82072_fd_inb(int port)
@@ -242,10 +229,7 @@ static inline void virtual_dma_init(void)
 static inline void sun_fd_disable_dma(void)
 {
        doing_pdma = 0;
-        if (pdma_base) {
+        pdma_base = NULL;
-                mmu_unlockarea(pdma_base, pdma_areasize);
-                pdma_base = NULL;
-        }
 }
 static inline void sun_fd_set_dma_mode(int mode)
@@ -275,7 +259,6 @@ static inline void sun_fd_set_dma_count(int length)
 static inline void sun_fd_enable_dma(void)
 {
-        pdma_vaddr = mmu_lockarea(pdma_vaddr, pdma_size);
        pdma_base = pdma_vaddr;
        pdma_areasize = pdma_size;
 }
@@ -301,38 +284,36 @@ static int sun_floppy_init(void)
 {
        struct platform_device *op;
        struct device_node *dp;
+        struct resource r;
        char state[128];
-        phandle tnode, fd_node;
+        phandle fd_node;
+        phandle tnode;
        int num_regs;
-        struct resource r;
        use_virtual_dma = 1;
        /* Forget it if we aren't on a machine that could possibly
         * ever have a floppy drive.
         */
-        if((sparc_cpu_model != sun4c && sparc_cpu_model != sun4m) ||
+        if (sparc_cpu_model != sun4m) {
-           ((idprom->id_machtype == (SM_SUN4C | SM_4C_SLC)) ||
-            (idprom->id_machtype == (SM_SUN4C | SM_4C_ELC)))) {
                /* We certainly don't have a floppy controller. */
                goto no_sun_fdc;
        }
        /* Well, try to find one. */
        tnode = prom_getchild(prom_root_node);
        fd_node = prom_searchsiblings(tnode, "obio");
-        if(fd_node != 0) {
+        if (fd_node != 0) {
                tnode = prom_getchild(fd_node);
                fd_node = prom_searchsiblings(tnode, "SUNW,fdtwo");
        } else {
                fd_node = prom_searchsiblings(tnode, "fd");
        }
-        if(fd_node == 0) {
+        if (fd_node == 0) {
                goto no_sun_fdc;
        }
        /* The sun4m lets us know if the controller is actually usable. */
-        if(sparc_cpu_model == sun4m &&
+        if (prom_getproperty(fd_node, "status", state, sizeof(state)) != -1) {
-           prom_getproperty(fd_node, "status", state, sizeof(state)) != -1) {
                if(!strcmp(state, "disabled")) {
                        goto no_sun_fdc;
                }
@@ -343,12 +324,12 @@ static int sun_floppy_init(void)
        memset(&r, 0, sizeof(r));
        r.flags = fd_regs[0].which_io;
        r.start = fd_regs[0].phys_addr;
-        sun_fdc = (struct sun_flpy_controller *)
+        sun_fdc = of_ioremap(&r, 0, fd_regs[0].reg_size, "floppy");
-            of_ioremap(&r, 0, fd_regs[0].reg_size, "floppy");
        /* Look up irq in platform_device.
         * We try "SUNW,fdtwo" and "fd"
         */
+        op = NULL;
        for_each_node_by_name(dp, "SUNW,fdtwo") {
                op = of_find_device_by_node(dp);
                if (op)
@@ -367,7 +348,7 @@ static int sun_floppy_init(void)
        FLOPPY_IRQ = op->archdata.irqs[0];
        /* Last minute sanity check... */
-        if(sun_fdc->status_82072 == 0xff) {
+        if (sun_fdc->status_82072 == 0xff) {
                sun_fdc = NULL;
                goto no_sun_fdc;
        }
diff --git a/arch/sparc/include/asm/floppy_64.h b/arch/sparc/include/asm/floppy_64.h
index bcef1f5a2a6d..e204f902e6c9 100644
--- a/arch/sparc/include/asm/floppy_64.h
+++ b/arch/sparc/include/asm/floppy_64.h
@@ -161,10 +161,7 @@ unsigned long pdma_areasize;
 static void sun_fd_disable_dma(void)
 {
        doing_pdma = 0;
-        if (pdma_base) {
+        pdma_base = NULL;
-                mmu_unlockarea(pdma_base, pdma_areasize);
-                pdma_base = NULL;
-        }
 }
 static void sun_fd_set_dma_mode(int mode)
@@ -194,7 +191,6 @@ static void sun_fd_set_dma_count(int length)
 static void sun_fd_enable_dma(void)
 {
-        pdma_vaddr = mmu_lockarea(pdma_vaddr, pdma_size);
        pdma_base = pdma_vaddr;
        pdma_areasize = pdma_size;
 }
diff --git a/arch/sparc/include/asm/head_32.h b/arch/sparc/include/asm/head_32.h
index 7c35491a8b53..a76874838f61 100644
--- a/arch/sparc/include/asm/head_32.h
+++ b/arch/sparc/include/asm/head_32.h
@@ -2,15 +2,8 @@
 #define __SPARC_HEAD_H
 #define KERNBASE        0xf0000000  /* First address the kernel will eventually be */
-#define LOAD_ADDR       0x4000      /* prom jumps to us here unless this is elf /boot */
-#define SUN4C_SEGSZ     (1 << 18)
-#define SRMMU_L1_KBASE_OFFSET ((KERNBASE>>24)<<2)  /* Used in boot remapping. */
-#define INTS_ENAB        0x01           /* entry.S uses this. */
-#define SUN4_PROM_VECTOR 0xFFE81000     /* SUN4 PROM needs to be hardwired */
 #define WRITE_PAUSE      nop; nop; nop; /* Have to do this after %wim/%psr chg */
-#define NOP_INSN         0x01000000     /* Used to patch sparc_save_state */
 /* Here are some trap goodies */
@@ -18,9 +11,7 @@
 #define TRAP_ENTRY(type, label) \
        rd %psr, %l0; b label; rd %wim, %l3; nop;
-/* Data/text faults. Defaults to sun4c version at boot time. */
+/* Data/text faults */
-#define SPARC_TFAULT rd %psr, %l0; rd %wim, %l3; b sun4c_fault; mov 1, %l7;
-#define SPARC_DFAULT rd %psr, %l0; rd %wim, %l3; b sun4c_fault; mov 0, %l7;
 #define SRMMU_TFAULT rd %psr, %l0; rd %wim, %l3; b srmmu_fault; mov 1, %l7;
 #define SRMMU_DFAULT rd %psr, %l0; rd %wim, %l3; b srmmu_fault; mov 0, %l7;
@@ -80,16 +71,6 @@
 #define TRAP_ENTRY_INTERRUPT(int_level) \
        mov int_level, %l7; rd %psr, %l0; b real_irq_entry; rd %wim, %l3;
-/* NMI's (Non Maskable Interrupts) are special, you can't keep them
- * from coming in, and basically if you get one, the shows over. ;(
- * On the sun4c they are usually asynchronous memory errors, on the
- * the sun4m they could be either due to mem errors or a software
- * initiated interrupt from the prom/kern on an SMP box saying "I
- * command you to do CPU tricks, read your mailbox for more info."
- */
-#define NMI_TRAP \
-        rd %wim, %l3; b linux_trap_nmi_sun4c; mov %psr, %l0; nop;
 /* Window overflows/underflows are special and we need to try to be as
 * efficient as possible here....
 */
diff --git a/arch/sparc/include/asm/leon.h b/arch/sparc/include/asm/leon.h
index a4e457f003ed..07659124c140 100644
--- a/arch/sparc/include/asm/leon.h
+++ b/arch/sparc/include/asm/leon.h
@@ -10,19 +10,6 @@
 #ifdef CONFIG_SPARC_LEON
-#define ASI_LEON_NOCACHE        0x01
-#define ASI_LEON_DCACHE_MISS    0x1
-#define ASI_LEON_CACHEREGS      0x02
-#define ASI_LEON_IFLUSH         0x10
-#define ASI_LEON_DFLUSH         0x11
-#define ASI_LEON_MMUFLUSH       0x18
-#define ASI_LEON_MMUREGS        0x19
-#define ASI_LEON_BYPASS         0x1c
-#define ASI_LEON_FLUSH_PAGE     0x10
 /* mmu register access, ASI_LEON_MMUREGS */
 #define LEON_CNR_CTRL           0x000
 #define LEON_CNR_CTXP           0x100
@@ -57,29 +44,6 @@
 #define LEON_IRQMASK_R          0x0000fffe      /* bit 15- 1 of lregs.irqmask */
 #define LEON_IRQPRIO_R          0xfffe0000      /* bit 31-17 of lregs.irqmask */
-/* leon uart register definitions */
-#define LEON_OFF_UDATA  0x0
-#define LEON_OFF_USTAT  0x4
-#define LEON_OFF_UCTRL  0x8
-#define LEON_OFF_USCAL  0xc
-#define LEON_UCTRL_RE   0x01
-#define LEON_UCTRL_TE   0x02
-#define LEON_UCTRL_RI   0x04
-#define LEON_UCTRL_TI   0x08
-#define LEON_UCTRL_PS   0x10
-#define LEON_UCTRL_PE   0x20
-#define LEON_UCTRL_FL   0x40
-#define LEON_UCTRL_LB   0x80
-#define LEON_USTAT_DR   0x01
-#define LEON_USTAT_TS   0x02
-#define LEON_USTAT_TH   0x04
-#define LEON_USTAT_BR   0x08
-#define LEON_USTAT_OV   0x10
-#define LEON_USTAT_PE   0x20
-#define LEON_USTAT_FE   0x40
 #define LEON_MCFG2_SRAMDIS              0x00002000
 #define LEON_MCFG2_SDRAMEN              0x00004000
 #define LEON_MCFG2_SRAMBANKSZ           0x00001e00      /* [12-9] */
@@ -89,8 +53,6 @@
 #define LEON_TCNT0_MASK 0x7fffff
-#define LEON_USTAT_ERROR (LEON_USTAT_OV | LEON_USTAT_PE | LEON_USTAT_FE)
-/* no break yet */
 #define ASI_LEON3_SYSCTRL               0x02
 #define ASI_LEON3_SYSCTRL_ICFG          0x08
@@ -278,18 +240,11 @@ static inline int sparc_leon3_cpuid(void)
 #define LEON2_CFG_SSIZE_MASK 0x00007000UL
 #ifndef __ASSEMBLY__
-extern unsigned long srmmu_swprobe(unsigned long vaddr, unsigned long *paddr);
-extern void leon_flush_icache_all(void);
-extern void leon_flush_dcache_all(void);
-extern void leon_flush_cache_all(void);
-extern void leon_flush_tlb_all(void);
-extern int leon_flush_during_switch;
-extern int leon_flush_needed(void);
 struct vm_area_struct;
+extern unsigned long srmmu_swprobe(unsigned long vaddr, unsigned long *paddr);
 extern void leon_flush_icache_all(void);
 extern void leon_flush_dcache_all(void);
-extern void leon_flush_pcache_all(struct vm_area_struct *vma, unsigned long page);
 extern void leon_flush_cache_all(void);
 extern void leon_flush_tlb_all(void);
 extern int leon_flush_during_switch;
@@ -315,28 +270,19 @@ struct leon2_cacheregs {
 #include <linux/interrupt.h>
 struct device_node;
+struct task_struct;
 extern unsigned int leon_build_device_irq(unsigned int real_irq,
                                           irq_flow_handler_t flow_handler,
                                           const char *name, int do_ack);
 extern void leon_update_virq_handling(unsigned int virq,
                              irq_flow_handler_t flow_handler,
                              const char *name, int do_ack);
-extern void leon_clear_clock_irq(void);
+extern void leon_init_timers(void);
-extern void leon_load_profile_irq(int cpu, unsigned int limit);
-extern void leon_init_timers(irq_handler_t counter_fn);
-extern void leon_clear_clock_irq(void);
-extern void leon_load_profile_irq(int cpu, unsigned int limit);
 extern void leon_trans_init(struct device_node *dp);
 extern void leon_node_init(struct device_node *dp, struct device_node ***nextp);
-extern void leon_init_IRQ(void);
-extern void leon_init(void);
-extern unsigned long srmmu_swprobe(unsigned long vaddr, unsigned long *paddr);
 extern void init_leon(void);
 extern void poke_leonsparc(void);
 extern void leon3_getCacheRegs(struct leon3_cacheregs *regs);
-extern int leon_flush_needed(void);
-extern void leon_switch_mm(void);
-extern int srmmu_swprobe_trace;
 extern int leon3_ticker_irq;
 #ifdef CONFIG_SMP
@@ -344,7 +290,7 @@ extern int leon_smp_nrcpus(void);
 extern void leon_clear_profile_irq(int cpu);
 extern void leon_smp_done(void);
 extern void leon_boot_cpus(void);
-extern int leon_boot_one_cpu(int i);
+extern int leon_boot_one_cpu(int i, struct task_struct *);
 void leon_init_smp(void);
 extern void cpu_idle(void);
 extern void init_IRQ(void);
@@ -380,7 +326,7 @@ extern int leon_ipi_irq;
 #define init_leon() do {} while (0)
 #define leon_smp_done() do {} while (0)
 #define leon_boot_cpus() do {} while (0)
-#define leon_boot_one_cpu(i) 1
+#define leon_boot_one_cpu(i, t) 1
 #define leon_init_smp() do {} while (0)
 #endif /* !defined(CONFIG_SPARC_LEON) */
diff --git a/arch/sparc/include/asm/machines.h b/arch/sparc/include/asm/machines.h
index cd9c099567e4..fd6ddb05d1b7 100644
--- a/arch/sparc/include/asm/machines.h
+++ b/arch/sparc/include/asm/machines.h
@@ -12,11 +12,6 @@ struct Sun_Machine_Models {
        unsigned char id_machtype;
 };
-/* Current number of machines we know about that has an IDPROM
- * machtype entry including one entry for the 0x80 OBP machines.
- */
-#define NUM_SUN_MACHINES   16
 /* The machine type in the idprom area looks like this:
 *
 * ---------------
@@ -24,36 +19,20 @@ struct Sun_Machine_Models {
 * ---------------
 *  7    4 3    0
 *
- * The ARCH field determines the architecture line (sun4, sun4c, etc).
+ * The ARCH field determines the architecture line (sun4m, etc).
 * The MACH field determines the machine make within that architecture.
 */
 #define SM_ARCH_MASK  0xf0
-#define SM_SUN4       0x20
 #define  M_LEON       0x30
-#define SM_SUN4C      0x50
 #define SM_SUN4M      0x70
 #define SM_SUN4M_OBP  0x80
 #define SM_TYP_MASK   0x0f
-/* Sun4 machines */
-#define SM_4_260      0x01    /* Sun 4/200 series */
-#define SM_4_110      0x02    /* Sun 4/100 series */
-#define SM_4_330      0x03    /* Sun 4/300 series */
-#define SM_4_470      0x04    /* Sun 4/400 series */
 /* Leon machines */
 #define M_LEON3_SOC   0x02    /* Leon3 SoC */
-/* Sun4c machines                Full Name              - PROM NAME */
-#define SM_4C_SS1     0x01    /* Sun4c SparcStation 1   - Sun 4/60  */
-#define SM_4C_IPC     0x02    /* Sun4c SparcStation IPC - Sun 4/40  */
-#define SM_4C_SS1PLUS 0x03    /* Sun4c SparcStation 1+  - Sun 4/65  */
-#define SM_4C_SLC     0x04    /* Sun4c SparcStation SLC - Sun 4/20  */
-#define SM_4C_SS2     0x05    /* Sun4c SparcStation 2   - Sun 4/75  */
-#define SM_4C_ELC     0x06    /* Sun4c SparcStation ELC - Sun 4/25  */
-#define SM_4C_IPX     0x07    /* Sun4c SparcStation IPX - Sun 4/50  */
 /* Sun4m machines, these predate the OpenBoot.  These values only mean
 * something if the value in the ARCH field is SM_SUN4M, if it is
 * SM_SUN4M_OBP then you have the following situation:
diff --git a/arch/sparc/include/asm/mbus.h b/arch/sparc/include/asm/mbus.h
index 69f07a022ee6..14128bcc5821 100644
--- a/arch/sparc/include/asm/mbus.h
+++ b/arch/sparc/include/asm/mbus.h
@@ -8,14 +8,10 @@
 #define _SPARC_MBUS_H
 #include <asm/ross.h>    /* HyperSparc stuff */
-#include <asm/cypress.h> /* Cypress Chips */
 #include <asm/viking.h>  /* Ugh, bug city... */
 enum mbus_module {
        HyperSparc        = 0,
-        Cypress           = 1,
-        Cypress_vE        = 2,
-        Cypress_vD        = 3,
        Swift_ok          = 4,
        Swift_bad_c       = 5,
        Swift_lots_o_bugs = 6,
diff --git a/arch/sparc/include/asm/memreg.h b/arch/sparc/include/asm/memreg.h
deleted file mode 100644
index 845ad2b39183..000000000000
--- a/arch/sparc/include/asm/memreg.h
+++ /dev/null
@@ -1,51 +0,0 @@
-#ifndef _SPARC_MEMREG_H
-#define _SPARC_MEMREG_H
-/* memreg.h:  Definitions of the values found in the synchronous
- *            and asynchronous memory error registers when a fault
- *            occurs on the sun4c.
- *
- * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
- */
-/* First the synchronous error codes, these are usually just
- * normal page faults.
- */
-#define SUN4C_SYNC_WDRESET   0x0001  /* watchdog reset */
-#define SUN4C_SYNC_SIZE      0x0002  /* bad access size? whuz this? */
-#define SUN4C_SYNC_PARITY    0x0008  /* bad ram chips caused a parity error */
-#define SUN4C_SYNC_SBUS      0x0010  /* the SBUS had some problems... */
-#define SUN4C_SYNC_NOMEM     0x0020  /* translation to non-existent ram */
-#define SUN4C_SYNC_PROT      0x0040  /* access violated pte protections */
-#define SUN4C_SYNC_NPRESENT  0x0080  /* pte said that page was not present */
-#define SUN4C_SYNC_BADWRITE  0x8000  /* while writing something went bogus */
-#define SUN4C_SYNC_BOLIXED  \
-        (SUN4C_SYNC_WDRESET | SUN4C_SYNC_SIZE | SUN4C_SYNC_SBUS | \
-         SUN4C_SYNC_NOMEM | SUN4C_SYNC_PARITY)
-/* Now the asynchronous error codes, these are almost always produced
- * by the cache writing things back to memory and getting a bad translation.
- * Bad DVMA transactions can cause these faults too.
- */
-#define SUN4C_ASYNC_BADDVMA 0x0010  /* error during DVMA access */
-#define SUN4C_ASYNC_NOMEM   0x0020  /* write back pointed to bad phys addr */
-#define SUN4C_ASYNC_BADWB   0x0080  /* write back points to non-present page */
-/* Memory parity error register with associated bit constants. */
-#ifndef __ASSEMBLY__
-extern __volatile__ unsigned long __iomem *sun4c_memerr_reg;
-#endif
-#define SUN4C_MPE_ERROR 0x80    /* Parity error detected. (ro) */
-#define SUN4C_MPE_MULTI 0x40    /* Multiple parity errors detected. (ro) */
-#define SUN4C_MPE_TEST  0x20    /* Write inverse parity. (rw) */
-#define SUN4C_MPE_CHECK 0x10    /* Enable parity checking. (rw) */
-#define SUN4C_MPE_ERR00 0x08    /* Parity error in bits 0-7. (ro) */
-#define SUN4C_MPE_ERR08 0x04    /* Parity error in bits 8-15. (ro) */
-#define SUN4C_MPE_ERR16 0x02    /* Parity error in bits 16-23. (ro) */
-#define SUN4C_MPE_ERR24 0x01    /* Parity error in bits 24-31. (ro) */
-#define SUN4C_MPE_ERRS  0x0F    /* Bit mask for the error bits. (ro) */
-#endif /* !(_SPARC_MEMREG_H) */
diff --git a/arch/sparc/include/asm/mmu_context_32.h b/arch/sparc/include/asm/mmu_context_32.h
index 671a997b9e69..01456c900720 100644
--- a/arch/sparc/include/asm/mmu_context_32.h
+++ b/arch/sparc/include/asm/mmu_context_32.h
@@ -1,8 +1,6 @@
 #ifndef __SPARC_MMU_CONTEXT_H
 #define __SPARC_MMU_CONTEXT_H
-#include <asm/btfixup.h>
 #ifndef __ASSEMBLY__
 #include <asm-generic/mm_hooks.h>
@@ -23,14 +21,11 @@ static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
 * all the page tables have been flushed.  Our job is to destroy
 * any remaining processor-specific state.
 */
-BTFIXUPDEF_CALL(void, destroy_context, struct mm_struct *)
+void destroy_context(struct mm_struct *mm);
-#define destroy_context(mm) BTFIXUP_CALL(destroy_context)(mm)
 /* Switch the current MM context. */
-BTFIXUPDEF_CALL(void, switch_mm, struct mm_struct *, struct mm_struct *, struct task_struct *)
+void switch_mm(struct mm_struct *old_mm, struct mm_struct *mm,
+               struct task_struct *tsk);
-#define switch_mm(old_mm, mm, tsk) BTFIXUP_CALL(switch_mm)(old_mm, mm, tsk)
 #define deactivate_mm(tsk,mm)   do { } while (0)
diff --git a/arch/sparc/include/asm/obio.h b/arch/sparc/include/asm/obio.h
index 4ade0c8a2c79..910c1d9af1f8 100644
--- a/arch/sparc/include/asm/obio.h
+++ b/arch/sparc/include/asm/obio.h
@@ -220,19 +220,6 @@ static inline void cc_set_igen(unsigned gen)
                              "i" (ASI_M_MXCC));
 }
-/* +-------+-------------+-----------+------------------------------------+
- * | bcast |  devid      |   sid     |              levels mask           |
- * +-------+-------------+-----------+------------------------------------+
- *  31      30         23 22       15 14                                 0
- */
-#define IGEN_MESSAGE(bcast, devid, sid, levels) \
-        (((bcast) << 31) | ((devid) << 23) | ((sid) << 15) | (levels))
-            
-static inline void sun4d_send_ipi(int cpu, int level)
-{
-        cc_set_igen(IGEN_MESSAGE(0, cpu << 3, 6 + ((level >> 1) & 7), 1 << (level - 1)));
-}
 #endif /* !__ASSEMBLY__ */
 #endif /* !(_SPARC_OBIO_H) */
diff --git a/arch/sparc/include/asm/oplib_32.h b/arch/sparc/include/asm/oplib_32.h
index 71e5e9aeb67e..27517879a6c2 100644
--- a/arch/sparc/include/asm/oplib_32.h
+++ b/arch/sparc/include/asm/oplib_32.h
@@ -105,14 +105,6 @@ extern void prom_write(const char *buf, unsigned int len);
 extern int prom_startcpu(int cpunode, struct linux_prom_registers *context_table,
                         int context, char *program_counter);
-/* Sun4/sun4c specific memory-management startup hook. */
-/* Map the passed segment in the given context at the passed
- * virtual address.
- */
-extern void prom_putsegment(int context, unsigned long virt_addr,
-                            int physical_segment);
 /* Initialize the memory lists based upon the prom version. */
 void prom_meminit(void);
diff --git a/arch/sparc/include/asm/page_32.h b/arch/sparc/include/asm/page_32.h
index bb5c2ac4055d..fab78a308ebf 100644
--- a/arch/sparc/include/asm/page_32.h
+++ b/arch/sparc/include/asm/page_32.h
@@ -14,8 +14,6 @@
 #define PAGE_SIZE    (_AC(1, UL) << PAGE_SHIFT)
 #define PAGE_MASK    (~(PAGE_SIZE-1))
-#include <asm/btfixup.h>
 #ifndef __ASSEMBLY__
 #define clear_page(page)         memset((void *)(page), 0, PAGE_SIZE)
@@ -45,12 +43,6 @@ struct sparc_phys_banks {
 extern struct sparc_phys_banks sp_banks[SPARC_PHYS_BANKS+1];
-/* Cache alias structure.  Entry is valid if context != -1. */
-struct cache_palias {
-        unsigned long vaddr;
-        int context;
-};
 /* passing structs on the Sparc slow us down tremendously... */
 /* #define STRICT_MM_TYPECHECKS */
@@ -116,10 +108,7 @@ typedef unsigned long iopgprot_t;
 typedef struct page *pgtable_t;
 extern unsigned long sparc_unmapped_base;
+#define TASK_UNMAPPED_BASE      sparc_unmapped_base
-BTFIXUPDEF_SETHI(sparc_unmapped_base)
-#define TASK_UNMAPPED_BASE      BTFIXUP_SETHI(sparc_unmapped_base)
 #else /* !(__ASSEMBLY__) */
diff --git a/arch/sparc/include/asm/pgalloc_32.h b/arch/sparc/include/asm/pgalloc_32.h
index ca2b34456c4b..e5b169b46d21 100644
--- a/arch/sparc/include/asm/pgalloc_32.h
+++ b/arch/sparc/include/asm/pgalloc_32.h
@@ -4,8 +4,10 @@
 #include <linux/kernel.h>
 #include <linux/sched.h>
+#include <asm/pgtsrmmu.h>
+#include <asm/pgtable.h>
+#include <asm/vaddrs.h>
 #include <asm/page.h>
-#include <asm/btfixup.h>
 struct page;
@@ -15,54 +17,74 @@ extern struct pgtable_cache_struct {
        unsigned long pgtable_cache_sz;
        unsigned long pgd_cache_sz;
 } pgt_quicklists;
+unsigned long srmmu_get_nocache(int size, int align);
+void srmmu_free_nocache(unsigned long vaddr, int size);
 #define pgd_quicklist           (pgt_quicklists.pgd_cache)
 #define pmd_quicklist           ((unsigned long *)0)
 #define pte_quicklist           (pgt_quicklists.pte_cache)
 #define pgtable_cache_size      (pgt_quicklists.pgtable_cache_sz)
 #define pgd_cache_size          (pgt_quicklists.pgd_cache_sz)
-extern void check_pgt_cache(void);
+#define check_pgt_cache()       do { } while (0)
-BTFIXUPDEF_CALL(void,    do_check_pgt_cache, int, int)
-#define do_check_pgt_cache(low,high) BTFIXUP_CALL(do_check_pgt_cache)(low,high)
-BTFIXUPDEF_CALL(pgd_t *, get_pgd_fast, void)
-#define get_pgd_fast()          BTFIXUP_CALL(get_pgd_fast)()
-BTFIXUPDEF_CALL(void, free_pgd_fast, pgd_t *)
+pgd_t *get_pgd_fast(void);
-#define free_pgd_fast(pgd)      BTFIXUP_CALL(free_pgd_fast)(pgd)
+static inline void free_pgd_fast(pgd_t *pgd)
+{
+        srmmu_free_nocache((unsigned long)pgd, SRMMU_PGD_TABLE_SIZE);
+}
 #define pgd_free(mm, pgd)       free_pgd_fast(pgd)
 #define pgd_alloc(mm)   get_pgd_fast()
-BTFIXUPDEF_CALL(void, pgd_set, pgd_t *, pmd_t *)
+static inline void pgd_set(pgd_t * pgdp, pmd_t * pmdp)
-#define pgd_set(pgdp,pmdp) BTFIXUP_CALL(pgd_set)(pgdp,pmdp)
+{
+        unsigned long pa = __nocache_pa((unsigned long)pmdp);
+        set_pte((pte_t *)pgdp, (SRMMU_ET_PTD | (pa >> 4)));
+}
 #define pgd_populate(MM, PGD, PMD)      pgd_set(PGD, PMD)
-BTFIXUPDEF_CALL(pmd_t *, pmd_alloc_one, struct mm_struct *, unsigned long)
+static inline pmd_t *pmd_alloc_one(struct mm_struct *mm,
-#define pmd_alloc_one(mm, address)      BTFIXUP_CALL(pmd_alloc_one)(mm, address)
+                                   unsigned long address)
+{
+        return (pmd_t *)srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE,
+                                          SRMMU_PMD_TABLE_SIZE);
+}
-BTFIXUPDEF_CALL(void, free_pmd_fast, pmd_t *)
+static inline void free_pmd_fast(pmd_t * pmd)
-#define free_pmd_fast(pmd)      BTFIXUP_CALL(free_pmd_fast)(pmd)
+{
+        srmmu_free_nocache((unsigned long)pmd, SRMMU_PMD_TABLE_SIZE);
+}
 #define pmd_free(mm, pmd)               free_pmd_fast(pmd)
 #define __pmd_free_tlb(tlb, pmd, addr)  pmd_free((tlb)->mm, pmd)
-BTFIXUPDEF_CALL(void, pmd_populate, pmd_t *, struct page *)
+void pmd_populate(struct mm_struct *mm, pmd_t *pmdp, struct page *ptep);
-#define pmd_populate(MM, PMD, PTE)        BTFIXUP_CALL(pmd_populate)(PMD, PTE)
 #define pmd_pgtable(pmd) pmd_page(pmd)
-BTFIXUPDEF_CALL(void, pmd_set, pmd_t *, pte_t *)
-#define pmd_populate_kernel(MM, PMD, PTE) BTFIXUP_CALL(pmd_set)(PMD, PTE)
-BTFIXUPDEF_CALL(pgtable_t , pte_alloc_one, struct mm_struct *, unsigned long)
+void pmd_set(pmd_t *pmdp, pte_t *ptep);
-#define pte_alloc_one(mm, address)      BTFIXUP_CALL(pte_alloc_one)(mm, address)
+#define pmd_populate_kernel(MM, PMD, PTE) pmd_set(PMD, PTE)
-BTFIXUPDEF_CALL(pte_t *, pte_alloc_one_kernel, struct mm_struct *, unsigned long)
-#define pte_alloc_one_kernel(mm, addr)  BTFIXUP_CALL(pte_alloc_one_kernel)(mm, addr)
+pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long address);
+static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
+                                          unsigned long address)
+{
+        return (pte_t *)srmmu_get_nocache(PTE_SIZE, PTE_SIZE);
+}
+static inline void free_pte_fast(pte_t *pte)
+{
+        srmmu_free_nocache((unsigned long)pte, PTE_SIZE);
+}
-BTFIXUPDEF_CALL(void, free_pte_fast, pte_t *)
+#define pte_free_kernel(mm, pte)        free_pte_fast(pte)
-#define pte_free_kernel(mm, pte)        BTFIXUP_CALL(free_pte_fast)(pte)
-BTFIXUPDEF_CALL(void, pte_free, pgtable_t )
+void pte_free(struct mm_struct * mm, pgtable_t pte);
-#define pte_free(mm, pte)               BTFIXUP_CALL(pte_free)(pte)
 #define __pte_free_tlb(tlb, pte, addr)  pte_free((tlb)->mm, pte)
 #endif /* _SPARC_PGALLOC_H */
diff --git a/arch/sparc/include/asm/pgtable_32.h b/arch/sparc/include/asm/pgtable_32.h
index 3d7101860e68..cbbbed5cb3aa 100644
--- a/arch/sparc/include/asm/pgtable_32.h
+++ b/arch/sparc/include/asm/pgtable_32.h
@@ -16,11 +16,9 @@
 #include <linux/spinlock.h>
 #include <linux/swap.h>
 #include <asm/types.h>
-#include <asm/pgtsun4c.h>
 #include <asm/pgtsrmmu.h>
-#include <asm/vac-ops.h>
+#include <asm/vaddrs.h>
 #include <asm/oplib.h>
-#include <asm/btfixup.h>
 #include <asm/cpu_type.h>
@@ -30,87 +28,55 @@ struct page;
 extern void load_mmu(void);
 extern unsigned long calc_highpages(void);
-BTFIXUPDEF_SIMM13(pgdir_shift)
-BTFIXUPDEF_SETHI(pgdir_size)
-BTFIXUPDEF_SETHI(pgdir_mask)
-BTFIXUPDEF_SIMM13(ptrs_per_pmd)
-BTFIXUPDEF_SIMM13(ptrs_per_pgd)
-BTFIXUPDEF_SIMM13(user_ptrs_per_pgd)
 #define pte_ERROR(e)   __builtin_trap()
 #define pmd_ERROR(e)   __builtin_trap()
 #define pgd_ERROR(e)   __builtin_trap()
-BTFIXUPDEF_INT(page_none)
+#define PMD_SHIFT               22
-BTFIXUPDEF_INT(page_copy)
-BTFIXUPDEF_INT(page_readonly)
-BTFIXUPDEF_INT(page_kernel)
-#define PMD_SHIFT               SUN4C_PMD_SHIFT
 #define PMD_SIZE                (1UL << PMD_SHIFT)
 #define PMD_MASK                (~(PMD_SIZE-1))
 #define PMD_ALIGN(__addr)       (((__addr) + ~PMD_MASK) & PMD_MASK)
-#define PGDIR_SHIFT             BTFIXUP_SIMM13(pgdir_shift)
+#define PGDIR_SHIFT             SRMMU_PGDIR_SHIFT
-#define PGDIR_SIZE              BTFIXUP_SETHI(pgdir_size)
+#define PGDIR_SIZE              SRMMU_PGDIR_SIZE
-#define PGDIR_MASK              BTFIXUP_SETHI(pgdir_mask)
+#define PGDIR_MASK              SRMMU_PGDIR_MASK
 #define PTRS_PER_PTE            1024
-#define PTRS_PER_PMD            BTFIXUP_SIMM13(ptrs_per_pmd)
+#define PTRS_PER_PMD            SRMMU_PTRS_PER_PMD
-#define PTRS_PER_PGD            BTFIXUP_SIMM13(ptrs_per_pgd)
+#define PTRS_PER_PGD            SRMMU_PTRS_PER_PGD
-#define USER_PTRS_PER_PGD       BTFIXUP_SIMM13(user_ptrs_per_pgd)
+#define USER_PTRS_PER_PGD       PAGE_OFFSET / SRMMU_PGDIR_SIZE
 #define FIRST_USER_ADDRESS      0
 #define PTE_SIZE                (PTRS_PER_PTE*4)
-#define PAGE_NONE      __pgprot(BTFIXUP_INT(page_none))
+#define PAGE_NONE       SRMMU_PAGE_NONE
-extern pgprot_t PAGE_SHARED;
+#define PAGE_SHARED     SRMMU_PAGE_SHARED
-#define PAGE_COPY      __pgprot(BTFIXUP_INT(page_copy))
+#define PAGE_COPY       SRMMU_PAGE_COPY
-#define PAGE_READONLY  __pgprot(BTFIXUP_INT(page_readonly))
+#define PAGE_READONLY   SRMMU_PAGE_RDONLY
+#define PAGE_KERNEL     SRMMU_PAGE_KERNEL
-extern unsigned long page_kernel;
-#ifdef MODULE
-#define PAGE_KERNEL     page_kernel
-#else
-#define PAGE_KERNEL    __pgprot(BTFIXUP_INT(page_kernel))
-#endif
 /* Top-level page directory */
 extern pgd_t swapper_pg_dir[1024];
 extern void paging_init(void);
-/* Page table for 0-4MB for everybody, on the Sparc this
- * holds the same as on the i386.
- */
-extern pte_t pg0[1024];
-extern pte_t pg1[1024];
-extern pte_t pg2[1024];
-extern pte_t pg3[1024];
 extern unsigned long ptr_in_current_pgd;
-/* Here is a trick, since mmap.c need the initializer elements for
+/*         xwr */
- * protection_map[] to be constant at compile time, I set the following
+#define __P000  PAGE_NONE
- * to all zeros.  I set it to the real values after I link in the
+#define __P001  PAGE_READONLY
- * appropriate MMU page table routines at boot time.
+#define __P010  PAGE_COPY
- */
+#define __P011  PAGE_COPY
-#define __P000  __pgprot(0)
+#define __P100  PAGE_READONLY
-#define __P001  __pgprot(0)
+#define __P101  PAGE_READONLY
-#define __P010  __pgprot(0)
+#define __P110  PAGE_COPY
-#define __P011  __pgprot(0)
+#define __P111  PAGE_COPY
-#define __P100  __pgprot(0)
-#define __P101  __pgprot(0)
+#define __S000  PAGE_NONE
-#define __P110  __pgprot(0)
+#define __S001  PAGE_READONLY
-#define __P111  __pgprot(0)
+#define __S010  PAGE_SHARED
+#define __S011  PAGE_SHARED
-#define __S000  __pgprot(0)
+#define __S100  PAGE_READONLY
-#define __S001  __pgprot(0)
+#define __S101  PAGE_READONLY
-#define __S010  __pgprot(0)
+#define __S110  PAGE_SHARED
-#define __S011  __pgprot(0)
+#define __S111  PAGE_SHARED
-#define __S100  __pgprot(0)
-#define __S101  __pgprot(0)
-#define __S110  __pgprot(0)
-#define __S111  __pgprot(0)
 extern int num_contexts;
@@ -137,82 +103,137 @@ extern unsigned long empty_zero_page;
 #define ZERO_PAGE(vaddr) (virt_to_page(&empty_zero_page))
 /*
+ * In general all page table modifications should use the V8 atomic
+ * swap instruction.  This insures the mmu and the cpu are in sync
+ * with respect to ref/mod bits in the page tables.
+ */
+static inline unsigned long srmmu_swap(unsigned long *addr, unsigned long value)
+{
+        __asm__ __volatile__("swap [%2], %0" : "=&r" (value) : "0" (value), "r" (addr));
+        return value;
+}
+/* Certain architectures need to do special things when pte's
+ * within a page table are directly modified.  Thus, the following
+ * hook is made available.
 */
-BTFIXUPDEF_CALL_CONST(struct page *, pmd_page, pmd_t)
-BTFIXUPDEF_CALL_CONST(unsigned long, pgd_page_vaddr, pgd_t)
-#define pmd_page(pmd) BTFIXUP_CALL(pmd_page)(pmd)
+static inline void set_pte(pte_t *ptep, pte_t pteval)
-#define pgd_page_vaddr(pgd) BTFIXUP_CALL(pgd_page_vaddr)(pgd)
+{
+        srmmu_swap((unsigned long *)ptep, pte_val(pteval));
+}
+#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
+static inline int srmmu_device_memory(unsigned long x)
+{
+        return ((x & 0xF0000000) != 0);
+}
+static inline struct page *pmd_page(pmd_t pmd)
+{
+        if (srmmu_device_memory(pmd_val(pmd)))
+                BUG();
+        return pfn_to_page((pmd_val(pmd) & SRMMU_PTD_PMASK) >> (PAGE_SHIFT-4));
+}
+static inline unsigned long pgd_page_vaddr(pgd_t pgd)
+{
+        if (srmmu_device_memory(pgd_val(pgd))) {
+                return ~0;
+        } else {
+                unsigned long v = pgd_val(pgd) & SRMMU_PTD_PMASK;
+                return (unsigned long)__nocache_va(v << 4);
+        }
+}
-BTFIXUPDEF_CALL_CONST(int, pte_present, pte_t)
+static inline int pte_present(pte_t pte)
-BTFIXUPDEF_CALL(void, pte_clear, pte_t *)
+{
+        return ((pte_val(pte) & SRMMU_ET_MASK) == SRMMU_ET_PTE);
+}
 static inline int pte_none(pte_t pte)
 {
        return !pte_val(pte);
 }
-#define pte_present(pte) BTFIXUP_CALL(pte_present)(pte)
+static inline void __pte_clear(pte_t *ptep)
-#define pte_clear(mm,addr,pte) BTFIXUP_CALL(pte_clear)(pte)
+{
+        set_pte(ptep, __pte(0));
+}
+static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
+{
+        __pte_clear(ptep);
+}
+static inline int pmd_bad(pmd_t pmd)
+{
+        return (pmd_val(pmd) & SRMMU_ET_MASK) != SRMMU_ET_PTD;
+}
-BTFIXUPDEF_CALL_CONST(int, pmd_bad, pmd_t)
+static inline int pmd_present(pmd_t pmd)
-BTFIXUPDEF_CALL_CONST(int, pmd_present, pmd_t)
+{
-BTFIXUPDEF_CALL(void, pmd_clear, pmd_t *)
+        return ((pmd_val(pmd) & SRMMU_ET_MASK) == SRMMU_ET_PTD);
+}
 static inline int pmd_none(pmd_t pmd)
 {
        return !pmd_val(pmd);
 }
-#define pmd_bad(pmd) BTFIXUP_CALL(pmd_bad)(pmd)
+static inline void pmd_clear(pmd_t *pmdp)
-#define pmd_present(pmd) BTFIXUP_CALL(pmd_present)(pmd)
+{
-#define pmd_clear(pmd) BTFIXUP_CALL(pmd_clear)(pmd)
+        int i;
+        for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++)
+                set_pte((pte_t *)&pmdp->pmdv[i], __pte(0));
+}
-BTFIXUPDEF_CALL_CONST(int, pgd_none, pgd_t)
+static inline int pgd_none(pgd_t pgd)          
-BTFIXUPDEF_CALL_CONST(int, pgd_bad, pgd_t)
+{
-BTFIXUPDEF_CALL_CONST(int, pgd_present, pgd_t)
+        return !(pgd_val(pgd) & 0xFFFFFFF);
-BTFIXUPDEF_CALL(void, pgd_clear, pgd_t *)
+}
-#define pgd_none(pgd) BTFIXUP_CALL(pgd_none)(pgd)
+static inline int pgd_bad(pgd_t pgd)
-#define pgd_bad(pgd) BTFIXUP_CALL(pgd_bad)(pgd)
+{
-#define pgd_present(pgd) BTFIXUP_CALL(pgd_present)(pgd)
+        return (pgd_val(pgd) & SRMMU_ET_MASK) != SRMMU_ET_PTD;
-#define pgd_clear(pgd) BTFIXUP_CALL(pgd_clear)(pgd)
+}
+static inline int pgd_present(pgd_t pgd)
+{
+        return ((pgd_val(pgd) & SRMMU_ET_MASK) == SRMMU_ET_PTD);
+}
+static inline void pgd_clear(pgd_t *pgdp)
+{
+        set_pte((pte_t *)pgdp, __pte(0));
+}
 /*
 * The following only work if pte_present() is true.
 * Undefined behaviour if not..
 */
-BTFIXUPDEF_HALF(pte_writei)
-BTFIXUPDEF_HALF(pte_dirtyi)
-BTFIXUPDEF_HALF(pte_youngi)
-static int pte_write(pte_t pte) __attribute_const__;
 static inline int pte_write(pte_t pte)
 {
-        return pte_val(pte) & BTFIXUP_HALF(pte_writei);
+        return pte_val(pte) & SRMMU_WRITE;
 }
-static int pte_dirty(pte_t pte) __attribute_const__;
 static inline int pte_dirty(pte_t pte)
 {
-        return pte_val(pte) & BTFIXUP_HALF(pte_dirtyi);
+        return pte_val(pte) & SRMMU_DIRTY;
 }
-static int pte_young(pte_t pte) __attribute_const__;
 static inline int pte_young(pte_t pte)
 {
-        return pte_val(pte) & BTFIXUP_HALF(pte_youngi);
+        return pte_val(pte) & SRMMU_REF;
 }
 /*
 * The following only work if pte_present() is not true.
 */
-BTFIXUPDEF_HALF(pte_filei)
-static int pte_file(pte_t pte) __attribute_const__;
 static inline int pte_file(pte_t pte)
 {
-        return pte_val(pte) & BTFIXUP_HALF(pte_filei);
+        return pte_val(pte) & SRMMU_FILE;
 }
 static inline int pte_special(pte_t pte)
@@ -220,68 +241,85 @@ static inline int pte_special(pte_t pte)
        return 0;
 }
-/*
- */
-BTFIXUPDEF_HALF(pte_wrprotecti)
-BTFIXUPDEF_HALF(pte_mkcleani)
-BTFIXUPDEF_HALF(pte_mkoldi)
-static pte_t pte_wrprotect(pte_t pte) __attribute_const__;
 static inline pte_t pte_wrprotect(pte_t pte)
 {
-        return __pte(pte_val(pte) & ~BTFIXUP_HALF(pte_wrprotecti));
+        return __pte(pte_val(pte) & ~SRMMU_WRITE);
 }
-static pte_t pte_mkclean(pte_t pte) __attribute_const__;
 static inline pte_t pte_mkclean(pte_t pte)
 {
-        return __pte(pte_val(pte) & ~BTFIXUP_HALF(pte_mkcleani));
+        return __pte(pte_val(pte) & ~SRMMU_DIRTY);
 }
-static pte_t pte_mkold(pte_t pte) __attribute_const__;
 static inline pte_t pte_mkold(pte_t pte)
 {
-        return __pte(pte_val(pte) & ~BTFIXUP_HALF(pte_mkoldi));
+        return __pte(pte_val(pte) & ~SRMMU_REF);
 }
-BTFIXUPDEF_CALL_CONST(pte_t, pte_mkwrite, pte_t)
+static inline pte_t pte_mkwrite(pte_t pte)
-BTFIXUPDEF_CALL_CONST(pte_t, pte_mkdirty, pte_t)
+{
-BTFIXUPDEF_CALL_CONST(pte_t, pte_mkyoung, pte_t)
+        return __pte(pte_val(pte) | SRMMU_WRITE);
+}
+static inline pte_t pte_mkdirty(pte_t pte)
+{
+        return __pte(pte_val(pte) | SRMMU_DIRTY);
+}
-#define pte_mkwrite(pte) BTFIXUP_CALL(pte_mkwrite)(pte)
+static inline pte_t pte_mkyoung(pte_t pte)
-#define pte_mkdirty(pte) BTFIXUP_CALL(pte_mkdirty)(pte)
+{
-#define pte_mkyoung(pte) BTFIXUP_CALL(pte_mkyoung)(pte)
+        return __pte(pte_val(pte) | SRMMU_REF);
+}
 #define pte_mkspecial(pte)    (pte)
 #define pfn_pte(pfn, prot)              mk_pte(pfn_to_page(pfn), prot)
-BTFIXUPDEF_CALL(unsigned long,   pte_pfn, pte_t)
+static inline unsigned long pte_pfn(pte_t pte)
-#define pte_pfn(pte) BTFIXUP_CALL(pte_pfn)(pte)
+{
+        if (srmmu_device_memory(pte_val(pte))) {
+                /* Just return something that will cause
+                 * pfn_valid() to return false.  This makes
+                 * copy_one_pte() to just directly copy to
+                 * PTE over.
+                 */
+                return ~0UL;
+        }
+        return (pte_val(pte) & SRMMU_PTE_PMASK) >> (PAGE_SHIFT-4);
+}
 #define pte_page(pte)   pfn_to_page(pte_pfn(pte))
 /*
 * Conversion functions: convert a page and protection to a page entry,
 * and a page entry and page directory to the page they refer to.
 */
-BTFIXUPDEF_CALL_CONST(pte_t, mk_pte, struct page *, pgprot_t)
+static inline pte_t mk_pte(struct page *page, pgprot_t pgprot)
+{
-BTFIXUPDEF_CALL_CONST(pte_t, mk_pte_phys, unsigned long, pgprot_t)
+        return __pte((page_to_pfn(page) << (PAGE_SHIFT-4)) | pgprot_val(pgprot));
-BTFIXUPDEF_CALL_CONST(pte_t, mk_pte_io, unsigned long, pgprot_t, int)
+}
-BTFIXUPDEF_CALL_CONST(pgprot_t, pgprot_noncached, pgprot_t)
-#define mk_pte(page,pgprot) BTFIXUP_CALL(mk_pte)(page,pgprot)
+static inline pte_t mk_pte_phys(unsigned long page, pgprot_t pgprot)
-#define mk_pte_phys(page,pgprot) BTFIXUP_CALL(mk_pte_phys)(page,pgprot)
+{
-#define mk_pte_io(page,pgprot,space) BTFIXUP_CALL(mk_pte_io)(page,pgprot,space)
+        return __pte(((page) >> 4) | pgprot_val(pgprot));
+}
-#define pgprot_noncached(pgprot) BTFIXUP_CALL(pgprot_noncached)(pgprot)
+static inline pte_t mk_pte_io(unsigned long page, pgprot_t pgprot, int space)
+{
+        return __pte(((page) >> 4) | (space << 28) | pgprot_val(pgprot));
+}
-BTFIXUPDEF_INT(pte_modify_mask)
+#define pgprot_noncached pgprot_noncached
+static inline pgprot_t pgprot_noncached(pgprot_t prot)
+{
+        prot &= ~__pgprot(SRMMU_CACHE);
+        return prot;
+}
 static pte_t pte_modify(pte_t pte, pgprot_t newprot) __attribute_const__;
 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 {
-        return __pte((pte_val(pte) & BTFIXUP_INT(pte_modify_mask)) |
+        return __pte((pte_val(pte) & SRMMU_CHG_MASK) |
                pgprot_val(newprot));
 }
@@ -294,74 +332,69 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
 /* Find an entry in the second-level page table.. */
-BTFIXUPDEF_CALL(pmd_t *, pmd_offset, pgd_t *, unsigned long)
+static inline pmd_t *pmd_offset(pgd_t * dir, unsigned long address)
-#define pmd_offset(dir,addr) BTFIXUP_CALL(pmd_offset)(dir,addr)
+{
+        return (pmd_t *) pgd_page_vaddr(*dir) +
+                ((address >> PMD_SHIFT) & (PTRS_PER_PMD - 1));
+}
 /* Find an entry in the third-level page table.. */
-BTFIXUPDEF_CALL(pte_t *, pte_offset_kernel, pmd_t *, unsigned long)
+pte_t *pte_offset_kernel(pmd_t * dir, unsigned long address);
-#define pte_offset_kernel(dir,addr) BTFIXUP_CALL(pte_offset_kernel)(dir,addr)
 /*
- * This shortcut works on sun4m (and sun4d) because the nocache area is static,
+ * This shortcut works on sun4m (and sun4d) because the nocache area is static.
- * and sun4c is guaranteed to have no highmem anyway.
 */
 #define pte_offset_map(d, a)            pte_offset_kernel(d,a)
 #define pte_unmap(pte)          do{}while(0)
-/* Certain architectures need to do special things when pte's
- * within a page table are directly modified.  Thus, the following
- * hook is made available.
- */
-BTFIXUPDEF_CALL(void, set_pte, pte_t *, pte_t)
-#define set_pte(ptep,pteval) BTFIXUP_CALL(set_pte)(ptep,pteval)
-#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
 struct seq_file;
-BTFIXUPDEF_CALL(void, mmu_info, struct seq_file *)
+void mmu_info(struct seq_file *m);
-#define mmu_info(p) BTFIXUP_CALL(mmu_info)(p)
 /* Fault handler stuff... */
 #define FAULT_CODE_PROT     0x1
 #define FAULT_CODE_WRITE    0x2
 #define FAULT_CODE_USER     0x4
-BTFIXUPDEF_CALL(void, update_mmu_cache, struct vm_area_struct *, unsigned long, pte_t *)
+#define update_mmu_cache(vma, address, ptep) do { } while (0)
-#define update_mmu_cache(vma,addr,ptep) BTFIXUP_CALL(update_mmu_cache)(vma,addr,ptep)
-BTFIXUPDEF_CALL(void, sparc_mapiorange, unsigned int, unsigned long,
-    unsigned long, unsigned int)
-BTFIXUPDEF_CALL(void, sparc_unmapiorange, unsigned long, unsigned int)
-#define sparc_mapiorange(bus,pa,va,len) BTFIXUP_CALL(sparc_mapiorange)(bus,pa,va,len)
-#define sparc_unmapiorange(va,len) BTFIXUP_CALL(sparc_unmapiorange)(va,len)
-extern int invalid_segment;
+void srmmu_mapiorange(unsigned int bus, unsigned long xpa,
+                      unsigned long xva, unsigned int len);
+void srmmu_unmapiorange(unsigned long virt_addr, unsigned int len);
 /* Encode and de-code a swap entry */
-BTFIXUPDEF_CALL(unsigned long, __swp_type, swp_entry_t)
+static inline unsigned long __swp_type(swp_entry_t entry)
-BTFIXUPDEF_CALL(unsigned long, __swp_offset, swp_entry_t)
+{
-BTFIXUPDEF_CALL(swp_entry_t, __swp_entry, unsigned long, unsigned long)
+        return (entry.val >> SRMMU_SWP_TYPE_SHIFT) & SRMMU_SWP_TYPE_MASK;
+}
+static inline unsigned long __swp_offset(swp_entry_t entry)
+{
+        return (entry.val >> SRMMU_SWP_OFF_SHIFT) & SRMMU_SWP_OFF_MASK;
+}
-#define __swp_type(__x)                 BTFIXUP_CALL(__swp_type)(__x)
+static inline swp_entry_t __swp_entry(unsigned long type, unsigned long offset)
-#define __swp_offset(__x)               BTFIXUP_CALL(__swp_offset)(__x)
+{
-#define __swp_entry(__type,__off)       BTFIXUP_CALL(__swp_entry)(__type,__off)
+        return (swp_entry_t) {
+                (type & SRMMU_SWP_TYPE_MASK) << SRMMU_SWP_TYPE_SHIFT
+                | (offset & SRMMU_SWP_OFF_MASK) << SRMMU_SWP_OFF_SHIFT };
+}
 #define __pte_to_swp_entry(pte)         ((swp_entry_t) { pte_val(pte) })
 #define __swp_entry_to_pte(x)           ((pte_t) { (x).val })
 /* file-offset-in-pte helpers */
-BTFIXUPDEF_CALL(unsigned long, pte_to_pgoff, pte_t pte);
+static inline unsigned long pte_to_pgoff(pte_t pte)
-BTFIXUPDEF_CALL(pte_t, pgoff_to_pte, unsigned long pgoff);
+{
+        return pte_val(pte) >> SRMMU_PTE_FILE_SHIFT;
+}
-#define pte_to_pgoff(pte) BTFIXUP_CALL(pte_to_pgoff)(pte)
+static inline pte_t pgoff_to_pte(unsigned long pgoff)
-#define pgoff_to_pte(off) BTFIXUP_CALL(pgoff_to_pte)(off)
+{
+        return __pte((pgoff << SRMMU_PTE_FILE_SHIFT) | SRMMU_FILE);
+}
 /*
 * This is made a constant because mm/fremap.c required a constant.
- * Note that layout of these bits is different between sun4c.c and srmmu.c.
 */
 #define PTE_FILE_MAX_BITS 24
@@ -399,9 +432,6 @@ static inline unsigned long
 __get_phys (unsigned long addr)
 {
        switch (sparc_cpu_model){
-        case sun4:
-        case sun4c:
-                return sun4c_get_pte (addr) << PAGE_SHIFT;
        case sun4m:
        case sun4d:
                return ((srmmu_get_pte (addr) & 0xffffff00) << 4);
@@ -414,9 +444,6 @@ static inline int
 __get_iospace (unsigned long addr)
 {
        switch (sparc_cpu_model){
-        case sun4:
-        case sun4c:
-                return -1; /* Don't check iospace on sun4c */
        case sun4m:
        case sun4d:
                return (srmmu_get_pte (addr) >> 28);
@@ -463,7 +490,7 @@ static inline int io_remap_pfn_range(struct vm_area_struct *vma,
                set_pte_at((__vma)->vm_mm, (__address), __ptep, __entry); \
                flush_tlb_page(__vma, __address);                         \
        }                                                                 \
-        (sparc_cpu_model == sun4c) || __changed;                          \
+        __changed;                                                        \
 })
 #include <asm-generic/pgtable.h>
@@ -471,10 +498,8 @@ static inline int io_remap_pfn_range(struct vm_area_struct *vma,
 #endif /* !(__ASSEMBLY__) */
 #define VMALLOC_START           _AC(0xfe600000,UL)
-/* XXX Alter this when I get around to fixing sun4c - Anton */
 #define VMALLOC_END             _AC(0xffc00000,UL)
 /* We provide our own get_unmapped_area to cope with VA holes for userland */
 #define HAVE_ARCH_UNMAPPED_AREA
diff --git a/arch/sparc/include/asm/pgtable_64.h b/arch/sparc/include/asm/pgtable_64.h
index 76e4a52aa85e..61210db139fb 100644
--- a/arch/sparc/include/asm/pgtable_64.h
+++ b/arch/sparc/include/asm/pgtable_64.h
@@ -717,10 +717,6 @@ extern unsigned long find_ecache_flush_span(unsigned long size);
 struct seq_file;
 extern void mmu_info(struct seq_file *);
-/* These do nothing with the way I have things setup. */
-#define mmu_lockarea(vaddr, len)                (vaddr)
-#define mmu_unlockarea(vaddr, len)              do { } while(0)
 struct vm_area_struct;
 extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t *);
diff --git a/arch/sparc/include/asm/pgtsrmmu.h b/arch/sparc/include/asm/pgtsrmmu.h
index f6ae2b2b6870..cb828703a63a 100644
--- a/arch/sparc/include/asm/pgtsrmmu.h
+++ b/arch/sparc/include/asm/pgtsrmmu.h
@@ -173,17 +173,6 @@ static inline void srmmu_set_ctable_ptr(unsigned long paddr)
                             "memory");
 }
-static inline unsigned long srmmu_get_ctable_ptr(void)
-{
-        unsigned int retval;
-        __asm__ __volatile__("lda [%1] %2, %0\n\t" :
-                             "=r" (retval) :
-                             "r" (SRMMU_CTXTBL_PTR),
-                             "i" (ASI_M_MMUREGS));
-        return (retval & SRMMU_CTX_PMASK) << 4;
-}
 static inline void srmmu_set_context(int context)
 {
        __asm__ __volatile__("sta %0, [%1] %2\n\t" : :
@@ -231,42 +220,6 @@ static inline void srmmu_flush_whole_tlb(void)
 }
 /* These flush types are not available on all chips... */
-static inline void srmmu_flush_tlb_ctx(void)
-{
-        __asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
-                             "r" (0x300),        /* Flush TLB ctx.. */
-                             "i" (ASI_M_FLUSH_PROBE) : "memory");
-}
-static inline void srmmu_flush_tlb_region(unsigned long addr)
-{
-        addr &= SRMMU_PGDIR_MASK;
-        __asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
-                             "r" (addr | 0x200), /* Flush TLB region.. */
-                             "i" (ASI_M_FLUSH_PROBE) : "memory");
-}
-static inline void srmmu_flush_tlb_segment(unsigned long addr)
-{
-        addr &= SRMMU_REAL_PMD_MASK;
-        __asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
-                             "r" (addr | 0x100), /* Flush TLB segment.. */
-                             "i" (ASI_M_FLUSH_PROBE) : "memory");
-}
-static inline void srmmu_flush_tlb_page(unsigned long page)
-{
-        page &= PAGE_MASK;
-        __asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
-                             "r" (page),        /* Flush TLB page.. */
-                             "i" (ASI_M_FLUSH_PROBE) : "memory");
-}
 #ifndef CONFIG_SPARC_LEON
 static inline unsigned long srmmu_hwprobe(unsigned long vaddr)
 {
@@ -294,9 +247,6 @@ srmmu_get_pte (unsigned long addr)
        return entry;
 }
-extern unsigned long (*srmmu_read_physical)(unsigned long paddr);
-extern void (*srmmu_write_physical)(unsigned long paddr, unsigned long word);
 #endif /* !(__ASSEMBLY__) */
 #endif /* !(_SPARC_PGTSRMMU_H) */
diff --git a/arch/sparc/include/asm/pgtsun4c.h b/arch/sparc/include/asm/pgtsun4c.h
deleted file mode 100644
index aeb25e912179..000000000000
--- a/arch/sparc/include/asm/pgtsun4c.h
+++ /dev/null
@@ -1,172 +0,0 @@
-/*
- * pgtsun4c.h:  Sun4c specific pgtable.h defines and code.
- *
- * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
- */
-#ifndef _SPARC_PGTSUN4C_H
-#define _SPARC_PGTSUN4C_H
-#include <asm/contregs.h>
-/* PMD_SHIFT determines the size of the area a second-level page table can map */
-#define SUN4C_PMD_SHIFT       22
-/* PGDIR_SHIFT determines what a third-level page table entry can map */
-#define SUN4C_PGDIR_SHIFT       22
-#define SUN4C_PGDIR_SIZE        (1UL << SUN4C_PGDIR_SHIFT)
-#define SUN4C_PGDIR_MASK        (~(SUN4C_PGDIR_SIZE-1))
-#define SUN4C_PGDIR_ALIGN(addr) (((addr)+SUN4C_PGDIR_SIZE-1)&SUN4C_PGDIR_MASK)
-/* To represent how the sun4c mmu really lays things out. */
-#define SUN4C_REAL_PGDIR_SHIFT       18
-#define SUN4C_REAL_PGDIR_SIZE        (1UL << SUN4C_REAL_PGDIR_SHIFT)
-#define SUN4C_REAL_PGDIR_MASK        (~(SUN4C_REAL_PGDIR_SIZE-1))
-#define SUN4C_REAL_PGDIR_ALIGN(addr) (((addr)+SUN4C_REAL_PGDIR_SIZE-1)&SUN4C_REAL_PGDIR_MASK)
-/* 16 bit PFN on sun4c */
-#define SUN4C_PFN_MASK 0xffff
-/* Don't increase these unless the structures in sun4c.c are fixed */
-#define SUN4C_MAX_SEGMAPS 256
-#define SUN4C_MAX_CONTEXTS 16
-/*
- * To be efficient, and not have to worry about allocating such
- * a huge pgd, we make the kernel sun4c tables each hold 1024
- * entries and the pgd similarly just like the i386 tables.
- */
-#define SUN4C_PTRS_PER_PTE    1024
-#define SUN4C_PTRS_PER_PMD    1
-#define SUN4C_PTRS_PER_PGD    1024
-/*
- * Sparc SUN4C pte fields.
- */
-#define _SUN4C_PAGE_VALID        0x80000000
-#define _SUN4C_PAGE_SILENT_READ  0x80000000   /* synonym */
-#define _SUN4C_PAGE_DIRTY        0x40000000
-#define _SUN4C_PAGE_SILENT_WRITE 0x40000000   /* synonym */
-#define _SUN4C_PAGE_PRIV         0x20000000   /* privileged page */
-#define _SUN4C_PAGE_NOCACHE      0x10000000   /* non-cacheable page */
-#define _SUN4C_PAGE_PRESENT      0x08000000   /* implemented in software */
-#define _SUN4C_PAGE_IO           0x04000000   /* I/O page */
-#define _SUN4C_PAGE_FILE         0x02000000   /* implemented in software */
-#define _SUN4C_PAGE_READ         0x00800000   /* implemented in software */
-#define _SUN4C_PAGE_WRITE        0x00400000   /* implemented in software */
-#define _SUN4C_PAGE_ACCESSED     0x00200000   /* implemented in software */
-#define _SUN4C_PAGE_MODIFIED     0x00100000   /* implemented in software */
-#define _SUN4C_READABLE         (_SUN4C_PAGE_READ|_SUN4C_PAGE_SILENT_READ|\
-                                 _SUN4C_PAGE_ACCESSED)
-#define _SUN4C_WRITEABLE        (_SUN4C_PAGE_WRITE|_SUN4C_PAGE_SILENT_WRITE|\
-                                 _SUN4C_PAGE_MODIFIED)
-#define _SUN4C_PAGE_CHG_MASK    (0xffff|_SUN4C_PAGE_ACCESSED|_SUN4C_PAGE_MODIFIED)
-#define SUN4C_PAGE_NONE         __pgprot(_SUN4C_PAGE_PRESENT)
-#define SUN4C_PAGE_SHARED       __pgprot(_SUN4C_PAGE_PRESENT|_SUN4C_READABLE|\
-                                         _SUN4C_PAGE_WRITE)
-#define SUN4C_PAGE_COPY         __pgprot(_SUN4C_PAGE_PRESENT|_SUN4C_READABLE)
-#define SUN4C_PAGE_READONLY     __pgprot(_SUN4C_PAGE_PRESENT|_SUN4C_READABLE)
-#define SUN4C_PAGE_KERNEL       __pgprot(_SUN4C_READABLE|_SUN4C_WRITEABLE|\
-                                         _SUN4C_PAGE_DIRTY|_SUN4C_PAGE_PRIV)
-/* SUN4C swap entry encoding
- *
- * We use 5 bits for the type and 19 for the offset.  This gives us
- * 32 swapfiles of 4GB each.  Encoding looks like:
- *
- * RRRRRRRRooooooooooooooooooottttt
- * fedcba9876543210fedcba9876543210
- *
- * The top 8 bits are reserved for protection and status bits, especially
- * FILE and PRESENT.
- */
-#define SUN4C_SWP_TYPE_MASK     0x1f
-#define SUN4C_SWP_OFF_MASK      0x7ffff
-#define SUN4C_SWP_OFF_SHIFT     5
-#ifndef __ASSEMBLY__
-static inline unsigned long sun4c_get_synchronous_error(void)
-{
-        unsigned long sync_err;
-        __asm__ __volatile__("lda [%1] %2, %0\n\t" :
-                             "=r" (sync_err) :
-                             "r" (AC_SYNC_ERR), "i" (ASI_CONTROL));
-        return sync_err;
-}
-static inline unsigned long sun4c_get_synchronous_address(void)
-{
-        unsigned long sync_addr;
-        __asm__ __volatile__("lda [%1] %2, %0\n\t" :
-                             "=r" (sync_addr) :
-                             "r" (AC_SYNC_VA), "i" (ASI_CONTROL));
-        return sync_addr;
-}
-/* SUN4C pte, segmap, and context manipulation */
-static inline unsigned long sun4c_get_segmap(unsigned long addr)
-{
-  register unsigned long entry;
-  __asm__ __volatile__("\n\tlduba [%1] %2, %0\n\t" : 
-                       "=r" (entry) :
-                       "r" (addr), "i" (ASI_SEGMAP));
-  return entry;
-}
-static inline void sun4c_put_segmap(unsigned long addr, unsigned long entry)
-{
-  __asm__ __volatile__("\n\tstba %1, [%0] %2; nop; nop; nop;\n\t" : :
-                       "r" (addr), "r" (entry),
-                       "i" (ASI_SEGMAP)
-                       : "memory");
-}
-static inline unsigned long sun4c_get_pte(unsigned long addr)
-{
-  register unsigned long entry;
-  __asm__ __volatile__("\n\tlda [%1] %2, %0\n\t" : 
-                       "=r" (entry) :
-                       "r" (addr), "i" (ASI_PTE));
-  return entry;
-}
-static inline void sun4c_put_pte(unsigned long addr, unsigned long entry)
-{
-  __asm__ __volatile__("\n\tsta %1, [%0] %2; nop; nop; nop;\n\t" : :
-                       "r" (addr), 
-                       "r" ((entry & ~(_SUN4C_PAGE_PRESENT))), "i" (ASI_PTE)
-                       : "memory");
-}
-static inline int sun4c_get_context(void)
-{
-  register int ctx;
-  __asm__ __volatile__("\n\tlduba [%1] %2, %0\n\t" :
-                       "=r" (ctx) :
-                       "r" (AC_CONTEXT), "i" (ASI_CONTROL));
-  return ctx;
-}
-static inline int sun4c_set_context(int ctx)
-{
-  __asm__ __volatile__("\n\tstba %0, [%1] %2; nop; nop; nop;\n\t" : :
-                       "r" (ctx), "r" (AC_CONTEXT), "i" (ASI_CONTROL)
-                       : "memory");
-  return ctx;
-}
-#endif /* !(__ASSEMBLY__) */
-#endif /* !(_SPARC_PGTSUN4C_H) */
diff --git a/arch/sparc/include/asm/processor_32.h b/arch/sparc/include/asm/processor_32.h
index 09521c6a5edb..9cbd854fdfdd 100644
--- a/arch/sparc/include/asm/processor_32.h
+++ b/arch/sparc/include/asm/processor_32.h
@@ -16,7 +16,6 @@
 #include <asm/ptrace.h>
 #include <asm/head.h>
 #include <asm/signal.h>
-#include <asm/btfixup.h>
 #include <asm/page.h>
 /*
diff --git a/arch/sparc/include/asm/setup.h b/arch/sparc/include/asm/setup.h
index 00497abec996..8a83699a5507 100644
--- a/arch/sparc/include/asm/setup.h
+++ b/arch/sparc/include/asm/setup.h
@@ -20,10 +20,7 @@ extern char reboot_command[];
 * Only sun4d + leon may have boot_cpu_id != 0
 */
 extern unsigned char boot_cpu_id;
-extern unsigned char boot_cpu_id4;
-extern unsigned long empty_bad_page;
-extern unsigned long empty_bad_page_table;
 extern unsigned long empty_zero_page;
 extern int serial_console;
diff --git a/arch/sparc/include/asm/shmparam_32.h b/arch/sparc/include/asm/shmparam_32.h
index 59a1243c12f3..142825c8d3ac 100644
--- a/arch/sparc/include/asm/shmparam_32.h
+++ b/arch/sparc/include/asm/shmparam_32.h
@@ -4,8 +4,6 @@
 #define __ARCH_FORCE_SHMLBA     1
 extern int vac_cache_size;
-#define SHMLBA (vac_cache_size ? vac_cache_size : \
+#define SHMLBA (vac_cache_size ? vac_cache_size : PAGE_SIZE)
-                (sparc_cpu_model == sun4c ? (64 * 1024) : \
-                 (sparc_cpu_model == sun4 ? (128 * 1024) : PAGE_SIZE)))
 #endif /* _ASMSPARC_SHMPARAM_H */
diff --git a/arch/sparc/include/asm/smp_32.h b/arch/sparc/include/asm/smp_32.h
index 01c51c704341..b73da3c5f10a 100644
--- a/arch/sparc/include/asm/smp_32.h
+++ b/arch/sparc/include/asm/smp_32.h
@@ -8,7 +8,6 @@
 #include <linux/threads.h>
 #include <asm/head.h>
-#include <asm/btfixup.h>
 #ifndef __ASSEMBLY__
@@ -58,104 +57,53 @@ struct seq_file;
 void smp_bogo(struct seq_file *);
 void smp_info(struct seq_file *);
-BTFIXUPDEF_CALL(void, smp_cross_call, smpfunc_t, cpumask_t, unsigned long, unsigned long, unsigned long, unsigned long)
+struct sparc32_ipi_ops {
-BTFIXUPDEF_CALL(int, __hard_smp_processor_id, void)
+        void (*cross_call)(smpfunc_t func, cpumask_t mask, unsigned long arg1,
-BTFIXUPDEF_CALL(void, smp_ipi_resched, int);
+                           unsigned long arg2, unsigned long arg3,
-BTFIXUPDEF_CALL(void, smp_ipi_single, int);
+                           unsigned long arg4);
-BTFIXUPDEF_CALL(void, smp_ipi_mask_one, int);
+        void (*resched)(int cpu);
-BTFIXUPDEF_BLACKBOX(hard_smp_processor_id)
+        void (*single)(int cpu);
-BTFIXUPDEF_BLACKBOX(load_current)
+        void (*mask_one)(int cpu);
+};
-#define smp_cross_call(func,mask,arg1,arg2,arg3,arg4) BTFIXUP_CALL(smp_cross_call)(func,mask,arg1,arg2,arg3,arg4)
+extern const struct sparc32_ipi_ops *sparc32_ipi_ops;
+static inline void xc0(smpfunc_t func)
+{
+        sparc32_ipi_ops->cross_call(func, *cpu_online_mask, 0, 0, 0, 0);
+}
-static inline void xc0(smpfunc_t func) { smp_cross_call(func, *cpu_online_mask, 0, 0, 0, 0); }
 static inline void xc1(smpfunc_t func, unsigned long arg1)
-{ smp_cross_call(func, *cpu_online_mask, arg1, 0, 0, 0); }
-static inline void xc2(smpfunc_t func, unsigned long arg1, unsigned long arg2)
-{ smp_cross_call(func, *cpu_online_mask, arg1, arg2, 0, 0); }
-static inline void xc3(smpfunc_t func, unsigned long arg1, unsigned long arg2,
-                           unsigned long arg3)
-{ smp_cross_call(func, *cpu_online_mask, arg1, arg2, arg3, 0); }
-static inline void xc4(smpfunc_t func, unsigned long arg1, unsigned long arg2,
-                           unsigned long arg3, unsigned long arg4)
-{ smp_cross_call(func, *cpu_online_mask, arg1, arg2, arg3, arg4); }
-extern void arch_send_call_function_single_ipi(int cpu);
-extern void arch_send_call_function_ipi_mask(const struct cpumask *mask);
-static inline int cpu_logical_map(int cpu)
 {
-        return cpu;
+        sparc32_ipi_ops->cross_call(func, *cpu_online_mask, arg1, 0, 0, 0);
 }
+static inline void xc2(smpfunc_t func, unsigned long arg1, unsigned long arg2)
-static inline int hard_smp4m_processor_id(void)
 {
-        int cpuid;
+        sparc32_ipi_ops->cross_call(func, *cpu_online_mask, arg1, arg2, 0, 0);
-        __asm__ __volatile__("rd %%tbr, %0\n\t"
-                             "srl %0, 12, %0\n\t"
-                             "and %0, 3, %0\n\t" :
-                             "=&r" (cpuid));
-        return cpuid;
 }
-static inline int hard_smp4d_processor_id(void)
+static inline void xc3(smpfunc_t func, unsigned long arg1, unsigned long arg2,
+                       unsigned long arg3)
 {
-        int cpuid;
+        sparc32_ipi_ops->cross_call(func, *cpu_online_mask,
+                                    arg1, arg2, arg3, 0);
-        __asm__ __volatile__("lda [%%g0] %1, %0\n\t" :
-                             "=&r" (cpuid) : "i" (ASI_M_VIKING_TMP1));
-        return cpuid;
 }
-extern inline int hard_smpleon_processor_id(void)
+static inline void xc4(smpfunc_t func, unsigned long arg1, unsigned long arg2,
+                       unsigned long arg3, unsigned long arg4)
 {
-        int cpuid;
+        sparc32_ipi_ops->cross_call(func, *cpu_online_mask,
-        __asm__ __volatile__("rd     %%asr17,%0\n\t"
+                                    arg1, arg2, arg3, arg4);
-                             "srl    %0,28,%0" :
-                             "=&r" (cpuid) : );
-        return cpuid;
 }
-#ifndef MODULE
+extern void arch_send_call_function_single_ipi(int cpu);
-static inline int hard_smp_processor_id(void)
+extern void arch_send_call_function_ipi_mask(const struct cpumask *mask);
+static inline int cpu_logical_map(int cpu)
 {
-        int cpuid;
+        return cpu;
-        /* Black box - sun4m
-                __asm__ __volatile__("rd %%tbr, %0\n\t"
-                                     "srl %0, 12, %0\n\t"
-                                     "and %0, 3, %0\n\t" :
-                                     "=&r" (cpuid));
-                     - sun4d
-                __asm__ __volatile__("lda [%g0] ASI_M_VIKING_TMP1, %0\n\t"
-                                     "nop; nop" :
-                                     "=&r" (cpuid));
-                     - leon
-                __asm__ __volatile__(   "rd %asr17, %0\n\t"
-                                        "srl %0, 0x1c, %0\n\t"
-                                        "nop\n\t" :
-                                        "=&r" (cpuid));
-           See btfixup.h and btfixupprep.c to understand how a blackbox works.
-         */
-        __asm__ __volatile__("sethi %%hi(___b_hard_smp_processor_id), %0\n\t"
-                             "sethi %%hi(boot_cpu_id), %0\n\t"
-                             "ldub [%0 + %%lo(boot_cpu_id)], %0\n\t" :
-                             "=&r" (cpuid));
-        return cpuid;
 }
-#else
-static inline int hard_smp_processor_id(void)
-{
-        int cpuid;
-        __asm__ __volatile__("mov %%o7, %%g1\n\t"
+extern int hard_smp_processor_id(void);
-                             "call ___f___hard_smp_processor_id\n\t"
-                             " nop\n\t"
-                             "mov %%g2, %0\n\t" : "=r"(cpuid) : : "g1", "g2");
-        return cpuid;
-}
-#endif
 #define raw_smp_processor_id()          (current_thread_info()->cpu)
diff --git a/arch/sparc/include/asm/smpprim.h b/arch/sparc/include/asm/smpprim.h
deleted file mode 100644
index eb849d862c64..000000000000
--- a/arch/sparc/include/asm/smpprim.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- *  smpprim.h:  SMP locking primitives on the Sparc
- *
- *  God knows we won't be actually using this code for some time
- *  but I thought I'd write it since I knew how.
- *
- *  Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
- */
-#ifndef __SPARC_SMPPRIM_H
-#define __SPARC_SMPPRIM_H
-/* Test and set the unsigned byte at ADDR to 1.  Returns the previous
- * value.  On the Sparc we use the ldstub instruction since it is
- * atomic.
- */
-static inline __volatile__ char test_and_set(void *addr)
-{
-        char state = 0;
-        __asm__ __volatile__("ldstub [%0], %1         ! test_and_set\n\t"
-                             "=r" (addr), "=r" (state) :
-                             "0" (addr), "1" (state) : "memory");
-        return state;
-}
-/* Initialize a spin-lock. */
-static inline __volatile__ smp_initlock(void *spinlock)
-{
-        /* Unset the lock. */
-        *((unsigned char *) spinlock) = 0;
-        return;
-}
-/* This routine spins until it acquires the lock at ADDR. */
-static inline __volatile__ smp_lock(void *addr)
-{
-        while(test_and_set(addr) == 0xff)
-                ;
-        /* We now have the lock */
-        return;
-}
-/* This routine releases the lock at ADDR. */
-static inline __volatile__ smp_unlock(void *addr)
-{
-        *((unsigned char *) addr) = 0;
-}
-#endif /* !(__SPARC_SMPPRIM_H) */
diff --git a/arch/sparc/include/asm/string_32.h b/arch/sparc/include/asm/string_32.h
index edf196ee4ef8..12f67857152e 100644
--- a/arch/sparc/include/asm/string_32.h
+++ b/arch/sparc/include/asm/string_32.h
@@ -61,68 +61,7 @@ extern int memcmp(const void *,const void *,__kernel_size_t);
 extern __kernel_size_t strlen(const char *);
 #define __HAVE_ARCH_STRNCMP
+extern int strncmp(const char *, const char *, __kernel_size_t);
-extern int __strncmp(const char *, const char *, __kernel_size_t);
-static inline int __constant_strncmp(const char *src, const char *dest, __kernel_size_t count)
-{
-        register int retval;
-        switch(count) {
-        case 0: return 0;
-        case 1: return (src[0] - dest[0]);
-        case 2: retval = (src[0] - dest[0]);
-                if(!retval && src[0])
-                  retval = (src[1] - dest[1]);
-                return retval;
-        case 3: retval = (src[0] - dest[0]);
-                if(!retval && src[0]) {
-                  retval = (src[1] - dest[1]);
-                  if(!retval && src[1])
-                    retval = (src[2] - dest[2]);
-                }
-                return retval;
-        case 4: retval = (src[0] - dest[0]);
-                if(!retval && src[0]) {
-                  retval = (src[1] - dest[1]);
-                  if(!retval && src[1]) {
-                    retval = (src[2] - dest[2]);
-                    if (!retval && src[2])
-                      retval = (src[3] - dest[3]);
-                  }
-                }
-                return retval;
-        case 5: retval = (src[0] - dest[0]);
-                if(!retval && src[0]) {
-                  retval = (src[1] - dest[1]);
-                  if(!retval && src[1]) {
-                    retval = (src[2] - dest[2]);
-                    if (!retval && src[2]) {
-                      retval = (src[3] - dest[3]);
-                      if (!retval && src[3])
-                        retval = (src[4] - dest[4]);
-                    }
-                  }
-                }
-                return retval;
-        default:
-                retval = (src[0] - dest[0]);
-                if(!retval && src[0]) {
-                  retval = (src[1] - dest[1]);
-                  if(!retval && src[1]) {
-                    retval = (src[2] - dest[2]);
-                    if(!retval && src[2])
-                      retval = __strncmp(src+3,dest+3,count-3);
-                  }
-                }
-                return retval;
-        }
-}
-#undef strncmp
-#define strncmp(__arg0, __arg1, __arg2) \
-(__builtin_constant_p(__arg2) ? \
- __constant_strncmp(__arg0, __arg1, __arg2) : \
- __strncmp(__arg0, __arg1, __arg2))
 #endif /* !EXPORT_SYMTAB_STROPS */
diff --git a/arch/sparc/include/asm/sysen.h b/arch/sparc/include/asm/sysen.h
deleted file mode 100644
index 6af34abde6e7..000000000000
--- a/arch/sparc/include/asm/sysen.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * sysen.h:  Bit fields within the "System Enable" register accessed via
- *           the ASI_CONTROL address space at address AC_SYSENABLE.
- *
- * Copyright (C) 1994 David S. Miller (davem@caip.rutgers.edu)
- */
-#ifndef _SPARC_SYSEN_H
-#define _SPARC_SYSEN_H
-#define SENABLE_DVMA   0x20   /* enable dvma transfers */
-#define SENABLE_CACHE  0x10   /* enable VAC cache */
-#define SENABLE_RESET  0x04   /* reset whole machine, danger Will Robinson */
-#endif /* _SPARC_SYSEN_H */
diff --git a/arch/sparc/include/asm/thread_info_32.h b/arch/sparc/include/asm/thread_info_32.h
index c2a1080cdd3b..21a38946541d 100644
--- a/arch/sparc/include/asm/thread_info_32.h
+++ b/arch/sparc/include/asm/thread_info_32.h
@@ -15,7 +15,6 @@
 #ifndef __ASSEMBLY__
-#include <asm/btfixup.h>
 #include <asm/ptrace.h>
 #include <asm/page.h>
@@ -80,13 +79,8 @@ register struct thread_info *current_thread_info_reg asm("g6");
 */
 #define THREAD_INFO_ORDER  1
-#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR
+struct thread_info * alloc_thread_info_node(struct task_struct *tsk, int node);
+void free_thread_info(struct thread_info *);
-BTFIXUPDEF_CALL(struct thread_info *, alloc_thread_info_node, int)
-#define alloc_thread_info_node(tsk, node) BTFIXUP_CALL(alloc_thread_info_node)(node)
-BTFIXUPDEF_CALL(void, free_thread_info, struct thread_info *)
-#define free_thread_info(ti) BTFIXUP_CALL(free_thread_info)(ti)
 #endif /* __ASSEMBLY__ */
diff --git a/arch/sparc/include/asm/thread_info_64.h b/arch/sparc/include/asm/thread_info_64.h
index 01d057fe6a3f..7f0981b09451 100644
--- a/arch/sparc/include/asm/thread_info_64.h
+++ b/arch/sparc/include/asm/thread_info_64.h
@@ -138,32 +138,11 @@ register struct thread_info *current_thread_info_reg asm("g6");
 /* thread information allocation */
 #if PAGE_SHIFT == 13
-#define __THREAD_INFO_ORDER     1
+#define THREAD_SIZE_ORDER       1
 #else /* PAGE_SHIFT == 13 */
-#define __THREAD_INFO_ORDER     0
+#define THREAD_SIZE_ORDER       0
 #endif /* PAGE_SHIFT == 13 */
-#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR
-#ifdef CONFIG_DEBUG_STACK_USAGE
-#define THREAD_FLAGS (GFP_KERNEL | __GFP_ZERO)
-#else
-#define THREAD_FLAGS (GFP_KERNEL)
-#endif
-#define alloc_thread_info_node(tsk, node)                               \
-({                                                                      \
-        struct page *page = alloc_pages_node(node, THREAD_FLAGS,        \
-                                             __THREAD_INFO_ORDER);      \
-        struct thread_info *ret;                                        \
-                                                                        \
-        ret = page ? page_address(page) : NULL;                         \
-        ret;                                                            \
-})
-#define free_thread_info(ti) \
-        free_pages((unsigned long)(ti),__THREAD_INFO_ORDER)
 #define __thread_flag_byte_ptr(ti)      \
        ((unsigned char *)(&((ti)->flags)))
 #define __cur_thread_flag_byte_ptr      __thread_flag_byte_ptr(current_thread_info())
diff --git a/arch/sparc/include/asm/timer_32.h b/arch/sparc/include/asm/timer_32.h
index 1a91e11dd104..72f40a546de3 100644
--- a/arch/sparc/include/asm/timer_32.h
+++ b/arch/sparc/include/asm/timer_32.h
@@ -8,14 +8,37 @@
 #ifndef _SPARC_TIMER_H
 #define _SPARC_TIMER_H
+#include <linux/clocksource.h>
+#include <linux/irqreturn.h>
+#include <asm-generic/percpu.h>
 #include <asm/cpu_type.h>  /* For SUN4M_NCPUS */
-#include <asm/btfixup.h>
+#define SBUS_CLOCK_RATE   2000000 /* 2MHz */
+#define TIMER_VALUE_SHIFT 9
+#define TIMER_VALUE_MASK  0x3fffff
+#define TIMER_LIMIT_BIT   (1 << 31)  /* Bit 31 in Counter-Timer register */
+/* The counter timer register has the value offset by 9 bits.
+ * From sun4m manual:
+ * When a counter reaches the value in the corresponding limit register,
+ * the Limit bit is set and the counter is set to 500 nS (i.e. 0x00000200).
+ *
+ * To compensate for this add one to the value.
+ */
+static inline unsigned int timer_value(unsigned int value)
+{
+        return (value + 1) << TIMER_VALUE_SHIFT;
+}
 extern __volatile__ unsigned int *master_l10_counter;
-/* FIXME: Make do_[gs]ettimeofday btfixup calls */
+extern irqreturn_t notrace timer_interrupt(int dummy, void *dev_id);
-struct timespec;
-BTFIXUPDEF_CALL(int, bus_do_settimeofday, struct timespec *tv)
+#ifdef CONFIG_SMP
-#define bus_do_settimeofday(tv) BTFIXUP_CALL(bus_do_settimeofday)(tv)
+DECLARE_PER_CPU(struct clock_event_device, sparc32_clockevent);
+extern void register_percpu_ce(int cpu);
+#endif
 #endif /* !(_SPARC_TIMER_H) */
diff --git a/arch/sparc/include/asm/timex_32.h b/arch/sparc/include/asm/timex_32.h
index a254750e4c03..b6ccdb0d6f7d 100644
--- a/arch/sparc/include/asm/timex_32.h
+++ b/arch/sparc/include/asm/timex_32.h
@@ -12,5 +12,4 @@
 typedef unsigned long cycles_t;
 #define get_cycles()    (0)
-extern u32 (*do_arch_gettimeoffset)(void);
 #endif
diff --git a/arch/sparc/include/asm/tlbflush_32.h b/arch/sparc/include/asm/tlbflush_32.h
index fe0a71abc9bb..a5c4142130f5 100644
--- a/arch/sparc/include/asm/tlbflush_32.h
+++ b/arch/sparc/include/asm/tlbflush_32.h
@@ -1,52 +1,16 @@
 #ifndef _SPARC_TLBFLUSH_H
 #define _SPARC_TLBFLUSH_H
-#include <linux/mm.h>
+#include <asm/cachetlb_32.h>
-// #include <asm/processor.h>
+#define flush_tlb_all() \
-/*
+        sparc32_cachetlb_ops->tlb_all()
- * TLB flushing:
+#define flush_tlb_mm(mm) \
- *
+        sparc32_cachetlb_ops->tlb_mm(mm)
- *  - flush_tlb() flushes the current mm struct TLBs    XXX Exists?
+#define flush_tlb_range(vma, start, end) \
- *  - flush_tlb_all() flushes all processes TLBs
+        sparc32_cachetlb_ops->tlb_range(vma, start, end)
- *  - flush_tlb_mm(mm) flushes the specified mm context TLB's
+#define flush_tlb_page(vma, addr) \
- *  - flush_tlb_page(vma, vmaddr) flushes one page
+        sparc32_cachetlb_ops->tlb_page(vma, addr)
- *  - flush_tlb_range(vma, start, end) flushes a range of pages
- *  - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
- */
-#ifdef CONFIG_SMP
-BTFIXUPDEF_CALL(void, local_flush_tlb_all, void)
-BTFIXUPDEF_CALL(void, local_flush_tlb_mm, struct mm_struct *)
-BTFIXUPDEF_CALL(void, local_flush_tlb_range, struct vm_area_struct *, unsigned long, unsigned long)
-BTFIXUPDEF_CALL(void, local_flush_tlb_page, struct vm_area_struct *, unsigned long)
-#define local_flush_tlb_all() BTFIXUP_CALL(local_flush_tlb_all)()
-#define local_flush_tlb_mm(mm) BTFIXUP_CALL(local_flush_tlb_mm)(mm)
-#define local_flush_tlb_range(vma,start,end) BTFIXUP_CALL(local_flush_tlb_range)(vma,start,end)
-#define local_flush_tlb_page(vma,addr) BTFIXUP_CALL(local_flush_tlb_page)(vma,addr)
-extern void smp_flush_tlb_all(void);
-extern void smp_flush_tlb_mm(struct mm_struct *mm);
-extern void smp_flush_tlb_range(struct vm_area_struct *vma,
-                                  unsigned long start,
-                                  unsigned long end);
-extern void smp_flush_tlb_page(struct vm_area_struct *mm, unsigned long page);
-#endif /* CONFIG_SMP */
-BTFIXUPDEF_CALL(void, flush_tlb_all, void)
-BTFIXUPDEF_CALL(void, flush_tlb_mm, struct mm_struct *)
-BTFIXUPDEF_CALL(void, flush_tlb_range, struct vm_area_struct *, unsigned long, unsigned long)
-BTFIXUPDEF_CALL(void, flush_tlb_page, struct vm_area_struct *, unsigned long)
-#define flush_tlb_all() BTFIXUP_CALL(flush_tlb_all)()
-#define flush_tlb_mm(mm) BTFIXUP_CALL(flush_tlb_mm)(mm)
-#define flush_tlb_range(vma,start,end) BTFIXUP_CALL(flush_tlb_range)(vma,start,end)
-#define flush_tlb_page(vma,addr) BTFIXUP_CALL(flush_tlb_page)(vma,addr)
-// #define flush_tlb() flush_tlb_mm(current->active_mm) /* XXX Sure? */
 /*
 * This is a kludge, until I know better. --zaitcev XXX
diff --git a/arch/sparc/include/asm/topology_64.h b/arch/sparc/include/asm/topology_64.h
index 8b9c556d630b..1754390a426f 100644
--- a/arch/sparc/include/asm/topology_64.h
+++ b/arch/sparc/include/asm/topology_64.h
@@ -31,25 +31,6 @@ static inline int pcibus_to_node(struct pci_bus *pbus)
         cpu_all_mask : \
         cpumask_of_node(pcibus_to_node(bus)))
-#define SD_NODE_INIT (struct sched_domain) {            \
-        .min_interval           = 8,                    \
-        .max_interval           = 32,                   \
-        .busy_factor            = 32,                   \
-        .imbalance_pct          = 125,                  \
-        .cache_nice_tries       = 2,                    \
-        .busy_idx               = 3,                    \
-        .idle_idx               = 2,                    \
-        .newidle_idx            = 0,                    \
-        .wake_idx               = 0,                    \
-        .forkexec_idx           = 0,                    \
-        .flags                  = SD_LOAD_BALANCE       \
-                                | SD_BALANCE_FORK       \
-                                | SD_BALANCE_EXEC       \
-                                | SD_SERIALIZE,         \
-        .last_balance           = jiffies,              \
-        .balance_interval       = 1,                    \
-}
 #else /* CONFIG_NUMA */
 #include <asm-generic/topology.h>
diff --git a/arch/sparc/include/asm/uaccess_32.h b/arch/sparc/include/asm/uaccess_32.h
index 8303ac481034..d50c310f5d38 100644
--- a/arch/sparc/include/asm/uaccess_32.h
+++ b/arch/sparc/include/asm/uaccess_32.h
@@ -12,7 +12,6 @@
 #include <linux/sched.h>
 #include <linux/string.h>
 #include <linux/errno.h>
-#include <asm/vac-ops.h>
 #endif
 #ifndef __ASSEMBLY__
diff --git a/arch/sparc/include/asm/vac-ops.h b/arch/sparc/include/asm/vac-ops.h
deleted file mode 100644
index a63e88ef0426..000000000000
--- a/arch/sparc/include/asm/vac-ops.h
+++ /dev/null
@@ -1,127 +0,0 @@
-#ifndef _SPARC_VAC_OPS_H
-#define _SPARC_VAC_OPS_H
-/* vac-ops.h: Inline assembly routines to do operations on the Sparc
- *            VAC (virtual address cache) for the sun4c.
- *
- * Copyright (C) 1994, David S. Miller (davem@caip.rutgers.edu)
- */
-#include <asm/sysen.h>
-#include <asm/contregs.h>
-#include <asm/asi.h>
-/* The SUN4C models have a virtually addressed write-through
- * cache.
- *
- * The cache tags are directly accessible through an ASI and
- * each have the form:
- *
- * ------------------------------------------------------------
- * | MBZ | CONTEXT | WRITE | PRIV | VALID | MBZ | TagID | MBZ |
- * ------------------------------------------------------------
- *  31 25  24   22     21     20     19    18 16  15   2  1  0
- *
- * MBZ: These bits are either unused and/or reserved and should
- *      be written as zeroes.
- *
- * CONTEXT: Records the context to which this cache line belongs.
- *
- * WRITE: A copy of the writable bit from the mmu pte access bits.
- *
- * PRIV: A copy of the privileged bit from the pte access bits.
- *
- * VALID: If set, this line is valid, else invalid.
- *
- * TagID: Fourteen bits of tag ID.
- *
- * Every virtual address is seen by the cache like this:
- *
- * ----------------------------------------
- * |  RESV  | TagID | LINE | BYTE-in-LINE |
- * ----------------------------------------
- *  31    30 29   16 15   4 3            0
- *
- * RESV: Unused/reserved.
- *
- * TagID: Used to match the Tag-ID in that vac tags.
- *
- * LINE: Which line within the cache
- *
- * BYTE-in-LINE: Which byte within the cache line.
- */
-/* Sun4c VAC Tags */
-#define S4CVACTAG_CID      0x01c00000
-#define S4CVACTAG_W        0x00200000
-#define S4CVACTAG_P        0x00100000
-#define S4CVACTAG_V        0x00080000
-#define S4CVACTAG_TID      0x0000fffc
-/* Sun4c VAC Virtual Address */
-/* These aren't used, why bother? (Anton) */
-#if 0
-#define S4CVACVA_TID       0x3fff0000
-#define S4CVACVA_LINE      0x0000fff0
-#define S4CVACVA_BIL       0x0000000f
-#endif
-/* The indexing of cache lines creates a problem.  Because the line
- * field of a virtual address extends past the page offset within
- * the virtual address it is possible to have what are called
- * 'bad aliases' which will create inconsistencies.  So we must make
- * sure that within a context that if a physical page is mapped
- * more than once, that 'extra' line bits are the same.  If this is
- * not the case, and thus is a 'bad alias' we must turn off the
- * cacheable bit in the pte's of all such pages.
- */
-#define S4CVAC_BADBITS    0x0000f000
-/* The following is true if vaddr1 and vaddr2 would cause
- * a 'bad alias'.
- */
-#define S4CVAC_BADALIAS(vaddr1, vaddr2) \
-        ((((unsigned long) (vaddr1)) ^ ((unsigned long) (vaddr2))) & \
-         (S4CVAC_BADBITS))
-/* The following structure describes the characteristics of a sun4c
- * VAC as probed from the prom during boot time.
- */
-struct sun4c_vac_props {
-        unsigned int num_bytes;     /* Size of the cache */
-        unsigned int do_hwflushes;  /* Hardware flushing available? */
-        unsigned int linesize;      /* Size of each line in bytes */
-        unsigned int log2lsize;     /* log2(linesize) */
-        unsigned int on;            /* VAC is enabled */
-};
-extern struct sun4c_vac_props sun4c_vacinfo;
-/* sun4c_enable_vac() enables the sun4c virtual address cache. */
-static inline void sun4c_enable_vac(void)
-{
-        __asm__ __volatile__("lduba [%0] %1, %%g1\n\t"
-                             "or    %%g1, %2, %%g1\n\t"
-                             "stba  %%g1, [%0] %1\n\t"
-                             : /* no outputs */
-                             : "r" ((unsigned int) AC_SENABLE),
-                             "i" (ASI_CONTROL), "i" (SENABLE_CACHE)
-                             : "g1", "memory");
-        sun4c_vacinfo.on = 1;
-}
-/* sun4c_disable_vac() disables the virtual address cache. */
-static inline void sun4c_disable_vac(void)
-{
-        __asm__ __volatile__("lduba [%0] %1, %%g1\n\t"
-                             "andn  %%g1, %2, %%g1\n\t"
-                             "stba  %%g1, [%0] %1\n\t"
-                             : /* no outputs */
-                             : "r" ((unsigned int) AC_SENABLE),
-                             "i" (ASI_CONTROL), "i" (SENABLE_CACHE)
-                             : "g1", "memory");
-        sun4c_vacinfo.on = 0;
-}
-#endif /* !(_SPARC_VAC_OPS_H) */
diff --git a/arch/sparc/include/asm/vaddrs.h b/arch/sparc/include/asm/vaddrs.h
index 541e13755cec..da6535d88a72 100644
--- a/arch/sparc/include/asm/vaddrs.h
+++ b/arch/sparc/include/asm/vaddrs.h
@@ -34,22 +34,6 @@
 #define IOBASE_VADDR            0xfe000000
 #define IOBASE_END              0xfe600000
-/*
- * On the sun4/4c we need a place
- * to reliably map locked down kernel data.  This includes the
- * task_struct and kernel stack pages of each process plus the
- * scsi buffers during dvma IO transfers, also the floppy buffers
- * during pseudo dma which runs with traps off (no faults allowed).
- * Some quick calculations yield:
- *       NR_TASKS <512> * (3 * PAGE_SIZE) == 0x600000
- * Subtract this from 0xc00000 and you get 0x927C0 of vm left
- * over to map SCSI dvma + floppy pseudo-dma buffers.  So be
- * careful if you change NR_TASKS or else there won't be enough
- * room for it all.
- */
-#define SUN4C_LOCK_VADDR        0xff000000
-#define SUN4C_LOCK_END          0xffc00000
 #define KADB_DEBUGGER_BEGVM     0xffc00000 /* Where kern debugger is in virt-mem */
 #define KADB_DEBUGGER_ENDVM     0xffd00000
 #define DEBUG_FIRSTVADDR        KADB_DEBUGGER_BEGVM
diff --git a/arch/sparc/include/asm/winmacro.h b/arch/sparc/include/asm/winmacro.h
index a9be04b0d049..9b7b21764cde 100644
--- a/arch/sparc/include/asm/winmacro.h
+++ b/arch/sparc/include/asm/winmacro.h
@@ -103,37 +103,24 @@
        st       %scratch, [%cur_reg + TI_W_SAVED];
 #ifdef CONFIG_SMP
-/* Results of LOAD_CURRENT() after BTFIXUP for SUN4M, SUN4D & LEON (comments) */
+#define LOAD_CURRENT(dest_reg, idreg)                   \
-#define LOAD_CURRENT4M(dest_reg, idreg) \
+661:    rd      %tbr, %idreg;                           \
-        rd       %tbr, %idreg; \
+        srl     %idreg, 10, %idreg;                     \
-        sethi    %hi(current_set), %dest_reg; \
+        and     %idreg, 0xc, %idreg;                    \
-        srl      %idreg, 10, %idreg; \
+        .section        .cpuid_patch, "ax";             \
-        or       %dest_reg, %lo(current_set), %dest_reg; \
+        /* Instruction location. */                     \
-        and      %idreg, 0xc, %idreg; \
+        .word           661b;                           \
-        ld       [%idreg + %dest_reg], %dest_reg;
+        /* SUN4D implementation. */                     \
+        lda      [%g0] ASI_M_VIKING_TMP1, %idreg;       \
-#define LOAD_CURRENT4D(dest_reg, idreg) \
+        sll      %idreg, 2, %idreg;                     \
-        lda      [%g0] ASI_M_VIKING_TMP1, %idreg; \
+        nop;                                            \
-        sethi   %hi(C_LABEL(current_set)), %dest_reg; \
+        /* LEON implementation. */                      \
-        sll     %idreg, 2, %idreg; \
+        rd      %asr17, %idreg;                         \
-        or      %dest_reg, %lo(C_LABEL(current_set)), %dest_reg; \
+        srl     %idreg, 0x1c, %idreg;                   \
-        ld      [%idreg + %dest_reg], %dest_reg;
+        sll     %idreg, 0x02, %idreg;                   \
+        .previous;                                      \
-#define LOAD_CURRENT_LEON(dest_reg, idreg)                      \
+        sethi    %hi(current_set), %dest_reg;           \
-        rd      %asr17, %idreg;                                 \
+        or       %dest_reg, %lo(current_set), %dest_reg;\
-        sethi   %hi(current_set), %dest_reg;                    \
-        srl     %idreg, 0x1c, %idreg;                           \
-        or      %dest_reg, %lo(current_set), %dest_reg;         \
-        sll     %idreg, 0x2, %idreg;                            \
-        ld      [%idreg + %dest_reg], %dest_reg;
-/* Blackbox - take care with this... - check smp4m and smp4d before changing this. */
-#define LOAD_CURRENT(dest_reg, idreg)                                   \
-        sethi    %hi(___b_load_current), %idreg;                        \
-        sethi    %hi(current_set), %dest_reg;                   \
-        sethi    %hi(boot_cpu_id4), %idreg;                     \
-        or       %dest_reg, %lo(current_set), %dest_reg;        \
-        ldub     [%idreg + %lo(boot_cpu_id4)], %idreg;          \
        ld       [%idreg + %dest_reg], %dest_reg;
 #else
 #define LOAD_CURRENT(dest_reg, idreg) \
diff --git a/arch/sparc/kernel/Makefile b/arch/sparc/kernel/Makefile
index cb85458f89d2..72308f9b0096 100644
--- a/arch/sparc/kernel/Makefile
+++ b/arch/sparc/kernel/Makefile
@@ -6,7 +6,6 @@ asflags-y := -ansi
 ccflags-y := -Werror
 extra-y     := head_$(BITS).o
-extra-y     += init_task.o
 # Undefine sparc when processing vmlinux.lds - it is used
 # And teach CPP we are doing $(BITS) builds (for this case)
@@ -28,7 +27,7 @@ obj-y                   += traps_$(BITS).o
 # IRQ
 obj-y                   += irq_$(BITS).o
-obj-$(CONFIG_SPARC32)   += sun4m_irq.o sun4c_irq.o sun4d_irq.o
+obj-$(CONFIG_SPARC32)   += sun4m_irq.o sun4d_irq.o
 obj-y                   += process_$(BITS).o
 obj-y                   += signal_$(BITS).o
@@ -46,7 +45,6 @@ obj-$(CONFIG_SPARC32)   += tadpole.o
 obj-y                   += ptrace_$(BITS).o
 obj-y                   += unaligned_$(BITS).o
 obj-y                   += una_asm_$(BITS).o
-obj-$(CONFIG_SPARC32)   += muldiv.o
 obj-y                   += prom_common.o
 obj-y                   += prom_$(BITS).o
 obj-y                   += of_device_common.o
diff --git a/arch/sparc/kernel/auxio_32.c b/arch/sparc/kernel/auxio_32.c
index 56d0f52c3e62..e20cc55fb768 100644
--- a/arch/sparc/kernel/auxio_32.c
+++ b/arch/sparc/kernel/auxio_32.c
@@ -32,7 +32,6 @@ void __init auxio_probe(void)
        switch (sparc_cpu_model) {
        case sparc_leon:
        case sun4d:
-        case sun4:
                return;
        default:
                break;
@@ -65,9 +64,8 @@ void __init auxio_probe(void)
        r.start = auxregs[0].phys_addr;
        r.end = auxregs[0].phys_addr + auxregs[0].reg_size - 1;
        auxio_register = of_ioremap(&r, 0, auxregs[0].reg_size, "auxio");
-        /* Fix the address on sun4m and sun4c. */
+        /* Fix the address on sun4m. */
-        if((((unsigned long) auxregs[0].phys_addr) & 3) == 3 ||
+        if ((((unsigned long) auxregs[0].phys_addr) & 3) == 3)
-           sparc_cpu_model == sun4c)
                auxio_register += (3 - ((unsigned long)auxio_register & 3));
        set_auxio(AUXIO_LED, 0);
@@ -86,12 +84,7 @@ void set_auxio(unsigned char bits_on, unsigned char bits_off)
        unsigned char regval;
        unsigned long flags;
        spin_lock_irqsave(&auxio_lock, flags);
-        switch(sparc_cpu_model) {
+        switch (sparc_cpu_model) {
-        case sun4c:
-                regval = sbus_readb(auxio_register);
-                sbus_writeb(((regval | bits_on) & ~bits_off) | AUXIO_ORMEIN,
-                        auxio_register);
-                break;
        case sun4m:
                if(!auxio_register)
                        break;     /* VME chassis sun4m, no auxio. */
diff --git a/arch/sparc/kernel/central.c b/arch/sparc/kernel/central.c
index 38d48a59879c..9708851a8b9f 100644
--- a/arch/sparc/kernel/central.c
+++ b/arch/sparc/kernel/central.c
@@ -269,4 +269,4 @@ static int __init sunfire_init(void)
        return 0;
 }
-subsys_initcall(sunfire_init);
+fs_initcall(sunfire_init);
diff --git a/arch/sparc/kernel/devices.c b/arch/sparc/kernel/devices.c
index 6b2f56a6f8af..3d465e87f7e2 100644
--- a/arch/sparc/kernel/devices.c
+++ b/arch/sparc/kernel/devices.c
@@ -21,7 +21,6 @@
 #include <asm/cpu_type.h>
 extern void clock_stop_probe(void); /* tadpole.c */
-extern void sun4c_probe_memerr_reg(void);
 static char *cpu_mid_prop(void)
 {
@@ -139,7 +138,4 @@ void __init device_scan(void)
                auxio_power_probe();
        }
        clock_stop_probe();
-        if (ARCH_SUN4C)
-                sun4c_probe_memerr_reg();
 }
diff --git a/arch/sparc/kernel/ds.c b/arch/sparc/kernel/ds.c
index fea13c7b1aee..f09257c86107 100644
--- a/arch/sparc/kernel/ds.c
+++ b/arch/sparc/kernel/ds.c
@@ -868,7 +868,7 @@ void ldom_power_off(void)
 static void ds_conn_reset(struct ds_info *dp)
 {
-        printk(KERN_ERR "ds-%llu: ds_conn_reset() from %p\n",
+        printk(KERN_ERR "ds-%llu: ds_conn_reset() from %pf\n",
               dp->id, __builtin_return_address(0));
 }
@@ -1264,4 +1264,4 @@ static int __init ds_init(void)
        return vio_register_driver(&ds_driver);
 }
-subsys_initcall(ds_init);
+fs_initcall(ds_init);
diff --git a/arch/sparc/kernel/entry.S b/arch/sparc/kernel/entry.S
index f445e98463e6..2dbe1806e530 100644
--- a/arch/sparc/kernel/entry.S
+++ b/arch/sparc/kernel/entry.S
@@ -7,6 +7,7 @@
 * Copyright (C) 1997 Anton Blanchard (anton@progsoc.uts.edu.au)
 */
+#include <linux/linkage.h>
 #include <linux/errno.h>
 #include <asm/head.h>
@@ -17,10 +18,8 @@
 #include <asm/asm-offsets.h>
 #include <asm/psr.h>
 #include <asm/vaddrs.h>
-#include <asm/memreg.h>
 #include <asm/page.h>
 #include <asm/pgtable.h>
-#include <asm/pgtsun4c.h>
 #include <asm/winmacro.h>
 #include <asm/signal.h>
 #include <asm/obio.h>
@@ -125,22 +124,11 @@ floppy_tdone:
        set     auxio_register, %l7
        ld      [%l7], %l7
-        set     sparc_cpu_model, %l5
+        ldub    [%l7], %l5
-        ld      [%l5], %l5
-        subcc   %l5, 1, %g0             /* enum { sun4c = 1 }; */
-        be      1f
-         ldub   [%l7], %l5
        or      %l5, 0xc2, %l5
        stb     %l5, [%l7]
        andn    %l5, 0x02, %l5
-        b       2f
-         nop
-1:
-        or      %l5, 0xf4, %l5
-        stb     %l5, [%l7]
-        andn    %l5, 0x04, %l5
 2:
        /* Kill some time so the bits set */
@@ -266,6 +254,11 @@ smp4m_ticker:
        WRITE_PAUSE
        RESTORE_ALL
+#define GET_PROCESSOR4M_ID(reg) \
+        rd      %tbr, %reg;     \
+        srl     %reg, 12, %reg; \
+        and     %reg, 3, %reg;
        /* Here is where we check for possible SMP IPI passed to us
         * on some level other than 15 which is the NMI and only used
         * for cross calls.  That has a separate entry point below.
@@ -328,7 +321,7 @@ linux_trap_ipi15_sun4m:
        ld      [%o5 + %o0], %o5
        ld      [%o5 + 0x00], %o3       ! sun4m_irq_percpu[cpu]->pending
        andcc   %o3, %o2, %g0
-        be      1f                      ! Must be an NMI async memory error
+        be      sun4m_nmi_error         ! Must be an NMI async memory error
         st     %o2, [%o5 + 0x04]       ! sun4m_irq_percpu[cpu]->clear=0x80000000
        WRITE_PAUSE
        ld      [%o5 + 0x00], %g0       ! sun4m_irq_percpu[cpu]->pending
@@ -342,27 +335,6 @@ linux_trap_ipi15_sun4m:
         nop
        b       ret_trap_lockless_ipi
         clr    %l6
-1:
-        /* NMI async memory error handling. */
-        sethi   %hi(0x80000000), %l4
-        sethi   %hi(sun4m_irq_global), %o5
-        ld      [%o5 + %lo(sun4m_irq_global)], %l5
-        st      %l4, [%l5 + 0x0c]       ! sun4m_irq_global->mask_set=0x80000000
-        WRITE_PAUSE
-        ld      [%l5 + 0x00], %g0       ! sun4m_irq_global->pending
-        WRITE_PAUSE
-        or      %l0, PSR_PIL, %l4
-        wr      %l4, 0x0, %psr
-        WRITE_PAUSE
-        wr      %l4, PSR_ET, %psr
-        WRITE_PAUSE
-        call    sun4m_nmi
-         nop
-        st      %l4, [%l5 + 0x08]       ! sun4m_irq_global->mask_clear=0x80000000
-        WRITE_PAUSE
-        ld      [%l5 + 0x00], %g0       ! sun4m_irq_global->pending
-        WRITE_PAUSE
-        RESTORE_ALL
        .globl  smp4d_ticker
        /* SMP per-cpu ticker interrupts are handled specially. */
@@ -760,326 +732,37 @@ setcc_trap_handler:
        jmp     %l2             ! advance over trap instruction
        rett    %l2 + 0x4       ! like this...
-        .align  4
+sun4m_nmi_error:
-        .globl  linux_trap_nmi_sun4c
+        /* NMI async memory error handling. */
-linux_trap_nmi_sun4c:
+        sethi   %hi(0x80000000), %l4
-        SAVE_ALL
+        sethi   %hi(sun4m_irq_global), %o5
+        ld      [%o5 + %lo(sun4m_irq_global)], %l5
-        /* Ugh, we need to clear the IRQ line.  This is now
+        st      %l4, [%l5 + 0x0c]       ! sun4m_irq_global->mask_set=0x80000000
-         * a very sun4c specific trap handler...
-         */
-        sethi   %hi(interrupt_enable), %l5
-        ld      [%l5 + %lo(interrupt_enable)], %l5
-        ldub    [%l5], %l6
-        andn    %l6, INTS_ENAB, %l6
-        stb     %l6, [%l5]
-        /* Now it is safe to re-enable traps without recursion. */
-        or      %l0, PSR_PIL, %l0
-        wr      %l0, PSR_ET, %psr
        WRITE_PAUSE
+        ld      [%l5 + 0x00], %g0       ! sun4m_irq_global->pending
-        /* Now call the c-code with the pt_regs frame ptr and the
-         * memory error registers as arguments.  The ordering chosen
-         * here is due to unlatching semantics.
-         */
-        sethi   %hi(AC_SYNC_ERR), %o0
-        add     %o0, 0x4, %o0
-        lda     [%o0] ASI_CONTROL, %o2  ! sync vaddr
-        sub     %o0, 0x4, %o0
-        lda     [%o0] ASI_CONTROL, %o1  ! sync error
-        add     %o0, 0xc, %o0
-        lda     [%o0] ASI_CONTROL, %o4  ! async vaddr
-        sub     %o0, 0x4, %o0
-        lda     [%o0] ASI_CONTROL, %o3  ! async error
-        call    sparc_lvl15_nmi
-         add    %sp, STACKFRAME_SZ, %o0
-        RESTORE_ALL
-        .align  4
-        .globl  invalid_segment_patch1_ff
-        .globl  invalid_segment_patch2_ff
-invalid_segment_patch1_ff:      cmp     %l4, 0xff
-invalid_segment_patch2_ff:      mov     0xff, %l3
-        .align  4
-        .globl  invalid_segment_patch1_1ff
-        .globl  invalid_segment_patch2_1ff
-invalid_segment_patch1_1ff:     cmp     %l4, 0x1ff
-invalid_segment_patch2_1ff:     mov     0x1ff, %l3
-        .align  4
-        .globl  num_context_patch1_16, num_context_patch2_16
-num_context_patch1_16:          mov     0x10, %l7
-num_context_patch2_16:          mov     0x10, %l7
-        .align  4
-        .globl  vac_linesize_patch_32
-vac_linesize_patch_32:          subcc   %l7, 32, %l7
-        .align  4
-        .globl  vac_hwflush_patch1_on, vac_hwflush_patch2_on
-/*
- * Ugly, but we can't use hardware flushing on the sun4 and we'd require
- * two instructions (Anton)
- */
-vac_hwflush_patch1_on:          addcc   %l7, -PAGE_SIZE, %l7
-vac_hwflush_patch2_on:          sta     %g0, [%l3 + %l7] ASI_HWFLUSHSEG
-        .globl  invalid_segment_patch1, invalid_segment_patch2
-        .globl  num_context_patch1
-        .globl  vac_linesize_patch, vac_hwflush_patch1
-        .globl  vac_hwflush_patch2
-        .align  4
-        .globl  sun4c_fault
-! %l0 = %psr
-! %l1 = %pc
-! %l2 = %npc
-! %l3 = %wim
-! %l7 = 1 for textfault
-! We want error in %l5, vaddr in %l6
-sun4c_fault:
-        sethi   %hi(AC_SYNC_ERR), %l4
-        add     %l4, 0x4, %l6                   ! AC_SYNC_VA in %l6
-        lda     [%l6] ASI_CONTROL, %l5          ! Address
-        lda     [%l4] ASI_CONTROL, %l6          ! Error, retained for a bit
-        andn    %l5, 0xfff, %l5                 ! Encode all info into l7
-        srl     %l6, 14, %l4
-        and     %l4, 2, %l4
-        or      %l5, %l4, %l4
-        or      %l4, %l7, %l7                   ! l7 = [addr,write,txtfault]
-        andcc   %l0, PSR_PS, %g0
-        be      sun4c_fault_fromuser
-         andcc  %l7, 1, %g0                     ! Text fault?
-        be      1f
-         sethi  %hi(KERNBASE), %l4
-        mov     %l1, %l5                        ! PC
-1:
-        cmp     %l5, %l4
-        blu     sun4c_fault_fromuser
-         sethi  %hi(~((1 << SUN4C_REAL_PGDIR_SHIFT) - 1)), %l4
-        /* If the kernel references a bum kernel pointer, or a pte which
-         * points to a non existent page in ram, we will run this code
-         * _forever_ and lock up the machine!!!!! So we must check for
-         * this condition, the AC_SYNC_ERR bits are what we must examine.
-         * Also a parity error would make this happen as well.  So we just
-         * check that we are in fact servicing a tlb miss and not some
-         * other type of fault for the kernel.
-         */
-        andcc   %l6, 0x80, %g0
-        be      sun4c_fault_fromuser
-         and    %l5, %l4, %l5
-        /* Test for NULL pte_t * in vmalloc area. */
-        sethi   %hi(VMALLOC_START), %l4
-        cmp     %l5, %l4
-        blu,a   invalid_segment_patch1
-         lduXa  [%l5] ASI_SEGMAP, %l4
-        sethi   %hi(swapper_pg_dir), %l4
-        srl     %l5, SUN4C_PGDIR_SHIFT, %l6
-        or      %l4, %lo(swapper_pg_dir), %l4
-        sll     %l6, 2, %l6
-        ld      [%l4 + %l6], %l4
-        andcc   %l4, PAGE_MASK, %g0
-        be      sun4c_fault_fromuser
-         lduXa  [%l5] ASI_SEGMAP, %l4
-invalid_segment_patch1:
-        cmp     %l4, 0x7f
-        bne     1f
-         sethi  %hi(sun4c_kfree_ring), %l4
-        or      %l4, %lo(sun4c_kfree_ring), %l4
-        ld      [%l4 + 0x18], %l3
-        deccc   %l3                     ! do we have a free entry?
-        bcs,a   2f                      ! no, unmap one.
-         sethi  %hi(sun4c_kernel_ring), %l4
-        st      %l3, [%l4 + 0x18]       ! sun4c_kfree_ring.num_entries--
-        ld      [%l4 + 0x00], %l6       ! entry = sun4c_kfree_ring.ringhd.next
-        st      %l5, [%l6 + 0x08]       ! entry->vaddr = address
-        ld      [%l6 + 0x00], %l3       ! next = entry->next
-        ld      [%l6 + 0x04], %l7       ! entry->prev
-        st      %l7, [%l3 + 0x04]       ! next->prev = entry->prev
-        st      %l3, [%l7 + 0x00]       ! entry->prev->next = next
-        sethi   %hi(sun4c_kernel_ring), %l4
-        or      %l4, %lo(sun4c_kernel_ring), %l4
-                                        ! head = &sun4c_kernel_ring.ringhd
-        ld      [%l4 + 0x00], %l7       ! head->next
-        st      %l4, [%l6 + 0x04]       ! entry->prev = head
-        st      %l7, [%l6 + 0x00]       ! entry->next = head->next
-        st      %l6, [%l7 + 0x04]       ! head->next->prev = entry
-        st      %l6, [%l4 + 0x00]       ! head->next = entry
-        ld      [%l4 + 0x18], %l3
-        inc     %l3                     ! sun4c_kernel_ring.num_entries++
-        st      %l3, [%l4 + 0x18]
-        b       4f
-         ld     [%l6 + 0x08], %l5
-2:
-        or      %l4, %lo(sun4c_kernel_ring), %l4
-                                        ! head = &sun4c_kernel_ring.ringhd
-        ld      [%l4 + 0x04], %l6       ! entry = head->prev
-        ld      [%l6 + 0x08], %l3       ! tmp = entry->vaddr
-        ! Flush segment from the cache.
-        sethi   %hi((64 * 1024)), %l7
-9:
-vac_hwflush_patch1:
-vac_linesize_patch:
-        subcc   %l7, 16, %l7
-        bne     9b
-vac_hwflush_patch2:
-         sta    %g0, [%l3 + %l7] ASI_FLUSHSEG
-        st      %l5, [%l6 + 0x08]       ! entry->vaddr = address
-        ld      [%l6 + 0x00], %l5       ! next = entry->next
-        ld      [%l6 + 0x04], %l7       ! entry->prev
-        st      %l7, [%l5 + 0x04]       ! next->prev = entry->prev
-        st      %l5, [%l7 + 0x00]       ! entry->prev->next = next
-        st      %l4, [%l6 + 0x04]       ! entry->prev = head
-        ld      [%l4 + 0x00], %l7       ! head->next
-        st      %l7, [%l6 + 0x00]       ! entry->next = head->next
-        st      %l6, [%l7 + 0x04]       ! head->next->prev = entry
-        st      %l6, [%l4 + 0x00]       ! head->next = entry
-        mov     %l3, %l5                ! address = tmp
-4:
-num_context_patch1:
-        mov     0x08, %l7
-        ld      [%l6 + 0x08], %l4
-        ldub    [%l6 + 0x0c], %l3
-        or      %l4, %l3, %l4           ! encode new vaddr/pseg into l4
-        sethi   %hi(AC_CONTEXT), %l3
-        lduba   [%l3] ASI_CONTROL, %l6
-        /* Invalidate old mapping, instantiate new mapping,
-         * for each context.  Registers l6/l7 are live across
-         * this loop.
-         */
-3:      deccc   %l7
-        sethi   %hi(AC_CONTEXT), %l3
-        stba    %l7, [%l3] ASI_CONTROL
-invalid_segment_patch2:
-        mov     0x7f, %l3
-        stXa    %l3, [%l5] ASI_SEGMAP
-        andn    %l4, 0x1ff, %l3
-        bne     3b
-         stXa   %l4, [%l3] ASI_SEGMAP
-        sethi   %hi(AC_CONTEXT), %l3
-        stba    %l6, [%l3] ASI_CONTROL
-        andn    %l4, 0x1ff, %l5
-1:
-        sethi   %hi(VMALLOC_START), %l4
-        cmp     %l5, %l4
-        bgeu    1f
-         mov    1 << (SUN4C_REAL_PGDIR_SHIFT - PAGE_SHIFT), %l7
-        sethi   %hi(KERNBASE), %l6
-        sub     %l5, %l6, %l4
-        srl     %l4, PAGE_SHIFT, %l4
-        sethi   %hi((SUN4C_PAGE_KERNEL & 0xf4000000)), %l3
-        or      %l3, %l4, %l3
-        sethi   %hi(PAGE_SIZE), %l4
-2:
-        sta     %l3, [%l5] ASI_PTE
-        deccc   %l7
-        inc     %l3
-        bne     2b
-         add    %l5, %l4, %l5
-        b       7f
-         sethi  %hi(sun4c_kernel_faults), %l4
-1:
-        srl     %l5, SUN4C_PGDIR_SHIFT, %l3
-        sethi   %hi(swapper_pg_dir), %l4
-        or      %l4, %lo(swapper_pg_dir), %l4
-        sll     %l3, 2, %l3
-        ld      [%l4 + %l3], %l4
-        and     %l4, PAGE_MASK, %l4
-        srl     %l5, (PAGE_SHIFT - 2), %l6
-        and     %l6, ((SUN4C_PTRS_PER_PTE - 1) << 2), %l6
-        add     %l6, %l4, %l6
-        sethi   %hi(PAGE_SIZE), %l4
-2:
-        ld      [%l6], %l3
-        deccc   %l7
-        sta     %l3, [%l5] ASI_PTE
-        add     %l6, 0x4, %l6
-        bne     2b
-         add    %l5, %l4, %l5
-        sethi   %hi(sun4c_kernel_faults), %l4
-7:
-        ld      [%l4 + %lo(sun4c_kernel_faults)], %l3
-        inc     %l3
-        st      %l3, [%l4 + %lo(sun4c_kernel_faults)]
-        /* Restore condition codes */
-        wr      %l0, 0x0, %psr
        WRITE_PAUSE
-        jmp     %l1
+        or      %l0, PSR_PIL, %l4
-         rett   %l2
+        wr      %l4, 0x0, %psr
+        WRITE_PAUSE
-sun4c_fault_fromuser:
+        wr      %l4, PSR_ET, %psr
-        SAVE_ALL
+        WRITE_PAUSE
+        call    sun4m_nmi
         nop
-        
+        st      %l4, [%l5 + 0x08]       ! sun4m_irq_global->mask_clear=0x80000000
-        mov     %l7, %o1                ! Decode the info from %l7
-        mov     %l7, %o2
-        and     %o1, 1, %o1             ! arg2 = text_faultp
-        mov     %l7, %o3
-        and     %o2, 2, %o2             ! arg3 = writep
-        andn    %o3, 0xfff, %o3         ! arg4 = faulting address
-        wr      %l0, PSR_ET, %psr
        WRITE_PAUSE
+        ld      [%l5 + 0x00], %g0       ! sun4m_irq_global->pending
+        WRITE_PAUSE
+        RESTORE_ALL
-        call    do_sun4c_fault
+#ifndef CONFIG_SMP
-         add    %sp, STACKFRAME_SZ, %o0 ! arg1 = pt_regs ptr
+        .align  4
+        .globl  linux_trap_ipi15_sun4m
+linux_trap_ipi15_sun4m:
+        SAVE_ALL
-        RESTORE_ALL
+        ba      sun4m_nmi_error
+         nop
+#endif /* CONFIG_SMP */
        .align  4
        .globl  srmmu_fault
@@ -1483,11 +1166,13 @@ fpload:
        .globl  __ndelay
 __ndelay:
        save    %sp, -STACKFRAME_SZ, %sp
-        mov     %i0, %o0
+        mov     %i0, %o0                ! round multiplier up so large ns ok
-        call    .umul                   ! round multiplier up so large ns ok
+        mov     0x1ae, %o1              ! 2**32 / (1 000 000 000 / HZ)
-         mov    0x1ae, %o1              ! 2**32 / (1 000 000 000 / HZ)
+        umul    %o0, %o1, %o0
-        call    .umul
+        rd      %y, %o1
-         mov    %i1, %o1                ! udelay_val
+        mov     %i1, %o1                ! udelay_val
+        umul    %o0, %o1, %o0
+        rd      %y, %o1
        ba      delay_continue
         mov    %o1, %o0                ! >>32 later for better resolution
@@ -1496,18 +1181,21 @@ __udelay:
        save    %sp, -STACKFRAME_SZ, %sp
        mov     %i0, %o0
        sethi   %hi(0x10c7), %o1        ! round multiplier up so large us ok
-        call    .umul
+        or      %o1, %lo(0x10c7), %o1   ! 2**32 / 1 000 000
-         or     %o1, %lo(0x10c7), %o1   ! 2**32 / 1 000 000
+        umul    %o0, %o1, %o0
-        call    .umul
+        rd      %y, %o1
-         mov    %i1, %o1                ! udelay_val
+        mov     %i1, %o1                ! udelay_val
+        umul    %o0, %o1, %o0
+        rd      %y, %o1
        sethi   %hi(0x028f4b62), %l0    ! Add in rounding constant * 2**32,
        or      %g0, %lo(0x028f4b62), %l0
        addcc   %o0, %l0, %o0           ! 2**32 * 0.009 999
        bcs,a   3f
         add    %o1, 0x01, %o1
 3:
-        call    .umul
+        mov     HZ, %o0                 ! >>32 earlier for wider range
-         mov    HZ, %o0                 ! >>32 earlier for wider range
+        umul    %o0, %o1, %o0
+        rd      %y, %o1
 delay_continue:
        cmp     %o0, 0x0
@@ -1670,4 +1358,26 @@ flushw_all:
        ret
         restore
+#ifdef CONFIG_SMP
+ENTRY(hard_smp_processor_id)
+661:    rd              %tbr, %g1
+        srl             %g1, 12, %o0
+        and             %o0, 3, %o0
+        .section        .cpuid_patch, "ax"
+        /* Instruction location. */
+        .word           661b
+        /* SUN4D implementation. */
+        lda             [%g0] ASI_M_VIKING_TMP1, %o0
+        nop
+        nop
+        /* LEON implementation. */
+        rd              %asr17, %o0
+        srl             %o0, 0x1c, %o0
+        nop
+        .previous
+        retl
+         nop
+ENDPROC(hard_smp_processor_id)
+#endif
 /* End of entry.S */
diff --git a/arch/sparc/kernel/etrap_32.S b/arch/sparc/kernel/etrap_32.S
index e806fcdc46db..84b5f0d2afde 100644
--- a/arch/sparc/kernel/etrap_32.S
+++ b/arch/sparc/kernel/etrap_32.S
@@ -216,9 +216,7 @@ tsetup_patch6:
        /* Call MMU-architecture dependent stack checking
         * routine.
         */
-        .globl  tsetup_mmu_patchme
+        b       tsetup_srmmu_stackchk
-tsetup_mmu_patchme:
-        b       tsetup_sun4c_stackchk
         andcc  %sp, 0x7, %g0
        /* Architecture specific stack checking routines.  When either
@@ -228,52 +226,6 @@ tsetup_mmu_patchme:
         */
 #define glob_tmp     g1
-tsetup_sun4c_stackchk:
-        /* Done by caller: andcc %sp, 0x7, %g0 */
-        bne     trap_setup_user_stack_is_bolixed
-         sra    %sp, 29, %glob_tmp
-        add     %glob_tmp, 0x1, %glob_tmp
-        andncc  %glob_tmp, 0x1, %g0
-        bne     trap_setup_user_stack_is_bolixed
-         and    %sp, 0xfff, %glob_tmp           ! delay slot
-        /* See if our dump area will be on more than one
-         * page.
-         */
-        add     %glob_tmp, 0x38, %glob_tmp
-        andncc  %glob_tmp, 0xff8, %g0
-        be      tsetup_sun4c_onepage            ! only one page to check
-         lda    [%sp] ASI_PTE, %glob_tmp        ! have to check first page anyways
-tsetup_sun4c_twopages:
-        /* Is first page ok permission wise? */
-        srl     %glob_tmp, 29, %glob_tmp
-        cmp     %glob_tmp, 0x6
-        bne     trap_setup_user_stack_is_bolixed
-         add    %sp, 0x38, %glob_tmp            /* Is second page in vma hole? */
-        sra     %glob_tmp, 29, %glob_tmp
-        add     %glob_tmp, 0x1, %glob_tmp
-        andncc  %glob_tmp, 0x1, %g0
-        bne     trap_setup_user_stack_is_bolixed
-         add    %sp, 0x38, %glob_tmp
-        lda     [%glob_tmp] ASI_PTE, %glob_tmp
-tsetup_sun4c_onepage:
-        srl     %glob_tmp, 29, %glob_tmp
-        cmp     %glob_tmp, 0x6                          ! can user write to it?
-        bne     trap_setup_user_stack_is_bolixed        ! failure
-         nop
-        STORE_WINDOW(sp)
-        restore %g0, %g0, %g0
-        jmpl    %t_retpc + 0x8, %g0
-         mov    %t_kstack, %sp
        .globl  tsetup_srmmu_stackchk
 tsetup_srmmu_stackchk:
        /* Check results of callers andcc %sp, 0x7, %g0 */
diff --git a/arch/sparc/kernel/head_32.S b/arch/sparc/kernel/head_32.S
index 587785759838..a0f5c20e4b9c 100644
--- a/arch/sparc/kernel/head_32.S
+++ b/arch/sparc/kernel/head_32.S
@@ -26,11 +26,9 @@
 #include <asm/pgtsrmmu.h>       /* SRMMU_PGDIR_SHIFT */
        .data
-/* 
+/* The following are used with the prom_vector node-ops to figure out
- * The following are used with the prom_vector node-ops to figure out
+ * the cpu-type
- * the cpu-type 
 */
        .align 4
 cputyp:
        .word   1
@@ -38,384 +36,35 @@ cputyp:
        .align 4
        .globl cputypval
 cputypval:
-        .asciz "sun4c"
+        .asciz "sun4m"
        .ascii "     "
-cputypvalend:
+/* Tested on SS-5, SS-10 */
-cputypvallen = cputypvar - cputypval
        .align 4
-/*
- * Sun people can't spell worth damn. "compatability" indeed.
- * At least we *know* we can't spell, and use a spell-checker.
- */
-/* Uh, actually Linus it is I who cannot spell. Too much murky
- * Sparc assembly will do this to ya.
- */
 cputypvar:
-        .asciz "compatability"
-/* Tested on SS-5, SS-10. Probably someone at Sun applied a spell-checker. */
-        .align 4
-cputypvar_sun4m:
        .asciz "compatible"
        .align 4
-sun4_notsup:
+sun4c_notsup:
-        .asciz  "Sparc-Linux sun4 support does no longer exist.\n\n"
+        .asciz  "Sparc-Linux sun4/sun4c support does no longer exist.\n\n"
        .align 4
 sun4e_notsup:
        .asciz  "Sparc-Linux sun4e support does not exist\n\n"
        .align 4
-        /* The Sparc trap table, bootloader gives us control at _start. */
+/* The trap-table - located in the __HEAD section */
-        __HEAD
+#include "ttable_32.S"
-        .globl  _stext, _start, __stext
-        .globl  trapbase
-_start:   /* danger danger */
-__stext:
-_stext:
-trapbase:
-#ifdef CONFIG_SMP
-trapbase_cpu0:
-#endif
-/* We get control passed to us here at t_zero. */
-t_zero: b gokernel; nop; nop; nop;
-t_tflt: SPARC_TFAULT                        /* Inst. Access Exception        */
-t_bins: TRAP_ENTRY(0x2, bad_instruction)    /* Illegal Instruction           */
-t_pins: TRAP_ENTRY(0x3, priv_instruction)   /* Privileged Instruction        */
-t_fpd:  TRAP_ENTRY(0x4, fpd_trap_handler)   /* Floating Point Disabled       */
-t_wovf: WINDOW_SPILL                        /* Window Overflow               */
-t_wunf: WINDOW_FILL                         /* Window Underflow              */
-t_mna:  TRAP_ENTRY(0x7, mna_handler)        /* Memory Address Not Aligned    */
-t_fpe:  TRAP_ENTRY(0x8, fpe_trap_handler)   /* Floating Point Exception      */
-t_dflt: SPARC_DFAULT                        /* Data Miss Exception           */
-t_tio:  TRAP_ENTRY(0xa, do_tag_overflow)    /* Tagged Instruction Ovrflw     */
-t_wpt:  TRAP_ENTRY(0xb, do_watchpoint)      /* Watchpoint Detected           */
-t_badc: BAD_TRAP(0xc) BAD_TRAP(0xd) BAD_TRAP(0xe) BAD_TRAP(0xf) BAD_TRAP(0x10)
-t_irq1: TRAP_ENTRY_INTERRUPT(1)             /* IRQ Software/SBUS Level 1     */
-t_irq2: TRAP_ENTRY_INTERRUPT(2)             /* IRQ SBUS Level 2              */
-t_irq3: TRAP_ENTRY_INTERRUPT(3)             /* IRQ SCSI/DMA/SBUS Level 3     */
-t_irq4: TRAP_ENTRY_INTERRUPT(4)             /* IRQ Software Level 4          */
-t_irq5: TRAP_ENTRY_INTERRUPT(5)             /* IRQ SBUS/Ethernet Level 5     */
-t_irq6: TRAP_ENTRY_INTERRUPT(6)             /* IRQ Software Level 6          */
-t_irq7: TRAP_ENTRY_INTERRUPT(7)             /* IRQ Video/SBUS Level 5        */
-t_irq8: TRAP_ENTRY_INTERRUPT(8)             /* IRQ SBUS Level 6              */
-t_irq9: TRAP_ENTRY_INTERRUPT(9)             /* IRQ SBUS Level 7              */
-t_irq10:TRAP_ENTRY_INTERRUPT(10)            /* IRQ Timer #1 (one we use)     */
-t_irq11:TRAP_ENTRY_INTERRUPT(11)            /* IRQ Floppy Intr.              */
-t_irq12:TRAP_ENTRY_INTERRUPT(12)            /* IRQ Zilog serial chip         */
-t_irq13:TRAP_ENTRY_INTERRUPT(13)            /* IRQ Audio Intr.               */
-t_irq14:TRAP_ENTRY_INTERRUPT(14)            /* IRQ Timer #2                  */
-        .globl  t_nmi
-#ifndef CONFIG_SMP
-t_nmi:  NMI_TRAP                            /* Level 15 (NMI)                */
-#else
-t_nmi:  TRAP_ENTRY(0x1f, linux_trap_ipi15_sun4m)
-#endif
-t_racc: TRAP_ENTRY(0x20, do_reg_access)     /* General Register Access Error */
-t_iacce:BAD_TRAP(0x21)                      /* Instr Access Error            */
-t_bad22:BAD_TRAP(0x22) BAD_TRAP(0x23)
-t_cpdis:TRAP_ENTRY(0x24, do_cp_disabled)    /* Co-Processor Disabled         */
-t_uflsh:SKIP_TRAP(0x25, unimp_flush)        /* Unimplemented FLUSH inst.     */
-t_bad26:BAD_TRAP(0x26) BAD_TRAP(0x27)
-t_cpexc:TRAP_ENTRY(0x28, do_cp_exception)   /* Co-Processor Exception        */
-t_dacce:SPARC_DFAULT                        /* Data Access Error             */
-t_hwdz: TRAP_ENTRY(0x2a, do_hw_divzero)     /* Division by zero, you lose... */
-t_dserr:BAD_TRAP(0x2b)                      /* Data Store Error              */
-t_daccm:BAD_TRAP(0x2c)                      /* Data Access MMU-Miss          */
-t_bad2d:BAD_TRAP(0x2d) BAD_TRAP(0x2e) BAD_TRAP(0x2f) BAD_TRAP(0x30) BAD_TRAP(0x31)
-t_bad32:BAD_TRAP(0x32) BAD_TRAP(0x33) BAD_TRAP(0x34) BAD_TRAP(0x35) BAD_TRAP(0x36)
-t_bad37:BAD_TRAP(0x37) BAD_TRAP(0x38) BAD_TRAP(0x39) BAD_TRAP(0x3a) BAD_TRAP(0x3b)
-t_iaccm:BAD_TRAP(0x3c)                      /* Instr Access MMU-Miss         */
-t_bad3d:BAD_TRAP(0x3d) BAD_TRAP(0x3e) BAD_TRAP(0x3f) BAD_TRAP(0x40) BAD_TRAP(0x41)
-t_bad42:BAD_TRAP(0x42) BAD_TRAP(0x43) BAD_TRAP(0x44) BAD_TRAP(0x45) BAD_TRAP(0x46)
-t_bad47:BAD_TRAP(0x47) BAD_TRAP(0x48) BAD_TRAP(0x49) BAD_TRAP(0x4a) BAD_TRAP(0x4b)
-t_bad4c:BAD_TRAP(0x4c) BAD_TRAP(0x4d) BAD_TRAP(0x4e) BAD_TRAP(0x4f) BAD_TRAP(0x50)
-t_bad51:BAD_TRAP(0x51) BAD_TRAP(0x52) BAD_TRAP(0x53) BAD_TRAP(0x54) BAD_TRAP(0x55)
-t_bad56:BAD_TRAP(0x56) BAD_TRAP(0x57) BAD_TRAP(0x58) BAD_TRAP(0x59) BAD_TRAP(0x5a)
-t_bad5b:BAD_TRAP(0x5b) BAD_TRAP(0x5c) BAD_TRAP(0x5d) BAD_TRAP(0x5e) BAD_TRAP(0x5f)
-t_bad60:BAD_TRAP(0x60) BAD_TRAP(0x61) BAD_TRAP(0x62) BAD_TRAP(0x63) BAD_TRAP(0x64)
-t_bad65:BAD_TRAP(0x65) BAD_TRAP(0x66) BAD_TRAP(0x67) BAD_TRAP(0x68) BAD_TRAP(0x69)
-t_bad6a:BAD_TRAP(0x6a) BAD_TRAP(0x6b) BAD_TRAP(0x6c) BAD_TRAP(0x6d) BAD_TRAP(0x6e)
-t_bad6f:BAD_TRAP(0x6f) BAD_TRAP(0x70) BAD_TRAP(0x71) BAD_TRAP(0x72) BAD_TRAP(0x73)
-t_bad74:BAD_TRAP(0x74) BAD_TRAP(0x75) BAD_TRAP(0x76) BAD_TRAP(0x77) BAD_TRAP(0x78)
-t_bad79:BAD_TRAP(0x79) BAD_TRAP(0x7a) BAD_TRAP(0x7b) BAD_TRAP(0x7c) BAD_TRAP(0x7d)
-t_bad7e:BAD_TRAP(0x7e) BAD_TRAP(0x7f)
-t_bad80:BAD_TRAP(0x80)                      /* SunOS System Call             */
-t_sbkpt:BREAKPOINT_TRAP                     /* Software Breakpoint/KGDB      */
-t_divz: TRAP_ENTRY(0x82, do_hw_divzero)     /* Divide by zero trap           */
-t_flwin:TRAP_ENTRY(0x83, do_flush_windows)  /* Flush Windows Trap            */
-t_clwin:BAD_TRAP(0x84)                      /* Clean Windows Trap            */
-t_rchk: BAD_TRAP(0x85)                      /* Range Check                   */
-t_funal:BAD_TRAP(0x86)                      /* Fix Unaligned Access Trap     */
-t_iovf: BAD_TRAP(0x87)                      /* Integer Overflow Trap         */
-t_bad88:BAD_TRAP(0x88)                      /* Slowaris System Call          */
-t_bad89:BAD_TRAP(0x89)                      /* Net-B.S. System Call          */
-t_bad8a:BAD_TRAP(0x8a) BAD_TRAP(0x8b) BAD_TRAP(0x8c) BAD_TRAP(0x8d) BAD_TRAP(0x8e)
-t_bad8f:BAD_TRAP(0x8f)
-t_linux:LINUX_SYSCALL_TRAP                  /* Linux System Call             */
-t_bad91:BAD_TRAP(0x91) BAD_TRAP(0x92) BAD_TRAP(0x93) BAD_TRAP(0x94) BAD_TRAP(0x95)
-t_bad96:BAD_TRAP(0x96) BAD_TRAP(0x97) BAD_TRAP(0x98) BAD_TRAP(0x99) BAD_TRAP(0x9a)
-t_bad9b:BAD_TRAP(0x9b) BAD_TRAP(0x9c) BAD_TRAP(0x9d) BAD_TRAP(0x9e) BAD_TRAP(0x9f)
-t_getcc:GETCC_TRAP                          /* Get Condition Codes           */
-t_setcc:SETCC_TRAP                          /* Set Condition Codes           */
-t_getpsr:GETPSR_TRAP                        /* Get PSR Register              */
-t_bada3:BAD_TRAP(0xa3) BAD_TRAP(0xa4) BAD_TRAP(0xa5) BAD_TRAP(0xa6)
-t_bada7:BAD_TRAP(0xa7)
-t_bada8:BAD_TRAP(0xa8) BAD_TRAP(0xa9) BAD_TRAP(0xaa) BAD_TRAP(0xab)
-t_badac:BAD_TRAP(0xac) BAD_TRAP(0xad) BAD_TRAP(0xae) BAD_TRAP(0xaf) BAD_TRAP(0xb0)
-t_badb1:BAD_TRAP(0xb1) BAD_TRAP(0xb2) BAD_TRAP(0xb3) BAD_TRAP(0xb4) BAD_TRAP(0xb5)
-t_badb6:BAD_TRAP(0xb6) BAD_TRAP(0xb7) BAD_TRAP(0xb8) BAD_TRAP(0xb9) BAD_TRAP(0xba)
-t_badbb:BAD_TRAP(0xbb) BAD_TRAP(0xbc) BAD_TRAP(0xbd) BAD_TRAP(0xbe) BAD_TRAP(0xbf)
-t_badc0:BAD_TRAP(0xc0) BAD_TRAP(0xc1) BAD_TRAP(0xc2) BAD_TRAP(0xc3) BAD_TRAP(0xc4)
-t_badc5:BAD_TRAP(0xc5) BAD_TRAP(0xc6) BAD_TRAP(0xc7) BAD_TRAP(0xc8) BAD_TRAP(0xc9)
-t_badca:BAD_TRAP(0xca) BAD_TRAP(0xcb) BAD_TRAP(0xcc) BAD_TRAP(0xcd) BAD_TRAP(0xce)
-t_badcf:BAD_TRAP(0xcf) BAD_TRAP(0xd0) BAD_TRAP(0xd1) BAD_TRAP(0xd2) BAD_TRAP(0xd3)
-t_badd4:BAD_TRAP(0xd4) BAD_TRAP(0xd5) BAD_TRAP(0xd6) BAD_TRAP(0xd7) BAD_TRAP(0xd8)
-t_badd9:BAD_TRAP(0xd9) BAD_TRAP(0xda) BAD_TRAP(0xdb) BAD_TRAP(0xdc) BAD_TRAP(0xdd)
-t_badde:BAD_TRAP(0xde) BAD_TRAP(0xdf) BAD_TRAP(0xe0) BAD_TRAP(0xe1) BAD_TRAP(0xe2)
-t_bade3:BAD_TRAP(0xe3) BAD_TRAP(0xe4) BAD_TRAP(0xe5) BAD_TRAP(0xe6) BAD_TRAP(0xe7)
-t_bade8:BAD_TRAP(0xe8) BAD_TRAP(0xe9) BAD_TRAP(0xea) BAD_TRAP(0xeb) BAD_TRAP(0xec)
-t_baded:BAD_TRAP(0xed) BAD_TRAP(0xee) BAD_TRAP(0xef) BAD_TRAP(0xf0) BAD_TRAP(0xf1)
-t_badf2:BAD_TRAP(0xf2) BAD_TRAP(0xf3) BAD_TRAP(0xf4) BAD_TRAP(0xf5) BAD_TRAP(0xf6)
-t_badf7:BAD_TRAP(0xf7) BAD_TRAP(0xf8) BAD_TRAP(0xf9) BAD_TRAP(0xfa) BAD_TRAP(0xfb)
-t_badfc:BAD_TRAP(0xfc)
-t_kgdb: KGDB_TRAP(0xfd)
-dbtrap: BAD_TRAP(0xfe)                      /* Debugger/PROM breakpoint #1   */
-dbtrap2:BAD_TRAP(0xff)                      /* Debugger/PROM breakpoint #2   */ 
-        .globl  end_traptable
-end_traptable:
-#ifdef CONFIG_SMP
-        /* Trap tables for the other cpus. */
-        .globl  trapbase_cpu1, trapbase_cpu2, trapbase_cpu3
-trapbase_cpu1:
-        BAD_TRAP(0x0) SRMMU_TFAULT TRAP_ENTRY(0x2, bad_instruction)
-        TRAP_ENTRY(0x3, priv_instruction) TRAP_ENTRY(0x4, fpd_trap_handler)
-        WINDOW_SPILL WINDOW_FILL TRAP_ENTRY(0x7, mna_handler)
-        TRAP_ENTRY(0x8, fpe_trap_handler) SRMMU_DFAULT
-        TRAP_ENTRY(0xa, do_tag_overflow) TRAP_ENTRY(0xb, do_watchpoint)
-        BAD_TRAP(0xc) BAD_TRAP(0xd) BAD_TRAP(0xe) BAD_TRAP(0xf) BAD_TRAP(0x10)
-        TRAP_ENTRY_INTERRUPT(1) TRAP_ENTRY_INTERRUPT(2)
-        TRAP_ENTRY_INTERRUPT(3) TRAP_ENTRY_INTERRUPT(4)
-        TRAP_ENTRY_INTERRUPT(5) TRAP_ENTRY_INTERRUPT(6)
-        TRAP_ENTRY_INTERRUPT(7) TRAP_ENTRY_INTERRUPT(8)
-        TRAP_ENTRY_INTERRUPT(9) TRAP_ENTRY_INTERRUPT(10)
-        TRAP_ENTRY_INTERRUPT(11) TRAP_ENTRY_INTERRUPT(12)
-        TRAP_ENTRY_INTERRUPT(13) TRAP_ENTRY_INTERRUPT(14)
-        TRAP_ENTRY(0x1f, linux_trap_ipi15_sun4m)
-        TRAP_ENTRY(0x20, do_reg_access) BAD_TRAP(0x21) BAD_TRAP(0x22)
-        BAD_TRAP(0x23) TRAP_ENTRY(0x24, do_cp_disabled) SKIP_TRAP(0x25, unimp_flush)
-        BAD_TRAP(0x26) BAD_TRAP(0x27) TRAP_ENTRY(0x28, do_cp_exception)
-        SRMMU_DFAULT TRAP_ENTRY(0x2a, do_hw_divzero) BAD_TRAP(0x2b) BAD_TRAP(0x2c)
-        BAD_TRAP(0x2d) BAD_TRAP(0x2e) BAD_TRAP(0x2f) BAD_TRAP(0x30) BAD_TRAP(0x31)
-        BAD_TRAP(0x32) BAD_TRAP(0x33) BAD_TRAP(0x34) BAD_TRAP(0x35) BAD_TRAP(0x36)
-        BAD_TRAP(0x37) BAD_TRAP(0x38) BAD_TRAP(0x39) BAD_TRAP(0x3a) BAD_TRAP(0x3b)
-        BAD_TRAP(0x3c) BAD_TRAP(0x3d) BAD_TRAP(0x3e) BAD_TRAP(0x3f) BAD_TRAP(0x40)
-        BAD_TRAP(0x41) BAD_TRAP(0x42) BAD_TRAP(0x43) BAD_TRAP(0x44) BAD_TRAP(0x45)
-        BAD_TRAP(0x46) BAD_TRAP(0x47) BAD_TRAP(0x48) BAD_TRAP(0x49) BAD_TRAP(0x4a)
-        BAD_TRAP(0x4b) BAD_TRAP(0x4c) BAD_TRAP(0x4d) BAD_TRAP(0x4e) BAD_TRAP(0x4f)
-        BAD_TRAP(0x50)
-        BAD_TRAP(0x51) BAD_TRAP(0x52) BAD_TRAP(0x53) BAD_TRAP(0x54) BAD_TRAP(0x55)
-        BAD_TRAP(0x56) BAD_TRAP(0x57) BAD_TRAP(0x58) BAD_TRAP(0x59) BAD_TRAP(0x5a)
-        BAD_TRAP(0x5b) BAD_TRAP(0x5c) BAD_TRAP(0x5d) BAD_TRAP(0x5e) BAD_TRAP(0x5f)
-        BAD_TRAP(0x60) BAD_TRAP(0x61) BAD_TRAP(0x62) BAD_TRAP(0x63) BAD_TRAP(0x64)
-        BAD_TRAP(0x65) BAD_TRAP(0x66) BAD_TRAP(0x67) BAD_TRAP(0x68) BAD_TRAP(0x69)
-        BAD_TRAP(0x6a) BAD_TRAP(0x6b) BAD_TRAP(0x6c) BAD_TRAP(0x6d) BAD_TRAP(0x6e)
-        BAD_TRAP(0x6f) BAD_TRAP(0x70) BAD_TRAP(0x71) BAD_TRAP(0x72) BAD_TRAP(0x73)
-        BAD_TRAP(0x74) BAD_TRAP(0x75) BAD_TRAP(0x76) BAD_TRAP(0x77) BAD_TRAP(0x78)
-        BAD_TRAP(0x79) BAD_TRAP(0x7a) BAD_TRAP(0x7b) BAD_TRAP(0x7c) BAD_TRAP(0x7d)
-        BAD_TRAP(0x7e) BAD_TRAP(0x7f)
-        BAD_TRAP(0x80)
-        BREAKPOINT_TRAP
-        TRAP_ENTRY(0x82, do_hw_divzero)
-        TRAP_ENTRY(0x83, do_flush_windows) BAD_TRAP(0x84) BAD_TRAP(0x85)
-        BAD_TRAP(0x86) BAD_TRAP(0x87) BAD_TRAP(0x88)
-        BAD_TRAP(0x89) BAD_TRAP(0x8a) BAD_TRAP(0x8b) BAD_TRAP(0x8c)
-        BAD_TRAP(0x8d) BAD_TRAP(0x8e) BAD_TRAP(0x8f)
-        LINUX_SYSCALL_TRAP BAD_TRAP(0x91) BAD_TRAP(0x92) BAD_TRAP(0x93) BAD_TRAP(0x94)
-        BAD_TRAP(0x95) BAD_TRAP(0x96) BAD_TRAP(0x97) BAD_TRAP(0x98) BAD_TRAP(0x99)
-        BAD_TRAP(0x9a) BAD_TRAP(0x9b) BAD_TRAP(0x9c) BAD_TRAP(0x9d) BAD_TRAP(0x9e)
-        BAD_TRAP(0x9f) GETCC_TRAP SETCC_TRAP GETPSR_TRAP
-        BAD_TRAP(0xa3) BAD_TRAP(0xa4) BAD_TRAP(0xa5) BAD_TRAP(0xa6)
-        BAD_TRAP(0xa7) BAD_TRAP(0xa8) BAD_TRAP(0xa9) BAD_TRAP(0xaa) BAD_TRAP(0xab)
-        BAD_TRAP(0xac) BAD_TRAP(0xad) BAD_TRAP(0xae) BAD_TRAP(0xaf) BAD_TRAP(0xb0)
-        BAD_TRAP(0xb1) BAD_TRAP(0xb2) BAD_TRAP(0xb3) BAD_TRAP(0xb4) BAD_TRAP(0xb5)
-        BAD_TRAP(0xb6) BAD_TRAP(0xb7) BAD_TRAP(0xb8) BAD_TRAP(0xb9) BAD_TRAP(0xba)
-        BAD_TRAP(0xbb) BAD_TRAP(0xbc) BAD_TRAP(0xbd) BAD_TRAP(0xbe) BAD_TRAP(0xbf)
-        BAD_TRAP(0xc0) BAD_TRAP(0xc1) BAD_TRAP(0xc2) BAD_TRAP(0xc3) BAD_TRAP(0xc4)
-        BAD_TRAP(0xc5) BAD_TRAP(0xc6) BAD_TRAP(0xc7) BAD_TRAP(0xc8) BAD_TRAP(0xc9)
-        BAD_TRAP(0xca) BAD_TRAP(0xcb) BAD_TRAP(0xcc) BAD_TRAP(0xcd) BAD_TRAP(0xce)
-        BAD_TRAP(0xcf) BAD_TRAP(0xd0) BAD_TRAP(0xd1) BAD_TRAP(0xd2) BAD_TRAP(0xd3)
-        BAD_TRAP(0xd4) BAD_TRAP(0xd5) BAD_TRAP(0xd6) BAD_TRAP(0xd7) BAD_TRAP(0xd8)
-        BAD_TRAP(0xd9) BAD_TRAP(0xda) BAD_TRAP(0xdb) BAD_TRAP(0xdc) BAD_TRAP(0xdd)
-        BAD_TRAP(0xde) BAD_TRAP(0xdf) BAD_TRAP(0xe0) BAD_TRAP(0xe1) BAD_TRAP(0xe2)
-        BAD_TRAP(0xe3) BAD_TRAP(0xe4) BAD_TRAP(0xe5) BAD_TRAP(0xe6) BAD_TRAP(0xe7)
-        BAD_TRAP(0xe8) BAD_TRAP(0xe9) BAD_TRAP(0xea) BAD_TRAP(0xeb) BAD_TRAP(0xec)
-        BAD_TRAP(0xed) BAD_TRAP(0xee) BAD_TRAP(0xef) BAD_TRAP(0xf0) BAD_TRAP(0xf1)
-        BAD_TRAP(0xf2) BAD_TRAP(0xf3) BAD_TRAP(0xf4) BAD_TRAP(0xf5) BAD_TRAP(0xf6)
-        BAD_TRAP(0xf7) BAD_TRAP(0xf8) BAD_TRAP(0xf9) BAD_TRAP(0xfa) BAD_TRAP(0xfb)
-        BAD_TRAP(0xfc) KGDB_TRAP(0xfd) BAD_TRAP(0xfe) BAD_TRAP(0xff)
-trapbase_cpu2:
-        BAD_TRAP(0x0) SRMMU_TFAULT TRAP_ENTRY(0x2, bad_instruction)
-        TRAP_ENTRY(0x3, priv_instruction) TRAP_ENTRY(0x4, fpd_trap_handler)
-        WINDOW_SPILL WINDOW_FILL TRAP_ENTRY(0x7, mna_handler)
-        TRAP_ENTRY(0x8, fpe_trap_handler) SRMMU_DFAULT
-        TRAP_ENTRY(0xa, do_tag_overflow) TRAP_ENTRY(0xb, do_watchpoint)
-        BAD_TRAP(0xc) BAD_TRAP(0xd) BAD_TRAP(0xe) BAD_TRAP(0xf) BAD_TRAP(0x10)
-        TRAP_ENTRY_INTERRUPT(1) TRAP_ENTRY_INTERRUPT(2)
-        TRAP_ENTRY_INTERRUPT(3) TRAP_ENTRY_INTERRUPT(4)
-        TRAP_ENTRY_INTERRUPT(5) TRAP_ENTRY_INTERRUPT(6)
-        TRAP_ENTRY_INTERRUPT(7) TRAP_ENTRY_INTERRUPT(8)
-        TRAP_ENTRY_INTERRUPT(9) TRAP_ENTRY_INTERRUPT(10)
-        TRAP_ENTRY_INTERRUPT(11) TRAP_ENTRY_INTERRUPT(12)
-        TRAP_ENTRY_INTERRUPT(13) TRAP_ENTRY_INTERRUPT(14)
-        TRAP_ENTRY(0x1f, linux_trap_ipi15_sun4m)
-        TRAP_ENTRY(0x20, do_reg_access) BAD_TRAP(0x21) BAD_TRAP(0x22)
-        BAD_TRAP(0x23) TRAP_ENTRY(0x24, do_cp_disabled) SKIP_TRAP(0x25, unimp_flush)
-        BAD_TRAP(0x26) BAD_TRAP(0x27) TRAP_ENTRY(0x28, do_cp_exception)
-        SRMMU_DFAULT TRAP_ENTRY(0x2a, do_hw_divzero) BAD_TRAP(0x2b) BAD_TRAP(0x2c)
-        BAD_TRAP(0x2d) BAD_TRAP(0x2e) BAD_TRAP(0x2f) BAD_TRAP(0x30) BAD_TRAP(0x31)
-        BAD_TRAP(0x32) BAD_TRAP(0x33) BAD_TRAP(0x34) BAD_TRAP(0x35) BAD_TRAP(0x36)
-        BAD_TRAP(0x37) BAD_TRAP(0x38) BAD_TRAP(0x39) BAD_TRAP(0x3a) BAD_TRAP(0x3b)
-        BAD_TRAP(0x3c) BAD_TRAP(0x3d) BAD_TRAP(0x3e) BAD_TRAP(0x3f) BAD_TRAP(0x40)
-        BAD_TRAP(0x41) BAD_TRAP(0x42) BAD_TRAP(0x43) BAD_TRAP(0x44) BAD_TRAP(0x45)
-        BAD_TRAP(0x46) BAD_TRAP(0x47) BAD_TRAP(0x48) BAD_TRAP(0x49) BAD_TRAP(0x4a)
-        BAD_TRAP(0x4b) BAD_TRAP(0x4c) BAD_TRAP(0x4d) BAD_TRAP(0x4e) BAD_TRAP(0x4f)
-        BAD_TRAP(0x50)
-        BAD_TRAP(0x51) BAD_TRAP(0x52) BAD_TRAP(0x53) BAD_TRAP(0x54) BAD_TRAP(0x55)
-        BAD_TRAP(0x56) BAD_TRAP(0x57) BAD_TRAP(0x58) BAD_TRAP(0x59) BAD_TRAP(0x5a)
-        BAD_TRAP(0x5b) BAD_TRAP(0x5c) BAD_TRAP(0x5d) BAD_TRAP(0x5e) BAD_TRAP(0x5f)
-        BAD_TRAP(0x60) BAD_TRAP(0x61) BAD_TRAP(0x62) BAD_TRAP(0x63) BAD_TRAP(0x64)
-        BAD_TRAP(0x65) BAD_TRAP(0x66) BAD_TRAP(0x67) BAD_TRAP(0x68) BAD_TRAP(0x69)
-        BAD_TRAP(0x6a) BAD_TRAP(0x6b) BAD_TRAP(0x6c) BAD_TRAP(0x6d) BAD_TRAP(0x6e)
-        BAD_TRAP(0x6f) BAD_TRAP(0x70) BAD_TRAP(0x71) BAD_TRAP(0x72) BAD_TRAP(0x73)
-        BAD_TRAP(0x74) BAD_TRAP(0x75) BAD_TRAP(0x76) BAD_TRAP(0x77) BAD_TRAP(0x78)
-        BAD_TRAP(0x79) BAD_TRAP(0x7a) BAD_TRAP(0x7b) BAD_TRAP(0x7c) BAD_TRAP(0x7d)
-        BAD_TRAP(0x7e) BAD_TRAP(0x7f)
-        BAD_TRAP(0x80)
-        BREAKPOINT_TRAP
-        TRAP_ENTRY(0x82, do_hw_divzero)
-        TRAP_ENTRY(0x83, do_flush_windows) BAD_TRAP(0x84) BAD_TRAP(0x85)
-        BAD_TRAP(0x86) BAD_TRAP(0x87) BAD_TRAP(0x88)
-        BAD_TRAP(0x89) BAD_TRAP(0x8a) BAD_TRAP(0x8b) BAD_TRAP(0x8c)
-        BAD_TRAP(0x8d) BAD_TRAP(0x8e) BAD_TRAP(0x8f)
-        LINUX_SYSCALL_TRAP BAD_TRAP(0x91) BAD_TRAP(0x92) BAD_TRAP(0x93) BAD_TRAP(0x94)
-        BAD_TRAP(0x95) BAD_TRAP(0x96) BAD_TRAP(0x97) BAD_TRAP(0x98) BAD_TRAP(0x99)
-        BAD_TRAP(0x9a) BAD_TRAP(0x9b) BAD_TRAP(0x9c) BAD_TRAP(0x9d) BAD_TRAP(0x9e)
-        BAD_TRAP(0x9f) GETCC_TRAP SETCC_TRAP GETPSR_TRAP
-        BAD_TRAP(0xa3) BAD_TRAP(0xa4) BAD_TRAP(0xa5) BAD_TRAP(0xa6)
-        BAD_TRAP(0xa7) BAD_TRAP(0xa8) BAD_TRAP(0xa9) BAD_TRAP(0xaa) BAD_TRAP(0xab)
-        BAD_TRAP(0xac) BAD_TRAP(0xad) BAD_TRAP(0xae) BAD_TRAP(0xaf) BAD_TRAP(0xb0)
-        BAD_TRAP(0xb1) BAD_TRAP(0xb2) BAD_TRAP(0xb3) BAD_TRAP(0xb4) BAD_TRAP(0xb5)
-        BAD_TRAP(0xb6) BAD_TRAP(0xb7) BAD_TRAP(0xb8) BAD_TRAP(0xb9) BAD_TRAP(0xba)
-        BAD_TRAP(0xbb) BAD_TRAP(0xbc) BAD_TRAP(0xbd) BAD_TRAP(0xbe) BAD_TRAP(0xbf)
-        BAD_TRAP(0xc0) BAD_TRAP(0xc1) BAD_TRAP(0xc2) BAD_TRAP(0xc3) BAD_TRAP(0xc4)
-        BAD_TRAP(0xc5) BAD_TRAP(0xc6) BAD_TRAP(0xc7) BAD_TRAP(0xc8) BAD_TRAP(0xc9)
-        BAD_TRAP(0xca) BAD_TRAP(0xcb) BAD_TRAP(0xcc) BAD_TRAP(0xcd) BAD_TRAP(0xce)
-        BAD_TRAP(0xcf) BAD_TRAP(0xd0) BAD_TRAP(0xd1) BAD_TRAP(0xd2) BAD_TRAP(0xd3)
-        BAD_TRAP(0xd4) BAD_TRAP(0xd5) BAD_TRAP(0xd6) BAD_TRAP(0xd7) BAD_TRAP(0xd8)
-        BAD_TRAP(0xd9) BAD_TRAP(0xda) BAD_TRAP(0xdb) BAD_TRAP(0xdc) BAD_TRAP(0xdd)
-        BAD_TRAP(0xde) BAD_TRAP(0xdf) BAD_TRAP(0xe0) BAD_TRAP(0xe1) BAD_TRAP(0xe2)
-        BAD_TRAP(0xe3) BAD_TRAP(0xe4) BAD_TRAP(0xe5) BAD_TRAP(0xe6) BAD_TRAP(0xe7)
-        BAD_TRAP(0xe8) BAD_TRAP(0xe9) BAD_TRAP(0xea) BAD_TRAP(0xeb) BAD_TRAP(0xec)
-        BAD_TRAP(0xed) BAD_TRAP(0xee) BAD_TRAP(0xef) BAD_TRAP(0xf0) BAD_TRAP(0xf1)
-        BAD_TRAP(0xf2) BAD_TRAP(0xf3) BAD_TRAP(0xf4) BAD_TRAP(0xf5) BAD_TRAP(0xf6)
-        BAD_TRAP(0xf7) BAD_TRAP(0xf8) BAD_TRAP(0xf9) BAD_TRAP(0xfa) BAD_TRAP(0xfb)
-        BAD_TRAP(0xfc) KGDB_TRAP(0xfd) BAD_TRAP(0xfe) BAD_TRAP(0xff)
-trapbase_cpu3:
-        BAD_TRAP(0x0) SRMMU_TFAULT TRAP_ENTRY(0x2, bad_instruction)
-        TRAP_ENTRY(0x3, priv_instruction) TRAP_ENTRY(0x4, fpd_trap_handler)
-        WINDOW_SPILL WINDOW_FILL TRAP_ENTRY(0x7, mna_handler)
-        TRAP_ENTRY(0x8, fpe_trap_handler) SRMMU_DFAULT
-        TRAP_ENTRY(0xa, do_tag_overflow) TRAP_ENTRY(0xb, do_watchpoint)
-        BAD_TRAP(0xc) BAD_TRAP(0xd) BAD_TRAP(0xe) BAD_TRAP(0xf) BAD_TRAP(0x10)
-        TRAP_ENTRY_INTERRUPT(1) TRAP_ENTRY_INTERRUPT(2)
-        TRAP_ENTRY_INTERRUPT(3) TRAP_ENTRY_INTERRUPT(4)
-        TRAP_ENTRY_INTERRUPT(5) TRAP_ENTRY_INTERRUPT(6)
-        TRAP_ENTRY_INTERRUPT(7) TRAP_ENTRY_INTERRUPT(8)
-        TRAP_ENTRY_INTERRUPT(9) TRAP_ENTRY_INTERRUPT(10)
-        TRAP_ENTRY_INTERRUPT(11) TRAP_ENTRY_INTERRUPT(12)
-        TRAP_ENTRY_INTERRUPT(13) TRAP_ENTRY_INTERRUPT(14)
-        TRAP_ENTRY(0x1f, linux_trap_ipi15_sun4m)
-        TRAP_ENTRY(0x20, do_reg_access) BAD_TRAP(0x21) BAD_TRAP(0x22)
-        BAD_TRAP(0x23) TRAP_ENTRY(0x24, do_cp_disabled) SKIP_TRAP(0x25, unimp_flush)
-        BAD_TRAP(0x26) BAD_TRAP(0x27) TRAP_ENTRY(0x28, do_cp_exception)
-        SRMMU_DFAULT TRAP_ENTRY(0x2a, do_hw_divzero) BAD_TRAP(0x2b) BAD_TRAP(0x2c)
-        BAD_TRAP(0x2d) BAD_TRAP(0x2e) BAD_TRAP(0x2f) BAD_TRAP(0x30) BAD_TRAP(0x31)
-        BAD_TRAP(0x32) BAD_TRAP(0x33) BAD_TRAP(0x34) BAD_TRAP(0x35) BAD_TRAP(0x36)
-        BAD_TRAP(0x37) BAD_TRAP(0x38) BAD_TRAP(0x39) BAD_TRAP(0x3a) BAD_TRAP(0x3b)
-        BAD_TRAP(0x3c) BAD_TRAP(0x3d) BAD_TRAP(0x3e) BAD_TRAP(0x3f) BAD_TRAP(0x40)
-        BAD_TRAP(0x41) BAD_TRAP(0x42) BAD_TRAP(0x43) BAD_TRAP(0x44) BAD_TRAP(0x45)
-        BAD_TRAP(0x46) BAD_TRAP(0x47) BAD_TRAP(0x48) BAD_TRAP(0x49) BAD_TRAP(0x4a)
-        BAD_TRAP(0x4b) BAD_TRAP(0x4c) BAD_TRAP(0x4d) BAD_TRAP(0x4e) BAD_TRAP(0x4f)
-        BAD_TRAP(0x50)
-        BAD_TRAP(0x51) BAD_TRAP(0x52) BAD_TRAP(0x53) BAD_TRAP(0x54) BAD_TRAP(0x55)
-        BAD_TRAP(0x56) BAD_TRAP(0x57) BAD_TRAP(0x58) BAD_TRAP(0x59) BAD_TRAP(0x5a)
-        BAD_TRAP(0x5b) BAD_TRAP(0x5c) BAD_TRAP(0x5d) BAD_TRAP(0x5e) BAD_TRAP(0x5f)
-        BAD_TRAP(0x60) BAD_TRAP(0x61) BAD_TRAP(0x62) BAD_TRAP(0x63) BAD_TRAP(0x64)
-        BAD_TRAP(0x65) BAD_TRAP(0x66) BAD_TRAP(0x67) BAD_TRAP(0x68) BAD_TRAP(0x69)
-        BAD_TRAP(0x6a) BAD_TRAP(0x6b) BAD_TRAP(0x6c) BAD_TRAP(0x6d) BAD_TRAP(0x6e)
-        BAD_TRAP(0x6f) BAD_TRAP(0x70) BAD_TRAP(0x71) BAD_TRAP(0x72) BAD_TRAP(0x73)
-        BAD_TRAP(0x74) BAD_TRAP(0x75) BAD_TRAP(0x76) BAD_TRAP(0x77) BAD_TRAP(0x78)
-        BAD_TRAP(0x79) BAD_TRAP(0x7a) BAD_TRAP(0x7b) BAD_TRAP(0x7c) BAD_TRAP(0x7d)
-        BAD_TRAP(0x7e) BAD_TRAP(0x7f)
-        BAD_TRAP(0x80)
-        BREAKPOINT_TRAP
-        TRAP_ENTRY(0x82, do_hw_divzero)
-        TRAP_ENTRY(0x83, do_flush_windows) BAD_TRAP(0x84) BAD_TRAP(0x85)
-        BAD_TRAP(0x86) BAD_TRAP(0x87) BAD_TRAP(0x88)
-        BAD_TRAP(0x89) BAD_TRAP(0x8a) BAD_TRAP(0x8b) BAD_TRAP(0x8c)
-        BAD_TRAP(0x8d) BAD_TRAP(0x8e) BAD_TRAP(0x8f)
-        LINUX_SYSCALL_TRAP BAD_TRAP(0x91) BAD_TRAP(0x92) BAD_TRAP(0x93) BAD_TRAP(0x94)
-        BAD_TRAP(0x95) BAD_TRAP(0x96) BAD_TRAP(0x97) BAD_TRAP(0x98) BAD_TRAP(0x99)
-        BAD_TRAP(0x9a) BAD_TRAP(0x9b) BAD_TRAP(0x9c) BAD_TRAP(0x9d) BAD_TRAP(0x9e)
-        BAD_TRAP(0x9f) GETCC_TRAP SETCC_TRAP GETPSR_TRAP
-        BAD_TRAP(0xa3) BAD_TRAP(0xa4) BAD_TRAP(0xa5) BAD_TRAP(0xa6)
-        BAD_TRAP(0xa7) BAD_TRAP(0xa8) BAD_TRAP(0xa9) BAD_TRAP(0xaa) BAD_TRAP(0xab)
-        BAD_TRAP(0xac) BAD_TRAP(0xad) BAD_TRAP(0xae) BAD_TRAP(0xaf) BAD_TRAP(0xb0)
-        BAD_TRAP(0xb1) BAD_TRAP(0xb2) BAD_TRAP(0xb3) BAD_TRAP(0xb4) BAD_TRAP(0xb5)
-        BAD_TRAP(0xb6) BAD_TRAP(0xb7) BAD_TRAP(0xb8) BAD_TRAP(0xb9) BAD_TRAP(0xba)
-        BAD_TRAP(0xbb) BAD_TRAP(0xbc) BAD_TRAP(0xbd) BAD_TRAP(0xbe) BAD_TRAP(0xbf)
-        BAD_TRAP(0xc0) BAD_TRAP(0xc1) BAD_TRAP(0xc2) BAD_TRAP(0xc3) BAD_TRAP(0xc4)
-        BAD_TRAP(0xc5) BAD_TRAP(0xc6) BAD_TRAP(0xc7) BAD_TRAP(0xc8) BAD_TRAP(0xc9)
-        BAD_TRAP(0xca) BAD_TRAP(0xcb) BAD_TRAP(0xcc) BAD_TRAP(0xcd) BAD_TRAP(0xce)
-        BAD_TRAP(0xcf) BAD_TRAP(0xd0) BAD_TRAP(0xd1) BAD_TRAP(0xd2) BAD_TRAP(0xd3)
-        BAD_TRAP(0xd4) BAD_TRAP(0xd5) BAD_TRAP(0xd6) BAD_TRAP(0xd7) BAD_TRAP(0xd8)
-        BAD_TRAP(0xd9) BAD_TRAP(0xda) BAD_TRAP(0xdb) BAD_TRAP(0xdc) BAD_TRAP(0xdd)
-        BAD_TRAP(0xde) BAD_TRAP(0xdf) BAD_TRAP(0xe0) BAD_TRAP(0xe1) BAD_TRAP(0xe2)
-        BAD_TRAP(0xe3) BAD_TRAP(0xe4) BAD_TRAP(0xe5) BAD_TRAP(0xe6) BAD_TRAP(0xe7)
-        BAD_TRAP(0xe8) BAD_TRAP(0xe9) BAD_TRAP(0xea) BAD_TRAP(0xeb) BAD_TRAP(0xec)
-        BAD_TRAP(0xed) BAD_TRAP(0xee) BAD_TRAP(0xef) BAD_TRAP(0xf0) BAD_TRAP(0xf1)
-        BAD_TRAP(0xf2) BAD_TRAP(0xf3) BAD_TRAP(0xf4) BAD_TRAP(0xf5) BAD_TRAP(0xf6)
-        BAD_TRAP(0xf7) BAD_TRAP(0xf8) BAD_TRAP(0xf9) BAD_TRAP(0xfa) BAD_TRAP(0xfb)
-        BAD_TRAP(0xfc) KGDB_TRAP(0xfd) BAD_TRAP(0xfe) BAD_TRAP(0xff)
-#endif
        .align PAGE_SIZE
 /* This was the only reasonable way I could think of to properly align
 * these page-table data structures.
 */
-        .globl pg0, pg1, pg2, pg3
-        .globl empty_bad_page
-        .globl empty_bad_page_table
-        .globl empty_zero_page
        .globl swapper_pg_dir
 swapper_pg_dir:         .skip PAGE_SIZE
-pg0:                    .skip PAGE_SIZE
+        .globl empty_zero_page
-pg1:                    .skip PAGE_SIZE
-pg2:                    .skip PAGE_SIZE
-pg3:                    .skip PAGE_SIZE
-empty_bad_page:         .skip PAGE_SIZE
-empty_bad_page_table:   .skip PAGE_SIZE
 empty_zero_page:        .skip PAGE_SIZE
        .global root_flags
@@ -523,10 +172,10 @@ copy_prom_lvl14:
                ldd     [%g2 + 0x8], %g4
                std     %g4, [%g3 + 0x8]        ! Copy proms handler
-/* Must determine whether we are on a sun4c MMU, SRMMU, or SUN4/400 MUTANT
+/* DON'T TOUCH %l0 thru %l5 in these remapping routines,
- * MMU so we can remap ourselves properly.  DON'T TOUCH %l0 thru %l5 in these
+ * we need their values afterwards!
- * remapping routines, we need their values afterwards!
 */
                /* Now check whether we are already mapped, if we
                 * are we can skip all this garbage coming up.
                 */
@@ -535,26 +184,29 @@ copy_prom_done:
                be      go_to_highmem           ! this will be a nop then
                 nop
-                set     LOAD_ADDR, %g6
+                /* Validate that we are in fact running on an
+                 * SRMMU based cpu.
+                 */
+                set     0x4000, %g6
                cmp     %g7, %g6
-                bne     remap_not_a_sun4        ! This is not a Sun4
+                bne     not_a_sun4
                 nop
-                or      %g0, 0x1, %g1
+halt_sun4_or_sun4c:
-                lduba   [%g1] ASI_CONTROL, %g1  ! Only safe to try on Sun4.
+                ld      [%g7 + 0x68], %o1
-                subcc   %g1, 0x24, %g0          ! Is this a mutant Sun4/400???
+                set     sun4c_notsup, %o0
-                be      sun4_mutant_remap       ! Ugh, it is...
+                sub     %o0, %l6, %o0
+                call    %o1
                 nop
+                ba      halt_me
-                b       sun4_normal_remap       ! regular sun4, 2 level mmu
                 nop
-remap_not_a_sun4:
+not_a_sun4:
-                lda     [%g0] ASI_M_MMUREGS, %g1 ! same as ASI_PTE on sun4c
+                lda     [%g0] ASI_M_MMUREGS, %g1
-                and     %g1, 0x1, %g1           ! Test SRMMU Enable bit ;-)
+                andcc   %g1, 1, %g0
-                cmp     %g1, 0x0
+                be      halt_sun4_or_sun4c
-                be      sun4c_remap             ! A sun4c MMU or normal Sun4
                 nop
 srmmu_remap:
                /* First, check for a viking (TI) module. */
                set     0x40000000, %g2
@@ -660,72 +312,6 @@ srmmu_nviking:
                b       go_to_highmem
                 nop                                    ! wheee....
-                /* This remaps the kernel on Sun4/4xx machines
-                 * that have the Sun Mutant Three Level MMU.
-                 * It's like a platypus, Sun didn't have the
-                 * SRMMU in conception so they kludged the three
-                 * level logic in the regular Sun4 MMU probably.
-                 *
-                 * Basically, you take each entry in the top level
-                 * directory that maps the low 3MB starting at
-                 * address zero and put the mapping in the KERNBASE
-                 * slots.  These top level pgd's are called regmaps.
-                 */
-sun4_mutant_remap:
-                or      %g0, %g0, %g3           ! source base
-                sethi   %hi(KERNBASE), %g4      ! destination base
-                or      %g4, %lo(KERNBASE), %g4
-                sethi   %hi(0x300000), %g5
-                or      %g5, %lo(0x300000), %g5 ! upper bound 3MB
-                or      %g0, 0x1, %l6
-                sll     %l6, 24, %l6            ! Regmap mapping size
-                add     %g3, 0x2, %g3           ! Base magic
-                add     %g4, 0x2, %g4           ! Base magic
-                /* Main remapping loop on Sun4-Mutant-MMU.
-                 * "I am not an animal..." -Famous Mutant Person
-                 */
-sun4_mutant_loop:
-                lduha   [%g3] ASI_REGMAP, %g2   ! Get lower entry
-                stha    %g2, [%g4] ASI_REGMAP   ! Store in high entry
-                add     %g4, %l6, %g4           ! Move up high memory ptr
-                subcc   %g3, %g5, %g0           ! Reached our limit?
-                blu     sun4_mutant_loop        ! Nope, loop again
-                 add    %g3, %l6, %g3           ! delay, Move up low ptr
-                b       go_to_highmem           ! Jump to high memory.
-                 nop
-                /* The following is for non-4/4xx sun4 MMU's. */
-sun4_normal_remap:
-                mov     0, %g3                  ! source base
-                set     KERNBASE, %g4           ! destination base
-                set     0x300000, %g5           ! upper bound 3MB
-                mov     1, %l6
-                sll     %l6, 18, %l6            ! sun4 mmu segmap size
-sun4_normal_loop:
-                lduha   [%g3] ASI_SEGMAP, %g6   ! load phys_seg
-                stha    %g6, [%g4] ASI_SEGMAP   ! stort new virt mapping
-                add     %g3, %l6, %g3           ! increment source pointer
-                subcc   %g3, %g5, %g0           ! reached limit?
-                blu     sun4_normal_loop        ! nope, loop again
-                 add    %g4, %l6, %g4           ! delay, increment dest ptr
-                b       go_to_highmem
-                 nop
-                /* The following works for Sun4c MMU's */
-sun4c_remap:
-                mov     0, %g3                  ! source base
-                set     KERNBASE, %g4           ! destination base
-                set     0x300000, %g5           ! upper bound 3MB
-                mov     1, %l6
-                sll     %l6, 18, %l6            ! sun4c mmu segmap size
-sun4c_remap_loop:
-                lda     [%g3] ASI_SEGMAP, %g6   ! load phys_seg
-                sta     %g6, [%g4] ASI_SEGMAP   ! store new virt mapping
-                add     %g3, %l6, %g3           ! Increment source ptr
-                subcc   %g3, %g5, %g0           ! Reached limit?
-                bl      sun4c_remap_loop        ! Nope, loop again
-                 add    %g4, %l6, %g4           ! delay, Increment dest ptr
 /* Now do a non-relative jump so that PC is in high-memory */
 go_to_highmem:
@@ -750,35 +336,12 @@ execute_in_high_mem:
                sethi   %hi(linux_dbvec), %g1
                st      %o1, [%g1 + %lo(linux_dbvec)]
-                ld      [%o0 + 0x4], %o3
-                and     %o3, 0x3, %o5                   ! get the version
-                cmp     %o3, 0x2                        ! a v2 prom?
-                be      found_version
-                 nop
-                /* paul@sfe.com.au */
-                cmp     %o3, 0x3                        ! a v3 prom?
-                be      found_version
-                 nop
-/* Old sun4's pass our load address into %o0 instead of the prom
- * pointer. On sun4's you have to hard code the romvec pointer into
- * your code. Sun probably still does that because they don't even
- * trust their own "OpenBoot" specifications.
- */
-                set     LOAD_ADDR, %g6
-                cmp     %o0, %g6                ! an old sun4?
-                be      sun4_init
-                 nop
-found_version:
 /* Get the machine type via the mysterious romvec node operations. */
-                add     %g7, 0x1c, %l1          
+                add     %g7, 0x1c, %l1
                ld      [%l1], %l0
                ld      [%l0], %l0
-                call    %l0
+                call    %l0
                 or     %g0, %g0, %o0           ! next_node(0) = first_node
                or      %o0, %g0, %g6
@@ -786,28 +349,13 @@ found_version:
                or      %o1, %lo(cputypvar), %o1
                sethi   %hi(cputypval), %o2     ! information, the string
                or      %o2, %lo(cputypval), %o2
-                ld      [%l1], %l0              ! 'compatibility' tells
+                ld      [%l1], %l0              ! 'compatible' tells
                ld      [%l0 + 0xc], %l0        ! that we want 'sun4x' where
-                call    %l0                     ! x is one of '', 'c', 'm',
+                call    %l0                     ! x is one of 'm', 'd' or 'e'.
-                 nop                            ! 'd' or 'e'. %o2 holds pointer
+                 nop                            ! %o2 holds pointer
                                                ! to a buf where above string
                                                ! will get stored by the prom.
-                subcc   %o0, %g0, %g0
-                bpos    got_prop                ! Got the property
-                 nop
-                or      %g6, %g0, %o0
-                sethi   %hi(cputypvar_sun4m), %o1
-                or      %o1, %lo(cputypvar_sun4m), %o1
-                sethi   %hi(cputypval), %o2
-                or      %o2, %lo(cputypval), %o2
-                ld      [%l1], %l0
-                ld      [%l0 + 0xc], %l0
-                call    %l0
-                 nop
-got_prop:
 #ifdef CONFIG_SPARC_LEON
                /* no cpu-type check is needed, it is a SPARC-LEON */
@@ -826,45 +374,29 @@ got_prop:
                /* Update boot_cpu_id only on boot cpu */
                stub    %g1, [%g2 + %lo(boot_cpu_id)]
-                ba sun4c_continue_boot
+                ba continue_boot
                 nop
 #endif
+/* Check to cputype. We may be booted on a sun4u (64 bit box),
+ * and sun4d needs special treatment.
+ */
                set     cputypval, %o2
                ldub    [%o2 + 0x4], %l1
-                cmp     %l1, ' '
+                cmp     %l1, 'm'
-                be      1f
+                be      sun4m_init
-                 cmp    %l1, 'c'
-                be      1f
-                 cmp    %l1, 'm'
-                be      1f
                 cmp    %l1, 's'
-                be      1f
+                be      sun4m_init
                 cmp    %l1, 'd'
-                be      1f
+                be      sun4d_init
                 cmp    %l1, 'e'
                be      no_sun4e_here           ! Could be a sun4e.
                 nop
                b       no_sun4u_here           ! AIEEE, a V9 sun4u... Get our BIG BROTHER kernel :))
                 nop
-1:              set     cputypval, %l1
-                ldub    [%l1 + 0x4], %l1
-                cmp     %l1, 'm'                ! Test for sun4d, sun4e ?
-                be      sun4m_init
-                 cmp    %l1, 's'                ! Treat sun4s as sun4m
-                be      sun4m_init
-                 cmp    %l1, 'd'                ! Let us see how the beast will die
-                be      sun4d_init
-                 nop
-                /* Jump into mmu context zero. */
-                set     AC_CONTEXT, %g1
-                stba    %g0, [%g1] ASI_CONTROL
-                b       sun4c_continue_boot
-                 nop
 /* CPUID in bootbus can be found at PA 0xff0140000 */
 #define SUN4D_BOOTBUS_CPUID     0xf0140000
@@ -892,66 +424,6 @@ sun4d_init:
        /* Fall through to sun4m_init */
 sun4m_init:
-        /* XXX Fucking Cypress... */
-        lda     [%g0] ASI_M_MMUREGS, %g5
-        srl     %g5, 28, %g4
-        cmp     %g4, 1
-        bne     1f
-         srl    %g5, 24, %g4
-        and     %g4, 0xf, %g4
-        cmp     %g4, 7          /* This would be a HyperSparc. */
-        bne     2f
-         nop
-1:
-#define PATCH_IT(dst, src)      \
-        set     (dst), %g5;     \
-        set     (src), %g4;     \
-        ld      [%g4], %g3;     \
-        st      %g3, [%g5];     \
-        ld      [%g4+0x4], %g3; \
-        st      %g3, [%g5+0x4];
-        /* Signed multiply. */
-        PATCH_IT(.mul, .mul_patch)
-        PATCH_IT(.mul+0x08, .mul_patch+0x08)
-        /* Signed remainder. */
-        PATCH_IT(.rem, .rem_patch)
-        PATCH_IT(.rem+0x08, .rem_patch+0x08)
-        PATCH_IT(.rem+0x10, .rem_patch+0x10)
-        PATCH_IT(.rem+0x18, .rem_patch+0x18)
-        PATCH_IT(.rem+0x20, .rem_patch+0x20)
-        PATCH_IT(.rem+0x28, .rem_patch+0x28)
-        /* Signed division. */
-        PATCH_IT(.div, .div_patch)
-        PATCH_IT(.div+0x08, .div_patch+0x08)
-        PATCH_IT(.div+0x10, .div_patch+0x10)
-        PATCH_IT(.div+0x18, .div_patch+0x18)
-        PATCH_IT(.div+0x20, .div_patch+0x20)
-        /* Unsigned multiply. */
-        PATCH_IT(.umul, .umul_patch)
-        PATCH_IT(.umul+0x08, .umul_patch+0x08)
-        /* Unsigned remainder. */
-        PATCH_IT(.urem, .urem_patch)
-        PATCH_IT(.urem+0x08, .urem_patch+0x08)
-        PATCH_IT(.urem+0x10, .urem_patch+0x10)
-        PATCH_IT(.urem+0x18, .urem_patch+0x18)
-        /* Unsigned division. */
-        PATCH_IT(.udiv, .udiv_patch)
-        PATCH_IT(.udiv+0x08, .udiv_patch+0x08)
-        PATCH_IT(.udiv+0x10, .udiv_patch+0x10)
-#undef PATCH_IT
 /* Ok, the PROM could have done funny things and apple cider could still
 * be sitting in the fault status/address registers.  Read them all to
 * clear them so we don't get magic faults later on.
@@ -962,7 +434,7 @@ sun4m_init:
                srl     %o1, 28, %o1            ! Get a type of the CPU
                subcc   %o1, 4, %g0             ! TI: Viking or MicroSPARC
-                be      sun4c_continue_boot
+                be      continue_boot
                 nop
                set     AC_M_SFSR, %o0
@@ -972,7 +444,7 @@ sun4m_init:
                /* Fujitsu MicroSPARC-II has no asynchronous flavors of FARs */
                subcc   %o1, 0, %g0
-                be      sun4c_continue_boot
+                be      continue_boot
                 nop
                set     AC_M_AFSR, %o0
@@ -982,8 +454,7 @@ sun4m_init:
                 nop
-sun4c_continue_boot:
+continue_boot:
 /* Aieee, now set PC and nPC, enable traps, give ourselves a stack and it's
 * show-time!
@@ -1026,10 +497,7 @@ sun4c_continue_boot:
                mov     %g0, %g3
                stub    %g3, [%g2 + %lo(boot_cpu_id)]
-1:              /* boot_cpu_id set. calculate boot_cpu_id4 = boot_cpu_id*4 */
+1:              sll     %g3, 2, %g3
-                sll     %g3, 2, %g3
-                sethi   %hi(boot_cpu_id4), %g2
-                stub    %g3, [%g2 + %lo(boot_cpu_id4)]
                /* Initialize the uwinmask value for init task just in case.
                 * But first make current_set[boot_cpu_id] point to something useful.
@@ -1165,19 +633,6 @@ sun4c_continue_boot:
                call    halt_me
                 nop
-sun4_init:
-                sethi   %hi(SUN4_PROM_VECTOR+0x84), %o1
-                ld      [%o1 + %lo(SUN4_PROM_VECTOR+0x84)], %o1
-                set     sun4_notsup, %o0
-                call    %o1     /* printf */
-                 nop
-                sethi   %hi(SUN4_PROM_VECTOR+0xc4), %o1
-                ld      [%o1 + %lo(SUN4_PROM_VECTOR+0xc4)], %o1
-                call    %o1     /* exittomon */
-                 nop
-1:              ba      1b                      ! Cannot exit into KMON
-                 nop
 no_sun4e_here:
                ld      [%g7 + 0x68], %o1
                set     sun4e_notsup, %o0
diff --git a/arch/sparc/kernel/head_64.S b/arch/sparc/kernel/head_64.S
index 0d810c2f1d00..b42ddbf9651e 100644
--- a/arch/sparc/kernel/head_64.S
+++ b/arch/sparc/kernel/head_64.S
@@ -906,7 +906,7 @@ swapper_4m_tsb:
         * error and will instead write junk into the relocation and
         * you'll have an unbootable kernel.
         */
-#include "ttable.S"
+#include "ttable_64.S"
 ! 0x0000000000428000
diff --git a/arch/sparc/kernel/idprom.c b/arch/sparc/kernel/idprom.c
index 9167db40720e..6bd75012109d 100644
--- a/arch/sparc/kernel/idprom.c
+++ b/arch/sparc/kernel/idprom.c
@@ -25,22 +25,9 @@ static struct idprom idprom_buffer;
 * of the Sparc CPU and have a meaningful IDPROM machtype value that we
 * know about.  See asm-sparc/machines.h for empirical constants.
 */
-static struct Sun_Machine_Models Sun_Machines[NUM_SUN_MACHINES] = {
+static struct Sun_Machine_Models Sun_Machines[] = {
-/* First, Sun4's */
+/* First, Leon */
-{ .name = "Sun 4/100 Series",        .id_machtype = (SM_SUN4 | SM_4_110) },
-{ .name = "Sun 4/200 Series",        .id_machtype = (SM_SUN4 | SM_4_260) },
-{ .name = "Sun 4/300 Series",        .id_machtype = (SM_SUN4 | SM_4_330) },
-{ .name = "Sun 4/400 Series",        .id_machtype = (SM_SUN4 | SM_4_470) },
-/* Now Leon */
 { .name = "Leon3 System-on-a-Chip",  .id_machtype = (M_LEON | M_LEON3_SOC) },
-/* Now, Sun4c's */
-{ .name = "Sun4c SparcStation 1",    .id_machtype = (SM_SUN4C | SM_4C_SS1) },
-{ .name = "Sun4c SparcStation IPC",  .id_machtype = (SM_SUN4C | SM_4C_IPC) },
-{ .name = "Sun4c SparcStation 1+",   .id_machtype = (SM_SUN4C | SM_4C_SS1PLUS) },
-{ .name = "Sun4c SparcStation SLC",  .id_machtype = (SM_SUN4C | SM_4C_SLC) },
-{ .name = "Sun4c SparcStation 2",    .id_machtype = (SM_SUN4C | SM_4C_SS2) },
-{ .name = "Sun4c SparcStation ELC",  .id_machtype = (SM_SUN4C | SM_4C_ELC) },
-{ .name = "Sun4c SparcStation IPX",  .id_machtype = (SM_SUN4C | SM_4C_IPX) },
 /* Finally, early Sun4m's */
 { .name = "Sun4m SparcSystem600",    .id_machtype = (SM_SUN4M | SM_4M_SS60) },
 { .name = "Sun4m SparcStation10/20", .id_machtype = (SM_SUN4M | SM_4M_SS50) },
@@ -53,7 +40,7 @@ static void __init display_system_type(unsigned char machtype)
        char sysname[128];
        register int i;
-        for (i = 0; i < NUM_SUN_MACHINES; i++) {
+        for (i = 0; i < ARRAY_SIZE(Sun_Machines); i++) {
                if (Sun_Machines[i].id_machtype == machtype) {
                        if (machtype != (SM_SUN4M_OBP | 0x00) ||
                            prom_getproperty(prom_root_node, "banner-name",
diff --git a/arch/sparc/kernel/init_task.c b/arch/sparc/kernel/init_task.c
deleted file mode 100644
index 35f141a9f506..000000000000
--- a/arch/sparc/kernel/init_task.c
+++ /dev/null
@@ -1,22 +0,0 @@
-#include <linux/mm.h>
-#include <linux/fs.h>
-#include <linux/module.h>
-#include <linux/sched.h>
-#include <linux/init_task.h>
-#include <linux/mqueue.h>
-#include <asm/pgtable.h>
-#include <asm/uaccess.h>
-static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
-static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
-struct task_struct init_task = INIT_TASK(init_task);
-EXPORT_SYMBOL(init_task);
-/* .text section in head.S is aligned at 8k boundary and this gets linked
- * right after that so that the init_thread_union is aligned properly as well.
- * If this is not aligned on a 8k boundary, then you should change code
- * in etrap.S which assumes it.
- */
-union thread_union init_thread_union __init_task_data =
-        { INIT_THREAD_INFO(init_task) };
diff --git a/arch/sparc/kernel/ioport.c b/arch/sparc/kernel/ioport.c
index 21bd73943f7f..a2846f5e32d8 100644
--- a/arch/sparc/kernel/ioport.c
+++ b/arch/sparc/kernel/ioport.c
@@ -50,6 +50,8 @@
 #include <asm/io-unit.h>
 #include <asm/leon.h>
+const struct sparc32_dma_ops *sparc32_dma_ops;
 /* This function must make sure that caches and memory are coherent after DMA
 * On LEON systems without cache snooping it flushes the entire D-CACHE.
 */
@@ -229,7 +231,7 @@ _sparc_ioremap(struct resource *res, u32 bus, u32 pa, int sz)
        }
        pa &= PAGE_MASK;
-        sparc_mapiorange(bus, pa, res->start, resource_size(res));
+        srmmu_mapiorange(bus, pa, res->start, resource_size(res));
        return (void __iomem *)(unsigned long)(res->start + offset);
 }
@@ -243,7 +245,7 @@ static void _sparc_free_io(struct resource *res)
        plen = resource_size(res);
        BUG_ON((plen & (PAGE_SIZE-1)) != 0);
-        sparc_unmapiorange(res->start, plen);
+        srmmu_unmapiorange(res->start, plen);
        release_resource(res);
 }
@@ -292,13 +294,13 @@ static void *sbus_alloc_coherent(struct device *dev, size_t len,
                goto err_nova;
        }
-        // XXX The mmu_map_dma_area does this for us below, see comments.
+        // XXX The sbus_map_dma_area does this for us below, see comments.
-        // sparc_mapiorange(0, virt_to_phys(va), res->start, len_total);
+        // srmmu_mapiorange(0, virt_to_phys(va), res->start, len_total);
        /*
         * XXX That's where sdev would be used. Currently we load
         * all iommu tables with the same translations.
         */
-        if (mmu_map_dma_area(dev, dma_addrp, va, res->start, len_total) != 0)
+        if (sbus_map_dma_area(dev, dma_addrp, va, res->start, len_total) != 0)
                goto err_noiommu;
        res->name = op->dev.of_node->name;
@@ -343,7 +345,7 @@ static void sbus_free_coherent(struct device *dev, size_t n, void *p,
        kfree(res);
        pgv = virt_to_page(p);
-        mmu_unmap_dma_area(dev, ba, n);
+        sbus_unmap_dma_area(dev, ba, n);
        __free_pages(pgv, get_order(n));
 }
@@ -381,11 +383,6 @@ static int sbus_map_sg(struct device *dev, struct scatterlist *sg, int n,
                       enum dma_data_direction dir, struct dma_attrs *attrs)
 {
        mmu_get_scsi_sgl(dev, sg, n);
-        /*
-         * XXX sparc64 can return a partial length here. sun4c should do this
-         * but it currently panics if it can't fulfill the request - Anton
-         */
        return n;
 }
@@ -469,7 +466,7 @@ static void *pci32_alloc_coherent(struct device *dev, size_t len,
                printk("pci_alloc_consistent: cannot occupy 0x%lx", len_total);
                goto err_nova;
        }
-        sparc_mapiorange(0, virt_to_phys(va), res->start, len_total);
+        srmmu_mapiorange(0, virt_to_phys(va), res->start, len_total);
        *pba = virt_to_phys(va); /* equals virt_to_bus (R.I.P.) for us. */
        return (void *) res->start;
@@ -514,7 +511,7 @@ static void pci32_free_coherent(struct device *dev, size_t n, void *p,
        }
        dma_make_coherent(ba, n);
-        sparc_unmapiorange((unsigned long)p, n);
+        srmmu_unmapiorange((unsigned long)p, n);
        release_resource(res);
        kfree(res);
diff --git a/arch/sparc/kernel/irq.h b/arch/sparc/kernel/irq.h
index 5a021dd2f854..b66b6aad1d6d 100644
--- a/arch/sparc/kernel/irq.h
+++ b/arch/sparc/kernel/irq.h
@@ -1,6 +1,5 @@
 #include <linux/platform_device.h>
-#include <asm/btfixup.h>
 #include <asm/cpu_type.h>
 struct irq_bucket {
@@ -10,6 +9,9 @@ struct irq_bucket {
        unsigned int pil;
 };
+#define SUN4M_HARD_INT(x)       (0x000000001 << (x))
+#define SUN4M_SOFT_INT(x)       (0x000010000 << (x))
 #define SUN4D_MAX_BOARD 10
 #define SUN4D_MAX_IRQ ((SUN4D_MAX_BOARD + 2) << 5)
@@ -41,52 +43,46 @@ struct sun4m_irq_global {
 extern struct sun4m_irq_percpu __iomem *sun4m_irq_percpu[SUN4M_NCPUS];
 extern struct sun4m_irq_global __iomem *sun4m_irq_global;
+/* The following definitions describe the individual platform features: */
+#define FEAT_L10_CLOCKSOURCE (1 << 0) /* L10 timer is used as a clocksource */
+#define FEAT_L10_CLOCKEVENT  (1 << 1) /* L10 timer is used as a clockevent */
+#define FEAT_L14_ONESHOT     (1 << 2) /* L14 timer clockevent can oneshot */
 /*
- * Platform specific irq configuration
+ * Platform specific configuration
 * The individual platforms assign their platform
 * specifics in their init functions.
 */
-struct sparc_irq_config {
+struct sparc_config {
-        void (*init_timers)(irq_handler_t);
+        void (*init_timers)(void);
        unsigned int (*build_device_irq)(struct platform_device *op,
                                         unsigned int real_irq);
+        /* generic clockevent features - see FEAT_* above */
+        int features;
+        /* clock rate used for clock event timer */
+        int clock_rate;
+        /* one period for clock source timer */
+        unsigned int cs_period;
+        /* function to obtain offsett for cs period */
+        unsigned int (*get_cycles_offset)(void);
+        void (*clear_clock_irq)(void);
+        void (*load_profile_irq)(int cpu, unsigned int limit);
 };
-extern struct sparc_irq_config sparc_irq_config;
+extern struct sparc_config sparc_config;
 unsigned int irq_alloc(unsigned int real_irq, unsigned int pil);
 void irq_link(unsigned int irq);
 void irq_unlink(unsigned int irq);
 void handler_irq(unsigned int pil, struct pt_regs *regs);
-/* Dave Redman (djhr@tadpole.co.uk)
+unsigned long leon_get_irqmask(unsigned int irq);
- * changed these to function pointers.. it saves cycles and will allow
- * the irq dependencies to be split into different files at a later date
- * sun4c_irq.c, sun4m_irq.c etc so we could reduce the kernel size.
- * Jakub Jelinek (jj@sunsite.mff.cuni.cz)
- * Changed these to btfixup entities... It saves cycles :)
- */
-BTFIXUPDEF_CALL(void, clear_clock_irq, void)
-BTFIXUPDEF_CALL(void, load_profile_irq, int, unsigned int)
-static inline void clear_clock_irq(void)
-{
-        BTFIXUP_CALL(clear_clock_irq)();
-}
-static inline void load_profile_irq(int cpu, int limit)
-{
-        BTFIXUP_CALL(load_profile_irq)(cpu, limit);
-}
 #ifdef CONFIG_SMP
-BTFIXUPDEF_CALL(void, set_cpu_int, int, int)
-BTFIXUPDEF_CALL(void, clear_cpu_int, int, int)
-BTFIXUPDEF_CALL(void, set_irq_udt, int)
-#define set_cpu_int(cpu,level) BTFIXUP_CALL(set_cpu_int)(cpu,level)
-#define clear_cpu_int(cpu,level) BTFIXUP_CALL(clear_cpu_int)(cpu,level)
-#define set_irq_udt(cpu) BTFIXUP_CALL(set_irq_udt)(cpu)
 /* All SUN4D IPIs are sent on this IRQ, may be shared with hard IRQs */
 #define SUN4D_IPI_IRQ 13
diff --git a/arch/sparc/kernel/irq_32.c b/arch/sparc/kernel/irq_32.c
index b2668afd1c34..ae04914f7774 100644
--- a/arch/sparc/kernel/irq_32.c
+++ b/arch/sparc/kernel/irq_32.c
@@ -23,16 +23,8 @@
 #include "kernel.h"
 #include "irq.h"
-#ifdef CONFIG_SMP
-#define SMP_NOP2 "nop; nop;\n\t"
-#define SMP_NOP3 "nop; nop; nop;\n\t"
-#else
-#define SMP_NOP2
-#define SMP_NOP3
-#endif /* SMP */
 /* platform specific irq setup */
-struct sparc_irq_config sparc_irq_config;
+struct sparc_config sparc_config;
 unsigned long arch_local_irq_save(void)
 {
@@ -41,7 +33,6 @@ unsigned long arch_local_irq_save(void)
        __asm__ __volatile__(
                "rd     %%psr, %0\n\t"
-                SMP_NOP3        /* Sun4m + Cypress + SMP bug */
                "or     %0, %2, %1\n\t"
                "wr     %1, 0, %%psr\n\t"
                "nop; nop; nop\n"
@@ -59,7 +50,6 @@ void arch_local_irq_enable(void)
        __asm__ __volatile__(
                "rd     %%psr, %0\n\t"
-                SMP_NOP3        /* Sun4m + Cypress + SMP bug */
                "andn   %0, %1, %0\n\t"
                "wr     %0, 0, %%psr\n\t"
                "nop; nop; nop\n"
@@ -76,7 +66,6 @@ void arch_local_irq_restore(unsigned long old_psr)
        __asm__ __volatile__(
                "rd     %%psr, %0\n\t"
                "and    %2, %1, %2\n\t"
-                SMP_NOP2        /* Sun4m + Cypress + SMP bug */
                "andn   %0, %1, %0\n\t"
                "wr     %0, %2, %%psr\n\t"
                "nop; nop; nop\n"
@@ -346,11 +335,6 @@ void sparc_floppy_irq(int irq, void *dev_id, struct pt_regs *regs)
 void __init init_IRQ(void)
 {
        switch (sparc_cpu_model) {
-        case sun4c:
-        case sun4:
-                sun4c_init_IRQ();
-                break;
        case sun4m:
                pcic_probe();
                if (pcic_present())
@@ -371,6 +355,5 @@ void __init init_IRQ(void)
                prom_printf("Cannot initialize IRQs on this Sun machine...");
                break;
        }
-        btfixup();
 }
diff --git a/arch/sparc/kernel/irq_64.c b/arch/sparc/kernel/irq_64.c
index dff2c3d7d370..9bcbbe2c4e7e 100644
--- a/arch/sparc/kernel/irq_64.c
+++ b/arch/sparc/kernel/irq_64.c
@@ -799,7 +799,7 @@ static void kill_prom_timer(void)
        prom_limit0 = prom_timers->limit0;
        prom_limit1 = prom_timers->limit1;
-        /* Just as in sun4c/sun4m PROM uses timer which ticks at IRQ 14.
+        /* Just as in sun4c PROM uses timer which ticks at IRQ 14.
         * We turn both off here just to be paranoid.
         */
        prom_timers->limit0 = 0;
diff --git a/arch/sparc/kernel/kernel.h b/arch/sparc/kernel/kernel.h
index fd6c36b1df74..a86372d34587 100644
--- a/arch/sparc/kernel/kernel.h
+++ b/arch/sparc/kernel/kernel.h
@@ -32,9 +32,6 @@ extern void cpu_probe(void);
 /* traps_32.c */
 extern void handle_hw_divzero(struct pt_regs *regs, unsigned long pc,
                              unsigned long npc, unsigned long psr);
-/* muldiv.c */
-extern int do_user_muldiv (struct pt_regs *, unsigned long);
 /* irq_32.c */
 extern struct irqaction static_irqaction[];
 extern int static_irq_count;
@@ -43,12 +40,7 @@ extern spinlock_t irq_action_lock;
 extern void unexpected_irq(int irq, void *dev_id, struct pt_regs * regs);
 extern void init_IRQ(void);
-/* sun4c_irq.c */
-extern void sun4c_init_IRQ(void);
 /* sun4m_irq.c */
-extern unsigned int lvl14_resolution;
 extern void sun4m_init_IRQ(void);
 extern void sun4m_unmask_profile_irq(void);
 extern void sun4m_clear_profile_irq(int cpu);
@@ -85,8 +77,6 @@ extern unsigned int patchme_maybe_smp_msg[];
 extern void floppy_hardint(void);
 /* trampoline_32.S */
-extern int __smp4m_processor_id(void);
-extern int __smp4d_processor_id(void);
 extern unsigned long sun4m_cpu_startup;
 extern unsigned long sun4d_cpu_startup;
diff --git a/arch/sparc/kernel/leon_kernel.c b/arch/sparc/kernel/leon_kernel.c
index 35e43673c453..77c1b916e4dd 100644
--- a/arch/sparc/kernel/leon_kernel.c
+++ b/arch/sparc/kernel/leon_kernel.c
@@ -10,6 +10,8 @@
 #include <linux/of_platform.h>
 #include <linux/interrupt.h>
 #include <linux/of_device.h>
+#include <linux/clocksource.h>
+#include <linux/clockchips.h>
 #include <asm/oplib.h>
 #include <asm/timer.h>
@@ -84,7 +86,7 @@ void leon_eirq_setup(unsigned int eirq)
        sparc_leon_eirq = eirq;
 }
-static inline unsigned long get_irqmask(unsigned int irq)
+unsigned long leon_get_irqmask(unsigned int irq)
 {
        unsigned long mask;
@@ -210,7 +212,7 @@ unsigned int leon_build_device_irq(unsigned int real_irq,
        unsigned long mask;
        irq = 0;
-        mask = get_irqmask(real_irq);
+        mask = leon_get_irqmask(real_irq);
        if (mask == 0)
                goto out;
@@ -250,7 +252,38 @@ void leon_update_virq_handling(unsigned int virq,
        irq_set_chip_data(virq, (void *)mask);
 }
-void __init leon_init_timers(irq_handler_t counter_fn)
+static u32 leon_cycles_offset(void)
+{
+        u32 rld, val, off;
+        rld = LEON3_BYPASS_LOAD_PA(&leon3_gptimer_regs->e[leon3_gptimer_idx].rld);
+        val = LEON3_BYPASS_LOAD_PA(&leon3_gptimer_regs->e[leon3_gptimer_idx].val);
+        off = rld - val;
+        return rld - val;
+}
+#ifdef CONFIG_SMP
+/* smp clockevent irq */
+irqreturn_t leon_percpu_timer_ce_interrupt(int irq, void *unused)
+{
+        struct clock_event_device *ce;
+        int cpu = smp_processor_id();
+        leon_clear_profile_irq(cpu);
+        ce = &per_cpu(sparc32_clockevent, cpu);
+        irq_enter();
+        if (ce->event_handler)
+                ce->event_handler(ce);
+        irq_exit();
+        return IRQ_HANDLED;
+}
+#endif /* CONFIG_SMP */
+void __init leon_init_timers(void)
 {
        int irq, eirq;
        struct device_node *rootnp, *np, *nnp;
@@ -260,6 +293,14 @@ void __init leon_init_timers(irq_handler_t counter_fn)
        int ampopts;
        int err;
+        sparc_config.get_cycles_offset = leon_cycles_offset;
+        sparc_config.cs_period = 1000000 / HZ;
+        sparc_config.features |= FEAT_L10_CLOCKSOURCE;
+#ifndef CONFIG_SMP
+        sparc_config.features |= FEAT_L10_CLOCKEVENT;
+#endif
        leondebug_irq_disable = 0;
        leon_debug_irqout = 0;
        master_l10_counter = (unsigned int *)&dummy_master_l10_counter;
@@ -369,7 +410,7 @@ void __init leon_init_timers(irq_handler_t counter_fn)
                leon_eirq_setup(eirq);
        irq = _leon_build_device_irq(NULL, leon3_gptimer_irq+leon3_gptimer_idx);
-        err = request_irq(irq, counter_fn, IRQF_TIMER, "timer", NULL);
+        err = request_irq(irq, timer_interrupt, IRQF_TIMER, "timer", NULL);
        if (err) {
                printk(KERN_ERR "unable to attach timer IRQ%d\n", irq);
                prom_halt();
@@ -386,7 +427,7 @@ void __init leon_init_timers(irq_handler_t counter_fn)
                 */
                local_irq_save(flags);
                patchme_maybe_smp_msg[0] = 0x01000000; /* NOP out the branch */
-                local_flush_cache_all();
+                local_ops->cache_all();
                local_irq_restore(flags);
        }
 #endif
@@ -401,7 +442,7 @@ void __init leon_init_timers(irq_handler_t counter_fn)
        /* Install per-cpu IRQ handler for broadcasted ticker */
        irq = leon_build_device_irq(leon3_ticker_irq, handle_percpu_irq,
                                    "per-cpu", 0);
-        err = request_irq(irq, leon_percpu_timer_interrupt,
+        err = request_irq(irq, leon_percpu_timer_ce_interrupt,
                          IRQF_PERCPU | IRQF_TIMER, "ticker",
                          NULL);
        if (err) {
@@ -422,13 +463,12 @@ bad:
        return;
 }
-void leon_clear_clock_irq(void)
+static void leon_clear_clock_irq(void)
 {
 }
-void leon_load_profile_irq(int cpu, unsigned int limit)
+static void leon_load_profile_irq(int cpu, unsigned int limit)
 {
-        BUG();
 }
 void __init leon_trans_init(struct device_node *dp)
@@ -457,25 +497,6 @@ void __init leon_node_init(struct device_node *dp, struct device_node ***nextp)
 }
 #ifdef CONFIG_SMP
-void leon_set_cpu_int(int cpu, int level)
-{
-        unsigned long mask;
-        mask = get_irqmask(level);
-        LEON3_BYPASS_STORE_PA(&leon3_irqctrl_regs->force[cpu], mask);
-}
-static void leon_clear_ipi(int cpu, int level)
-{
-        unsigned long mask;
-        mask = get_irqmask(level);
-        LEON3_BYPASS_STORE_PA(&leon3_irqctrl_regs->force[cpu], mask<<16);
-}
-static void leon_set_udt(int cpu)
-{
-}
 void leon_clear_profile_irq(int cpu)
 {
 }
@@ -483,7 +504,7 @@ void leon_clear_profile_irq(int cpu)
 void leon_enable_irq_cpu(unsigned int irq_nr, unsigned int cpu)
 {
        unsigned long mask, flags, *addr;
-        mask = get_irqmask(irq_nr);
+        mask = leon_get_irqmask(irq_nr);
        spin_lock_irqsave(&leon_irq_lock, flags);
        addr = (unsigned long *)LEON_IMASK(cpu);
        LEON3_BYPASS_STORE_PA(addr, (LEON3_BYPASS_LOAD_PA(addr) | mask));
@@ -494,20 +515,11 @@ void leon_enable_irq_cpu(unsigned int irq_nr, unsigned int cpu)
 void __init leon_init_IRQ(void)
 {
-        sparc_irq_config.init_timers      = leon_init_timers;
+        sparc_config.init_timers      = leon_init_timers;
-        sparc_irq_config.build_device_irq = _leon_build_device_irq;
+        sparc_config.build_device_irq = _leon_build_device_irq;
+        sparc_config.clock_rate       = 1000000;
-        BTFIXUPSET_CALL(clear_clock_irq, leon_clear_clock_irq,
+        sparc_config.clear_clock_irq  = leon_clear_clock_irq;
-                        BTFIXUPCALL_NORM);
+        sparc_config.load_profile_irq = leon_load_profile_irq;
-        BTFIXUPSET_CALL(load_profile_irq, leon_load_profile_irq,
-                        BTFIXUPCALL_NOP);
-#ifdef CONFIG_SMP
-        BTFIXUPSET_CALL(set_cpu_int, leon_set_cpu_int, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(clear_cpu_int, leon_clear_ipi, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(set_irq_udt, leon_set_udt, BTFIXUPCALL_NORM);
-#endif
 }
 void __init leon_init(void)
diff --git a/arch/sparc/kernel/leon_pci.c b/arch/sparc/kernel/leon_pci.c
index aba6b958b2a5..19f56058742b 100644
--- a/arch/sparc/kernel/leon_pci.c
+++ b/arch/sparc/kernel/leon_pci.c
@@ -45,7 +45,6 @@ void leon_pci_init(struct platform_device *ofdev, struct leon_pci_info *info)
 void __devinit pcibios_fixup_bus(struct pci_bus *pbus)
 {
-        struct leon_pci_info *info = pbus->sysdata;
        struct pci_dev *dev;
        int i, has_io, has_mem;
        u16 cmd;
@@ -111,18 +110,6 @@ int pcibios_enable_device(struct pci_dev *dev, int mask)
        return pci_enable_resources(dev, mask);
 }
-struct device_node *pci_device_to_OF_node(struct pci_dev *pdev)
-{
-        /*
-         * Currently the OpenBoot nodes are not connected with the PCI device,
-         * this is because the LEON PROM does not create PCI nodes. Eventually
-         * this will change and the same approach as pcic.c can be used to
-         * match PROM nodes with pci devices.
-         */
-        return NULL;
-}
-EXPORT_SYMBOL(pci_device_to_OF_node);
 void __devinit pcibios_update_irq(struct pci_dev *dev, int irq)
 {
 #ifdef CONFIG_PCI_DEBUG
diff --git a/arch/sparc/kernel/leon_smp.c b/arch/sparc/kernel/leon_smp.c
index 1210fde18740..a469090faf9f 100644
--- a/arch/sparc/kernel/leon_smp.c
+++ b/arch/sparc/kernel/leon_smp.c
@@ -23,6 +23,8 @@
 #include <linux/pm.h>
 #include <linux/delay.h>
 #include <linux/gfp.h>
+#include <linux/cpu.h>
+#include <linux/clockchips.h>
 #include <asm/cacheflush.h>
 #include <asm/tlbflush.h>
@@ -42,6 +44,7 @@
 #include <asm/asi.h>
 #include <asm/leon.h>
 #include <asm/leon_amba.h>
+#include <asm/timer.h>
 #include "kernel.h"
@@ -68,24 +71,24 @@ static inline unsigned long do_swap(volatile unsigned long *ptr,
        return val;
 }
-static void smp_setup_percpu_timer(void);
 void __cpuinit leon_callin(void)
 {
-        int cpuid = hard_smpleon_processor_id();
+        int cpuid = hard_smp_processor_id();
-        local_flush_cache_all();
+        local_ops->cache_all();
-        local_flush_tlb_all();
+        local_ops->tlb_all();
        leon_configure_cache_smp();
+        notify_cpu_starting(cpuid);
        /* Get our local ticker going. */
-        smp_setup_percpu_timer();
+        register_percpu_ce(cpuid);
        calibrate_delay();
        smp_store_cpu_info(cpuid);
-        local_flush_cache_all();
+        local_ops->cache_all();
-        local_flush_tlb_all();
+        local_ops->tlb_all();
        /*
         * Unblock the master CPU _only_ when the scheduler state
@@ -96,8 +99,8 @@ void __cpuinit leon_callin(void)
         */
        do_swap(&cpu_callin_map[cpuid], 1);
-        local_flush_cache_all();
+        local_ops->cache_all();
-        local_flush_tlb_all();
+        local_ops->tlb_all();
        /* Fix idle thread fields. */
        __asm__ __volatile__("ld [%0], %%g6\n\t" : : "r"(&current_set[cpuid])
@@ -140,8 +143,8 @@ void __init leon_configure_cache_smp(void)
                }
        }
-        local_flush_cache_all();
+        local_ops->cache_all();
-        local_flush_tlb_all();
+        local_ops->tlb_all();
 }
 void leon_smp_setbroadcast(unsigned int mask)
@@ -196,21 +199,15 @@ void __init leon_boot_cpus(void)
        leon_smp_setbroadcast(1 << LEON3_IRQ_TICKER);
        leon_configure_cache_smp();
-        smp_setup_percpu_timer();
+        local_ops->cache_all();
-        local_flush_cache_all();
 }
-int __cpuinit leon_boot_one_cpu(int i)
+int __cpuinit leon_boot_one_cpu(int i, struct task_struct *idle)
 {
-        struct task_struct *p;
        int timeout;
-        /* Cook up an idler for this guy. */
+        current_set[i] = task_thread_info(idle);
-        p = fork_idle(i);
-        current_set[i] = task_thread_info(p);
        /* See trampoline.S:leon_smp_cpu_startup for details...
         * Initialize the contexts table
@@ -224,7 +221,7 @@ int __cpuinit leon_boot_one_cpu(int i)
        /* whirrr, whirrr, whirrrrrrrrr... */
        printk(KERN_INFO "Starting CPU %d : (irqmp: 0x%x)\n", (unsigned int)i,
               (unsigned int)&leon3_irqctrl_regs->mpstatus);
-        local_flush_cache_all();
+        local_ops->cache_all();
        /* Make sure all IRQs are of from the start for this new CPU */
        LEON_BYPASS_STORE_PA(&leon3_irqctrl_regs->mask[i], 0);
@@ -249,7 +246,7 @@ int __cpuinit leon_boot_one_cpu(int i)
                leon_enable_irq_cpu(leon_ipi_irq, i);
        }
-        local_flush_cache_all();
+        local_ops->cache_all();
        return 0;
 }
@@ -269,7 +266,7 @@ void __init leon_smp_done(void)
                }
        }
        *prev = first;
-        local_flush_cache_all();
+        local_ops->cache_all();
        /* Free unneeded trap tables */
        if (!cpu_present(1)) {
@@ -335,7 +332,7 @@ static void __init leon_ipi_init(void)
        local_irq_save(flags);
        trap_table = &sparc_ttable[SP_TRAP_IRQ1 + (leon_ipi_irq - 1)];
        trap_table->inst_three += smpleon_ipi - real_irq_entry;
-        local_flush_cache_all();
+        local_ops->cache_all();
        local_irq_restore(flags);
        for_each_possible_cpu(cpu) {
@@ -344,6 +341,13 @@ static void __init leon_ipi_init(void)
        }
 }
+static void leon_send_ipi(int cpu, int level)
+{
+        unsigned long mask;
+        mask = leon_get_irqmask(level);
+        LEON3_BYPASS_STORE_PA(&leon3_irqctrl_regs->force[cpu], mask);
+}
 static void leon_ipi_single(int cpu)
 {
        struct leon_ipi_work *work = &per_cpu(leon_ipi_work, cpu);
@@ -352,7 +356,7 @@ static void leon_ipi_single(int cpu)
        work->single = 1;
        /* Generate IRQ on the CPU */
-        set_cpu_int(cpu, leon_ipi_irq);
+        leon_send_ipi(cpu, leon_ipi_irq);
 }
 static void leon_ipi_mask_one(int cpu)
@@ -363,7 +367,7 @@ static void leon_ipi_mask_one(int cpu)
        work->msk = 1;
        /* Generate IRQ on the CPU */
-        set_cpu_int(cpu, leon_ipi_irq);
+        leon_send_ipi(cpu, leon_ipi_irq);
 }
 static void leon_ipi_resched(int cpu)
@@ -374,7 +378,7 @@ static void leon_ipi_resched(int cpu)
        work->resched = 1;
        /* Generate IRQ on the CPU (any IRQ will cause resched) */
-        set_cpu_int(cpu, leon_ipi_irq);
+        leon_send_ipi(cpu, leon_ipi_irq);
 }
 void leonsmp_ipi_interrupt(void)
@@ -446,7 +450,7 @@ static void leon_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1,
                                if (cpumask_test_cpu(i, &mask)) {
                                        ccall_info.processors_in[i] = 0;
                                        ccall_info.processors_out[i] = 0;
-                                        set_cpu_int(i, LEON3_IRQ_CROSS_CALL);
+                                        leon_send_ipi(i, LEON3_IRQ_CROSS_CALL);
                                }
                        }
@@ -489,68 +493,19 @@ void leon_cross_call_irq(void)
        ccall_info.processors_out[i] = 1;
 }
-irqreturn_t leon_percpu_timer_interrupt(int irq, void *unused)
+static const struct sparc32_ipi_ops leon_ipi_ops = {
-{
+        .cross_call = leon_cross_call,
-        int cpu = smp_processor_id();
+        .resched    = leon_ipi_resched,
+        .single     = leon_ipi_single,
-        leon_clear_profile_irq(cpu);
+        .mask_one   = leon_ipi_mask_one,
+};
-        profile_tick(CPU_PROFILING);
-        if (!--prof_counter(cpu)) {
-                int user = user_mode(get_irq_regs());
-                update_process_times(user);
-                prof_counter(cpu) = prof_multiplier(cpu);
-        }
-        return IRQ_HANDLED;
-}
-static void __init smp_setup_percpu_timer(void)
-{
-        int cpu = smp_processor_id();
-        prof_counter(cpu) = prof_multiplier(cpu) = 1;
-}
-void __init leon_blackbox_id(unsigned *addr)
-{
-        int rd = *addr & 0x3e000000;
-        int rs1 = rd >> 11;
-        /* patch places where ___b_hard_smp_processor_id appears */
-        addr[0] = 0x81444000 | rd;      /* rd %asr17, reg */
-        addr[1] = 0x8130201c | rd | rs1;        /* srl reg, 0x1c, reg */
-        addr[2] = 0x01000000;   /* nop */
-}
-void __init leon_blackbox_current(unsigned *addr)
-{
-        int rd = *addr & 0x3e000000;
-        int rs1 = rd >> 11;
-        /* patch LOAD_CURRENT macro where ___b_load_current appears */
-        addr[0] = 0x81444000 | rd;      /* rd %asr17, reg */
-        addr[2] = 0x8130201c | rd | rs1;        /* srl reg, 0x1c, reg */
-        addr[4] = 0x81282002 | rd | rs1;        /* sll reg, 0x2, reg */
-}
 void __init leon_init_smp(void)
 {
        /* Patch ipi15 trap table */
        t_nmi[1] = t_nmi[1] + (linux_trap_ipi15_leon - linux_trap_ipi15_sun4m);
-        BTFIXUPSET_BLACKBOX(hard_smp_processor_id, leon_blackbox_id);
+        sparc32_ipi_ops = &leon_ipi_ops;
-        BTFIXUPSET_BLACKBOX(load_current, leon_blackbox_current);
-        BTFIXUPSET_CALL(smp_cross_call, leon_cross_call, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(__hard_smp_processor_id, __leon_processor_id,
-                        BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(smp_ipi_resched, leon_ipi_resched, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(smp_ipi_single, leon_ipi_single, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(smp_ipi_mask_one, leon_ipi_mask_one, BTFIXUPCALL_NORM);
 }
 #endif /* CONFIG_SPARC_LEON */
diff --git a/arch/sparc/kernel/module.c b/arch/sparc/kernel/module.c
index 276359e1ff56..15e0a1693976 100644
--- a/arch/sparc/kernel/module.c
+++ b/arch/sparc/kernel/module.c
@@ -32,26 +32,11 @@ static void *module_map(unsigned long size)
                                GFP_KERNEL, PAGE_KERNEL, -1,
                                __builtin_return_address(0));
 }
-static char *dot2underscore(char *name)
-{
-        return name;
-}
 #else
 static void *module_map(unsigned long size)
 {
        return vmalloc(size);
 }
-/* Replace references to .func with _Func */
-static char *dot2underscore(char *name)
-{
-        if (name[0] == '.') {
-                name[0] = '_';
-                name[1] = toupper(name[1]);
-        }
-        return name;
-}
 #endif /* CONFIG_SPARC64 */
 void *module_alloc(unsigned long size)
@@ -93,12 +78,8 @@ int module_frob_arch_sections(Elf_Ehdr *hdr,
        for (i = 1; i < sechdrs[symidx].sh_size / sizeof(Elf_Sym); i++) {
                if (sym[i].st_shndx == SHN_UNDEF) {
-                        if (ELF_ST_TYPE(sym[i].st_info) == STT_REGISTER) {
+                        if (ELF_ST_TYPE(sym[i].st_info) == STT_REGISTER)
                                sym[i].st_shndx = SHN_ABS;
-                        } else {
-                                char *name = strtab + sym[i].st_name;
-                                dot2underscore(name);
-                        }
                }
        }
        return 0;
diff --git a/arch/sparc/kernel/muldiv.c b/arch/sparc/kernel/muldiv.c
deleted file mode 100644
index f7db516b07d8..000000000000
--- a/arch/sparc/kernel/muldiv.c
+++ /dev/null
@@ -1,238 +0,0 @@
-/*
- * muldiv.c: Hardware multiply/division illegal instruction trap
- *              for sun4c/sun4 (which do not have those instructions)
- *
- * Copyright (C) 1996 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
- * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
- *
- * 2004-12-25   Krzysztof Helt (krzysztof.h1@wp.pl) 
- *              - fixed registers constrains in inline assembly declarations
- */
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/mm.h>
-#include <asm/ptrace.h>
-#include <asm/processor.h>
-#include <asm/uaccess.h>
-#include "kernel.h"
-/* #define DEBUG_MULDIV */
-static inline int has_imm13(int insn)
-{
-        return (insn & 0x2000);
-}
-static inline int is_foocc(int insn)
-{
-        return (insn & 0x800000);
-}
-static inline int sign_extend_imm13(int imm)
-{
-        return imm << 19 >> 19;
-}
-static inline void advance(struct pt_regs *regs)
-{
-        regs->pc   = regs->npc;
-        regs->npc += 4;
-}
-static inline void maybe_flush_windows(unsigned int rs1, unsigned int rs2,
-                                       unsigned int rd)
-{
-        if(rs2 >= 16 || rs1 >= 16 || rd >= 16) {
-                /* Wheee... */
-                __asm__ __volatile__("save %sp, -0x40, %sp\n\t"
-                                     "save %sp, -0x40, %sp\n\t"
-                                     "save %sp, -0x40, %sp\n\t"
-                                     "save %sp, -0x40, %sp\n\t"
-                                     "save %sp, -0x40, %sp\n\t"
-                                     "save %sp, -0x40, %sp\n\t"
-                                     "save %sp, -0x40, %sp\n\t"
-                                     "restore; restore; restore; restore;\n\t"
-                                     "restore; restore; restore;\n\t");
-        }
-}
-#define fetch_reg(reg, regs) ({                                         \
-        struct reg_window32 __user *win;                                        \
-        register unsigned long ret;                                     \
-                                                                        \
-        if (!(reg)) ret = 0;                                            \
-        else if ((reg) < 16) {                                          \
-                ret = regs->u_regs[(reg)];                              \
-        } else {                                                        \
-                /* Ho hum, the slightly complicated case. */            \
-                win = (struct reg_window32 __user *)regs->u_regs[UREG_FP];\
-                if (get_user (ret, &win->locals[(reg) - 16])) return -1;\
-        }                                                               \
-        ret;                                                            \
-})
-static inline int
-store_reg(unsigned int result, unsigned int reg, struct pt_regs *regs)
-{
-        struct reg_window32 __user *win;
-        if (!reg)
-                return 0;
-        if (reg < 16) {
-                regs->u_regs[reg] = result;
-                return 0;
-        } else {
-                /* need to use put_user() in this case: */
-                win = (struct reg_window32 __user *) regs->u_regs[UREG_FP];
-                return (put_user(result, &win->locals[reg - 16]));
-        }
-}
-/* Should return 0 if mul/div emulation succeeded and SIGILL should
- * not be issued.
- */
-int do_user_muldiv(struct pt_regs *regs, unsigned long pc)
-{
-        unsigned int insn;
-        int inst;
-        unsigned int rs1, rs2, rdv;
-        if (!pc)
-                return -1; /* This happens to often, I think */
-        if (get_user (insn, (unsigned int __user *)pc))
-                return -1;
-        if ((insn & 0xc1400000) != 0x80400000)
-                return -1;
-        inst = ((insn >> 19) & 0xf);
-        if ((inst & 0xe) != 10 && (inst & 0xe) != 14)
-                return -1;
-        /* Now we know we have to do something with umul, smul, udiv or sdiv */
-        rs1 = (insn >> 14) & 0x1f;
-        rs2 = insn & 0x1f;
-        rdv = (insn >> 25) & 0x1f;
-        if (has_imm13(insn)) {
-                maybe_flush_windows(rs1, 0, rdv);
-                rs2 = sign_extend_imm13(insn);
-        } else {
-                maybe_flush_windows(rs1, rs2, rdv);
-                rs2 = fetch_reg(rs2, regs);
-        }
-        rs1 = fetch_reg(rs1, regs);
-        switch (inst) {
-        case 10: /* umul */
-#ifdef DEBUG_MULDIV     
-                printk ("unsigned muldiv: 0x%x * 0x%x = ", rs1, rs2);
-#endif          
-                __asm__ __volatile__ ("\n\t"
-                        "mov    %0, %%o0\n\t"
-                        "call   .umul\n\t"
-                        " mov   %1, %%o1\n\t"
-                        "mov    %%o0, %0\n\t"
-                        "mov    %%o1, %1\n\t"
-                        : "=r" (rs1), "=r" (rs2)
-                        : "0" (rs1), "1" (rs2)
-                        : "o0", "o1", "o2", "o3", "o4", "o5", "o7", "cc");
-#ifdef DEBUG_MULDIV
-                printk ("0x%x%08x\n", rs2, rs1);
-#endif
-                if (store_reg(rs1, rdv, regs))
-                        return -1;
-                regs->y = rs2;
-                break;
-        case 11: /* smul */
-#ifdef DEBUG_MULDIV
-                printk ("signed muldiv: 0x%x * 0x%x = ", rs1, rs2);
-#endif
-                __asm__ __volatile__ ("\n\t"
-                        "mov    %0, %%o0\n\t"
-                        "call   .mul\n\t"
-                        " mov   %1, %%o1\n\t"
-                        "mov    %%o0, %0\n\t"
-                        "mov    %%o1, %1\n\t"
-                        : "=r" (rs1), "=r" (rs2)
-                        : "0" (rs1), "1" (rs2)
-                        : "o0", "o1", "o2", "o3", "o4", "o5", "o7", "cc");
-#ifdef DEBUG_MULDIV
-                printk ("0x%x%08x\n", rs2, rs1);
-#endif
-                if (store_reg(rs1, rdv, regs))
-                        return -1;
-                regs->y = rs2;
-                break;
-        case 14: /* udiv */
-#ifdef DEBUG_MULDIV
-                printk ("unsigned muldiv: 0x%x%08x / 0x%x = ", regs->y, rs1, rs2);
-#endif
-                if (!rs2) {
-#ifdef DEBUG_MULDIV
-                        printk ("DIVISION BY ZERO\n");
-#endif
-                        handle_hw_divzero (regs, pc, regs->npc, regs->psr);
-                        return 0;
-                }
-                __asm__ __volatile__ ("\n\t"
-                        "mov    %2, %%o0\n\t"
-                        "mov    %0, %%o1\n\t"
-                        "mov    %%g0, %%o2\n\t"
-                        "call   __udivdi3\n\t"
-                        " mov   %1, %%o3\n\t"
-                        "mov    %%o1, %0\n\t"
-                        "mov    %%o0, %1\n\t"
-                        : "=r" (rs1), "=r" (rs2)
-                        : "r" (regs->y), "0" (rs1), "1" (rs2)
-                        : "o0", "o1", "o2", "o3", "o4", "o5", "o7",
-                          "g1", "g2", "g3", "cc");
-#ifdef DEBUG_MULDIV
-                printk ("0x%x\n", rs1);
-#endif
-                if (store_reg(rs1, rdv, regs))
-                        return -1;
-                break;
-        case 15: /* sdiv */
-#ifdef DEBUG_MULDIV
-                printk ("signed muldiv: 0x%x%08x / 0x%x = ", regs->y, rs1, rs2);
-#endif
-                if (!rs2) {
-#ifdef DEBUG_MULDIV
-                        printk ("DIVISION BY ZERO\n");
-#endif
-                        handle_hw_divzero (regs, pc, regs->npc, regs->psr);
-                        return 0;
-                }
-                __asm__ __volatile__ ("\n\t"
-                        "mov    %2, %%o0\n\t"
-                        "mov    %0, %%o1\n\t"
-                        "mov    %%g0, %%o2\n\t"
-                        "call   __divdi3\n\t"
-                        " mov   %1, %%o3\n\t"
-                        "mov    %%o1, %0\n\t"
-                        "mov    %%o0, %1\n\t"
-                        : "=r" (rs1), "=r" (rs2)
-                        : "r" (regs->y), "0" (rs1), "1" (rs2)
-                        : "o0", "o1", "o2", "o3", "o4", "o5", "o7",
-                          "g1", "g2", "g3", "cc");
-#ifdef DEBUG_MULDIV
-                printk ("0x%x\n", rs1);
-#endif
-                if (store_reg(rs1, rdv, regs))
-                        return -1;
-                break;
-        }
-        if (is_foocc (insn)) {
-                regs->psr &= ~PSR_ICC;
-                if ((inst & 0xe) == 14) {
-                        /* ?div */
-                        if (rs2) regs->psr |= PSR_V;
-                }
-                if (!rs1) regs->psr |= PSR_Z;
-                if (((int)rs1) < 0) regs->psr |= PSR_N;
-#ifdef DEBUG_MULDIV
-                printk ("psr muldiv: %08x\n", regs->psr);
-#endif
-        }
-        advance(regs);
-        return 0;
-}
diff --git a/arch/sparc/kernel/of_device_32.c b/arch/sparc/kernel/of_device_32.c
index 4ee8ce0d5d8d..185aa96fa5be 100644
--- a/arch/sparc/kernel/of_device_32.c
+++ b/arch/sparc/kernel/of_device_32.c
@@ -356,7 +356,7 @@ static struct platform_device * __init scan_one_device(struct device_node *dp,
                op->archdata.num_irqs = len / sizeof(struct linux_prom_irqs);
                for (i = 0; i < op->archdata.num_irqs; i++)
                        op->archdata.irqs[i] =
-                            sparc_irq_config.build_device_irq(op, intr[i].pri);
+                            sparc_config.build_device_irq(op, intr[i].pri);
        } else {
                const unsigned int *irq =
                        of_get_property(dp, "interrupts", &len);
@@ -365,7 +365,7 @@ static struct platform_device * __init scan_one_device(struct device_node *dp,
                        op->archdata.num_irqs = len / sizeof(unsigned int);
                        for (i = 0; i < op->archdata.num_irqs; i++)
                                op->archdata.irqs[i] =
-                                    sparc_irq_config.build_device_irq(op, irq[i]);
+                                    sparc_config.build_device_irq(op, irq[i]);
                } else {
                        op->archdata.num_irqs = 0;
                }
diff --git a/arch/sparc/kernel/pcic.c b/arch/sparc/kernel/pcic.c
index fcc148effaac..ded3f6090c3f 100644
--- a/arch/sparc/kernel/pcic.c
+++ b/arch/sparc/kernel/pcic.c
@@ -703,31 +703,28 @@ static void pcic_clear_clock_irq(void)
        pcic_timer_dummy = readl(pcic0.pcic_regs+PCI_SYS_LIMIT);
 }
-static irqreturn_t pcic_timer_handler (int irq, void *h)
+/* CPU frequency is 100 MHz, timer increments every 4 CPU clocks */
+#define USECS_PER_JIFFY  (1000000 / HZ)
+#define TICK_TIMER_LIMIT ((100 * 1000000 / 4) / HZ)
+static unsigned int pcic_cycles_offset(void)
 {
-        pcic_clear_clock_irq();
+        u32 value, count;
-        xtime_update(1);
-#ifndef CONFIG_SMP
-        update_process_times(user_mode(get_irq_regs()));
-#endif
-        return IRQ_HANDLED;
-}
-#define USECS_PER_JIFFY  10000  /* We have 100HZ "standard" timer for sparc */
+        value = readl(pcic0.pcic_regs + PCI_SYS_COUNTER);
-#define TICK_TIMER_LIMIT ((100*1000000/4)/100)
+        count = value & ~PCI_SYS_COUNTER_OVERFLOW;
-u32 pci_gettimeoffset(void)
+        if (value & PCI_SYS_COUNTER_OVERFLOW)
-{
+                count += TICK_TIMER_LIMIT;
        /*
-         * We divide all by 100
+         * We divide all by HZ
         * to have microsecond resolution and to avoid overflow
         */
-        unsigned long count =
+        count = ((count / HZ) * USECS_PER_JIFFY) / (TICK_TIMER_LIMIT / HZ);
-            readl(pcic0.pcic_regs+PCI_SYS_COUNTER) & ~PCI_SYS_COUNTER_OVERFLOW;
-        count = ((count/100)*USECS_PER_JIFFY) / (TICK_TIMER_LIMIT/100);
-        return count * 1000;
-}
+        /* Coordinate with the sparc_config.clock_rate setting */
+        return count * 2;
+}
 void __init pci_time_init(void)
 {
@@ -736,9 +733,16 @@ void __init pci_time_init(void)
        int timer_irq, irq;
        int err;
-        do_arch_gettimeoffset = pci_gettimeoffset;
+#ifndef CONFIG_SMP
+        /*
-        btfixup();
+         * The clock_rate is in SBUS dimension.
+         * We take into account this in pcic_cycles_offset()
+         */
+        sparc_config.clock_rate = SBUS_CLOCK_RATE / HZ;
+        sparc_config.features |= FEAT_L10_CLOCKEVENT;
+#endif
+        sparc_config.features |= FEAT_L10_CLOCKSOURCE;
+        sparc_config.get_cycles_offset = pcic_cycles_offset;
        writel (TICK_TIMER_LIMIT, pcic->pcic_regs+PCI_SYS_LIMIT);
        /* PROM should set appropriate irq */
@@ -747,7 +751,7 @@ void __init pci_time_init(void)
        writel (PCI_COUNTER_IRQ_SET(timer_irq, 0),
                pcic->pcic_regs+PCI_COUNTER_IRQ);
        irq = pcic_build_device_irq(NULL, timer_irq);
-        err = request_irq(irq, pcic_timer_handler,
+        err = request_irq(irq, timer_interrupt,
                          IRQF_TIMER, "timer", NULL);
        if (err) {
                prom_printf("time_init: unable to attach IRQ%d\n", timer_irq);
@@ -875,10 +879,9 @@ static void pcic_load_profile_irq(int cpu, unsigned int limit)
 void __init sun4m_pci_init_IRQ(void)
 {
-        sparc_irq_config.build_device_irq = pcic_build_device_irq;
+        sparc_config.build_device_irq = pcic_build_device_irq;
+        sparc_config.clear_clock_irq  = pcic_clear_clock_irq;
-        BTFIXUPSET_CALL(clear_clock_irq, pcic_clear_clock_irq, BTFIXUPCALL_NORM);
+        sparc_config.load_profile_irq = pcic_load_profile_irq;
-        BTFIXUPSET_CALL(load_profile_irq, pcic_load_profile_irq, BTFIXUPCALL_NORM);
 }
 int pcibios_assign_resource(struct pci_dev *pdev, int resource)
diff --git a/arch/sparc/kernel/perf_event.c b/arch/sparc/kernel/perf_event.c
index 28559ce5eeb5..5713957dcb8a 100644
--- a/arch/sparc/kernel/perf_event.c
+++ b/arch/sparc/kernel/perf_event.c
@@ -1296,8 +1296,6 @@ static int __kprobes perf_event_nmi_handler(struct notifier_block *self,
        regs = args->regs;
-        perf_sample_data_init(&data, 0);
        cpuc = &__get_cpu_var(cpu_hw_events);
        /* If the PMU has the TOE IRQ enable bits, we need to do a
@@ -1321,7 +1319,7 @@ static int __kprobes perf_event_nmi_handler(struct notifier_block *self,
                if (val & (1ULL << 31))
                        continue;
-                data.period = event->hw.last_period;
+                perf_sample_data_init(&data, 0, hwc->last_period);
                if (!sparc_perf_event_set_period(event, hwc, idx))
                        continue;
diff --git a/arch/sparc/kernel/process_32.c b/arch/sparc/kernel/process_32.c
index efa07542e85f..fe6787cc62fc 100644
--- a/arch/sparc/kernel/process_32.c
+++ b/arch/sparc/kernel/process_32.c
@@ -67,8 +67,6 @@ struct thread_info *current_set[NR_CPUS];
 #ifndef CONFIG_SMP
-#define SUN4C_FAULT_HIGH 100
 /*
 * the idle loop on a Sparc... ;)
 */
@@ -76,36 +74,6 @@ void cpu_idle(void)
 {
        /* endless idle loop with no priority at all */
        for (;;) {
-                if (ARCH_SUN4C) {
-                        static int count = HZ;
-                        static unsigned long last_jiffies;
-                        static unsigned long last_faults;
-                        static unsigned long fps;
-                        unsigned long now;
-                        unsigned long faults;
-                        extern unsigned long sun4c_kernel_faults;
-                        extern void sun4c_grow_kernel_ring(void);
-                        local_irq_disable();
-                        now = jiffies;
-                        count -= (now - last_jiffies);
-                        last_jiffies = now;
-                        if (count < 0) {
-                                count += HZ;
-                                faults = sun4c_kernel_faults;
-                                fps = (fps + (faults - last_faults)) >> 1;
-                                last_faults = faults;
-#if 0
-                                printk("kernel faults / second = %ld\n", fps);
-#endif
-                                if (fps >= SUN4C_FAULT_HIGH) {
-                                        sun4c_grow_kernel_ring();
-                                }
-                        }
-                        local_irq_enable();
-                }
                if (pm_idle) {
                        while (!need_resched())
                                (*pm_idle)();
@@ -114,7 +82,6 @@ void cpu_idle(void)
                                cpu_relax();
                }
                schedule_preempt_disabled();
-                check_pgt_cache();
        }
 }
@@ -137,7 +104,6 @@ void cpu_idle(void)
                                cpu_relax();
                }
                schedule_preempt_disabled();
-                check_pgt_cache();
        }
 }
@@ -179,88 +145,6 @@ void machine_power_off(void)
        machine_halt();
 }
-#if 0
-static DEFINE_SPINLOCK(sparc_backtrace_lock);
-void __show_backtrace(unsigned long fp)
-{
-        struct reg_window32 *rw;
-        unsigned long flags;
-        int cpu = smp_processor_id();
-        spin_lock_irqsave(&sparc_backtrace_lock, flags);
-        rw = (struct reg_window32 *)fp;
-        while(rw && (((unsigned long) rw) >= PAGE_OFFSET) &&
-            !(((unsigned long) rw) & 0x7)) {
-                printk("CPU[%d]: ARGS[%08lx,%08lx,%08lx,%08lx,%08lx,%08lx] "
-                       "FP[%08lx] CALLER[%08lx]: ", cpu,
-                       rw->ins[0], rw->ins[1], rw->ins[2], rw->ins[3],
-                       rw->ins[4], rw->ins[5],
-                       rw->ins[6],
-                       rw->ins[7]);
-                printk("%pS\n", (void *) rw->ins[7]);
-                rw = (struct reg_window32 *) rw->ins[6];
-        }
-        spin_unlock_irqrestore(&sparc_backtrace_lock, flags);
-}
-#define __SAVE __asm__ __volatile__("save %sp, -0x40, %sp\n\t")
-#define __RESTORE __asm__ __volatile__("restore %g0, %g0, %g0\n\t")
-#define __GET_FP(fp) __asm__ __volatile__("mov %%i6, %0" : "=r" (fp))
-void show_backtrace(void)
-{
-        unsigned long fp;
-        __SAVE; __SAVE; __SAVE; __SAVE;
-        __SAVE; __SAVE; __SAVE; __SAVE;
-        __RESTORE; __RESTORE; __RESTORE; __RESTORE;
-        __RESTORE; __RESTORE; __RESTORE; __RESTORE;
-        __GET_FP(fp);
-        __show_backtrace(fp);
-}
-#ifdef CONFIG_SMP
-void smp_show_backtrace_all_cpus(void)
-{
-        xc0((smpfunc_t) show_backtrace);
-        show_backtrace();
-}
-#endif
-void show_stackframe(struct sparc_stackf *sf)
-{
-        unsigned long size;
-        unsigned long *stk;
-        int i;
-        printk("l0: %08lx l1: %08lx l2: %08lx l3: %08lx "
-               "l4: %08lx l5: %08lx l6: %08lx l7: %08lx\n",
-               sf->locals[0], sf->locals[1], sf->locals[2], sf->locals[3],
-               sf->locals[4], sf->locals[5], sf->locals[6], sf->locals[7]);
-        printk("i0: %08lx i1: %08lx i2: %08lx i3: %08lx "
-               "i4: %08lx i5: %08lx fp: %08lx i7: %08lx\n",
-               sf->ins[0], sf->ins[1], sf->ins[2], sf->ins[3],
-               sf->ins[4], sf->ins[5], (unsigned long)sf->fp, sf->callers_pc);
-        printk("sp: %08lx x0: %08lx x1: %08lx x2: %08lx "
-               "x3: %08lx x4: %08lx x5: %08lx xx: %08lx\n",
-               (unsigned long)sf->structptr, sf->xargs[0], sf->xargs[1],
-               sf->xargs[2], sf->xargs[3], sf->xargs[4], sf->xargs[5],
-               sf->xxargs[0]);
-        size = ((unsigned long)sf->fp) - ((unsigned long)sf);
-        size -= STACKFRAME_SZ;
-        stk = (unsigned long *)((unsigned long)sf + STACKFRAME_SZ);
-        i = 0;
-        do {
-                printk("s%d: %08lx\n", i++, *stk++);
-        } while ((size -= sizeof(unsigned long)));
-}
-#endif
 void show_regs(struct pt_regs *r)
 {
        struct reg_window32 *rw = (struct reg_window32 *) r->u_regs[14];
diff --git a/arch/sparc/kernel/ptrace_64.c b/arch/sparc/kernel/ptrace_64.c
index 6f97c0767995..484dabac7045 100644
--- a/arch/sparc/kernel/ptrace_64.c
+++ b/arch/sparc/kernel/ptrace_64.c
@@ -1062,7 +1062,7 @@ asmlinkage int syscall_trace_enter(struct pt_regs *regs)
        int ret = 0;
        /* do the secure computing check first */
-        secure_computing(regs->u_regs[UREG_G1]);
+        secure_computing_strict(regs->u_regs[UREG_G1]);
        if (test_thread_flag(TIF_SYSCALL_TRACE))
                ret = tracehook_report_syscall_entry(regs);
diff --git a/arch/sparc/kernel/rtrap_32.S b/arch/sparc/kernel/rtrap_32.S
index 5f5f74c2c2ca..7abc24e2bf1a 100644
--- a/arch/sparc/kernel/rtrap_32.S
+++ b/arch/sparc/kernel/rtrap_32.S
@@ -128,13 +128,12 @@ rtrap_patch2:	and	%glob_tmp, 0xff, %glob_tmp
                wr      %glob_tmp, 0x0, %wim
-                                /* Here comes the architecture specific 
+        /* Here comes the architecture specific
-                                 * branch to the user stack checking routine
+         * branch to the user stack checking routine
-                                 * for return from traps.
+         * for return from traps.
-                                 */
+         */
-                                .globl  rtrap_mmu_patchme
+        b       srmmu_rett_stackchk
-rtrap_mmu_patchme:      b       sun4c_rett_stackchk
+         andcc  %fp, 0x7, %g0
-                                 andcc  %fp, 0x7, %g0   
 ret_trap_userwins_ok:
        LOAD_PT_PRIV(sp, t_psr, t_pc, t_npc)
@@ -225,69 +224,6 @@ ret_trap_user_stack_is_bolixed:
        b       signal_p
         ld     [%curptr + TI_FLAGS], %g2
-sun4c_rett_stackchk:
-        be      1f
-         and    %fp, 0xfff, %g1         ! delay slot
-        b       ret_trap_user_stack_is_bolixed + 0x4
-         wr     %t_wim, 0x0, %wim
-        /* See if we have to check the sanity of one page or two */
-1:
-        add     %g1, 0x38, %g1
-        sra     %fp, 29, %g2
-        add     %g2, 0x1, %g2
-        andncc  %g2, 0x1, %g0
-        be      1f
-         andncc %g1, 0xff8, %g0
-        /* %sp is in vma hole, yuck */
-        b       ret_trap_user_stack_is_bolixed + 0x4
-         wr     %t_wim, 0x0, %wim
-1:
-        be      sun4c_rett_onepage      /* Only one page to check */
-         lda    [%fp] ASI_PTE, %g2
-sun4c_rett_twopages:
-        add     %fp, 0x38, %g1
-        sra     %g1, 29, %g2
-        add     %g2, 0x1, %g2
-        andncc  %g2, 0x1, %g0
-        be      1f
-         lda    [%g1] ASI_PTE, %g2
-        /* Second page is in vma hole */
-        b       ret_trap_user_stack_is_bolixed + 0x4
-         wr     %t_wim, 0x0, %wim
-1:
-        srl     %g2, 29, %g2
-        andcc   %g2, 0x4, %g0
-        bne     sun4c_rett_onepage
-         lda    [%fp] ASI_PTE, %g2
-        /* Second page has bad perms */
-        b       ret_trap_user_stack_is_bolixed + 0x4
-         wr     %t_wim, 0x0, %wim
-sun4c_rett_onepage:
-        srl     %g2, 29, %g2
-        andcc   %g2, 0x4, %g0
-        bne,a   1f
-         restore %g0, %g0, %g0
-        /* A page had bad page permissions, losing... */
-        b       ret_trap_user_stack_is_bolixed + 0x4
-         wr     %t_wim, 0x0, %wim
-        /* Whee, things are ok, load the window and continue. */
-1:
-        LOAD_WINDOW(sp)
-        b       ret_trap_userwins_ok
-         save   %g0, %g0, %g0
        .globl  srmmu_rett_stackchk
 srmmu_rett_stackchk:
        bne     ret_trap_user_stack_is_bolixed
diff --git a/arch/sparc/kernel/rtrap_64.S b/arch/sparc/kernel/rtrap_64.S
index 77f1b95e0806..afa2a9e3d0a0 100644
--- a/arch/sparc/kernel/rtrap_64.S
+++ b/arch/sparc/kernel/rtrap_64.S
@@ -20,11 +20,6 @@
                .text
                .align                  32
-__handle_softirq:
-                call                    do_softirq
-                 nop
-                ba,a,pt                 %xcc, __handle_softirq_continue
-                 nop
 __handle_preemption:
                call                    schedule
                 wrpr                   %g0, RTRAP_PSTATE, %pstate
@@ -78,20 +73,8 @@ rtrap_nmi:	ldx			[%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
                .globl                  rtrap_irq, rtrap, irqsz_patchme, rtrap_xcall
 rtrap_irq:
 rtrap:
-#ifndef CONFIG_SMP
-                sethi                   %hi(__cpu_data), %l0
-                lduw                    [%l0 + %lo(__cpu_data)], %l1
-#else
-                sethi                   %hi(__cpu_data), %l0
-                or                      %l0, %lo(__cpu_data), %l0
-                lduw                    [%l0 + %g5], %l1
-#endif
-                cmp                     %l1, 0
                /* mm/ultra.S:xcall_report_regs KNOWS about this load. */
-                bne,pn                  %icc, __handle_softirq
+                ldx                     [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
-                 ldx                    [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
-__handle_softirq_continue:
 rtrap_xcall:
                sethi                   %hi(0xf << 20), %l4
                and                     %l1, %l4, %l4
diff --git a/arch/sparc/kernel/setup_32.c b/arch/sparc/kernel/setup_32.c
index d444468b27f6..c052313f4dc5 100644
--- a/arch/sparc/kernel/setup_32.c
+++ b/arch/sparc/kernel/setup_32.c
@@ -42,7 +42,6 @@
 #include <asm/vaddrs.h>
 #include <asm/mbus.h>
 #include <asm/idprom.h>
-#include <asm/machines.h>
 #include <asm/cpudata.h>
 #include <asm/setup.h>
 #include <asm/cacheflush.h>
@@ -106,7 +105,6 @@ unsigned long cmdline_memory_size __initdata = 0;
 /* which CPU booted us (0xff = not set) */
 unsigned char boot_cpu_id = 0xff; /* 0xff will make it into DATA section... */
-unsigned char boot_cpu_id4; /* boot_cpu_id << 2 */
 static void
 prom_console_write(struct console *con, const char *s, unsigned n)
@@ -182,13 +180,6 @@ static void __init boot_flags_init(char *commands)
        }
 }
-/* This routine will in the future do all the nasty prom stuff
- * to probe for the mmu type and its parameters, etc. This will
- * also be where SMP things happen.
- */
-extern void sun4c_probe_vac(void);
 extern unsigned short root_flags;
 extern unsigned short root_dev;
 extern unsigned short ram_flags;
@@ -200,6 +191,52 @@ extern int root_mountflags;
 char reboot_command[COMMAND_LINE_SIZE];
+struct cpuid_patch_entry {
+        unsigned int    addr;
+        unsigned int    sun4d[3];
+        unsigned int    leon[3];
+};
+extern struct cpuid_patch_entry __cpuid_patch, __cpuid_patch_end;
+static void __init per_cpu_patch(void)
+{
+        struct cpuid_patch_entry *p;
+        if (sparc_cpu_model == sun4m) {
+                /* Nothing to do, this is what the unpatched code
+                 * targets.
+                 */
+                return;
+        }
+        p = &__cpuid_patch;
+        while (p < &__cpuid_patch_end) {
+                unsigned long addr = p->addr;
+                unsigned int *insns;
+                switch (sparc_cpu_model) {
+                case sun4d:
+                        insns = &p->sun4d[0];
+                        break;
+                case sparc_leon:
+                        insns = &p->leon[0];
+                        break;
+                default:
+                        prom_printf("Unknown cpu type, halting.\n");
+                        prom_halt();
+                }
+                *(unsigned int *) (addr + 0) = insns[0];
+                flushi(addr + 0);
+                *(unsigned int *) (addr + 4) = insns[1];
+                flushi(addr + 4);
+                *(unsigned int *) (addr + 8) = insns[2];
+                flushi(addr + 8);
+                p++;
+        }
+}
 enum sparc_cpu sparc_cpu_model;
 EXPORT_SYMBOL(sparc_cpu_model);
@@ -225,10 +262,6 @@ void __init setup_arch(char **cmdline_p)
        /* Set sparc_cpu_model */
        sparc_cpu_model = sun_unknown;
-        if (!strcmp(&cputypval[0], "sun4 "))
-                sparc_cpu_model = sun4;
-        if (!strcmp(&cputypval[0], "sun4c"))
-                sparc_cpu_model = sun4c;
        if (!strcmp(&cputypval[0], "sun4m"))
                sparc_cpu_model = sun4m;
        if (!strcmp(&cputypval[0], "sun4s"))
@@ -244,12 +277,6 @@ void __init setup_arch(char **cmdline_p)
        printk("ARCH: ");
        switch(sparc_cpu_model) {
-        case sun4:
-                printk("SUN4\n");
-                break;
-        case sun4c:
-                printk("SUN4C\n");
-                break;
        case sun4m:
                printk("SUN4M\n");
                break;
@@ -275,8 +302,6 @@ void __init setup_arch(char **cmdline_p)
 #endif
        idprom_init();
-        if (ARCH_SUN4C)
-                sun4c_probe_vac();
        load_mmu();
        phys_base = 0xffffffffUL;
@@ -313,6 +338,9 @@ void __init setup_arch(char **cmdline_p)
        init_mm.context = (unsigned long) NO_CONTEXT;
        init_task.thread.kregs = &fake_swapper_regs;
+        /* Run-time patch instructions to match the cpu model */
+        per_cpu_patch();
        paging_init();
        smp_setup_cpu_possible_map();
diff --git a/arch/sparc/kernel/signal_32.c b/arch/sparc/kernel/signal_32.c
index 1e750e415d7a..ac8e66b50f07 100644
--- a/arch/sparc/kernel/signal_32.c
+++ b/arch/sparc/kernel/signal_32.c
@@ -217,12 +217,9 @@ segv:
 /* Checks if the fp is valid */
 static inline int invalid_frame_pointer(void __user *fp, int fplen)
 {
-        if ((((unsigned long) fp) & 7) ||
+        if ((((unsigned long) fp) & 7) || !__access_ok((unsigned long)fp, fplen))
-            !__access_ok((unsigned long)fp, fplen) ||
-            ((sparc_cpu_model == sun4 || sparc_cpu_model == sun4c) &&
-             ((unsigned long) fp < 0xe0000000 && (unsigned long) fp >= 0x20000000)))
                return 1;
-        
        return 0;
 }
diff --git a/arch/sparc/kernel/smp_32.c b/arch/sparc/kernel/smp_32.c
index f671e7fd6ddc..79db45e5134a 100644
--- a/arch/sparc/kernel/smp_32.c
+++ b/arch/sparc/kernel/smp_32.c
@@ -40,6 +40,8 @@ volatile unsigned long cpu_callin_map[NR_CPUS] __cpuinitdata = {0,};
 cpumask_t smp_commenced_mask = CPU_MASK_NONE;
+const struct sparc32_ipi_ops *sparc32_ipi_ops;
 /* The only guaranteed locking primitive available on all Sparc
 * processors is 'ldstub [%reg + immediate], %dest_reg' which atomically
 * places the current byte at the effective address into dest_reg and
@@ -85,14 +87,6 @@ void __init smp_cpus_done(unsigned int max_cpus)
                (bogosum/(5000/HZ))%100);
        switch(sparc_cpu_model) {
-        case sun4:
-                printk("SUN4\n");
-                BUG();
-                break;
-        case sun4c:
-                printk("SUN4C\n");
-                BUG();
-                break;
        case sun4m:
                smp4m_smp_done();
                break;
@@ -132,7 +126,7 @@ void smp_send_reschedule(int cpu)
         * a single CPU. The trap handler needs only to do trap entry/return
         * to call schedule.
         */
-        BTFIXUP_CALL(smp_ipi_resched)(cpu);
+        sparc32_ipi_ops->resched(cpu);
 }
 void smp_send_stop(void)
@@ -142,7 +136,7 @@ void smp_send_stop(void)
 void arch_send_call_function_single_ipi(int cpu)
 {
        /* trigger one IPI single call on one CPU */
-        BTFIXUP_CALL(smp_ipi_single)(cpu);
+        sparc32_ipi_ops->single(cpu);
 }
 void arch_send_call_function_ipi_mask(const struct cpumask *mask)
@@ -151,7 +145,7 @@ void arch_send_call_function_ipi_mask(const struct cpumask *mask)
        /* trigger IPI mask call on each CPU */
        for_each_cpu(cpu, mask)
-                BTFIXUP_CALL(smp_ipi_mask_one)(cpu);
+                sparc32_ipi_ops->mask_one(cpu);
 }
 void smp_resched_interrupt(void)
@@ -179,150 +173,9 @@ void smp_call_function_interrupt(void)
        irq_exit();
 }
-void smp_flush_cache_all(void)
-{
-        xc0((smpfunc_t) BTFIXUP_CALL(local_flush_cache_all));
-        local_flush_cache_all();
-}
-void smp_flush_tlb_all(void)
-{
-        xc0((smpfunc_t) BTFIXUP_CALL(local_flush_tlb_all));
-        local_flush_tlb_all();
-}
-void smp_flush_cache_mm(struct mm_struct *mm)
-{
-        if(mm->context != NO_CONTEXT) {
-                cpumask_t cpu_mask;
-                cpumask_copy(&cpu_mask, mm_cpumask(mm));
-                cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
-                if (!cpumask_empty(&cpu_mask))
-                        xc1((smpfunc_t) BTFIXUP_CALL(local_flush_cache_mm), (unsigned long) mm);
-                local_flush_cache_mm(mm);
-        }
-}
-void smp_flush_tlb_mm(struct mm_struct *mm)
-{
-        if(mm->context != NO_CONTEXT) {
-                cpumask_t cpu_mask;
-                cpumask_copy(&cpu_mask, mm_cpumask(mm));
-                cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
-                if (!cpumask_empty(&cpu_mask)) {
-                        xc1((smpfunc_t) BTFIXUP_CALL(local_flush_tlb_mm), (unsigned long) mm);
-                        if(atomic_read(&mm->mm_users) == 1 && current->active_mm == mm)
-                                cpumask_copy(mm_cpumask(mm),
-                                             cpumask_of(smp_processor_id()));
-                }
-                local_flush_tlb_mm(mm);
-        }
-}
-void smp_flush_cache_range(struct vm_area_struct *vma, unsigned long start,
-                           unsigned long end)
-{
-        struct mm_struct *mm = vma->vm_mm;
-        if (mm->context != NO_CONTEXT) {
-                cpumask_t cpu_mask;
-                cpumask_copy(&cpu_mask, mm_cpumask(mm));
-                cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
-                if (!cpumask_empty(&cpu_mask))
-                        xc3((smpfunc_t) BTFIXUP_CALL(local_flush_cache_range), (unsigned long) vma, start, end);
-                local_flush_cache_range(vma, start, end);
-        }
-}
-void smp_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
-                         unsigned long end)
-{
-        struct mm_struct *mm = vma->vm_mm;
-        if (mm->context != NO_CONTEXT) {
-                cpumask_t cpu_mask;
-                cpumask_copy(&cpu_mask, mm_cpumask(mm));
-                cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
-                if (!cpumask_empty(&cpu_mask))
-                        xc3((smpfunc_t) BTFIXUP_CALL(local_flush_tlb_range), (unsigned long) vma, start, end);
-                local_flush_tlb_range(vma, start, end);
-        }
-}
-void smp_flush_cache_page(struct vm_area_struct *vma, unsigned long page)
-{
-        struct mm_struct *mm = vma->vm_mm;
-        if(mm->context != NO_CONTEXT) {
-                cpumask_t cpu_mask;
-                cpumask_copy(&cpu_mask, mm_cpumask(mm));
-                cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
-                if (!cpumask_empty(&cpu_mask))
-                        xc2((smpfunc_t) BTFIXUP_CALL(local_flush_cache_page), (unsigned long) vma, page);
-                local_flush_cache_page(vma, page);
-        }
-}
-void smp_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
-{
-        struct mm_struct *mm = vma->vm_mm;
-        if(mm->context != NO_CONTEXT) {
-                cpumask_t cpu_mask;
-                cpumask_copy(&cpu_mask, mm_cpumask(mm));
-                cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
-                if (!cpumask_empty(&cpu_mask))
-                        xc2((smpfunc_t) BTFIXUP_CALL(local_flush_tlb_page), (unsigned long) vma, page);
-                local_flush_tlb_page(vma, page);
-        }
-}
-void smp_flush_page_to_ram(unsigned long page)
-{
-        /* Current theory is that those who call this are the one's
-         * who have just dirtied their cache with the pages contents
-         * in kernel space, therefore we only run this on local cpu.
-         *
-         * XXX This experiment failed, research further... -DaveM
-         */
-#if 1
-        xc1((smpfunc_t) BTFIXUP_CALL(local_flush_page_to_ram), page);
-#endif
-        local_flush_page_to_ram(page);
-}
-void smp_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr)
-{
-        cpumask_t cpu_mask;
-        cpumask_copy(&cpu_mask, mm_cpumask(mm));
-        cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
-        if (!cpumask_empty(&cpu_mask))
-                xc2((smpfunc_t) BTFIXUP_CALL(local_flush_sig_insns), (unsigned long) mm, insn_addr);
-        local_flush_sig_insns(mm, insn_addr);
-}
-extern unsigned int lvl14_resolution;
-/* /proc/profile writes can call this, don't __init it please. */
-static DEFINE_SPINLOCK(prof_setup_lock);
 int setup_profiling_timer(unsigned int multiplier)
 {
-        int i;
+        return -EINVAL;
-        unsigned long flags;
-        /* Prevent level14 ticker IRQ flooding. */
-        if((!multiplier) || (lvl14_resolution / multiplier) < 500)
-                return -EINVAL;
-        spin_lock_irqsave(&prof_setup_lock, flags);
-        for_each_possible_cpu(i) {
-                load_profile_irq(i, lvl14_resolution / multiplier);
-                prof_multiplier(i) = multiplier;
-        }
-        spin_unlock_irqrestore(&prof_setup_lock, flags);
-        return 0;
 }
 void __init smp_prepare_cpus(unsigned int max_cpus)
@@ -345,14 +198,6 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
        smp_store_cpu_info(boot_cpu_id);
        switch(sparc_cpu_model) {
-        case sun4:
-                printk("SUN4\n");
-                BUG();
-                break;
-        case sun4c:
-                printk("SUN4C\n");
-                BUG();
-                break;
        case sun4m:
                smp4m_boot_cpus();
                break;
@@ -411,29 +256,21 @@ void __init smp_prepare_boot_cpu(void)
        set_cpu_possible(cpuid, true);
 }
-int __cpuinit __cpu_up(unsigned int cpu)
+int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *tidle)
 {
-        extern int __cpuinit smp4m_boot_one_cpu(int);
+        extern int __cpuinit smp4m_boot_one_cpu(int, struct task_struct *);
-        extern int __cpuinit smp4d_boot_one_cpu(int);
+        extern int __cpuinit smp4d_boot_one_cpu(int, struct task_struct *);
        int ret=0;
        switch(sparc_cpu_model) {
-        case sun4:
-                printk("SUN4\n");
-                BUG();
-                break;
-        case sun4c:
-                printk("SUN4C\n");
-                BUG();
-                break;
        case sun4m:
-                ret = smp4m_boot_one_cpu(cpu);
+                ret = smp4m_boot_one_cpu(cpu, tidle);
                break;
        case sun4d:
-                ret = smp4d_boot_one_cpu(cpu);
+                ret = smp4d_boot_one_cpu(cpu, tidle);
                break;
        case sparc_leon:
-                ret = leon_boot_one_cpu(cpu);
+                ret = leon_boot_one_cpu(cpu, tidle);
                break;
        case sun4e:
                printk("SUN4E\n");
diff --git a/arch/sparc/kernel/smp_64.c b/arch/sparc/kernel/smp_64.c
index 3b1bd7c50164..f591598d92f6 100644
--- a/arch/sparc/kernel/smp_64.c
+++ b/arch/sparc/kernel/smp_64.c
@@ -343,21 +343,17 @@ extern unsigned long sparc64_cpu_startup;
 */
 static struct thread_info *cpu_new_thread = NULL;
-static int __cpuinit smp_boot_one_cpu(unsigned int cpu)
+static int __cpuinit smp_boot_one_cpu(unsigned int cpu, struct task_struct *idle)
 {
        unsigned long entry =
                (unsigned long)(&sparc64_cpu_startup);
        unsigned long cookie =
                (unsigned long)(&cpu_new_thread);
-        struct task_struct *p;
        void *descr = NULL;
        int timeout, ret;
-        p = fork_idle(cpu);
-        if (IS_ERR(p))
-                return PTR_ERR(p);
        callin_flag = 0;
-        cpu_new_thread = task_thread_info(p);
+        cpu_new_thread = task_thread_info(idle);
        if (tlb_type == hypervisor) {
 #if defined(CONFIG_SUN_LDOMS) && defined(CONFIG_HOTPLUG_CPU)
@@ -1227,9 +1223,9 @@ void __devinit smp_fill_in_sib_core_maps(void)
        }
 }
-int __cpuinit __cpu_up(unsigned int cpu)
+int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *tidle)
 {
-        int ret = smp_boot_one_cpu(cpu);
+        int ret = smp_boot_one_cpu(cpu, tidle);
        if (!ret) {
                cpumask_set_cpu(cpu, &smp_commenced_mask);
diff --git a/arch/sparc/kernel/sparc_ksyms_32.c b/arch/sparc/kernel/sparc_ksyms_32.c
index baeab8720237..e521c54560f9 100644
--- a/arch/sparc/kernel/sparc_ksyms_32.c
+++ b/arch/sparc/kernel/sparc_ksyms_32.c
@@ -28,19 +28,5 @@ EXPORT_SYMBOL(__ndelay);
 EXPORT_SYMBOL(__ret_efault);
 EXPORT_SYMBOL(empty_zero_page);
-/* Defined using magic */
-#ifndef CONFIG_SMP
-EXPORT_SYMBOL(BTFIXUP_CALL(___xchg32));
-#else
-EXPORT_SYMBOL(BTFIXUP_CALL(__hard_smp_processor_id));
-#endif
-EXPORT_SYMBOL(BTFIXUP_CALL(mmu_unlockarea));
-EXPORT_SYMBOL(BTFIXUP_CALL(mmu_lockarea));
-EXPORT_SYMBOL(BTFIXUP_CALL(mmu_get_scsi_sgl));
-EXPORT_SYMBOL(BTFIXUP_CALL(mmu_get_scsi_one));
-EXPORT_SYMBOL(BTFIXUP_CALL(mmu_release_scsi_sgl));
-EXPORT_SYMBOL(BTFIXUP_CALL(mmu_release_scsi_one));
-EXPORT_SYMBOL(BTFIXUP_CALL(pgprot_noncached));
 /* Exporting a symbol from /init/main.c */
 EXPORT_SYMBOL(saved_command_line);
diff --git a/arch/sparc/kernel/sun4c_irq.c b/arch/sparc/kernel/sun4c_irq.c
deleted file mode 100644
index f6bf25a2ff80..000000000000
--- a/arch/sparc/kernel/sun4c_irq.c
+++ /dev/null
@@ -1,264 +0,0 @@
-/*
- * sun4c irq support
- *
- *  djhr: Hacked out of irq.c into a CPU dependent version.
- *
- *  Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
- *  Copyright (C) 1995 Miguel de Icaza (miguel@nuclecu.unam.mx)
- *  Copyright (C) 1995 Pete A. Zaitcev (zaitcev@yahoo.com)
- *  Copyright (C) 1996 Dave Redman (djhr@tadpole.co.uk)
- */
-#include <linux/init.h>
-#include <asm/oplib.h>
-#include <asm/timer.h>
-#include <asm/irq.h>
-#include <asm/io.h>
-#include "irq.h"
-/* Sun4c interrupts are typically laid out as follows:
- *
- *  1 - Software interrupt, SBUS level 1
- *  2 - SBUS level 2
- *  3 - ESP SCSI, SBUS level 3
- *  4 - Software interrupt
- *  5 - Lance ethernet, SBUS level 4
- *  6 - Software interrupt
- *  7 - Graphics card, SBUS level 5
- *  8 - SBUS level 6
- *  9 - SBUS level 7
- * 10 - Counter timer
- * 11 - Floppy
- * 12 - Zilog uart
- * 13 - CS4231 audio
- * 14 - Profiling timer
- * 15 - NMI
- *
- * The interrupt enable bits in the interrupt mask register are
- * really only used to enable/disable the timer interrupts, and
- * for signalling software interrupts.  There is also a master
- * interrupt enable bit in this register.
- *
- * Interrupts are enabled by setting the SUN4C_INT_* bits, they
- * are disabled by clearing those bits.
- */
-/*
- * Bit field defines for the interrupt registers on various
- * Sparc machines.
- */
-/* The sun4c interrupt register. */
-#define SUN4C_INT_ENABLE  0x01     /* Allow interrupts. */
-#define SUN4C_INT_E14     0x80     /* Enable level 14 IRQ. */
-#define SUN4C_INT_E10     0x20     /* Enable level 10 IRQ. */
-#define SUN4C_INT_E8      0x10     /* Enable level 8 IRQ. */
-#define SUN4C_INT_E6      0x08     /* Enable level 6 IRQ. */
-#define SUN4C_INT_E4      0x04     /* Enable level 4 IRQ. */
-#define SUN4C_INT_E1      0x02     /* Enable level 1 IRQ. */
-/*
- * Pointer to the interrupt enable byte
- * Used by entry.S
- */
-unsigned char __iomem *interrupt_enable;
-static void sun4c_mask_irq(struct irq_data *data)
-{
-        unsigned long mask = (unsigned long)data->chip_data;
-        if (mask) {
-                unsigned long flags;
-                local_irq_save(flags);
-                mask = sbus_readb(interrupt_enable) & ~mask;
-                sbus_writeb(mask, interrupt_enable);
-                local_irq_restore(flags);
-        }
-}
-static void sun4c_unmask_irq(struct irq_data *data)
-{
-        unsigned long mask = (unsigned long)data->chip_data;
-        if (mask) {
-                unsigned long flags;
-                local_irq_save(flags);
-                mask = sbus_readb(interrupt_enable) | mask;
-                sbus_writeb(mask, interrupt_enable);
-                local_irq_restore(flags);
-        }
-}
-static unsigned int sun4c_startup_irq(struct irq_data *data)
-{
-        irq_link(data->irq);
-        sun4c_unmask_irq(data);
-        return 0;
-}
-static void sun4c_shutdown_irq(struct irq_data *data)
-{
-        sun4c_mask_irq(data);
-        irq_unlink(data->irq);
-}
-static struct irq_chip sun4c_irq = {
-        .name           = "sun4c",
-        .irq_startup    = sun4c_startup_irq,
-        .irq_shutdown   = sun4c_shutdown_irq,
-        .irq_mask       = sun4c_mask_irq,
-        .irq_unmask     = sun4c_unmask_irq,
-};
-static unsigned int sun4c_build_device_irq(struct platform_device *op,
-                                           unsigned int real_irq)
-{
-         unsigned int irq;
-        if (real_irq >= 16) {
-                prom_printf("Bogus sun4c IRQ %u\n", real_irq);
-                prom_halt();
-        }
-        irq = irq_alloc(real_irq, real_irq);
-        if (irq) {
-                unsigned long mask = 0UL;
-                switch (real_irq) {
-                case 1:
-                        mask = SUN4C_INT_E1;
-                        break;
-                case 8:
-                        mask = SUN4C_INT_E8;
-                        break;
-                case 10:
-                        mask = SUN4C_INT_E10;
-                        break;
-                case 14:
-                        mask = SUN4C_INT_E14;
-                        break;
-                default:
-                        /* All the rest are either always enabled,
-                         * or are for signalling software interrupts.
-                         */
-                        break;
-                }
-                irq_set_chip_and_handler_name(irq, &sun4c_irq,
-                                              handle_level_irq, "level");
-                irq_set_chip_data(irq, (void *)mask);
-        }
-        return irq;
-}
-struct sun4c_timer_info {
-        u32             l10_count;
-        u32             l10_limit;
-        u32             l14_count;
-        u32             l14_limit;
-};
-static struct sun4c_timer_info __iomem *sun4c_timers;
-static void sun4c_clear_clock_irq(void)
-{
-        sbus_readl(&sun4c_timers->l10_limit);
-}
-static void sun4c_load_profile_irq(int cpu, unsigned int limit)
-{
-        /* Errm.. not sure how to do this.. */
-}
-static void __init sun4c_init_timers(irq_handler_t counter_fn)
-{
-        const struct linux_prom_irqs *prom_irqs;
-        struct device_node *dp;
-        unsigned int irq;
-        const u32 *addr;
-        int err;
-        dp = of_find_node_by_name(NULL, "counter-timer");
-        if (!dp) {
-                prom_printf("sun4c_init_timers: Unable to find counter-timer\n");
-                prom_halt();
-        }
-        addr = of_get_property(dp, "address", NULL);
-        if (!addr) {
-                prom_printf("sun4c_init_timers: No address property\n");
-                prom_halt();
-        }
-        sun4c_timers = (void __iomem *) (unsigned long) addr[0];
-        prom_irqs = of_get_property(dp, "intr", NULL);
-        of_node_put(dp);
-        if (!prom_irqs) {
-                prom_printf("sun4c_init_timers: No intr property\n");
-                prom_halt();
-        }
-        /* Have the level 10 timer tick at 100HZ.  We don't touch the
-         * level 14 timer limit since we are letting the prom handle
-         * them until we have a real console driver so L1-A works.
-         */
-        sbus_writel((((1000000/HZ) + 1) << 10), &sun4c_timers->l10_limit);
-        master_l10_counter = &sun4c_timers->l10_count;
-        irq = sun4c_build_device_irq(NULL, prom_irqs[0].pri);
-        err = request_irq(irq, counter_fn, IRQF_TIMER, "timer", NULL);
-        if (err) {
-                prom_printf("sun4c_init_timers: request_irq() fails with %d\n", err);
-                prom_halt();
-        }
-        /* disable timer interrupt */
-        sun4c_mask_irq(irq_get_irq_data(irq));
-}
-#ifdef CONFIG_SMP
-static void sun4c_nop(void)
-{
-}
-#endif
-void __init sun4c_init_IRQ(void)
-{
-        struct device_node *dp;
-        const u32 *addr;
-        dp = of_find_node_by_name(NULL, "interrupt-enable");
-        if (!dp) {
-                prom_printf("sun4c_init_IRQ: Unable to find interrupt-enable\n");
-                prom_halt();
-        }
-        addr = of_get_property(dp, "address", NULL);
-        of_node_put(dp);
-        if (!addr) {
-                prom_printf("sun4c_init_IRQ: No address property\n");
-                prom_halt();
-        }
-        interrupt_enable = (void __iomem *) (unsigned long) addr[0];
-        BTFIXUPSET_CALL(clear_clock_irq, sun4c_clear_clock_irq, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(load_profile_irq, sun4c_load_profile_irq, BTFIXUPCALL_NOP);
-        sparc_irq_config.init_timers      = sun4c_init_timers;
-        sparc_irq_config.build_device_irq = sun4c_build_device_irq;
-#ifdef CONFIG_SMP
-        BTFIXUPSET_CALL(set_cpu_int, sun4c_nop, BTFIXUPCALL_NOP);
-        BTFIXUPSET_CALL(clear_cpu_int, sun4c_nop, BTFIXUPCALL_NOP);
-        BTFIXUPSET_CALL(set_irq_udt, sun4c_nop, BTFIXUPCALL_NOP);
-#endif
-        sbus_writeb(SUN4C_INT_ENABLE, interrupt_enable);
-        /* Cannot enable interrupts until OBP ticker is disabled. */
-}
diff --git a/arch/sparc/kernel/sun4d_irq.c b/arch/sparc/kernel/sun4d_irq.c
index 1d13c5bda0b1..e490ac9327c7 100644
--- a/arch/sparc/kernel/sun4d_irq.c
+++ b/arch/sparc/kernel/sun4d_irq.c
@@ -15,6 +15,7 @@
 #include <asm/sbi.h>
 #include <asm/cacheflush.h>
 #include <asm/setup.h>
+#include <asm/oplib.h>
 #include "kernel.h"
 #include "irq.h"
@@ -243,19 +244,6 @@ struct irq_chip sun4d_irq = {
 };
 #ifdef CONFIG_SMP
-static void sun4d_set_cpu_int(int cpu, int level)
-{
-        sun4d_send_ipi(cpu, level);
-}
-static void sun4d_clear_ipi(int cpu, int level)
-{
-}
-static void sun4d_set_udt(int cpu)
-{
-}
 /* Setup IRQ distribution scheme. */
 void __init sun4d_distribute_irqs(void)
 {
@@ -282,7 +270,8 @@ static void sun4d_clear_clock_irq(void)
 static void sun4d_load_profile_irq(int cpu, unsigned int limit)
 {
-        bw_set_prof_limit(cpu, limit);
+        unsigned int value = limit ? timer_value(limit) : 0;
+        bw_set_prof_limit(cpu, value);
 }
 static void __init sun4d_load_profile_irqs(void)
@@ -418,12 +407,12 @@ static void __init sun4d_fixup_trap_table(void)
        trap_table->inst_two = lvl14_save[1];
        trap_table->inst_three = lvl14_save[2];
        trap_table->inst_four = lvl14_save[3];
-        local_flush_cache_all();
+        local_ops->cache_all();
        local_irq_restore(flags);
 #endif
 }
-static void __init sun4d_init_timers(irq_handler_t counter_fn)
+static void __init sun4d_init_timers(void)
 {
        struct device_node *dp;
        struct resource res;
@@ -466,12 +455,20 @@ static void __init sun4d_init_timers(irq_handler_t counter_fn)
                prom_halt();
        }
-        sbus_writel((((1000000/HZ) + 1) << 10), &sun4d_timers->l10_timer_limit);
+#ifdef CONFIG_SMP
+        sparc_config.cs_period = SBUS_CLOCK_RATE * 2;  /* 2 seconds */
+#else
+        sparc_config.cs_period = SBUS_CLOCK_RATE / HZ; /* 1/HZ sec  */
+        sparc_config.features |= FEAT_L10_CLOCKEVENT;
+#endif
+        sparc_config.features |= FEAT_L10_CLOCKSOURCE;
+        sbus_writel(timer_value(sparc_config.cs_period),
+                    &sun4d_timers->l10_timer_limit);
        master_l10_counter = &sun4d_timers->l10_cur_count;
        irq = sun4d_build_timer_irq(board, SUN4D_TIMER_IRQ);
-        err = request_irq(irq, counter_fn, IRQF_TIMER, "timer", NULL);
+        err = request_irq(irq, timer_interrupt, IRQF_TIMER, "timer", NULL);
        if (err) {
                prom_printf("sun4d_init_timers: request_irq() failed with %d\n",
                             err);
@@ -509,16 +506,11 @@ void __init sun4d_init_IRQ(void)
 {
        local_irq_disable();
-        BTFIXUPSET_CALL(clear_clock_irq, sun4d_clear_clock_irq, BTFIXUPCALL_NORM);
+        sparc_config.init_timers      = sun4d_init_timers;
-        BTFIXUPSET_CALL(load_profile_irq, sun4d_load_profile_irq, BTFIXUPCALL_NORM);
+        sparc_config.build_device_irq = sun4d_build_device_irq;
+        sparc_config.clock_rate       = SBUS_CLOCK_RATE;
+        sparc_config.clear_clock_irq  = sun4d_clear_clock_irq;
+        sparc_config.load_profile_irq = sun4d_load_profile_irq;
-        sparc_irq_config.init_timers      = sun4d_init_timers;
-        sparc_irq_config.build_device_irq = sun4d_build_device_irq;
-#ifdef CONFIG_SMP
-        BTFIXUPSET_CALL(set_cpu_int, sun4d_set_cpu_int, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(clear_cpu_int, sun4d_clear_ipi, BTFIXUPCALL_NOP);
-        BTFIXUPSET_CALL(set_irq_udt, sun4d_set_udt, BTFIXUPCALL_NOP);
-#endif
        /* Cannot enable interrupts until OBP ticker is disabled. */
 }
diff --git a/arch/sparc/kernel/sun4d_smp.c b/arch/sparc/kernel/sun4d_smp.c
index 540b2fec09f0..ddaea31de586 100644
--- a/arch/sparc/kernel/sun4d_smp.c
+++ b/arch/sparc/kernel/sun4d_smp.c
@@ -6,16 +6,20 @@
 * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
 */
+#include <linux/clockchips.h>
 #include <linux/interrupt.h>
 #include <linux/profile.h>
 #include <linux/delay.h>
+#include <linux/sched.h>
 #include <linux/cpu.h>
+#include <asm/cacheflush.h>
+#include <asm/switch_to.h>
+#include <asm/tlbflush.h>
+#include <asm/timer.h>
+#include <asm/oplib.h>
 #include <asm/sbi.h>
 #include <asm/mmu.h>
-#include <asm/tlbflush.h>
-#include <asm/switch_to.h>
-#include <asm/cacheflush.h>
 #include "kernel.h"
 #include "irq.h"
@@ -34,7 +38,6 @@ static inline unsigned long sun4d_swap(volatile unsigned long *ptr, unsigned lon
 }
 static void smp4d_ipi_init(void);
-static void smp_setup_percpu_timer(void);
 static unsigned char cpu_leds[32];
@@ -49,7 +52,7 @@ static inline void show_leds(int cpuid)
 void __cpuinit smp4d_callin(void)
 {
-        int cpuid = hard_smp4d_processor_id();
+        int cpuid = hard_smp_processor_id();
        unsigned long flags;
        /* Show we are alive */
@@ -59,8 +62,8 @@ void __cpuinit smp4d_callin(void)
        /* Enable level15 interrupt, disable level14 interrupt for now */
        cc_set_imsk((cc_get_imsk() & ~0x8000) | 0x4000);
-        local_flush_cache_all();
+        local_ops->cache_all();
-        local_flush_tlb_all();
+        local_ops->tlb_all();
        notify_cpu_starting(cpuid);
        /*
@@ -70,17 +73,17 @@ void __cpuinit smp4d_callin(void)
         * to call the scheduler code.
         */
        /* Get our local ticker going. */
-        smp_setup_percpu_timer();
+        register_percpu_ce(cpuid);
        calibrate_delay();
        smp_store_cpu_info(cpuid);
-        local_flush_cache_all();
+        local_ops->cache_all();
-        local_flush_tlb_all();
+        local_ops->tlb_all();
        /* Allow master to continue. */
        sun4d_swap((unsigned long *)&cpu_callin_map[cpuid], 1);
-        local_flush_cache_all();
+        local_ops->cache_all();
-        local_flush_tlb_all();
+        local_ops->tlb_all();
        while ((unsigned long)current_set[cpuid] < PAGE_OFFSET)
                barrier();
@@ -100,8 +103,8 @@ void __cpuinit smp4d_callin(void)
        atomic_inc(&init_mm.mm_count);
        current->active_mm = &init_mm;
-        local_flush_cache_all();
+        local_ops->cache_all();
-        local_flush_tlb_all();
+        local_ops->tlb_all();
        local_irq_enable();     /* We don't allow PIL 14 yet */
@@ -123,22 +126,17 @@ void __init smp4d_boot_cpus(void)
        smp4d_ipi_init();
        if (boot_cpu_id)
                current_set[0] = NULL;
-        smp_setup_percpu_timer();
+        local_ops->cache_all();
-        local_flush_cache_all();
 }
-int __cpuinit smp4d_boot_one_cpu(int i)
+int __cpuinit smp4d_boot_one_cpu(int i, struct task_struct *idle)
 {
        unsigned long *entry = &sun4d_cpu_startup;
-        struct task_struct *p;
        int timeout;
        int cpu_node;
        cpu_find_by_instance(i, &cpu_node, NULL);
-        /* Cook up an idler for this guy. */
+        current_set[i] = task_thread_info(idle);
-        p = fork_idle(i);
-        current_set[i] = task_thread_info(p);
        /*
         * Initialize the contexts table
         * Since the call to prom_startcpu() trashes the structure,
@@ -150,7 +148,7 @@ int __cpuinit smp4d_boot_one_cpu(int i)
        /* whirrr, whirrr, whirrrrrrrrr... */
        printk(KERN_INFO "Starting CPU %d at %p\n", i, entry);
-        local_flush_cache_all();
+        local_ops->cache_all();
        prom_startcpu(cpu_node,
                      &smp_penguin_ctable, 0, (char *)entry);
@@ -168,7 +166,7 @@ int __cpuinit smp4d_boot_one_cpu(int i)
                return -ENODEV;
        }
-        local_flush_cache_all();
+        local_ops->cache_all();
        return 0;
 }
@@ -185,7 +183,7 @@ void __init smp4d_smp_done(void)
                prev = &cpu_data(i).next;
        }
        *prev = first;
-        local_flush_cache_all();
+        local_ops->cache_all();
        /* Ok, they are spinning and ready to go. */
        smp_processors_ready = 1;
@@ -233,7 +231,20 @@ void sun4d_ipi_interrupt(void)
        }
 }
-static void smp4d_ipi_single(int cpu)
+/* +-------+-------------+-----------+------------------------------------+
+ * | bcast |  devid      |   sid     |              levels mask           |
+ * +-------+-------------+-----------+------------------------------------+
+ *  31      30         23 22       15 14                                 0
+ */
+#define IGEN_MESSAGE(bcast, devid, sid, levels) \
+        (((bcast) << 31) | ((devid) << 23) | ((sid) << 15) | (levels))
+static void sun4d_send_ipi(int cpu, int level)
+{
+        cc_set_igen(IGEN_MESSAGE(0, cpu << 3, 6 + ((level >> 1) & 7), 1 << (level - 1)));
+}
+static void sun4d_ipi_single(int cpu)
 {
        struct sun4d_ipi_work *work = &per_cpu(sun4d_ipi_work, cpu);
@@ -244,7 +255,7 @@ static void smp4d_ipi_single(int cpu)
        sun4d_send_ipi(cpu, SUN4D_IPI_IRQ);
 }
-static void smp4d_ipi_mask_one(int cpu)
+static void sun4d_ipi_mask_one(int cpu)
 {
        struct sun4d_ipi_work *work = &per_cpu(sun4d_ipi_work, cpu);
@@ -255,7 +266,7 @@ static void smp4d_ipi_mask_one(int cpu)
        sun4d_send_ipi(cpu, SUN4D_IPI_IRQ);
 }
-static void smp4d_ipi_resched(int cpu)
+static void sun4d_ipi_resched(int cpu)
 {
        struct sun4d_ipi_work *work = &per_cpu(sun4d_ipi_work, cpu);
@@ -280,7 +291,7 @@ static struct smp_funcall {
 static DEFINE_SPINLOCK(cross_call_lock);
 /* Cross calls must be serialized, at least currently. */
-static void smp4d_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1,
+static void sun4d_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1,
                             unsigned long arg2, unsigned long arg3,
                             unsigned long arg4)
 {
@@ -352,7 +363,7 @@ static void smp4d_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1,
 /* Running cross calls. */
 void smp4d_cross_call_irq(void)
 {
-        int i = hard_smp4d_processor_id();
+        int i = hard_smp_processor_id();
        ccall_info.processors_in[i] = 1;
        ccall_info.func(ccall_info.arg1, ccall_info.arg2, ccall_info.arg3,
@@ -363,7 +374,8 @@ void smp4d_cross_call_irq(void)
 void smp4d_percpu_timer_interrupt(struct pt_regs *regs)
 {
        struct pt_regs *old_regs;
-        int cpu = hard_smp4d_processor_id();
+        int cpu = hard_smp_processor_id();
+        struct clock_event_device *ce;
        static int cpu_tick[NR_CPUS];
        static char led_mask[] = { 0xe, 0xd, 0xb, 0x7, 0xb, 0xd };
@@ -379,45 +391,21 @@ void smp4d_percpu_timer_interrupt(struct pt_regs *regs)
                show_leds(cpu);
        }
-        profile_tick(CPU_PROFILING);
+        ce = &per_cpu(sparc32_clockevent, cpu);
-        if (!--prof_counter(cpu)) {
-                int user = user_mode(regs);
-                irq_enter();
+        irq_enter();
-                update_process_times(user);
+        ce->event_handler(ce);
-                irq_exit();
+        irq_exit();
-                prof_counter(cpu) = prof_multiplier(cpu);
-        }
        set_irq_regs(old_regs);
 }
-static void __cpuinit smp_setup_percpu_timer(void)
+static const struct sparc32_ipi_ops sun4d_ipi_ops = {
-{
+        .cross_call = sun4d_cross_call,
-        int cpu = hard_smp4d_processor_id();
+        .resched    = sun4d_ipi_resched,
+        .single     = sun4d_ipi_single,
-        prof_counter(cpu) = prof_multiplier(cpu) = 1;
+        .mask_one   = sun4d_ipi_mask_one,
-        load_profile_irq(cpu, lvl14_resolution);
+};
-}
-void __init smp4d_blackbox_id(unsigned *addr)
-{
-        int rd = *addr & 0x3e000000;
-        addr[0] = 0xc0800800 | rd;              /* lda [%g0] ASI_M_VIKING_TMP1, reg */
-        addr[1] = 0x01000000;                   /* nop */
-        addr[2] = 0x01000000;                   /* nop */
-}
-void __init smp4d_blackbox_current(unsigned *addr)
-{
-        int rd = *addr & 0x3e000000;
-        addr[0] = 0xc0800800 | rd;              /* lda [%g0] ASI_M_VIKING_TMP1, reg */
-        addr[2] = 0x81282002 | rd | (rd >> 11); /* sll reg, 2, reg */
-        addr[4] = 0x01000000;                   /* nop */
-}
 void __init sun4d_init_smp(void)
 {
@@ -426,14 +414,7 @@ void __init sun4d_init_smp(void)
        /* Patch ipi15 trap table */
        t_nmi[1] = t_nmi[1] + (linux_trap_ipi15_sun4d - linux_trap_ipi15_sun4m);
-        /* And set btfixup... */
+        sparc32_ipi_ops = &sun4d_ipi_ops;
-        BTFIXUPSET_BLACKBOX(hard_smp_processor_id, smp4d_blackbox_id);
-        BTFIXUPSET_BLACKBOX(load_current, smp4d_blackbox_current);
-        BTFIXUPSET_CALL(smp_cross_call, smp4d_cross_call, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(__hard_smp_processor_id, __smp4d_processor_id, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(smp_ipi_resched, smp4d_ipi_resched, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(smp_ipi_single, smp4d_ipi_single, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(smp_ipi_mask_one, smp4d_ipi_mask_one, BTFIXUPCALL_NORM);
        for (i = 0; i < NR_CPUS; i++) {
                ccall_info.processors_in[i] = 1;
diff --git a/arch/sparc/kernel/sun4m_irq.c b/arch/sparc/kernel/sun4m_irq.c
index e61165161dd3..c5ade9d27a1d 100644
--- a/arch/sparc/kernel/sun4m_irq.c
+++ b/arch/sparc/kernel/sun4m_irq.c
@@ -112,9 +112,6 @@ struct sun4m_handler_data {
 #define SUN4M_INT_E14           0x00000080
 #define SUN4M_INT_E10           0x00080000
-#define SUN4M_HARD_INT(x)       (0x000000001 << (x))
-#define SUN4M_SOFT_INT(x)       (0x000010000 << (x))
 #define SUN4M_INT_MASKALL       0x80000000        /* mask all interrupts */
 #define SUN4M_INT_MODULE_ERR    0x40000000        /* module error */
 #define SUN4M_INT_M2S_WRITE_ERR 0x20000000        /* write buffer error */
@@ -282,23 +279,6 @@ out:
        return irq;
 }
-#ifdef CONFIG_SMP
-static void sun4m_send_ipi(int cpu, int level)
-{
-        sbus_writel(SUN4M_SOFT_INT(level), &sun4m_irq_percpu[cpu]->set);
-}
-static void sun4m_clear_ipi(int cpu, int level)
-{
-        sbus_writel(SUN4M_SOFT_INT(level), &sun4m_irq_percpu[cpu]->clear);
-}
-static void sun4m_set_udt(int cpu)
-{
-        sbus_writel(cpu, &sun4m_irq_global->interrupt_target);
-}
-#endif
 struct sun4m_timer_percpu {
        u32             l14_limit;
        u32             l14_count;
@@ -318,9 +298,6 @@ struct sun4m_timer_global {
 static struct sun4m_timer_global __iomem *timers_global;
-unsigned int lvl14_resolution = (((1000000/HZ) + 1) << 10);
 static void sun4m_clear_clock_irq(void)
 {
        sbus_readl(&timers_global->l10_limit);
@@ -369,10 +346,11 @@ void sun4m_clear_profile_irq(int cpu)
 static void sun4m_load_profile_irq(int cpu, unsigned int limit)
 {
-        sbus_writel(limit, &timers_percpu[cpu]->l14_limit);
+        unsigned int value = limit ? timer_value(limit) : 0;
+        sbus_writel(value, &timers_percpu[cpu]->l14_limit);
 }
-static void __init sun4m_init_timers(irq_handler_t counter_fn)
+static void __init sun4m_init_timers(void)
 {
        struct device_node *dp = of_find_node_by_name(NULL, "counter");
        int i, err, len, num_cpu_timers;
@@ -402,13 +380,22 @@ static void __init sun4m_init_timers(irq_handler_t counter_fn)
        /* Every per-cpu timer works in timer mode */
        sbus_writel(0x00000000, &timers_global->timer_config);
-        sbus_writel((((1000000/HZ) + 1) << 10), &timers_global->l10_limit);
+#ifdef CONFIG_SMP
+        sparc_config.cs_period = SBUS_CLOCK_RATE * 2;  /* 2 seconds */
+        sparc_config.features |= FEAT_L14_ONESHOT;
+#else
+        sparc_config.cs_period = SBUS_CLOCK_RATE / HZ; /* 1/HZ sec  */
+        sparc_config.features |= FEAT_L10_CLOCKEVENT;
+#endif
+        sparc_config.features |= FEAT_L10_CLOCKSOURCE;
+        sbus_writel(timer_value(sparc_config.cs_period),
+                    &timers_global->l10_limit);
        master_l10_counter = &timers_global->l10_count;
        irq = sun4m_build_device_irq(NULL, SUN4M_TIMER_IRQ);
-        err = request_irq(irq, counter_fn, IRQF_TIMER, "timer", NULL);
+        err = request_irq(irq, timer_interrupt, IRQF_TIMER, "timer", NULL);
        if (err) {
                printk(KERN_ERR "sun4m_init_timers: Register IRQ error %d.\n",
                        err);
@@ -434,7 +421,7 @@ static void __init sun4m_init_timers(irq_handler_t counter_fn)
                trap_table->inst_two = lvl14_save[1];
                trap_table->inst_three = lvl14_save[2];
                trap_table->inst_four = lvl14_save[3];
-                local_flush_cache_all();
+                local_ops->cache_all();
                local_irq_restore(flags);
        }
 #endif
@@ -475,17 +462,12 @@ void __init sun4m_init_IRQ(void)
        if (num_cpu_iregs == 4)
                sbus_writel(0, &sun4m_irq_global->interrupt_target);
-        BTFIXUPSET_CALL(clear_clock_irq, sun4m_clear_clock_irq, BTFIXUPCALL_NORM);
+        sparc_config.init_timers      = sun4m_init_timers;
-        BTFIXUPSET_CALL(load_profile_irq, sun4m_load_profile_irq, BTFIXUPCALL_NORM);
+        sparc_config.build_device_irq = sun4m_build_device_irq;
+        sparc_config.clock_rate       = SBUS_CLOCK_RATE;
-        sparc_irq_config.init_timers = sun4m_init_timers;
+        sparc_config.clear_clock_irq  = sun4m_clear_clock_irq;
-        sparc_irq_config.build_device_irq = sun4m_build_device_irq;
+        sparc_config.load_profile_irq = sun4m_load_profile_irq;
-#ifdef CONFIG_SMP
-        BTFIXUPSET_CALL(set_cpu_int, sun4m_send_ipi, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(clear_cpu_int, sun4m_clear_ipi, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(set_irq_udt, sun4m_set_udt, BTFIXUPCALL_NORM);
-#endif
        /* Cannot enable interrupts until OBP ticker is disabled. */
 }
diff --git a/arch/sparc/kernel/sun4m_smp.c b/arch/sparc/kernel/sun4m_smp.c
index 02db9a0412ce..128af7304288 100644
--- a/arch/sparc/kernel/sun4m_smp.c
+++ b/arch/sparc/kernel/sun4m_smp.c
@@ -4,14 +4,18 @@
 * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
 */
+#include <linux/clockchips.h>
 #include <linux/interrupt.h>
 #include <linux/profile.h>
 #include <linux/delay.h>
+#include <linux/sched.h>
 #include <linux/cpu.h>
 #include <asm/cacheflush.h>
 #include <asm/switch_to.h>
 #include <asm/tlbflush.h>
+#include <asm/timer.h>
+#include <asm/oplib.h>
 #include "irq.h"
 #include "kernel.h"
@@ -30,26 +34,22 @@ swap_ulong(volatile unsigned long *ptr, unsigned long val)
        return val;
 }
-static void smp4m_ipi_init(void);
-static void smp_setup_percpu_timer(void);
 void __cpuinit smp4m_callin(void)
 {
        int cpuid = hard_smp_processor_id();
-        local_flush_cache_all();
+        local_ops->cache_all();
-        local_flush_tlb_all();
+        local_ops->tlb_all();
        notify_cpu_starting(cpuid);
-        /* Get our local ticker going. */
+        register_percpu_ce(cpuid);
-        smp_setup_percpu_timer();
        calibrate_delay();
        smp_store_cpu_info(cpuid);
-        local_flush_cache_all();
+        local_ops->cache_all();
-        local_flush_tlb_all();
+        local_ops->tlb_all();
        /*
         * Unblock the master CPU _only_ when the scheduler state
@@ -61,8 +61,8 @@ void __cpuinit smp4m_callin(void)
        swap_ulong(&cpu_callin_map[cpuid], 1);
        /* XXX: What's up with all the flushes? */
-        local_flush_cache_all();
+        local_ops->cache_all();
-        local_flush_tlb_all();
+        local_ops->tlb_all();
        /* Fix idle thread fields. */
        __asm__ __volatile__("ld [%0], %%g6\n\t"
@@ -86,23 +86,19 @@ void __cpuinit smp4m_callin(void)
 */
 void __init smp4m_boot_cpus(void)
 {
-        smp4m_ipi_init();
+        sun4m_unmask_profile_irq();
-        smp_setup_percpu_timer();
+        local_ops->cache_all();
-        local_flush_cache_all();
 }
-int __cpuinit smp4m_boot_one_cpu(int i)
+int __cpuinit smp4m_boot_one_cpu(int i, struct task_struct *idle)
 {
        unsigned long *entry = &sun4m_cpu_startup;
-        struct task_struct *p;
        int timeout;
        int cpu_node;
        cpu_find_by_mid(i, &cpu_node);
+        current_set[i] = task_thread_info(idle);
-        /* Cook up an idler for this guy. */
-        p = fork_idle(i);
-        current_set[i] = task_thread_info(p);
        /* See trampoline.S for details... */
        entry += ((i - 1) * 3);
@@ -117,7 +113,7 @@ int __cpuinit smp4m_boot_one_cpu(int i)
        /* whirrr, whirrr, whirrrrrrrrr... */
        printk(KERN_INFO "Starting CPU %d at %p\n", i, entry);
-        local_flush_cache_all();
+        local_ops->cache_all();
        prom_startcpu(cpu_node, &smp_penguin_ctable, 0, (char *)entry);
        /* wheee... it's going... */
@@ -132,7 +128,7 @@ int __cpuinit smp4m_boot_one_cpu(int i)
                return -ENODEV;
        }
-        local_flush_cache_all();
+        local_ops->cache_all();
        return 0;
 }
@@ -149,30 +145,29 @@ void __init smp4m_smp_done(void)
                prev = &cpu_data(i).next;
        }
        *prev = first;
-        local_flush_cache_all();
+        local_ops->cache_all();
        /* Ok, they are spinning and ready to go. */
 }
+static void sun4m_send_ipi(int cpu, int level)
-/* Initialize IPIs on the SUN4M SMP machine */
-static void __init smp4m_ipi_init(void)
 {
+        sbus_writel(SUN4M_SOFT_INT(level), &sun4m_irq_percpu[cpu]->set);
 }
-static void smp4m_ipi_resched(int cpu)
+static void sun4m_ipi_resched(int cpu)
 {
-        set_cpu_int(cpu, IRQ_IPI_RESCHED);
+        sun4m_send_ipi(cpu, IRQ_IPI_RESCHED);
 }
-static void smp4m_ipi_single(int cpu)
+static void sun4m_ipi_single(int cpu)
 {
-        set_cpu_int(cpu, IRQ_IPI_SINGLE);
+        sun4m_send_ipi(cpu, IRQ_IPI_SINGLE);
 }
-static void smp4m_ipi_mask_one(int cpu)
+static void sun4m_ipi_mask_one(int cpu)
 {
-        set_cpu_int(cpu, IRQ_IPI_MASK);
+        sun4m_send_ipi(cpu, IRQ_IPI_MASK);
 }
 static struct smp_funcall {
@@ -189,7 +184,7 @@ static struct smp_funcall {
 static DEFINE_SPINLOCK(cross_call_lock);
 /* Cross calls must be serialized, at least currently. */
-static void smp4m_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1,
+static void sun4m_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1,
                             unsigned long arg2, unsigned long arg3,
                             unsigned long arg4)
 {
@@ -216,7 +211,7 @@ static void smp4m_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1,
                                if (cpumask_test_cpu(i, &mask)) {
                                        ccall_info.processors_in[i] = 0;
                                        ccall_info.processors_out[i] = 0;
-                                        set_cpu_int(i, IRQ_CROSS_CALL);
+                                        sun4m_send_ipi(i, IRQ_CROSS_CALL);
                                } else {
                                        ccall_info.processors_in[i] = 1;
                                        ccall_info.processors_out[i] = 1;
@@ -260,64 +255,33 @@ void smp4m_cross_call_irq(void)
 void smp4m_percpu_timer_interrupt(struct pt_regs *regs)
 {
        struct pt_regs *old_regs;
+        struct clock_event_device *ce;
        int cpu = smp_processor_id();
        old_regs = set_irq_regs(regs);
-        sun4m_clear_profile_irq(cpu);
+        ce = &per_cpu(sparc32_clockevent, cpu);
-        profile_tick(CPU_PROFILING);
-        if (!--prof_counter(cpu)) {
+        if (ce->mode & CLOCK_EVT_MODE_PERIODIC)
-                int user = user_mode(regs);
+                sun4m_clear_profile_irq(cpu);
+        else
+                sparc_config.load_profile_irq(cpu, 0); /* Is this needless? */
-                irq_enter();
+        irq_enter();
-                update_process_times(user);
+        ce->event_handler(ce);
-                irq_exit();
+        irq_exit();
-                prof_counter(cpu) = prof_multiplier(cpu);
-        }
        set_irq_regs(old_regs);
 }
-static void __cpuinit smp_setup_percpu_timer(void)
+static const struct sparc32_ipi_ops sun4m_ipi_ops = {
-{
+        .cross_call = sun4m_cross_call,
-        int cpu = smp_processor_id();
+        .resched    = sun4m_ipi_resched,
+        .single     = sun4m_ipi_single,
-        prof_counter(cpu) = prof_multiplier(cpu) = 1;
+        .mask_one   = sun4m_ipi_mask_one,
-        load_profile_irq(cpu, lvl14_resolution);
+};
-        if (cpu == boot_cpu_id)
-                sun4m_unmask_profile_irq();
-}
-static void __init smp4m_blackbox_id(unsigned *addr)
-{
-        int rd = *addr & 0x3e000000;
-        int rs1 = rd >> 11;
-        addr[0] = 0x81580000 | rd;              /* rd %tbr, reg */
-        addr[1] = 0x8130200c | rd | rs1;        /* srl reg, 0xc, reg */
-        addr[2] = 0x80082003 | rd | rs1;        /* and reg, 3, reg */
-}
-static void __init smp4m_blackbox_current(unsigned *addr)
-{
-        int rd = *addr & 0x3e000000;
-        int rs1 = rd >> 11;
-        addr[0] = 0x81580000 | rd;              /* rd %tbr, reg */
-        addr[2] = 0x8130200a | rd | rs1;        /* srl reg, 0xa, reg */
-        addr[4] = 0x8008200c | rd | rs1;        /* and reg, 0xc, reg */
-}
 void __init sun4m_init_smp(void)
 {
-        BTFIXUPSET_BLACKBOX(hard_smp_processor_id, smp4m_blackbox_id);
+        sparc32_ipi_ops = &sun4m_ipi_ops;
-        BTFIXUPSET_BLACKBOX(load_current, smp4m_blackbox_current);
-        BTFIXUPSET_CALL(smp_cross_call, smp4m_cross_call, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(__hard_smp_processor_id, __smp4m_processor_id, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(smp_ipi_resched, smp4m_ipi_resched, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(smp_ipi_single, smp4m_ipi_single, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(smp_ipi_mask_one, smp4m_ipi_mask_one, BTFIXUPCALL_NORM);
 }
diff --git a/arch/sparc/kernel/sys_sparc_32.c b/arch/sparc/kernel/sys_sparc_32.c
index 42b282fa6112..627e89af1d71 100644
--- a/arch/sparc/kernel/sys_sparc_32.c
+++ b/arch/sparc/kernel/sys_sparc_32.c
@@ -53,8 +53,6 @@ unsigned long arch_get_unmapped_area(struct file *filp, unsigned long addr, unsi
        /* See asm-sparc/uaccess.h */
        if (len > TASK_SIZE - PAGE_SIZE)
                return -ENOMEM;
-        if (ARCH_SUN4C && len > 0x20000000)
-                return -ENOMEM;
        if (!addr)
                addr = TASK_UNMAPPED_BASE;
@@ -65,10 +63,6 @@ unsigned long arch_get_unmapped_area(struct file *filp, unsigned long addr, unsi
        for (vmm = find_vma(current->mm, addr); ; vmm = vmm->vm_next) {
                /* At this point:  (!vmm || addr < vmm->vm_end). */
-                if (ARCH_SUN4C && addr < 0xe0000000 && 0x20000000 - len < addr) {
-                        addr = PAGE_OFFSET;
-                        vmm = find_vma(current->mm, PAGE_OFFSET);
-                }
                if (TASK_SIZE - PAGE_SIZE - len < addr)
                        return -ENOMEM;
                if (!vmm || addr + len <= vmm->vm_start)
@@ -99,11 +93,6 @@ out:
 int sparc_mmap_check(unsigned long addr, unsigned long len)
 {
-        if (ARCH_SUN4C &&
-            (len > 0x20000000 ||
-             (addr < 0xe0000000 && addr + len > 0x20000000)))
-                return -EINVAL;
        /* See asm-sparc/uaccess.h */
        if (len > TASK_SIZE - PAGE_SIZE || addr + len > TASK_SIZE - PAGE_SIZE)
                return -EINVAL;
diff --git a/arch/sparc/kernel/sys_sparc_64.c b/arch/sparc/kernel/sys_sparc_64.c
index 232df9949530..3ee51f189a55 100644
--- a/arch/sparc/kernel/sys_sparc_64.c
+++ b/arch/sparc/kernel/sys_sparc_64.c
@@ -566,15 +566,10 @@ out:
 SYSCALL_DEFINE2(64_munmap, unsigned long, addr, size_t, len)
 {
-        long ret;
        if (invalid_64bit_range(addr, len))
                return -EINVAL;
-        down_write(&current->mm->mmap_sem);
+        return vm_munmap(addr, len);
-        ret = do_munmap(current->mm, addr, len);
-        up_write(&current->mm->mmap_sem);
-        return ret;
 }
 extern unsigned long do_mremap(unsigned long addr,
diff --git a/arch/sparc/kernel/systbls_64.S b/arch/sparc/kernel/systbls_64.S
index db86b1a0e9a9..3a58e0d66f51 100644
--- a/arch/sparc/kernel/systbls_64.S
+++ b/arch/sparc/kernel/systbls_64.S
@@ -74,7 +74,7 @@ sys_call_table32:
        .word sys_timer_delete, compat_sys_timer_create, sys_ni_syscall, compat_sys_io_setup, sys_io_destroy
 /*270*/ .word sys32_io_submit, sys_io_cancel, compat_sys_io_getevents, sys32_mq_open, sys_mq_unlink
        .word compat_sys_mq_timedsend, compat_sys_mq_timedreceive, compat_sys_mq_notify, compat_sys_mq_getsetattr, compat_sys_waitid
-/*280*/ .word sys32_tee, sys_add_key, sys_request_key, sys_keyctl, compat_sys_openat
+/*280*/ .word sys32_tee, sys_add_key, sys_request_key, compat_sys_keyctl, compat_sys_openat
        .word sys_mkdirat, sys_mknodat, sys_fchownat, compat_sys_futimesat, compat_sys_fstatat64
 /*290*/ .word sys_unlinkat, sys_renameat, sys_linkat, sys_symlinkat, sys_readlinkat
        .word sys_fchmodat, sys_faccessat, compat_sys_pselect6, compat_sys_ppoll, sys_unshare
diff --git a/arch/sparc/kernel/time_32.c b/arch/sparc/kernel/time_32.c
index 7d0c088e8aba..953641549e82 100644
--- a/arch/sparc/kernel/time_32.c
+++ b/arch/sparc/kernel/time_32.c
@@ -26,6 +26,8 @@
 #include <linux/rtc.h>
 #include <linux/rtc/m48t59.h>
 #include <linux/timex.h>
+#include <linux/clocksource.h>
+#include <linux/clockchips.h>
 #include <linux/init.h>
 #include <linux/pci.h>
 #include <linux/ioport.h>
@@ -40,13 +42,24 @@
 #include <asm/irq.h>
 #include <asm/io.h>
 #include <asm/idprom.h>
-#include <asm/machines.h>
 #include <asm/page.h>
 #include <asm/pcic.h>
 #include <asm/irq_regs.h>
+#include <asm/setup.h>
 #include "irq.h"
+static __cacheline_aligned_in_smp DEFINE_SEQLOCK(timer_cs_lock);
+static __volatile__ u64 timer_cs_internal_counter = 0;
+static char timer_cs_enabled = 0;
+static struct clock_event_device timer_ce;
+static char timer_ce_enabled = 0;
+#ifdef CONFIG_SMP
+DEFINE_PER_CPU(struct clock_event_device, sparc32_clockevent);
+#endif
 DEFINE_SPINLOCK(rtc_lock);
 EXPORT_SYMBOL(rtc_lock);
@@ -55,7 +68,6 @@ static int set_rtc_mmss(unsigned long);
 unsigned long profile_pc(struct pt_regs *regs)
 {
        extern char __copy_user_begin[], __copy_user_end[];
-        extern char __atomic_begin[], __atomic_end[];
        extern char __bzero_begin[], __bzero_end[];
        unsigned long pc = regs->pc;
@@ -63,8 +75,6 @@ unsigned long profile_pc(struct pt_regs *regs)
        if (in_lock_functions(pc) ||
            (pc >= (unsigned long) __copy_user_begin &&
             pc < (unsigned long) __copy_user_end) ||
-            (pc >= (unsigned long) __atomic_begin &&
-             pc < (unsigned long) __atomic_end) ||
            (pc >= (unsigned long) __bzero_begin &&
             pc < (unsigned long) __bzero_end))
                pc = regs->u_regs[UREG_RETPC];
@@ -75,36 +85,168 @@ EXPORT_SYMBOL(profile_pc);
 __volatile__ unsigned int *master_l10_counter;
-u32 (*do_arch_gettimeoffset)(void);
 int update_persistent_clock(struct timespec now)
 {
        return set_rtc_mmss(now.tv_sec);
 }
-/*
+irqreturn_t notrace timer_interrupt(int dummy, void *dev_id)
- * timer_interrupt() needs to keep up the real-time clock,
+{
- * as well as call the "xtime_update()" routine every clocktick
+        if (timer_cs_enabled) {
- */
+                write_seqlock(&timer_cs_lock);
+                timer_cs_internal_counter++;
+                sparc_config.clear_clock_irq();
+                write_sequnlock(&timer_cs_lock);
+        } else {
+                sparc_config.clear_clock_irq();
+        }
-#define TICK_SIZE (tick_nsec / 1000)
+        if (timer_ce_enabled)
+                timer_ce.event_handler(&timer_ce);
-static irqreturn_t timer_interrupt(int dummy, void *dev_id)
+        return IRQ_HANDLED;
+}
+static void timer_ce_set_mode(enum clock_event_mode mode,
+                              struct clock_event_device *evt)
 {
-#ifndef CONFIG_SMP
+        switch (mode) {
-        profile_tick(CPU_PROFILING);
+                case CLOCK_EVT_MODE_PERIODIC:
-#endif
+                case CLOCK_EVT_MODE_RESUME:
+                        timer_ce_enabled = 1;
+                        break;
+                case CLOCK_EVT_MODE_SHUTDOWN:
+                        timer_ce_enabled = 0;
+                        break;
+                default:
+                        break;
+        }
+        smp_mb();
+}
-        clear_clock_irq();
+static __init void setup_timer_ce(void)
+{
+        struct clock_event_device *ce = &timer_ce;
+        BUG_ON(smp_processor_id() != boot_cpu_id);
+        ce->name     = "timer_ce";
+        ce->rating   = 100;
+        ce->features = CLOCK_EVT_FEAT_PERIODIC;
+        ce->set_mode = timer_ce_set_mode;
+        ce->cpumask  = cpu_possible_mask;
+        ce->shift    = 32;
+        ce->mult     = div_sc(sparc_config.clock_rate, NSEC_PER_SEC,
+                              ce->shift);
+        clockevents_register_device(ce);
+}
-        xtime_update(1);
+static unsigned int sbus_cycles_offset(void)
+{
+        unsigned int val, offset;
-#ifndef CONFIG_SMP
+        val = *master_l10_counter;
-        update_process_times(user_mode(get_irq_regs()));
+        offset = (val >> TIMER_VALUE_SHIFT) & TIMER_VALUE_MASK;
-#endif
-        return IRQ_HANDLED;
+        /* Limit hit? */
+        if (val & TIMER_LIMIT_BIT)
+                offset += sparc_config.cs_period;
+        return offset;
+}
+static cycle_t timer_cs_read(struct clocksource *cs)
+{
+        unsigned int seq, offset;
+        u64 cycles;
+        do {
+                seq = read_seqbegin(&timer_cs_lock);
+                cycles = timer_cs_internal_counter;
+                offset = sparc_config.get_cycles_offset();
+        } while (read_seqretry(&timer_cs_lock, seq));
+        /* Count absolute cycles */
+        cycles *= sparc_config.cs_period;
+        cycles += offset;
+        return cycles;
+}
+static struct clocksource timer_cs = {
+        .name   = "timer_cs",
+        .rating = 100,
+        .read   = timer_cs_read,
+        .mask   = CLOCKSOURCE_MASK(64),
+        .shift  = 2,
+        .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+static __init int setup_timer_cs(void)
+{
+        timer_cs_enabled = 1;
+        timer_cs.mult = clocksource_hz2mult(sparc_config.clock_rate,
+                                            timer_cs.shift);
+        return clocksource_register(&timer_cs);
 }
+#ifdef CONFIG_SMP
+static void percpu_ce_setup(enum clock_event_mode mode,
+                        struct clock_event_device *evt)
+{
+        int cpu = __first_cpu(evt->cpumask);
+        switch (mode) {
+                case CLOCK_EVT_MODE_PERIODIC:
+                        sparc_config.load_profile_irq(cpu,
+                                                      SBUS_CLOCK_RATE / HZ);
+                        break;
+                case CLOCK_EVT_MODE_ONESHOT:
+                case CLOCK_EVT_MODE_SHUTDOWN:
+                case CLOCK_EVT_MODE_UNUSED:
+                        sparc_config.load_profile_irq(cpu, 0);
+                        break;
+                default:
+                        break;
+        }
+}
+static int percpu_ce_set_next_event(unsigned long delta,
+                                    struct clock_event_device *evt)
+{
+        int cpu = __first_cpu(evt->cpumask);
+        unsigned int next = (unsigned int)delta;
+        sparc_config.load_profile_irq(cpu, next);
+        return 0;
+}
+void register_percpu_ce(int cpu)
+{
+        struct clock_event_device *ce = &per_cpu(sparc32_clockevent, cpu);
+        unsigned int features = CLOCK_EVT_FEAT_PERIODIC;
+        if (sparc_config.features & FEAT_L14_ONESHOT)
+                features |= CLOCK_EVT_FEAT_ONESHOT;
+        ce->name           = "percpu_ce";
+        ce->rating         = 200;
+        ce->features       = features;
+        ce->set_mode       = percpu_ce_setup;
+        ce->set_next_event = percpu_ce_set_next_event;
+        ce->cpumask        = cpumask_of(cpu);
+        ce->shift          = 32;
+        ce->mult           = div_sc(sparc_config.clock_rate, NSEC_PER_SEC,
+                                    ce->shift);
+        ce->max_delta_ns   = clockevent_delta2ns(sparc_config.clock_rate, ce);
+        ce->min_delta_ns   = clockevent_delta2ns(100, ce);
+        clockevents_register_device(ce);
+}
+#endif
 static unsigned char mostek_read_byte(struct device *dev, u32 ofs)
 {
        struct platform_device *pdev = to_platform_device(dev);
@@ -195,38 +337,28 @@ static int __init clock_init(void)
 */
 fs_initcall(clock_init);
+static void __init sparc32_late_time_init(void)
-u32 sbus_do_gettimeoffset(void)
-{
-        unsigned long val = *master_l10_counter;
-        unsigned long usec = (val >> 10) & 0x1fffff;
-        /* Limit hit?  */
-        if (val & 0x80000000)
-                usec += 1000000 / HZ;
-        return usec * 1000;
-}
-u32 arch_gettimeoffset(void)
 {
-        if (unlikely(!do_arch_gettimeoffset))
+        if (sparc_config.features & FEAT_L10_CLOCKEVENT)
-                return 0;
+                setup_timer_ce();
-        return do_arch_gettimeoffset();
+        if (sparc_config.features & FEAT_L10_CLOCKSOURCE)
+                setup_timer_cs();
+#ifdef CONFIG_SMP
+        register_percpu_ce(smp_processor_id());
+#endif
 }
 static void __init sbus_time_init(void)
 {
-        do_arch_gettimeoffset = sbus_do_gettimeoffset;
+        sparc_config.get_cycles_offset = sbus_cycles_offset;
+        sparc_config.init_timers();
-        btfixup();
-        sparc_irq_config.init_timers(timer_interrupt);
 }
 void __init time_init(void)
 {
+        sparc_config.features = 0;
+        late_time_init = sparc32_late_time_init;
        if (pcic_present())
                pci_time_init();
        else
diff --git a/arch/sparc/kernel/trampoline_32.S b/arch/sparc/kernel/trampoline_32.S
index 691f484e03b3..7364ddc9e5aa 100644
--- a/arch/sparc/kernel/trampoline_32.S
+++ b/arch/sparc/kernel/trampoline_32.S
@@ -15,8 +15,8 @@
 #include <asm/contregs.h>
 #include <asm/thread_info.h>
-        .globl sun4m_cpu_startup, __smp4m_processor_id, __leon_processor_id
+        .globl sun4m_cpu_startup
-        .globl sun4d_cpu_startup, __smp4d_processor_id
+        .globl sun4d_cpu_startup
        __CPUINIT
        .align 4
@@ -94,24 +94,6 @@ smp_do_cpu_idle:
        call    cpu_panic
         nop
-__smp4m_processor_id:
-        rd      %tbr, %g2
-        srl     %g2, 12, %g2
-        and     %g2, 3, %g2
-        retl
-         mov    %g1, %o7
-__smp4d_processor_id:
-        lda     [%g0] ASI_M_VIKING_TMP1, %g2
-        retl
-         mov    %g1, %o7
-__leon_processor_id:
-        rd     %asr17,%g2
-        srl    %g2,28,%g2
-        retl
-         mov    %g1, %o7
 /* CPUID in bootbus can be found at PA 0xff0140000 */
 #define SUN4D_BOOTBUS_CPUID     0xf0140000
diff --git a/arch/sparc/kernel/traps_32.c b/arch/sparc/kernel/traps_32.c
index d2de21333146..a5785ea2a85d 100644
--- a/arch/sparc/kernel/traps_32.c
+++ b/arch/sparc/kernel/traps_32.c
@@ -120,8 +120,6 @@ void do_illegal_instruction(struct pt_regs *regs, unsigned long pc, unsigned lon
        printk("Ill instr. at pc=%08lx instruction is %08lx\n",
               regs->pc, *(unsigned long *)regs->pc);
 #endif
-        if (!do_user_muldiv (regs, pc))
-                return;
        info.si_signo = SIGILL;
        info.si_errno = 0;
diff --git a/arch/sparc/kernel/ttable_32.S b/arch/sparc/kernel/ttable_32.S
new file mode 100644
index 000000000000..8a7a96ca676f
--- /dev/null
+++ b/arch/sparc/kernel/ttable_32.S
@@ -0,0 +1,417 @@
+/* The Sparc trap table, bootloader gives us control at _start. */
+        __HEAD
+        .globl  _start
+_start:
+        .globl _stext
+_stext:
+        .globl  trapbase
+trapbase:
+#ifdef CONFIG_SMP
+trapbase_cpu0:
+#endif
+/* We get control passed to us here at t_zero. */
+t_zero: b gokernel; nop; nop; nop;
+t_tflt: SRMMU_TFAULT                        /* Inst. Access Exception        */
+t_bins: TRAP_ENTRY(0x2, bad_instruction)    /* Illegal Instruction           */
+t_pins: TRAP_ENTRY(0x3, priv_instruction)   /* Privileged Instruction        */
+t_fpd:  TRAP_ENTRY(0x4, fpd_trap_handler)   /* Floating Point Disabled       */
+t_wovf: WINDOW_SPILL                        /* Window Overflow               */
+t_wunf: WINDOW_FILL                         /* Window Underflow              */
+t_mna:  TRAP_ENTRY(0x7, mna_handler)        /* Memory Address Not Aligned    */
+t_fpe:  TRAP_ENTRY(0x8, fpe_trap_handler)   /* Floating Point Exception      */
+t_dflt: SRMMU_DFAULT                        /* Data Miss Exception           */
+t_tio:  TRAP_ENTRY(0xa, do_tag_overflow)    /* Tagged Instruction Ovrflw     */
+t_wpt:  TRAP_ENTRY(0xb, do_watchpoint)      /* Watchpoint Detected           */
+t_badc: BAD_TRAP(0xc) BAD_TRAP(0xd) BAD_TRAP(0xe) BAD_TRAP(0xf) BAD_TRAP(0x10)
+t_irq1: TRAP_ENTRY_INTERRUPT(1)             /* IRQ Software/SBUS Level 1     */
+t_irq2: TRAP_ENTRY_INTERRUPT(2)             /* IRQ SBUS Level 2              */
+t_irq3: TRAP_ENTRY_INTERRUPT(3)             /* IRQ SCSI/DMA/SBUS Level 3     */
+t_irq4: TRAP_ENTRY_INTERRUPT(4)             /* IRQ Software Level 4          */
+t_irq5: TRAP_ENTRY_INTERRUPT(5)             /* IRQ SBUS/Ethernet Level 5     */
+t_irq6: TRAP_ENTRY_INTERRUPT(6)             /* IRQ Software Level 6          */
+t_irq7: TRAP_ENTRY_INTERRUPT(7)             /* IRQ Video/SBUS Level 5        */
+t_irq8: TRAP_ENTRY_INTERRUPT(8)             /* IRQ SBUS Level 6              */
+t_irq9: TRAP_ENTRY_INTERRUPT(9)             /* IRQ SBUS Level 7              */
+t_irq10:TRAP_ENTRY_INTERRUPT(10)            /* IRQ Timer #1 (one we use)     */
+t_irq11:TRAP_ENTRY_INTERRUPT(11)            /* IRQ Floppy Intr.              */
+t_irq12:TRAP_ENTRY_INTERRUPT(12)            /* IRQ Zilog serial chip         */
+t_irq13:TRAP_ENTRY_INTERRUPT(13)            /* IRQ Audio Intr.               */
+t_irq14:TRAP_ENTRY_INTERRUPT(14)            /* IRQ Timer #2                  */
+        .globl  t_nmi
+t_nmi:  TRAP_ENTRY(0x1f, linux_trap_ipi15_sun4m)
+t_racc: TRAP_ENTRY(0x20, do_reg_access)     /* General Register Access Error */
+t_iacce:BAD_TRAP(0x21)                      /* Instr Access Error            */
+t_bad22:BAD_TRAP(0x22)
+        BAD_TRAP(0x23)
+t_cpdis:TRAP_ENTRY(0x24, do_cp_disabled)    /* Co-Processor Disabled         */
+t_uflsh:SKIP_TRAP(0x25, unimp_flush)        /* Unimplemented FLUSH inst.     */
+t_bad26:BAD_TRAP(0x26) BAD_TRAP(0x27)
+t_cpexc:TRAP_ENTRY(0x28, do_cp_exception)   /* Co-Processor Exception        */
+t_dacce:SRMMU_DFAULT                        /* Data Access Error             */
+t_hwdz: TRAP_ENTRY(0x2a, do_hw_divzero)     /* Division by zero, you lose... */
+t_dserr:BAD_TRAP(0x2b)                      /* Data Store Error              */
+t_daccm:BAD_TRAP(0x2c)                      /* Data Access MMU-Miss          */
+t_bad2d:BAD_TRAP(0x2d) BAD_TRAP(0x2e) BAD_TRAP(0x2f) BAD_TRAP(0x30) BAD_TRAP(0x31)
+t_bad32:BAD_TRAP(0x32) BAD_TRAP(0x33) BAD_TRAP(0x34) BAD_TRAP(0x35) BAD_TRAP(0x36)
+t_bad37:BAD_TRAP(0x37) BAD_TRAP(0x38) BAD_TRAP(0x39) BAD_TRAP(0x3a) BAD_TRAP(0x3b)
+t_iaccm:BAD_TRAP(0x3c)                      /* Instr Access MMU-Miss         */
+t_bad3d:BAD_TRAP(0x3d) BAD_TRAP(0x3e) BAD_TRAP(0x3f) BAD_TRAP(0x40) BAD_TRAP(0x41)
+t_bad42:BAD_TRAP(0x42) BAD_TRAP(0x43) BAD_TRAP(0x44) BAD_TRAP(0x45) BAD_TRAP(0x46)
+t_bad47:BAD_TRAP(0x47) BAD_TRAP(0x48) BAD_TRAP(0x49) BAD_TRAP(0x4a) BAD_TRAP(0x4b)
+t_bad4c:BAD_TRAP(0x4c) BAD_TRAP(0x4d) BAD_TRAP(0x4e) BAD_TRAP(0x4f) BAD_TRAP(0x50)
+t_bad51:BAD_TRAP(0x51) BAD_TRAP(0x52) BAD_TRAP(0x53) BAD_TRAP(0x54) BAD_TRAP(0x55)
+t_bad56:BAD_TRAP(0x56) BAD_TRAP(0x57) BAD_TRAP(0x58) BAD_TRAP(0x59) BAD_TRAP(0x5a)
+t_bad5b:BAD_TRAP(0x5b) BAD_TRAP(0x5c) BAD_TRAP(0x5d) BAD_TRAP(0x5e) BAD_TRAP(0x5f)
+t_bad60:BAD_TRAP(0x60) BAD_TRAP(0x61) BAD_TRAP(0x62) BAD_TRAP(0x63) BAD_TRAP(0x64)
+t_bad65:BAD_TRAP(0x65) BAD_TRAP(0x66) BAD_TRAP(0x67) BAD_TRAP(0x68) BAD_TRAP(0x69)
+t_bad6a:BAD_TRAP(0x6a) BAD_TRAP(0x6b) BAD_TRAP(0x6c) BAD_TRAP(0x6d) BAD_TRAP(0x6e)
+t_bad6f:BAD_TRAP(0x6f) BAD_TRAP(0x70) BAD_TRAP(0x71) BAD_TRAP(0x72) BAD_TRAP(0x73)
+t_bad74:BAD_TRAP(0x74) BAD_TRAP(0x75) BAD_TRAP(0x76) BAD_TRAP(0x77) BAD_TRAP(0x78)
+t_bad79:BAD_TRAP(0x79) BAD_TRAP(0x7a) BAD_TRAP(0x7b) BAD_TRAP(0x7c) BAD_TRAP(0x7d)
+t_bad7e:BAD_TRAP(0x7e) BAD_TRAP(0x7f)
+t_bad80:BAD_TRAP(0x80)                      /* SunOS System Call             */
+t_sbkpt:BREAKPOINT_TRAP                     /* Software Breakpoint/KGDB      */
+t_divz: TRAP_ENTRY(0x82, do_hw_divzero)     /* Divide by zero trap           */
+t_flwin:TRAP_ENTRY(0x83, do_flush_windows)  /* Flush Windows Trap            */
+t_clwin:BAD_TRAP(0x84)                      /* Clean Windows Trap            */
+t_rchk: BAD_TRAP(0x85)                      /* Range Check                   */
+t_funal:BAD_TRAP(0x86)                      /* Fix Unaligned Access Trap     */
+t_iovf: BAD_TRAP(0x87)                      /* Integer Overflow Trap         */
+t_bad88:BAD_TRAP(0x88)                      /* Slowaris System Call          */
+t_bad89:BAD_TRAP(0x89)                      /* Net-B.S. System Call          */
+t_bad8a:BAD_TRAP(0x8a) BAD_TRAP(0x8b) BAD_TRAP(0x8c) BAD_TRAP(0x8d) BAD_TRAP(0x8e)
+t_bad8f:BAD_TRAP(0x8f)
+t_linux:LINUX_SYSCALL_TRAP                  /* Linux System Call             */
+t_bad91:BAD_TRAP(0x91) BAD_TRAP(0x92) BAD_TRAP(0x93) BAD_TRAP(0x94) BAD_TRAP(0x95)
+t_bad96:BAD_TRAP(0x96) BAD_TRAP(0x97) BAD_TRAP(0x98) BAD_TRAP(0x99) BAD_TRAP(0x9a)
+t_bad9b:BAD_TRAP(0x9b) BAD_TRAP(0x9c) BAD_TRAP(0x9d) BAD_TRAP(0x9e) BAD_TRAP(0x9f)
+t_getcc:GETCC_TRAP                          /* Get Condition Codes           */
+t_setcc:SETCC_TRAP                          /* Set Condition Codes           */
+t_getpsr:GETPSR_TRAP                        /* Get PSR Register              */
+t_bada3:BAD_TRAP(0xa3) BAD_TRAP(0xa4) BAD_TRAP(0xa5) BAD_TRAP(0xa6)
+t_bada7:BAD_TRAP(0xa7)
+t_bada8:BAD_TRAP(0xa8) BAD_TRAP(0xa9) BAD_TRAP(0xaa) BAD_TRAP(0xab)
+t_badac:BAD_TRAP(0xac) BAD_TRAP(0xad) BAD_TRAP(0xae) BAD_TRAP(0xaf) BAD_TRAP(0xb0)
+t_badb1:BAD_TRAP(0xb1) BAD_TRAP(0xb2) BAD_TRAP(0xb3) BAD_TRAP(0xb4) BAD_TRAP(0xb5)
+t_badb6:BAD_TRAP(0xb6) BAD_TRAP(0xb7) BAD_TRAP(0xb8) BAD_TRAP(0xb9) BAD_TRAP(0xba)
+t_badbb:BAD_TRAP(0xbb) BAD_TRAP(0xbc) BAD_TRAP(0xbd) BAD_TRAP(0xbe) BAD_TRAP(0xbf)
+t_badc0:BAD_TRAP(0xc0) BAD_TRAP(0xc1) BAD_TRAP(0xc2) BAD_TRAP(0xc3) BAD_TRAP(0xc4)
+t_badc5:BAD_TRAP(0xc5) BAD_TRAP(0xc6) BAD_TRAP(0xc7) BAD_TRAP(0xc8) BAD_TRAP(0xc9)
+t_badca:BAD_TRAP(0xca) BAD_TRAP(0xcb) BAD_TRAP(0xcc) BAD_TRAP(0xcd) BAD_TRAP(0xce)
+t_badcf:BAD_TRAP(0xcf) BAD_TRAP(0xd0) BAD_TRAP(0xd1) BAD_TRAP(0xd2) BAD_TRAP(0xd3)
+t_badd4:BAD_TRAP(0xd4) BAD_TRAP(0xd5) BAD_TRAP(0xd6) BAD_TRAP(0xd7) BAD_TRAP(0xd8)
+t_badd9:BAD_TRAP(0xd9) BAD_TRAP(0xda) BAD_TRAP(0xdb) BAD_TRAP(0xdc) BAD_TRAP(0xdd)
+t_badde:BAD_TRAP(0xde) BAD_TRAP(0xdf) BAD_TRAP(0xe0) BAD_TRAP(0xe1) BAD_TRAP(0xe2)
+t_bade3:BAD_TRAP(0xe3) BAD_TRAP(0xe4) BAD_TRAP(0xe5) BAD_TRAP(0xe6) BAD_TRAP(0xe7)
+t_bade8:BAD_TRAP(0xe8) BAD_TRAP(0xe9) BAD_TRAP(0xea) BAD_TRAP(0xeb) BAD_TRAP(0xec)
+t_baded:BAD_TRAP(0xed) BAD_TRAP(0xee) BAD_TRAP(0xef) BAD_TRAP(0xf0) BAD_TRAP(0xf1)
+t_badf2:BAD_TRAP(0xf2) BAD_TRAP(0xf3) BAD_TRAP(0xf4) BAD_TRAP(0xf5) BAD_TRAP(0xf6)
+t_badf7:BAD_TRAP(0xf7) BAD_TRAP(0xf8) BAD_TRAP(0xf9) BAD_TRAP(0xfa) BAD_TRAP(0xfb)
+t_badfc:BAD_TRAP(0xfc)
+t_kgdb: KGDB_TRAP(0xfd)
+dbtrap: BAD_TRAP(0xfe)                      /* Debugger/PROM breakpoint #1   */
+dbtrap2:BAD_TRAP(0xff)                      /* Debugger/PROM breakpoint #2   */
+        .globl  end_traptable
+end_traptable:
+#ifdef CONFIG_SMP
+        /* Trap tables for the other cpus. */
+        .globl  trapbase_cpu1, trapbase_cpu2, trapbase_cpu3
+trapbase_cpu1:
+        BAD_TRAP(0x0)
+        SRMMU_TFAULT
+        TRAP_ENTRY(0x2, bad_instruction)
+        TRAP_ENTRY(0x3, priv_instruction)
+        TRAP_ENTRY(0x4, fpd_trap_handler)
+        WINDOW_SPILL
+        WINDOW_FILL
+        TRAP_ENTRY(0x7, mna_handler)
+        TRAP_ENTRY(0x8, fpe_trap_handler)
+        SRMMU_DFAULT
+        TRAP_ENTRY(0xa, do_tag_overflow)
+        TRAP_ENTRY(0xb, do_watchpoint)
+        BAD_TRAP(0xc) BAD_TRAP(0xd) BAD_TRAP(0xe) BAD_TRAP(0xf) BAD_TRAP(0x10)
+        TRAP_ENTRY_INTERRUPT(1) TRAP_ENTRY_INTERRUPT(2)
+        TRAP_ENTRY_INTERRUPT(3) TRAP_ENTRY_INTERRUPT(4)
+        TRAP_ENTRY_INTERRUPT(5) TRAP_ENTRY_INTERRUPT(6)
+        TRAP_ENTRY_INTERRUPT(7) TRAP_ENTRY_INTERRUPT(8)
+        TRAP_ENTRY_INTERRUPT(9) TRAP_ENTRY_INTERRUPT(10)
+        TRAP_ENTRY_INTERRUPT(11) TRAP_ENTRY_INTERRUPT(12)
+        TRAP_ENTRY_INTERRUPT(13) TRAP_ENTRY_INTERRUPT(14)
+        TRAP_ENTRY(0x1f, linux_trap_ipi15_sun4m)
+        TRAP_ENTRY(0x20, do_reg_access)
+        BAD_TRAP(0x21)
+        BAD_TRAP(0x22)
+        BAD_TRAP(0x23)
+        TRAP_ENTRY(0x24, do_cp_disabled)
+        SKIP_TRAP(0x25, unimp_flush)
+        BAD_TRAP(0x26)
+        BAD_TRAP(0x27)
+        TRAP_ENTRY(0x28, do_cp_exception)
+        SRMMU_DFAULT
+        TRAP_ENTRY(0x2a, do_hw_divzero)
+        BAD_TRAP(0x2b)
+        BAD_TRAP(0x2c)
+        BAD_TRAP(0x2d) BAD_TRAP(0x2e) BAD_TRAP(0x2f) BAD_TRAP(0x30) BAD_TRAP(0x31)
+        BAD_TRAP(0x32) BAD_TRAP(0x33) BAD_TRAP(0x34) BAD_TRAP(0x35) BAD_TRAP(0x36)
+        BAD_TRAP(0x37) BAD_TRAP(0x38) BAD_TRAP(0x39) BAD_TRAP(0x3a) BAD_TRAP(0x3b)
+        BAD_TRAP(0x3c) BAD_TRAP(0x3d) BAD_TRAP(0x3e) BAD_TRAP(0x3f) BAD_TRAP(0x40)
+        BAD_TRAP(0x41) BAD_TRAP(0x42) BAD_TRAP(0x43) BAD_TRAP(0x44) BAD_TRAP(0x45)
+        BAD_TRAP(0x46) BAD_TRAP(0x47) BAD_TRAP(0x48) BAD_TRAP(0x49) BAD_TRAP(0x4a)
+        BAD_TRAP(0x4b) BAD_TRAP(0x4c) BAD_TRAP(0x4d) BAD_TRAP(0x4e) BAD_TRAP(0x4f)
+        BAD_TRAP(0x50)
+        BAD_TRAP(0x51) BAD_TRAP(0x52) BAD_TRAP(0x53) BAD_TRAP(0x54) BAD_TRAP(0x55)
+        BAD_TRAP(0x56) BAD_TRAP(0x57) BAD_TRAP(0x58) BAD_TRAP(0x59) BAD_TRAP(0x5a)
+        BAD_TRAP(0x5b) BAD_TRAP(0x5c) BAD_TRAP(0x5d) BAD_TRAP(0x5e) BAD_TRAP(0x5f)
+        BAD_TRAP(0x60) BAD_TRAP(0x61) BAD_TRAP(0x62) BAD_TRAP(0x63) BAD_TRAP(0x64)
+        BAD_TRAP(0x65) BAD_TRAP(0x66) BAD_TRAP(0x67) BAD_TRAP(0x68) BAD_TRAP(0x69)
+        BAD_TRAP(0x6a) BAD_TRAP(0x6b) BAD_TRAP(0x6c) BAD_TRAP(0x6d) BAD_TRAP(0x6e)
+        BAD_TRAP(0x6f) BAD_TRAP(0x70) BAD_TRAP(0x71) BAD_TRAP(0x72) BAD_TRAP(0x73)
+        BAD_TRAP(0x74) BAD_TRAP(0x75) BAD_TRAP(0x76) BAD_TRAP(0x77) BAD_TRAP(0x78)
+        BAD_TRAP(0x79) BAD_TRAP(0x7a) BAD_TRAP(0x7b) BAD_TRAP(0x7c) BAD_TRAP(0x7d)
+        BAD_TRAP(0x7e) BAD_TRAP(0x7f)
+        BAD_TRAP(0x80)
+        BREAKPOINT_TRAP
+        TRAP_ENTRY(0x82, do_hw_divzero)
+        TRAP_ENTRY(0x83, do_flush_windows)
+        BAD_TRAP(0x84) BAD_TRAP(0x85) BAD_TRAP(0x86)
+        BAD_TRAP(0x87) BAD_TRAP(0x88) BAD_TRAP(0x89)
+        BAD_TRAP(0x8a) BAD_TRAP(0x8b) BAD_TRAP(0x8c)
+        BAD_TRAP(0x8d) BAD_TRAP(0x8e) BAD_TRAP(0x8f)
+        LINUX_SYSCALL_TRAP BAD_TRAP(0x91)
+        BAD_TRAP(0x92) BAD_TRAP(0x93) BAD_TRAP(0x94)
+        BAD_TRAP(0x95) BAD_TRAP(0x96) BAD_TRAP(0x97) BAD_TRAP(0x98) BAD_TRAP(0x99)
+        BAD_TRAP(0x9a) BAD_TRAP(0x9b) BAD_TRAP(0x9c) BAD_TRAP(0x9d) BAD_TRAP(0x9e)
+        BAD_TRAP(0x9f)
+        GETCC_TRAP
+        SETCC_TRAP
+        GETPSR_TRAP
+        BAD_TRAP(0xa3) BAD_TRAP(0xa4) BAD_TRAP(0xa5) BAD_TRAP(0xa6)
+        BAD_TRAP(0xa7) BAD_TRAP(0xa8) BAD_TRAP(0xa9) BAD_TRAP(0xaa) BAD_TRAP(0xab)
+        BAD_TRAP(0xac) BAD_TRAP(0xad) BAD_TRAP(0xae) BAD_TRAP(0xaf) BAD_TRAP(0xb0)
+        BAD_TRAP(0xb1) BAD_TRAP(0xb2) BAD_TRAP(0xb3) BAD_TRAP(0xb4) BAD_TRAP(0xb5)
+        BAD_TRAP(0xb6) BAD_TRAP(0xb7) BAD_TRAP(0xb8) BAD_TRAP(0xb9) BAD_TRAP(0xba)
+        BAD_TRAP(0xbb) BAD_TRAP(0xbc) BAD_TRAP(0xbd) BAD_TRAP(0xbe) BAD_TRAP(0xbf)
+        BAD_TRAP(0xc0) BAD_TRAP(0xc1) BAD_TRAP(0xc2) BAD_TRAP(0xc3) BAD_TRAP(0xc4)
+        BAD_TRAP(0xc5) BAD_TRAP(0xc6) BAD_TRAP(0xc7) BAD_TRAP(0xc8) BAD_TRAP(0xc9)
+        BAD_TRAP(0xca) BAD_TRAP(0xcb) BAD_TRAP(0xcc) BAD_TRAP(0xcd) BAD_TRAP(0xce)
+        BAD_TRAP(0xcf) BAD_TRAP(0xd0) BAD_TRAP(0xd1) BAD_TRAP(0xd2) BAD_TRAP(0xd3)
+        BAD_TRAP(0xd4) BAD_TRAP(0xd5) BAD_TRAP(0xd6) BAD_TRAP(0xd7) BAD_TRAP(0xd8)
+        BAD_TRAP(0xd9) BAD_TRAP(0xda) BAD_TRAP(0xdb) BAD_TRAP(0xdc) BAD_TRAP(0xdd)
+        BAD_TRAP(0xde) BAD_TRAP(0xdf) BAD_TRAP(0xe0) BAD_TRAP(0xe1) BAD_TRAP(0xe2)
+        BAD_TRAP(0xe3) BAD_TRAP(0xe4) BAD_TRAP(0xe5) BAD_TRAP(0xe6) BAD_TRAP(0xe7)
+        BAD_TRAP(0xe8) BAD_TRAP(0xe9) BAD_TRAP(0xea) BAD_TRAP(0xeb) BAD_TRAP(0xec)
+        BAD_TRAP(0xed) BAD_TRAP(0xee) BAD_TRAP(0xef) BAD_TRAP(0xf0) BAD_TRAP(0xf1)
+        BAD_TRAP(0xf2) BAD_TRAP(0xf3) BAD_TRAP(0xf4) BAD_TRAP(0xf5) BAD_TRAP(0xf6)
+        BAD_TRAP(0xf7) BAD_TRAP(0xf8) BAD_TRAP(0xf9) BAD_TRAP(0xfa) BAD_TRAP(0xfb)
+        BAD_TRAP(0xfc)
+        KGDB_TRAP(0xfd)
+        BAD_TRAP(0xfe)
+        BAD_TRAP(0xff)
+trapbase_cpu2:
+        BAD_TRAP(0x0)
+        SRMMU_TFAULT
+        TRAP_ENTRY(0x2, bad_instruction)
+        TRAP_ENTRY(0x3, priv_instruction)
+        TRAP_ENTRY(0x4, fpd_trap_handler)
+        WINDOW_SPILL
+        WINDOW_FILL
+        TRAP_ENTRY(0x7, mna_handler)
+        TRAP_ENTRY(0x8, fpe_trap_handler)
+        SRMMU_DFAULT
+        TRAP_ENTRY(0xa, do_tag_overflow)
+        TRAP_ENTRY(0xb, do_watchpoint)
+        BAD_TRAP(0xc) BAD_TRAP(0xd) BAD_TRAP(0xe) BAD_TRAP(0xf) BAD_TRAP(0x10)
+        TRAP_ENTRY_INTERRUPT(1)
+        TRAP_ENTRY_INTERRUPT(2)
+        TRAP_ENTRY_INTERRUPT(3)
+        TRAP_ENTRY_INTERRUPT(4)
+        TRAP_ENTRY_INTERRUPT(5)
+        TRAP_ENTRY_INTERRUPT(6)
+        TRAP_ENTRY_INTERRUPT(7)
+        TRAP_ENTRY_INTERRUPT(8)
+        TRAP_ENTRY_INTERRUPT(9)
+        TRAP_ENTRY_INTERRUPT(10)
+        TRAP_ENTRY_INTERRUPT(11)
+        TRAP_ENTRY_INTERRUPT(12)
+        TRAP_ENTRY_INTERRUPT(13)
+        TRAP_ENTRY_INTERRUPT(14)
+        TRAP_ENTRY(0x1f, linux_trap_ipi15_sun4m)
+        TRAP_ENTRY(0x20, do_reg_access)
+        BAD_TRAP(0x21)
+        BAD_TRAP(0x22)
+        BAD_TRAP(0x23)
+        TRAP_ENTRY(0x24, do_cp_disabled)
+        SKIP_TRAP(0x25, unimp_flush)
+        BAD_TRAP(0x26)
+        BAD_TRAP(0x27)
+        TRAP_ENTRY(0x28, do_cp_exception)
+        SRMMU_DFAULT
+        TRAP_ENTRY(0x2a, do_hw_divzero)
+        BAD_TRAP(0x2b)
+        BAD_TRAP(0x2c)
+        BAD_TRAP(0x2d) BAD_TRAP(0x2e) BAD_TRAP(0x2f) BAD_TRAP(0x30) BAD_TRAP(0x31)
+        BAD_TRAP(0x32) BAD_TRAP(0x33) BAD_TRAP(0x34) BAD_TRAP(0x35) BAD_TRAP(0x36)
+        BAD_TRAP(0x37) BAD_TRAP(0x38) BAD_TRAP(0x39) BAD_TRAP(0x3a) BAD_TRAP(0x3b)
+        BAD_TRAP(0x3c) BAD_TRAP(0x3d) BAD_TRAP(0x3e) BAD_TRAP(0x3f) BAD_TRAP(0x40)
+        BAD_TRAP(0x41) BAD_TRAP(0x42) BAD_TRAP(0x43) BAD_TRAP(0x44) BAD_TRAP(0x45)
+        BAD_TRAP(0x46) BAD_TRAP(0x47) BAD_TRAP(0x48) BAD_TRAP(0x49) BAD_TRAP(0x4a)
+        BAD_TRAP(0x4b) BAD_TRAP(0x4c) BAD_TRAP(0x4d) BAD_TRAP(0x4e) BAD_TRAP(0x4f)
+        BAD_TRAP(0x50)
+        BAD_TRAP(0x51) BAD_TRAP(0x52) BAD_TRAP(0x53) BAD_TRAP(0x54) BAD_TRAP(0x55)
+        BAD_TRAP(0x56) BAD_TRAP(0x57) BAD_TRAP(0x58) BAD_TRAP(0x59) BAD_TRAP(0x5a)
+        BAD_TRAP(0x5b) BAD_TRAP(0x5c) BAD_TRAP(0x5d) BAD_TRAP(0x5e) BAD_TRAP(0x5f)
+        BAD_TRAP(0x60) BAD_TRAP(0x61) BAD_TRAP(0x62) BAD_TRAP(0x63) BAD_TRAP(0x64)
+        BAD_TRAP(0x65) BAD_TRAP(0x66) BAD_TRAP(0x67) BAD_TRAP(0x68) BAD_TRAP(0x69)
+        BAD_TRAP(0x6a) BAD_TRAP(0x6b) BAD_TRAP(0x6c) BAD_TRAP(0x6d) BAD_TRAP(0x6e)
+        BAD_TRAP(0x6f) BAD_TRAP(0x70) BAD_TRAP(0x71) BAD_TRAP(0x72) BAD_TRAP(0x73)
+        BAD_TRAP(0x74) BAD_TRAP(0x75) BAD_TRAP(0x76) BAD_TRAP(0x77) BAD_TRAP(0x78)
+        BAD_TRAP(0x79) BAD_TRAP(0x7a) BAD_TRAP(0x7b) BAD_TRAP(0x7c) BAD_TRAP(0x7d)
+        BAD_TRAP(0x7e) BAD_TRAP(0x7f)
+        BAD_TRAP(0x80)
+        BREAKPOINT_TRAP
+        TRAP_ENTRY(0x82, do_hw_divzero)
+        TRAP_ENTRY(0x83, do_flush_windows)
+        BAD_TRAP(0x84)
+        BAD_TRAP(0x85)
+        BAD_TRAP(0x86) BAD_TRAP(0x87) BAD_TRAP(0x88)
+        BAD_TRAP(0x89) BAD_TRAP(0x8a) BAD_TRAP(0x8b) BAD_TRAP(0x8c)
+        BAD_TRAP(0x8d) BAD_TRAP(0x8e) BAD_TRAP(0x8f)
+        LINUX_SYSCALL_TRAP BAD_TRAP(0x91)
+        BAD_TRAP(0x92) BAD_TRAP(0x93) BAD_TRAP(0x94)
+        BAD_TRAP(0x95) BAD_TRAP(0x96) BAD_TRAP(0x97) BAD_TRAP(0x98) BAD_TRAP(0x99)
+        BAD_TRAP(0x9a) BAD_TRAP(0x9b) BAD_TRAP(0x9c) BAD_TRAP(0x9d) BAD_TRAP(0x9e)
+        BAD_TRAP(0x9f)
+        GETCC_TRAP
+        SETCC_TRAP
+        GETPSR_TRAP
+        BAD_TRAP(0xa3) BAD_TRAP(0xa4) BAD_TRAP(0xa5) BAD_TRAP(0xa6)
+        BAD_TRAP(0xa7) BAD_TRAP(0xa8) BAD_TRAP(0xa9) BAD_TRAP(0xaa) BAD_TRAP(0xab)
+        BAD_TRAP(0xac) BAD_TRAP(0xad) BAD_TRAP(0xae) BAD_TRAP(0xaf) BAD_TRAP(0xb0)
+        BAD_TRAP(0xb1) BAD_TRAP(0xb2) BAD_TRAP(0xb3) BAD_TRAP(0xb4) BAD_TRAP(0xb5)
+        BAD_TRAP(0xb6) BAD_TRAP(0xb7) BAD_TRAP(0xb8) BAD_TRAP(0xb9) BAD_TRAP(0xba)
+        BAD_TRAP(0xbb) BAD_TRAP(0xbc) BAD_TRAP(0xbd) BAD_TRAP(0xbe) BAD_TRAP(0xbf)
+        BAD_TRAP(0xc0) BAD_TRAP(0xc1) BAD_TRAP(0xc2) BAD_TRAP(0xc3) BAD_TRAP(0xc4)
+        BAD_TRAP(0xc5) BAD_TRAP(0xc6) BAD_TRAP(0xc7) BAD_TRAP(0xc8) BAD_TRAP(0xc9)
+        BAD_TRAP(0xca) BAD_TRAP(0xcb) BAD_TRAP(0xcc) BAD_TRAP(0xcd) BAD_TRAP(0xce)
+        BAD_TRAP(0xcf) BAD_TRAP(0xd0) BAD_TRAP(0xd1) BAD_TRAP(0xd2) BAD_TRAP(0xd3)
+        BAD_TRAP(0xd4) BAD_TRAP(0xd5) BAD_TRAP(0xd6) BAD_TRAP(0xd7) BAD_TRAP(0xd8)
+        BAD_TRAP(0xd9) BAD_TRAP(0xda) BAD_TRAP(0xdb) BAD_TRAP(0xdc) BAD_TRAP(0xdd)
+        BAD_TRAP(0xde) BAD_TRAP(0xdf) BAD_TRAP(0xe0) BAD_TRAP(0xe1) BAD_TRAP(0xe2)
+        BAD_TRAP(0xe3) BAD_TRAP(0xe4) BAD_TRAP(0xe5) BAD_TRAP(0xe6) BAD_TRAP(0xe7)
+        BAD_TRAP(0xe8) BAD_TRAP(0xe9) BAD_TRAP(0xea) BAD_TRAP(0xeb) BAD_TRAP(0xec)
+        BAD_TRAP(0xed) BAD_TRAP(0xee) BAD_TRAP(0xef) BAD_TRAP(0xf0) BAD_TRAP(0xf1)
+        BAD_TRAP(0xf2) BAD_TRAP(0xf3) BAD_TRAP(0xf4) BAD_TRAP(0xf5) BAD_TRAP(0xf6)
+        BAD_TRAP(0xf7) BAD_TRAP(0xf8) BAD_TRAP(0xf9) BAD_TRAP(0xfa) BAD_TRAP(0xfb)
+        BAD_TRAP(0xfc)
+        KGDB_TRAP(0xfd)
+        BAD_TRAP(0xfe)
+        BAD_TRAP(0xff)
+trapbase_cpu3:
+        BAD_TRAP(0x0)
+        SRMMU_TFAULT
+        TRAP_ENTRY(0x2, bad_instruction)
+        TRAP_ENTRY(0x3, priv_instruction)
+        TRAP_ENTRY(0x4, fpd_trap_handler)
+        WINDOW_SPILL
+        WINDOW_FILL
+        TRAP_ENTRY(0x7, mna_handler)
+        TRAP_ENTRY(0x8, fpe_trap_handler)
+        SRMMU_DFAULT
+        TRAP_ENTRY(0xa, do_tag_overflow)
+        TRAP_ENTRY(0xb, do_watchpoint)
+        BAD_TRAP(0xc) BAD_TRAP(0xd) BAD_TRAP(0xe) BAD_TRAP(0xf) BAD_TRAP(0x10)
+        TRAP_ENTRY_INTERRUPT(1)
+        TRAP_ENTRY_INTERRUPT(2)
+        TRAP_ENTRY_INTERRUPT(3)
+        TRAP_ENTRY_INTERRUPT(4)
+        TRAP_ENTRY_INTERRUPT(5)
+        TRAP_ENTRY_INTERRUPT(6)
+        TRAP_ENTRY_INTERRUPT(7)
+        TRAP_ENTRY_INTERRUPT(8)
+        TRAP_ENTRY_INTERRUPT(9)
+        TRAP_ENTRY_INTERRUPT(10)
+        TRAP_ENTRY_INTERRUPT(11)
+        TRAP_ENTRY_INTERRUPT(12)
+        TRAP_ENTRY_INTERRUPT(13)
+        TRAP_ENTRY_INTERRUPT(14)
+        TRAP_ENTRY(0x1f, linux_trap_ipi15_sun4m)
+        TRAP_ENTRY(0x20, do_reg_access)
+        BAD_TRAP(0x21)
+        BAD_TRAP(0x22)
+        BAD_TRAP(0x23)
+        TRAP_ENTRY(0x24, do_cp_disabled)
+        SKIP_TRAP(0x25, unimp_flush)
+        BAD_TRAP(0x26)
+        BAD_TRAP(0x27)
+        TRAP_ENTRY(0x28, do_cp_exception)
+        SRMMU_DFAULT
+        TRAP_ENTRY(0x2a, do_hw_divzero)
+        BAD_TRAP(0x2b) BAD_TRAP(0x2c)
+        BAD_TRAP(0x2d) BAD_TRAP(0x2e) BAD_TRAP(0x2f) BAD_TRAP(0x30) BAD_TRAP(0x31)
+        BAD_TRAP(0x32) BAD_TRAP(0x33) BAD_TRAP(0x34) BAD_TRAP(0x35) BAD_TRAP(0x36)
+        BAD_TRAP(0x37) BAD_TRAP(0x38) BAD_TRAP(0x39) BAD_TRAP(0x3a) BAD_TRAP(0x3b)
+        BAD_TRAP(0x3c) BAD_TRAP(0x3d) BAD_TRAP(0x3e) BAD_TRAP(0x3f) BAD_TRAP(0x40)
+        BAD_TRAP(0x41) BAD_TRAP(0x42) BAD_TRAP(0x43) BAD_TRAP(0x44) BAD_TRAP(0x45)
+        BAD_TRAP(0x46) BAD_TRAP(0x47) BAD_TRAP(0x48) BAD_TRAP(0x49) BAD_TRAP(0x4a)
+        BAD_TRAP(0x4b) BAD_TRAP(0x4c) BAD_TRAP(0x4d) BAD_TRAP(0x4e) BAD_TRAP(0x4f)
+        BAD_TRAP(0x50)
+        BAD_TRAP(0x51) BAD_TRAP(0x52) BAD_TRAP(0x53) BAD_TRAP(0x54) BAD_TRAP(0x55)
+        BAD_TRAP(0x56) BAD_TRAP(0x57) BAD_TRAP(0x58) BAD_TRAP(0x59) BAD_TRAP(0x5a)
+        BAD_TRAP(0x5b) BAD_TRAP(0x5c) BAD_TRAP(0x5d) BAD_TRAP(0x5e) BAD_TRAP(0x5f)
+        BAD_TRAP(0x60) BAD_TRAP(0x61) BAD_TRAP(0x62) BAD_TRAP(0x63) BAD_TRAP(0x64)
+        BAD_TRAP(0x65) BAD_TRAP(0x66) BAD_TRAP(0x67) BAD_TRAP(0x68) BAD_TRAP(0x69)
+        BAD_TRAP(0x6a) BAD_TRAP(0x6b) BAD_TRAP(0x6c) BAD_TRAP(0x6d) BAD_TRAP(0x6e)
+        BAD_TRAP(0x6f) BAD_TRAP(0x70) BAD_TRAP(0x71) BAD_TRAP(0x72) BAD_TRAP(0x73)
+        BAD_TRAP(0x74) BAD_TRAP(0x75) BAD_TRAP(0x76) BAD_TRAP(0x77) BAD_TRAP(0x78)
+        BAD_TRAP(0x79) BAD_TRAP(0x7a) BAD_TRAP(0x7b) BAD_TRAP(0x7c) BAD_TRAP(0x7d)
+        BAD_TRAP(0x7e) BAD_TRAP(0x7f)
+        BAD_TRAP(0x80)
+        BREAKPOINT_TRAP
+        TRAP_ENTRY(0x82, do_hw_divzero)
+        TRAP_ENTRY(0x83, do_flush_windows)
+        BAD_TRAP(0x84) BAD_TRAP(0x85)
+        BAD_TRAP(0x86) BAD_TRAP(0x87) BAD_TRAP(0x88)
+        BAD_TRAP(0x89) BAD_TRAP(0x8a) BAD_TRAP(0x8b) BAD_TRAP(0x8c)
+        BAD_TRAP(0x8d) BAD_TRAP(0x8e) BAD_TRAP(0x8f)
+        LINUX_SYSCALL_TRAP
+        BAD_TRAP(0x91) BAD_TRAP(0x92) BAD_TRAP(0x93) BAD_TRAP(0x94)
+        BAD_TRAP(0x95) BAD_TRAP(0x96) BAD_TRAP(0x97) BAD_TRAP(0x98) BAD_TRAP(0x99)
+        BAD_TRAP(0x9a) BAD_TRAP(0x9b) BAD_TRAP(0x9c) BAD_TRAP(0x9d) BAD_TRAP(0x9e)
+        BAD_TRAP(0x9f)
+        GETCC_TRAP
+        SETCC_TRAP
+        GETPSR_TRAP
+        BAD_TRAP(0xa3) BAD_TRAP(0xa4) BAD_TRAP(0xa5) BAD_TRAP(0xa6)
+        BAD_TRAP(0xa7) BAD_TRAP(0xa8) BAD_TRAP(0xa9) BAD_TRAP(0xaa) BAD_TRAP(0xab)
+        BAD_TRAP(0xac) BAD_TRAP(0xad) BAD_TRAP(0xae) BAD_TRAP(0xaf) BAD_TRAP(0xb0)
+        BAD_TRAP(0xb1) BAD_TRAP(0xb2) BAD_TRAP(0xb3) BAD_TRAP(0xb4) BAD_TRAP(0xb5)
+        BAD_TRAP(0xb6) BAD_TRAP(0xb7) BAD_TRAP(0xb8) BAD_TRAP(0xb9) BAD_TRAP(0xba)
+        BAD_TRAP(0xbb) BAD_TRAP(0xbc) BAD_TRAP(0xbd) BAD_TRAP(0xbe) BAD_TRAP(0xbf)
+        BAD_TRAP(0xc0) BAD_TRAP(0xc1) BAD_TRAP(0xc2) BAD_TRAP(0xc3) BAD_TRAP(0xc4)
+        BAD_TRAP(0xc5) BAD_TRAP(0xc6) BAD_TRAP(0xc7) BAD_TRAP(0xc8) BAD_TRAP(0xc9)
+        BAD_TRAP(0xca) BAD_TRAP(0xcb) BAD_TRAP(0xcc) BAD_TRAP(0xcd) BAD_TRAP(0xce)
+        BAD_TRAP(0xcf) BAD_TRAP(0xd0) BAD_TRAP(0xd1) BAD_TRAP(0xd2) BAD_TRAP(0xd3)
+        BAD_TRAP(0xd4) BAD_TRAP(0xd5) BAD_TRAP(0xd6) BAD_TRAP(0xd7) BAD_TRAP(0xd8)
+        BAD_TRAP(0xd9) BAD_TRAP(0xda) BAD_TRAP(0xdb) BAD_TRAP(0xdc) BAD_TRAP(0xdd)
+        BAD_TRAP(0xde) BAD_TRAP(0xdf) BAD_TRAP(0xe0) BAD_TRAP(0xe1) BAD_TRAP(0xe2)
+        BAD_TRAP(0xe3) BAD_TRAP(0xe4) BAD_TRAP(0xe5) BAD_TRAP(0xe6) BAD_TRAP(0xe7)
+        BAD_TRAP(0xe8) BAD_TRAP(0xe9) BAD_TRAP(0xea) BAD_TRAP(0xeb) BAD_TRAP(0xec)
+        BAD_TRAP(0xed) BAD_TRAP(0xee) BAD_TRAP(0xef) BAD_TRAP(0xf0) BAD_TRAP(0xf1)
+        BAD_TRAP(0xf2) BAD_TRAP(0xf3) BAD_TRAP(0xf4) BAD_TRAP(0xf5) BAD_TRAP(0xf6)
+        BAD_TRAP(0xf7) BAD_TRAP(0xf8) BAD_TRAP(0xf9) BAD_TRAP(0xfa) BAD_TRAP(0xfb)
+        BAD_TRAP(0xfc)
+        KGDB_TRAP(0xfd)
+        BAD_TRAP(0xfe)
+        BAD_TRAP(0xff)
+#endif
diff --git a/arch/sparc/kernel/ttable.S b/arch/sparc/kernel/ttable_64.S
index c6dfdaa29e20..c6dfdaa29e20 100644
--- a/arch/sparc/kernel/ttable.S
+++ b/arch/sparc/kernel/ttable_64.S
diff --git a/arch/sparc/kernel/unaligned_64.c b/arch/sparc/kernel/unaligned_64.c
index dae85bc2eda5..f81d038f7340 100644
--- a/arch/sparc/kernel/unaligned_64.c
+++ b/arch/sparc/kernel/unaligned_64.c
@@ -21,7 +21,6 @@
 #include <linux/bitops.h>
 #include <linux/perf_event.h>
 #include <linux/ratelimit.h>
-#include <linux/bitops.h>
 #include <asm/fpumacro.h>
 #include <asm/cacheflush.h>
diff --git a/arch/sparc/kernel/wof.S b/arch/sparc/kernel/wof.S
index 3bbcd8dc9abf..4c2de3cf309b 100644
--- a/arch/sparc/kernel/wof.S
+++ b/arch/sparc/kernel/wof.S
@@ -163,9 +163,8 @@ spwin_fromuser:
         * the label 'spwin_user_stack_is_bolixed' which will take
         * care of things at that point.
         */
-        .globl  spwin_mmu_patchme
+        b       spwin_srmmu_stackchk
-spwin_mmu_patchme:      b       spwin_sun4c_stackchk
+         andcc  %sp, 0x7, %g0
-                                 andcc  %sp, 0x7, %g0
 spwin_good_ustack:
        /* LOCATION: Window to be saved */
@@ -306,73 +305,6 @@ spwin_bad_ustack_from_kernel:
 * As noted above %curptr cannot be touched by this routine at all.
 */
-spwin_sun4c_stackchk:
-        /* LOCATION: Window to be saved on the stack */
-        /* See if the stack is in the address space hole but first,
-         * check results of callers andcc %sp, 0x7, %g0
-         */
-        be      1f
-         sra    %sp, 29, %glob_tmp
-        rd      %psr, %glob_tmp
-        b       spwin_user_stack_is_bolixed + 0x4
-         nop
-1:
-        add     %glob_tmp, 0x1, %glob_tmp
-        andncc  %glob_tmp, 0x1, %g0
-        be      1f
-         and    %sp, 0xfff, %glob_tmp           ! delay slot
-        rd      %psr, %glob_tmp
-        b       spwin_user_stack_is_bolixed + 0x4
-         nop
-        /* See if our dump area will be on more than one
-         * page.
-         */
-1:
-        add     %glob_tmp, 0x38, %glob_tmp
-        andncc  %glob_tmp, 0xff8, %g0
-        be      spwin_sun4c_onepage             ! only one page to check
-         lda    [%sp] ASI_PTE, %glob_tmp        ! have to check first page anyways
-spwin_sun4c_twopages:
-        /* Is first page ok permission wise? */
-        srl     %glob_tmp, 29, %glob_tmp
-        cmp     %glob_tmp, 0x6
-        be      1f
-         add    %sp, 0x38, %glob_tmp    /* Is second page in vma hole? */
-        rd      %psr, %glob_tmp
-        b       spwin_user_stack_is_bolixed + 0x4
-         nop
-1:
-        sra     %glob_tmp, 29, %glob_tmp
-        add     %glob_tmp, 0x1, %glob_tmp
-        andncc  %glob_tmp, 0x1, %g0
-        be      1f
-         add    %sp, 0x38, %glob_tmp
-        rd      %psr, %glob_tmp
-        b       spwin_user_stack_is_bolixed + 0x4
-         nop
-1:
-        lda     [%glob_tmp] ASI_PTE, %glob_tmp
-spwin_sun4c_onepage:
-        srl     %glob_tmp, 29, %glob_tmp
-        cmp     %glob_tmp, 0x6                          ! can user write to it?
-        be      spwin_good_ustack                       ! success
-         nop
-        rd      %psr, %glob_tmp
-        b       spwin_user_stack_is_bolixed + 0x4
-         nop
        /* This is a generic SRMMU routine.  As far as I know this
         * works for all current v8/srmmu implementations, we'll
         * see...
diff --git a/arch/sparc/kernel/wuf.S b/arch/sparc/kernel/wuf.S
index 779ff750603d..9fde91a249e0 100644
--- a/arch/sparc/kernel/wuf.S
+++ b/arch/sparc/kernel/wuf.S
@@ -131,12 +131,9 @@ fwin_from_user:
        /* LOCATION: Window 'W' */
-        /* Branch to the architecture specific stack validation
+        /* Branch to the stack validation routine */
-         * routine.  They can be found below...
+        b       srmmu_fwin_stackchk
-         */
+         andcc  %sp, 0x7, %g0
-        .globl  fwin_mmu_patchme
-fwin_mmu_patchme:       b       sun4c_fwin_stackchk
-                                 andcc  %sp, 0x7, %g0
 #define STACK_OFFSET (THREAD_SIZE - TRACEREG_SZ - STACKFRAME_SZ)
@@ -242,57 +239,6 @@ fwin_user_finish_up:
         * 'someone elses' window possibly.
         */
-        .align  4
-sun4c_fwin_stackchk:
-        /* LOCATION: Window 'W' */
-        /* Caller did 'andcc %sp, 0x7, %g0' */
-        be      1f
-         and    %sp, 0xfff, %l0         ! delay slot
-        b,a     fwin_user_stack_is_bolixed
-        /* See if we have to check the sanity of one page or two */
-1:
-        add     %l0, 0x38, %l0
-        sra     %sp, 29, %l5
-        add     %l5, 0x1, %l5
-        andncc  %l5, 0x1, %g0
-        be      1f
-         andncc %l0, 0xff8, %g0
-        b,a     fwin_user_stack_is_bolixed      /* %sp is in vma hole, yuck */
-1:
-        be      sun4c_fwin_onepage      /* Only one page to check */
-         lda    [%sp] ASI_PTE, %l1
-sun4c_fwin_twopages:
-        add     %sp, 0x38, %l0
-        sra     %l0, 29, %l5
-        add     %l5, 0x1, %l5
-        andncc  %l5, 0x1, %g0
-        be      1f
-         lda    [%l0] ASI_PTE, %l1
-        b,a     fwin_user_stack_is_bolixed      /* Second page in vma hole */
-1:
-        srl     %l1, 29, %l1
-        andcc   %l1, 0x4, %g0
-        bne     sun4c_fwin_onepage
-         lda    [%sp] ASI_PTE, %l1      
-        b,a     fwin_user_stack_is_bolixed      /* Second page has bad perms */
-sun4c_fwin_onepage:
-        srl     %l1, 29, %l1
-        andcc   %l1, 0x4, %g0
-        bne     fwin_user_stack_is_ok
-         nop
-        /* A page had bad page permissions, losing... */
-        b,a     fwin_user_stack_is_bolixed
        .globl  srmmu_fwin_stackchk
 srmmu_fwin_stackchk:
        /* LOCATION: Window 'W' */
diff --git a/arch/sparc/lib/Makefile b/arch/sparc/lib/Makefile
index a3fc4375a150..389628f50a15 100644
--- a/arch/sparc/lib/Makefile
+++ b/arch/sparc/lib/Makefile
@@ -4,7 +4,7 @@
 asflags-y := -ansi -DST_DIV0=0x02
 ccflags-y := -Werror
-lib-$(CONFIG_SPARC32) += mul.o rem.o sdiv.o udiv.o umul.o urem.o ashrdi3.o
+lib-$(CONFIG_SPARC32) += ashrdi3.o
 lib-$(CONFIG_SPARC32) += memcpy.o memset.o
 lib-y                 += strlen.o
 lib-y                 += checksum_$(BITS).o
@@ -13,7 +13,7 @@ lib-y                 += memscan_$(BITS).o memcmp.o strncmp_$(BITS).o
 lib-y                 += strncpy_from_user_$(BITS).o strlen_user_$(BITS).o
 lib-$(CONFIG_SPARC32) += divdi3.o udivdi3.o
 lib-$(CONFIG_SPARC32) += copy_user.o locks.o
-lib-y                 += atomic_$(BITS).o
+lib-$(CONFIG_SPARC64) += atomic_64.o
 lib-$(CONFIG_SPARC32) += lshrdi3.o ashldi3.o
 lib-$(CONFIG_SPARC32) += muldi3.o bitext.o cmpdi2.o
@@ -40,7 +40,7 @@ lib-$(CONFIG_SPARC64) += copy_in_user.o user_fixup.o memmove.o
 lib-$(CONFIG_SPARC64) += mcount.o ipcsum.o xor.o hweight.o ffs.o
 obj-y                 += iomap.o
-obj-$(CONFIG_SPARC32) += atomic32.o
+obj-$(CONFIG_SPARC32) += atomic32.o ucmpdi2.o
 obj-y                 += ksyms.o
 obj-$(CONFIG_SPARC64) += PeeCeeI.o
 obj-y                 += usercopy.o
diff --git a/arch/sparc/lib/ashldi3.S b/arch/sparc/lib/ashldi3.S
index 17912e608716..86f60de07b0a 100644
--- a/arch/sparc/lib/ashldi3.S
+++ b/arch/sparc/lib/ashldi3.S
@@ -5,10 +5,10 @@
 * Copyright (C) 1999 David S. Miller (davem@redhat.com)
 */
+#include <linux/linkage.h>
        .text
-        .align  4
+ENTRY(__ashldi3)
-        .globl  __ashldi3
-__ashldi3:
        cmp     %o2, 0
        be      9f
         mov    0x20, %g2
@@ -32,3 +32,4 @@ __ashldi3:
 9:
        retl
         nop
+ENDPROC(__ashldi3)
diff --git a/arch/sparc/lib/ashrdi3.S b/arch/sparc/lib/ashrdi3.S
index 85398fd6dcc9..6eb8ba2dd50e 100644
--- a/arch/sparc/lib/ashrdi3.S
+++ b/arch/sparc/lib/ashrdi3.S
@@ -5,10 +5,10 @@
 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
 */
+#include <linux/linkage.h>
        .text
-        .align  4
+ENTRY(__ashrdi3)
-        .globl __ashrdi3
-__ashrdi3:
        tst     %o2
        be      3f
         or     %g0, 32, %g2
@@ -34,3 +34,4 @@ __ashrdi3:
 3:
        jmpl    %o7 + 8, %g0
         nop
+ENDPROC(__ashrdi3)
diff --git a/arch/sparc/lib/atomic_32.S b/arch/sparc/lib/atomic_32.S
deleted file mode 100644
index eb6c7359cbd1..000000000000
--- a/arch/sparc/lib/atomic_32.S
+++ /dev/null
@@ -1,44 +0,0 @@
-/* atomic.S: Move this stuff here for better ICACHE hit rates.
- *
- * Copyright (C) 1996 David S. Miller (davem@caipfs.rutgers.edu)
- */
-#include <asm/ptrace.h>
-#include <asm/psr.h>
-        .text
-        .align  4
-        .globl  __atomic_begin
-__atomic_begin:
-#ifndef CONFIG_SMP
-        .globl  ___xchg32_sun4c
-___xchg32_sun4c:
-        rd      %psr, %g3
-        andcc   %g3, PSR_PIL, %g0
-        bne     1f
-         nop
-        wr      %g3, PSR_PIL, %psr
-        nop; nop; nop
-1:
-        andcc   %g3, PSR_PIL, %g0
-        ld      [%g1], %g7
-        bne     1f
-         st     %g2, [%g1]
-        wr      %g3, 0x0, %psr
-        nop; nop; nop
-1:
-        mov     %g7, %g2
-        jmpl    %o7 + 8, %g0
-         mov    %g4, %o7
-        .globl  ___xchg32_sun4md
-___xchg32_sun4md:
-        swap    [%g1], %g2
-        jmpl    %o7 + 8, %g0
-         mov    %g4, %o7
-#endif
-        .globl  __atomic_end
-__atomic_end:
diff --git a/arch/sparc/lib/atomic_64.S b/arch/sparc/lib/atomic_64.S
index 59186e0fcf39..4d502da3de78 100644
--- a/arch/sparc/lib/atomic_64.S
+++ b/arch/sparc/lib/atomic_64.S
@@ -3,6 +3,7 @@
 * Copyright (C) 1999, 2007 David S. Miller (davem@davemloft.net)
 */
+#include <linux/linkage.h>
 #include <asm/asi.h>
 #include <asm/backoff.h>
@@ -13,9 +14,7 @@
         * memory barriers, and a second which returns
         * a value and does the barriers.
         */
-        .globl  atomic_add
+ENTRY(atomic_add) /* %o0 = increment, %o1 = atomic_ptr */
-        .type   atomic_add,#function
-atomic_add: /* %o0 = increment, %o1 = atomic_ptr */
        BACKOFF_SETUP(%o2)
 1:      lduw    [%o1], %g1
        add     %g1, %o0, %g7
@@ -26,11 +25,9 @@ atomic_add: /* %o0 = increment, %o1 = atomic_ptr */
        retl
         nop
 2:      BACKOFF_SPIN(%o2, %o3, 1b)
-        .size   atomic_add, .-atomic_add
+ENDPROC(atomic_add)
-        .globl  atomic_sub
+ENTRY(atomic_sub) /* %o0 = decrement, %o1 = atomic_ptr */
-        .type   atomic_sub,#function
-atomic_sub: /* %o0 = decrement, %o1 = atomic_ptr */
        BACKOFF_SETUP(%o2)
 1:      lduw    [%o1], %g1
        sub     %g1, %o0, %g7
@@ -41,11 +38,9 @@ atomic_sub: /* %o0 = decrement, %o1 = atomic_ptr */
        retl
         nop
 2:      BACKOFF_SPIN(%o2, %o3, 1b)
-        .size   atomic_sub, .-atomic_sub
+ENDPROC(atomic_sub)
-        .globl  atomic_add_ret
+ENTRY(atomic_add_ret) /* %o0 = increment, %o1 = atomic_ptr */
-        .type   atomic_add_ret,#function
-atomic_add_ret: /* %o0 = increment, %o1 = atomic_ptr */
        BACKOFF_SETUP(%o2)
 1:      lduw    [%o1], %g1
        add     %g1, %o0, %g7
@@ -56,11 +51,9 @@ atomic_add_ret: /* %o0 = increment, %o1 = atomic_ptr */
        retl
         sra    %g1, 0, %o0
 2:      BACKOFF_SPIN(%o2, %o3, 1b)
-        .size   atomic_add_ret, .-atomic_add_ret
+ENDPROC(atomic_add_ret)
-        .globl  atomic_sub_ret
+ENTRY(atomic_sub_ret) /* %o0 = decrement, %o1 = atomic_ptr */
-        .type   atomic_sub_ret,#function
-atomic_sub_ret: /* %o0 = decrement, %o1 = atomic_ptr */
        BACKOFF_SETUP(%o2)
 1:      lduw    [%o1], %g1
        sub     %g1, %o0, %g7
@@ -71,11 +64,9 @@ atomic_sub_ret: /* %o0 = decrement, %o1 = atomic_ptr */
        retl
         sra    %g1, 0, %o0
 2:      BACKOFF_SPIN(%o2, %o3, 1b)
-        .size   atomic_sub_ret, .-atomic_sub_ret
+ENDPROC(atomic_sub_ret)
-        .globl  atomic64_add
+ENTRY(atomic64_add) /* %o0 = increment, %o1 = atomic_ptr */
-        .type   atomic64_add,#function
-atomic64_add: /* %o0 = increment, %o1 = atomic_ptr */
        BACKOFF_SETUP(%o2)
 1:      ldx     [%o1], %g1
        add     %g1, %o0, %g7
@@ -86,11 +77,9 @@ atomic64_add: /* %o0 = increment, %o1 = atomic_ptr */
        retl
         nop
 2:      BACKOFF_SPIN(%o2, %o3, 1b)
-        .size   atomic64_add, .-atomic64_add
+ENDPROC(atomic64_add)
-        .globl  atomic64_sub
+ENTRY(atomic64_sub) /* %o0 = decrement, %o1 = atomic_ptr */
-        .type   atomic64_sub,#function
-atomic64_sub: /* %o0 = decrement, %o1 = atomic_ptr */
        BACKOFF_SETUP(%o2)
 1:      ldx     [%o1], %g1
        sub     %g1, %o0, %g7
@@ -101,11 +90,9 @@ atomic64_sub: /* %o0 = decrement, %o1 = atomic_ptr */
        retl
         nop
 2:      BACKOFF_SPIN(%o2, %o3, 1b)
-        .size   atomic64_sub, .-atomic64_sub
+ENDPROC(atomic64_sub)
-        .globl  atomic64_add_ret
+ENTRY(atomic64_add_ret) /* %o0 = increment, %o1 = atomic_ptr */
-        .type   atomic64_add_ret,#function
-atomic64_add_ret: /* %o0 = increment, %o1 = atomic_ptr */
        BACKOFF_SETUP(%o2)
 1:      ldx     [%o1], %g1
        add     %g1, %o0, %g7
@@ -116,11 +103,9 @@ atomic64_add_ret: /* %o0 = increment, %o1 = atomic_ptr */
        retl
         add    %g1, %o0, %o0
 2:      BACKOFF_SPIN(%o2, %o3, 1b)
-        .size   atomic64_add_ret, .-atomic64_add_ret
+ENDPROC(atomic64_add_ret)
-        .globl  atomic64_sub_ret
+ENTRY(atomic64_sub_ret) /* %o0 = decrement, %o1 = atomic_ptr */
-        .type   atomic64_sub_ret,#function
-atomic64_sub_ret: /* %o0 = decrement, %o1 = atomic_ptr */
        BACKOFF_SETUP(%o2)
 1:      ldx     [%o1], %g1
        sub     %g1, %o0, %g7
@@ -131,4 +116,4 @@ atomic64_sub_ret: /* %o0 = decrement, %o1 = atomic_ptr */
        retl
         sub    %g1, %o0, %o0
 2:      BACKOFF_SPIN(%o2, %o3, 1b)
-        .size   atomic64_sub_ret, .-atomic64_sub_ret
+ENDPROC(atomic64_sub_ret)
diff --git a/arch/sparc/lib/bitops.S b/arch/sparc/lib/bitops.S
index 3dc61d5537c0..36f72cc0e67e 100644
--- a/arch/sparc/lib/bitops.S
+++ b/arch/sparc/lib/bitops.S
@@ -3,14 +3,13 @@
 * Copyright (C) 2000, 2007 David S. Miller (davem@davemloft.net)
 */
+#include <linux/linkage.h>
 #include <asm/asi.h>
 #include <asm/backoff.h>
        .text
-        .globl  test_and_set_bit
+ENTRY(test_and_set_bit) /* %o0=nr, %o1=addr */
-        .type   test_and_set_bit,#function
-test_and_set_bit:       /* %o0=nr, %o1=addr */
        BACKOFF_SETUP(%o3)
        srlx    %o0, 6, %g1
        mov     1, %o2
@@ -29,11 +28,9 @@ test_and_set_bit:	/* %o0=nr, %o1=addr */
        retl
         nop
 2:      BACKOFF_SPIN(%o3, %o4, 1b)
-        .size   test_and_set_bit, .-test_and_set_bit
+ENDPROC(test_and_set_bit)
-        .globl  test_and_clear_bit
+ENTRY(test_and_clear_bit) /* %o0=nr, %o1=addr */
-        .type   test_and_clear_bit,#function
-test_and_clear_bit:     /* %o0=nr, %o1=addr */
        BACKOFF_SETUP(%o3)
        srlx    %o0, 6, %g1
        mov     1, %o2
@@ -52,11 +49,9 @@ test_and_clear_bit:	/* %o0=nr, %o1=addr */
        retl
         nop
 2:      BACKOFF_SPIN(%o3, %o4, 1b)
-        .size   test_and_clear_bit, .-test_and_clear_bit
+ENDPROC(test_and_clear_bit)
-        .globl  test_and_change_bit
+ENTRY(test_and_change_bit) /* %o0=nr, %o1=addr */
-        .type   test_and_change_bit,#function
-test_and_change_bit:    /* %o0=nr, %o1=addr */
        BACKOFF_SETUP(%o3)
        srlx    %o0, 6, %g1
        mov     1, %o2
@@ -75,11 +70,9 @@ test_and_change_bit:	/* %o0=nr, %o1=addr */
        retl
         nop
 2:      BACKOFF_SPIN(%o3, %o4, 1b)
-        .size   test_and_change_bit, .-test_and_change_bit
+ENDPROC(test_and_change_bit)
-        .globl  set_bit
+ENTRY(set_bit) /* %o0=nr, %o1=addr */
-        .type   set_bit,#function
-set_bit:                /* %o0=nr, %o1=addr */
        BACKOFF_SETUP(%o3)
        srlx    %o0, 6, %g1
        mov     1, %o2
@@ -96,11 +89,9 @@ set_bit:		/* %o0=nr, %o1=addr */
        retl
         nop
 2:      BACKOFF_SPIN(%o3, %o4, 1b)
-        .size   set_bit, .-set_bit
+ENDPROC(set_bit)
-        .globl  clear_bit
+ENTRY(clear_bit) /* %o0=nr, %o1=addr */
-        .type   clear_bit,#function
-clear_bit:              /* %o0=nr, %o1=addr */
        BACKOFF_SETUP(%o3)
        srlx    %o0, 6, %g1
        mov     1, %o2
@@ -117,11 +108,9 @@ clear_bit:		/* %o0=nr, %o1=addr */
        retl
         nop
 2:      BACKOFF_SPIN(%o3, %o4, 1b)
-        .size   clear_bit, .-clear_bit
+ENDPROC(clear_bit)
-        .globl  change_bit
+ENTRY(change_bit) /* %o0=nr, %o1=addr */
-        .type   change_bit,#function
-change_bit:             /* %o0=nr, %o1=addr */
        BACKOFF_SETUP(%o3)
        srlx    %o0, 6, %g1
        mov     1, %o2
@@ -138,4 +127,4 @@ change_bit:		/* %o0=nr, %o1=addr */
        retl
         nop
 2:      BACKOFF_SPIN(%o3, %o4, 1b)
-        .size   change_bit, .-change_bit
+ENDPROC(change_bit)
diff --git a/arch/sparc/lib/blockops.S b/arch/sparc/lib/blockops.S
index 804be87f9a42..3c771011ff4b 100644
--- a/arch/sparc/lib/blockops.S
+++ b/arch/sparc/lib/blockops.S
@@ -4,6 +4,7 @@
 * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
 */
+#include <linux/linkage.h>
 #include <asm/page.h>
        /* Zero out 64 bytes of memory at (buf + offset).
@@ -44,10 +45,7 @@
         */
        .text
-        .align  4
+ENTRY(bzero_1page)
-        .globl  bzero_1page, __copy_1page
-bzero_1page:
 /* NOTE: If you change the number of insns of this routine, please check
 * arch/sparc/mm/hypersparc.S */
        /* %o0 = buf */
@@ -65,8 +63,9 @@ bzero_1page:
        retl
         nop
+ENDPROC(bzero_1page)
-__copy_1page:
+ENTRY(__copy_1page)
 /* NOTE: If you change the number of insns of this routine, please check
 * arch/sparc/mm/hypersparc.S */
        /* %o0 = dst, %o1 = src */
@@ -87,3 +86,4 @@ __copy_1page:
        retl
         nop
+ENDPROC(__copy_1page)
diff --git a/arch/sparc/lib/bzero.S b/arch/sparc/lib/bzero.S
index 615f401edf69..8c058114b649 100644
--- a/arch/sparc/lib/bzero.S
+++ b/arch/sparc/lib/bzero.S
@@ -4,11 +4,11 @@
 * Copyright (C) 2005 David S. Miller <davem@davemloft.net>
 */
+#include <linux/linkage.h>
        .text
-        .globl  memset
+ENTRY(memset) /* %o0=buf, %o1=pat, %o2=len */
-        .type   memset, #function
-memset:                 /* %o0=buf, %o1=pat, %o2=len */
        and             %o1, 0xff, %o3
        mov             %o2, %o1
        sllx            %o3, 8, %g1
@@ -19,9 +19,7 @@ memset:			/* %o0=buf, %o1=pat, %o2=len */
        ba,pt           %xcc, 1f
         or             %g1, %o2, %o2
-        .globl  __bzero
+ENTRY(__bzero) /* %o0=buf, %o1=len */
-        .type   __bzero, #function
-__bzero:                /* %o0=buf, %o1=len */
        clr             %o2
 1:      mov             %o0, %o3
        brz,pn          %o1, __bzero_done
@@ -78,8 +76,8 @@ __bzero_tiny:
 __bzero_done:
        retl
         mov            %o3, %o0
-        .size           __bzero, .-__bzero
+ENDPROC(__bzero)
-        .size           memset, .-memset
+ENDPROC(memset)
 #define EX_ST(x,y)              \
 98:     x,y;                    \
@@ -89,9 +87,7 @@ __bzero_done:
        .text;                  \
        .align 4;
-        .globl  __clear_user
+ENTRY(__clear_user) /* %o0=buf, %o1=len */
-        .type   __clear_user, #function
-__clear_user:           /* %o0=buf, %o1=len */
        brz,pn          %o1, __clear_user_done
         cmp            %o1, 16
        bl,pn           %icc, __clear_user_tiny
@@ -146,4 +142,4 @@ __clear_user_tiny:
 __clear_user_done:
        retl
         clr            %o0
-        .size           __clear_user, .-__clear_user
+ENDPROC(__clear_user)
diff --git a/arch/sparc/lib/divdi3.S b/arch/sparc/lib/divdi3.S
index d74bc0925f2d..9614b48b6ef8 100644
--- a/arch/sparc/lib/divdi3.S
+++ b/arch/sparc/lib/divdi3.S
@@ -19,7 +19,6 @@ Boston, MA 02111-1307, USA.  */
        .text
        .align 4
-        .global .udiv
        .globl __divdi3
 __divdi3:
        save %sp,-104,%sp
@@ -83,8 +82,9 @@ __divdi3:
        bne .LL85
        mov %i0,%o2
        mov 1,%o0
-        call .udiv,0
        mov 0,%o1
+        wr %g0, 0, %y
+        udiv %o0, %o1, %o0
        mov %o0,%o4
        mov %i0,%o2
 .LL85:
diff --git a/arch/sparc/lib/ipcsum.S b/arch/sparc/lib/ipcsum.S
index 58ca5b9a8778..4742d59029ee 100644
--- a/arch/sparc/lib/ipcsum.S
+++ b/arch/sparc/lib/ipcsum.S
@@ -1,8 +1,7 @@
+#include <linux/linkage.h>
        .text
-        .align  32
+ENTRY(ip_fast_csum) /* %o0 = iph, %o1 = ihl */
-        .globl  ip_fast_csum
-        .type   ip_fast_csum,#function
-ip_fast_csum:   /* %o0 = iph, %o1 = ihl */
        sub     %o1, 4, %g7
        lduw    [%o0 + 0x00], %o2
        lduw    [%o0 + 0x04], %g2
@@ -31,4 +30,4 @@ ip_fast_csum:	/* %o0 = iph, %o1 = ihl */
        set     0xffff, %o1
        retl
         and    %o2, %o1, %o0
-        .size   ip_fast_csum, .-ip_fast_csum
+ENDPROC(ip_fast_csum)
diff --git a/arch/sparc/lib/ksyms.c b/arch/sparc/lib/ksyms.c
index f73c2240fe60..2dc30875c8bc 100644
--- a/arch/sparc/lib/ksyms.c
+++ b/arch/sparc/lib/ksyms.c
@@ -56,23 +56,11 @@ extern int __divdi3(int, int);
 extern void (*__copy_1page)(void *, const void *);
 extern void (*bzero_1page)(void *);
-extern int __strncmp(const char *, const char *, __kernel_size_t);
 extern void ___rw_read_enter(void);
 extern void ___rw_read_try(void);
 extern void ___rw_read_exit(void);
 extern void ___rw_write_enter(void);
-/* Alias functions whose names begin with "." and export the aliases.
- * The module references will be fixed up by module_frob_arch_sections.
- */
-extern int _Div(int, int);
-extern int _Mul(int, int);
-extern int _Rem(int, int);
-extern unsigned _Udiv(unsigned, unsigned);
-extern unsigned _Umul(unsigned, unsigned);
-extern unsigned _Urem(unsigned, unsigned);
 /* Networking helper routines. */
 EXPORT_SYMBOL(__csum_partial_copy_sparc_generic);
@@ -81,9 +69,6 @@ EXPORT_SYMBOL(__copy_1page);
 EXPORT_SYMBOL(__memmove);
 EXPORT_SYMBOL(bzero_1page);
-/* string functions */
-EXPORT_SYMBOL(__strncmp);
 /* Moving data to/from/in userspace. */
 EXPORT_SYMBOL(__copy_user);
@@ -100,13 +85,6 @@ EXPORT_SYMBOL(__ashldi3);
 EXPORT_SYMBOL(__lshrdi3);
 EXPORT_SYMBOL(__muldi3);
 EXPORT_SYMBOL(__divdi3);
-EXPORT_SYMBOL(_Rem);
-EXPORT_SYMBOL(_Urem);
-EXPORT_SYMBOL(_Mul);
-EXPORT_SYMBOL(_Umul);
-EXPORT_SYMBOL(_Div);
-EXPORT_SYMBOL(_Udiv);
 #endif
 /*
diff --git a/arch/sparc/lib/lshrdi3.S b/arch/sparc/lib/lshrdi3.S
index 47a1354c1602..60ebc7cdbee0 100644
--- a/arch/sparc/lib/lshrdi3.S
+++ b/arch/sparc/lib/lshrdi3.S
@@ -1,6 +1,6 @@
+#include <linux/linkage.h>
-        .globl  __lshrdi3
+ENTRY(__lshrdi3)
-__lshrdi3:
        cmp     %o2, 0
        be      3f
         mov    0x20, %g2
@@ -24,3 +24,4 @@ __lshrdi3:
 3:
        retl 
         nop 
+ENDPROC(__lshrdi3)
diff --git a/arch/sparc/lib/memmove.S b/arch/sparc/lib/memmove.S
index 97395802c23c..b7f6334e159f 100644
--- a/arch/sparc/lib/memmove.S
+++ b/arch/sparc/lib/memmove.S
@@ -4,11 +4,10 @@
 * Copyright (C) 1996, 1997, 1998, 1999 Jakub Jelinek (jj@ultra.linux.cz)
 */
+#include <linux/linkage.h>
        .text
-        .align          32
+ENTRY(memmove) /* o0=dst o1=src o2=len */
-        .globl          memmove
-        .type           memmove,#function
-memmove:                /* o0=dst o1=src o2=len */
        mov             %o0, %g1
        cmp             %o0, %o1
        bleu,pt         %xcc, memcpy
@@ -28,4 +27,4 @@ memmove:		/* o0=dst o1=src o2=len */
        retl
         mov            %g1, %o0
-        .size           memmove, .-memmove
+ENDPROC(memmove)
diff --git a/arch/sparc/lib/mul.S b/arch/sparc/lib/mul.S
deleted file mode 100644
index c45470d0b0ce..000000000000
--- a/arch/sparc/lib/mul.S
+++ /dev/null
@@ -1,137 +0,0 @@
-/*
- * mul.S:       This routine was taken from glibc-1.09 and is covered
- *              by the GNU Library General Public License Version 2.
- */
-/*
- * Signed multiply, from Appendix E of the Sparc Version 8
- * Architecture Manual.
- */
-/*
- * Returns %o0 * %o1 in %o1%o0 (i.e., %o1 holds the upper 32 bits of
- * the 64-bit product).
- *
- * This code optimizes short (less than 13-bit) multiplies.
- */
-        .globl .mul
-        .globl _Mul
-.mul:
-_Mul:   /* needed for export */
-        mov     %o0, %y         ! multiplier -> Y
-        andncc  %o0, 0xfff, %g0 ! test bits 12..31
-        be      Lmul_shortway   ! if zero, can do it the short way
-         andcc  %g0, %g0, %o4   ! zero the partial product and clear N and V
-        /*
-         * Long multiply.  32 steps, followed by a final shift step.
-         */
-        mulscc  %o4, %o1, %o4   ! 1
-        mulscc  %o4, %o1, %o4   ! 2
-        mulscc  %o4, %o1, %o4   ! 3
-        mulscc  %o4, %o1, %o4   ! 4
-        mulscc  %o4, %o1, %o4   ! 5
-        mulscc  %o4, %o1, %o4   ! 6
-        mulscc  %o4, %o1, %o4   ! 7
-        mulscc  %o4, %o1, %o4   ! 8
-        mulscc  %o4, %o1, %o4   ! 9
-        mulscc  %o4, %o1, %o4   ! 10
-        mulscc  %o4, %o1, %o4   ! 11
-        mulscc  %o4, %o1, %o4   ! 12
-        mulscc  %o4, %o1, %o4   ! 13
-        mulscc  %o4, %o1, %o4   ! 14
-        mulscc  %o4, %o1, %o4   ! 15
-        mulscc  %o4, %o1, %o4   ! 16
-        mulscc  %o4, %o1, %o4   ! 17
-        mulscc  %o4, %o1, %o4   ! 18
-        mulscc  %o4, %o1, %o4   ! 19
-        mulscc  %o4, %o1, %o4   ! 20
-        mulscc  %o4, %o1, %o4   ! 21
-        mulscc  %o4, %o1, %o4   ! 22
-        mulscc  %o4, %o1, %o4   ! 23
-        mulscc  %o4, %o1, %o4   ! 24
-        mulscc  %o4, %o1, %o4   ! 25
-        mulscc  %o4, %o1, %o4   ! 26
-        mulscc  %o4, %o1, %o4   ! 27
-        mulscc  %o4, %o1, %o4   ! 28
-        mulscc  %o4, %o1, %o4   ! 29
-        mulscc  %o4, %o1, %o4   ! 30
-        mulscc  %o4, %o1, %o4   ! 31
-        mulscc  %o4, %o1, %o4   ! 32
-        mulscc  %o4, %g0, %o4   ! final shift
-        ! If %o0 was negative, the result is
-        !       (%o0 * %o1) + (%o1 << 32))
-        ! We fix that here.
-#if 0
-        tst     %o0
-        bge     1f
-         rd     %y, %o0
-        ! %o0 was indeed negative; fix upper 32 bits of result by subtracting 
-        ! %o1 (i.e., return %o4 - %o1 in %o1).
-        retl
-         sub    %o4, %o1, %o1
-1:
-        retl
-         mov    %o4, %o1
-#else
-        /* Faster code adapted from tege@sics.se's code for umul.S.  */
-        sra     %o0, 31, %o2    ! make mask from sign bit
-        and     %o1, %o2, %o2   ! %o2 = 0 or %o1, depending on sign of %o0
-        rd      %y, %o0         ! get lower half of product
-        retl
-         sub    %o4, %o2, %o1   ! subtract compensation 
-                                !  and put upper half in place
-#endif
-Lmul_shortway:
-        /*
-         * Short multiply.  12 steps, followed by a final shift step.
-         * The resulting bits are off by 12 and (32-12) = 20 bit positions,
-         * but there is no problem with %o0 being negative (unlike above).
-         */
-        mulscc  %o4, %o1, %o4   ! 1
-        mulscc  %o4, %o1, %o4   ! 2
-        mulscc  %o4, %o1, %o4   ! 3
-        mulscc  %o4, %o1, %o4   ! 4
-        mulscc  %o4, %o1, %o4   ! 5
-        mulscc  %o4, %o1, %o4   ! 6
-        mulscc  %o4, %o1, %o4   ! 7
-        mulscc  %o4, %o1, %o4   ! 8
-        mulscc  %o4, %o1, %o4   ! 9
-        mulscc  %o4, %o1, %o4   ! 10
-        mulscc  %o4, %o1, %o4   ! 11
-        mulscc  %o4, %o1, %o4   ! 12
-        mulscc  %o4, %g0, %o4   ! final shift
-        /*
-         *  %o4 has 20 of the bits that should be in the low part of the
-         * result; %y has the bottom 12 (as %y's top 12).  That is:
-         *
-         *        %o4               %y
-         * +----------------+----------------+
-         * | -12- |   -20-  | -12- |   -20-  |
-         * +------(---------+------)---------+
-         *  --hi-- ----low-part----
-         *
-         * The upper 12 bits of %o4 should be sign-extended to form the
-         * high part of the product (i.e., highpart = %o4 >> 20).
-         */
-        rd      %y, %o5
-        sll     %o4, 12, %o0    ! shift middle bits left 12
-        srl     %o5, 20, %o5    ! shift low bits right 20, zero fill at left
-        or      %o5, %o0, %o0   ! construct low part of result
-        retl
-         sra    %o4, 20, %o1    ! ... and extract high part of result
-        .globl  .mul_patch
-.mul_patch:
-        smul    %o0, %o1, %o0
-        retl
-         rd     %y, %o1
-        nop
diff --git a/arch/sparc/lib/muldi3.S b/arch/sparc/lib/muldi3.S
index 7f17872d0603..9794939d1c12 100644
--- a/arch/sparc/lib/muldi3.S
+++ b/arch/sparc/lib/muldi3.S
@@ -63,12 +63,12 @@ __muldi3:
        rd  %y, %o1
        mov  %o1, %l3
        mov  %i1, %o0
-        call  .umul
        mov  %i2, %o1
+        umul %o0, %o1, %o0
        mov  %o0, %l0
        mov  %i0, %o0
-        call  .umul
        mov  %i3, %o1
+        umul %o0, %o1, %o0
        add  %l0, %o0, %l0
        mov  %l2, %i0
        add  %l2, %l0, %i0
diff --git a/arch/sparc/lib/rem.S b/arch/sparc/lib/rem.S
deleted file mode 100644
index 42fb86252815..000000000000
--- a/arch/sparc/lib/rem.S
+++ /dev/null
@@ -1,384 +0,0 @@
-/*
- * rem.S:       This routine was taken from glibc-1.09 and is covered
- *              by the GNU Library General Public License Version 2.
- */
-/* This file is generated from divrem.m4; DO NOT EDIT! */
-/*
- * Division and remainder, from Appendix E of the Sparc Version 8
- * Architecture Manual, with fixes from Gordon Irlam.
- */
-/*
- * Input: dividend and divisor in %o0 and %o1 respectively.
- *
- * m4 parameters:
- *  .rem        name of function to generate
- *  rem         rem=div => %o0 / %o1; rem=rem => %o0 % %o1
- *  true                true=true => signed; true=false => unsigned
- *
- * Algorithm parameters:
- *  N           how many bits per iteration we try to get (4)
- *  WORDSIZE    total number of bits (32)
- *
- * Derived constants:
- *  TOPBITS     number of bits in the top decade of a number
- *
- * Important variables:
- *  Q           the partial quotient under development (initially 0)
- *  R           the remainder so far, initially the dividend
- *  ITER        number of main division loop iterations required;
- *              equal to ceil(log2(quotient) / N).  Note that this
- *              is the log base (2^N) of the quotient.
- *  V           the current comparand, initially divisor*2^(ITER*N-1)
- *
- * Cost:
- *  Current estimate for non-large dividend is
- *      ceil(log2(quotient) / N) * (10 + 7N/2) + C
- *  A large dividend is one greater than 2^(31-TOPBITS) and takes a
- *  different path, as the upper bits of the quotient must be developed
- *  one bit at a time.
- */
-        .globl .rem
-        .globl _Rem
-.rem:
-_Rem:   /* needed for export */
-        ! compute sign of result; if neither is negative, no problem
-        orcc    %o1, %o0, %g0   ! either negative?
-        bge     2f                      ! no, go do the divide
-         mov    %o0, %g2        ! compute sign in any case
-        tst     %o1
-        bge     1f
-         tst    %o0
-        ! %o1 is definitely negative; %o0 might also be negative
-        bge     2f                      ! if %o0 not negative...
-         sub    %g0, %o1, %o1   ! in any case, make %o1 nonneg
-1:      ! %o0 is negative, %o1 is nonnegative
-        sub     %g0, %o0, %o0   ! make %o0 nonnegative
-2:
-        ! Ready to divide.  Compute size of quotient; scale comparand.
-        orcc    %o1, %g0, %o5
-        bne     1f
-         mov    %o0, %o3
-                ! Divide by zero trap.  If it returns, return 0 (about as
-                ! wrong as possible, but that is what SunOS does...).
-                ta      ST_DIV0
-                retl
-                 clr    %o0
-1:
-        cmp     %o3, %o5                        ! if %o1 exceeds %o0, done
-        blu     Lgot_result             ! (and algorithm fails otherwise)
-         clr    %o2
-        sethi   %hi(1 << (32 - 4 - 1)), %g1
-        cmp     %o3, %g1
-        blu     Lnot_really_big
-         clr    %o4
-        ! Here the dividend is >= 2**(31-N) or so.  We must be careful here,
-        ! as our usual N-at-a-shot divide step will cause overflow and havoc.
-        ! The number of bits in the result here is N*ITER+SC, where SC <= N.
-        ! Compute ITER in an unorthodox manner: know we need to shift V into
-        ! the top decade: so do not even bother to compare to R.
-        1:
-                cmp     %o5, %g1
-                bgeu    3f
-                 mov    1, %g7
-                sll     %o5, 4, %o5
-                b       1b
-                 add    %o4, 1, %o4
-        ! Now compute %g7.
-        2:
-                addcc   %o5, %o5, %o5
-                bcc     Lnot_too_big
-                 add    %g7, 1, %g7
-                ! We get here if the %o1 overflowed while shifting.
-                ! This means that %o3 has the high-order bit set.
-                ! Restore %o5 and subtract from %o3.
-                sll     %g1, 4, %g1     ! high order bit
-                srl     %o5, 1, %o5             ! rest of %o5
-                add     %o5, %g1, %o5
-                b       Ldo_single_div
-                 sub    %g7, 1, %g7
-        Lnot_too_big:
-        3:
-                cmp     %o5, %o3
-                blu     2b
-                 nop
-                be      Ldo_single_div
-                 nop
-        /* NB: these are commented out in the V8-Sparc manual as well */
-        /* (I do not understand this) */
-        ! %o5 > %o3: went too far: back up 1 step
-        !       srl     %o5, 1, %o5
-        !       dec     %g7
-        ! do single-bit divide steps
-        !
-        ! We have to be careful here.  We know that %o3 >= %o5, so we can do the
-        ! first divide step without thinking.  BUT, the others are conditional,
-        ! and are only done if %o3 >= 0.  Because both %o3 and %o5 may have the high-
-        ! order bit set in the first step, just falling into the regular
-        ! division loop will mess up the first time around.
-        ! So we unroll slightly...
-        Ldo_single_div:
-                subcc   %g7, 1, %g7
-                bl      Lend_regular_divide
-                 nop
-                sub     %o3, %o5, %o3
-                mov     1, %o2
-                b       Lend_single_divloop
-                 nop
-        Lsingle_divloop:
-                sll     %o2, 1, %o2
-                bl      1f
-                 srl    %o5, 1, %o5
-                ! %o3 >= 0
-                sub     %o3, %o5, %o3
-                b       2f
-                 add    %o2, 1, %o2
-        1:      ! %o3 < 0
-                add     %o3, %o5, %o3
-                sub     %o2, 1, %o2
-        2:
-        Lend_single_divloop:
-                subcc   %g7, 1, %g7
-                bge     Lsingle_divloop
-                 tst    %o3
-                b,a     Lend_regular_divide
-Lnot_really_big:
-1:
-        sll     %o5, 4, %o5
-        cmp     %o5, %o3
-        bleu    1b
-         addcc  %o4, 1, %o4
-        be      Lgot_result
-         sub    %o4, 1, %o4
-        tst     %o3     ! set up for initial iteration
-Ldivloop:
-        sll     %o2, 4, %o2
-                ! depth 1, accumulated bits 0
-        bl      L.1.16
-         srl    %o5,1,%o5
-        ! remainder is positive
-        subcc   %o3,%o5,%o3
-                        ! depth 2, accumulated bits 1
-        bl      L.2.17
-         srl    %o5,1,%o5
-        ! remainder is positive
-        subcc   %o3,%o5,%o3
-                        ! depth 3, accumulated bits 3
-        bl      L.3.19
-         srl    %o5,1,%o5
-        ! remainder is positive
-        subcc   %o3,%o5,%o3
-                        ! depth 4, accumulated bits 7
-        bl      L.4.23
-         srl    %o5,1,%o5
-        ! remainder is positive
-        subcc   %o3,%o5,%o3
-        b       9f
-         add    %o2, (7*2+1), %o2
-        
-L.4.23:
-        ! remainder is negative
-        addcc   %o3,%o5,%o3
-        b       9f
-         add    %o2, (7*2-1), %o2
-        
-L.3.19:
-        ! remainder is negative
-        addcc   %o3,%o5,%o3
-                        ! depth 4, accumulated bits 5
-        bl      L.4.21
-         srl    %o5,1,%o5
-        ! remainder is positive
-        subcc   %o3,%o5,%o3
-        b       9f
-         add    %o2, (5*2+1), %o2
-        
-L.4.21:
-        ! remainder is negative
-        addcc   %o3,%o5,%o3
-        b       9f
-         add    %o2, (5*2-1), %o2
-        
-L.2.17:
-        ! remainder is negative
-        addcc   %o3,%o5,%o3
-                        ! depth 3, accumulated bits 1
-        bl      L.3.17
-         srl    %o5,1,%o5
-        ! remainder is positive
-        subcc   %o3,%o5,%o3
-                        ! depth 4, accumulated bits 3
-        bl      L.4.19
-         srl    %o5,1,%o5
-        ! remainder is positive
-        subcc   %o3,%o5,%o3
-        b       9f
-         add    %o2, (3*2+1), %o2
-L.4.19:
-        ! remainder is negative
-        addcc   %o3,%o5,%o3
-        b       9f
-         add    %o2, (3*2-1), %o2
-L.3.17:
-        ! remainder is negative
-        addcc   %o3,%o5,%o3
-                        ! depth 4, accumulated bits 1
-        bl      L.4.17
-         srl    %o5,1,%o5
-        ! remainder is positive
-        subcc   %o3,%o5,%o3
-        b       9f
-         add    %o2, (1*2+1), %o2
-L.4.17:
-        ! remainder is negative
-        addcc   %o3,%o5,%o3
-        b       9f
-         add    %o2, (1*2-1), %o2
-L.1.16:
-        ! remainder is negative
-        addcc   %o3,%o5,%o3
-                        ! depth 2, accumulated bits -1
-        bl      L.2.15
-         srl    %o5,1,%o5
-        ! remainder is positive
-        subcc   %o3,%o5,%o3
-                        ! depth 3, accumulated bits -1
-        bl      L.3.15
-         srl    %o5,1,%o5
-        ! remainder is positive
-        subcc   %o3,%o5,%o3
-                        ! depth 4, accumulated bits -1
-        bl      L.4.15
-         srl    %o5,1,%o5
-        ! remainder is positive
-        subcc   %o3,%o5,%o3
-        b       9f
-         add    %o2, (-1*2+1), %o2
-L.4.15:
-        ! remainder is negative
-        addcc   %o3,%o5,%o3
-        b       9f
-         add    %o2, (-1*2-1), %o2
-L.3.15:
-        ! remainder is negative
-        addcc   %o3,%o5,%o3
-                        ! depth 4, accumulated bits -3
-        bl      L.4.13
-         srl    %o5,1,%o5
-        ! remainder is positive
-        subcc   %o3,%o5,%o3
-        b       9f
-         add    %o2, (-3*2+1), %o2
-L.4.13:
-        ! remainder is negative
-        addcc   %o3,%o5,%o3
-        b       9f
-         add    %o2, (-3*2-1), %o2
-L.2.15:
-        ! remainder is negative
-        addcc   %o3,%o5,%o3
-                        ! depth 3, accumulated bits -3
-        bl      L.3.13
-         srl    %o5,1,%o5
-        ! remainder is positive
-        subcc   %o3,%o5,%o3
-                        ! depth 4, accumulated bits -5
-        bl      L.4.11
-         srl    %o5,1,%o5
-        ! remainder is positive
-        subcc   %o3,%o5,%o3
-        b       9f
-         add    %o2, (-5*2+1), %o2
-L.4.11:
-        ! remainder is negative
-        addcc   %o3,%o5,%o3
-        b       9f
-         add    %o2, (-5*2-1), %o2
-L.3.13:
-        ! remainder is negative
-        addcc   %o3,%o5,%o3
-                        ! depth 4, accumulated bits -7
-        bl      L.4.9
-         srl    %o5,1,%o5
-        ! remainder is positive
-        subcc   %o3,%o5,%o3
-        b       9f
-         add    %o2, (-7*2+1), %o2
-L.4.9:
-        ! remainder is negative
-        addcc   %o3,%o5,%o3
-        b       9f
-         add    %o2, (-7*2-1), %o2
-        9:
-Lend_regular_divide:
-        subcc   %o4, 1, %o4
-        bge     Ldivloop
-         tst    %o3
-        bl,a    Lgot_result
-        ! non-restoring fixup here (one instruction only!)
-        add     %o3, %o1, %o3
-Lgot_result:
-        ! check to see if answer should be < 0
-        tst     %g2
-        bl,a    1f
-         sub %g0, %o3, %o3
-1:
-        retl
-         mov %o3, %o0
-        .globl  .rem_patch
-.rem_patch:
-        sra     %o0, 0x1f, %o4
-        wr      %o4, 0x0, %y
-        nop
-        nop
-        nop
-        sdivcc  %o0, %o1, %o2
-        bvs,a   1f
-         xnor   %o2, %g0, %o2
-1:      smul    %o2, %o1, %o2
-        retl
-         sub    %o0, %o2, %o0
-        nop
diff --git a/arch/sparc/lib/sdiv.S b/arch/sparc/lib/sdiv.S
deleted file mode 100644
index f0a0d4e4db78..000000000000
--- a/arch/sparc/lib/sdiv.S
+++ /dev/null
@@ -1,381 +0,0 @@
-/*
- * sdiv.S:      This routine was taken from glibc-1.09 and is covered
- *              by the GNU Library General Public License Version 2.
- */
-/* This file is generated from divrem.m4; DO NOT EDIT! */
-/*
- * Division and remainder, from Appendix E of the Sparc Version 8
- * Architecture Manual, with fixes from Gordon Irlam.
- */
-/*
- * Input: dividend and divisor in %o0 and %o1 respectively.
- *
- * m4 parameters:
- *  .div        name of function to generate
- *  div         div=div => %o0 / %o1; div=rem => %o0 % %o1
- *  true                true=true => signed; true=false => unsigned
- *
- * Algorithm parameters:
- *  N           how many bits per iteration we try to get (4)
- *  WORDSIZE    total number of bits (32)
- *
- * Derived constants:
- *  TOPBITS     number of bits in the top decade of a number
- *
- * Important variables:
- *  Q           the partial quotient under development (initially 0)
- *  R           the remainder so far, initially the dividend
- *  ITER        number of main division loop iterations required;
- *              equal to ceil(log2(quotient) / N).  Note that this
- *              is the log base (2^N) of the quotient.
- *  V           the current comparand, initially divisor*2^(ITER*N-1)
- *
- * Cost:
- *  Current estimate for non-large dividend is
- *      ceil(log2(quotient) / N) * (10 + 7N/2) + C
- *  A large dividend is one greater than 2^(31-TOPBITS) and takes a
- *  different path, as the upper bits of the quotient must be developed
- *  one bit at a time.
- */
-        .globl .div
-        .globl _Div
-.div:
-_Div:   /* needed for export */
-        ! compute sign of result; if neither is negative, no problem
-        orcc    %o1, %o0, %g0   ! either negative?
-        bge     2f                      ! no, go do the divide
-         xor    %o1, %o0, %g2   ! compute sign in any case
-        tst     %o1
-        bge     1f
-         tst    %o0
-        ! %o1 is definitely negative; %o0 might also be negative
-        bge     2f                      ! if %o0 not negative...
-         sub    %g0, %o1, %o1   ! in any case, make %o1 nonneg
-1:      ! %o0 is negative, %o1 is nonnegative
-        sub     %g0, %o0, %o0   ! make %o0 nonnegative
-2:
-        ! Ready to divide.  Compute size of quotient; scale comparand.
-        orcc    %o1, %g0, %o5
-        bne     1f
-         mov    %o0, %o3
-                ! Divide by zero trap.  If it returns, return 0 (about as
-                ! wrong as possible, but that is what SunOS does...).
-                ta      ST_DIV0
-                retl
-                 clr    %o0
-1:
-        cmp     %o3, %o5                        ! if %o1 exceeds %o0, done
-        blu     Lgot_result             ! (and algorithm fails otherwise)
-         clr    %o2
-        sethi   %hi(1 << (32 - 4 - 1)), %g1
-        cmp     %o3, %g1
-        blu     Lnot_really_big
-         clr    %o4
-        ! Here the dividend is >= 2**(31-N) or so.  We must be careful here,
-        ! as our usual N-at-a-shot divide step will cause overflow and havoc.
-        ! The number of bits in the result here is N*ITER+SC, where SC <= N.
-        ! Compute ITER in an unorthodox manner: know we need to shift V into
-        ! the top decade: so do not even bother to compare to R.
-        1:
-                cmp     %o5, %g1
-                bgeu    3f
-                 mov    1, %g7
-                sll     %o5, 4, %o5
-                b       1b
-                 add    %o4, 1, %o4
-        ! Now compute %g7.
-        2:
-                addcc   %o5, %o5, %o5
-                bcc     Lnot_too_big
-                 add    %g7, 1, %g7
-                ! We get here if the %o1 overflowed while shifting.
-                ! This means that %o3 has the high-order bit set.
-                ! Restore %o5 and subtract from %o3.
-                sll     %g1, 4, %g1     ! high order bit
-                srl     %o5, 1, %o5             ! rest of %o5
-                add     %o5, %g1, %o5
-                b       Ldo_single_div
-                 sub    %g7, 1, %g7
-        Lnot_too_big:
-        3:
-                cmp     %o5, %o3
-                blu     2b
-                 nop
-                be      Ldo_single_div
-                 nop
-        /* NB: these are commented out in the V8-Sparc manual as well */
-        /* (I do not understand this) */
-        ! %o5 > %o3: went too far: back up 1 step
-        !       srl     %o5, 1, %o5
-        !       dec     %g7
-        ! do single-bit divide steps
-        !
-        ! We have to be careful here.  We know that %o3 >= %o5, so we can do the
-        ! first divide step without thinking.  BUT, the others are conditional,
-        ! and are only done if %o3 >= 0.  Because both %o3 and %o5 may have the high-
-        ! order bit set in the first step, just falling into the regular
-        ! division loop will mess up the first time around.
-        ! So we unroll slightly...
-        Ldo_single_div:
-                subcc   %g7, 1, %g7
-                bl      Lend_regular_divide
-                 nop
-                sub     %o3, %o5, %o3
-                mov     1, %o2
-                b       Lend_single_divloop
-                 nop
-        Lsingle_divloop:
-                sll     %o2, 1, %o2
-                bl      1f
-                 srl    %o5, 1, %o5
-                ! %o3 >= 0
-                sub     %o3, %o5, %o3
-                b       2f
-                 add    %o2, 1, %o2
-        1:      ! %o3 < 0
-                add     %o3, %o5, %o3
-                sub     %o2, 1, %o2
-        2:
-        Lend_single_divloop:
-                subcc   %g7, 1, %g7
-                bge     Lsingle_divloop
-                 tst    %o3
-                b,a     Lend_regular_divide
-Lnot_really_big:
-1:
-        sll     %o5, 4, %o5
-        cmp     %o5, %o3
-        bleu    1b
-         addcc  %o4, 1, %o4
-        be      Lgot_result
-         sub    %o4, 1, %o4
-        tst     %o3     ! set up for initial iteration
-Ldivloop:
-        sll     %o2, 4, %o2
-                ! depth 1, accumulated bits 0
-        bl      L.1.16
-         srl    %o5,1,%o5
-        ! remainder is positive
-        subcc   %o3,%o5,%o3
-                        ! depth 2, accumulated bits 1
-        bl      L.2.17
-         srl    %o5,1,%o5
-        ! remainder is positive
-        subcc   %o3,%o5,%o3
-                        ! depth 3, accumulated bits 3
-        bl      L.3.19
-         srl    %o5,1,%o5
-        ! remainder is positive
-        subcc   %o3,%o5,%o3
-                        ! depth 4, accumulated bits 7
-        bl      L.4.23
-         srl    %o5,1,%o5
-        ! remainder is positive
-        subcc   %o3,%o5,%o3
-        b       9f
-         add    %o2, (7*2+1), %o2
-L.4.23:
-        ! remainder is negative
-        addcc   %o3,%o5,%o3
-        b       9f
-         add    %o2, (7*2-1), %o2
-L.3.19:
-        ! remainder is negative
-        addcc   %o3,%o5,%o3
-                        ! depth 4, accumulated bits 5
-        bl      L.4.21
-         srl    %o5,1,%o5
-        ! remainder is positive
-        subcc   %o3,%o5,%o3
-        b       9f
-         add    %o2, (5*2+1), %o2
-L.4.21:
-        ! remainder is negative
-        addcc   %o3,%o5,%o3
-        b       9f
-         add    %o2, (5*2-1), %o2
-L.2.17:
-        ! remainder is negative
-        addcc   %o3,%o5,%o3
-                        ! depth 3, accumulated bits 1
-        bl      L.3.17
-         srl    %o5,1,%o5
-        ! remainder is positive
-        subcc   %o3,%o5,%o3
-                        ! depth 4, accumulated bits 3
-        bl      L.4.19
-         srl    %o5,1,%o5
-        ! remainder is positive
-        subcc   %o3,%o5,%o3
-        b       9f
-         add    %o2, (3*2+1), %o2
-L.4.19:
-        ! remainder is negative
-        addcc   %o3,%o5,%o3
-        b       9f
-         add    %o2, (3*2-1), %o2
-        
-        
-L.3.17:
-        ! remainder is negative
-        addcc   %o3,%o5,%o3
-                        ! depth 4, accumulated bits 1
-        bl      L.4.17
-         srl    %o5,1,%o5
-        ! remainder is positive
-        subcc   %o3,%o5,%o3
-        b       9f
-         add    %o2, (1*2+1), %o2
-L.4.17:
-        ! remainder is negative
-        addcc   %o3,%o5,%o3
-        b       9f
-         add    %o2, (1*2-1), %o2
-L.1.16:
-        ! remainder is negative
-        addcc   %o3,%o5,%o3
-                        ! depth 2, accumulated bits -1
-        bl      L.2.15
-         srl    %o5,1,%o5
-        ! remainder is positive
-        subcc   %o3,%o5,%o3
-                        ! depth 3, accumulated bits -1
-        bl      L.3.15
-         srl    %o5,1,%o5
-        ! remainder is positive
-        subcc   %o3,%o5,%o3
-                        ! depth 4, accumulated bits -1
-        bl      L.4.15
-         srl    %o5,1,%o5
-        ! remainder is positive
-        subcc   %o3,%o5,%o3
-        b       9f
-         add    %o2, (-1*2+1), %o2
-L.4.15:
-        ! remainder is negative
-        addcc   %o3,%o5,%o3
-        b       9f
-         add    %o2, (-1*2-1), %o2
-L.3.15:
-        ! remainder is negative
-        addcc   %o3,%o5,%o3
-                        ! depth 4, accumulated bits -3
-        bl      L.4.13
-         srl    %o5,1,%o5
-        ! remainder is positive
-        subcc   %o3,%o5,%o3
-        b       9f
-         add    %o2, (-3*2+1), %o2
-L.4.13:
-        ! remainder is negative
-        addcc   %o3,%o5,%o3
-        b       9f
-         add    %o2, (-3*2-1), %o2
-L.2.15:
-        ! remainder is negative
-        addcc   %o3,%o5,%o3
-                        ! depth 3, accumulated bits -3
-        bl      L.3.13
-         srl    %o5,1,%o5
-        ! remainder is positive
-        subcc   %o3,%o5,%o3
-                        ! depth 4, accumulated bits -5
-        bl      L.4.11
-         srl    %o5,1,%o5
-        ! remainder is positive
-        subcc   %o3,%o5,%o3
-        b       9f
-         add    %o2, (-5*2+1), %o2
-L.4.11:
-        ! remainder is negative
-        addcc   %o3,%o5,%o3
-        b       9f
-         add    %o2, (-5*2-1), %o2
-L.3.13:
-        ! remainder is negative
-        addcc   %o3,%o5,%o3
-                        ! depth 4, accumulated bits -7
-        bl      L.4.9
-         srl    %o5,1,%o5
-        ! remainder is positive
-        subcc   %o3,%o5,%o3
-        b       9f
-         add    %o2, (-7*2+1), %o2
-L.4.9:
-        ! remainder is negative
-        addcc   %o3,%o5,%o3
-        b       9f
-         add    %o2, (-7*2-1), %o2
-        9:
-Lend_regular_divide:
-        subcc   %o4, 1, %o4
-        bge     Ldivloop
-         tst    %o3
-        bl,a    Lgot_result
-        ! non-restoring fixup here (one instruction only!)
-        sub     %o2, 1, %o2
-Lgot_result:
-        ! check to see if answer should be < 0
-        tst     %g2
-        bl,a    1f
-         sub %g0, %o2, %o2
-1:
-        retl
-         mov %o2, %o0
-        .globl  .div_patch
-.div_patch:
-        sra     %o0, 0x1f, %o2
-        wr      %o2, 0x0, %y
-        nop
-        nop
-        nop
-        sdivcc  %o0, %o1, %o0
-        bvs,a   1f
-         xnor   %o0, %g0, %o0
-1:      retl
-         nop
diff --git a/arch/sparc/lib/strlen_user_64.S b/arch/sparc/lib/strlen_user_64.S
index 114ed111e251..c3df71fa4928 100644
--- a/arch/sparc/lib/strlen_user_64.S
+++ b/arch/sparc/lib/strlen_user_64.S
@@ -8,16 +8,16 @@
 * Copyright (C) 1996,1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
 */
+#include <linux/linkage.h>
 #include <asm/asi.h>
 #define LO_MAGIC 0x01010101
 #define HI_MAGIC 0x80808080
        .align 4
-        .global __strlen_user, __strnlen_user
+ENTRY(__strlen_user)
-__strlen_user:
        sethi   %hi(32768), %o1
-__strnlen_user: 
+ENTRY(__strnlen_user)
        mov     %o1, %g1
        mov     %o0, %o1
        andcc   %o0, 3, %g0
@@ -78,6 +78,8 @@ __strnlen_user:
         mov    2, %o0
 23:     retl
         mov    3, %o0
+ENDPROC(__strlen_user)
+ENDPROC(__strnlen_user)
        .section .fixup,#alloc,#execinstr
        .align  4
diff --git a/arch/sparc/lib/strncmp_32.S b/arch/sparc/lib/strncmp_32.S
index 494ec664537a..c0d1b568c1c5 100644
--- a/arch/sparc/lib/strncmp_32.S
+++ b/arch/sparc/lib/strncmp_32.S
@@ -3,11 +3,10 @@
 *            generic strncmp routine.
 */
+#include <linux/linkage.h>
        .text
-        .align 4
+ENTRY(strncmp)
-        .global __strncmp, strncmp
-__strncmp:
-strncmp:
        mov     %o0, %g3
        mov     0, %o3
@@ -116,3 +115,4 @@ strncmp:
        and     %g2, 0xff, %o0
        retl
         sub    %o3, %o0, %o0
+ENDPROC(strncmp)
diff --git a/arch/sparc/lib/strncmp_64.S b/arch/sparc/lib/strncmp_64.S
index 980e83751556..0656627166f3 100644
--- a/arch/sparc/lib/strncmp_64.S
+++ b/arch/sparc/lib/strncmp_64.S
@@ -4,13 +4,11 @@
 * Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
 */
+#include <linux/linkage.h>
 #include <asm/asi.h>
        .text
-        .align  32
+ENTRY(strncmp)
-        .globl  strncmp
-        .type   strncmp,#function
-strncmp:
        brlez,pn %o2, 3f
         lduba  [%o0] (ASI_PNF), %o3
 1:
@@ -29,4 +27,4 @@ strncmp:
 3:
        retl
         clr    %o0
-        .size   strncmp, .-strncmp
+ENDPROC(strncmp)
diff --git a/arch/sparc/lib/strncpy_from_user_32.S b/arch/sparc/lib/strncpy_from_user_32.S
index d77198976a66..db0ed2964bdb 100644
--- a/arch/sparc/lib/strncpy_from_user_32.S
+++ b/arch/sparc/lib/strncpy_from_user_32.S
@@ -3,11 +3,11 @@
 *  Copyright(C) 1996 David S. Miller
 */
+#include <linux/linkage.h>
 #include <asm/ptrace.h>
 #include <asm/errno.h>
        .text
-        .align  4
        /* Must return:
         *
@@ -16,8 +16,7 @@
         * bytes copied         if we hit a null byte
         */
-        .globl  __strncpy_from_user
+ENTRY(__strncpy_from_user)
-__strncpy_from_user:
        /* %o0=dest, %o1=src, %o2=count */
        mov     %o2, %o3
 1:
@@ -35,6 +34,7 @@ __strncpy_from_user:
        add     %o2, 1, %o0
        retl
         sub    %o3, %o0, %o0
+ENDPROC(__strncpy_from_user)
        .section .fixup,#alloc,#execinstr
        .align  4
diff --git a/arch/sparc/lib/strncpy_from_user_64.S b/arch/sparc/lib/strncpy_from_user_64.S
index 511c8f136f95..d1246b713077 100644
--- a/arch/sparc/lib/strncpy_from_user_64.S
+++ b/arch/sparc/lib/strncpy_from_user_64.S
@@ -4,6 +4,7 @@
 *  Copyright (C) 1997, 1999 Jakub Jelinek (jj@ultra.linux.cz)
 */
+#include <linux/linkage.h>
 #include <asm/asi.h>
 #include <asm/errno.h>
@@ -12,7 +13,6 @@
 0:      .xword  0x0101010101010101
        .text
-        .align  32
        /* Must return:
         *
@@ -30,9 +30,7 @@
         * and average length is 18 or so.
         */
-        .globl  __strncpy_from_user
+ENTRY(__strncpy_from_user)
-        .type   __strncpy_from_user,#function
-__strncpy_from_user:
        /* %o0=dest, %o1=src, %o2=count */
        andcc   %o1, 7, %g0             ! IEU1  Group
        bne,pn  %icc, 30f               ! CTI
@@ -123,7 +121,7 @@ __strncpy_from_user:
         mov    %o2, %o0
 2:      retl
         add    %o2, %o3, %o0
-        .size   __strncpy_from_user, .-__strncpy_from_user
+ENDPROC(__strncpy_from_user)
        .section __ex_table,"a"
        .align  4
diff --git a/arch/sparc/lib/ucmpdi2.c b/arch/sparc/lib/ucmpdi2.c
new file mode 100644
index 000000000000..1e06ed500682
--- /dev/null
+++ b/arch/sparc/lib/ucmpdi2.c
@@ -0,0 +1,19 @@
+#include <linux/module.h>
+#include "libgcc.h"
+word_type __ucmpdi2(unsigned long long a, unsigned long long b)
+{
+        const DWunion au = {.ll = a};
+        const DWunion bu = {.ll = b};
+        if ((unsigned int) au.s.high < (unsigned int) bu.s.high)
+                return 0;
+        else if ((unsigned int) au.s.high > (unsigned int) bu.s.high)
+                return 2;
+        if ((unsigned int) au.s.low < (unsigned int) bu.s.low)
+                return 0;
+        else if ((unsigned int) au.s.low > (unsigned int) bu.s.low)
+                return 2;
+        return 1;
+}
+EXPORT_SYMBOL(__ucmpdi2);
diff --git a/arch/sparc/lib/udiv.S b/arch/sparc/lib/udiv.S
deleted file mode 100644
index 2101405bdfcb..000000000000
--- a/arch/sparc/lib/udiv.S
+++ /dev/null
@@ -1,357 +0,0 @@
-/*
- * udiv.S:      This routine was taken from glibc-1.09 and is covered
- *              by the GNU Library General Public License Version 2.
- */
-/* This file is generated from divrem.m4; DO NOT EDIT! */
-/*
- * Division and remainder, from Appendix E of the Sparc Version 8
- * Architecture Manual, with fixes from Gordon Irlam.
- */
-/*
- * Input: dividend and divisor in %o0 and %o1 respectively.
- *
- * m4 parameters:
- *  .udiv       name of function to generate
- *  div         div=div => %o0 / %o1; div=rem => %o0 % %o1
- *  false               false=true => signed; false=false => unsigned
- *
- * Algorithm parameters:
- *  N           how many bits per iteration we try to get (4)
- *  WORDSIZE    total number of bits (32)
- *
- * Derived constants:
- *  TOPBITS     number of bits in the top decade of a number
- *
- * Important variables:
- *  Q           the partial quotient under development (initially 0)
- *  R           the remainder so far, initially the dividend
- *  ITER        number of main division loop iterations required;
- *              equal to ceil(log2(quotient) / N).  Note that this
- *              is the log base (2^N) of the quotient.
- *  V           the current comparand, initially divisor*2^(ITER*N-1)
- *
- * Cost:
- *  Current estimate for non-large dividend is
- *      ceil(log2(quotient) / N) * (10 + 7N/2) + C
- *  A large dividend is one greater than 2^(31-TOPBITS) and takes a
- *  different path, as the upper bits of the quotient must be developed
- *  one bit at a time.
- */
-        .globl .udiv
-        .globl _Udiv
-.udiv:
-_Udiv:  /* needed for export */
-        ! Ready to divide.  Compute size of quotient; scale comparand.
-        orcc    %o1, %g0, %o5
-        bne     1f
-         mov    %o0, %o3
-                ! Divide by zero trap.  If it returns, return 0 (about as
-                ! wrong as possible, but that is what SunOS does...).
-                ta      ST_DIV0
-                retl
-                 clr    %o0
-1:
-        cmp     %o3, %o5                        ! if %o1 exceeds %o0, done
-        blu     Lgot_result             ! (and algorithm fails otherwise)
-         clr    %o2
-        sethi   %hi(1 << (32 - 4 - 1)), %g1
-        cmp     %o3, %g1
-        blu     Lnot_really_big
-         clr    %o4
-        ! Here the dividend is >= 2**(31-N) or so.  We must be careful here,
-        ! as our usual N-at-a-shot divide step will cause overflow and havoc.
-        ! The number of bits in the result here is N*ITER+SC, where SC <= N.
-        ! Compute ITER in an unorthodox manner: know we need to shift V into
-        ! the top decade: so do not even bother to compare to R.
-        1:
-                cmp     %o5, %g1
-                bgeu    3f
-                 mov    1, %g7
-                sll     %o5, 4, %o5
-                b       1b
-                 add    %o4, 1, %o4
-        ! Now compute %g7.
-        2:
-                addcc   %o5, %o5, %o5
-                bcc     Lnot_too_big
-                 add    %g7, 1, %g7
-                ! We get here if the %o1 overflowed while shifting.
-                ! This means that %o3 has the high-order bit set.
-                ! Restore %o5 and subtract from %o3.
-                sll     %g1, 4, %g1     ! high order bit
-                srl     %o5, 1, %o5             ! rest of %o5
-                add     %o5, %g1, %o5
-                b       Ldo_single_div
-                 sub    %g7, 1, %g7
-        Lnot_too_big:
-        3:
-                cmp     %o5, %o3
-                blu     2b
-                 nop
-                be      Ldo_single_div
-                 nop
-        /* NB: these are commented out in the V8-Sparc manual as well */
-        /* (I do not understand this) */
-        ! %o5 > %o3: went too far: back up 1 step
-        !       srl     %o5, 1, %o5
-        !       dec     %g7
-        ! do single-bit divide steps
-        !
-        ! We have to be careful here.  We know that %o3 >= %o5, so we can do the
-        ! first divide step without thinking.  BUT, the others are conditional,
-        ! and are only done if %o3 >= 0.  Because both %o3 and %o5 may have the high-
-        ! order bit set in the first step, just falling into the regular
-        ! division loop will mess up the first time around.
-        ! So we unroll slightly...
-        Ldo_single_div:
-                subcc   %g7, 1, %g7
-                bl      Lend_regular_divide
-                 nop
-                sub     %o3, %o5, %o3
-                mov     1, %o2
-                b       Lend_single_divloop
-                 nop
-        Lsingle_divloop:
-                sll     %o2, 1, %o2
-                bl      1f
-                 srl    %o5, 1, %o5
-                ! %o3 >= 0
-                sub     %o3, %o5, %o3
-                b       2f
-                 add    %o2, 1, %o2
-        1:      ! %o3 < 0
-                add     %o3, %o5, %o3
-                sub     %o2, 1, %o2
-        2:
-        Lend_single_divloop:
-                subcc   %g7, 1, %g7
-                bge     Lsingle_divloop
-                 tst    %o3
-                b,a     Lend_regular_divide
-Lnot_really_big:
-1:
-        sll     %o5, 4, %o5
-        cmp     %o5, %o3
-        bleu    1b
-         addcc  %o4, 1, %o4
-        be      Lgot_result
-         sub    %o4, 1, %o4
-        tst     %o3     ! set up for initial iteration
-Ldivloop:
-        sll     %o2, 4, %o2
-                ! depth 1, accumulated bits 0
-        bl      L.1.16
-         srl    %o5,1,%o5
-        ! remainder is positive
-        subcc   %o3,%o5,%o3
-                        ! depth 2, accumulated bits 1
-        bl      L.2.17
-         srl    %o5,1,%o5
-        ! remainder is positive
-        subcc   %o3,%o5,%o3
-                        ! depth 3, accumulated bits 3
-        bl      L.3.19
-         srl    %o5,1,%o5
-        ! remainder is positive
-        subcc   %o3,%o5,%o3
-                        ! depth 4, accumulated bits 7
-        bl      L.4.23
-         srl    %o5,1,%o5
-        ! remainder is positive
-        subcc   %o3,%o5,%o3
-        b       9f
-         add    %o2, (7*2+1), %o2
-L.4.23:
-        ! remainder is negative
-        addcc   %o3,%o5,%o3
-        b       9f
-         add    %o2, (7*2-1), %o2
-L.3.19:
-        ! remainder is negative
-        addcc   %o3,%o5,%o3
-                        ! depth 4, accumulated bits 5
-        bl      L.4.21
-         srl    %o5,1,%o5
-        ! remainder is positive
-        subcc   %o3,%o5,%o3
-        b       9f
-         add    %o2, (5*2+1), %o2
-L.4.21:
-        ! remainder is negative
-        addcc   %o3,%o5,%o3
-        b       9f
-         add    %o2, (5*2-1), %o2
-L.2.17:
-        ! remainder is negative
-        addcc   %o3,%o5,%o3
-                        ! depth 3, accumulated bits 1
-        bl      L.3.17
-         srl    %o5,1,%o5
-        ! remainder is positive
-        subcc   %o3,%o5,%o3
-                        ! depth 4, accumulated bits 3
-        bl      L.4.19
-         srl    %o5,1,%o5
-        ! remainder is positive
-        subcc   %o3,%o5,%o3
-        b       9f
-         add    %o2, (3*2+1), %o2
-L.4.19:
-        ! remainder is negative
-        addcc   %o3,%o5,%o3
-        b       9f
-         add    %o2, (3*2-1), %o2
-L.3.17:
-        ! remainder is negative
-        addcc   %o3,%o5,%o3
-                        ! depth 4, accumulated bits 1
-        bl      L.4.17
-         srl    %o5,1,%o5
-        ! remainder is positive
-        subcc   %o3,%o5,%o3
-        b       9f
-         add    %o2, (1*2+1), %o2
-L.4.17:
-        ! remainder is negative
-        addcc   %o3,%o5,%o3
-        b       9f
-         add    %o2, (1*2-1), %o2
-L.1.16:
-        ! remainder is negative
-        addcc   %o3,%o5,%o3
-                        ! depth 2, accumulated bits -1
-        bl      L.2.15
-         srl    %o5,1,%o5
-        ! remainder is positive
-        subcc   %o3,%o5,%o3
-                        ! depth 3, accumulated bits -1
-        bl      L.3.15
-         srl    %o5,1,%o5
-        ! remainder is positive
-        subcc   %o3,%o5,%o3
-                        ! depth 4, accumulated bits -1
-        bl      L.4.15
-         srl    %o5,1,%o5
-        ! remainder is positive
-        subcc   %o3,%o5,%o3
-        b       9f
-         add    %o2, (-1*2+1), %o2
-L.4.15:
-        ! remainder is negative
-        addcc   %o3,%o5,%o3
-        b       9f
-         add    %o2, (-1*2-1), %o2
-L.3.15:
-        ! remainder is negative
-        addcc   %o3,%o5,%o3
-                        ! depth 4, accumulated bits -3
-        bl      L.4.13
-         srl    %o5,1,%o5
-        ! remainder is positive
-        subcc   %o3,%o5,%o3
-        b       9f
-         add    %o2, (-3*2+1), %o2
-L.4.13:
-        ! remainder is negative
-        addcc   %o3,%o5,%o3
-        b       9f
-         add    %o2, (-3*2-1), %o2
-L.2.15:
-        ! remainder is negative
-        addcc   %o3,%o5,%o3
-                        ! depth 3, accumulated bits -3
-        bl      L.3.13
-         srl    %o5,1,%o5
-        ! remainder is positive
-        subcc   %o3,%o5,%o3
-                        ! depth 4, accumulated bits -5
-        bl      L.4.11
-         srl    %o5,1,%o5
-        ! remainder is positive
-        subcc   %o3,%o5,%o3
-        b       9f
-         add    %o2, (-5*2+1), %o2
-L.4.11:
-        ! remainder is negative
-        addcc   %o3,%o5,%o3
-        b       9f
-         add    %o2, (-5*2-1), %o2
-L.3.13:
-        ! remainder is negative
-        addcc   %o3,%o5,%o3
-                        ! depth 4, accumulated bits -7
-        bl      L.4.9
-         srl    %o5,1,%o5
-        ! remainder is positive
-        subcc   %o3,%o5,%o3
-        b       9f
-         add    %o2, (-7*2+1), %o2
-L.4.9:
-        ! remainder is negative
-        addcc   %o3,%o5,%o3
-        b       9f
-         add    %o2, (-7*2-1), %o2
-        9:
-Lend_regular_divide:
-        subcc   %o4, 1, %o4
-        bge     Ldivloop
-         tst    %o3
-        bl,a    Lgot_result
-        ! non-restoring fixup here (one instruction only!)
-        sub     %o2, 1, %o2
-Lgot_result:
-        retl
-         mov %o2, %o0
-        .globl  .udiv_patch
-.udiv_patch:
-        wr      %g0, 0x0, %y
-        nop
-        nop
-        retl
-         udiv   %o0, %o1, %o0
-        nop
diff --git a/arch/sparc/lib/udivdi3.S b/arch/sparc/lib/udivdi3.S
index b430f1f0ef62..24e0a355e2e8 100644
--- a/arch/sparc/lib/udivdi3.S
+++ b/arch/sparc/lib/udivdi3.S
@@ -60,8 +60,9 @@ __udivdi3:
        bne .LL77
        mov %i0,%o2
        mov 1,%o0
-        call .udiv,0
        mov 0,%o1
+        wr %g0, 0, %y
+        udiv %o0, %o1, %o0
        mov %o0,%o3
        mov %i0,%o2
 .LL77:
diff --git a/arch/sparc/lib/umul.S b/arch/sparc/lib/umul.S
deleted file mode 100644
index 1f36ae682529..000000000000
--- a/arch/sparc/lib/umul.S
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
- * umul.S:      This routine was taken from glibc-1.09 and is covered
- *              by the GNU Library General Public License Version 2.
- */
-/*
- * Unsigned multiply.  Returns %o0 * %o1 in %o1%o0 (i.e., %o1 holds the
- * upper 32 bits of the 64-bit product).
- *
- * This code optimizes short (less than 13-bit) multiplies.  Short
- * multiplies require 25 instruction cycles, and long ones require
- * 45 instruction cycles.
- *
- * On return, overflow has occurred (%o1 is not zero) if and only if
- * the Z condition code is clear, allowing, e.g., the following:
- *
- *      call    .umul
- *      nop
- *      bnz     overflow        (or tnz)
- */
-        .globl .umul
-        .globl _Umul
-.umul:
-_Umul:  /* needed for export */
-        or      %o0, %o1, %o4
-        mov     %o0, %y         ! multiplier -> Y
-        andncc  %o4, 0xfff, %g0 ! test bits 12..31 of *both* args
-        be      Lmul_shortway   ! if zero, can do it the short way
-         andcc  %g0, %g0, %o4   ! zero the partial product and clear N and V
-        /*
-         * Long multiply.  32 steps, followed by a final shift step.
-         */
-        mulscc  %o4, %o1, %o4   ! 1
-        mulscc  %o4, %o1, %o4   ! 2
-        mulscc  %o4, %o1, %o4   ! 3
-        mulscc  %o4, %o1, %o4   ! 4
-        mulscc  %o4, %o1, %o4   ! 5
-        mulscc  %o4, %o1, %o4   ! 6
-        mulscc  %o4, %o1, %o4   ! 7
-        mulscc  %o4, %o1, %o4   ! 8
-        mulscc  %o4, %o1, %o4   ! 9
-        mulscc  %o4, %o1, %o4   ! 10
-        mulscc  %o4, %o1, %o4   ! 11
-        mulscc  %o4, %o1, %o4   ! 12
-        mulscc  %o4, %o1, %o4   ! 13
-        mulscc  %o4, %o1, %o4   ! 14
-        mulscc  %o4, %o1, %o4   ! 15
-        mulscc  %o4, %o1, %o4   ! 16
-        mulscc  %o4, %o1, %o4   ! 17
-        mulscc  %o4, %o1, %o4   ! 18
-        mulscc  %o4, %o1, %o4   ! 19
-        mulscc  %o4, %o1, %o4   ! 20
-        mulscc  %o4, %o1, %o4   ! 21
-        mulscc  %o4, %o1, %o4   ! 22
-        mulscc  %o4, %o1, %o4   ! 23
-        mulscc  %o4, %o1, %o4   ! 24
-        mulscc  %o4, %o1, %o4   ! 25
-        mulscc  %o4, %o1, %o4   ! 26
-        mulscc  %o4, %o1, %o4   ! 27
-        mulscc  %o4, %o1, %o4   ! 28
-        mulscc  %o4, %o1, %o4   ! 29
-        mulscc  %o4, %o1, %o4   ! 30
-        mulscc  %o4, %o1, %o4   ! 31
-        mulscc  %o4, %o1, %o4   ! 32
-        mulscc  %o4, %g0, %o4   ! final shift
-        /*
-         * Normally, with the shift-and-add approach, if both numbers are
-         * positive you get the correct result.  With 32-bit two's-complement
-         * numbers, -x is represented as
-         *
-         *                x                 32
-         *      ( 2  -  ------ ) mod 2  *  2
-         *                 32
-         *                2
-         *
-         * (the `mod 2' subtracts 1 from 1.bbbb).  To avoid lots of 2^32s,
-         * we can treat this as if the radix point were just to the left
-         * of the sign bit (multiply by 2^32), and get
-         *
-         *      -x  =  (2 - x) mod 2
-         *
-         * Then, ignoring the `mod 2's for convenience:
-         *
-         *   x *  y     = xy
-         *  -x *  y     = 2y - xy
-         *   x * -y     = 2x - xy
-         *  -x * -y     = 4 - 2x - 2y + xy
-         *
-         * For signed multiplies, we subtract (x << 32) from the partial
-         * product to fix this problem for negative multipliers (see mul.s).
-         * Because of the way the shift into the partial product is calculated
-         * (N xor V), this term is automatically removed for the multiplicand,
-         * so we don't have to adjust.
-         *
-         * But for unsigned multiplies, the high order bit wasn't a sign bit,
-         * and the correction is wrong.  So for unsigned multiplies where the
-         * high order bit is one, we end up with xy - (y << 32).  To fix it
-         * we add y << 32.
-         */
-#if 0
-        tst     %o1
-        bl,a    1f              ! if %o1 < 0 (high order bit = 1),
-         add    %o4, %o0, %o4   ! %o4 += %o0 (add y to upper half)
-1:
-        rd      %y, %o0         ! get lower half of product
-        retl
-         addcc  %o4, %g0, %o1   ! put upper half in place and set Z for %o1==0
-#else
-        /* Faster code from tege@sics.se.  */
-        sra     %o1, 31, %o2    ! make mask from sign bit
-        and     %o0, %o2, %o2   ! %o2 = 0 or %o0, depending on sign of %o1
-        rd      %y, %o0         ! get lower half of product
-        retl
-         addcc  %o4, %o2, %o1   ! add compensation and put upper half in place
-#endif
-Lmul_shortway:
-        /*
-         * Short multiply.  12 steps, followed by a final shift step.
-         * The resulting bits are off by 12 and (32-12) = 20 bit positions,
-         * but there is no problem with %o0 being negative (unlike above),
-         * and overflow is impossible (the answer is at most 24 bits long).
-         */
-        mulscc  %o4, %o1, %o4   ! 1
-        mulscc  %o4, %o1, %o4   ! 2
-        mulscc  %o4, %o1, %o4   ! 3
-        mulscc  %o4, %o1, %o4   ! 4
-        mulscc  %o4, %o1, %o4   ! 5
-        mulscc  %o4, %o1, %o4   ! 6
-        mulscc  %o4, %o1, %o4   ! 7
-        mulscc  %o4, %o1, %o4   ! 8
-        mulscc  %o4, %o1, %o4   ! 9
-        mulscc  %o4, %o1, %o4   ! 10
-        mulscc  %o4, %o1, %o4   ! 11
-        mulscc  %o4, %o1, %o4   ! 12
-        mulscc  %o4, %g0, %o4   ! final shift
-        /*
-         * %o4 has 20 of the bits that should be in the result; %y has
-         * the bottom 12 (as %y's top 12).  That is:
-         *
-         *        %o4               %y
-         * +----------------+----------------+
-         * | -12- |   -20-  | -12- |   -20-  |
-         * +------(---------+------)---------+
-         *         -----result-----
-         *
-         * The 12 bits of %o4 left of the `result' area are all zero;
-         * in fact, all top 20 bits of %o4 are zero.
-         */
-        rd      %y, %o5
-        sll     %o4, 12, %o0    ! shift middle bits left 12
-        srl     %o5, 20, %o5    ! shift low bits right 20
-        or      %o5, %o0, %o0
-        retl
-         addcc  %g0, %g0, %o1   ! %o1 = zero, and set Z
-        .globl  .umul_patch
-.umul_patch:
-        umul    %o0, %o1, %o0
-        retl
-         rd     %y, %o1
-        nop
diff --git a/arch/sparc/lib/urem.S b/arch/sparc/lib/urem.S
deleted file mode 100644
index 77123eb83c44..000000000000
--- a/arch/sparc/lib/urem.S
+++ /dev/null
@@ -1,357 +0,0 @@
-/*
- * urem.S:      This routine was taken from glibc-1.09 and is covered
- *              by the GNU Library General Public License Version 2.
- */
-/* This file is generated from divrem.m4; DO NOT EDIT! */
-/*
- * Division and remainder, from Appendix E of the Sparc Version 8
- * Architecture Manual, with fixes from Gordon Irlam.
- */
-/*
- * Input: dividend and divisor in %o0 and %o1 respectively.
- *
- * m4 parameters:
- *  .urem       name of function to generate
- *  rem         rem=div => %o0 / %o1; rem=rem => %o0 % %o1
- *  false               false=true => signed; false=false => unsigned
- *
- * Algorithm parameters:
- *  N           how many bits per iteration we try to get (4)
- *  WORDSIZE    total number of bits (32)
- *
- * Derived constants:
- *  TOPBITS     number of bits in the top decade of a number
- *
- * Important variables:
- *  Q           the partial quotient under development (initially 0)
- *  R           the remainder so far, initially the dividend
- *  ITER        number of main division loop iterations required;
- *              equal to ceil(log2(quotient) / N).  Note that this
- *              is the log base (2^N) of the quotient.
- *  V           the current comparand, initially divisor*2^(ITER*N-1)
- *
- * Cost:
- *  Current estimate for non-large dividend is
- *      ceil(log2(quotient) / N) * (10 + 7N/2) + C
- *  A large dividend is one greater than 2^(31-TOPBITS) and takes a
- *  different path, as the upper bits of the quotient must be developed
- *  one bit at a time.
- */
-        .globl .urem
-        .globl _Urem
-.urem:
-_Urem:  /* needed for export */
-        ! Ready to divide.  Compute size of quotient; scale comparand.
-        orcc    %o1, %g0, %o5
-        bne     1f
-         mov    %o0, %o3
-                ! Divide by zero trap.  If it returns, return 0 (about as
-                ! wrong as possible, but that is what SunOS does...).
-                ta      ST_DIV0
-                retl
-                 clr    %o0
-1:
-        cmp     %o3, %o5                        ! if %o1 exceeds %o0, done
-        blu     Lgot_result             ! (and algorithm fails otherwise)
-         clr    %o2
-        sethi   %hi(1 << (32 - 4 - 1)), %g1
-        cmp     %o3, %g1
-        blu     Lnot_really_big
-         clr    %o4
-        ! Here the dividend is >= 2**(31-N) or so.  We must be careful here,
-        ! as our usual N-at-a-shot divide step will cause overflow and havoc.
-        ! The number of bits in the result here is N*ITER+SC, where SC <= N.
-        ! Compute ITER in an unorthodox manner: know we need to shift V into
-        ! the top decade: so do not even bother to compare to R.
-        1:
-                cmp     %o5, %g1
-                bgeu    3f
-                 mov    1, %g7
-                sll     %o5, 4, %o5
-                b       1b
-                 add    %o4, 1, %o4
-        ! Now compute %g7.
-        2:
-                addcc   %o5, %o5, %o5
-                bcc     Lnot_too_big
-                 add    %g7, 1, %g7
-                ! We get here if the %o1 overflowed while shifting.
-                ! This means that %o3 has the high-order bit set.
-                ! Restore %o5 and subtract from %o3.
-                sll     %g1, 4, %g1     ! high order bit
-                srl     %o5, 1, %o5             ! rest of %o5
-                add     %o5, %g1, %o5
-                b       Ldo_single_div
-                 sub    %g7, 1, %g7
-        Lnot_too_big:
-        3:
-                cmp     %o5, %o3
-                blu     2b
-                 nop
-                be      Ldo_single_div
-                 nop
-        /* NB: these are commented out in the V8-Sparc manual as well */
-        /* (I do not understand this) */
-        ! %o5 > %o3: went too far: back up 1 step
-        !       srl     %o5, 1, %o5
-        !       dec     %g7
-        ! do single-bit divide steps
-        !
-        ! We have to be careful here.  We know that %o3 >= %o5, so we can do the
-        ! first divide step without thinking.  BUT, the others are conditional,
-        ! and are only done if %o3 >= 0.  Because both %o3 and %o5 may have the high-
-        ! order bit set in the first step, just falling into the regular
-        ! division loop will mess up the first time around.
-        ! So we unroll slightly...
-        Ldo_single_div:
-                subcc   %g7, 1, %g7
-                bl      Lend_regular_divide
-                 nop
-                sub     %o3, %o5, %o3
-                mov     1, %o2
-                b       Lend_single_divloop
-                 nop
-        Lsingle_divloop:
-                sll     %o2, 1, %o2
-                bl      1f
-                 srl    %o5, 1, %o5
-                ! %o3 >= 0
-                sub     %o3, %o5, %o3
-                b       2f
-                 add    %o2, 1, %o2
-        1:      ! %o3 < 0
-                add     %o3, %o5, %o3
-                sub     %o2, 1, %o2
-        2:
-        Lend_single_divloop:
-                subcc   %g7, 1, %g7
-                bge     Lsingle_divloop
-                 tst    %o3
-                b,a     Lend_regular_divide
-Lnot_really_big:
-1:
-        sll     %o5, 4, %o5
-        cmp     %o5, %o3
-        bleu    1b
-         addcc  %o4, 1, %o4
-        be      Lgot_result
-         sub    %o4, 1, %o4
-        tst     %o3     ! set up for initial iteration
-Ldivloop:
-        sll     %o2, 4, %o2
-                ! depth 1, accumulated bits 0
-        bl      L.1.16
-         srl    %o5,1,%o5
-        ! remainder is positive
-        subcc   %o3,%o5,%o3
-                        ! depth 2, accumulated bits 1
-        bl      L.2.17
-         srl    %o5,1,%o5
-        ! remainder is positive
-        subcc   %o3,%o5,%o3
-                        ! depth 3, accumulated bits 3
-        bl      L.3.19
-         srl    %o5,1,%o5
-        ! remainder is positive
-        subcc   %o3,%o5,%o3
-                        ! depth 4, accumulated bits 7
-        bl      L.4.23
-         srl    %o5,1,%o5
-        ! remainder is positive
-        subcc   %o3,%o5,%o3
-        b       9f
-         add    %o2, (7*2+1), %o2
-L.4.23:
-        ! remainder is negative
-        addcc   %o3,%o5,%o3
-        b       9f
-         add    %o2, (7*2-1), %o2
-L.3.19:
-        ! remainder is negative
-        addcc   %o3,%o5,%o3
-                        ! depth 4, accumulated bits 5
-        bl      L.4.21
-         srl    %o5,1,%o5
-        ! remainder is positive
-        subcc   %o3,%o5,%o3
-        b       9f
-         add    %o2, (5*2+1), %o2
-L.4.21:
-        ! remainder is negative
-        addcc   %o3,%o5,%o3
-        b       9f
-         add    %o2, (5*2-1), %o2
-L.2.17:
-        ! remainder is negative
-        addcc   %o3,%o5,%o3
-                        ! depth 3, accumulated bits 1
-        bl      L.3.17
-         srl    %o5,1,%o5
-        ! remainder is positive
-        subcc   %o3,%o5,%o3
-                        ! depth 4, accumulated bits 3
-        bl      L.4.19
-         srl    %o5,1,%o5
-        ! remainder is positive
-        subcc   %o3,%o5,%o3
-        b       9f
-         add    %o2, (3*2+1), %o2
-L.4.19:
-        ! remainder is negative
-        addcc   %o3,%o5,%o3
-        b       9f
-         add    %o2, (3*2-1), %o2
-L.3.17:
-        ! remainder is negative
-        addcc   %o3,%o5,%o3
-                        ! depth 4, accumulated bits 1
-        bl      L.4.17
-         srl    %o5,1,%o5
-        ! remainder is positive
-        subcc   %o3,%o5,%o3
-        b       9f
-         add    %o2, (1*2+1), %o2
-        
-L.4.17:
-        ! remainder is negative
-        addcc   %o3,%o5,%o3
-        b       9f
-         add    %o2, (1*2-1), %o2
-L.1.16:
-        ! remainder is negative
-        addcc   %o3,%o5,%o3
-                        ! depth 2, accumulated bits -1
-        bl      L.2.15
-         srl    %o5,1,%o5
-        ! remainder is positive
-        subcc   %o3,%o5,%o3
-                        ! depth 3, accumulated bits -1
-        bl      L.3.15
-         srl    %o5,1,%o5
-        ! remainder is positive
-        subcc   %o3,%o5,%o3
-                        ! depth 4, accumulated bits -1
-        bl      L.4.15
-         srl    %o5,1,%o5
-        ! remainder is positive
-        subcc   %o3,%o5,%o3
-        b       9f
-         add    %o2, (-1*2+1), %o2
-L.4.15:
-        ! remainder is negative
-        addcc   %o3,%o5,%o3
-        b       9f
-         add    %o2, (-1*2-1), %o2
-L.3.15:
-        ! remainder is negative
-        addcc   %o3,%o5,%o3
-                        ! depth 4, accumulated bits -3
-        bl      L.4.13
-         srl    %o5,1,%o5
-        ! remainder is positive
-        subcc   %o3,%o5,%o3
-        b       9f
-         add    %o2, (-3*2+1), %o2
-L.4.13:
-        ! remainder is negative
-        addcc   %o3,%o5,%o3
-        b       9f
-         add    %o2, (-3*2-1), %o2
-L.2.15:
-        ! remainder is negative
-        addcc   %o3,%o5,%o3
-                        ! depth 3, accumulated bits -3
-        bl      L.3.13
-         srl    %o5,1,%o5
-        ! remainder is positive
-        subcc   %o3,%o5,%o3
-                        ! depth 4, accumulated bits -5
-        bl      L.4.11
-         srl    %o5,1,%o5
-        ! remainder is positive
-        subcc   %o3,%o5,%o3
-        b       9f
-         add    %o2, (-5*2+1), %o2
-        
-L.4.11:
-        ! remainder is negative
-        addcc   %o3,%o5,%o3
-        b       9f
-         add    %o2, (-5*2-1), %o2
-L.3.13:
-        ! remainder is negative
-        addcc   %o3,%o5,%o3
-                        ! depth 4, accumulated bits -7
-        bl      L.4.9
-         srl    %o5,1,%o5
-        ! remainder is positive
-        subcc   %o3,%o5,%o3
-        b       9f
-         add    %o2, (-7*2+1), %o2
-L.4.9:
-        ! remainder is negative
-        addcc   %o3,%o5,%o3
-        b       9f
-         add    %o2, (-7*2-1), %o2
-        9:
-Lend_regular_divide:
-        subcc   %o4, 1, %o4
-        bge     Ldivloop
-         tst    %o3
-        bl,a    Lgot_result
-        ! non-restoring fixup here (one instruction only!)
-        add     %o3, %o1, %o3
-Lgot_result:
-        retl
-         mov %o3, %o0
-        .globl  .urem_patch
-.urem_patch:
-        wr      %g0, 0x0, %y
-        nop
-        nop
-        nop
-        udiv    %o0, %o1, %o2
-        umul    %o2, %o1, %o2
-        retl
-         sub    %o0, %o2, %o0
diff --git a/arch/sparc/lib/xor.S b/arch/sparc/lib/xor.S
index f44f58f40234..2c05641c3263 100644
--- a/arch/sparc/lib/xor.S
+++ b/arch/sparc/lib/xor.S
@@ -8,6 +8,7 @@
 * Copyright (C) 2006 David S. Miller <davem@davemloft.net>
 */
+#include <linux/linkage.h>
 #include <asm/visasm.h>
 #include <asm/asi.h>
 #include <asm/dcu.h>
@@ -19,12 +20,9 @@
 *      !(len & 127) && len >= 256
 */
        .text
-        .align  32
        /* VIS versions. */
-        .globl  xor_vis_2
+ENTRY(xor_vis_2)
-        .type   xor_vis_2,#function
-xor_vis_2:
        rd      %fprs, %o5
        andcc   %o5, FPRS_FEF|FPRS_DU, %g0
        be,pt   %icc, 0f
@@ -91,11 +89,9 @@ xor_vis_2:
        wr      %g1, %g0, %asi
        retl
          wr    %g0, 0, %fprs
-        .size   xor_vis_2, .-xor_vis_2
+ENDPROC(xor_vis_2)
-        .globl  xor_vis_3
+ENTRY(xor_vis_3)
-        .type   xor_vis_3,#function
-xor_vis_3:
        rd      %fprs, %o5
        andcc   %o5, FPRS_FEF|FPRS_DU, %g0
        be,pt   %icc, 0f
@@ -159,11 +155,9 @@ xor_vis_3:
        wr      %g1, %g0, %asi
        retl
         wr     %g0, 0, %fprs
-        .size   xor_vis_3, .-xor_vis_3
+ENDPROC(xor_vis_3)
-        .globl  xor_vis_4
+ENTRY(xor_vis_4)
-        .type   xor_vis_4,#function
-xor_vis_4:
        rd      %fprs, %o5
        andcc   %o5, FPRS_FEF|FPRS_DU, %g0
        be,pt   %icc, 0f
@@ -246,11 +240,9 @@ xor_vis_4:
        wr      %g1, %g0, %asi
        retl
         wr     %g0, 0, %fprs
-        .size   xor_vis_4, .-xor_vis_4
+ENDPROC(xor_vis_4)
-        .globl  xor_vis_5
+ENTRY(xor_vis_5)
-        .type   xor_vis_5,#function
-xor_vis_5:
        save    %sp, -192, %sp
        rd      %fprs, %o5
        andcc   %o5, FPRS_FEF|FPRS_DU, %g0
@@ -354,12 +346,10 @@ xor_vis_5:
        wr      %g0, 0, %fprs
        ret
         restore
-        .size   xor_vis_5, .-xor_vis_5
+ENDPROC(xor_vis_5)
        /* Niagara versions. */
-        .globl          xor_niagara_2
+ENTRY(xor_niagara_2) /* %o0=bytes, %o1=dest, %o2=src */
-        .type           xor_niagara_2,#function
-xor_niagara_2:          /* %o0=bytes, %o1=dest, %o2=src */
        save            %sp, -192, %sp
        prefetch        [%i1], #n_writes
        prefetch        [%i2], #one_read
@@ -402,11 +392,9 @@ xor_niagara_2:		/* %o0=bytes, %o1=dest, %o2=src */
        wr              %g7, 0x0, %asi
        ret
         restore
-        .size           xor_niagara_2, .-xor_niagara_2
+ENDPROC(xor_niagara_2)
-        .globl          xor_niagara_3
+ENTRY(xor_niagara_3) /* %o0=bytes, %o1=dest, %o2=src1, %o3=src2 */
-        .type           xor_niagara_3,#function
-xor_niagara_3:          /* %o0=bytes, %o1=dest, %o2=src1, %o3=src2 */
        save            %sp, -192, %sp
        prefetch        [%i1], #n_writes
        prefetch        [%i2], #one_read
@@ -465,11 +453,9 @@ xor_niagara_3:		/* %o0=bytes, %o1=dest, %o2=src1, %o3=src2 */
        wr              %g7, 0x0, %asi
        ret
         restore
-        .size           xor_niagara_3, .-xor_niagara_3
+ENDPROC(xor_niagara_3)
-        .globl          xor_niagara_4
+ENTRY(xor_niagara_4) /* %o0=bytes, %o1=dest, %o2=src1, %o3=src2, %o4=src3 */
-        .type           xor_niagara_4,#function
-xor_niagara_4:          /* %o0=bytes, %o1=dest, %o2=src1, %o3=src2, %o4=src3 */
        save            %sp, -192, %sp
        prefetch        [%i1], #n_writes
        prefetch        [%i2], #one_read
@@ -549,11 +535,9 @@ xor_niagara_4:		/* %o0=bytes, %o1=dest, %o2=src1, %o3=src2, %o4=src3 */
        wr              %g7, 0x0, %asi
        ret
         restore
-        .size           xor_niagara_4, .-xor_niagara_4
+ENDPROC(xor_niagara_4)
-        .globl          xor_niagara_5
+ENTRY(xor_niagara_5) /* %o0=bytes, %o1=dest, %o2=src1, %o3=src2, %o4=src3, %o5=src4 */
-        .type           xor_niagara_5,#function
-xor_niagara_5:          /* %o0=bytes, %o1=dest, %o2=src1, %o3=src2, %o4=src3, %o5=src4 */
        save            %sp, -192, %sp
        prefetch        [%i1], #n_writes
        prefetch        [%i2], #one_read
@@ -649,4 +633,4 @@ xor_niagara_5:		/* %o0=bytes, %o1=dest, %o2=src1, %o3=src2, %o4=src3, %o5=src4 *
        wr              %g7, 0x0, %asi
        ret
         restore
-        .size           xor_niagara_5, .-xor_niagara_5
+ENDPROC(xor_niagara_5)
diff --git a/arch/sparc/mm/Makefile b/arch/sparc/mm/Makefile
index 301421c11291..69ffd3112fed 100644
--- a/arch/sparc/mm/Makefile
+++ b/arch/sparc/mm/Makefile
@@ -7,8 +7,7 @@ ccflags-y := -Werror
 obj-$(CONFIG_SPARC64)   += ultra.o tlb.o tsb.o gup.o
 obj-y                   += fault_$(BITS).o
 obj-y                   += init_$(BITS).o
-obj-$(CONFIG_SPARC32)   += loadmmu.o
+obj-$(CONFIG_SPARC32)   += extable.o srmmu.o iommu.o io-unit.o
-obj-$(CONFIG_SPARC32)   += extable.o btfixup.o srmmu.o iommu.o io-unit.o
 obj-$(CONFIG_SPARC32)   += hypersparc.o viking.o tsunami.o swift.o
 obj-$(CONFIG_SPARC_LEON)+= leon_mm.o
@@ -17,9 +16,3 @@ obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o
 # Only used by sparc32
 obj-$(CONFIG_HIGHMEM)   += highmem.o
-ifdef CONFIG_SMP
-obj-$(CONFIG_SPARC32) += nosun4c.o
-else
-obj-$(CONFIG_SPARC32) += sun4c.o
-endif
diff --git a/arch/sparc/mm/btfixup.c b/arch/sparc/mm/btfixup.c
deleted file mode 100644
index 09d6af22db2d..000000000000
--- a/arch/sparc/mm/btfixup.c
+++ /dev/null
@@ -1,328 +0,0 @@
-/* btfixup.c: Boot time code fixup and relocator, so that
- * we can get rid of most indirect calls to achieve single
- * image sun4c and srmmu kernel.
- *
- * Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <asm/btfixup.h>
-#include <asm/page.h>
-#include <asm/pgalloc.h>
-#include <asm/pgtable.h>
-#include <asm/oplib.h>
-#include <asm/cacheflush.h>
-#define BTFIXUP_OPTIMIZE_NOP
-#define BTFIXUP_OPTIMIZE_OTHER
-extern char *srmmu_name;
-static char version[] __initdata = "Boot time fixup v1.6. 4/Mar/98 Jakub Jelinek (jj@ultra.linux.cz). Patching kernel for ";
-static char str_sun4c[] __initdata = "sun4c\n";
-static char str_srmmu[] __initdata = "srmmu[%s]/";
-static char str_iommu[] __initdata = "iommu\n";
-static char str_iounit[] __initdata = "io-unit\n";
-static int visited __initdata = 0;
-extern unsigned int ___btfixup_start[], ___btfixup_end[], __init_begin[], __init_end[], __init_text_end[];
-extern unsigned int _stext[], _end[], __start___ksymtab[], __stop___ksymtab[];
-static char wrong_f[] __initdata = "Trying to set f fixup %p to invalid function %08x\n";
-static char wrong_b[] __initdata = "Trying to set b fixup %p to invalid function %08x\n";
-static char wrong_s[] __initdata = "Trying to set s fixup %p to invalid value %08x\n";
-static char wrong_h[] __initdata = "Trying to set h fixup %p to invalid value %08x\n";
-static char wrong_a[] __initdata = "Trying to set a fixup %p to invalid value %08x\n";
-static char wrong[] __initdata = "Wrong address for %c fixup %p\n";
-static char insn_f[] __initdata = "Fixup f %p refers to weird instructions at %p[%08x,%08x]\n";
-static char insn_b[] __initdata = "Fixup b %p doesn't refer to a SETHI at %p[%08x]\n";
-static char insn_s[] __initdata = "Fixup s %p doesn't refer to an OR at %p[%08x]\n";
-static char insn_h[] __initdata = "Fixup h %p doesn't refer to a SETHI at %p[%08x]\n";
-static char insn_a[] __initdata = "Fixup a %p doesn't refer to a SETHI nor OR at %p[%08x]\n";
-static char insn_i[] __initdata = "Fixup i %p doesn't refer to a valid instruction at %p[%08x]\n";
-static char fca_und[] __initdata = "flush_cache_all undefined in btfixup()\n";
-static char wrong_setaddr[] __initdata = "Garbled CALL/INT patch at %p[%08x,%08x,%08x]=%08x\n";
-#ifdef BTFIXUP_OPTIMIZE_OTHER
-static void __init set_addr(unsigned int *addr, unsigned int q1, int fmangled, unsigned int value)
-{
-        if (!fmangled)
-                *addr = value;
-        else {
-                unsigned int *q = (unsigned int *)q1;
-                if (*addr == 0x01000000) {
-                        /* Noped */
-                        *q = value;
-                } else if (addr[-1] == *q) {
-                        /* Moved */
-                        addr[-1] = value;
-                        *q = value;
-                } else {
-                        prom_printf(wrong_setaddr, addr-1, addr[-1], *addr, *q, value);
-                        prom_halt();
-                }
-        }
-}
-#else
-static inline void set_addr(unsigned int *addr, unsigned int q1, int fmangled, unsigned int value)
-{
-        *addr = value;
-}
-#endif
-void __init btfixup(void)
-{
-        unsigned int *p, *q;
-        int type, count;
-        unsigned insn;
-        unsigned *addr;
-        int fmangled = 0;
-        void (*flush_cacheall)(void);
-        
-        if (!visited) {
-                visited++;
-                printk(version);
-                if (ARCH_SUN4C)
-                        printk(str_sun4c);
-                else {
-                        printk(str_srmmu, srmmu_name);
-                        if (sparc_cpu_model == sun4d)
-                                printk(str_iounit);
-                        else
-                                printk(str_iommu);
-                }
-        }
-        for (p = ___btfixup_start; p < ___btfixup_end; ) {
-                count = p[2];
-                q = p + 3;
-                switch (type = *(unsigned char *)p) {
-                case 'f': 
-                        count = p[3];
-                        q = p + 4;
-                        if (((p[0] & 1) || p[1]) 
-                            && ((p[1] & 3) || (unsigned *)(p[1]) < _stext || (unsigned *)(p[1]) >= _end)) {
-                                prom_printf(wrong_f, p, p[1]);
-                                prom_halt();
-                        }
-                        break;
-                case 'b':
-                        if (p[1] < (unsigned long)__init_begin || p[1] >= (unsigned long)__init_text_end || (p[1] & 3)) {
-                                prom_printf(wrong_b, p, p[1]);
-                                prom_halt();
-                        }
-                        break;
-                case 's':
-                        if (p[1] + 0x1000 >= 0x2000) {
-                                prom_printf(wrong_s, p, p[1]);
-                                prom_halt();
-                        }
-                        break;
-                case 'h':
-                        if (p[1] & 0x3ff) {
-                                prom_printf(wrong_h, p, p[1]);
-                                prom_halt();
-                        }
-                        break;
-                case 'a':
-                        if (p[1] + 0x1000 >= 0x2000 && (p[1] & 0x3ff)) {
-                                prom_printf(wrong_a, p, p[1]);
-                                prom_halt();
-                        }
-                        break;
-                }
-                if (p[0] & 1) {
-                        p[0] &= ~1;
-                        while (count) {
-                                fmangled = 0;
-                                addr = (unsigned *)*q;
-                                if (addr < _stext || addr >= _end) {
-                                        prom_printf(wrong, type, p);
-                                        prom_halt();
-                                }
-                                insn = *addr;
-#ifdef BTFIXUP_OPTIMIZE_OTHER                           
-                                if (type != 'f' && q[1]) {
-                                        insn = *(unsigned int *)q[1];
-                                        if (!insn || insn == 1)
-                                                insn = *addr;
-                                        else
-                                                fmangled = 1;
-                                }
-#endif
-                                switch (type) {
-                                case 'f':       /* CALL */
-                                        if (addr >= __start___ksymtab && addr < __stop___ksymtab) {
-                                                *addr = p[1];
-                                                break;
-                                        } else if (!q[1]) {
-                                                if ((insn & 0xc1c00000) == 0x01000000) { /* SETHI */
-                                                        *addr = (insn & 0xffc00000) | (p[1] >> 10); break;
-                                                } else if ((insn & 0xc1f82000) == 0x80102000) { /* OR X, %LO(i), Y */
-                                                        *addr = (insn & 0xffffe000) | (p[1] & 0x3ff); break;
-                                                } else if ((insn & 0xc0000000) != 0x40000000) { /* !CALL */
-                                bad_f:
-                                                        prom_printf(insn_f, p, addr, insn, addr[1]);
-                                                        prom_halt();
-                                                }
-                                        } else if (q[1] != 1)
-                                                addr[1] = q[1];
-                                        if (p[2] == BTFIXUPCALL_NORM) {
-                                norm_f: 
-                                                *addr = 0x40000000 | ((p[1] - (unsigned)addr) >> 2);
-                                                q[1] = 0;
-                                                break;
-                                        }
-#ifndef BTFIXUP_OPTIMIZE_NOP
-                                        goto norm_f;
-#else
-                                        if (!(addr[1] & 0x80000000)) {
-                                                if ((addr[1] & 0xc1c00000) != 0x01000000)       /* !SETHI */
-                                                        goto bad_f; /* CALL, Bicc, FBfcc, CBccc are weird in delay slot, aren't they? */
-                                        } else {
-                                                if ((addr[1] & 0x01800000) == 0x01800000) {
-                                                        if ((addr[1] & 0x01f80000) == 0x01e80000) {
-                                                                /* RESTORE */
-                                                                goto norm_f; /* It is dangerous to patch that */
-                                                        }
-                                                        goto bad_f;
-                                                }
-                                                if ((addr[1] & 0xffffe003) == 0x9e03e000) {
-                                                        /* ADD %O7, XX, %o7 */
-                                                        int displac = (addr[1] << 19);
-                                                        
-                                                        displac = (displac >> 21) + 2;
-                                                        *addr = (0x10800000) + (displac & 0x3fffff);
-                                                        q[1] = addr[1];
-                                                        addr[1] = p[2];
-                                                        break;
-                                                }
-                                                if ((addr[1] & 0x201f) == 0x200f || (addr[1] & 0x7c000) == 0x3c000)
-                                                        goto norm_f; /* Someone is playing bad tricks with us: rs1 or rs2 is o7 */
-                                                if ((addr[1] & 0x3e000000) == 0x1e000000)
-                                                        goto norm_f; /* rd is %o7. We'd better take care. */
-                                        }
-                                        if (p[2] == BTFIXUPCALL_NOP) {
-                                                *addr = 0x01000000;
-                                                q[1] = 1;
-                                                break;
-                                        }
-#ifndef BTFIXUP_OPTIMIZE_OTHER
-                                        goto norm_f;
-#else
-                                        if (addr[1] == 0x01000000) {    /* NOP in the delay slot */
-                                                q[1] = addr[1];
-                                                *addr = p[2];
-                                                break;
-                                        }
-                                        if ((addr[1] & 0xc0000000) != 0xc0000000) {
-                                                /* Not a memory operation */
-                                                if ((addr[1] & 0x30000000) == 0x10000000) {
-                                                        /* Ok, non-memory op with rd %oX */
-                                                        if ((addr[1] & 0x3e000000) == 0x1c000000)
-                                                                goto bad_f; /* Aiee. Someone is playing strange %sp tricks */
-                                                        if ((addr[1] & 0x3e000000) > 0x12000000 ||
-                                                            ((addr[1] & 0x3e000000) == 0x12000000 &&
-                                                             p[2] != BTFIXUPCALL_STO1O0 && p[2] != BTFIXUPCALL_SWAPO0O1) ||
-                                                            ((p[2] & 0xffffe000) == BTFIXUPCALL_RETINT(0))) {
-                                                                /* Nobody uses the result. We can nop it out. */
-                                                                *addr = p[2];
-                                                                q[1] = addr[1];
-                                                                addr[1] = 0x01000000;
-                                                                break;
-                                                        }
-                                                        if ((addr[1] & 0xf1ffffe0) == 0x90100000) {
-                                                                /* MOV %reg, %Ox */
-                                                                if ((addr[1] & 0x3e000000) == 0x10000000 &&
-                                                                    (p[2] & 0x7c000) == 0x20000) {
-                                                                        /* Ok, it is call xx; mov reg, %o0 and call optimizes
-                                                                           to doing something on %o0. Patch the patch. */
-                                                                        *addr = (p[2] & ~0x7c000) | ((addr[1] & 0x1f) << 14);
-                                                                        q[1] = addr[1];
-                                                                        addr[1] = 0x01000000;
-                                                                        break;
-                                                                }
-                                                                if ((addr[1] & 0x3e000000) == 0x12000000 &&
-                                                                    p[2] == BTFIXUPCALL_STO1O0) {
-                                                                        *addr = (p[2] & ~0x3e000000) | ((addr[1] & 0x1f) << 25);
-                                                                        q[1] = addr[1];
-                                                                        addr[1] = 0x01000000;
-                                                                        break;
-                                                                }
-                                                        }
-                                                }
-                                        }
-                                        *addr = addr[1];
-                                        q[1] = addr[1];
-                                        addr[1] = p[2];
-                                        break;
-#endif /* BTFIXUP_OPTIMIZE_OTHER */
-#endif /* BTFIXUP_OPTIMIZE_NOP */
-                                case 'b':       /* BLACKBOX */
-                                        /* Has to be sethi i, xx */
-                                        if ((insn & 0xc1c00000) != 0x01000000) {
-                                                prom_printf(insn_b, p, addr, insn);
-                                                prom_halt();
-                                        } else {
-                                                void (*do_fixup)(unsigned *);
-                                                
-                                                do_fixup = (void (*)(unsigned *))p[1];
-                                                do_fixup(addr);
-                                        }
-                                        break;
-                                case 's':       /* SIMM13 */
-                                        /* Has to be or %g0, i, xx */
-                                        if ((insn & 0xc1ffe000) != 0x80102000) {
-                                                prom_printf(insn_s, p, addr, insn);
-                                                prom_halt();
-                                        }
-                                        set_addr(addr, q[1], fmangled, (insn & 0xffffe000) | (p[1] & 0x1fff));
-                                        break;
-                                case 'h':       /* SETHI */
-                                        /* Has to be sethi i, xx */
-                                        if ((insn & 0xc1c00000) != 0x01000000) {
-                                                prom_printf(insn_h, p, addr, insn);
-                                                prom_halt();
-                                        }
-                                        set_addr(addr, q[1], fmangled, (insn & 0xffc00000) | (p[1] >> 10));
-                                        break;
-                                case 'a':       /* HALF */
-                                        /* Has to be sethi i, xx or or %g0, i, xx */
-                                        if ((insn & 0xc1c00000) != 0x01000000 &&
-                                            (insn & 0xc1ffe000) != 0x80102000) {
-                                                prom_printf(insn_a, p, addr, insn);
-                                                prom_halt();
-                                        }
-                                        if (p[1] & 0x3ff)
-                                                set_addr(addr, q[1], fmangled, 
-                                                        (insn & 0x3e000000) | 0x80102000 | (p[1] & 0x1fff));
-                                        else
-                                                set_addr(addr, q[1], fmangled, 
-                                                        (insn & 0x3e000000) | 0x01000000 | (p[1] >> 10));
-                                        break;
-                                case 'i':       /* INT */
-                                        if ((insn & 0xc1c00000) == 0x01000000) /* %HI */
-                                                set_addr(addr, q[1], fmangled, (insn & 0xffc00000) | (p[1] >> 10));
-                                        else if ((insn & 0x80002000) == 0x80002000) /* %LO */
-                                                set_addr(addr, q[1], fmangled, (insn & 0xffffe000) | (p[1] & 0x3ff));
-                                        else {
-                                                prom_printf(insn_i, p, addr, insn);
-                                                prom_halt();
-                                        }
-                                        break;
-                                }
-                                count -= 2;
-                                q += 2;
-                        }
-                } else
-                        p = q + count;
-        }
-#ifdef CONFIG_SMP
-        flush_cacheall = (void (*)(void))BTFIXUPVAL_CALL(local_flush_cache_all);
-#else
-        flush_cacheall = (void (*)(void))BTFIXUPVAL_CALL(flush_cache_all);
-#endif
-        if (!flush_cacheall) {
-                prom_printf(fca_und);
-                prom_halt();
-        }
-        (*flush_cacheall)();
-}
diff --git a/arch/sparc/mm/fault_32.c b/arch/sparc/mm/fault_32.c
index 7705c6731e28..f46cf6be3370 100644
--- a/arch/sparc/mm/fault_32.c
+++ b/arch/sparc/mm/fault_32.c
@@ -24,29 +24,19 @@
 #include <asm/page.h>
 #include <asm/pgtable.h>
-#include <asm/memreg.h>
 #include <asm/openprom.h>
 #include <asm/oplib.h>
 #include <asm/smp.h>
 #include <asm/traps.h>
 #include <asm/uaccess.h>
-extern int prom_node_root;
 int show_unhandled_signals = 1;
 /* At boot time we determine these two values necessary for setting
 * up the segment maps and page table entries (pte's).
 */
-int num_segmaps, num_contexts;
+int num_contexts;
-int invalid_segment;
-/* various Virtual Address Cache parameters we find at boot time... */
-int vac_size, vac_linesize, vac_do_hw_vac_flushes;
-int vac_entries_per_context, vac_entries_per_segment;
-int vac_entries_per_page;
 /* Return how much physical memory we have.  */
 unsigned long probe_memory(void)
@@ -60,55 +50,36 @@ unsigned long probe_memory(void)
        return total;
 }
-extern void sun4c_complete_all_stores(void);
-/* Whee, a level 15 NMI interrupt memory error.  Let's have fun... */
-asmlinkage void sparc_lvl15_nmi(struct pt_regs *regs, unsigned long serr,
-                                unsigned long svaddr, unsigned long aerr,
-                                unsigned long avaddr)
-{
-        sun4c_complete_all_stores();
-        printk("FAULT: NMI received\n");
-        printk("SREGS: Synchronous Error %08lx\n", serr);
-        printk("       Synchronous Vaddr %08lx\n", svaddr);
-        printk("      Asynchronous Error %08lx\n", aerr);
-        printk("      Asynchronous Vaddr %08lx\n", avaddr);
-        if (sun4c_memerr_reg)
-                printk("     Memory Parity Error %08lx\n", *sun4c_memerr_reg);
-        printk("REGISTER DUMP:\n");
-        show_regs(regs);
-        prom_halt();
-}
 static void unhandled_fault(unsigned long, struct task_struct *,
                struct pt_regs *) __attribute__ ((noreturn));
-static void unhandled_fault(unsigned long address, struct task_struct *tsk,
+static void __noreturn unhandled_fault(unsigned long address,
-                     struct pt_regs *regs)
+                                       struct task_struct *tsk,
+                                       struct pt_regs *regs)
 {
-        if((unsigned long) address < PAGE_SIZE) {
+        if ((unsigned long) address < PAGE_SIZE) {
                printk(KERN_ALERT
                    "Unable to handle kernel NULL pointer dereference\n");
        } else {
-                printk(KERN_ALERT "Unable to handle kernel paging request "
+                printk(KERN_ALERT "Unable to handle kernel paging request at virtual address %08lx\n",
-                       "at virtual address %08lx\n", address);
+                       address);
        }
        printk(KERN_ALERT "tsk->{mm,active_mm}->context = %08lx\n",
                (tsk->mm ? tsk->mm->context : tsk->active_mm->context));
        printk(KERN_ALERT "tsk->{mm,active_mm}->pgd = %08lx\n",
                (tsk->mm ? (unsigned long) tsk->mm->pgd :
-                        (unsigned long) tsk->active_mm->pgd));
+                        (unsigned long) tsk->active_mm->pgd));
        die_if_kernel("Oops", regs);
 }
-asmlinkage int lookup_fault(unsigned long pc, unsigned long ret_pc, 
+asmlinkage int lookup_fault(unsigned long pc, unsigned long ret_pc,
                            unsigned long address)
 {
        struct pt_regs regs;
        unsigned long g2;
        unsigned int insn;
        int i;
-        
        i = search_extables_range(ret_pc, &g2);
        switch (i) {
        case 3:
@@ -128,14 +99,14 @@ asmlinkage int lookup_fault(unsigned long pc, unsigned long ret_pc,
                /* for _from_ macros */
                insn = *((unsigned int *) pc);
                if (!((insn >> 21) & 1) || ((insn>>19)&0x3f) == 15)
-                        return 2; 
+                        return 2;
-                break; 
+                break;
        default:
                break;
        }
-        memset(&regs, 0, sizeof (regs));
+        memset(&regs, 0, sizeof(regs));
        regs.pc = pc;
        regs.npc = pc + 4;
        __asm__ __volatile__(
@@ -198,11 +169,10 @@ static unsigned long compute_si_addr(struct pt_regs *regs, int text_fault)
        if (text_fault)
                return regs->pc;
-        if (regs->psr & PSR_PS) {
+        if (regs->psr & PSR_PS)
                insn = *(unsigned int *) regs->pc;
-        } else {
+        else
                __get_user(insn, (unsigned int *) regs->pc);
-        }
        return safe_compute_effective_address(regs, insn);
 }
@@ -225,8 +195,10 @@ asmlinkage void do_sparc_fault(struct pt_regs *regs, int text_fault, int write,
        unsigned long g2;
        int from_user = !(regs->psr & PSR_PS);
        int fault, code;
+        unsigned int flags = (FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE |
+                              (write ? FAULT_FLAG_WRITE : 0));
-        if(text_fault)
+        if (text_fault)
                address = regs->pc;
        /*
@@ -239,35 +211,32 @@ asmlinkage void do_sparc_fault(struct pt_regs *regs, int text_fault, int write,
         * nothing more.
         */
        code = SEGV_MAPERR;
-        if (!ARCH_SUN4C && address >= TASK_SIZE)
+        if (address >= TASK_SIZE)
                goto vmalloc_fault;
        /*
         * If we're in an interrupt or have no user
         * context, we must not take the fault..
         */
-        if (in_atomic() || !mm)
+        if (in_atomic() || !mm)
-                goto no_context;
+                goto no_context;
        perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, regs, address);
+retry:
        down_read(&mm->mmap_sem);
-        /*
+        if (!from_user && address >= PAGE_OFFSET)
-         * The kernel referencing a bad kernel pointer can lock up
-         * a sun4c machine completely, so we must attempt recovery.
-         */
-        if(!from_user && address >= PAGE_OFFSET)
                goto bad_area;
        vma = find_vma(mm, address);
-        if(!vma)
+        if (!vma)
                goto bad_area;
-        if(vma->vm_start <= address)
+        if (vma->vm_start <= address)
                goto good_area;
-        if(!(vma->vm_flags & VM_GROWSDOWN))
+        if (!(vma->vm_flags & VM_GROWSDOWN))
                goto bad_area;
-        if(expand_stack(vma, address))
+        if (expand_stack(vma, address))
                goto bad_area;
        /*
         * Ok, we have a good vm_area for this memory access, so
@@ -275,12 +244,12 @@ asmlinkage void do_sparc_fault(struct pt_regs *regs, int text_fault, int write,
         */
 good_area:
        code = SEGV_ACCERR;
-        if(write) {
+        if (write) {
-                if(!(vma->vm_flags & VM_WRITE))
+                if (!(vma->vm_flags & VM_WRITE))
                        goto bad_area;
        } else {
                /* Allow reads even for write-only mappings */
-                if(!(vma->vm_flags & (VM_READ | VM_EXEC)))
+                if (!(vma->vm_flags & (VM_READ | VM_EXEC)))
                        goto bad_area;
        }
@@ -289,7 +258,11 @@ good_area:
         * make sure we exit gracefully rather than endlessly redo
         * the fault.
         */
-        fault = handle_mm_fault(mm, vma, address, write ? FAULT_FLAG_WRITE : 0);
+        fault = handle_mm_fault(mm, vma, address, flags);
+        if ((fault & VM_FAULT_RETRY) && fatal_signal_pending(current))
+                return;
        if (unlikely(fault & VM_FAULT_ERROR)) {
                if (fault & VM_FAULT_OOM)
                        goto out_of_memory;
@@ -297,13 +270,29 @@ good_area:
                        goto do_sigbus;
                BUG();
        }
-        if (fault & VM_FAULT_MAJOR) {
-                current->maj_flt++;
+        if (flags & FAULT_FLAG_ALLOW_RETRY) {
-                perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1, regs, address);
+                if (fault & VM_FAULT_MAJOR) {
-        } else {
+                        current->maj_flt++;
-                current->min_flt++;
+                        perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ,
-                perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1, regs, address);
+                                      1, regs, address);
+                } else {
+                        current->min_flt++;
+                        perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN,
+                                      1, regs, address);
+                }
+                if (fault & VM_FAULT_RETRY) {
+                        flags &= ~FAULT_FLAG_ALLOW_RETRY;
+                        /* No need to up_read(&mm->mmap_sem) as we would
+                         * have already released it in __lock_page_or_retry
+                         * in mm/filemap.c.
+                         */
+                        goto retry;
+                }
        }
        up_read(&mm->mmap_sem);
        return;
@@ -326,14 +315,16 @@ no_context:
        g2 = regs->u_regs[UREG_G2];
        if (!from_user) {
                fixup = search_extables_range(regs->pc, &g2);
-                if (fixup > 10) { /* Values below are reserved for other things */
+                /* Values below 10 are reserved for other things */
+                if (fixup > 10) {
                        extern const unsigned __memset_start[];
                        extern const unsigned __memset_end[];
                        extern const unsigned __csum_partial_copy_start[];
                        extern const unsigned __csum_partial_copy_end[];
 #ifdef DEBUG_EXCEPTIONS
-                        printk("Exception: PC<%08lx> faddr<%08lx>\n", regs->pc, address);
+                        printk("Exception: PC<%08lx> faddr<%08lx>\n",
+                               regs->pc, address);
                        printk("EX_TABLE: insn<%08lx> fixup<%08x> g2<%08lx>\n",
                                regs->pc, fixup, g2);
 #endif
@@ -341,7 +332,7 @@ no_context:
                             regs->pc < (unsigned long)__memset_end) ||
                            (regs->pc >= (unsigned long)__csum_partial_copy_start &&
                             regs->pc < (unsigned long)__csum_partial_copy_end)) {
-                                regs->u_regs[UREG_I4] = address;
+                                regs->u_regs[UREG_I4] = address;
                                regs->u_regs[UREG_I5] = regs->pc;
                        }
                        regs->u_regs[UREG_G2] = g2;
@@ -350,8 +341,8 @@ no_context:
                        return;
                }
        }
-        
-        unhandled_fault (address, tsk, regs);
+        unhandled_fault(address, tsk, regs);
        do_exit(SIGKILL);
 /*
@@ -397,97 +388,12 @@ vmalloc_fault:
                if (pmd_present(*pmd) || !pmd_present(*pmd_k))
                        goto bad_area_nosemaphore;
                *pmd = *pmd_k;
                return;
        }
 }
-asmlinkage void do_sun4c_fault(struct pt_regs *regs, int text_fault, int write,
-                               unsigned long address)
-{
-        extern void sun4c_update_mmu_cache(struct vm_area_struct *,
-                                           unsigned long,pte_t *);
-        extern pte_t *sun4c_pte_offset_kernel(pmd_t *,unsigned long);
-        struct task_struct *tsk = current;
-        struct mm_struct *mm = tsk->mm;
-        pgd_t *pgdp;
-        pte_t *ptep;
-        if (text_fault) {
-                address = regs->pc;
-        } else if (!write &&
-                   !(regs->psr & PSR_PS)) {
-                unsigned int insn, __user *ip;
-                ip = (unsigned int __user *)regs->pc;
-                if (!get_user(insn, ip)) {
-                        if ((insn & 0xc1680000) == 0xc0680000)
-                                write = 1;
-                }
-        }
-        if (!mm) {
-                /* We are oopsing. */
-                do_sparc_fault(regs, text_fault, write, address);
-                BUG();  /* P3 Oops already, you bitch */
-        }
-        pgdp = pgd_offset(mm, address);
-        ptep = sun4c_pte_offset_kernel((pmd_t *) pgdp, address);
-        if (pgd_val(*pgdp)) {
-            if (write) {
-                if ((pte_val(*ptep) & (_SUN4C_PAGE_WRITE|_SUN4C_PAGE_PRESENT))
-                                   == (_SUN4C_PAGE_WRITE|_SUN4C_PAGE_PRESENT)) {
-                        unsigned long flags;
-                        *ptep = __pte(pte_val(*ptep) | _SUN4C_PAGE_ACCESSED |
-                                      _SUN4C_PAGE_MODIFIED |
-                                      _SUN4C_PAGE_VALID |
-                                      _SUN4C_PAGE_DIRTY);
-                        local_irq_save(flags);
-                        if (sun4c_get_segmap(address) != invalid_segment) {
-                                sun4c_put_pte(address, pte_val(*ptep));
-                                local_irq_restore(flags);
-                                return;
-                        }
-                        local_irq_restore(flags);
-                }
-            } else {
-                if ((pte_val(*ptep) & (_SUN4C_PAGE_READ|_SUN4C_PAGE_PRESENT))
-                                   == (_SUN4C_PAGE_READ|_SUN4C_PAGE_PRESENT)) {
-                        unsigned long flags;
-                        *ptep = __pte(pte_val(*ptep) | _SUN4C_PAGE_ACCESSED |
-                                      _SUN4C_PAGE_VALID);
-                        local_irq_save(flags);
-                        if (sun4c_get_segmap(address) != invalid_segment) {
-                                sun4c_put_pte(address, pte_val(*ptep));
-                                local_irq_restore(flags);
-                                return;
-                        }
-                        local_irq_restore(flags);
-                }
-            }
-        }
-        /* This conditional is 'interesting'. */
-        if (pgd_val(*pgdp) && !(write && !(pte_val(*ptep) & _SUN4C_PAGE_WRITE))
-            && (pte_val(*ptep) & _SUN4C_PAGE_VALID))
-                /* Note: It is safe to not grab the MMAP semaphore here because
-                 *       we know that update_mmu_cache() will not sleep for
-                 *       any reason (at least not in the current implementation)
-                 *       and therefore there is no danger of another thread getting
-                 *       on the CPU and doing a shrink_mmap() on this vma.
-                 */
-                sun4c_update_mmu_cache (find_vma(current->mm, address), address,
-                                        ptep);
-        else
-                do_sparc_fault(regs, text_fault, write, address);
-}
 /* This always deals with user addresses. */
 static void force_user_fault(unsigned long address, int write)
 {
@@ -500,21 +406,21 @@ static void force_user_fault(unsigned long address, int write)
        down_read(&mm->mmap_sem);
        vma = find_vma(mm, address);
-        if(!vma)
+        if (!vma)
                goto bad_area;
-        if(vma->vm_start <= address)
+        if (vma->vm_start <= address)
                goto good_area;
-        if(!(vma->vm_flags & VM_GROWSDOWN))
+        if (!(vma->vm_flags & VM_GROWSDOWN))
                goto bad_area;
-        if(expand_stack(vma, address))
+        if (expand_stack(vma, address))
                goto bad_area;
 good_area:
        code = SEGV_ACCERR;
-        if(write) {
+        if (write) {
-                if(!(vma->vm_flags & VM_WRITE))
+                if (!(vma->vm_flags & VM_WRITE))
                        goto bad_area;
        } else {
-                if(!(vma->vm_flags & (VM_READ | VM_EXEC)))
+                if (!(vma->vm_flags & (VM_READ | VM_EXEC)))
                        goto bad_area;
        }
        switch (handle_mm_fault(mm, vma, address, write ? FAULT_FLAG_WRITE : 0)) {
@@ -545,7 +451,7 @@ void window_overflow_fault(void)
        unsigned long sp;
        sp = current_thread_info()->rwbuf_stkptrs[0];
-        if(((sp + 0x38) & PAGE_MASK) != (sp & PAGE_MASK))
+        if (((sp + 0x38) & PAGE_MASK) != (sp & PAGE_MASK))
                force_user_fault(sp + 0x38, 1);
        force_user_fault(sp, 1);
@@ -554,7 +460,7 @@ void window_overflow_fault(void)
 void window_underflow_fault(unsigned long sp)
 {
-        if(((sp + 0x38) & PAGE_MASK) != (sp & PAGE_MASK))
+        if (((sp + 0x38) & PAGE_MASK) != (sp & PAGE_MASK))
                force_user_fault(sp + 0x38, 0);
        force_user_fault(sp, 0);
@@ -566,7 +472,7 @@ void window_ret_fault(struct pt_regs *regs)
        unsigned long sp;
        sp = regs->u_regs[UREG_FP];
-        if(((sp + 0x38) & PAGE_MASK) != (sp & PAGE_MASK))
+        if (((sp + 0x38) & PAGE_MASK) != (sp & PAGE_MASK))
                force_user_fault(sp + 0x38, 0);
        force_user_fault(sp, 0);
diff --git a/arch/sparc/mm/fault_64.c b/arch/sparc/mm/fault_64.c
index 504c0622f729..1fe0429b6314 100644
--- a/arch/sparc/mm/fault_64.c
+++ b/arch/sparc/mm/fault_64.c
@@ -279,6 +279,7 @@ asmlinkage void __kprobes do_sparc64_fault(struct pt_regs *regs)
        unsigned int insn = 0;
        int si_code, fault_code, fault;
        unsigned long address, mm_rss;
+        unsigned int flags = FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE;
        fault_code = get_thread_fault_code();
@@ -333,6 +334,8 @@ asmlinkage void __kprobes do_sparc64_fault(struct pt_regs *regs)
                        insn = get_fault_insn(regs, insn);
                        goto handle_kernel_fault;
                }
+retry:
                down_read(&mm->mmap_sem);
        }
@@ -423,7 +426,12 @@ good_area:
                        goto bad_area;
        }
-        fault = handle_mm_fault(mm, vma, address, (fault_code & FAULT_CODE_WRITE) ? FAULT_FLAG_WRITE : 0);
+        flags |= ((fault_code & FAULT_CODE_WRITE) ? FAULT_FLAG_WRITE : 0);
+        fault = handle_mm_fault(mm, vma, address, flags);
+        if ((fault & VM_FAULT_RETRY) && fatal_signal_pending(current))
+                return;
        if (unlikely(fault & VM_FAULT_ERROR)) {
                if (fault & VM_FAULT_OOM)
                        goto out_of_memory;
@@ -431,12 +439,27 @@ good_area:
                        goto do_sigbus;
                BUG();
        }
-        if (fault & VM_FAULT_MAJOR) {
-                current->maj_flt++;
+        if (flags & FAULT_FLAG_ALLOW_RETRY) {
-                perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1, regs, address);
+                if (fault & VM_FAULT_MAJOR) {
-        } else {
+                        current->maj_flt++;
-                current->min_flt++;
+                        perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ,
-                perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1, regs, address);
+                                      1, regs, address);
+                } else {
+                        current->min_flt++;
+                        perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN,
+                                      1, regs, address);
+                }
+                if (fault & VM_FAULT_RETRY) {
+                        flags &= ~FAULT_FLAG_ALLOW_RETRY;
+                        /* No need to up_read(&mm->mmap_sem) as we would
+                         * have already released it in __lock_page_or_retry
+                         * in mm/filemap.c.
+                         */
+                        goto retry;
+                }
        }
        up_read(&mm->mmap_sem);
diff --git a/arch/sparc/mm/init_32.c b/arch/sparc/mm/init_32.c
index c5f9021b1a01..ef5c779ec855 100644
--- a/arch/sparc/mm/init_32.c
+++ b/arch/sparc/mm/init_32.c
@@ -27,7 +27,6 @@
 #include <linux/gfp.h>
 #include <asm/sections.h>
-#include <asm/vac-ops.h>
 #include <asm/page.h>
 #include <asm/pgtable.h>
 #include <asm/vaddrs.h>
@@ -45,9 +44,6 @@ EXPORT_SYMBOL(phys_base);
 unsigned long pfn_base;
 EXPORT_SYMBOL(pfn_base);
-unsigned long page_kernel;
-EXPORT_SYMBOL(page_kernel);
 struct sparc_phys_banks sp_banks[SPARC_PHYS_BANKS+1];
 unsigned long sparc_unmapped_base;
@@ -287,44 +283,16 @@ unsigned long __init bootmem_init(unsigned long *pages_avail)
 }
 /*
- * check_pgt_cache
- *
- * This is called at the end of unmapping of VMA (zap_page_range),
- * to rescan the page cache for architecture specific things,
- * presumably something like sun4/sun4c PMEGs. Most architectures
- * define check_pgt_cache empty.
- *
- * We simply copy the 2.4 implementation for now.
- */
-static int pgt_cache_water[2] = { 25, 50 };
-void check_pgt_cache(void)
-{
-        do_check_pgt_cache(pgt_cache_water[0], pgt_cache_water[1]);
-}
-/*
 * paging_init() sets up the page tables: We call the MMU specific
 * init routine based upon the Sun model type on the Sparc.
 *
 */
-extern void sun4c_paging_init(void);
 extern void srmmu_paging_init(void);
 extern void device_scan(void);
-pgprot_t PAGE_SHARED __read_mostly;
-EXPORT_SYMBOL(PAGE_SHARED);
 void __init paging_init(void)
 {
        switch(sparc_cpu_model) {
-        case sun4c:
-        case sun4e:
-        case sun4:
-                sun4c_paging_init();
-                sparc_unmapped_base = 0xe0000000;
-                BTFIXUPSET_SETHI(sparc_unmapped_base, 0xe0000000);
-                break;
        case sparc_leon:
                leon_init();
                /* fall through */
@@ -332,7 +300,6 @@ void __init paging_init(void)
        case sun4d:
                srmmu_paging_init();
                sparc_unmapped_base = 0x50000000;
-                BTFIXUPSET_SETHI(sparc_unmapped_base, 0x50000000);
                break;
        default:
                prom_printf("paging_init: Cannot init paging on this Sparc\n");
@@ -341,24 +308,6 @@ void __init paging_init(void)
                prom_halt();
        }
-        /* Initialize the protection map with non-constant, MMU dependent values. */
-        protection_map[0] = PAGE_NONE;
-        protection_map[1] = PAGE_READONLY;
-        protection_map[2] = PAGE_COPY;
-        protection_map[3] = PAGE_COPY;
-        protection_map[4] = PAGE_READONLY;
-        protection_map[5] = PAGE_READONLY;
-        protection_map[6] = PAGE_COPY;
-        protection_map[7] = PAGE_COPY;
-        protection_map[8] = PAGE_NONE;
-        protection_map[9] = PAGE_READONLY;
-        protection_map[10] = PAGE_SHARED;
-        protection_map[11] = PAGE_SHARED;
-        protection_map[12] = PAGE_READONLY;
-        protection_map[13] = PAGE_READONLY;
-        protection_map[14] = PAGE_SHARED;
-        protection_map[15] = PAGE_SHARED;
-        btfixup();
        prom_build_devicetree();
        of_fill_in_cpu_data();
        device_scan();
diff --git a/arch/sparc/mm/init_64.c b/arch/sparc/mm/init_64.c
index 21faaeea85de..6026fdd1b2ed 100644
--- a/arch/sparc/mm/init_64.c
+++ b/arch/sparc/mm/init_64.c
@@ -741,7 +741,6 @@ static void __init find_ramdisk(unsigned long phys_base)
 struct node_mem_mask {
        unsigned long mask;
        unsigned long val;
-        unsigned long bootmem_paddr;
 };
 static struct node_mem_mask node_masks[MAX_NUMNODES];
 static int num_node_masks;
@@ -806,12 +805,6 @@ static u64 memblock_nid_range(u64 start, u64 end, int *nid)
        return start;
 }
-#else
-static u64 memblock_nid_range(u64 start, u64 end, int *nid)
-{
-        *nid = 0;
-        return end;
-}
 #endif
 /* This must be invoked after performing all of the necessary
@@ -820,10 +813,11 @@ static u64 memblock_nid_range(u64 start, u64 end, int *nid)
 */
 static void __init allocate_node_data(int nid)
 {
-        unsigned long paddr, num_pages, start_pfn, end_pfn;
        struct pglist_data *p;
+        unsigned long start_pfn, end_pfn;
 #ifdef CONFIG_NEED_MULTIPLE_NODES
+        unsigned long paddr;
        paddr = memblock_alloc_try_nid(sizeof(struct pglist_data), SMP_CACHE_BYTES, nid);
        if (!paddr) {
                prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid);
@@ -832,7 +826,7 @@ static void __init allocate_node_data(int nid)
        NODE_DATA(nid) = __va(paddr);
        memset(NODE_DATA(nid), 0, sizeof(struct pglist_data));
-        NODE_DATA(nid)->bdata = &bootmem_node_data[nid];
+        NODE_DATA(nid)->node_id = nid;
 #endif
        p = NODE_DATA(nid);
@@ -840,18 +834,6 @@ static void __init allocate_node_data(int nid)
        get_pfn_range_for_nid(nid, &start_pfn, &end_pfn);
        p->node_start_pfn = start_pfn;
        p->node_spanned_pages = end_pfn - start_pfn;
-        if (p->node_spanned_pages) {
-                num_pages = bootmem_bootmap_pages(p->node_spanned_pages);
-                paddr = memblock_alloc_try_nid(num_pages << PAGE_SHIFT, PAGE_SIZE, nid);
-                if (!paddr) {
-                        prom_printf("Cannot allocate bootmap for nid[%d]\n",
-                                  nid);
-                        prom_halt();
-                }
-                node_masks[nid].bootmem_paddr = paddr;
-        }
 }
 static void init_node_masks_nonnuma(void)
@@ -1292,75 +1274,9 @@ static void __init bootmem_init_nonnuma(void)
        node_set_online(0);
 }
-static void __init reserve_range_in_node(int nid, unsigned long start,
-                                         unsigned long end)
-{
-        numadbg("    reserve_range_in_node(nid[%d],start[%lx],end[%lx]\n",
-                nid, start, end);
-        while (start < end) {
-                unsigned long this_end;
-                int n;
-                this_end = memblock_nid_range(start, end, &n);
-                if (n == nid) {
-                        numadbg("      MATCH reserving range [%lx:%lx]\n",
-                                start, this_end);
-                        reserve_bootmem_node(NODE_DATA(nid), start,
-                                             (this_end - start), BOOTMEM_DEFAULT);
-                } else
-                        numadbg("      NO MATCH, advancing start to %lx\n",
-                                this_end);
-                start = this_end;
-        }
-}
-static void __init trim_reserved_in_node(int nid)
-{
-        struct memblock_region *reg;
-        numadbg("  trim_reserved_in_node(%d)\n", nid);
-        for_each_memblock(reserved, reg)
-                reserve_range_in_node(nid, reg->base, reg->base + reg->size);
-}
-static void __init bootmem_init_one_node(int nid)
-{
-        struct pglist_data *p;
-        numadbg("bootmem_init_one_node(%d)\n", nid);
-        p = NODE_DATA(nid);
-        if (p->node_spanned_pages) {
-                unsigned long paddr = node_masks[nid].bootmem_paddr;
-                unsigned long end_pfn;
-                end_pfn = p->node_start_pfn + p->node_spanned_pages;
-                numadbg("  init_bootmem_node(%d, %lx, %lx, %lx)\n",
-                        nid, paddr >> PAGE_SHIFT, p->node_start_pfn, end_pfn);
-                init_bootmem_node(p, paddr >> PAGE_SHIFT,
-                                  p->node_start_pfn, end_pfn);
-                numadbg("  free_bootmem_with_active_regions(%d, %lx)\n",
-                        nid, end_pfn);
-                free_bootmem_with_active_regions(nid, end_pfn);
-                trim_reserved_in_node(nid);
-                numadbg("  sparse_memory_present_with_active_regions(%d)\n",
-                        nid);
-                sparse_memory_present_with_active_regions(nid);
-        }
-}
 static unsigned long __init bootmem_init(unsigned long phys_base)
 {
        unsigned long end_pfn;
-        int nid;
        end_pfn = memblock_end_of_DRAM() >> PAGE_SHIFT;
        max_pfn = max_low_pfn = end_pfn;
@@ -1369,11 +1285,12 @@ static unsigned long __init bootmem_init(unsigned long phys_base)
        if (bootmem_init_numa() < 0)
                bootmem_init_nonnuma();
-        /* XXX cpu notifier XXX */
+        /* Dump memblock with node info. */
+        memblock_dump_all();
-        for_each_online_node(nid)
+        /* XXX cpu notifier XXX */
-                bootmem_init_one_node(nid);
+        sparse_memory_present_with_active_regions(MAX_NUMNODES);
        sparse_init();
        return end_pfn;
@@ -1701,6 +1618,7 @@ void __init paging_init(void)
 {
        unsigned long end_pfn, shift, phys_base;
        unsigned long real_end, i;
+        int node;
        /* These build time checkes make sure that the dcache_dirty_cpu()
         * page->flags usage will work.
@@ -1826,22 +1744,24 @@ void __init paging_init(void)
 #endif
        }
+        /* Setup bootmem... */
+        last_valid_pfn = end_pfn = bootmem_init(phys_base);
        /* Once the OF device tree and MDESC have been setup, we know
         * the list of possible cpus.  Therefore we can allocate the
         * IRQ stacks.
         */
        for_each_possible_cpu(i) {
-                /* XXX Use node local allocations... XXX */
+                node = cpu_to_node(i);
-                softirq_stack[i] = __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
-                hardirq_stack[i] = __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
-        }
-        /* Setup bootmem... */
+                softirq_stack[i] = __alloc_bootmem_node(NODE_DATA(node),
-        last_valid_pfn = end_pfn = bootmem_init(phys_base);
+                                                        THREAD_SIZE,
+                                                        THREAD_SIZE, 0);
+                hardirq_stack[i] = __alloc_bootmem_node(NODE_DATA(node),
+                                                        THREAD_SIZE,
+                                                        THREAD_SIZE, 0);
+        }
-#ifndef CONFIG_NEED_MULTIPLE_NODES
-        max_mapnr = last_valid_pfn;
-#endif
        kernel_physical_mapping_init();
        {
@@ -1973,6 +1893,7 @@ void __init mem_init(void)
                                        free_all_bootmem_node(NODE_DATA(i));
                        }
                }
+                totalram_pages += free_low_memory_core_early(MAX_NUMNODES);
        }
 #else
        totalram_pages = free_all_bootmem();
diff --git a/arch/sparc/mm/io-unit.c b/arch/sparc/mm/io-unit.c
index fc58c3e917df..eb99862e9654 100644
--- a/arch/sparc/mm/io-unit.c
+++ b/arch/sparc/mm/io-unit.c
@@ -197,7 +197,7 @@ static void iounit_release_scsi_sgl(struct device *dev, struct scatterlist *sg,
 }
 #ifdef CONFIG_SBUS
-static int iounit_map_dma_area(struct device *dev, dma_addr_t *pba, unsigned long va, __u32 addr, int len)
+static int iounit_map_dma_area(struct device *dev, dma_addr_t *pba, unsigned long va, unsigned long addr, int len)
 {
        struct iounit_struct *iounit = dev->archdata.iommu;
        unsigned long page, end;
@@ -242,29 +242,18 @@ static void iounit_unmap_dma_area(struct device *dev, unsigned long addr, int le
 }
 #endif
-static char *iounit_lockarea(char *vaddr, unsigned long len)
+static const struct sparc32_dma_ops iounit_dma_ops = {
-{
+        .get_scsi_one           = iounit_get_scsi_one,
-/* FIXME: Write this */
+        .get_scsi_sgl           = iounit_get_scsi_sgl,
-        return vaddr;
+        .release_scsi_one       = iounit_release_scsi_one,
-}
+        .release_scsi_sgl       = iounit_release_scsi_sgl,
+#ifdef CONFIG_SBUS
-static void iounit_unlockarea(char *vaddr, unsigned long len)
+        .map_dma_area           = iounit_map_dma_area,
-{
+        .unmap_dma_area         = iounit_unmap_dma_area,
-/* FIXME: Write this */
+#endif
-}
+};
 void __init ld_mmu_iounit(void)
 {
-        BTFIXUPSET_CALL(mmu_lockarea, iounit_lockarea, BTFIXUPCALL_RETO0);
+        sparc32_dma_ops = &iounit_dma_ops;
-        BTFIXUPSET_CALL(mmu_unlockarea, iounit_unlockarea, BTFIXUPCALL_NOP);
-        BTFIXUPSET_CALL(mmu_get_scsi_one, iounit_get_scsi_one, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(mmu_get_scsi_sgl, iounit_get_scsi_sgl, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(mmu_release_scsi_one, iounit_release_scsi_one, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(mmu_release_scsi_sgl, iounit_release_scsi_sgl, BTFIXUPCALL_NORM);
-#ifdef CONFIG_SBUS
-        BTFIXUPSET_CALL(mmu_map_dma_area, iounit_map_dma_area, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(mmu_unmap_dma_area, iounit_unmap_dma_area, BTFIXUPCALL_NORM);
-#endif
 }
diff --git a/arch/sparc/mm/iommu.c b/arch/sparc/mm/iommu.c
index 07fc6a65d9b6..a8a58cad9d2b 100644
--- a/arch/sparc/mm/iommu.c
+++ b/arch/sparc/mm/iommu.c
@@ -39,8 +39,6 @@
 /* srmmu.c */
 extern int viking_mxcc_present;
-BTFIXUPDEF_CALL(void, flush_page_for_dma, unsigned long)
-#define flush_page_for_dma(page) BTFIXUP_CALL(flush_page_for_dma)(page)
 extern int flush_page_for_dma_global;
 static int viking_flush;
 /* viking.S */
@@ -143,7 +141,6 @@ static int __init iommu_init(void)
 subsys_initcall(iommu_init);
-/* This begs to be btfixup-ed by srmmu. */
 /* Flush the iotlb entries to ram. */
 /* This could be better if we didn't have to flush whole pages. */
 static void iommu_flush_iotlb(iopte_t *iopte, unsigned int niopte)
@@ -216,11 +213,6 @@ static u32 iommu_get_scsi_one(struct device *dev, char *vaddr, unsigned int len)
        return busa + off;
 }
-static __u32 iommu_get_scsi_one_noflush(struct device *dev, char *vaddr, unsigned long len)
-{
-        return iommu_get_scsi_one(dev, vaddr, len);
-}
 static __u32 iommu_get_scsi_one_gflush(struct device *dev, char *vaddr, unsigned long len)
 {
        flush_page_for_dma(0);
@@ -238,19 +230,6 @@ static __u32 iommu_get_scsi_one_pflush(struct device *dev, char *vaddr, unsigned
        return iommu_get_scsi_one(dev, vaddr, len);
 }
-static void iommu_get_scsi_sgl_noflush(struct device *dev, struct scatterlist *sg, int sz)
-{
-        int n;
-        while (sz != 0) {
-                --sz;
-                n = (sg->length + sg->offset + PAGE_SIZE-1) >> PAGE_SHIFT;
-                sg->dma_address = iommu_get_one(dev, sg_page(sg), n) + sg->offset;
-                sg->dma_length = sg->length;
-                sg = sg_next(sg);
-        }
-}
 static void iommu_get_scsi_sgl_gflush(struct device *dev, struct scatterlist *sg, int sz)
 {
        int n;
@@ -426,40 +405,36 @@ static void iommu_unmap_dma_area(struct device *dev, unsigned long busa, int len
 }
 #endif
-static char *iommu_lockarea(char *vaddr, unsigned long len)
+static const struct sparc32_dma_ops iommu_dma_gflush_ops = {
-{
+        .get_scsi_one           = iommu_get_scsi_one_gflush,
-        return vaddr;
+        .get_scsi_sgl           = iommu_get_scsi_sgl_gflush,
-}
+        .release_scsi_one       = iommu_release_scsi_one,
+        .release_scsi_sgl       = iommu_release_scsi_sgl,
+#ifdef CONFIG_SBUS
+        .map_dma_area           = iommu_map_dma_area,
+        .unmap_dma_area         = iommu_unmap_dma_area,
+#endif
+};
-static void iommu_unlockarea(char *vaddr, unsigned long len)
+static const struct sparc32_dma_ops iommu_dma_pflush_ops = {
-{
+        .get_scsi_one           = iommu_get_scsi_one_pflush,
-}
+        .get_scsi_sgl           = iommu_get_scsi_sgl_pflush,
+        .release_scsi_one       = iommu_release_scsi_one,
+        .release_scsi_sgl       = iommu_release_scsi_sgl,
+#ifdef CONFIG_SBUS
+        .map_dma_area           = iommu_map_dma_area,
+        .unmap_dma_area         = iommu_unmap_dma_area,
+#endif
+};
 void __init ld_mmu_iommu(void)
 {
-        viking_flush = (BTFIXUPVAL_CALL(flush_page_for_dma) == (unsigned long)viking_flush_page);
+        if (flush_page_for_dma_global) {
-        BTFIXUPSET_CALL(mmu_lockarea, iommu_lockarea, BTFIXUPCALL_RETO0);
-        BTFIXUPSET_CALL(mmu_unlockarea, iommu_unlockarea, BTFIXUPCALL_NOP);
-        if (!BTFIXUPVAL_CALL(flush_page_for_dma)) {
-                /* IO coherent chip */
-                BTFIXUPSET_CALL(mmu_get_scsi_one, iommu_get_scsi_one_noflush, BTFIXUPCALL_RETO0);
-                BTFIXUPSET_CALL(mmu_get_scsi_sgl, iommu_get_scsi_sgl_noflush, BTFIXUPCALL_NORM);
-        } else if (flush_page_for_dma_global) {
                /* flush_page_for_dma flushes everything, no matter of what page is it */
-                BTFIXUPSET_CALL(mmu_get_scsi_one, iommu_get_scsi_one_gflush, BTFIXUPCALL_NORM);
+                sparc32_dma_ops = &iommu_dma_gflush_ops;
-                BTFIXUPSET_CALL(mmu_get_scsi_sgl, iommu_get_scsi_sgl_gflush, BTFIXUPCALL_NORM);
        } else {
-                BTFIXUPSET_CALL(mmu_get_scsi_one, iommu_get_scsi_one_pflush, BTFIXUPCALL_NORM);
+                sparc32_dma_ops = &iommu_dma_pflush_ops;
-                BTFIXUPSET_CALL(mmu_get_scsi_sgl, iommu_get_scsi_sgl_pflush, BTFIXUPCALL_NORM);
        }
-        BTFIXUPSET_CALL(mmu_release_scsi_one, iommu_release_scsi_one, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(mmu_release_scsi_sgl, iommu_release_scsi_sgl, BTFIXUPCALL_NORM);
-#ifdef CONFIG_SBUS
-        BTFIXUPSET_CALL(mmu_map_dma_area, iommu_map_dma_area, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(mmu_unmap_dma_area, iommu_unmap_dma_area, BTFIXUPCALL_NORM);
-#endif
        if (viking_mxcc_present || srmmu_modtype == HyperSparc) {
                dvma_prot = __pgprot(SRMMU_CACHE | SRMMU_ET_PTE | SRMMU_PRIV);
diff --git a/arch/sparc/mm/leon_mm.c b/arch/sparc/mm/leon_mm.c
index 13c2169822a8..4c67ae6e5023 100644
--- a/arch/sparc/mm/leon_mm.c
+++ b/arch/sparc/mm/leon_mm.c
@@ -15,9 +15,23 @@
 #include <asm/leon.h>
 #include <asm/tlbflush.h>
+#include "srmmu.h"
 int leon_flush_during_switch = 1;
 int srmmu_swprobe_trace;
+static inline unsigned long leon_get_ctable_ptr(void)
+{
+        unsigned int retval;
+        __asm__ __volatile__("lda [%1] %2, %0\n\t" :
+                             "=r" (retval) :
+                             "r" (SRMMU_CTXTBL_PTR),
+                             "i" (ASI_LEON_MMUREGS));
+        return (retval & SRMMU_CTX_PMASK) << 4;
+}
 unsigned long srmmu_swprobe(unsigned long vaddr, unsigned long *paddr)
 {
@@ -33,10 +47,10 @@ unsigned long srmmu_swprobe(unsigned long vaddr, unsigned long *paddr)
        if (srmmu_swprobe_trace)
                printk(KERN_INFO "swprobe: trace on\n");
-        ctxtbl = srmmu_get_ctable_ptr();
+        ctxtbl = leon_get_ctable_ptr();
        if (!(ctxtbl)) {
                if (srmmu_swprobe_trace)
-                        printk(KERN_INFO "swprobe: srmmu_get_ctable_ptr returned 0=>0\n");
+                        printk(KERN_INFO "swprobe: leon_get_ctable_ptr returned 0=>0\n");
                return 0;
        }
        if (!_pfn_valid(PFN(ctxtbl))) {
@@ -258,3 +272,80 @@ void leon_switch_mm(void)
        if (leon_flush_during_switch)
                leon_flush_cache_all();
 }
+static void leon_flush_cache_mm(struct mm_struct *mm)
+{
+        leon_flush_cache_all();
+}
+static void leon_flush_cache_page(struct vm_area_struct *vma, unsigned long page)
+{
+        leon_flush_pcache_all(vma, page);
+}
+static void leon_flush_cache_range(struct vm_area_struct *vma,
+                                   unsigned long start,
+                                   unsigned long end)
+{
+        leon_flush_cache_all();
+}
+static void leon_flush_tlb_mm(struct mm_struct *mm)
+{
+        leon_flush_tlb_all();
+}
+static void leon_flush_tlb_page(struct vm_area_struct *vma,
+                                unsigned long page)
+{
+        leon_flush_tlb_all();
+}
+static void leon_flush_tlb_range(struct vm_area_struct *vma,
+                                 unsigned long start,
+                                 unsigned long end)
+{
+        leon_flush_tlb_all();
+}
+static void leon_flush_page_to_ram(unsigned long page)
+{
+        leon_flush_cache_all();
+}
+static void leon_flush_sig_insns(struct mm_struct *mm, unsigned long page)
+{
+        leon_flush_cache_all();
+}
+static void leon_flush_page_for_dma(unsigned long page)
+{
+        leon_flush_dcache_all();
+}
+void __init poke_leonsparc(void)
+{
+}
+static const struct sparc32_cachetlb_ops leon_ops = {
+        .cache_all      = leon_flush_cache_all,
+        .cache_mm       = leon_flush_cache_mm,
+        .cache_page     = leon_flush_cache_page,
+        .cache_range    = leon_flush_cache_range,
+        .tlb_all        = leon_flush_tlb_all,
+        .tlb_mm         = leon_flush_tlb_mm,
+        .tlb_page       = leon_flush_tlb_page,
+        .tlb_range      = leon_flush_tlb_range,
+        .page_to_ram    = leon_flush_page_to_ram,
+        .sig_insns      = leon_flush_sig_insns,
+        .page_for_dma   = leon_flush_page_for_dma,
+};
+void __init init_leon(void)
+{
+        srmmu_name = "LEON";
+        sparc32_cachetlb_ops = &leon_ops;
+        poke_srmmu = poke_leonsparc;
+        leon_flush_during_switch = leon_flush_needed();
+}
diff --git a/arch/sparc/mm/loadmmu.c b/arch/sparc/mm/loadmmu.c
deleted file mode 100644
index c5bf2a6c3858..000000000000
--- a/arch/sparc/mm/loadmmu.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * loadmmu.c:  This code loads up all the mm function pointers once the
- *             machine type has been determined.  It also sets the static
- *             mmu values such as PAGE_NONE, etc.
- *
- * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
- * Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
- */
-#include <linux/kernel.h>
-#include <linux/mm.h>
-#include <linux/init.h>
-#include <asm/page.h>
-#include <asm/pgtable.h>
-#include <asm/mmu_context.h>
-#include <asm/oplib.h>
-struct ctx_list *ctx_list_pool;
-struct ctx_list ctx_free;
-struct ctx_list ctx_used;
-extern void ld_mmu_sun4c(void);
-extern void ld_mmu_srmmu(void);
-void __init load_mmu(void)
-{
-        switch(sparc_cpu_model) {
-        case sun4c:
-        case sun4:
-                ld_mmu_sun4c();
-                break;
-        case sun4m:
-        case sun4d:
-        case sparc_leon:
-                ld_mmu_srmmu();
-                break;
-        default:
-                prom_printf("load_mmu: %d unsupported\n", (int)sparc_cpu_model);
-                prom_halt();
-        }
-        btfixup();
-}
diff --git a/arch/sparc/mm/nosun4c.c b/arch/sparc/mm/nosun4c.c
deleted file mode 100644
index 4e62c27147c4..000000000000
--- a/arch/sparc/mm/nosun4c.c
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * nosun4c.c: This file is a bunch of dummies for SMP compiles, 
- *         so that it does not need sun4c and avoid ifdefs.
- *
- * Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
- */
-#include <linux/kernel.h>
-#include <linux/mm.h>
-#include <linux/init.h>
-#include <asm/pgtable.h>
-static char shouldnothappen[] __initdata = "32bit SMP kernel only supports sun4m and sun4d\n";
-/* Dummies */
-struct sun4c_mmu_ring {
-        unsigned long xxx1[3];
-        unsigned char xxx2[2];
-        int xxx3;
-};
-struct sun4c_mmu_ring sun4c_kernel_ring;
-struct sun4c_mmu_ring sun4c_kfree_ring;
-unsigned long sun4c_kernel_faults;
-unsigned long *sun4c_memerr_reg;
-static void __init should_not_happen(void)
-{
-        prom_printf(shouldnothappen);
-        prom_halt();
-}
-unsigned long __init sun4c_paging_init(unsigned long start_mem, unsigned long end_mem)
-{
-        should_not_happen();
-        return 0;
-}
-void __init ld_mmu_sun4c(void)
-{
-        should_not_happen();
-}
-void sun4c_mapioaddr(unsigned long physaddr, unsigned long virt_addr, int bus_type, int rdonly)
-{
-}
-void sun4c_unmapioaddr(unsigned long virt_addr)
-{
-}
-void sun4c_complete_all_stores(void)
-{
-}
-pte_t *sun4c_pte_offset(pmd_t * dir, unsigned long address)
-{
-        return NULL;
-}
-pte_t *sun4c_pte_offset_kernel(pmd_t *dir, unsigned long address)
-{
-        return NULL;
-}
-void sun4c_update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
-{
-}
-void __init sun4c_probe_vac(void)
-{
-        should_not_happen();
-}
-void __init sun4c_probe_memerr_reg(void)
-{
-        should_not_happen();
-}
diff --git a/arch/sparc/mm/srmmu.c b/arch/sparc/mm/srmmu.c
index cbef74e793b8..8e97e0305b01 100644
--- a/arch/sparc/mm/srmmu.c
+++ b/arch/sparc/mm/srmmu.c
@@ -48,39 +48,37 @@
 #include <asm/turbosparc.h>
 #include <asm/leon.h>
-#include <asm/btfixup.h>
+#include "srmmu.h"
 enum mbus_module srmmu_modtype;
 static unsigned int hwbug_bitmask;
 int vac_cache_size;
 int vac_line_size;
+struct ctx_list *ctx_list_pool;
+struct ctx_list ctx_free;
+struct ctx_list ctx_used;
 extern struct resource sparc_iomap;
 extern unsigned long last_valid_pfn;
-extern unsigned long page_kernel;
 static pgd_t *srmmu_swapper_pg_dir;
+const struct sparc32_cachetlb_ops *sparc32_cachetlb_ops;
 #ifdef CONFIG_SMP
+const struct sparc32_cachetlb_ops *local_ops;
 #define FLUSH_BEGIN(mm)
 #define FLUSH_END
 #else
-#define FLUSH_BEGIN(mm) if((mm)->context != NO_CONTEXT) {
+#define FLUSH_BEGIN(mm) if ((mm)->context != NO_CONTEXT) {
 #define FLUSH_END       }
 #endif
-BTFIXUPDEF_CALL(void, flush_page_for_dma, unsigned long)
-#define flush_page_for_dma(page) BTFIXUP_CALL(flush_page_for_dma)(page)
 int flush_page_for_dma_global = 1;
-#ifdef CONFIG_SMP
-BTFIXUPDEF_CALL(void, local_flush_page_for_dma, unsigned long)
-#define local_flush_page_for_dma(page) BTFIXUP_CALL(local_flush_page_for_dma)(page)
-#endif
 char *srmmu_name;
 ctxd_t *srmmu_ctx_table_phys;
@@ -91,28 +89,6 @@ static DEFINE_SPINLOCK(srmmu_context_spinlock);
 static int is_hypersparc;
-/*
- * In general all page table modifications should use the V8 atomic
- * swap instruction.  This insures the mmu and the cpu are in sync
- * with respect to ref/mod bits in the page tables.
- */
-static inline unsigned long srmmu_swap(unsigned long *addr, unsigned long value)
-{
-        __asm__ __volatile__("swap [%2], %0" : "=&r" (value) : "0" (value), "r" (addr));
-        return value;
-}
-static inline void srmmu_set_pte(pte_t *ptep, pte_t pteval)
-{
-        srmmu_swap((unsigned long *)ptep, pte_val(pteval));
-}
-/* The very generic SRMMU page table operations. */
-static inline int srmmu_device_memory(unsigned long x)
-{
-        return ((x & 0xF0000000) != 0);
-}
 static int srmmu_cache_pagetables;
 /* these will be initialized in srmmu_nocache_calcsize() */
@@ -129,145 +105,39 @@ void *srmmu_nocache_pool;
 void *srmmu_nocache_bitmap;
 static struct bit_map srmmu_nocache_map;
-static unsigned long srmmu_pte_pfn(pte_t pte)
-{
-        if (srmmu_device_memory(pte_val(pte))) {
-                /* Just return something that will cause
-                 * pfn_valid() to return false.  This makes
-                 * copy_one_pte() to just directly copy to
-                 * PTE over.
-                 */
-                return ~0UL;
-        }
-        return (pte_val(pte) & SRMMU_PTE_PMASK) >> (PAGE_SHIFT-4);
-}
-static struct page *srmmu_pmd_page(pmd_t pmd)
-{
-        if (srmmu_device_memory(pmd_val(pmd)))
-                BUG();
-        return pfn_to_page((pmd_val(pmd) & SRMMU_PTD_PMASK) >> (PAGE_SHIFT-4));
-}
-static inline unsigned long srmmu_pgd_page(pgd_t pgd)
-{ return srmmu_device_memory(pgd_val(pgd))?~0:(unsigned long)__nocache_va((pgd_val(pgd) & SRMMU_PTD_PMASK) << 4); }
-static inline int srmmu_pte_none(pte_t pte)
-{ return !(pte_val(pte) & 0xFFFFFFF); }
-static inline int srmmu_pte_present(pte_t pte)
-{ return ((pte_val(pte) & SRMMU_ET_MASK) == SRMMU_ET_PTE); }
-static inline void srmmu_pte_clear(pte_t *ptep)
-{ srmmu_set_pte(ptep, __pte(0)); }
 static inline int srmmu_pmd_none(pmd_t pmd)
 { return !(pmd_val(pmd) & 0xFFFFFFF); }
-static inline int srmmu_pmd_bad(pmd_t pmd)
-{ return (pmd_val(pmd) & SRMMU_ET_MASK) != SRMMU_ET_PTD; }
-static inline int srmmu_pmd_present(pmd_t pmd)
-{ return ((pmd_val(pmd) & SRMMU_ET_MASK) == SRMMU_ET_PTD); }
-static inline void srmmu_pmd_clear(pmd_t *pmdp) {
-        int i;
-        for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++)
-                srmmu_set_pte((pte_t *)&pmdp->pmdv[i], __pte(0));
-}
-static inline int srmmu_pgd_none(pgd_t pgd)          
-{ return !(pgd_val(pgd) & 0xFFFFFFF); }
-static inline int srmmu_pgd_bad(pgd_t pgd)
-{ return (pgd_val(pgd) & SRMMU_ET_MASK) != SRMMU_ET_PTD; }
-static inline int srmmu_pgd_present(pgd_t pgd)
-{ return ((pgd_val(pgd) & SRMMU_ET_MASK) == SRMMU_ET_PTD); }
-static inline void srmmu_pgd_clear(pgd_t * pgdp)
-{ srmmu_set_pte((pte_t *)pgdp, __pte(0)); }
-static inline pte_t srmmu_pte_wrprotect(pte_t pte)
-{ return __pte(pte_val(pte) & ~SRMMU_WRITE);}
-static inline pte_t srmmu_pte_mkclean(pte_t pte)
-{ return __pte(pte_val(pte) & ~SRMMU_DIRTY);}
-static inline pte_t srmmu_pte_mkold(pte_t pte)
-{ return __pte(pte_val(pte) & ~SRMMU_REF);}
-static inline pte_t srmmu_pte_mkwrite(pte_t pte)
-{ return __pte(pte_val(pte) | SRMMU_WRITE);}
-static inline pte_t srmmu_pte_mkdirty(pte_t pte)
-{ return __pte(pte_val(pte) | SRMMU_DIRTY);}
-static inline pte_t srmmu_pte_mkyoung(pte_t pte)
-{ return __pte(pte_val(pte) | SRMMU_REF);}
-/*
- * Conversion functions: convert a page and protection to a page entry,
- * and a page entry and page directory to the page they refer to.
- */
-static pte_t srmmu_mk_pte(struct page *page, pgprot_t pgprot)
-{ return __pte((page_to_pfn(page) << (PAGE_SHIFT-4)) | pgprot_val(pgprot)); }
-static pte_t srmmu_mk_pte_phys(unsigned long page, pgprot_t pgprot)
-{ return __pte(((page) >> 4) | pgprot_val(pgprot)); }
-static pte_t srmmu_mk_pte_io(unsigned long page, pgprot_t pgprot, int space)
-{ return __pte(((page) >> 4) | (space << 28) | pgprot_val(pgprot)); }
 /* XXX should we hyper_flush_whole_icache here - Anton */
 static inline void srmmu_ctxd_set(ctxd_t *ctxp, pgd_t *pgdp)
-{ srmmu_set_pte((pte_t *)ctxp, (SRMMU_ET_PTD | (__nocache_pa((unsigned long) pgdp) >> 4))); }
+{ set_pte((pte_t *)ctxp, (SRMMU_ET_PTD | (__nocache_pa((unsigned long) pgdp) >> 4))); }
-static inline void srmmu_pgd_set(pgd_t * pgdp, pmd_t * pmdp)
+void pmd_set(pmd_t *pmdp, pte_t *ptep)
-{ srmmu_set_pte((pte_t *)pgdp, (SRMMU_ET_PTD | (__nocache_pa((unsigned long) pmdp) >> 4))); }
-static void srmmu_pmd_set(pmd_t *pmdp, pte_t *ptep)
 {
        unsigned long ptp;      /* Physical address, shifted right by 4 */
        int i;
        ptp = __nocache_pa((unsigned long) ptep) >> 4;
        for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++) {
-                srmmu_set_pte((pte_t *)&pmdp->pmdv[i], SRMMU_ET_PTD | ptp);
+                set_pte((pte_t *)&pmdp->pmdv[i], SRMMU_ET_PTD | ptp);
                ptp += (SRMMU_REAL_PTRS_PER_PTE*sizeof(pte_t) >> 4);
        }
 }
-static void srmmu_pmd_populate(pmd_t *pmdp, struct page *ptep)
+void pmd_populate(struct mm_struct *mm, pmd_t *pmdp, struct page *ptep)
 {
        unsigned long ptp;      /* Physical address, shifted right by 4 */
        int i;
        ptp = page_to_pfn(ptep) << (PAGE_SHIFT-4);      /* watch for overflow */
        for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++) {
-                srmmu_set_pte((pte_t *)&pmdp->pmdv[i], SRMMU_ET_PTD | ptp);
+                set_pte((pte_t *)&pmdp->pmdv[i], SRMMU_ET_PTD | ptp);
                ptp += (SRMMU_REAL_PTRS_PER_PTE*sizeof(pte_t) >> 4);
        }
 }
-static inline pte_t srmmu_pte_modify(pte_t pte, pgprot_t newprot)
-{ return __pte((pte_val(pte) & SRMMU_CHG_MASK) | pgprot_val(newprot)); }
-/* to find an entry in a top-level page table... */
-static inline pgd_t *srmmu_pgd_offset(struct mm_struct * mm, unsigned long address)
-{ return mm->pgd + (address >> SRMMU_PGDIR_SHIFT); }
-/* Find an entry in the second-level page table.. */
-static inline pmd_t *srmmu_pmd_offset(pgd_t * dir, unsigned long address)
-{
-        return (pmd_t *) srmmu_pgd_page(*dir) +
-            ((address >> PMD_SHIFT) & (PTRS_PER_PMD - 1));
-}
 /* Find an entry in the third-level page table.. */ 
-static inline pte_t *srmmu_pte_offset(pmd_t * dir, unsigned long address)
+pte_t *pte_offset_kernel(pmd_t * dir, unsigned long address)
 {
        void *pte;
@@ -276,23 +146,6 @@ static inline pte_t *srmmu_pte_offset(pmd_t * dir, unsigned long address)
            ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1));
 }
-static unsigned long srmmu_swp_type(swp_entry_t entry)
-{
-        return (entry.val >> SRMMU_SWP_TYPE_SHIFT) & SRMMU_SWP_TYPE_MASK;
-}
-static unsigned long srmmu_swp_offset(swp_entry_t entry)
-{
-        return (entry.val >> SRMMU_SWP_OFF_SHIFT) & SRMMU_SWP_OFF_MASK;
-}
-static swp_entry_t srmmu_swp_entry(unsigned long type, unsigned long offset)
-{
-        return (swp_entry_t) {
-                  (type & SRMMU_SWP_TYPE_MASK) << SRMMU_SWP_TYPE_SHIFT
-                | (offset & SRMMU_SWP_OFF_MASK) << SRMMU_SWP_OFF_SHIFT };
-}
 /*
 * size: bytes to allocate in the nocache area.
 * align: bytes, number to align at.
@@ -325,7 +178,7 @@ static unsigned long __srmmu_get_nocache(int size, int align)
        return (SRMMU_NOCACHE_VADDR + (offset << SRMMU_NOCACHE_BITMAP_SHIFT));
 }
-static unsigned long srmmu_get_nocache(int size, int align)
+unsigned long srmmu_get_nocache(int size, int align)
 {
        unsigned long tmp;
@@ -337,7 +190,7 @@ static unsigned long srmmu_get_nocache(int size, int align)
        return tmp;
 }
-static void srmmu_free_nocache(unsigned long vaddr, int size)
+void srmmu_free_nocache(unsigned long vaddr, int size)
 {
        int offset;
@@ -429,15 +282,15 @@ static void __init srmmu_nocache_init(void)
        while (vaddr < srmmu_nocache_end) {
                pgd = pgd_offset_k(vaddr);
-                pmd = srmmu_pmd_offset(__nocache_fix(pgd), vaddr);
+                pmd = pmd_offset(__nocache_fix(pgd), vaddr);
-                pte = srmmu_pte_offset(__nocache_fix(pmd), vaddr);
+                pte = pte_offset_kernel(__nocache_fix(pmd), vaddr);
                pteval = ((paddr >> 4) | SRMMU_ET_PTE | SRMMU_PRIV);
                if (srmmu_cache_pagetables)
                        pteval |= SRMMU_CACHE;
-                srmmu_set_pte(__nocache_fix(pte), __pte(pteval));
+                set_pte(__nocache_fix(pte), __pte(pteval));
                vaddr += PAGE_SIZE;
                paddr += PAGE_SIZE;
@@ -447,7 +300,7 @@ static void __init srmmu_nocache_init(void)
        flush_tlb_all();
 }
-static inline pgd_t *srmmu_get_pgd_fast(void)
+pgd_t *get_pgd_fast(void)
 {
        pgd_t *pgd = NULL;
@@ -462,21 +315,6 @@ static inline pgd_t *srmmu_get_pgd_fast(void)
        return pgd;
 }
-static void srmmu_free_pgd_fast(pgd_t *pgd)
-{
-        srmmu_free_nocache((unsigned long)pgd, SRMMU_PGD_TABLE_SIZE);
-}
-static pmd_t *srmmu_pmd_alloc_one(struct mm_struct *mm, unsigned long address)
-{
-        return (pmd_t *)srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
-}
-static void srmmu_pmd_free(pmd_t * pmd)
-{
-        srmmu_free_nocache((unsigned long)pmd, SRMMU_PMD_TABLE_SIZE);
-}
 /*
 * Hardware needs alignment to 256 only, but we align to whole page size
 * to reduce fragmentation problems due to the buddy principle.
@@ -485,31 +323,19 @@ static void srmmu_pmd_free(pmd_t * pmd)
 * Alignments up to the page size are the same for physical and virtual
 * addresses of the nocache area.
 */
-static pte_t *
+pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long address)
-srmmu_pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address)
-{
-        return (pte_t *)srmmu_get_nocache(PTE_SIZE, PTE_SIZE);
-}
-static pgtable_t
-srmmu_pte_alloc_one(struct mm_struct *mm, unsigned long address)
 {
        unsigned long pte;
        struct page *page;
-        if ((pte = (unsigned long)srmmu_pte_alloc_one_kernel(mm, address)) == 0)
+        if ((pte = (unsigned long)pte_alloc_one_kernel(mm, address)) == 0)
                return NULL;
        page = pfn_to_page( __nocache_pa(pte) >> PAGE_SHIFT );
        pgtable_page_ctor(page);
        return page;
 }
-static void srmmu_free_pte_fast(pte_t *pte)
+void pte_free(struct mm_struct *mm, pgtable_t pte)
-{
-        srmmu_free_nocache((unsigned long)pte, PTE_SIZE);
-}
-static void srmmu_pte_free(pgtable_t pte)
 {
        unsigned long p;
@@ -560,8 +386,8 @@ static inline void free_context(int context)
 }
-static void srmmu_switch_mm(struct mm_struct *old_mm, struct mm_struct *mm,
+void switch_mm(struct mm_struct *old_mm, struct mm_struct *mm,
-    struct task_struct *tsk, int cpu)
+               struct task_struct *tsk)
 {
        if(mm->context == NO_CONTEXT) {
                spin_lock(&srmmu_context_spinlock);
@@ -590,8 +416,8 @@ static inline void srmmu_mapioaddr(unsigned long physaddr,
        physaddr &= PAGE_MASK;
        pgdp = pgd_offset_k(virt_addr);
-        pmdp = srmmu_pmd_offset(pgdp, virt_addr);
+        pmdp = pmd_offset(pgdp, virt_addr);
-        ptep = srmmu_pte_offset(pmdp, virt_addr);
+        ptep = pte_offset_kernel(pmdp, virt_addr);
        tmp = (physaddr >> 4) | SRMMU_ET_PTE;
        /*
@@ -602,11 +428,11 @@ static inline void srmmu_mapioaddr(unsigned long physaddr,
        tmp |= (bus_type << 28);
        tmp |= SRMMU_PRIV;
        __flush_page_to_ram(virt_addr);
-        srmmu_set_pte(ptep, __pte(tmp));
+        set_pte(ptep, __pte(tmp));
 }
-static void srmmu_mapiorange(unsigned int bus, unsigned long xpa,
+void srmmu_mapiorange(unsigned int bus, unsigned long xpa,
-    unsigned long xva, unsigned int len)
+                      unsigned long xva, unsigned int len)
 {
        while (len != 0) {
                len -= PAGE_SIZE;
@@ -624,14 +450,14 @@ static inline void srmmu_unmapioaddr(unsigned long virt_addr)
        pte_t *ptep;
        pgdp = pgd_offset_k(virt_addr);
-        pmdp = srmmu_pmd_offset(pgdp, virt_addr);
+        pmdp = pmd_offset(pgdp, virt_addr);
-        ptep = srmmu_pte_offset(pmdp, virt_addr);
+        ptep = pte_offset_kernel(pmdp, virt_addr);
        /* No need to flush uncacheable page. */
-        srmmu_pte_clear(ptep);
+        __pte_clear(ptep);
 }
-static void srmmu_unmapiorange(unsigned long virt_addr, unsigned int len)
+void srmmu_unmapiorange(unsigned long virt_addr, unsigned int len)
 {
        while (len != 0) {
                len -= PAGE_SIZE;
@@ -647,10 +473,9 @@ static void srmmu_unmapiorange(unsigned long virt_addr, unsigned int len)
 * pool.  As a side effect we are putting a little too much pressure
 * on the gfp() subsystem.  This setup also makes the logic of the
 * iommu mapping code a lot easier as we can transparently handle
- * mappings on the kernel stack without any special code as we did
+ * mappings on the kernel stack without any special code.
- * need on the sun4c.
 */
-static struct thread_info *srmmu_alloc_thread_info_node(int node)
+struct thread_info *alloc_thread_info_node(struct task_struct *tsk, int node)
 {
        struct thread_info *ret;
@@ -664,7 +489,7 @@ static struct thread_info *srmmu_alloc_thread_info_node(int node)
        return ret;
 }
-static void srmmu_free_thread_info(struct thread_info *ti)
+void free_thread_info(struct thread_info *ti)
 {
        free_pages((unsigned long)ti, THREAD_INFO_ORDER);
 }
@@ -683,38 +508,6 @@ extern void tsunami_flush_tlb_range(struct vm_area_struct *vma, unsigned long st
 extern void tsunami_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
 extern void tsunami_setup_blockops(void);
-/*
- * Workaround, until we find what's going on with Swift. When low on memory,
- * it sometimes loops in fault/handle_mm_fault incl. flush_tlb_page to find
- * out it is already in page tables/ fault again on the same instruction.
- * I really don't understand it, have checked it and contexts
- * are right, flush_tlb_all is done as well, and it faults again...
- * Strange. -jj
- *
- * The following code is a deadwood that may be necessary when
- * we start to make precise page flushes again. --zaitcev
- */
-static void swift_update_mmu_cache(struct vm_area_struct * vma, unsigned long address, pte_t *ptep)
-{
-#if 0
-        static unsigned long last;
-        unsigned int val;
-        /* unsigned int n; */
-        if (address == last) {
-                val = srmmu_hwprobe(address);
-                if (val != 0 && pte_val(*ptep) != val) {
-                        printk("swift_update_mmu_cache: "
-                            "addr %lx put %08x probed %08x from %p\n",
-                            address, pte_val(*ptep), val,
-                            __builtin_return_address(0));
-                        srmmu_flush_whole_tlb();
-                }
-        }
-        last = address;
-#endif
-}
 /* swift.S */
 extern void swift_flush_cache_all(void);
 extern void swift_flush_cache_mm(struct mm_struct *mm);
@@ -767,244 +560,6 @@ void swift_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
 * with respect to cache coherency.
 */
-/* Cypress flushes. */
-static void cypress_flush_cache_all(void)
-{
-        volatile unsigned long cypress_sucks;
-        unsigned long faddr, tagval;
-        flush_user_windows();
-        for(faddr = 0; faddr < 0x10000; faddr += 0x20) {
-                __asm__ __volatile__("lda [%1 + %2] %3, %0\n\t" :
-                                     "=r" (tagval) :
-                                     "r" (faddr), "r" (0x40000),
-                                     "i" (ASI_M_DATAC_TAG));
-                /* If modified and valid, kick it. */
-                if((tagval & 0x60) == 0x60)
-                        cypress_sucks = *(unsigned long *)(0xf0020000 + faddr);
-        }
-}
-static void cypress_flush_cache_mm(struct mm_struct *mm)
-{
-        register unsigned long a, b, c, d, e, f, g;
-        unsigned long flags, faddr;
-        int octx;
-        FLUSH_BEGIN(mm)
-        flush_user_windows();
-        local_irq_save(flags);
-        octx = srmmu_get_context();
-        srmmu_set_context(mm->context);
-        a = 0x20; b = 0x40; c = 0x60;
-        d = 0x80; e = 0xa0; f = 0xc0; g = 0xe0;
-        faddr = (0x10000 - 0x100);
-        goto inside;
-        do {
-                faddr -= 0x100;
-        inside:
-                __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
-                                     "sta %%g0, [%0 + %2] %1\n\t"
-                                     "sta %%g0, [%0 + %3] %1\n\t"
-                                     "sta %%g0, [%0 + %4] %1\n\t"
-                                     "sta %%g0, [%0 + %5] %1\n\t"
-                                     "sta %%g0, [%0 + %6] %1\n\t"
-                                     "sta %%g0, [%0 + %7] %1\n\t"
-                                     "sta %%g0, [%0 + %8] %1\n\t" : :
-                                     "r" (faddr), "i" (ASI_M_FLUSH_CTX),
-                                     "r" (a), "r" (b), "r" (c), "r" (d),
-                                     "r" (e), "r" (f), "r" (g));
-        } while(faddr);
-        srmmu_set_context(octx);
-        local_irq_restore(flags);
-        FLUSH_END
-}
-static void cypress_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
-{
-        struct mm_struct *mm = vma->vm_mm;
-        register unsigned long a, b, c, d, e, f, g;
-        unsigned long flags, faddr;
-        int octx;
-        FLUSH_BEGIN(mm)
-        flush_user_windows();
-        local_irq_save(flags);
-        octx = srmmu_get_context();
-        srmmu_set_context(mm->context);
-        a = 0x20; b = 0x40; c = 0x60;
-        d = 0x80; e = 0xa0; f = 0xc0; g = 0xe0;
-        start &= SRMMU_REAL_PMD_MASK;
-        while(start < end) {
-                faddr = (start + (0x10000 - 0x100));
-                goto inside;
-                do {
-                        faddr -= 0x100;
-                inside:
-                        __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
-                                             "sta %%g0, [%0 + %2] %1\n\t"
-                                             "sta %%g0, [%0 + %3] %1\n\t"
-                                             "sta %%g0, [%0 + %4] %1\n\t"
-                                             "sta %%g0, [%0 + %5] %1\n\t"
-                                             "sta %%g0, [%0 + %6] %1\n\t"
-                                             "sta %%g0, [%0 + %7] %1\n\t"
-                                             "sta %%g0, [%0 + %8] %1\n\t" : :
-                                             "r" (faddr),
-                                             "i" (ASI_M_FLUSH_SEG),
-                                             "r" (a), "r" (b), "r" (c), "r" (d),
-                                             "r" (e), "r" (f), "r" (g));
-                } while (faddr != start);
-                start += SRMMU_REAL_PMD_SIZE;
-        }
-        srmmu_set_context(octx);
-        local_irq_restore(flags);
-        FLUSH_END
-}
-static void cypress_flush_cache_page(struct vm_area_struct *vma, unsigned long page)
-{
-        register unsigned long a, b, c, d, e, f, g;
-        struct mm_struct *mm = vma->vm_mm;
-        unsigned long flags, line;
-        int octx;
-        FLUSH_BEGIN(mm)
-        flush_user_windows();
-        local_irq_save(flags);
-        octx = srmmu_get_context();
-        srmmu_set_context(mm->context);
-        a = 0x20; b = 0x40; c = 0x60;
-        d = 0x80; e = 0xa0; f = 0xc0; g = 0xe0;
-        page &= PAGE_MASK;
-        line = (page + PAGE_SIZE) - 0x100;
-        goto inside;
-        do {
-                line -= 0x100;
-        inside:
-                        __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
-                                             "sta %%g0, [%0 + %2] %1\n\t"
-                                             "sta %%g0, [%0 + %3] %1\n\t"
-                                             "sta %%g0, [%0 + %4] %1\n\t"
-                                             "sta %%g0, [%0 + %5] %1\n\t"
-                                             "sta %%g0, [%0 + %6] %1\n\t"
-                                             "sta %%g0, [%0 + %7] %1\n\t"
-                                             "sta %%g0, [%0 + %8] %1\n\t" : :
-                                             "r" (line),
-                                             "i" (ASI_M_FLUSH_PAGE),
-                                             "r" (a), "r" (b), "r" (c), "r" (d),
-                                             "r" (e), "r" (f), "r" (g));
-        } while(line != page);
-        srmmu_set_context(octx);
-        local_irq_restore(flags);
-        FLUSH_END
-}
-/* Cypress is copy-back, at least that is how we configure it. */
-static void cypress_flush_page_to_ram(unsigned long page)
-{
-        register unsigned long a, b, c, d, e, f, g;
-        unsigned long line;
-        a = 0x20; b = 0x40; c = 0x60; d = 0x80; e = 0xa0; f = 0xc0; g = 0xe0;
-        page &= PAGE_MASK;
-        line = (page + PAGE_SIZE) - 0x100;
-        goto inside;
-        do {
-                line -= 0x100;
-        inside:
-                __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
-                                     "sta %%g0, [%0 + %2] %1\n\t"
-                                     "sta %%g0, [%0 + %3] %1\n\t"
-                                     "sta %%g0, [%0 + %4] %1\n\t"
-                                     "sta %%g0, [%0 + %5] %1\n\t"
-                                     "sta %%g0, [%0 + %6] %1\n\t"
-                                     "sta %%g0, [%0 + %7] %1\n\t"
-                                     "sta %%g0, [%0 + %8] %1\n\t" : :
-                                     "r" (line),
-                                     "i" (ASI_M_FLUSH_PAGE),
-                                     "r" (a), "r" (b), "r" (c), "r" (d),
-                                     "r" (e), "r" (f), "r" (g));
-        } while(line != page);
-}
-/* Cypress is also IO cache coherent. */
-static void cypress_flush_page_for_dma(unsigned long page)
-{
-}
-/* Cypress has unified L2 VIPT, from which both instructions and data
- * are stored.  It does not have an onboard icache of any sort, therefore
- * no flush is necessary.
- */
-static void cypress_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr)
-{
-}
-static void cypress_flush_tlb_all(void)
-{
-        srmmu_flush_whole_tlb();
-}
-static void cypress_flush_tlb_mm(struct mm_struct *mm)
-{
-        FLUSH_BEGIN(mm)
-        __asm__ __volatile__(
-        "lda    [%0] %3, %%g5\n\t"
-        "sta    %2, [%0] %3\n\t"
-        "sta    %%g0, [%1] %4\n\t"
-        "sta    %%g5, [%0] %3\n"
-        : /* no outputs */
-        : "r" (SRMMU_CTX_REG), "r" (0x300), "r" (mm->context),
-          "i" (ASI_M_MMUREGS), "i" (ASI_M_FLUSH_PROBE)
-        : "g5");
-        FLUSH_END
-}
-static void cypress_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
-{
-        struct mm_struct *mm = vma->vm_mm;
-        unsigned long size;
-        FLUSH_BEGIN(mm)
-        start &= SRMMU_PGDIR_MASK;
-        size = SRMMU_PGDIR_ALIGN(end) - start;
-        __asm__ __volatile__(
-                "lda    [%0] %5, %%g5\n\t"
-                "sta    %1, [%0] %5\n"
-                "1:\n\t"
-                "subcc  %3, %4, %3\n\t"
-                "bne    1b\n\t"
-                " sta   %%g0, [%2 + %3] %6\n\t"
-                "sta    %%g5, [%0] %5\n"
-        : /* no outputs */
-        : "r" (SRMMU_CTX_REG), "r" (mm->context), "r" (start | 0x200),
-          "r" (size), "r" (SRMMU_PGDIR_SIZE), "i" (ASI_M_MMUREGS),
-          "i" (ASI_M_FLUSH_PROBE)
-        : "g5", "cc");
-        FLUSH_END
-}
-static void cypress_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
-{
-        struct mm_struct *mm = vma->vm_mm;
-        FLUSH_BEGIN(mm)
-        __asm__ __volatile__(
-        "lda    [%0] %3, %%g5\n\t"
-        "sta    %1, [%0] %3\n\t"
-        "sta    %%g0, [%2] %4\n\t"
-        "sta    %%g5, [%0] %3\n"
-        : /* no outputs */
-        : "r" (SRMMU_CTX_REG), "r" (mm->context), "r" (page & PAGE_MASK),
-          "i" (ASI_M_MMUREGS), "i" (ASI_M_FLUSH_PROBE)
-        : "g5");
-        FLUSH_END
-}
 /* viking.S */
 extern void viking_flush_cache_all(void);
 extern void viking_flush_cache_mm(struct mm_struct *mm);
@@ -1065,21 +620,21 @@ static void __init srmmu_early_allocate_ptable_skeleton(unsigned long start,
        while(start < end) {
                pgdp = pgd_offset_k(start);
-                if(srmmu_pgd_none(*(pgd_t *)__nocache_fix(pgdp))) {
+                if (pgd_none(*(pgd_t *)__nocache_fix(pgdp))) {
                        pmdp = (pmd_t *) __srmmu_get_nocache(
                            SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
                        if (pmdp == NULL)
                                early_pgtable_allocfail("pmd");
                        memset(__nocache_fix(pmdp), 0, SRMMU_PMD_TABLE_SIZE);
-                        srmmu_pgd_set(__nocache_fix(pgdp), pmdp);
+                        pgd_set(__nocache_fix(pgdp), pmdp);
                }
-                pmdp = srmmu_pmd_offset(__nocache_fix(pgdp), start);
+                pmdp = pmd_offset(__nocache_fix(pgdp), start);
                if(srmmu_pmd_none(*(pmd_t *)__nocache_fix(pmdp))) {
                        ptep = (pte_t *)__srmmu_get_nocache(PTE_SIZE, PTE_SIZE);
                        if (ptep == NULL)
                                early_pgtable_allocfail("pte");
                        memset(__nocache_fix(ptep), 0, PTE_SIZE);
-                        srmmu_pmd_set(__nocache_fix(pmdp), ptep);
+                        pmd_set(__nocache_fix(pmdp), ptep);
                }
                if (start > (0xffffffffUL - PMD_SIZE))
                        break;
@@ -1096,21 +651,21 @@ static void __init srmmu_allocate_ptable_skeleton(unsigned long start,
        while(start < end) {
                pgdp = pgd_offset_k(start);
-                if(srmmu_pgd_none(*pgdp)) {
+                if (pgd_none(*pgdp)) {
                        pmdp = (pmd_t *)__srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
                        if (pmdp == NULL)
                                early_pgtable_allocfail("pmd");
                        memset(pmdp, 0, SRMMU_PMD_TABLE_SIZE);
-                        srmmu_pgd_set(pgdp, pmdp);
+                        pgd_set(pgdp, pmdp);
                }
-                pmdp = srmmu_pmd_offset(pgdp, start);
+                pmdp = pmd_offset(pgdp, start);
                if(srmmu_pmd_none(*pmdp)) {
                        ptep = (pte_t *) __srmmu_get_nocache(PTE_SIZE,
                                                             PTE_SIZE);
                        if (ptep == NULL)
                                early_pgtable_allocfail("pte");
                        memset(ptep, 0, PTE_SIZE);
-                        srmmu_pmd_set(pmdp, ptep);
+                        pmd_set(pmdp, ptep);
                }
                if (start > (0xffffffffUL - PMD_SIZE))
                        break;
@@ -1162,21 +717,21 @@ static void __init srmmu_inherit_prom_mappings(unsigned long start,
                        start += SRMMU_PGDIR_SIZE;
                        continue;
                }
-                if(srmmu_pgd_none(*(pgd_t *)__nocache_fix(pgdp))) {
+                if (pgd_none(*(pgd_t *)__nocache_fix(pgdp))) {
                        pmdp = (pmd_t *)__srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
                        if (pmdp == NULL)
                                early_pgtable_allocfail("pmd");
                        memset(__nocache_fix(pmdp), 0, SRMMU_PMD_TABLE_SIZE);
-                        srmmu_pgd_set(__nocache_fix(pgdp), pmdp);
+                        pgd_set(__nocache_fix(pgdp), pmdp);
                }
-                pmdp = srmmu_pmd_offset(__nocache_fix(pgdp), start);
+                pmdp = pmd_offset(__nocache_fix(pgdp), start);
                if(srmmu_pmd_none(*(pmd_t *)__nocache_fix(pmdp))) {
                        ptep = (pte_t *) __srmmu_get_nocache(PTE_SIZE,
                                                             PTE_SIZE);
                        if (ptep == NULL)
                                early_pgtable_allocfail("pte");
                        memset(__nocache_fix(ptep), 0, PTE_SIZE);
-                        srmmu_pmd_set(__nocache_fix(pmdp), ptep);
+                        pmd_set(__nocache_fix(pmdp), ptep);
                }
                if(what == 1) {
                        /*
@@ -1190,7 +745,7 @@ static void __init srmmu_inherit_prom_mappings(unsigned long start,
                        start += SRMMU_REAL_PMD_SIZE;
                        continue;
                }
-                ptep = srmmu_pte_offset(__nocache_fix(pmdp), start);
+                ptep = pte_offset_kernel(__nocache_fix(pmdp), start);
                *(pte_t *)__nocache_fix(ptep) = __pte(prompte);
                start += PAGE_SIZE;
        }
@@ -1231,13 +786,6 @@ static unsigned long __init map_spbank(unsigned long vbase, int sp_entry)
        return vstart;
 }
-static inline void memprobe_error(char *msg)
-{
-        prom_printf(msg);
-        prom_printf("Halting now...\n");
-        prom_halt();
-}
 static inline void map_kernel(void)
 {
        int i;
@@ -1249,8 +797,6 @@ static inline void map_kernel(void)
        for (i = 0; sp_banks[i].num_bytes != 0; i++) {
                map_spbank((unsigned long)__va(sp_banks[i].base_addr), i);
        }
-        BTFIXUPSET_SIMM13(user_ptrs_per_pgd, PAGE_OFFSET / SRMMU_PGDIR_SIZE);
 }
 /* Paging initialization on the Sparc Reference MMU. */
@@ -1312,7 +858,7 @@ void __init srmmu_paging_init(void)
        srmmu_set_ctable_ptr((unsigned long)srmmu_ctx_table_phys);
 #ifdef CONFIG_SMP
        /* Stop from hanging here... */
-        local_flush_tlb_all();
+        local_ops->tlb_all();
 #else
        flush_tlb_all();
 #endif
@@ -1326,8 +872,8 @@ void __init srmmu_paging_init(void)
        srmmu_allocate_ptable_skeleton(PKMAP_BASE, PKMAP_END);
        pgd = pgd_offset_k(PKMAP_BASE);
-        pmd = srmmu_pmd_offset(pgd, PKMAP_BASE);
+        pmd = pmd_offset(pgd, PKMAP_BASE);
-        pte = srmmu_pte_offset(pmd, PKMAP_BASE);
+        pte = pte_offset_kernel(pmd, PKMAP_BASE);
        pkmap_page_table = pte;
        flush_cache_all();
@@ -1359,7 +905,7 @@ void __init srmmu_paging_init(void)
        }
 }
-static void srmmu_mmu_info(struct seq_file *m)
+void mmu_info(struct seq_file *m)
 {
        seq_printf(m, 
                   "MMU type\t: %s\n"
@@ -1372,11 +918,7 @@ static void srmmu_mmu_info(struct seq_file *m)
                   srmmu_nocache_map.used << SRMMU_NOCACHE_BITMAP_SHIFT);
 }
-static void srmmu_update_mmu_cache(struct vm_area_struct * vma, unsigned long address, pte_t pte)
+void destroy_context(struct mm_struct *mm)
-{
-}
-static void srmmu_destroy_context(struct mm_struct *mm)
 {
        if(mm->context != NO_CONTEXT) {
@@ -1474,6 +1016,20 @@ static void __cpuinit poke_hypersparc(void)
        clear = srmmu_get_fstatus();
 }
+static const struct sparc32_cachetlb_ops hypersparc_ops = {
+        .cache_all      = hypersparc_flush_cache_all,
+        .cache_mm       = hypersparc_flush_cache_mm,
+        .cache_page     = hypersparc_flush_cache_page,
+        .cache_range    = hypersparc_flush_cache_range,
+        .tlb_all        = hypersparc_flush_tlb_all,
+        .tlb_mm         = hypersparc_flush_tlb_mm,
+        .tlb_page       = hypersparc_flush_tlb_page,
+        .tlb_range      = hypersparc_flush_tlb_range,
+        .page_to_ram    = hypersparc_flush_page_to_ram,
+        .sig_insns      = hypersparc_flush_sig_insns,
+        .page_for_dma   = hypersparc_flush_page_for_dma,
+};
 static void __init init_hypersparc(void)
 {
        srmmu_name = "ROSS HyperSparc";
@@ -1482,118 +1038,13 @@ static void __init init_hypersparc(void)
        init_vac_layout();
        is_hypersparc = 1;
+        sparc32_cachetlb_ops = &hypersparc_ops;
-        BTFIXUPSET_CALL(pte_clear, srmmu_pte_clear, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(pmd_clear, srmmu_pmd_clear, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(pgd_clear, srmmu_pgd_clear, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(flush_cache_all, hypersparc_flush_cache_all, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(flush_cache_mm, hypersparc_flush_cache_mm, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(flush_cache_range, hypersparc_flush_cache_range, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(flush_cache_page, hypersparc_flush_cache_page, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(flush_tlb_all, hypersparc_flush_tlb_all, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(flush_tlb_mm, hypersparc_flush_tlb_mm, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(flush_tlb_range, hypersparc_flush_tlb_range, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(flush_tlb_page, hypersparc_flush_tlb_page, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(__flush_page_to_ram, hypersparc_flush_page_to_ram, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(flush_sig_insns, hypersparc_flush_sig_insns, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(flush_page_for_dma, hypersparc_flush_page_for_dma, BTFIXUPCALL_NOP);
        poke_srmmu = poke_hypersparc;
        hypersparc_setup_blockops();
 }
-static void __cpuinit poke_cypress(void)
-{
-        unsigned long mreg = srmmu_get_mmureg();
-        unsigned long faddr, tagval;
-        volatile unsigned long cypress_sucks;
-        volatile unsigned long clear;
-        clear = srmmu_get_faddr();
-        clear = srmmu_get_fstatus();
-        if (!(mreg & CYPRESS_CENABLE)) {
-                for(faddr = 0x0; faddr < 0x10000; faddr += 20) {
-                        __asm__ __volatile__("sta %%g0, [%0 + %1] %2\n\t"
-                                             "sta %%g0, [%0] %2\n\t" : :
-                                             "r" (faddr), "r" (0x40000),
-                                             "i" (ASI_M_DATAC_TAG));
-                }
-        } else {
-                for(faddr = 0; faddr < 0x10000; faddr += 0x20) {
-                        __asm__ __volatile__("lda [%1 + %2] %3, %0\n\t" :
-                                             "=r" (tagval) :
-                                             "r" (faddr), "r" (0x40000),
-                                             "i" (ASI_M_DATAC_TAG));
-                        /* If modified and valid, kick it. */
-                        if((tagval & 0x60) == 0x60)
-                                cypress_sucks = *(unsigned long *)
-                                                        (0xf0020000 + faddr);
-                }
-        }
-        /* And one more, for our good neighbor, Mr. Broken Cypress. */
-        clear = srmmu_get_faddr();
-        clear = srmmu_get_fstatus();
-        mreg |= (CYPRESS_CENABLE | CYPRESS_CMODE);
-        srmmu_set_mmureg(mreg);
-}
-static void __init init_cypress_common(void)
-{
-        init_vac_layout();
-        BTFIXUPSET_CALL(pte_clear, srmmu_pte_clear, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(pmd_clear, srmmu_pmd_clear, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(pgd_clear, srmmu_pgd_clear, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(flush_cache_all, cypress_flush_cache_all, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(flush_cache_mm, cypress_flush_cache_mm, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(flush_cache_range, cypress_flush_cache_range, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(flush_cache_page, cypress_flush_cache_page, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(flush_tlb_all, cypress_flush_tlb_all, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(flush_tlb_mm, cypress_flush_tlb_mm, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(flush_tlb_page, cypress_flush_tlb_page, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(flush_tlb_range, cypress_flush_tlb_range, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(__flush_page_to_ram, cypress_flush_page_to_ram, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(flush_sig_insns, cypress_flush_sig_insns, BTFIXUPCALL_NOP);
-        BTFIXUPSET_CALL(flush_page_for_dma, cypress_flush_page_for_dma, BTFIXUPCALL_NOP);
-        poke_srmmu = poke_cypress;
-}
-static void __init init_cypress_604(void)
-{
-        srmmu_name = "ROSS Cypress-604(UP)";
-        srmmu_modtype = Cypress;
-        init_cypress_common();
-}
-static void __init init_cypress_605(unsigned long mrev)
-{
-        srmmu_name = "ROSS Cypress-605(MP)";
-        if(mrev == 0xe) {
-                srmmu_modtype = Cypress_vE;
-                hwbug_bitmask |= HWBUG_COPYBACK_BROKEN;
-        } else {
-                if(mrev == 0xd) {
-                        srmmu_modtype = Cypress_vD;
-                        hwbug_bitmask |= HWBUG_ASIFLUSH_BROKEN;
-                } else {
-                        srmmu_modtype = Cypress;
-                }
-        }
-        init_cypress_common();
-}
 static void __cpuinit poke_swift(void)
 {
        unsigned long mreg;
@@ -1617,6 +1068,20 @@ static void __cpuinit poke_swift(void)
        srmmu_set_mmureg(mreg);
 }
+static const struct sparc32_cachetlb_ops swift_ops = {
+        .cache_all      = swift_flush_cache_all,
+        .cache_mm       = swift_flush_cache_mm,
+        .cache_page     = swift_flush_cache_page,
+        .cache_range    = swift_flush_cache_range,
+        .tlb_all        = swift_flush_tlb_all,
+        .tlb_mm         = swift_flush_tlb_mm,
+        .tlb_page       = swift_flush_tlb_page,
+        .tlb_range      = swift_flush_tlb_range,
+        .page_to_ram    = swift_flush_page_to_ram,
+        .sig_insns      = swift_flush_sig_insns,
+        .page_for_dma   = swift_flush_page_for_dma,
+};
 #define SWIFT_MASKID_ADDR  0x10003018
 static void __init init_swift(void)
 {
@@ -1667,23 +1132,7 @@ static void __init init_swift(void)
                break;
        }
-        BTFIXUPSET_CALL(flush_cache_all, swift_flush_cache_all, BTFIXUPCALL_NORM);
+        sparc32_cachetlb_ops = &swift_ops;
-        BTFIXUPSET_CALL(flush_cache_mm, swift_flush_cache_mm, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(flush_cache_page, swift_flush_cache_page, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(flush_cache_range, swift_flush_cache_range, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(flush_tlb_all, swift_flush_tlb_all, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(flush_tlb_mm, swift_flush_tlb_mm, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(flush_tlb_page, swift_flush_tlb_page, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(flush_tlb_range, swift_flush_tlb_range, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(__flush_page_to_ram, swift_flush_page_to_ram, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(flush_sig_insns, swift_flush_sig_insns, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(flush_page_for_dma, swift_flush_page_for_dma, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(update_mmu_cache, swift_update_mmu_cache, BTFIXUPCALL_NORM);
        flush_page_for_dma_global = 0;
        /*
@@ -1816,26 +1265,25 @@ static void __cpuinit poke_turbosparc(void)
        srmmu_set_mmureg(mreg);
 }
+static const struct sparc32_cachetlb_ops turbosparc_ops = {
+        .cache_all      = turbosparc_flush_cache_all,
+        .cache_mm       = turbosparc_flush_cache_mm,
+        .cache_page     = turbosparc_flush_cache_page,
+        .cache_range    = turbosparc_flush_cache_range,
+        .tlb_all        = turbosparc_flush_tlb_all,
+        .tlb_mm         = turbosparc_flush_tlb_mm,
+        .tlb_page       = turbosparc_flush_tlb_page,
+        .tlb_range      = turbosparc_flush_tlb_range,
+        .page_to_ram    = turbosparc_flush_page_to_ram,
+        .sig_insns      = turbosparc_flush_sig_insns,
+        .page_for_dma   = turbosparc_flush_page_for_dma,
+};
 static void __init init_turbosparc(void)
 {
        srmmu_name = "Fujitsu TurboSparc";
        srmmu_modtype = TurboSparc;
+        sparc32_cachetlb_ops = &turbosparc_ops;
-        BTFIXUPSET_CALL(flush_cache_all, turbosparc_flush_cache_all, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(flush_cache_mm, turbosparc_flush_cache_mm, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(flush_cache_page, turbosparc_flush_cache_page, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(flush_cache_range, turbosparc_flush_cache_range, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(flush_tlb_all, turbosparc_flush_tlb_all, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(flush_tlb_mm, turbosparc_flush_tlb_mm, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(flush_tlb_page, turbosparc_flush_tlb_page, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(flush_tlb_range, turbosparc_flush_tlb_range, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(__flush_page_to_ram, turbosparc_flush_page_to_ram, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(flush_sig_insns, turbosparc_flush_sig_insns, BTFIXUPCALL_NOP);
-        BTFIXUPSET_CALL(flush_page_for_dma, turbosparc_flush_page_for_dma, BTFIXUPCALL_NORM);
        poke_srmmu = poke_turbosparc;
 }
@@ -1850,6 +1298,20 @@ static void __cpuinit poke_tsunami(void)
        srmmu_set_mmureg(mreg);
 }
+static const struct sparc32_cachetlb_ops tsunami_ops = {
+        .cache_all      = tsunami_flush_cache_all,
+        .cache_mm       = tsunami_flush_cache_mm,
+        .cache_page     = tsunami_flush_cache_page,
+        .cache_range    = tsunami_flush_cache_range,
+        .tlb_all        = tsunami_flush_tlb_all,
+        .tlb_mm         = tsunami_flush_tlb_mm,
+        .tlb_page       = tsunami_flush_tlb_page,
+        .tlb_range      = tsunami_flush_tlb_range,
+        .page_to_ram    = tsunami_flush_page_to_ram,
+        .sig_insns      = tsunami_flush_sig_insns,
+        .page_for_dma   = tsunami_flush_page_for_dma,
+};
 static void __init init_tsunami(void)
 {
        /*
@@ -1860,22 +1322,7 @@ static void __init init_tsunami(void)
        srmmu_name = "TI Tsunami";
        srmmu_modtype = Tsunami;
+        sparc32_cachetlb_ops = &tsunami_ops;
-        BTFIXUPSET_CALL(flush_cache_all, tsunami_flush_cache_all, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(flush_cache_mm, tsunami_flush_cache_mm, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(flush_cache_page, tsunami_flush_cache_page, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(flush_cache_range, tsunami_flush_cache_range, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(flush_tlb_all, tsunami_flush_tlb_all, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(flush_tlb_mm, tsunami_flush_tlb_mm, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(flush_tlb_page, tsunami_flush_tlb_page, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(flush_tlb_range, tsunami_flush_tlb_range, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(__flush_page_to_ram, tsunami_flush_page_to_ram, BTFIXUPCALL_NOP);
-        BTFIXUPSET_CALL(flush_sig_insns, tsunami_flush_sig_insns, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(flush_page_for_dma, tsunami_flush_page_for_dma, BTFIXUPCALL_NORM);
        poke_srmmu = poke_tsunami;
        tsunami_setup_blockops();
@@ -1886,7 +1333,7 @@ static void __cpuinit poke_viking(void)
        unsigned long mreg = srmmu_get_mmureg();
        static int smp_catch;
-        if(viking_mxcc_present) {
+        if (viking_mxcc_present) {
                unsigned long mxcc_control = mxcc_get_creg();
                mxcc_control |= (MXCC_CTL_ECE | MXCC_CTL_PRE | MXCC_CTL_MCE);
@@ -1923,6 +1370,52 @@ static void __cpuinit poke_viking(void)
        srmmu_set_mmureg(mreg);
 }
+static struct sparc32_cachetlb_ops viking_ops = {
+        .cache_all      = viking_flush_cache_all,
+        .cache_mm       = viking_flush_cache_mm,
+        .cache_page     = viking_flush_cache_page,
+        .cache_range    = viking_flush_cache_range,
+        .tlb_all        = viking_flush_tlb_all,
+        .tlb_mm         = viking_flush_tlb_mm,
+        .tlb_page       = viking_flush_tlb_page,
+        .tlb_range      = viking_flush_tlb_range,
+        .page_to_ram    = viking_flush_page_to_ram,
+        .sig_insns      = viking_flush_sig_insns,
+        .page_for_dma   = viking_flush_page_for_dma,
+};
+#ifdef CONFIG_SMP
+/* On sun4d the cpu broadcasts local TLB flushes, so we can just
+ * perform the local TLB flush and all the other cpus will see it.
+ * But, unfortunately, there is a bug in the sun4d XBUS backplane
+ * that requires that we add some synchronization to these flushes.
+ *
+ * The bug is that the fifo which keeps track of all the pending TLB
+ * broadcasts in the system is an entry or two too small, so if we
+ * have too many going at once we'll overflow that fifo and lose a TLB
+ * flush resulting in corruption.
+ *
+ * Our workaround is to take a global spinlock around the TLB flushes,
+ * which guarentees we won't ever have too many pending.  It's a big
+ * hammer, but a semaphore like system to make sure we only have N TLB
+ * flushes going at once will require SMP locking anyways so there's
+ * no real value in trying any harder than this.
+ */
+static struct sparc32_cachetlb_ops viking_sun4d_smp_ops = {
+        .cache_all      = viking_flush_cache_all,
+        .cache_mm       = viking_flush_cache_mm,
+        .cache_page     = viking_flush_cache_page,
+        .cache_range    = viking_flush_cache_range,
+        .tlb_all        = sun4dsmp_flush_tlb_all,
+        .tlb_mm         = sun4dsmp_flush_tlb_mm,
+        .tlb_page       = sun4dsmp_flush_tlb_page,
+        .tlb_range      = sun4dsmp_flush_tlb_range,
+        .page_to_ram    = viking_flush_page_to_ram,
+        .sig_insns      = viking_flush_sig_insns,
+        .page_for_dma   = viking_flush_page_for_dma,
+};
+#endif
 static void __init init_viking(void)
 {
        unsigned long mreg = srmmu_get_mmureg();
@@ -1933,10 +1426,6 @@ static void __init init_viking(void)
                viking_mxcc_present = 0;
                msi_set_sync();
-                BTFIXUPSET_CALL(pte_clear, srmmu_pte_clear, BTFIXUPCALL_NORM);
-                BTFIXUPSET_CALL(pmd_clear, srmmu_pmd_clear, BTFIXUPCALL_NORM);
-                BTFIXUPSET_CALL(pgd_clear, srmmu_pgd_clear, BTFIXUPCALL_NORM);
                /*
                 * We need this to make sure old viking takes no hits
                 * on it's cache for dma snoops to workaround the
@@ -1944,84 +1433,28 @@ static void __init init_viking(void)
                 * This is only necessary because of the new way in
                 * which we use the IOMMU.
                 */
-                BTFIXUPSET_CALL(flush_page_for_dma, viking_flush_page, BTFIXUPCALL_NORM);
+                viking_ops.page_for_dma = viking_flush_page;
+#ifdef CONFIG_SMP
+                viking_sun4d_smp_ops.page_for_dma = viking_flush_page;
+#endif
                flush_page_for_dma_global = 0;
        } else {
                srmmu_name = "TI Viking/MXCC";
                viking_mxcc_present = 1;
                srmmu_cache_pagetables = 1;
-                /* MXCC vikings lack the DMA snooping bug. */
-                BTFIXUPSET_CALL(flush_page_for_dma, viking_flush_page_for_dma, BTFIXUPCALL_NOP);
        }
-        BTFIXUPSET_CALL(flush_cache_all, viking_flush_cache_all, BTFIXUPCALL_NORM);
+        sparc32_cachetlb_ops = (const struct sparc32_cachetlb_ops *)
-        BTFIXUPSET_CALL(flush_cache_mm, viking_flush_cache_mm, BTFIXUPCALL_NORM);
+                &viking_ops;
-        BTFIXUPSET_CALL(flush_cache_page, viking_flush_cache_page, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(flush_cache_range, viking_flush_cache_range, BTFIXUPCALL_NORM);
 #ifdef CONFIG_SMP
-        if (sparc_cpu_model == sun4d) {
+        if (sparc_cpu_model == sun4d)
-                BTFIXUPSET_CALL(flush_tlb_all, sun4dsmp_flush_tlb_all, BTFIXUPCALL_NORM);
+                sparc32_cachetlb_ops = (const struct sparc32_cachetlb_ops *)
-                BTFIXUPSET_CALL(flush_tlb_mm, sun4dsmp_flush_tlb_mm, BTFIXUPCALL_NORM);
+                        &viking_sun4d_smp_ops;
-                BTFIXUPSET_CALL(flush_tlb_page, sun4dsmp_flush_tlb_page, BTFIXUPCALL_NORM);
-                BTFIXUPSET_CALL(flush_tlb_range, sun4dsmp_flush_tlb_range, BTFIXUPCALL_NORM);
-        } else
 #endif
-        {
-                BTFIXUPSET_CALL(flush_tlb_all, viking_flush_tlb_all, BTFIXUPCALL_NORM);
-                BTFIXUPSET_CALL(flush_tlb_mm, viking_flush_tlb_mm, BTFIXUPCALL_NORM);
-                BTFIXUPSET_CALL(flush_tlb_page, viking_flush_tlb_page, BTFIXUPCALL_NORM);
-                BTFIXUPSET_CALL(flush_tlb_range, viking_flush_tlb_range, BTFIXUPCALL_NORM);
-        }
-        BTFIXUPSET_CALL(__flush_page_to_ram, viking_flush_page_to_ram, BTFIXUPCALL_NOP);
-        BTFIXUPSET_CALL(flush_sig_insns, viking_flush_sig_insns, BTFIXUPCALL_NOP);
        poke_srmmu = poke_viking;
 }
-#ifdef CONFIG_SPARC_LEON
-void __init poke_leonsparc(void)
-{
-}
-void __init init_leon(void)
-{
-        srmmu_name = "LEON";
-        BTFIXUPSET_CALL(flush_cache_all, leon_flush_cache_all,
-                        BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(flush_cache_mm, leon_flush_cache_all,
-                        BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(flush_cache_page, leon_flush_pcache_all,
-                        BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(flush_cache_range, leon_flush_cache_all,
-                        BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(flush_page_for_dma, leon_flush_dcache_all,
-                        BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(flush_tlb_all, leon_flush_tlb_all, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(flush_tlb_mm, leon_flush_tlb_all, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(flush_tlb_page, leon_flush_tlb_all, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(flush_tlb_range, leon_flush_tlb_all, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(__flush_page_to_ram, leon_flush_cache_all,
-                        BTFIXUPCALL_NOP);
-        BTFIXUPSET_CALL(flush_sig_insns, leon_flush_cache_all, BTFIXUPCALL_NOP);
-        poke_srmmu = poke_leonsparc;
-        srmmu_cache_pagetables = 0;
-        leon_flush_during_switch = leon_flush_needed();
-}
-#endif
 /* Probe for the srmmu chip version. */
 static void __init get_srmmu_type(void)
 {
@@ -2052,22 +1485,15 @@ static void __init get_srmmu_type(void)
                        break;
                case 0:
                case 2:
-                        /* Uniprocessor Cypress */
-                        init_cypress_604();
-                        break;
                case 10:
                case 11:
                case 12:
-                        /* _REALLY OLD_ Cypress MP chips... */
                case 13:
                case 14:
                case 15:
-                        /* MP Cypress mmu/cache-controller */
-                        init_cypress_605(mod_rev);
-                        break;
                default:
-                        /* Some other Cypress revision, assume a 605. */
+                        prom_printf("Sparc-Linux Cypress support does not longer exit.\n");
-                        init_cypress_605(mod_rev);
+                        prom_halt();
                        break;
                }
                return;
@@ -2123,203 +1549,193 @@ static void __init get_srmmu_type(void)
        srmmu_is_bad();
 }
-/* don't laugh, static pagetables */
+#ifdef CONFIG_SMP
-static void srmmu_check_pgt_cache(int low, int high)
+/* Local cross-calls. */
+static void smp_flush_page_for_dma(unsigned long page)
 {
+        xc1((smpfunc_t) local_ops->page_for_dma, page);
+        local_ops->page_for_dma(page);
 }
-extern unsigned long spwin_mmu_patchme, fwin_mmu_patchme,
+static void smp_flush_cache_all(void)
-        tsetup_mmu_patchme, rtrap_mmu_patchme;
-extern unsigned long spwin_srmmu_stackchk, srmmu_fwin_stackchk,
-        tsetup_srmmu_stackchk, srmmu_rett_stackchk;
-extern unsigned long srmmu_fault;
-#define PATCH_BRANCH(insn, dest) do { \
-                iaddr = &(insn); \
-                daddr = &(dest); \
-                *iaddr = SPARC_BRANCH((unsigned long) daddr, (unsigned long) iaddr); \
-        } while(0)
-static void __init patch_window_trap_handlers(void)
 {
-        unsigned long *iaddr, *daddr;
+        xc0((smpfunc_t) local_ops->cache_all);
-        
+        local_ops->cache_all();
-        PATCH_BRANCH(spwin_mmu_patchme, spwin_srmmu_stackchk);
-        PATCH_BRANCH(fwin_mmu_patchme, srmmu_fwin_stackchk);
-        PATCH_BRANCH(tsetup_mmu_patchme, tsetup_srmmu_stackchk);
-        PATCH_BRANCH(rtrap_mmu_patchme, srmmu_rett_stackchk);
-        PATCH_BRANCH(sparc_ttable[SP_TRAP_TFLT].inst_three, srmmu_fault);
-        PATCH_BRANCH(sparc_ttable[SP_TRAP_DFLT].inst_three, srmmu_fault);
-        PATCH_BRANCH(sparc_ttable[SP_TRAP_DACC].inst_three, srmmu_fault);
 }
-#ifdef CONFIG_SMP
+static void smp_flush_tlb_all(void)
-/* Local cross-calls. */
-static void smp_flush_page_for_dma(unsigned long page)
 {
-        xc1((smpfunc_t) BTFIXUP_CALL(local_flush_page_for_dma), page);
+        xc0((smpfunc_t) local_ops->tlb_all);
-        local_flush_page_for_dma(page);
+        local_ops->tlb_all();
 }
-#endif
+static void smp_flush_cache_mm(struct mm_struct *mm)
-static pte_t srmmu_pgoff_to_pte(unsigned long pgoff)
 {
-        return __pte((pgoff << SRMMU_PTE_FILE_SHIFT) | SRMMU_FILE);
+        if (mm->context != NO_CONTEXT) {
+                cpumask_t cpu_mask;
+                cpumask_copy(&cpu_mask, mm_cpumask(mm));
+                cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
+                if (!cpumask_empty(&cpu_mask))
+                        xc1((smpfunc_t) local_ops->cache_mm, (unsigned long) mm);
+                local_ops->cache_mm(mm);
+        }
 }
-static unsigned long srmmu_pte_to_pgoff(pte_t pte)
+static void smp_flush_tlb_mm(struct mm_struct *mm)
 {
-        return pte_val(pte) >> SRMMU_PTE_FILE_SHIFT;
+        if (mm->context != NO_CONTEXT) {
+                cpumask_t cpu_mask;
+                cpumask_copy(&cpu_mask, mm_cpumask(mm));
+                cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
+                if (!cpumask_empty(&cpu_mask)) {
+                        xc1((smpfunc_t) local_ops->tlb_mm, (unsigned long) mm);
+                        if (atomic_read(&mm->mm_users) == 1 && current->active_mm == mm)
+                                cpumask_copy(mm_cpumask(mm),
+                                             cpumask_of(smp_processor_id()));
+                }
+                local_ops->tlb_mm(mm);
+        }
 }
-static pgprot_t srmmu_pgprot_noncached(pgprot_t prot)
+static void smp_flush_cache_range(struct vm_area_struct *vma,
+                                  unsigned long start,
+                                  unsigned long end)
 {
-        prot &= ~__pgprot(SRMMU_CACHE);
+        struct mm_struct *mm = vma->vm_mm;
-        return prot;
+        if (mm->context != NO_CONTEXT) {
+                cpumask_t cpu_mask;
+                cpumask_copy(&cpu_mask, mm_cpumask(mm));
+                cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
+                if (!cpumask_empty(&cpu_mask))
+                        xc3((smpfunc_t) local_ops->cache_range,
+                            (unsigned long) vma, start, end);
+                local_ops->cache_range(vma, start, end);
+        }
 }
-/* Load up routines and constants for sun4m and sun4d mmu */
+static void smp_flush_tlb_range(struct vm_area_struct *vma,
-void __init ld_mmu_srmmu(void)
+                                unsigned long start,
+                                unsigned long end)
 {
-        extern void ld_mmu_iommu(void);
+        struct mm_struct *mm = vma->vm_mm;
-        extern void ld_mmu_iounit(void);
-        extern void ___xchg32_sun4md(void);
-        BTFIXUPSET_SIMM13(pgdir_shift, SRMMU_PGDIR_SHIFT);
-        BTFIXUPSET_SETHI(pgdir_size, SRMMU_PGDIR_SIZE);
-        BTFIXUPSET_SETHI(pgdir_mask, SRMMU_PGDIR_MASK);
-        BTFIXUPSET_SIMM13(ptrs_per_pmd, SRMMU_PTRS_PER_PMD);
-        BTFIXUPSET_SIMM13(ptrs_per_pgd, SRMMU_PTRS_PER_PGD);
-        BTFIXUPSET_INT(page_none, pgprot_val(SRMMU_PAGE_NONE));
-        PAGE_SHARED = pgprot_val(SRMMU_PAGE_SHARED);
-        BTFIXUPSET_INT(page_copy, pgprot_val(SRMMU_PAGE_COPY));
-        BTFIXUPSET_INT(page_readonly, pgprot_val(SRMMU_PAGE_RDONLY));
-        BTFIXUPSET_INT(page_kernel, pgprot_val(SRMMU_PAGE_KERNEL));
-        page_kernel = pgprot_val(SRMMU_PAGE_KERNEL);
-        /* Functions */
+        if (mm->context != NO_CONTEXT) {
-        BTFIXUPSET_CALL(pgprot_noncached, srmmu_pgprot_noncached, BTFIXUPCALL_NORM);
+                cpumask_t cpu_mask;
-#ifndef CONFIG_SMP      
+                cpumask_copy(&cpu_mask, mm_cpumask(mm));
-        BTFIXUPSET_CALL(___xchg32, ___xchg32_sun4md, BTFIXUPCALL_SWAPG1G2);
+                cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
-#endif
+                if (!cpumask_empty(&cpu_mask))
-        BTFIXUPSET_CALL(do_check_pgt_cache, srmmu_check_pgt_cache, BTFIXUPCALL_NOP);
+                        xc3((smpfunc_t) local_ops->tlb_range,
+                            (unsigned long) vma, start, end);
+                local_ops->tlb_range(vma, start, end);
+        }
+}
-        BTFIXUPSET_CALL(set_pte, srmmu_set_pte, BTFIXUPCALL_SWAPO0O1);
+static void smp_flush_cache_page(struct vm_area_struct *vma, unsigned long page)
-        BTFIXUPSET_CALL(switch_mm, srmmu_switch_mm, BTFIXUPCALL_NORM);
+{
+        struct mm_struct *mm = vma->vm_mm;
-        BTFIXUPSET_CALL(pte_pfn, srmmu_pte_pfn, BTFIXUPCALL_NORM);
+        if (mm->context != NO_CONTEXT) {
-        BTFIXUPSET_CALL(pmd_page, srmmu_pmd_page, BTFIXUPCALL_NORM);
+                cpumask_t cpu_mask;
-        BTFIXUPSET_CALL(pgd_page_vaddr, srmmu_pgd_page, BTFIXUPCALL_NORM);
+                cpumask_copy(&cpu_mask, mm_cpumask(mm));
+                cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
+                if (!cpumask_empty(&cpu_mask))
+                        xc2((smpfunc_t) local_ops->cache_page,
+                            (unsigned long) vma, page);
+                local_ops->cache_page(vma, page);
+        }
+}
-        BTFIXUPSET_CALL(pte_present, srmmu_pte_present, BTFIXUPCALL_NORM);
+static void smp_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
-        BTFIXUPSET_CALL(pte_clear, srmmu_pte_clear, BTFIXUPCALL_SWAPO0G0);
+{
+        struct mm_struct *mm = vma->vm_mm;
-        BTFIXUPSET_CALL(pmd_bad, srmmu_pmd_bad, BTFIXUPCALL_NORM);
+        if (mm->context != NO_CONTEXT) {
-        BTFIXUPSET_CALL(pmd_present, srmmu_pmd_present, BTFIXUPCALL_NORM);
+                cpumask_t cpu_mask;
-        BTFIXUPSET_CALL(pmd_clear, srmmu_pmd_clear, BTFIXUPCALL_SWAPO0G0);
+                cpumask_copy(&cpu_mask, mm_cpumask(mm));
+                cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
+                if (!cpumask_empty(&cpu_mask))
+                        xc2((smpfunc_t) local_ops->tlb_page,
+                            (unsigned long) vma, page);
+                local_ops->tlb_page(vma, page);
+        }
+}
-        BTFIXUPSET_CALL(pgd_none, srmmu_pgd_none, BTFIXUPCALL_NORM);
+static void smp_flush_page_to_ram(unsigned long page)
-        BTFIXUPSET_CALL(pgd_bad, srmmu_pgd_bad, BTFIXUPCALL_NORM);
+{
-        BTFIXUPSET_CALL(pgd_present, srmmu_pgd_present, BTFIXUPCALL_NORM);
+        /* Current theory is that those who call this are the one's
-        BTFIXUPSET_CALL(pgd_clear, srmmu_pgd_clear, BTFIXUPCALL_SWAPO0G0);
+         * who have just dirtied their cache with the pages contents
+         * in kernel space, therefore we only run this on local cpu.
+         *
+         * XXX This experiment failed, research further... -DaveM
+         */
+#if 1
+        xc1((smpfunc_t) local_ops->page_to_ram, page);
+#endif
+        local_ops->page_to_ram(page);
+}
+static void smp_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr)
+{
+        cpumask_t cpu_mask;
+        cpumask_copy(&cpu_mask, mm_cpumask(mm));
+        cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
+        if (!cpumask_empty(&cpu_mask))
+                xc2((smpfunc_t) local_ops->sig_insns,
+                    (unsigned long) mm, insn_addr);
+        local_ops->sig_insns(mm, insn_addr);
+}
+static struct sparc32_cachetlb_ops smp_cachetlb_ops = {
+        .cache_all      = smp_flush_cache_all,
+        .cache_mm       = smp_flush_cache_mm,
+        .cache_page     = smp_flush_cache_page,
+        .cache_range    = smp_flush_cache_range,
+        .tlb_all        = smp_flush_tlb_all,
+        .tlb_mm         = smp_flush_tlb_mm,
+        .tlb_page       = smp_flush_tlb_page,
+        .tlb_range      = smp_flush_tlb_range,
+        .page_to_ram    = smp_flush_page_to_ram,
+        .sig_insns      = smp_flush_sig_insns,
+        .page_for_dma   = smp_flush_page_for_dma,
+};
+#endif
-        BTFIXUPSET_CALL(mk_pte, srmmu_mk_pte, BTFIXUPCALL_NORM);
+/* Load up routines and constants for sun4m and sun4d mmu */
-        BTFIXUPSET_CALL(mk_pte_phys, srmmu_mk_pte_phys, BTFIXUPCALL_NORM);
+void __init load_mmu(void)
-        BTFIXUPSET_CALL(mk_pte_io, srmmu_mk_pte_io, BTFIXUPCALL_NORM);
+{
-        BTFIXUPSET_CALL(pgd_set, srmmu_pgd_set, BTFIXUPCALL_NORM);
+        extern void ld_mmu_iommu(void);
-        BTFIXUPSET_CALL(pmd_set, srmmu_pmd_set, BTFIXUPCALL_NORM);
+        extern void ld_mmu_iounit(void);
-        BTFIXUPSET_CALL(pmd_populate, srmmu_pmd_populate, BTFIXUPCALL_NORM);
-        
-        BTFIXUPSET_INT(pte_modify_mask, SRMMU_CHG_MASK);
-        BTFIXUPSET_CALL(pmd_offset, srmmu_pmd_offset, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(pte_offset_kernel, srmmu_pte_offset, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(free_pte_fast, srmmu_free_pte_fast, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(pte_free, srmmu_pte_free, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(pte_alloc_one_kernel, srmmu_pte_alloc_one_kernel, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(pte_alloc_one, srmmu_pte_alloc_one, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(free_pmd_fast, srmmu_pmd_free, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(pmd_alloc_one, srmmu_pmd_alloc_one, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(free_pgd_fast, srmmu_free_pgd_fast, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(get_pgd_fast, srmmu_get_pgd_fast, BTFIXUPCALL_NORM);
-        BTFIXUPSET_HALF(pte_writei, SRMMU_WRITE);
-        BTFIXUPSET_HALF(pte_dirtyi, SRMMU_DIRTY);
-        BTFIXUPSET_HALF(pte_youngi, SRMMU_REF);
-        BTFIXUPSET_HALF(pte_filei, SRMMU_FILE);
-        BTFIXUPSET_HALF(pte_wrprotecti, SRMMU_WRITE);
-        BTFIXUPSET_HALF(pte_mkcleani, SRMMU_DIRTY);
-        BTFIXUPSET_HALF(pte_mkoldi, SRMMU_REF);
-        BTFIXUPSET_CALL(pte_mkwrite, srmmu_pte_mkwrite, BTFIXUPCALL_ORINT(SRMMU_WRITE));
-        BTFIXUPSET_CALL(pte_mkdirty, srmmu_pte_mkdirty, BTFIXUPCALL_ORINT(SRMMU_DIRTY));
-        BTFIXUPSET_CALL(pte_mkyoung, srmmu_pte_mkyoung, BTFIXUPCALL_ORINT(SRMMU_REF));
-        BTFIXUPSET_CALL(update_mmu_cache, srmmu_update_mmu_cache, BTFIXUPCALL_NOP);
-        BTFIXUPSET_CALL(destroy_context, srmmu_destroy_context, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(sparc_mapiorange, srmmu_mapiorange, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(sparc_unmapiorange, srmmu_unmapiorange, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(__swp_type, srmmu_swp_type, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(__swp_offset, srmmu_swp_offset, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(__swp_entry, srmmu_swp_entry, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(mmu_info, srmmu_mmu_info, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(alloc_thread_info_node, srmmu_alloc_thread_info_node, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(free_thread_info, srmmu_free_thread_info, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(pte_to_pgoff, srmmu_pte_to_pgoff, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(pgoff_to_pte, srmmu_pgoff_to_pte, BTFIXUPCALL_NORM);
+        /* Functions */
        get_srmmu_type();
-        patch_window_trap_handlers();
 #ifdef CONFIG_SMP
        /* El switcheroo... */
+        local_ops = sparc32_cachetlb_ops;
-        BTFIXUPCOPY_CALL(local_flush_cache_all, flush_cache_all);
+        if (sparc_cpu_model == sun4d || sparc_cpu_model == sparc_leon) {
-        BTFIXUPCOPY_CALL(local_flush_cache_mm, flush_cache_mm);
+                smp_cachetlb_ops.tlb_all = local_ops->tlb_all;
-        BTFIXUPCOPY_CALL(local_flush_cache_range, flush_cache_range);
+                smp_cachetlb_ops.tlb_mm = local_ops->tlb_mm;
-        BTFIXUPCOPY_CALL(local_flush_cache_page, flush_cache_page);
+                smp_cachetlb_ops.tlb_range = local_ops->tlb_range;
-        BTFIXUPCOPY_CALL(local_flush_tlb_all, flush_tlb_all);
+                smp_cachetlb_ops.tlb_page = local_ops->tlb_page;
-        BTFIXUPCOPY_CALL(local_flush_tlb_mm, flush_tlb_mm);
-        BTFIXUPCOPY_CALL(local_flush_tlb_range, flush_tlb_range);
-        BTFIXUPCOPY_CALL(local_flush_tlb_page, flush_tlb_page);
-        BTFIXUPCOPY_CALL(local_flush_page_to_ram, __flush_page_to_ram);
-        BTFIXUPCOPY_CALL(local_flush_sig_insns, flush_sig_insns);
-        BTFIXUPCOPY_CALL(local_flush_page_for_dma, flush_page_for_dma);
-        BTFIXUPSET_CALL(flush_cache_all, smp_flush_cache_all, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(flush_cache_mm, smp_flush_cache_mm, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(flush_cache_range, smp_flush_cache_range, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(flush_cache_page, smp_flush_cache_page, BTFIXUPCALL_NORM);
-        if (sparc_cpu_model != sun4d &&
-            sparc_cpu_model != sparc_leon) {
-                BTFIXUPSET_CALL(flush_tlb_all, smp_flush_tlb_all, BTFIXUPCALL_NORM);
-                BTFIXUPSET_CALL(flush_tlb_mm, smp_flush_tlb_mm, BTFIXUPCALL_NORM);
-                BTFIXUPSET_CALL(flush_tlb_range, smp_flush_tlb_range, BTFIXUPCALL_NORM);
-                BTFIXUPSET_CALL(flush_tlb_page, smp_flush_tlb_page, BTFIXUPCALL_NORM);
        }
-        BTFIXUPSET_CALL(__flush_page_to_ram, smp_flush_page_to_ram, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(flush_sig_insns, smp_flush_sig_insns, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(flush_page_for_dma, smp_flush_page_for_dma, BTFIXUPCALL_NORM);
        if (poke_srmmu == poke_viking) {
                /* Avoid unnecessary cross calls. */
-                BTFIXUPCOPY_CALL(flush_cache_all, local_flush_cache_all);
+                smp_cachetlb_ops.cache_all = local_ops->cache_all;
-                BTFIXUPCOPY_CALL(flush_cache_mm, local_flush_cache_mm);
+                smp_cachetlb_ops.cache_mm = local_ops->cache_mm;
-                BTFIXUPCOPY_CALL(flush_cache_range, local_flush_cache_range);
+                smp_cachetlb_ops.cache_range = local_ops->cache_range;
-                BTFIXUPCOPY_CALL(flush_cache_page, local_flush_cache_page);
+                smp_cachetlb_ops.cache_page = local_ops->cache_page;
-                BTFIXUPCOPY_CALL(__flush_page_to_ram, local_flush_page_to_ram);
-                BTFIXUPCOPY_CALL(flush_sig_insns, local_flush_sig_insns);
+                smp_cachetlb_ops.page_to_ram = local_ops->page_to_ram;
-                BTFIXUPCOPY_CALL(flush_page_for_dma, local_flush_page_for_dma);
+                smp_cachetlb_ops.sig_insns = local_ops->sig_insns;
+                smp_cachetlb_ops.page_for_dma = local_ops->page_for_dma;
        }
+        /* It really is const after this point. */
+        sparc32_cachetlb_ops = (const struct sparc32_cachetlb_ops *)
+                &smp_cachetlb_ops;
 #endif
        if (sparc_cpu_model == sun4d)
diff --git a/arch/sparc/mm/srmmu.h b/arch/sparc/mm/srmmu.h
new file mode 100644
index 000000000000..5703274ccf89
--- /dev/null
+++ b/arch/sparc/mm/srmmu.h
@@ -0,0 +1,4 @@
+/* srmmu.c */
+extern char *srmmu_name;
+extern void (*poke_srmmu)(void);
diff --git a/arch/sparc/mm/sun4c.c b/arch/sparc/mm/sun4c.c
deleted file mode 100644
index 1cf4f198709a..000000000000
--- a/arch/sparc/mm/sun4c.c
+++ /dev/null
@@ -1,2166 +0,0 @@
-/* sun4c.c: Doing in software what should be done in hardware.
- *
- * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
- * Copyright (C) 1996 Eddie C. Dost (ecd@skynet.be)
- * Copyright (C) 1996 Andrew Tridgell (Andrew.Tridgell@anu.edu.au)
- * Copyright (C) 1997-2000 Anton Blanchard (anton@samba.org)
- * Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
- */
-#define NR_TASK_BUCKETS 512
-#include <linux/kernel.h>
-#include <linux/mm.h>
-#include <linux/init.h>
-#include <linux/slab.h>
-#include <linux/bootmem.h>
-#include <linux/highmem.h>
-#include <linux/fs.h>
-#include <linux/seq_file.h>
-#include <linux/scatterlist.h>
-#include <linux/bitmap.h>
-#include <asm/sections.h>
-#include <asm/page.h>
-#include <asm/pgalloc.h>
-#include <asm/pgtable.h>
-#include <asm/vaddrs.h>
-#include <asm/idprom.h>
-#include <asm/machines.h>
-#include <asm/memreg.h>
-#include <asm/processor.h>
-#include <asm/auxio.h>
-#include <asm/io.h>
-#include <asm/oplib.h>
-#include <asm/openprom.h>
-#include <asm/mmu_context.h>
-#include <asm/highmem.h>
-#include <asm/btfixup.h>
-#include <asm/cacheflush.h>
-#include <asm/tlbflush.h>
-/* Because of our dynamic kernel TLB miss strategy, and how
- * our DVMA mapping allocation works, you _MUST_:
- *
- * 1) Disable interrupts _and_ not touch any dynamic kernel
- *    memory while messing with kernel MMU state.  By
- *    dynamic memory I mean any object which is not in
- *    the kernel image itself or a thread_union (both of
- *    which are locked into the MMU).
- * 2) Disable interrupts while messing with user MMU state.
- */
-extern int num_segmaps, num_contexts;
-extern unsigned long page_kernel;
-/* That's it, we prom_halt() on sun4c if the cache size is something other than 65536.
- * So let's save some cycles and just use that everywhere except for that bootup
- * sanity check.
- */
-#define SUN4C_VAC_SIZE 65536
-#define SUN4C_KERNEL_BUCKETS 32
-/* Flushing the cache. */
-struct sun4c_vac_props sun4c_vacinfo;
-unsigned long sun4c_kernel_faults;
-/* Invalidate every sun4c cache line tag. */
-static void __init sun4c_flush_all(void)
-{
-        unsigned long begin, end;
-        if (sun4c_vacinfo.on)
-                panic("SUN4C: AIEEE, trying to invalidate vac while it is on.");
-        /* Clear 'valid' bit in all cache line tags */
-        begin = AC_CACHETAGS;
-        end = (AC_CACHETAGS + SUN4C_VAC_SIZE);
-        while (begin < end) {
-                __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
-                                     "r" (begin), "i" (ASI_CONTROL));
-                begin += sun4c_vacinfo.linesize;
-        }
-}
-static void sun4c_flush_context_hw(void)
-{
-        unsigned long end = SUN4C_VAC_SIZE;
-        __asm__ __volatile__(
-                "1:     addcc   %0, -4096, %0\n\t"
-                "       bne     1b\n\t"
-                "        sta    %%g0, [%0] %2"
-        : "=&r" (end)
-        : "0" (end), "i" (ASI_HWFLUSHCONTEXT)
-        : "cc");
-}
-/* Must be called minimally with IRQs disabled. */
-static void sun4c_flush_segment_hw(unsigned long addr)
-{
-        if (sun4c_get_segmap(addr) != invalid_segment) {
-                unsigned long vac_size = SUN4C_VAC_SIZE;
-                __asm__ __volatile__(
-                        "1:     addcc   %0, -4096, %0\n\t"
-                        "       bne     1b\n\t"
-                        "        sta    %%g0, [%2 + %0] %3"
-                        : "=&r" (vac_size)
-                        : "0" (vac_size), "r" (addr), "i" (ASI_HWFLUSHSEG)
-                        : "cc");
-        }
-}
-/* File local boot time fixups. */
-BTFIXUPDEF_CALL(void, sun4c_flush_page, unsigned long)
-BTFIXUPDEF_CALL(void, sun4c_flush_segment, unsigned long)
-BTFIXUPDEF_CALL(void, sun4c_flush_context, void)
-#define sun4c_flush_page(addr) BTFIXUP_CALL(sun4c_flush_page)(addr)
-#define sun4c_flush_segment(addr) BTFIXUP_CALL(sun4c_flush_segment)(addr)
-#define sun4c_flush_context() BTFIXUP_CALL(sun4c_flush_context)()
-/* Must be called minimally with interrupts disabled. */
-static void sun4c_flush_page_hw(unsigned long addr)
-{
-        addr &= PAGE_MASK;
-        if ((int)sun4c_get_pte(addr) < 0)
-                __asm__ __volatile__("sta %%g0, [%0] %1"
-                                     : : "r" (addr), "i" (ASI_HWFLUSHPAGE));
-}
-/* Don't inline the software version as it eats too many cache lines if expanded. */
-static void sun4c_flush_context_sw(void)
-{
-        unsigned long nbytes = SUN4C_VAC_SIZE;
-        unsigned long lsize = sun4c_vacinfo.linesize;
-        __asm__ __volatile__(
-        "add    %2, %2, %%g1\n\t"
-        "add    %2, %%g1, %%g2\n\t"
-        "add    %2, %%g2, %%g3\n\t"
-        "add    %2, %%g3, %%g4\n\t"
-        "add    %2, %%g4, %%g5\n\t"
-        "add    %2, %%g5, %%o4\n\t"
-        "add    %2, %%o4, %%o5\n"
-        "1:\n\t"
-        "subcc  %0, %%o5, %0\n\t"
-        "sta    %%g0, [%0] %3\n\t"
-        "sta    %%g0, [%0 + %2] %3\n\t"
-        "sta    %%g0, [%0 + %%g1] %3\n\t"
-        "sta    %%g0, [%0 + %%g2] %3\n\t"
-        "sta    %%g0, [%0 + %%g3] %3\n\t"
-        "sta    %%g0, [%0 + %%g4] %3\n\t"
-        "sta    %%g0, [%0 + %%g5] %3\n\t"
-        "bg     1b\n\t"
-        " sta   %%g0, [%1 + %%o4] %3\n"
-        : "=&r" (nbytes)
-        : "0" (nbytes), "r" (lsize), "i" (ASI_FLUSHCTX)
-        : "g1", "g2", "g3", "g4", "g5", "o4", "o5", "cc");
-}
-/* Don't inline the software version as it eats too many cache lines if expanded. */
-static void sun4c_flush_segment_sw(unsigned long addr)
-{
-        if (sun4c_get_segmap(addr) != invalid_segment) {
-                unsigned long nbytes = SUN4C_VAC_SIZE;
-                unsigned long lsize = sun4c_vacinfo.linesize;
-                __asm__ __volatile__(
-                "add    %2, %2, %%g1\n\t"
-                "add    %2, %%g1, %%g2\n\t"
-                "add    %2, %%g2, %%g3\n\t"
-                "add    %2, %%g3, %%g4\n\t"
-                "add    %2, %%g4, %%g5\n\t"
-                "add    %2, %%g5, %%o4\n\t"
-                "add    %2, %%o4, %%o5\n"
-                "1:\n\t"
-                "subcc  %1, %%o5, %1\n\t"
-                "sta    %%g0, [%0] %6\n\t"
-                "sta    %%g0, [%0 + %2] %6\n\t"
-                "sta    %%g0, [%0 + %%g1] %6\n\t"
-                "sta    %%g0, [%0 + %%g2] %6\n\t"
-                "sta    %%g0, [%0 + %%g3] %6\n\t"
-                "sta    %%g0, [%0 + %%g4] %6\n\t"
-                "sta    %%g0, [%0 + %%g5] %6\n\t"
-                "sta    %%g0, [%0 + %%o4] %6\n\t"
-                "bg     1b\n\t"
-                " add   %0, %%o5, %0\n"
-                : "=&r" (addr), "=&r" (nbytes), "=&r" (lsize)
-                : "0" (addr), "1" (nbytes), "2" (lsize),
-                  "i" (ASI_FLUSHSEG)
-                : "g1", "g2", "g3", "g4", "g5", "o4", "o5", "cc");
-        }
-}
-/* Don't inline the software version as it eats too many cache lines if expanded. */
-static void sun4c_flush_page_sw(unsigned long addr)
-{
-        addr &= PAGE_MASK;
-        if ((sun4c_get_pte(addr) & (_SUN4C_PAGE_NOCACHE | _SUN4C_PAGE_VALID)) ==
-            _SUN4C_PAGE_VALID) {
-                unsigned long left = PAGE_SIZE;
-                unsigned long lsize = sun4c_vacinfo.linesize;
-                __asm__ __volatile__(
-                "add    %2, %2, %%g1\n\t"
-                "add    %2, %%g1, %%g2\n\t"
-                "add    %2, %%g2, %%g3\n\t"
-                "add    %2, %%g3, %%g4\n\t"
-                "add    %2, %%g4, %%g5\n\t"
-                "add    %2, %%g5, %%o4\n\t"
-                "add    %2, %%o4, %%o5\n"
-                "1:\n\t"
-                "subcc  %1, %%o5, %1\n\t"
-                "sta    %%g0, [%0] %6\n\t"
-                "sta    %%g0, [%0 + %2] %6\n\t"
-                "sta    %%g0, [%0 + %%g1] %6\n\t"
-                "sta    %%g0, [%0 + %%g2] %6\n\t"
-                "sta    %%g0, [%0 + %%g3] %6\n\t"
-                "sta    %%g0, [%0 + %%g4] %6\n\t"
-                "sta    %%g0, [%0 + %%g5] %6\n\t"
-                "sta    %%g0, [%0 + %%o4] %6\n\t"
-                "bg     1b\n\t"
-                " add   %0, %%o5, %0\n"
-                : "=&r" (addr), "=&r" (left), "=&r" (lsize)
-                : "0" (addr), "1" (left), "2" (lsize),
-                  "i" (ASI_FLUSHPG)
-                : "g1", "g2", "g3", "g4", "g5", "o4", "o5", "cc");
-        }
-}
-/* The sun4c's do have an on chip store buffer.  And the way you
- * clear them out isn't so obvious.  The only way I can think of
- * to accomplish this is to read the current context register,
- * store the same value there, then read an external hardware
- * register.
- */
-void sun4c_complete_all_stores(void)
-{
-        volatile int _unused;
-        _unused = sun4c_get_context();
-        sun4c_set_context(_unused);
-        _unused = get_auxio();
-}
-/* Bootup utility functions. */
-static inline void sun4c_init_clean_segmap(unsigned char pseg)
-{
-        unsigned long vaddr;
-        sun4c_put_segmap(0, pseg);
-        for (vaddr = 0; vaddr < SUN4C_REAL_PGDIR_SIZE; vaddr += PAGE_SIZE)
-                sun4c_put_pte(vaddr, 0);
-        sun4c_put_segmap(0, invalid_segment);
-}
-static inline void sun4c_init_clean_mmu(unsigned long kernel_end)
-{
-        unsigned long vaddr;
-        unsigned char savectx, ctx;
-        savectx = sun4c_get_context();
-        for (ctx = 0; ctx < num_contexts; ctx++) {
-                sun4c_set_context(ctx);
-                for (vaddr = 0; vaddr < 0x20000000; vaddr += SUN4C_REAL_PGDIR_SIZE)
-                        sun4c_put_segmap(vaddr, invalid_segment);
-                for (vaddr = 0xe0000000; vaddr < KERNBASE; vaddr += SUN4C_REAL_PGDIR_SIZE)
-                        sun4c_put_segmap(vaddr, invalid_segment);
-                for (vaddr = kernel_end; vaddr < KADB_DEBUGGER_BEGVM; vaddr += SUN4C_REAL_PGDIR_SIZE)
-                        sun4c_put_segmap(vaddr, invalid_segment);
-                for (vaddr = LINUX_OPPROM_ENDVM; vaddr; vaddr += SUN4C_REAL_PGDIR_SIZE)
-                        sun4c_put_segmap(vaddr, invalid_segment);
-        }
-        sun4c_set_context(savectx);
-}
-void __init sun4c_probe_vac(void)
-{
-        sun4c_disable_vac();
-        if ((idprom->id_machtype == (SM_SUN4C | SM_4C_SS1)) ||
-            (idprom->id_machtype == (SM_SUN4C | SM_4C_SS1PLUS))) {
-                /* PROM on SS1 lacks this info, to be super safe we
-                 * hard code it here since this arch is cast in stone.
-                 */
-                sun4c_vacinfo.num_bytes = 65536;
-                sun4c_vacinfo.linesize = 16;
-        } else {
-                sun4c_vacinfo.num_bytes =
-                 prom_getintdefault(prom_root_node, "vac-size", 65536);
-                sun4c_vacinfo.linesize =
-                 prom_getintdefault(prom_root_node, "vac-linesize", 16);
-        }
-        sun4c_vacinfo.do_hwflushes =
-         prom_getintdefault(prom_root_node, "vac-hwflush", 0);
-        if (sun4c_vacinfo.do_hwflushes == 0)
-                sun4c_vacinfo.do_hwflushes =
-                 prom_getintdefault(prom_root_node, "vac_hwflush", 0);
-        if (sun4c_vacinfo.num_bytes != 65536) {
-                prom_printf("WEIRD Sun4C VAC cache size, "
-                            "tell sparclinux@vger.kernel.org");
-                prom_halt();
-        }
-        switch (sun4c_vacinfo.linesize) {
-        case 16:
-                sun4c_vacinfo.log2lsize = 4;
-                break;
-        case 32:
-                sun4c_vacinfo.log2lsize = 5;
-                break;
-        default:
-                prom_printf("probe_vac: Didn't expect vac-linesize of %d, halting\n",
-                            sun4c_vacinfo.linesize);
-                prom_halt();
-        }
-        sun4c_flush_all();
-        sun4c_enable_vac();
-}
-/* Patch instructions for the low level kernel fault handler. */
-extern unsigned long invalid_segment_patch1, invalid_segment_patch1_ff;
-extern unsigned long invalid_segment_patch2, invalid_segment_patch2_ff;
-extern unsigned long invalid_segment_patch1_1ff, invalid_segment_patch2_1ff;
-extern unsigned long num_context_patch1, num_context_patch1_16;
-extern unsigned long num_context_patch2_16;
-extern unsigned long vac_linesize_patch, vac_linesize_patch_32;
-extern unsigned long vac_hwflush_patch1, vac_hwflush_patch1_on;
-extern unsigned long vac_hwflush_patch2, vac_hwflush_patch2_on;
-#define PATCH_INSN(src, dst) do {       \
-                daddr = &(dst);         \
-                iaddr = &(src);         \
-                *daddr = *iaddr;        \
-        } while (0)
-static void __init patch_kernel_fault_handler(void)
-{
-        unsigned long *iaddr, *daddr;
-        switch (num_segmaps) {
-                case 128:
-                        /* Default, nothing to do. */
-                        break;
-                case 256:
-                        PATCH_INSN(invalid_segment_patch1_ff,
-                                   invalid_segment_patch1);
-                        PATCH_INSN(invalid_segment_patch2_ff,
-                                   invalid_segment_patch2);
-                        break;
-                case 512:
-                        PATCH_INSN(invalid_segment_patch1_1ff,
-                                   invalid_segment_patch1);
-                        PATCH_INSN(invalid_segment_patch2_1ff,
-                                   invalid_segment_patch2);
-                        break;
-                default:
-                        prom_printf("Unhandled number of segmaps: %d\n",
-                                    num_segmaps);
-                        prom_halt();
-        }
-        switch (num_contexts) {
-                case 8:
-                        /* Default, nothing to do. */
-                        break;
-                case 16:
-                        PATCH_INSN(num_context_patch1_16,
-                                   num_context_patch1);
-                        break;
-                default:
-                        prom_printf("Unhandled number of contexts: %d\n",
-                                    num_contexts);
-                        prom_halt();
-        }
-        if (sun4c_vacinfo.do_hwflushes != 0) {
-                PATCH_INSN(vac_hwflush_patch1_on, vac_hwflush_patch1);
-                PATCH_INSN(vac_hwflush_patch2_on, vac_hwflush_patch2);
-        } else {
-                switch (sun4c_vacinfo.linesize) {
-                case 16:
-                        /* Default, nothing to do. */
-                        break;
-                case 32:
-                        PATCH_INSN(vac_linesize_patch_32, vac_linesize_patch);
-                        break;
-                default:
-                        prom_printf("Impossible VAC linesize %d, halting...\n",
-                                    sun4c_vacinfo.linesize);
-                        prom_halt();
-                }
-        }
-}
-static void __init sun4c_probe_mmu(void)
-{
-        if ((idprom->id_machtype == (SM_SUN4C | SM_4C_SS1)) ||
-            (idprom->id_machtype == (SM_SUN4C | SM_4C_SS1PLUS))) {
-                /* Hardcode these just to be safe, PROM on SS1 does
-                * not have this info available in the root node.
-                */
-                num_segmaps = 128;
-                num_contexts = 8;
-        } else {
-                num_segmaps =
-                    prom_getintdefault(prom_root_node, "mmu-npmg", 128);
-                num_contexts =
-                    prom_getintdefault(prom_root_node, "mmu-nctx", 0x8);
-        }
-        patch_kernel_fault_handler();
-}
-volatile unsigned long __iomem *sun4c_memerr_reg = NULL;
-void __init sun4c_probe_memerr_reg(void)
-{
-        phandle node;
-        struct linux_prom_registers regs[1];
-        node = prom_getchild(prom_root_node);
-        node = prom_searchsiblings(prom_root_node, "memory-error");
-        if (!node)
-                return;
-        if (prom_getproperty(node, "reg", (char *)regs, sizeof(regs)) <= 0)
-                return;
-        /* hmm I think regs[0].which_io is zero here anyways */
-        sun4c_memerr_reg = ioremap(regs[0].phys_addr, regs[0].reg_size);
-}
-static inline void sun4c_init_ss2_cache_bug(void)
-{
-        if ((idprom->id_machtype == (SM_SUN4C | SM_4C_SS2)) ||
-            (idprom->id_machtype == (SM_SUN4C | SM_4C_IPX)) ||
-            (idprom->id_machtype == (SM_SUN4C | SM_4C_ELC))) {
-                /* Whee.. */
-                printk("SS2 cache bug detected, uncaching trap table page\n");
-                sun4c_flush_page((unsigned int) &_start);
-                sun4c_put_pte(((unsigned long) &_start),
-                        (sun4c_get_pte((unsigned long) &_start) | _SUN4C_PAGE_NOCACHE));
-        }
-}
-/* Addr is always aligned on a page boundary for us already. */
-static int sun4c_map_dma_area(struct device *dev, dma_addr_t *pba, unsigned long va,
-                              unsigned long addr, int len)
-{
-        unsigned long page, end;
-        *pba = addr;
-        end = PAGE_ALIGN((addr + len));
-        while (addr < end) {
-                page = va;
-                sun4c_flush_page(page);
-                page -= PAGE_OFFSET;
-                page >>= PAGE_SHIFT;
-                page |= (_SUN4C_PAGE_VALID | _SUN4C_PAGE_DIRTY |
-                         _SUN4C_PAGE_NOCACHE | _SUN4C_PAGE_PRIV);
-                sun4c_put_pte(addr, page);
-                addr += PAGE_SIZE;
-                va += PAGE_SIZE;
-        }
-        return 0;
-}
-static void sun4c_unmap_dma_area(struct device *dev, unsigned long busa, int len)
-{
-        /* Fortunately for us, bus_addr == uncached_virt in sun4c. */
-        /* XXX Implement this */
-}
-/* TLB management. */
-/* Don't change this struct without changing entry.S. This is used
- * in the in-window kernel fault handler, and you don't want to mess
- * with that. (See sun4c_fault in entry.S).
- */
-struct sun4c_mmu_entry {
-        struct sun4c_mmu_entry *next;
-        struct sun4c_mmu_entry *prev;
-        unsigned long vaddr;
-        unsigned char pseg;
-        unsigned char locked;
-        /* For user mappings only, and completely hidden from kernel
-         * TLB miss code.
-         */
-        unsigned char ctx;
-        struct sun4c_mmu_entry *lru_next;
-        struct sun4c_mmu_entry *lru_prev;
-};
-static struct sun4c_mmu_entry mmu_entry_pool[SUN4C_MAX_SEGMAPS];
-static void __init sun4c_init_mmu_entry_pool(void)
-{
-        int i;
-        for (i=0; i < SUN4C_MAX_SEGMAPS; i++) {
-                mmu_entry_pool[i].pseg = i;
-                mmu_entry_pool[i].next = NULL;
-                mmu_entry_pool[i].prev = NULL;
-                mmu_entry_pool[i].vaddr = 0;
-                mmu_entry_pool[i].locked = 0;
-                mmu_entry_pool[i].ctx = 0;
-                mmu_entry_pool[i].lru_next = NULL;
-                mmu_entry_pool[i].lru_prev = NULL;
-        }
-        mmu_entry_pool[invalid_segment].locked = 1;
-}
-static inline void fix_permissions(unsigned long vaddr, unsigned long bits_on,
-                                   unsigned long bits_off)
-{
-        unsigned long start, end;
-        end = vaddr + SUN4C_REAL_PGDIR_SIZE;
-        for (start = vaddr; start < end; start += PAGE_SIZE)
-                if (sun4c_get_pte(start) & _SUN4C_PAGE_VALID)
-                        sun4c_put_pte(start, (sun4c_get_pte(start) | bits_on) &
-                                      ~bits_off);
-}
-static inline void sun4c_init_map_kernelprom(unsigned long kernel_end)
-{
-        unsigned long vaddr;
-        unsigned char pseg, ctx;
-        for (vaddr = KADB_DEBUGGER_BEGVM;
-             vaddr < LINUX_OPPROM_ENDVM;
-             vaddr += SUN4C_REAL_PGDIR_SIZE) {
-                pseg = sun4c_get_segmap(vaddr);
-                if (pseg != invalid_segment) {
-                        mmu_entry_pool[pseg].locked = 1;
-                        for (ctx = 0; ctx < num_contexts; ctx++)
-                                prom_putsegment(ctx, vaddr, pseg);
-                        fix_permissions(vaddr, _SUN4C_PAGE_PRIV, 0);
-                }
-        }
-        for (vaddr = KERNBASE; vaddr < kernel_end; vaddr += SUN4C_REAL_PGDIR_SIZE) {
-                pseg = sun4c_get_segmap(vaddr);
-                mmu_entry_pool[pseg].locked = 1;
-                for (ctx = 0; ctx < num_contexts; ctx++)
-                        prom_putsegment(ctx, vaddr, pseg);
-                fix_permissions(vaddr, _SUN4C_PAGE_PRIV, _SUN4C_PAGE_NOCACHE);
-        }
-}
-static void __init sun4c_init_lock_area(unsigned long start, unsigned long end)
-{
-        int i, ctx;
-        while (start < end) {
-                for (i = 0; i < invalid_segment; i++)
-                        if (!mmu_entry_pool[i].locked)
-                                break;
-                mmu_entry_pool[i].locked = 1;
-                sun4c_init_clean_segmap(i);
-                for (ctx = 0; ctx < num_contexts; ctx++)
-                        prom_putsegment(ctx, start, mmu_entry_pool[i].pseg);
-                start += SUN4C_REAL_PGDIR_SIZE;
-        }
-}
-/* Don't change this struct without changing entry.S. This is used
- * in the in-window kernel fault handler, and you don't want to mess
- * with that. (See sun4c_fault in entry.S).
- */
-struct sun4c_mmu_ring {
-        struct sun4c_mmu_entry ringhd;
-        int num_entries;
-};
-static struct sun4c_mmu_ring sun4c_context_ring[SUN4C_MAX_CONTEXTS]; /* used user entries */
-static struct sun4c_mmu_ring sun4c_ufree_ring;       /* free user entries */
-static struct sun4c_mmu_ring sun4c_ulru_ring;        /* LRU user entries */
-struct sun4c_mmu_ring sun4c_kernel_ring;      /* used kernel entries */
-struct sun4c_mmu_ring sun4c_kfree_ring;       /* free kernel entries */
-static inline void sun4c_init_rings(void)
-{
-        int i;
-        for (i = 0; i < SUN4C_MAX_CONTEXTS; i++) {
-                sun4c_context_ring[i].ringhd.next =
-                        sun4c_context_ring[i].ringhd.prev =
-                        &sun4c_context_ring[i].ringhd;
-                sun4c_context_ring[i].num_entries = 0;
-        }
-        sun4c_ufree_ring.ringhd.next = sun4c_ufree_ring.ringhd.prev =
-                &sun4c_ufree_ring.ringhd;
-        sun4c_ufree_ring.num_entries = 0;
-        sun4c_ulru_ring.ringhd.lru_next = sun4c_ulru_ring.ringhd.lru_prev =
-                &sun4c_ulru_ring.ringhd;
-        sun4c_ulru_ring.num_entries = 0;
-        sun4c_kernel_ring.ringhd.next = sun4c_kernel_ring.ringhd.prev =
-                &sun4c_kernel_ring.ringhd;
-        sun4c_kernel_ring.num_entries = 0;
-        sun4c_kfree_ring.ringhd.next = sun4c_kfree_ring.ringhd.prev =
-                &sun4c_kfree_ring.ringhd;
-        sun4c_kfree_ring.num_entries = 0;
-}
-static void add_ring(struct sun4c_mmu_ring *ring,
-                     struct sun4c_mmu_entry *entry)
-{
-        struct sun4c_mmu_entry *head = &ring->ringhd;
-        entry->prev = head;
-        (entry->next = head->next)->prev = entry;
-        head->next = entry;
-        ring->num_entries++;
-}
-static inline void add_lru(struct sun4c_mmu_entry *entry)
-{
-        struct sun4c_mmu_ring *ring = &sun4c_ulru_ring;
-        struct sun4c_mmu_entry *head = &ring->ringhd;
-        entry->lru_next = head;
-        (entry->lru_prev = head->lru_prev)->lru_next = entry;
-        head->lru_prev = entry;
-}
-static void add_ring_ordered(struct sun4c_mmu_ring *ring,
-                             struct sun4c_mmu_entry *entry)
-{
-        struct sun4c_mmu_entry *head = &ring->ringhd;
-        unsigned long addr = entry->vaddr;
-        while ((head->next != &ring->ringhd) && (head->next->vaddr < addr))
-                head = head->next;
-        entry->prev = head;
-        (entry->next = head->next)->prev = entry;
-        head->next = entry;
-        ring->num_entries++;
-        add_lru(entry);
-}
-static inline void remove_ring(struct sun4c_mmu_ring *ring,
-                                   struct sun4c_mmu_entry *entry)
-{
-        struct sun4c_mmu_entry *next = entry->next;
-        (next->prev = entry->prev)->next = next;
-        ring->num_entries--;
-}
-static void remove_lru(struct sun4c_mmu_entry *entry)
-{
-        struct sun4c_mmu_entry *next = entry->lru_next;
-        (next->lru_prev = entry->lru_prev)->lru_next = next;
-}
-static void free_user_entry(int ctx, struct sun4c_mmu_entry *entry)
-{
-        remove_ring(sun4c_context_ring+ctx, entry);
-        remove_lru(entry);
-        add_ring(&sun4c_ufree_ring, entry);
-}
-static void free_kernel_entry(struct sun4c_mmu_entry *entry,
-                              struct sun4c_mmu_ring *ring)
-{
-        remove_ring(ring, entry);
-        add_ring(&sun4c_kfree_ring, entry);
-}
-static void __init sun4c_init_fill_kernel_ring(int howmany)
-{
-        int i;
-        while (howmany) {
-                for (i = 0; i < invalid_segment; i++)
-                        if (!mmu_entry_pool[i].locked)
-                                break;
-                mmu_entry_pool[i].locked = 1;
-                sun4c_init_clean_segmap(i);
-                add_ring(&sun4c_kfree_ring, &mmu_entry_pool[i]);
-                howmany--;
-        }
-}
-static void __init sun4c_init_fill_user_ring(void)
-{
-        int i;
-        for (i = 0; i < invalid_segment; i++) {
-                if (mmu_entry_pool[i].locked)
-                        continue;
-                sun4c_init_clean_segmap(i);
-                add_ring(&sun4c_ufree_ring, &mmu_entry_pool[i]);
-        }
-}
-static void sun4c_kernel_unmap(struct sun4c_mmu_entry *kentry)
-{
-        int savectx, ctx;
-        savectx = sun4c_get_context();
-        for (ctx = 0; ctx < num_contexts; ctx++) {
-                sun4c_set_context(ctx);
-                sun4c_put_segmap(kentry->vaddr, invalid_segment);
-        }
-        sun4c_set_context(savectx);
-}
-static void sun4c_kernel_map(struct sun4c_mmu_entry *kentry)
-{
-        int savectx, ctx;
-        savectx = sun4c_get_context();
-        for (ctx = 0; ctx < num_contexts; ctx++) {
-                sun4c_set_context(ctx);
-                sun4c_put_segmap(kentry->vaddr, kentry->pseg);
-        }
-        sun4c_set_context(savectx);
-}
-#define sun4c_user_unmap(__entry) \
-        sun4c_put_segmap((__entry)->vaddr, invalid_segment)
-static void sun4c_demap_context(struct sun4c_mmu_ring *crp, unsigned char ctx)
-{
-        struct sun4c_mmu_entry *head = &crp->ringhd;
-        unsigned long flags;
-        local_irq_save(flags);
-        if (head->next != head) {
-                struct sun4c_mmu_entry *entry = head->next;
-                int savectx = sun4c_get_context();
-                flush_user_windows();
-                sun4c_set_context(ctx);
-                sun4c_flush_context();
-                do {
-                        struct sun4c_mmu_entry *next = entry->next;
-                        sun4c_user_unmap(entry);
-                        free_user_entry(ctx, entry);
-                        entry = next;
-                } while (entry != head);
-                sun4c_set_context(savectx);
-        }
-        local_irq_restore(flags);
-}
-static int sun4c_user_taken_entries;  /* This is how much we have.             */
-static int max_user_taken_entries;    /* This limits us and prevents deadlock. */
-static struct sun4c_mmu_entry *sun4c_kernel_strategy(void)
-{
-        struct sun4c_mmu_entry *this_entry;
-        /* If some are free, return first one. */
-        if (sun4c_kfree_ring.num_entries) {
-                this_entry = sun4c_kfree_ring.ringhd.next;
-                return this_entry;
-        }
-        /* Else free one up. */
-        this_entry = sun4c_kernel_ring.ringhd.prev;
-        sun4c_flush_segment(this_entry->vaddr);
-        sun4c_kernel_unmap(this_entry);
-        free_kernel_entry(this_entry, &sun4c_kernel_ring);
-        this_entry = sun4c_kfree_ring.ringhd.next;
-        return this_entry;
-}
-/* Using this method to free up mmu entries eliminates a lot of
- * potential races since we have a kernel that incurs tlb
- * replacement faults.  There may be performance penalties.
- *
- * NOTE: Must be called with interrupts disabled.
- */
-static struct sun4c_mmu_entry *sun4c_user_strategy(void)
-{
-        struct sun4c_mmu_entry *entry;
-        unsigned char ctx;
-        int savectx;
-        /* If some are free, return first one. */
-        if (sun4c_ufree_ring.num_entries) {
-                entry = sun4c_ufree_ring.ringhd.next;
-                goto unlink_out;
-        }
-        if (sun4c_user_taken_entries) {
-                entry = sun4c_kernel_strategy();
-                sun4c_user_taken_entries--;
-                goto kunlink_out;
-        }
-        /* Grab from the beginning of the LRU list. */
-        entry = sun4c_ulru_ring.ringhd.lru_next;
-        ctx = entry->ctx;
-        savectx = sun4c_get_context();
-        flush_user_windows();
-        sun4c_set_context(ctx);
-        sun4c_flush_segment(entry->vaddr);
-        sun4c_user_unmap(entry);
-        remove_ring(sun4c_context_ring + ctx, entry);
-        remove_lru(entry);
-        sun4c_set_context(savectx);
-        return entry;
-unlink_out:
-        remove_ring(&sun4c_ufree_ring, entry);
-        return entry;
-kunlink_out:
-        remove_ring(&sun4c_kfree_ring, entry);
-        return entry;
-}
-/* NOTE: Must be called with interrupts disabled. */
-void sun4c_grow_kernel_ring(void)
-{
-        struct sun4c_mmu_entry *entry;
-        /* Prevent deadlock condition. */
-        if (sun4c_user_taken_entries >= max_user_taken_entries)
-                return;
-        if (sun4c_ufree_ring.num_entries) {
-                entry = sun4c_ufree_ring.ringhd.next;
-                remove_ring(&sun4c_ufree_ring, entry);
-                add_ring(&sun4c_kfree_ring, entry);
-                sun4c_user_taken_entries++;
-        }
-}
-/* 2 page buckets for task struct and kernel stack allocation.
- *
- * TASK_STACK_BEGIN
- * bucket[0]
- * bucket[1]
- *   [ ... ]
- * bucket[NR_TASK_BUCKETS-1]
- * TASK_STACK_BEGIN + (sizeof(struct task_bucket) * NR_TASK_BUCKETS)
- *
- * Each slot looks like:
- *
- *  page 1 --  task struct + beginning of kernel stack
- *  page 2 --  rest of kernel stack
- */
-union task_union *sun4c_bucket[NR_TASK_BUCKETS];
-static int sun4c_lowbucket_avail;
-#define BUCKET_EMPTY     ((union task_union *) 0)
-#define BUCKET_SHIFT     (PAGE_SHIFT + 1)        /* log2(sizeof(struct task_bucket)) */
-#define BUCKET_SIZE      (1 << BUCKET_SHIFT)
-#define BUCKET_NUM(addr) ((((addr) - SUN4C_LOCK_VADDR) >> BUCKET_SHIFT))
-#define BUCKET_ADDR(num) (((num) << BUCKET_SHIFT) + SUN4C_LOCK_VADDR)
-#define BUCKET_PTE(page)       \
-        ((((page) - PAGE_OFFSET) >> PAGE_SHIFT) | pgprot_val(SUN4C_PAGE_KERNEL))
-#define BUCKET_PTE_PAGE(pte)   \
-        (PAGE_OFFSET + (((pte) & SUN4C_PFN_MASK) << PAGE_SHIFT))
-static void get_locked_segment(unsigned long addr)
-{
-        struct sun4c_mmu_entry *stolen;
-        unsigned long flags;
-        local_irq_save(flags);
-        addr &= SUN4C_REAL_PGDIR_MASK;
-        stolen = sun4c_user_strategy();
-        max_user_taken_entries--;
-        stolen->vaddr = addr;
-        flush_user_windows();
-        sun4c_kernel_map(stolen);
-        local_irq_restore(flags);
-}
-static void free_locked_segment(unsigned long addr)
-{
-        struct sun4c_mmu_entry *entry;
-        unsigned long flags;
-        unsigned char pseg;
-        local_irq_save(flags);
-        addr &= SUN4C_REAL_PGDIR_MASK;
-        pseg = sun4c_get_segmap(addr);
-        entry = &mmu_entry_pool[pseg];
-        flush_user_windows();
-        sun4c_flush_segment(addr);
-        sun4c_kernel_unmap(entry);
-        add_ring(&sun4c_ufree_ring, entry);
-        max_user_taken_entries++;
-        local_irq_restore(flags);
-}
-static inline void garbage_collect(int entry)
-{
-        int start, end;
-        /* 32 buckets per segment... */
-        entry &= ~31;
-        start = entry;
-        for (end = (start + 32); start < end; start++)
-                if (sun4c_bucket[start] != BUCKET_EMPTY)
-                        return;
-        /* Entire segment empty, release it. */
-        free_locked_segment(BUCKET_ADDR(entry));
-}
-static struct thread_info *sun4c_alloc_thread_info_node(int node)
-{
-        unsigned long addr, pages;
-        int entry;
-        pages = __get_free_pages(GFP_KERNEL, THREAD_INFO_ORDER);
-        if (!pages)
-                return NULL;
-        for (entry = sun4c_lowbucket_avail; entry < NR_TASK_BUCKETS; entry++)
-                if (sun4c_bucket[entry] == BUCKET_EMPTY)
-                        break;
-        if (entry == NR_TASK_BUCKETS) {
-                free_pages(pages, THREAD_INFO_ORDER);
-                return NULL;
-        }
-        if (entry >= sun4c_lowbucket_avail)
-                sun4c_lowbucket_avail = entry + 1;
-        addr = BUCKET_ADDR(entry);
-        sun4c_bucket[entry] = (union task_union *) addr;
-        if(sun4c_get_segmap(addr) == invalid_segment)
-                get_locked_segment(addr);
-        /* We are changing the virtual color of the page(s)
-         * so we must flush the cache to guarantee consistency.
-         */
-        sun4c_flush_page(pages);
-        sun4c_flush_page(pages + PAGE_SIZE);
-        sun4c_put_pte(addr, BUCKET_PTE(pages));
-        sun4c_put_pte(addr + PAGE_SIZE, BUCKET_PTE(pages + PAGE_SIZE));
-#ifdef CONFIG_DEBUG_STACK_USAGE
-        memset((void *)addr, 0, PAGE_SIZE << THREAD_INFO_ORDER);
-#endif /* DEBUG_STACK_USAGE */
-        return (struct thread_info *) addr;
-}
-static void sun4c_free_thread_info(struct thread_info *ti)
-{
-        unsigned long tiaddr = (unsigned long) ti;
-        unsigned long pages = BUCKET_PTE_PAGE(sun4c_get_pte(tiaddr));
-        int entry = BUCKET_NUM(tiaddr);
-        /* We are deleting a mapping, so the flush here is mandatory. */
-        sun4c_flush_page(tiaddr);
-        sun4c_flush_page(tiaddr + PAGE_SIZE);
-        sun4c_put_pte(tiaddr, 0);
-        sun4c_put_pte(tiaddr + PAGE_SIZE, 0);
-        sun4c_bucket[entry] = BUCKET_EMPTY;
-        if (entry < sun4c_lowbucket_avail)
-                sun4c_lowbucket_avail = entry;
-        free_pages(pages, THREAD_INFO_ORDER);
-        garbage_collect(entry);
-}
-static void __init sun4c_init_buckets(void)
-{
-        int entry;
-        if (sizeof(union thread_union) != (PAGE_SIZE << THREAD_INFO_ORDER)) {
-                extern void thread_info_size_is_bolixed_pete(void);
-                thread_info_size_is_bolixed_pete();
-        }
-        for (entry = 0; entry < NR_TASK_BUCKETS; entry++)
-                sun4c_bucket[entry] = BUCKET_EMPTY;
-        sun4c_lowbucket_avail = 0;
-}
-static unsigned long sun4c_iobuffer_start;
-static unsigned long sun4c_iobuffer_end;
-static unsigned long sun4c_iobuffer_high;
-static unsigned long *sun4c_iobuffer_map;
-static int iobuffer_map_size;
-/*
- * Alias our pages so they do not cause a trap.
- * Also one page may be aliased into several I/O areas and we may
- * finish these I/O separately.
- */
-static char *sun4c_lockarea(char *vaddr, unsigned long size)
-{
-        unsigned long base, scan;
-        unsigned long npages;
-        unsigned long vpage;
-        unsigned long pte;
-        unsigned long apage;
-        unsigned long high;
-        unsigned long flags;
-        npages = (((unsigned long)vaddr & ~PAGE_MASK) +
-                  size + (PAGE_SIZE-1)) >> PAGE_SHIFT;
-        local_irq_save(flags);
-        base = bitmap_find_next_zero_area(sun4c_iobuffer_map, iobuffer_map_size,
-                                                0, npages, 0);
-        if (base >= iobuffer_map_size)
-                goto abend;
-        high = ((base + npages) << PAGE_SHIFT) + sun4c_iobuffer_start;
-        high = SUN4C_REAL_PGDIR_ALIGN(high);
-        while (high > sun4c_iobuffer_high) {
-                get_locked_segment(sun4c_iobuffer_high);
-                sun4c_iobuffer_high += SUN4C_REAL_PGDIR_SIZE;
-        }
-        vpage = ((unsigned long) vaddr) & PAGE_MASK;
-        for (scan = base; scan < base+npages; scan++) {
-                pte = ((vpage-PAGE_OFFSET) >> PAGE_SHIFT);
-                pte |= pgprot_val(SUN4C_PAGE_KERNEL);
-                pte |= _SUN4C_PAGE_NOCACHE;
-                set_bit(scan, sun4c_iobuffer_map);
-                apage = (scan << PAGE_SHIFT) + sun4c_iobuffer_start;
-                /* Flush original mapping so we see the right things later. */
-                sun4c_flush_page(vpage);
-                sun4c_put_pte(apage, pte);
-                vpage += PAGE_SIZE;
-        }
-        local_irq_restore(flags);
-        return (char *) ((base << PAGE_SHIFT) + sun4c_iobuffer_start +
-                         (((unsigned long) vaddr) & ~PAGE_MASK));
-abend:
-        local_irq_restore(flags);
-        printk("DMA vaddr=0x%p size=%08lx\n", vaddr, size);
-        panic("Out of iobuffer table");
-        return NULL;
-}
-static void sun4c_unlockarea(char *vaddr, unsigned long size)
-{
-        unsigned long vpage, npages;
-        unsigned long flags;
-        int scan, high;
-        vpage = (unsigned long)vaddr & PAGE_MASK;
-        npages = (((unsigned long)vaddr & ~PAGE_MASK) +
-                  size + (PAGE_SIZE-1)) >> PAGE_SHIFT;
-        local_irq_save(flags);
-        while (npages != 0) {
-                --npages;
-                /* This mapping is marked non-cachable, no flush necessary. */
-                sun4c_put_pte(vpage, 0);
-                clear_bit((vpage - sun4c_iobuffer_start) >> PAGE_SHIFT,
-                          sun4c_iobuffer_map);
-                vpage += PAGE_SIZE;
-        }
-        /* garbage collect */
-        scan = (sun4c_iobuffer_high - sun4c_iobuffer_start) >> PAGE_SHIFT;
-        while (scan >= 0 && !sun4c_iobuffer_map[scan >> 5])
-                scan -= 32;
-        scan += 32;
-        high = sun4c_iobuffer_start + (scan << PAGE_SHIFT);
-        high = SUN4C_REAL_PGDIR_ALIGN(high) + SUN4C_REAL_PGDIR_SIZE;
-        while (high < sun4c_iobuffer_high) {
-                sun4c_iobuffer_high -= SUN4C_REAL_PGDIR_SIZE;
-                free_locked_segment(sun4c_iobuffer_high);
-        }
-        local_irq_restore(flags);
-}
-/* Note the scsi code at init time passes to here buffers
- * which sit on the kernel stack, those are already locked
- * by implication and fool the page locking code above
- * if passed to by mistake.
- */
-static __u32 sun4c_get_scsi_one(struct device *dev, char *bufptr, unsigned long len)
-{
-        unsigned long page;
-        page = ((unsigned long)bufptr) & PAGE_MASK;
-        if (!virt_addr_valid(page)) {
-                sun4c_flush_page(page);
-                return (__u32)bufptr; /* already locked */
-        }
-        return (__u32)sun4c_lockarea(bufptr, len);
-}
-static void sun4c_get_scsi_sgl(struct device *dev, struct scatterlist *sg, int sz)
-{
-        while (sz != 0) {
-                --sz;
-                sg->dma_address = (__u32)sun4c_lockarea(sg_virt(sg), sg->length);
-                sg->dma_length = sg->length;
-                sg = sg_next(sg);
-        }
-}
-static void sun4c_release_scsi_one(struct device *dev, __u32 bufptr, unsigned long len)
-{
-        if (bufptr < sun4c_iobuffer_start)
-                return; /* On kernel stack or similar, see above */
-        sun4c_unlockarea((char *)bufptr, len);
-}
-static void sun4c_release_scsi_sgl(struct device *dev, struct scatterlist *sg, int sz)
-{
-        while (sz != 0) {
-                --sz;
-                sun4c_unlockarea((char *)sg->dma_address, sg->length);
-                sg = sg_next(sg);
-        }
-}
-#define TASK_ENTRY_SIZE    BUCKET_SIZE /* see above */
-#define LONG_ALIGN(x) (((x)+(sizeof(long))-1)&~((sizeof(long))-1))
-struct vm_area_struct sun4c_kstack_vma;
-static void __init sun4c_init_lock_areas(void)
-{
-        unsigned long sun4c_taskstack_start;
-        unsigned long sun4c_taskstack_end;
-        int bitmap_size;
-        sun4c_init_buckets();
-        sun4c_taskstack_start = SUN4C_LOCK_VADDR;
-        sun4c_taskstack_end = (sun4c_taskstack_start +
-                               (TASK_ENTRY_SIZE * NR_TASK_BUCKETS));
-        if (sun4c_taskstack_end >= SUN4C_LOCK_END) {
-                prom_printf("Too many tasks, decrease NR_TASK_BUCKETS please.\n");
-                prom_halt();
-        }
-        sun4c_iobuffer_start = sun4c_iobuffer_high =
-                                SUN4C_REAL_PGDIR_ALIGN(sun4c_taskstack_end);
-        sun4c_iobuffer_end = SUN4C_LOCK_END;
-        bitmap_size = (sun4c_iobuffer_end - sun4c_iobuffer_start) >> PAGE_SHIFT;
-        bitmap_size = (bitmap_size + 7) >> 3;
-        bitmap_size = LONG_ALIGN(bitmap_size);
-        iobuffer_map_size = bitmap_size << 3;
-        sun4c_iobuffer_map = __alloc_bootmem(bitmap_size, SMP_CACHE_BYTES, 0UL);
-        memset((void *) sun4c_iobuffer_map, 0, bitmap_size);
-        sun4c_kstack_vma.vm_mm = &init_mm;
-        sun4c_kstack_vma.vm_start = sun4c_taskstack_start;
-        sun4c_kstack_vma.vm_end = sun4c_taskstack_end;
-        sun4c_kstack_vma.vm_page_prot = PAGE_SHARED;
-        sun4c_kstack_vma.vm_flags = VM_READ | VM_WRITE | VM_EXEC;
-        insert_vm_struct(&init_mm, &sun4c_kstack_vma);
-}
-/* Cache flushing on the sun4c. */
-static void sun4c_flush_cache_all(void)
-{
-        unsigned long begin, end;
-        flush_user_windows();
-        begin = (KERNBASE + SUN4C_REAL_PGDIR_SIZE);
-        end = (begin + SUN4C_VAC_SIZE);
-        if (sun4c_vacinfo.linesize == 32) {
-                while (begin < end) {
-                        __asm__ __volatile__(
-                        "ld     [%0 + 0x00], %%g0\n\t"
-                        "ld     [%0 + 0x20], %%g0\n\t"
-                        "ld     [%0 + 0x40], %%g0\n\t"
-                        "ld     [%0 + 0x60], %%g0\n\t"
-                        "ld     [%0 + 0x80], %%g0\n\t"
-                        "ld     [%0 + 0xa0], %%g0\n\t"
-                        "ld     [%0 + 0xc0], %%g0\n\t"
-                        "ld     [%0 + 0xe0], %%g0\n\t"
-                        "ld     [%0 + 0x100], %%g0\n\t"
-                        "ld     [%0 + 0x120], %%g0\n\t"
-                        "ld     [%0 + 0x140], %%g0\n\t"
-                        "ld     [%0 + 0x160], %%g0\n\t"
-                        "ld     [%0 + 0x180], %%g0\n\t"
-                        "ld     [%0 + 0x1a0], %%g0\n\t"
-                        "ld     [%0 + 0x1c0], %%g0\n\t"
-                        "ld     [%0 + 0x1e0], %%g0\n"
-                        : : "r" (begin));
-                        begin += 512;
-                }
-        } else {
-                while (begin < end) {
-                        __asm__ __volatile__(
-                        "ld     [%0 + 0x00], %%g0\n\t"
-                        "ld     [%0 + 0x10], %%g0\n\t"
-                        "ld     [%0 + 0x20], %%g0\n\t"
-                        "ld     [%0 + 0x30], %%g0\n\t"
-                        "ld     [%0 + 0x40], %%g0\n\t"
-                        "ld     [%0 + 0x50], %%g0\n\t"
-                        "ld     [%0 + 0x60], %%g0\n\t"
-                        "ld     [%0 + 0x70], %%g0\n\t"
-                        "ld     [%0 + 0x80], %%g0\n\t"
-                        "ld     [%0 + 0x90], %%g0\n\t"
-                        "ld     [%0 + 0xa0], %%g0\n\t"
-                        "ld     [%0 + 0xb0], %%g0\n\t"
-                        "ld     [%0 + 0xc0], %%g0\n\t"
-                        "ld     [%0 + 0xd0], %%g0\n\t"
-                        "ld     [%0 + 0xe0], %%g0\n\t"
-                        "ld     [%0 + 0xf0], %%g0\n"
-                        : : "r" (begin));
-                        begin += 256;
-                }
-        }
-}
-static void sun4c_flush_cache_mm(struct mm_struct *mm)
-{
-        int new_ctx = mm->context;
-        if (new_ctx != NO_CONTEXT) {
-                flush_user_windows();
-                if (sun4c_context_ring[new_ctx].num_entries) {
-                        struct sun4c_mmu_entry *head = &sun4c_context_ring[new_ctx].ringhd;
-                        unsigned long flags;
-                        local_irq_save(flags);
-                        if (head->next != head) {
-                                struct sun4c_mmu_entry *entry = head->next;
-                                int savectx = sun4c_get_context();
-                                sun4c_set_context(new_ctx);
-                                sun4c_flush_context();
-                                do {
-                                        struct sun4c_mmu_entry *next = entry->next;
-                                        sun4c_user_unmap(entry);
-                                        free_user_entry(new_ctx, entry);
-                                        entry = next;
-                                } while (entry != head);
-                                sun4c_set_context(savectx);
-                        }
-                        local_irq_restore(flags);
-                }
-        }
-}
-static void sun4c_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
-{
-        struct mm_struct *mm = vma->vm_mm;
-        int new_ctx = mm->context;
-        if (new_ctx != NO_CONTEXT) {
-                struct sun4c_mmu_entry *head = &sun4c_context_ring[new_ctx].ringhd;
-                struct sun4c_mmu_entry *entry;
-                unsigned long flags;
-                flush_user_windows();
-                local_irq_save(flags);
-                /* All user segmap chains are ordered on entry->vaddr. */
-                for (entry = head->next;
-                     (entry != head) && ((entry->vaddr+SUN4C_REAL_PGDIR_SIZE) < start);
-                     entry = entry->next)
-                        ;
-                /* Tracing various job mixtures showed that this conditional
-                 * only passes ~35% of the time for most worse case situations,
-                 * therefore we avoid all of this gross overhead ~65% of the time.
-                 */
-                if ((entry != head) && (entry->vaddr < end)) {
-                        int octx = sun4c_get_context();
-                        sun4c_set_context(new_ctx);
-                        /* At this point, always, (start >= entry->vaddr) and
-                         * (entry->vaddr < end), once the latter condition
-                         * ceases to hold, or we hit the end of the list, we
-                         * exit the loop.  The ordering of all user allocated
-                         * segmaps makes this all work out so beautifully.
-                         */
-                        do {
-                                struct sun4c_mmu_entry *next = entry->next;
-                                unsigned long realend;
-                                /* "realstart" is always >= entry->vaddr */
-                                realend = entry->vaddr + SUN4C_REAL_PGDIR_SIZE;
-                                if (end < realend)
-                                        realend = end;
-                                if ((realend - entry->vaddr) <= (PAGE_SIZE << 3)) {
-                                        unsigned long page = entry->vaddr;
-                                        while (page < realend) {
-                                                sun4c_flush_page(page);
-                                                page += PAGE_SIZE;
-                                        }
-                                } else {
-                                        sun4c_flush_segment(entry->vaddr);
-                                        sun4c_user_unmap(entry);
-                                        free_user_entry(new_ctx, entry);
-                                }
-                                entry = next;
-                        } while ((entry != head) && (entry->vaddr < end));
-                        sun4c_set_context(octx);
-                }
-                local_irq_restore(flags);
-        }
-}
-static void sun4c_flush_cache_page(struct vm_area_struct *vma, unsigned long page)
-{
-        struct mm_struct *mm = vma->vm_mm;
-        int new_ctx = mm->context;
-        /* Sun4c has no separate I/D caches so cannot optimize for non
-         * text page flushes.
-         */
-        if (new_ctx != NO_CONTEXT) {
-                int octx = sun4c_get_context();
-                unsigned long flags;
-                flush_user_windows();
-                local_irq_save(flags);
-                sun4c_set_context(new_ctx);
-                sun4c_flush_page(page);
-                sun4c_set_context(octx);
-                local_irq_restore(flags);
-        }
-}
-static void sun4c_flush_page_to_ram(unsigned long page)
-{
-        unsigned long flags;
-        local_irq_save(flags);
-        sun4c_flush_page(page);
-        local_irq_restore(flags);
-}
-/* Sun4c cache is unified, both instructions and data live there, so
- * no need to flush the on-stack instructions for new signal handlers.
- */
-static void sun4c_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr)
-{
-}
-/* TLB flushing on the sun4c.  These routines count on the cache
- * flushing code to flush the user register windows so that we need
- * not do so when we get here.
- */
-static void sun4c_flush_tlb_all(void)
-{
-        struct sun4c_mmu_entry *this_entry, *next_entry;
-        unsigned long flags;
-        int savectx, ctx;
-        local_irq_save(flags);
-        this_entry = sun4c_kernel_ring.ringhd.next;
-        savectx = sun4c_get_context();
-        flush_user_windows();
-        while (sun4c_kernel_ring.num_entries) {
-                next_entry = this_entry->next;
-                sun4c_flush_segment(this_entry->vaddr);
-                for (ctx = 0; ctx < num_contexts; ctx++) {
-                        sun4c_set_context(ctx);
-                        sun4c_put_segmap(this_entry->vaddr, invalid_segment);
-                }
-                free_kernel_entry(this_entry, &sun4c_kernel_ring);
-                this_entry = next_entry;
-        }
-        sun4c_set_context(savectx);
-        local_irq_restore(flags);
-}
-static void sun4c_flush_tlb_mm(struct mm_struct *mm)
-{
-        int new_ctx = mm->context;
-        if (new_ctx != NO_CONTEXT) {
-                struct sun4c_mmu_entry *head = &sun4c_context_ring[new_ctx].ringhd;
-                unsigned long flags;
-                local_irq_save(flags);
-                if (head->next != head) {
-                        struct sun4c_mmu_entry *entry = head->next;
-                        int savectx = sun4c_get_context();
-                        sun4c_set_context(new_ctx);
-                        sun4c_flush_context();
-                        do {
-                                struct sun4c_mmu_entry *next = entry->next;
-                                sun4c_user_unmap(entry);
-                                free_user_entry(new_ctx, entry);
-                                entry = next;
-                        } while (entry != head);
-                        sun4c_set_context(savectx);
-                }
-                local_irq_restore(flags);
-        }
-}
-static void sun4c_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
-{
-        struct mm_struct *mm = vma->vm_mm;
-        int new_ctx = mm->context;
-        if (new_ctx != NO_CONTEXT) {
-                struct sun4c_mmu_entry *head = &sun4c_context_ring[new_ctx].ringhd;
-                struct sun4c_mmu_entry *entry;
-                unsigned long flags;
-                local_irq_save(flags);
-                /* See commentary in sun4c_flush_cache_range(). */
-                for (entry = head->next;
-                     (entry != head) && ((entry->vaddr+SUN4C_REAL_PGDIR_SIZE) < start);
-                     entry = entry->next)
-                        ;
-                if ((entry != head) && (entry->vaddr < end)) {
-                        int octx = sun4c_get_context();
-                        sun4c_set_context(new_ctx);
-                        do {
-                                struct sun4c_mmu_entry *next = entry->next;
-                                sun4c_flush_segment(entry->vaddr);
-                                sun4c_user_unmap(entry);
-                                free_user_entry(new_ctx, entry);
-                                entry = next;
-                        } while ((entry != head) && (entry->vaddr < end));
-                        sun4c_set_context(octx);
-                }
-                local_irq_restore(flags);
-        }
-}
-static void sun4c_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
-{
-        struct mm_struct *mm = vma->vm_mm;
-        int new_ctx = mm->context;
-        if (new_ctx != NO_CONTEXT) {
-                int savectx = sun4c_get_context();
-                unsigned long flags;
-                local_irq_save(flags);
-                sun4c_set_context(new_ctx);
-                page &= PAGE_MASK;
-                sun4c_flush_page(page);
-                sun4c_put_pte(page, 0);
-                sun4c_set_context(savectx);
-                local_irq_restore(flags);
-        }
-}
-static inline void sun4c_mapioaddr(unsigned long physaddr, unsigned long virt_addr)
-{
-        unsigned long page_entry, pg_iobits;
-        pg_iobits = _SUN4C_PAGE_PRESENT | _SUN4C_READABLE | _SUN4C_WRITEABLE |
-                    _SUN4C_PAGE_IO | _SUN4C_PAGE_NOCACHE;
-        page_entry = ((physaddr >> PAGE_SHIFT) & SUN4C_PFN_MASK);
-        page_entry |= ((pg_iobits | _SUN4C_PAGE_PRIV) & ~(_SUN4C_PAGE_PRESENT));
-        sun4c_put_pte(virt_addr, page_entry);
-}
-static void sun4c_mapiorange(unsigned int bus, unsigned long xpa,
-    unsigned long xva, unsigned int len)
-{
-        while (len != 0) {
-                len -= PAGE_SIZE;
-                sun4c_mapioaddr(xpa, xva);
-                xva += PAGE_SIZE;
-                xpa += PAGE_SIZE;
-        }
-}
-static void sun4c_unmapiorange(unsigned long virt_addr, unsigned int len)
-{
-        while (len != 0) {
-                len -= PAGE_SIZE;
-                sun4c_put_pte(virt_addr, 0);
-                virt_addr += PAGE_SIZE;
-        }
-}
-static void sun4c_alloc_context(struct mm_struct *old_mm, struct mm_struct *mm)
-{
-        struct ctx_list *ctxp;
-        ctxp = ctx_free.next;
-        if (ctxp != &ctx_free) {
-                remove_from_ctx_list(ctxp);
-                add_to_used_ctxlist(ctxp);
-                mm->context = ctxp->ctx_number;
-                ctxp->ctx_mm = mm;
-                return;
-        }
-        ctxp = ctx_used.next;
-        if (ctxp->ctx_mm == old_mm)
-                ctxp = ctxp->next;
-        remove_from_ctx_list(ctxp);
-        add_to_used_ctxlist(ctxp);
-        ctxp->ctx_mm->context = NO_CONTEXT;
-        ctxp->ctx_mm = mm;
-        mm->context = ctxp->ctx_number;
-        sun4c_demap_context(&sun4c_context_ring[ctxp->ctx_number],
-                               ctxp->ctx_number);
-}
-/* Switch the current MM context. */
-static void sun4c_switch_mm(struct mm_struct *old_mm, struct mm_struct *mm, struct task_struct *tsk, int cpu)
-{
-        struct ctx_list *ctx;
-        int dirty = 0;
-        if (mm->context == NO_CONTEXT) {
-                dirty = 1;
-                sun4c_alloc_context(old_mm, mm);
-        } else {
-                /* Update the LRU ring of contexts. */
-                ctx = ctx_list_pool + mm->context;
-                remove_from_ctx_list(ctx);
-                add_to_used_ctxlist(ctx);
-        }
-        if (dirty || old_mm != mm)
-                sun4c_set_context(mm->context);
-}
-static void sun4c_destroy_context(struct mm_struct *mm)
-{
-        struct ctx_list *ctx_old;
-        if (mm->context != NO_CONTEXT) {
-                sun4c_demap_context(&sun4c_context_ring[mm->context], mm->context);
-                ctx_old = ctx_list_pool + mm->context;
-                remove_from_ctx_list(ctx_old);
-                add_to_free_ctxlist(ctx_old);
-                mm->context = NO_CONTEXT;
-        }
-}
-static void sun4c_mmu_info(struct seq_file *m)
-{
-        int used_user_entries, i;
-        used_user_entries = 0;
-        for (i = 0; i < num_contexts; i++)
-                used_user_entries += sun4c_context_ring[i].num_entries;
-        seq_printf(m, 
-                   "vacsize\t\t: %d bytes\n"
-                   "vachwflush\t: %s\n"
-                   "vaclinesize\t: %d bytes\n"
-                   "mmuctxs\t\t: %d\n"
-                   "mmupsegs\t: %d\n"
-                   "kernelpsegs\t: %d\n"
-                   "kfreepsegs\t: %d\n"
-                   "usedpsegs\t: %d\n"
-                   "ufreepsegs\t: %d\n"
-                   "user_taken\t: %d\n"
-                   "max_taken\t: %d\n",
-                   sun4c_vacinfo.num_bytes,
-                   (sun4c_vacinfo.do_hwflushes ? "yes" : "no"),
-                   sun4c_vacinfo.linesize,
-                   num_contexts,
-                   (invalid_segment + 1),
-                   sun4c_kernel_ring.num_entries,
-                   sun4c_kfree_ring.num_entries,
-                   used_user_entries,
-                   sun4c_ufree_ring.num_entries,
-                   sun4c_user_taken_entries,
-                   max_user_taken_entries);
-}
-/* Nothing below here should touch the mmu hardware nor the mmu_entry
- * data structures.
- */
-/* First the functions which the mid-level code uses to directly
- * manipulate the software page tables.  Some defines since we are
- * emulating the i386 page directory layout.
- */
-#define PGD_PRESENT  0x001
-#define PGD_RW       0x002
-#define PGD_USER     0x004
-#define PGD_ACCESSED 0x020
-#define PGD_DIRTY    0x040
-#define PGD_TABLE    (PGD_PRESENT | PGD_RW | PGD_USER | PGD_ACCESSED | PGD_DIRTY)
-static void sun4c_set_pte(pte_t *ptep, pte_t pte)
-{
-        *ptep = pte;
-}
-static void sun4c_pgd_set(pgd_t * pgdp, pmd_t * pmdp)
-{
-}
-static void sun4c_pmd_set(pmd_t * pmdp, pte_t * ptep)
-{
-        pmdp->pmdv[0] = PGD_TABLE | (unsigned long) ptep;
-}
-static void sun4c_pmd_populate(pmd_t * pmdp, struct page * ptep)
-{
-        if (page_address(ptep) == NULL) BUG();  /* No highmem on sun4c */
-        pmdp->pmdv[0] = PGD_TABLE | (unsigned long) page_address(ptep);
-}
-static int sun4c_pte_present(pte_t pte)
-{
-        return ((pte_val(pte) & (_SUN4C_PAGE_PRESENT | _SUN4C_PAGE_PRIV)) != 0);
-}
-static void sun4c_pte_clear(pte_t *ptep)        { *ptep = __pte(0); }
-static int sun4c_pmd_bad(pmd_t pmd)
-{
-        return (((pmd_val(pmd) & ~PAGE_MASK) != PGD_TABLE) ||
-                (!virt_addr_valid(pmd_val(pmd))));
-}
-static int sun4c_pmd_present(pmd_t pmd)
-{
-        return ((pmd_val(pmd) & PGD_PRESENT) != 0);
-}
-#if 0 /* if PMD takes one word */
-static void sun4c_pmd_clear(pmd_t *pmdp)        { *pmdp = __pmd(0); }
-#else /* if pmd_t is a longish aggregate */
-static void sun4c_pmd_clear(pmd_t *pmdp) {
-        memset((void *)pmdp, 0, sizeof(pmd_t));
-}
-#endif
-static int sun4c_pgd_none(pgd_t pgd)            { return 0; }
-static int sun4c_pgd_bad(pgd_t pgd)             { return 0; }
-static int sun4c_pgd_present(pgd_t pgd)         { return 1; }
-static void sun4c_pgd_clear(pgd_t * pgdp)       { }
-/*
- * The following only work if pte_present() is true.
- * Undefined behaviour if not..
- */
-static pte_t sun4c_pte_mkwrite(pte_t pte)
-{
-        pte = __pte(pte_val(pte) | _SUN4C_PAGE_WRITE);
-        if (pte_val(pte) & _SUN4C_PAGE_MODIFIED)
-                pte = __pte(pte_val(pte) | _SUN4C_PAGE_SILENT_WRITE);
-        return pte;
-}
-static pte_t sun4c_pte_mkdirty(pte_t pte)
-{
-        pte = __pte(pte_val(pte) | _SUN4C_PAGE_MODIFIED);
-        if (pte_val(pte) & _SUN4C_PAGE_WRITE)
-                pte = __pte(pte_val(pte) | _SUN4C_PAGE_SILENT_WRITE);
-        return pte;
-}
-static pte_t sun4c_pte_mkyoung(pte_t pte)
-{
-        pte = __pte(pte_val(pte) | _SUN4C_PAGE_ACCESSED);
-        if (pte_val(pte) & _SUN4C_PAGE_READ)
-                pte = __pte(pte_val(pte) | _SUN4C_PAGE_SILENT_READ);
-        return pte;
-}
-/*
- * Conversion functions: convert a page and protection to a page entry,
- * and a page entry and page directory to the page they refer to.
- */
-static pte_t sun4c_mk_pte(struct page *page, pgprot_t pgprot)
-{
-        return __pte(page_to_pfn(page) | pgprot_val(pgprot));
-}
-static pte_t sun4c_mk_pte_phys(unsigned long phys_page, pgprot_t pgprot)
-{
-        return __pte((phys_page >> PAGE_SHIFT) | pgprot_val(pgprot));
-}
-static pte_t sun4c_mk_pte_io(unsigned long page, pgprot_t pgprot, int space)
-{
-        return __pte(((page - PAGE_OFFSET) >> PAGE_SHIFT) | pgprot_val(pgprot));
-}
-static unsigned long sun4c_pte_pfn(pte_t pte)
-{
-        return pte_val(pte) & SUN4C_PFN_MASK;
-}
-static pte_t sun4c_pgoff_to_pte(unsigned long pgoff)
-{
-        return __pte(pgoff | _SUN4C_PAGE_FILE);
-}
-static unsigned long sun4c_pte_to_pgoff(pte_t pte)
-{
-        return pte_val(pte) & ((1UL << PTE_FILE_MAX_BITS) - 1);
-}
-static inline unsigned long sun4c_pmd_page_v(pmd_t pmd)
-{
-        return (pmd_val(pmd) & PAGE_MASK);
-}
-static struct page *sun4c_pmd_page(pmd_t pmd)
-{
-        return virt_to_page(sun4c_pmd_page_v(pmd));
-}
-static unsigned long sun4c_pgd_page(pgd_t pgd) { return 0; }
-/* to find an entry in a page-table-directory */
-static inline pgd_t *sun4c_pgd_offset(struct mm_struct * mm, unsigned long address)
-{
-        return mm->pgd + (address >> SUN4C_PGDIR_SHIFT);
-}
-/* Find an entry in the second-level page table.. */
-static pmd_t *sun4c_pmd_offset(pgd_t * dir, unsigned long address)
-{
-        return (pmd_t *) dir;
-}
-/* Find an entry in the third-level page table.. */ 
-pte_t *sun4c_pte_offset_kernel(pmd_t * dir, unsigned long address)
-{
-        return (pte_t *) sun4c_pmd_page_v(*dir) +
-                        ((address >> PAGE_SHIFT) & (SUN4C_PTRS_PER_PTE - 1));
-}
-static unsigned long sun4c_swp_type(swp_entry_t entry)
-{
-        return (entry.val & SUN4C_SWP_TYPE_MASK);
-}
-static unsigned long sun4c_swp_offset(swp_entry_t entry)
-{
-        return (entry.val >> SUN4C_SWP_OFF_SHIFT) & SUN4C_SWP_OFF_MASK;
-}
-static swp_entry_t sun4c_swp_entry(unsigned long type, unsigned long offset)
-{
-        return (swp_entry_t) {
-                  (offset & SUN4C_SWP_OFF_MASK) << SUN4C_SWP_OFF_SHIFT
-                | (type & SUN4C_SWP_TYPE_MASK) };
-}
-static void sun4c_free_pte_slow(pte_t *pte)
-{
-        free_page((unsigned long)pte);
-}
-static void sun4c_free_pgd_slow(pgd_t *pgd)
-{
-        free_page((unsigned long)pgd);
-}
-static pgd_t *sun4c_get_pgd_fast(void)
-{
-        unsigned long *ret;
-        if ((ret = pgd_quicklist) != NULL) {
-                pgd_quicklist = (unsigned long *)(*ret);
-                ret[0] = ret[1];
-                pgtable_cache_size--;
-        } else {
-                pgd_t *init;
-                
-                ret = (unsigned long *)__get_free_page(GFP_KERNEL);
-                memset (ret, 0, (KERNBASE / SUN4C_PGDIR_SIZE) * sizeof(pgd_t));
-                init = sun4c_pgd_offset(&init_mm, 0);
-                memcpy (((pgd_t *)ret) + USER_PTRS_PER_PGD, init + USER_PTRS_PER_PGD,
-                        (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
-        }
-        return (pgd_t *)ret;
-}
-static void sun4c_free_pgd_fast(pgd_t *pgd)
-{
-        *(unsigned long *)pgd = (unsigned long) pgd_quicklist;
-        pgd_quicklist = (unsigned long *) pgd;
-        pgtable_cache_size++;
-}
-static inline pte_t *
-sun4c_pte_alloc_one_fast(struct mm_struct *mm, unsigned long address)
-{
-        unsigned long *ret;
-        if ((ret = (unsigned long *)pte_quicklist) != NULL) {
-                pte_quicklist = (unsigned long *)(*ret);
-                ret[0] = ret[1];
-                pgtable_cache_size--;
-        }
-        return (pte_t *)ret;
-}
-static pte_t *sun4c_pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address)
-{
-        pte_t *pte;
-        if ((pte = sun4c_pte_alloc_one_fast(mm, address)) != NULL)
-                return pte;
-        pte = (pte_t *)get_zeroed_page(GFP_KERNEL|__GFP_REPEAT);
-        return pte;
-}
-static pgtable_t sun4c_pte_alloc_one(struct mm_struct *mm, unsigned long address)
-{
-        pte_t *pte;
-        struct page *page;
-        pte = sun4c_pte_alloc_one_kernel(mm, address);
-        if (pte == NULL)
-                return NULL;
-        page = virt_to_page(pte);
-        pgtable_page_ctor(page);
-        return page;
-}
-static inline void sun4c_free_pte_fast(pte_t *pte)
-{
-        *(unsigned long *)pte = (unsigned long) pte_quicklist;
-        pte_quicklist = (unsigned long *) pte;
-        pgtable_cache_size++;
-}
-static void sun4c_pte_free(pgtable_t pte)
-{
-        pgtable_page_dtor(pte);
-        sun4c_free_pte_fast(page_address(pte));
-}
-/*
- * allocating and freeing a pmd is trivial: the 1-entry pmd is
- * inside the pgd, so has no extra memory associated with it.
- */
-static pmd_t *sun4c_pmd_alloc_one(struct mm_struct *mm, unsigned long address)
-{
-        BUG();
-        return NULL;
-}
-static void sun4c_free_pmd_fast(pmd_t * pmd) { }
-static void sun4c_check_pgt_cache(int low, int high)
-{
-        if (pgtable_cache_size > high) {
-                do {
-                        if (pgd_quicklist)
-                                sun4c_free_pgd_slow(sun4c_get_pgd_fast());
-                        if (pte_quicklist)
-                                sun4c_free_pte_slow(sun4c_pte_alloc_one_fast(NULL, 0));
-                } while (pgtable_cache_size > low);
-        }
-}
-/* An experiment, turn off by default for now... -DaveM */
-#define SUN4C_PRELOAD_PSEG
-void sun4c_update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
-{
-        unsigned long flags;
-        int pseg;
-        if (vma->vm_mm->context == NO_CONTEXT)
-                return;
-        local_irq_save(flags);
-        address &= PAGE_MASK;
-        if ((pseg = sun4c_get_segmap(address)) == invalid_segment) {
-                struct sun4c_mmu_entry *entry = sun4c_user_strategy();
-                struct mm_struct *mm = vma->vm_mm;
-                unsigned long start, end;
-                entry->vaddr = start = (address & SUN4C_REAL_PGDIR_MASK);
-                entry->ctx = mm->context;
-                add_ring_ordered(sun4c_context_ring + mm->context, entry);
-                sun4c_put_segmap(entry->vaddr, entry->pseg);
-                end = start + SUN4C_REAL_PGDIR_SIZE;
-                while (start < end) {
-#ifdef SUN4C_PRELOAD_PSEG
-                        pgd_t *pgdp = sun4c_pgd_offset(mm, start);
-                        pte_t *ptep;
-                        if (!pgdp)
-                                goto no_mapping;
-                        ptep = sun4c_pte_offset_kernel((pmd_t *) pgdp, start);
-                        if (!ptep || !(pte_val(*ptep) & _SUN4C_PAGE_PRESENT))
-                                goto no_mapping;
-                        sun4c_put_pte(start, pte_val(*ptep));
-                        goto next;
-                no_mapping:
-#endif
-                        sun4c_put_pte(start, 0);
-#ifdef SUN4C_PRELOAD_PSEG
-                next:
-#endif
-                        start += PAGE_SIZE;
-                }
-#ifndef SUN4C_PRELOAD_PSEG
-                sun4c_put_pte(address, pte_val(*ptep));
-#endif
-                local_irq_restore(flags);
-                return;
-        } else {
-                struct sun4c_mmu_entry *entry = &mmu_entry_pool[pseg];
-                remove_lru(entry);
-                add_lru(entry);
-        }
-        sun4c_put_pte(address, pte_val(*ptep));
-        local_irq_restore(flags);
-}
-extern void sparc_context_init(int);
-extern unsigned long bootmem_init(unsigned long *pages_avail);
-extern unsigned long last_valid_pfn;
-void __init sun4c_paging_init(void)
-{
-        int i, cnt;
-        unsigned long kernel_end, vaddr;
-        extern struct resource sparc_iomap;
-        unsigned long end_pfn, pages_avail;
-        kernel_end = (unsigned long) &_end;
-        kernel_end = SUN4C_REAL_PGDIR_ALIGN(kernel_end);
-        pages_avail = 0;
-        last_valid_pfn = bootmem_init(&pages_avail);
-        end_pfn = last_valid_pfn;
-        sun4c_probe_mmu();
-        invalid_segment = (num_segmaps - 1);
-        sun4c_init_mmu_entry_pool();
-        sun4c_init_rings();
-        sun4c_init_map_kernelprom(kernel_end);
-        sun4c_init_clean_mmu(kernel_end);
-        sun4c_init_fill_kernel_ring(SUN4C_KERNEL_BUCKETS);
-        sun4c_init_lock_area(sparc_iomap.start, IOBASE_END);
-        sun4c_init_lock_area(DVMA_VADDR, DVMA_END);
-        sun4c_init_lock_areas();
-        sun4c_init_fill_user_ring();
-        sun4c_set_context(0);
-        memset(swapper_pg_dir, 0, PAGE_SIZE);
-        memset(pg0, 0, PAGE_SIZE);
-        memset(pg1, 0, PAGE_SIZE);
-        memset(pg2, 0, PAGE_SIZE);
-        memset(pg3, 0, PAGE_SIZE);
-        /* Save work later. */
-        vaddr = VMALLOC_START;
-        swapper_pg_dir[vaddr>>SUN4C_PGDIR_SHIFT] = __pgd(PGD_TABLE | (unsigned long) pg0);
-        vaddr += SUN4C_PGDIR_SIZE;
-        swapper_pg_dir[vaddr>>SUN4C_PGDIR_SHIFT] = __pgd(PGD_TABLE | (unsigned long) pg1);
-        vaddr += SUN4C_PGDIR_SIZE;
-        swapper_pg_dir[vaddr>>SUN4C_PGDIR_SHIFT] = __pgd(PGD_TABLE | (unsigned long) pg2);
-        vaddr += SUN4C_PGDIR_SIZE;
-        swapper_pg_dir[vaddr>>SUN4C_PGDIR_SHIFT] = __pgd(PGD_TABLE | (unsigned long) pg3);
-        sun4c_init_ss2_cache_bug();
-        sparc_context_init(num_contexts);
-        {
-                unsigned long zones_size[MAX_NR_ZONES];
-                unsigned long zholes_size[MAX_NR_ZONES];
-                unsigned long npages;
-                int znum;
-                for (znum = 0; znum < MAX_NR_ZONES; znum++)
-                        zones_size[znum] = zholes_size[znum] = 0;
-                npages = max_low_pfn - pfn_base;
-                zones_size[ZONE_DMA] = npages;
-                zholes_size[ZONE_DMA] = npages - pages_avail;
-                npages = highend_pfn - max_low_pfn;
-                zones_size[ZONE_HIGHMEM] = npages;
-                zholes_size[ZONE_HIGHMEM] = npages - calc_highpages();
-                free_area_init_node(0, zones_size, pfn_base, zholes_size);
-        }
-        cnt = 0;
-        for (i = 0; i < num_segmaps; i++)
-                if (mmu_entry_pool[i].locked)
-                        cnt++;
-        max_user_taken_entries = num_segmaps - cnt - 40 - 1;
-        printk("SUN4C: %d mmu entries for the kernel\n", cnt);
-}
-static pgprot_t sun4c_pgprot_noncached(pgprot_t prot)
-{
-        prot |= __pgprot(_SUN4C_PAGE_IO | _SUN4C_PAGE_NOCACHE);
-        return prot;
-}
-/* Load up routines and constants for sun4c mmu */
-void __init ld_mmu_sun4c(void)
-{
-        extern void ___xchg32_sun4c(void);
-        
-        printk("Loading sun4c MMU routines\n");
-        /* First the constants */
-        BTFIXUPSET_SIMM13(pgdir_shift, SUN4C_PGDIR_SHIFT);
-        BTFIXUPSET_SETHI(pgdir_size, SUN4C_PGDIR_SIZE);
-        BTFIXUPSET_SETHI(pgdir_mask, SUN4C_PGDIR_MASK);
-        BTFIXUPSET_SIMM13(ptrs_per_pmd, SUN4C_PTRS_PER_PMD);
-        BTFIXUPSET_SIMM13(ptrs_per_pgd, SUN4C_PTRS_PER_PGD);
-        BTFIXUPSET_SIMM13(user_ptrs_per_pgd, KERNBASE / SUN4C_PGDIR_SIZE);
-        BTFIXUPSET_INT(page_none, pgprot_val(SUN4C_PAGE_NONE));
-        PAGE_SHARED = pgprot_val(SUN4C_PAGE_SHARED);
-        BTFIXUPSET_INT(page_copy, pgprot_val(SUN4C_PAGE_COPY));
-        BTFIXUPSET_INT(page_readonly, pgprot_val(SUN4C_PAGE_READONLY));
-        BTFIXUPSET_INT(page_kernel, pgprot_val(SUN4C_PAGE_KERNEL));
-        page_kernel = pgprot_val(SUN4C_PAGE_KERNEL);
-        /* Functions */
-        BTFIXUPSET_CALL(pgprot_noncached, sun4c_pgprot_noncached, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(___xchg32, ___xchg32_sun4c, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(do_check_pgt_cache, sun4c_check_pgt_cache, BTFIXUPCALL_NORM);
-        
-        BTFIXUPSET_CALL(flush_cache_all, sun4c_flush_cache_all, BTFIXUPCALL_NORM);
-        if (sun4c_vacinfo.do_hwflushes) {
-                BTFIXUPSET_CALL(sun4c_flush_page, sun4c_flush_page_hw, BTFIXUPCALL_NORM);
-                BTFIXUPSET_CALL(sun4c_flush_segment, sun4c_flush_segment_hw, BTFIXUPCALL_NORM);
-                BTFIXUPSET_CALL(sun4c_flush_context, sun4c_flush_context_hw, BTFIXUPCALL_NORM);
-        } else {
-                BTFIXUPSET_CALL(sun4c_flush_page, sun4c_flush_page_sw, BTFIXUPCALL_NORM);
-                BTFIXUPSET_CALL(sun4c_flush_segment, sun4c_flush_segment_sw, BTFIXUPCALL_NORM);
-                BTFIXUPSET_CALL(sun4c_flush_context, sun4c_flush_context_sw, BTFIXUPCALL_NORM);
-        }
-        BTFIXUPSET_CALL(flush_tlb_mm, sun4c_flush_tlb_mm, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(flush_cache_mm, sun4c_flush_cache_mm, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(destroy_context, sun4c_destroy_context, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(switch_mm, sun4c_switch_mm, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(flush_cache_page, sun4c_flush_cache_page, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(flush_tlb_page, sun4c_flush_tlb_page, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(flush_tlb_range, sun4c_flush_tlb_range, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(flush_cache_range, sun4c_flush_cache_range, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(__flush_page_to_ram, sun4c_flush_page_to_ram, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(flush_tlb_all, sun4c_flush_tlb_all, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(flush_sig_insns, sun4c_flush_sig_insns, BTFIXUPCALL_NOP);
-        BTFIXUPSET_CALL(set_pte, sun4c_set_pte, BTFIXUPCALL_STO1O0);
-        BTFIXUPSET_CALL(pte_pfn, sun4c_pte_pfn, BTFIXUPCALL_NORM);
-#if 0 /* PAGE_SHIFT <= 12 */ /* Eek. Investigate. XXX */
-        BTFIXUPSET_CALL(pmd_page, sun4c_pmd_page, BTFIXUPCALL_ANDNINT(PAGE_SIZE - 1));
-#else
-        BTFIXUPSET_CALL(pmd_page, sun4c_pmd_page, BTFIXUPCALL_NORM);
-#endif
-        BTFIXUPSET_CALL(pmd_set, sun4c_pmd_set, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(pmd_populate, sun4c_pmd_populate, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(pte_present, sun4c_pte_present, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(pte_clear, sun4c_pte_clear, BTFIXUPCALL_STG0O0);
-        BTFIXUPSET_CALL(pmd_bad, sun4c_pmd_bad, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(pmd_present, sun4c_pmd_present, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(pmd_clear, sun4c_pmd_clear, BTFIXUPCALL_STG0O0);
-        BTFIXUPSET_CALL(pgd_none, sun4c_pgd_none, BTFIXUPCALL_RETINT(0));
-        BTFIXUPSET_CALL(pgd_bad, sun4c_pgd_bad, BTFIXUPCALL_RETINT(0));
-        BTFIXUPSET_CALL(pgd_present, sun4c_pgd_present, BTFIXUPCALL_RETINT(1));
-        BTFIXUPSET_CALL(pgd_clear, sun4c_pgd_clear, BTFIXUPCALL_NOP);
-        BTFIXUPSET_CALL(mk_pte, sun4c_mk_pte, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(mk_pte_phys, sun4c_mk_pte_phys, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(mk_pte_io, sun4c_mk_pte_io, BTFIXUPCALL_NORM);
-        BTFIXUPSET_INT(pte_modify_mask, _SUN4C_PAGE_CHG_MASK);
-        BTFIXUPSET_CALL(pmd_offset, sun4c_pmd_offset, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(pte_offset_kernel, sun4c_pte_offset_kernel, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(free_pte_fast, sun4c_free_pte_fast, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(pte_free, sun4c_pte_free, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(pte_alloc_one_kernel, sun4c_pte_alloc_one_kernel, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(pte_alloc_one, sun4c_pte_alloc_one, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(free_pmd_fast, sun4c_free_pmd_fast, BTFIXUPCALL_NOP);
-        BTFIXUPSET_CALL(pmd_alloc_one, sun4c_pmd_alloc_one, BTFIXUPCALL_RETO0);
-        BTFIXUPSET_CALL(free_pgd_fast, sun4c_free_pgd_fast, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(get_pgd_fast, sun4c_get_pgd_fast, BTFIXUPCALL_NORM);
-        BTFIXUPSET_HALF(pte_writei, _SUN4C_PAGE_WRITE);
-        BTFIXUPSET_HALF(pte_dirtyi, _SUN4C_PAGE_MODIFIED);
-        BTFIXUPSET_HALF(pte_youngi, _SUN4C_PAGE_ACCESSED);
-        BTFIXUPSET_HALF(pte_filei, _SUN4C_PAGE_FILE);
-        BTFIXUPSET_HALF(pte_wrprotecti, _SUN4C_PAGE_WRITE|_SUN4C_PAGE_SILENT_WRITE);
-        BTFIXUPSET_HALF(pte_mkcleani, _SUN4C_PAGE_MODIFIED|_SUN4C_PAGE_SILENT_WRITE);
-        BTFIXUPSET_HALF(pte_mkoldi, _SUN4C_PAGE_ACCESSED|_SUN4C_PAGE_SILENT_READ);
-        BTFIXUPSET_CALL(pte_mkwrite, sun4c_pte_mkwrite, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(pte_mkdirty, sun4c_pte_mkdirty, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(pte_mkyoung, sun4c_pte_mkyoung, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(update_mmu_cache, sun4c_update_mmu_cache, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(pte_to_pgoff, sun4c_pte_to_pgoff, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(pgoff_to_pte, sun4c_pgoff_to_pte, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(mmu_lockarea, sun4c_lockarea, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(mmu_unlockarea, sun4c_unlockarea, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(mmu_get_scsi_one, sun4c_get_scsi_one, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(mmu_get_scsi_sgl, sun4c_get_scsi_sgl, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(mmu_release_scsi_one, sun4c_release_scsi_one, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(mmu_release_scsi_sgl, sun4c_release_scsi_sgl, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(mmu_map_dma_area, sun4c_map_dma_area, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(mmu_unmap_dma_area, sun4c_unmap_dma_area, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(sparc_mapiorange, sun4c_mapiorange, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(sparc_unmapiorange, sun4c_unmapiorange, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(__swp_type, sun4c_swp_type, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(__swp_offset, sun4c_swp_offset, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(__swp_entry, sun4c_swp_entry, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(alloc_thread_info_node, sun4c_alloc_thread_info_node, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(free_thread_info, sun4c_free_thread_info, BTFIXUPCALL_NORM);
-        BTFIXUPSET_CALL(mmu_info, sun4c_mmu_info, BTFIXUPCALL_NORM);
-        /* These should _never_ get called with two level tables. */
-        BTFIXUPSET_CALL(pgd_set, sun4c_pgd_set, BTFIXUPCALL_NOP);
-        BTFIXUPSET_CALL(pgd_page_vaddr, sun4c_pgd_page, BTFIXUPCALL_RETO0);
-}
diff --git a/arch/sparc/mm/ultra.S b/arch/sparc/mm/ultra.S
index b57a5942ba64..874162a11ceb 100644
--- a/arch/sparc/mm/ultra.S
+++ b/arch/sparc/mm/ultra.S
@@ -495,11 +495,11 @@ xcall_fetch_glob_regs:
        stx             %o7, [%g1 + GR_SNAP_O7]
        stx             %i7, [%g1 + GR_SNAP_I7]
        /* Don't try this at home kids... */
-        rdpr            %cwp, %g2
+        rdpr            %cwp, %g3
-        sub             %g2, 1, %g7
+        sub             %g3, 1, %g7
        wrpr            %g7, %cwp
        mov             %i7, %g7
-        wrpr            %g2, %cwp
+        wrpr            %g3, %cwp
        stx             %g7, [%g1 + GR_SNAP_RPC]
        sethi           %hi(trap_block), %g7
        or              %g7, %lo(trap_block), %g7
diff --git a/arch/sparc/mm/viking.S b/arch/sparc/mm/viking.S
index 6dfcc13d3100..bf8ee0613ae7 100644
--- a/arch/sparc/mm/viking.S
+++ b/arch/sparc/mm/viking.S
@@ -14,7 +14,6 @@
 #include <asm/page.h>
 #include <asm/pgtsrmmu.h>
 #include <asm/viking.h>
-#include <asm/btfixup.h>
 #ifdef CONFIG_SMP
        .data
diff --git a/arch/sparc/net/Makefile b/arch/sparc/net/Makefile
new file mode 100644
index 000000000000..1306a58ac541
--- /dev/null
+++ b/arch/sparc/net/Makefile
@@ -0,0 +1,4 @@
+#
+# Arch-specific network modules
+#
+obj-$(CONFIG_BPF_JIT) += bpf_jit_asm.o bpf_jit_comp.o
diff --git a/arch/sparc/net/bpf_jit.h b/arch/sparc/net/bpf_jit.h
new file mode 100644
index 000000000000..33d6b375ff12
--- /dev/null
+++ b/arch/sparc/net/bpf_jit.h
@@ -0,0 +1,68 @@
+#ifndef _BPF_JIT_H
+#define _BPF_JIT_H
+/* Conventions:
+ *  %g1 : temporary
+ *  %g2 : Secondary temporary used by SKB data helper stubs.
+ *  %g3 : packet offset passed into SKB data helper stubs.
+ *  %o0 : pointer to skb (first argument given to JIT function)
+ *  %o1 : BPF A accumulator
+ *  %o2 : BPF X accumulator
+ *  %o3 : Holds saved %o7 so we can call helper functions without needing
+ *        to allocate a register window.
+ *  %o4 : skb->len - skb->data_len
+ *  %o5 : skb->data
+ */
+#ifndef __ASSEMBLER__
+#define G0              0x00
+#define G1              0x01
+#define G3              0x03
+#define G6              0x06
+#define O0              0x08
+#define O1              0x09
+#define O2              0x0a
+#define O3              0x0b
+#define O4              0x0c
+#define O5              0x0d
+#define SP              0x0e
+#define O7              0x0f
+#define FP              0x1e
+#define r_SKB           O0
+#define r_A             O1
+#define r_X             O2
+#define r_saved_O7      O3
+#define r_HEADLEN       O4
+#define r_SKB_DATA      O5
+#define r_TMP           G1
+#define r_TMP2          G2
+#define r_OFF           G3
+/* assembly code in arch/sparc/net/bpf_jit_asm.S */
+extern u32 bpf_jit_load_word[];
+extern u32 bpf_jit_load_half[];
+extern u32 bpf_jit_load_byte[];
+extern u32 bpf_jit_load_byte_msh[];
+extern u32 bpf_jit_load_word_positive_offset[];
+extern u32 bpf_jit_load_half_positive_offset[];
+extern u32 bpf_jit_load_byte_positive_offset[];
+extern u32 bpf_jit_load_byte_msh_positive_offset[];
+extern u32 bpf_jit_load_word_negative_offset[];
+extern u32 bpf_jit_load_half_negative_offset[];
+extern u32 bpf_jit_load_byte_negative_offset[];
+extern u32 bpf_jit_load_byte_msh_negative_offset[];
+#else
+#define r_SKB           %o0
+#define r_A             %o1
+#define r_X             %o2
+#define r_saved_O7      %o3
+#define r_HEADLEN       %o4
+#define r_SKB_DATA      %o5
+#define r_TMP           %g1
+#define r_TMP2          %g2
+#define r_OFF           %g3
+#endif
+#endif /* _BPF_JIT_H */
diff --git a/arch/sparc/net/bpf_jit_asm.S b/arch/sparc/net/bpf_jit_asm.S
new file mode 100644
index 000000000000..9d016c7017f7
--- /dev/null
+++ b/arch/sparc/net/bpf_jit_asm.S
@@ -0,0 +1,205 @@
+#include <asm/ptrace.h>
+#include "bpf_jit.h"
+#ifdef CONFIG_SPARC64
+#define SAVE_SZ         176
+#define SCRATCH_OFF     STACK_BIAS + 128
+#define BE_PTR(label)   be,pn %xcc, label
+#else
+#define SAVE_SZ         96
+#define SCRATCH_OFF     72
+#define BE_PTR(label)   be label
+#endif
+#define SKF_MAX_NEG_OFF (-0x200000) /* SKF_LL_OFF from filter.h */
+        .text
+        .globl  bpf_jit_load_word
+bpf_jit_load_word:
+        cmp     r_OFF, 0
+        bl      bpf_slow_path_word_neg
+         nop
+        .globl  bpf_jit_load_word_positive_offset
+bpf_jit_load_word_positive_offset:
+        sub     r_HEADLEN, r_OFF, r_TMP
+        cmp     r_TMP, 3
+        ble     bpf_slow_path_word
+         add    r_SKB_DATA, r_OFF, r_TMP
+        andcc   r_TMP, 3, %g0
+        bne     load_word_unaligned
+         nop
+        retl
+         ld     [r_TMP], r_A
+load_word_unaligned:
+        ldub    [r_TMP + 0x0], r_OFF
+        ldub    [r_TMP + 0x1], r_TMP2
+        sll     r_OFF, 8, r_OFF
+        or      r_OFF, r_TMP2, r_OFF
+        ldub    [r_TMP + 0x2], r_TMP2
+        sll     r_OFF, 8, r_OFF
+        or      r_OFF, r_TMP2, r_OFF
+        ldub    [r_TMP + 0x3], r_TMP2
+        sll     r_OFF, 8, r_OFF
+        retl
+         or     r_OFF, r_TMP2, r_A
+        .globl  bpf_jit_load_half
+bpf_jit_load_half:
+        cmp     r_OFF, 0
+        bl      bpf_slow_path_half_neg
+         nop
+        .globl  bpf_jit_load_half_positive_offset
+bpf_jit_load_half_positive_offset:
+        sub     r_HEADLEN, r_OFF, r_TMP
+        cmp     r_TMP, 1
+        ble     bpf_slow_path_half
+         add    r_SKB_DATA, r_OFF, r_TMP
+        andcc   r_TMP, 1, %g0
+        bne     load_half_unaligned
+         nop
+        retl
+         lduh   [r_TMP], r_A
+load_half_unaligned:
+        ldub    [r_TMP + 0x0], r_OFF
+        ldub    [r_TMP + 0x1], r_TMP2
+        sll     r_OFF, 8, r_OFF
+        retl
+         or     r_OFF, r_TMP2, r_A
+        .globl  bpf_jit_load_byte
+bpf_jit_load_byte:
+        cmp     r_OFF, 0
+        bl      bpf_slow_path_byte_neg
+         nop
+        .globl  bpf_jit_load_byte_positive_offset
+bpf_jit_load_byte_positive_offset:
+        cmp     r_OFF, r_HEADLEN
+        bge     bpf_slow_path_byte
+         nop
+        retl
+         ldub   [r_SKB_DATA + r_OFF], r_A
+        .globl  bpf_jit_load_byte_msh
+bpf_jit_load_byte_msh:
+        cmp     r_OFF, 0
+        bl      bpf_slow_path_byte_msh_neg
+         nop
+        .globl  bpf_jit_load_byte_msh_positive_offset
+bpf_jit_load_byte_msh_positive_offset:
+        cmp     r_OFF, r_HEADLEN
+        bge     bpf_slow_path_byte_msh
+         nop
+        ldub    [r_SKB_DATA + r_OFF], r_OFF
+        and     r_OFF, 0xf, r_OFF
+        retl
+         sll    r_OFF, 2, r_X
+#define bpf_slow_path_common(LEN)       \
+        save    %sp, -SAVE_SZ, %sp;     \
+        mov     %i0, %o0;               \
+        mov     r_OFF, %o1;             \
+        add     %fp, SCRATCH_OFF, %o2;  \
+        call    skb_copy_bits;          \
+         mov    (LEN), %o3;             \
+        cmp     %o0, 0;                 \
+        restore;
+bpf_slow_path_word:
+        bpf_slow_path_common(4)
+        bl      bpf_error
+         ld     [%sp + SCRATCH_OFF], r_A
+        retl
+         nop
+bpf_slow_path_half:
+        bpf_slow_path_common(2)
+        bl      bpf_error
+         lduh   [%sp + SCRATCH_OFF], r_A
+        retl
+         nop
+bpf_slow_path_byte:
+        bpf_slow_path_common(1)
+        bl      bpf_error
+         ldub   [%sp + SCRATCH_OFF], r_A
+        retl
+         nop
+bpf_slow_path_byte_msh:
+        bpf_slow_path_common(1)
+        bl      bpf_error
+         ldub   [%sp + SCRATCH_OFF], r_A
+        and     r_OFF, 0xf, r_OFF
+        retl
+         sll    r_OFF, 2, r_X
+#define bpf_negative_common(LEN)                        \
+        save    %sp, -SAVE_SZ, %sp;                     \
+        mov     %i0, %o0;                               \
+        mov     r_OFF, %o1;                             \
+        call    bpf_internal_load_pointer_neg_helper;   \
+         mov    (LEN), %o2;                             \
+        mov     %o0, r_TMP;                             \
+        cmp     %o0, 0;                                 \
+        BE_PTR(bpf_error);                              \
+         restore;
+bpf_slow_path_word_neg:
+        sethi   %hi(SKF_MAX_NEG_OFF), r_TMP
+        cmp     r_OFF, r_TMP
+        bl      bpf_error
+         nop
+        .globl  bpf_jit_load_word_negative_offset
+bpf_jit_load_word_negative_offset:
+        bpf_negative_common(4)
+        andcc   r_TMP, 3, %g0
+        bne     load_word_unaligned
+         nop
+        retl
+         ld     [r_TMP], r_A
+bpf_slow_path_half_neg:
+        sethi   %hi(SKF_MAX_NEG_OFF), r_TMP
+        cmp     r_OFF, r_TMP
+        bl      bpf_error
+         nop
+        .globl  bpf_jit_load_half_negative_offset
+bpf_jit_load_half_negative_offset:
+        bpf_negative_common(2)
+        andcc   r_TMP, 1, %g0
+        bne     load_half_unaligned
+         nop
+        retl
+         lduh   [r_TMP], r_A
+bpf_slow_path_byte_neg:
+        sethi   %hi(SKF_MAX_NEG_OFF), r_TMP
+        cmp     r_OFF, r_TMP
+        bl      bpf_error
+         nop
+        .globl  bpf_jit_load_byte_negative_offset
+bpf_jit_load_byte_negative_offset:
+        bpf_negative_common(1)
+        retl
+         ldub   [r_TMP], r_A
+bpf_slow_path_byte_msh_neg:
+        sethi   %hi(SKF_MAX_NEG_OFF), r_TMP
+        cmp     r_OFF, r_TMP
+        bl      bpf_error
+         nop
+        .globl  bpf_jit_load_byte_msh_negative_offset
+bpf_jit_load_byte_msh_negative_offset:
+        bpf_negative_common(1)
+        ldub    [r_TMP], r_OFF
+        and     r_OFF, 0xf, r_OFF
+        retl
+         sll    r_OFF, 2, r_X
+bpf_error:
+        /* Make the JIT program return zero.  The JIT epilogue
+         * stores away the original %o7 into r_saved_O7.  The
+         * normal leaf function return is to use "retl" which
+         * would evalute to "jmpl %o7 + 8, %g0" but we want to
+         * use the saved value thus the sequence you see here.
+         */
+        jmpl    r_saved_O7 + 8, %g0
+         clr    %o0
diff --git a/arch/sparc/net/bpf_jit_comp.c b/arch/sparc/net/bpf_jit_comp.c
new file mode 100644
index 000000000000..1a69244e785b
--- /dev/null
+++ b/arch/sparc/net/bpf_jit_comp.c
@@ -0,0 +1,802 @@
+#include <linux/moduleloader.h>
+#include <linux/workqueue.h>
+#include <linux/netdevice.h>
+#include <linux/filter.h>
+#include <linux/cache.h>
+#include <asm/cacheflush.h>
+#include <asm/ptrace.h>
+#include "bpf_jit.h"
+int bpf_jit_enable __read_mostly;
+static inline bool is_simm13(unsigned int value)
+{
+        return value + 0x1000 < 0x2000;
+}
+static void bpf_flush_icache(void *start_, void *end_)
+{
+#ifdef CONFIG_SPARC64
+        /* Cheetah's I-cache is fully coherent.  */
+        if (tlb_type == spitfire) {
+                unsigned long start = (unsigned long) start_;
+                unsigned long end = (unsigned long) end_;
+                start &= ~7UL;
+                end = (end + 7UL) & ~7UL;
+                while (start < end) {
+                        flushi(start);
+                        start += 32;
+                }
+        }
+#endif
+}
+#define SEEN_DATAREF 1 /* might call external helpers */
+#define SEEN_XREG    2 /* ebx is used */
+#define SEEN_MEM     4 /* use mem[] for temporary storage */
+#define S13(X)          ((X) & 0x1fff)
+#define IMMED           0x00002000
+#define RD(X)           ((X) << 25)
+#define RS1(X)          ((X) << 14)
+#define RS2(X)          ((X))
+#define OP(X)           ((X) << 30)
+#define OP2(X)          ((X) << 22)
+#define OP3(X)          ((X) << 19)
+#define COND(X)         ((X) << 25)
+#define F1(X)           OP(X)
+#define F2(X, Y)        (OP(X) | OP2(Y))
+#define F3(X, Y)        (OP(X) | OP3(Y))
+#define CONDN           COND(0x0)
+#define CONDE           COND(0x1)
+#define CONDLE          COND(0x2)
+#define CONDL           COND(0x3)
+#define CONDLEU         COND(0x4)
+#define CONDCS          COND(0x5)
+#define CONDNEG         COND(0x6)
+#define CONDVC          COND(0x7)
+#define CONDA           COND(0x8)
+#define CONDNE          COND(0x9)
+#define CONDG           COND(0xa)
+#define CONDGE          COND(0xb)
+#define CONDGU          COND(0xc)
+#define CONDCC          COND(0xd)
+#define CONDPOS         COND(0xe)
+#define CONDVS          COND(0xf)
+#define CONDGEU         CONDCC
+#define CONDLU          CONDCS
+#define WDISP22(X)      (((X) >> 2) & 0x3fffff)
+#define BA              (F2(0, 2) | CONDA)
+#define BGU             (F2(0, 2) | CONDGU)
+#define BLEU            (F2(0, 2) | CONDLEU)
+#define BGEU            (F2(0, 2) | CONDGEU)
+#define BLU             (F2(0, 2) | CONDLU)
+#define BE              (F2(0, 2) | CONDE)
+#define BNE             (F2(0, 2) | CONDNE)
+#ifdef CONFIG_SPARC64
+#define BNE_PTR         (F2(0, 1) | CONDNE | (2 << 20))
+#else
+#define BNE_PTR         BNE
+#endif
+#define SETHI(K, REG)   \
+        (F2(0, 0x4) | RD(REG) | (((K) >> 10) & 0x3fffff))
+#define OR_LO(K, REG)   \
+        (F3(2, 0x02) | IMMED | RS1(REG) | ((K) & 0x3ff) | RD(REG))
+#define ADD             F3(2, 0x00)
+#define AND             F3(2, 0x01)
+#define ANDCC           F3(2, 0x11)
+#define OR              F3(2, 0x02)
+#define SUB             F3(2, 0x04)
+#define SUBCC           F3(2, 0x14)
+#define MUL             F3(2, 0x0a)     /* umul */
+#define DIV             F3(2, 0x0e)     /* udiv */
+#define SLL             F3(2, 0x25)
+#define SRL             F3(2, 0x26)
+#define JMPL            F3(2, 0x38)
+#define CALL            F1(1)
+#define BR              F2(0, 0x01)
+#define RD_Y            F3(2, 0x28)
+#define WR_Y            F3(2, 0x30)
+#define LD32            F3(3, 0x00)
+#define LD8             F3(3, 0x01)
+#define LD16            F3(3, 0x02)
+#define LD64            F3(3, 0x0b)
+#define ST32            F3(3, 0x04)
+#ifdef CONFIG_SPARC64
+#define LDPTR           LD64
+#define BASE_STACKFRAME 176
+#else
+#define LDPTR           LD32
+#define BASE_STACKFRAME 96
+#endif
+#define LD32I           (LD32 | IMMED)
+#define LD8I            (LD8 | IMMED)
+#define LD16I           (LD16 | IMMED)
+#define LD64I           (LD64 | IMMED)
+#define LDPTRI          (LDPTR | IMMED)
+#define ST32I           (ST32 | IMMED)
+#define emit_nop()              \
+do {                            \
+        *prog++ = SETHI(0, G0); \
+} while (0)
+#define emit_neg()                                      \
+do {    /* sub %g0, r_A, r_A */                         \
+        *prog++ = SUB | RS1(G0) | RS2(r_A) | RD(r_A);   \
+} while (0)
+#define emit_reg_move(FROM, TO)                         \
+do {    /* or %g0, FROM, TO */                          \
+        *prog++ = OR | RS1(G0) | RS2(FROM) | RD(TO);    \
+} while (0)
+#define emit_clear(REG)                                 \
+do {    /* or %g0, %g0, REG */                          \
+        *prog++ = OR | RS1(G0) | RS2(G0) | RD(REG);     \
+} while (0)
+#define emit_set_const(K, REG)                                  \
+do {    /* sethi %hi(K), REG */                                 \
+        *prog++ = SETHI(K, REG);                                \
+        /* or REG, %lo(K), REG */                               \
+        *prog++ = OR_LO(K, REG);                                \
+} while (0)
+        /* Emit
+         *
+         *      OP      r_A, r_X, r_A
+         */
+#define emit_alu_X(OPCODE)                                      \
+do {                                                            \
+        seen |= SEEN_XREG;                                      \
+        *prog++ = OPCODE | RS1(r_A) | RS2(r_X) | RD(r_A);       \
+} while (0)
+        /* Emit either:
+         *
+         *      OP      r_A, K, r_A
+         *
+         * or
+         *
+         *      sethi   %hi(K), r_TMP
+         *      or      r_TMP, %lo(K), r_TMP
+         *      OP      r_A, r_TMP, r_A
+         *
+         * depending upon whether K fits in a signed 13-bit
+         * immediate instruction field.  Emit nothing if K
+         * is zero.
+         */
+#define emit_alu_K(OPCODE, K)                                   \
+do {                                                            \
+        if (K) {                                                \
+                unsigned int _insn = OPCODE;                    \
+                _insn |= RS1(r_A) | RD(r_A);                    \
+                if (is_simm13(K)) {                             \
+                        *prog++ = _insn | IMMED | S13(K);       \
+                } else {                                        \
+                        emit_set_const(K, r_TMP);               \
+                        *prog++ = _insn | RS2(r_TMP);           \
+                }                                               \
+        }                                                       \
+} while (0)
+#define emit_loadimm(K, DEST)                                           \
+do {                                                                    \
+        if (is_simm13(K)) {                                             \
+                /* or %g0, K, DEST */                                   \
+                *prog++ = OR | IMMED | RS1(G0) | S13(K) | RD(DEST);     \
+        } else {                                                        \
+                emit_set_const(K, DEST);                                \
+        }                                                               \
+} while (0)
+#define emit_loadptr(BASE, STRUCT, FIELD, DEST)                         \
+do {    unsigned int _off = offsetof(STRUCT, FIELD);                    \
+        BUILD_BUG_ON(FIELD_SIZEOF(STRUCT, FIELD) != sizeof(void *));    \
+        *prog++ = LDPTRI | RS1(BASE) | S13(_off) | RD(DEST);            \
+} while (0)
+#define emit_load32(BASE, STRUCT, FIELD, DEST)                          \
+do {    unsigned int _off = offsetof(STRUCT, FIELD);                    \
+        BUILD_BUG_ON(FIELD_SIZEOF(STRUCT, FIELD) != sizeof(u32));       \
+        *prog++ = LD32I | RS1(BASE) | S13(_off) | RD(DEST);             \
+} while (0)
+#define emit_load16(BASE, STRUCT, FIELD, DEST)                          \
+do {    unsigned int _off = offsetof(STRUCT, FIELD);                    \
+        BUILD_BUG_ON(FIELD_SIZEOF(STRUCT, FIELD) != sizeof(u16));       \
+        *prog++ = LD16I | RS1(BASE) | S13(_off) | RD(DEST);             \
+} while (0)
+#define __emit_load8(BASE, STRUCT, FIELD, DEST)                         \
+do {    unsigned int _off = offsetof(STRUCT, FIELD);                    \
+        *prog++ = LD8I | RS1(BASE) | S13(_off) | RD(DEST);              \
+} while (0)
+#define emit_load8(BASE, STRUCT, FIELD, DEST)                           \
+do {    BUILD_BUG_ON(FIELD_SIZEOF(STRUCT, FIELD) != sizeof(u8));        \
+        __emit_load8(BASE, STRUCT, FIELD, DEST);                        \
+} while (0)
+#define emit_ldmem(OFF, DEST)                                   \
+do {    *prog++ = LD32I | RS1(FP) | S13(-(OFF)) | RD(DEST);     \
+} while (0)
+#define emit_stmem(OFF, SRC)                                    \
+do {    *prog++ = LD32I | RS1(FP) | S13(-(OFF)) | RD(SRC);      \
+} while (0)
+#ifdef CONFIG_SMP
+#ifdef CONFIG_SPARC64
+#define emit_load_cpu(REG)                                              \
+        emit_load16(G6, struct thread_info, cpu, REG)
+#else
+#define emit_load_cpu(REG)                                              \
+        emit_load32(G6, struct thread_info, cpu, REG)
+#endif
+#else
+#define emit_load_cpu(REG)      emit_clear(REG)
+#endif
+#define emit_skb_loadptr(FIELD, DEST) \
+        emit_loadptr(r_SKB, struct sk_buff, FIELD, DEST)
+#define emit_skb_load32(FIELD, DEST) \
+        emit_load32(r_SKB, struct sk_buff, FIELD, DEST)
+#define emit_skb_load16(FIELD, DEST) \
+        emit_load16(r_SKB, struct sk_buff, FIELD, DEST)
+#define __emit_skb_load8(FIELD, DEST) \
+        __emit_load8(r_SKB, struct sk_buff, FIELD, DEST)
+#define emit_skb_load8(FIELD, DEST) \
+        emit_load8(r_SKB, struct sk_buff, FIELD, DEST)
+#define emit_jmpl(BASE, IMM_OFF, LREG) \
+        *prog++ = (JMPL | IMMED | RS1(BASE) | S13(IMM_OFF) | RD(LREG))
+#define emit_call(FUNC)                                 \
+do {    void *_here = image + addrs[i] - 8;             \
+        unsigned int _off = (void *)(FUNC) - _here;     \
+        *prog++ = CALL | (((_off) >> 2) & 0x3fffffff);  \
+        emit_nop();                                     \
+} while (0)
+#define emit_branch(BR_OPC, DEST)                       \
+do {    unsigned int _here = addrs[i] - 8;              \
+        *prog++ = BR_OPC | WDISP22((DEST) - _here);     \
+} while (0)
+#define emit_branch_off(BR_OPC, OFF)                    \
+do {    *prog++ = BR_OPC | WDISP22(OFF);                \
+} while (0)
+#define emit_jump(DEST)         emit_branch(BA, DEST)
+#define emit_read_y(REG)        *prog++ = RD_Y | RD(REG)
+#define emit_write_y(REG)       *prog++ = WR_Y | IMMED | RS1(REG) | S13(0)
+#define emit_cmp(R1, R2) \
+        *prog++ = (SUBCC | RS1(R1) | RS2(R2) | RD(G0))
+#define emit_cmpi(R1, IMM) \
+        *prog++ = (SUBCC | IMMED | RS1(R1) | S13(IMM) | RD(G0));
+#define emit_btst(R1, R2) \
+        *prog++ = (ANDCC | RS1(R1) | RS2(R2) | RD(G0))
+#define emit_btsti(R1, IMM) \
+        *prog++ = (ANDCC | IMMED | RS1(R1) | S13(IMM) | RD(G0));
+#define emit_sub(R1, R2, R3) \
+        *prog++ = (SUB | RS1(R1) | RS2(R2) | RD(R3))
+#define emit_subi(R1, IMM, R3) \
+        *prog++ = (SUB | IMMED | RS1(R1) | S13(IMM) | RD(R3))
+#define emit_add(R1, R2, R3) \
+        *prog++ = (ADD | RS1(R1) | RS2(R2) | RD(R3))
+#define emit_addi(R1, IMM, R3) \
+        *prog++ = (ADD | IMMED | RS1(R1) | S13(IMM) | RD(R3))
+#define emit_alloc_stack(SZ) \
+        *prog++ = (SUB | IMMED | RS1(SP) | S13(SZ) | RD(SP))
+#define emit_release_stack(SZ) \
+        *prog++ = (ADD | IMMED | RS1(SP) | S13(SZ) | RD(SP))
+/* A note about branch offset calculations.  The addrs[] array,
+ * indexed by BPF instruction, records the address after all the
+ * sparc instructions emitted for that BPF instruction.
+ *
+ * The most common case is to emit a branch at the end of such
+ * a code sequence.  So this would be two instructions, the
+ * branch and it's delay slot.
+ *
+ * Therefore by default the branch emitters calculate the branch
+ * offset field as:
+ *
+ *      destination - (addrs[i] - 8)
+ *
+ * This "addrs[i] - 8" is the address of the branch itself or
+ * what "." would be in assembler notation.  The "8" part is
+ * how we take into consideration the branch and it's delay
+ * slot mentioned above.
+ *
+ * Sometimes we need to emit a branch earlier in the code
+ * sequence.  And in these situations we adjust "destination"
+ * to accomodate this difference.  For example, if we needed
+ * to emit a branch (and it's delay slot) right before the
+ * final instruction emitted for a BPF opcode, we'd use
+ * "destination + 4" instead of just plain "destination" above.
+ *
+ * This is why you see all of these funny emit_branch() and
+ * emit_jump() calls with adjusted offsets.
+ */
+void bpf_jit_compile(struct sk_filter *fp)
+{
+        unsigned int cleanup_addr, proglen, oldproglen = 0;
+        u32 temp[8], *prog, *func, seen = 0, pass;
+        const struct sock_filter *filter = fp->insns;
+        int i, flen = fp->len, pc_ret0 = -1;
+        unsigned int *addrs;
+        void *image;
+        if (!bpf_jit_enable)
+                return;
+        addrs = kmalloc(flen * sizeof(*addrs), GFP_KERNEL);
+        if (addrs == NULL)
+                return;
+        /* Before first pass, make a rough estimation of addrs[]
+         * each bpf instruction is translated to less than 64 bytes
+         */
+        for (proglen = 0, i = 0; i < flen; i++) {
+                proglen += 64;
+                addrs[i] = proglen;
+        }
+        cleanup_addr = proglen; /* epilogue address */
+        image = NULL;
+        for (pass = 0; pass < 10; pass++) {
+                u8 seen_or_pass0 = (pass == 0) ? (SEEN_XREG | SEEN_DATAREF | SEEN_MEM) : seen;
+                /* no prologue/epilogue for trivial filters (RET something) */
+                proglen = 0;
+                prog = temp;
+                /* Prologue */
+                if (seen_or_pass0) {
+                        if (seen_or_pass0 & SEEN_MEM) {
+                                unsigned int sz = BASE_STACKFRAME;
+                                sz += BPF_MEMWORDS * sizeof(u32);
+                                emit_alloc_stack(sz);
+                        }
+                        /* Make sure we dont leek kernel memory. */
+                        if (seen_or_pass0 & SEEN_XREG)
+                                emit_clear(r_X);
+                        /* If this filter needs to access skb data,
+                         * load %o4 and %o5 with:
+                         *  %o4 = skb->len - skb->data_len
+                         *  %o5 = skb->data
+                         * And also back up %o7 into r_saved_O7 so we can
+                         * invoke the stubs using 'call'.
+                         */
+                        if (seen_or_pass0 & SEEN_DATAREF) {
+                                emit_load32(r_SKB, struct sk_buff, len, r_HEADLEN);
+                                emit_load32(r_SKB, struct sk_buff, data_len, r_TMP);
+                                emit_sub(r_HEADLEN, r_TMP, r_HEADLEN);
+                                emit_loadptr(r_SKB, struct sk_buff, data, r_SKB_DATA);
+                        }
+                }
+                emit_reg_move(O7, r_saved_O7);
+                switch (filter[0].code) {
+                case BPF_S_RET_K:
+                case BPF_S_LD_W_LEN:
+                case BPF_S_ANC_PROTOCOL:
+                case BPF_S_ANC_PKTTYPE:
+                case BPF_S_ANC_IFINDEX:
+                case BPF_S_ANC_MARK:
+                case BPF_S_ANC_RXHASH:
+                case BPF_S_ANC_CPU:
+                case BPF_S_ANC_QUEUE:
+                case BPF_S_LD_W_ABS:
+                case BPF_S_LD_H_ABS:
+                case BPF_S_LD_B_ABS:
+                        /* The first instruction sets the A register (or is
+                         * a "RET 'constant'")
+                         */
+                        break;
+                default:
+                        /* Make sure we dont leak kernel information to the
+                         * user.
+                         */
+                        emit_clear(r_A); /* A = 0 */
+                }
+                for (i = 0; i < flen; i++) {
+                        unsigned int K = filter[i].k;
+                        unsigned int t_offset;
+                        unsigned int f_offset;
+                        u32 t_op, f_op;
+                        int ilen;
+                        switch (filter[i].code) {
+                        case BPF_S_ALU_ADD_X:   /* A += X; */
+                                emit_alu_X(ADD);
+                                break;
+                        case BPF_S_ALU_ADD_K:   /* A += K; */
+                                emit_alu_K(ADD, K);
+                                break;
+                        case BPF_S_ALU_SUB_X:   /* A -= X; */
+                                emit_alu_X(SUB);
+                                break;
+                        case BPF_S_ALU_SUB_K:   /* A -= K */
+                                emit_alu_K(SUB, K);
+                                break;
+                        case BPF_S_ALU_AND_X:   /* A &= X */
+                                emit_alu_X(AND);
+                                break;
+                        case BPF_S_ALU_AND_K:   /* A &= K */
+                                emit_alu_K(AND, K);
+                                break;
+                        case BPF_S_ALU_OR_X:    /* A |= X */
+                                emit_alu_X(OR);
+                                break;
+                        case BPF_S_ALU_OR_K:    /* A |= K */
+                                emit_alu_K(OR, K);
+                                break;
+                        case BPF_S_ALU_LSH_X:   /* A <<= X */
+                                emit_alu_X(SLL);
+                                break;
+                        case BPF_S_ALU_LSH_K:   /* A <<= K */
+                                emit_alu_K(SLL, K);
+                                break;
+                        case BPF_S_ALU_RSH_X:   /* A >>= X */
+                                emit_alu_X(SRL);
+                                break;
+                        case BPF_S_ALU_RSH_K:   /* A >>= K */
+                                emit_alu_K(SRL, K);
+                                break;
+                        case BPF_S_ALU_MUL_X:   /* A *= X; */
+                                emit_alu_X(MUL);
+                                break;
+                        case BPF_S_ALU_MUL_K:   /* A *= K */
+                                emit_alu_K(MUL, K);
+                                break;
+                        case BPF_S_ALU_DIV_K:   /* A /= K */
+                                emit_alu_K(MUL, K);
+                                emit_read_y(r_A);
+                                break;
+                        case BPF_S_ALU_DIV_X:   /* A /= X; */
+                                emit_cmpi(r_X, 0);
+                                if (pc_ret0 > 0) {
+                                        t_offset = addrs[pc_ret0 - 1];
+#ifdef CONFIG_SPARC32
+                                        emit_branch(BE, t_offset + 20);
+#else
+                                        emit_branch(BE, t_offset + 8);
+#endif
+                                        emit_nop(); /* delay slot */
+                                } else {
+                                        emit_branch_off(BNE, 16);
+                                        emit_nop();
+#ifdef CONFIG_SPARC32
+                                        emit_jump(cleanup_addr + 20);
+#else
+                                        emit_jump(cleanup_addr + 8);
+#endif
+                                        emit_clear(r_A);
+                                }
+                                emit_write_y(G0);
+#ifdef CONFIG_SPARC32
+                                /* The Sparc v8 architecture requires
+                                 * three instructions between a %y
+                                 * register write and the first use.
+                                 */
+                                emit_nop();
+                                emit_nop();
+                                emit_nop();
+#endif
+                                emit_alu_X(DIV);
+                                break;
+                        case BPF_S_ALU_NEG:
+                                emit_neg();
+                                break;
+                        case BPF_S_RET_K:
+                                if (!K) {
+                                        if (pc_ret0 == -1)
+                                                pc_ret0 = i;
+                                        emit_clear(r_A);
+                                } else {
+                                        emit_loadimm(K, r_A);
+                                }
+                                /* Fallthrough */
+                        case BPF_S_RET_A:
+                                if (seen_or_pass0) {
+                                        if (i != flen - 1) {
+                                                emit_jump(cleanup_addr);
+                                                emit_nop();
+                                                break;
+                                        }
+                                        if (seen_or_pass0 & SEEN_MEM) {
+                                                unsigned int sz = BASE_STACKFRAME;
+                                                sz += BPF_MEMWORDS * sizeof(u32);
+                                                emit_release_stack(sz);
+                                        }
+                                }
+                                /* jmpl %r_saved_O7 + 8, %g0 */
+                                emit_jmpl(r_saved_O7, 8, G0);
+                                emit_reg_move(r_A, O0); /* delay slot */
+                                break;
+                        case BPF_S_MISC_TAX:
+                                seen |= SEEN_XREG;
+                                emit_reg_move(r_A, r_X);
+                                break;
+                        case BPF_S_MISC_TXA:
+                                seen |= SEEN_XREG;
+                                emit_reg_move(r_X, r_A);
+                                break;
+                        case BPF_S_ANC_CPU:
+                                emit_load_cpu(r_A);
+                                break;
+                        case BPF_S_ANC_PROTOCOL:
+                                emit_skb_load16(protocol, r_A);
+                                break;
+#if 0
+                                /* GCC won't let us take the address of
+                                 * a bit field even though we very much
+                                 * know what we are doing here.
+                                 */
+                        case BPF_S_ANC_PKTTYPE:
+                                __emit_skb_load8(pkt_type, r_A);
+                                emit_alu_K(SRL, 5);
+                                break;
+#endif
+                        case BPF_S_ANC_IFINDEX:
+                                emit_skb_loadptr(dev, r_A);
+                                emit_cmpi(r_A, 0);
+                                emit_branch(BNE_PTR, cleanup_addr + 4);
+                                emit_nop();
+                                emit_load32(r_A, struct net_device, ifindex, r_A);
+                                break;
+                        case BPF_S_ANC_MARK:
+                                emit_skb_load32(mark, r_A);
+                                break;
+                        case BPF_S_ANC_QUEUE:
+                                emit_skb_load16(queue_mapping, r_A);
+                                break;
+                        case BPF_S_ANC_HATYPE:
+                                emit_skb_loadptr(dev, r_A);
+                                emit_cmpi(r_A, 0);
+                                emit_branch(BNE_PTR, cleanup_addr + 4);
+                                emit_nop();
+                                emit_load16(r_A, struct net_device, type, r_A);
+                                break;
+                        case BPF_S_ANC_RXHASH:
+                                emit_skb_load32(rxhash, r_A);
+                                break;
+                        case BPF_S_LD_IMM:
+                                emit_loadimm(K, r_A);
+                                break;
+                        case BPF_S_LDX_IMM:
+                                emit_loadimm(K, r_X);
+                                break;
+                        case BPF_S_LD_MEM:
+                                emit_ldmem(K * 4, r_A);
+                                break;
+                        case BPF_S_LDX_MEM:
+                                emit_ldmem(K * 4, r_X);
+                                break;
+                        case BPF_S_ST:
+                                emit_stmem(K * 4, r_A);
+                                break;
+                        case BPF_S_STX:
+                                emit_stmem(K * 4, r_X);
+                                break;
+#define CHOOSE_LOAD_FUNC(K, func) \
+        ((int)K < 0 ? ((int)K >= SKF_LL_OFF ? func##_negative_offset : func) : func##_positive_offset)
+                        case BPF_S_LD_W_ABS:
+                                func = CHOOSE_LOAD_FUNC(K, bpf_jit_load_word);
+common_load:                    seen |= SEEN_DATAREF;
+                                emit_loadimm(K, r_OFF);
+                                emit_call(func);
+                                break;
+                        case BPF_S_LD_H_ABS:
+                                func = CHOOSE_LOAD_FUNC(K, bpf_jit_load_half);
+                                goto common_load;
+                        case BPF_S_LD_B_ABS:
+                                func = CHOOSE_LOAD_FUNC(K, bpf_jit_load_byte);
+                                goto common_load;
+                        case BPF_S_LDX_B_MSH:
+                                func = CHOOSE_LOAD_FUNC(K, bpf_jit_load_byte_msh);
+                                goto common_load;
+                        case BPF_S_LD_W_IND:
+                                func = bpf_jit_load_word;
+common_load_ind:                seen |= SEEN_DATAREF | SEEN_XREG;
+                                if (K) {
+                                        if (is_simm13(K)) {
+                                                emit_addi(r_X, K, r_OFF);
+                                        } else {
+                                                emit_loadimm(K, r_TMP);
+                                                emit_add(r_X, r_TMP, r_OFF);
+                                        }
+                                } else {
+                                        emit_reg_move(r_X, r_OFF);
+                                }
+                                emit_call(func);
+                                break;
+                        case BPF_S_LD_H_IND:
+                                func = bpf_jit_load_half;
+                                goto common_load_ind;
+                        case BPF_S_LD_B_IND:
+                                func = bpf_jit_load_byte;
+                                goto common_load_ind;
+                        case BPF_S_JMP_JA:
+                                emit_jump(addrs[i + K]);
+                                emit_nop();
+                                break;
+#define COND_SEL(CODE, TOP, FOP)        \
+        case CODE:                      \
+                t_op = TOP;             \
+                f_op = FOP;             \
+                goto cond_branch
+                        COND_SEL(BPF_S_JMP_JGT_K, BGU, BLEU);
+                        COND_SEL(BPF_S_JMP_JGE_K, BGEU, BLU);
+                        COND_SEL(BPF_S_JMP_JEQ_K, BE, BNE);
+                        COND_SEL(BPF_S_JMP_JSET_K, BNE, BE);
+                        COND_SEL(BPF_S_JMP_JGT_X, BGU, BLEU);
+                        COND_SEL(BPF_S_JMP_JGE_X, BGEU, BLU);
+                        COND_SEL(BPF_S_JMP_JEQ_X, BE, BNE);
+                        COND_SEL(BPF_S_JMP_JSET_X, BNE, BE);
+cond_branch:                    f_offset = addrs[i + filter[i].jf];
+                                t_offset = addrs[i + filter[i].jt];
+                                /* same targets, can avoid doing the test :) */
+                                if (filter[i].jt == filter[i].jf) {
+                                        emit_jump(t_offset);
+                                        emit_nop();
+                                        break;
+                                }
+                                switch (filter[i].code) {
+                                case BPF_S_JMP_JGT_X:
+                                case BPF_S_JMP_JGE_X:
+                                case BPF_S_JMP_JEQ_X:
+                                        seen |= SEEN_XREG;
+                                        emit_cmp(r_A, r_X);
+                                        break;
+                                case BPF_S_JMP_JSET_X:
+                                        seen |= SEEN_XREG;
+                                        emit_btst(r_A, r_X);
+                                        break;
+                                case BPF_S_JMP_JEQ_K:
+                                case BPF_S_JMP_JGT_K:
+                                case BPF_S_JMP_JGE_K:
+                                        if (is_simm13(K)) {
+                                                emit_cmpi(r_A, K);
+                                        } else {
+                                                emit_loadimm(K, r_TMP);
+                                                emit_cmp(r_A, r_TMP);
+                                        }
+                                        break;
+                                case BPF_S_JMP_JSET_K:
+                                        if (is_simm13(K)) {
+                                                emit_btsti(r_A, K);
+                                        } else {
+                                                emit_loadimm(K, r_TMP);
+                                                emit_btst(r_A, r_TMP);
+                                        }
+                                        break;
+                                }
+                                if (filter[i].jt != 0) {
+                                        if (filter[i].jf)
+                                                t_offset += 8;
+                                        emit_branch(t_op, t_offset);
+                                        emit_nop(); /* delay slot */
+                                        if (filter[i].jf) {
+                                                emit_jump(f_offset);
+                                                emit_nop();
+                                        }
+                                        break;
+                                }
+                                emit_branch(f_op, f_offset);
+                                emit_nop(); /* delay slot */
+                                break;
+                        default:
+                                /* hmm, too complex filter, give up with jit compiler */
+                                goto out;
+                        }
+                        ilen = (void *) prog - (void *) temp;
+                        if (image) {
+                                if (unlikely(proglen + ilen > oldproglen)) {
+                                        pr_err("bpb_jit_compile fatal error\n");
+                                        kfree(addrs);
+                                        module_free(NULL, image);
+                                        return;
+                                }
+                                memcpy(image + proglen, temp, ilen);
+                        }
+                        proglen += ilen;
+                        addrs[i] = proglen;
+                        prog = temp;
+                }
+                /* last bpf instruction is always a RET :
+                 * use it to give the cleanup instruction(s) addr
+                 */
+                cleanup_addr = proglen - 8; /* jmpl; mov r_A,%o0; */
+                if (seen_or_pass0 & SEEN_MEM)
+                        cleanup_addr -= 4; /* add %sp, X, %sp; */
+                if (image) {
+                        if (proglen != oldproglen)
+                                pr_err("bpb_jit_compile proglen=%u != oldproglen=%u\n",
+                                       proglen, oldproglen);
+                        break;
+                }
+                if (proglen == oldproglen) {
+                        image = module_alloc(max_t(unsigned int,
+                                                   proglen,
+                                                   sizeof(struct work_struct)));
+                        if (!image)
+                                goto out;
+                }
+                oldproglen = proglen;
+        }
+        if (bpf_jit_enable > 1)
+                pr_err("flen=%d proglen=%u pass=%d image=%p\n",
+                       flen, proglen, pass, image);
+        if (image) {
+                if (bpf_jit_enable > 1)
+                        print_hex_dump(KERN_ERR, "JIT code: ", DUMP_PREFIX_ADDRESS,
+                                       16, 1, image, proglen, false);
+                bpf_flush_icache(image, image + proglen);
+                fp->bpf_func = (void *)image;
+        }
+out:
+        kfree(addrs);
+        return;
+}
+static void jit_free_defer(struct work_struct *arg)
+{
+        module_free(NULL, arg);
+}
+/* run from softirq, we must use a work_struct to call
+ * module_free() from process context
+ */
+void bpf_jit_free(struct sk_filter *fp)
+{
+        if (fp->bpf_func != sk_run_filter) {
+                struct work_struct *work = (struct work_struct *)fp->bpf_func;
+                INIT_WORK(work, jit_free_defer);
+                schedule_work(work);
+        }
+}
diff --git a/arch/sparc/prom/Makefile b/arch/sparc/prom/Makefile
index 8287bbe88768..020300b18c0b 100644
--- a/arch/sparc/prom/Makefile
+++ b/arch/sparc/prom/Makefile
@@ -10,7 +10,6 @@ lib-$(CONFIG_SPARC32) += memory.o
 lib-y                 += misc_$(BITS).o
 lib-$(CONFIG_SPARC32) += mp.o
 lib-$(CONFIG_SPARC32) += ranges.o
-lib-$(CONFIG_SPARC32) += segment.o
 lib-y                 += console_$(BITS).o
 lib-y                 += printf.o
 lib-y                 += tree_$(BITS).o
diff --git a/arch/sparc/prom/segment.c b/arch/sparc/prom/segment.c
deleted file mode 100644
index 86a663f1d3c5..000000000000
--- a/arch/sparc/prom/segment.c
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * segment.c:  Prom routine to map segments in other contexts before
- *             a standalone is completely mapped.  This is for sun4 and
- *             sun4c architectures only.
- *
- * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
- */
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <asm/openprom.h>
-#include <asm/oplib.h>
-extern void restore_current(void);
-/* Set physical segment 'segment' at virtual address 'vaddr' in
- * context 'ctx'.
- */
-void
-prom_putsegment(int ctx, unsigned long vaddr, int segment)
-{
-        unsigned long flags;
-        spin_lock_irqsave(&prom_lock, flags);
-        (*(romvec->pv_setctxt))(ctx, (char *) vaddr, segment);
-        restore_current();
-        spin_unlock_irqrestore(&prom_lock, flags);
-}
diff --git a/arch/tile/Kconfig b/arch/tile/Kconfig
index 96033e2d6845..74239dd77e06 100644
--- a/arch/tile/Kconfig
+++ b/arch/tile/Kconfig
@@ -11,6 +11,7 @@ config TILE
        select GENERIC_IRQ_PROBE
        select GENERIC_PENDING_IRQ if SMP
        select GENERIC_IRQ_SHOW
+        select HAVE_SYSCALL_WRAPPERS if TILEGX
        select SYS_HYPERVISOR
        select ARCH_HAVE_NMI_SAFE_CMPXCHG
diff --git a/arch/tile/include/asm/pci.h b/arch/tile/include/asm/pci.h
index 5d5a635530bd..32e6cbe8dff3 100644
--- a/arch/tile/include/asm/pci.h
+++ b/arch/tile/include/asm/pci.h
@@ -47,8 +47,8 @@ struct pci_controller {
 */
 #define PCI_DMA_BUS_IS_PHYS     1
-int __devinit tile_pci_init(void);
+int __init tile_pci_init(void);
-int __devinit pcibios_init(void);
+int __init pcibios_init(void);
 static inline void pci_iounmap(struct pci_dev *dev, void __iomem *addr) {}
diff --git a/arch/tile/include/asm/thread_info.h b/arch/tile/include/asm/thread_info.h
index bc4f562bd459..656c486e64fa 100644
--- a/arch/tile/include/asm/thread_info.h
+++ b/arch/tile/include/asm/thread_info.h
@@ -77,16 +77,14 @@ struct thread_info {
 #ifndef __ASSEMBLY__
+void arch_release_thread_info(struct thread_info *info);
 /* How to get the thread information struct from C. */
 register unsigned long stack_pointer __asm__("sp");
 #define current_thread_info() \
  ((struct thread_info *)(stack_pointer & -THREAD_SIZE))
-#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR
-extern struct thread_info *alloc_thread_info_node(struct task_struct *task, int node);
-extern void free_thread_info(struct thread_info *info);
 /* Sit on a nap instruction until interrupted. */
 extern void smp_nap(void);
@@ -100,9 +98,14 @@ extern void cpu_idle_on_new_stack(struct thread_info *old_ti,
 #else /* __ASSEMBLY__ */
-/* how to get the thread information struct from ASM */
+/*
+ * How to get the thread information struct from assembly.
+ * Note that we use different macros since different architectures
+ * have different semantics in their "mm" instruction and we would
+ * like to guarantee that the macro expands to exactly one instruction.
+ */
 #ifdef __tilegx__
-#define GET_THREAD_INFO(reg) move reg, sp; mm reg, zero, LOG2_THREAD_SIZE, 63
+#define EXTRACT_THREAD_INFO(reg) mm reg, zero, LOG2_THREAD_SIZE, 63
 #else
 #define GET_THREAD_INFO(reg) mm reg, sp, zero, LOG2_THREAD_SIZE, 31
 #endif
diff --git a/arch/tile/include/asm/topology.h b/arch/tile/include/asm/topology.h
index 6fdd0c860193..7a7ce390534f 100644
--- a/arch/tile/include/asm/topology.h
+++ b/arch/tile/include/asm/topology.h
@@ -78,32 +78,6 @@ static inline const struct cpumask *cpumask_of_node(int node)
        .balance_interval       = 32,                                   \
 }
-/* sched_domains SD_NODE_INIT for TILE architecture */
-#define SD_NODE_INIT (struct sched_domain) {                            \
-        .min_interval           = 16,                                   \
-        .max_interval           = 512,                                  \
-        .busy_factor            = 32,                                   \
-        .imbalance_pct          = 125,                                  \
-        .cache_nice_tries       = 1,                                    \
-        .busy_idx               = 3,                                    \
-        .idle_idx               = 1,                                    \
-        .newidle_idx            = 2,                                    \
-        .wake_idx               = 1,                                    \
-        .flags                  = 1*SD_LOAD_BALANCE                     \
-                                | 1*SD_BALANCE_NEWIDLE                  \
-                                | 1*SD_BALANCE_EXEC                     \
-                                | 1*SD_BALANCE_FORK                     \
-                                | 0*SD_BALANCE_WAKE                     \
-                                | 0*SD_WAKE_AFFINE                      \
-                                | 0*SD_PREFER_LOCAL                     \
-                                | 0*SD_SHARE_CPUPOWER                   \
-                                | 0*SD_SHARE_PKG_RESOURCES              \
-                                | 1*SD_SERIALIZE                        \
-                                ,                                       \
-        .last_balance           = jiffies,                              \
-        .balance_interval       = 128,                                  \
-}
 /* By definition, we create nodes based on online memory. */
 #define node_has_online_mem(nid) 1
diff --git a/arch/tile/kernel/Makefile b/arch/tile/kernel/Makefile
index b4dbc057baad..0d826faf8f35 100644
--- a/arch/tile/kernel/Makefile
+++ b/arch/tile/kernel/Makefile
@@ -3,7 +3,7 @@
 #
 extra-y := vmlinux.lds head_$(BITS).o
-obj-y := backtrace.o entry.o init_task.o irq.o messaging.o \
+obj-y := backtrace.o entry.o irq.o messaging.o \
        pci-dma.o proc.o process.o ptrace.o reboot.o \
        setup.o signal.o single_step.o stack.o sys.o sysfs.o time.o traps.o \
        intvec_$(BITS).o regs_$(BITS).o tile-desc_$(BITS).o
diff --git a/arch/tile/kernel/compat_signal.c b/arch/tile/kernel/compat_signal.c
index 77763ccd5a7d..cdef6e5ec022 100644
--- a/arch/tile/kernel/compat_signal.c
+++ b/arch/tile/kernel/compat_signal.c
@@ -403,19 +403,17 @@ int compat_setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
         * Set up registers for signal handler.
         * Registers that we don't modify keep the value they had from
         * user-space at the time we took the signal.
+         * We always pass siginfo and mcontext, regardless of SA_SIGINFO,
+         * since some things rely on this (e.g. glibc's debug/segfault.c).
         */
        regs->pc = ptr_to_compat_reg(ka->sa.sa_handler);
        regs->ex1 = PL_ICS_EX1(USER_PL, 1); /* set crit sec in handler */
        regs->sp = ptr_to_compat_reg(frame);
        regs->lr = restorer;
        regs->regs[0] = (unsigned long) usig;
+        regs->regs[1] = ptr_to_compat_reg(&frame->info);
-        if (ka->sa.sa_flags & SA_SIGINFO) {
+        regs->regs[2] = ptr_to_compat_reg(&frame->uc);
-                /* Need extra arguments, so mark to restore caller-saves. */
+        regs->flags |= PT_FLAGS_CALLER_SAVES;
-                regs->regs[1] = ptr_to_compat_reg(&frame->info);
-                regs->regs[2] = ptr_to_compat_reg(&frame->uc);
-                regs->flags |= PT_FLAGS_CALLER_SAVES;
-        }
        /*
         * Notify any tracer that was single-stepping it.
diff --git a/arch/tile/kernel/init_task.c b/arch/tile/kernel/init_task.c
deleted file mode 100644
index 928b31870669..000000000000
--- a/arch/tile/kernel/init_task.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- *   This program is free software; you can redistribute it and/or
- *   modify it under the terms of the GNU General Public License
- *   as published by the Free Software Foundation, version 2.
- *
- *   This program is distributed in the hope that it will be useful, but
- *   WITHOUT ANY WARRANTY; without even the implied warranty of
- *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- *   NON INFRINGEMENT.  See the GNU General Public License for
- *   more details.
- */
-#include <linux/mm.h>
-#include <linux/fs.h>
-#include <linux/init_task.h>
-#include <linux/mqueue.h>
-#include <linux/module.h>
-#include <linux/start_kernel.h>
-#include <linux/uaccess.h>
-static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
-static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
-/*
- * Initial thread structure.
- *
- * We need to make sure that this is THREAD_SIZE aligned due to the
- * way process stacks are handled. This is done by having a special
- * "init_task" linker map entry..
- */
-union thread_union init_thread_union __init_task_data = {
-        INIT_THREAD_INFO(init_task)
-};
-/*
- * Initial task structure.
- *
- * All other task structs will be allocated on slabs in fork.c
- */
-struct task_struct init_task = INIT_TASK(init_task);
-EXPORT_SYMBOL(init_task);
-/*
- * per-CPU stack and boot info.
- */
-DEFINE_PER_CPU(unsigned long, boot_sp) =
-        (unsigned long)init_stack + THREAD_SIZE;
-#ifdef CONFIG_SMP
-DEFINE_PER_CPU(unsigned long, boot_pc) = (unsigned long)start_kernel;
-#else
-/*
- * The variable must be __initdata since it references __init code.
- * With CONFIG_SMP it is per-cpu data, which is exempt from validation.
- */
-unsigned long __initdata boot_pc = (unsigned long)start_kernel;
-#endif
diff --git a/arch/tile/kernel/intvec_32.S b/arch/tile/kernel/intvec_32.S
index 5d56a1ef5ba5..6943515100f8 100644
--- a/arch/tile/kernel/intvec_32.S
+++ b/arch/tile/kernel/intvec_32.S
@@ -839,6 +839,18 @@ STD_ENTRY(interrupt_return)
        FEEDBACK_REENTER(interrupt_return)
        /*
+         * Use r33 to hold whether we have already loaded the callee-saves
+         * into ptregs.  We don't want to do it twice in this loop, since
+         * then we'd clobber whatever changes are made by ptrace, etc.
+         * Get base of stack in r32.
+         */
+        {
+         GET_THREAD_INFO(r32)
+         movei  r33, 0
+        }
+.Lretry_work_pending:
+        /*
         * Disable interrupts so as to make sure we don't
         * miss an interrupt that sets any of the thread flags (like
         * need_resched or sigpending) between sampling and the iret.
@@ -848,9 +860,6 @@ STD_ENTRY(interrupt_return)
        IRQ_DISABLE(r20, r21)
        TRACE_IRQS_OFF  /* Note: clobbers registers r0-r29 */
-        /* Get base of stack in r32; note r30/31 are used as arguments here. */
-        GET_THREAD_INFO(r32)
        /* Check to see if there is any work to do before returning to user. */
        {
@@ -866,16 +875,18 @@ STD_ENTRY(interrupt_return)
        /*
         * Make sure we have all the registers saved for signal
-         * handling or single-step.  Call out to C code to figure out
+         * handling, notify-resume, or single-step.  Call out to C
-         * exactly what we need to do for each flag bit, then if
+         * code to figure out exactly what we need to do for each flag bit,
-         * necessary, reload the flags and recheck.
+         * then if necessary, reload the flags and recheck.
         */
-        push_extra_callee_saves r0
        {
         PTREGS_PTR(r0, PTREGS_OFFSET_BASE)
-         jal    do_work_pending
+         bnz    r33, 1f
        }
-        bnz     r0, .Lresume_userspace
+        push_extra_callee_saves r0
+        movei   r33, 1
+1:      jal     do_work_pending
+        bnz     r0, .Lretry_work_pending
        /*
         * In the NMI case we
@@ -1180,10 +1191,12 @@ handle_syscall:
        add     r20, r20, tp
        lw      r21, r20
        addi    r21, r21, 1
-        sw      r20, r21
+        {
+         sw     r20, r21
+         GET_THREAD_INFO(r31)
+        }
        /* Trace syscalls, if requested. */
-        GET_THREAD_INFO(r31)
        addi    r31, r31, THREAD_INFO_FLAGS_OFFSET
        lw      r30, r31
        andi    r30, r30, _TIF_SYSCALL_TRACE
@@ -1362,7 +1375,10 @@ handle_ill:
 3:
        /* set PC and continue */
        lw      r26, r24
-        sw      r28, r26
+        {
+         sw     r28, r26
+         GET_THREAD_INFO(r0)
+        }
        /*
         * Clear TIF_SINGLESTEP to prevent recursion if we execute an ill.
@@ -1370,7 +1386,6 @@ handle_ill:
         * need to clear it here and can't really impose on all other arches.
         * So what's another write between friends?
         */
-        GET_THREAD_INFO(r0)
        addi    r1, r0, THREAD_INFO_FLAGS_OFFSET
        {
diff --git a/arch/tile/kernel/intvec_64.S b/arch/tile/kernel/intvec_64.S
index 49d9d6621682..30ae76e50c44 100644
--- a/arch/tile/kernel/intvec_64.S
+++ b/arch/tile/kernel/intvec_64.S
@@ -647,6 +647,20 @@ STD_ENTRY(interrupt_return)
        FEEDBACK_REENTER(interrupt_return)
        /*
+         * Use r33 to hold whether we have already loaded the callee-saves
+         * into ptregs.  We don't want to do it twice in this loop, since
+         * then we'd clobber whatever changes are made by ptrace, etc.
+         */
+        {
+         movei  r33, 0
+         move   r32, sp
+        }
+        /* Get base of stack in r32. */
+        EXTRACT_THREAD_INFO(r32)
+.Lretry_work_pending:
+        /*
         * Disable interrupts so as to make sure we don't
         * miss an interrupt that sets any of the thread flags (like
         * need_resched or sigpending) between sampling and the iret.
@@ -656,9 +670,6 @@ STD_ENTRY(interrupt_return)
        IRQ_DISABLE(r20, r21)
        TRACE_IRQS_OFF  /* Note: clobbers registers r0-r29 */
-        /* Get base of stack in r32; note r30/31 are used as arguments here. */
-        GET_THREAD_INFO(r32)
        /* Check to see if there is any work to do before returning to user. */
        {
@@ -674,16 +685,18 @@ STD_ENTRY(interrupt_return)
        /*
         * Make sure we have all the registers saved for signal
-         * handling or single-step.  Call out to C code to figure out
+         * handling or notify-resume.  Call out to C code to figure out
         * exactly what we need to do for each flag bit, then if
         * necessary, reload the flags and recheck.
         */
-        push_extra_callee_saves r0
        {
         PTREGS_PTR(r0, PTREGS_OFFSET_BASE)
-         jal    do_work_pending
+         bnez   r33, 1f
        }
-        bnez    r0, .Lresume_userspace
+        push_extra_callee_saves r0
+        movei   r33, 1
+1:      jal     do_work_pending
+        bnez    r0, .Lretry_work_pending
        /*
         * In the NMI case we
@@ -968,11 +981,16 @@ handle_syscall:
        shl16insli r20, r20, hw0(irq_stat + IRQ_CPUSTAT_SYSCALL_COUNT_OFFSET)
        add     r20, r20, tp
        ld4s    r21, r20
-        addi    r21, r21, 1
+        {
-        st4     r20, r21
+         addi   r21, r21, 1
+         move   r31, sp
+        }
+        {
+         st4    r20, r21
+         EXTRACT_THREAD_INFO(r31)
+        }
        /* Trace syscalls, if requested. */
-        GET_THREAD_INFO(r31)
        addi    r31, r31, THREAD_INFO_FLAGS_OFFSET
        ld      r30, r31
        andi    r30, r30, _TIF_SYSCALL_TRACE
diff --git a/arch/tile/kernel/pci.c b/arch/tile/kernel/pci.c
index a1bb59eecc18..b56d12bf5900 100644
--- a/arch/tile/kernel/pci.c
+++ b/arch/tile/kernel/pci.c
@@ -141,7 +141,7 @@ static int __devinit tile_init_irqs(int controller_id,
 *
 * Returns the number of controllers discovered.
 */
-int __devinit tile_pci_init(void)
+int __init tile_pci_init(void)
 {
        int i;
@@ -287,7 +287,7 @@ static void __devinit fixup_read_and_payload_sizes(void)
 * The controllers have been set up by the time we get here, by a call to
 * tile_pci_init.
 */
-int __devinit pcibios_init(void)
+int __init pcibios_init(void)
 {
        int i;
diff --git a/arch/tile/kernel/proc.c b/arch/tile/kernel/proc.c
index 7a9327046404..446a7f52cc11 100644
--- a/arch/tile/kernel/proc.c
+++ b/arch/tile/kernel/proc.c
@@ -146,7 +146,6 @@ static ctl_table unaligned_table[] = {
        },
        {}
 };
-#endif
 static struct ctl_path tile_path[] = {
        { .procname = "tile" },
@@ -155,10 +154,9 @@ static struct ctl_path tile_path[] = {
 static int __init proc_sys_tile_init(void)
 {
-#ifndef __tilegx__  /* FIXME: GX: no support for unaligned access yet */
        register_sysctl_paths(tile_path, unaligned_table);
-#endif
        return 0;
 }
 arch_initcall(proc_sys_tile_init);
+#endif
diff --git a/arch/tile/kernel/process.c b/arch/tile/kernel/process.c
index 2d5ef617bb39..f572c19c4082 100644
--- a/arch/tile/kernel/process.c
+++ b/arch/tile/kernel/process.c
@@ -114,27 +114,10 @@ void cpu_idle(void)
        }
 }
-struct thread_info *alloc_thread_info_node(struct task_struct *task, int node)
-{
-        struct page *page;
-        gfp_t flags = GFP_KERNEL;
-#ifdef CONFIG_DEBUG_STACK_USAGE
-        flags |= __GFP_ZERO;
-#endif
-        page = alloc_pages_node(node, flags, THREAD_SIZE_ORDER);
-        if (!page)
-                return NULL;
-        return (struct thread_info *)page_address(page);
-}
 /*
- * Free a thread_info node, and all of its derivative
+ * Release a thread_info structure
- * data structures.
 */
-void free_thread_info(struct thread_info *info)
+void arch_release_thread_info(struct thread_info *info)
 {
        struct single_step_state *step_state = info->step_state;
@@ -169,8 +152,6 @@ void free_thread_info(struct thread_info *info)
                 */
                kfree(step_state);
        }
-        free_pages((unsigned long)info, THREAD_SIZE_ORDER);
 }
 static void save_arch_state(struct thread_struct *t);
@@ -567,6 +548,10 @@ struct task_struct *__sched _switch_to(struct task_struct *prev,
 */
 int do_work_pending(struct pt_regs *regs, u32 thread_info_flags)
 {
+        /* If we enter in kernel mode, do nothing and exit the caller loop. */
+        if (!user_mode(regs))
+                return 0;
        if (thread_info_flags & _TIF_NEED_RESCHED) {
                schedule();
                return 1;
@@ -589,8 +574,7 @@ int do_work_pending(struct pt_regs *regs, u32 thread_info_flags)
                return 1;
        }
        if (thread_info_flags & _TIF_SINGLESTEP) {
-                if ((regs->ex1 & SPR_EX_CONTEXT_1_1__PL_MASK) == 0)
+                single_step_once(regs);
-                        single_step_once(regs);
                return 0;
        }
        panic("work_pending: bad flags %#x\n", thread_info_flags);
diff --git a/arch/tile/kernel/setup.c b/arch/tile/kernel/setup.c
index bff23f476110..98d80eb49ddb 100644
--- a/arch/tile/kernel/setup.c
+++ b/arch/tile/kernel/setup.c
@@ -61,6 +61,22 @@ unsigned long __initdata node_free_pfn[MAX_NUMNODES];
 static unsigned long __initdata node_percpu[MAX_NUMNODES];
+/*
+ * per-CPU stack and boot info.
+ */
+DEFINE_PER_CPU(unsigned long, boot_sp) =
+        (unsigned long)init_stack + THREAD_SIZE;
+#ifdef CONFIG_SMP
+DEFINE_PER_CPU(unsigned long, boot_pc) = (unsigned long)start_kernel;
+#else
+/*
+ * The variable must be __initdata since it references __init code.
+ * With CONFIG_SMP it is per-cpu data, which is exempt from validation.
+ */
+unsigned long __initdata boot_pc = (unsigned long)start_kernel;
+#endif
 #ifdef CONFIG_HIGHMEM
 /* Page frame index of end of lowmem on each controller. */
 unsigned long __cpuinitdata node_lowmem_end_pfn[MAX_NUMNODES];
diff --git a/arch/tile/kernel/single_step.c b/arch/tile/kernel/single_step.c
index 9efbc1391b3c..89529c9f0605 100644
--- a/arch/tile/kernel/single_step.c
+++ b/arch/tile/kernel/single_step.c
@@ -346,12 +346,10 @@ void single_step_once(struct pt_regs *regs)
                }
                /* allocate a cache line of writable, executable memory */
-                down_write(&current->mm->mmap_sem);
+                buffer = (void __user *) vm_mmap(NULL, 0, 64,
-                buffer = (void __user *) do_mmap(NULL, 0, 64,
                                          PROT_EXEC | PROT_READ | PROT_WRITE,
                                          MAP_PRIVATE | MAP_ANONYMOUS,
                                          0);
-                up_write(&current->mm->mmap_sem);
                if (IS_ERR((void __force *)buffer)) {
                        kfree(state);
diff --git a/arch/tile/kernel/smpboot.c b/arch/tile/kernel/smpboot.c
index b949edcec200..84873fbe8f27 100644
--- a/arch/tile/kernel/smpboot.c
+++ b/arch/tile/kernel/smpboot.c
@@ -196,6 +196,8 @@ void __cpuinit online_secondary(void)
        /* This must be done before setting cpu_online_mask */
        wmb();
+        notify_cpu_starting(smp_processor_id());
        /*
         * We need to hold call_lock, so there is no inconsistency
         * between the time smp_call_function() determines number of
@@ -220,7 +222,7 @@ void __cpuinit online_secondary(void)
        cpu_idle();
 }
-int __cpuinit __cpu_up(unsigned int cpu)
+int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *tidle)
 {
        /* Wait 5s total for all CPUs for them to come online */
        static int timeout;
diff --git a/arch/um/drivers/cow.h b/arch/um/drivers/cow.h
index dc36b222100b..6673508f3426 100644
--- a/arch/um/drivers/cow.h
+++ b/arch/um/drivers/cow.h
@@ -3,41 +3,6 @@
 #include <asm/types.h>
-#if defined(__KERNEL__)
-# include <asm/byteorder.h>
-# if defined(__BIG_ENDIAN)
-#       define ntohll(x) (x)
-#       define htonll(x) (x)
-# elif defined(__LITTLE_ENDIAN)
-#       define ntohll(x)  be64_to_cpu(x)
-#       define htonll(x)  cpu_to_be64(x)
-# else
-#       error "Could not determine byte order"
-# endif
-#else
-/* For the definition of ntohl, htonl and __BYTE_ORDER */
-#include <endian.h>
-#include <netinet/in.h>
-#if defined(__BYTE_ORDER)
-#  if __BYTE_ORDER == __BIG_ENDIAN
-#       define ntohll(x) (x)
-#       define htonll(x) (x)
-#  elif __BYTE_ORDER == __LITTLE_ENDIAN
-#       define ntohll(x)  bswap_64(x)
-#       define htonll(x)  bswap_64(x)
-#  else
-#       error "Could not determine byte order: __BYTE_ORDER uncorrectly defined"
-#  endif
-#else  /* ! defined(__BYTE_ORDER) */
-#       error "Could not determine byte order: __BYTE_ORDER not defined"
-#endif
-#endif /* ! defined(__KERNEL__) */
 extern int init_cow_file(int fd, char *cow_file, char *backing_file,
                         int sectorsize, int alignment, int *bitmap_offset_out,
                         unsigned long *bitmap_len_out, int *data_offset_out);
diff --git a/arch/um/drivers/cow_user.c b/arch/um/drivers/cow_user.c
index 9cbb426c0b91..0ee9cc6cc4c7 100644
--- a/arch/um/drivers/cow_user.c
+++ b/arch/um/drivers/cow_user.c
@@ -8,11 +8,10 @@
 * that.
 */
 #include <unistd.h>
-#include <byteswap.h>
 #include <errno.h>
 #include <string.h>
 #include <arpa/inet.h>
-#include <asm/types.h>
+#include <endian.h>
 #include "cow.h"
 #include "cow_sys.h"
@@ -214,8 +213,8 @@ int write_cow_header(char *cow_file, int fd, char *backing_file,
                           "header\n");
                goto out;
        }
-        header->magic = htonl(COW_MAGIC);
+        header->magic = htobe32(COW_MAGIC);
-        header->version = htonl(COW_VERSION);
+        header->version = htobe32(COW_VERSION);
        err = -EINVAL;
        if (strlen(backing_file) > sizeof(header->backing_file) - 1) {
@@ -246,10 +245,10 @@ int write_cow_header(char *cow_file, int fd, char *backing_file,
                goto out_free;
        }
-        header->mtime = htonl(modtime);
+        header->mtime = htobe32(modtime);
-        header->size = htonll(*size);
+        header->size = htobe64(*size);
-        header->sectorsize = htonl(sectorsize);
+        header->sectorsize = htobe32(sectorsize);
-        header->alignment = htonl(alignment);
+        header->alignment = htobe32(alignment);
        header->cow_format = COW_BITMAP;
        err = cow_write_file(fd, header, sizeof(*header));
@@ -301,8 +300,8 @@ int read_cow_header(int (*reader)(__u64, char *, int, void *), void *arg,
        magic = header->v1.magic;
        if (magic == COW_MAGIC)
                version = header->v1.version;
-        else if (magic == ntohl(COW_MAGIC))
+        else if (magic == be32toh(COW_MAGIC))
-                version = ntohl(header->v1.version);
+                version = be32toh(header->v1.version);
        /* No error printed because the non-COW case comes through here */
        else goto out;
@@ -327,9 +326,9 @@ int read_cow_header(int (*reader)(__u64, char *, int, void *), void *arg,
                                   "header\n");
                        goto out;
                }
-                *mtime_out = ntohl(header->v2.mtime);
+                *mtime_out = be32toh(header->v2.mtime);
-                *size_out = ntohll(header->v2.size);
+                *size_out = be64toh(header->v2.size);
-                *sectorsize_out = ntohl(header->v2.sectorsize);
+                *sectorsize_out = be32toh(header->v2.sectorsize);
                *bitmap_offset_out = sizeof(header->v2);
                *align_out = *sectorsize_out;
                file = header->v2.backing_file;
@@ -341,10 +340,10 @@ int read_cow_header(int (*reader)(__u64, char *, int, void *), void *arg,
                                   "header\n");
                        goto out;
                }
-                *mtime_out = ntohl(header->v3.mtime);
+                *mtime_out = be32toh(header->v3.mtime);
-                *size_out = ntohll(header->v3.size);
+                *size_out = be64toh(header->v3.size);
-                *sectorsize_out = ntohl(header->v3.sectorsize);
+                *sectorsize_out = be32toh(header->v3.sectorsize);
-                *align_out = ntohl(header->v3.alignment);
+                *align_out = be32toh(header->v3.alignment);
                if (*align_out == 0) {
                        cow_printf("read_cow_header - invalid COW header, "
                                   "align == 0\n");
@@ -366,16 +365,16 @@ int read_cow_header(int (*reader)(__u64, char *, int, void *), void *arg,
                 * this was used until Dec2005 - 64bits are needed to represent
                 * 2038+. I.e. we can safely do this truncating cast.
                 *
-                 * Additionally, we must use ntohl() instead of ntohll(), since
+                 * Additionally, we must use be32toh() instead of be64toh(), since
                 * the program used to use the former (tested - I got mtime
                 * mismatch "0 vs whatever").
                 *
                 * Ever heard about bug-to-bug-compatibility ? ;-) */
-                *mtime_out = (time32_t) ntohl(header->v3_b.mtime);
+                *mtime_out = (time32_t) be32toh(header->v3_b.mtime);
-                *size_out = ntohll(header->v3_b.size);
+                *size_out = be64toh(header->v3_b.size);
-                *sectorsize_out = ntohl(header->v3_b.sectorsize);
+                *sectorsize_out = be32toh(header->v3_b.sectorsize);
-                *align_out = ntohl(header->v3_b.alignment);
+                *align_out = be32toh(header->v3_b.alignment);
                if (*align_out == 0) {
                        cow_printf("read_cow_header - invalid COW header, "
                                   "align == 0\n");
diff --git a/arch/um/drivers/mconsole_kern.c b/arch/um/drivers/mconsole_kern.c
index e672bd6d43e3..88e466b159dc 100644
--- a/arch/um/drivers/mconsole_kern.c
+++ b/arch/um/drivers/mconsole_kern.c
@@ -22,6 +22,7 @@
 #include <linux/workqueue.h>
 #include <linux/mutex.h>
 #include <asm/uaccess.h>
+#include <asm/switch_to.h>
 #include "init.h"
 #include "irq_kern.h"
@@ -704,6 +705,7 @@ static void stack_proc(void *arg)
        struct task_struct *from = current, *to = arg;
        to->thread.saved_task = from;
+        rcu_switch_from(from);
        switch_to(from, to, from);
 }
diff --git a/arch/um/include/asm/Kbuild b/arch/um/include/asm/Kbuild
index 8419f5cf2ac7..fff24352255d 100644
--- a/arch/um/include/asm/Kbuild
+++ b/arch/um/include/asm/Kbuild
@@ -1,3 +1,4 @@
 generic-y += bug.h cputime.h device.h emergency-restart.h futex.h hardirq.h
 generic-y += hw_irq.h irq_regs.h kdebug.h percpu.h sections.h topology.h xor.h
-generic-y += ftrace.h pci.h io.h param.h delay.h mutex.h current.h
+generic-y += ftrace.h pci.h io.h param.h delay.h mutex.h current.h exec.h
+generic-y += switch_to.h
diff --git a/arch/um/include/asm/processor-generic.h b/arch/um/include/asm/processor-generic.h
index 98d01bc4fa92..7827394a5b6c 100644
--- a/arch/um/include/asm/processor-generic.h
+++ b/arch/um/include/asm/processor-generic.h
@@ -68,8 +68,6 @@ struct thread_struct {
        .request                = { 0 } \
 }
-extern struct task_struct *alloc_task_struct_node(int node);
 static inline void release_thread(struct task_struct *task)
 {
 }
diff --git a/arch/um/kernel/Makefile b/arch/um/kernel/Makefile
index 492bc4c1b62b..babe21826e3e 100644
--- a/arch/um/kernel/Makefile
+++ b/arch/um/kernel/Makefile
@@ -3,13 +3,14 @@
 # Licensed under the GPL
 #
-CPPFLAGS_vmlinux.lds := -DSTART=$(LDS_START) \
+CPPFLAGS_vmlinux.lds := -DSTART=$(LDS_START)            \
-                        -DELF_ARCH=$(LDS_ELF_ARCH)        \
+                        -DELF_ARCH=$(LDS_ELF_ARCH)      \
-                        -DELF_FORMAT=$(LDS_ELF_FORMAT)
+                        -DELF_FORMAT=$(LDS_ELF_FORMAT)  \
+                        $(LDS_EXTRA)
 extra-y := vmlinux.lds
 clean-files :=
-obj-y = config.o exec.o exitcode.o init_task.o irq.o ksyms.o mem.o \
+obj-y = config.o exec.o exitcode.o irq.o ksyms.o mem.o \
        physmem.o process.o ptrace.o reboot.o sigio.o \
        signal.o smp.o syscall.o sysrq.o time.o tlb.o trap.o \
        um_arch.o umid.o skas/
diff --git a/arch/um/kernel/init_task.c b/arch/um/kernel/init_task.c
deleted file mode 100644
index ddc9698b66ed..000000000000
--- a/arch/um/kernel/init_task.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * Copyright (C) 2000 - 2007 Jeff Dike (jdike@{addtoit,intel.linux}.com)
- * Licensed under the GPL
- */
-#include "linux/sched.h"
-#include "linux/init_task.h"
-#include "linux/fs.h"
-#include "linux/module.h"
-#include "linux/mqueue.h"
-#include "asm/uaccess.h"
-static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
-static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
-/*
- * Initial task structure.
- *
- * All other task structs will be allocated on slabs in fork.c
- */
-struct task_struct init_task = INIT_TASK(init_task);
-EXPORT_SYMBOL(init_task);
-/*
- * Initial thread structure.
- *
- * We need to make sure that this is aligned due to the
- * way process stacks are handled. This is done by having a special
- * "init_task" linker map entry..
- */
-union thread_union init_thread_union __init_task_data =
-        { INIT_THREAD_INFO(init_task) };
-union thread_union cpu0_irqstack
-        __attribute__((__section__(".data..init_irqstack"))) =
-                { INIT_THREAD_INFO(init_task) };
diff --git a/arch/um/kernel/process.c b/arch/um/kernel/process.c
index f386d04a84a5..2b73dedb44ca 100644
--- a/arch/um/kernel/process.c
+++ b/arch/um/kernel/process.c
@@ -88,11 +88,8 @@ static inline void set_current(struct task_struct *task)
 extern void arch_switch_to(struct task_struct *to);
-void *_switch_to(void *prev, void *next, void *last)
+void *__switch_to(struct task_struct *from, struct task_struct *to)
 {
-        struct task_struct *from = prev;
-        struct task_struct *to = next;
        to->thread.prev_sched = from;
        set_current(to);
@@ -111,7 +108,6 @@ void *_switch_to(void *prev, void *next, void *last)
        } while (current->thread.saved_task);
        return current->thread.prev_sched;
 }
 void interrupt_end(void)
diff --git a/arch/um/kernel/skas/mmu.c b/arch/um/kernel/skas/mmu.c
index 4947b319f53a..0a49ef0c2bf4 100644
--- a/arch/um/kernel/skas/mmu.c
+++ b/arch/um/kernel/skas/mmu.c
@@ -103,7 +103,6 @@ int init_new_context(struct task_struct *task, struct mm_struct *mm)
 void uml_setup_stubs(struct mm_struct *mm)
 {
-        struct page **pages;
        int err, ret;
        if (!skas_needs_stub)
diff --git a/arch/um/kernel/smp.c b/arch/um/kernel/smp.c
index 6f588e160fb0..a02b7e9e6b94 100644
--- a/arch/um/kernel/smp.c
+++ b/arch/um/kernel/smp.c
@@ -140,7 +140,7 @@ void smp_prepare_boot_cpu(void)
        set_cpu_online(smp_processor_id(), true);
 }
-int __cpu_up(unsigned int cpu)
+int __cpu_up(unsigned int cpu, struct task_struct *tidle)
 {
        cpu_set(cpu, smp_commenced_mask);
        while (!cpu_online(cpu))
diff --git a/arch/um/kernel/um_arch.c b/arch/um/kernel/um_arch.c
index ba00eae45aad..4db8770906ca 100644
--- a/arch/um/kernel/um_arch.c
+++ b/arch/um/kernel/um_arch.c
@@ -10,6 +10,7 @@
 #include <linux/seq_file.h>
 #include <linux/string.h>
 #include <linux/utsname.h>
+#include <linux/sched.h>
 #include <asm/pgtable.h>
 #include <asm/processor.h>
 #include <asm/setup.h>
@@ -47,6 +48,10 @@ struct cpuinfo_um boot_cpu_data = {
        .ipi_pipe               = { -1, -1 }
 };
+union thread_union cpu0_irqstack
+        __attribute__((__section__(".data..init_irqstack"))) =
+                { INIT_THREAD_INFO(init_task) };
 unsigned long thread_saved_pc(struct task_struct *task)
 {
        /* FIXME: Need to look up userspace_pid by cpu */
diff --git a/arch/unicore32/Makefile b/arch/unicore32/Makefile
index 6af4bc415f2b..b6f5c4c1eaf9 100644
--- a/arch/unicore32/Makefile
+++ b/arch/unicore32/Makefile
@@ -33,7 +33,6 @@ endif
 CHECKFLAGS              += -D__unicore32__
 head-y                  := arch/unicore32/kernel/head.o
-head-y                  += arch/unicore32/kernel/init_task.o
 core-y                  += arch/unicore32/kernel/
 core-y                  += arch/unicore32/mm/
diff --git a/arch/unicore32/kernel/Makefile b/arch/unicore32/kernel/Makefile
index aeb0f181568e..324010156958 100644
--- a/arch/unicore32/kernel/Makefile
+++ b/arch/unicore32/kernel/Makefile
@@ -29,4 +29,4 @@ obj-$(CONFIG_PUV3_NB0916)	+= puv3-nb0916.o
 head-y                          := head.o
 obj-$(CONFIG_DEBUG_LL)          += debug.o
-extra-y                         := $(head-y) init_task.o vmlinux.lds
+extra-y                         := $(head-y) vmlinux.lds
diff --git a/arch/unicore32/kernel/init_task.c b/arch/unicore32/kernel/init_task.c
deleted file mode 100644
index a35a1e50e4f4..000000000000
--- a/arch/unicore32/kernel/init_task.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * linux/arch/unicore32/kernel/init_task.c
- *
- * Code specific to PKUnity SoC and UniCore ISA
- *
- * Copyright (C) 2001-2010 GUAN Xue-tao
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/fs.h>
-#include <linux/sched.h>
-#include <linux/init.h>
-#include <linux/init_task.h>
-#include <linux/mqueue.h>
-#include <linux/uaccess.h>
-#include <asm/pgtable.h>
-static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
-static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
-/*
- * Initial thread structure.
- *
- * We need to make sure that this is 8192-byte aligned due to the
- * way process stacks are handled. This is done by making sure
- * the linker maps this in the .text segment right after head.S,
- * and making head.S ensure the proper alignment.
- *
- * The things we do for performance..
- */
-union thread_union init_thread_union __init_task_data = {
-        INIT_THREAD_INFO(init_task) };
-/*
- * Initial task structure.
- *
- * All other task structs will be allocated on slabs in fork.c
- */
-struct task_struct init_task = INIT_TASK(init_task);
-EXPORT_SYMBOL(init_task);
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 1d14cc6b79ad..7b383d8da7b9 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -40,7 +40,6 @@ config X86
        select HAVE_FUNCTION_GRAPH_TRACER
        select HAVE_FUNCTION_GRAPH_FP_TEST
        select HAVE_FUNCTION_TRACE_MCOUNT_TEST
-        select HAVE_FTRACE_NMI_ENTER if DYNAMIC_FTRACE
        select HAVE_SYSCALL_TRACEPOINTS
        select HAVE_KVM
        select HAVE_ARCH_KGDB
@@ -77,11 +76,13 @@ config X86
        select GENERIC_CLOCKEVENTS_MIN_ADJUST
        select IRQ_FORCED_THREADING
        select USE_GENERIC_SMP_HELPERS if SMP
-        select HAVE_BPF_JIT if (X86_64 && NET)
+        select HAVE_BPF_JIT if X86_64
        select CLKEVT_I8253
        select ARCH_HAVE_NMI_SAFE_CMPXCHG
        select GENERIC_IOMAP
-        select DCACHE_WORD_ACCESS if !DEBUG_PAGEALLOC
+        select DCACHE_WORD_ACCESS
+        select GENERIC_SMP_IDLE_THREAD
+        select HAVE_ARCH_SECCOMP_FILTER
 config INSTRUCTION_DECODER
        def_bool (KPROBES || PERF_EVENTS)
@@ -160,9 +161,6 @@ config RWSEM_GENERIC_SPINLOCK
 config RWSEM_XCHGADD_ALGORITHM
        def_bool X86_XADD
-config ARCH_HAS_CPU_IDLE_WAIT
-        def_bool y
 config GENERIC_CALIBRATE_DELAY
        def_bool y
diff --git a/arch/x86/Makefile b/arch/x86/Makefile
index 41a7237606a3..277418ff8b52 100644
--- a/arch/x86/Makefile
+++ b/arch/x86/Makefile
@@ -134,6 +134,9 @@ KBUILD_CFLAGS += $(call cc-option,-mno-avx,)
 KBUILD_CFLAGS += $(mflags-y)
 KBUILD_AFLAGS += $(mflags-y)
+archscripts:
+        $(Q)$(MAKE) $(build)=arch/x86/tools relocs
 ###
 # Syscall table generation
@@ -146,7 +149,6 @@ archheaders:
 head-y := arch/x86/kernel/head_$(BITS).o
 head-y += arch/x86/kernel/head$(BITS).o
 head-y += arch/x86/kernel/head.o
-head-y += arch/x86/kernel/init_task.o
 libs-y  += arch/x86/lib/
diff --git a/arch/x86/Makefile.um b/arch/x86/Makefile.um
index 4be406abeefd..36b62bc52638 100644
--- a/arch/x86/Makefile.um
+++ b/arch/x86/Makefile.um
@@ -14,6 +14,9 @@ LINK-y			+= $(call cc-option,-m32)
 export LDFLAGS
+LDS_EXTRA               := -Ui386
+export LDS_EXTRA
 # First of all, tune CFLAGS for the specific CPU. This actually sets cflags-y.
 include $(srctree)/arch/x86/Makefile_32.cpu
diff --git a/arch/x86/boot/compressed/Makefile b/arch/x86/boot/compressed/Makefile
index fd55a2ff3ad8..e398bb5d63bb 100644
--- a/arch/x86/boot/compressed/Makefile
+++ b/arch/x86/boot/compressed/Makefile
@@ -40,13 +40,12 @@ OBJCOPYFLAGS_vmlinux.bin :=  -R .comment -S
 $(obj)/vmlinux.bin: vmlinux FORCE
        $(call if_changed,objcopy)
+targets += vmlinux.bin.all vmlinux.relocs
-targets += vmlinux.bin.all vmlinux.relocs relocs
+CMD_RELOCS = arch/x86/tools/relocs
-hostprogs-$(CONFIG_X86_NEED_RELOCS) += relocs
 quiet_cmd_relocs = RELOCS  $@
-      cmd_relocs = $(obj)/relocs $< > $@;$(obj)/relocs --abs-relocs $<
+      cmd_relocs = $(CMD_RELOCS) $< > $@;$(CMD_RELOCS) --abs-relocs $<
-$(obj)/vmlinux.relocs: vmlinux $(obj)/relocs FORCE
+$(obj)/vmlinux.relocs: vmlinux FORCE
        $(call if_changed,relocs)
 vmlinux.bin.all-y := $(obj)/vmlinux.bin
diff --git a/arch/x86/boot/compressed/head_32.S b/arch/x86/boot/compressed/head_32.S
index a0559930a180..c85e3ac99bba 100644
--- a/arch/x86/boot/compressed/head_32.S
+++ b/arch/x86/boot/compressed/head_32.S
@@ -33,6 +33,9 @@
        __HEAD
 ENTRY(startup_32)
 #ifdef CONFIG_EFI_STUB
+        jmp     preferred_addr
+        .balign 0x10
        /*
         * We don't need the return address, so set up the stack so
         * efi_main() can find its arugments.
@@ -41,12 +44,17 @@ ENTRY(startup_32)
        call    efi_main
        cmpl    $0, %eax
-        je      preferred_addr
        movl    %eax, %esi
-        call    1f
+        jne     2f
 1:
+        /* EFI init failed, so hang. */
+        hlt
+        jmp     1b
+2:
+        call    3f
+3:
        popl    %eax
-        subl    $1b, %eax
+        subl    $3b, %eax
        subl    BP_pref_address(%esi), %eax
        add     BP_code32_start(%esi), %eax
        leal    preferred_addr(%eax), %eax
diff --git a/arch/x86/boot/compressed/head_64.S b/arch/x86/boot/compressed/head_64.S
index 558d76ce23bc..87e03a13d8e3 100644
--- a/arch/x86/boot/compressed/head_64.S
+++ b/arch/x86/boot/compressed/head_64.S
@@ -200,18 +200,28 @@ ENTRY(startup_64)
         * entire text+data+bss and hopefully all of memory.
         */
 #ifdef CONFIG_EFI_STUB
-        pushq   %rsi
+        /*
+         * The entry point for the PE/COFF executable is 0x210, so only
+         * legacy boot loaders will execute this jmp.
+         */
+        jmp     preferred_addr
+        .org 0x210
        mov     %rcx, %rdi
        mov     %rdx, %rsi
        call    efi_main
-        popq    %rsi
-        cmpq    $0,%rax
-        je      preferred_addr
        movq    %rax,%rsi
-        call    1f
+        cmpq    $0,%rax
+        jne     2f
 1:
+        /* EFI init failed, so hang. */
+        hlt
+        jmp     1b
+2:
+        call    3f
+3:
        popq    %rax
-        subq    $1b, %rax
+        subq    $3b, %rax
        subq    BP_pref_address(%rsi), %rax
        add     BP_code32_start(%esi), %eax
        leaq    preferred_addr(%rax), %rax
diff --git a/arch/x86/boot/tools/build.c b/arch/x86/boot/tools/build.c
index ed549767a231..24443a332083 100644
--- a/arch/x86/boot/tools/build.c
+++ b/arch/x86/boot/tools/build.c
@@ -205,8 +205,13 @@ int main(int argc, char ** argv)
        put_unaligned_le32(file_sz, &buf[pe_header + 0x50]);
 #ifdef CONFIG_X86_32
-        /* Address of entry point */
+        /*
-        put_unaligned_le32(i, &buf[pe_header + 0x28]);
+         * Address of entry point.
+         *
+         * The EFI stub entry point is +16 bytes from the start of
+         * the .text section.
+         */
+        put_unaligned_le32(i + 16, &buf[pe_header + 0x28]);
        /* .text size */
        put_unaligned_le32(file_sz, &buf[pe_header + 0xb0]);
@@ -217,9 +222,11 @@ int main(int argc, char ** argv)
        /*
         * Address of entry point. startup_32 is at the beginning and
         * the 64-bit entry point (startup_64) is always 512 bytes
-         * after.
+         * after. The EFI stub entry point is 16 bytes after that, as
+         * the first instruction allows legacy loaders to jump over
+         * the EFI stub initialisation
         */
-        put_unaligned_le32(i + 512, &buf[pe_header + 0x28]);
+        put_unaligned_le32(i + 528, &buf[pe_header + 0x28]);
        /* .text size */
        put_unaligned_le32(file_sz, &buf[pe_header + 0xc0]);
diff --git a/arch/x86/ia32/ia32_aout.c b/arch/x86/ia32/ia32_aout.c
index d511d951a052..07b3a68d2d29 100644
--- a/arch/x86/ia32/ia32_aout.c
+++ b/arch/x86/ia32/ia32_aout.c
@@ -119,9 +119,7 @@ static void set_brk(unsigned long start, unsigned long end)
        end = PAGE_ALIGN(end);
        if (end <= start)
                return;
-        down_write(&current->mm->mmap_sem);
+        vm_brk(start, end - start);
-        do_brk(start, end - start);
-        up_write(&current->mm->mmap_sem);
 }
 #ifdef CORE_DUMP
@@ -296,8 +294,7 @@ static int load_aout_binary(struct linux_binprm *bprm, struct pt_regs *regs)
        /* OK, This is the point of no return */
        set_personality(PER_LINUX);
-        set_thread_flag(TIF_IA32);
+        set_personality_ia32(false);
-        current->mm->context.ia32_compat = 1;
        setup_new_exec(bprm);
@@ -332,9 +329,7 @@ static int load_aout_binary(struct linux_binprm *bprm, struct pt_regs *regs)
                pos = 32;
                map_size = ex.a_text+ex.a_data;
-                down_write(&current->mm->mmap_sem);
+                error = vm_brk(text_addr & PAGE_MASK, map_size);
-                error = do_brk(text_addr & PAGE_MASK, map_size);
-                up_write(&current->mm->mmap_sem);
                if (error != (text_addr & PAGE_MASK)) {
                        send_sig(SIGKILL, current, 0);
@@ -373,9 +368,7 @@ static int load_aout_binary(struct linux_binprm *bprm, struct pt_regs *regs)
                if (!bprm->file->f_op->mmap || (fd_offset & ~PAGE_MASK) != 0) {
                        loff_t pos = fd_offset;
-                        down_write(&current->mm->mmap_sem);
+                        vm_brk(N_TXTADDR(ex), ex.a_text+ex.a_data);
-                        do_brk(N_TXTADDR(ex), ex.a_text+ex.a_data);
-                        up_write(&current->mm->mmap_sem);
                        bprm->file->f_op->read(bprm->file,
                                        (char __user *)N_TXTADDR(ex),
                                        ex.a_text+ex.a_data, &pos);
@@ -385,26 +378,22 @@ static int load_aout_binary(struct linux_binprm *bprm, struct pt_regs *regs)
                        goto beyond_if;
                }
-                down_write(&current->mm->mmap_sem);
+                error = vm_mmap(bprm->file, N_TXTADDR(ex), ex.a_text,
-                error = do_mmap(bprm->file, N_TXTADDR(ex), ex.a_text,
                                PROT_READ | PROT_EXEC,
                                MAP_FIXED | MAP_PRIVATE | MAP_DENYWRITE |
                                MAP_EXECUTABLE | MAP_32BIT,
                                fd_offset);
-                up_write(&current->mm->mmap_sem);
                if (error != N_TXTADDR(ex)) {
                        send_sig(SIGKILL, current, 0);
                        return error;
                }
-                down_write(&current->mm->mmap_sem);
+                error = vm_mmap(bprm->file, N_DATADDR(ex), ex.a_data,
-                error = do_mmap(bprm->file, N_DATADDR(ex), ex.a_data,
                                PROT_READ | PROT_WRITE | PROT_EXEC,
                                MAP_FIXED | MAP_PRIVATE | MAP_DENYWRITE |
                                MAP_EXECUTABLE | MAP_32BIT,
                                fd_offset + ex.a_text);
-                up_write(&current->mm->mmap_sem);
                if (error != N_DATADDR(ex)) {
                        send_sig(SIGKILL, current, 0);
                        return error;
@@ -476,9 +465,7 @@ static int load_aout_library(struct file *file)
                        error_time = jiffies;
                }
 #endif
-                down_write(&current->mm->mmap_sem);
+                vm_brk(start_addr, ex.a_text + ex.a_data + ex.a_bss);
-                do_brk(start_addr, ex.a_text + ex.a_data + ex.a_bss);
-                up_write(&current->mm->mmap_sem);
                file->f_op->read(file, (char __user *)start_addr,
                        ex.a_text + ex.a_data, &pos);
@@ -490,12 +477,10 @@ static int load_aout_library(struct file *file)
                goto out;
        }
        /* Now use mmap to map the library into memory. */
-        down_write(&current->mm->mmap_sem);
+        error = vm_mmap(file, start_addr, ex.a_text + ex.a_data,
-        error = do_mmap(file, start_addr, ex.a_text + ex.a_data,
                        PROT_READ | PROT_WRITE | PROT_EXEC,
                        MAP_FIXED | MAP_PRIVATE | MAP_DENYWRITE | MAP_32BIT,
                        N_TXTOFF(ex));
-        up_write(&current->mm->mmap_sem);
        retval = error;
        if (error != start_addr)
                goto out;
@@ -503,9 +488,7 @@ static int load_aout_library(struct file *file)
        len = PAGE_ALIGN(ex.a_text + ex.a_data);
        bss = ex.a_text + ex.a_data + ex.a_bss;
        if (bss > len) {
-                down_write(&current->mm->mmap_sem);
+                error = vm_brk(start_addr + len, bss - len);
-                error = do_brk(start_addr + len, bss - len);
-                up_write(&current->mm->mmap_sem);
                retval = error;
                if (error != start_addr + len)
                        goto out;
diff --git a/arch/x86/ia32/ia32_signal.c b/arch/x86/ia32/ia32_signal.c
index a69245ba27e3..0b3f2354f6aa 100644
--- a/arch/x86/ia32/ia32_signal.c
+++ b/arch/x86/ia32/ia32_signal.c
@@ -67,6 +67,10 @@ int copy_siginfo_to_user32(compat_siginfo_t __user *to, siginfo_t *from)
                        switch (from->si_code >> 16) {
                        case __SI_FAULT >> 16:
                                break;
+                        case __SI_SYS >> 16:
+                                put_user_ex(from->si_syscall, &to->si_syscall);
+                                put_user_ex(from->si_arch, &to->si_arch);
+                                break;
                        case __SI_CHLD >> 16:
                                if (ia32) {
                                        put_user_ex(from->si_utime, &to->si_utime);
diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h
index d85410171260..eaff4790ed96 100644
--- a/arch/x86/include/asm/apic.h
+++ b/arch/x86/include/asm/apic.h
@@ -138,6 +138,11 @@ static inline void native_apic_msr_write(u32 reg, u32 v)
        wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
 }
+static inline void native_apic_msr_eoi_write(u32 reg, u32 v)
+{
+        wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0);
+}
 static inline u32 native_apic_msr_read(u32 reg)
 {
        u64 msr;
@@ -351,6 +356,14 @@ struct apic {
        /* apic ops */
        u32 (*read)(u32 reg);
        void (*write)(u32 reg, u32 v);
+        /*
+         * ->eoi_write() has the same signature as ->write().
+         *
+         * Drivers can support both ->eoi_write() and ->write() by passing the same
+         * callback value. Kernel can override ->eoi_write() and fall back
+         * on write for EOI.
+         */
+        void (*eoi_write)(u32 reg, u32 v);
        u64 (*icr_read)(void);
        void (*icr_write)(u32 low, u32 high);
        void (*wait_icr_idle)(void);
@@ -426,6 +439,11 @@ static inline void apic_write(u32 reg, u32 val)
        apic->write(reg, val);
 }
+static inline void apic_eoi(void)
+{
+        apic->eoi_write(APIC_EOI, APIC_EOI_ACK);
+}
 static inline u64 apic_icr_read(void)
 {
        return apic->icr_read();
@@ -450,6 +468,7 @@ static inline u32 safe_apic_wait_icr_idle(void)
 static inline u32 apic_read(u32 reg) { return 0; }
 static inline void apic_write(u32 reg, u32 val) { }
+static inline void apic_eoi(void) { }
 static inline u64 apic_icr_read(void) { return 0; }
 static inline void apic_icr_write(u32 low, u32 high) { }
 static inline void apic_wait_icr_idle(void) { }
@@ -463,9 +482,7 @@ static inline void ack_APIC_irq(void)
         * ack_APIC_irq() actually gets compiled as a single instruction
         * ... yummie.
         */
+        apic_eoi();
-        /* Docs say use 0 for future compatibility */
-        apic_write(APIC_EOI, 0);
 }
 static inline unsigned default_get_apic_id(unsigned long x)
diff --git a/arch/x86/include/asm/apicdef.h b/arch/x86/include/asm/apicdef.h
index 134bba00df09..c46bb99d5fb2 100644
--- a/arch/x86/include/asm/apicdef.h
+++ b/arch/x86/include/asm/apicdef.h
@@ -37,7 +37,7 @@
 #define         APIC_ARBPRI_MASK        0xFFu
 #define APIC_PROCPRI    0xA0
 #define APIC_EOI        0xB0
-#define         APIC_EIO_ACK            0x0
+#define         APIC_EOI_ACK            0x0 /* Docs say 0 for future compat. */
 #define APIC_RRR        0xC0
 #define APIC_LDR        0xD0
 #define         APIC_LDR_MASK           (0xFFu << 24)
diff --git a/arch/x86/include/asm/boot.h b/arch/x86/include/asm/boot.h
index 5e1a2eef3e7c..b13fe63bdc59 100644
--- a/arch/x86/include/asm/boot.h
+++ b/arch/x86/include/asm/boot.h
@@ -19,7 +19,7 @@
 #ifdef CONFIG_X86_64
 #define MIN_KERNEL_ALIGN_LG2    PMD_SHIFT
 #else
-#define MIN_KERNEL_ALIGN_LG2    (PAGE_SHIFT + THREAD_ORDER)
+#define MIN_KERNEL_ALIGN_LG2    (PAGE_SHIFT + THREAD_SIZE_ORDER)
 #endif
 #define MIN_KERNEL_ALIGN        (_AC(1, UL) << MIN_KERNEL_ALIGN_LG2)
diff --git a/arch/x86/include/asm/cmpxchg.h b/arch/x86/include/asm/cmpxchg.h
index b3b733262909..99480e55973d 100644
--- a/arch/x86/include/asm/cmpxchg.h
+++ b/arch/x86/include/asm/cmpxchg.h
@@ -43,7 +43,7 @@ extern void __add_wrong_size(void)
                switch (sizeof(*(ptr))) {                               \
                case __X86_CASE_B:                                      \
                        asm volatile (lock #op "b %b0, %1\n"            \
-                                      : "+r" (__ret), "+m" (*(ptr))     \
+                                      : "+q" (__ret), "+m" (*(ptr))     \
                                      : : "memory", "cc");              \
                        break;                                          \
                case __X86_CASE_W:                                      \
@@ -173,7 +173,7 @@ extern void __add_wrong_size(void)
                switch (sizeof(*(ptr))) {                               \
                case __X86_CASE_B:                                      \
                        asm volatile (lock "addb %b1, %0\n"             \
-                                      : "+m" (*(ptr)) : "ri" (inc)      \
+                                      : "+m" (*(ptr)) : "qi" (inc)      \
                                      : "memory", "cc");                \
                        break;                                          \
                case __X86_CASE_W:                                      \
diff --git a/arch/x86/include/asm/compat.h b/arch/x86/include/asm/compat.h
index d6805798d6fc..fedf32b73e65 100644
--- a/arch/x86/include/asm/compat.h
+++ b/arch/x86/include/asm/compat.h
@@ -229,7 +229,7 @@ static inline void __user *arch_compat_alloc_user_space(long len)
                sp = task_pt_regs(current)->sp;
        } else {
                /* -128 for the x32 ABI redzone */
-                sp = percpu_read(old_rsp) - 128;
+                sp = this_cpu_read(old_rsp) - 128;
        }
        return (void __user *)round_down(sp - len, 16);
diff --git a/arch/x86/include/asm/current.h b/arch/x86/include/asm/current.h
index 4d447b732d82..9476c04ee635 100644
--- a/arch/x86/include/asm/current.h
+++ b/arch/x86/include/asm/current.h
@@ -11,7 +11,7 @@ DECLARE_PER_CPU(struct task_struct *, current_task);
 static __always_inline struct task_struct *get_current(void)
 {
-        return percpu_read_stable(current_task);
+        return this_cpu_read_stable(current_task);
 }
 #define current get_current()
diff --git a/arch/x86/include/asm/desc.h b/arch/x86/include/asm/desc.h
index e95822d683f4..8bf1c06070d5 100644
--- a/arch/x86/include/asm/desc.h
+++ b/arch/x86/include/asm/desc.h
@@ -6,6 +6,7 @@
 #include <asm/mmu.h>
 #include <linux/smp.h>
+#include <linux/percpu.h>
 static inline void fill_ldt(struct desc_struct *desc, const struct user_desc *info)
 {
diff --git a/arch/x86/include/asm/fpu-internal.h b/arch/x86/include/asm/fpu-internal.h
index 4fa88154e4de..75f4c6d6a331 100644
--- a/arch/x86/include/asm/fpu-internal.h
+++ b/arch/x86/include/asm/fpu-internal.h
@@ -290,14 +290,14 @@ static inline int __thread_has_fpu(struct task_struct *tsk)
 static inline void __thread_clear_has_fpu(struct task_struct *tsk)
 {
        tsk->thread.fpu.has_fpu = 0;
-        percpu_write(fpu_owner_task, NULL);
+        this_cpu_write(fpu_owner_task, NULL);
 }
 /* Must be paired with a 'clts' before! */
 static inline void __thread_set_has_fpu(struct task_struct *tsk)
 {
        tsk->thread.fpu.has_fpu = 1;
-        percpu_write(fpu_owner_task, tsk);
+        this_cpu_write(fpu_owner_task, tsk);
 }
 /*
@@ -344,7 +344,7 @@ typedef struct { int preload; } fpu_switch_t;
 */
 static inline int fpu_lazy_restore(struct task_struct *new, unsigned int cpu)
 {
-        return new == percpu_read_stable(fpu_owner_task) &&
+        return new == this_cpu_read_stable(fpu_owner_task) &&
                cpu == new->thread.fpu.last_cpu;
 }
diff --git a/arch/x86/include/asm/ftrace.h b/arch/x86/include/asm/ftrace.h
index 268c783ab1c0..18d9005d9e4f 100644
--- a/arch/x86/include/asm/ftrace.h
+++ b/arch/x86/include/asm/ftrace.h
@@ -34,6 +34,7 @@
 #ifndef __ASSEMBLY__
 extern void mcount(void);
+extern int modifying_ftrace_code;
 static inline unsigned long ftrace_call_adjust(unsigned long addr)
 {
@@ -50,6 +51,8 @@ struct dyn_arch_ftrace {
        /* No extra data needed for x86 */
 };
+int ftrace_int3_handler(struct pt_regs *regs);
 #endif /*  CONFIG_DYNAMIC_FTRACE */
 #endif /* __ASSEMBLY__ */
 #endif /* CONFIG_FUNCTION_TRACER */
diff --git a/arch/x86/include/asm/hardirq.h b/arch/x86/include/asm/hardirq.h
index 382f75d735f3..d3895dbf4ddb 100644
--- a/arch/x86/include/asm/hardirq.h
+++ b/arch/x86/include/asm/hardirq.h
@@ -35,14 +35,15 @@ DECLARE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t, irq_stat);
 #define __ARCH_IRQ_STAT
-#define inc_irq_stat(member)    percpu_inc(irq_stat.member)
+#define inc_irq_stat(member)    this_cpu_inc(irq_stat.member)
-#define local_softirq_pending() percpu_read(irq_stat.__softirq_pending)
+#define local_softirq_pending() this_cpu_read(irq_stat.__softirq_pending)
 #define __ARCH_SET_SOFTIRQ_PENDING
-#define set_softirq_pending(x)  percpu_write(irq_stat.__softirq_pending, (x))
+#define set_softirq_pending(x)  \
-#define or_softirq_pending(x)   percpu_or(irq_stat.__softirq_pending, (x))
+                this_cpu_write(irq_stat.__softirq_pending, (x))
+#define or_softirq_pending(x)   this_cpu_or(irq_stat.__softirq_pending, (x))
 extern void ack_bad_irq(unsigned int irq);
diff --git a/arch/x86/include/asm/ia32.h b/arch/x86/include/asm/ia32.h
index ee52760549f0..b04cbdb138cd 100644
--- a/arch/x86/include/asm/ia32.h
+++ b/arch/x86/include/asm/ia32.h
@@ -144,6 +144,12 @@ typedef struct compat_siginfo {
                        int _band;      /* POLL_IN, POLL_OUT, POLL_MSG */
                        int _fd;
                } _sigpoll;
+                struct {
+                        unsigned int _call_addr; /* calling insn */
+                        int _syscall;   /* triggering system call number */
+                        unsigned int _arch;     /* AUDIT_ARCH_* of syscall */
+                } _sigsys;
        } _sifields;
 } compat_siginfo_t;
diff --git a/arch/x86/include/asm/io_apic.h b/arch/x86/include/asm/io_apic.h
index 2c4943de5150..73d8c5398ea9 100644
--- a/arch/x86/include/asm/io_apic.h
+++ b/arch/x86/include/asm/io_apic.h
@@ -5,7 +5,7 @@
 #include <asm/mpspec.h>
 #include <asm/apicdef.h>
 #include <asm/irq_vectors.h>
+#include <asm/x86_init.h>
 /*
 * Intel IO-APIC support for SMP and UP systems.
 *
@@ -21,15 +21,6 @@
 #define IO_APIC_REDIR_LEVEL_TRIGGER     (1 << 15)
 #define IO_APIC_REDIR_MASKED            (1 << 16)
-struct io_apic_ops {
-        void            (*init)  (void);
-        unsigned int    (*read)  (unsigned int apic, unsigned int reg);
-        void            (*write) (unsigned int apic, unsigned int reg, unsigned int value);
-        void            (*modify)(unsigned int apic, unsigned int reg, unsigned int value);
-};
-void __init set_io_apic_ops(const struct io_apic_ops *);
 /*
 * The structure of the IO-APIC:
 */
@@ -156,7 +147,6 @@ struct io_apic_irq_attr;
 extern int io_apic_set_pci_routing(struct device *dev, int irq,
                 struct io_apic_irq_attr *irq_attr);
 void setup_IO_APIC_irq_extra(u32 gsi);
-extern void ioapic_and_gsi_init(void);
 extern void ioapic_insert_resources(void);
 int io_apic_setup_irq_pin_once(unsigned int irq, int node, struct io_apic_irq_attr *attr);
@@ -185,12 +175,29 @@ extern void mp_save_irq(struct mpc_intsrc *m);
 extern void disable_ioapic_support(void);
+extern void __init native_io_apic_init_mappings(void);
+extern unsigned int native_io_apic_read(unsigned int apic, unsigned int reg);
+extern void native_io_apic_write(unsigned int apic, unsigned int reg, unsigned int val);
+extern void native_io_apic_modify(unsigned int apic, unsigned int reg, unsigned int val);
+static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
+{
+        return x86_io_apic_ops.read(apic, reg);
+}
+static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
+{
+        x86_io_apic_ops.write(apic, reg, value);
+}
+static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
+{
+        x86_io_apic_ops.modify(apic, reg, value);
+}
 #else  /* !CONFIG_X86_IO_APIC */
 #define io_apic_assign_pci_irqs 0
 #define setup_ioapic_ids_from_mpc x86_init_noop
 static const int timer_through_8259 = 0;
-static inline void ioapic_and_gsi_init(void) { }
 static inline void ioapic_insert_resources(void) { }
 #define gsi_top (NR_IRQS_LEGACY)
 static inline int mp_find_ioapic(u32 gsi) { return 0; }
@@ -212,6 +219,10 @@ static inline int restore_ioapic_entries(void)
 static inline void mp_save_irq(struct mpc_intsrc *m) { };
 static inline void disable_ioapic_support(void) { }
+#define native_io_apic_init_mappings    NULL
+#define native_io_apic_read             NULL
+#define native_io_apic_write            NULL
+#define native_io_apic_modify           NULL
 #endif
 #endif /* _ASM_X86_IO_APIC_H */
diff --git a/arch/x86/include/asm/irq_regs.h b/arch/x86/include/asm/irq_regs.h
index 77843225b7ea..d82250b1debb 100644
--- a/arch/x86/include/asm/irq_regs.h
+++ b/arch/x86/include/asm/irq_regs.h
@@ -15,7 +15,7 @@ DECLARE_PER_CPU(struct pt_regs *, irq_regs);
 static inline struct pt_regs *get_irq_regs(void)
 {
-        return percpu_read(irq_regs);
+        return this_cpu_read(irq_regs);
 }
 static inline struct pt_regs *set_irq_regs(struct pt_regs *new_regs)
@@ -23,7 +23,7 @@ static inline struct pt_regs *set_irq_regs(struct pt_regs *new_regs)
        struct pt_regs *old_regs;
        old_regs = get_irq_regs();
-        percpu_write(irq_regs, new_regs);
+        this_cpu_write(irq_regs, new_regs);
        return old_regs;
 }
diff --git a/arch/x86/include/asm/irq_remapping.h b/arch/x86/include/asm/irq_remapping.h
index 47d99934580f..5fb9bbbd2f14 100644
--- a/arch/x86/include/asm/irq_remapping.h
+++ b/arch/x86/include/asm/irq_remapping.h
@@ -1,45 +1,101 @@
-#ifndef _ASM_X86_IRQ_REMAPPING_H
+/*
-#define _ASM_X86_IRQ_REMAPPING_H
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Author: Joerg Roedel <joerg.roedel@amd.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ * This header file contains the interface of the interrupt remapping code to
+ * the x86 interrupt management code.
+ */
-#define IRTE_DEST(dest) ((x2apic_mode) ? dest : dest << 8)
+#ifndef __X86_IRQ_REMAPPING_H
+#define __X86_IRQ_REMAPPING_H
+#include <asm/io_apic.h>
 #ifdef CONFIG_IRQ_REMAP
-static void irq_remap_modify_chip_defaults(struct irq_chip *chip);
-static inline void prepare_irte(struct irte *irte, int vector,
+extern int irq_remapping_enabled;
-                                unsigned int dest)
+extern void setup_irq_remapping_ops(void);
+extern int irq_remapping_supported(void);
+extern int irq_remapping_prepare(void);
+extern int irq_remapping_enable(void);
+extern void irq_remapping_disable(void);
+extern int irq_remapping_reenable(int);
+extern int irq_remap_enable_fault_handling(void);
+extern int setup_ioapic_remapped_entry(int irq,
+                                       struct IO_APIC_route_entry *entry,
+                                       unsigned int destination,
+                                       int vector,
+                                       struct io_apic_irq_attr *attr);
+extern int set_remapped_irq_affinity(struct irq_data *data,
+                                     const struct cpumask *mask,
+                                     bool force);
+extern void free_remapped_irq(int irq);
+extern void compose_remapped_msi_msg(struct pci_dev *pdev,
+                                     unsigned int irq, unsigned int dest,
+                                     struct msi_msg *msg, u8 hpet_id);
+extern int msi_alloc_remapped_irq(struct pci_dev *pdev, int irq, int nvec);
+extern int msi_setup_remapped_irq(struct pci_dev *pdev, unsigned int irq,
+                                  int index, int sub_handle);
+extern int setup_hpet_msi_remapped(unsigned int irq, unsigned int id);
+#else  /* CONFIG_IRQ_REMAP */
+#define irq_remapping_enabled   0
+static inline void setup_irq_remapping_ops(void) { }
+static inline int irq_remapping_supported(void) { return 0; }
+static inline int irq_remapping_prepare(void) { return -ENODEV; }
+static inline int irq_remapping_enable(void) { return -ENODEV; }
+static inline void irq_remapping_disable(void) { }
+static inline int irq_remapping_reenable(int eim) { return -ENODEV; }
+static inline int irq_remap_enable_fault_handling(void) { return -ENODEV; }
+static inline int setup_ioapic_remapped_entry(int irq,
+                                              struct IO_APIC_route_entry *entry,
+                                              unsigned int destination,
+                                              int vector,
+                                              struct io_apic_irq_attr *attr)
+{
+        return -ENODEV;
+}
+static inline int set_remapped_irq_affinity(struct irq_data *data,
+                                            const struct cpumask *mask,
+                                            bool force)
 {
-        memset(irte, 0, sizeof(*irte));
+        return 0;
-        irte->present = 1;
-        irte->dst_mode = apic->irq_dest_mode;
-        /*
-         * Trigger mode in the IRTE will always be edge, and for IO-APIC, the
-         * actual level or edge trigger will be setup in the IO-APIC
-         * RTE. This will help simplify level triggered irq migration.
-         * For more details, see the comments (in io_apic.c) explainig IO-APIC
-         * irq migration in the presence of interrupt-remapping.
-        */
-        irte->trigger_mode = 0;
-        irte->dlvry_mode = apic->irq_delivery_mode;
-        irte->vector = vector;
-        irte->dest_id = IRTE_DEST(dest);
-        irte->redir_hint = 1;
 }
-static inline bool irq_remapped(struct irq_cfg *cfg)
+static inline void free_remapped_irq(int irq) { }
+static inline void compose_remapped_msi_msg(struct pci_dev *pdev,
+                                            unsigned int irq, unsigned int dest,
+                                            struct msi_msg *msg, u8 hpet_id)
 {
-        return cfg->irq_2_iommu.iommu != NULL;
 }
-#else
+static inline int msi_alloc_remapped_irq(struct pci_dev *pdev, int irq, int nvec)
-static void prepare_irte(struct irte *irte, int vector, unsigned int dest)
 {
+        return -ENODEV;
 }
-static inline bool irq_remapped(struct irq_cfg *cfg)
+static inline int msi_setup_remapped_irq(struct pci_dev *pdev, unsigned int irq,
+                                         int index, int sub_handle)
 {
-        return false;
+        return -ENODEV;
 }
-static inline void irq_remap_modify_chip_defaults(struct irq_chip *chip)
+static inline int setup_hpet_msi_remapped(unsigned int irq, unsigned int id)
 {
+        return -ENODEV;
 }
-#endif
+#endif /* CONFIG_IRQ_REMAP */
-#endif  /* _ASM_X86_IRQ_REMAPPING_H */
+#endif /* __X86_IRQ_REMAPPING_H */
diff --git a/arch/x86/include/asm/kvm_para.h b/arch/x86/include/asm/kvm_para.h
index 734c3767cfac..183922e13de1 100644
--- a/arch/x86/include/asm/kvm_para.h
+++ b/arch/x86/include/asm/kvm_para.h
@@ -170,6 +170,9 @@ static inline int kvm_para_available(void)
        unsigned int eax, ebx, ecx, edx;
        char signature[13];
+        if (boot_cpu_data.cpuid_level < 0)
+                return 0;       /* So we don't blow up on old processors */
        cpuid(KVM_CPUID_SIGNATURE, &eax, &ebx, &ecx, &edx);
        memcpy(signature + 0, &ebx, 4);
        memcpy(signature + 4, &ecx, 4);
diff --git a/arch/x86/include/asm/mmu_context.h b/arch/x86/include/asm/mmu_context.h
index 69021528b43c..cdbf36776106 100644
--- a/arch/x86/include/asm/mmu_context.h
+++ b/arch/x86/include/asm/mmu_context.h
@@ -25,8 +25,8 @@ void destroy_context(struct mm_struct *mm);
 static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
 {
 #ifdef CONFIG_SMP
-        if (percpu_read(cpu_tlbstate.state) == TLBSTATE_OK)
+        if (this_cpu_read(cpu_tlbstate.state) == TLBSTATE_OK)
-                percpu_write(cpu_tlbstate.state, TLBSTATE_LAZY);
+                this_cpu_write(cpu_tlbstate.state, TLBSTATE_LAZY);
 #endif
 }
@@ -37,8 +37,8 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
        if (likely(prev != next)) {
 #ifdef CONFIG_SMP
-                percpu_write(cpu_tlbstate.state, TLBSTATE_OK);
+                this_cpu_write(cpu_tlbstate.state, TLBSTATE_OK);
-                percpu_write(cpu_tlbstate.active_mm, next);
+                this_cpu_write(cpu_tlbstate.active_mm, next);
 #endif
                cpumask_set_cpu(cpu, mm_cpumask(next));
@@ -56,8 +56,8 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
        }
 #ifdef CONFIG_SMP
        else {
-                percpu_write(cpu_tlbstate.state, TLBSTATE_OK);
+                this_cpu_write(cpu_tlbstate.state, TLBSTATE_OK);
-                BUG_ON(percpu_read(cpu_tlbstate.active_mm) != next);
+                BUG_ON(this_cpu_read(cpu_tlbstate.active_mm) != next);
                if (!cpumask_test_and_set_cpu(cpu, mm_cpumask(next))) {
                        /* We were in lazy tlb mode and leave_mm disabled
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index ccb805966f68..957ec87385af 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -134,6 +134,8 @@
 #define MSR_AMD64_IBSFETCHCTL           0xc0011030
 #define MSR_AMD64_IBSFETCHLINAD         0xc0011031
 #define MSR_AMD64_IBSFETCHPHYSAD        0xc0011032
+#define MSR_AMD64_IBSFETCH_REG_COUNT    3
+#define MSR_AMD64_IBSFETCH_REG_MASK     ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1)
 #define MSR_AMD64_IBSOPCTL              0xc0011033
 #define MSR_AMD64_IBSOPRIP              0xc0011034
 #define MSR_AMD64_IBSOPDATA             0xc0011035
@@ -141,8 +143,11 @@
 #define MSR_AMD64_IBSOPDATA3            0xc0011037
 #define MSR_AMD64_IBSDCLINAD            0xc0011038
 #define MSR_AMD64_IBSDCPHYSAD           0xc0011039
+#define MSR_AMD64_IBSOP_REG_COUNT       7
+#define MSR_AMD64_IBSOP_REG_MASK        ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1)
 #define MSR_AMD64_IBSCTL                0xc001103a
 #define MSR_AMD64_IBSBRTARGET           0xc001103b
+#define MSR_AMD64_IBS_REG_COUNT_MAX     8 /* includes MSR_AMD64_IBSBRTARGET */
 /* Fam 15h MSRs */
 #define MSR_F15H_PERF_CTL               0xc0010200
diff --git a/arch/x86/include/asm/nmi.h b/arch/x86/include/asm/nmi.h
index fd3f9f18cf3f..0e3793b821ef 100644
--- a/arch/x86/include/asm/nmi.h
+++ b/arch/x86/include/asm/nmi.h
@@ -27,6 +27,8 @@ void arch_trigger_all_cpu_backtrace(void);
 enum {
        NMI_LOCAL=0,
        NMI_UNKNOWN,
+        NMI_SERR,
+        NMI_IO_CHECK,
        NMI_MAX
 };
@@ -35,8 +37,24 @@ enum {
 typedef int (*nmi_handler_t)(unsigned int, struct pt_regs *);
-int register_nmi_handler(unsigned int, nmi_handler_t, unsigned long,
+struct nmiaction {
-                         const char *);
+        struct list_head        list;
+        nmi_handler_t           handler;
+        unsigned long           flags;
+        const char              *name;
+};
+#define register_nmi_handler(t, fn, fg, n)              \
+({                                                      \
+        static struct nmiaction fn##_na = {             \
+                .handler = (fn),                        \
+                .name = (n),                            \
+                .flags = (fg),                          \
+        };                                              \
+        __register_nmi_handler((t), &fn##_na);  \
+})
+int __register_nmi_handler(unsigned int, struct nmiaction *);
 void unregister_nmi_handler(unsigned int, const char *);
diff --git a/arch/x86/include/asm/page_32_types.h b/arch/x86/include/asm/page_32_types.h
index ade619ff9e2a..ef17af013475 100644
--- a/arch/x86/include/asm/page_32_types.h
+++ b/arch/x86/include/asm/page_32_types.h
@@ -15,8 +15,8 @@
 */
 #define __PAGE_OFFSET           _AC(CONFIG_PAGE_OFFSET, UL)
-#define THREAD_ORDER    1
+#define THREAD_SIZE_ORDER       1
-#define THREAD_SIZE     (PAGE_SIZE << THREAD_ORDER)
+#define THREAD_SIZE             (PAGE_SIZE << THREAD_SIZE_ORDER)
 #define STACKFAULT_STACK 0
 #define DOUBLEFAULT_STACK 1
diff --git a/arch/x86/include/asm/page_64_types.h b/arch/x86/include/asm/page_64_types.h
index 7639dbf5d223..320f7bb95f76 100644
--- a/arch/x86/include/asm/page_64_types.h
+++ b/arch/x86/include/asm/page_64_types.h
@@ -1,8 +1,8 @@
 #ifndef _ASM_X86_PAGE_64_DEFS_H
 #define _ASM_X86_PAGE_64_DEFS_H
-#define THREAD_ORDER    1
+#define THREAD_SIZE_ORDER       1
-#define THREAD_SIZE  (PAGE_SIZE << THREAD_ORDER)
+#define THREAD_SIZE  (PAGE_SIZE << THREAD_SIZE_ORDER)
 #define CURRENT_MASK (~(THREAD_SIZE - 1))
 #define EXCEPTION_STACK_ORDER 0
diff --git a/arch/x86/include/asm/percpu.h b/arch/x86/include/asm/percpu.h
index 7a11910a63c4..d9b8e3f7f42a 100644
--- a/arch/x86/include/asm/percpu.h
+++ b/arch/x86/include/asm/percpu.h
@@ -46,7 +46,7 @@
 #ifdef CONFIG_SMP
 #define __percpu_prefix         "%%"__stringify(__percpu_seg)":"
-#define __my_cpu_offset         percpu_read(this_cpu_off)
+#define __my_cpu_offset         this_cpu_read(this_cpu_off)
 /*
 * Compared to the generic __my_cpu_offset version, the following
@@ -351,23 +351,15 @@ do {									\
 })
 /*
- * percpu_read() makes gcc load the percpu variable every time it is
+ * this_cpu_read() makes gcc load the percpu variable every time it is
- * accessed while percpu_read_stable() allows the value to be cached.
+ * accessed while this_cpu_read_stable() allows the value to be cached.
- * percpu_read_stable() is more efficient and can be used if its value
+ * this_cpu_read_stable() is more efficient and can be used if its value
 * is guaranteed to be valid across cpus.  The current users include
 * get_current() and get_thread_info() both of which are actually
 * per-thread variables implemented as per-cpu variables and thus
 * stable for the duration of the respective task.
 */
-#define percpu_read(var)                percpu_from_op("mov", var, "m" (var))
+#define this_cpu_read_stable(var)       percpu_from_op("mov", var, "p" (&(var)))
-#define percpu_read_stable(var)         percpu_from_op("mov", var, "p" (&(var)))
-#define percpu_write(var, val)          percpu_to_op("mov", var, val)
-#define percpu_add(var, val)            percpu_add_op(var, val)
-#define percpu_sub(var, val)            percpu_add_op(var, -(val))
-#define percpu_and(var, val)            percpu_to_op("and", var, val)
-#define percpu_or(var, val)             percpu_to_op("or", var, val)
-#define percpu_xor(var, val)            percpu_to_op("xor", var, val)
-#define percpu_inc(var)         percpu_unary_op("inc", var)
 #define __this_cpu_read_1(pcp)          percpu_from_op("mov", (pcp), "m"(pcp))
 #define __this_cpu_read_2(pcp)          percpu_from_op("mov", (pcp), "m"(pcp))
@@ -512,7 +504,11 @@ static __always_inline int x86_this_cpu_constant_test_bit(unsigned int nr,
 {
        unsigned long __percpu *a = (unsigned long *)addr + nr / BITS_PER_LONG;
-        return ((1UL << (nr % BITS_PER_LONG)) & percpu_read(*a)) != 0;
+#ifdef CONFIG_X86_64
+        return ((1UL << (nr % BITS_PER_LONG)) & __this_cpu_read_8(*a)) != 0;
+#else
+        return ((1UL << (nr % BITS_PER_LONG)) & __this_cpu_read_4(*a)) != 0;
+#endif
 }
 static inline int x86_this_cpu_variable_test_bit(int nr,
diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
index 2291895b1836..588f52ea810e 100644
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -158,6 +158,7 @@ struct x86_pmu_capability {
 #define IBS_CAPS_OPCNT                  (1U<<4)
 #define IBS_CAPS_BRNTRGT                (1U<<5)
 #define IBS_CAPS_OPCNTEXT               (1U<<6)
+#define IBS_CAPS_RIPINVALIDCHK          (1U<<7)
 #define IBS_CAPS_DEFAULT                (IBS_CAPS_AVAIL         \
                                         | IBS_CAPS_FETCHSAM    \
@@ -170,21 +171,28 @@ struct x86_pmu_capability {
 #define IBSCTL_LVT_OFFSET_VALID         (1ULL<<8)
 #define IBSCTL_LVT_OFFSET_MASK          0x0F
-/* IbsFetchCtl bits/masks */
+/* ibs fetch bits/masks */
 #define IBS_FETCH_RAND_EN       (1ULL<<57)
 #define IBS_FETCH_VAL           (1ULL<<49)
 #define IBS_FETCH_ENABLE        (1ULL<<48)
 #define IBS_FETCH_CNT           0xFFFF0000ULL
 #define IBS_FETCH_MAX_CNT       0x0000FFFFULL
-/* IbsOpCtl bits */
+/* ibs op bits/masks */
+/* lower 4 bits of the current count are ignored: */
+#define IBS_OP_CUR_CNT          (0xFFFF0ULL<<32)
 #define IBS_OP_CNT_CTL          (1ULL<<19)
 #define IBS_OP_VAL              (1ULL<<18)
 #define IBS_OP_ENABLE           (1ULL<<17)
 #define IBS_OP_MAX_CNT          0x0000FFFFULL
 #define IBS_OP_MAX_CNT_EXT      0x007FFFFFULL   /* not a register bit mask */
+#define IBS_RIP_INVALID         (1ULL<<38)
+#ifdef CONFIG_X86_LOCAL_APIC
 extern u32 get_ibs_caps(void);
+#else
+static inline u32 get_ibs_caps(void) { return 0; }
+#endif
 #ifdef CONFIG_PERF_EVENTS
 extern void perf_events_lapic_init(void);
diff --git a/arch/x86/include/asm/posix_types.h b/arch/x86/include/asm/posix_types.h
index 3427b7798dbc..7ef7c3020e5c 100644
--- a/arch/x86/include/asm/posix_types.h
+++ b/arch/x86/include/asm/posix_types.h
@@ -7,9 +7,9 @@
 #else
 # ifdef __i386__
 #  include "posix_types_32.h"
-# elif defined(__LP64__)
+# elif defined(__ILP32__)
-#  include "posix_types_64.h"
-# else
 #  include "posix_types_x32.h"
+# else
+#  include "posix_types_64.h"
 # endif
 #endif
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index 4fa7dcceb6c0..ccbb1ea99ccb 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -974,8 +974,6 @@ extern bool cpu_has_amd_erratum(const int *);
 #define cpu_has_amd_erratum(x)  (false)
 #endif /* CONFIG_CPU_SUP_AMD */
-void cpu_idle_wait(void);
 extern unsigned long arch_align_stack(unsigned long sp);
 extern void free_init_pages(char *what, unsigned long begin, unsigned long end);
diff --git a/arch/x86/include/asm/sigcontext.h b/arch/x86/include/asm/sigcontext.h
index 4a085383af27..5ca71c065eef 100644
--- a/arch/x86/include/asm/sigcontext.h
+++ b/arch/x86/include/asm/sigcontext.h
@@ -257,7 +257,7 @@ struct sigcontext {
        __u64 oldmask;
        __u64 cr2;
        struct _fpstate __user *fpstate;        /* zero when no FPU context */
-#ifndef __LP64__
+#ifdef __ILP32__
        __u32 __fpstate_pad;
 #endif
        __u64 reserved1[8];
diff --git a/arch/x86/include/asm/siginfo.h b/arch/x86/include/asm/siginfo.h
index fc1aa5535646..34c47b3341c0 100644
--- a/arch/x86/include/asm/siginfo.h
+++ b/arch/x86/include/asm/siginfo.h
@@ -2,7 +2,13 @@
 #define _ASM_X86_SIGINFO_H
 #ifdef __x86_64__
-# define __ARCH_SI_PREAMBLE_SIZE        (4 * sizeof(int))
+# ifdef __ILP32__ /* x32 */
+typedef long long __kernel_si_clock_t __attribute__((aligned(4)));
+#  define __ARCH_SI_CLOCK_T             __kernel_si_clock_t
+#  define __ARCH_SI_ATTRIBUTES          __attribute__((aligned(8)))
+# else /* x86-64 */
+#  define __ARCH_SI_PREAMBLE_SIZE       (4 * sizeof(int))
+# endif
 #endif
 #include <asm-generic/siginfo.h>
diff --git a/arch/x86/include/asm/smp.h b/arch/x86/include/asm/smp.h
index 0434c400287c..f48394513c37 100644
--- a/arch/x86/include/asm/smp.h
+++ b/arch/x86/include/asm/smp.h
@@ -62,6 +62,8 @@ DECLARE_EARLY_PER_CPU(int, x86_cpu_to_logical_apicid);
 /* Static state in head.S used to set up a CPU */
 extern unsigned long stack_start; /* Initial stack pointer address */
+struct task_struct;
 struct smp_ops {
        void (*smp_prepare_boot_cpu)(void);
        void (*smp_prepare_cpus)(unsigned max_cpus);
@@ -70,7 +72,7 @@ struct smp_ops {
        void (*stop_other_cpus)(int wait);
        void (*smp_send_reschedule)(int cpu);
-        int (*cpu_up)(unsigned cpu);
+        int (*cpu_up)(unsigned cpu, struct task_struct *tidle);
        int (*cpu_disable)(void);
        void (*cpu_die)(unsigned int cpu);
        void (*play_dead)(void);
@@ -113,9 +115,9 @@ static inline void smp_cpus_done(unsigned int max_cpus)
        smp_ops.smp_cpus_done(max_cpus);
 }
-static inline int __cpu_up(unsigned int cpu)
+static inline int __cpu_up(unsigned int cpu, struct task_struct *tidle)
 {
-        return smp_ops.cpu_up(cpu);
+        return smp_ops.cpu_up(cpu, tidle);
 }
 static inline int __cpu_disable(void)
@@ -152,7 +154,7 @@ void cpu_disable_common(void);
 void native_smp_prepare_boot_cpu(void);
 void native_smp_prepare_cpus(unsigned int max_cpus);
 void native_smp_cpus_done(unsigned int max_cpus);
-int native_cpu_up(unsigned int cpunum);
+int native_cpu_up(unsigned int cpunum, struct task_struct *tidle);
 int native_cpu_disable(void);
 void native_cpu_die(unsigned int cpu);
 void native_play_dead(void);
@@ -162,6 +164,7 @@ int wbinvd_on_all_cpus(void);
 void native_send_call_func_ipi(const struct cpumask *mask);
 void native_send_call_func_single_ipi(int cpu);
+void x86_idle_thread_init(unsigned int cpu, struct task_struct *idle);
 void smp_store_cpu_info(int id);
 #define cpu_physical_id(cpu)    per_cpu(x86_cpu_to_apicid, cpu)
@@ -188,11 +191,11 @@ extern unsigned disabled_cpus __cpuinitdata;
 * from the initial startup. We map APIC_BASE very early in page_setup(),
 * so this is correct in the x86 case.
 */
-#define raw_smp_processor_id() (percpu_read(cpu_number))
+#define raw_smp_processor_id() (this_cpu_read(cpu_number))
 extern int safe_smp_processor_id(void);
 #elif defined(CONFIG_X86_64_SMP)
-#define raw_smp_processor_id() (percpu_read(cpu_number))
+#define raw_smp_processor_id() (this_cpu_read(cpu_number))
 #define stack_smp_processor_id()                                        \
 ({                                                              \
diff --git a/arch/x86/include/asm/stackprotector.h b/arch/x86/include/asm/stackprotector.h
index b5d9533d2c38..6a998598f172 100644
--- a/arch/x86/include/asm/stackprotector.h
+++ b/arch/x86/include/asm/stackprotector.h
@@ -75,9 +75,9 @@ static __always_inline void boot_init_stack_canary(void)
        current->stack_canary = canary;
 #ifdef CONFIG_X86_64
-        percpu_write(irq_stack_union.stack_canary, canary);
+        this_cpu_write(irq_stack_union.stack_canary, canary);
 #else
-        percpu_write(stack_canary.canary, canary);
+        this_cpu_write(stack_canary.canary, canary);
 #endif
 }
diff --git a/arch/x86/include/asm/stat.h b/arch/x86/include/asm/stat.h
index e0b1d9bbcbc6..7b3ddc348585 100644
--- a/arch/x86/include/asm/stat.h
+++ b/arch/x86/include/asm/stat.h
@@ -25,6 +25,12 @@ struct stat {
        unsigned long  __unused5;
 };
+/* We don't need to memset the whole thing just to initialize the padding */
+#define INIT_STRUCT_STAT_PADDING(st) do {       \
+        st.__unused4 = 0;                       \
+        st.__unused5 = 0;                       \
+} while (0)
 #define STAT64_HAS_BROKEN_ST_INO        1
 /* This matches struct stat64 in glibc2.1, hence the absolutely
@@ -63,6 +69,12 @@ struct stat64 {
        unsigned long long      st_ino;
 };
+/* We don't need to memset the whole thing just to initialize the padding */
+#define INIT_STRUCT_STAT64_PADDING(st) do {             \
+        memset(&st.__pad0, 0, sizeof(st.__pad0));       \
+        memset(&st.__pad3, 0, sizeof(st.__pad3));       \
+} while (0)
 #else /* __i386__ */
 struct stat {
@@ -87,6 +99,15 @@ struct stat {
        unsigned long   st_ctime_nsec;
        long            __unused[3];
 };
+/* We don't need to memset the whole thing just to initialize the padding */
+#define INIT_STRUCT_STAT_PADDING(st) do {       \
+        st.__pad0 = 0;                          \
+        st.__unused[0] = 0;                     \
+        st.__unused[1] = 0;                     \
+        st.__unused[2] = 0;                     \
+} while (0)
 #endif
 /* for 32bit emulation and 32 bit kernels */
diff --git a/arch/x86/include/asm/syscall.h b/arch/x86/include/asm/syscall.h
index 386b78686c4d..1ace47b62592 100644
--- a/arch/x86/include/asm/syscall.h
+++ b/arch/x86/include/asm/syscall.h
@@ -13,9 +13,11 @@
 #ifndef _ASM_X86_SYSCALL_H
 #define _ASM_X86_SYSCALL_H
+#include <linux/audit.h>
 #include <linux/sched.h>
 #include <linux/err.h>
 #include <asm/asm-offsets.h>    /* For NR_syscalls */
+#include <asm/thread_info.h>    /* for TS_COMPAT */
 #include <asm/unistd.h>
 extern const unsigned long sys_call_table[];
@@ -88,6 +90,12 @@ static inline void syscall_set_arguments(struct task_struct *task,
        memcpy(&regs->bx + i, args, n * sizeof(args[0]));
 }
+static inline int syscall_get_arch(struct task_struct *task,
+                                   struct pt_regs *regs)
+{
+        return AUDIT_ARCH_I386;
+}
 #else    /* CONFIG_X86_64 */
 static inline void syscall_get_arguments(struct task_struct *task,
@@ -212,6 +220,25 @@ static inline void syscall_set_arguments(struct task_struct *task,
                }
 }
+static inline int syscall_get_arch(struct task_struct *task,
+                                   struct pt_regs *regs)
+{
+#ifdef CONFIG_IA32_EMULATION
+        /*
+         * TS_COMPAT is set for 32-bit syscall entry and then
+         * remains set until we return to user mode.
+         *
+         * TIF_IA32 tasks should always have TS_COMPAT set at
+         * system call time.
+         *
+         * x32 tasks should be considered AUDIT_ARCH_X86_64.
+         */
+        if (task_thread_info(task)->status & TS_COMPAT)
+                return AUDIT_ARCH_I386;
+#endif
+        /* Both x32 and x86_64 are considered "64-bit". */
+        return AUDIT_ARCH_X86_64;
+}
 #endif  /* CONFIG_X86_32 */
 #endif  /* _ASM_X86_SYSCALL_H */
diff --git a/arch/x86/include/asm/thread_info.h b/arch/x86/include/asm/thread_info.h
index ad6df8ccd715..3c9aebc00d39 100644
--- a/arch/x86/include/asm/thread_info.h
+++ b/arch/x86/include/asm/thread_info.h
@@ -155,24 +155,6 @@ struct thread_info {
 #define PREEMPT_ACTIVE          0x10000000
-/* thread information allocation */
-#ifdef CONFIG_DEBUG_STACK_USAGE
-#define THREAD_FLAGS (GFP_KERNEL | __GFP_NOTRACK | __GFP_ZERO)
-#else
-#define THREAD_FLAGS (GFP_KERNEL | __GFP_NOTRACK)
-#endif
-#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR
-#define alloc_thread_info_node(tsk, node)                               \
-({                                                                      \
-        struct page *page = alloc_pages_node(node, THREAD_FLAGS,        \
-                                             THREAD_ORDER);             \
-        struct thread_info *ret = page ? page_address(page) : NULL;     \
-                                                                        \
-        ret;                                                            \
-})
 #ifdef CONFIG_X86_32
 #define STACK_WARN      (THREAD_SIZE/8)
@@ -222,7 +204,7 @@ DECLARE_PER_CPU(unsigned long, kernel_stack);
 static inline struct thread_info *current_thread_info(void)
 {
        struct thread_info *ti;
-        ti = (void *)(percpu_read_stable(kernel_stack) +
+        ti = (void *)(this_cpu_read_stable(kernel_stack) +
                      KERNEL_STACK_OFFSET - THREAD_SIZE);
        return ti;
 }
@@ -282,8 +264,7 @@ static inline bool is_ia32_task(void)
 #ifndef __ASSEMBLY__
 extern void arch_task_cache_init(void);
-extern void free_thread_info(struct thread_info *ti);
 extern int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src);
-#define arch_task_cache_init arch_task_cache_init
+extern void arch_release_task_struct(struct task_struct *tsk);
 #endif
 #endif /* _ASM_X86_THREAD_INFO_H */
diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h
index c0e108e08079..1620d23f14d7 100644
--- a/arch/x86/include/asm/tlbflush.h
+++ b/arch/x86/include/asm/tlbflush.h
@@ -156,8 +156,8 @@ DECLARE_PER_CPU_SHARED_ALIGNED(struct tlb_state, cpu_tlbstate);
 static inline void reset_lazy_tlbstate(void)
 {
-        percpu_write(cpu_tlbstate.state, 0);
+        this_cpu_write(cpu_tlbstate.state, 0);
-        percpu_write(cpu_tlbstate.active_mm, &init_mm);
+        this_cpu_write(cpu_tlbstate.active_mm, &init_mm);
 }
 #endif  /* SMP */
diff --git a/arch/x86/include/asm/topology.h b/arch/x86/include/asm/topology.h
index b9676ae37ada..095b21507b6a 100644
--- a/arch/x86/include/asm/topology.h
+++ b/arch/x86/include/asm/topology.h
@@ -92,44 +92,6 @@ extern void setup_node_to_cpumask_map(void);
 #define pcibus_to_node(bus) __pcibus_to_node(bus)
-#ifdef CONFIG_X86_32
-# define SD_CACHE_NICE_TRIES    1
-# define SD_IDLE_IDX            1
-#else
-# define SD_CACHE_NICE_TRIES    2
-# define SD_IDLE_IDX            2
-#endif
-/* sched_domains SD_NODE_INIT for NUMA machines */
-#define SD_NODE_INIT (struct sched_domain) {                            \
-        .min_interval           = 8,                                    \
-        .max_interval           = 32,                                   \
-        .busy_factor            = 32,                                   \
-        .imbalance_pct          = 125,                                  \
-        .cache_nice_tries       = SD_CACHE_NICE_TRIES,                  \
-        .busy_idx               = 3,                                    \
-        .idle_idx               = SD_IDLE_IDX,                          \
-        .newidle_idx            = 0,                                    \
-        .wake_idx               = 0,                                    \
-        .forkexec_idx           = 0,                                    \
-                                                                        \
-        .flags                  = 1*SD_LOAD_BALANCE                     \
-                                | 1*SD_BALANCE_NEWIDLE                  \
-                                | 1*SD_BALANCE_EXEC                     \
-                                | 1*SD_BALANCE_FORK                     \
-                                | 0*SD_BALANCE_WAKE                     \
-                                | 1*SD_WAKE_AFFINE                      \
-                                | 0*SD_PREFER_LOCAL                     \
-                                | 0*SD_SHARE_CPUPOWER                   \
-                                | 0*SD_POWERSAVINGS_BALANCE             \
-                                | 0*SD_SHARE_PKG_RESOURCES              \
-                                | 1*SD_SERIALIZE                        \
-                                | 0*SD_PREFER_SIBLING                   \
-                                ,                                       \
-        .last_balance           = jiffies,                              \
-        .balance_interval       = 1,                                    \
-}
 extern int __node_distance(int, int);
 #define node_distance(a, b) __node_distance(a, b)
diff --git a/arch/x86/include/asm/uaccess.h b/arch/x86/include/asm/uaccess.h
index 8be5f54d9360..e0544597cfe7 100644
--- a/arch/x86/include/asm/uaccess.h
+++ b/arch/x86/include/asm/uaccess.h
@@ -557,6 +557,8 @@ struct __large_struct { unsigned long buf[100]; };
 extern unsigned long
 copy_from_user_nmi(void *to, const void __user *from, unsigned long n);
+extern __must_check long
+strncpy_from_user(char *dst, const char __user *src, long count);
 /*
 * movsl can be slow when source and dest are not both 8-byte aligned
diff --git a/arch/x86/include/asm/uaccess_32.h b/arch/x86/include/asm/uaccess_32.h
index 566e803cc602..8084bc73b18c 100644
--- a/arch/x86/include/asm/uaccess_32.h
+++ b/arch/x86/include/asm/uaccess_32.h
@@ -213,11 +213,6 @@ static inline unsigned long __must_check copy_from_user(void *to,
        return n;
 }
-long __must_check strncpy_from_user(char *dst, const char __user *src,
-                                    long count);
-long __must_check __strncpy_from_user(char *dst,
-                                      const char __user *src, long count);
 /**
 * strlen_user: - Get the size of a string in user space.
 * @str: The string to measure.
diff --git a/arch/x86/include/asm/uaccess_64.h b/arch/x86/include/asm/uaccess_64.h
index 1c66d30971ad..fcd4b6f3ef02 100644
--- a/arch/x86/include/asm/uaccess_64.h
+++ b/arch/x86/include/asm/uaccess_64.h
@@ -208,10 +208,6 @@ int __copy_in_user(void __user *dst, const void __user *src, unsigned size)
        }
 }
-__must_check long
-strncpy_from_user(char *dst, const char __user *src, long count);
-__must_check long
-__strncpy_from_user(char *dst, const char __user *src, long count);
 __must_check long strnlen_user(const char __user *str, long n);
 __must_check long __strnlen_user(const char __user *str, long n);
 __must_check long strlen_user(const char __user *str);
diff --git a/arch/x86/include/asm/unistd.h b/arch/x86/include/asm/unistd.h
index 37cdc9d99bb1..4437001d8e3d 100644
--- a/arch/x86/include/asm/unistd.h
+++ b/arch/x86/include/asm/unistd.h
@@ -63,10 +63,10 @@
 #else
 # ifdef __i386__
 #  include <asm/unistd_32.h>
-# elif defined(__LP64__)
+# elif defined(__ILP32__)
-#  include <asm/unistd_64.h>
-# else
 #  include <asm/unistd_x32.h>
+# else
+#  include <asm/unistd_64.h>
 # endif
 #endif
diff --git a/arch/x86/include/asm/word-at-a-time.h b/arch/x86/include/asm/word-at-a-time.h
index 6fe6767b7124..e58f03b206c3 100644
--- a/arch/x86/include/asm/word-at-a-time.h
+++ b/arch/x86/include/asm/word-at-a-time.h
@@ -43,4 +43,37 @@ static inline unsigned long has_zero(unsigned long a)
        return ((a - REPEAT_BYTE(0x01)) & ~a) & REPEAT_BYTE(0x80);
 }
+/*
+ * Load an unaligned word from kernel space.
+ *
+ * In the (very unlikely) case of the word being a page-crosser
+ * and the next page not being mapped, take the exception and
+ * return zeroes in the non-existing part.
+ */
+static inline unsigned long load_unaligned_zeropad(const void *addr)
+{
+        unsigned long ret, dummy;
+        asm(
+                "1:\tmov %2,%0\n"
+                "2:\n"
+                ".section .fixup,\"ax\"\n"
+                "3:\t"
+                "lea %2,%1\n\t"
+                "and %3,%1\n\t"
+                "mov (%1),%0\n\t"
+                "leal %2,%%ecx\n\t"
+                "andl %4,%%ecx\n\t"
+                "shll $3,%%ecx\n\t"
+                "shr %%cl,%0\n\t"
+                "jmp 2b\n"
+                ".previous\n"
+                _ASM_EXTABLE(1b, 3b)
+                :"=&r" (ret),"=&c" (dummy)
+                :"m" (*(unsigned long *)addr),
+                 "i" (-sizeof(unsigned long)),
+                 "i" (sizeof(unsigned long)-1));
+        return ret;
+}
 #endif /* _ASM_WORD_AT_A_TIME_H */
diff --git a/arch/x86/include/asm/x86_init.h b/arch/x86/include/asm/x86_init.h
index baaca8defec8..c090af10ac7d 100644
--- a/arch/x86/include/asm/x86_init.h
+++ b/arch/x86/include/asm/x86_init.h
@@ -188,13 +188,19 @@ struct x86_msi_ops {
        void (*restore_msi_irqs)(struct pci_dev *dev, int irq);
 };
+struct x86_io_apic_ops {
+        void            (*init)  (void);
+        unsigned int    (*read)  (unsigned int apic, unsigned int reg);
+        void            (*write) (unsigned int apic, unsigned int reg, unsigned int value);
+        void            (*modify)(unsigned int apic, unsigned int reg, unsigned int value);
+};
 extern struct x86_init_ops x86_init;
 extern struct x86_cpuinit_ops x86_cpuinit;
 extern struct x86_platform_ops x86_platform;
 extern struct x86_msi_ops x86_msi;
+extern struct x86_io_apic_ops x86_io_apic_ops;
 extern void x86_init_noop(void);
 extern void x86_init_uint_noop(unsigned int unused);
-extern void x86_default_fixup_cpu_id(struct cpuinfo_x86 *c, int node);
 #endif
diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile
index 532d2e090e6f..56ebd1f98447 100644
--- a/arch/x86/kernel/Makefile
+++ b/arch/x86/kernel/Makefile
@@ -2,7 +2,7 @@
 # Makefile for the linux kernel.
 #
-extra-y                := head_$(BITS).o head$(BITS).o head.o init_task.o vmlinux.lds
+extra-y                := head_$(BITS).o head$(BITS).o head.o vmlinux.lds
 CPPFLAGS_vmlinux.lds += -U$(UTS_MACHINE)
diff --git a/arch/x86/kernel/acpi/boot.c b/arch/x86/kernel/acpi/boot.c
index a415b1f44365..7c439fe4941b 100644
--- a/arch/x86/kernel/acpi/boot.c
+++ b/arch/x86/kernel/acpi/boot.c
@@ -593,7 +593,7 @@ void __init acpi_set_irq_model_ioapic(void)
 #ifdef CONFIG_ACPI_HOTPLUG_CPU
 #include <acpi/processor.h>
-static void __cpuinitdata acpi_map_cpu2node(acpi_handle handle, int cpu, int physid)
+static void __cpuinit acpi_map_cpu2node(acpi_handle handle, int cpu, int physid)
 {
 #ifdef CONFIG_ACPI_NUMA
        int nid;
diff --git a/arch/x86/kernel/acpi/sleep.c b/arch/x86/kernel/acpi/sleep.c
index 103b6ab368d3..146a49c763a4 100644
--- a/arch/x86/kernel/acpi/sleep.c
+++ b/arch/x86/kernel/acpi/sleep.c
@@ -24,6 +24,10 @@ unsigned long acpi_realmode_flags;
 static char temp_stack[4096];
 #endif
+asmlinkage void acpi_enter_s3(void)
+{
+        acpi_enter_sleep_state(3, wake_sleep_flags);
+}
 /**
 * acpi_suspend_lowlevel - save kernel state
 *
diff --git a/arch/x86/kernel/acpi/sleep.h b/arch/x86/kernel/acpi/sleep.h
index 416d4be13fef..d68677a2a010 100644
--- a/arch/x86/kernel/acpi/sleep.h
+++ b/arch/x86/kernel/acpi/sleep.h
@@ -3,12 +3,16 @@
 */
 #include <asm/trampoline.h>
+#include <linux/linkage.h>
 extern unsigned long saved_video_mode;
 extern long saved_magic;
 extern int wakeup_pmode_return;
+extern u8 wake_sleep_flags;
+extern asmlinkage void acpi_enter_s3(void);
 extern unsigned long acpi_copy_wakeup_routine(unsigned long);
 extern void wakeup_long64(void);
diff --git a/arch/x86/kernel/acpi/wakeup_32.S b/arch/x86/kernel/acpi/wakeup_32.S
index 13ab720573e3..72610839f03b 100644
--- a/arch/x86/kernel/acpi/wakeup_32.S
+++ b/arch/x86/kernel/acpi/wakeup_32.S
@@ -74,9 +74,7 @@ restore_registers:
 ENTRY(do_suspend_lowlevel)
        call    save_processor_state
        call    save_registers
-        pushl   $3
+        call    acpi_enter_s3
-        call    acpi_enter_sleep_state
-        addl    $4, %esp
 #       In case of S3 failure, we'll emerge here.  Jump
 #       to ret_point to recover
diff --git a/arch/x86/kernel/acpi/wakeup_64.S b/arch/x86/kernel/acpi/wakeup_64.S
index 8ea5164cbd04..014d1d28c397 100644
--- a/arch/x86/kernel/acpi/wakeup_64.S
+++ b/arch/x86/kernel/acpi/wakeup_64.S
@@ -71,9 +71,7 @@ ENTRY(do_suspend_lowlevel)
        movq    %rsi, saved_rsi
        addq    $8, %rsp
-        movl    $3, %edi
+        call    acpi_enter_s3
-        xorl    %eax, %eax
-        call    acpi_enter_sleep_state
        /* in case something went wrong, restore the machine status and go on */
        jmp     resume_point
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index 11544d8f1e97..39a222e094af 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -35,6 +35,7 @@
 #include <linux/smp.h>
 #include <linux/mm.h>
+#include <asm/irq_remapping.h>
 #include <asm/perf_event.h>
 #include <asm/x86_init.h>
 #include <asm/pgalloc.h>
@@ -1325,11 +1326,13 @@ void __cpuinit setup_local_APIC(void)
                               acked);
                        break;
                }
-                if (cpu_has_tsc) {
+                if (queued) {
-                        rdtscll(ntsc);
+                        if (cpu_has_tsc) {
-                        max_loops = (cpu_khz << 10) - (ntsc - tsc);
+                                rdtscll(ntsc);
-                } else
+                                max_loops = (cpu_khz << 10) - (ntsc - tsc);
-                        max_loops--;
+                        } else
+                                max_loops--;
+                }
        } while (queued && max_loops > 0);
        WARN_ON(max_loops <= 0);
@@ -1441,8 +1444,8 @@ void __init bsp_end_local_APIC_setup(void)
         * Now that local APIC setup is completed for BP, configure the fault
         * handling for interrupt remapping.
         */
-        if (intr_remapping_enabled)
+        if (irq_remapping_enabled)
-                enable_drhd_fault_handling();
+                irq_remap_enable_fault_handling();
 }
@@ -1517,7 +1520,7 @@ void enable_x2apic(void)
 int __init enable_IR(void)
 {
 #ifdef CONFIG_IRQ_REMAP
-        if (!intr_remapping_supported()) {
+        if (!irq_remapping_supported()) {
                pr_debug("intr-remapping not supported\n");
                return -1;
        }
@@ -1528,7 +1531,7 @@ int __init enable_IR(void)
                return -1;
        }
-        return enable_intr_remapping();
+        return irq_remapping_enable();
 #endif
        return -1;
 }
@@ -1537,10 +1540,13 @@ void __init enable_IR_x2apic(void)
 {
        unsigned long flags;
        int ret, x2apic_enabled = 0;
-        int dmar_table_init_ret;
+        int hardware_init_ret;
+        /* Make sure irq_remap_ops are initialized */
+        setup_irq_remapping_ops();
-        dmar_table_init_ret = dmar_table_init();
+        hardware_init_ret = irq_remapping_prepare();
-        if (dmar_table_init_ret && !x2apic_supported())
+        if (hardware_init_ret && !x2apic_supported())
                return;
        ret = save_ioapic_entries();
@@ -1556,7 +1562,7 @@ void __init enable_IR_x2apic(void)
        if (x2apic_preenabled && nox2apic)
                disable_x2apic();
-        if (dmar_table_init_ret)
+        if (hardware_init_ret)
                ret = -1;
        else
                ret = enable_IR();
@@ -1637,9 +1643,11 @@ static int __init apic_verify(void)
        mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
        /* The BIOS may have set up the APIC at some other address */
-        rdmsr(MSR_IA32_APICBASE, l, h);
+        if (boot_cpu_data.x86 >= 6) {
-        if (l & MSR_IA32_APICBASE_ENABLE)
+                rdmsr(MSR_IA32_APICBASE, l, h);
-                mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
+                if (l & MSR_IA32_APICBASE_ENABLE)
+                        mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
+        }
        pr_info("Found and enabled local APIC!\n");
        return 0;
@@ -1657,13 +1665,15 @@ int __init apic_force_enable(unsigned long addr)
         * MSR. This can only be done in software for Intel P6 or later
         * and AMD K7 (Model > 1) or later.
         */
-        rdmsr(MSR_IA32_APICBASE, l, h);
+        if (boot_cpu_data.x86 >= 6) {
-        if (!(l & MSR_IA32_APICBASE_ENABLE)) {
+                rdmsr(MSR_IA32_APICBASE, l, h);
-                pr_info("Local APIC disabled by BIOS -- reenabling.\n");
+                if (!(l & MSR_IA32_APICBASE_ENABLE)) {
-                l &= ~MSR_IA32_APICBASE_BASE;
+                        pr_info("Local APIC disabled by BIOS -- reenabling.\n");
-                l |= MSR_IA32_APICBASE_ENABLE | addr;
+                        l &= ~MSR_IA32_APICBASE_BASE;
-                wrmsr(MSR_IA32_APICBASE, l, h);
+                        l |= MSR_IA32_APICBASE_ENABLE | addr;
-                enabled_via_apicbase = 1;
+                        wrmsr(MSR_IA32_APICBASE, l, h);
+                        enabled_via_apicbase = 1;
+                }
        }
        return apic_verify();
 }
@@ -2172,8 +2182,8 @@ static int lapic_suspend(void)
        local_irq_save(flags);
        disable_local_APIC();
-        if (intr_remapping_enabled)
+        if (irq_remapping_enabled)
-                disable_intr_remapping();
+                irq_remapping_disable();
        local_irq_restore(flags);
        return 0;
@@ -2189,7 +2199,7 @@ static void lapic_resume(void)
                return;
        local_irq_save(flags);
-        if (intr_remapping_enabled) {
+        if (irq_remapping_enabled) {
                /*
                 * IO-APIC and PIC have their own resume routines.
                 * We just mask them here to make sure the interrupt
@@ -2209,10 +2219,12 @@ static void lapic_resume(void)
                 * FIXME! This will be wrong if we ever support suspend on
                 * SMP! We'll need to do this as part of the CPU restore!
                 */
-                rdmsr(MSR_IA32_APICBASE, l, h);
+                if (boot_cpu_data.x86 >= 6) {
-                l &= ~MSR_IA32_APICBASE_BASE;
+                        rdmsr(MSR_IA32_APICBASE, l, h);
-                l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
+                        l &= ~MSR_IA32_APICBASE_BASE;
-                wrmsr(MSR_IA32_APICBASE, l, h);
+                        l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
+                        wrmsr(MSR_IA32_APICBASE, l, h);
+                }
        }
        maxlvt = lapic_get_maxlvt();
@@ -2239,8 +2251,8 @@ static void lapic_resume(void)
        apic_write(APIC_ESR, 0);
        apic_read(APIC_ESR);
-        if (intr_remapping_enabled)
+        if (irq_remapping_enabled)
-                reenable_intr_remapping(x2apic_mode);
+                irq_remapping_reenable(x2apic_mode);
        local_irq_restore(flags);
 }
diff --git a/arch/x86/kernel/apic/apic_flat_64.c b/arch/x86/kernel/apic/apic_flat_64.c
index 359b6899a36c..0e881c46e8c8 100644
--- a/arch/x86/kernel/apic/apic_flat_64.c
+++ b/arch/x86/kernel/apic/apic_flat_64.c
@@ -227,6 +227,7 @@ static struct apic apic_flat =  {
        .read                           = native_apic_mem_read,
        .write                          = native_apic_mem_write,
+        .eoi_write                      = native_apic_mem_write,
        .icr_read                       = native_apic_icr_read,
        .icr_write                      = native_apic_icr_write,
        .wait_icr_idle                  = native_apic_wait_icr_idle,
@@ -386,6 +387,7 @@ static struct apic apic_physflat =  {
        .read                           = native_apic_mem_read,
        .write                          = native_apic_mem_write,
+        .eoi_write                      = native_apic_mem_write,
        .icr_read                       = native_apic_icr_read,
        .icr_write                      = native_apic_icr_write,
        .wait_icr_idle                  = native_apic_wait_icr_idle,
diff --git a/arch/x86/kernel/apic/apic_noop.c b/arch/x86/kernel/apic/apic_noop.c
index 634ae6cdd5c9..a6e4c6e06c08 100644
--- a/arch/x86/kernel/apic/apic_noop.c
+++ b/arch/x86/kernel/apic/apic_noop.c
@@ -181,6 +181,7 @@ struct apic apic_noop = {
        .read                           = noop_apic_read,
        .write                          = noop_apic_write,
+        .eoi_write                      = noop_apic_write,
        .icr_read                       = noop_apic_icr_read,
        .icr_write                      = noop_apic_icr_write,
        .wait_icr_idle                  = noop_apic_wait_icr_idle,
diff --git a/arch/x86/kernel/apic/apic_numachip.c b/arch/x86/kernel/apic/apic_numachip.c
index 899803e03214..6ec6d5d297c3 100644
--- a/arch/x86/kernel/apic/apic_numachip.c
+++ b/arch/x86/kernel/apic/apic_numachip.c
@@ -207,8 +207,11 @@ static void __init map_csrs(void)
 static void fixup_cpu_id(struct cpuinfo_x86 *c, int node)
 {
-        c->phys_proc_id = node;
-        per_cpu(cpu_llc_id, smp_processor_id()) = node;
+        if (c->phys_proc_id != node) {
+                c->phys_proc_id = node;
+                per_cpu(cpu_llc_id, smp_processor_id()) = node;
+        }
 }
 static int __init numachip_system_init(void)
@@ -292,6 +295,7 @@ static struct apic apic_numachip __refconst = {
        .read                           = native_apic_mem_read,
        .write                          = native_apic_mem_write,
+        .eoi_write                      = native_apic_mem_write,
        .icr_read                       = native_apic_icr_read,
        .icr_write                      = native_apic_icr_write,
        .wait_icr_idle                  = native_apic_wait_icr_idle,
diff --git a/arch/x86/kernel/apic/bigsmp_32.c b/arch/x86/kernel/apic/bigsmp_32.c
index 0cdec7065aff..31fbdbfbf960 100644
--- a/arch/x86/kernel/apic/bigsmp_32.c
+++ b/arch/x86/kernel/apic/bigsmp_32.c
@@ -248,6 +248,7 @@ static struct apic apic_bigsmp = {
        .read                           = native_apic_mem_read,
        .write                          = native_apic_mem_write,
+        .eoi_write                      = native_apic_mem_write,
        .icr_read                       = native_apic_icr_read,
        .icr_write                      = native_apic_icr_write,
        .wait_icr_idle                  = native_apic_wait_icr_idle,
diff --git a/arch/x86/kernel/apic/es7000_32.c b/arch/x86/kernel/apic/es7000_32.c
index e42d1d3b9134..db4ab1be3c79 100644
--- a/arch/x86/kernel/apic/es7000_32.c
+++ b/arch/x86/kernel/apic/es7000_32.c
@@ -678,6 +678,7 @@ static struct apic __refdata apic_es7000_cluster = {
        .read                           = native_apic_mem_read,
        .write                          = native_apic_mem_write,
+        .eoi_write                      = native_apic_mem_write,
        .icr_read                       = native_apic_icr_read,
        .icr_write                      = native_apic_icr_write,
        .wait_icr_idle                  = native_apic_wait_icr_idle,
@@ -742,6 +743,7 @@ static struct apic __refdata apic_es7000 = {
        .read                           = native_apic_mem_read,
        .write                          = native_apic_mem_write,
+        .eoi_write                      = native_apic_mem_write,
        .icr_read                       = native_apic_icr_read,
        .icr_write                      = native_apic_icr_write,
        .wait_icr_idle                  = native_apic_wait_icr_idle,
diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c
index e88300d8e80a..ffdc152e507d 100644
--- a/arch/x86/kernel/apic/io_apic.c
+++ b/arch/x86/kernel/apic/io_apic.c
@@ -68,23 +68,21 @@
 #define for_each_irq_pin(entry, head) \
        for (entry = head; entry; entry = entry->next)
-static void             __init __ioapic_init_mappings(void);
+#ifdef CONFIG_IRQ_REMAP
+static void irq_remap_modify_chip_defaults(struct irq_chip *chip);
-static unsigned int     __io_apic_read  (unsigned int apic, unsigned int reg);
+static inline bool irq_remapped(struct irq_cfg *cfg)
-static void             __io_apic_write (unsigned int apic, unsigned int reg, unsigned int val);
+{
-static void             __io_apic_modify(unsigned int apic, unsigned int reg, unsigned int val);
+        return cfg->irq_2_iommu.iommu != NULL;
+}
-static struct io_apic_ops io_apic_ops = {
+#else
-        .init   = __ioapic_init_mappings,
+static inline bool irq_remapped(struct irq_cfg *cfg)
-        .read   = __io_apic_read,
+{
-        .write  = __io_apic_write,
+        return false;
-        .modify = __io_apic_modify,
+}
-};
+static inline void irq_remap_modify_chip_defaults(struct irq_chip *chip)
-void __init set_io_apic_ops(const struct io_apic_ops *ops)
 {
-        io_apic_ops = *ops;
 }
+#endif
 /*
 *      Is the SiS APIC rmw bug present ?
@@ -313,21 +311,6 @@ static void free_irq_at(unsigned int at, struct irq_cfg *cfg)
        irq_free_desc(at);
 }
-static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
-{
-        return io_apic_ops.read(apic, reg);
-}
-static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
-{
-        io_apic_ops.write(apic, reg, value);
-}
-static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
-{
-        io_apic_ops.modify(apic, reg, value);
-}
 struct io_apic {
        unsigned int index;
@@ -349,14 +332,14 @@ static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
        writel(vector, &io_apic->eoi);
 }
-static unsigned int __io_apic_read(unsigned int apic, unsigned int reg)
+unsigned int native_io_apic_read(unsigned int apic, unsigned int reg)
 {
        struct io_apic __iomem *io_apic = io_apic_base(apic);
        writel(reg, &io_apic->index);
        return readl(&io_apic->data);
 }
-static void __io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
+void native_io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
 {
        struct io_apic __iomem *io_apic = io_apic_base(apic);
@@ -370,7 +353,7 @@ static void __io_apic_write(unsigned int apic, unsigned int reg, unsigned int va
 *
 * Older SiS APIC requires we rewrite the index register
 */
-static void __io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
+void native_io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
 {
        struct io_apic __iomem *io_apic = io_apic_base(apic);
@@ -379,29 +362,6 @@ static void __io_apic_modify(unsigned int apic, unsigned int reg, unsigned int v
        writel(value, &io_apic->data);
 }
-static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
-{
-        struct irq_pin_list *entry;
-        unsigned long flags;
-        raw_spin_lock_irqsave(&ioapic_lock, flags);
-        for_each_irq_pin(entry, cfg->irq_2_pin) {
-                unsigned int reg;
-                int pin;
-                pin = entry->pin;
-                reg = io_apic_read(entry->apic, 0x10 + pin*2);
-                /* Is the remote IRR bit set? */
-                if (reg & IO_APIC_REDIR_REMOTE_IRR) {
-                        raw_spin_unlock_irqrestore(&ioapic_lock, flags);
-                        return true;
-                }
-        }
-        raw_spin_unlock_irqrestore(&ioapic_lock, flags);
-        return false;
-}
 union entry_union {
        struct { u32 w1, w2; };
        struct IO_APIC_route_entry entry;
@@ -1361,77 +1321,13 @@ static void ioapic_register_intr(unsigned int irq, struct irq_cfg *cfg,
                                      fasteoi ? "fasteoi" : "edge");
 }
-static int setup_ir_ioapic_entry(int irq,
-                              struct IR_IO_APIC_route_entry *entry,
-                              unsigned int destination, int vector,
-                              struct io_apic_irq_attr *attr)
-{
-        int index;
-        struct irte irte;
-        int ioapic_id = mpc_ioapic_id(attr->ioapic);
-        struct intel_iommu *iommu = map_ioapic_to_ir(ioapic_id);
-        if (!iommu) {
-                pr_warn("No mapping iommu for ioapic %d\n", ioapic_id);
-                return -ENODEV;
-        }
-        index = alloc_irte(iommu, irq, 1);
-        if (index < 0) {
-                pr_warn("Failed to allocate IRTE for ioapic %d\n", ioapic_id);
-                return -ENOMEM;
-        }
-        prepare_irte(&irte, vector, destination);
-        /* Set source-id of interrupt request */
-        set_ioapic_sid(&irte, ioapic_id);
-        modify_irte(irq, &irte);
-        apic_printk(APIC_VERBOSE, KERN_DEBUG "IOAPIC[%d]: "
-                "Set IRTE entry (P:%d FPD:%d Dst_Mode:%d "
-                "Redir_hint:%d Trig_Mode:%d Dlvry_Mode:%X "
-                "Avail:%X Vector:%02X Dest:%08X "
-                "SID:%04X SQ:%X SVT:%X)\n",
-                attr->ioapic, irte.present, irte.fpd, irte.dst_mode,
-                irte.redir_hint, irte.trigger_mode, irte.dlvry_mode,
-                irte.avail, irte.vector, irte.dest_id,
-                irte.sid, irte.sq, irte.svt);
-        memset(entry, 0, sizeof(*entry));
-        entry->index2   = (index >> 15) & 0x1;
-        entry->zero     = 0;
-        entry->format   = 1;
-        entry->index    = (index & 0x7fff);
-        /*
-         * IO-APIC RTE will be configured with virtual vector.
-         * irq handler will do the explicit EOI to the io-apic.
-         */
-        entry->vector   = attr->ioapic_pin;
-        entry->mask     = 0;                    /* enable IRQ */
-        entry->trigger  = attr->trigger;
-        entry->polarity = attr->polarity;
-        /* Mask level triggered irqs.
-         * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
-         */
-        if (attr->trigger)
-                entry->mask = 1;
-        return 0;
-}
 static int setup_ioapic_entry(int irq, struct IO_APIC_route_entry *entry,
                               unsigned int destination, int vector,
                               struct io_apic_irq_attr *attr)
 {
-        if (intr_remapping_enabled)
+        if (irq_remapping_enabled)
-                return setup_ir_ioapic_entry(irq,
+                return setup_ioapic_remapped_entry(irq, entry, destination,
-                         (struct IR_IO_APIC_route_entry *)entry,
+                                                   vector, attr);
-                         destination, vector, attr);
        memset(entry, 0, sizeof(*entry));
@@ -1588,7 +1484,7 @@ static void __init setup_timer_IRQ0_pin(unsigned int ioapic_idx,
 {
        struct IO_APIC_route_entry entry;
-        if (intr_remapping_enabled)
+        if (irq_remapping_enabled)
                return;
        memset(&entry, 0, sizeof(entry));
@@ -1674,7 +1570,7 @@ __apicdebuginit(void) print_IO_APIC(int ioapic_idx)
        printk(KERN_DEBUG ".... IRQ redirection table:\n");
-        if (intr_remapping_enabled) {
+        if (irq_remapping_enabled) {
                printk(KERN_DEBUG " NR Indx Fmt Mask Trig IRR"
                        " Pol Stat Indx2 Zero Vect:\n");
        } else {
@@ -1683,7 +1579,7 @@ __apicdebuginit(void) print_IO_APIC(int ioapic_idx)
        }
        for (i = 0; i <= reg_01.bits.entries; i++) {
-                if (intr_remapping_enabled) {
+                if (irq_remapping_enabled) {
                        struct IO_APIC_route_entry entry;
                        struct IR_IO_APIC_route_entry *ir_entry;
@@ -2050,7 +1946,7 @@ void disable_IO_APIC(void)
         * IOAPIC RTE as well as interrupt-remapping table entry).
         * As this gets called during crash dump, keep this simple for now.
         */
-        if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) {
+        if (ioapic_i8259.pin != -1 && !irq_remapping_enabled) {
                struct IO_APIC_route_entry entry;
                memset(&entry, 0, sizeof(entry));
@@ -2074,7 +1970,7 @@ void disable_IO_APIC(void)
         * Use virtual wire A mode when interrupt remapping is enabled.
         */
        if (cpu_has_apic || apic_from_smp_config())
-                disconnect_bsp_APIC(!intr_remapping_enabled &&
+                disconnect_bsp_APIC(!irq_remapping_enabled &&
                                ioapic_i8259.pin != -1);
 }
@@ -2390,71 +2286,6 @@ ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
        return ret;
 }
-#ifdef CONFIG_IRQ_REMAP
-/*
- * Migrate the IO-APIC irq in the presence of intr-remapping.
- *
- * For both level and edge triggered, irq migration is a simple atomic
- * update(of vector and cpu destination) of IRTE and flush the hardware cache.
- *
- * For level triggered, we eliminate the io-apic RTE modification (with the
- * updated vector information), by using a virtual vector (io-apic pin number).
- * Real vector that is used for interrupting cpu will be coming from
- * the interrupt-remapping table entry.
- *
- * As the migration is a simple atomic update of IRTE, the same mechanism
- * is used to migrate MSI irq's in the presence of interrupt-remapping.
- */
-static int
-ir_ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
-                       bool force)
-{
-        struct irq_cfg *cfg = data->chip_data;
-        unsigned int dest, irq = data->irq;
-        struct irte irte;
-        if (!cpumask_intersects(mask, cpu_online_mask))
-                return -EINVAL;
-        if (get_irte(irq, &irte))
-                return -EBUSY;
-        if (assign_irq_vector(irq, cfg, mask))
-                return -EBUSY;
-        dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask);
-        irte.vector = cfg->vector;
-        irte.dest_id = IRTE_DEST(dest);
-        /*
-         * Atomically updates the IRTE with the new destination, vector
-         * and flushes the interrupt entry cache.
-         */
-        modify_irte(irq, &irte);
-        /*
-         * After this point, all the interrupts will start arriving
-         * at the new destination. So, time to cleanup the previous
-         * vector allocation.
-         */
-        if (cfg->move_in_progress)
-                send_cleanup_vector(cfg);
-        cpumask_copy(data->affinity, mask);
-        return 0;
-}
-#else
-static inline int
-ir_ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
-                       bool force)
-{
-        return 0;
-}
-#endif
 asmlinkage void smp_irq_move_cleanup_interrupt(void)
 {
        unsigned vector, me;
@@ -2552,6 +2383,29 @@ static void ack_apic_edge(struct irq_data *data)
 atomic_t irq_mis_count;
 #ifdef CONFIG_GENERIC_PENDING_IRQ
+static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
+{
+        struct irq_pin_list *entry;
+        unsigned long flags;
+        raw_spin_lock_irqsave(&ioapic_lock, flags);
+        for_each_irq_pin(entry, cfg->irq_2_pin) {
+                unsigned int reg;
+                int pin;
+                pin = entry->pin;
+                reg = io_apic_read(entry->apic, 0x10 + pin*2);
+                /* Is the remote IRR bit set? */
+                if (reg & IO_APIC_REDIR_REMOTE_IRR) {
+                        raw_spin_unlock_irqrestore(&ioapic_lock, flags);
+                        return true;
+                }
+        }
+        raw_spin_unlock_irqrestore(&ioapic_lock, flags);
+        return false;
+}
 static inline bool ioapic_irqd_mask(struct irq_data *data, struct irq_cfg *cfg)
 {
        /* If we are moving the irq we need to mask it */
@@ -2699,7 +2553,7 @@ static void irq_remap_modify_chip_defaults(struct irq_chip *chip)
        chip->irq_eoi = ir_ack_apic_level;
 #ifdef CONFIG_SMP
-        chip->irq_set_affinity = ir_ioapic_set_affinity;
+        chip->irq_set_affinity = set_remapped_irq_affinity;
 #endif
 }
 #endif /* CONFIG_IRQ_REMAP */
@@ -2912,7 +2766,7 @@ static inline void __init check_timer(void)
         * 8259A.
         */
        if (pin1 == -1) {
-                if (intr_remapping_enabled)
+                if (irq_remapping_enabled)
                        panic("BIOS bug: timer not connected to IO-APIC");
                pin1 = pin2;
                apic1 = apic2;
@@ -2945,7 +2799,7 @@ static inline void __init check_timer(void)
                                clear_IO_APIC_pin(0, pin1);
                        goto out;
                }
-                if (intr_remapping_enabled)
+                if (irq_remapping_enabled)
                        panic("timer doesn't work through Interrupt-remapped IO-APIC");
                local_irq_disable();
                clear_IO_APIC_pin(apic1, pin1);
@@ -3169,7 +3023,7 @@ void destroy_irq(unsigned int irq)
        irq_set_status_flags(irq, IRQ_NOREQUEST|IRQ_NOPROBE);
        if (irq_remapped(cfg))
-                free_irte(irq);
+                free_remapped_irq(irq);
        raw_spin_lock_irqsave(&vector_lock, flags);
        __clear_irq_vector(irq, cfg);
        raw_spin_unlock_irqrestore(&vector_lock, flags);
@@ -3198,54 +3052,34 @@ static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq,
        dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
        if (irq_remapped(cfg)) {
-                struct irte irte;
+                compose_remapped_msi_msg(pdev, irq, dest, msg, hpet_id);
-                int ir_index;
+                return err;
-                u16 sub_handle;
+        }
-                ir_index = map_irq_to_irte_handle(irq, &sub_handle);
-                BUG_ON(ir_index == -1);
-                prepare_irte(&irte, cfg->vector, dest);
-                /* Set source-id of interrupt request */
-                if (pdev)
-                        set_msi_sid(&irte, pdev);
-                else
-                        set_hpet_sid(&irte, hpet_id);
-                modify_irte(irq, &irte);
+        if (x2apic_enabled())
+                msg->address_hi = MSI_ADDR_BASE_HI |
+                                  MSI_ADDR_EXT_DEST_ID(dest);
+        else
                msg->address_hi = MSI_ADDR_BASE_HI;
-                msg->data = sub_handle;
-                msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
-                                  MSI_ADDR_IR_SHV |
-                                  MSI_ADDR_IR_INDEX1(ir_index) |
-                                  MSI_ADDR_IR_INDEX2(ir_index);
-        } else {
-                if (x2apic_enabled())
-                        msg->address_hi = MSI_ADDR_BASE_HI |
-                                          MSI_ADDR_EXT_DEST_ID(dest);
-                else
-                        msg->address_hi = MSI_ADDR_BASE_HI;
-                msg->address_lo =
+        msg->address_lo =
-                        MSI_ADDR_BASE_LO |
+                MSI_ADDR_BASE_LO |
-                        ((apic->irq_dest_mode == 0) ?
+                ((apic->irq_dest_mode == 0) ?
-                                MSI_ADDR_DEST_MODE_PHYSICAL:
+                        MSI_ADDR_DEST_MODE_PHYSICAL:
-                                MSI_ADDR_DEST_MODE_LOGICAL) |
+                        MSI_ADDR_DEST_MODE_LOGICAL) |
-                        ((apic->irq_delivery_mode != dest_LowestPrio) ?
+                ((apic->irq_delivery_mode != dest_LowestPrio) ?
-                                MSI_ADDR_REDIRECTION_CPU:
+                        MSI_ADDR_REDIRECTION_CPU:
-                                MSI_ADDR_REDIRECTION_LOWPRI) |
+                        MSI_ADDR_REDIRECTION_LOWPRI) |
-                        MSI_ADDR_DEST_ID(dest);
+                MSI_ADDR_DEST_ID(dest);
+        msg->data =
+                MSI_DATA_TRIGGER_EDGE |
+                MSI_DATA_LEVEL_ASSERT |
+                ((apic->irq_delivery_mode != dest_LowestPrio) ?
+                        MSI_DATA_DELIVERY_FIXED:
+                        MSI_DATA_DELIVERY_LOWPRI) |
+                MSI_DATA_VECTOR(cfg->vector);
-                msg->data =
-                        MSI_DATA_TRIGGER_EDGE |
-                        MSI_DATA_LEVEL_ASSERT |
-                        ((apic->irq_delivery_mode != dest_LowestPrio) ?
-                                MSI_DATA_DELIVERY_FIXED:
-                                MSI_DATA_DELIVERY_LOWPRI) |
-                        MSI_DATA_VECTOR(cfg->vector);
-        }
        return err;
 }
@@ -3288,33 +3122,6 @@ static struct irq_chip msi_chip = {
        .irq_retrigger          = ioapic_retrigger_irq,
 };
-/*
- * Map the PCI dev to the corresponding remapping hardware unit
- * and allocate 'nvec' consecutive interrupt-remapping table entries
- * in it.
- */
-static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
-{
-        struct intel_iommu *iommu;
-        int index;
-        iommu = map_dev_to_ir(dev);
-        if (!iommu) {
-                printk(KERN_ERR
-                       "Unable to map PCI %s to iommu\n", pci_name(dev));
-                return -ENOENT;
-        }
-        index = alloc_irte(iommu, irq, nvec);
-        if (index < 0) {
-                printk(KERN_ERR
-                       "Unable to allocate %d IRTE for PCI %s\n", nvec,
-                       pci_name(dev));
-                return -ENOSPC;
-        }
-        return index;
-}
 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
 {
        struct irq_chip *chip = &msi_chip;
@@ -3345,7 +3152,6 @@ int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
        int node, ret, sub_handle, index = 0;
        unsigned int irq, irq_want;
        struct msi_desc *msidesc;
-        struct intel_iommu *iommu = NULL;
        /* x86 doesn't support multiple MSI yet */
        if (type == PCI_CAP_ID_MSI && nvec > 1)
@@ -3359,7 +3165,7 @@ int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
                if (irq == 0)
                        return -1;
                irq_want = irq + 1;
-                if (!intr_remapping_enabled)
+                if (!irq_remapping_enabled)
                        goto no_ir;
                if (!sub_handle) {
@@ -3367,23 +3173,16 @@ int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
                         * allocate the consecutive block of IRTE's
                         * for 'nvec'
                         */
-                        index = msi_alloc_irte(dev, irq, nvec);
+                        index = msi_alloc_remapped_irq(dev, irq, nvec);
                        if (index < 0) {
                                ret = index;
                                goto error;
                        }
                } else {
-                        iommu = map_dev_to_ir(dev);
+                        ret = msi_setup_remapped_irq(dev, irq, index,
-                        if (!iommu) {
+                                                     sub_handle);
-                                ret = -ENOENT;
+                        if (ret < 0)
                                goto error;
-                        }
-                        /*
-                         * setup the mapping between the irq and the IRTE
-                         * base index, the sub_handle pointing to the
-                         * appropriate interrupt remap table entry.
-                         */
-                        set_irte_irq(irq, iommu, index, sub_handle);
                }
 no_ir:
                ret = setup_msi_irq(dev, msidesc, irq);
@@ -3501,15 +3300,8 @@ int arch_setup_hpet_msi(unsigned int irq, unsigned int id)
        struct msi_msg msg;
        int ret;
-        if (intr_remapping_enabled) {
+        if (irq_remapping_enabled) {
-                struct intel_iommu *iommu = map_hpet_to_ir(id);
+                if (!setup_hpet_msi_remapped(irq, id))
-                int index;
-                if (!iommu)
-                        return -1;
-                index = alloc_irte(iommu, irq, 1);
-                if (index < 0)
                        return -1;
        }
@@ -3888,8 +3680,8 @@ void __init setup_ioapic_dest(void)
                else
                        mask = apic->target_cpus();
-                if (intr_remapping_enabled)
+                if (irq_remapping_enabled)
-                        ir_ioapic_set_affinity(idata, mask, false);
+                        set_remapped_irq_affinity(idata, mask, false);
                else
                        ioapic_set_affinity(idata, mask, false);
        }
@@ -3931,12 +3723,7 @@ static struct resource * __init ioapic_setup_resources(int nr_ioapics)
        return res;
 }
-void __init ioapic_and_gsi_init(void)
+void __init native_io_apic_init_mappings(void)
-{
-        io_apic_ops.init();
-}
-static void __init __ioapic_init_mappings(void)
 {
        unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
        struct resource *ioapic_res;
diff --git a/arch/x86/kernel/apic/numaq_32.c b/arch/x86/kernel/apic/numaq_32.c
index 00d2422ca7c9..f00a68cca37a 100644
--- a/arch/x86/kernel/apic/numaq_32.c
+++ b/arch/x86/kernel/apic/numaq_32.c
@@ -530,6 +530,7 @@ static struct apic __refdata apic_numaq = {
        .read                           = native_apic_mem_read,
        .write                          = native_apic_mem_write,
+        .eoi_write                      = native_apic_mem_write,
        .icr_read                       = native_apic_icr_read,
        .icr_write                      = native_apic_icr_write,
        .wait_icr_idle                  = native_apic_wait_icr_idle,
diff --git a/arch/x86/kernel/apic/probe_32.c b/arch/x86/kernel/apic/probe_32.c
index ff2c1b9aac4d..1b291da09e60 100644
--- a/arch/x86/kernel/apic/probe_32.c
+++ b/arch/x86/kernel/apic/probe_32.c
@@ -142,6 +142,7 @@ static struct apic apic_default = {
        .read                           = native_apic_mem_read,
        .write                          = native_apic_mem_write,
+        .eoi_write                      = native_apic_mem_write,
        .icr_read                       = native_apic_icr_read,
        .icr_write                      = native_apic_icr_write,
        .wait_icr_idle                  = native_apic_wait_icr_idle,
diff --git a/arch/x86/kernel/apic/summit_32.c b/arch/x86/kernel/apic/summit_32.c
index fea000b27f07..659897c00755 100644
--- a/arch/x86/kernel/apic/summit_32.c
+++ b/arch/x86/kernel/apic/summit_32.c
@@ -546,6 +546,7 @@ static struct apic apic_summit = {
        .read                           = native_apic_mem_read,
        .write                          = native_apic_mem_write,
+        .eoi_write                      = native_apic_mem_write,
        .icr_read                       = native_apic_icr_read,
        .icr_write                      = native_apic_icr_write,
        .wait_icr_idle                  = native_apic_wait_icr_idle,
diff --git a/arch/x86/kernel/apic/x2apic_cluster.c b/arch/x86/kernel/apic/x2apic_cluster.c
index 48f3103b3c93..ff35cff0e1a7 100644
--- a/arch/x86/kernel/apic/x2apic_cluster.c
+++ b/arch/x86/kernel/apic/x2apic_cluster.c
@@ -260,6 +260,7 @@ static struct apic apic_x2apic_cluster = {
        .read                           = native_apic_msr_read,
        .write                          = native_apic_msr_write,
+        .eoi_write                      = native_apic_msr_eoi_write,
        .icr_read                       = native_x2apic_icr_read,
        .icr_write                      = native_x2apic_icr_write,
        .wait_icr_idle                  = native_x2apic_wait_icr_idle,
diff --git a/arch/x86/kernel/apic/x2apic_phys.c b/arch/x86/kernel/apic/x2apic_phys.c
index 8a778db45e3a..c17e982db275 100644
--- a/arch/x86/kernel/apic/x2apic_phys.c
+++ b/arch/x86/kernel/apic/x2apic_phys.c
@@ -24,6 +24,12 @@ static int x2apic_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
 {
        if (x2apic_phys)
                return x2apic_enabled();
+        else if ((acpi_gbl_FADT.header.revision >= FADT2_REVISION_ID) &&
+                (acpi_gbl_FADT.flags & ACPI_FADT_APIC_PHYSICAL) &&
+                x2apic_enabled()) {
+                printk(KERN_DEBUG "System requires x2apic physical mode\n");
+                return 1;
+        }
        else
                return 0;
 }
@@ -166,6 +172,7 @@ static struct apic apic_x2apic_phys = {
        .read                           = native_apic_msr_read,
        .write                          = native_apic_msr_write,
+        .eoi_write                      = native_apic_msr_eoi_write,
        .icr_read                       = native_x2apic_icr_read,
        .icr_write                      = native_x2apic_icr_write,
        .wait_icr_idle                  = native_x2apic_wait_icr_idle,
diff --git a/arch/x86/kernel/apic/x2apic_uv_x.c b/arch/x86/kernel/apic/x2apic_uv_x.c
index 87bfa69e216e..c6d03f7a4401 100644
--- a/arch/x86/kernel/apic/x2apic_uv_x.c
+++ b/arch/x86/kernel/apic/x2apic_uv_x.c
@@ -404,6 +404,7 @@ static struct apic __refdata apic_x2apic_uv_x = {
        .read                           = native_apic_msr_read,
        .write                          = native_apic_msr_write,
+        .eoi_write                      = native_apic_msr_eoi_write,
        .icr_read                       = native_x2apic_icr_read,
        .icr_write                      = native_x2apic_icr_write,
        .wait_icr_idle                  = native_x2apic_wait_icr_idle,
diff --git a/arch/x86/kernel/apm_32.c b/arch/x86/kernel/apm_32.c
index 459e78cbf61e..07b0c0db466c 100644
--- a/arch/x86/kernel/apm_32.c
+++ b/arch/x86/kernel/apm_32.c
@@ -2401,7 +2401,7 @@ static void __exit apm_exit(void)
                 * (pm_idle), Wait for all processors to update cached/local
                 * copies of pm_idle before proceeding.
                 */
-                cpu_idle_wait();
+                kick_all_cpus_sync();
        }
        if (((apm_info.bios.flags & APM_BIOS_DISENGAGED) == 0)
            && (apm_info.connection_version > 0x0100)) {
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 0a44b90602b0..146bb6218eec 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -26,7 +26,8 @@
 *      contact AMD for precise details and a CPU swap.
 *
 *      See     http://www.multimania.com/poulot/k6bug.html
- *              http://www.amd.com/K6/k6docs/revgd.html
+ *      and     section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6"
+ *              (Publication # 21266  Issue Date: August 1998)
 *
 *      The following test is erm.. interesting. AMD neglected to up
 *      the chip setting when fixing the bug but they also tweaked some
@@ -94,7 +95,6 @@ static void __cpuinit init_amd_k6(struct cpuinfo_x86 *c)
                                "system stability may be impaired when more than 32 MB are used.\n");
                else
                        printk(KERN_CONT "probably OK (after B9730xxxx).\n");
-                printk(KERN_INFO "Please see http://membres.lycos.fr/poulot/k6bug.html\n");
        }
        /* K6 with old style WHCR */
@@ -353,10 +353,11 @@ static void __cpuinit srat_detect_node(struct cpuinfo_x86 *c)
                node = per_cpu(cpu_llc_id, cpu);
        /*
-         * If core numbers are inconsistent, it's likely a multi-fabric platform,
+         * On multi-fabric platform (e.g. Numascale NumaChip) a
-         * so invoke platform-specific handler
+         * platform-specific handler needs to be called to fixup some
+         * IDs of the CPU.
         */
-        if (c->phys_proc_id != node)
+        if (x86_cpuinit.fixup_cpu_id)
                x86_cpuinit.fixup_cpu_id(c, node);
        if (!node_online(node)) {
@@ -579,6 +580,24 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
                }
        }
+        /* re-enable TopologyExtensions if switched off by BIOS */
+        if ((c->x86 == 0x15) &&
+            (c->x86_model >= 0x10) && (c->x86_model <= 0x1f) &&
+            !cpu_has(c, X86_FEATURE_TOPOEXT)) {
+                u64 val;
+                if (!rdmsrl_amd_safe(0xc0011005, &val)) {
+                        val |= 1ULL << 54;
+                        wrmsrl_amd_safe(0xc0011005, val);
+                        rdmsrl(0xc0011005, val);
+                        if (val & (1ULL << 54)) {
+                                set_cpu_cap(c, X86_FEATURE_TOPOEXT);
+                                printk(KERN_INFO FW_INFO "CPU: Re-enabling "
+                                  "disabled Topology Extensions Support\n");
+                        }
+                }
+        }
        cpu_detect_cache_sizes(c);
        /* Multi core CPU? */
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 67e258362a3d..82f29e70d058 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -1163,15 +1163,6 @@ static void dbg_restore_debug_regs(void)
 #endif /* ! CONFIG_KGDB */
 /*
- * Prints an error where the NUMA and configured core-number mismatch and the
- * platform didn't override this to fix it up
- */
-void __cpuinit x86_default_fixup_cpu_id(struct cpuinfo_x86 *c, int node)
-{
-        pr_err("NUMA core number %d differs from configured core number %d\n", node, c->phys_proc_id);
-}
-/*
 * cpu_init() initializes state that is per-CPU. Some data is already
 * initialized (naturally) in the bootstrap process, such as the GDT
 * and IDT. We reload them nevertheless, this function acts as a
@@ -1194,7 +1185,7 @@ void __cpuinit cpu_init(void)
        oist = &per_cpu(orig_ist, cpu);
 #ifdef CONFIG_NUMA
-        if (cpu != 0 && percpu_read(numa_node) == 0 &&
+        if (cpu != 0 && this_cpu_read(numa_node) == 0 &&
            early_cpu_to_node(cpu) != NUMA_NO_NODE)
                set_numa_node(early_cpu_to_node(cpu));
 #endif
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index 73d08ed98a64..b8f3653dddbc 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -433,14 +433,14 @@ int amd_set_l3_disable_slot(struct amd_northbridge *nb, int cpu, unsigned slot,
        /*  check if @slot is already used or the index is already disabled */
        ret = amd_get_l3_disable_slot(nb, slot);
        if (ret >= 0)
-                return -EINVAL;
+                return -EEXIST;
        if (index > nb->l3_cache.indices)
                return -EINVAL;
        /* check whether the other slot has disabled the same index already */
        if (index == amd_get_l3_disable_slot(nb, !slot))
-                return -EINVAL;
+                return -EEXIST;
        amd_l3_disable_index(nb, cpu, slot, index);
@@ -468,8 +468,8 @@ static ssize_t store_cache_disable(struct _cpuid4_info *this_leaf,
        err = amd_set_l3_disable_slot(this_leaf->base.nb, cpu, slot, val);
        if (err) {
                if (err == -EEXIST)
-                        printk(KERN_WARNING "L3 disable slot %d in use!\n",
+                        pr_warning("L3 slot %d in use/index already disabled!\n",
-                                            slot);
+                                   slot);
                return err;
        }
        return count;
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index d086a09c087d..297edb1b1fb3 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -583,7 +583,7 @@ void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
        struct mce m;
        int i;
-        percpu_inc(mce_poll_count);
+        this_cpu_inc(mce_poll_count);
        mce_gather_info(&m, NULL);
@@ -945,9 +945,10 @@ struct mce_info {
        atomic_t                inuse;
        struct task_struct      *t;
        __u64                   paddr;
+        int                     restartable;
 } mce_info[MCE_INFO_MAX];
-static void mce_save_info(__u64 addr)
+static void mce_save_info(__u64 addr, int c)
 {
        struct mce_info *mi;
@@ -955,6 +956,7 @@ static void mce_save_info(__u64 addr)
                if (atomic_cmpxchg(&mi->inuse, 0, 1) == 0) {
                        mi->t = current;
                        mi->paddr = addr;
+                        mi->restartable = c;
                        return;
                }
        }
@@ -1015,7 +1017,7 @@ void do_machine_check(struct pt_regs *regs, long error_code)
        atomic_inc(&mce_entry);
-        percpu_inc(mce_exception_count);
+        this_cpu_inc(mce_exception_count);
        if (!banks)
                goto out;
@@ -1130,7 +1132,7 @@ void do_machine_check(struct pt_regs *regs, long error_code)
                        mce_panic("Fatal machine check on current CPU", &m, msg);
                if (worst == MCE_AR_SEVERITY) {
                        /* schedule action before return to userland */
-                        mce_save_info(m.addr);
+                        mce_save_info(m.addr, m.mcgstatus & MCG_STATUS_RIPV);
                        set_thread_flag(TIF_MCE_NOTIFY);
                } else if (kill_it) {
                        force_sig(SIGBUS, current);
@@ -1179,7 +1181,13 @@ void mce_notify_process(void)
        pr_err("Uncorrected hardware memory error in user-access at %llx",
                 mi->paddr);
-        if (memory_failure(pfn, MCE_VECTOR, MF_ACTION_REQUIRED) < 0) {
+        /*
+         * We must call memory_failure() here even if the current process is
+         * doomed. We still need to mark the page as poisoned and alert any
+         * other users of the page.
+         */
+        if (memory_failure(pfn, MCE_VECTOR, MF_ACTION_REQUIRED) < 0 ||
+                           mi->restartable == 0) {
                pr_err("Memory error not recovered");
                force_sig(SIGBUS, current);
        }
diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c
index bb8e03407e18..e049d6da0183 100644
--- a/arch/x86/kernel/cpu/perf_event.c
+++ b/arch/x86/kernel/cpu/perf_event.c
@@ -484,9 +484,6 @@ static int __x86_pmu_event_init(struct perf_event *event)
        /* mark unused */
        event->hw.extra_reg.idx = EXTRA_REG_NONE;
-        /* mark not used */
-        event->hw.extra_reg.idx = EXTRA_REG_NONE;
        event->hw.branch_reg.idx = EXTRA_REG_NONE;
        return x86_pmu.hw_config(event);
@@ -1186,8 +1183,6 @@ int x86_pmu_handle_irq(struct pt_regs *regs)
        int idx, handled = 0;
        u64 val;
-        perf_sample_data_init(&data, 0);
        cpuc = &__get_cpu_var(cpu_hw_events);
        /*
@@ -1222,7 +1217,7 @@ int x86_pmu_handle_irq(struct pt_regs *regs)
                 * event overflow
                 */
                handled++;
-                data.period     = event->hw.last_period;
+                perf_sample_data_init(&data, 0, event->hw.last_period);
                if (!x86_perf_event_set_period(event))
                        continue;
diff --git a/arch/x86/kernel/cpu/perf_event_amd.c b/arch/x86/kernel/cpu/perf_event_amd.c
index 95e7fe1c5f0b..65652265fffd 100644
--- a/arch/x86/kernel/cpu/perf_event_amd.c
+++ b/arch/x86/kernel/cpu/perf_event_amd.c
@@ -134,8 +134,13 @@ static u64 amd_pmu_event_map(int hw_event)
 static int amd_pmu_hw_config(struct perf_event *event)
 {
-        int ret = x86_pmu_hw_config(event);
+        int ret;
+        /* pass precise event sampling to ibs: */
+        if (event->attr.precise_ip && get_ibs_caps())
+                return -ENOENT;
+        ret = x86_pmu_hw_config(event);
        if (ret)
                return ret;
@@ -205,10 +210,8 @@ static void amd_put_event_constraints(struct cpu_hw_events *cpuc,
         * when we come here
         */
        for (i = 0; i < x86_pmu.num_counters; i++) {
-                if (nb->owners[i] == event) {
+                if (cmpxchg(nb->owners + i, event, NULL) == event)
-                        cmpxchg(nb->owners+i, event, NULL);
                        break;
-                }
        }
 }
diff --git a/arch/x86/kernel/cpu/perf_event_amd_ibs.c b/arch/x86/kernel/cpu/perf_event_amd_ibs.c
index 3b8a2d30d14e..da9bcdcd9856 100644
--- a/arch/x86/kernel/cpu/perf_event_amd_ibs.c
+++ b/arch/x86/kernel/cpu/perf_event_amd_ibs.c
@@ -9,6 +9,7 @@
 #include <linux/perf_event.h>
 #include <linux/module.h>
 #include <linux/pci.h>
+#include <linux/ptrace.h>
 #include <asm/apic.h>
@@ -16,36 +17,591 @@ static u32 ibs_caps;
 #if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD)
-static struct pmu perf_ibs;
+#include <linux/kprobes.h>
+#include <linux/hardirq.h>
+#include <asm/nmi.h>
+#define IBS_FETCH_CONFIG_MASK   (IBS_FETCH_RAND_EN | IBS_FETCH_MAX_CNT)
+#define IBS_OP_CONFIG_MASK      IBS_OP_MAX_CNT
+enum ibs_states {
+        IBS_ENABLED     = 0,
+        IBS_STARTED     = 1,
+        IBS_STOPPING    = 2,
+        IBS_MAX_STATES,
+};
+struct cpu_perf_ibs {
+        struct perf_event       *event;
+        unsigned long           state[BITS_TO_LONGS(IBS_MAX_STATES)];
+};
+struct perf_ibs {
+        struct pmu      pmu;
+        unsigned int    msr;
+        u64             config_mask;
+        u64             cnt_mask;
+        u64             enable_mask;
+        u64             valid_mask;
+        u64             max_period;
+        unsigned long   offset_mask[1];
+        int             offset_max;
+        struct cpu_perf_ibs __percpu *pcpu;
+        u64             (*get_count)(u64 config);
+};
+struct perf_ibs_data {
+        u32             size;
+        union {
+                u32     data[0];        /* data buffer starts here */
+                u32     caps;
+        };
+        u64             regs[MSR_AMD64_IBS_REG_COUNT_MAX];
+};
+static int
+perf_event_set_period(struct hw_perf_event *hwc, u64 min, u64 max, u64 *hw_period)
+{
+        s64 left = local64_read(&hwc->period_left);
+        s64 period = hwc->sample_period;
+        int overflow = 0;
+        /*
+         * If we are way outside a reasonable range then just skip forward:
+         */
+        if (unlikely(left <= -period)) {
+                left = period;
+                local64_set(&hwc->period_left, left);
+                hwc->last_period = period;
+                overflow = 1;
+        }
+        if (unlikely(left < (s64)min)) {
+                left += period;
+                local64_set(&hwc->period_left, left);
+                hwc->last_period = period;
+                overflow = 1;
+        }
+        /*
+         * If the hw period that triggers the sw overflow is too short
+         * we might hit the irq handler. This biases the results.
+         * Thus we shorten the next-to-last period and set the last
+         * period to the max period.
+         */
+        if (left > max) {
+                left -= max;
+                if (left > max)
+                        left = max;
+                else if (left < min)
+                        left = min;
+        }
+        *hw_period = (u64)left;
+        return overflow;
+}
+static  int
+perf_event_try_update(struct perf_event *event, u64 new_raw_count, int width)
+{
+        struct hw_perf_event *hwc = &event->hw;
+        int shift = 64 - width;
+        u64 prev_raw_count;
+        u64 delta;
+        /*
+         * Careful: an NMI might modify the previous event value.
+         *
+         * Our tactic to handle this is to first atomically read and
+         * exchange a new raw count - then add that new-prev delta
+         * count to the generic event atomically:
+         */
+        prev_raw_count = local64_read(&hwc->prev_count);
+        if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
+                                        new_raw_count) != prev_raw_count)
+                return 0;
+        /*
+         * Now we have the new raw value and have updated the prev
+         * timestamp already. We can now calculate the elapsed delta
+         * (event-)time and add that to the generic event.
+         *
+         * Careful, not all hw sign-extends above the physical width
+         * of the count.
+         */
+        delta = (new_raw_count << shift) - (prev_raw_count << shift);
+        delta >>= shift;
+        local64_add(delta, &event->count);
+        local64_sub(delta, &hwc->period_left);
+        return 1;
+}
+static struct perf_ibs perf_ibs_fetch;
+static struct perf_ibs perf_ibs_op;
+static struct perf_ibs *get_ibs_pmu(int type)
+{
+        if (perf_ibs_fetch.pmu.type == type)
+                return &perf_ibs_fetch;
+        if (perf_ibs_op.pmu.type == type)
+                return &perf_ibs_op;
+        return NULL;
+}
+/*
+ * Use IBS for precise event sampling:
+ *
+ *  perf record -a -e cpu-cycles:p ...    # use ibs op counting cycle count
+ *  perf record -a -e r076:p ...          # same as -e cpu-cycles:p
+ *  perf record -a -e r0C1:p ...          # use ibs op counting micro-ops
+ *
+ * IbsOpCntCtl (bit 19) of IBS Execution Control Register (IbsOpCtl,
+ * MSRC001_1033) is used to select either cycle or micro-ops counting
+ * mode.
+ *
+ * The rip of IBS samples has skid 0. Thus, IBS supports precise
+ * levels 1 and 2 and the PERF_EFLAGS_EXACT is set. In rare cases the
+ * rip is invalid when IBS was not able to record the rip correctly.
+ * We clear PERF_EFLAGS_EXACT and take the rip from pt_regs then.
+ *
+ */
+static int perf_ibs_precise_event(struct perf_event *event, u64 *config)
+{
+        switch (event->attr.precise_ip) {
+        case 0:
+                return -ENOENT;
+        case 1:
+        case 2:
+                break;
+        default:
+                return -EOPNOTSUPP;
+        }
+        switch (event->attr.type) {
+        case PERF_TYPE_HARDWARE:
+                switch (event->attr.config) {
+                case PERF_COUNT_HW_CPU_CYCLES:
+                        *config = 0;
+                        return 0;
+                }
+                break;
+        case PERF_TYPE_RAW:
+                switch (event->attr.config) {
+                case 0x0076:
+                        *config = 0;
+                        return 0;
+                case 0x00C1:
+                        *config = IBS_OP_CNT_CTL;
+                        return 0;
+                }
+                break;
+        default:
+                return -ENOENT;
+        }
+        return -EOPNOTSUPP;
+}
 static int perf_ibs_init(struct perf_event *event)
 {
-        if (perf_ibs.type != event->attr.type)
+        struct hw_perf_event *hwc = &event->hw;
+        struct perf_ibs *perf_ibs;
+        u64 max_cnt, config;
+        int ret;
+        perf_ibs = get_ibs_pmu(event->attr.type);
+        if (perf_ibs) {
+                config = event->attr.config;
+        } else {
+                perf_ibs = &perf_ibs_op;
+                ret = perf_ibs_precise_event(event, &config);
+                if (ret)
+                        return ret;
+        }
+        if (event->pmu != &perf_ibs->pmu)
                return -ENOENT;
+        if (config & ~perf_ibs->config_mask)
+                return -EINVAL;
+        if (hwc->sample_period) {
+                if (config & perf_ibs->cnt_mask)
+                        /* raw max_cnt may not be set */
+                        return -EINVAL;
+                if (!event->attr.sample_freq && hwc->sample_period & 0x0f)
+                        /*
+                         * lower 4 bits can not be set in ibs max cnt,
+                         * but allowing it in case we adjust the
+                         * sample period to set a frequency.
+                         */
+                        return -EINVAL;
+                hwc->sample_period &= ~0x0FULL;
+                if (!hwc->sample_period)
+                        hwc->sample_period = 0x10;
+        } else {
+                max_cnt = config & perf_ibs->cnt_mask;
+                config &= ~perf_ibs->cnt_mask;
+                event->attr.sample_period = max_cnt << 4;
+                hwc->sample_period = event->attr.sample_period;
+        }
+        if (!hwc->sample_period)
+                return -EINVAL;
+        /*
+         * If we modify hwc->sample_period, we also need to update
+         * hwc->last_period and hwc->period_left.
+         */
+        hwc->last_period = hwc->sample_period;
+        local64_set(&hwc->period_left, hwc->sample_period);
+        hwc->config_base = perf_ibs->msr;
+        hwc->config = config;
        return 0;
 }
+static int perf_ibs_set_period(struct perf_ibs *perf_ibs,
+                               struct hw_perf_event *hwc, u64 *period)
+{
+        int overflow;
+        /* ignore lower 4 bits in min count: */
+        overflow = perf_event_set_period(hwc, 1<<4, perf_ibs->max_period, period);
+        local64_set(&hwc->prev_count, 0);
+        return overflow;
+}
+static u64 get_ibs_fetch_count(u64 config)
+{
+        return (config & IBS_FETCH_CNT) >> 12;
+}
+static u64 get_ibs_op_count(u64 config)
+{
+        u64 count = 0;
+        if (config & IBS_OP_VAL)
+                count += (config & IBS_OP_MAX_CNT) << 4; /* cnt rolled over */
+        if (ibs_caps & IBS_CAPS_RDWROPCNT)
+                count += (config & IBS_OP_CUR_CNT) >> 32;
+        return count;
+}
+static void
+perf_ibs_event_update(struct perf_ibs *perf_ibs, struct perf_event *event,
+                      u64 *config)
+{
+        u64 count = perf_ibs->get_count(*config);
+        /*
+         * Set width to 64 since we do not overflow on max width but
+         * instead on max count. In perf_ibs_set_period() we clear
+         * prev count manually on overflow.
+         */
+        while (!perf_event_try_update(event, count, 64)) {
+                rdmsrl(event->hw.config_base, *config);
+                count = perf_ibs->get_count(*config);
+        }
+}
+static inline void perf_ibs_enable_event(struct perf_ibs *perf_ibs,
+                                         struct hw_perf_event *hwc, u64 config)
+{
+        wrmsrl(hwc->config_base, hwc->config | config | perf_ibs->enable_mask);
+}
+/*
+ * Erratum #420 Instruction-Based Sampling Engine May Generate
+ * Interrupt that Cannot Be Cleared:
+ *
+ * Must clear counter mask first, then clear the enable bit. See
+ * Revision Guide for AMD Family 10h Processors, Publication #41322.
+ */
+static inline void perf_ibs_disable_event(struct perf_ibs *perf_ibs,
+                                          struct hw_perf_event *hwc, u64 config)
+{
+        config &= ~perf_ibs->cnt_mask;
+        wrmsrl(hwc->config_base, config);
+        config &= ~perf_ibs->enable_mask;
+        wrmsrl(hwc->config_base, config);
+}
+/*
+ * We cannot restore the ibs pmu state, so we always needs to update
+ * the event while stopping it and then reset the state when starting
+ * again. Thus, ignoring PERF_EF_RELOAD and PERF_EF_UPDATE flags in
+ * perf_ibs_start()/perf_ibs_stop() and instead always do it.
+ */
+static void perf_ibs_start(struct perf_event *event, int flags)
+{
+        struct hw_perf_event *hwc = &event->hw;
+        struct perf_ibs *perf_ibs = container_of(event->pmu, struct perf_ibs, pmu);
+        struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);
+        u64 period;
+        if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED)))
+                return;
+        WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
+        hwc->state = 0;
+        perf_ibs_set_period(perf_ibs, hwc, &period);
+        set_bit(IBS_STARTED, pcpu->state);
+        perf_ibs_enable_event(perf_ibs, hwc, period >> 4);
+        perf_event_update_userpage(event);
+}
+static void perf_ibs_stop(struct perf_event *event, int flags)
+{
+        struct hw_perf_event *hwc = &event->hw;
+        struct perf_ibs *perf_ibs = container_of(event->pmu, struct perf_ibs, pmu);
+        struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);
+        u64 config;
+        int stopping;
+        stopping = test_and_clear_bit(IBS_STARTED, pcpu->state);
+        if (!stopping && (hwc->state & PERF_HES_UPTODATE))
+                return;
+        rdmsrl(hwc->config_base, config);
+        if (stopping) {
+                set_bit(IBS_STOPPING, pcpu->state);
+                perf_ibs_disable_event(perf_ibs, hwc, config);
+                WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
+                hwc->state |= PERF_HES_STOPPED;
+        }
+        if (hwc->state & PERF_HES_UPTODATE)
+                return;
+        /*
+         * Clear valid bit to not count rollovers on update, rollovers
+         * are only updated in the irq handler.
+         */
+        config &= ~perf_ibs->valid_mask;
+        perf_ibs_event_update(perf_ibs, event, &config);
+        hwc->state |= PERF_HES_UPTODATE;
+}
 static int perf_ibs_add(struct perf_event *event, int flags)
 {
+        struct perf_ibs *perf_ibs = container_of(event->pmu, struct perf_ibs, pmu);
+        struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);
+        if (test_and_set_bit(IBS_ENABLED, pcpu->state))
+                return -ENOSPC;
+        event->hw.state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
+        pcpu->event = event;
+        if (flags & PERF_EF_START)
+                perf_ibs_start(event, PERF_EF_RELOAD);
        return 0;
 }
 static void perf_ibs_del(struct perf_event *event, int flags)
 {
+        struct perf_ibs *perf_ibs = container_of(event->pmu, struct perf_ibs, pmu);
+        struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);
+        if (!test_and_clear_bit(IBS_ENABLED, pcpu->state))
+                return;
+        perf_ibs_stop(event, PERF_EF_UPDATE);
+        pcpu->event = NULL;
+        perf_event_update_userpage(event);
 }
-static struct pmu perf_ibs = {
+static void perf_ibs_read(struct perf_event *event) { }
-        .event_init= perf_ibs_init,
-        .add= perf_ibs_add,
+static struct perf_ibs perf_ibs_fetch = {
-        .del= perf_ibs_del,
+        .pmu = {
+                .task_ctx_nr    = perf_invalid_context,
+                .event_init     = perf_ibs_init,
+                .add            = perf_ibs_add,
+                .del            = perf_ibs_del,
+                .start          = perf_ibs_start,
+                .stop           = perf_ibs_stop,
+                .read           = perf_ibs_read,
+        },
+        .msr                    = MSR_AMD64_IBSFETCHCTL,
+        .config_mask            = IBS_FETCH_CONFIG_MASK,
+        .cnt_mask               = IBS_FETCH_MAX_CNT,
+        .enable_mask            = IBS_FETCH_ENABLE,
+        .valid_mask             = IBS_FETCH_VAL,
+        .max_period             = IBS_FETCH_MAX_CNT << 4,
+        .offset_mask            = { MSR_AMD64_IBSFETCH_REG_MASK },
+        .offset_max             = MSR_AMD64_IBSFETCH_REG_COUNT,
+        .get_count              = get_ibs_fetch_count,
 };
+static struct perf_ibs perf_ibs_op = {
+        .pmu = {
+                .task_ctx_nr    = perf_invalid_context,
+                .event_init     = perf_ibs_init,
+                .add            = perf_ibs_add,
+                .del            = perf_ibs_del,
+                .start          = perf_ibs_start,
+                .stop           = perf_ibs_stop,
+                .read           = perf_ibs_read,
+        },
+        .msr                    = MSR_AMD64_IBSOPCTL,
+        .config_mask            = IBS_OP_CONFIG_MASK,
+        .cnt_mask               = IBS_OP_MAX_CNT,
+        .enable_mask            = IBS_OP_ENABLE,
+        .valid_mask             = IBS_OP_VAL,
+        .max_period             = IBS_OP_MAX_CNT << 4,
+        .offset_mask            = { MSR_AMD64_IBSOP_REG_MASK },
+        .offset_max             = MSR_AMD64_IBSOP_REG_COUNT,
+        .get_count              = get_ibs_op_count,
+};
+static int perf_ibs_handle_irq(struct perf_ibs *perf_ibs, struct pt_regs *iregs)
+{
+        struct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);
+        struct perf_event *event = pcpu->event;
+        struct hw_perf_event *hwc = &event->hw;
+        struct perf_sample_data data;
+        struct perf_raw_record raw;
+        struct pt_regs regs;
+        struct perf_ibs_data ibs_data;
+        int offset, size, check_rip, offset_max, throttle = 0;
+        unsigned int msr;
+        u64 *buf, *config, period;
+        if (!test_bit(IBS_STARTED, pcpu->state)) {
+                /*
+                 * Catch spurious interrupts after stopping IBS: After
+                 * disabling IBS there could be still incomming NMIs
+                 * with samples that even have the valid bit cleared.
+                 * Mark all this NMIs as handled.
+                 */
+                return test_and_clear_bit(IBS_STOPPING, pcpu->state) ? 1 : 0;
+        }
+        msr = hwc->config_base;
+        buf = ibs_data.regs;
+        rdmsrl(msr, *buf);
+        if (!(*buf++ & perf_ibs->valid_mask))
+                return 0;
+        config = &ibs_data.regs[0];
+        perf_ibs_event_update(perf_ibs, event, config);
+        perf_sample_data_init(&data, 0, hwc->last_period);
+        if (!perf_ibs_set_period(perf_ibs, hwc, &period))
+                goto out;       /* no sw counter overflow */
+        ibs_data.caps = ibs_caps;
+        size = 1;
+        offset = 1;
+        check_rip = (perf_ibs == &perf_ibs_op && (ibs_caps & IBS_CAPS_RIPINVALIDCHK));
+        if (event->attr.sample_type & PERF_SAMPLE_RAW)
+                offset_max = perf_ibs->offset_max;
+        else if (check_rip)
+                offset_max = 2;
+        else
+                offset_max = 1;
+        do {
+                rdmsrl(msr + offset, *buf++);
+                size++;
+                offset = find_next_bit(perf_ibs->offset_mask,
+                                       perf_ibs->offset_max,
+                                       offset + 1);
+        } while (offset < offset_max);
+        ibs_data.size = sizeof(u64) * size;
+        regs = *iregs;
+        if (check_rip && (ibs_data.regs[2] & IBS_RIP_INVALID)) {
+                regs.flags &= ~PERF_EFLAGS_EXACT;
+        } else {
+                instruction_pointer_set(&regs, ibs_data.regs[1]);
+                regs.flags |= PERF_EFLAGS_EXACT;
+        }
+        if (event->attr.sample_type & PERF_SAMPLE_RAW) {
+                raw.size = sizeof(u32) + ibs_data.size;
+                raw.data = ibs_data.data;
+                data.raw = &raw;
+        }
+        throttle = perf_event_overflow(event, &data, &regs);
+out:
+        if (throttle)
+                perf_ibs_disable_event(perf_ibs, hwc, *config);
+        else
+                perf_ibs_enable_event(perf_ibs, hwc, period >> 4);
+        perf_event_update_userpage(event);
+        return 1;
+}
+static int __kprobes
+perf_ibs_nmi_handler(unsigned int cmd, struct pt_regs *regs)
+{
+        int handled = 0;
+        handled += perf_ibs_handle_irq(&perf_ibs_fetch, regs);
+        handled += perf_ibs_handle_irq(&perf_ibs_op, regs);
+        if (handled)
+                inc_irq_stat(apic_perf_irqs);
+        return handled;
+}
+static __init int perf_ibs_pmu_init(struct perf_ibs *perf_ibs, char *name)
+{
+        struct cpu_perf_ibs __percpu *pcpu;
+        int ret;
+        pcpu = alloc_percpu(struct cpu_perf_ibs);
+        if (!pcpu)
+                return -ENOMEM;
+        perf_ibs->pcpu = pcpu;
+        ret = perf_pmu_register(&perf_ibs->pmu, name, -1);
+        if (ret) {
+                perf_ibs->pcpu = NULL;
+                free_percpu(pcpu);
+        }
+        return ret;
+}
 static __init int perf_event_ibs_init(void)
 {
        if (!ibs_caps)
                return -ENODEV; /* ibs not supported by the cpu */
-        perf_pmu_register(&perf_ibs, "ibs", -1);
+        perf_ibs_pmu_init(&perf_ibs_fetch, "ibs_fetch");
+        if (ibs_caps & IBS_CAPS_OPCNT)
+                perf_ibs_op.config_mask |= IBS_OP_CNT_CTL;
+        perf_ibs_pmu_init(&perf_ibs_op, "ibs_op");
+        register_nmi_handler(NMI_LOCAL, perf_ibs_nmi_handler, 0, "perf_ibs");
        printk(KERN_INFO "perf: AMD IBS detected (0x%08x)\n", ibs_caps);
        return 0;
diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index 26b3e2fef104..166546ec6aef 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -1027,8 +1027,6 @@ static int intel_pmu_handle_irq(struct pt_regs *regs)
        u64 status;
        int handled;
-        perf_sample_data_init(&data, 0);
        cpuc = &__get_cpu_var(cpu_hw_events);
        /*
@@ -1082,7 +1080,7 @@ again:
                if (!intel_pmu_save_and_restart(event))
                        continue;
-                data.period = event->hw.last_period;
+                perf_sample_data_init(&data, 0, event->hw.last_period);
                if (has_branch_stack(event))
                        data.br_stack = &cpuc->lbr_stack;
diff --git a/arch/x86/kernel/cpu/perf_event_intel_ds.c b/arch/x86/kernel/cpu/perf_event_intel_ds.c
index 7f64df19e7dd..5a3edc27f6e5 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_ds.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_ds.c
@@ -316,8 +316,7 @@ int intel_pmu_drain_bts_buffer(void)
        ds->bts_index = ds->bts_buffer_base;
-        perf_sample_data_init(&data, 0);
+        perf_sample_data_init(&data, 0, event->hw.last_period);
-        data.period = event->hw.last_period;
        regs.ip     = 0;
        /*
@@ -564,8 +563,7 @@ static void __intel_pmu_pebs_event(struct perf_event *event,
        if (!intel_pmu_save_and_restart(event))
                return;
-        perf_sample_data_init(&data, 0);
+        perf_sample_data_init(&data, 0, event->hw.last_period);
-        data.period = event->hw.last_period;
        /*
         * We use the interrupt regs as a base because the PEBS record
diff --git a/arch/x86/kernel/cpu/perf_event_p4.c b/arch/x86/kernel/cpu/perf_event_p4.c
index a2dfacfd7103..47124a73dd73 100644
--- a/arch/x86/kernel/cpu/perf_event_p4.c
+++ b/arch/x86/kernel/cpu/perf_event_p4.c
@@ -1005,8 +1005,6 @@ static int p4_pmu_handle_irq(struct pt_regs *regs)
        int idx, handled = 0;
        u64 val;
-        perf_sample_data_init(&data, 0);
        cpuc = &__get_cpu_var(cpu_hw_events);
        for (idx = 0; idx < x86_pmu.num_counters; idx++) {
@@ -1034,10 +1032,12 @@ static int p4_pmu_handle_irq(struct pt_regs *regs)
                handled += overflow;
                /* event overflow for sure */
-                data.period = event->hw.last_period;
+                perf_sample_data_init(&data, 0, hwc->last_period);
                if (!x86_perf_event_set_period(event))
                        continue;
                if (perf_event_overflow(event, &data, regs))
                        x86_pmu_stop(event, 0);
        }
diff --git a/arch/x86/kernel/ftrace.c b/arch/x86/kernel/ftrace.c
index c9a281f272fd..32ff36596ab1 100644
--- a/arch/x86/kernel/ftrace.c
+++ b/arch/x86/kernel/ftrace.c
@@ -24,40 +24,21 @@
 #include <trace/syscall.h>
 #include <asm/cacheflush.h>
+#include <asm/kprobes.h>
 #include <asm/ftrace.h>
 #include <asm/nops.h>
-#include <asm/nmi.h>
 #ifdef CONFIG_DYNAMIC_FTRACE
-/*
- * modifying_code is set to notify NMIs that they need to use
- * memory barriers when entering or exiting. But we don't want
- * to burden NMIs with unnecessary memory barriers when code
- * modification is not being done (which is most of the time).
- *
- * A mutex is already held when ftrace_arch_code_modify_prepare
- * and post_process are called. No locks need to be taken here.
- *
- * Stop machine will make sure currently running NMIs are done
- * and new NMIs will see the updated variable before we need
- * to worry about NMIs doing memory barriers.
- */
-static int modifying_code __read_mostly;
-static DEFINE_PER_CPU(int, save_modifying_code);
 int ftrace_arch_code_modify_prepare(void)
 {
        set_kernel_text_rw();
        set_all_modules_text_rw();
-        modifying_code = 1;
        return 0;
 }
 int ftrace_arch_code_modify_post_process(void)
 {
-        modifying_code = 0;
        set_all_modules_text_ro();
        set_kernel_text_ro();
        return 0;
@@ -90,134 +71,6 @@ static unsigned char *ftrace_call_replace(unsigned long ip, unsigned long addr)
        return calc.code;
 }
-/*
- * Modifying code must take extra care. On an SMP machine, if
- * the code being modified is also being executed on another CPU
- * that CPU will have undefined results and possibly take a GPF.
- * We use kstop_machine to stop other CPUS from exectuing code.
- * But this does not stop NMIs from happening. We still need
- * to protect against that. We separate out the modification of
- * the code to take care of this.
- *
- * Two buffers are added: An IP buffer and a "code" buffer.
- *
- * 1) Put the instruction pointer into the IP buffer
- *    and the new code into the "code" buffer.
- * 2) Wait for any running NMIs to finish and set a flag that says
- *    we are modifying code, it is done in an atomic operation.
- * 3) Write the code
- * 4) clear the flag.
- * 5) Wait for any running NMIs to finish.
- *
- * If an NMI is executed, the first thing it does is to call
- * "ftrace_nmi_enter". This will check if the flag is set to write
- * and if it is, it will write what is in the IP and "code" buffers.
- *
- * The trick is, it does not matter if everyone is writing the same
- * content to the code location. Also, if a CPU is executing code
- * it is OK to write to that code location if the contents being written
- * are the same as what exists.
- */
-#define MOD_CODE_WRITE_FLAG (1 << 31)   /* set when NMI should do the write */
-static atomic_t nmi_running = ATOMIC_INIT(0);
-static int mod_code_status;             /* holds return value of text write */
-static void *mod_code_ip;               /* holds the IP to write to */
-static const void *mod_code_newcode;    /* holds the text to write to the IP */
-static unsigned nmi_wait_count;
-static atomic_t nmi_update_count = ATOMIC_INIT(0);
-int ftrace_arch_read_dyn_info(char *buf, int size)
-{
-        int r;
-        r = snprintf(buf, size, "%u %u",
-                     nmi_wait_count,
-                     atomic_read(&nmi_update_count));
-        return r;
-}
-static void clear_mod_flag(void)
-{
-        int old = atomic_read(&nmi_running);
-        for (;;) {
-                int new = old & ~MOD_CODE_WRITE_FLAG;
-                if (old == new)
-                        break;
-                old = atomic_cmpxchg(&nmi_running, old, new);
-        }
-}
-static void ftrace_mod_code(void)
-{
-        /*
-         * Yes, more than one CPU process can be writing to mod_code_status.
-         *    (and the code itself)
-         * But if one were to fail, then they all should, and if one were
-         * to succeed, then they all should.
-         */
-        mod_code_status = probe_kernel_write(mod_code_ip, mod_code_newcode,
-                                             MCOUNT_INSN_SIZE);
-        /* if we fail, then kill any new writers */
-        if (mod_code_status)
-                clear_mod_flag();
-}
-void ftrace_nmi_enter(void)
-{
-        __this_cpu_write(save_modifying_code, modifying_code);
-        if (!__this_cpu_read(save_modifying_code))
-                return;
-        if (atomic_inc_return(&nmi_running) & MOD_CODE_WRITE_FLAG) {
-                smp_rmb();
-                ftrace_mod_code();
-                atomic_inc(&nmi_update_count);
-        }
-        /* Must have previous changes seen before executions */
-        smp_mb();
-}
-void ftrace_nmi_exit(void)
-{
-        if (!__this_cpu_read(save_modifying_code))
-                return;
-        /* Finish all executions before clearing nmi_running */
-        smp_mb();
-        atomic_dec(&nmi_running);
-}
-static void wait_for_nmi_and_set_mod_flag(void)
-{
-        if (!atomic_cmpxchg(&nmi_running, 0, MOD_CODE_WRITE_FLAG))
-                return;
-        do {
-                cpu_relax();
-        } while (atomic_cmpxchg(&nmi_running, 0, MOD_CODE_WRITE_FLAG));
-        nmi_wait_count++;
-}
-static void wait_for_nmi(void)
-{
-        if (!atomic_read(&nmi_running))
-                return;
-        do {
-                cpu_relax();
-        } while (atomic_read(&nmi_running));
-        nmi_wait_count++;
-}
 static inline int
 within(unsigned long addr, unsigned long start, unsigned long end)
 {
@@ -238,26 +91,7 @@ do_ftrace_mod_code(unsigned long ip, const void *new_code)
        if (within(ip, (unsigned long)_text, (unsigned long)_etext))
                ip = (unsigned long)__va(__pa(ip));
-        mod_code_ip = (void *)ip;
+        return probe_kernel_write((void *)ip, new_code, MCOUNT_INSN_SIZE);
-        mod_code_newcode = new_code;
-        /* The buffers need to be visible before we let NMIs write them */
-        smp_mb();
-        wait_for_nmi_and_set_mod_flag();
-        /* Make sure all running NMIs have finished before we write the code */
-        smp_mb();
-        ftrace_mod_code();
-        /* Make sure the write happens before clearing the bit */
-        smp_mb();
-        clear_mod_flag();
-        wait_for_nmi();
-        return mod_code_status;
 }
 static const unsigned char *ftrace_nop_replace(void)
@@ -334,6 +168,336 @@ int ftrace_update_ftrace_func(ftrace_func_t func)
        return ret;
 }
+int modifying_ftrace_code __read_mostly;
+/*
+ * A breakpoint was added to the code address we are about to
+ * modify, and this is the handle that will just skip over it.
+ * We are either changing a nop into a trace call, or a trace
+ * call to a nop. While the change is taking place, we treat
+ * it just like it was a nop.
+ */
+int ftrace_int3_handler(struct pt_regs *regs)
+{
+        if (WARN_ON_ONCE(!regs))
+                return 0;
+        if (!ftrace_location(regs->ip - 1))
+                return 0;
+        regs->ip += MCOUNT_INSN_SIZE - 1;
+        return 1;
+}
+static int ftrace_write(unsigned long ip, const char *val, int size)
+{
+        /*
+         * On x86_64, kernel text mappings are mapped read-only with
+         * CONFIG_DEBUG_RODATA. So we use the kernel identity mapping instead
+         * of the kernel text mapping to modify the kernel text.
+         *
+         * For 32bit kernels, these mappings are same and we can use
+         * kernel identity mapping to modify code.
+         */
+        if (within(ip, (unsigned long)_text, (unsigned long)_etext))
+                ip = (unsigned long)__va(__pa(ip));
+        return probe_kernel_write((void *)ip, val, size);
+}
+static int add_break(unsigned long ip, const char *old)
+{
+        unsigned char replaced[MCOUNT_INSN_SIZE];
+        unsigned char brk = BREAKPOINT_INSTRUCTION;
+        if (probe_kernel_read(replaced, (void *)ip, MCOUNT_INSN_SIZE))
+                return -EFAULT;
+        /* Make sure it is what we expect it to be */
+        if (memcmp(replaced, old, MCOUNT_INSN_SIZE) != 0)
+                return -EINVAL;
+        if (ftrace_write(ip, &brk, 1))
+                return -EPERM;
+        return 0;
+}
+static int add_brk_on_call(struct dyn_ftrace *rec, unsigned long addr)
+{
+        unsigned const char *old;
+        unsigned long ip = rec->ip;
+        old = ftrace_call_replace(ip, addr);
+        return add_break(rec->ip, old);
+}
+static int add_brk_on_nop(struct dyn_ftrace *rec)
+{
+        unsigned const char *old;
+        old = ftrace_nop_replace();
+        return add_break(rec->ip, old);
+}
+static int add_breakpoints(struct dyn_ftrace *rec, int enable)
+{
+        unsigned long ftrace_addr;
+        int ret;
+        ret = ftrace_test_record(rec, enable);
+        ftrace_addr = (unsigned long)FTRACE_ADDR;
+        switch (ret) {
+        case FTRACE_UPDATE_IGNORE:
+                return 0;
+        case FTRACE_UPDATE_MAKE_CALL:
+                /* converting nop to call */
+                return add_brk_on_nop(rec);
+        case FTRACE_UPDATE_MAKE_NOP:
+                /* converting a call to a nop */
+                return add_brk_on_call(rec, ftrace_addr);
+        }
+        return 0;
+}
+/*
+ * On error, we need to remove breakpoints. This needs to
+ * be done caefully. If the address does not currently have a
+ * breakpoint, we know we are done. Otherwise, we look at the
+ * remaining 4 bytes of the instruction. If it matches a nop
+ * we replace the breakpoint with the nop. Otherwise we replace
+ * it with the call instruction.
+ */
+static int remove_breakpoint(struct dyn_ftrace *rec)
+{
+        unsigned char ins[MCOUNT_INSN_SIZE];
+        unsigned char brk = BREAKPOINT_INSTRUCTION;
+        const unsigned char *nop;
+        unsigned long ftrace_addr;
+        unsigned long ip = rec->ip;
+        /* If we fail the read, just give up */
+        if (probe_kernel_read(ins, (void *)ip, MCOUNT_INSN_SIZE))
+                return -EFAULT;
+        /* If this does not have a breakpoint, we are done */
+        if (ins[0] != brk)
+                return -1;
+        nop = ftrace_nop_replace();
+        /*
+         * If the last 4 bytes of the instruction do not match
+         * a nop, then we assume that this is a call to ftrace_addr.
+         */
+        if (memcmp(&ins[1], &nop[1], MCOUNT_INSN_SIZE - 1) != 0) {
+                /*
+                 * For extra paranoidism, we check if the breakpoint is on
+                 * a call that would actually jump to the ftrace_addr.
+                 * If not, don't touch the breakpoint, we make just create
+                 * a disaster.
+                 */
+                ftrace_addr = (unsigned long)FTRACE_ADDR;
+                nop = ftrace_call_replace(ip, ftrace_addr);
+                if (memcmp(&ins[1], &nop[1], MCOUNT_INSN_SIZE - 1) != 0)
+                        return -EINVAL;
+        }
+        return probe_kernel_write((void *)ip, &nop[0], 1);
+}
+static int add_update_code(unsigned long ip, unsigned const char *new)
+{
+        /* skip breakpoint */
+        ip++;
+        new++;
+        if (ftrace_write(ip, new, MCOUNT_INSN_SIZE - 1))
+                return -EPERM;
+        return 0;
+}
+static int add_update_call(struct dyn_ftrace *rec, unsigned long addr)
+{
+        unsigned long ip = rec->ip;
+        unsigned const char *new;
+        new = ftrace_call_replace(ip, addr);
+        return add_update_code(ip, new);
+}
+static int add_update_nop(struct dyn_ftrace *rec)
+{
+        unsigned long ip = rec->ip;
+        unsigned const char *new;
+        new = ftrace_nop_replace();
+        return add_update_code(ip, new);
+}
+static int add_update(struct dyn_ftrace *rec, int enable)
+{
+        unsigned long ftrace_addr;
+        int ret;
+        ret = ftrace_test_record(rec, enable);
+        ftrace_addr = (unsigned long)FTRACE_ADDR;
+        switch (ret) {
+        case FTRACE_UPDATE_IGNORE:
+                return 0;
+        case FTRACE_UPDATE_MAKE_CALL:
+                /* converting nop to call */
+                return add_update_call(rec, ftrace_addr);
+        case FTRACE_UPDATE_MAKE_NOP:
+                /* converting a call to a nop */
+                return add_update_nop(rec);
+        }
+        return 0;
+}
+static int finish_update_call(struct dyn_ftrace *rec, unsigned long addr)
+{
+        unsigned long ip = rec->ip;
+        unsigned const char *new;
+        new = ftrace_call_replace(ip, addr);
+        if (ftrace_write(ip, new, 1))
+                return -EPERM;
+        return 0;
+}
+static int finish_update_nop(struct dyn_ftrace *rec)
+{
+        unsigned long ip = rec->ip;
+        unsigned const char *new;
+        new = ftrace_nop_replace();
+        if (ftrace_write(ip, new, 1))
+                return -EPERM;
+        return 0;
+}
+static int finish_update(struct dyn_ftrace *rec, int enable)
+{
+        unsigned long ftrace_addr;
+        int ret;
+        ret = ftrace_update_record(rec, enable);
+        ftrace_addr = (unsigned long)FTRACE_ADDR;
+        switch (ret) {
+        case FTRACE_UPDATE_IGNORE:
+                return 0;
+        case FTRACE_UPDATE_MAKE_CALL:
+                /* converting nop to call */
+                return finish_update_call(rec, ftrace_addr);
+        case FTRACE_UPDATE_MAKE_NOP:
+                /* converting a call to a nop */
+                return finish_update_nop(rec);
+        }
+        return 0;
+}
+static void do_sync_core(void *data)
+{
+        sync_core();
+}
+static void run_sync(void)
+{
+        int enable_irqs = irqs_disabled();
+        /* We may be called with interrupts disbled (on bootup). */
+        if (enable_irqs)
+                local_irq_enable();
+        on_each_cpu(do_sync_core, NULL, 1);
+        if (enable_irqs)
+                local_irq_disable();
+}
+void ftrace_replace_code(int enable)
+{
+        struct ftrace_rec_iter *iter;
+        struct dyn_ftrace *rec;
+        const char *report = "adding breakpoints";
+        int count = 0;
+        int ret;
+        for_ftrace_rec_iter(iter) {
+                rec = ftrace_rec_iter_record(iter);
+                ret = add_breakpoints(rec, enable);
+                if (ret)
+                        goto remove_breakpoints;
+                count++;
+        }
+        run_sync();
+        report = "updating code";
+        for_ftrace_rec_iter(iter) {
+                rec = ftrace_rec_iter_record(iter);
+                ret = add_update(rec, enable);
+                if (ret)
+                        goto remove_breakpoints;
+        }
+        run_sync();
+        report = "removing breakpoints";
+        for_ftrace_rec_iter(iter) {
+                rec = ftrace_rec_iter_record(iter);
+                ret = finish_update(rec, enable);
+                if (ret)
+                        goto remove_breakpoints;
+        }
+        run_sync();
+        return;
+ remove_breakpoints:
+        ftrace_bug(ret, rec ? rec->ip : 0);
+        printk(KERN_WARNING "Failed on %s (%d):\n", report, count);
+        for_ftrace_rec_iter(iter) {
+                rec = ftrace_rec_iter_record(iter);
+                remove_breakpoint(rec);
+        }
+}
+void arch_ftrace_update_code(int command)
+{
+        modifying_ftrace_code++;
+        ftrace_modify_all_code(command);
+        modifying_ftrace_code--;
+}
 int __init ftrace_dyn_arch_init(void *data)
 {
        /* The return code is retured via data */
diff --git a/arch/x86/kernel/i387.c b/arch/x86/kernel/i387.c
index 7734bcbb5a3a..f250431fb505 100644
--- a/arch/x86/kernel/i387.c
+++ b/arch/x86/kernel/i387.c
@@ -88,7 +88,7 @@ void kernel_fpu_begin(void)
                __thread_clear_has_fpu(me);
                /* We do 'stts()' in kernel_fpu_end() */
        } else {
-                percpu_write(fpu_owner_task, NULL);
+                this_cpu_write(fpu_owner_task, NULL);
                clts();
        }
 }
@@ -235,6 +235,7 @@ int init_fpu(struct task_struct *tsk)
        if (tsk_used_math(tsk)) {
                if (HAVE_HWFP && tsk == current)
                        unlazy_fpu(tsk);
+                tsk->thread.fpu.last_cpu = ~0;
                return 0;
        }
diff --git a/arch/x86/kernel/init_task.c b/arch/x86/kernel/init_task.c
deleted file mode 100644
index 43e9ccf44947..000000000000
--- a/arch/x86/kernel/init_task.c
+++ /dev/null
@@ -1,42 +0,0 @@
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/sched.h>
-#include <linux/init.h>
-#include <linux/init_task.h>
-#include <linux/fs.h>
-#include <linux/mqueue.h>
-#include <asm/uaccess.h>
-#include <asm/pgtable.h>
-#include <asm/desc.h>
-static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
-static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
-/*
- * Initial thread structure.
- *
- * We need to make sure that this is THREAD_SIZE aligned due to the
- * way process stacks are handled. This is done by having a special
- * "init_task" linker map entry..
- */
-union thread_union init_thread_union __init_task_data =
-        { INIT_THREAD_INFO(init_task) };
-/*
- * Initial task structure.
- *
- * All other task structs will be allocated on slabs in fork.c
- */
-struct task_struct init_task = INIT_TASK(init_task);
-EXPORT_SYMBOL(init_task);
-/*
- * per-CPU TSS segments. Threads are completely 'soft' on Linux,
- * no more per-task TSS's. The TSS size is kept cacheline-aligned
- * so they are allowed to end up in the .data..cacheline_aligned
- * section. Since TSS's are completely CPU-local, we want them
- * on exact cacheline boundaries, to eliminate cacheline ping-pong.
- */
-DEFINE_PER_CPU_SHARED_ALIGNED(struct tss_struct, init_tss) = INIT_TSS;
diff --git a/arch/x86/kernel/irq_32.c b/arch/x86/kernel/irq_32.c
index 58b7f27cb3e9..344faf8d0d62 100644
--- a/arch/x86/kernel/irq_32.c
+++ b/arch/x86/kernel/irq_32.c
@@ -127,8 +127,8 @@ void __cpuinit irq_ctx_init(int cpu)
                return;
        irqctx = page_address(alloc_pages_node(cpu_to_node(cpu),
-                                               THREAD_FLAGS,
+                                               THREADINFO_GFP,
-                                               THREAD_ORDER));
+                                               THREAD_SIZE_ORDER));
        memset(&irqctx->tinfo, 0, sizeof(struct thread_info));
        irqctx->tinfo.cpu               = cpu;
        irqctx->tinfo.preempt_count     = HARDIRQ_OFFSET;
@@ -137,8 +137,8 @@ void __cpuinit irq_ctx_init(int cpu)
        per_cpu(hardirq_ctx, cpu) = irqctx;
        irqctx = page_address(alloc_pages_node(cpu_to_node(cpu),
-                                               THREAD_FLAGS,
+                                               THREADINFO_GFP,
-                                               THREAD_ORDER));
+                                               THREAD_SIZE_ORDER));
        memset(&irqctx->tinfo, 0, sizeof(struct thread_info));
        irqctx->tinfo.cpu               = cpu;
        irqctx->tinfo.addr_limit        = MAKE_MM_SEG(0);
diff --git a/arch/x86/kernel/kvm.c b/arch/x86/kernel/kvm.c
index b8ba6e4a27e4..e554e5ad2fe8 100644
--- a/arch/x86/kernel/kvm.c
+++ b/arch/x86/kernel/kvm.c
@@ -79,7 +79,6 @@ struct kvm_task_sleep_node {
        u32 token;
        int cpu;
        bool halted;
-        struct mm_struct *mm;
 };
 static struct kvm_task_sleep_head {
@@ -126,9 +125,7 @@ void kvm_async_pf_task_wait(u32 token)
        n.token = token;
        n.cpu = smp_processor_id();
-        n.mm = current->active_mm;
        n.halted = idle || preempt_count() > 1;
-        atomic_inc(&n.mm->mm_count);
        init_waitqueue_head(&n.wq);
        hlist_add_head(&n.link, &b->list);
        spin_unlock(&b->lock);
@@ -161,9 +158,6 @@ EXPORT_SYMBOL_GPL(kvm_async_pf_task_wait);
 static void apf_task_wake_one(struct kvm_task_sleep_node *n)
 {
        hlist_del_init(&n->link);
-        if (!n->mm)
-                return;
-        mmdrop(n->mm);
        if (n->halted)
                smp_send_reschedule(n->cpu);
        else if (waitqueue_active(&n->wq))
@@ -207,7 +201,7 @@ again:
                 * async PF was not yet handled.
                 * Add dummy entry for the token.
                 */
-                n = kmalloc(sizeof(*n), GFP_ATOMIC);
+                n = kzalloc(sizeof(*n), GFP_ATOMIC);
                if (!n) {
                        /*
                         * Allocation failed! Busy wait while other cpu
@@ -219,7 +213,6 @@ again:
                }
                n->token = token;
                n->cpu = smp_processor_id();
-                n->mm = NULL;
                init_waitqueue_head(&n->wq);
                hlist_add_head(&n->link, &b->list);
        } else
diff --git a/arch/x86/kernel/microcode_amd.c b/arch/x86/kernel/microcode_amd.c
index 73465aab28f8..8a2ce8fd41c0 100644
--- a/arch/x86/kernel/microcode_amd.c
+++ b/arch/x86/kernel/microcode_amd.c
@@ -82,11 +82,6 @@ static int collect_cpu_info_amd(int cpu, struct cpu_signature *csig)
 {
        struct cpuinfo_x86 *c = &cpu_data(cpu);
-        if (c->x86_vendor != X86_VENDOR_AMD || c->x86 < 0x10) {
-                pr_warning("CPU%d: family %d not supported\n", cpu, c->x86);
-                return -1;
-        }
        csig->rev = c->microcode;
        pr_info("CPU%d: patch_level=0x%08x\n", cpu, csig->rev);
@@ -380,6 +375,13 @@ static struct microcode_ops microcode_amd_ops = {
 struct microcode_ops * __init init_amd_microcode(void)
 {
+        struct cpuinfo_x86 *c = &cpu_data(0);
+        if (c->x86_vendor != X86_VENDOR_AMD || c->x86 < 0x10) {
+                pr_warning("AMD CPU family 0x%x not supported\n", c->x86);
+                return NULL;
+        }
        patch = (void *)get_zeroed_page(GFP_KERNEL);
        if (!patch)
                return NULL;
diff --git a/arch/x86/kernel/microcode_core.c b/arch/x86/kernel/microcode_core.c
index 87a0f8688301..c9bda6d6035c 100644
--- a/arch/x86/kernel/microcode_core.c
+++ b/arch/x86/kernel/microcode_core.c
@@ -419,10 +419,8 @@ static int mc_device_add(struct device *dev, struct subsys_interface *sif)
        if (err)
                return err;
-        if (microcode_init_cpu(cpu) == UCODE_ERROR) {
+        if (microcode_init_cpu(cpu) == UCODE_ERROR)
-                sysfs_remove_group(&dev->kobj, &mc_attr_group);
                return -EINVAL;
-        }
        return err;
 }
@@ -528,11 +526,11 @@ static int __init microcode_init(void)
                microcode_ops = init_intel_microcode();
        else if (c->x86_vendor == X86_VENDOR_AMD)
                microcode_ops = init_amd_microcode();
+        else
-        if (!microcode_ops) {
                pr_err("no support for this CPU vendor\n");
+        if (!microcode_ops)
                return -ENODEV;
-        }
        microcode_pdev = platform_device_register_simple("microcode", -1,
                                                         NULL, 0);
diff --git a/arch/x86/kernel/microcode_intel.c b/arch/x86/kernel/microcode_intel.c
index 3ca42d0e43a2..0327e2b3c408 100644
--- a/arch/x86/kernel/microcode_intel.c
+++ b/arch/x86/kernel/microcode_intel.c
@@ -147,12 +147,6 @@ static int collect_cpu_info(int cpu_num, struct cpu_signature *csig)
        memset(csig, 0, sizeof(*csig));
-        if (c->x86_vendor != X86_VENDOR_INTEL || c->x86 < 6 ||
-            cpu_has(c, X86_FEATURE_IA64)) {
-                pr_err("CPU%d not a capable Intel processor\n", cpu_num);
-                return -1;
-        }
        csig->sig = cpuid_eax(0x00000001);
        if ((c->x86_model >= 5) || (c->x86 > 6)) {
@@ -463,6 +457,14 @@ static struct microcode_ops microcode_intel_ops = {
 struct microcode_ops * __init init_intel_microcode(void)
 {
+        struct cpuinfo_x86 *c = &cpu_data(0);
+        if (c->x86_vendor != X86_VENDOR_INTEL || c->x86 < 6 ||
+            cpu_has(c, X86_FEATURE_IA64)) {
+                pr_err("Intel CPU family 0x%x not supported\n", c->x86);
+                return NULL;
+        }
        return &microcode_intel_ops;
 }
diff --git a/arch/x86/kernel/nmi.c b/arch/x86/kernel/nmi.c
index 47acaf319165..a1faed5ac6a2 100644
--- a/arch/x86/kernel/nmi.c
+++ b/arch/x86/kernel/nmi.c
@@ -31,14 +31,6 @@
 #include <asm/nmi.h>
 #include <asm/x86_init.h>
-#define NMI_MAX_NAMELEN 16
-struct nmiaction {
-        struct list_head list;
-        nmi_handler_t handler;
-        unsigned int flags;
-        char *name;
-};
 struct nmi_desc {
        spinlock_t lock;
        struct list_head head;
@@ -54,6 +46,14 @@ static struct nmi_desc nmi_desc[NMI_MAX] =
                .lock = __SPIN_LOCK_UNLOCKED(&nmi_desc[1].lock),
                .head = LIST_HEAD_INIT(nmi_desc[1].head),
        },
+        {
+                .lock = __SPIN_LOCK_UNLOCKED(&nmi_desc[2].lock),
+                .head = LIST_HEAD_INIT(nmi_desc[2].head),
+        },
+        {
+                .lock = __SPIN_LOCK_UNLOCKED(&nmi_desc[3].lock),
+                .head = LIST_HEAD_INIT(nmi_desc[3].head),
+        },
 };
@@ -84,7 +84,7 @@ __setup("unknown_nmi_panic", setup_unknown_nmi_panic);
 #define nmi_to_desc(type) (&nmi_desc[type])
-static int notrace __kprobes nmi_handle(unsigned int type, struct pt_regs *regs, bool b2b)
+static int __kprobes nmi_handle(unsigned int type, struct pt_regs *regs, bool b2b)
 {
        struct nmi_desc *desc = nmi_to_desc(type);
        struct nmiaction *a;
@@ -107,11 +107,14 @@ static int notrace __kprobes nmi_handle(unsigned int type, struct pt_regs *regs,
        return handled;
 }
-static int __setup_nmi(unsigned int type, struct nmiaction *action)
+int __register_nmi_handler(unsigned int type, struct nmiaction *action)
 {
        struct nmi_desc *desc = nmi_to_desc(type);
        unsigned long flags;
+        if (!action->handler)
+                return -EINVAL;
        spin_lock_irqsave(&desc->lock, flags);
        /*
@@ -120,6 +123,8 @@ static int __setup_nmi(unsigned int type, struct nmiaction *action)
         * to manage expectations
         */
        WARN_ON_ONCE(type == NMI_UNKNOWN && !list_empty(&desc->head));
+        WARN_ON_ONCE(type == NMI_SERR && !list_empty(&desc->head));
+        WARN_ON_ONCE(type == NMI_IO_CHECK && !list_empty(&desc->head));
        /*
         * some handlers need to be executed first otherwise a fake
@@ -133,8 +138,9 @@ static int __setup_nmi(unsigned int type, struct nmiaction *action)
        spin_unlock_irqrestore(&desc->lock, flags);
        return 0;
 }
+EXPORT_SYMBOL(__register_nmi_handler);
-static struct nmiaction *__free_nmi(unsigned int type, const char *name)
+void unregister_nmi_handler(unsigned int type, const char *name)
 {
        struct nmi_desc *desc = nmi_to_desc(type);
        struct nmiaction *n;
@@ -157,61 +163,16 @@ static struct nmiaction *__free_nmi(unsigned int type, const char *name)
        spin_unlock_irqrestore(&desc->lock, flags);
        synchronize_rcu();
-        return (n);
 }
-int register_nmi_handler(unsigned int type, nmi_handler_t handler,
-                        unsigned long nmiflags, const char *devname)
-{
-        struct nmiaction *action;
-        int retval = -ENOMEM;
-        if (!handler)
-                return -EINVAL;
-        action = kzalloc(sizeof(struct nmiaction), GFP_KERNEL);
-        if (!action)
-                goto fail_action;
-        action->handler = handler;
-        action->flags = nmiflags;
-        action->name = kstrndup(devname, NMI_MAX_NAMELEN, GFP_KERNEL);
-        if (!action->name)
-                goto fail_action_name;
-        retval = __setup_nmi(type, action);
-        if (retval)
-                goto fail_setup_nmi;
-        return retval;
-fail_setup_nmi:
-        kfree(action->name);
-fail_action_name:
-        kfree(action);
-fail_action:    
-        return retval;
-}
-EXPORT_SYMBOL_GPL(register_nmi_handler);
-void unregister_nmi_handler(unsigned int type, const char *name)
-{
-        struct nmiaction *a;
-        a = __free_nmi(type, name);
-        if (a) {
-                kfree(a->name);
-                kfree(a);
-        }
-}
 EXPORT_SYMBOL_GPL(unregister_nmi_handler);
-static notrace __kprobes void
+static __kprobes void
 pci_serr_error(unsigned char reason, struct pt_regs *regs)
 {
+        /* check to see if anyone registered against these types of errors */
+        if (nmi_handle(NMI_SERR, regs, false))
+                return;
        pr_emerg("NMI: PCI system error (SERR) for reason %02x on CPU %d.\n",
                 reason, smp_processor_id());
@@ -236,11 +197,15 @@ pci_serr_error(unsigned char reason, struct pt_regs *regs)
        outb(reason, NMI_REASON_PORT);
 }
-static notrace __kprobes void
+static __kprobes void
 io_check_error(unsigned char reason, struct pt_regs *regs)
 {
        unsigned long i;
+        /* check to see if anyone registered against these types of errors */
+        if (nmi_handle(NMI_IO_CHECK, regs, false))
+                return;
        pr_emerg(
        "NMI: IOCK error (debug interrupt?) for reason %02x on CPU %d.\n",
                 reason, smp_processor_id());
@@ -263,7 +228,7 @@ io_check_error(unsigned char reason, struct pt_regs *regs)
        outb(reason, NMI_REASON_PORT);
 }
-static notrace __kprobes void
+static __kprobes void
 unknown_nmi_error(unsigned char reason, struct pt_regs *regs)
 {
        int handled;
@@ -305,7 +270,7 @@ unknown_nmi_error(unsigned char reason, struct pt_regs *regs)
 static DEFINE_PER_CPU(bool, swallow_nmi);
 static DEFINE_PER_CPU(unsigned long, last_nmi_rip);
-static notrace __kprobes void default_do_nmi(struct pt_regs *regs)
+static __kprobes void default_do_nmi(struct pt_regs *regs)
 {
        unsigned char reason = 0;
        int handled;
diff --git a/arch/x86/kernel/nmi_selftest.c b/arch/x86/kernel/nmi_selftest.c
index 2c39dcd510fa..ff3698625081 100644
--- a/arch/x86/kernel/nmi_selftest.c
+++ b/arch/x86/kernel/nmi_selftest.c
@@ -13,6 +13,7 @@
 #include <linux/cpumask.h>
 #include <linux/delay.h>
 #include <linux/init.h>
+#include <linux/percpu.h>
 #include <asm/apic.h>
 #include <asm/nmi.h>
diff --git a/arch/x86/kernel/paravirt.c b/arch/x86/kernel/paravirt.c
index ab137605e694..9ce885996fd7 100644
--- a/arch/x86/kernel/paravirt.c
+++ b/arch/x86/kernel/paravirt.c
@@ -241,16 +241,16 @@ static DEFINE_PER_CPU(enum paravirt_lazy_mode, paravirt_lazy_mode) = PARAVIRT_LA
 static inline void enter_lazy(enum paravirt_lazy_mode mode)
 {
-        BUG_ON(percpu_read(paravirt_lazy_mode) != PARAVIRT_LAZY_NONE);
+        BUG_ON(this_cpu_read(paravirt_lazy_mode) != PARAVIRT_LAZY_NONE);
-        percpu_write(paravirt_lazy_mode, mode);
+        this_cpu_write(paravirt_lazy_mode, mode);
 }
 static void leave_lazy(enum paravirt_lazy_mode mode)
 {
-        BUG_ON(percpu_read(paravirt_lazy_mode) != mode);
+        BUG_ON(this_cpu_read(paravirt_lazy_mode) != mode);
-        percpu_write(paravirt_lazy_mode, PARAVIRT_LAZY_NONE);
+        this_cpu_write(paravirt_lazy_mode, PARAVIRT_LAZY_NONE);
 }
 void paravirt_enter_lazy_mmu(void)
@@ -267,7 +267,7 @@ void paravirt_start_context_switch(struct task_struct *prev)
 {
        BUG_ON(preemptible());
-        if (percpu_read(paravirt_lazy_mode) == PARAVIRT_LAZY_MMU) {
+        if (this_cpu_read(paravirt_lazy_mode) == PARAVIRT_LAZY_MMU) {
                arch_leave_lazy_mmu_mode();
                set_ti_thread_flag(task_thread_info(prev), TIF_LAZY_MMU_UPDATES);
        }
@@ -289,7 +289,7 @@ enum paravirt_lazy_mode paravirt_get_lazy_mode(void)
        if (in_interrupt())
                return PARAVIRT_LAZY_NONE;
-        return percpu_read(paravirt_lazy_mode);
+        return this_cpu_read(paravirt_lazy_mode);
 }
 void arch_flush_lazy_mmu_mode(void)
diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c
index 1d92a5ab6e8b..8040b752ee4f 100644
--- a/arch/x86/kernel/process.c
+++ b/arch/x86/kernel/process.c
@@ -27,6 +27,15 @@
 #include <asm/debugreg.h>
 #include <asm/nmi.h>
+/*
+ * per-CPU TSS segments. Threads are completely 'soft' on Linux,
+ * no more per-task TSS's. The TSS size is kept cacheline-aligned
+ * so they are allowed to end up in the .data..cacheline_aligned
+ * section. Since TSS's are completely CPU-local, we want them
+ * on exact cacheline boundaries, to eliminate cacheline ping-pong.
+ */
+DEFINE_PER_CPU_SHARED_ALIGNED(struct tss_struct, init_tss) = INIT_TSS;
 #ifdef CONFIG_X86_64
 static DEFINE_PER_CPU(unsigned char, is_idle);
 static ATOMIC_NOTIFIER_HEAD(idle_notifier);
@@ -67,10 +76,9 @@ void free_thread_xstate(struct task_struct *tsk)
        fpu_free(&tsk->thread.fpu);
 }
-void free_thread_info(struct thread_info *ti)
+void arch_release_task_struct(struct task_struct *tsk)
 {
-        free_thread_xstate(ti->task);
+        free_thread_xstate(tsk);
-        free_pages((unsigned long)ti, THREAD_ORDER);
 }
 void arch_task_cache_init(void)
@@ -377,7 +385,7 @@ static inline void play_dead(void)
 #ifdef CONFIG_X86_64
 void enter_idle(void)
 {
-        percpu_write(is_idle, 1);
+        this_cpu_write(is_idle, 1);
        atomic_notifier_call_chain(&idle_notifier, IDLE_START, NULL);
 }
@@ -516,26 +524,6 @@ void stop_this_cpu(void *dummy)
        }
 }
-static void do_nothing(void *unused)
-{
-}
-/*
- * cpu_idle_wait - Used to ensure that all the CPUs discard old value of
- * pm_idle and update to new pm_idle value. Required while changing pm_idle
- * handler on SMP systems.
- *
- * Caller must have changed pm_idle to the new value before the call. Old
- * pm_idle value will not be used by any CPU after the return of this function.
- */
-void cpu_idle_wait(void)
-{
-        smp_mb();
-        /* kick all the CPUs so that they exit out of pm_idle */
-        smp_call_function(do_nothing, NULL, 1);
-}
-EXPORT_SYMBOL_GPL(cpu_idle_wait);
 /* Default MONITOR/MWAIT with no hints, used for default C1 state */
 static void mwait_idle(void)
 {
@@ -594,9 +582,17 @@ int mwait_usable(const struct cpuinfo_x86 *c)
 {
        u32 eax, ebx, ecx, edx;
+        /* Use mwait if idle=mwait boot option is given */
        if (boot_option_idle_override == IDLE_FORCE_MWAIT)
                return 1;
+        /*
+         * Any idle= boot option other than idle=mwait means that we must not
+         * use mwait. Eg: idle=halt or idle=poll or idle=nomwait
+         */
+        if (boot_option_idle_override != IDLE_NO_OVERRIDE)
+                return 0;
        if (c->cpuid_level < MWAIT_INFO)
                return 0;
diff --git a/arch/x86/kernel/process_32.c b/arch/x86/kernel/process_32.c
index ae6847303e26..01d8d40ccaf6 100644
--- a/arch/x86/kernel/process_32.c
+++ b/arch/x86/kernel/process_32.c
@@ -302,7 +302,7 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p)
        switch_fpu_finish(next_p, fpu);
-        percpu_write(current_task, next_p);
+        this_cpu_write(current_task, next_p);
        return prev_p;
 }
diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c
index 733ca39f367e..28e810255a0a 100644
--- a/arch/x86/kernel/process_64.c
+++ b/arch/x86/kernel/process_64.c
@@ -237,7 +237,7 @@ start_thread_common(struct pt_regs *regs, unsigned long new_ip,
        current->thread.usersp  = new_sp;
        regs->ip                = new_ip;
        regs->sp                = new_sp;
-        percpu_write(old_rsp, new_sp);
+        this_cpu_write(old_rsp, new_sp);
        regs->cs                = _cs;
        regs->ss                = _ss;
        regs->flags             = X86_EFLAGS_IF;
@@ -359,11 +359,11 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p)
        /*
         * Switch the PDA and FPU contexts.
         */
-        prev->usersp = percpu_read(old_rsp);
+        prev->usersp = this_cpu_read(old_rsp);
-        percpu_write(old_rsp, next->usersp);
+        this_cpu_write(old_rsp, next->usersp);
-        percpu_write(current_task, next_p);
+        this_cpu_write(current_task, next_p);
-        percpu_write(kernel_stack,
+        this_cpu_write(kernel_stack,
                  (unsigned long)task_stack_page(next_p) +
                  THREAD_SIZE - KERNEL_STACK_OFFSET);
@@ -423,6 +423,7 @@ void set_personality_ia32(bool x32)
                current_thread_info()->status |= TS_COMPAT;
        }
 }
+EXPORT_SYMBOL_GPL(set_personality_ia32);
 unsigned long get_wchan(struct task_struct *p)
 {
diff --git a/arch/x86/kernel/ptrace.c b/arch/x86/kernel/ptrace.c
index 685845cf16e0..13b1990c7c58 100644
--- a/arch/x86/kernel/ptrace.c
+++ b/arch/x86/kernel/ptrace.c
@@ -1480,7 +1480,11 @@ long syscall_trace_enter(struct pt_regs *regs)
                regs->flags |= X86_EFLAGS_TF;
        /* do the secure computing check first */
-        secure_computing(regs->orig_ax);
+        if (secure_computing(regs->orig_ax)) {
+                /* seccomp failures shouldn't expose any additional code. */
+                ret = -1L;
+                goto out;
+        }
        if (unlikely(test_thread_flag(TIF_SYSCALL_EMU)))
                ret = -1L;
@@ -1505,6 +1509,7 @@ long syscall_trace_enter(struct pt_regs *regs)
                                    regs->dx, regs->r10);
 #endif
+out:
        return ret ?: regs->orig_ax;
 }
diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c
index 1a2901562059..7e67c5a71061 100644
--- a/arch/x86/kernel/setup.c
+++ b/arch/x86/kernel/setup.c
@@ -1012,7 +1012,8 @@ void __init setup_arch(char **cmdline_p)
        init_cpu_to_node();
        init_apic_mappings();
-        ioapic_and_gsi_init();
+        if (x86_io_apic_ops.init)
+                x86_io_apic_ops.init();
        kvm_guest_init();
diff --git a/arch/x86/kernel/setup_percpu.c b/arch/x86/kernel/setup_percpu.c
index 71f4727da373..5a98aa272184 100644
--- a/arch/x86/kernel/setup_percpu.c
+++ b/arch/x86/kernel/setup_percpu.c
@@ -185,10 +185,22 @@ void __init setup_per_cpu_areas(void)
 #endif
        rc = -EINVAL;
        if (pcpu_chosen_fc != PCPU_FC_PAGE) {
-                const size_t atom_size = cpu_has_pse ? PMD_SIZE : PAGE_SIZE;
                const size_t dyn_size = PERCPU_MODULE_RESERVE +
                        PERCPU_DYNAMIC_RESERVE - PERCPU_FIRST_CHUNK_RESERVE;
+                size_t atom_size;
+                /*
+                 * On 64bit, use PMD_SIZE for atom_size so that embedded
+                 * percpu areas are aligned to PMD.  This, in the future,
+                 * can also allow using PMD mappings in vmalloc area.  Use
+                 * PAGE_SIZE on 32bit as vmalloc space is highly contended
+                 * and large vmalloc area allocs can easily fail.
+                 */
+#ifdef CONFIG_X86_64
+                atom_size = PMD_SIZE;
+#else
+                atom_size = PAGE_SIZE;
+#endif
                rc = pcpu_embed_first_chunk(PERCPU_FIRST_CHUNK_RESERVE,
                                            dyn_size, atom_size,
                                            pcpu_cpu_distance,
diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c
index 6e1e406038c2..433529e29be4 100644
--- a/arch/x86/kernel/smpboot.c
+++ b/arch/x86/kernel/smpboot.c
@@ -76,20 +76,8 @@
 /* State of each CPU */
 DEFINE_PER_CPU(int, cpu_state) = { 0 };
-/* Store all idle threads, this can be reused instead of creating
-* a new thread. Also avoids complicated thread destroy functionality
-* for idle threads.
-*/
 #ifdef CONFIG_HOTPLUG_CPU
 /*
- * Needed only for CONFIG_HOTPLUG_CPU because __cpuinitdata is
- * removed after init for !CONFIG_HOTPLUG_CPU.
- */
-static DEFINE_PER_CPU(struct task_struct *, idle_thread_array);
-#define get_idle_for_cpu(x)      (per_cpu(idle_thread_array, x))
-#define set_idle_for_cpu(x, p)   (per_cpu(idle_thread_array, x) = (p))
-/*
 * We need this for trampoline_base protection from concurrent accesses when
 * off- and onlining cores wildly.
 */
@@ -97,20 +85,16 @@ static DEFINE_MUTEX(x86_cpu_hotplug_driver_mutex);
 void cpu_hotplug_driver_lock(void)
 {
-        mutex_lock(&x86_cpu_hotplug_driver_mutex);
+        mutex_lock(&x86_cpu_hotplug_driver_mutex);
 }
 void cpu_hotplug_driver_unlock(void)
 {
-        mutex_unlock(&x86_cpu_hotplug_driver_mutex);
+        mutex_unlock(&x86_cpu_hotplug_driver_mutex);
 }
 ssize_t arch_cpu_probe(const char *buf, size_t count) { return -1; }
 ssize_t arch_cpu_release(const char *buf, size_t count) { return -1; }
-#else
-static struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ;
-#define get_idle_for_cpu(x)      (idle_thread_array[(x)])
-#define set_idle_for_cpu(x, p)   (idle_thread_array[(x)] = (p))
 #endif
 /* Number of siblings per CPU package */
@@ -315,59 +299,90 @@ void __cpuinit smp_store_cpu_info(int id)
                identify_secondary_cpu(c);
 }
-static void __cpuinit link_thread_siblings(int cpu1, int cpu2)
+static bool __cpuinit
+topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name)
 {
-        cpumask_set_cpu(cpu1, cpu_sibling_mask(cpu2));
+        int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
-        cpumask_set_cpu(cpu2, cpu_sibling_mask(cpu1));
-        cpumask_set_cpu(cpu1, cpu_core_mask(cpu2));
+        return !WARN_ONCE(cpu_to_node(cpu1) != cpu_to_node(cpu2),
-        cpumask_set_cpu(cpu2, cpu_core_mask(cpu1));
+                "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
-        cpumask_set_cpu(cpu1, cpu_llc_shared_mask(cpu2));
+                "[node: %d != %d]. Ignoring dependency.\n",
-        cpumask_set_cpu(cpu2, cpu_llc_shared_mask(cpu1));
+                cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2));
 }
+#define link_mask(_m, c1, c2)                                           \
+do {                                                                    \
+        cpumask_set_cpu((c1), cpu_##_m##_mask(c2));                     \
+        cpumask_set_cpu((c2), cpu_##_m##_mask(c1));                     \
+} while (0)
+static bool __cpuinit match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
+{
+        if (cpu_has(c, X86_FEATURE_TOPOEXT)) {
+                int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
+                if (c->phys_proc_id == o->phys_proc_id &&
+                    per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2) &&
+                    c->compute_unit_id == o->compute_unit_id)
+                        return topology_sane(c, o, "smt");
+        } else if (c->phys_proc_id == o->phys_proc_id &&
+                   c->cpu_core_id == o->cpu_core_id) {
+                return topology_sane(c, o, "smt");
+        }
+        return false;
+}
+static bool __cpuinit match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
+{
+        int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
+        if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID &&
+            per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2))
+                return topology_sane(c, o, "llc");
+        return false;
+}
+static bool __cpuinit match_mc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
+{
+        if (c->phys_proc_id == o->phys_proc_id)
+                return topology_sane(c, o, "mc");
+        return false;
+}
 void __cpuinit set_cpu_sibling_map(int cpu)
 {
-        int i;
+        bool has_mc = boot_cpu_data.x86_max_cores > 1;
+        bool has_smt = smp_num_siblings > 1;
        struct cpuinfo_x86 *c = &cpu_data(cpu);
+        struct cpuinfo_x86 *o;
+        int i;
        cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
-        if (smp_num_siblings > 1) {
+        if (!has_smt && !has_mc) {
-                for_each_cpu(i, cpu_sibling_setup_mask) {
-                        struct cpuinfo_x86 *o = &cpu_data(i);
-                        if (cpu_has(c, X86_FEATURE_TOPOEXT)) {
-                                if (c->phys_proc_id == o->phys_proc_id &&
-                                    per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i) &&
-                                    c->compute_unit_id == o->compute_unit_id)
-                                        link_thread_siblings(cpu, i);
-                        } else if (c->phys_proc_id == o->phys_proc_id &&
-                                   c->cpu_core_id == o->cpu_core_id) {
-                                link_thread_siblings(cpu, i);
-                        }
-                }
-        } else {
                cpumask_set_cpu(cpu, cpu_sibling_mask(cpu));
-        }
+                cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
+                cpumask_set_cpu(cpu, cpu_core_mask(cpu));
-        cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
-        if (__this_cpu_read(cpu_info.x86_max_cores) == 1) {
-                cpumask_copy(cpu_core_mask(cpu), cpu_sibling_mask(cpu));
                c->booted_cores = 1;
                return;
        }
        for_each_cpu(i, cpu_sibling_setup_mask) {
-                if (per_cpu(cpu_llc_id, cpu) != BAD_APICID &&
+                o = &cpu_data(i);
-                    per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i)) {
-                        cpumask_set_cpu(i, cpu_llc_shared_mask(cpu));
+                if ((i == cpu) || (has_smt && match_smt(c, o)))
-                        cpumask_set_cpu(cpu, cpu_llc_shared_mask(i));
+                        link_mask(sibling, cpu, i);
-                }
-                if (c->phys_proc_id == cpu_data(i).phys_proc_id) {
+                if ((i == cpu) || (has_mc && match_llc(c, o)))
-                        cpumask_set_cpu(i, cpu_core_mask(cpu));
+                        link_mask(llc_shared, cpu, i);
-                        cpumask_set_cpu(cpu, cpu_core_mask(i));
+                if ((i == cpu) || (has_mc && match_mc(c, o))) {
+                        link_mask(core, cpu, i);
                        /*
                         *  Does this new cpu bringup a new core?
                         */
@@ -398,8 +413,7 @@ const struct cpumask *cpu_coregroup_mask(int cpu)
         * For perf, we return last level cache shared map.
         * And for power savings, we return cpu_core_map
         */
-        if ((sched_mc_power_savings || sched_smt_power_savings) &&
+        if (!(cpu_has(c, X86_FEATURE_AMD_DCM)))
-            !(cpu_has(c, X86_FEATURE_AMD_DCM)))
                return cpu_core_mask(cpu);
        else
                return cpu_llc_shared_mask(cpu);
@@ -618,22 +632,6 @@ wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
        return (send_status | accept_status);
 }
-struct create_idle {
-        struct work_struct work;
-        struct task_struct *idle;
-        struct completion done;
-        int cpu;
-};
-static void __cpuinit do_fork_idle(struct work_struct *work)
-{
-        struct create_idle *c_idle =
-                container_of(work, struct create_idle, work);
-        c_idle->idle = fork_idle(c_idle->cpu);
-        complete(&c_idle->done);
-}
 /* reduce the number of lines printed when booting a large cpu count system */
 static void __cpuinit announce_cpu(int cpu, int apicid)
 {
@@ -660,58 +658,31 @@ static void __cpuinit announce_cpu(int cpu, int apicid)
 * Returns zero if CPU booted OK, else error code from
 * ->wakeup_secondary_cpu.
 */
-static int __cpuinit do_boot_cpu(int apicid, int cpu)
+static int __cpuinit do_boot_cpu(int apicid, int cpu, struct task_struct *idle)
 {
        unsigned long boot_error = 0;
        unsigned long start_ip;
        int timeout;
-        struct create_idle c_idle = {
-                .cpu    = cpu,
-                .done   = COMPLETION_INITIALIZER_ONSTACK(c_idle.done),
-        };
-        INIT_WORK_ONSTACK(&c_idle.work, do_fork_idle);
        alternatives_smp_switch(1);
-        c_idle.idle = get_idle_for_cpu(cpu);
+        idle->thread.sp = (unsigned long) (((struct pt_regs *)
+                          (THREAD_SIZE +  task_stack_page(idle))) - 1);
-        /*
+        per_cpu(current_task, cpu) = idle;
-         * We can't use kernel_thread since we must avoid to
-         * reschedule the child.
-         */
-        if (c_idle.idle) {
-                c_idle.idle->thread.sp = (unsigned long) (((struct pt_regs *)
-                        (THREAD_SIZE +  task_stack_page(c_idle.idle))) - 1);
-                init_idle(c_idle.idle, cpu);
-                goto do_rest;
-        }
-        schedule_work(&c_idle.work);
-        wait_for_completion(&c_idle.done);
-        if (IS_ERR(c_idle.idle)) {
-                printk("failed fork for CPU %d\n", cpu);
-                destroy_work_on_stack(&c_idle.work);
-                return PTR_ERR(c_idle.idle);
-        }
-        set_idle_for_cpu(cpu, c_idle.idle);
-do_rest:
-        per_cpu(current_task, cpu) = c_idle.idle;
 #ifdef CONFIG_X86_32
        /* Stack for startup_32 can be just as for start_secondary onwards */
        irq_ctx_init(cpu);
 #else
-        clear_tsk_thread_flag(c_idle.idle, TIF_FORK);
+        clear_tsk_thread_flag(idle, TIF_FORK);
        initial_gs = per_cpu_offset(cpu);
        per_cpu(kernel_stack, cpu) =
-                (unsigned long)task_stack_page(c_idle.idle) -
+                (unsigned long)task_stack_page(idle) -
                KERNEL_STACK_OFFSET + THREAD_SIZE;
 #endif
        early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu);
        initial_code = (unsigned long)start_secondary;
-        stack_start  = c_idle.idle->thread.sp;
+        stack_start  = idle->thread.sp;
        /* start_ip had better be page-aligned! */
        start_ip = trampoline_address();
@@ -813,12 +784,10 @@ do_rest:
                 */
                smpboot_restore_warm_reset_vector();
        }
-        destroy_work_on_stack(&c_idle.work);
        return boot_error;
 }
-int __cpuinit native_cpu_up(unsigned int cpu)
+int __cpuinit native_cpu_up(unsigned int cpu, struct task_struct *tidle)
 {
        int apicid = apic->cpu_present_to_apicid(cpu);
        unsigned long flags;
@@ -851,7 +820,7 @@ int __cpuinit native_cpu_up(unsigned int cpu)
        per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
-        err = do_boot_cpu(apicid, cpu);
+        err = do_boot_cpu(apicid, cpu, tidle);
        if (err) {
                pr_debug("do_boot_cpu failed %d\n", err);
                return -EIO;
diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c
index ff9281f16029..92d5756d85fc 100644
--- a/arch/x86/kernel/traps.c
+++ b/arch/x86/kernel/traps.c
@@ -50,6 +50,7 @@
 #include <asm/processor.h>
 #include <asm/debugreg.h>
 #include <linux/atomic.h>
+#include <asm/ftrace.h>
 #include <asm/traps.h>
 #include <asm/desc.h>
 #include <asm/i387.h>
@@ -303,8 +304,13 @@ gp_in_kernel:
 }
 /* May run on IST stack. */
-dotraplinkage void __kprobes do_int3(struct pt_regs *regs, long error_code)
+dotraplinkage void __kprobes notrace do_int3(struct pt_regs *regs, long error_code)
 {
+#ifdef CONFIG_DYNAMIC_FTRACE
+        /* ftrace must be first, everything else may cause a recursive crash */
+        if (unlikely(modifying_ftrace_code) && ftrace_int3_handler(regs))
+                return;
+#endif
 #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
        if (kgdb_ll_trap(DIE_INT3, "int3", regs, error_code, X86_TRAP_BP,
                                SIGTRAP) == NOTIFY_STOP)
diff --git a/arch/x86/kernel/vsyscall_64.c b/arch/x86/kernel/vsyscall_64.c
index f386dc49f988..7515cf0e1805 100644
--- a/arch/x86/kernel/vsyscall_64.c
+++ b/arch/x86/kernel/vsyscall_64.c
@@ -216,9 +216,9 @@ bool emulate_vsyscall(struct pt_regs *regs, unsigned long address)
        current_thread_info()->sig_on_uaccess_error = 1;
        /*
-         * 0 is a valid user pointer (in the access_ok sense) on 32-bit and
+         * NULL is a valid user pointer (in the access_ok sense) on 32-bit and
         * 64-bit, so we don't need to special-case it here.  For all the
-         * vsyscalls, 0 means "don't write anything" not "write it at
+         * vsyscalls, NULL means "don't write anything" not "write it at
         * address 0".
         */
        ret = -EFAULT;
@@ -247,7 +247,7 @@ bool emulate_vsyscall(struct pt_regs *regs, unsigned long address)
                ret = sys_getcpu((unsigned __user *)regs->di,
                                 (unsigned __user *)regs->si,
-                                 0);
+                                 NULL);
                break;
        }
diff --git a/arch/x86/kernel/x86_init.c b/arch/x86/kernel/x86_init.c
index e9f265fd79ae..35c5e543f550 100644
--- a/arch/x86/kernel/x86_init.c
+++ b/arch/x86/kernel/x86_init.c
@@ -18,6 +18,7 @@
 #include <asm/e820.h>
 #include <asm/time.h>
 #include <asm/irq.h>
+#include <asm/io_apic.h>
 #include <asm/pat.h>
 #include <asm/tsc.h>
 #include <asm/iommu.h>
@@ -93,7 +94,6 @@ struct x86_init_ops x86_init __initdata = {
 struct x86_cpuinit_ops x86_cpuinit __cpuinitdata = {
        .early_percpu_clock_init        = x86_init_noop,
        .setup_percpu_clockev           = setup_secondary_APIC_clock,
-        .fixup_cpu_id                   = x86_default_fixup_cpu_id,
 };
 static void default_nmi_init(void) { };
@@ -120,3 +120,10 @@ struct x86_msi_ops x86_msi = {
        .teardown_msi_irqs = default_teardown_msi_irqs,
        .restore_msi_irqs = default_restore_msi_irqs,
 };
+struct x86_io_apic_ops x86_io_apic_ops = {
+        .init   = native_io_apic_init_mappings,
+        .read   = native_io_apic_read,
+        .write  = native_io_apic_write,
+        .modify = native_io_apic_modify,
+};
diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c
index 173df38dbda5..2e88438ffd83 100644
--- a/arch/x86/kvm/pmu.c
+++ b/arch/x86/kvm/pmu.c
@@ -459,17 +459,17 @@ void kvm_pmu_cpuid_update(struct kvm_vcpu *vcpu)
        pmu->available_event_types = ~entry->ebx & ((1ull << bitmap_len) - 1);
        if (pmu->version == 1) {
-                pmu->global_ctrl = (1 << pmu->nr_arch_gp_counters) - 1;
+                pmu->nr_arch_fixed_counters = 0;
-                return;
+        } else {
+                pmu->nr_arch_fixed_counters = min((int)(entry->edx & 0x1f),
+                                X86_PMC_MAX_FIXED);
+                pmu->counter_bitmask[KVM_PMC_FIXED] =
+                        ((u64)1 << ((entry->edx >> 5) & 0xff)) - 1;
        }
-        pmu->nr_arch_fixed_counters = min((int)(entry->edx & 0x1f),
+        pmu->global_ctrl = ((1 << pmu->nr_arch_gp_counters) - 1) |
-                        X86_PMC_MAX_FIXED);
+                (((1ull << pmu->nr_arch_fixed_counters) - 1) << X86_PMC_IDX_FIXED);
-        pmu->counter_bitmask[KVM_PMC_FIXED] =
+        pmu->global_ctrl_mask = ~pmu->global_ctrl;
-                ((u64)1 << ((entry->edx >> 5) & 0xff)) - 1;
-        pmu->global_ctrl_mask = ~(((1 << pmu->nr_arch_gp_counters) - 1)
-                        | (((1ull << pmu->nr_arch_fixed_counters) - 1)
-                                << X86_PMC_IDX_FIXED));
 }
 void kvm_pmu_init(struct kvm_vcpu *vcpu)
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index ad85adfef843..4ff0ab9bc3c8 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -2210,9 +2210,12 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
                msr = find_msr_entry(vmx, msr_index);
                if (msr) {
                        msr->data = data;
-                        if (msr - vmx->guest_msrs < vmx->save_nmsrs)
+                        if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
+                                preempt_disable();
                                kvm_set_shared_msr(msr->index, msr->data,
                                                   msr->mask);
+                                preempt_enable();
+                        }
                        break;
                }
                ret = kvm_set_msr_common(vcpu, msr_index, data);
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 4044ce0bf7c1..185a2b823a2d 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -6336,13 +6336,11 @@ int kvm_arch_prepare_memory_region(struct kvm *kvm,
                if (npages && !old.rmap) {
                        unsigned long userspace_addr;
-                        down_write(&current->mm->mmap_sem);
+                        userspace_addr = vm_mmap(NULL, 0,
-                        userspace_addr = do_mmap(NULL, 0,
                                                 npages * PAGE_SIZE,
                                                 PROT_READ | PROT_WRITE,
                                                 map_flags,
                                                 0);
-                        up_write(&current->mm->mmap_sem);
                        if (IS_ERR((void *)userspace_addr))
                                return PTR_ERR((void *)userspace_addr);
@@ -6366,10 +6364,8 @@ void kvm_arch_commit_memory_region(struct kvm *kvm,
        if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
                int ret;
-                down_write(&current->mm->mmap_sem);
+                ret = vm_munmap(old.userspace_addr,
-                ret = do_munmap(current->mm, old.userspace_addr,
                                old.npages * PAGE_SIZE);
-                up_write(&current->mm->mmap_sem);
                if (ret < 0)
                        printk(KERN_WARNING
                               "kvm_vm_ioctl_set_memory_region: "
@@ -6585,6 +6581,7 @@ void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
                kvm_inject_page_fault(vcpu, &fault);
        }
        vcpu->arch.apf.halted = false;
+        vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
 }
 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
diff --git a/arch/x86/lib/insn.c b/arch/x86/lib/insn.c
index 25feb1ae71c5..b1e6c4b2e8eb 100644
--- a/arch/x86/lib/insn.c
+++ b/arch/x86/lib/insn.c
@@ -379,8 +379,8 @@ err_out:
        return;
 }
-/* Decode moffset16/32/64 */
+/* Decode moffset16/32/64. Return 0 if failed */
-static void __get_moffset(struct insn *insn)
+static int __get_moffset(struct insn *insn)
 {
        switch (insn->addr_bytes) {
        case 2:
@@ -397,15 +397,19 @@ static void __get_moffset(struct insn *insn)
                insn->moffset2.value = get_next(int, insn);
                insn->moffset2.nbytes = 4;
                break;
+        default:        /* opnd_bytes must be modified manually */
+                goto err_out;
        }
        insn->moffset1.got = insn->moffset2.got = 1;
+        return 1;
 err_out:
-        return;
+        return 0;
 }
-/* Decode imm v32(Iz) */
+/* Decode imm v32(Iz). Return 0 if failed */
-static void __get_immv32(struct insn *insn)
+static int __get_immv32(struct insn *insn)
 {
        switch (insn->opnd_bytes) {
        case 2:
@@ -417,14 +421,18 @@ static void __get_immv32(struct insn *insn)
                insn->immediate.value = get_next(int, insn);
                insn->immediate.nbytes = 4;
                break;
+        default:        /* opnd_bytes must be modified manually */
+                goto err_out;
        }
+        return 1;
 err_out:
-        return;
+        return 0;
 }
-/* Decode imm v64(Iv/Ov) */
+/* Decode imm v64(Iv/Ov), Return 0 if failed */
-static void __get_immv(struct insn *insn)
+static int __get_immv(struct insn *insn)
 {
        switch (insn->opnd_bytes) {
        case 2:
@@ -441,15 +449,18 @@ static void __get_immv(struct insn *insn)
                insn->immediate2.value = get_next(int, insn);
                insn->immediate2.nbytes = 4;
                break;
+        default:        /* opnd_bytes must be modified manually */
+                goto err_out;
        }
        insn->immediate1.got = insn->immediate2.got = 1;
+        return 1;
 err_out:
-        return;
+        return 0;
 }
 /* Decode ptr16:16/32(Ap) */
-static void __get_immptr(struct insn *insn)
+static int __get_immptr(struct insn *insn)
 {
        switch (insn->opnd_bytes) {
        case 2:
@@ -462,14 +473,17 @@ static void __get_immptr(struct insn *insn)
                break;
        case 8:
                /* ptr16:64 is not exist (no segment) */
-                return;
+                return 0;
+        default:        /* opnd_bytes must be modified manually */
+                goto err_out;
        }
        insn->immediate2.value = get_next(unsigned short, insn);
        insn->immediate2.nbytes = 2;
        insn->immediate1.got = insn->immediate2.got = 1;
+        return 1;
 err_out:
-        return;
+        return 0;
 }
 /**
@@ -489,7 +503,8 @@ void insn_get_immediate(struct insn *insn)
                insn_get_displacement(insn);
        if (inat_has_moffset(insn->attr)) {
-                __get_moffset(insn);
+                if (!__get_moffset(insn))
+                        goto err_out;
                goto done;
        }
@@ -517,16 +532,20 @@ void insn_get_immediate(struct insn *insn)
                insn->immediate2.nbytes = 4;
                break;
        case INAT_IMM_PTR:
-                __get_immptr(insn);
+                if (!__get_immptr(insn))
+                        goto err_out;
                break;
        case INAT_IMM_VWORD32:
-                __get_immv32(insn);
+                if (!__get_immv32(insn))
+                        goto err_out;
                break;
        case INAT_IMM_VWORD:
-                __get_immv(insn);
+                if (!__get_immv(insn))
+                        goto err_out;
                break;
        default:
-                break;
+                /* Here, insn must have an immediate, but failed */
+                goto err_out;
        }
        if (inat_has_second_immediate(insn->attr)) {
                insn->immediate2.value = get_next(char, insn);
diff --git a/arch/x86/lib/usercopy.c b/arch/x86/lib/usercopy.c
index 97be9cb54483..2e4e4b02c37a 100644
--- a/arch/x86/lib/usercopy.c
+++ b/arch/x86/lib/usercopy.c
@@ -7,6 +7,8 @@
 #include <linux/highmem.h>
 #include <linux/module.h>
+#include <asm/word-at-a-time.h>
 /*
 * best effort, GUP based copy_from_user() that is NMI-safe
 */
@@ -41,3 +43,100 @@ copy_from_user_nmi(void *to, const void __user *from, unsigned long n)
        return len;
 }
 EXPORT_SYMBOL_GPL(copy_from_user_nmi);
+/*
+ * Do a strncpy, return length of string without final '\0'.
+ * 'count' is the user-supplied count (return 'count' if we
+ * hit it), 'max' is the address space maximum (and we return
+ * -EFAULT if we hit it).
+ */
+static inline long do_strncpy_from_user(char *dst, const char __user *src, long count, unsigned long max)
+{
+        long res = 0;
+        /*
+         * Truncate 'max' to the user-specified limit, so that
+         * we only have one limit we need to check in the loop
+         */
+        if (max > count)
+                max = count;
+        while (max >= sizeof(unsigned long)) {
+                unsigned long c, mask;
+                /* Fall back to byte-at-a-time if we get a page fault */
+                if (unlikely(__get_user(c,(unsigned long __user *)(src+res))))
+                        break;
+                mask = has_zero(c);
+                if (mask) {
+                        mask = (mask - 1) & ~mask;
+                        mask >>= 7;
+                        *(unsigned long *)(dst+res) = c & mask;
+                        return res + count_masked_bytes(mask);
+                }
+                *(unsigned long *)(dst+res) = c;
+                res += sizeof(unsigned long);
+                max -= sizeof(unsigned long);
+        }
+        while (max) {
+                char c;
+                if (unlikely(__get_user(c,src+res)))
+                        return -EFAULT;
+                dst[res] = c;
+                if (!c)
+                        return res;
+                res++;
+                max--;
+        }
+        /*
+         * Uhhuh. We hit 'max'. But was that the user-specified maximum
+         * too? If so, that's ok - we got as much as the user asked for.
+         */
+        if (res >= count)
+                return res;
+        /*
+         * Nope: we hit the address space limit, and we still had more
+         * characters the caller would have wanted. That's an EFAULT.
+         */
+        return -EFAULT;
+}
+/**
+ * strncpy_from_user: - Copy a NUL terminated string from userspace.
+ * @dst:   Destination address, in kernel space.  This buffer must be at
+ *         least @count bytes long.
+ * @src:   Source address, in user space.
+ * @count: Maximum number of bytes to copy, including the trailing NUL.
+ *
+ * Copies a NUL-terminated string from userspace to kernel space.
+ *
+ * On success, returns the length of the string (not including the trailing
+ * NUL).
+ *
+ * If access to userspace fails, returns -EFAULT (some data may have been
+ * copied).
+ *
+ * If @count is smaller than the length of the string, copies @count bytes
+ * and returns @count.
+ */
+long
+strncpy_from_user(char *dst, const char __user *src, long count)
+{
+        unsigned long max_addr, src_addr;
+        if (unlikely(count <= 0))
+                return 0;
+        max_addr = current_thread_info()->addr_limit.seg;
+        src_addr = (unsigned long)src;
+        if (likely(src_addr < max_addr)) {
+                unsigned long max = max_addr - src_addr;
+                return do_strncpy_from_user(dst, src, count, max);
+        }
+        return -EFAULT;
+}
+EXPORT_SYMBOL(strncpy_from_user);
diff --git a/arch/x86/lib/usercopy_32.c b/arch/x86/lib/usercopy_32.c
index d9b094ca7aaa..ef2a6a5d78e3 100644
--- a/arch/x86/lib/usercopy_32.c
+++ b/arch/x86/lib/usercopy_32.c
@@ -33,93 +33,6 @@ static inline int __movsl_is_ok(unsigned long a1, unsigned long a2, unsigned lon
        __movsl_is_ok((unsigned long)(a1), (unsigned long)(a2), (n))
 /*
- * Copy a null terminated string from userspace.
- */
-#define __do_strncpy_from_user(dst, src, count, res)                       \
-do {                                                                       \
-        int __d0, __d1, __d2;                                              \
-        might_fault();                                                     \
-        __asm__ __volatile__(                                              \
-                "       testl %1,%1\n"                                     \
-                "       jz 2f\n"                                           \
-                "0:     lodsb\n"                                           \
-                "       stosb\n"                                           \
-                "       testb %%al,%%al\n"                                 \
-                "       jz 1f\n"                                           \
-                "       decl %1\n"                                         \
-                "       jnz 0b\n"                                          \
-                "1:     subl %1,%0\n"                                      \
-                "2:\n"                                                     \
-                ".section .fixup,\"ax\"\n"                                 \
-                "3:     movl %5,%0\n"                                      \
-                "       jmp 2b\n"                                          \
-                ".previous\n"                                              \
-                _ASM_EXTABLE(0b,3b)                                        \
-                : "=&d"(res), "=&c"(count), "=&a" (__d0), "=&S" (__d1),    \
-                  "=&D" (__d2)                                             \
-                : "i"(-EFAULT), "0"(count), "1"(count), "3"(src), "4"(dst) \
-                : "memory");                                               \
-} while (0)
-/**
- * __strncpy_from_user: - Copy a NUL terminated string from userspace, with less checking.
- * @dst:   Destination address, in kernel space.  This buffer must be at
- *         least @count bytes long.
- * @src:   Source address, in user space.
- * @count: Maximum number of bytes to copy, including the trailing NUL.
- *
- * Copies a NUL-terminated string from userspace to kernel space.
- * Caller must check the specified block with access_ok() before calling
- * this function.
- *
- * On success, returns the length of the string (not including the trailing
- * NUL).
- *
- * If access to userspace fails, returns -EFAULT (some data may have been
- * copied).
- *
- * If @count is smaller than the length of the string, copies @count bytes
- * and returns @count.
- */
-long
-__strncpy_from_user(char *dst, const char __user *src, long count)
-{
-        long res;
-        __do_strncpy_from_user(dst, src, count, res);
-        return res;
-}
-EXPORT_SYMBOL(__strncpy_from_user);
-/**
- * strncpy_from_user: - Copy a NUL terminated string from userspace.
- * @dst:   Destination address, in kernel space.  This buffer must be at
- *         least @count bytes long.
- * @src:   Source address, in user space.
- * @count: Maximum number of bytes to copy, including the trailing NUL.
- *
- * Copies a NUL-terminated string from userspace to kernel space.
- *
- * On success, returns the length of the string (not including the trailing
- * NUL).
- *
- * If access to userspace fails, returns -EFAULT (some data may have been
- * copied).
- *
- * If @count is smaller than the length of the string, copies @count bytes
- * and returns @count.
- */
-long
-strncpy_from_user(char *dst, const char __user *src, long count)
-{
-        long res = -EFAULT;
-        if (access_ok(VERIFY_READ, src, 1))
-                __do_strncpy_from_user(dst, src, count, res);
-        return res;
-}
-EXPORT_SYMBOL(strncpy_from_user);
-/*
 * Zero Userspace
 */
diff --git a/arch/x86/lib/usercopy_64.c b/arch/x86/lib/usercopy_64.c
index b7c2849ffb66..0d0326f388c0 100644
--- a/arch/x86/lib/usercopy_64.c
+++ b/arch/x86/lib/usercopy_64.c
@@ -9,55 +9,6 @@
 #include <asm/uaccess.h>
 /*
- * Copy a null terminated string from userspace.
- */
-#define __do_strncpy_from_user(dst,src,count,res)                          \
-do {                                                                       \
-        long __d0, __d1, __d2;                                             \
-        might_fault();                                                     \
-        __asm__ __volatile__(                                              \
-                "       testq %1,%1\n"                                     \
-                "       jz 2f\n"                                           \
-                "0:     lodsb\n"                                           \
-                "       stosb\n"                                           \
-                "       testb %%al,%%al\n"                                 \
-                "       jz 1f\n"                                           \
-                "       decq %1\n"                                         \
-                "       jnz 0b\n"                                          \
-                "1:     subq %1,%0\n"                                      \
-                "2:\n"                                                     \
-                ".section .fixup,\"ax\"\n"                                 \
-                "3:     movq %5,%0\n"                                      \
-                "       jmp 2b\n"                                          \
-                ".previous\n"                                              \
-                _ASM_EXTABLE(0b,3b)                                        \
-                : "=&r"(res), "=&c"(count), "=&a" (__d0), "=&S" (__d1),    \
-                  "=&D" (__d2)                                             \
-                : "i"(-EFAULT), "0"(count), "1"(count), "3"(src), "4"(dst) \
-                : "memory");                                               \
-} while (0)
-long
-__strncpy_from_user(char *dst, const char __user *src, long count)
-{
-        long res;
-        __do_strncpy_from_user(dst, src, count, res);
-        return res;
-}
-EXPORT_SYMBOL(__strncpy_from_user);
-long
-strncpy_from_user(char *dst, const char __user *src, long count)
-{
-        long res = -EFAULT;
-        if (access_ok(VERIFY_READ, src, 1))
-                return __strncpy_from_user(dst, src, count);
-        return res;
-}
-EXPORT_SYMBOL(strncpy_from_user);
-/*
 * Zero Userspace
 */
diff --git a/arch/x86/mm/numa_emulation.c b/arch/x86/mm/numa_emulation.c
index 53489ff6bf82..871dd8868170 100644
--- a/arch/x86/mm/numa_emulation.c
+++ b/arch/x86/mm/numa_emulation.c
@@ -339,9 +339,11 @@ void __init numa_emulation(struct numa_meminfo *numa_meminfo, int numa_dist_cnt)
        } else {
                unsigned long n;
-                n = simple_strtoul(emu_cmdline, NULL, 0);
+                n = simple_strtoul(emu_cmdline, &emu_cmdline, 0);
                ret = split_nodes_interleave(&ei, &pi, 0, max_addr, n);
        }
+        if (*emu_cmdline == ':')
+                emu_cmdline++;
        if (ret < 0)
                goto no_emu;
@@ -418,7 +420,9 @@ void __init numa_emulation(struct numa_meminfo *numa_meminfo, int numa_dist_cnt)
                        int physj = emu_nid_to_phys[j];
                        int dist;
-                        if (physi >= numa_dist_cnt || physj >= numa_dist_cnt)
+                        if (get_option(&emu_cmdline, &dist) == 2)
+                                ;
+                        else if (physi >= numa_dist_cnt || physj >= numa_dist_cnt)
                                dist = physi == physj ?
                                        LOCAL_DISTANCE : REMOTE_DISTANCE;
                        else
diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c
index d6c0418c3e47..3804471db104 100644
--- a/arch/x86/mm/tlb.c
+++ b/arch/x86/mm/tlb.c
@@ -61,10 +61,10 @@ static DEFINE_PER_CPU_READ_MOSTLY(int, tlb_vector_offset);
 */
 void leave_mm(int cpu)
 {
-        if (percpu_read(cpu_tlbstate.state) == TLBSTATE_OK)
+        if (this_cpu_read(cpu_tlbstate.state) == TLBSTATE_OK)
                BUG();
        cpumask_clear_cpu(cpu,
-                          mm_cpumask(percpu_read(cpu_tlbstate.active_mm)));
+                          mm_cpumask(this_cpu_read(cpu_tlbstate.active_mm)));
        load_cr3(swapper_pg_dir);
 }
 EXPORT_SYMBOL_GPL(leave_mm);
@@ -152,8 +152,8 @@ void smp_invalidate_interrupt(struct pt_regs *regs)
                 * BUG();
                 */
-        if (f->flush_mm == percpu_read(cpu_tlbstate.active_mm)) {
+        if (f->flush_mm == this_cpu_read(cpu_tlbstate.active_mm)) {
-                if (percpu_read(cpu_tlbstate.state) == TLBSTATE_OK) {
+                if (this_cpu_read(cpu_tlbstate.state) == TLBSTATE_OK) {
                        if (f->flush_va == TLB_FLUSH_ALL)
                                local_flush_tlb();
                        else
@@ -322,7 +322,7 @@ void flush_tlb_page(struct vm_area_struct *vma, unsigned long va)
 static void do_flush_tlb_all(void *info)
 {
        __flush_tlb_all();
-        if (percpu_read(cpu_tlbstate.state) == TLBSTATE_LAZY)
+        if (this_cpu_read(cpu_tlbstate.state) == TLBSTATE_LAZY)
                leave_mm(smp_processor_id());
 }
diff --git a/arch/x86/pci/acpi.c b/arch/x86/pci/acpi.c
index ed2835e148b5..fc09c2754e08 100644
--- a/arch/x86/pci/acpi.c
+++ b/arch/x86/pci/acpi.c
@@ -9,11 +9,11 @@
 struct pci_root_info {
        struct acpi_device *bridge;
-        char *name;
+        char name[16];
        unsigned int res_num;
        struct resource *res;
-        struct list_head *resources;
        int busnum;
+        struct pci_sysdata sd;
 };
 static bool pci_use_crs = true;
@@ -245,13 +245,6 @@ setup_resource(struct acpi_resource *acpi_res, void *data)
        return AE_OK;
 }
-static bool resource_contains(struct resource *res, resource_size_t point)
-{
-        if (res->start <= point && point <= res->end)
-                return true;
-        return false;
-}
 static void coalesce_windows(struct pci_root_info *info, unsigned long type)
 {
        int i, j;
@@ -272,10 +265,7 @@ static void coalesce_windows(struct pci_root_info *info, unsigned long type)
                         * our resources no longer match the ACPI _CRS, but
                         * the kernel resource tree doesn't allow overlaps.
                         */
-                        if (resource_contains(res1, res2->start) ||
+                        if (resource_overlaps(res1, res2)) {
-                            resource_contains(res1, res2->end) ||
-                            resource_contains(res2, res1->start) ||
-                            resource_contains(res2, res1->end)) {
                                res1->start = min(res1->start, res2->start);
                                res1->end = max(res1->end, res2->end);
                                dev_info(&info->bridge->dev,
@@ -287,7 +277,8 @@ static void coalesce_windows(struct pci_root_info *info, unsigned long type)
        }
 }
-static void add_resources(struct pci_root_info *info)
+static void add_resources(struct pci_root_info *info,
+                          struct list_head *resources)
 {
        int i;
        struct resource *res, *root, *conflict;
@@ -311,53 +302,74 @@ static void add_resources(struct pci_root_info *info)
                                 "ignoring host bridge window %pR (conflicts with %s %pR)\n",
                                 res, conflict->name, conflict);
                else
-                        pci_add_resource(info->resources, res);
+                        pci_add_resource(resources, res);
        }
 }
+static void free_pci_root_info_res(struct pci_root_info *info)
+{
+        kfree(info->res);
+        info->res = NULL;
+        info->res_num = 0;
+}
+static void __release_pci_root_info(struct pci_root_info *info)
+{
+        int i;
+        struct resource *res;
+        for (i = 0; i < info->res_num; i++) {
+                res = &info->res[i];
+                if (!res->parent)
+                        continue;
+                if (!(res->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
+                        continue;
+                release_resource(res);
+        }
+        free_pci_root_info_res(info);
+        kfree(info);
+}
+static void release_pci_root_info(struct pci_host_bridge *bridge)
+{
+        struct pci_root_info *info = bridge->release_data;
+        __release_pci_root_info(info);
+}
 static void
-get_current_resources(struct acpi_device *device, int busnum,
+probe_pci_root_info(struct pci_root_info *info, struct acpi_device *device,
-                      int domain, struct list_head *resources)
+                    int busnum, int domain)
 {
-        struct pci_root_info info;
        size_t size;
-        info.bridge = device;
+        info->bridge = device;
-        info.res_num = 0;
+        info->res_num = 0;
-        info.resources = resources;
        acpi_walk_resources(device->handle, METHOD_NAME__CRS, count_resource,
-                                &info);
+                                info);
-        if (!info.res_num)
+        if (!info->res_num)
                return;
-        size = sizeof(*info.res) * info.res_num;
+        size = sizeof(*info->res) * info->res_num;
-        info.res = kmalloc(size, GFP_KERNEL);
+        info->res_num = 0;
-        if (!info.res)
+        info->res = kmalloc(size, GFP_KERNEL);
+        if (!info->res)
                return;
-        info.name = kasprintf(GFP_KERNEL, "PCI Bus %04x:%02x", domain, busnum);
+        sprintf(info->name, "PCI Bus %04x:%02x", domain, busnum);
-        if (!info.name)
-                goto name_alloc_fail;
-        info.res_num = 0;
        acpi_walk_resources(device->handle, METHOD_NAME__CRS, setup_resource,
-                                &info);
+                                info);
-        if (pci_use_crs) {
-                add_resources(&info);
-                return;
-        }
-        kfree(info.name);
-name_alloc_fail:
-        kfree(info.res);
 }
 struct pci_bus * __devinit pci_acpi_scan_root(struct acpi_pci_root *root)
 {
        struct acpi_device *device = root->device;
+        struct pci_root_info *info = NULL;
        int domain = root->segment;
        int busnum = root->secondary.start;
        LIST_HEAD(resources);
@@ -389,17 +401,14 @@ struct pci_bus * __devinit pci_acpi_scan_root(struct acpi_pci_root *root)
        if (node != -1 && !node_online(node))
                node = -1;
-        /* Allocate per-root-bus (not per bus) arch-specific data.
+        info = kzalloc(sizeof(*info), GFP_KERNEL);
-         * TODO: leak; this memory is never freed.
+        if (!info) {
-         * It's arguable whether it's worth the trouble to care.
-         */
-        sd = kzalloc(sizeof(*sd), GFP_KERNEL);
-        if (!sd) {
                printk(KERN_WARNING "pci_bus %04x:%02x: "
                       "ignored (out of memory)\n", domain, busnum);
                return NULL;
        }
+        sd = &info->sd;
        sd->domain = domain;
        sd->node = node;
        /*
@@ -413,22 +422,32 @@ struct pci_bus * __devinit pci_acpi_scan_root(struct acpi_pci_root *root)
                 * be replaced by sd.
                 */
                memcpy(bus->sysdata, sd, sizeof(*sd));
-                kfree(sd);
+                kfree(info);
        } else {
-                get_current_resources(device, busnum, domain, &resources);
+                probe_pci_root_info(info, device, busnum, domain);
                /*
                 * _CRS with no apertures is normal, so only fall back to
                 * defaults or native bridge info if we're ignoring _CRS.
                 */
-                if (!pci_use_crs)
+                if (pci_use_crs)
+                        add_resources(info, &resources);
+                else {
+                        free_pci_root_info_res(info);
                        x86_pci_root_bus_resources(busnum, &resources);
+                }
                bus = pci_create_root_bus(NULL, busnum, &pci_root_ops, sd,
                                          &resources);
-                if (bus)
+                if (bus) {
                        bus->subordinate = pci_scan_child_bus(bus);
-                else
+                        pci_set_host_bridge_release(
+                                to_pci_host_bridge(bus->bridge),
+                                release_pci_root_info, info);
+                } else {
                        pci_free_resource_list(&resources);
+                        __release_pci_root_info(info);
+                }
        }
        /* After the PCI-E bus has been walked and all devices discovered,
@@ -445,9 +464,6 @@ struct pci_bus * __devinit pci_acpi_scan_root(struct acpi_pci_root *root)
                }
        }
-        if (!bus)
-                kfree(sd);
        if (bus && node != -1) {
 #ifdef CONFIG_ACPI_NUMA
                if (pxm >= 0)
diff --git a/arch/x86/pci/amd_bus.c b/arch/x86/pci/amd_bus.c
index 0567df3890e1..5aed49bff058 100644
--- a/arch/x86/pci/amd_bus.c
+++ b/arch/x86/pci/amd_bus.c
@@ -32,6 +32,27 @@ static struct pci_hostbridge_probe pci_probes[] __initdata = {
 #define RANGE_NUM 16
+static struct pci_root_info __init *find_pci_root_info(int node, int link)
+{
+        struct pci_root_info *info;
+        /* find the position */
+        list_for_each_entry(info, &pci_root_infos, list)
+                if (info->node == node && info->link == link)
+                        return info;
+        return NULL;
+}
+static void __init set_mp_bus_range_to_node(int min_bus, int max_bus, int node)
+{
+#ifdef CONFIG_NUMA
+        int j;
+        for (j = min_bus; j <= max_bus; j++)
+                set_mp_bus_to_node(j, node);
+#endif
+}
 /**
 * early_fill_mp_bus_to_node()
 * called before pcibios_scan_root and pci_scan_bus
@@ -41,7 +62,6 @@ static struct pci_hostbridge_probe pci_probes[] __initdata = {
 static int __init early_fill_mp_bus_info(void)
 {
        int i;
-        int j;
        unsigned bus;
        unsigned slot;
        int node;
@@ -50,7 +70,6 @@ static int __init early_fill_mp_bus_info(void)
        int def_link;
        struct pci_root_info *info;
        u32 reg;
-        struct resource *res;
        u64 start;
        u64 end;
        struct range range[RANGE_NUM];
@@ -86,7 +105,6 @@ static int __init early_fill_mp_bus_info(void)
        if (!found)
                return 0;
-        pci_root_num = 0;
        for (i = 0; i < 4; i++) {
                int min_bus;
                int max_bus;
@@ -99,19 +117,11 @@ static int __init early_fill_mp_bus_info(void)
                min_bus = (reg >> 16) & 0xff;
                max_bus = (reg >> 24) & 0xff;
                node = (reg >> 4) & 0x07;
-#ifdef CONFIG_NUMA
+                set_mp_bus_range_to_node(min_bus, max_bus, node);
-                for (j = min_bus; j <= max_bus; j++)
-                        set_mp_bus_to_node(j, node);
-#endif
                link = (reg >> 8) & 0x03;
-                info = &pci_root_info[pci_root_num];
+                info = alloc_pci_root_info(min_bus, max_bus, node, link);
-                info->bus_min = min_bus;
-                info->bus_max = max_bus;
-                info->node = node;
-                info->link = link;
                sprintf(info->name, "PCI Bus #%02x", min_bus);
-                pci_root_num++;
        }
        /* get the default node and link for left over res */
@@ -134,16 +144,10 @@ static int __init early_fill_mp_bus_info(void)
                link = (reg >> 4) & 0x03;
                end = (reg & 0xfff000) | 0xfff;
-                /* find the position */
+                info = find_pci_root_info(node, link);
-                for (j = 0; j < pci_root_num; j++) {
+                if (!info)
-                        info = &pci_root_info[j];
-                        if (info->node == node && info->link == link)
-                                break;
-                }
-                if (j == pci_root_num)
                        continue; /* not found */
-                info = &pci_root_info[j];
                printk(KERN_DEBUG "node %d link %d: io port [%llx, %llx]\n",
                       node, link, start, end);
@@ -155,13 +159,8 @@ static int __init early_fill_mp_bus_info(void)
        }
        /* add left over io port range to def node/link, [0, 0xffff] */
        /* find the position */
-        for (j = 0; j < pci_root_num; j++) {
+        info = find_pci_root_info(def_node, def_link);
-                info = &pci_root_info[j];
+        if (info) {
-                if (info->node == def_node && info->link == def_link)
-                        break;
-        }
-        if (j < pci_root_num) {
-                info = &pci_root_info[j];
                for (i = 0; i < RANGE_NUM; i++) {
                        if (!range[i].end)
                                continue;
@@ -214,16 +213,10 @@ static int __init early_fill_mp_bus_info(void)
                end <<= 8;
                end |= 0xffff;
-                /* find the position */
+                info = find_pci_root_info(node, link);
-                for (j = 0; j < pci_root_num; j++) {
-                        info = &pci_root_info[j];
-                        if (info->node == node && info->link == link)
-                                break;
-                }
-                if (j == pci_root_num)
-                        continue; /* not found */
-                info = &pci_root_info[j];
+                if (!info)
+                        continue;
                printk(KERN_DEBUG "node %d link %d: mmio [%llx, %llx]",
                       node, link, start, end);
@@ -291,14 +284,8 @@ static int __init early_fill_mp_bus_info(void)
         * add left over mmio range to def node/link ?
         * that is tricky, just record range in from start_min to 4G
         */
-        for (j = 0; j < pci_root_num; j++) {
+        info = find_pci_root_info(def_node, def_link);
-                info = &pci_root_info[j];
+        if (info) {
-                if (info->node == def_node && info->link == def_link)
-                        break;
-        }
-        if (j < pci_root_num) {
-                info = &pci_root_info[j];
                for (i = 0; i < RANGE_NUM; i++) {
                        if (!range[i].end)
                                continue;
@@ -309,20 +296,16 @@ static int __init early_fill_mp_bus_info(void)
                }
        }
-        for (i = 0; i < pci_root_num; i++) {
+        list_for_each_entry(info, &pci_root_infos, list) {
-                int res_num;
                int busnum;
+                struct pci_root_res *root_res;
-                info = &pci_root_info[i];
-                res_num = info->res_num;
                busnum = info->bus_min;
                printk(KERN_DEBUG "bus: [%02x, %02x] on node %x link %x\n",
                       info->bus_min, info->bus_max, info->node, info->link);
-                for (j = 0; j < res_num; j++) {
+                list_for_each_entry(root_res, &info->resources, list)
-                        res = &info->res[j];
+                        printk(KERN_DEBUG "bus: %02x %pR\n",
-                        printk(KERN_DEBUG "bus: %02x index %x %pR\n",
+                                       busnum, &root_res->res);
-                                       busnum, j, res);
-                }
        }
        return 0;
diff --git a/arch/x86/pci/broadcom_bus.c b/arch/x86/pci/broadcom_bus.c
index f3a7c569a403..614392ced7d6 100644
--- a/arch/x86/pci/broadcom_bus.c
+++ b/arch/x86/pci/broadcom_bus.c
@@ -22,19 +22,15 @@
 static void __init cnb20le_res(u8 bus, u8 slot, u8 func)
 {
        struct pci_root_info *info;
+        struct pci_root_res *root_res;
        struct resource res;
        u16 word1, word2;
        u8 fbus, lbus;
-        int i;
-        info = &pci_root_info[pci_root_num];
-        pci_root_num++;
        /* read the PCI bus numbers */
        fbus = read_pci_config_byte(bus, slot, func, 0x44);
        lbus = read_pci_config_byte(bus, slot, func, 0x45);
-        info->bus_min = fbus;
+        info = alloc_pci_root_info(fbus, lbus, 0, 0);
-        info->bus_max = lbus;
        /*
         * Add the legacy IDE ports on bus 0
@@ -86,8 +82,8 @@ static void __init cnb20le_res(u8 bus, u8 slot, u8 func)
        res.flags = IORESOURCE_BUS;
        printk(KERN_INFO "CNB20LE PCI Host Bridge (domain 0000 %pR)\n", &res);
-        for (i = 0; i < info->res_num; i++)
+        list_for_each_entry(root_res, &info->resources, list)
-                printk(KERN_INFO "host bridge window %pR\n", &info->res[i]);
+                printk(KERN_INFO "host bridge window %pR\n", &root_res->res);
 }
 static int __init broadcom_postcore_init(void)
diff --git a/arch/x86/pci/bus_numa.c b/arch/x86/pci/bus_numa.c
index fd3f65510e9d..306579f7d0fd 100644
--- a/arch/x86/pci/bus_numa.c
+++ b/arch/x86/pci/bus_numa.c
@@ -4,35 +4,38 @@
 #include "bus_numa.h"
-int pci_root_num;
+LIST_HEAD(pci_root_infos);
-struct pci_root_info pci_root_info[PCI_ROOT_NR];
-void x86_pci_root_bus_resources(int bus, struct list_head *resources)
+static struct pci_root_info *x86_find_pci_root_info(int bus)
 {
-        int i;
-        int j;
        struct pci_root_info *info;
-        if (!pci_root_num)
+        if (list_empty(&pci_root_infos))
-                goto default_resources;
+                return NULL;
-        for (i = 0; i < pci_root_num; i++) {
+        list_for_each_entry(info, &pci_root_infos, list)
-                if (pci_root_info[i].bus_min == bus)
+                if (info->bus_min == bus)
-                        break;
+                        return info;
-        }
+        return NULL;
+}
-        if (i == pci_root_num)
+void x86_pci_root_bus_resources(int bus, struct list_head *resources)
+{
+        struct pci_root_info *info = x86_find_pci_root_info(bus);
+        struct pci_root_res *root_res;
+        if (!info)
                goto default_resources;
        printk(KERN_DEBUG "PCI: root bus %02x: hardware-probed resources\n",
               bus);
-        info = &pci_root_info[i];
+        list_for_each_entry(root_res, &info->resources, list) {
-        for (j = 0; j < info->res_num; j++) {
                struct resource *res;
                struct resource *root;
-                res = &info->res[j];
+                res = &root_res->res;
                pci_add_resource(resources, res);
                if (res->flags & IORESOURCE_IO)
                        root = &ioport_resource;
@@ -53,11 +56,32 @@ default_resources:
        pci_add_resource(resources, &iomem_resource);
 }
+struct pci_root_info __init *alloc_pci_root_info(int bus_min, int bus_max,
+                                                 int node, int link)
+{
+        struct pci_root_info *info;
+        info = kzalloc(sizeof(*info), GFP_KERNEL);
+        if (!info)
+                return info;
+        INIT_LIST_HEAD(&info->resources);
+        info->bus_min = bus_min;
+        info->bus_max = bus_max;
+        info->node = node;
+        info->link = link;
+        list_add_tail(&info->list, &pci_root_infos);
+        return info;
+}
 void __devinit update_res(struct pci_root_info *info, resource_size_t start,
                          resource_size_t end, unsigned long flags, int merge)
 {
-        int i;
        struct resource *res;
+        struct pci_root_res *root_res;
        if (start > end)
                return;
@@ -69,11 +93,11 @@ void __devinit update_res(struct pci_root_info *info, resource_size_t start,
                goto addit;
        /* try to merge it with old one */
-        for (i = 0; i < info->res_num; i++) {
+        list_for_each_entry(root_res, &info->resources, list) {
                resource_size_t final_start, final_end;
                resource_size_t common_start, common_end;
-                res = &info->res[i];
+                res = &root_res->res;
                if (res->flags != flags)
                        continue;
@@ -93,14 +117,15 @@ void __devinit update_res(struct pci_root_info *info, resource_size_t start,
 addit:
        /* need to add that */
-        if (info->res_num >= RES_NUM)
+        root_res = kzalloc(sizeof(*root_res), GFP_KERNEL);
+        if (!root_res)
                return;
-        res = &info->res[info->res_num];
+        res = &root_res->res;
        res->name = info->name;
        res->flags = flags;
        res->start = start;
        res->end = end;
-        res->child = NULL;
-        info->res_num++;
+        list_add_tail(&root_res->list, &info->resources);
 }
diff --git a/arch/x86/pci/bus_numa.h b/arch/x86/pci/bus_numa.h
index 804a4b40c31a..226a466b2b2b 100644
--- a/arch/x86/pci/bus_numa.h
+++ b/arch/x86/pci/bus_numa.h
@@ -4,22 +4,24 @@
 * sub bus (transparent) will use entres from 3 to store extra from
 * root, so need to make sure we have enough slot there.
 */
-#define RES_NUM 16
+struct pci_root_res {
+        struct list_head list;
+        struct resource res;
+};
 struct pci_root_info {
+        struct list_head list;
        char name[12];
-        unsigned int res_num;
+        struct list_head resources;
-        struct resource res[RES_NUM];
        int bus_min;
        int bus_max;
        int node;
        int link;
 };
-/* 4 at this time, it may become to 32 */
+extern struct list_head pci_root_infos;
-#define PCI_ROOT_NR 4
+struct pci_root_info *alloc_pci_root_info(int bus_min, int bus_max,
-extern int pci_root_num;
+                                                int node, int link);
-extern struct pci_root_info pci_root_info[PCI_ROOT_NR];
 extern void update_res(struct pci_root_info *info, resource_size_t start,
                      resource_size_t end, unsigned long flags, int merge);
 #endif
diff --git a/arch/x86/pci/common.c b/arch/x86/pci/common.c
index 323481e06ef8..0ad990a20d4a 100644
--- a/arch/x86/pci/common.c
+++ b/arch/x86/pci/common.c
@@ -11,6 +11,7 @@
 #include <linux/dmi.h>
 #include <linux/slab.h>
+#include <asm-generic/pci-bridge.h>
 #include <asm/acpi.h>
 #include <asm/segment.h>
 #include <asm/io.h>
@@ -229,6 +230,14 @@ static int __devinit assign_all_busses(const struct dmi_system_id *d)
 }
 #endif
+static int __devinit set_scan_all(const struct dmi_system_id *d)
+{
+        printk(KERN_INFO "PCI: %s detected, enabling pci=pcie_scan_all\n",
+               d->ident);
+        pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
+        return 0;
+}
 static const struct dmi_system_id __devinitconst pciprobe_dmi_table[] = {
 #ifdef __i386__
 /*
@@ -420,6 +429,13 @@ static const struct dmi_system_id __devinitconst pciprobe_dmi_table[] = {
                        DMI_MATCH(DMI_PRODUCT_NAME, "ProLiant DL585 G2"),
                },
        },
+        {
+                .callback = set_scan_all,
+                .ident = "Stratus/NEC ftServer",
+                .matches = {
+                        DMI_MATCH(DMI_SYS_VENDOR, "ftServer"),
+                },
+        },
        {}
 };
@@ -430,9 +446,7 @@ void __init dmi_check_pciprobe(void)
 struct pci_bus * __devinit pcibios_scan_root(int busnum)
 {
-        LIST_HEAD(resources);
        struct pci_bus *bus = NULL;
-        struct pci_sysdata *sd;
        while ((bus = pci_find_next_bus(bus)) != NULL) {
                if (bus->number == busnum) {
@@ -441,28 +455,10 @@ struct pci_bus * __devinit pcibios_scan_root(int busnum)
                }
        }
-        /* Allocate per-root-bus (not per bus) arch-specific data.
+        return pci_scan_bus_on_node(busnum, &pci_root_ops,
-         * TODO: leak; this memory is never freed.
+                                        get_mp_bus_to_node(busnum));
-         * It's arguable whether it's worth the trouble to care.
-         */
-        sd = kzalloc(sizeof(*sd), GFP_KERNEL);
-        if (!sd) {
-                printk(KERN_ERR "PCI: OOM, not probing PCI bus %02x\n", busnum);
-                return NULL;
-        }
-        sd->node = get_mp_bus_to_node(busnum);
-        printk(KERN_DEBUG "PCI: Probing PCI hardware (bus %02x)\n", busnum);
-        x86_pci_root_bus_resources(busnum, &resources);
-        bus = pci_scan_root_bus(NULL, busnum, &pci_root_ops, sd, &resources);
-        if (!bus) {
-                pci_free_resource_list(&resources);
-                kfree(sd);
-        }
-        return bus;
 }
 void __init pcibios_set_cache_line_size(void)
 {
        struct cpuinfo_x86 *c = &boot_cpu_data;
@@ -656,6 +652,7 @@ struct pci_bus * __devinit pci_scan_bus_on_node(int busno, struct pci_ops *ops,
        }
        sd->node = node;
        x86_pci_root_bus_resources(busno, &resources);
+        printk(KERN_DEBUG "PCI: Probing PCI hardware (bus %02x)\n", busno);
        bus = pci_scan_root_bus(NULL, busno, ops, sd, &resources);
        if (!bus) {
                pci_free_resource_list(&resources);
diff --git a/arch/x86/pci/i386.c b/arch/x86/pci/i386.c
index 831971e731f7..dd8ca6f7223b 100644
--- a/arch/x86/pci/i386.c
+++ b/arch/x86/pci/i386.c
@@ -57,7 +57,7 @@ static struct pcibios_fwaddrmap *pcibios_fwaddrmap_lookup(struct pci_dev *dev)
 {
        struct pcibios_fwaddrmap *map;
-        WARN_ON(!spin_is_locked(&pcibios_fwaddrmap_lock));
+        WARN_ON_SMP(!spin_is_locked(&pcibios_fwaddrmap_lock));
        list_for_each_entry(map, &pcibios_fwaddrmappings, list)
                if (map->dev == dev)
diff --git a/arch/x86/platform/geode/net5501.c b/arch/x86/platform/geode/net5501.c
index 66d377e334f7..646e3b5b4bb6 100644
--- a/arch/x86/platform/geode/net5501.c
+++ b/arch/x86/platform/geode/net5501.c
@@ -63,7 +63,7 @@ static struct gpio_led net5501_leds[] = {
                .name = "net5501:1",
                .gpio = 6,
                .default_trigger = "default-on",
-                .active_low = 1,
+                .active_low = 0,
        },
 };
diff --git a/arch/x86/platform/mrst/mrst.c b/arch/x86/platform/mrst/mrst.c
index e0a37233c0af..e31bcd8f2eee 100644
--- a/arch/x86/platform/mrst/mrst.c
+++ b/arch/x86/platform/mrst/mrst.c
@@ -805,7 +805,7 @@ void intel_scu_devices_create(void)
                } else
                        i2c_register_board_info(i2c_bus[i], i2c_devs[i], 1);
        }
-        intel_scu_notifier_post(SCU_AVAILABLE, 0L);
+        intel_scu_notifier_post(SCU_AVAILABLE, NULL);
 }
 EXPORT_SYMBOL_GPL(intel_scu_devices_create);
@@ -814,7 +814,7 @@ void intel_scu_devices_destroy(void)
 {
        int i;
-        intel_scu_notifier_post(SCU_DOWN, 0L);
+        intel_scu_notifier_post(SCU_DOWN, NULL);
        for (i = 0; i < ipc_next_dev; i++)
                platform_device_del(ipc_devs[i]);
diff --git a/arch/x86/platform/visws/visws_quirks.c b/arch/x86/platform/visws/visws_quirks.c
index c7abf13a213f..94d8a39332ec 100644
--- a/arch/x86/platform/visws/visws_quirks.c
+++ b/arch/x86/platform/visws/visws_quirks.c
@@ -445,7 +445,7 @@ static void ack_cobalt_irq(struct irq_data *data)
        spin_lock_irqsave(&cobalt_lock, flags);
        disable_cobalt_irq(data);
-        apic_write(APIC_EOI, APIC_EIO_ACK);
+        apic_write(APIC_EOI, APIC_EOI_ACK);
        spin_unlock_irqrestore(&cobalt_lock, flags);
 }
diff --git a/arch/x86/tools/.gitignore b/arch/x86/tools/.gitignore
new file mode 100644
index 000000000000..be0ed065249b
--- /dev/null
+++ b/arch/x86/tools/.gitignore
@@ -0,0 +1 @@
+relocs
diff --git a/arch/x86/tools/Makefile b/arch/x86/tools/Makefile
index d511aa97533a..733057b435b0 100644
--- a/arch/x86/tools/Makefile
+++ b/arch/x86/tools/Makefile
@@ -36,3 +36,7 @@ HOSTCFLAGS_insn_sanity.o := -Wall -I$(objtree)/arch/x86/lib/ -I$(srctree)/arch/x
 $(obj)/test_get_len.o: $(srctree)/arch/x86/lib/insn.c $(srctree)/arch/x86/lib/inat.c $(srctree)/arch/x86/include/asm/inat_types.h $(srctree)/arch/x86/include/asm/inat.h $(srctree)/arch/x86/include/asm/insn.h $(objtree)/arch/x86/lib/inat-tables.c
 $(obj)/insn_sanity.o: $(srctree)/arch/x86/lib/insn.c $(srctree)/arch/x86/lib/inat.c $(srctree)/arch/x86/include/asm/inat_types.h $(srctree)/arch/x86/include/asm/inat.h $(srctree)/arch/x86/include/asm/insn.h $(objtree)/arch/x86/lib/inat-tables.c
+HOST_EXTRACFLAGS += -I$(srctree)/tools/include
+hostprogs-y     += relocs
+relocs: $(obj)/relocs
diff --git a/arch/x86/boot/compressed/relocs.c b/arch/x86/tools/relocs.c
index fb7117a4ade1..b43cfcd9bf40 100644
--- a/arch/x86/boot/compressed/relocs.c
+++ b/arch/x86/tools/relocs.c
@@ -18,6 +18,8 @@ static void die(char *fmt, ...);
 static Elf32_Ehdr ehdr;
 static unsigned long reloc_count, reloc_idx;
 static unsigned long *relocs;
+static unsigned long reloc16_count, reloc16_idx;
+static unsigned long *relocs16;
 struct section {
        Elf32_Shdr     shdr;
@@ -28,52 +30,86 @@ struct section {
 };
 static struct section *secs;
+enum symtype {
+        S_ABS,
+        S_REL,
+        S_SEG,
+        S_LIN,
+        S_NSYMTYPES
+};
+static const char * const sym_regex_kernel[S_NSYMTYPES] = {
 /*
 * Following symbols have been audited. There values are constant and do
 * not change if bzImage is loaded at a different physical address than
 * the address for which it has been compiled. Don't warn user about
 * absolute relocations present w.r.t these symbols.
 */
-static const char abs_sym_regex[] =
+        [S_ABS] =
        "^(xen_irq_disable_direct_reloc$|"
        "xen_save_fl_direct_reloc$|"
        "VDSO|"
-        "__crc_)";
+        "__crc_)",
-static regex_t abs_sym_regex_c;
-static int is_abs_reloc(const char *sym_name)
-{
-        return !regexec(&abs_sym_regex_c, sym_name, 0, NULL, 0);
-}
 /*
 * These symbols are known to be relative, even if the linker marks them
 * as absolute (typically defined outside any section in the linker script.)
 */
-static const char rel_sym_regex[] =
+        [S_REL] =
-        "^_end$";
+        "^(__init_(begin|end)|"
-static regex_t rel_sym_regex_c;
+        "__x86_cpu_dev_(start|end)|"
-static int is_rel_reloc(const char *sym_name)
+        "(__parainstructions|__alt_instructions)(|_end)|"
+        "(__iommu_table|__apicdrivers|__smp_locks)(|_end)|"
+        "_end)$"
+};
+static const char * const sym_regex_realmode[S_NSYMTYPES] = {
+/*
+ * These are 16-bit segment symbols when compiling 16-bit code.
+ */
+        [S_SEG] =
+        "^real_mode_seg$",
+/*
+ * These are offsets belonging to segments, as opposed to linear addresses,
+ * when compiling 16-bit code.
+ */
+        [S_LIN] =
+        "^pa_",
+};
+static const char * const *sym_regex;
+static regex_t sym_regex_c[S_NSYMTYPES];
+static int is_reloc(enum symtype type, const char *sym_name)
 {
-        return !regexec(&rel_sym_regex_c, sym_name, 0, NULL, 0);
+        return sym_regex[type] &&
+                !regexec(&sym_regex_c[type], sym_name, 0, NULL, 0);
 }
-static void regex_init(void)
+static void regex_init(int use_real_mode)
 {
        char errbuf[128];
        int err;
-        
+        int i;
-        err = regcomp(&abs_sym_regex_c, abs_sym_regex,
-                      REG_EXTENDED|REG_NOSUB);
+        if (use_real_mode)
-        if (err) {
+                sym_regex = sym_regex_realmode;
-                regerror(err, &abs_sym_regex_c, errbuf, sizeof errbuf);
+        else
-                die("%s", errbuf);
+                sym_regex = sym_regex_kernel;
-        }
-        err = regcomp(&rel_sym_regex_c, rel_sym_regex,
+        for (i = 0; i < S_NSYMTYPES; i++) {
-                      REG_EXTENDED|REG_NOSUB);
+                if (!sym_regex[i])
-        if (err) {
+                        continue;
-                regerror(err, &rel_sym_regex_c, errbuf, sizeof errbuf);
-                die("%s", errbuf);
+                err = regcomp(&sym_regex_c[i], sym_regex[i],
+                              REG_EXTENDED|REG_NOSUB);
+                if (err) {
+                        regerror(err, &sym_regex_c[i], errbuf, sizeof errbuf);
+                        die("%s", errbuf);
+                }
        }
 }
@@ -154,6 +190,10 @@ static const char *rel_type(unsigned type)
                REL_TYPE(R_386_RELATIVE),
                REL_TYPE(R_386_GOTOFF),
                REL_TYPE(R_386_GOTPC),
+                REL_TYPE(R_386_8),
+                REL_TYPE(R_386_PC8),
+                REL_TYPE(R_386_16),
+                REL_TYPE(R_386_PC16),
 #undef REL_TYPE
        };
        const char *name = "unknown type rel type name";
@@ -189,7 +229,7 @@ static const char *sym_name(const char *sym_strtab, Elf32_Sym *sym)
                name = sym_strtab + sym->st_name;
        }
        else {
-                name = sec_name(secs[sym->st_shndx].shdr.sh_name);
+                name = sec_name(sym->st_shndx);
        }
        return name;
 }
@@ -472,7 +512,7 @@ static void print_absolute_relocs(void)
                         * Before warning check if this absolute symbol
                         * relocation is harmless.
                         */
-                        if (is_abs_reloc(name) || is_rel_reloc(name))
+                        if (is_reloc(S_ABS, name) || is_reloc(S_REL, name))
                                continue;
                        if (!printed) {
@@ -496,7 +536,8 @@ static void print_absolute_relocs(void)
                printf("\n");
 }
-static void walk_relocs(void (*visit)(Elf32_Rel *rel, Elf32_Sym *sym))
+static void walk_relocs(void (*visit)(Elf32_Rel *rel, Elf32_Sym *sym),
+                        int use_real_mode)
 {
        int i;
        /* Walk through the relocations */
@@ -521,30 +562,67 @@ static void walk_relocs(void (*visit)(Elf32_Rel *rel, Elf32_Sym *sym))
                        Elf32_Rel *rel;
                        Elf32_Sym *sym;
                        unsigned r_type;
+                        const char *symname;
+                        int shn_abs;
                        rel = &sec->reltab[j];
                        sym = &sh_symtab[ELF32_R_SYM(rel->r_info)];
                        r_type = ELF32_R_TYPE(rel->r_info);
-                        /* Don't visit relocations to absolute symbols */
-                        if (sym->st_shndx == SHN_ABS &&
+                        shn_abs = sym->st_shndx == SHN_ABS;
-                            !is_rel_reloc(sym_name(sym_strtab, sym))) {
-                                continue;
-                        }
                        switch (r_type) {
                        case R_386_NONE:
                        case R_386_PC32:
+                        case R_386_PC16:
+                        case R_386_PC8:
                                /*
                                 * NONE can be ignored and and PC relative
                                 * relocations don't need to be adjusted.
                                 */
                                break;
+                        case R_386_16:
+                                symname = sym_name(sym_strtab, sym);
+                                if (!use_real_mode)
+                                        goto bad;
+                                if (shn_abs) {
+                                        if (is_reloc(S_ABS, symname))
+                                                break;
+                                        else if (!is_reloc(S_SEG, symname))
+                                                goto bad;
+                                } else {
+                                        if (is_reloc(S_LIN, symname))
+                                                goto bad;
+                                        else
+                                                break;
+                                }
+                                visit(rel, sym);
+                                break;
                        case R_386_32:
-                                /* Visit relocations that need to be adjusted */
+                                symname = sym_name(sym_strtab, sym);
+                                if (shn_abs) {
+                                        if (is_reloc(S_ABS, symname))
+                                                break;
+                                        else if (!is_reloc(S_REL, symname))
+                                                goto bad;
+                                } else {
+                                        if (use_real_mode &&
+                                            !is_reloc(S_LIN, symname))
+                                                break;
+                                }
                                visit(rel, sym);
                                break;
                        default:
                                die("Unsupported relocation type: %s (%d)\n",
                                    rel_type(r_type), r_type);
                                break;
+                        bad:
+                                symname = sym_name(sym_strtab, sym);
+                                die("Invalid %s %s relocation: %s\n",
+                                    shn_abs ? "absolute" : "relative",
+                                    rel_type(r_type), symname);
                        }
                }
        }
@@ -552,13 +630,19 @@ static void walk_relocs(void (*visit)(Elf32_Rel *rel, Elf32_Sym *sym))
 static void count_reloc(Elf32_Rel *rel, Elf32_Sym *sym)
 {
-        reloc_count += 1;
+        if (ELF32_R_TYPE(rel->r_info) == R_386_16)
+                reloc16_count++;
+        else
+                reloc_count++;
 }
 static void collect_reloc(Elf32_Rel *rel, Elf32_Sym *sym)
 {
        /* Remember the address that needs to be adjusted. */
-        relocs[reloc_idx++] = rel->r_offset;
+        if (ELF32_R_TYPE(rel->r_info) == R_386_16)
+                relocs16[reloc16_idx++] = rel->r_offset;
+        else
+                relocs[reloc_idx++] = rel->r_offset;
 }
 static int cmp_relocs(const void *va, const void *vb)
@@ -568,23 +652,41 @@ static int cmp_relocs(const void *va, const void *vb)
        return (*a == *b)? 0 : (*a > *b)? 1 : -1;
 }
-static void emit_relocs(int as_text)
+static int write32(unsigned int v, FILE *f)
+{
+        unsigned char buf[4];
+        put_unaligned_le32(v, buf);
+        return fwrite(buf, 1, 4, f) == 4 ? 0 : -1;
+}
+static void emit_relocs(int as_text, int use_real_mode)
 {
        int i;
        /* Count how many relocations I have and allocate space for them. */
        reloc_count = 0;
-        walk_relocs(count_reloc);
+        walk_relocs(count_reloc, use_real_mode);
        relocs = malloc(reloc_count * sizeof(relocs[0]));
        if (!relocs) {
                die("malloc of %d entries for relocs failed\n",
                        reloc_count);
        }
+        relocs16 = malloc(reloc16_count * sizeof(relocs[0]));
+        if (!relocs16) {
+                die("malloc of %d entries for relocs16 failed\n",
+                        reloc16_count);
+        }
        /* Collect up the relocations */
        reloc_idx = 0;
-        walk_relocs(collect_reloc);
+        walk_relocs(collect_reloc, use_real_mode);
+        if (reloc16_count && !use_real_mode)
+                die("Segment relocations found but --realmode not specified\n");
        /* Order the relocations for more efficient processing */
        qsort(relocs, reloc_count, sizeof(relocs[0]), cmp_relocs);
+        qsort(relocs16, reloc16_count, sizeof(relocs16[0]), cmp_relocs);
        /* Print the relocations */
        if (as_text) {
@@ -593,58 +695,83 @@ static void emit_relocs(int as_text)
                 */
                printf(".section \".data.reloc\",\"a\"\n");
                printf(".balign 4\n");
-                for (i = 0; i < reloc_count; i++) {
+                if (use_real_mode) {
-                        printf("\t .long 0x%08lx\n", relocs[i]);
+                        printf("\t.long %lu\n", reloc16_count);
+                        for (i = 0; i < reloc16_count; i++)
+                                printf("\t.long 0x%08lx\n", relocs16[i]);
+                        printf("\t.long %lu\n", reloc_count);
+                        for (i = 0; i < reloc_count; i++) {
+                                printf("\t.long 0x%08lx\n", relocs[i]);
+                        }
+                } else {
+                        /* Print a stop */
+                        printf("\t.long 0x%08lx\n", (unsigned long)0);
+                        for (i = 0; i < reloc_count; i++) {
+                                printf("\t.long 0x%08lx\n", relocs[i]);
+                        }
                }
                printf("\n");
        }
        else {
-                unsigned char buf[4];
+                if (use_real_mode) {
-                /* Print a stop */
+                        write32(reloc16_count, stdout);
-                fwrite("\0\0\0\0", 4, 1, stdout);
+                        for (i = 0; i < reloc16_count; i++)
-                /* Now print each relocation */
+                                write32(relocs16[i], stdout);
-                for (i = 0; i < reloc_count; i++) {
+                        write32(reloc_count, stdout);
-                        put_unaligned_le32(relocs[i], buf);
-                        fwrite(buf, 4, 1, stdout);
+                        /* Now print each relocation */
+                        for (i = 0; i < reloc_count; i++)
+                                write32(relocs[i], stdout);
+                } else {
+                        /* Print a stop */
+                        write32(0, stdout);
+                        /* Now print each relocation */
+                        for (i = 0; i < reloc_count; i++) {
+                                write32(relocs[i], stdout);
+                        }
                }
        }
 }
 static void usage(void)
 {
-        die("relocs [--abs-syms |--abs-relocs | --text] vmlinux\n");
+        die("relocs [--abs-syms|--abs-relocs|--text|--realmode] vmlinux\n");
 }
 int main(int argc, char **argv)
 {
        int show_absolute_syms, show_absolute_relocs;
-        int as_text;
+        int as_text, use_real_mode;
        const char *fname;
        FILE *fp;
        int i;
-        regex_init();
        show_absolute_syms = 0;
        show_absolute_relocs = 0;
        as_text = 0;
+        use_real_mode = 0;
        fname = NULL;
        for (i = 1; i < argc; i++) {
                char *arg = argv[i];
                if (*arg == '-') {
-                        if (strcmp(argv[1], "--abs-syms") == 0) {
+                        if (strcmp(arg, "--abs-syms") == 0) {
                                show_absolute_syms = 1;
                                continue;
                        }
+                        if (strcmp(arg, "--abs-relocs") == 0) {
-                        if (strcmp(argv[1], "--abs-relocs") == 0) {
                                show_absolute_relocs = 1;
                                continue;
                        }
-                        else if (strcmp(argv[1], "--text") == 0) {
+                        if (strcmp(arg, "--text") == 0) {
                                as_text = 1;
                                continue;
                        }
+                        if (strcmp(arg, "--realmode") == 0) {
+                                use_real_mode = 1;
+                                continue;
+                        }
                }
                else if (!fname) {
                        fname = arg;
@@ -655,6 +782,7 @@ int main(int argc, char **argv)
        if (!fname) {
                usage();
        }
+        regex_init(use_real_mode);
        fp = fopen(fname, "r");
        if (!fp) {
                die("Cannot open %s: %s\n",
@@ -673,6 +801,6 @@ int main(int argc, char **argv)
                print_absolute_relocs();
                return 0;
        }
-        emit_relocs(as_text);
+        emit_relocs(as_text, use_real_mode);
        return 0;
 }
diff --git a/arch/x86/um/asm/barrier.h b/arch/x86/um/asm/barrier.h
new file mode 100644
index 000000000000..7d01b8c56c00
--- /dev/null
+++ b/arch/x86/um/asm/barrier.h
@@ -0,0 +1,75 @@
+#ifndef _ASM_UM_BARRIER_H_
+#define _ASM_UM_BARRIER_H_
+#include <asm/asm.h>
+#include <asm/segment.h>
+#include <asm/cpufeature.h>
+#include <asm/cmpxchg.h>
+#include <asm/nops.h>
+#include <linux/kernel.h>
+#include <linux/irqflags.h>
+/*
+ * Force strict CPU ordering.
+ * And yes, this is required on UP too when we're talking
+ * to devices.
+ */
+#ifdef CONFIG_X86_32
+#define mb()    alternative("lock; addl $0,0(%%esp)", "mfence", X86_FEATURE_XMM2)
+#define rmb()   alternative("lock; addl $0,0(%%esp)", "lfence", X86_FEATURE_XMM2)
+#define wmb()   alternative("lock; addl $0,0(%%esp)", "sfence", X86_FEATURE_XMM)
+#else /* CONFIG_X86_32 */
+#define mb()    asm volatile("mfence" : : : "memory")
+#define rmb()   asm volatile("lfence" : : : "memory")
+#define wmb()   asm volatile("sfence" : : : "memory")
+#endif /* CONFIG_X86_32 */
+#define read_barrier_depends()  do { } while (0)
+#ifdef CONFIG_SMP
+#define smp_mb()        mb()
+#ifdef CONFIG_X86_PPRO_FENCE
+#define smp_rmb()       rmb()
+#else /* CONFIG_X86_PPRO_FENCE */
+#define smp_rmb()       barrier()
+#endif /* CONFIG_X86_PPRO_FENCE */
+#ifdef CONFIG_X86_OOSTORE
+#define smp_wmb()       wmb()
+#else /* CONFIG_X86_OOSTORE */
+#define smp_wmb()       barrier()
+#endif /* CONFIG_X86_OOSTORE */
+#define smp_read_barrier_depends()      read_barrier_depends()
+#define set_mb(var, value) do { (void)xchg(&var, value); } while (0)
+#else /* CONFIG_SMP */
+#define smp_mb()        barrier()
+#define smp_rmb()       barrier()
+#define smp_wmb()       barrier()
+#define smp_read_barrier_depends()      do { } while (0)
+#define set_mb(var, value) do { var = value; barrier(); } while (0)
+#endif /* CONFIG_SMP */
+/*
+ * Stop RDTSC speculation. This is needed when you need to use RDTSC
+ * (or get_cycles or vread that possibly accesses the TSC) in a defined
+ * code region.
+ *
+ * (Could use an alternative three way for this if there was one.)
+ */
+static inline void rdtsc_barrier(void)
+{
+        alternative(ASM_NOP3, "mfence", X86_FEATURE_MFENCE_RDTSC);
+        alternative(ASM_NOP3, "lfence", X86_FEATURE_LFENCE_RDTSC);
+}
+#endif
diff --git a/arch/x86/um/asm/system.h b/arch/x86/um/asm/system.h
deleted file mode 100644
index a459fd9b7598..000000000000
--- a/arch/x86/um/asm/system.h
+++ /dev/null
@@ -1,135 +0,0 @@
-#ifndef _ASM_X86_SYSTEM_H_
-#define _ASM_X86_SYSTEM_H_
-#include <asm/asm.h>
-#include <asm/segment.h>
-#include <asm/cpufeature.h>
-#include <asm/cmpxchg.h>
-#include <asm/nops.h>
-#include <linux/kernel.h>
-#include <linux/irqflags.h>
-/* entries in ARCH_DLINFO: */
-#ifdef CONFIG_IA32_EMULATION
-# define AT_VECTOR_SIZE_ARCH 2
-#else
-# define AT_VECTOR_SIZE_ARCH 1
-#endif
-extern unsigned long arch_align_stack(unsigned long sp);
-void default_idle(void);
-/*
- * Force strict CPU ordering.
- * And yes, this is required on UP too when we're talking
- * to devices.
- */
-#ifdef CONFIG_X86_32
-/*
- * Some non-Intel clones support out of order store. wmb() ceases to be a
- * nop for these.
- */
-#define mb() alternative("lock; addl $0,0(%%esp)", "mfence", X86_FEATURE_XMM2)
-#define rmb() alternative("lock; addl $0,0(%%esp)", "lfence", X86_FEATURE_XMM2)
-#define wmb() alternative("lock; addl $0,0(%%esp)", "sfence", X86_FEATURE_XMM)
-#else
-#define mb()    asm volatile("mfence":::"memory")
-#define rmb()   asm volatile("lfence":::"memory")
-#define wmb()   asm volatile("sfence" ::: "memory")
-#endif
-/**
- * read_barrier_depends - Flush all pending reads that subsequents reads
- * depend on.
- *
- * No data-dependent reads from memory-like regions are ever reordered
- * over this barrier.  All reads preceding this primitive are guaranteed
- * to access memory (but not necessarily other CPUs' caches) before any
- * reads following this primitive that depend on the data return by
- * any of the preceding reads.  This primitive is much lighter weight than
- * rmb() on most CPUs, and is never heavier weight than is
- * rmb().
- *
- * These ordering constraints are respected by both the local CPU
- * and the compiler.
- *
- * Ordering is not guaranteed by anything other than these primitives,
- * not even by data dependencies.  See the documentation for
- * memory_barrier() for examples and URLs to more information.
- *
- * For example, the following code would force ordering (the initial
- * value of "a" is zero, "b" is one, and "p" is "&a"):
- *
- * <programlisting>
- *      CPU 0                           CPU 1
- *
- *      b = 2;
- *      memory_barrier();
- *      p = &b;                         q = p;
- *                                      read_barrier_depends();
- *                                      d = *q;
- * </programlisting>
- *
- * because the read of "*q" depends on the read of "p" and these
- * two reads are separated by a read_barrier_depends().  However,
- * the following code, with the same initial values for "a" and "b":
- *
- * <programlisting>
- *      CPU 0                           CPU 1
- *
- *      a = 2;
- *      memory_barrier();
- *      b = 3;                          y = b;
- *                                      read_barrier_depends();
- *                                      x = a;
- * </programlisting>
- *
- * does not enforce ordering, since there is no data dependency between
- * the read of "a" and the read of "b".  Therefore, on some CPUs, such
- * as Alpha, "y" could be set to 3 and "x" to 0.  Use rmb()
- * in cases like this where there are no data dependencies.
- **/
-#define read_barrier_depends()  do { } while (0)
-#ifdef CONFIG_SMP
-#define smp_mb()        mb()
-#ifdef CONFIG_X86_PPRO_FENCE
-# define smp_rmb()      rmb()
-#else
-# define smp_rmb()      barrier()
-#endif
-#ifdef CONFIG_X86_OOSTORE
-# define smp_wmb()      wmb()
-#else
-# define smp_wmb()      barrier()
-#endif
-#define smp_read_barrier_depends()      read_barrier_depends()
-#define set_mb(var, value) do { (void)xchg(&var, value); } while (0)
-#else
-#define smp_mb()        barrier()
-#define smp_rmb()       barrier()
-#define smp_wmb()       barrier()
-#define smp_read_barrier_depends()      do { } while (0)
-#define set_mb(var, value) do { var = value; barrier(); } while (0)
-#endif
-/*
- * Stop RDTSC speculation. This is needed when you need to use RDTSC
- * (or get_cycles or vread that possibly accesses the TSC) in a defined
- * code region.
- *
- * (Could use an alternative three way for this if there was one.)
- */
-static inline void rdtsc_barrier(void)
-{
-        alternative(ASM_NOP3, "mfence", X86_FEATURE_MFENCE_RDTSC);
-        alternative(ASM_NOP3, "lfence", X86_FEATURE_LFENCE_RDTSC);
-}
-extern void *_switch_to(void *prev, void *next, void *last);
-#define switch_to(prev, next, last) prev = _switch_to(prev, next, last)
-#endif
diff --git a/arch/x86/xen/Makefile b/arch/x86/xen/Makefile
index add2c2d729ce..96ab2c09cb68 100644
--- a/arch/x86/xen/Makefile
+++ b/arch/x86/xen/Makefile
@@ -20,5 +20,5 @@ obj-$(CONFIG_EVENT_TRACING) += trace.o
 obj-$(CONFIG_SMP)               += smp.o
 obj-$(CONFIG_PARAVIRT_SPINLOCKS)+= spinlock.o
 obj-$(CONFIG_XEN_DEBUG_FS)      += debugfs.o
-obj-$(CONFIG_XEN_DOM0)          += vga.o
+obj-$(CONFIG_XEN_DOM0)          += apic.o vga.o
 obj-$(CONFIG_SWIOTLB_XEN)       += pci-swiotlb-xen.o
diff --git a/arch/x86/xen/apic.c b/arch/x86/xen/apic.c
new file mode 100644
index 000000000000..ec57bd3818a4
--- /dev/null
+++ b/arch/x86/xen/apic.c
@@ -0,0 +1,33 @@
+#include <linux/init.h>
+#include <asm/x86_init.h>
+#include <asm/apic.h>
+#include <asm/xen/hypercall.h>
+#include <xen/xen.h>
+#include <xen/interface/physdev.h>
+unsigned int xen_io_apic_read(unsigned apic, unsigned reg)
+{
+        struct physdev_apic apic_op;
+        int ret;
+        apic_op.apic_physbase = mpc_ioapic_addr(apic);
+        apic_op.reg = reg;
+        ret = HYPERVISOR_physdev_op(PHYSDEVOP_apic_read, &apic_op);
+        if (!ret)
+                return apic_op.value;
+        /* fallback to return an emulated IO_APIC values */
+        if (reg == 0x1)
+                return 0x00170020;
+        else if (reg == 0x0)
+                return apic << 24;
+        return 0xfd;
+}
+void __init xen_init_apic(void)
+{
+        x86_io_apic_ops.read = xen_io_apic_read;
+}
diff --git a/arch/x86/xen/enlighten.c b/arch/x86/xen/enlighten.c
index 4f51bebac02c..c0f5facdb10c 100644
--- a/arch/x86/xen/enlighten.c
+++ b/arch/x86/xen/enlighten.c
@@ -63,6 +63,7 @@
 #include <asm/stackprotector.h>
 #include <asm/hypervisor.h>
 #include <asm/mwait.h>
+#include <asm/pci_x86.h>
 #ifdef CONFIG_ACPI
 #include <linux/acpi.h>
@@ -261,7 +262,8 @@ static void xen_cpuid(unsigned int *ax, unsigned int *bx,
 static bool __init xen_check_mwait(void)
 {
-#ifdef CONFIG_ACPI
+#if defined(CONFIG_ACPI) && !defined(CONFIG_ACPI_PROCESSOR_AGGREGATOR) && \
+        !defined(CONFIG_ACPI_PROCESSOR_AGGREGATOR_MODULE)
        struct xen_platform_op op = {
                .cmd                    = XENPF_set_processor_pminfo,
                .u.set_pminfo.id        = -1,
@@ -349,7 +351,6 @@ static void __init xen_init_cpuid_mask(void)
        /* Xen will set CR4.OSXSAVE if supported and not disabled by force */
        if ((cx & xsave_mask) != xsave_mask)
                cpuid_leaf1_ecx_mask &= ~xsave_mask; /* disable XSAVE & OSXSAVE */
        if (xen_check_mwait())
                cpuid_leaf1_ecx_set_mask = (1 << (X86_FEATURE_MWAIT % 32));
 }
@@ -809,9 +810,40 @@ static void xen_io_delay(void)
 }
 #ifdef CONFIG_X86_LOCAL_APIC
+static unsigned long xen_set_apic_id(unsigned int x)
+{
+        WARN_ON(1);
+        return x;
+}
+static unsigned int xen_get_apic_id(unsigned long x)
+{
+        return ((x)>>24) & 0xFFu;
+}
 static u32 xen_apic_read(u32 reg)
 {
-        return 0;
+        struct xen_platform_op op = {
+                .cmd = XENPF_get_cpuinfo,
+                .interface_version = XENPF_INTERFACE_VERSION,
+                .u.pcpu_info.xen_cpuid = 0,
+        };
+        int ret = 0;
+        /* Shouldn't need this as APIC is turned off for PV, and we only
+         * get called on the bootup processor. But just in case. */
+        if (!xen_initial_domain() || smp_processor_id())
+                return 0;
+        if (reg == APIC_LVR)
+                return 0x10;
+        if (reg != APIC_ID)
+                return 0;
+        ret = HYPERVISOR_dom0_op(&op);
+        if (ret)
+                return 0;
+        return op.u.pcpu_info.apic_id << 24;
 }
 static void xen_apic_write(u32 reg, u32 val)
@@ -849,6 +881,8 @@ static void set_xen_basic_apic_ops(void)
        apic->icr_write = xen_apic_icr_write;
        apic->wait_icr_idle = xen_apic_wait_icr_idle;
        apic->safe_wait_icr_idle = xen_safe_apic_wait_icr_idle;
+        apic->set_apic_id = xen_set_apic_id;
+        apic->get_apic_id = xen_get_apic_id;
 }
 #endif
@@ -1362,11 +1396,15 @@ asmlinkage void __init xen_start_kernel(void)
                xen_start_info->console.domU.mfn = 0;
                xen_start_info->console.domU.evtchn = 0;
+                xen_init_apic();
                /* Make sure ACS will be enabled */
                pci_request_acs();
        }
-                
+#ifdef CONFIG_PCI
+        /* PCI BIOS service won't work from a PV guest. */
+        pci_probe &= ~PCI_PROBE_BIOS;
+#endif
        xen_raw_console_write("about to get started...\n");
        xen_setup_runstate_info(0);
diff --git a/arch/x86/xen/mmu.c b/arch/x86/xen/mmu.c
index b8e279479a6b..3506cd4f9a43 100644
--- a/arch/x86/xen/mmu.c
+++ b/arch/x86/xen/mmu.c
@@ -353,8 +353,13 @@ static pteval_t pte_mfn_to_pfn(pteval_t val)
 {
        if (val & _PAGE_PRESENT) {
                unsigned long mfn = (val & PTE_PFN_MASK) >> PAGE_SHIFT;
+                unsigned long pfn = mfn_to_pfn(mfn);
                pteval_t flags = val & PTE_FLAGS_MASK;
-                val = ((pteval_t)mfn_to_pfn(mfn) << PAGE_SHIFT) | flags;
+                if (unlikely(pfn == ~0))
+                        val = flags & ~_PAGE_PRESENT;
+                else
+                        val = ((pteval_t)pfn << PAGE_SHIFT) | flags;
        }
        return val;
@@ -1859,7 +1864,6 @@ pgd_t * __init xen_setup_kernel_pagetable(pgd_t *pgd,
 #endif  /* CONFIG_X86_64 */
 static unsigned char dummy_mapping[PAGE_SIZE] __page_aligned_bss;
-static unsigned char fake_ioapic_mapping[PAGE_SIZE] __page_aligned_bss;
 static void xen_set_fixmap(unsigned idx, phys_addr_t phys, pgprot_t prot)
 {
@@ -1900,7 +1904,7 @@ static void xen_set_fixmap(unsigned idx, phys_addr_t phys, pgprot_t prot)
                 * We just don't map the IO APIC - all access is via
                 * hypercalls.  Keep the address in the pte for reference.
                 */
-                pte = pfn_pte(PFN_DOWN(__pa(fake_ioapic_mapping)), PAGE_KERNEL);
+                pte = pfn_pte(PFN_DOWN(__pa(dummy_mapping)), PAGE_KERNEL);
                break;
 #endif
@@ -2065,7 +2069,6 @@ void __init xen_init_mmu_ops(void)
        pv_mmu_ops = xen_mmu_ops;
        memset(dummy_mapping, 0xff, PAGE_SIZE);
-        memset(fake_ioapic_mapping, 0xfd, PAGE_SIZE);
 }
 /* Protected by xen_reservation_lock. */
diff --git a/arch/x86/xen/smp.c b/arch/x86/xen/smp.c
index 5fac6919b957..3700945ed0d5 100644
--- a/arch/x86/xen/smp.c
+++ b/arch/x86/xen/smp.c
@@ -178,6 +178,7 @@ static void __init xen_fill_possible_map(void)
 static void __init xen_filter_cpu_maps(void)
 {
        int i, rc;
+        unsigned int subtract = 0;
        if (!xen_initial_domain())
                return;
@@ -192,8 +193,22 @@ static void __init xen_filter_cpu_maps(void)
                } else {
                        set_cpu_possible(i, false);
                        set_cpu_present(i, false);
+                        subtract++;
                }
        }
+#ifdef CONFIG_HOTPLUG_CPU
+        /* This is akin to using 'nr_cpus' on the Linux command line.
+         * Which is OK as when we use 'dom0_max_vcpus=X' we can only
+         * have up to X, while nr_cpu_ids is greater than X. This
+         * normally is not a problem, except when CPU hotplugging
+         * is involved and then there might be more than X CPUs
+         * in the guest - which will not work as there is no
+         * hypercall to expand the max number of VCPUs an already
+         * running guest has. So cap it up to X. */
+        if (subtract)
+                nr_cpu_ids = nr_cpu_ids - subtract;
+#endif
 }
 static void __init xen_smp_prepare_boot_cpu(void)
@@ -250,18 +265,8 @@ static void __init xen_smp_prepare_cpus(unsigned int max_cpus)
                set_cpu_possible(cpu, false);
        }
-        for_each_possible_cpu (cpu) {
+        for_each_possible_cpu(cpu)
-                struct task_struct *idle;
-                if (cpu == 0)
-                        continue;
-                idle = fork_idle(cpu);
-                if (IS_ERR(idle))
-                        panic("failed fork for CPU %d", cpu);
                set_cpu_present(cpu, true);
-        }
 }
 static int __cpuinit
@@ -331,9 +336,8 @@ cpu_initialize_context(unsigned int cpu, struct task_struct *idle)
        return 0;
 }
-static int __cpuinit xen_cpu_up(unsigned int cpu)
+static int __cpuinit xen_cpu_up(unsigned int cpu, struct task_struct *idle)
 {
-        struct task_struct *idle = idle_task(cpu);
        int rc;
        per_cpu(current_task, cpu) = idle;
@@ -547,10 +551,10 @@ static void __init xen_hvm_smp_prepare_cpus(unsigned int max_cpus)
        xen_init_lock_cpu(0);
 }
-static int __cpuinit xen_hvm_cpu_up(unsigned int cpu)
+static int __cpuinit xen_hvm_cpu_up(unsigned int cpu, struct task_struct *tidle)
 {
        int rc;
-        rc = native_cpu_up(cpu);
+        rc = native_cpu_up(cpu, tidle);
        WARN_ON (xen_smp_intr_init(cpu));
        return rc;
 }
diff --git a/arch/x86/xen/xen-asm.S b/arch/x86/xen/xen-asm.S
index 79d7362ad6d1..3e45aa000718 100644
--- a/arch/x86/xen/xen-asm.S
+++ b/arch/x86/xen/xen-asm.S
@@ -96,7 +96,7 @@ ENTRY(xen_restore_fl_direct)
        /* check for unmasked and pending */
        cmpw $0x0001, PER_CPU_VAR(xen_vcpu_info) + XEN_vcpu_info_pending
-        jz 1f
+        jnz 1f
 2:      call check_events
 1:
 ENDPATCH(xen_restore_fl_direct)
diff --git a/arch/x86/xen/xen-ops.h b/arch/x86/xen/xen-ops.h
index b095739ccd4c..45c0c0667bd9 100644
--- a/arch/x86/xen/xen-ops.h
+++ b/arch/x86/xen/xen-ops.h
@@ -92,11 +92,15 @@ struct dom0_vga_console_info;
 #ifdef CONFIG_XEN_DOM0
 void __init xen_init_vga(const struct dom0_vga_console_info *, size_t size);
+void __init xen_init_apic(void);
 #else
 static inline void __init xen_init_vga(const struct dom0_vga_console_info *info,
                                       size_t size)
 {
 }
+static inline void __init xen_init_apic(void)
+{
+}
 #endif
 /* Declare an asm function, along with symbols needed to make it
diff --git a/arch/xtensa/configs/common_defconfig b/arch/xtensa/configs/common_defconfig
index b90038e40dd3..a182a4e6d688 100644
--- a/arch/xtensa/configs/common_defconfig
+++ b/arch/xtensa/configs/common_defconfig
@@ -333,11 +333,6 @@ CONFIG_XT2000_SONIC=y
 # CONFIG_S2IO is not set
 #
-# Token Ring devices
-#
-# CONFIG_TR is not set
-#
 # Wireless LAN (non-hamradio)
 #
 CONFIG_NET_RADIO=y
diff --git a/arch/xtensa/include/asm/hardirq.h b/arch/xtensa/include/asm/hardirq.h
index 26664cef8f11..91695a135498 100644
--- a/arch/xtensa/include/asm/hardirq.h
+++ b/arch/xtensa/include/asm/hardirq.h
@@ -11,9 +11,6 @@
 #ifndef _XTENSA_HARDIRQ_H
 #define _XTENSA_HARDIRQ_H
-void ack_bad_irq(unsigned int irq);
-#define ack_bad_irq ack_bad_irq
 #include <asm-generic/hardirq.h>
 #endif  /* _XTENSA_HARDIRQ_H */
diff --git a/arch/xtensa/include/asm/io.h b/arch/xtensa/include/asm/io.h
index d04cd3a625fa..4beb43c087d3 100644
--- a/arch/xtensa/include/asm/io.h
+++ b/arch/xtensa/include/asm/io.h
@@ -14,6 +14,7 @@
 #ifdef __KERNEL__
 #include <asm/byteorder.h>
 #include <asm/page.h>
+#include <linux/bug.h>
 #include <linux/kernel.h>
 #include <linux/types.h>
diff --git a/arch/xtensa/kernel/Makefile b/arch/xtensa/kernel/Makefile
index 2d2728b3e862..59fc3fe15572 100644
--- a/arch/xtensa/kernel/Makefile
+++ b/arch/xtensa/kernel/Makefile
@@ -6,7 +6,7 @@ extra-y := head.o vmlinux.lds
 obj-y := align.o entry.o irq.o coprocessor.o process.o ptrace.o \
         setup.o signal.o syscall.o time.o traps.o vectors.o platform.o  \
-         pci-dma.o init_task.o io.o
+         pci-dma.o io.o
 obj-$(CONFIG_KGDB) += xtensa-stub.o
 obj-$(CONFIG_PCI) += pci.o
diff --git a/arch/xtensa/kernel/init_task.c b/arch/xtensa/kernel/init_task.c
deleted file mode 100644
index cd122fb7e48a..000000000000
--- a/arch/xtensa/kernel/init_task.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * arch/xtensa/kernel/init_task.c
- *
- * Xtensa Processor version.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2007 Tensilica Inc.
- *
- * Chris Zankel <chris@zankel.net>
- */
-#include <linux/mm.h>
-#include <linux/fs.h>
-#include <linux/init.h>
-#include <linux/init_task.h>
-#include <linux/module.h>
-#include <linux/mqueue.h>
-#include <asm/uaccess.h>
-static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
-static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
-union thread_union init_thread_union __init_task_data =
-        { INIT_THREAD_INFO(init_task) };
-struct task_struct init_task = INIT_TASK(init_task);
-EXPORT_SYMBOL(init_task);
diff --git a/arch/xtensa/kernel/signal.c b/arch/xtensa/kernel/signal.c
index b69b000349fc..d78869a00b11 100644
--- a/arch/xtensa/kernel/signal.c
+++ b/arch/xtensa/kernel/signal.c
@@ -496,6 +496,7 @@ int do_signal(struct pt_regs *regs, sigset_t *oldset)
        signr = get_signal_to_deliver(&info, &ka, regs, NULL);
        if (signr > 0) {
+                int ret;
                /* Are we from a system call? */